1 ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; millicode call delay slot description. Note it disallows delay slot
109 ;; when TARGET_PORTABLE_RUNTIME is true.
110 (define_delay (eq_attr "type" "milli")
111 [(and (eq_attr "in_call_delay" "true")
112 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0)))
115 ;; Return and other similar instructions.
116 (define_delay (eq_attr "type" "branch,parallel_branch")
117 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
119 ;; Floating point conditional branch delay slot description and
120 (define_delay (eq_attr "type" "fbranch")
121 [(eq_attr "in_branch_delay" "true")
122 (eq_attr "in_nullified_branch_delay" "true")
125 ;; Integer conditional branch delay slot description.
126 ;; Nullification of conditional branches on the PA is dependent on the
127 ;; direction of the branch. Forward branches nullify true and
128 ;; backward branches nullify false. If the direction is unknown
129 ;; then nullification is not allowed.
130 (define_delay (eq_attr "type" "cbranch")
131 [(eq_attr "in_branch_delay" "true")
132 (and (eq_attr "in_nullified_branch_delay" "true")
133 (attr_flag "forward"))
134 (and (eq_attr "in_nullified_branch_delay" "true")
135 (attr_flag "backward"))])
137 (define_delay (and (eq_attr "type" "uncond_branch")
138 (eq (symbol_ref "following_call (insn)")
140 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
142 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
143 ;; load: 2, fpload: 3
144 ;; store, fpstore: 3, no D-cache operations should be scheduled.
146 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
148 ;; Instruction Time Unit Minimum Distance (unit contention)
155 ;; fmpyadd 3 ALU,MPY 2
156 ;; fmpysub 3 ALU,MPY 2
157 ;; fmpycfxt 3 ALU,MPY 2
160 ;; fdiv,sgl 10 MPY 10
161 ;; fdiv,dbl 12 MPY 12
162 ;; fsqrt,sgl 14 MPY 14
163 ;; fsqrt,dbl 18 MPY 18
165 ;; We don't model fmpyadd/fmpysub properly as those instructions
166 ;; keep both the FP ALU and MPY units busy. Given that these
167 ;; processors are obsolete, I'm not going to spend the time to
168 ;; model those instructions correctly.
170 (define_automaton "pa700")
171 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
173 (define_insn_reservation "W0" 4
174 (and (eq_attr "type" "fpcc")
175 (eq_attr "cpu" "700"))
178 (define_insn_reservation "W1" 3
179 (and (eq_attr "type" "fpalu")
180 (eq_attr "cpu" "700"))
183 (define_insn_reservation "W2" 3
184 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
185 (eq_attr "cpu" "700"))
188 (define_insn_reservation "W3" 10
189 (and (eq_attr "type" "fpdivsgl")
190 (eq_attr "cpu" "700"))
193 (define_insn_reservation "W4" 12
194 (and (eq_attr "type" "fpdivdbl")
195 (eq_attr "cpu" "700"))
198 (define_insn_reservation "W5" 14
199 (and (eq_attr "type" "fpsqrtsgl")
200 (eq_attr "cpu" "700"))
203 (define_insn_reservation "W6" 18
204 (and (eq_attr "type" "fpsqrtdbl")
205 (eq_attr "cpu" "700"))
208 (define_insn_reservation "W7" 2
209 (and (eq_attr "type" "load")
210 (eq_attr "cpu" "700"))
213 (define_insn_reservation "W8" 2
214 (and (eq_attr "type" "fpload")
215 (eq_attr "cpu" "700"))
218 (define_insn_reservation "W9" 3
219 (and (eq_attr "type" "store")
220 (eq_attr "cpu" "700"))
223 (define_insn_reservation "W10" 3
224 (and (eq_attr "type" "fpstore")
225 (eq_attr "cpu" "700"))
228 (define_insn_reservation "W11" 1
229 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
230 (eq_attr "cpu" "700"))
233 ;; We have a bypass for all computations in the FP unit which feed an
234 ;; FP store as long as the sizes are the same.
235 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
237 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
238 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
239 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
241 ;; We have an "anti-bypass" for FP loads which feed an FP store.
242 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
244 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
245 ;; floating point computations with non-floating point computations (fp loads
246 ;; and stores are not fp computations).
248 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
249 ;; take two cycles, during which no Dcache operations should be scheduled.
250 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
251 ;; all have the same memory characteristics if one disregards cache misses.
253 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
254 ;; There's no value in modeling the ALU and MUL separately though
255 ;; since there can never be a functional unit conflict given the
256 ;; latency and issue rates for those units.
259 ;; Instruction Time Unit Minimum Distance (unit contention)
266 ;; fmpyadd 2 ALU,MPY 1
267 ;; fmpysub 2 ALU,MPY 1
268 ;; fmpycfxt 2 ALU,MPY 1
272 ;; fdiv,dbl 15 DIV 15
274 ;; fsqrt,dbl 15 DIV 15
276 (define_automaton "pa7100")
277 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
279 (define_insn_reservation "X0" 2
280 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
281 (eq_attr "cpu" "7100"))
284 (define_insn_reservation "X1" 8
285 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
286 (eq_attr "cpu" "7100"))
287 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
289 (define_insn_reservation "X2" 15
290 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
291 (eq_attr "cpu" "7100"))
292 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
294 (define_insn_reservation "X3" 2
295 (and (eq_attr "type" "load")
296 (eq_attr "cpu" "7100"))
299 (define_insn_reservation "X4" 2
300 (and (eq_attr "type" "fpload")
301 (eq_attr "cpu" "7100"))
304 (define_insn_reservation "X5" 2
305 (and (eq_attr "type" "store")
306 (eq_attr "cpu" "7100"))
307 "i_7100+mem_7100,mem_7100")
309 (define_insn_reservation "X6" 2
310 (and (eq_attr "type" "fpstore")
311 (eq_attr "cpu" "7100"))
312 "i_7100+mem_7100,mem_7100")
314 (define_insn_reservation "X7" 1
315 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
316 (eq_attr "cpu" "7100"))
319 ;; We have a bypass for all computations in the FP unit which feed an
320 ;; FP store as long as the sizes are the same.
321 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
322 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
323 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
325 ;; We have an "anti-bypass" for FP loads which feed an FP store.
326 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
328 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
329 ;; There's no value in modeling the ALU and MUL separately though
330 ;; since there can never be a functional unit conflict that
331 ;; can be avoided given the latency, issue rates and mandatory
332 ;; one cycle cpu-wide lock for a double precision fp multiply.
335 ;; Instruction Time Unit Minimum Distance (unit contention)
342 ;; fmpyadd,sgl 2 ALU,MPY 1
343 ;; fmpyadd,dbl 3 ALU,MPY 2
344 ;; fmpysub,sgl 2 ALU,MPY 1
345 ;; fmpysub,dbl 3 ALU,MPY 2
346 ;; fmpycfxt,sgl 2 ALU,MPY 1
347 ;; fmpycfxt,dbl 3 ALU,MPY 2
352 ;; fdiv,dbl 15 DIV 15
354 ;; fsqrt,dbl 15 DIV 15
356 ;; The PA7200 is just like the PA7100LC except that there is
357 ;; no store-store penalty.
359 ;; The PA7300 is just like the PA7200 except that there is
360 ;; no store-load penalty.
362 ;; Note there are some aspects of the 7100LC we are not modeling
363 ;; at the moment. I'll be reviewing the 7100LC scheduling info
364 ;; shortly and updating this description.
368 ;; other issue modeling
370 (define_automaton "pa7100lc")
371 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
372 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
373 (define_cpu_unit "mem_7100lc" "pa7100lc")
375 ;; Double precision multiplies lock the entire CPU for one
376 ;; cycle. There is no way to avoid this lock and trying to
377 ;; schedule around the lock is pointless and thus there is no
378 ;; value in trying to model this lock.
380 ;; Not modeling the lock allows us to treat fp multiplies just
381 ;; like any other FP alu instruction. It allows for a smaller
382 ;; DFA and may reduce register pressure.
383 (define_insn_reservation "Y0" 2
384 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
385 (eq_attr "cpu" "7100LC,7200,7300"))
386 "f_7100lc,fpmac_7100lc")
388 ;; fp division and sqrt instructions lock the entire CPU for
389 ;; 7 cycles (single precision) or 14 cycles (double precision).
390 ;; There is no way to avoid this lock and trying to schedule
391 ;; around the lock is pointless and thus there is no value in
392 ;; trying to model this lock. Not modeling the lock allows
393 ;; for a smaller DFA and may reduce register pressure.
394 (define_insn_reservation "Y1" 1
395 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
396 (eq_attr "cpu" "7100LC,7200,7300"))
399 (define_insn_reservation "Y2" 2
400 (and (eq_attr "type" "load")
401 (eq_attr "cpu" "7100LC,7200,7300"))
402 "i1_7100lc+mem_7100lc")
404 (define_insn_reservation "Y3" 2
405 (and (eq_attr "type" "fpload")
406 (eq_attr "cpu" "7100LC,7200,7300"))
407 "i1_7100lc+mem_7100lc")
409 (define_insn_reservation "Y4" 2
410 (and (eq_attr "type" "store")
411 (eq_attr "cpu" "7100LC"))
412 "i1_7100lc+mem_7100lc,mem_7100lc")
414 (define_insn_reservation "Y5" 2
415 (and (eq_attr "type" "fpstore")
416 (eq_attr "cpu" "7100LC"))
417 "i1_7100lc+mem_7100lc,mem_7100lc")
419 (define_insn_reservation "Y6" 1
420 (and (eq_attr "type" "shift,nullshift")
421 (eq_attr "cpu" "7100LC,7200,7300"))
424 (define_insn_reservation "Y7" 1
425 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
426 (eq_attr "cpu" "7100LC,7200,7300"))
427 "(i0_7100lc|i1_7100lc)")
429 ;; The 7200 has a store-load penalty
430 (define_insn_reservation "Y8" 2
431 (and (eq_attr "type" "store")
432 (eq_attr "cpu" "7200"))
433 "i1_7100lc,mem_7100lc")
435 (define_insn_reservation "Y9" 2
436 (and (eq_attr "type" "fpstore")
437 (eq_attr "cpu" "7200"))
438 "i1_7100lc,mem_7100lc")
440 ;; The 7300 has no penalty for store-store or store-load
441 (define_insn_reservation "Y10" 2
442 (and (eq_attr "type" "store")
443 (eq_attr "cpu" "7300"))
446 (define_insn_reservation "Y11" 2
447 (and (eq_attr "type" "fpstore")
448 (eq_attr "cpu" "7300"))
451 ;; We have an "anti-bypass" for FP loads which feed an FP store.
452 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
454 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
455 ;; traditional architecture.
457 ;; The PA8000 has a large (56) entry reorder buffer that is split between
458 ;; memory and non-memory operations.
460 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
461 ;; the function units, with the exception of branches and multi-output
462 ;; instructions. The PA8000 can retire two non-memory operations per cycle
463 ;; and two memory operations per cycle, only one of which may be a store.
465 ;; Given the large reorder buffer, the processor can hide most latencies.
466 ;; According to HP, they've got the best results by scheduling for retirement
467 ;; bandwidth with limited latency scheduling for floating point operations.
468 ;; Latency for integer operations and memory references is ignored.
471 ;; We claim floating point operations have a 2 cycle latency and are
472 ;; fully pipelined, except for div and sqrt which are not pipelined and
473 ;; take from 17 to 31 cycles to complete.
475 ;; It's worth noting that there is no way to saturate all the functional
476 ;; units on the PA8000 as there is not enough issue bandwidth.
478 (define_automaton "pa8000")
479 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
480 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
481 (define_cpu_unit "store_8000" "pa8000")
482 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
483 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
484 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
485 (define_reservation "im_8000" "im0_8000 | im1_8000")
486 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
487 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
488 (define_reservation "f_8000" "f0_8000 | f1_8000")
489 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
491 ;; We can issue any two memops per cycle, but we can only retire
492 ;; one memory store per cycle. We assume that the reorder buffer
493 ;; will hide any memory latencies per HP's recommendation.
494 (define_insn_reservation "Z0" 0
496 (eq_attr "type" "load,fpload")
497 (eq_attr "cpu" "8000"))
500 (define_insn_reservation "Z1" 0
502 (eq_attr "type" "store,fpstore")
503 (eq_attr "cpu" "8000"))
504 "im_8000,rm_8000+store_8000")
506 ;; We can issue and retire two non-memory operations per cycle with
507 ;; a few exceptions (branches). This group catches those we want
508 ;; to assume have zero latency.
509 (define_insn_reservation "Z2" 0
511 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
512 (eq_attr "cpu" "8000"))
515 ;; Branches use both slots in the non-memory issue and
517 (define_insn_reservation "Z3" 0
519 (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
520 (eq_attr "cpu" "8000"))
521 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
523 ;; We partial latency schedule the floating point units.
524 ;; They can issue/retire two at a time in the non-memory
525 ;; units. We fix their latency at 2 cycles and they
526 ;; are fully pipelined.
527 (define_insn_reservation "Z4" 1
529 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
530 (eq_attr "cpu" "8000"))
531 "inm_8000,f_8000,rnm_8000")
533 ;; The fdivsqrt units are not pipelined and have a very long latency.
534 ;; To keep the DFA from exploding, we do not show all the
535 ;; reservations for the divsqrt unit.
536 (define_insn_reservation "Z5" 17
538 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
539 (eq_attr "cpu" "8000"))
540 "inm_8000,fdivsqrt_8000*6,rnm_8000")
542 (define_insn_reservation "Z6" 31
544 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
545 (eq_attr "cpu" "8000"))
546 "inm_8000,fdivsqrt_8000*6,rnm_8000")
550 ;; Compare instructions.
551 ;; This controls RTL generation and register allocation.
553 ;; We generate RTL for comparisons and branches by having the cmpxx
554 ;; patterns store away the operands. Then, the scc and bcc patterns
555 ;; emit RTL for both the compare and the branch.
558 (define_expand "cmpdi"
560 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
561 (match_operand:DI 1 "register_operand" "")))]
566 hppa_compare_op0 = operands[0];
567 hppa_compare_op1 = operands[1];
568 hppa_branch_type = CMP_SI;
572 (define_expand "cmpsi"
574 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
575 (match_operand:SI 1 "arith5_operand" "")))]
579 hppa_compare_op0 = operands[0];
580 hppa_compare_op1 = operands[1];
581 hppa_branch_type = CMP_SI;
585 (define_expand "cmpsf"
587 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
588 (match_operand:SF 1 "reg_or_0_operand" "")))]
589 "! TARGET_SOFT_FLOAT"
592 hppa_compare_op0 = operands[0];
593 hppa_compare_op1 = operands[1];
594 hppa_branch_type = CMP_SF;
598 (define_expand "cmpdf"
600 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
601 (match_operand:DF 1 "reg_or_0_operand" "")))]
602 "! TARGET_SOFT_FLOAT"
605 hppa_compare_op0 = operands[0];
606 hppa_compare_op1 = operands[1];
607 hppa_branch_type = CMP_DF;
613 (match_operator:CCFP 2 "comparison_operator"
614 [(match_operand:SF 0 "reg_or_0_operand" "fG")
615 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
616 "! TARGET_SOFT_FLOAT"
617 "fcmp,sgl,%Y2 %f0,%f1"
618 [(set_attr "length" "4")
619 (set_attr "type" "fpcc")])
623 (match_operator:CCFP 2 "comparison_operator"
624 [(match_operand:DF 0 "reg_or_0_operand" "fG")
625 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
626 "! TARGET_SOFT_FLOAT"
627 "fcmp,dbl,%Y2 %f0,%f1"
628 [(set_attr "length" "4")
629 (set_attr "type" "fpcc")])
634 [(set (match_operand:SI 0 "register_operand" "")
640 /* fp scc patterns rarely match, and are not a win on the PA. */
641 if (hppa_branch_type != CMP_SI)
643 /* set up operands from compare. */
644 operands[1] = hppa_compare_op0;
645 operands[2] = hppa_compare_op1;
646 /* fall through and generate default code */
650 [(set (match_operand:SI 0 "register_operand" "")
656 /* fp scc patterns rarely match, and are not a win on the PA. */
657 if (hppa_branch_type != CMP_SI)
659 operands[1] = hppa_compare_op0;
660 operands[2] = hppa_compare_op1;
664 [(set (match_operand:SI 0 "register_operand" "")
670 /* fp scc patterns rarely match, and are not a win on the PA. */
671 if (hppa_branch_type != CMP_SI)
673 operands[1] = hppa_compare_op0;
674 operands[2] = hppa_compare_op1;
678 [(set (match_operand:SI 0 "register_operand" "")
684 /* fp scc patterns rarely match, and are not a win on the PA. */
685 if (hppa_branch_type != CMP_SI)
687 operands[1] = hppa_compare_op0;
688 operands[2] = hppa_compare_op1;
692 [(set (match_operand:SI 0 "register_operand" "")
698 /* fp scc patterns rarely match, and are not a win on the PA. */
699 if (hppa_branch_type != CMP_SI)
701 operands[1] = hppa_compare_op0;
702 operands[2] = hppa_compare_op1;
706 [(set (match_operand:SI 0 "register_operand" "")
712 /* fp scc patterns rarely match, and are not a win on the PA. */
713 if (hppa_branch_type != CMP_SI)
715 operands[1] = hppa_compare_op0;
716 operands[2] = hppa_compare_op1;
719 (define_expand "sltu"
720 [(set (match_operand:SI 0 "register_operand" "")
721 (ltu:SI (match_dup 1)
726 if (hppa_branch_type != CMP_SI)
728 operands[1] = hppa_compare_op0;
729 operands[2] = hppa_compare_op1;
732 (define_expand "sgtu"
733 [(set (match_operand:SI 0 "register_operand" "")
734 (gtu:SI (match_dup 1)
739 if (hppa_branch_type != CMP_SI)
741 operands[1] = hppa_compare_op0;
742 operands[2] = hppa_compare_op1;
745 (define_expand "sleu"
746 [(set (match_operand:SI 0 "register_operand" "")
747 (leu:SI (match_dup 1)
752 if (hppa_branch_type != CMP_SI)
754 operands[1] = hppa_compare_op0;
755 operands[2] = hppa_compare_op1;
758 (define_expand "sgeu"
759 [(set (match_operand:SI 0 "register_operand" "")
760 (geu:SI (match_dup 1)
765 if (hppa_branch_type != CMP_SI)
767 operands[1] = hppa_compare_op0;
768 operands[2] = hppa_compare_op1;
771 ;; Instruction canonicalization puts immediate operands second, which
772 ;; is the reverse of what we want.
775 [(set (match_operand:SI 0 "register_operand" "=r")
776 (match_operator:SI 3 "comparison_operator"
777 [(match_operand:SI 1 "register_operand" "r")
778 (match_operand:SI 2 "arith11_operand" "rI")]))]
780 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
781 [(set_attr "type" "binary")
782 (set_attr "length" "8")])
785 [(set (match_operand:DI 0 "register_operand" "=r")
786 (match_operator:DI 3 "comparison_operator"
787 [(match_operand:DI 1 "register_operand" "r")
788 (match_operand:DI 2 "arith11_operand" "rI")]))]
790 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
791 [(set_attr "type" "binary")
792 (set_attr "length" "8")])
794 (define_insn "iorscc"
795 [(set (match_operand:SI 0 "register_operand" "=r")
796 (ior:SI (match_operator:SI 3 "comparison_operator"
797 [(match_operand:SI 1 "register_operand" "r")
798 (match_operand:SI 2 "arith11_operand" "rI")])
799 (match_operator:SI 6 "comparison_operator"
800 [(match_operand:SI 4 "register_operand" "r")
801 (match_operand:SI 5 "arith11_operand" "rI")])))]
803 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
804 [(set_attr "type" "binary")
805 (set_attr "length" "12")])
808 [(set (match_operand:DI 0 "register_operand" "=r")
809 (ior:DI (match_operator:DI 3 "comparison_operator"
810 [(match_operand:DI 1 "register_operand" "r")
811 (match_operand:DI 2 "arith11_operand" "rI")])
812 (match_operator:DI 6 "comparison_operator"
813 [(match_operand:DI 4 "register_operand" "r")
814 (match_operand:DI 5 "arith11_operand" "rI")])))]
816 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
817 [(set_attr "type" "binary")
818 (set_attr "length" "12")])
820 ;; Combiner patterns for common operations performed with the output
821 ;; from an scc insn (negscc and incscc).
822 (define_insn "negscc"
823 [(set (match_operand:SI 0 "register_operand" "=r")
824 (neg:SI (match_operator:SI 3 "comparison_operator"
825 [(match_operand:SI 1 "register_operand" "r")
826 (match_operand:SI 2 "arith11_operand" "rI")])))]
828 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
829 [(set_attr "type" "binary")
830 (set_attr "length" "8")])
833 [(set (match_operand:DI 0 "register_operand" "=r")
834 (neg:DI (match_operator:DI 3 "comparison_operator"
835 [(match_operand:DI 1 "register_operand" "r")
836 (match_operand:DI 2 "arith11_operand" "rI")])))]
838 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
839 [(set_attr "type" "binary")
840 (set_attr "length" "8")])
842 ;; Patterns for adding/subtracting the result of a boolean expression from
843 ;; a register. First we have special patterns that make use of the carry
844 ;; bit, and output only two instructions. For the cases we can't in
845 ;; general do in two instructions, the incscc pattern at the end outputs
846 ;; two or three instructions.
849 [(set (match_operand:SI 0 "register_operand" "=r")
850 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
851 (match_operand:SI 3 "arith11_operand" "rI"))
852 (match_operand:SI 1 "register_operand" "r")))]
854 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
855 [(set_attr "type" "binary")
856 (set_attr "length" "8")])
859 [(set (match_operand:DI 0 "register_operand" "=r")
860 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
861 (match_operand:DI 3 "arith11_operand" "rI"))
862 (match_operand:DI 1 "register_operand" "r")))]
864 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
865 [(set_attr "type" "binary")
866 (set_attr "length" "8")])
868 ; This need only accept registers for op3, since canonicalization
869 ; replaces geu with gtu when op3 is an integer.
871 [(set (match_operand:SI 0 "register_operand" "=r")
872 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
873 (match_operand:SI 3 "register_operand" "r"))
874 (match_operand:SI 1 "register_operand" "r")))]
876 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
877 [(set_attr "type" "binary")
878 (set_attr "length" "8")])
881 [(set (match_operand:DI 0 "register_operand" "=r")
882 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
883 (match_operand:DI 3 "register_operand" "r"))
884 (match_operand:DI 1 "register_operand" "r")))]
886 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
887 [(set_attr "type" "binary")
888 (set_attr "length" "8")])
890 ; Match only integers for op3 here. This is used as canonical form of the
891 ; geu pattern when op3 is an integer. Don't match registers since we can't
892 ; make better code than the general incscc pattern.
894 [(set (match_operand:SI 0 "register_operand" "=r")
895 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
896 (match_operand:SI 3 "int11_operand" "I"))
897 (match_operand:SI 1 "register_operand" "r")))]
899 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
900 [(set_attr "type" "binary")
901 (set_attr "length" "8")])
904 [(set (match_operand:DI 0 "register_operand" "=r")
905 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
906 (match_operand:DI 3 "int11_operand" "I"))
907 (match_operand:DI 1 "register_operand" "r")))]
909 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
910 [(set_attr "type" "binary")
911 (set_attr "length" "8")])
913 (define_insn "incscc"
914 [(set (match_operand:SI 0 "register_operand" "=r,r")
915 (plus:SI (match_operator:SI 4 "comparison_operator"
916 [(match_operand:SI 2 "register_operand" "r,r")
917 (match_operand:SI 3 "arith11_operand" "rI,rI")])
918 (match_operand:SI 1 "register_operand" "0,?r")))]
921 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
922 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
923 [(set_attr "type" "binary,binary")
924 (set_attr "length" "8,12")])
927 [(set (match_operand:DI 0 "register_operand" "=r,r")
928 (plus:DI (match_operator:DI 4 "comparison_operator"
929 [(match_operand:DI 2 "register_operand" "r,r")
930 (match_operand:DI 3 "arith11_operand" "rI,rI")])
931 (match_operand:DI 1 "register_operand" "0,?r")))]
934 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
935 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
936 [(set_attr "type" "binary,binary")
937 (set_attr "length" "8,12")])
940 [(set (match_operand:SI 0 "register_operand" "=r")
941 (minus:SI (match_operand:SI 1 "register_operand" "r")
942 (gtu:SI (match_operand:SI 2 "register_operand" "r")
943 (match_operand:SI 3 "arith11_operand" "rI"))))]
945 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
946 [(set_attr "type" "binary")
947 (set_attr "length" "8")])
950 [(set (match_operand:DI 0 "register_operand" "=r")
951 (minus:DI (match_operand:DI 1 "register_operand" "r")
952 (gtu:DI (match_operand:DI 2 "register_operand" "r")
953 (match_operand:DI 3 "arith11_operand" "rI"))))]
955 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
956 [(set_attr "type" "binary")
957 (set_attr "length" "8")])
960 [(set (match_operand:SI 0 "register_operand" "=r")
961 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
962 (gtu:SI (match_operand:SI 2 "register_operand" "r")
963 (match_operand:SI 3 "arith11_operand" "rI")))
964 (match_operand:SI 4 "register_operand" "r")))]
966 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
967 [(set_attr "type" "binary")
968 (set_attr "length" "8")])
971 [(set (match_operand:DI 0 "register_operand" "=r")
972 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
973 (gtu:DI (match_operand:DI 2 "register_operand" "r")
974 (match_operand:DI 3 "arith11_operand" "rI")))
975 (match_operand:DI 4 "register_operand" "r")))]
977 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
978 [(set_attr "type" "binary")
979 (set_attr "length" "8")])
981 ; This need only accept registers for op3, since canonicalization
982 ; replaces ltu with leu when op3 is an integer.
984 [(set (match_operand:SI 0 "register_operand" "=r")
985 (minus:SI (match_operand:SI 1 "register_operand" "r")
986 (ltu:SI (match_operand:SI 2 "register_operand" "r")
987 (match_operand:SI 3 "register_operand" "r"))))]
989 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
990 [(set_attr "type" "binary")
991 (set_attr "length" "8")])
994 [(set (match_operand:DI 0 "register_operand" "=r")
995 (minus:DI (match_operand:DI 1 "register_operand" "r")
996 (ltu:DI (match_operand:DI 2 "register_operand" "r")
997 (match_operand:DI 3 "register_operand" "r"))))]
999 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1000 [(set_attr "type" "binary")
1001 (set_attr "length" "8")])
1004 [(set (match_operand:SI 0 "register_operand" "=r")
1005 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1006 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1007 (match_operand:SI 3 "register_operand" "r")))
1008 (match_operand:SI 4 "register_operand" "r")))]
1010 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1011 [(set_attr "type" "binary")
1012 (set_attr "length" "8")])
1015 [(set (match_operand:DI 0 "register_operand" "=r")
1016 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1017 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1018 (match_operand:DI 3 "register_operand" "r")))
1019 (match_operand:DI 4 "register_operand" "r")))]
1021 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1022 [(set_attr "type" "binary")
1023 (set_attr "length" "8")])
1025 ; Match only integers for op3 here. This is used as canonical form of the
1026 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1027 ; make better code than the general incscc pattern.
1029 [(set (match_operand:SI 0 "register_operand" "=r")
1030 (minus:SI (match_operand:SI 1 "register_operand" "r")
1031 (leu:SI (match_operand:SI 2 "register_operand" "r")
1032 (match_operand:SI 3 "int11_operand" "I"))))]
1034 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1035 [(set_attr "type" "binary")
1036 (set_attr "length" "8")])
1039 [(set (match_operand:DI 0 "register_operand" "=r")
1040 (minus:DI (match_operand:DI 1 "register_operand" "r")
1041 (leu:DI (match_operand:DI 2 "register_operand" "r")
1042 (match_operand:DI 3 "int11_operand" "I"))))]
1044 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1045 [(set_attr "type" "binary")
1046 (set_attr "length" "8")])
1049 [(set (match_operand:SI 0 "register_operand" "=r")
1050 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1051 (leu:SI (match_operand:SI 2 "register_operand" "r")
1052 (match_operand:SI 3 "int11_operand" "I")))
1053 (match_operand:SI 4 "register_operand" "r")))]
1055 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1056 [(set_attr "type" "binary")
1057 (set_attr "length" "8")])
1060 [(set (match_operand:DI 0 "register_operand" "=r")
1061 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1062 (leu:DI (match_operand:DI 2 "register_operand" "r")
1063 (match_operand:DI 3 "int11_operand" "I")))
1064 (match_operand:DI 4 "register_operand" "r")))]
1066 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1067 [(set_attr "type" "binary")
1068 (set_attr "length" "8")])
1070 (define_insn "decscc"
1071 [(set (match_operand:SI 0 "register_operand" "=r,r")
1072 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1073 (match_operator:SI 4 "comparison_operator"
1074 [(match_operand:SI 2 "register_operand" "r,r")
1075 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1078 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1079 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1080 [(set_attr "type" "binary,binary")
1081 (set_attr "length" "8,12")])
1084 [(set (match_operand:DI 0 "register_operand" "=r,r")
1085 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1086 (match_operator:DI 4 "comparison_operator"
1087 [(match_operand:DI 2 "register_operand" "r,r")
1088 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1091 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1092 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1093 [(set_attr "type" "binary,binary")
1094 (set_attr "length" "8,12")])
1096 ; Patterns for max and min. (There is no need for an earlyclobber in the
1097 ; last alternative since the middle alternative will match if op0 == op1.)
1099 (define_insn "sminsi3"
1100 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1101 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1102 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1105 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1106 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1107 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1108 [(set_attr "type" "multi,multi,multi")
1109 (set_attr "length" "8,8,8")])
1111 (define_insn "smindi3"
1112 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1113 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1114 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1117 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1118 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1119 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1120 [(set_attr "type" "multi,multi,multi")
1121 (set_attr "length" "8,8,8")])
1123 (define_insn "uminsi3"
1124 [(set (match_operand:SI 0 "register_operand" "=r,r")
1125 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1126 (match_operand:SI 2 "arith11_operand" "r,I")))]
1129 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1130 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1131 [(set_attr "type" "multi,multi")
1132 (set_attr "length" "8,8")])
1134 (define_insn "umindi3"
1135 [(set (match_operand:DI 0 "register_operand" "=r,r")
1136 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1137 (match_operand:DI 2 "arith11_operand" "r,I")))]
1140 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1141 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1142 [(set_attr "type" "multi,multi")
1143 (set_attr "length" "8,8")])
1145 (define_insn "smaxsi3"
1146 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1147 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1148 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1151 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1152 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1153 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1154 [(set_attr "type" "multi,multi,multi")
1155 (set_attr "length" "8,8,8")])
1157 (define_insn "smaxdi3"
1158 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1159 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1160 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1163 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1164 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1165 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1166 [(set_attr "type" "multi,multi,multi")
1167 (set_attr "length" "8,8,8")])
1169 (define_insn "umaxsi3"
1170 [(set (match_operand:SI 0 "register_operand" "=r,r")
1171 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1172 (match_operand:SI 2 "arith11_operand" "r,I")))]
1175 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1176 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1177 [(set_attr "type" "multi,multi")
1178 (set_attr "length" "8,8")])
1180 (define_insn "umaxdi3"
1181 [(set (match_operand:DI 0 "register_operand" "=r,r")
1182 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1183 (match_operand:DI 2 "arith11_operand" "r,I")))]
1186 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1187 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1188 [(set_attr "type" "multi,multi")
1189 (set_attr "length" "8,8")])
1191 (define_insn "abssi2"
1192 [(set (match_operand:SI 0 "register_operand" "=r")
1193 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1195 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1196 [(set_attr "type" "multi")
1197 (set_attr "length" "8")])
1199 (define_insn "absdi2"
1200 [(set (match_operand:DI 0 "register_operand" "=r")
1201 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1203 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1204 [(set_attr "type" "multi")
1205 (set_attr "length" "8")])
1207 ;;; Experimental conditional move patterns
1209 (define_expand "movsicc"
1210 [(set (match_operand:SI 0 "register_operand" "")
1212 (match_operator 1 "comparison_operator"
1215 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1216 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1220 enum rtx_code code = GET_CODE (operands[1]);
1222 if (hppa_branch_type != CMP_SI)
1225 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1226 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1229 /* operands[1] is currently the result of compare_from_rtx. We want to
1230 emit a compare of the original operands. */
1231 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1232 operands[4] = hppa_compare_op0;
1233 operands[5] = hppa_compare_op1;
1236 ;; We used to accept any register for op1.
1238 ;; However, it loses sometimes because the compiler will end up using
1239 ;; different registers for op0 and op1 in some critical cases. local-alloc
1240 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1242 ;; If/when global register allocation supports tying we should allow any
1243 ;; register for op1 again.
1245 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1247 (match_operator 2 "comparison_operator"
1248 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1249 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1250 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1254 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1255 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1256 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1257 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1258 [(set_attr "type" "multi,multi,multi,nullshift")
1259 (set_attr "length" "8,8,8,8")])
1262 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1264 (match_operator 5 "comparison_operator"
1265 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1266 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1267 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1268 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1271 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1272 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1273 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1274 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1275 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1276 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1277 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1278 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1279 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1280 (set_attr "length" "8,8,8,8,8,8,8,8")])
1282 (define_expand "movdicc"
1283 [(set (match_operand:DI 0 "register_operand" "")
1285 (match_operator 1 "comparison_operator"
1288 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1289 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1293 enum rtx_code code = GET_CODE (operands[1]);
1295 if (hppa_branch_type != CMP_SI)
1298 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1299 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1302 /* operands[1] is currently the result of compare_from_rtx. We want to
1303 emit a compare of the original operands. */
1304 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1305 operands[4] = hppa_compare_op0;
1306 operands[5] = hppa_compare_op1;
1309 ; We need the first constraint alternative in order to avoid
1310 ; earlyclobbers on all other alternatives.
1312 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1314 (match_operator 2 "comparison_operator"
1315 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1316 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1317 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1321 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1322 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1323 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1324 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1325 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1326 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1327 (set_attr "length" "8,8,8,8,8")])
1330 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1332 (match_operator 5 "comparison_operator"
1333 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1334 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1335 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1336 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1339 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1340 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1341 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1342 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1343 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1344 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1345 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1346 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1347 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1348 (set_attr "length" "8,8,8,8,8,8,8,8")])
1350 ;; Conditional Branches
1352 (define_expand "beq"
1354 (if_then_else (eq (match_dup 1) (match_dup 2))
1355 (label_ref (match_operand 0 "" ""))
1360 if (hppa_branch_type != CMP_SI)
1362 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1363 emit_bcond_fp (NE, operands[0]);
1366 /* set up operands from compare. */
1367 operands[1] = hppa_compare_op0;
1368 operands[2] = hppa_compare_op1;
1369 /* fall through and generate default code */
1372 (define_expand "bne"
1374 (if_then_else (ne (match_dup 1) (match_dup 2))
1375 (label_ref (match_operand 0 "" ""))
1380 if (hppa_branch_type != CMP_SI)
1382 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1383 emit_bcond_fp (NE, operands[0]);
1386 operands[1] = hppa_compare_op0;
1387 operands[2] = hppa_compare_op1;
1390 (define_expand "bgt"
1392 (if_then_else (gt (match_dup 1) (match_dup 2))
1393 (label_ref (match_operand 0 "" ""))
1398 if (hppa_branch_type != CMP_SI)
1400 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1401 emit_bcond_fp (NE, operands[0]);
1404 operands[1] = hppa_compare_op0;
1405 operands[2] = hppa_compare_op1;
1408 (define_expand "blt"
1410 (if_then_else (lt (match_dup 1) (match_dup 2))
1411 (label_ref (match_operand 0 "" ""))
1416 if (hppa_branch_type != CMP_SI)
1418 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1419 emit_bcond_fp (NE, operands[0]);
1422 operands[1] = hppa_compare_op0;
1423 operands[2] = hppa_compare_op1;
1426 (define_expand "bge"
1428 (if_then_else (ge (match_dup 1) (match_dup 2))
1429 (label_ref (match_operand 0 "" ""))
1434 if (hppa_branch_type != CMP_SI)
1436 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1437 emit_bcond_fp (NE, operands[0]);
1440 operands[1] = hppa_compare_op0;
1441 operands[2] = hppa_compare_op1;
1444 (define_expand "ble"
1446 (if_then_else (le (match_dup 1) (match_dup 2))
1447 (label_ref (match_operand 0 "" ""))
1452 if (hppa_branch_type != CMP_SI)
1454 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1455 emit_bcond_fp (NE, operands[0]);
1458 operands[1] = hppa_compare_op0;
1459 operands[2] = hppa_compare_op1;
1462 (define_expand "bgtu"
1464 (if_then_else (gtu (match_dup 1) (match_dup 2))
1465 (label_ref (match_operand 0 "" ""))
1470 if (hppa_branch_type != CMP_SI)
1472 operands[1] = hppa_compare_op0;
1473 operands[2] = hppa_compare_op1;
1476 (define_expand "bltu"
1478 (if_then_else (ltu (match_dup 1) (match_dup 2))
1479 (label_ref (match_operand 0 "" ""))
1484 if (hppa_branch_type != CMP_SI)
1486 operands[1] = hppa_compare_op0;
1487 operands[2] = hppa_compare_op1;
1490 (define_expand "bgeu"
1492 (if_then_else (geu (match_dup 1) (match_dup 2))
1493 (label_ref (match_operand 0 "" ""))
1498 if (hppa_branch_type != CMP_SI)
1500 operands[1] = hppa_compare_op0;
1501 operands[2] = hppa_compare_op1;
1504 (define_expand "bleu"
1506 (if_then_else (leu (match_dup 1) (match_dup 2))
1507 (label_ref (match_operand 0 "" ""))
1512 if (hppa_branch_type != CMP_SI)
1514 operands[1] = hppa_compare_op0;
1515 operands[2] = hppa_compare_op1;
1518 (define_expand "bltgt"
1520 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1521 (label_ref (match_operand 0 "" ""))
1526 if (hppa_branch_type == CMP_SI)
1528 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1529 emit_bcond_fp (NE, operands[0]);
1533 (define_expand "bunle"
1535 (if_then_else (unle (match_dup 1) (match_dup 2))
1536 (label_ref (match_operand 0 "" ""))
1541 if (hppa_branch_type == CMP_SI)
1543 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1544 emit_bcond_fp (NE, operands[0]);
1548 (define_expand "bunlt"
1550 (if_then_else (unlt (match_dup 1) (match_dup 2))
1551 (label_ref (match_operand 0 "" ""))
1556 if (hppa_branch_type == CMP_SI)
1558 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1559 emit_bcond_fp (NE, operands[0]);
1563 (define_expand "bunge"
1565 (if_then_else (unge (match_dup 1) (match_dup 2))
1566 (label_ref (match_operand 0 "" ""))
1571 if (hppa_branch_type == CMP_SI)
1573 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1574 emit_bcond_fp (NE, operands[0]);
1578 (define_expand "bungt"
1580 (if_then_else (ungt (match_dup 1) (match_dup 2))
1581 (label_ref (match_operand 0 "" ""))
1586 if (hppa_branch_type == CMP_SI)
1588 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1589 emit_bcond_fp (NE, operands[0]);
1593 (define_expand "buneq"
1595 (if_then_else (uneq (match_dup 1) (match_dup 2))
1596 (label_ref (match_operand 0 "" ""))
1601 if (hppa_branch_type == CMP_SI)
1603 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1604 emit_bcond_fp (NE, operands[0]);
1608 (define_expand "bunordered"
1610 (if_then_else (unordered (match_dup 1) (match_dup 2))
1611 (label_ref (match_operand 0 "" ""))
1616 if (hppa_branch_type == CMP_SI)
1618 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1619 emit_bcond_fp (NE, operands[0]);
1623 (define_expand "bordered"
1625 (if_then_else (ordered (match_dup 1) (match_dup 2))
1626 (label_ref (match_operand 0 "" ""))
1631 if (hppa_branch_type == CMP_SI)
1633 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1634 emit_bcond_fp (NE, operands[0]);
1638 ;; Match the branch patterns.
1641 ;; Note a long backward conditional branch with an annulled delay slot
1642 ;; has a length of 12.
1646 (match_operator 3 "comparison_operator"
1647 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1648 (match_operand:SI 2 "arith5_operand" "rL")])
1649 (label_ref (match_operand 0 "" ""))
1654 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1655 get_attr_length (insn), 0, insn);
1657 [(set_attr "type" "cbranch")
1658 (set (attr "length")
1659 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1662 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1665 (eq (symbol_ref "flag_pic") (const_int 0))
1669 ;; Match the negated branch.
1674 (match_operator 3 "comparison_operator"
1675 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1676 (match_operand:SI 2 "arith5_operand" "rL")])
1678 (label_ref (match_operand 0 "" ""))))]
1682 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1683 get_attr_length (insn), 1, insn);
1685 [(set_attr "type" "cbranch")
1686 (set (attr "length")
1687 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1690 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (eq (symbol_ref "flag_pic") (const_int 0))
1700 (match_operator 3 "comparison_operator"
1701 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1702 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1703 (label_ref (match_operand 0 "" ""))
1708 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1709 get_attr_length (insn), 0, insn);
1711 [(set_attr "type" "cbranch")
1712 (set (attr "length")
1713 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1716 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1719 (eq (symbol_ref "flag_pic") (const_int 0))
1723 ;; Match the negated branch.
1728 (match_operator 3 "comparison_operator"
1729 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1730 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1732 (label_ref (match_operand 0 "" ""))))]
1736 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1737 get_attr_length (insn), 1, insn);
1739 [(set_attr "type" "cbranch")
1740 (set (attr "length")
1741 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1744 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (eq (symbol_ref "flag_pic") (const_int 0))
1753 (match_operator 3 "cmpib_comparison_operator"
1754 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1755 (match_operand:DI 2 "arith5_operand" "rL")])
1756 (label_ref (match_operand 0 "" ""))
1761 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1762 get_attr_length (insn), 0, insn);
1764 [(set_attr "type" "cbranch")
1765 (set (attr "length")
1766 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1769 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1772 (eq (symbol_ref "flag_pic") (const_int 0))
1776 ;; Match the negated branch.
1781 (match_operator 3 "cmpib_comparison_operator"
1782 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1783 (match_operand:DI 2 "arith5_operand" "rL")])
1785 (label_ref (match_operand 0 "" ""))))]
1789 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1790 get_attr_length (insn), 1, insn);
1792 [(set_attr "type" "cbranch")
1793 (set (attr "length")
1794 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1797 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (eq (symbol_ref "flag_pic") (const_int 0))
1804 ;; Branch on Bit patterns.
1808 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1810 (match_operand:SI 1 "uint5_operand" ""))
1812 (label_ref (match_operand 2 "" ""))
1817 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1818 get_attr_length (insn), 0, insn, 0);
1820 [(set_attr "type" "cbranch")
1821 (set (attr "length")
1822 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1830 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1832 (match_operand:DI 1 "uint32_operand" ""))
1834 (label_ref (match_operand 2 "" ""))
1839 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1840 get_attr_length (insn), 0, insn, 0);
1842 [(set_attr "type" "cbranch")
1843 (set (attr "length")
1844 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1852 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1854 (match_operand:SI 1 "uint5_operand" ""))
1857 (label_ref (match_operand 2 "" ""))))]
1861 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1862 get_attr_length (insn), 1, insn, 0);
1864 [(set_attr "type" "cbranch")
1865 (set (attr "length")
1866 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1874 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1876 (match_operand:DI 1 "uint32_operand" ""))
1879 (label_ref (match_operand 2 "" ""))))]
1883 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1884 get_attr_length (insn), 1, insn, 0);
1886 [(set_attr "type" "cbranch")
1887 (set (attr "length")
1888 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1896 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1898 (match_operand:SI 1 "uint5_operand" ""))
1900 (label_ref (match_operand 2 "" ""))
1905 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1906 get_attr_length (insn), 0, insn, 1);
1908 [(set_attr "type" "cbranch")
1909 (set (attr "length")
1910 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1918 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1920 (match_operand:DI 1 "uint32_operand" ""))
1922 (label_ref (match_operand 2 "" ""))
1927 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1928 get_attr_length (insn), 0, insn, 1);
1930 [(set_attr "type" "cbranch")
1931 (set (attr "length")
1932 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1940 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1942 (match_operand:SI 1 "uint5_operand" ""))
1945 (label_ref (match_operand 2 "" ""))))]
1949 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1950 get_attr_length (insn), 1, insn, 1);
1952 [(set_attr "type" "cbranch")
1953 (set (attr "length")
1954 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1962 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1964 (match_operand:DI 1 "uint32_operand" ""))
1967 (label_ref (match_operand 2 "" ""))))]
1971 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1972 get_attr_length (insn), 1, insn, 1);
1974 [(set_attr "type" "cbranch")
1975 (set (attr "length")
1976 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1981 ;; Branch on Variable Bit patterns.
1985 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1987 (match_operand:SI 1 "register_operand" "q"))
1989 (label_ref (match_operand 2 "" ""))
1994 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1995 get_attr_length (insn), 0, insn, 0);
1997 [(set_attr "type" "cbranch")
1998 (set (attr "length")
1999 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2007 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2009 (match_operand:DI 1 "register_operand" "q"))
2011 (label_ref (match_operand 2 "" ""))
2016 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2017 get_attr_length (insn), 0, insn, 0);
2019 [(set_attr "type" "cbranch")
2020 (set (attr "length")
2021 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2029 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2031 (match_operand:SI 1 "register_operand" "q"))
2034 (label_ref (match_operand 2 "" ""))))]
2038 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2039 get_attr_length (insn), 1, insn, 0);
2041 [(set_attr "type" "cbranch")
2042 (set (attr "length")
2043 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2051 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2053 (match_operand:DI 1 "register_operand" "q"))
2056 (label_ref (match_operand 2 "" ""))))]
2060 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2061 get_attr_length (insn), 1, insn, 0);
2063 [(set_attr "type" "cbranch")
2064 (set (attr "length")
2065 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2073 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2075 (match_operand:SI 1 "register_operand" "q"))
2077 (label_ref (match_operand 2 "" ""))
2082 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2083 get_attr_length (insn), 0, insn, 1);
2085 [(set_attr "type" "cbranch")
2086 (set (attr "length")
2087 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2095 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2097 (match_operand:DI 1 "register_operand" "q"))
2099 (label_ref (match_operand 2 "" ""))
2104 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2105 get_attr_length (insn), 0, insn, 1);
2107 [(set_attr "type" "cbranch")
2108 (set (attr "length")
2109 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2117 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2119 (match_operand:SI 1 "register_operand" "q"))
2122 (label_ref (match_operand 2 "" ""))))]
2126 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2127 get_attr_length (insn), 1, insn, 1);
2129 [(set_attr "type" "cbranch")
2130 (set (attr "length")
2131 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2139 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2141 (match_operand:DI 1 "register_operand" "q"))
2144 (label_ref (match_operand 2 "" ""))))]
2148 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2149 get_attr_length (insn), 1, insn, 1);
2151 [(set_attr "type" "cbranch")
2152 (set (attr "length")
2153 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2158 ;; Floating point branches
2160 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2161 (label_ref (match_operand 0 "" ""))
2163 "! TARGET_SOFT_FLOAT"
2166 if (INSN_ANNULLED_BRANCH_P (insn))
2167 return \"ftest\;b,n %0\";
2169 return \"ftest\;b%* %0\";
2171 [(set_attr "type" "fbranch")
2172 (set_attr "length" "8")])
2175 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2177 (label_ref (match_operand 0 "" ""))))]
2178 "! TARGET_SOFT_FLOAT"
2181 if (INSN_ANNULLED_BRANCH_P (insn))
2182 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2184 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2186 [(set_attr "type" "fbranch")
2187 (set_attr "length" "12")])
2189 ;; Move instructions
2191 (define_expand "movsi"
2192 [(set (match_operand:SI 0 "general_operand" "")
2193 (match_operand:SI 1 "general_operand" ""))]
2197 if (emit_move_sequence (operands, SImode, 0))
2201 ;; Reloading an SImode or DImode value requires a scratch register if
2202 ;; going in to or out of float point registers.
2204 (define_expand "reload_insi"
2205 [(set (match_operand:SI 0 "register_operand" "=Z")
2206 (match_operand:SI 1 "non_hard_reg_operand" ""))
2207 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2211 if (emit_move_sequence (operands, SImode, operands[2]))
2214 /* We don't want the clobber emitted, so handle this ourselves. */
2215 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2219 (define_expand "reload_outsi"
2220 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2221 (match_operand:SI 1 "register_operand" "Z"))
2222 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2226 if (emit_move_sequence (operands, SImode, operands[2]))
2229 /* We don't want the clobber emitted, so handle this ourselves. */
2230 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2235 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2236 "=r,r,r,r,r,r,Q,*q,!f,f,*TR")
2237 (match_operand:SI 1 "move_operand"
2238 "A,r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
2239 "(register_operand (operands[0], SImode)
2240 || reg_or_0_operand (operands[1], SImode))
2241 && ! TARGET_SOFT_FLOAT"
2247 {zdepi|depwi,z} %Z1,%0
2254 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2255 (set_attr "pa_combine_type" "addmove")
2256 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
2259 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2260 "=r,r,r,r,r,r,Q,*q")
2261 (match_operand:SI 1 "move_operand"
2262 "A,r,J,N,K,RQ,rM,rM"))]
2263 "(register_operand (operands[0], SImode)
2264 || reg_or_0_operand (operands[1], SImode))
2265 && TARGET_SOFT_FLOAT"
2271 {zdepi|depwi,z} %Z1,%0
2275 [(set_attr "type" "load,move,move,move,move,load,store,move")
2276 (set_attr "pa_combine_type" "addmove")
2277 (set_attr "length" "4,4,4,4,4,4,4,4")])
2280 [(set (match_operand:SI 0 "register_operand" "=r")
2281 (mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2282 (match_operand:SI 2 "register_operand" "r"))))]
2283 "! TARGET_DISABLE_INDEXING"
2284 "{ldwx|ldw} %2(%1),%0"
2285 [(set_attr "type" "load")
2286 (set_attr "length" "4")])
2289 [(set (match_operand:SI 0 "register_operand" "=r")
2290 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2291 (match_operand:SI 2 "basereg_operand" "r"))))]
2292 "! TARGET_DISABLE_INDEXING"
2293 "{ldwx|ldw} %1(%2),%0"
2294 [(set_attr "type" "load")
2295 (set_attr "length" "4")])
2297 ;; Load or store with base-register modification.
2299 (define_expand "pre_load"
2300 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2301 (mem (plus (match_operand 1 "register_operand" "")
2302 (match_operand 2 "pre_cint_operand" ""))))
2304 (plus (match_dup 1) (match_dup 2)))])]
2310 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2313 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2317 (define_insn "pre_ldw"
2318 [(set (match_operand:SI 0 "register_operand" "=r")
2319 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2320 (match_operand:SI 2 "pre_cint_operand" ""))))
2322 (plus:SI (match_dup 1) (match_dup 2)))]
2326 if (INTVAL (operands[2]) < 0)
2327 return \"{ldwm|ldw,mb} %2(%1),%0\";
2328 return \"{ldws|ldw},mb %2(%1),%0\";
2330 [(set_attr "type" "load")
2331 (set_attr "length" "4")])
2333 (define_insn "pre_ldd"
2334 [(set (match_operand:DI 0 "register_operand" "=r")
2335 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2336 (match_operand:DI 2 "pre_cint_operand" ""))))
2338 (plus:DI (match_dup 1) (match_dup 2)))]
2341 [(set_attr "type" "load")
2342 (set_attr "length" "4")])
2345 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2346 (match_operand:SI 1 "pre_cint_operand" "")))
2347 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2349 (plus:SI (match_dup 0) (match_dup 1)))]
2353 if (INTVAL (operands[1]) < 0)
2354 return \"{stwm|stw,mb} %r2,%1(%0)\";
2355 return \"{stws|stw},mb %r2,%1(%0)\";
2357 [(set_attr "type" "store")
2358 (set_attr "length" "4")])
2361 [(set (match_operand:SI 0 "register_operand" "=r")
2362 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2364 (plus:SI (match_dup 1)
2365 (match_operand:SI 2 "post_cint_operand" "")))]
2369 if (INTVAL (operands[2]) > 0)
2370 return \"{ldwm|ldw,ma} %2(%1),%0\";
2371 return \"{ldws|ldw},ma %2(%1),%0\";
2373 [(set_attr "type" "load")
2374 (set_attr "length" "4")])
2376 (define_expand "post_store"
2377 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2378 (match_operand 1 "reg_or_0_operand" ""))
2381 (match_operand 2 "post_cint_operand" "")))])]
2387 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2390 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2394 (define_insn "post_stw"
2395 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2396 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2398 (plus:SI (match_dup 0)
2399 (match_operand:SI 2 "post_cint_operand" "")))]
2403 if (INTVAL (operands[2]) > 0)
2404 return \"{stwm|stw,ma} %r1,%2(%0)\";
2405 return \"{stws|stw},ma %r1,%2(%0)\";
2407 [(set_attr "type" "store")
2408 (set_attr "length" "4")])
2410 (define_insn "post_std"
2411 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2412 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2414 (plus:DI (match_dup 0)
2415 (match_operand:DI 2 "post_cint_operand" "")))]
2418 [(set_attr "type" "store")
2419 (set_attr "length" "4")])
2421 ;; For loading the address of a label while generating PIC code.
2422 ;; Note since this pattern can be created at reload time (via movsi), all
2423 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2425 [(set (match_operand 0 "pmode_register_operand" "=a")
2426 (match_operand 1 "pic_label_operand" ""))]
2431 extern FILE *asm_out_file;
2433 xoperands[0] = operands[0];
2434 xoperands[1] = operands[1];
2435 if (TARGET_SOM || ! TARGET_GAS)
2436 xoperands[2] = gen_label_rtx ();
2438 output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands);
2439 output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands);
2440 if (TARGET_SOM || ! TARGET_GAS)
2441 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2442 CODE_LABEL_NUMBER (xoperands[2]));
2444 /* If we're trying to load the address of a label that happens to be
2445 close, then we can use a shorter sequence. */
2446 if (GET_CODE (operands[1]) == LABEL_REF
2447 && INSN_ADDRESSES_SET_P ()
2448 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2449 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2451 /* Prefixing with R% here is wrong, it extracts just 11 bits and is
2452 always non-negative. */
2453 if (TARGET_SOM || ! TARGET_GAS)
2454 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2456 output_asm_insn (\"ldo %1-$PIC_pcrel$0+8(%0),%0\", xoperands);
2460 if (TARGET_SOM || ! TARGET_GAS)
2462 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2463 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2467 output_asm_insn (\"addil L%%%1-$PIC_pcrel$0+8,%0\", xoperands);
2468 output_asm_insn (\"ldo R%%%1-$PIC_pcrel$0+12(%0),%0\",
2474 [(set_attr "type" "multi")
2475 (set_attr "length" "16")]) ; 12 or 16
2478 [(set (match_operand:SI 0 "register_operand" "=a")
2479 (plus:SI (match_operand:SI 1 "register_operand" "r")
2480 (high:SI (match_operand 2 "" ""))))]
2481 "symbolic_operand (operands[2], Pmode)
2482 && ! function_label_operand (operands[2], Pmode)
2485 [(set_attr "type" "binary")
2486 (set_attr "length" "4")])
2489 [(set (match_operand:DI 0 "register_operand" "=a")
2490 (plus:DI (match_operand:DI 1 "register_operand" "r")
2491 (high:DI (match_operand 2 "" ""))))]
2492 "symbolic_operand (operands[2], Pmode)
2493 && ! function_label_operand (operands[2], Pmode)
2497 [(set_attr "type" "binary")
2498 (set_attr "length" "4")])
2500 ;; Always use addil rather than ldil;add sequences. This allows the
2501 ;; HP linker to eliminate the dp relocation if the symbolic operand
2502 ;; lives in the TEXT space.
2504 [(set (match_operand:SI 0 "register_operand" "=a")
2505 (high:SI (match_operand 1 "" "")))]
2506 "symbolic_operand (operands[1], Pmode)
2507 && ! function_label_operand (operands[1], Pmode)
2508 && ! read_only_operand (operands[1], Pmode)
2512 if (TARGET_LONG_LOAD_STORE)
2513 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2515 return \"addil LR'%H1,%%r27\";
2517 [(set_attr "type" "binary")
2518 (set (attr "length")
2519 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2524 ;; This is for use in the prologue/epilogue code. We need it
2525 ;; to add large constants to a stack pointer or frame pointer.
2526 ;; Because of the additional %r1 pressure, we probably do not
2527 ;; want to use this in general code, so make it available
2528 ;; only after reload.
2530 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2531 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2532 (high:SI (match_operand 2 "const_int_operand" ""))))]
2536 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2537 [(set_attr "type" "binary,binary")
2538 (set_attr "length" "4,8")])
2541 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2542 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2543 (high:DI (match_operand 2 "const_int_operand" ""))))]
2544 "reload_completed && TARGET_64BIT"
2547 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2548 [(set_attr "type" "binary,binary")
2549 (set_attr "length" "4,8")])
2552 [(set (match_operand:SI 0 "register_operand" "=r")
2553 (high:SI (match_operand 1 "" "")))]
2554 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2555 && !is_function_label_plus_const (operands[1])"
2558 if (symbolic_operand (operands[1], Pmode))
2559 return \"ldil LR'%H1,%0\";
2561 return \"ldil L'%G1,%0\";
2563 [(set_attr "type" "move")
2564 (set_attr "length" "4")])
2567 [(set (match_operand:DI 0 "register_operand" "=r")
2568 (high:DI (match_operand 1 "const_int_operand" "")))]
2571 [(set_attr "type" "move")
2572 (set_attr "length" "4")])
2575 [(set (match_operand:DI 0 "register_operand" "=r")
2576 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2577 (match_operand:DI 2 "const_int_operand" "i")))]
2580 [(set_attr "type" "move")
2581 (set_attr "length" "4")])
2584 [(set (match_operand:SI 0 "register_operand" "=r")
2585 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2586 (match_operand:SI 2 "immediate_operand" "i")))]
2587 "!is_function_label_plus_const (operands[2])"
2590 if (flag_pic && symbolic_operand (operands[2], Pmode))
2592 else if (symbolic_operand (operands[2], Pmode))
2593 return \"ldo RR'%G2(%1),%0\";
2595 return \"ldo R'%G2(%1),%0\";
2597 [(set_attr "type" "move")
2598 (set_attr "length" "4")])
2600 ;; Now that a symbolic_address plus a constant is broken up early
2601 ;; in the compilation phase (for better CSE) we need a special
2602 ;; combiner pattern to load the symbolic address plus the constant
2603 ;; in only 2 instructions. (For cases where the symbolic address
2604 ;; was not a common subexpression.)
2606 [(set (match_operand:SI 0 "register_operand" "")
2607 (match_operand:SI 1 "symbolic_operand" ""))
2608 (clobber (match_operand:SI 2 "register_operand" ""))]
2609 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2610 [(set (match_dup 2) (high:SI (match_dup 1)))
2611 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2614 ;; hppa_legitimize_address goes to a great deal of trouble to
2615 ;; create addresses which use indexing. In some cases, this
2616 ;; is a lose because there isn't any store instructions which
2617 ;; allow indexed addresses (with integer register source).
2619 ;; These define_splits try to turn a 3 insn store into
2620 ;; a 2 insn store with some creative RTL rewriting.
2622 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2623 (match_operand:SI 1 "shadd_operand" ""))
2624 (plus:SI (match_operand:SI 2 "register_operand" "")
2625 (match_operand:SI 3 "const_int_operand" ""))))
2626 (match_operand:SI 4 "register_operand" ""))
2627 (clobber (match_operand:SI 5 "register_operand" ""))]
2629 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2631 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2635 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2636 (match_operand:SI 1 "shadd_operand" ""))
2637 (plus:SI (match_operand:SI 2 "register_operand" "")
2638 (match_operand:SI 3 "const_int_operand" ""))))
2639 (match_operand:HI 4 "register_operand" ""))
2640 (clobber (match_operand:SI 5 "register_operand" ""))]
2642 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2644 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2648 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2649 (match_operand:SI 1 "shadd_operand" ""))
2650 (plus:SI (match_operand:SI 2 "register_operand" "")
2651 (match_operand:SI 3 "const_int_operand" ""))))
2652 (match_operand:QI 4 "register_operand" ""))
2653 (clobber (match_operand:SI 5 "register_operand" ""))]
2655 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2657 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2660 (define_expand "movhi"
2661 [(set (match_operand:HI 0 "general_operand" "")
2662 (match_operand:HI 1 "general_operand" ""))]
2666 if (emit_move_sequence (operands, HImode, 0))
2671 [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2672 (match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2673 "register_operand (operands[0], HImode)
2674 || reg_or_0_operand (operands[1], HImode)"
2679 {zdepi|depwi,z} %Z1,%0
2684 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2685 (set_attr "pa_combine_type" "addmove")
2686 (set_attr "length" "4,4,4,4,4,4,4,4")])
2689 [(set (match_operand:HI 0 "register_operand" "=r")
2690 (mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2691 (match_operand:SI 2 "register_operand" "r"))))]
2692 "! TARGET_DISABLE_INDEXING"
2693 "{ldhx|ldh} %2(%1),%0"
2694 [(set_attr "type" "load")
2695 (set_attr "length" "4")])
2698 [(set (match_operand:HI 0 "register_operand" "=r")
2699 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
2700 (match_operand:SI 2 "basereg_operand" "r"))))]
2701 "! TARGET_DISABLE_INDEXING"
2702 "{ldhx|ldh} %1(%2),%0"
2703 [(set_attr "type" "load")
2704 (set_attr "length" "4")])
2706 ; Now zero extended variants.
2708 [(set (match_operand:SI 0 "register_operand" "=r")
2709 (zero_extend:SI (mem:HI
2711 (match_operand:SI 1 "basereg_operand" "r")
2712 (match_operand:SI 2 "register_operand" "r")))))]
2713 "! TARGET_DISABLE_INDEXING"
2714 "{ldhx|ldh} %2(%1),%0"
2715 [(set_attr "type" "load")
2716 (set_attr "length" "4")])
2719 [(set (match_operand:SI 0 "register_operand" "=r")
2720 (zero_extend:SI (mem:HI
2722 (match_operand:SI 1 "register_operand" "r")
2723 (match_operand:SI 2 "basereg_operand" "r")))))]
2724 "! TARGET_DISABLE_INDEXING"
2725 "{ldhx|ldh} %1(%2),%0"
2726 [(set_attr "type" "load")
2727 (set_attr "length" "4")])
2730 [(set (match_operand:HI 0 "register_operand" "=r")
2731 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2732 (match_operand:SI 2 "int5_operand" "L"))))
2734 (plus:SI (match_dup 1) (match_dup 2)))]
2736 "{ldhs|ldh},mb %2(%1),%0"
2737 [(set_attr "type" "load")
2738 (set_attr "length" "4")])
2740 ; And a zero extended variant.
2742 [(set (match_operand:SI 0 "register_operand" "=r")
2743 (zero_extend:SI (mem:HI
2745 (match_operand:SI 1 "register_operand" "+r")
2746 (match_operand:SI 2 "int5_operand" "L")))))
2748 (plus:SI (match_dup 1) (match_dup 2)))]
2750 "{ldhs|ldh},mb %2(%1),%0"
2751 [(set_attr "type" "load")
2752 (set_attr "length" "4")])
2755 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2756 (match_operand:SI 1 "int5_operand" "L")))
2757 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2759 (plus:SI (match_dup 0) (match_dup 1)))]
2761 "{sths|sth},mb %r2,%1(%0)"
2762 [(set_attr "type" "store")
2763 (set_attr "length" "4")])
2766 [(set (match_operand:HI 0 "register_operand" "=r")
2767 (plus:HI (match_operand:HI 1 "register_operand" "r")
2768 (match_operand 2 "const_int_operand" "J")))]
2771 [(set_attr "type" "binary")
2772 (set_attr "pa_combine_type" "addmove")
2773 (set_attr "length" "4")])
2775 (define_expand "movqi"
2776 [(set (match_operand:QI 0 "general_operand" "")
2777 (match_operand:QI 1 "general_operand" ""))]
2781 if (emit_move_sequence (operands, QImode, 0))
2786 [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2787 (match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2788 "register_operand (operands[0], QImode)
2789 || reg_or_0_operand (operands[1], QImode)"
2794 {zdepi|depwi,z} %Z1,%0
2799 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2800 (set_attr "pa_combine_type" "addmove")
2801 (set_attr "length" "4,4,4,4,4,4,4,4")])
2804 [(set (match_operand:QI 0 "register_operand" "=r")
2805 (mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2806 (match_operand:SI 2 "register_operand" "r"))))]
2807 "! TARGET_DISABLE_INDEXING"
2808 "{ldbx|ldb} %2(%1),%0"
2809 [(set_attr "type" "load")
2810 (set_attr "length" "4")])
2813 [(set (match_operand:QI 0 "register_operand" "=r")
2814 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
2815 (match_operand:SI 2 "basereg_operand" "r"))))]
2816 "! TARGET_DISABLE_INDEXING"
2817 "{ldbx|ldb} %1(%2),%0"
2818 [(set_attr "type" "load")
2819 (set_attr "length" "4")])
2821 ; Indexed byte load with zero extension to SImode or HImode.
2823 [(set (match_operand:SI 0 "register_operand" "=r")
2824 (zero_extend:SI (mem:QI
2826 (match_operand:SI 1 "basereg_operand" "r")
2827 (match_operand:SI 2 "register_operand" "r")))))]
2828 "! TARGET_DISABLE_INDEXING"
2829 "{ldbx|ldb} %2(%1),%0"
2830 [(set_attr "type" "load")
2831 (set_attr "length" "4")])
2834 [(set (match_operand:SI 0 "register_operand" "=r")
2835 (zero_extend:SI (mem:QI
2837 (match_operand:SI 1 "register_operand" "r")
2838 (match_operand:SI 2 "basereg_operand" "r")))))]
2839 "! TARGET_DISABLE_INDEXING"
2840 "{ldbx|ldb} %1(%2),%0"
2841 [(set_attr "type" "load")
2842 (set_attr "length" "4")])
2845 [(set (match_operand:HI 0 "register_operand" "=r")
2846 (zero_extend:HI (mem:QI
2848 (match_operand:SI 1 "basereg_operand" "r")
2849 (match_operand:SI 2 "register_operand" "r")))))]
2850 "! TARGET_DISABLE_INDEXING"
2851 "{ldbx|ldb} %2(%1),%0"
2852 [(set_attr "type" "load")
2853 (set_attr "length" "4")])
2856 [(set (match_operand:HI 0 "register_operand" "=r")
2857 (zero_extend:HI (mem:QI
2859 (match_operand:SI 1 "register_operand" "r")
2860 (match_operand:SI 2 "basereg_operand" "r")))))]
2861 "! TARGET_DISABLE_INDEXING"
2862 "{ldbx|ldb} %1(%2),%0"
2863 [(set_attr "type" "load")
2864 (set_attr "length" "4")])
2867 [(set (match_operand:QI 0 "register_operand" "=r")
2868 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2869 (match_operand:SI 2 "int5_operand" "L"))))
2870 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2872 "{ldbs|ldb},mb %2(%1),%0"
2873 [(set_attr "type" "load")
2874 (set_attr "length" "4")])
2876 ; Now the same thing with zero extensions.
2878 [(set (match_operand:SI 0 "register_operand" "=r")
2879 (zero_extend:SI (mem:QI (plus:SI
2880 (match_operand:SI 1 "register_operand" "+r")
2881 (match_operand:SI 2 "int5_operand" "L")))))
2882 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2884 "{ldbs|ldb},mb %2(%1),%0"
2885 [(set_attr "type" "load")
2886 (set_attr "length" "4")])
2889 [(set (match_operand:HI 0 "register_operand" "=r")
2890 (zero_extend:HI (mem:QI (plus:SI
2891 (match_operand:SI 1 "register_operand" "+r")
2892 (match_operand:SI 2 "int5_operand" "L")))))
2893 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2895 "{ldbs|ldb},mb %2(%1),%0"
2896 [(set_attr "type" "load")
2897 (set_attr "length" "4")])
2900 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2901 (match_operand:SI 1 "int5_operand" "L")))
2902 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2904 (plus:SI (match_dup 0) (match_dup 1)))]
2906 "{stbs|stb},mb %r2,%1(%0)"
2907 [(set_attr "type" "store")
2908 (set_attr "length" "4")])
2910 ;; The definition of this insn does not really explain what it does,
2911 ;; but it should suffice
2912 ;; that anything generated as this insn will be recognized as one
2913 ;; and that it will not successfully combine with anything.
2914 (define_expand "movstrsi"
2915 [(parallel [(set (match_operand:BLK 0 "" "")
2916 (match_operand:BLK 1 "" ""))
2917 (clobber (match_dup 7))
2918 (clobber (match_dup 8))
2919 (clobber (match_dup 4))
2920 (clobber (match_dup 5))
2921 (clobber (match_dup 6))
2922 (use (match_operand:SI 2 "arith_operand" ""))
2923 (use (match_operand:SI 3 "const_int_operand" ""))])]
2929 /* HP provides very fast block move library routine for the PA;
2930 this routine includes:
2932 4x4 byte at a time block moves,
2933 1x4 byte at a time with alignment checked at runtime with
2934 attempts to align the source and destination as needed
2937 With that in mind, here's the heuristics to try and guess when
2938 the inlined block move will be better than the library block
2941 If the size isn't constant, then always use the library routines.
2943 If the size is large in respect to the known alignment, then use
2944 the library routines.
2946 If the size is small in repsect to the known alignment, then open
2947 code the copy (since that will lead to better scheduling).
2949 Else use the block move pattern. */
2951 /* Undetermined size, use the library routine. */
2952 if (GET_CODE (operands[2]) != CONST_INT)
2955 size = INTVAL (operands[2]);
2956 align = INTVAL (operands[3]);
2957 align = align > 4 ? 4 : align;
2959 /* If size/alignment > 8 (eg size is large in respect to alignment),
2960 then use the library routines. */
2961 if (size / align > 16)
2964 /* This does happen, but not often enough to worry much about. */
2965 if (size / align < MOVE_RATIO)
2968 /* Fall through means we're going to use our block move pattern. */
2970 = replace_equiv_address (operands[0],
2971 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
2973 = replace_equiv_address (operands[1],
2974 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
2975 operands[4] = gen_reg_rtx (SImode);
2976 operands[5] = gen_reg_rtx (SImode);
2977 operands[6] = gen_reg_rtx (SImode);
2978 operands[7] = XEXP (operands[0], 0);
2979 operands[8] = XEXP (operands[1], 0);
2982 ;; The operand constraints are written like this to support both compile-time
2983 ;; and run-time determined byte count. If the count is run-time determined,
2984 ;; the register with the byte count is clobbered by the copying code, and
2985 ;; therefore it is forced to operand 2. If the count is compile-time
2986 ;; determined, we need two scratch registers for the unrolled code.
2987 (define_insn "movstrsi_internal"
2988 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
2989 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
2990 (clobber (match_dup 0))
2991 (clobber (match_dup 1))
2992 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
2993 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp
2994 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
2995 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
2996 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
2998 "* return output_block_move (operands, !which_alternative);"
2999 [(set_attr "type" "multi,multi")])
3001 ;; Floating point move insns
3003 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3004 ;; to be reloaded by putting the constant into memory when
3005 ;; reg is a floating point register.
3007 ;; For integer registers we use ldil;ldo to set the appropriate
3010 ;; This must come before the movdf pattern, and it must be present
3011 ;; to handle obscure reloading cases.
3013 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3014 (match_operand:DF 1 "" "?F,m"))]
3015 "GET_CODE (operands[1]) == CONST_DOUBLE
3016 && operands[1] != CONST0_RTX (DFmode)
3018 && ! TARGET_SOFT_FLOAT"
3019 "* return (which_alternative == 0 ? output_move_double (operands)
3020 : \"fldd%F1 %1,%0\");"
3021 [(set_attr "type" "move,fpload")
3022 (set_attr "length" "16,4")])
3024 (define_expand "movdf"
3025 [(set (match_operand:DF 0 "general_operand" "")
3026 (match_operand:DF 1 "general_operand" ""))]
3030 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3031 operands[1] = force_const_mem (DFmode, operands[1]);
3033 if (emit_move_sequence (operands, DFmode, 0))
3037 ;; Reloading an SImode or DImode value requires a scratch register if
3038 ;; going in to or out of float point registers.
3040 (define_expand "reload_indf"
3041 [(set (match_operand:DF 0 "register_operand" "=Z")
3042 (match_operand:DF 1 "non_hard_reg_operand" ""))
3043 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3047 if (emit_move_sequence (operands, DFmode, operands[2]))
3050 /* We don't want the clobber emitted, so handle this ourselves. */
3051 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3055 (define_expand "reload_outdf"
3056 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3057 (match_operand:DF 1 "register_operand" "Z"))
3058 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3062 if (emit_move_sequence (operands, DFmode, operands[2]))
3065 /* We don't want the clobber emitted, so handle this ourselves. */
3066 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3071 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3072 "=f,*r,RQ,?o,?Q,f,*r,*r")
3073 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3074 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3075 "(register_operand (operands[0], DFmode)
3076 || reg_or_0_operand (operands[1], DFmode))
3077 && ! (GET_CODE (operands[1]) == CONST_DOUBLE
3078 && GET_CODE (operands[0]) == MEM)
3080 && ! TARGET_SOFT_FLOAT"
3083 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3084 || operands[1] == CONST0_RTX (DFmode))
3085 return output_fp_move_double (operands);
3086 return output_move_double (operands);
3088 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3089 (set_attr "length" "4,8,4,8,16,4,8,16")])
3092 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3094 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3096 "(register_operand (operands[0], DFmode)
3097 || reg_or_0_operand (operands[1], DFmode))
3099 && TARGET_SOFT_FLOAT"
3102 return output_move_double (operands);
3104 [(set_attr "type" "move,store,store,load,load")
3105 (set_attr "length" "8,8,16,8,16")])
3108 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3109 "=r,r,r,r,r,Q,*q,!f,f,*TR")
3110 (match_operand:DF 1 "move_operand"
3111 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3112 "(register_operand (operands[0], DFmode)
3113 || reg_or_0_operand (operands[1], DFmode))
3114 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3126 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3127 (set_attr "pa_combine_type" "addmove")
3128 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3131 [(set (match_operand:DF 0 "register_operand" "=fx")
3132 (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3133 (match_operand:SI 2 "register_operand" "r"))))]
3134 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3135 "{flddx|fldd} %2(%1),%0"
3136 [(set_attr "type" "fpload")
3137 (set_attr "length" "4")])
3140 [(set (match_operand:DF 0 "register_operand" "=fx")
3141 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3142 (match_operand:SI 2 "basereg_operand" "r"))))]
3143 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3144 "{flddx|fldd} %1(%2),%0"
3145 [(set_attr "type" "fpload")
3146 (set_attr "length" "4")])
3149 [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3150 (match_operand:SI 2 "register_operand" "r")))
3151 (match_operand:DF 0 "register_operand" "fx"))]
3152 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3153 "{fstdx|fstd} %0,%2(%1)"
3154 [(set_attr "type" "fpstore")
3155 (set_attr "length" "4")])
3158 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3159 (match_operand:SI 2 "basereg_operand" "r")))
3160 (match_operand:DF 0 "register_operand" "fx"))]
3161 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3162 "{fstdx|fstd} %0,%1(%2)"
3163 [(set_attr "type" "fpstore")
3164 (set_attr "length" "4")])
3166 (define_expand "movdi"
3167 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
3168 (match_operand:DI 1 "general_operand" ""))]
3172 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3173 operands[1] = force_const_mem (DImode, operands[1]);
3175 if (emit_move_sequence (operands, DImode, 0))
3179 (define_expand "reload_indi"
3180 [(set (match_operand:DI 0 "register_operand" "=Z")
3181 (match_operand:DI 1 "non_hard_reg_operand" ""))
3182 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3186 if (emit_move_sequence (operands, DImode, operands[2]))
3189 /* We don't want the clobber emitted, so handle this ourselves. */
3190 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3194 (define_expand "reload_outdi"
3195 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
3196 (match_operand:DI 1 "register_operand" "Z"))
3197 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3201 if (emit_move_sequence (operands, DImode, operands[2]))
3204 /* We don't want the clobber emitted, so handle this ourselves. */
3205 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3210 [(set (match_operand:DI 0 "register_operand" "=r")
3211 (high:DI (match_operand 1 "" "")))]
3215 rtx op0 = operands[0];
3216 rtx op1 = operands[1];
3218 if (GET_CODE (op1) == CONST_INT)
3220 operands[0] = operand_subword (op0, 1, 0, DImode);
3221 output_asm_insn (\"ldil L'%1,%0\", operands);
3223 operands[0] = operand_subword (op0, 0, 0, DImode);
3224 if (INTVAL (op1) < 0)
3225 output_asm_insn (\"ldi -1,%0\", operands);
3227 output_asm_insn (\"ldi 0,%0\", operands);
3230 else if (GET_CODE (op1) == CONST_DOUBLE)
3232 operands[0] = operand_subword (op0, 1, 0, DImode);
3233 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3234 output_asm_insn (\"ldil L'%1,%0\", operands);
3236 operands[0] = operand_subword (op0, 0, 0, DImode);
3237 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3238 output_asm_insn (singlemove_string (operands), operands);
3244 [(set_attr "type" "move")
3245 (set_attr "length" "8")])
3248 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3249 "=r,o,Q,r,r,r,f,f,*TR")
3250 (match_operand:DI 1 "general_operand"
3251 "rM,r,r,o*R,Q,i,fM,*TR,f"))]
3252 "(register_operand (operands[0], DImode)
3253 || reg_or_0_operand (operands[1], DImode))
3255 && ! TARGET_SOFT_FLOAT"
3258 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3259 || (operands[1] == CONST0_RTX (DImode)))
3260 return output_fp_move_double (operands);
3261 return output_move_double (operands);
3263 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
3264 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
3267 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3268 "=r,r,r,r,r,r,Q,*q,!f,f,*TR")
3269 (match_operand:DI 1 "move_operand"
3270 "A,r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3271 "(register_operand (operands[0], DImode)
3272 || reg_or_0_operand (operands[1], DImode))
3273 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3286 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3287 (set_attr "pa_combine_type" "addmove")
3288 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
3291 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3293 (match_operand:DI 1 "general_operand"
3295 "(register_operand (operands[0], DImode)
3296 || reg_or_0_operand (operands[1], DImode))
3298 && TARGET_SOFT_FLOAT"
3301 return output_move_double (operands);
3303 [(set_attr "type" "move,store,store,load,load,multi")
3304 (set_attr "length" "8,8,16,8,16,16")])
3307 [(set (match_operand:DI 0 "register_operand" "=r,&r")
3308 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
3309 (match_operand:DI 2 "immediate_operand" "i,i")))]
3313 /* Don't output a 64 bit constant, since we can't trust the assembler to
3314 handle it correctly. */
3315 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3316 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3317 if (which_alternative == 1)
3318 output_asm_insn (\"copy %1,%0\", operands);
3319 return \"ldo R'%G2(%R1),%R0\";
3321 [(set_attr "type" "move,move")
3322 (set_attr "length" "4,8")])
3324 ;; This pattern forces (set (reg:SF ...) (const_double ...))
3325 ;; to be reloaded by putting the constant into memory when
3326 ;; reg is a floating point register.
3328 ;; For integer registers we use ldil;ldo to set the appropriate
3331 ;; This must come before the movsf pattern, and it must be present
3332 ;; to handle obscure reloading cases.
3334 [(set (match_operand:SF 0 "register_operand" "=?r,f")
3335 (match_operand:SF 1 "" "?F,m"))]
3336 "GET_CODE (operands[1]) == CONST_DOUBLE
3337 && operands[1] != CONST0_RTX (SFmode)
3338 && ! TARGET_SOFT_FLOAT"
3339 "* return (which_alternative == 0 ? singlemove_string (operands)
3340 : \" fldw%F1 %1,%0\");"
3341 [(set_attr "type" "move,fpload")
3342 (set_attr "length" "8,4")])
3344 (define_expand "movsf"
3345 [(set (match_operand:SF 0 "general_operand" "")
3346 (match_operand:SF 1 "general_operand" ""))]
3350 if (emit_move_sequence (operands, SFmode, 0))
3354 ;; Reloading an SImode or DImode value requires a scratch register if
3355 ;; going in to or out of float point registers.
3357 (define_expand "reload_insf"
3358 [(set (match_operand:SF 0 "register_operand" "=Z")
3359 (match_operand:SF 1 "non_hard_reg_operand" ""))
3360 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3364 if (emit_move_sequence (operands, SFmode, operands[2]))
3367 /* We don't want the clobber emitted, so handle this ourselves. */
3368 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3372 (define_expand "reload_outsf"
3373 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
3374 (match_operand:SF 1 "register_operand" "Z"))
3375 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3379 if (emit_move_sequence (operands, SFmode, operands[2]))
3382 /* We don't want the clobber emitted, so handle this ourselves. */
3383 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3388 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3390 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3391 "fG,rG,RQ,RQ,f,rG"))]
3392 "(register_operand (operands[0], SFmode)
3393 || reg_or_0_operand (operands[1], SFmode))
3394 && ! TARGET_SOFT_FLOAT"
3402 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
3403 (set_attr "pa_combine_type" "addmove")
3404 (set_attr "length" "4,4,4,4,4,4")])
3407 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3409 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3411 "(register_operand (operands[0], SFmode)
3412 || reg_or_0_operand (operands[1], SFmode))
3413 && TARGET_SOFT_FLOAT"
3418 [(set_attr "type" "move,load,store")
3419 (set_attr "pa_combine_type" "addmove")
3420 (set_attr "length" "4,4,4")])
3423 [(set (match_operand:SF 0 "register_operand" "=fx")
3424 (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3425 (match_operand:SI 2 "register_operand" "r"))))]
3426 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3427 "{fldwx|fldw} %2(%1),%0"
3428 [(set_attr "type" "fpload")
3429 (set_attr "length" "4")])
3432 [(set (match_operand:SF 0 "register_operand" "=fx")
3433 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3434 (match_operand:SI 2 "basereg_operand" "r"))))]
3435 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3436 "{fldwx|fldw} %1(%2),%0"
3437 [(set_attr "type" "fpload")
3438 (set_attr "length" "4")])
3441 [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3442 (match_operand:SI 2 "register_operand" "r")))
3443 (match_operand:SF 0 "register_operand" "fx"))]
3444 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3445 "{fstwx|fstw} %0,%2(%1)"
3446 [(set_attr "type" "fpstore")
3447 (set_attr "length" "4")])
3450 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3451 (match_operand:SI 2 "basereg_operand" "r")))
3452 (match_operand:SF 0 "register_operand" "fx"))]
3453 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3454 "{fstwx|fstw} %0,%1(%2)"
3455 [(set_attr "type" "fpstore")
3456 (set_attr "length" "4")])
3459 ;;- zero extension instructions
3460 ;; We have define_expand for zero extension patterns to make sure the
3461 ;; operands get loaded into registers. The define_insns accept
3462 ;; memory operands. This gives us better overall code than just
3463 ;; having a pattern that does or does not accept memory operands.
3465 (define_expand "zero_extendhisi2"
3466 [(set (match_operand:SI 0 "register_operand" "")
3468 (match_operand:HI 1 "register_operand" "")))]
3473 [(set (match_operand:SI 0 "register_operand" "=r,r")
3475 (match_operand:HI 1 "move_operand" "r,RQ")))]
3476 "GET_CODE (operands[1]) != CONST_INT"
3478 {extru|extrw,u} %1,31,16,%0
3480 [(set_attr "type" "shift,load")
3481 (set_attr "length" "4,4")])
3483 (define_expand "zero_extendqihi2"
3484 [(set (match_operand:HI 0 "register_operand" "")
3486 (match_operand:QI 1 "register_operand" "")))]
3491 [(set (match_operand:HI 0 "register_operand" "=r,r")
3493 (match_operand:QI 1 "move_operand" "r,RQ")))]
3494 "GET_CODE (operands[1]) != CONST_INT"
3496 {extru|extrw,u} %1,31,8,%0
3498 [(set_attr "type" "shift,load")
3499 (set_attr "length" "4,4")])
3501 (define_expand "zero_extendqisi2"
3502 [(set (match_operand:SI 0 "register_operand" "")
3504 (match_operand:QI 1 "register_operand" "")))]
3509 [(set (match_operand:SI 0 "register_operand" "=r,r")
3511 (match_operand:QI 1 "move_operand" "r,RQ")))]
3512 "GET_CODE (operands[1]) != CONST_INT"
3514 {extru|extrw,u} %1,31,8,%0
3516 [(set_attr "type" "shift,load")
3517 (set_attr "length" "4,4")])
3519 (define_insn "zero_extendqidi2"
3520 [(set (match_operand:DI 0 "register_operand" "=r")
3521 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3523 "extrd,u %1,63,8,%0"
3524 [(set_attr "type" "shift")
3525 (set_attr "length" "4")])
3527 (define_insn "zero_extendhidi2"
3528 [(set (match_operand:DI 0 "register_operand" "=r")
3529 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3531 "extrd,u %1,63,16,%0"
3532 [(set_attr "type" "shift")
3533 (set_attr "length" "4")])
3535 (define_insn "zero_extendsidi2"
3536 [(set (match_operand:DI 0 "register_operand" "=r")
3537 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3539 "extrd,u %1,63,32,%0"
3540 [(set_attr "type" "shift")
3541 (set_attr "length" "4")])
3543 ;;- sign extension instructions
3545 (define_insn "extendhisi2"
3546 [(set (match_operand:SI 0 "register_operand" "=r")
3547 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
3549 "{extrs|extrw,s} %1,31,16,%0"
3550 [(set_attr "type" "shift")
3551 (set_attr "length" "4")])
3553 (define_insn "extendqihi2"
3554 [(set (match_operand:HI 0 "register_operand" "=r")
3555 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
3557 "{extrs|extrw,s} %1,31,8,%0"
3558 [(set_attr "type" "shift")
3559 (set_attr "length" "4")])
3561 (define_insn "extendqisi2"
3562 [(set (match_operand:SI 0 "register_operand" "=r")
3563 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
3565 "{extrs|extrw,s} %1,31,8,%0"
3566 [(set_attr "type" "shift")
3567 (set_attr "length" "4")])
3569 (define_insn "extendqidi2"
3570 [(set (match_operand:DI 0 "register_operand" "=r")
3571 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3573 "extrd,s %1,63,8,%0"
3574 [(set_attr "type" "shift")
3575 (set_attr "length" "4")])
3577 (define_insn "extendhidi2"
3578 [(set (match_operand:DI 0 "register_operand" "=r")
3579 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3581 "extrd,s %1,63,16,%0"
3582 [(set_attr "type" "shift")
3583 (set_attr "length" "4")])
3585 (define_insn "extendsidi2"
3586 [(set (match_operand:DI 0 "register_operand" "=r")
3587 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3589 "extrd,s %1,63,32,%0"
3590 [(set_attr "type" "shift")
3591 (set_attr "length" "4")])
3594 ;; Conversions between float and double.
3596 (define_insn "extendsfdf2"
3597 [(set (match_operand:DF 0 "register_operand" "=f")
3599 (match_operand:SF 1 "register_operand" "f")))]
3600 "! TARGET_SOFT_FLOAT"
3601 "{fcnvff|fcnv},sgl,dbl %1,%0"
3602 [(set_attr "type" "fpalu")
3603 (set_attr "length" "4")])
3605 (define_insn "truncdfsf2"
3606 [(set (match_operand:SF 0 "register_operand" "=f")
3608 (match_operand:DF 1 "register_operand" "f")))]
3609 "! TARGET_SOFT_FLOAT"
3610 "{fcnvff|fcnv},dbl,sgl %1,%0"
3611 [(set_attr "type" "fpalu")
3612 (set_attr "length" "4")])
3614 ;; Conversion between fixed point and floating point.
3615 ;; Note that among the fix-to-float insns
3616 ;; the ones that start with SImode come first.
3617 ;; That is so that an operand that is a CONST_INT
3618 ;; (and therefore lacks a specific machine mode).
3619 ;; will be recognized as SImode (which is always valid)
3620 ;; rather than as QImode or HImode.
3622 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
3623 ;; to be reloaded by putting the constant into memory.
3624 ;; It must come before the more general floatsisf2 pattern.
3626 [(set (match_operand:SF 0 "register_operand" "=f")
3627 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
3628 "! TARGET_SOFT_FLOAT"
3629 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
3630 [(set_attr "type" "fpalu")
3631 (set_attr "length" "8")])
3633 (define_insn "floatsisf2"
3634 [(set (match_operand:SF 0 "register_operand" "=f")
3635 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3636 "! TARGET_SOFT_FLOAT"
3637 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
3638 [(set_attr "type" "fpalu")
3639 (set_attr "length" "4")])
3641 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
3642 ;; to be reloaded by putting the constant into memory.
3643 ;; It must come before the more general floatsidf2 pattern.
3645 [(set (match_operand:DF 0 "register_operand" "=f")
3646 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
3647 "! TARGET_SOFT_FLOAT"
3648 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
3649 [(set_attr "type" "fpalu")
3650 (set_attr "length" "8")])
3652 (define_insn "floatsidf2"
3653 [(set (match_operand:DF 0 "register_operand" "=f")
3654 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3655 "! TARGET_SOFT_FLOAT"
3656 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
3657 [(set_attr "type" "fpalu")
3658 (set_attr "length" "4")])
3660 (define_expand "floatunssisf2"
3661 [(set (subreg:SI (match_dup 2) 4)
3662 (match_operand:SI 1 "register_operand" ""))
3663 (set (subreg:SI (match_dup 2) 0)
3665 (set (match_operand:SF 0 "register_operand" "")
3666 (float:SF (match_dup 2)))]
3667 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3672 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
3675 operands[2] = gen_reg_rtx (DImode);
3678 (define_expand "floatunssidf2"
3679 [(set (subreg:SI (match_dup 2) 4)
3680 (match_operand:SI 1 "register_operand" ""))
3681 (set (subreg:SI (match_dup 2) 0)
3683 (set (match_operand:DF 0 "register_operand" "")
3684 (float:DF (match_dup 2)))]
3685 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3690 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
3693 operands[2] = gen_reg_rtx (DImode);
3696 (define_insn "floatdisf2"
3697 [(set (match_operand:SF 0 "register_operand" "=f")
3698 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3699 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3700 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
3701 [(set_attr "type" "fpalu")
3702 (set_attr "length" "4")])
3704 (define_insn "floatdidf2"
3705 [(set (match_operand:DF 0 "register_operand" "=f")
3706 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3707 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3708 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
3709 [(set_attr "type" "fpalu")
3710 (set_attr "length" "4")])
3712 ;; Convert a float to an actual integer.
3713 ;; Truncation is performed as part of the conversion.
3715 (define_insn "fix_truncsfsi2"
3716 [(set (match_operand:SI 0 "register_operand" "=f")
3717 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3718 "! TARGET_SOFT_FLOAT"
3719 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
3720 [(set_attr "type" "fpalu")
3721 (set_attr "length" "4")])
3723 (define_insn "fix_truncdfsi2"
3724 [(set (match_operand:SI 0 "register_operand" "=f")
3725 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3726 "! TARGET_SOFT_FLOAT"
3727 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
3728 [(set_attr "type" "fpalu")
3729 (set_attr "length" "4")])
3731 (define_insn "fix_truncsfdi2"
3732 [(set (match_operand:DI 0 "register_operand" "=f")
3733 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3734 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3735 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
3736 [(set_attr "type" "fpalu")
3737 (set_attr "length" "4")])
3739 (define_insn "fix_truncdfdi2"
3740 [(set (match_operand:DI 0 "register_operand" "=f")
3741 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3742 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3743 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
3744 [(set_attr "type" "fpalu")
3745 (set_attr "length" "4")])
3747 (define_insn "floatunssidf2_pa20"
3748 [(set (match_operand:DF 0 "register_operand" "=f")
3749 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
3750 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3752 [(set_attr "type" "fpalu")
3753 (set_attr "length" "4")])
3755 (define_insn "floatunssisf2_pa20"
3756 [(set (match_operand:SF 0 "register_operand" "=f")
3757 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
3758 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3760 [(set_attr "type" "fpalu")
3761 (set_attr "length" "4")])
3763 (define_insn "floatunsdisf2"
3764 [(set (match_operand:SF 0 "register_operand" "=f")
3765 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
3766 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3767 "fcnv,udw,sgl %1,%0"
3768 [(set_attr "type" "fpalu")
3769 (set_attr "length" "4")])
3771 (define_insn "floatunsdidf2"
3772 [(set (match_operand:DF 0 "register_operand" "=f")
3773 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
3774 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3775 "fcnv,udw,dbl %1,%0"
3776 [(set_attr "type" "fpalu")
3777 (set_attr "length" "4")])
3779 (define_insn "fixuns_truncsfsi2"
3780 [(set (match_operand:SI 0 "register_operand" "=f")
3781 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3782 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3783 "fcnv,t,sgl,uw %1,%0"
3784 [(set_attr "type" "fpalu")
3785 (set_attr "length" "4")])
3787 (define_insn "fixuns_truncdfsi2"
3788 [(set (match_operand:SI 0 "register_operand" "=f")
3789 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3790 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3791 "fcnv,t,dbl,uw %1,%0"
3792 [(set_attr "type" "fpalu")
3793 (set_attr "length" "4")])
3795 (define_insn "fixuns_truncsfdi2"
3796 [(set (match_operand:DI 0 "register_operand" "=f")
3797 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3798 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3799 "fcnv,t,sgl,udw %1,%0"
3800 [(set_attr "type" "fpalu")
3801 (set_attr "length" "4")])
3803 (define_insn "fixuns_truncdfdi2"
3804 [(set (match_operand:DI 0 "register_operand" "=f")
3805 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3806 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3807 "fcnv,t,dbl,udw %1,%0"
3808 [(set_attr "type" "fpalu")
3809 (set_attr "length" "4")])
3811 ;;- arithmetic instructions
3813 (define_expand "adddi3"
3814 [(set (match_operand:DI 0 "register_operand" "")
3815 (plus:DI (match_operand:DI 1 "register_operand" "")
3816 (match_operand:DI 2 "adddi3_operand" "")))]
3821 [(set (match_operand:DI 0 "register_operand" "=r")
3822 (plus:DI (match_operand:DI 1 "register_operand" "%r")
3823 (match_operand:DI 2 "arith11_operand" "rI")))]
3827 if (GET_CODE (operands[2]) == CONST_INT)
3829 if (INTVAL (operands[2]) >= 0)
3830 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
3832 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
3835 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
3837 [(set_attr "type" "binary")
3838 (set_attr "length" "8")])
3841 [(set (match_operand:DI 0 "register_operand" "=r,r")
3842 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
3843 (match_operand:DI 2 "arith_operand" "r,J")))]
3846 {addl|add,l} %1,%2,%0
3848 [(set_attr "type" "binary,binary")
3849 (set_attr "pa_combine_type" "addmove")
3850 (set_attr "length" "4,4")])
3853 [(set (match_operand:DI 0 "register_operand" "=r")
3854 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
3855 (match_operand:DI 2 "register_operand" "r")))]
3858 [(set_attr "type" "binary")
3859 (set_attr "length" "4")])
3862 [(set (match_operand:SI 0 "register_operand" "=r")
3863 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3864 (match_operand:SI 2 "register_operand" "r")))]
3867 [(set_attr "type" "binary")
3868 (set_attr "length" "4")])
3870 ;; define_splits to optimize cases of adding a constant integer
3871 ;; to a register when the constant does not fit in 14 bits. */
3873 [(set (match_operand:SI 0 "register_operand" "")
3874 (plus:SI (match_operand:SI 1 "register_operand" "")
3875 (match_operand:SI 2 "const_int_operand" "")))
3876 (clobber (match_operand:SI 4 "register_operand" ""))]
3877 "! cint_ok_for_move (INTVAL (operands[2]))
3878 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
3879 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
3880 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
3883 int val = INTVAL (operands[2]);
3884 int low = (val < 0) ? -0x2000 : 0x1fff;
3885 int rest = val - low;
3887 operands[2] = GEN_INT (rest);
3888 operands[3] = GEN_INT (low);
3892 [(set (match_operand:SI 0 "register_operand" "")
3893 (plus:SI (match_operand:SI 1 "register_operand" "")
3894 (match_operand:SI 2 "const_int_operand" "")))
3895 (clobber (match_operand:SI 4 "register_operand" ""))]
3896 "! cint_ok_for_move (INTVAL (operands[2]))"
3897 [(set (match_dup 4) (match_dup 2))
3898 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
3902 HOST_WIDE_INT intval = INTVAL (operands[2]);
3904 /* Try dividing the constant by 2, then 4, and finally 8 to see
3905 if we can get a constant which can be loaded into a register
3906 in a single instruction (cint_ok_for_move).
3908 If that fails, try to negate the constant and subtract it
3909 from our input operand. */
3910 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
3912 operands[2] = GEN_INT (intval / 2);
3913 operands[3] = GEN_INT (2);
3915 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
3917 operands[2] = GEN_INT (intval / 4);
3918 operands[3] = GEN_INT (4);
3920 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
3922 operands[2] = GEN_INT (intval / 8);
3923 operands[3] = GEN_INT (8);
3925 else if (cint_ok_for_move (-intval))
3927 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
3928 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
3935 (define_insn "addsi3"
3936 [(set (match_operand:SI 0 "register_operand" "=r,r")
3937 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3938 (match_operand:SI 2 "arith_operand" "r,J")))]
3941 {addl|add,l} %1,%2,%0
3943 [(set_attr "type" "binary,binary")
3944 (set_attr "pa_combine_type" "addmove")
3945 (set_attr "length" "4,4")])
3947 (define_expand "subdi3"
3948 [(set (match_operand:DI 0 "register_operand" "")
3949 (minus:DI (match_operand:DI 1 "register_operand" "")
3950 (match_operand:DI 2 "register_operand" "")))]
3955 [(set (match_operand:DI 0 "register_operand" "=r")
3956 (minus:DI (match_operand:DI 1 "register_operand" "r")
3957 (match_operand:DI 2 "register_operand" "r")))]
3959 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
3960 [(set_attr "type" "binary")
3961 (set_attr "length" "8")])
3964 [(set (match_operand:DI 0 "register_operand" "=r,r,q")
3965 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,U")
3966 (match_operand:DI 2 "register_operand" "r,r,r")))]
3972 [(set_attr "type" "binary,binary,move")
3973 (set_attr "length" "4,4,4")])
3975 (define_expand "subsi3"
3976 [(set (match_operand:SI 0 "register_operand" "")
3977 (minus:SI (match_operand:SI 1 "arith11_operand" "")
3978 (match_operand:SI 2 "register_operand" "")))]
3983 [(set (match_operand:SI 0 "register_operand" "=r,r")
3984 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
3985 (match_operand:SI 2 "register_operand" "r,r")))]
3990 [(set_attr "type" "binary,binary")
3991 (set_attr "length" "4,4")])
3994 [(set (match_operand:SI 0 "register_operand" "=r,r,q")
3995 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,S")
3996 (match_operand:SI 2 "register_operand" "r,r,r")))]
4002 [(set_attr "type" "binary,binary,move")
4003 (set_attr "length" "4,4,4")])
4005 ;; Clobbering a "register_operand" instead of a match_scratch
4006 ;; in operand3 of millicode calls avoids spilling %r1 and
4007 ;; produces better code.
4009 ;; The mulsi3 insns set up registers for the millicode call.
4010 (define_expand "mulsi3"
4011 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4012 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4013 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4014 (clobber (match_dup 3))
4015 (clobber (reg:SI 26))
4016 (clobber (reg:SI 25))
4017 (clobber (match_dup 4))])
4018 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4022 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4023 if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
4025 rtx scratch = gen_reg_rtx (DImode);
4026 operands[1] = force_reg (SImode, operands[1]);
4027 operands[2] = force_reg (SImode, operands[2]);
4028 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
4029 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4030 gen_rtx_SUBREG (SImode, scratch, GET_MODE_SIZE (SImode))));
4033 operands[3] = gen_reg_rtx (SImode);
4036 (define_insn "umulsidi3"
4037 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4038 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4039 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
4040 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4042 [(set_attr "type" "fpmuldbl")
4043 (set_attr "length" "4")])
4046 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4047 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4048 (match_operand:DI 2 "uint32_operand" "f")))]
4049 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
4051 [(set_attr "type" "fpmuldbl")
4052 (set_attr "length" "4")])
4055 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4056 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4057 (match_operand:DI 2 "uint32_operand" "f")))]
4058 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
4060 [(set_attr "type" "fpmuldbl")
4061 (set_attr "length" "4")])
4064 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4065 (clobber (match_operand:SI 0 "register_operand" "=a"))
4066 (clobber (reg:SI 26))
4067 (clobber (reg:SI 25))
4068 (clobber (reg:SI 31))]
4070 "* return output_mul_insn (0, insn);"
4071 [(set_attr "type" "milli")
4072 (set (attr "length")
4074 ;; Target (or stub) within reach
4075 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4077 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4082 (ne (symbol_ref "flag_pic")
4086 ;; Out of reach PORTABLE_RUNTIME
4087 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4091 ;; Out of reach, can use ble
4095 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4096 (clobber (match_operand:SI 0 "register_operand" "=a"))
4097 (clobber (reg:SI 26))
4098 (clobber (reg:SI 25))
4099 (clobber (reg:SI 2))]
4101 "* return output_mul_insn (0, insn);"
4102 [(set_attr "type" "milli")
4103 (set (attr "length") (const_int 4))])
4105 (define_expand "muldi3"
4106 [(set (match_operand:DI 0 "register_operand" "")
4107 (mult:DI (match_operand:DI 1 "register_operand" "")
4108 (match_operand:DI 2 "register_operand" "")))]
4109 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4112 rtx low_product = gen_reg_rtx (DImode);
4113 rtx cross_product1 = gen_reg_rtx (DImode);
4114 rtx cross_product2 = gen_reg_rtx (DImode);
4115 rtx cross_scratch = gen_reg_rtx (DImode);
4116 rtx cross_product = gen_reg_rtx (DImode);
4117 rtx op1l, op1r, op2l, op2r;
4118 rtx op1shifted, op2shifted;
4120 op1shifted = gen_reg_rtx (DImode);
4121 op2shifted = gen_reg_rtx (DImode);
4122 op1l = gen_reg_rtx (SImode);
4123 op1r = gen_reg_rtx (SImode);
4124 op2l = gen_reg_rtx (SImode);
4125 op2r = gen_reg_rtx (SImode);
4127 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
4129 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
4131 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
4132 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
4133 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
4134 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
4136 /* Emit multiplies for the cross products. */
4137 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
4138 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
4140 /* Emit a multiply for the low sub-word. */
4141 emit_insn (gen_umulsidi3 (low_product, op2r, op1r));
4143 /* Sum the cross products and shift them into proper position. */
4144 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
4145 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
4147 /* Add the cross product to the low product and store the result
4148 into the output operand . */
4149 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
4153 ;;; Division and mod.
4154 (define_expand "divsi3"
4155 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4156 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4157 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
4158 (clobber (match_dup 3))
4159 (clobber (match_dup 4))
4160 (clobber (reg:SI 26))
4161 (clobber (reg:SI 25))
4162 (clobber (match_dup 5))])
4163 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4167 operands[3] = gen_reg_rtx (SImode);
4170 operands[5] = gen_rtx_REG (SImode, 2);
4171 operands[4] = operands[5];
4175 operands[5] = gen_rtx_REG (SImode, 31);
4176 operands[4] = gen_reg_rtx (SImode);
4178 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
4184 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4185 (clobber (match_operand:SI 1 "register_operand" "=a"))
4186 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4187 (clobber (reg:SI 26))
4188 (clobber (reg:SI 25))
4189 (clobber (reg:SI 31))]
4192 return output_div_insn (operands, 0, insn);"
4193 [(set_attr "type" "milli")
4194 (set (attr "length")
4196 ;; Target (or stub) within reach
4197 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4199 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4204 (ne (symbol_ref "flag_pic")
4208 ;; Out of reach PORTABLE_RUNTIME
4209 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4213 ;; Out of reach, can use ble
4218 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4219 (clobber (match_operand:SI 1 "register_operand" "=a"))
4220 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4221 (clobber (reg:SI 26))
4222 (clobber (reg:SI 25))
4223 (clobber (reg:SI 2))]
4226 return output_div_insn (operands, 0, insn);"
4227 [(set_attr "type" "milli")
4228 (set (attr "length") (const_int 4))])
4230 (define_expand "udivsi3"
4231 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4232 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4233 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
4234 (clobber (match_dup 3))
4235 (clobber (match_dup 4))
4236 (clobber (reg:SI 26))
4237 (clobber (reg:SI 25))
4238 (clobber (match_dup 5))])
4239 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4243 operands[3] = gen_reg_rtx (SImode);
4246 operands[5] = gen_rtx_REG (SImode, 2);
4247 operands[4] = operands[5];
4251 operands[5] = gen_rtx_REG (SImode, 31);
4252 operands[4] = gen_reg_rtx (SImode);
4254 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
4260 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4261 (clobber (match_operand:SI 1 "register_operand" "=a"))
4262 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4263 (clobber (reg:SI 26))
4264 (clobber (reg:SI 25))
4265 (clobber (reg:SI 31))]
4268 return output_div_insn (operands, 1, insn);"
4269 [(set_attr "type" "milli")
4270 (set (attr "length")
4272 ;; Target (or stub) within reach
4273 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4275 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4280 (ne (symbol_ref "flag_pic")
4284 ;; Out of reach PORTABLE_RUNTIME
4285 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4289 ;; Out of reach, can use ble
4294 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4295 (clobber (match_operand:SI 1 "register_operand" "=a"))
4296 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4297 (clobber (reg:SI 26))
4298 (clobber (reg:SI 25))
4299 (clobber (reg:SI 2))]
4302 return output_div_insn (operands, 1, insn);"
4303 [(set_attr "type" "milli")
4304 (set (attr "length") (const_int 4))])
4306 (define_expand "modsi3"
4307 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4308 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4309 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4310 (clobber (match_dup 3))
4311 (clobber (match_dup 4))
4312 (clobber (reg:SI 26))
4313 (clobber (reg:SI 25))
4314 (clobber (match_dup 5))])
4315 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4321 operands[5] = gen_rtx_REG (SImode, 2);
4322 operands[4] = operands[5];
4326 operands[5] = gen_rtx_REG (SImode, 31);
4327 operands[4] = gen_reg_rtx (SImode);
4329 operands[3] = gen_reg_rtx (SImode);
4333 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4334 (clobber (match_operand:SI 0 "register_operand" "=a"))
4335 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4336 (clobber (reg:SI 26))
4337 (clobber (reg:SI 25))
4338 (clobber (reg:SI 31))]
4341 return output_mod_insn (0, insn);"
4342 [(set_attr "type" "milli")
4343 (set (attr "length")
4345 ;; Target (or stub) within reach
4346 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4348 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4353 (ne (symbol_ref "flag_pic")
4357 ;; Out of reach PORTABLE_RUNTIME
4358 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4362 ;; Out of reach, can use ble
4366 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4367 (clobber (match_operand:SI 0 "register_operand" "=a"))
4368 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4369 (clobber (reg:SI 26))
4370 (clobber (reg:SI 25))
4371 (clobber (reg:SI 2))]
4374 return output_mod_insn (0, insn);"
4375 [(set_attr "type" "milli")
4376 (set (attr "length") (const_int 4))])
4378 (define_expand "umodsi3"
4379 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4380 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4381 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4382 (clobber (match_dup 3))
4383 (clobber (match_dup 4))
4384 (clobber (reg:SI 26))
4385 (clobber (reg:SI 25))
4386 (clobber (match_dup 5))])
4387 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4393 operands[5] = gen_rtx_REG (SImode, 2);
4394 operands[4] = operands[5];
4398 operands[5] = gen_rtx_REG (SImode, 31);
4399 operands[4] = gen_reg_rtx (SImode);
4401 operands[3] = gen_reg_rtx (SImode);
4405 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4406 (clobber (match_operand:SI 0 "register_operand" "=a"))
4407 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4408 (clobber (reg:SI 26))
4409 (clobber (reg:SI 25))
4410 (clobber (reg:SI 31))]
4413 return output_mod_insn (1, insn);"
4414 [(set_attr "type" "milli")
4415 (set (attr "length")
4417 ;; Target (or stub) within reach
4418 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4420 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4425 (ne (symbol_ref "flag_pic")
4429 ;; Out of reach PORTABLE_RUNTIME
4430 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4434 ;; Out of reach, can use ble
4438 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4439 (clobber (match_operand:SI 0 "register_operand" "=a"))
4440 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4441 (clobber (reg:SI 26))
4442 (clobber (reg:SI 25))
4443 (clobber (reg:SI 2))]
4446 return output_mod_insn (1, insn);"
4447 [(set_attr "type" "milli")
4448 (set (attr "length") (const_int 4))])
4450 ;;- and instructions
4451 ;; We define DImode `and` so with DImode `not` we can get
4452 ;; DImode `andn`. Other combinations are possible.
4454 (define_expand "anddi3"
4455 [(set (match_operand:DI 0 "register_operand" "")
4456 (and:DI (match_operand:DI 1 "arith_double_operand" "")
4457 (match_operand:DI 2 "arith_double_operand" "")))]
4461 if (! register_operand (operands[1], DImode)
4462 || ! register_operand (operands[2], DImode))
4463 /* Let GCC break this into word-at-a-time operations. */
4468 [(set (match_operand:DI 0 "register_operand" "=r")
4469 (and:DI (match_operand:DI 1 "register_operand" "%r")
4470 (match_operand:DI 2 "register_operand" "r")))]
4472 "and %1,%2,%0\;and %R1,%R2,%R0"
4473 [(set_attr "type" "binary")
4474 (set_attr "length" "8")])
4477 [(set (match_operand:DI 0 "register_operand" "=r,r")
4478 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
4479 (match_operand:DI 2 "and_operand" "rO,P")))]
4481 "* return output_64bit_and (operands); "
4482 [(set_attr "type" "binary")
4483 (set_attr "length" "4")])
4485 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
4486 ; constant with ldil;ldo.
4487 (define_insn "andsi3"
4488 [(set (match_operand:SI 0 "register_operand" "=r,r")
4489 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
4490 (match_operand:SI 2 "and_operand" "rO,P")))]
4492 "* return output_and (operands); "
4493 [(set_attr "type" "binary,shift")
4494 (set_attr "length" "4,4")])
4497 [(set (match_operand:DI 0 "register_operand" "=r")
4498 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4499 (match_operand:DI 2 "register_operand" "r")))]
4501 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
4502 [(set_attr "type" "binary")
4503 (set_attr "length" "8")])
4506 [(set (match_operand:DI 0 "register_operand" "=r")
4507 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4508 (match_operand:DI 2 "register_operand" "r")))]
4511 [(set_attr "type" "binary")
4512 (set_attr "length" "4")])
4515 [(set (match_operand:SI 0 "register_operand" "=r")
4516 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4517 (match_operand:SI 2 "register_operand" "r")))]
4520 [(set_attr "type" "binary")
4521 (set_attr "length" "4")])
4523 (define_expand "iordi3"
4524 [(set (match_operand:DI 0 "register_operand" "")
4525 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
4526 (match_operand:DI 2 "arith_double_operand" "")))]
4530 if (! register_operand (operands[1], DImode)
4531 || ! register_operand (operands[2], DImode))
4532 /* Let GCC break this into word-at-a-time operations. */
4537 [(set (match_operand:DI 0 "register_operand" "=r")
4538 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4539 (match_operand:DI 2 "register_operand" "r")))]
4541 "or %1,%2,%0\;or %R1,%R2,%R0"
4542 [(set_attr "type" "binary")
4543 (set_attr "length" "8")])
4546 [(set (match_operand:DI 0 "register_operand" "=r,r")
4547 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
4548 (match_operand:DI 2 "ior_operand" "M,i")))]
4550 "* return output_64bit_ior (operands); "
4551 [(set_attr "type" "binary,shift")
4552 (set_attr "length" "4,4")])
4555 [(set (match_operand:DI 0 "register_operand" "=r")
4556 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4557 (match_operand:DI 2 "register_operand" "r")))]
4560 [(set_attr "type" "binary")
4561 (set_attr "length" "4")])
4563 ;; Need a define_expand because we've run out of CONST_OK... characters.
4564 (define_expand "iorsi3"
4565 [(set (match_operand:SI 0 "register_operand" "")
4566 (ior:SI (match_operand:SI 1 "register_operand" "")
4567 (match_operand:SI 2 "arith32_operand" "")))]
4571 if (! (ior_operand (operands[2], SImode)
4572 || register_operand (operands[2], SImode)))
4573 operands[2] = force_reg (SImode, operands[2]);
4577 [(set (match_operand:SI 0 "register_operand" "=r,r")
4578 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
4579 (match_operand:SI 2 "ior_operand" "M,i")))]
4581 "* return output_ior (operands); "
4582 [(set_attr "type" "binary,shift")
4583 (set_attr "length" "4,4")])
4586 [(set (match_operand:SI 0 "register_operand" "=r")
4587 (ior:SI (match_operand:SI 1 "register_operand" "%r")
4588 (match_operand:SI 2 "register_operand" "r")))]
4591 [(set_attr "type" "binary")
4592 (set_attr "length" "4")])
4594 (define_expand "xordi3"
4595 [(set (match_operand:DI 0 "register_operand" "")
4596 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
4597 (match_operand:DI 2 "arith_double_operand" "")))]
4601 if (! register_operand (operands[1], DImode)
4602 || ! register_operand (operands[2], DImode))
4603 /* Let GCC break this into word-at-a-time operations. */
4608 [(set (match_operand:DI 0 "register_operand" "=r")
4609 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4610 (match_operand:DI 2 "register_operand" "r")))]
4612 "xor %1,%2,%0\;xor %R1,%R2,%R0"
4613 [(set_attr "type" "binary")
4614 (set_attr "length" "8")])
4617 [(set (match_operand:DI 0 "register_operand" "=r")
4618 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4619 (match_operand:DI 2 "register_operand" "r")))]
4622 [(set_attr "type" "binary")
4623 (set_attr "length" "4")])
4625 (define_insn "xorsi3"
4626 [(set (match_operand:SI 0 "register_operand" "=r")
4627 (xor:SI (match_operand:SI 1 "register_operand" "%r")
4628 (match_operand:SI 2 "register_operand" "r")))]
4631 [(set_attr "type" "binary")
4632 (set_attr "length" "4")])
4634 (define_expand "negdi2"
4635 [(set (match_operand:DI 0 "register_operand" "")
4636 (neg:DI (match_operand:DI 1 "register_operand" "")))]
4641 [(set (match_operand:DI 0 "register_operand" "=r")
4642 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4644 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
4645 [(set_attr "type" "unary")
4646 (set_attr "length" "8")])
4649 [(set (match_operand:DI 0 "register_operand" "=r")
4650 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4653 [(set_attr "type" "unary")
4654 (set_attr "length" "4")])
4656 (define_insn "negsi2"
4657 [(set (match_operand:SI 0 "register_operand" "=r")
4658 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
4661 [(set_attr "type" "unary")
4662 (set_attr "length" "4")])
4664 (define_expand "one_cmpldi2"
4665 [(set (match_operand:DI 0 "register_operand" "")
4666 (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
4670 if (! register_operand (operands[1], DImode))
4675 [(set (match_operand:DI 0 "register_operand" "=r")
4676 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4678 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
4679 [(set_attr "type" "unary")
4680 (set_attr "length" "8")])
4683 [(set (match_operand:DI 0 "register_operand" "=r")
4684 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4687 [(set_attr "type" "unary")
4688 (set_attr "length" "4")])
4690 (define_insn "one_cmplsi2"
4691 [(set (match_operand:SI 0 "register_operand" "=r")
4692 (not:SI (match_operand:SI 1 "register_operand" "r")))]
4695 [(set_attr "type" "unary")
4696 (set_attr "length" "4")])
4698 ;; Floating point arithmetic instructions.
4700 (define_insn "adddf3"
4701 [(set (match_operand:DF 0 "register_operand" "=f")
4702 (plus:DF (match_operand:DF 1 "register_operand" "f")
4703 (match_operand:DF 2 "register_operand" "f")))]
4704 "! TARGET_SOFT_FLOAT"
4706 [(set_attr "type" "fpalu")
4707 (set_attr "pa_combine_type" "faddsub")
4708 (set_attr "length" "4")])
4710 (define_insn "addsf3"
4711 [(set (match_operand:SF 0 "register_operand" "=f")
4712 (plus:SF (match_operand:SF 1 "register_operand" "f")
4713 (match_operand:SF 2 "register_operand" "f")))]
4714 "! TARGET_SOFT_FLOAT"
4716 [(set_attr "type" "fpalu")
4717 (set_attr "pa_combine_type" "faddsub")
4718 (set_attr "length" "4")])
4720 (define_insn "subdf3"
4721 [(set (match_operand:DF 0 "register_operand" "=f")
4722 (minus:DF (match_operand:DF 1 "register_operand" "f")
4723 (match_operand:DF 2 "register_operand" "f")))]
4724 "! TARGET_SOFT_FLOAT"
4726 [(set_attr "type" "fpalu")
4727 (set_attr "pa_combine_type" "faddsub")
4728 (set_attr "length" "4")])
4730 (define_insn "subsf3"
4731 [(set (match_operand:SF 0 "register_operand" "=f")
4732 (minus:SF (match_operand:SF 1 "register_operand" "f")
4733 (match_operand:SF 2 "register_operand" "f")))]
4734 "! TARGET_SOFT_FLOAT"
4736 [(set_attr "type" "fpalu")
4737 (set_attr "pa_combine_type" "faddsub")
4738 (set_attr "length" "4")])
4740 (define_insn "muldf3"
4741 [(set (match_operand:DF 0 "register_operand" "=f")
4742 (mult:DF (match_operand:DF 1 "register_operand" "f")
4743 (match_operand:DF 2 "register_operand" "f")))]
4744 "! TARGET_SOFT_FLOAT"
4746 [(set_attr "type" "fpmuldbl")
4747 (set_attr "pa_combine_type" "fmpy")
4748 (set_attr "length" "4")])
4750 (define_insn "mulsf3"
4751 [(set (match_operand:SF 0 "register_operand" "=f")
4752 (mult:SF (match_operand:SF 1 "register_operand" "f")
4753 (match_operand:SF 2 "register_operand" "f")))]
4754 "! TARGET_SOFT_FLOAT"
4756 [(set_attr "type" "fpmulsgl")
4757 (set_attr "pa_combine_type" "fmpy")
4758 (set_attr "length" "4")])
4760 (define_insn "divdf3"
4761 [(set (match_operand:DF 0 "register_operand" "=f")
4762 (div:DF (match_operand:DF 1 "register_operand" "f")
4763 (match_operand:DF 2 "register_operand" "f")))]
4764 "! TARGET_SOFT_FLOAT"
4766 [(set_attr "type" "fpdivdbl")
4767 (set_attr "length" "4")])
4769 (define_insn "divsf3"
4770 [(set (match_operand:SF 0 "register_operand" "=f")
4771 (div:SF (match_operand:SF 1 "register_operand" "f")
4772 (match_operand:SF 2 "register_operand" "f")))]
4773 "! TARGET_SOFT_FLOAT"
4775 [(set_attr "type" "fpdivsgl")
4776 (set_attr "length" "4")])
4778 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
4779 ;; negation can be done by subtracting from plus zero. However, this
4780 ;; violates the IEEE standard when negating plus and minus zero.
4781 (define_expand "negdf2"
4782 [(parallel [(set (match_operand:DF 0 "register_operand" "")
4783 (neg:DF (match_operand:DF 1 "register_operand" "")))
4784 (use (match_dup 2))])]
4785 "! TARGET_SOFT_FLOAT"
4787 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
4788 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
4791 operands[2] = force_reg (DFmode,
4792 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
4793 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
4798 (define_insn "negdf2_fast"
4799 [(set (match_operand:DF 0 "register_operand" "=f")
4800 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
4801 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
4805 return \"fneg,dbl %1,%0\";
4807 return \"fsub,dbl %%fr0,%1,%0\";
4809 [(set_attr "type" "fpalu")
4810 (set_attr "length" "4")])
4812 (define_expand "negsf2"
4813 [(parallel [(set (match_operand:SF 0 "register_operand" "")
4814 (neg:SF (match_operand:SF 1 "register_operand" "")))
4815 (use (match_dup 2))])]
4816 "! TARGET_SOFT_FLOAT"
4818 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
4819 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
4822 operands[2] = force_reg (SFmode,
4823 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
4824 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
4829 (define_insn "negsf2_fast"
4830 [(set (match_operand:SF 0 "register_operand" "=f")
4831 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
4832 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
4836 return \"fneg,sgl %1,%0\";
4838 return \"fsub,sgl %%fr0,%1,%0\";
4840 [(set_attr "type" "fpalu")
4841 (set_attr "length" "4")])
4843 (define_insn "absdf2"
4844 [(set (match_operand:DF 0 "register_operand" "=f")
4845 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
4846 "! TARGET_SOFT_FLOAT"
4848 [(set_attr "type" "fpalu")
4849 (set_attr "length" "4")])
4851 (define_insn "abssf2"
4852 [(set (match_operand:SF 0 "register_operand" "=f")
4853 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
4854 "! TARGET_SOFT_FLOAT"
4856 [(set_attr "type" "fpalu")
4857 (set_attr "length" "4")])
4859 (define_insn "sqrtdf2"
4860 [(set (match_operand:DF 0 "register_operand" "=f")
4861 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
4862 "! TARGET_SOFT_FLOAT"
4864 [(set_attr "type" "fpsqrtdbl")
4865 (set_attr "length" "4")])
4867 (define_insn "sqrtsf2"
4868 [(set (match_operand:SF 0 "register_operand" "=f")
4869 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
4870 "! TARGET_SOFT_FLOAT"
4872 [(set_attr "type" "fpsqrtsgl")
4873 (set_attr "length" "4")])
4875 ;; PA 2.0 floating point instructions
4879 [(set (match_operand:DF 0 "register_operand" "=f")
4880 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4881 (match_operand:DF 2 "register_operand" "f"))
4882 (match_operand:DF 3 "register_operand" "f")))]
4883 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4884 "fmpyfadd,dbl %1,%2,%3,%0"
4885 [(set_attr "type" "fpmuldbl")
4886 (set_attr "length" "4")])
4889 [(set (match_operand:DF 0 "register_operand" "=f")
4890 (plus:DF (match_operand:DF 1 "register_operand" "f")
4891 (mult:DF (match_operand:DF 2 "register_operand" "f")
4892 (match_operand:DF 3 "register_operand" "f"))))]
4893 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4894 "fmpyfadd,dbl %2,%3,%1,%0"
4895 [(set_attr "type" "fpmuldbl")
4896 (set_attr "length" "4")])
4899 [(set (match_operand:SF 0 "register_operand" "=f")
4900 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4901 (match_operand:SF 2 "register_operand" "f"))
4902 (match_operand:SF 3 "register_operand" "f")))]
4903 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4904 "fmpyfadd,sgl %1,%2,%3,%0"
4905 [(set_attr "type" "fpmulsgl")
4906 (set_attr "length" "4")])
4909 [(set (match_operand:SF 0 "register_operand" "=f")
4910 (plus:SF (match_operand:SF 1 "register_operand" "f")
4911 (mult:SF (match_operand:SF 2 "register_operand" "f")
4912 (match_operand:SF 3 "register_operand" "f"))))]
4913 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4914 "fmpyfadd,sgl %2,%3,%1,%0"
4915 [(set_attr "type" "fpmulsgl")
4916 (set_attr "length" "4")])
4918 ; fmpynfadd patterns
4920 [(set (match_operand:DF 0 "register_operand" "=f")
4921 (minus:DF (match_operand:DF 1 "register_operand" "f")
4922 (mult:DF (match_operand:DF 2 "register_operand" "f")
4923 (match_operand:DF 3 "register_operand" "f"))))]
4924 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4925 "fmpynfadd,dbl %2,%3,%1,%0"
4926 [(set_attr "type" "fpmuldbl")
4927 (set_attr "length" "4")])
4930 [(set (match_operand:SF 0 "register_operand" "=f")
4931 (minus:SF (match_operand:SF 1 "register_operand" "f")
4932 (mult:SF (match_operand:SF 2 "register_operand" "f")
4933 (match_operand:SF 3 "register_operand" "f"))))]
4934 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4935 "fmpynfadd,sgl %2,%3,%1,%0"
4936 [(set_attr "type" "fpmulsgl")
4937 (set_attr "length" "4")])
4941 [(set (match_operand:DF 0 "register_operand" "=f")
4942 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
4943 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4945 [(set_attr "type" "fpalu")
4946 (set_attr "length" "4")])
4949 [(set (match_operand:SF 0 "register_operand" "=f")
4950 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
4951 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4953 [(set_attr "type" "fpalu")
4954 (set_attr "length" "4")])
4956 ;; Generating a fused multiply sequence is a win for this case as it will
4957 ;; reduce the latency for the fused case without impacting the plain
4960 ;; Similar possibilities exist for fnegabs, shadd and other insns which
4961 ;; perform two operations with the result of the first feeding the second.
4963 [(set (match_operand:DF 0 "register_operand" "=f")
4964 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4965 (match_operand:DF 2 "register_operand" "f"))
4966 (match_operand:DF 3 "register_operand" "f")))
4967 (set (match_operand:DF 4 "register_operand" "=&f")
4968 (mult:DF (match_dup 1) (match_dup 2)))]
4969 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4970 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4971 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4973 [(set_attr "type" "fpmuldbl")
4974 (set_attr "length" "8")])
4976 ;; We want to split this up during scheduling since we want both insns
4977 ;; to schedule independently.
4979 [(set (match_operand:DF 0 "register_operand" "")
4980 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
4981 (match_operand:DF 2 "register_operand" ""))
4982 (match_operand:DF 3 "register_operand" "")))
4983 (set (match_operand:DF 4 "register_operand" "")
4984 (mult:DF (match_dup 1) (match_dup 2)))]
4985 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4986 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4987 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
4992 [(set (match_operand:SF 0 "register_operand" "=f")
4993 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4994 (match_operand:SF 2 "register_operand" "f"))
4995 (match_operand:SF 3 "register_operand" "f")))
4996 (set (match_operand:SF 4 "register_operand" "=&f")
4997 (mult:SF (match_dup 1) (match_dup 2)))]
4998 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4999 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5000 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5002 [(set_attr "type" "fpmuldbl")
5003 (set_attr "length" "8")])
5005 ;; We want to split this up during scheduling since we want both insns
5006 ;; to schedule independently.
5008 [(set (match_operand:SF 0 "register_operand" "")
5009 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5010 (match_operand:SF 2 "register_operand" ""))
5011 (match_operand:SF 3 "register_operand" "")))
5012 (set (match_operand:SF 4 "register_operand" "")
5013 (mult:SF (match_dup 1) (match_dup 2)))]
5014 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5015 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5016 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
5020 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
5023 [(set (match_operand:DF 0 "register_operand" "=f")
5024 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5025 (match_operand:DF 2 "register_operand" "f"))))]
5026 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5027 "fmpynfadd,dbl %1,%2,%%fr0,%0"
5028 [(set_attr "type" "fpmuldbl")
5029 (set_attr "length" "4")])
5032 [(set (match_operand:SF 0 "register_operand" "=f")
5033 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5034 (match_operand:SF 2 "register_operand" "f"))))]
5035 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5036 "fmpynfadd,sgl %1,%2,%%fr0,%0"
5037 [(set_attr "type" "fpmuldbl")
5038 (set_attr "length" "4")])
5041 [(set (match_operand:DF 0 "register_operand" "=f")
5042 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5043 (match_operand:DF 2 "register_operand" "f"))))
5044 (set (match_operand:DF 3 "register_operand" "=&f")
5045 (mult:DF (match_dup 1) (match_dup 2)))]
5046 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5047 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5048 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5050 [(set_attr "type" "fpmuldbl")
5051 (set_attr "length" "8")])
5054 [(set (match_operand:DF 0 "register_operand" "")
5055 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5056 (match_operand:DF 2 "register_operand" ""))))
5057 (set (match_operand:DF 3 "register_operand" "")
5058 (mult:DF (match_dup 1) (match_dup 2)))]
5059 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5060 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
5061 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
5065 [(set (match_operand:SF 0 "register_operand" "=f")
5066 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5067 (match_operand:SF 2 "register_operand" "f"))))
5068 (set (match_operand:SF 3 "register_operand" "=&f")
5069 (mult:SF (match_dup 1) (match_dup 2)))]
5070 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5071 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5072 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5074 [(set_attr "type" "fpmuldbl")
5075 (set_attr "length" "8")])
5078 [(set (match_operand:SF 0 "register_operand" "")
5079 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5080 (match_operand:SF 2 "register_operand" ""))))
5081 (set (match_operand:SF 3 "register_operand" "")
5082 (mult:SF (match_dup 1) (match_dup 2)))]
5083 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5084 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
5085 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
5088 ;; Now fused multiplies with the result of the multiply negated.
5090 [(set (match_operand:DF 0 "register_operand" "=f")
5091 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5092 (match_operand:DF 2 "register_operand" "f")))
5093 (match_operand:DF 3 "register_operand" "f")))]
5094 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5095 "fmpynfadd,dbl %1,%2,%3,%0"
5096 [(set_attr "type" "fpmuldbl")
5097 (set_attr "length" "4")])
5100 [(set (match_operand:SF 0 "register_operand" "=f")
5101 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5102 (match_operand:SF 2 "register_operand" "f")))
5103 (match_operand:SF 3 "register_operand" "f")))]
5104 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5105 "fmpynfadd,sgl %1,%2,%3,%0"
5106 [(set_attr "type" "fpmuldbl")
5107 (set_attr "length" "4")])
5110 [(set (match_operand:DF 0 "register_operand" "=f")
5111 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5112 (match_operand:DF 2 "register_operand" "f")))
5113 (match_operand:DF 3 "register_operand" "f")))
5114 (set (match_operand:DF 4 "register_operand" "=&f")
5115 (mult:DF (match_dup 1) (match_dup 2)))]
5116 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5117 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5118 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5120 [(set_attr "type" "fpmuldbl")
5121 (set_attr "length" "8")])
5124 [(set (match_operand:DF 0 "register_operand" "")
5125 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5126 (match_operand:DF 2 "register_operand" "")))
5127 (match_operand:DF 3 "register_operand" "")))
5128 (set (match_operand:DF 4 "register_operand" "")
5129 (mult:DF (match_dup 1) (match_dup 2)))]
5130 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5131 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5132 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
5137 [(set (match_operand:SF 0 "register_operand" "=f")
5138 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5139 (match_operand:SF 2 "register_operand" "f")))
5140 (match_operand:SF 3 "register_operand" "f")))
5141 (set (match_operand:SF 4 "register_operand" "=&f")
5142 (mult:SF (match_dup 1) (match_dup 2)))]
5143 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5144 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5145 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5147 [(set_attr "type" "fpmuldbl")
5148 (set_attr "length" "8")])
5151 [(set (match_operand:SF 0 "register_operand" "")
5152 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5153 (match_operand:SF 2 "register_operand" "")))
5154 (match_operand:SF 3 "register_operand" "")))
5155 (set (match_operand:SF 4 "register_operand" "")
5156 (mult:SF (match_dup 1) (match_dup 2)))]
5157 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5158 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5159 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
5164 [(set (match_operand:DF 0 "register_operand" "=f")
5165 (minus:DF (match_operand:DF 3 "register_operand" "f")
5166 (mult:DF (match_operand:DF 1 "register_operand" "f")
5167 (match_operand:DF 2 "register_operand" "f"))))
5168 (set (match_operand:DF 4 "register_operand" "=&f")
5169 (mult:DF (match_dup 1) (match_dup 2)))]
5170 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5171 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5172 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5174 [(set_attr "type" "fpmuldbl")
5175 (set_attr "length" "8")])
5178 [(set (match_operand:DF 0 "register_operand" "")
5179 (minus:DF (match_operand:DF 3 "register_operand" "")
5180 (mult:DF (match_operand:DF 1 "register_operand" "")
5181 (match_operand:DF 2 "register_operand" ""))))
5182 (set (match_operand:DF 4 "register_operand" "")
5183 (mult:DF (match_dup 1) (match_dup 2)))]
5184 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5185 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5186 (set (match_dup 0) (minus:DF (match_dup 3)
5187 (mult:DF (match_dup 1) (match_dup 2))))]
5191 [(set (match_operand:SF 0 "register_operand" "=f")
5192 (minus:SF (match_operand:SF 3 "register_operand" "f")
5193 (mult:SF (match_operand:SF 1 "register_operand" "f")
5194 (match_operand:SF 2 "register_operand" "f"))))
5195 (set (match_operand:SF 4 "register_operand" "=&f")
5196 (mult:SF (match_dup 1) (match_dup 2)))]
5197 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5198 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5199 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5201 [(set_attr "type" "fpmuldbl")
5202 (set_attr "length" "8")])
5205 [(set (match_operand:SF 0 "register_operand" "")
5206 (minus:SF (match_operand:SF 3 "register_operand" "")
5207 (mult:SF (match_operand:SF 1 "register_operand" "")
5208 (match_operand:SF 2 "register_operand" ""))))
5209 (set (match_operand:SF 4 "register_operand" "")
5210 (mult:SF (match_dup 1) (match_dup 2)))]
5211 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5212 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5213 (set (match_dup 0) (minus:SF (match_dup 3)
5214 (mult:SF (match_dup 1) (match_dup 2))))]
5218 [(set (match_operand:DF 0 "register_operand" "=f")
5219 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
5220 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
5221 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5222 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5224 [(set_attr "type" "fpalu")
5225 (set_attr "length" "8")])
5228 [(set (match_operand:DF 0 "register_operand" "")
5229 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
5230 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
5231 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5232 [(set (match_dup 2) (abs:DF (match_dup 1)))
5233 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
5237 [(set (match_operand:SF 0 "register_operand" "=f")
5238 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
5239 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
5240 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5241 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5243 [(set_attr "type" "fpalu")
5244 (set_attr "length" "8")])
5247 [(set (match_operand:SF 0 "register_operand" "")
5248 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
5249 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
5250 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5251 [(set (match_dup 2) (abs:SF (match_dup 1)))
5252 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
5255 ;;- Shift instructions
5257 ;; Optimized special case of shifting.
5260 [(set (match_operand:SI 0 "register_operand" "=r")
5261 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5265 [(set_attr "type" "load")
5266 (set_attr "length" "4")])
5269 [(set (match_operand:SI 0 "register_operand" "=r")
5270 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5274 [(set_attr "type" "load")
5275 (set_attr "length" "4")])
5278 [(set (match_operand:SI 0 "register_operand" "=r")
5279 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
5280 (match_operand:SI 3 "shadd_operand" ""))
5281 (match_operand:SI 1 "register_operand" "r")))]
5283 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
5284 [(set_attr "type" "binary")
5285 (set_attr "length" "4")])
5288 [(set (match_operand:DI 0 "register_operand" "=r")
5289 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
5290 (match_operand:DI 3 "shadd_operand" ""))
5291 (match_operand:DI 1 "register_operand" "r")))]
5293 "shladd,l %2,%O3,%1,%0"
5294 [(set_attr "type" "binary")
5295 (set_attr "length" "4")])
5297 (define_expand "ashlsi3"
5298 [(set (match_operand:SI 0 "register_operand" "")
5299 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
5300 (match_operand:SI 2 "arith32_operand" "")))]
5304 if (GET_CODE (operands[2]) != CONST_INT)
5306 rtx temp = gen_reg_rtx (SImode);
5307 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5308 if (GET_CODE (operands[1]) == CONST_INT)
5309 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
5311 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
5314 /* Make sure both inputs are not constants,
5315 there are no patterns for that. */
5316 operands[1] = force_reg (SImode, operands[1]);
5320 [(set (match_operand:SI 0 "register_operand" "=r")
5321 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5322 (match_operand:SI 2 "const_int_operand" "n")))]
5324 "{zdep|depw,z} %1,%P2,%L2,%0"
5325 [(set_attr "type" "shift")
5326 (set_attr "length" "4")])
5328 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
5329 ; Doing it like this makes slightly better code since reload can
5330 ; replace a register with a known value in range -16..15 with a
5331 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
5332 ; but since we have no more CONST_OK... characters, that is not
5334 (define_insn "zvdep32"
5335 [(set (match_operand:SI 0 "register_operand" "=r,r")
5336 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
5337 (minus:SI (const_int 31)
5338 (match_operand:SI 2 "register_operand" "q,q"))))]
5341 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
5342 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
5343 [(set_attr "type" "shift,shift")
5344 (set_attr "length" "4,4")])
5346 (define_insn "zvdep_imm32"
5347 [(set (match_operand:SI 0 "register_operand" "=r")
5348 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
5349 (minus:SI (const_int 31)
5350 (match_operand:SI 2 "register_operand" "q"))))]
5354 int x = INTVAL (operands[1]);
5355 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5356 operands[1] = GEN_INT ((x & 0xf) - 0x10);
5357 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
5359 [(set_attr "type" "shift")
5360 (set_attr "length" "4")])
5362 (define_insn "vdepi_ior"
5363 [(set (match_operand:SI 0 "register_operand" "=r")
5364 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
5365 (minus:SI (const_int 31)
5366 (match_operand:SI 2 "register_operand" "q")))
5367 (match_operand:SI 3 "register_operand" "0")))]
5368 ; accept ...0001...1, can this be generalized?
5369 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5372 int x = INTVAL (operands[1]);
5373 operands[2] = GEN_INT (exact_log2 (x + 1));
5374 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
5376 [(set_attr "type" "shift")
5377 (set_attr "length" "4")])
5379 (define_insn "vdepi_and"
5380 [(set (match_operand:SI 0 "register_operand" "=r")
5381 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
5382 (minus:SI (const_int 31)
5383 (match_operand:SI 2 "register_operand" "q")))
5384 (match_operand:SI 3 "register_operand" "0")))]
5385 ; this can be generalized...!
5386 "INTVAL (operands[1]) == -2"
5389 int x = INTVAL (operands[1]);
5390 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5391 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
5393 [(set_attr "type" "shift")
5394 (set_attr "length" "4")])
5396 (define_expand "ashldi3"
5397 [(set (match_operand:DI 0 "register_operand" "")
5398 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
5399 (match_operand:DI 2 "arith32_operand" "")))]
5403 if (GET_CODE (operands[2]) != CONST_INT)
5405 rtx temp = gen_reg_rtx (DImode);
5406 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5407 if (GET_CODE (operands[1]) == CONST_INT)
5408 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
5410 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
5413 /* Make sure both inputs are not constants,
5414 there are no patterns for that. */
5415 operands[1] = force_reg (DImode, operands[1]);
5419 [(set (match_operand:DI 0 "register_operand" "=r")
5420 (ashift:DI (match_operand:DI 1 "register_operand" "r")
5421 (match_operand:DI 2 "const_int_operand" "n")))]
5423 "depd,z %1,%p2,%Q2,%0"
5424 [(set_attr "type" "shift")
5425 (set_attr "length" "4")])
5427 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
5428 ; Doing it like this makes slightly better code since reload can
5429 ; replace a register with a known value in range -16..15 with a
5430 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
5431 ; but since we have no more CONST_OK... characters, that is not
5433 (define_insn "zvdep64"
5434 [(set (match_operand:DI 0 "register_operand" "=r,r")
5435 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
5436 (minus:DI (const_int 63)
5437 (match_operand:DI 2 "register_operand" "q,q"))))]
5440 depd,z %1,%%sar,64,%0
5441 depdi,z %1,%%sar,64,%0"
5442 [(set_attr "type" "shift,shift")
5443 (set_attr "length" "4,4")])
5445 (define_insn "zvdep_imm64"
5446 [(set (match_operand:DI 0 "register_operand" "=r")
5447 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
5448 (minus:DI (const_int 63)
5449 (match_operand:DI 2 "register_operand" "q"))))]
5453 int x = INTVAL (operands[1]);
5454 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5455 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
5456 return \"depdi,z %1,%%sar,%2,%0\";
5458 [(set_attr "type" "shift")
5459 (set_attr "length" "4")])
5462 [(set (match_operand:DI 0 "register_operand" "=r")
5463 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
5464 (minus:DI (const_int 63)
5465 (match_operand:DI 2 "register_operand" "q")))
5466 (match_operand:DI 3 "register_operand" "0")))]
5467 ; accept ...0001...1, can this be generalized?
5468 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5471 int x = INTVAL (operands[1]);
5472 operands[2] = GEN_INT (exact_log2 (x + 1));
5473 return \"depdi -1,%%sar,%2,%0\";
5475 [(set_attr "type" "shift")
5476 (set_attr "length" "4")])
5479 [(set (match_operand:DI 0 "register_operand" "=r")
5480 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
5481 (minus:DI (const_int 63)
5482 (match_operand:DI 2 "register_operand" "q")))
5483 (match_operand:DI 3 "register_operand" "0")))]
5484 ; this can be generalized...!
5485 "TARGET_64BIT && INTVAL (operands[1]) == -2"
5488 int x = INTVAL (operands[1]);
5489 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5490 return \"depdi 0,%%sar,%2,%0\";
5492 [(set_attr "type" "shift")
5493 (set_attr "length" "4")])
5495 (define_expand "ashrsi3"
5496 [(set (match_operand:SI 0 "register_operand" "")
5497 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
5498 (match_operand:SI 2 "arith32_operand" "")))]
5502 if (GET_CODE (operands[2]) != CONST_INT)
5504 rtx temp = gen_reg_rtx (SImode);
5505 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5506 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
5512 [(set (match_operand:SI 0 "register_operand" "=r")
5513 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5514 (match_operand:SI 2 "const_int_operand" "n")))]
5516 "{extrs|extrw,s} %1,%P2,%L2,%0"
5517 [(set_attr "type" "shift")
5518 (set_attr "length" "4")])
5520 (define_insn "vextrs32"
5521 [(set (match_operand:SI 0 "register_operand" "=r")
5522 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5523 (minus:SI (const_int 31)
5524 (match_operand:SI 2 "register_operand" "q"))))]
5526 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
5527 [(set_attr "type" "shift")
5528 (set_attr "length" "4")])
5530 (define_expand "ashrdi3"
5531 [(set (match_operand:DI 0 "register_operand" "")
5532 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5533 (match_operand:DI 2 "arith32_operand" "")))]
5537 if (GET_CODE (operands[2]) != CONST_INT)
5539 rtx temp = gen_reg_rtx (DImode);
5540 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5541 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
5547 [(set (match_operand:DI 0 "register_operand" "=r")
5548 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5549 (match_operand:DI 2 "const_int_operand" "n")))]
5551 "extrd,s %1,%p2,%Q2,%0"
5552 [(set_attr "type" "shift")
5553 (set_attr "length" "4")])
5555 (define_insn "vextrs64"
5556 [(set (match_operand:DI 0 "register_operand" "=r")
5557 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5558 (minus:DI (const_int 63)
5559 (match_operand:DI 2 "register_operand" "q"))))]
5561 "extrd,s %1,%%sar,64,%0"
5562 [(set_attr "type" "shift")
5563 (set_attr "length" "4")])
5565 (define_insn "lshrsi3"
5566 [(set (match_operand:SI 0 "register_operand" "=r,r")
5567 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
5568 (match_operand:SI 2 "arith32_operand" "q,n")))]
5571 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
5572 {extru|extrw,u} %1,%P2,%L2,%0"
5573 [(set_attr "type" "shift")
5574 (set_attr "length" "4")])
5576 (define_insn "lshrdi3"
5577 [(set (match_operand:DI 0 "register_operand" "=r,r")
5578 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
5579 (match_operand:DI 2 "arith32_operand" "q,n")))]
5582 shrpd %%r0,%1,%%sar,%0
5583 extrd,u %1,%p2,%Q2,%0"
5584 [(set_attr "type" "shift")
5585 (set_attr "length" "4")])
5587 (define_insn "rotrsi3"
5588 [(set (match_operand:SI 0 "register_operand" "=r,r")
5589 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
5590 (match_operand:SI 2 "arith32_operand" "q,n")))]
5594 if (GET_CODE (operands[2]) == CONST_INT)
5596 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
5597 return \"{shd|shrpw} %1,%1,%2,%0\";
5600 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
5602 [(set_attr "type" "shift")
5603 (set_attr "length" "4")])
5605 (define_expand "rotlsi3"
5606 [(set (match_operand:SI 0 "register_operand" "")
5607 (rotate:SI (match_operand:SI 1 "register_operand" "")
5608 (match_operand:SI 2 "arith32_operand" "")))]
5612 if (GET_CODE (operands[2]) != CONST_INT)
5614 rtx temp = gen_reg_rtx (SImode);
5615 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
5616 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
5619 /* Else expand normally. */
5623 [(set (match_operand:SI 0 "register_operand" "=r")
5624 (rotate:SI (match_operand:SI 1 "register_operand" "r")
5625 (match_operand:SI 2 "const_int_operand" "n")))]
5629 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
5630 return \"{shd|shrpw} %1,%1,%2,%0\";
5632 [(set_attr "type" "shift")
5633 (set_attr "length" "4")])
5636 [(set (match_operand:SI 0 "register_operand" "=r")
5637 (match_operator:SI 5 "plus_xor_ior_operator"
5638 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
5639 (match_operand:SI 3 "const_int_operand" "n"))
5640 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5641 (match_operand:SI 4 "const_int_operand" "n"))]))]
5642 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5643 "{shd|shrpw} %1,%2,%4,%0"
5644 [(set_attr "type" "shift")
5645 (set_attr "length" "4")])
5648 [(set (match_operand:SI 0 "register_operand" "=r")
5649 (match_operator:SI 5 "plus_xor_ior_operator"
5650 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5651 (match_operand:SI 4 "const_int_operand" "n"))
5652 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5653 (match_operand:SI 3 "const_int_operand" "n"))]))]
5654 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5655 "{shd|shrpw} %1,%2,%4,%0"
5656 [(set_attr "type" "shift")
5657 (set_attr "length" "4")])
5660 [(set (match_operand:SI 0 "register_operand" "=r")
5661 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
5662 (match_operand:SI 2 "const_int_operand" ""))
5663 (match_operand:SI 3 "const_int_operand" "")))]
5664 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
5667 int cnt = INTVAL (operands[2]) & 31;
5668 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
5669 operands[2] = GEN_INT (31 - cnt);
5670 return \"{zdep|depw,z} %1,%2,%3,%0\";
5672 [(set_attr "type" "shift")
5673 (set_attr "length" "4")])
5675 ;; Unconditional and other jump instructions.
5677 ;; This can only be used in a leaf function, so we do
5678 ;; not need to use the PIC register when generating PIC code.
5679 (define_insn "return"
5683 "hppa_can_use_return_insn_p ()"
5687 return \"bve%* (%%r2)\";
5688 return \"bv%* %%r0(%%r2)\";
5690 [(set_attr "type" "branch")
5691 (set_attr "length" "4")])
5693 ;; Emit a different pattern for functions which have non-trivial
5694 ;; epilogues so as not to confuse jump and reorg.
5695 (define_insn "return_internal"
5703 return \"bve%* (%%r2)\";
5704 return \"bv%* %%r0(%%r2)\";
5706 [(set_attr "type" "branch")
5707 (set_attr "length" "4")])
5709 ;; Use the PIC register to ensure it's restored after a
5710 ;; call in PIC mode.
5711 (define_insn "return_internal_pic"
5713 (use (match_operand 0 "register_operand" "r"))
5715 "flag_pic && true_regnum (operands[0]) == PIC_OFFSET_TABLE_REGNUM"
5719 return \"bve%* (%%r2)\";
5720 return \"bv%* %%r0(%%r2)\";
5722 [(set_attr "type" "branch")
5723 (set_attr "length" "4")])
5725 ;; Use the PIC register to ensure it's restored after a
5726 ;; call in PIC mode. This is used for eh returns which
5727 ;; bypass the return stub.
5728 (define_insn "return_external_pic"
5730 (use (match_operand 0 "register_operand" "r"))
5732 (clobber (reg:SI 1))]
5734 && current_function_calls_eh_return
5735 && true_regnum (operands[0]) == PIC_OFFSET_TABLE_REGNUM"
5736 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
5737 [(set_attr "type" "branch")
5738 (set_attr "length" "12")])
5740 (define_expand "prologue"
5743 "hppa_expand_prologue ();DONE;")
5745 (define_expand "sibcall_epilogue"
5750 hppa_expand_epilogue ();
5754 (define_expand "epilogue"
5759 /* Try to use the trivial return first. Else use the full
5761 if (hppa_can_use_return_insn_p ())
5762 emit_jump_insn (gen_return ());
5767 hppa_expand_epilogue ();
5770 rtx pic = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
5772 /* EH returns bypass the normal return stub. Thus, we must do an
5773 interspace branch to return from functions that call eh_return.
5774 This is only a problem for returns from shared code. */
5775 if (current_function_calls_eh_return)
5776 x = gen_return_external_pic (pic);
5778 x = gen_return_internal_pic (pic);
5781 x = gen_return_internal ();
5787 ;; Special because we use the value placed in %r2 by the bl instruction
5788 ;; from within its delay slot to set the value for the 2nd parameter to
5790 (define_insn "call_profiler"
5791 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5792 (match_operand 1 "" ""))
5793 (use (match_operand 2 "" ""))
5796 (clobber (reg:SI 2))]
5802 output_arg_descriptor (insn);
5804 xoperands[0] = operands[0];
5805 xoperands[1] = operands[2];
5806 xoperands[2] = gen_label_rtx ();
5807 output_asm_insn (\"{bl|b,l} %0,%%r2\;ldo %1-%2(%%r2),%%r25\", xoperands);
5809 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5810 CODE_LABEL_NUMBER (xoperands[2]));
5813 [(set_attr "type" "multi")
5814 (set_attr "length" "8")])
5816 (define_insn "blockage"
5817 [(unspec_volatile [(const_int 2)] 0)]
5820 [(set_attr "length" "0")])
5823 [(set (pc) (label_ref (match_operand 0 "" "")))]
5827 extern int optimize;
5829 if (GET_MODE (insn) == SImode)
5832 /* An unconditional branch which can reach its target. */
5833 if (get_attr_length (insn) != 24
5834 && get_attr_length (insn) != 16)
5837 /* An unconditional branch which can not reach its target.
5839 We need to be able to use %r1 as a scratch register; however,
5840 we can never be sure whether or not it's got a live value in
5841 it. Therefore, we must restore its original value after the
5844 To make matters worse, we don't have a stack slot which we
5845 can always clobber. sp-12/sp-16 shouldn't ever have a live
5846 value during a non-optimizing compilation, so we use those
5847 slots for now. We don't support very long branches when
5848 optimizing -- they should be quite rare when optimizing.
5850 Really the way to go long term is a register scavenger; goto
5851 the target of the jump and find a register which we can use
5852 as a scratch to hold the value in %r1. */
5854 /* We don't know how to register scavenge yet. */
5858 /* First store %r1 into the stack. */
5859 output_asm_insn (\"stw %%r1,-16(%%r30)\", operands);
5861 /* Now load the target address into %r1 and do an indirect jump
5862 to the value specified in %r1. Be careful to generate PIC
5867 xoperands[0] = operands[0];
5868 if (TARGET_SOM || ! TARGET_GAS)
5870 xoperands[1] = gen_label_rtx ();
5872 output_asm_insn (\"{bl|b,l} .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\",
5874 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5875 CODE_LABEL_NUMBER (xoperands[1]));
5876 output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\", xoperands);
5880 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
5881 output_asm_insn (\"addil L'%l0-$PIC_pcrel$0+4,%%r1\", xoperands);
5882 output_asm_insn (\"ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1\", xoperands);
5884 output_asm_insn (\"bv %%r0(%%r1)\", xoperands);
5887 output_asm_insn (\"ldil L'%l0,%%r1\\n\\tbe R'%l0(%%sr4,%%r1)\", operands);;
5889 /* And restore the value of %r1 in the delay slot. We're not optimizing,
5890 so we know nothing else can be in the delay slot. */
5891 return \"ldw -16(%%r30),%%r1\";
5893 [(set_attr "type" "uncond_branch")
5894 (set_attr "pa_combine_type" "uncond_branch")
5895 (set (attr "length")
5896 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
5897 (if_then_else (lt (abs (minus (match_dup 0)
5898 (plus (pc) (const_int 8))))
5902 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
5904 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5909 ;; Subroutines of "casesi".
5910 ;; operand 0 is index
5911 ;; operand 1 is the minimum bound
5912 ;; operand 2 is the maximum bound - minimum bound + 1
5913 ;; operand 3 is CODE_LABEL for the table;
5914 ;; operand 4 is the CODE_LABEL to go to if index out of range.
5916 (define_expand "casesi"
5917 [(match_operand:SI 0 "general_operand" "")
5918 (match_operand:SI 1 "const_int_operand" "")
5919 (match_operand:SI 2 "const_int_operand" "")
5920 (match_operand 3 "" "")
5921 (match_operand 4 "" "")]
5925 if (GET_CODE (operands[0]) != REG)
5926 operands[0] = force_reg (SImode, operands[0]);
5928 if (operands[1] != const0_rtx)
5930 rtx reg = gen_reg_rtx (SImode);
5932 operands[1] = GEN_INT (-INTVAL (operands[1]));
5933 if (!INT_14_BITS (operands[1]))
5934 operands[1] = force_reg (SImode, operands[1]);
5935 emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
5940 /* In 64bit mode we must make sure to wipe the upper bits of the register
5941 just in case the addition overflowed or we had random bits in the
5942 high part of the register. */
5945 rtx reg = gen_reg_rtx (DImode);
5946 emit_insn (gen_extendsidi2 (reg, operands[0]));
5947 operands[0] = gen_rtx_SUBREG (SImode, reg, 4);
5950 if (!INT_5_BITS (operands[2]))
5951 operands[2] = force_reg (SImode, operands[2]);
5953 emit_insn (gen_cmpsi (operands[0], operands[2]));
5954 emit_jump_insn (gen_bgtu (operands[4]));
5955 if (TARGET_BIG_SWITCH)
5957 rtx temp = gen_reg_rtx (SImode);
5958 emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0]));
5961 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
5965 (define_insn "casesi0"
5967 (mem:SI (plus:SI (pc)
5968 (match_operand:SI 0 "register_operand" "r")))
5969 (label_ref (match_operand 1 "" ""))))]
5972 [(set_attr "type" "multi")
5973 (set_attr "length" "8")])
5975 ;; Need nops for the calls because execution is supposed to continue
5976 ;; past; we don't want to nullify an instruction that we need.
5977 ;;- jump to subroutine
5979 (define_expand "call"
5980 [(parallel [(call (match_operand:SI 0 "" "")
5981 (match_operand 1 "" ""))
5982 (clobber (reg:SI 2))])]
5989 if (TARGET_PORTABLE_RUNTIME)
5990 op = force_reg (SImode, XEXP (operands[0], 0));
5992 op = XEXP (operands[0], 0);
5995 emit_move_insn (arg_pointer_rtx,
5996 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
5999 /* Use two different patterns for calls to explicitly named functions
6000 and calls through function pointers. This is necessary as these two
6001 types of calls use different calling conventions, and CSE might try
6002 to change the named call into an indirect call in some cases (using
6003 two patterns keeps CSE from performing this optimization). */
6004 if (GET_CODE (op) == SYMBOL_REF)
6005 call_insn = emit_call_insn (gen_call_internal_symref (op, operands[1]));
6006 else if (TARGET_64BIT)
6008 rtx tmpreg = force_reg (word_mode, op);
6009 call_insn = emit_call_insn (gen_call_internal_reg_64bit (tmpreg,
6014 rtx tmpreg = gen_rtx_REG (word_mode, 22);
6015 emit_move_insn (tmpreg, force_reg (word_mode, op));
6016 call_insn = emit_call_insn (gen_call_internal_reg (operands[1]));
6021 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6023 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
6025 /* After each call we must restore the PIC register, even if it
6026 doesn't appear to be used. */
6027 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
6032 (define_insn "call_internal_symref"
6033 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6034 (match_operand 1 "" "i"))
6035 (clobber (reg:SI 2))
6036 (use (const_int 0))]
6037 "! TARGET_PORTABLE_RUNTIME"
6040 output_arg_descriptor (insn);
6041 return output_call (insn, operands[0], 0);
6043 [(set_attr "type" "call")
6044 (set (attr "length")
6045 ;; If we're sure that we can either reach the target or that the
6046 ;; linker can use a long-branch stub, then the length is at most
6049 ;; For long-calls the length will be at most 68 bytes (non-pic)
6050 ;; or 84 bytes (pic). */
6051 ;; Else we have to use a long-call;
6052 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6055 (if_then_else (eq (symbol_ref "flag_pic")
6060 (define_insn "call_internal_reg_64bit"
6061 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
6062 (match_operand 1 "" "i"))
6063 (clobber (reg:SI 2))
6064 (use (const_int 1))]
6068 /* ??? Needs more work. Length computation, split into multiple insns,
6069 do not use %r22 directly, expose delay slot. */
6070 return \"ldd 16(%0),%%r2\;ldd 24(%0),%%r27\;bve,l (%%r2),%%r2\;nop\";
6072 [(set_attr "type" "dyncall")
6073 (set (attr "length") (const_int 16))])
6075 (define_insn "call_internal_reg"
6076 [(call (mem:SI (reg:SI 22))
6077 (match_operand 0 "" "i"))
6078 (clobber (reg:SI 2))
6079 (use (const_int 1))]
6085 /* First the special case for kernels, level 0 systems, etc. */
6086 if (TARGET_FAST_INDIRECT_CALLS)
6087 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
6089 /* Now the normal case -- we can reach $$dyncall directly or
6090 we're sure that we can get there via a long-branch stub.
6092 No need to check target flags as the length uniquely identifies
6093 the remaining cases. */
6094 if (get_attr_length (insn) == 8)
6095 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
6097 /* Long millicode call, but we are not generating PIC or portable runtime
6099 if (get_attr_length (insn) == 12)
6100 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
6102 /* Long millicode call for portable runtime. */
6103 if (get_attr_length (insn) == 20)
6104 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
6106 /* If we're generating PIC code. */
6107 xoperands[0] = operands[0];
6108 if (TARGET_SOM || ! TARGET_GAS)
6109 xoperands[1] = gen_label_rtx ();
6110 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
6111 if (TARGET_SOM || ! TARGET_GAS)
6113 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
6114 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
6115 CODE_LABEL_NUMBER (xoperands[1]));
6116 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
6120 output_asm_insn (\"addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1\", xoperands);
6121 output_asm_insn (\"ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1\",
6124 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
6125 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
6128 [(set_attr "type" "dyncall")
6129 (set (attr "length")
6131 ;; First FAST_INDIRECT_CALLS
6132 (ne (symbol_ref "TARGET_FAST_INDIRECT_CALLS")
6136 ;; Target (or stub) within reach
6137 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
6139 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
6144 (ne (symbol_ref "flag_pic")
6148 ;; Out of reach PORTABLE_RUNTIME
6149 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
6153 ;; Out of reach, can use ble
6156 (define_expand "call_value"
6157 [(parallel [(set (match_operand 0 "" "")
6158 (call (match_operand:SI 1 "" "")
6159 (match_operand 2 "" "")))
6160 (clobber (reg:SI 2))])]
6167 if (TARGET_PORTABLE_RUNTIME)
6168 op = force_reg (word_mode, XEXP (operands[1], 0));
6170 op = XEXP (operands[1], 0);
6173 emit_move_insn (arg_pointer_rtx,
6174 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6177 /* Use two different patterns for calls to explicitly named functions
6178 and calls through function pointers. This is necessary as these two
6179 types of calls use different calling conventions, and CSE might try
6180 to change the named call into an indirect call in some cases (using
6181 two patterns keeps CSE from performing this optimization). */
6182 if (GET_CODE (op) == SYMBOL_REF)
6183 call_insn = emit_call_insn (gen_call_value_internal_symref (operands[0],
6186 else if (TARGET_64BIT)
6188 rtx tmpreg = force_reg (word_mode, op);
6190 = emit_call_insn (gen_call_value_internal_reg_64bit (operands[0],
6196 rtx tmpreg = gen_rtx_REG (word_mode, 22);
6197 emit_move_insn (tmpreg, force_reg (word_mode, op));
6198 call_insn = emit_call_insn (gen_call_value_internal_reg (operands[0],
6203 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6205 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
6207 /* After each call we must restore the PIC register, even if it
6208 doesn't appear to be used. */
6209 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
6214 (define_insn "call_value_internal_symref"
6215 [(set (match_operand 0 "" "=rf")
6216 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6217 (match_operand 2 "" "i")))
6218 (clobber (reg:SI 2))
6219 (use (const_int 0))]
6220 ;;- Don't use operand 1 for most machines.
6221 "! TARGET_PORTABLE_RUNTIME"
6224 output_arg_descriptor (insn);
6225 return output_call (insn, operands[1], 0);
6227 [(set_attr "type" "call")
6228 (set (attr "length")
6229 ;; If we're sure that we can either reach the target or that the
6230 ;; linker can use a long-branch stub, then the length is at most
6233 ;; For long-calls the length will be at most 68 bytes (non-pic)
6234 ;; or 84 bytes (pic). */
6235 ;; Else we have to use a long-call;
6236 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6239 (if_then_else (eq (symbol_ref "flag_pic")
6244 (define_insn "call_value_internal_reg_64bit"
6245 [(set (match_operand 0 "" "=rf")
6246 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
6247 (match_operand 2 "" "i")))
6248 (clobber (reg:SI 2))
6249 (use (const_int 1))]
6253 /* ??? Needs more work. Length computation, split into multiple insns,
6254 do not use %r22 directly, expose delay slot. */
6255 return \"ldd 16(%1),%%r2\;ldd 24(%1),%%r27\;bve,l (%%r2),%%r2\;nop\";
6257 [(set_attr "type" "dyncall")
6258 (set (attr "length") (const_int 16))])
6260 (define_insn "call_value_internal_reg"
6261 [(set (match_operand 0 "" "=rf")
6262 (call (mem:SI (reg:SI 22))
6263 (match_operand 1 "" "i")))
6264 (clobber (reg:SI 2))
6265 (use (const_int 1))]
6271 /* First the special case for kernels, level 0 systems, etc. */
6272 if (TARGET_FAST_INDIRECT_CALLS)
6273 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
6275 /* Now the normal case -- we can reach $$dyncall directly or
6276 we're sure that we can get there via a long-branch stub.
6278 No need to check target flags as the length uniquely identifies
6279 the remaining cases. */
6280 if (get_attr_length (insn) == 8)
6281 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
6283 /* Long millicode call, but we are not generating PIC or portable runtime
6285 if (get_attr_length (insn) == 12)
6286 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
6288 /* Long millicode call for portable runtime. */
6289 if (get_attr_length (insn) == 20)
6290 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
6292 /* If we're generating PIC code. */
6293 xoperands[0] = operands[1];
6294 if (TARGET_SOM || ! TARGET_GAS)
6295 xoperands[1] = gen_label_rtx ();
6296 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
6297 if (TARGET_SOM || ! TARGET_GAS)
6299 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
6300 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
6301 CODE_LABEL_NUMBER (xoperands[1]));
6302 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
6306 output_asm_insn (\"addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1\", xoperands);
6307 output_asm_insn (\"ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1\",
6310 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
6311 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
6314 [(set_attr "type" "dyncall")
6315 (set (attr "length")
6317 ;; First FAST_INDIRECT_CALLS
6318 (ne (symbol_ref "TARGET_FAST_INDIRECT_CALLS")
6322 ;; Target (or stub) within reach
6323 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
6325 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
6330 (ne (symbol_ref "flag_pic")
6334 ;; Out of reach PORTABLE_RUNTIME
6335 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
6339 ;; Out of reach, can use ble
6342 ;; Call subroutine returning any type.
6344 (define_expand "untyped_call"
6345 [(parallel [(call (match_operand 0 "" "")
6347 (match_operand 1 "" "")
6348 (match_operand 2 "" "")])]
6354 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6356 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6358 rtx set = XVECEXP (operands[2], 0, i);
6359 emit_move_insn (SET_DEST (set), SET_SRC (set));
6362 /* The optimizer does not know that the call sets the function value
6363 registers we stored in the result block. We avoid problems by
6364 claiming that all hard registers are used and clobbered at this
6366 emit_insn (gen_blockage ());
6371 (define_expand "sibcall"
6372 [(parallel [(call (match_operand:SI 0 "" "")
6373 (match_operand 1 "" ""))
6374 (clobber (reg:SI 0))])]
6375 "! TARGET_PORTABLE_RUNTIME"
6381 op = XEXP (operands[0], 0);
6383 /* We do not allow indirect sibling calls. */
6384 call_insn = emit_call_insn (gen_sibcall_internal_symref (op, operands[1]));
6388 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6390 /* After each call we must restore the PIC register, even if it
6391 doesn't appear to be used. */
6392 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
6397 (define_insn "sibcall_internal_symref"
6398 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6399 (match_operand 1 "" "i"))
6400 (clobber (reg:SI 0))
6402 (use (const_int 0))]
6403 "! TARGET_PORTABLE_RUNTIME"
6406 output_arg_descriptor (insn);
6407 return output_call (insn, operands[0], 1);
6409 [(set_attr "type" "call")
6410 (set (attr "length")
6411 ;; If we're sure that we can either reach the target or that the
6412 ;; linker can use a long-branch stub, then the length is at most
6415 ;; For long-calls the length will be at most 68 bytes (non-pic)
6416 ;; or 84 bytes (pic). */
6417 ;; Else we have to use a long-call;
6418 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6421 (if_then_else (eq (symbol_ref "flag_pic")
6426 (define_expand "sibcall_value"
6427 [(parallel [(set (match_operand 0 "" "")
6428 (call (match_operand:SI 1 "" "")
6429 (match_operand 2 "" "")))
6430 (clobber (reg:SI 0))])]
6431 "! TARGET_PORTABLE_RUNTIME"
6437 op = XEXP (operands[1], 0);
6439 /* We do not allow indirect sibling calls. */
6440 call_insn = emit_call_insn (gen_sibcall_value_internal_symref (operands[0],
6445 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6447 /* After each call we must restore the PIC register, even if it
6448 doesn't appear to be used. */
6449 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
6454 (define_insn "sibcall_value_internal_symref"
6455 [(set (match_operand 0 "" "=rf")
6456 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6457 (match_operand 2 "" "i")))
6458 (clobber (reg:SI 0))
6460 (use (const_int 0))]
6461 ;;- Don't use operand 1 for most machines.
6462 "! TARGET_PORTABLE_RUNTIME"
6465 output_arg_descriptor (insn);
6466 return output_call (insn, operands[1], 1);
6468 [(set_attr "type" "call")
6469 (set (attr "length")
6470 ;; If we're sure that we can either reach the target or that the
6471 ;; linker can use a long-branch stub, then the length is at most
6474 ;; For long-calls the length will be at most 68 bytes (non-pic)
6475 ;; or 84 bytes (pic). */
6476 ;; Else we have to use a long-call;
6477 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6480 (if_then_else (eq (symbol_ref "flag_pic")
6489 [(set_attr "type" "move")
6490 (set_attr "length" "4")])
6492 ;; These are just placeholders so we know where branch tables
6494 (define_insn "begin_brtab"
6499 /* Only GAS actually supports this pseudo-op. */
6501 return \".begin_brtab\";
6505 [(set_attr "type" "move")
6506 (set_attr "length" "0")])
6508 (define_insn "end_brtab"
6513 /* Only GAS actually supports this pseudo-op. */
6515 return \".end_brtab\";
6519 [(set_attr "type" "move")
6520 (set_attr "length" "0")])
6522 ;;; EH does longjmp's from and within the data section. Thus,
6523 ;;; an interspace branch is required for the longjmp implementation.
6524 ;;; Registers r1 and r2 are used as scratch registers for the jump.
6525 (define_expand "interspace_jump"
6527 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6528 (clobber (match_dup 1))])]
6532 operands[1] = gen_rtx_REG (word_mode, 2);
6536 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6537 (clobber (reg:SI 2))]
6539 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
6540 [(set_attr "type" "branch")
6541 (set_attr "length" "12")])
6544 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6545 (clobber (reg:DI 2))]
6547 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
6548 [(set_attr "type" "branch")
6549 (set_attr "length" "12")])
6551 (define_expand "builtin_longjmp"
6552 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6556 /* The elements of the buffer are, in order: */
6557 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6558 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
6559 POINTER_SIZE / BITS_PER_UNIT));
6560 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
6561 (POINTER_SIZE * 2) / BITS_PER_UNIT));
6562 rtx pv = gen_rtx_REG (Pmode, 1);
6564 /* This bit is the same as expand_builtin_longjmp. */
6565 emit_move_insn (hard_frame_pointer_rtx, fp);
6566 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6567 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6568 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6570 /* Load the label we are jumping through into r1 so that we know
6571 where to look for it when we get back to setjmp's function for
6572 restoring the gp. */
6573 emit_move_insn (pv, lab);
6575 /* Prevent the insns above from being scheduled into the delay slot
6576 of the interspace jump because the space register could change. */
6577 emit_insn (gen_blockage ());
6579 emit_jump_insn (gen_interspace_jump (pv));
6584 ;;; Hope this is only within a function...
6585 (define_insn "indirect_jump"
6586 [(set (pc) (match_operand 0 "register_operand" "r"))]
6587 "GET_MODE (operands[0]) == word_mode"
6589 [(set_attr "type" "branch")
6590 (set_attr "length" "4")])
6592 (define_expand "extzv"
6593 [(set (match_operand 0 "register_operand" "")
6594 (zero_extract (match_operand 1 "register_operand" "")
6595 (match_operand 2 "uint32_operand" "")
6596 (match_operand 3 "uint32_operand" "")))]
6601 emit_insn (gen_extzv_64 (operands[0], operands[1],
6602 operands[2], operands[3]));
6604 emit_insn (gen_extzv_32 (operands[0], operands[1],
6605 operands[2], operands[3]));
6609 (define_insn "extzv_32"
6610 [(set (match_operand:SI 0 "register_operand" "=r")
6611 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
6612 (match_operand:SI 2 "uint5_operand" "")
6613 (match_operand:SI 3 "uint5_operand" "")))]
6615 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
6616 [(set_attr "type" "shift")
6617 (set_attr "length" "4")])
6620 [(set (match_operand:SI 0 "register_operand" "=r")
6621 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
6623 (match_operand:SI 2 "register_operand" "q")))]
6625 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
6626 [(set_attr "type" "shift")
6627 (set_attr "length" "4")])
6629 (define_insn "extzv_64"
6630 [(set (match_operand:DI 0 "register_operand" "=r")
6631 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
6632 (match_operand:DI 2 "uint32_operand" "")
6633 (match_operand:DI 3 "uint32_operand" "")))]
6635 "extrd,u %1,%3+%2-1,%2,%0"
6636 [(set_attr "type" "shift")
6637 (set_attr "length" "4")])
6640 [(set (match_operand:DI 0 "register_operand" "=r")
6641 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
6643 (match_operand:DI 2 "register_operand" "q")))]
6645 "extrd,u %1,%%sar,1,%0"
6646 [(set_attr "type" "shift")
6647 (set_attr "length" "4")])
6649 (define_expand "extv"
6650 [(set (match_operand 0 "register_operand" "")
6651 (sign_extract (match_operand 1 "register_operand" "")
6652 (match_operand 2 "uint32_operand" "")
6653 (match_operand 3 "uint32_operand" "")))]
6658 emit_insn (gen_extv_64 (operands[0], operands[1],
6659 operands[2], operands[3]));
6662 if (! uint5_operand (operands[2], SImode)
6663 || ! uint5_operand (operands[3], SImode))
6665 emit_insn (gen_extv_32 (operands[0], operands[1],
6666 operands[2], operands[3]));
6671 (define_insn "extv_32"
6672 [(set (match_operand:SI 0 "register_operand" "=r")
6673 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
6674 (match_operand:SI 2 "uint5_operand" "")
6675 (match_operand:SI 3 "uint5_operand" "")))]
6677 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
6678 [(set_attr "type" "shift")
6679 (set_attr "length" "4")])
6682 [(set (match_operand:SI 0 "register_operand" "=r")
6683 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
6685 (match_operand:SI 2 "register_operand" "q")))]
6687 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
6688 [(set_attr "type" "shift")
6689 (set_attr "length" "4")])
6691 (define_insn "extv_64"
6692 [(set (match_operand:DI 0 "register_operand" "=r")
6693 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
6694 (match_operand:DI 2 "uint32_operand" "")
6695 (match_operand:DI 3 "uint32_operand" "")))]
6697 "extrd,s %1,%3+%2-1,%2,%0"
6698 [(set_attr "type" "shift")
6699 (set_attr "length" "4")])
6702 [(set (match_operand:DI 0 "register_operand" "=r")
6703 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
6705 (match_operand:DI 2 "register_operand" "q")))]
6707 "extrd,s %1,%%sar,1,%0"
6708 [(set_attr "type" "shift")
6709 (set_attr "length" "4")])
6711 ;; Only specify the mode operands 0, the rest are assumed to be word_mode.
6712 (define_expand "insv"
6713 [(set (zero_extract (match_operand 0 "register_operand" "")
6714 (match_operand 1 "uint32_operand" "")
6715 (match_operand 2 "uint32_operand" ""))
6716 (match_operand 3 "arith5_operand" ""))]
6721 emit_insn (gen_insv_64 (operands[0], operands[1],
6722 operands[2], operands[3]));
6724 emit_insn (gen_insv_32 (operands[0], operands[1],
6725 operands[2], operands[3]));
6729 (define_insn "insv_32"
6730 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
6731 (match_operand:SI 1 "uint5_operand" "")
6732 (match_operand:SI 2 "uint5_operand" ""))
6733 (match_operand:SI 3 "arith5_operand" "r,L"))]
6736 {dep|depw} %3,%2+%1-1,%1,%0
6737 {depi|depwi} %3,%2+%1-1,%1,%0"
6738 [(set_attr "type" "shift,shift")
6739 (set_attr "length" "4,4")])
6741 ;; Optimize insertion of const_int values of type 1...1xxxx.
6743 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
6744 (match_operand:SI 1 "uint5_operand" "")
6745 (match_operand:SI 2 "uint5_operand" ""))
6746 (match_operand:SI 3 "const_int_operand" ""))]
6747 "(INTVAL (operands[3]) & 0x10) != 0 &&
6748 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
6751 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
6752 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
6754 [(set_attr "type" "shift")
6755 (set_attr "length" "4")])
6757 (define_insn "insv_64"
6758 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
6759 (match_operand:DI 1 "uint32_operand" "")
6760 (match_operand:DI 2 "uint32_operand" ""))
6761 (match_operand:DI 3 "arith32_operand" "r,L"))]
6764 depd %3,%2+%1-1,%1,%0
6765 depdi %3,%2+%1-1,%1,%0"
6766 [(set_attr "type" "shift,shift")
6767 (set_attr "length" "4,4")])
6769 ;; Optimize insertion of const_int values of type 1...1xxxx.
6771 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
6772 (match_operand:DI 1 "uint32_operand" "")
6773 (match_operand:DI 2 "uint32_operand" ""))
6774 (match_operand:DI 3 "const_int_operand" ""))]
6775 "(INTVAL (operands[3]) & 0x10) != 0
6777 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
6780 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
6781 return \"depdi %3,%2+%1-1,%1,%0\";
6783 [(set_attr "type" "shift")
6784 (set_attr "length" "4")])
6787 [(set (match_operand:DI 0 "register_operand" "=r")
6788 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
6791 "depd,z %1,31,32,%0"
6792 [(set_attr "type" "shift")
6793 (set_attr "length" "4")])
6795 ;; This insn is used for some loop tests, typically loops reversed when
6796 ;; strength reduction is used. It is actually created when the instruction
6797 ;; combination phase combines the special loop test. Since this insn
6798 ;; is both a jump insn and has an output, it must deal with its own
6799 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
6800 ;; to not choose the register alternatives in the event a reload is needed.
6801 (define_insn "decrement_and_branch_until_zero"
6804 (match_operator 2 "comparison_operator"
6806 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
6807 (match_operand:SI 1 "int5_operand" "L,L,L"))
6809 (label_ref (match_operand 3 "" ""))
6812 (plus:SI (match_dup 0) (match_dup 1)))
6813 (clobber (match_scratch:SI 4 "=X,r,r"))]
6815 "* return output_dbra (operands, insn, which_alternative); "
6816 ;; Do not expect to understand this the first time through.
6817 [(set_attr "type" "cbranch,multi,multi")
6818 (set (attr "length")
6819 (if_then_else (eq_attr "alternative" "0")
6820 ;; Loop counter in register case
6821 ;; Short branch has length of 4
6822 ;; Long branch has length of 8
6823 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6828 ;; Loop counter in FP reg case.
6829 ;; Extra goo to deal with additional reload insns.
6830 (if_then_else (eq_attr "alternative" "1")
6831 (if_then_else (lt (match_dup 3) (pc))
6833 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
6838 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6842 ;; Loop counter in memory case.
6843 ;; Extra goo to deal with additional reload insns.
6844 (if_then_else (lt (match_dup 3) (pc))
6846 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6851 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6854 (const_int 16))))))])
6859 (match_operator 2 "movb_comparison_operator"
6860 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
6861 (label_ref (match_operand 3 "" ""))
6863 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
6866 "* return output_movb (operands, insn, which_alternative, 0); "
6867 ;; Do not expect to understand this the first time through.
6868 [(set_attr "type" "cbranch,multi,multi,multi")
6869 (set (attr "length")
6870 (if_then_else (eq_attr "alternative" "0")
6871 ;; Loop counter in register case
6872 ;; Short branch has length of 4
6873 ;; Long branch has length of 8
6874 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6879 ;; Loop counter in FP reg case.
6880 ;; Extra goo to deal with additional reload insns.
6881 (if_then_else (eq_attr "alternative" "1")
6882 (if_then_else (lt (match_dup 3) (pc))
6884 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6889 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6893 ;; Loop counter in memory or sar case.
6894 ;; Extra goo to deal with additional reload insns.
6896 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6899 (const_int 12)))))])
6901 ;; Handle negated branch.
6905 (match_operator 2 "movb_comparison_operator"
6906 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
6908 (label_ref (match_operand 3 "" ""))))
6909 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
6912 "* return output_movb (operands, insn, which_alternative, 1); "
6913 ;; Do not expect to understand this the first time through.
6914 [(set_attr "type" "cbranch,multi,multi,multi")
6915 (set (attr "length")
6916 (if_then_else (eq_attr "alternative" "0")
6917 ;; Loop counter in register case
6918 ;; Short branch has length of 4
6919 ;; Long branch has length of 8
6920 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6925 ;; Loop counter in FP reg case.
6926 ;; Extra goo to deal with additional reload insns.
6927 (if_then_else (eq_attr "alternative" "1")
6928 (if_then_else (lt (match_dup 3) (pc))
6930 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6935 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6939 ;; Loop counter in memory or SAR case.
6940 ;; Extra goo to deal with additional reload insns.
6942 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6945 (const_int 12)))))])
6948 [(set (pc) (label_ref (match_operand 3 "" "" )))
6949 (set (match_operand:SI 0 "ireg_operand" "=r")
6950 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
6951 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
6952 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
6955 return output_parallel_addb (operands, get_attr_length (insn));
6957 [(set_attr "type" "parallel_branch")
6958 (set (attr "length")
6959 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6965 [(set (pc) (label_ref (match_operand 2 "" "" )))
6966 (set (match_operand:SF 0 "ireg_operand" "=r")
6967 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
6971 return output_parallel_movb (operands, get_attr_length (insn));
6973 [(set_attr "type" "parallel_branch")
6974 (set (attr "length")
6975 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6981 [(set (pc) (label_ref (match_operand 2 "" "" )))
6982 (set (match_operand:SI 0 "ireg_operand" "=r")
6983 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
6987 return output_parallel_movb (operands, get_attr_length (insn));
6989 [(set_attr "type" "parallel_branch")
6990 (set (attr "length")
6991 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6997 [(set (pc) (label_ref (match_operand 2 "" "" )))
6998 (set (match_operand:HI 0 "ireg_operand" "=r")
6999 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
7003 return output_parallel_movb (operands, get_attr_length (insn));
7005 [(set_attr "type" "parallel_branch")
7006 (set (attr "length")
7007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7013 [(set (pc) (label_ref (match_operand 2 "" "" )))
7014 (set (match_operand:QI 0 "ireg_operand" "=r")
7015 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
7019 return output_parallel_movb (operands, get_attr_length (insn));
7021 [(set_attr "type" "parallel_branch")
7022 (set (attr "length")
7023 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7029 [(set (match_operand 0 "register_operand" "=f")
7030 (mult (match_operand 1 "register_operand" "f")
7031 (match_operand 2 "register_operand" "f")))
7032 (set (match_operand 3 "register_operand" "+f")
7033 (plus (match_operand 4 "register_operand" "f")
7034 (match_operand 5 "register_operand" "f")))]
7035 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7036 && reload_completed && fmpyaddoperands (operands)"
7039 if (GET_MODE (operands[0]) == DFmode)
7041 if (rtx_equal_p (operands[3], operands[5]))
7042 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
7044 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
7048 if (rtx_equal_p (operands[3], operands[5]))
7049 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
7051 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
7054 [(set_attr "type" "fpalu")
7055 (set_attr "length" "4")])
7058 [(set (match_operand 3 "register_operand" "+f")
7059 (plus (match_operand 4 "register_operand" "f")
7060 (match_operand 5 "register_operand" "f")))
7061 (set (match_operand 0 "register_operand" "=f")
7062 (mult (match_operand 1 "register_operand" "f")
7063 (match_operand 2 "register_operand" "f")))]
7064 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7065 && reload_completed && fmpyaddoperands (operands)"
7068 if (GET_MODE (operands[0]) == DFmode)
7070 if (rtx_equal_p (operands[3], operands[5]))
7071 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
7073 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
7077 if (rtx_equal_p (operands[3], operands[5]))
7078 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
7080 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
7083 [(set_attr "type" "fpalu")
7084 (set_attr "length" "4")])
7087 [(set (match_operand 0 "register_operand" "=f")
7088 (mult (match_operand 1 "register_operand" "f")
7089 (match_operand 2 "register_operand" "f")))
7090 (set (match_operand 3 "register_operand" "+f")
7091 (minus (match_operand 4 "register_operand" "f")
7092 (match_operand 5 "register_operand" "f")))]
7093 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7094 && reload_completed && fmpysuboperands (operands)"
7097 if (GET_MODE (operands[0]) == DFmode)
7098 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
7100 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
7102 [(set_attr "type" "fpalu")
7103 (set_attr "length" "4")])
7106 [(set (match_operand 3 "register_operand" "+f")
7107 (minus (match_operand 4 "register_operand" "f")
7108 (match_operand 5 "register_operand" "f")))
7109 (set (match_operand 0 "register_operand" "=f")
7110 (mult (match_operand 1 "register_operand" "f")
7111 (match_operand 2 "register_operand" "f")))]
7112 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7113 && reload_completed && fmpysuboperands (operands)"
7116 if (GET_MODE (operands[0]) == DFmode)
7117 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
7119 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
7121 [(set_attr "type" "fpalu")
7122 (set_attr "length" "4")])
7124 ;; Clean up turds left by reload.
7126 [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "")
7127 (match_operand 1 "register_operand" "fr"))
7128 (set (match_operand 2 "register_operand" "fr")
7130 "! TARGET_SOFT_FLOAT
7131 && GET_CODE (operands[0]) == MEM
7132 && ! MEM_VOLATILE_P (operands[0])
7133 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7134 && GET_MODE (operands[0]) == GET_MODE (operands[2])
7135 && GET_MODE (operands[0]) == DFmode
7136 && GET_CODE (operands[1]) == REG
7137 && GET_CODE (operands[2]) == REG
7138 && ! side_effects_p (XEXP (operands[0], 0))
7139 && REGNO_REG_CLASS (REGNO (operands[1]))
7140 == REGNO_REG_CLASS (REGNO (operands[2]))"
7145 if (FP_REG_P (operands[1]))
7146 output_asm_insn (output_fp_move_double (operands), operands);
7148 output_asm_insn (output_move_double (operands), operands);
7150 if (rtx_equal_p (operands[1], operands[2]))
7153 xoperands[0] = operands[2];
7154 xoperands[1] = operands[1];
7156 if (FP_REG_P (xoperands[1]))
7157 output_asm_insn (output_fp_move_double (xoperands), xoperands);
7159 output_asm_insn (output_move_double (xoperands), xoperands);
7165 [(set (match_operand 0 "register_operand" "fr")
7166 (match_operand 1 "reg_or_nonsymb_mem_operand" ""))
7167 (set (match_operand 2 "register_operand" "fr")
7169 "! TARGET_SOFT_FLOAT
7170 && GET_CODE (operands[1]) == MEM
7171 && ! MEM_VOLATILE_P (operands[1])
7172 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7173 && GET_MODE (operands[0]) == GET_MODE (operands[2])
7174 && GET_MODE (operands[0]) == DFmode
7175 && GET_CODE (operands[0]) == REG
7176 && GET_CODE (operands[2]) == REG
7177 && ! side_effects_p (XEXP (operands[1], 0))
7178 && REGNO_REG_CLASS (REGNO (operands[0]))
7179 == REGNO_REG_CLASS (REGNO (operands[2]))"
7184 if (FP_REG_P (operands[0]))
7185 output_asm_insn (output_fp_move_double (operands), operands);
7187 output_asm_insn (output_move_double (operands), operands);
7189 xoperands[0] = operands[2];
7190 xoperands[1] = operands[0];
7192 if (FP_REG_P (xoperands[1]))
7193 output_asm_insn (output_fp_move_double (xoperands), xoperands);
7195 output_asm_insn (output_move_double (xoperands), xoperands);
7200 ;; Flush the I and D cache line found at the address in operand 0.
7201 ;; This is used by the trampoline code for nested functions.
7202 ;; So long as the trampoline itself is less than 32 bytes this
7205 (define_insn "dcacheflush"
7206 [(unspec_volatile [(const_int 1)] 0)
7207 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7208 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))]
7210 "fdc 0(%0)\;fdc 0(%1)\;sync"
7211 [(set_attr "type" "multi")
7212 (set_attr "length" "12")])
7214 (define_insn "icacheflush"
7215 [(unspec_volatile [(const_int 2)] 0)
7216 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7217 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))
7218 (use (match_operand 2 "pmode_register_operand" "r"))
7219 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
7220 (clobber (match_operand 4 "pmode_register_operand" "=&r"))]
7222 "mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
7223 [(set_attr "type" "multi")
7224 (set_attr "length" "52")])
7226 ;; An out-of-line prologue.
7227 (define_insn "outline_prologue_call"
7228 [(unspec_volatile [(const_int 0)] 0)
7229 (clobber (reg:SI 31))
7230 (clobber (reg:SI 22))
7231 (clobber (reg:SI 21))
7232 (clobber (reg:SI 20))
7233 (clobber (reg:SI 19))
7234 (clobber (reg:SI 1))]
7238 extern int frame_pointer_needed;
7240 /* We need two different versions depending on whether or not we
7241 need a frame pointer. Also note that we return to the instruction
7242 immediately after the branch rather than two instructions after the
7243 break as normally is the case. */
7244 if (frame_pointer_needed)
7246 /* Must import the magic millicode routine(s). */
7247 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
7249 if (TARGET_PORTABLE_RUNTIME)
7251 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
7252 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
7256 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
7260 /* Must import the magic millicode routine(s). */
7261 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
7263 if (TARGET_PORTABLE_RUNTIME)
7265 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
7266 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
7269 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
7273 [(set_attr "type" "multi")
7274 (set_attr "length" "8")])
7276 ;; An out-of-line epilogue.
7277 (define_insn "outline_epilogue_call"
7278 [(unspec_volatile [(const_int 1)] 0)
7281 (clobber (reg:SI 31))
7282 (clobber (reg:SI 22))
7283 (clobber (reg:SI 21))
7284 (clobber (reg:SI 20))
7285 (clobber (reg:SI 19))
7286 (clobber (reg:SI 2))
7287 (clobber (reg:SI 1))]
7291 extern int frame_pointer_needed;
7293 /* We need two different versions depending on whether or not we
7294 need a frame pointer. Also note that we return to the instruction
7295 immediately after the branch rather than two instructions after the
7296 break as normally is the case. */
7297 if (frame_pointer_needed)
7299 /* Must import the magic millicode routine. */
7300 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
7302 /* The out-of-line prologue will make sure we return to the right
7304 if (TARGET_PORTABLE_RUNTIME)
7306 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
7307 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
7311 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
7315 /* Must import the magic millicode routine. */
7316 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
7318 /* The out-of-line prologue will make sure we return to the right
7320 if (TARGET_PORTABLE_RUNTIME)
7322 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
7323 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
7326 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
7330 [(set_attr "type" "multi")
7331 (set_attr "length" "8")])
7333 ;; Given a function pointer, canonicalize it so it can be
7334 ;; reliably compared to another function pointer. */
7335 (define_expand "canonicalize_funcptr_for_compare"
7336 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
7337 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7338 (clobber (match_dup 2))
7339 (clobber (reg:SI 26))
7340 (clobber (reg:SI 22))
7341 (clobber (reg:SI 31))])
7342 (set (match_operand:SI 0 "register_operand" "")
7344 "! TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && !TARGET_ELF32"
7347 operands[2] = gen_reg_rtx (SImode);
7348 if (GET_CODE (operands[1]) != REG)
7350 rtx tmp = gen_reg_rtx (Pmode);
7351 emit_move_insn (tmp, operands[1]);
7357 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7358 (clobber (match_operand:SI 0 "register_operand" "=a"))
7359 (clobber (reg:SI 26))
7360 (clobber (reg:SI 22))
7361 (clobber (reg:SI 31))]
7365 /* Must import the magic millicode routine. */
7366 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
7368 /* This is absolutely amazing.
7370 First, copy our input parameter into %r29 just in case we don't
7371 need to call $$sh_func_adrs. */
7372 output_asm_insn (\"copy %%r26,%%r29\", NULL);
7374 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
7375 we use %r26 unchanged. */
7376 if (get_attr_length (insn) == 32)
7377 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+24\", NULL);
7378 else if (get_attr_length (insn) == 40)
7379 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+32\", NULL);
7380 else if (get_attr_length (insn) == 44)
7381 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+36\", NULL);
7383 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+20\", NULL);
7385 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
7386 4096, then we use %r26 unchanged. */
7387 if (get_attr_length (insn) == 32)
7388 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+16\",
7390 else if (get_attr_length (insn) == 40)
7391 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+24\",
7393 else if (get_attr_length (insn) == 44)
7394 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+28\",
7397 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+12\",
7400 /* Else call $$sh_func_adrs to extract the function's real add24. */
7401 return output_millicode_call (insn,
7402 gen_rtx_SYMBOL_REF (SImode,
7403 \"$$sh_func_adrs\"));
7405 [(set_attr "type" "multi")
7406 (set (attr "length")
7408 ;; Target (or stub) within reach
7409 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
7411 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
7416 (ne (symbol_ref "flag_pic")
7420 ;; Out of reach PORTABLE_RUNTIME
7421 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
7425 ;; Out of reach, can use ble
7428 ;; On the PA, the PIC register is call clobbered, so it must
7429 ;; be saved & restored around calls by the caller. If the call
7430 ;; doesn't return normally (nonlocal goto, or an exception is
7431 ;; thrown), then the code at the exception handler label must
7432 ;; restore the PIC register.
7433 (define_expand "exception_receiver"
7438 /* Restore the PIC register using hppa_pic_save_rtx (). The
7439 PIC register is not saved in the frame in 64-bit ABI. */
7440 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
7444 (define_expand "builtin_setjmp_receiver"
7445 [(label_ref (match_operand 0 "" ""))]
7449 /* Restore the PIC register. Hopefully, this will always be from
7450 a stack slot. The only registers that are valid after a
7451 builtin_longjmp are the stack and frame pointers. */
7452 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());