1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by the Center for Software Science at the University
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Uses of UNSPEC in this file:
32 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
33 (UNSPEC_GOTO 1) ; indirect_goto
34 (UNSPEC_DLTIND14R 2) ;
43 (UNSPEC_TLSLDM_PIC 11)
50 [(UNSPECV_BLOCKAGE 0) ; blockage
51 (UNSPECV_DCACHE 1) ; dcacheflush
52 (UNSPECV_ICACHE 2) ; icacheflush
53 (UNSPECV_OPC 3) ; outline_prologue_call
54 (UNSPECV_OEC 4) ; outline_epilogue_call
55 (UNSPECV_LONGJMP 5) ; builtin_longjmp
58 ;; Maximum pc-relative branch offsets.
60 ;; These numbers are a bit smaller than the maximum allowable offsets
61 ;; so that a few instructions may be inserted before the actual branch.
64 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
65 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
68 ;; Mode and code iterators
70 ;; This mode iterator allows :P to be used for patterns that operate on
71 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
72 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
74 ;; This attribute defines the condition prefix for word and double word
75 ;; add, compare, subtract and logical instructions.
76 (define_mode_attr dwc [(SI "") (DI "*")])
78 ;; Insn type. Used to default other attribute values.
80 ;; type "unary" insns have one input operand (1) and one output operand (0)
81 ;; type "binary" insns have two input operands (1,2) and one output (0)
84 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
85 (const_string "binary"))
87 (define_attr "pa_combine_type"
88 "fmpy,faddsub,uncond_branch,addmove,none"
89 (const_string "none"))
91 ;; Processor type (for scheduling, not code generation) -- this attribute
92 ;; must exactly match the processor_type enumeration in pa.h.
94 ;; FIXME: Add 800 scheduling for completeness?
96 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
98 ;; Length (in # of bytes).
99 (define_attr "length" ""
100 (cond [(eq_attr "type" "load,fpload")
101 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
102 (const_int 8) (const_int 4))
104 (eq_attr "type" "store,fpstore")
105 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
106 (const_int 8) (const_int 4))
108 (eq_attr "type" "binary,shift,nullshift")
109 (if_then_else (match_operand 2 "arith_operand" "")
110 (const_int 4) (const_int 12))
112 (eq_attr "type" "move,unary,shift,nullshift")
113 (if_then_else (match_operand 1 "arith_operand" "")
114 (const_int 4) (const_int 8))]
118 (define_asm_attributes
119 [(set_attr "length" "4")
120 (set_attr "type" "multi")])
122 ;; Attributes for instruction and branch scheduling
124 ;; For conditional branches.
125 (define_attr "in_branch_delay" "false,true"
126 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
127 (eq_attr "length" "4"))
128 (const_string "true")
129 (const_string "false")))
131 ;; Disallow instructions which use the FPU since they will tie up the FPU
132 ;; even if the instruction is nullified.
133 (define_attr "in_nullified_branch_delay" "false,true"
134 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
135 (eq_attr "length" "4"))
136 (const_string "true")
137 (const_string "false")))
139 ;; For calls and millicode calls. Allow unconditional branches in the
141 (define_attr "in_call_delay" "false,true"
142 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
143 (eq_attr "length" "4"))
144 (const_string "true")
145 (eq_attr "type" "uncond_branch")
146 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
148 (const_string "true")
149 (const_string "false"))]
150 (const_string "false")))
153 ;; Call delay slot description.
154 (define_delay (eq_attr "type" "call")
155 [(eq_attr "in_call_delay" "true") (nil) (nil)])
157 ;; Millicode call delay slot description.
158 (define_delay (eq_attr "type" "milli")
159 [(eq_attr "in_call_delay" "true") (nil) (nil)])
161 ;; Return and other similar instructions.
162 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
163 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
165 ;; Floating point conditional branch delay slot description.
166 (define_delay (eq_attr "type" "fbranch")
167 [(eq_attr "in_branch_delay" "true")
168 (eq_attr "in_nullified_branch_delay" "true")
171 ;; Integer conditional branch delay slot description.
172 ;; Nullification of conditional branches on the PA is dependent on the
173 ;; direction of the branch. Forward branches nullify true and
174 ;; backward branches nullify false. If the direction is unknown
175 ;; then nullification is not allowed.
176 (define_delay (eq_attr "type" "cbranch")
177 [(eq_attr "in_branch_delay" "true")
178 (and (eq_attr "in_nullified_branch_delay" "true")
179 (attr_flag "forward"))
180 (and (eq_attr "in_nullified_branch_delay" "true")
181 (attr_flag "backward"))])
183 (define_delay (and (eq_attr "type" "uncond_branch")
184 (eq (symbol_ref "following_call (insn)")
186 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
188 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
189 ;; load: 2, fpload: 3
190 ;; store, fpstore: 3, no D-cache operations should be scheduled.
192 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
194 ;; Instruction Time Unit Minimum Distance (unit contention)
201 ;; fmpyadd 3 ALU,MPY 2
202 ;; fmpysub 3 ALU,MPY 2
203 ;; fmpycfxt 3 ALU,MPY 2
206 ;; fdiv,sgl 10 MPY 10
207 ;; fdiv,dbl 12 MPY 12
208 ;; fsqrt,sgl 14 MPY 14
209 ;; fsqrt,dbl 18 MPY 18
211 ;; We don't model fmpyadd/fmpysub properly as those instructions
212 ;; keep both the FP ALU and MPY units busy. Given that these
213 ;; processors are obsolete, I'm not going to spend the time to
214 ;; model those instructions correctly.
216 (define_automaton "pa700")
217 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
219 (define_insn_reservation "W0" 4
220 (and (eq_attr "type" "fpcc")
221 (eq_attr "cpu" "700"))
224 (define_insn_reservation "W1" 3
225 (and (eq_attr "type" "fpalu")
226 (eq_attr "cpu" "700"))
229 (define_insn_reservation "W2" 3
230 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
231 (eq_attr "cpu" "700"))
234 (define_insn_reservation "W3" 10
235 (and (eq_attr "type" "fpdivsgl")
236 (eq_attr "cpu" "700"))
239 (define_insn_reservation "W4" 12
240 (and (eq_attr "type" "fpdivdbl")
241 (eq_attr "cpu" "700"))
244 (define_insn_reservation "W5" 14
245 (and (eq_attr "type" "fpsqrtsgl")
246 (eq_attr "cpu" "700"))
249 (define_insn_reservation "W6" 18
250 (and (eq_attr "type" "fpsqrtdbl")
251 (eq_attr "cpu" "700"))
254 (define_insn_reservation "W7" 2
255 (and (eq_attr "type" "load")
256 (eq_attr "cpu" "700"))
259 (define_insn_reservation "W8" 2
260 (and (eq_attr "type" "fpload")
261 (eq_attr "cpu" "700"))
264 (define_insn_reservation "W9" 3
265 (and (eq_attr "type" "store")
266 (eq_attr "cpu" "700"))
269 (define_insn_reservation "W10" 3
270 (and (eq_attr "type" "fpstore")
271 (eq_attr "cpu" "700"))
274 (define_insn_reservation "W11" 5
275 (and (eq_attr "type" "fpstore_load")
276 (eq_attr "cpu" "700"))
279 (define_insn_reservation "W12" 6
280 (and (eq_attr "type" "store_fpload")
281 (eq_attr "cpu" "700"))
284 (define_insn_reservation "W13" 1
285 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
286 (eq_attr "cpu" "700"))
289 ;; We have a bypass for all computations in the FP unit which feed an
290 ;; FP store as long as the sizes are the same.
291 (define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
292 (define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
293 (define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
294 (define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
295 (define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
297 ;; We have an "anti-bypass" for FP loads which feed an FP store.
298 (define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
300 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
301 ;; floating point computations with non-floating point computations (fp loads
302 ;; and stores are not fp computations).
304 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
305 ;; take two cycles, during which no Dcache operations should be scheduled.
306 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
307 ;; all have the same memory characteristics if one disregards cache misses.
309 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
310 ;; There's no value in modeling the ALU and MUL separately though
311 ;; since there can never be a functional unit conflict given the
312 ;; latency and issue rates for those units.
315 ;; Instruction Time Unit Minimum Distance (unit contention)
322 ;; fmpyadd 2 ALU,MPY 1
323 ;; fmpysub 2 ALU,MPY 1
324 ;; fmpycfxt 2 ALU,MPY 1
328 ;; fdiv,dbl 15 DIV 15
330 ;; fsqrt,dbl 15 DIV 15
332 (define_automaton "pa7100")
333 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
335 (define_insn_reservation "X0" 2
336 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
337 (eq_attr "cpu" "7100"))
340 (define_insn_reservation "X1" 8
341 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
342 (eq_attr "cpu" "7100"))
343 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
345 (define_insn_reservation "X2" 15
346 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
347 (eq_attr "cpu" "7100"))
348 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
350 (define_insn_reservation "X3" 2
351 (and (eq_attr "type" "load")
352 (eq_attr "cpu" "7100"))
355 (define_insn_reservation "X4" 2
356 (and (eq_attr "type" "fpload")
357 (eq_attr "cpu" "7100"))
360 (define_insn_reservation "X5" 2
361 (and (eq_attr "type" "store")
362 (eq_attr "cpu" "7100"))
363 "i_7100+mem_7100,mem_7100")
365 (define_insn_reservation "X6" 2
366 (and (eq_attr "type" "fpstore")
367 (eq_attr "cpu" "7100"))
368 "i_7100+mem_7100,mem_7100")
370 (define_insn_reservation "X7" 4
371 (and (eq_attr "type" "fpstore_load")
372 (eq_attr "cpu" "7100"))
373 "i_7100+mem_7100,mem_7100*3")
375 (define_insn_reservation "X8" 4
376 (and (eq_attr "type" "store_fpload")
377 (eq_attr "cpu" "7100"))
378 "i_7100+mem_7100,mem_7100*3")
380 (define_insn_reservation "X9" 1
381 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
382 (eq_attr "cpu" "7100"))
385 ;; We have a bypass for all computations in the FP unit which feed an
386 ;; FP store as long as the sizes are the same.
387 (define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
388 (define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
389 (define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
391 ;; We have an "anti-bypass" for FP loads which feed an FP store.
392 (define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
394 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
395 ;; There's no value in modeling the ALU and MUL separately though
396 ;; since there can never be a functional unit conflict that
397 ;; can be avoided given the latency, issue rates and mandatory
398 ;; one cycle cpu-wide lock for a double precision fp multiply.
401 ;; Instruction Time Unit Minimum Distance (unit contention)
408 ;; fmpyadd,sgl 2 ALU,MPY 1
409 ;; fmpyadd,dbl 3 ALU,MPY 2
410 ;; fmpysub,sgl 2 ALU,MPY 1
411 ;; fmpysub,dbl 3 ALU,MPY 2
412 ;; fmpycfxt,sgl 2 ALU,MPY 1
413 ;; fmpycfxt,dbl 3 ALU,MPY 2
418 ;; fdiv,dbl 15 DIV 15
420 ;; fsqrt,dbl 15 DIV 15
422 ;; The PA7200 is just like the PA7100LC except that there is
423 ;; no store-store penalty.
425 ;; The PA7300 is just like the PA7200 except that there is
426 ;; no store-load penalty.
428 ;; Note there are some aspects of the 7100LC we are not modeling
429 ;; at the moment. I'll be reviewing the 7100LC scheduling info
430 ;; shortly and updating this description.
434 ;; other issue modeling
436 (define_automaton "pa7100lc")
437 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
438 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
439 (define_cpu_unit "mem_7100lc" "pa7100lc")
441 ;; Double precision multiplies lock the entire CPU for one
442 ;; cycle. There is no way to avoid this lock and trying to
443 ;; schedule around the lock is pointless and thus there is no
444 ;; value in trying to model this lock.
446 ;; Not modeling the lock allows us to treat fp multiplies just
447 ;; like any other FP alu instruction. It allows for a smaller
448 ;; DFA and may reduce register pressure.
449 (define_insn_reservation "Y0" 2
450 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
451 (eq_attr "cpu" "7100LC,7200,7300"))
452 "f_7100lc,fpmac_7100lc")
454 ;; fp division and sqrt instructions lock the entire CPU for
455 ;; 7 cycles (single precision) or 14 cycles (double precision).
456 ;; There is no way to avoid this lock and trying to schedule
457 ;; around the lock is pointless and thus there is no value in
458 ;; trying to model this lock. Not modeling the lock allows
459 ;; for a smaller DFA and may reduce register pressure.
460 (define_insn_reservation "Y1" 1
461 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
462 (eq_attr "cpu" "7100LC,7200,7300"))
465 (define_insn_reservation "Y2" 2
466 (and (eq_attr "type" "load")
467 (eq_attr "cpu" "7100LC,7200,7300"))
468 "i1_7100lc+mem_7100lc")
470 (define_insn_reservation "Y3" 2
471 (and (eq_attr "type" "fpload")
472 (eq_attr "cpu" "7100LC,7200,7300"))
473 "i1_7100lc+mem_7100lc")
475 (define_insn_reservation "Y4" 2
476 (and (eq_attr "type" "store")
477 (eq_attr "cpu" "7100LC"))
478 "i1_7100lc+mem_7100lc,mem_7100lc")
480 (define_insn_reservation "Y5" 2
481 (and (eq_attr "type" "fpstore")
482 (eq_attr "cpu" "7100LC"))
483 "i1_7100lc+mem_7100lc,mem_7100lc")
485 (define_insn_reservation "Y6" 4
486 (and (eq_attr "type" "fpstore_load")
487 (eq_attr "cpu" "7100LC"))
488 "i1_7100lc+mem_7100lc,mem_7100lc*3")
490 (define_insn_reservation "Y7" 4
491 (and (eq_attr "type" "store_fpload")
492 (eq_attr "cpu" "7100LC"))
493 "i1_7100lc+mem_7100lc,mem_7100lc*3")
495 (define_insn_reservation "Y8" 1
496 (and (eq_attr "type" "shift,nullshift")
497 (eq_attr "cpu" "7100LC,7200,7300"))
500 (define_insn_reservation "Y9" 1
501 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
502 (eq_attr "cpu" "7100LC,7200,7300"))
503 "(i0_7100lc|i1_7100lc)")
505 ;; The 7200 has a store-load penalty
506 (define_insn_reservation "Y10" 2
507 (and (eq_attr "type" "store")
508 (eq_attr "cpu" "7200"))
509 "i1_7100lc,mem_7100lc")
511 (define_insn_reservation "Y11" 2
512 (and (eq_attr "type" "fpstore")
513 (eq_attr "cpu" "7200"))
514 "i1_7100lc,mem_7100lc")
516 (define_insn_reservation "Y12" 4
517 (and (eq_attr "type" "fpstore_load")
518 (eq_attr "cpu" "7200"))
519 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
521 (define_insn_reservation "Y13" 4
522 (and (eq_attr "type" "store_fpload")
523 (eq_attr "cpu" "7200"))
524 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
526 ;; The 7300 has no penalty for store-store or store-load
527 (define_insn_reservation "Y14" 2
528 (and (eq_attr "type" "store")
529 (eq_attr "cpu" "7300"))
532 (define_insn_reservation "Y15" 2
533 (and (eq_attr "type" "fpstore")
534 (eq_attr "cpu" "7300"))
537 (define_insn_reservation "Y16" 4
538 (and (eq_attr "type" "fpstore_load")
539 (eq_attr "cpu" "7300"))
540 "i1_7100lc,i1_7100lc+mem_7100lc")
542 (define_insn_reservation "Y17" 4
543 (and (eq_attr "type" "store_fpload")
544 (eq_attr "cpu" "7300"))
545 "i1_7100lc,i1_7100lc+mem_7100lc")
547 ;; We have an "anti-bypass" for FP loads which feed an FP store.
548 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
550 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
551 ;; traditional architecture.
553 ;; The PA8000 has a large (56) entry reorder buffer that is split between
554 ;; memory and non-memory operations.
556 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
557 ;; the function units, with the exception of branches and multi-output
558 ;; instructions. The PA8000 can retire two non-memory operations per cycle
559 ;; and two memory operations per cycle, only one of which may be a store.
561 ;; Given the large reorder buffer, the processor can hide most latencies.
562 ;; According to HP, they've got the best results by scheduling for retirement
563 ;; bandwidth with limited latency scheduling for floating point operations.
564 ;; Latency for integer operations and memory references is ignored.
567 ;; We claim floating point operations have a 2 cycle latency and are
568 ;; fully pipelined, except for div and sqrt which are not pipelined and
569 ;; take from 17 to 31 cycles to complete.
571 ;; It's worth noting that there is no way to saturate all the functional
572 ;; units on the PA8000 as there is not enough issue bandwidth.
574 (define_automaton "pa8000")
575 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
576 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
577 (define_cpu_unit "store_8000" "pa8000")
578 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
579 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
580 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
581 (define_reservation "im_8000" "im0_8000 | im1_8000")
582 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
583 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
584 (define_reservation "f_8000" "f0_8000 | f1_8000")
585 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
587 ;; We can issue any two memops per cycle, but we can only retire
588 ;; one memory store per cycle. We assume that the reorder buffer
589 ;; will hide any memory latencies per HP's recommendation.
590 (define_insn_reservation "Z0" 0
592 (eq_attr "type" "load,fpload")
593 (eq_attr "cpu" "8000"))
596 (define_insn_reservation "Z1" 0
598 (eq_attr "type" "store,fpstore")
599 (eq_attr "cpu" "8000"))
600 "im_8000,rm_8000+store_8000")
602 (define_insn_reservation "Z2" 0
603 (and (eq_attr "type" "fpstore_load,store_fpload")
604 (eq_attr "cpu" "8000"))
605 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
607 ;; We can issue and retire two non-memory operations per cycle with
608 ;; a few exceptions (branches). This group catches those we want
609 ;; to assume have zero latency.
610 (define_insn_reservation "Z3" 0
612 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
613 (eq_attr "cpu" "8000"))
616 ;; Branches use both slots in the non-memory issue and
618 (define_insn_reservation "Z4" 0
620 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
621 (eq_attr "cpu" "8000"))
622 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
624 ;; We partial latency schedule the floating point units.
625 ;; They can issue/retire two at a time in the non-memory
626 ;; units. We fix their latency at 2 cycles and they
627 ;; are fully pipelined.
628 (define_insn_reservation "Z5" 1
630 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
631 (eq_attr "cpu" "8000"))
632 "inm_8000,f_8000,rnm_8000")
634 ;; The fdivsqrt units are not pipelined and have a very long latency.
635 ;; To keep the DFA from exploding, we do not show all the
636 ;; reservations for the divsqrt unit.
637 (define_insn_reservation "Z6" 17
639 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
640 (eq_attr "cpu" "8000"))
641 "inm_8000,fdivsqrt_8000*6,rnm_8000")
643 (define_insn_reservation "Z7" 31
645 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
646 (eq_attr "cpu" "8000"))
647 "inm_8000,fdivsqrt_8000*6,rnm_8000")
649 ;; Operand and operator predicates and constraints
651 (include "predicates.md")
652 (include "constraints.md")
654 ;; Compare instructions.
655 ;; This controls RTL generation and register allocation.
659 (match_operator:CCFP 2 "comparison_operator"
660 [(match_operand:SF 0 "reg_or_0_operand" "fG")
661 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
662 "! TARGET_SOFT_FLOAT"
663 "fcmp,sgl,%Y2 %f0,%f1"
664 [(set_attr "length" "4")
665 (set_attr "type" "fpcc")])
669 (match_operator:CCFP 2 "comparison_operator"
670 [(match_operand:DF 0 "reg_or_0_operand" "fG")
671 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
672 "! TARGET_SOFT_FLOAT"
673 "fcmp,dbl,%Y2 %f0,%f1"
674 [(set_attr "length" "4")
675 (set_attr "type" "fpcc")])
677 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
678 ;; placeholders. This is necessary in rare situations when a
679 ;; placeholder is re-emitted (see PR 8705).
681 (define_expand "movccfp"
683 (match_operand 0 "const_int_operand" ""))]
684 "! TARGET_SOFT_FLOAT"
687 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
691 ;; The following patterns are optimization placeholders. In almost
692 ;; all cases, the user of the condition code will be simplified and the
693 ;; original condition code setting insn should be eliminated.
695 (define_insn "*movccfp0"
698 "! TARGET_SOFT_FLOAT"
699 "fcmp,dbl,= %%fr0,%%fr0"
700 [(set_attr "length" "4")
701 (set_attr "type" "fpcc")])
703 (define_insn "*movccfp1"
706 "! TARGET_SOFT_FLOAT"
707 "fcmp,dbl,!= %%fr0,%%fr0"
708 [(set_attr "length" "4")
709 (set_attr "type" "fpcc")])
713 (define_expand "cstoresi4"
714 [(set (match_operand:SI 0 "register_operand")
715 (match_operator:SI 1 "ordered_comparison_operator"
716 [(match_operand:SI 2 "reg_or_0_operand" "")
717 (match_operand:SI 3 "arith5_operand" "")]))]
721 ;; Instruction canonicalization puts immediate operands second, which
722 ;; is the reverse of what we want.
725 [(set (match_operand:SI 0 "register_operand" "=r")
726 (match_operator:SI 3 "comparison_operator"
727 [(match_operand:SI 1 "register_operand" "r")
728 (match_operand:SI 2 "arith11_operand" "rI")]))]
730 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
731 [(set_attr "type" "binary")
732 (set_attr "length" "8")])
735 [(set (match_operand:DI 0 "register_operand" "=r")
736 (match_operator:DI 3 "comparison_operator"
737 [(match_operand:DI 1 "register_operand" "r")
738 (match_operand:DI 2 "arith11_operand" "rI")]))]
740 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
741 [(set_attr "type" "binary")
742 (set_attr "length" "8")])
744 (define_insn "iorscc"
745 [(set (match_operand:SI 0 "register_operand" "=r")
746 (ior:SI (match_operator:SI 3 "comparison_operator"
747 [(match_operand:SI 1 "register_operand" "r")
748 (match_operand:SI 2 "arith11_operand" "rI")])
749 (match_operator:SI 6 "comparison_operator"
750 [(match_operand:SI 4 "register_operand" "r")
751 (match_operand:SI 5 "arith11_operand" "rI")])))]
753 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
754 [(set_attr "type" "binary")
755 (set_attr "length" "12")])
758 [(set (match_operand:DI 0 "register_operand" "=r")
759 (ior:DI (match_operator:DI 3 "comparison_operator"
760 [(match_operand:DI 1 "register_operand" "r")
761 (match_operand:DI 2 "arith11_operand" "rI")])
762 (match_operator:DI 6 "comparison_operator"
763 [(match_operand:DI 4 "register_operand" "r")
764 (match_operand:DI 5 "arith11_operand" "rI")])))]
766 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
767 [(set_attr "type" "binary")
768 (set_attr "length" "12")])
770 ;; Combiner patterns for common operations performed with the output
771 ;; from an scc insn (negscc and incscc).
772 (define_insn "negscc"
773 [(set (match_operand:SI 0 "register_operand" "=r")
774 (neg:SI (match_operator:SI 3 "comparison_operator"
775 [(match_operand:SI 1 "register_operand" "r")
776 (match_operand:SI 2 "arith11_operand" "rI")])))]
778 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
779 [(set_attr "type" "binary")
780 (set_attr "length" "8")])
783 [(set (match_operand:DI 0 "register_operand" "=r")
784 (neg:DI (match_operator:DI 3 "comparison_operator"
785 [(match_operand:DI 1 "register_operand" "r")
786 (match_operand:DI 2 "arith11_operand" "rI")])))]
788 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
789 [(set_attr "type" "binary")
790 (set_attr "length" "8")])
792 ;; Patterns for adding/subtracting the result of a boolean expression from
793 ;; a register. First we have special patterns that make use of the carry
794 ;; bit, and output only two instructions. For the cases we can't in
795 ;; general do in two instructions, the incscc pattern at the end outputs
796 ;; two or three instructions.
799 [(set (match_operand:SI 0 "register_operand" "=r")
800 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
801 (match_operand:SI 3 "arith11_operand" "rI"))
802 (match_operand:SI 1 "register_operand" "r")))]
804 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
805 [(set_attr "type" "binary")
806 (set_attr "length" "8")])
809 [(set (match_operand:DI 0 "register_operand" "=r")
810 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
811 (match_operand:DI 3 "arith11_operand" "rI"))
812 (match_operand:DI 1 "register_operand" "r")))]
814 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
815 [(set_attr "type" "binary")
816 (set_attr "length" "8")])
818 ; This need only accept registers for op3, since canonicalization
819 ; replaces geu with gtu when op3 is an integer.
821 [(set (match_operand:SI 0 "register_operand" "=r")
822 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
823 (match_operand:SI 3 "register_operand" "r"))
824 (match_operand:SI 1 "register_operand" "r")))]
826 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
827 [(set_attr "type" "binary")
828 (set_attr "length" "8")])
831 [(set (match_operand:DI 0 "register_operand" "=r")
832 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
833 (match_operand:DI 3 "register_operand" "r"))
834 (match_operand:DI 1 "register_operand" "r")))]
836 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
837 [(set_attr "type" "binary")
838 (set_attr "length" "8")])
840 ; Match only integers for op3 here. This is used as canonical form of the
841 ; geu pattern when op3 is an integer. Don't match registers since we can't
842 ; make better code than the general incscc pattern.
844 [(set (match_operand:SI 0 "register_operand" "=r")
845 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
846 (match_operand:SI 3 "int11_operand" "I"))
847 (match_operand:SI 1 "register_operand" "r")))]
849 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
850 [(set_attr "type" "binary")
851 (set_attr "length" "8")])
854 [(set (match_operand:DI 0 "register_operand" "=r")
855 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
856 (match_operand:DI 3 "int11_operand" "I"))
857 (match_operand:DI 1 "register_operand" "r")))]
859 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
863 (define_insn "incscc"
864 [(set (match_operand:SI 0 "register_operand" "=r,r")
865 (plus:SI (match_operator:SI 4 "comparison_operator"
866 [(match_operand:SI 2 "register_operand" "r,r")
867 (match_operand:SI 3 "arith11_operand" "rI,rI")])
868 (match_operand:SI 1 "register_operand" "0,?r")))]
871 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
872 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
873 [(set_attr "type" "binary,binary")
874 (set_attr "length" "8,12")])
877 [(set (match_operand:DI 0 "register_operand" "=r,r")
878 (plus:DI (match_operator:DI 4 "comparison_operator"
879 [(match_operand:DI 2 "register_operand" "r,r")
880 (match_operand:DI 3 "arith11_operand" "rI,rI")])
881 (match_operand:DI 1 "register_operand" "0,?r")))]
884 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
885 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
886 [(set_attr "type" "binary,binary")
887 (set_attr "length" "8,12")])
890 [(set (match_operand:SI 0 "register_operand" "=r")
891 (minus:SI (match_operand:SI 1 "register_operand" "r")
892 (gtu:SI (match_operand:SI 2 "register_operand" "r")
893 (match_operand:SI 3 "arith11_operand" "rI"))))]
895 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
900 [(set (match_operand:DI 0 "register_operand" "=r")
901 (minus:DI (match_operand:DI 1 "register_operand" "r")
902 (gtu:DI (match_operand:DI 2 "register_operand" "r")
903 (match_operand:DI 3 "arith11_operand" "rI"))))]
905 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
906 [(set_attr "type" "binary")
907 (set_attr "length" "8")])
910 [(set (match_operand:SI 0 "register_operand" "=r")
911 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
912 (gtu:SI (match_operand:SI 2 "register_operand" "r")
913 (match_operand:SI 3 "arith11_operand" "rI")))
914 (match_operand:SI 4 "register_operand" "r")))]
916 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
917 [(set_attr "type" "binary")
918 (set_attr "length" "8")])
921 [(set (match_operand:DI 0 "register_operand" "=r")
922 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
923 (gtu:DI (match_operand:DI 2 "register_operand" "r")
924 (match_operand:DI 3 "arith11_operand" "rI")))
925 (match_operand:DI 4 "register_operand" "r")))]
927 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
928 [(set_attr "type" "binary")
929 (set_attr "length" "8")])
931 ; This need only accept registers for op3, since canonicalization
932 ; replaces ltu with leu when op3 is an integer.
934 [(set (match_operand:SI 0 "register_operand" "=r")
935 (minus:SI (match_operand:SI 1 "register_operand" "r")
936 (ltu:SI (match_operand:SI 2 "register_operand" "r")
937 (match_operand:SI 3 "register_operand" "r"))))]
939 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
940 [(set_attr "type" "binary")
941 (set_attr "length" "8")])
944 [(set (match_operand:DI 0 "register_operand" "=r")
945 (minus:DI (match_operand:DI 1 "register_operand" "r")
946 (ltu:DI (match_operand:DI 2 "register_operand" "r")
947 (match_operand:DI 3 "register_operand" "r"))))]
949 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
950 [(set_attr "type" "binary")
951 (set_attr "length" "8")])
954 [(set (match_operand:SI 0 "register_operand" "=r")
955 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
956 (ltu:SI (match_operand:SI 2 "register_operand" "r")
957 (match_operand:SI 3 "register_operand" "r")))
958 (match_operand:SI 4 "register_operand" "r")))]
960 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
961 [(set_attr "type" "binary")
962 (set_attr "length" "8")])
965 [(set (match_operand:DI 0 "register_operand" "=r")
966 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
967 (ltu:DI (match_operand:DI 2 "register_operand" "r")
968 (match_operand:DI 3 "register_operand" "r")))
969 (match_operand:DI 4 "register_operand" "r")))]
971 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
972 [(set_attr "type" "binary")
973 (set_attr "length" "8")])
975 ; Match only integers for op3 here. This is used as canonical form of the
976 ; ltu pattern when op3 is an integer. Don't match registers since we can't
977 ; make better code than the general incscc pattern.
979 [(set (match_operand:SI 0 "register_operand" "=r")
980 (minus:SI (match_operand:SI 1 "register_operand" "r")
981 (leu:SI (match_operand:SI 2 "register_operand" "r")
982 (match_operand:SI 3 "int11_operand" "I"))))]
984 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
985 [(set_attr "type" "binary")
986 (set_attr "length" "8")])
989 [(set (match_operand:DI 0 "register_operand" "=r")
990 (minus:DI (match_operand:DI 1 "register_operand" "r")
991 (leu:DI (match_operand:DI 2 "register_operand" "r")
992 (match_operand:DI 3 "int11_operand" "I"))))]
994 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
995 [(set_attr "type" "binary")
996 (set_attr "length" "8")])
999 [(set (match_operand:SI 0 "register_operand" "=r")
1000 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1001 (leu:SI (match_operand:SI 2 "register_operand" "r")
1002 (match_operand:SI 3 "int11_operand" "I")))
1003 (match_operand:SI 4 "register_operand" "r")))]
1005 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1006 [(set_attr "type" "binary")
1007 (set_attr "length" "8")])
1010 [(set (match_operand:DI 0 "register_operand" "=r")
1011 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1012 (leu:DI (match_operand:DI 2 "register_operand" "r")
1013 (match_operand:DI 3 "int11_operand" "I")))
1014 (match_operand:DI 4 "register_operand" "r")))]
1016 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1017 [(set_attr "type" "binary")
1018 (set_attr "length" "8")])
1020 (define_insn "decscc"
1021 [(set (match_operand:SI 0 "register_operand" "=r,r")
1022 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1023 (match_operator:SI 4 "comparison_operator"
1024 [(match_operand:SI 2 "register_operand" "r,r")
1025 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1028 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1029 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1030 [(set_attr "type" "binary,binary")
1031 (set_attr "length" "8,12")])
1034 [(set (match_operand:DI 0 "register_operand" "=r,r")
1035 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1036 (match_operator:DI 4 "comparison_operator"
1037 [(match_operand:DI 2 "register_operand" "r,r")
1038 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1041 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1042 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1043 [(set_attr "type" "binary,binary")
1044 (set_attr "length" "8,12")])
1046 ; Patterns for max and min. (There is no need for an earlyclobber in the
1047 ; last alternative since the middle alternative will match if op0 == op1.)
1049 (define_insn "sminsi3"
1050 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1051 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1052 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1055 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1056 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1057 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1058 [(set_attr "type" "multi,multi,multi")
1059 (set_attr "length" "8,8,8")])
1061 (define_insn "smindi3"
1062 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1063 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1064 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1067 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1068 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1069 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1070 [(set_attr "type" "multi,multi,multi")
1071 (set_attr "length" "8,8,8")])
1073 (define_insn "uminsi3"
1074 [(set (match_operand:SI 0 "register_operand" "=r,r")
1075 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1076 (match_operand:SI 2 "arith11_operand" "r,I")))]
1079 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1080 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1081 [(set_attr "type" "multi,multi")
1082 (set_attr "length" "8,8")])
1084 (define_insn "umindi3"
1085 [(set (match_operand:DI 0 "register_operand" "=r,r")
1086 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1087 (match_operand:DI 2 "arith11_operand" "r,I")))]
1090 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1091 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1092 [(set_attr "type" "multi,multi")
1093 (set_attr "length" "8,8")])
1095 (define_insn "smaxsi3"
1096 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1097 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1098 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1101 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1102 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1103 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1104 [(set_attr "type" "multi,multi,multi")
1105 (set_attr "length" "8,8,8")])
1107 (define_insn "smaxdi3"
1108 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1109 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1110 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1113 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1114 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1115 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1116 [(set_attr "type" "multi,multi,multi")
1117 (set_attr "length" "8,8,8")])
1119 (define_insn "umaxsi3"
1120 [(set (match_operand:SI 0 "register_operand" "=r,r")
1121 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1122 (match_operand:SI 2 "arith11_operand" "r,I")))]
1125 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1126 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1127 [(set_attr "type" "multi,multi")
1128 (set_attr "length" "8,8")])
1130 (define_insn "umaxdi3"
1131 [(set (match_operand:DI 0 "register_operand" "=r,r")
1132 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1133 (match_operand:DI 2 "arith11_operand" "r,I")))]
1136 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1137 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1138 [(set_attr "type" "multi,multi")
1139 (set_attr "length" "8,8")])
1141 (define_insn "abssi2"
1142 [(set (match_operand:SI 0 "register_operand" "=r")
1143 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1145 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1146 [(set_attr "type" "multi")
1147 (set_attr "length" "8")])
1149 (define_insn "absdi2"
1150 [(set (match_operand:DI 0 "register_operand" "=r")
1151 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1153 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1154 [(set_attr "type" "multi")
1155 (set_attr "length" "8")])
1157 ;;; Experimental conditional move patterns
1159 (define_expand "movsicc"
1160 [(set (match_operand:SI 0 "register_operand" "")
1162 (match_operand 1 "comparison_operator" "")
1163 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1164 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1168 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1169 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1173 ;; We used to accept any register for op1.
1175 ;; However, it loses sometimes because the compiler will end up using
1176 ;; different registers for op0 and op1 in some critical cases. local-alloc
1177 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1179 ;; If/when global register allocation supports tying we should allow any
1180 ;; register for op1 again.
1182 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1184 (match_operator 2 "comparison_operator"
1185 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1186 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1187 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1191 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1192 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1193 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1194 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1195 [(set_attr "type" "multi,multi,multi,nullshift")
1196 (set_attr "length" "8,8,8,8")])
1199 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1201 (match_operator 5 "comparison_operator"
1202 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1203 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1204 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1205 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1208 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1209 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1210 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1211 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1212 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1213 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1214 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1215 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1216 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1217 (set_attr "length" "8,8,8,8,8,8,8,8")])
1219 (define_expand "movdicc"
1220 [(set (match_operand:DI 0 "register_operand" "")
1222 (match_operand 1 "comparison_operator" "")
1223 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1224 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1228 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1229 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1233 ; We need the first constraint alternative in order to avoid
1234 ; earlyclobbers on all other alternatives.
1236 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1238 (match_operator 2 "comparison_operator"
1239 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1240 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1241 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1245 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1246 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1247 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1248 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1249 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1250 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1251 (set_attr "length" "8,8,8,8,8")])
1254 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1256 (match_operator 5 "comparison_operator"
1257 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1258 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1259 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1260 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1263 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1264 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1265 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1266 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1267 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1268 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1269 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1270 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1271 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1272 (set_attr "length" "8,8,8,8,8,8,8,8")])
1274 ;; Conditional Branches
1276 (define_expand "cbranchdi4"
1278 (if_then_else (match_operator 0 "ordered_comparison_operator"
1279 [(match_operand:DI 1 "reg_or_0_operand" "")
1280 (match_operand:DI 2 "register_operand" "")])
1281 (label_ref (match_operand 3 "" ""))
1286 (define_expand "cbranchsi4"
1288 (if_then_else (match_operator 0 "ordered_comparison_operator"
1289 [(match_operand:SI 1 "reg_or_0_operand" "")
1290 (match_operand:SI 2 "arith5_operand" "")])
1291 (label_ref (match_operand 3 "" ""))
1296 (define_expand "cbranchsf4"
1298 (if_then_else (match_operator 0 "comparison_operator"
1299 [(match_operand:SF 1 "reg_or_0_operand" "")
1300 (match_operand:SF 2 "reg_or_0_operand" "")])
1301 (label_ref (match_operand 3 "" ""))
1306 emit_bcond_fp (operands);
1311 (define_expand "cbranchdf4"
1313 (if_then_else (match_operator 0 "comparison_operator"
1314 [(match_operand:DF 1 "reg_or_0_operand" "")
1315 (match_operand:DF 2 "reg_or_0_operand" "")])
1316 (label_ref (match_operand 3 "" ""))
1321 emit_bcond_fp (operands);
1325 ;; Match the branch patterns.
1328 ;; Note a long backward conditional branch with an annulled delay slot
1329 ;; has a length of 12.
1333 (match_operator 3 "comparison_operator"
1334 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1335 (match_operand:SI 2 "arith5_operand" "rL")])
1336 (label_ref (match_operand 0 "" ""))
1341 return output_cbranch (operands, 0, insn);
1343 [(set_attr "type" "cbranch")
1344 (set (attr "length")
1345 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1346 (const_int MAX_12BIT_OFFSET))
1348 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1349 (const_int MAX_17BIT_OFFSET))
1351 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1353 (eq (symbol_ref "flag_pic") (const_int 0))
1357 ;; Match the negated branch.
1362 (match_operator 3 "comparison_operator"
1363 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1364 (match_operand:SI 2 "arith5_operand" "rL")])
1366 (label_ref (match_operand 0 "" ""))))]
1370 return output_cbranch (operands, 1, insn);
1372 [(set_attr "type" "cbranch")
1373 (set (attr "length")
1374 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1375 (const_int MAX_12BIT_OFFSET))
1377 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1378 (const_int MAX_17BIT_OFFSET))
1380 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1382 (eq (symbol_ref "flag_pic") (const_int 0))
1389 (match_operator 3 "comparison_operator"
1390 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1391 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1392 (label_ref (match_operand 0 "" ""))
1397 return output_cbranch (operands, 0, insn);
1399 [(set_attr "type" "cbranch")
1400 (set (attr "length")
1401 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1402 (const_int MAX_12BIT_OFFSET))
1404 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1405 (const_int MAX_17BIT_OFFSET))
1407 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1409 (eq (symbol_ref "flag_pic") (const_int 0))
1413 ;; Match the negated branch.
1418 (match_operator 3 "comparison_operator"
1419 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1420 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1422 (label_ref (match_operand 0 "" ""))))]
1426 return output_cbranch (operands, 1, insn);
1428 [(set_attr "type" "cbranch")
1429 (set (attr "length")
1430 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1431 (const_int MAX_12BIT_OFFSET))
1433 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1434 (const_int MAX_17BIT_OFFSET))
1436 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1438 (eq (symbol_ref "flag_pic") (const_int 0))
1444 (match_operator 3 "cmpib_comparison_operator"
1445 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1446 (match_operand:DI 2 "arith5_operand" "rL")])
1447 (label_ref (match_operand 0 "" ""))
1452 return output_cbranch (operands, 0, insn);
1454 [(set_attr "type" "cbranch")
1455 (set (attr "length")
1456 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1457 (const_int MAX_12BIT_OFFSET))
1459 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1460 (const_int MAX_17BIT_OFFSET))
1462 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1464 (eq (symbol_ref "flag_pic") (const_int 0))
1468 ;; Match the negated branch.
1473 (match_operator 3 "cmpib_comparison_operator"
1474 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1475 (match_operand:DI 2 "arith5_operand" "rL")])
1477 (label_ref (match_operand 0 "" ""))))]
1481 return output_cbranch (operands, 1, insn);
1483 [(set_attr "type" "cbranch")
1484 (set (attr "length")
1485 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1486 (const_int MAX_12BIT_OFFSET))
1488 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1489 (const_int MAX_17BIT_OFFSET))
1491 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1493 (eq (symbol_ref "flag_pic") (const_int 0))
1497 ;; Branch on Bit patterns.
1501 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1503 (match_operand:SI 1 "uint5_operand" ""))
1505 (label_ref (match_operand 2 "" ""))
1510 return output_bb (operands, 0, insn, 0);
1512 [(set_attr "type" "cbranch")
1513 (set (attr "length")
1514 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1515 (const_int MAX_12BIT_OFFSET))
1517 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1518 (const_int MAX_17BIT_OFFSET))
1520 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1522 (eq (symbol_ref "flag_pic") (const_int 0))
1529 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1531 (match_operand:DI 1 "uint32_operand" ""))
1533 (label_ref (match_operand 2 "" ""))
1538 return output_bb (operands, 0, insn, 0);
1540 [(set_attr "type" "cbranch")
1541 (set (attr "length")
1542 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1543 (const_int MAX_12BIT_OFFSET))
1545 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1546 (const_int MAX_17BIT_OFFSET))
1548 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1550 (eq (symbol_ref "flag_pic") (const_int 0))
1557 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1559 (match_operand:SI 1 "uint5_operand" ""))
1562 (label_ref (match_operand 2 "" ""))))]
1566 return output_bb (operands, 1, insn, 0);
1568 [(set_attr "type" "cbranch")
1569 (set (attr "length")
1570 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1571 (const_int MAX_12BIT_OFFSET))
1573 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1574 (const_int MAX_17BIT_OFFSET))
1576 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1578 (eq (symbol_ref "flag_pic") (const_int 0))
1585 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1587 (match_operand:DI 1 "uint32_operand" ""))
1590 (label_ref (match_operand 2 "" ""))))]
1594 return output_bb (operands, 1, insn, 0);
1596 [(set_attr "type" "cbranch")
1597 (set (attr "length")
1598 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1599 (const_int MAX_12BIT_OFFSET))
1601 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1602 (const_int MAX_17BIT_OFFSET))
1604 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1606 (eq (symbol_ref "flag_pic") (const_int 0))
1613 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1615 (match_operand:SI 1 "uint5_operand" ""))
1617 (label_ref (match_operand 2 "" ""))
1622 return output_bb (operands, 0, insn, 1);
1624 [(set_attr "type" "cbranch")
1625 (set (attr "length")
1626 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1627 (const_int MAX_12BIT_OFFSET))
1629 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1630 (const_int MAX_17BIT_OFFSET))
1632 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1634 (eq (symbol_ref "flag_pic") (const_int 0))
1641 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1643 (match_operand:DI 1 "uint32_operand" ""))
1645 (label_ref (match_operand 2 "" ""))
1650 return output_bb (operands, 0, insn, 1);
1652 [(set_attr "type" "cbranch")
1653 (set (attr "length")
1654 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1655 (const_int MAX_12BIT_OFFSET))
1657 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1658 (const_int MAX_17BIT_OFFSET))
1660 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1662 (eq (symbol_ref "flag_pic") (const_int 0))
1669 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1671 (match_operand:SI 1 "uint5_operand" ""))
1674 (label_ref (match_operand 2 "" ""))))]
1678 return output_bb (operands, 1, insn, 1);
1680 [(set_attr "type" "cbranch")
1681 (set (attr "length")
1682 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1683 (const_int MAX_12BIT_OFFSET))
1685 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1686 (const_int MAX_17BIT_OFFSET))
1688 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1690 (eq (symbol_ref "flag_pic") (const_int 0))
1697 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1699 (match_operand:DI 1 "uint32_operand" ""))
1702 (label_ref (match_operand 2 "" ""))))]
1706 return output_bb (operands, 1, insn, 1);
1708 [(set_attr "type" "cbranch")
1709 (set (attr "length")
1710 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1711 (const_int MAX_12BIT_OFFSET))
1713 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1714 (const_int MAX_17BIT_OFFSET))
1716 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1718 (eq (symbol_ref "flag_pic") (const_int 0))
1722 ;; Branch on Variable Bit patterns.
1726 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1728 (match_operand:SI 1 "register_operand" "q"))
1730 (label_ref (match_operand 2 "" ""))
1735 return output_bvb (operands, 0, insn, 0);
1737 [(set_attr "type" "cbranch")
1738 (set (attr "length")
1739 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1740 (const_int MAX_12BIT_OFFSET))
1742 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1743 (const_int MAX_17BIT_OFFSET))
1745 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1747 (eq (symbol_ref "flag_pic") (const_int 0))
1754 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1756 (match_operand:DI 1 "register_operand" "q"))
1758 (label_ref (match_operand 2 "" ""))
1763 return output_bvb (operands, 0, insn, 0);
1765 [(set_attr "type" "cbranch")
1766 (set (attr "length")
1767 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1768 (const_int MAX_12BIT_OFFSET))
1770 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1771 (const_int MAX_17BIT_OFFSET))
1773 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1775 (eq (symbol_ref "flag_pic") (const_int 0))
1782 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1784 (match_operand:SI 1 "register_operand" "q"))
1787 (label_ref (match_operand 2 "" ""))))]
1791 return output_bvb (operands, 1, insn, 0);
1793 [(set_attr "type" "cbranch")
1794 (set (attr "length")
1795 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1796 (const_int MAX_12BIT_OFFSET))
1798 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1799 (const_int MAX_17BIT_OFFSET))
1801 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1810 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1812 (match_operand:DI 1 "register_operand" "q"))
1815 (label_ref (match_operand 2 "" ""))))]
1819 return output_bvb (operands, 1, insn, 0);
1821 [(set_attr "type" "cbranch")
1822 (set (attr "length")
1823 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1824 (const_int MAX_12BIT_OFFSET))
1826 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1827 (const_int MAX_17BIT_OFFSET))
1829 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1838 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1840 (match_operand:SI 1 "register_operand" "q"))
1842 (label_ref (match_operand 2 "" ""))
1847 return output_bvb (operands, 0, insn, 1);
1849 [(set_attr "type" "cbranch")
1850 (set (attr "length")
1851 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1852 (const_int MAX_12BIT_OFFSET))
1854 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1855 (const_int MAX_17BIT_OFFSET))
1857 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1859 (eq (symbol_ref "flag_pic") (const_int 0))
1866 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1868 (match_operand:DI 1 "register_operand" "q"))
1870 (label_ref (match_operand 2 "" ""))
1875 return output_bvb (operands, 0, insn, 1);
1877 [(set_attr "type" "cbranch")
1878 (set (attr "length")
1879 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1880 (const_int MAX_12BIT_OFFSET))
1882 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (const_int MAX_17BIT_OFFSET))
1885 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1887 (eq (symbol_ref "flag_pic") (const_int 0))
1894 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1896 (match_operand:SI 1 "register_operand" "q"))
1899 (label_ref (match_operand 2 "" ""))))]
1903 return output_bvb (operands, 1, insn, 1);
1905 [(set_attr "type" "cbranch")
1906 (set (attr "length")
1907 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1908 (const_int MAX_12BIT_OFFSET))
1910 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1911 (const_int MAX_17BIT_OFFSET))
1913 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1915 (eq (symbol_ref "flag_pic") (const_int 0))
1922 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1924 (match_operand:DI 1 "register_operand" "q"))
1927 (label_ref (match_operand 2 "" ""))))]
1931 return output_bvb (operands, 1, insn, 1);
1933 [(set_attr "type" "cbranch")
1934 (set (attr "length")
1935 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1936 (const_int MAX_12BIT_OFFSET))
1938 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1939 (const_int MAX_17BIT_OFFSET))
1941 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1943 (eq (symbol_ref "flag_pic") (const_int 0))
1947 ;; Floating point branches
1949 ;; ??? Nullification is handled differently from other branches.
1950 ;; If nullification is specified, the delay slot is nullified on any
1951 ;; taken branch regardless of branch direction.
1953 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1954 (label_ref (match_operand 0 "" ""))
1956 "!TARGET_SOFT_FLOAT"
1959 int length = get_attr_length (insn);
1961 int nullify, xdelay;
1964 return \"ftest\;b%* %l0\";
1966 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
1970 xoperands[0] = GEN_INT (length - 8);
1976 xoperands[0] = GEN_INT (length - 4);
1980 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
1982 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
1983 return output_lbranch (operands[0], insn, xdelay);
1985 [(set_attr "type" "fbranch")
1986 (set (attr "length")
1987 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1988 (const_int MAX_17BIT_OFFSET))
1990 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1992 (eq (symbol_ref "flag_pic") (const_int 0))
1997 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1999 (label_ref (match_operand 0 "" ""))))]
2000 "!TARGET_SOFT_FLOAT"
2003 int length = get_attr_length (insn);
2005 int nullify, xdelay;
2008 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2010 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2014 xoperands[0] = GEN_INT (length - 4);
2020 xoperands[0] = GEN_INT (length);
2024 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2026 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2027 return output_lbranch (operands[0], insn, xdelay);
2029 [(set_attr "type" "fbranch")
2030 (set (attr "length")
2031 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2032 (const_int MAX_17BIT_OFFSET))
2034 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2036 (eq (symbol_ref "flag_pic") (const_int 0))
2040 ;; Move instructions
2042 (define_expand "movsi"
2043 [(set (match_operand:SI 0 "general_operand" "")
2044 (match_operand:SI 1 "general_operand" ""))]
2048 if (emit_move_sequence (operands, SImode, 0))
2052 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2053 (define_expand "reload_insi_r1"
2054 [(set (match_operand:SI 0 "register_operand" "=Z")
2055 (match_operand:SI 1 "non_hard_reg_operand" ""))
2056 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2060 if (emit_move_sequence (operands, SImode, operands[2]))
2063 /* We don't want the clobber emitted, so handle this ourselves. */
2064 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2068 ;; Handle SImode input reloads requiring a general register as a
2069 ;; scratch register.
2070 (define_expand "reload_insi"
2071 [(set (match_operand:SI 0 "register_operand" "=Z")
2072 (match_operand:SI 1 "non_hard_reg_operand" ""))
2073 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2077 if (emit_move_sequence (operands, SImode, operands[2]))
2080 /* We don't want the clobber emitted, so handle this ourselves. */
2081 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2085 ;; Handle SImode output reloads requiring a general register as a
2086 ;; scratch register.
2087 (define_expand "reload_outsi"
2088 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2089 (match_operand:SI 1 "register_operand" "Z"))
2090 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2094 if (emit_move_sequence (operands, SImode, operands[2]))
2097 /* We don't want the clobber emitted, so handle this ourselves. */
2098 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2103 [(set (match_operand:SI 0 "move_dest_operand"
2104 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2105 (match_operand:SI 1 "move_src_operand"
2106 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2107 "(register_operand (operands[0], SImode)
2108 || reg_or_0_operand (operands[1], SImode))
2109 && !TARGET_SOFT_FLOAT
2116 {zdepi|depwi,z} %Z1,%0
2120 {mfctl|mfctl,w} %%sar,%0
2124 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2125 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2126 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2127 (set_attr "pa_combine_type" "addmove")
2128 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2131 [(set (match_operand:SI 0 "move_dest_operand"
2132 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2133 (match_operand:SI 1 "move_src_operand"
2134 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2135 "(register_operand (operands[0], SImode)
2136 || reg_or_0_operand (operands[1], SImode))
2137 && !TARGET_SOFT_FLOAT
2144 {zdepi|depwi,z} %Z1,%0
2148 {mfctl|mfctl,w} %%sar,%0
2152 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2153 (set_attr "pa_combine_type" "addmove")
2154 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2157 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2158 (match_operand:SI 1 "register_operand" "f"))]
2160 && !TARGET_DISABLE_INDEXING
2161 && reload_completed"
2163 [(set_attr "type" "fpstore")
2164 (set_attr "pa_combine_type" "addmove")
2165 (set_attr "length" "4")])
2167 ; Rewrite RTL using an indexed store. This will allow the insn that
2168 ; computes the address to be deleted if the register it sets is dead.
2170 [(set (match_operand:SI 0 "register_operand" "")
2171 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2173 (match_operand:SI 2 "register_operand" "")))
2174 (set (mem:SI (match_dup 0))
2175 (match_operand:SI 3 "register_operand" ""))]
2177 && !TARGET_DISABLE_INDEXING
2178 && REG_OK_FOR_BASE_P (operands[2])
2179 && FP_REGNO_P (REGNO (operands[3]))"
2180 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2182 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2187 [(set (match_operand:SI 0 "register_operand" "")
2188 (plus:SI (match_operand:SI 2 "register_operand" "")
2189 (mult:SI (match_operand:SI 1 "register_operand" "")
2191 (set (mem:SI (match_dup 0))
2192 (match_operand:SI 3 "register_operand" ""))]
2194 && !TARGET_DISABLE_INDEXING
2195 && REG_OK_FOR_BASE_P (operands[2])
2196 && FP_REGNO_P (REGNO (operands[3]))"
2197 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2199 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2204 [(set (match_operand:DI 0 "register_operand" "")
2205 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2207 (match_operand:DI 2 "register_operand" "")))
2208 (set (mem:SI (match_dup 0))
2209 (match_operand:SI 3 "register_operand" ""))]
2211 && !TARGET_DISABLE_INDEXING
2213 && REG_OK_FOR_BASE_P (operands[2])
2214 && FP_REGNO_P (REGNO (operands[3]))"
2215 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2217 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2222 [(set (match_operand:DI 0 "register_operand" "")
2223 (plus:DI (match_operand:DI 2 "register_operand" "")
2224 (mult:DI (match_operand:DI 1 "register_operand" "")
2226 (set (mem:SI (match_dup 0))
2227 (match_operand:SI 3 "register_operand" ""))]
2229 && !TARGET_DISABLE_INDEXING
2231 && REG_OK_FOR_BASE_P (operands[2])
2232 && FP_REGNO_P (REGNO (operands[3]))"
2233 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2235 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2240 [(set (match_operand:SI 0 "register_operand" "")
2241 (plus:SI (match_operand:SI 1 "register_operand" "")
2242 (match_operand:SI 2 "register_operand" "")))
2243 (set (mem:SI (match_dup 0))
2244 (match_operand:SI 3 "register_operand" ""))]
2246 && !TARGET_DISABLE_INDEXING
2247 && TARGET_NO_SPACE_REGS
2248 && REG_OK_FOR_INDEX_P (operands[1])
2249 && REG_OK_FOR_BASE_P (operands[2])
2250 && FP_REGNO_P (REGNO (operands[3]))"
2251 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2253 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2257 [(set (match_operand:SI 0 "register_operand" "")
2258 (plus:SI (match_operand:SI 1 "register_operand" "")
2259 (match_operand:SI 2 "register_operand" "")))
2260 (set (mem:SI (match_dup 0))
2261 (match_operand:SI 3 "register_operand" ""))]
2263 && !TARGET_DISABLE_INDEXING
2264 && TARGET_NO_SPACE_REGS
2265 && REG_OK_FOR_BASE_P (operands[1])
2266 && REG_OK_FOR_INDEX_P (operands[2])
2267 && FP_REGNO_P (REGNO (operands[3]))"
2268 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2270 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2274 [(set (match_operand:DI 0 "register_operand" "")
2275 (plus:DI (match_operand:DI 1 "register_operand" "")
2276 (match_operand:DI 2 "register_operand" "")))
2277 (set (mem:SI (match_dup 0))
2278 (match_operand:SI 3 "register_operand" ""))]
2280 && !TARGET_DISABLE_INDEXING
2282 && TARGET_NO_SPACE_REGS
2283 && REG_OK_FOR_INDEX_P (operands[1])
2284 && REG_OK_FOR_BASE_P (operands[2])
2285 && FP_REGNO_P (REGNO (operands[3]))"
2286 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2288 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2292 [(set (match_operand:DI 0 "register_operand" "")
2293 (plus:DI (match_operand:DI 1 "register_operand" "")
2294 (match_operand:DI 2 "register_operand" "")))
2295 (set (mem:SI (match_dup 0))
2296 (match_operand:SI 3 "register_operand" ""))]
2298 && !TARGET_DISABLE_INDEXING
2300 && TARGET_NO_SPACE_REGS
2301 && REG_OK_FOR_BASE_P (operands[1])
2302 && REG_OK_FOR_INDEX_P (operands[2])
2303 && FP_REGNO_P (REGNO (operands[3]))"
2304 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2306 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2310 [(set (match_operand:SI 0 "move_dest_operand"
2311 "=r,r,r,r,r,r,Q,!*q,!r")
2312 (match_operand:SI 1 "move_src_operand"
2313 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2314 "(register_operand (operands[0], SImode)
2315 || reg_or_0_operand (operands[1], SImode))
2316 && TARGET_SOFT_FLOAT"
2322 {zdepi|depwi,z} %Z1,%0
2326 {mfctl|mfctl,w} %%sar,%0"
2327 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2328 (set_attr "pa_combine_type" "addmove")
2329 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2331 ;; Load or store with base-register modification.
2333 [(set (match_operand:SI 0 "register_operand" "=r")
2334 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2335 (match_operand:DI 2 "int5_operand" "L"))))
2337 (plus:DI (match_dup 1) (match_dup 2)))]
2340 [(set_attr "type" "load")
2341 (set_attr "length" "4")])
2343 ; And a zero extended variant.
2345 [(set (match_operand:DI 0 "register_operand" "=r")
2346 (zero_extend:DI (mem:SI
2348 (match_operand:DI 1 "register_operand" "+r")
2349 (match_operand:DI 2 "int5_operand" "L")))))
2351 (plus:DI (match_dup 1) (match_dup 2)))]
2354 [(set_attr "type" "load")
2355 (set_attr "length" "4")])
2357 (define_expand "pre_load"
2358 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2359 (mem (plus (match_operand 1 "register_operand" "")
2360 (match_operand 2 "pre_cint_operand" ""))))
2362 (plus (match_dup 1) (match_dup 2)))])]
2368 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2371 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2375 (define_insn "pre_ldw"
2376 [(set (match_operand:SI 0 "register_operand" "=r")
2377 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2378 (match_operand:SI 2 "pre_cint_operand" ""))))
2380 (plus:SI (match_dup 1) (match_dup 2)))]
2384 if (INTVAL (operands[2]) < 0)
2385 return \"{ldwm|ldw,mb} %2(%1),%0\";
2386 return \"{ldws|ldw},mb %2(%1),%0\";
2388 [(set_attr "type" "load")
2389 (set_attr "length" "4")])
2391 (define_insn "pre_ldd"
2392 [(set (match_operand:DI 0 "register_operand" "=r")
2393 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2394 (match_operand:DI 2 "pre_cint_operand" ""))))
2396 (plus:DI (match_dup 1) (match_dup 2)))]
2399 [(set_attr "type" "load")
2400 (set_attr "length" "4")])
2403 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2404 (match_operand:SI 1 "pre_cint_operand" "")))
2405 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2407 (plus:SI (match_dup 0) (match_dup 1)))]
2411 if (INTVAL (operands[1]) < 0)
2412 return \"{stwm|stw,mb} %r2,%1(%0)\";
2413 return \"{stws|stw},mb %r2,%1(%0)\";
2415 [(set_attr "type" "store")
2416 (set_attr "length" "4")])
2419 [(set (match_operand:SI 0 "register_operand" "=r")
2420 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2422 (plus:SI (match_dup 1)
2423 (match_operand:SI 2 "post_cint_operand" "")))]
2427 if (INTVAL (operands[2]) > 0)
2428 return \"{ldwm|ldw,ma} %2(%1),%0\";
2429 return \"{ldws|ldw},ma %2(%1),%0\";
2431 [(set_attr "type" "load")
2432 (set_attr "length" "4")])
2434 (define_expand "post_store"
2435 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2436 (match_operand 1 "reg_or_0_operand" ""))
2439 (match_operand 2 "post_cint_operand" "")))])]
2445 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2448 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2452 (define_insn "post_stw"
2453 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2454 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2456 (plus:SI (match_dup 0)
2457 (match_operand:SI 2 "post_cint_operand" "")))]
2461 if (INTVAL (operands[2]) > 0)
2462 return \"{stwm|stw,ma} %r1,%2(%0)\";
2463 return \"{stws|stw},ma %r1,%2(%0)\";
2465 [(set_attr "type" "store")
2466 (set_attr "length" "4")])
2468 (define_insn "post_std"
2469 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2470 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2472 (plus:DI (match_dup 0)
2473 (match_operand:DI 2 "post_cint_operand" "")))]
2476 [(set_attr "type" "store")
2477 (set_attr "length" "4")])
2479 ;; For loading the address of a label while generating PIC code.
2480 ;; Note since this pattern can be created at reload time (via movsi), all
2481 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2483 [(set (match_operand 0 "pmode_register_operand" "=a")
2484 (match_operand 1 "pic_label_operand" ""))]
2490 xoperands[0] = operands[0];
2491 xoperands[1] = operands[1];
2492 xoperands[2] = gen_label_rtx ();
2494 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2495 CODE_LABEL_NUMBER (xoperands[2]));
2496 output_asm_insn (\"mfia %0\", xoperands);
2498 /* If we're trying to load the address of a label that happens to be
2499 close, then we can use a shorter sequence. */
2500 if (GET_CODE (operands[1]) == LABEL_REF
2501 && !LABEL_REF_NONLOCAL_P (operands[1])
2502 && INSN_ADDRESSES_SET_P ()
2503 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2504 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2505 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2508 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2509 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2513 [(set_attr "type" "multi")
2514 (set_attr "length" "12")]) ; 8 or 12
2517 [(set (match_operand 0 "pmode_register_operand" "=a")
2518 (match_operand 1 "pic_label_operand" ""))]
2524 xoperands[0] = operands[0];
2525 xoperands[1] = operands[1];
2526 xoperands[2] = gen_label_rtx ();
2528 output_asm_insn (\"bl .+8,%0\", xoperands);
2529 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2530 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2531 CODE_LABEL_NUMBER (xoperands[2]));
2533 /* If we're trying to load the address of a label that happens to be
2534 close, then we can use a shorter sequence. */
2535 if (GET_CODE (operands[1]) == LABEL_REF
2536 && !LABEL_REF_NONLOCAL_P (operands[1])
2537 && INSN_ADDRESSES_SET_P ()
2538 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2539 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2540 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2543 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2544 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2548 [(set_attr "type" "multi")
2549 (set_attr "length" "16")]) ; 12 or 16
2552 [(set (match_operand:SI 0 "register_operand" "=a")
2553 (plus:SI (match_operand:SI 1 "register_operand" "r")
2554 (high:SI (match_operand 2 "" ""))))]
2555 "symbolic_operand (operands[2], Pmode)
2556 && ! function_label_operand (operands[2], Pmode)
2559 [(set_attr "type" "binary")
2560 (set_attr "length" "4")])
2563 [(set (match_operand:DI 0 "register_operand" "=a")
2564 (plus:DI (match_operand:DI 1 "register_operand" "r")
2565 (high:DI (match_operand 2 "" ""))))]
2566 "symbolic_operand (operands[2], Pmode)
2567 && ! function_label_operand (operands[2], Pmode)
2571 [(set_attr "type" "binary")
2572 (set_attr "length" "4")])
2574 ;; Always use addil rather than ldil;add sequences. This allows the
2575 ;; HP linker to eliminate the dp relocation if the symbolic operand
2576 ;; lives in the TEXT space.
2578 [(set (match_operand:SI 0 "register_operand" "=a")
2579 (high:SI (match_operand 1 "" "")))]
2580 "symbolic_operand (operands[1], Pmode)
2581 && ! function_label_operand (operands[1], Pmode)
2582 && ! read_only_operand (operands[1], Pmode)
2586 if (TARGET_LONG_LOAD_STORE)
2587 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2589 return \"addil LR'%H1,%%r27\";
2591 [(set_attr "type" "binary")
2592 (set (attr "length")
2593 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2598 ;; This is for use in the prologue/epilogue code. We need it
2599 ;; to add large constants to a stack pointer or frame pointer.
2600 ;; Because of the additional %r1 pressure, we probably do not
2601 ;; want to use this in general code, so make it available
2602 ;; only after reload.
2604 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2605 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2606 (high:SI (match_operand 2 "const_int_operand" ""))))]
2610 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2611 [(set_attr "type" "binary,binary")
2612 (set_attr "length" "4,8")])
2615 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2616 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2617 (high:DI (match_operand 2 "const_int_operand" ""))))]
2618 "reload_completed && TARGET_64BIT"
2621 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2622 [(set_attr "type" "binary,binary")
2623 (set_attr "length" "4,8")])
2626 [(set (match_operand:SI 0 "register_operand" "=r")
2627 (high:SI (match_operand 1 "" "")))]
2628 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2629 && !is_function_label_plus_const (operands[1])"
2632 if (symbolic_operand (operands[1], Pmode))
2633 return \"ldil LR'%H1,%0\";
2635 return \"ldil L'%G1,%0\";
2637 [(set_attr "type" "move")
2638 (set_attr "length" "4")])
2641 [(set (match_operand:DI 0 "register_operand" "=r")
2642 (high:DI (match_operand 1 "const_int_operand" "")))]
2645 [(set_attr "type" "move")
2646 (set_attr "length" "4")])
2649 [(set (match_operand:DI 0 "register_operand" "=r")
2650 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2651 (match_operand:DI 2 "const_int_operand" "i")))]
2654 [(set_attr "type" "move")
2655 (set_attr "length" "4")])
2658 [(set (match_operand:SI 0 "register_operand" "=r")
2659 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2660 (match_operand:SI 2 "immediate_operand" "i")))]
2661 "!is_function_label_plus_const (operands[2])"
2664 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
2666 if (symbolic_operand (operands[2], Pmode))
2667 return \"ldo RR'%G2(%1),%0\";
2669 return \"ldo R'%G2(%1),%0\";
2671 [(set_attr "type" "move")
2672 (set_attr "length" "4")])
2674 ;; Now that a symbolic_address plus a constant is broken up early
2675 ;; in the compilation phase (for better CSE) we need a special
2676 ;; combiner pattern to load the symbolic address plus the constant
2677 ;; in only 2 instructions. (For cases where the symbolic address
2678 ;; was not a common subexpression.)
2680 [(set (match_operand:SI 0 "register_operand" "")
2681 (match_operand:SI 1 "symbolic_operand" ""))
2682 (clobber (match_operand:SI 2 "register_operand" ""))]
2683 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2684 [(set (match_dup 2) (high:SI (match_dup 1)))
2685 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2688 ;; hppa_legitimize_address goes to a great deal of trouble to
2689 ;; create addresses which use indexing. In some cases, this
2690 ;; is a lose because there isn't any store instructions which
2691 ;; allow indexed addresses (with integer register source).
2693 ;; These define_splits try to turn a 3 insn store into
2694 ;; a 2 insn store with some creative RTL rewriting.
2696 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2697 (match_operand:SI 1 "shadd_operand" ""))
2698 (plus:SI (match_operand:SI 2 "register_operand" "")
2699 (match_operand:SI 3 "const_int_operand" ""))))
2700 (match_operand:SI 4 "register_operand" ""))
2701 (clobber (match_operand:SI 5 "register_operand" ""))]
2703 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2705 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2709 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2710 (match_operand:SI 1 "shadd_operand" ""))
2711 (plus:SI (match_operand:SI 2 "register_operand" "")
2712 (match_operand:SI 3 "const_int_operand" ""))))
2713 (match_operand:HI 4 "register_operand" ""))
2714 (clobber (match_operand:SI 5 "register_operand" ""))]
2716 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2718 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2722 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2723 (match_operand:SI 1 "shadd_operand" ""))
2724 (plus:SI (match_operand:SI 2 "register_operand" "")
2725 (match_operand:SI 3 "const_int_operand" ""))))
2726 (match_operand:QI 4 "register_operand" ""))
2727 (clobber (match_operand:SI 5 "register_operand" ""))]
2729 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2731 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2734 (define_expand "movhi"
2735 [(set (match_operand:HI 0 "general_operand" "")
2736 (match_operand:HI 1 "general_operand" ""))]
2740 if (emit_move_sequence (operands, HImode, 0))
2744 ;; Handle HImode input reloads requiring a general register as a
2745 ;; scratch register.
2746 (define_expand "reload_inhi"
2747 [(set (match_operand:HI 0 "register_operand" "=Z")
2748 (match_operand:HI 1 "non_hard_reg_operand" ""))
2749 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2753 if (emit_move_sequence (operands, HImode, operands[2]))
2756 /* We don't want the clobber emitted, so handle this ourselves. */
2757 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2761 ;; Handle HImode output reloads requiring a general register as a
2762 ;; scratch register.
2763 (define_expand "reload_outhi"
2764 [(set (match_operand:HI 0 "non_hard_reg_operand" "")
2765 (match_operand:HI 1 "register_operand" "Z"))
2766 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2770 if (emit_move_sequence (operands, HImode, operands[2]))
2773 /* We don't want the clobber emitted, so handle this ourselves. */
2774 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2779 [(set (match_operand:HI 0 "move_dest_operand"
2780 "=r,r,r,r,r,Q,!*q,!r")
2781 (match_operand:HI 1 "move_src_operand"
2782 "r,J,N,K,RQ,rM,!rM,!*q"))]
2783 "(register_operand (operands[0], HImode)
2784 || reg_or_0_operand (operands[1], HImode))"
2789 {zdepi|depwi,z} %Z1,%0
2793 {mfctl|mfctl,w} %sar,%0"
2794 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2795 (set_attr "pa_combine_type" "addmove")
2796 (set_attr "length" "4,4,4,4,4,4,4,4")])
2799 [(set (match_operand:HI 0 "register_operand" "=r")
2800 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2801 (match_operand:SI 2 "int5_operand" "L"))))
2803 (plus:SI (match_dup 1) (match_dup 2)))]
2805 "{ldhs|ldh},mb %2(%1),%0"
2806 [(set_attr "type" "load")
2807 (set_attr "length" "4")])
2810 [(set (match_operand:HI 0 "register_operand" "=r")
2811 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2812 (match_operand:DI 2 "int5_operand" "L"))))
2814 (plus:DI (match_dup 1) (match_dup 2)))]
2817 [(set_attr "type" "load")
2818 (set_attr "length" "4")])
2820 ; And a zero extended variant.
2822 [(set (match_operand:DI 0 "register_operand" "=r")
2823 (zero_extend:DI (mem:HI
2825 (match_operand:DI 1 "register_operand" "+r")
2826 (match_operand:DI 2 "int5_operand" "L")))))
2828 (plus:DI (match_dup 1) (match_dup 2)))]
2831 [(set_attr "type" "load")
2832 (set_attr "length" "4")])
2835 [(set (match_operand:SI 0 "register_operand" "=r")
2836 (zero_extend:SI (mem:HI
2838 (match_operand:SI 1 "register_operand" "+r")
2839 (match_operand:SI 2 "int5_operand" "L")))))
2841 (plus:SI (match_dup 1) (match_dup 2)))]
2843 "{ldhs|ldh},mb %2(%1),%0"
2844 [(set_attr "type" "load")
2845 (set_attr "length" "4")])
2848 [(set (match_operand:SI 0 "register_operand" "=r")
2849 (zero_extend:SI (mem:HI
2851 (match_operand:DI 1 "register_operand" "+r")
2852 (match_operand:DI 2 "int5_operand" "L")))))
2854 (plus:DI (match_dup 1) (match_dup 2)))]
2857 [(set_attr "type" "load")
2858 (set_attr "length" "4")])
2861 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2862 (match_operand:SI 1 "int5_operand" "L")))
2863 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2865 (plus:SI (match_dup 0) (match_dup 1)))]
2867 "{sths|sth},mb %r2,%1(%0)"
2868 [(set_attr "type" "store")
2869 (set_attr "length" "4")])
2872 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2873 (match_operand:DI 1 "int5_operand" "L")))
2874 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2876 (plus:DI (match_dup 0) (match_dup 1)))]
2879 [(set_attr "type" "store")
2880 (set_attr "length" "4")])
2883 [(set (match_operand:HI 0 "register_operand" "=r")
2884 (plus:HI (match_operand:HI 1 "register_operand" "r")
2885 (match_operand 2 "const_int_operand" "J")))]
2888 [(set_attr "type" "binary")
2889 (set_attr "pa_combine_type" "addmove")
2890 (set_attr "length" "4")])
2892 (define_expand "movqi"
2893 [(set (match_operand:QI 0 "general_operand" "")
2894 (match_operand:QI 1 "general_operand" ""))]
2898 if (emit_move_sequence (operands, QImode, 0))
2902 ;; Handle QImode input reloads requiring a general register as a
2903 ;; scratch register.
2904 (define_expand "reload_inqi"
2905 [(set (match_operand:QI 0 "register_operand" "=Z")
2906 (match_operand:QI 1 "non_hard_reg_operand" ""))
2907 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2911 if (emit_move_sequence (operands, QImode, operands[2]))
2914 /* We don't want the clobber emitted, so handle this ourselves. */
2915 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2919 ;; Handle QImode output reloads requiring a general register as a
2920 ;; scratch register.
2921 (define_expand "reload_outqi"
2922 [(set (match_operand:QI 0 "non_hard_reg_operand" "")
2923 (match_operand:QI 1 "register_operand" "Z"))
2924 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2928 if (emit_move_sequence (operands, QImode, operands[2]))
2931 /* We don't want the clobber emitted, so handle this ourselves. */
2932 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2937 [(set (match_operand:QI 0 "move_dest_operand"
2938 "=r,r,r,r,r,Q,!*q,!r")
2939 (match_operand:QI 1 "move_src_operand"
2940 "r,J,N,K,RQ,rM,!rM,!*q"))]
2941 "(register_operand (operands[0], QImode)
2942 || reg_or_0_operand (operands[1], QImode))"
2947 {zdepi|depwi,z} %Z1,%0
2951 {mfctl|mfctl,w} %%sar,%0"
2952 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2953 (set_attr "pa_combine_type" "addmove")
2954 (set_attr "length" "4,4,4,4,4,4,4,4")])
2957 [(set (match_operand:QI 0 "register_operand" "=r")
2958 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2959 (match_operand:SI 2 "int5_operand" "L"))))
2960 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2962 "{ldbs|ldb},mb %2(%1),%0"
2963 [(set_attr "type" "load")
2964 (set_attr "length" "4")])
2967 [(set (match_operand:QI 0 "register_operand" "=r")
2968 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2969 (match_operand:DI 2 "int5_operand" "L"))))
2970 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2973 [(set_attr "type" "load")
2974 (set_attr "length" "4")])
2976 ; Now the same thing with zero extensions.
2978 [(set (match_operand:DI 0 "register_operand" "=r")
2979 (zero_extend:DI (mem:QI (plus:DI
2980 (match_operand:DI 1 "register_operand" "+r")
2981 (match_operand:DI 2 "int5_operand" "L")))))
2982 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2985 [(set_attr "type" "load")
2986 (set_attr "length" "4")])
2989 [(set (match_operand:SI 0 "register_operand" "=r")
2990 (zero_extend:SI (mem:QI (plus:SI
2991 (match_operand:SI 1 "register_operand" "+r")
2992 (match_operand:SI 2 "int5_operand" "L")))))
2993 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2995 "{ldbs|ldb},mb %2(%1),%0"
2996 [(set_attr "type" "load")
2997 (set_attr "length" "4")])
3000 [(set (match_operand:SI 0 "register_operand" "=r")
3001 (zero_extend:SI (mem:QI (plus:DI
3002 (match_operand:DI 1 "register_operand" "+r")
3003 (match_operand:DI 2 "int5_operand" "L")))))
3004 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3007 [(set_attr "type" "load")
3008 (set_attr "length" "4")])
3011 [(set (match_operand:HI 0 "register_operand" "=r")
3012 (zero_extend:HI (mem:QI (plus:SI
3013 (match_operand:SI 1 "register_operand" "+r")
3014 (match_operand:SI 2 "int5_operand" "L")))))
3015 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3017 "{ldbs|ldb},mb %2(%1),%0"
3018 [(set_attr "type" "load")
3019 (set_attr "length" "4")])
3022 [(set (match_operand:HI 0 "register_operand" "=r")
3023 (zero_extend:HI (mem:QI (plus:DI
3024 (match_operand:DI 1 "register_operand" "+r")
3025 (match_operand:DI 2 "int5_operand" "L")))))
3026 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3029 [(set_attr "type" "load")
3030 (set_attr "length" "4")])
3033 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3034 (match_operand:SI 1 "int5_operand" "L")))
3035 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3037 (plus:SI (match_dup 0) (match_dup 1)))]
3039 "{stbs|stb},mb %r2,%1(%0)"
3040 [(set_attr "type" "store")
3041 (set_attr "length" "4")])
3044 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3045 (match_operand:DI 1 "int5_operand" "L")))
3046 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3048 (plus:DI (match_dup 0) (match_dup 1)))]
3051 [(set_attr "type" "store")
3052 (set_attr "length" "4")])
3054 ;; The definition of this insn does not really explain what it does,
3055 ;; but it should suffice that anything generated as this insn will be
3056 ;; recognized as a movmemsi operation, and that it will not successfully
3057 ;; combine with anything.
3058 (define_expand "movmemsi"
3059 [(parallel [(set (match_operand:BLK 0 "" "")
3060 (match_operand:BLK 1 "" ""))
3061 (clobber (match_dup 4))
3062 (clobber (match_dup 5))
3063 (clobber (match_dup 6))
3064 (clobber (match_dup 7))
3065 (clobber (match_dup 8))
3066 (use (match_operand:SI 2 "arith_operand" ""))
3067 (use (match_operand:SI 3 "const_int_operand" ""))])]
3068 "!TARGET_64BIT && optimize > 0"
3073 /* HP provides very fast block move library routine for the PA;
3074 this routine includes:
3076 4x4 byte at a time block moves,
3077 1x4 byte at a time with alignment checked at runtime with
3078 attempts to align the source and destination as needed
3081 With that in mind, here's the heuristics to try and guess when
3082 the inlined block move will be better than the library block
3085 If the size isn't constant, then always use the library routines.
3087 If the size is large in respect to the known alignment, then use
3088 the library routines.
3090 If the size is small in respect to the known alignment, then open
3091 code the copy (since that will lead to better scheduling).
3093 Else use the block move pattern. */
3095 /* Undetermined size, use the library routine. */
3096 if (GET_CODE (operands[2]) != CONST_INT)
3099 size = INTVAL (operands[2]);
3100 align = INTVAL (operands[3]);
3101 align = align > 4 ? 4 : (align ? align : 1);
3103 /* If size/alignment is large, then use the library routines. */
3104 if (size / align > 16)
3107 /* This does happen, but not often enough to worry much about. */
3108 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3111 /* Fall through means we're going to use our block move pattern. */
3113 = replace_equiv_address (operands[0],
3114 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3116 = replace_equiv_address (operands[1],
3117 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3118 operands[4] = gen_reg_rtx (SImode);
3119 operands[5] = gen_reg_rtx (SImode);
3120 operands[6] = gen_reg_rtx (SImode);
3121 operands[7] = gen_reg_rtx (SImode);
3122 operands[8] = gen_reg_rtx (SImode);
3125 ;; The operand constraints are written like this to support both compile-time
3126 ;; and run-time determined byte counts. The expander and output_block_move
3127 ;; only support compile-time determined counts at this time.
3129 ;; If the count is run-time determined, the register with the byte count
3130 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3132 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3133 ;; broke this semantic for pseudo registers. We can't use match_scratch
3134 ;; as this requires two registers in the class R1_REGS when the MEMs for
3135 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3136 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3137 ;; respectively. We then split or peephole optimize after reload.
3138 (define_insn "movmemsi_prereload"
3139 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3140 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3141 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3142 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3143 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3144 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3145 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3146 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3147 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3150 [(set_attr "type" "multi,multi")])
3153 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3154 (match_operand:BLK 1 "memory_operand" ""))
3155 (clobber (match_operand:SI 2 "register_operand" ""))
3156 (clobber (match_operand:SI 3 "register_operand" ""))
3157 (clobber (match_operand:SI 6 "register_operand" ""))
3158 (clobber (match_operand:SI 7 "register_operand" ""))
3159 (clobber (match_operand:SI 8 "register_operand" ""))
3160 (use (match_operand:SI 4 "arith_operand" ""))
3161 (use (match_operand:SI 5 "const_int_operand" ""))])]
3162 "!TARGET_64BIT && reload_completed && !flag_peephole2
3163 && GET_CODE (operands[0]) == MEM
3164 && register_operand (XEXP (operands[0], 0), SImode)
3165 && GET_CODE (operands[1]) == MEM
3166 && register_operand (XEXP (operands[1], 0), SImode)"
3167 [(set (match_dup 7) (match_dup 9))
3168 (set (match_dup 8) (match_dup 10))
3169 (parallel [(set (match_dup 0) (match_dup 1))
3170 (clobber (match_dup 2))
3171 (clobber (match_dup 3))
3172 (clobber (match_dup 6))
3173 (clobber (match_dup 7))
3174 (clobber (match_dup 8))
3180 operands[9] = XEXP (operands[0], 0);
3181 operands[10] = XEXP (operands[1], 0);
3182 operands[0] = replace_equiv_address (operands[0], operands[7]);
3183 operands[1] = replace_equiv_address (operands[1], operands[8]);
3187 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3188 (match_operand:BLK 1 "memory_operand" ""))
3189 (clobber (match_operand:SI 2 "register_operand" ""))
3190 (clobber (match_operand:SI 3 "register_operand" ""))
3191 (clobber (match_operand:SI 6 "register_operand" ""))
3192 (clobber (match_operand:SI 7 "register_operand" ""))
3193 (clobber (match_operand:SI 8 "register_operand" ""))
3194 (use (match_operand:SI 4 "arith_operand" ""))
3195 (use (match_operand:SI 5 "const_int_operand" ""))])]
3197 && GET_CODE (operands[0]) == MEM
3198 && register_operand (XEXP (operands[0], 0), SImode)
3199 && GET_CODE (operands[1]) == MEM
3200 && register_operand (XEXP (operands[1], 0), SImode)"
3201 [(parallel [(set (match_dup 0) (match_dup 1))
3202 (clobber (match_dup 2))
3203 (clobber (match_dup 3))
3204 (clobber (match_dup 6))
3205 (clobber (match_dup 7))
3206 (clobber (match_dup 8))
3212 rtx addr = XEXP (operands[0], 0);
3213 if (dead_or_set_p (curr_insn, addr))
3217 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3218 operands[0] = replace_equiv_address (operands[0], operands[7]);
3221 addr = XEXP (operands[1], 0);
3222 if (dead_or_set_p (curr_insn, addr))
3226 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3227 operands[1] = replace_equiv_address (operands[1], operands[8]);
3231 (define_insn "movmemsi_postreload"
3232 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3233 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3234 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3235 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3236 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3237 (clobber (match_dup 0))
3238 (clobber (match_dup 1))
3239 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3240 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3242 "!TARGET_64BIT && reload_completed"
3243 "* return output_block_move (operands, !which_alternative);"
3244 [(set_attr "type" "multi,multi")])
3246 (define_expand "movmemdi"
3247 [(parallel [(set (match_operand:BLK 0 "" "")
3248 (match_operand:BLK 1 "" ""))
3249 (clobber (match_dup 4))
3250 (clobber (match_dup 5))
3251 (clobber (match_dup 6))
3252 (clobber (match_dup 7))
3253 (clobber (match_dup 8))
3254 (use (match_operand:DI 2 "arith_operand" ""))
3255 (use (match_operand:DI 3 "const_int_operand" ""))])]
3256 "TARGET_64BIT && optimize > 0"
3261 /* HP provides very fast block move library routine for the PA;
3262 this routine includes:
3264 4x4 byte at a time block moves,
3265 1x4 byte at a time with alignment checked at runtime with
3266 attempts to align the source and destination as needed
3269 With that in mind, here's the heuristics to try and guess when
3270 the inlined block move will be better than the library block
3273 If the size isn't constant, then always use the library routines.
3275 If the size is large in respect to the known alignment, then use
3276 the library routines.
3278 If the size is small in respect to the known alignment, then open
3279 code the copy (since that will lead to better scheduling).
3281 Else use the block move pattern. */
3283 /* Undetermined size, use the library routine. */
3284 if (GET_CODE (operands[2]) != CONST_INT)
3287 size = INTVAL (operands[2]);
3288 align = INTVAL (operands[3]);
3289 align = align > 8 ? 8 : (align ? align : 1);
3291 /* If size/alignment is large, then use the library routines. */
3292 if (size / align > 16)
3295 /* This does happen, but not often enough to worry much about. */
3296 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3299 /* Fall through means we're going to use our block move pattern. */
3301 = replace_equiv_address (operands[0],
3302 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3304 = replace_equiv_address (operands[1],
3305 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3306 operands[4] = gen_reg_rtx (DImode);
3307 operands[5] = gen_reg_rtx (DImode);
3308 operands[6] = gen_reg_rtx (DImode);
3309 operands[7] = gen_reg_rtx (DImode);
3310 operands[8] = gen_reg_rtx (DImode);
3313 ;; The operand constraints are written like this to support both compile-time
3314 ;; and run-time determined byte counts. The expander and output_block_move
3315 ;; only support compile-time determined counts at this time.
3317 ;; If the count is run-time determined, the register with the byte count
3318 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3320 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3321 ;; broke this semantic for pseudo registers. We can't use match_scratch
3322 ;; as this requires two registers in the class R1_REGS when the MEMs for
3323 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3324 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3325 ;; respectively. We then split or peephole optimize after reload.
3326 (define_insn "movmemdi_prereload"
3327 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3328 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3329 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3330 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3331 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3332 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3333 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3334 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3335 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3338 [(set_attr "type" "multi,multi")])
3341 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3342 (match_operand:BLK 1 "memory_operand" ""))
3343 (clobber (match_operand:DI 2 "register_operand" ""))
3344 (clobber (match_operand:DI 3 "register_operand" ""))
3345 (clobber (match_operand:DI 6 "register_operand" ""))
3346 (clobber (match_operand:DI 7 "register_operand" ""))
3347 (clobber (match_operand:DI 8 "register_operand" ""))
3348 (use (match_operand:DI 4 "arith_operand" ""))
3349 (use (match_operand:DI 5 "const_int_operand" ""))])]
3350 "TARGET_64BIT && reload_completed && !flag_peephole2
3351 && GET_CODE (operands[0]) == MEM
3352 && register_operand (XEXP (operands[0], 0), DImode)
3353 && GET_CODE (operands[1]) == MEM
3354 && register_operand (XEXP (operands[1], 0), DImode)"
3355 [(set (match_dup 7) (match_dup 9))
3356 (set (match_dup 8) (match_dup 10))
3357 (parallel [(set (match_dup 0) (match_dup 1))
3358 (clobber (match_dup 2))
3359 (clobber (match_dup 3))
3360 (clobber (match_dup 6))
3361 (clobber (match_dup 7))
3362 (clobber (match_dup 8))
3368 operands[9] = XEXP (operands[0], 0);
3369 operands[10] = XEXP (operands[1], 0);
3370 operands[0] = replace_equiv_address (operands[0], operands[7]);
3371 operands[1] = replace_equiv_address (operands[1], operands[8]);
3375 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3376 (match_operand:BLK 1 "memory_operand" ""))
3377 (clobber (match_operand:DI 2 "register_operand" ""))
3378 (clobber (match_operand:DI 3 "register_operand" ""))
3379 (clobber (match_operand:DI 6 "register_operand" ""))
3380 (clobber (match_operand:DI 7 "register_operand" ""))
3381 (clobber (match_operand:DI 8 "register_operand" ""))
3382 (use (match_operand:DI 4 "arith_operand" ""))
3383 (use (match_operand:DI 5 "const_int_operand" ""))])]
3385 && GET_CODE (operands[0]) == MEM
3386 && register_operand (XEXP (operands[0], 0), DImode)
3387 && GET_CODE (operands[1]) == MEM
3388 && register_operand (XEXP (operands[1], 0), DImode)"
3389 [(parallel [(set (match_dup 0) (match_dup 1))
3390 (clobber (match_dup 2))
3391 (clobber (match_dup 3))
3392 (clobber (match_dup 6))
3393 (clobber (match_dup 7))
3394 (clobber (match_dup 8))
3400 rtx addr = XEXP (operands[0], 0);
3401 if (dead_or_set_p (curr_insn, addr))
3405 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3406 operands[0] = replace_equiv_address (operands[0], operands[7]);
3409 addr = XEXP (operands[1], 0);
3410 if (dead_or_set_p (curr_insn, addr))
3414 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3415 operands[1] = replace_equiv_address (operands[1], operands[8]);
3419 (define_insn "movmemdi_postreload"
3420 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3421 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3422 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3423 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3424 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3425 (clobber (match_dup 0))
3426 (clobber (match_dup 1))
3427 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3428 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3430 "TARGET_64BIT && reload_completed"
3431 "* return output_block_move (operands, !which_alternative);"
3432 [(set_attr "type" "multi,multi")])
3434 (define_expand "setmemsi"
3435 [(parallel [(set (match_operand:BLK 0 "" "")
3436 (match_operand 2 "const_int_operand" ""))
3437 (clobber (match_dup 4))
3438 (clobber (match_dup 5))
3439 (use (match_operand:SI 1 "arith_operand" ""))
3440 (use (match_operand:SI 3 "const_int_operand" ""))])]
3441 "!TARGET_64BIT && optimize > 0"
3446 /* If value to set is not zero, use the library routine. */
3447 if (operands[2] != const0_rtx)
3450 /* Undetermined size, use the library routine. */
3451 if (GET_CODE (operands[1]) != CONST_INT)
3454 size = INTVAL (operands[1]);
3455 align = INTVAL (operands[3]);
3456 align = align > 4 ? 4 : align;
3458 /* If size/alignment is large, then use the library routines. */
3459 if (size / align > 16)
3462 /* This does happen, but not often enough to worry much about. */
3463 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3466 /* Fall through means we're going to use our block clear pattern. */
3468 = replace_equiv_address (operands[0],
3469 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3470 operands[4] = gen_reg_rtx (SImode);
3471 operands[5] = gen_reg_rtx (SImode);
3474 (define_insn "clrmemsi_prereload"
3475 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3477 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3478 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3479 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3480 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3483 [(set_attr "type" "multi,multi")])
3486 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3488 (clobber (match_operand:SI 1 "register_operand" ""))
3489 (clobber (match_operand:SI 4 "register_operand" ""))
3490 (use (match_operand:SI 2 "arith_operand" ""))
3491 (use (match_operand:SI 3 "const_int_operand" ""))])]
3492 "!TARGET_64BIT && reload_completed && !flag_peephole2
3493 && GET_CODE (operands[0]) == MEM
3494 && register_operand (XEXP (operands[0], 0), SImode)"
3495 [(set (match_dup 4) (match_dup 5))
3496 (parallel [(set (match_dup 0) (const_int 0))
3497 (clobber (match_dup 1))
3498 (clobber (match_dup 4))
3504 operands[5] = XEXP (operands[0], 0);
3505 operands[0] = replace_equiv_address (operands[0], operands[4]);
3509 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3511 (clobber (match_operand:SI 1 "register_operand" ""))
3512 (clobber (match_operand:SI 4 "register_operand" ""))
3513 (use (match_operand:SI 2 "arith_operand" ""))
3514 (use (match_operand:SI 3 "const_int_operand" ""))])]
3516 && GET_CODE (operands[0]) == MEM
3517 && register_operand (XEXP (operands[0], 0), SImode)"
3518 [(parallel [(set (match_dup 0) (const_int 0))
3519 (clobber (match_dup 1))
3520 (clobber (match_dup 4))
3526 rtx addr = XEXP (operands[0], 0);
3527 if (dead_or_set_p (curr_insn, addr))
3531 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3532 operands[0] = replace_equiv_address (operands[0], operands[4]);
3536 (define_insn "clrmemsi_postreload"
3537 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3539 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3540 (clobber (match_dup 0))
3541 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3542 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3544 "!TARGET_64BIT && reload_completed"
3545 "* return output_block_clear (operands, !which_alternative);"
3546 [(set_attr "type" "multi,multi")])
3548 (define_expand "setmemdi"
3549 [(parallel [(set (match_operand:BLK 0 "" "")
3550 (match_operand 2 "const_int_operand" ""))
3551 (clobber (match_dup 4))
3552 (clobber (match_dup 5))
3553 (use (match_operand:DI 1 "arith_operand" ""))
3554 (use (match_operand:DI 3 "const_int_operand" ""))])]
3555 "TARGET_64BIT && optimize > 0"
3560 /* If value to set is not zero, use the library routine. */
3561 if (operands[2] != const0_rtx)
3564 /* Undetermined size, use the library routine. */
3565 if (GET_CODE (operands[1]) != CONST_INT)
3568 size = INTVAL (operands[1]);
3569 align = INTVAL (operands[3]);
3570 align = align > 8 ? 8 : align;
3572 /* If size/alignment is large, then use the library routines. */
3573 if (size / align > 16)
3576 /* This does happen, but not often enough to worry much about. */
3577 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3580 /* Fall through means we're going to use our block clear pattern. */
3582 = replace_equiv_address (operands[0],
3583 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3584 operands[4] = gen_reg_rtx (DImode);
3585 operands[5] = gen_reg_rtx (DImode);
3588 (define_insn "clrmemdi_prereload"
3589 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3591 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3592 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3593 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3594 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3597 [(set_attr "type" "multi,multi")])
3600 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3602 (clobber (match_operand:DI 1 "register_operand" ""))
3603 (clobber (match_operand:DI 4 "register_operand" ""))
3604 (use (match_operand:DI 2 "arith_operand" ""))
3605 (use (match_operand:DI 3 "const_int_operand" ""))])]
3606 "TARGET_64BIT && reload_completed && !flag_peephole2
3607 && GET_CODE (operands[0]) == MEM
3608 && register_operand (XEXP (operands[0], 0), DImode)"
3609 [(set (match_dup 4) (match_dup 5))
3610 (parallel [(set (match_dup 0) (const_int 0))
3611 (clobber (match_dup 1))
3612 (clobber (match_dup 4))
3618 operands[5] = XEXP (operands[0], 0);
3619 operands[0] = replace_equiv_address (operands[0], operands[4]);
3623 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3625 (clobber (match_operand:DI 1 "register_operand" ""))
3626 (clobber (match_operand:DI 4 "register_operand" ""))
3627 (use (match_operand:DI 2 "arith_operand" ""))
3628 (use (match_operand:DI 3 "const_int_operand" ""))])]
3630 && GET_CODE (operands[0]) == MEM
3631 && register_operand (XEXP (operands[0], 0), DImode)"
3632 [(parallel [(set (match_dup 0) (const_int 0))
3633 (clobber (match_dup 1))
3634 (clobber (match_dup 4))
3640 rtx addr = XEXP (operands[0], 0);
3641 if (dead_or_set_p (curr_insn, addr))
3645 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3646 operands[0] = replace_equiv_address (operands[0], operands[4]);
3650 (define_insn "clrmemdi_postreload"
3651 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3653 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3654 (clobber (match_dup 0))
3655 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3656 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3658 "TARGET_64BIT && reload_completed"
3659 "* return output_block_clear (operands, !which_alternative);"
3660 [(set_attr "type" "multi,multi")])
3662 ;; Floating point move insns
3664 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3665 ;; to be reloaded by putting the constant into memory when
3666 ;; reg is a floating point register.
3668 ;; For integer registers we use ldil;ldo to set the appropriate
3671 ;; This must come before the movdf pattern, and it must be present
3672 ;; to handle obscure reloading cases.
3674 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3675 (match_operand:DF 1 "" "?F,m"))]
3676 "GET_CODE (operands[1]) == CONST_DOUBLE
3677 && operands[1] != CONST0_RTX (DFmode)
3679 && !TARGET_SOFT_FLOAT"
3680 "* return (which_alternative == 0 ? output_move_double (operands)
3681 : \"fldd%F1 %1,%0\");"
3682 [(set_attr "type" "move,fpload")
3683 (set_attr "length" "16,4")])
3685 (define_expand "movdf"
3686 [(set (match_operand:DF 0 "general_operand" "")
3687 (match_operand:DF 1 "general_operand" ""))]
3691 if (GET_CODE (operands[1]) == CONST_DOUBLE
3692 && operands[1] != CONST0_RTX (DFmode))
3694 /* Reject CONST_DOUBLE loads to all hard registers when
3695 generating 64-bit code and to floating point registers
3696 when generating 32-bit code. */
3697 if (REG_P (operands[0])
3698 && HARD_REGISTER_P (operands[0])
3699 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
3703 operands[1] = force_const_mem (DFmode, operands[1]);
3706 if (emit_move_sequence (operands, DFmode, 0))
3710 ;; Handle DFmode input reloads requiring a general register as a
3711 ;; scratch register.
3712 (define_expand "reload_indf"
3713 [(set (match_operand:DF 0 "register_operand" "=Z")
3714 (match_operand:DF 1 "non_hard_reg_operand" ""))
3715 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3719 if (emit_move_sequence (operands, DFmode, operands[2]))
3722 /* We don't want the clobber emitted, so handle this ourselves. */
3723 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3727 ;; Handle DFmode output reloads requiring a general register as a
3728 ;; scratch register.
3729 (define_expand "reload_outdf"
3730 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3731 (match_operand:DF 1 "register_operand" "Z"))
3732 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3736 if (emit_move_sequence (operands, DFmode, operands[2]))
3739 /* We don't want the clobber emitted, so handle this ourselves. */
3740 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3745 [(set (match_operand:DF 0 "move_dest_operand"
3746 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
3747 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3748 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
3749 "(register_operand (operands[0], DFmode)
3750 || reg_or_0_operand (operands[1], DFmode))
3751 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3752 && GET_CODE (operands[0]) == MEM)
3754 && !TARGET_SOFT_FLOAT"
3757 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3758 || operands[1] == CONST0_RTX (DFmode))
3759 && !(REG_P (operands[0]) && REG_P (operands[1])
3760 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
3761 return output_fp_move_double (operands);
3762 return output_move_double (operands);
3764 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
3765 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
3768 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3769 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3771 && !TARGET_DISABLE_INDEXING
3772 && reload_completed"
3774 [(set_attr "type" "fpstore")
3775 (set_attr "pa_combine_type" "addmove")
3776 (set_attr "length" "4")])
3779 [(set (match_operand:SI 0 "register_operand" "")
3780 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3782 (match_operand:SI 2 "register_operand" "")))
3783 (set (mem:DF (match_dup 0))
3784 (match_operand:DF 3 "register_operand" ""))]
3786 && !TARGET_DISABLE_INDEXING
3787 && REG_OK_FOR_BASE_P (operands[2])
3788 && FP_REGNO_P (REGNO (operands[3]))"
3789 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3791 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3796 [(set (match_operand:SI 0 "register_operand" "")
3797 (plus:SI (match_operand:SI 2 "register_operand" "")
3798 (mult:SI (match_operand:SI 1 "register_operand" "")
3800 (set (mem:DF (match_dup 0))
3801 (match_operand:DF 3 "register_operand" ""))]
3803 && !TARGET_DISABLE_INDEXING
3804 && REG_OK_FOR_BASE_P (operands[2])
3805 && FP_REGNO_P (REGNO (operands[3]))"
3806 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3808 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3813 [(set (match_operand:DI 0 "register_operand" "")
3814 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3816 (match_operand:DI 2 "register_operand" "")))
3817 (set (mem:DF (match_dup 0))
3818 (match_operand:DF 3 "register_operand" ""))]
3820 && !TARGET_DISABLE_INDEXING
3822 && REG_OK_FOR_BASE_P (operands[2])
3823 && FP_REGNO_P (REGNO (operands[3]))"
3824 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3826 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3831 [(set (match_operand:DI 0 "register_operand" "")
3832 (plus:DI (match_operand:DI 2 "register_operand" "")
3833 (mult:DI (match_operand:DI 1 "register_operand" "")
3835 (set (mem:DF (match_dup 0))
3836 (match_operand:DF 3 "register_operand" ""))]
3838 && !TARGET_DISABLE_INDEXING
3840 && REG_OK_FOR_BASE_P (operands[2])
3841 && FP_REGNO_P (REGNO (operands[3]))"
3842 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3844 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3849 [(set (match_operand:SI 0 "register_operand" "")
3850 (plus:SI (match_operand:SI 1 "register_operand" "")
3851 (match_operand:SI 2 "register_operand" "")))
3852 (set (mem:DF (match_dup 0))
3853 (match_operand:DF 3 "register_operand" ""))]
3855 && !TARGET_DISABLE_INDEXING
3856 && TARGET_NO_SPACE_REGS
3857 && REG_OK_FOR_INDEX_P (operands[1])
3858 && REG_OK_FOR_BASE_P (operands[2])
3859 && FP_REGNO_P (REGNO (operands[3]))"
3860 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3862 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3866 [(set (match_operand:SI 0 "register_operand" "")
3867 (plus:SI (match_operand:SI 1 "register_operand" "")
3868 (match_operand:SI 2 "register_operand" "")))
3869 (set (mem:DF (match_dup 0))
3870 (match_operand:DF 3 "register_operand" ""))]
3872 && !TARGET_DISABLE_INDEXING
3873 && TARGET_NO_SPACE_REGS
3874 && REG_OK_FOR_BASE_P (operands[1])
3875 && REG_OK_FOR_INDEX_P (operands[2])
3876 && FP_REGNO_P (REGNO (operands[3]))"
3877 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3879 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3883 [(set (match_operand:DI 0 "register_operand" "")
3884 (plus:DI (match_operand:DI 1 "register_operand" "")
3885 (match_operand:DI 2 "register_operand" "")))
3886 (set (mem:DF (match_dup 0))
3887 (match_operand:DF 3 "register_operand" ""))]
3889 && !TARGET_DISABLE_INDEXING
3891 && TARGET_NO_SPACE_REGS
3892 && REG_OK_FOR_INDEX_P (operands[1])
3893 && REG_OK_FOR_BASE_P (operands[2])
3894 && FP_REGNO_P (REGNO (operands[3]))"
3895 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3897 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3901 [(set (match_operand:DI 0 "register_operand" "")
3902 (plus:DI (match_operand:DI 1 "register_operand" "")
3903 (match_operand:DI 2 "register_operand" "")))
3904 (set (mem:DF (match_dup 0))
3905 (match_operand:DF 3 "register_operand" ""))]
3907 && !TARGET_DISABLE_INDEXING
3909 && TARGET_NO_SPACE_REGS
3910 && REG_OK_FOR_BASE_P (operands[1])
3911 && REG_OK_FOR_INDEX_P (operands[2])
3912 && FP_REGNO_P (REGNO (operands[3]))"
3913 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3915 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3919 [(set (match_operand:DF 0 "move_dest_operand"
3921 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3923 "(register_operand (operands[0], DFmode)
3924 || reg_or_0_operand (operands[1], DFmode))
3926 && TARGET_SOFT_FLOAT"
3929 return output_move_double (operands);
3931 [(set_attr "type" "move,store,store,load,load")
3932 (set_attr "length" "8,8,16,8,16")])
3935 [(set (match_operand:DF 0 "move_dest_operand"
3936 "=!*r,*r,*r,*r,*r,Q,f,f,T")
3937 (match_operand:DF 1 "move_src_operand"
3938 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
3939 "(register_operand (operands[0], DFmode)
3940 || reg_or_0_operand (operands[1], DFmode))
3941 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3952 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
3953 (set_attr "pa_combine_type" "addmove")
3954 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3957 (define_expand "movdi"
3958 [(set (match_operand:DI 0 "general_operand" "")
3959 (match_operand:DI 1 "general_operand" ""))]
3963 /* Except for zero, we don't support loading a CONST_INT directly
3964 to a hard floating-point register since a scratch register is
3965 needed for the operation. While the operation could be handled
3966 before register allocation, the simplest solution is to fail. */
3968 && GET_CODE (operands[1]) == CONST_INT
3969 && operands[1] != CONST0_RTX (DImode)
3970 && REG_P (operands[0])
3971 && HARD_REGISTER_P (operands[0])
3972 && REGNO (operands[0]) >= 32)
3975 if (emit_move_sequence (operands, DImode, 0))
3979 ;; Handle DImode input reloads requiring %r1 as a scratch register.
3980 (define_expand "reload_indi_r1"
3981 [(set (match_operand:DI 0 "register_operand" "=Z")
3982 (match_operand:DI 1 "non_hard_reg_operand" ""))
3983 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
3987 if (emit_move_sequence (operands, DImode, operands[2]))
3990 /* We don't want the clobber emitted, so handle this ourselves. */
3991 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3995 ;; Handle DImode input reloads requiring a general register as a
3996 ;; scratch register.
3997 (define_expand "reload_indi"
3998 [(set (match_operand:DI 0 "register_operand" "=Z")
3999 (match_operand:DI 1 "non_hard_reg_operand" ""))
4000 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4004 if (emit_move_sequence (operands, DImode, operands[2]))
4007 /* We don't want the clobber emitted, so handle this ourselves. */
4008 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4012 ;; Handle DImode output reloads requiring a general register as a
4013 ;; scratch register.
4014 (define_expand "reload_outdi"
4015 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4016 (match_operand:DI 1 "register_operand" "Z"))
4017 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4021 if (emit_move_sequence (operands, DImode, operands[2]))
4024 /* We don't want the clobber emitted, so handle this ourselves. */
4025 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4030 [(set (match_operand:DI 0 "register_operand" "=r")
4031 (high:DI (match_operand 1 "" "")))]
4035 rtx op0 = operands[0];
4036 rtx op1 = operands[1];
4038 switch (GET_CODE (op1))
4041 #if HOST_BITS_PER_WIDE_INT <= 32
4042 operands[0] = operand_subword (op0, 1, 0, DImode);
4043 output_asm_insn (\"ldil L'%1,%0\", operands);
4045 operands[0] = operand_subword (op0, 0, 0, DImode);
4046 if (INTVAL (op1) < 0)
4047 output_asm_insn (\"ldi -1,%0\", operands);
4049 output_asm_insn (\"ldi 0,%0\", operands);
4051 operands[0] = operand_subword (op0, 1, 0, DImode);
4052 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4053 output_asm_insn (\"ldil L'%1,%0\", operands);
4055 operands[0] = operand_subword (op0, 0, 0, DImode);
4056 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4057 output_asm_insn (singlemove_string (operands), operands);
4062 operands[0] = operand_subword (op0, 1, 0, DImode);
4063 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4064 output_asm_insn (\"ldil L'%1,%0\", operands);
4066 operands[0] = operand_subword (op0, 0, 0, DImode);
4067 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4068 output_asm_insn (singlemove_string (operands), operands);
4076 [(set_attr "type" "move")
4077 (set_attr "length" "12")])
4080 [(set (match_operand:DI 0 "move_dest_operand"
4081 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4082 (match_operand:DI 1 "general_operand"
4083 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4084 "(register_operand (operands[0], DImode)
4085 || reg_or_0_operand (operands[1], DImode))
4087 && !TARGET_SOFT_FLOAT"
4090 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4091 || operands[1] == CONST0_RTX (DFmode))
4092 && !(REG_P (operands[0]) && REG_P (operands[1])
4093 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4094 return output_fp_move_double (operands);
4095 return output_move_double (operands);
4098 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4099 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4102 [(set (match_operand:DI 0 "move_dest_operand"
4103 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4104 (match_operand:DI 1 "move_src_operand"
4105 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4106 "(register_operand (operands[0], DImode)
4107 || reg_or_0_operand (operands[1], DImode))
4108 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4118 {mfctl|mfctl,w} %%sar,%0
4122 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4123 (set_attr "pa_combine_type" "addmove")
4124 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4127 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4128 (match_operand:DI 1 "register_operand" "f"))]
4131 && !TARGET_DISABLE_INDEXING
4132 && reload_completed"
4134 [(set_attr "type" "fpstore")
4135 (set_attr "pa_combine_type" "addmove")
4136 (set_attr "length" "4")])
4139 [(set (match_operand:DI 0 "register_operand" "")
4140 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4142 (match_operand:DI 2 "register_operand" "")))
4143 (set (mem:DI (match_dup 0))
4144 (match_operand:DI 3 "register_operand" ""))]
4146 && !TARGET_DISABLE_INDEXING
4148 && REG_OK_FOR_BASE_P (operands[2])
4149 && FP_REGNO_P (REGNO (operands[3]))"
4150 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4152 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4157 [(set (match_operand:DI 0 "register_operand" "")
4158 (plus:DI (match_operand:DI 2 "register_operand" "")
4159 (mult:DI (match_operand:DI 1 "register_operand" "")
4161 (set (mem:DI (match_dup 0))
4162 (match_operand:DI 3 "register_operand" ""))]
4164 && !TARGET_DISABLE_INDEXING
4166 && REG_OK_FOR_BASE_P (operands[2])
4167 && FP_REGNO_P (REGNO (operands[3]))"
4168 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4170 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4175 [(set (match_operand:DI 0 "register_operand" "")
4176 (plus:DI (match_operand:DI 1 "register_operand" "")
4177 (match_operand:DI 2 "register_operand" "")))
4178 (set (mem:DI (match_dup 0))
4179 (match_operand:DI 3 "register_operand" ""))]
4181 && !TARGET_DISABLE_INDEXING
4183 && TARGET_NO_SPACE_REGS
4184 && REG_OK_FOR_INDEX_P (operands[1])
4185 && REG_OK_FOR_BASE_P (operands[2])
4186 && FP_REGNO_P (REGNO (operands[3]))"
4187 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4189 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4193 [(set (match_operand:DI 0 "register_operand" "")
4194 (plus:DI (match_operand:DI 1 "register_operand" "")
4195 (match_operand:DI 2 "register_operand" "")))
4196 (set (mem:DI (match_dup 0))
4197 (match_operand:DI 3 "register_operand" ""))]
4199 && !TARGET_DISABLE_INDEXING
4201 && TARGET_NO_SPACE_REGS
4202 && REG_OK_FOR_BASE_P (operands[1])
4203 && REG_OK_FOR_INDEX_P (operands[2])
4204 && FP_REGNO_P (REGNO (operands[3]))"
4205 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4207 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4211 [(set (match_operand:DI 0 "move_dest_operand"
4213 (match_operand:DI 1 "general_operand"
4215 "(register_operand (operands[0], DImode)
4216 || reg_or_0_operand (operands[1], DImode))
4218 && TARGET_SOFT_FLOAT"
4221 return output_move_double (operands);
4223 [(set_attr "type" "move,store,store,load,load,multi")
4224 (set_attr "length" "8,8,16,8,16,16")])
4227 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4228 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4229 (match_operand:DI 2 "immediate_operand" "i,i")))]
4233 /* Don't output a 64-bit constant, since we can't trust the assembler to
4234 handle it correctly. */
4235 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4236 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4237 else if (HOST_BITS_PER_WIDE_INT > 32
4238 && GET_CODE (operands[2]) == CONST_INT)
4239 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4240 if (which_alternative == 1)
4241 output_asm_insn (\"copy %1,%0\", operands);
4242 return \"ldo R'%G2(%R1),%R0\";
4244 [(set_attr "type" "move,move")
4245 (set_attr "length" "4,8")])
4247 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4248 ;; to be reloaded by putting the constant into memory when
4249 ;; reg is a floating point register.
4251 ;; For integer registers we use ldil;ldo to set the appropriate
4254 ;; This must come before the movsf pattern, and it must be present
4255 ;; to handle obscure reloading cases.
4257 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4258 (match_operand:SF 1 "" "?F,m"))]
4259 "GET_CODE (operands[1]) == CONST_DOUBLE
4260 && operands[1] != CONST0_RTX (SFmode)
4261 && ! TARGET_SOFT_FLOAT"
4262 "* return (which_alternative == 0 ? singlemove_string (operands)
4263 : \" fldw%F1 %1,%0\");"
4264 [(set_attr "type" "move,fpload")
4265 (set_attr "length" "8,4")])
4267 (define_expand "movsf"
4268 [(set (match_operand:SF 0 "general_operand" "")
4269 (match_operand:SF 1 "general_operand" ""))]
4273 /* Reject CONST_DOUBLE loads to floating point registers. */
4274 if (GET_CODE (operands[1]) == CONST_DOUBLE
4275 && operands[1] != CONST0_RTX (SFmode)
4276 && REG_P (operands[0])
4277 && HARD_REGISTER_P (operands[0])
4278 && REGNO (operands[0]) >= 32)
4281 if (emit_move_sequence (operands, SFmode, 0))
4285 ;; Handle SFmode input reloads requiring a general register as a
4286 ;; scratch register.
4287 (define_expand "reload_insf"
4288 [(set (match_operand:SF 0 "register_operand" "=Z")
4289 (match_operand:SF 1 "non_hard_reg_operand" ""))
4290 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4294 if (emit_move_sequence (operands, SFmode, operands[2]))
4297 /* We don't want the clobber emitted, so handle this ourselves. */
4298 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4302 ;; Handle SFmode output reloads requiring a general register as a
4303 ;; scratch register.
4304 (define_expand "reload_outsf"
4305 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4306 (match_operand:SF 1 "register_operand" "Z"))
4307 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4311 if (emit_move_sequence (operands, SFmode, operands[2]))
4314 /* We don't want the clobber emitted, so handle this ourselves. */
4315 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4320 [(set (match_operand:SF 0 "move_dest_operand"
4321 "=f,!*r,f,*r,Q,Q,?*r,?f")
4322 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4323 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4324 "(register_operand (operands[0], SFmode)
4325 || reg_or_0_operand (operands[1], SFmode))
4326 && !TARGET_SOFT_FLOAT
4335 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4336 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4337 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4338 (set_attr "pa_combine_type" "addmove")
4339 (set_attr "length" "4,4,4,4,4,4,8,8")])
4342 [(set (match_operand:SF 0 "move_dest_operand"
4344 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4345 "fG,!*rG,RQ,RQ,f,*rG"))]
4346 "(register_operand (operands[0], SFmode)
4347 || reg_or_0_operand (operands[1], SFmode))
4348 && !TARGET_SOFT_FLOAT
4357 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4358 (set_attr "pa_combine_type" "addmove")
4359 (set_attr "length" "4,4,4,4,4,4")])
4362 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4363 (match_operand:SF 1 "register_operand" "f"))]
4365 && !TARGET_DISABLE_INDEXING
4366 && reload_completed"
4368 [(set_attr "type" "fpstore")
4369 (set_attr "pa_combine_type" "addmove")
4370 (set_attr "length" "4")])
4373 [(set (match_operand:SI 0 "register_operand" "")
4374 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4376 (match_operand:SI 2 "register_operand" "")))
4377 (set (mem:SF (match_dup 0))
4378 (match_operand:SF 3 "register_operand" ""))]
4380 && !TARGET_DISABLE_INDEXING
4381 && REG_OK_FOR_BASE_P (operands[2])
4382 && FP_REGNO_P (REGNO (operands[3]))"
4383 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4385 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4390 [(set (match_operand:SI 0 "register_operand" "")
4391 (plus:SI (match_operand:SI 2 "register_operand" "")
4392 (mult:SI (match_operand:SI 1 "register_operand" "")
4394 (set (mem:SF (match_dup 0))
4395 (match_operand:SF 3 "register_operand" ""))]
4397 && !TARGET_DISABLE_INDEXING
4398 && REG_OK_FOR_BASE_P (operands[2])
4399 && FP_REGNO_P (REGNO (operands[3]))"
4400 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4402 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4407 [(set (match_operand:DI 0 "register_operand" "")
4408 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4410 (match_operand:DI 2 "register_operand" "")))
4411 (set (mem:SF (match_dup 0))
4412 (match_operand:SF 3 "register_operand" ""))]
4414 && !TARGET_DISABLE_INDEXING
4416 && REG_OK_FOR_BASE_P (operands[2])
4417 && FP_REGNO_P (REGNO (operands[3]))"
4418 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4420 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4425 [(set (match_operand:DI 0 "register_operand" "")
4426 (plus:DI (match_operand:DI 2 "register_operand" "")
4427 (mult:DI (match_operand:DI 1 "register_operand" "")
4429 (set (mem:SF (match_dup 0))
4430 (match_operand:SF 3 "register_operand" ""))]
4432 && !TARGET_DISABLE_INDEXING
4434 && REG_OK_FOR_BASE_P (operands[2])
4435 && FP_REGNO_P (REGNO (operands[3]))"
4436 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4438 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4443 [(set (match_operand:SI 0 "register_operand" "")
4444 (plus:SI (match_operand:SI 1 "register_operand" "")
4445 (match_operand:SI 2 "register_operand" "")))
4446 (set (mem:SF (match_dup 0))
4447 (match_operand:SF 3 "register_operand" ""))]
4449 && !TARGET_DISABLE_INDEXING
4450 && TARGET_NO_SPACE_REGS
4451 && REG_OK_FOR_INDEX_P (operands[1])
4452 && REG_OK_FOR_BASE_P (operands[2])
4453 && FP_REGNO_P (REGNO (operands[3]))"
4454 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4456 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4460 [(set (match_operand:SI 0 "register_operand" "")
4461 (plus:SI (match_operand:SI 1 "register_operand" "")
4462 (match_operand:SI 2 "register_operand" "")))
4463 (set (mem:SF (match_dup 0))
4464 (match_operand:SF 3 "register_operand" ""))]
4466 && !TARGET_DISABLE_INDEXING
4467 && TARGET_NO_SPACE_REGS
4468 && REG_OK_FOR_BASE_P (operands[1])
4469 && REG_OK_FOR_INDEX_P (operands[2])
4470 && FP_REGNO_P (REGNO (operands[3]))"
4471 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4473 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4477 [(set (match_operand:DI 0 "register_operand" "")
4478 (plus:DI (match_operand:DI 1 "register_operand" "")
4479 (match_operand:DI 2 "register_operand" "")))
4480 (set (mem:SF (match_dup 0))
4481 (match_operand:SF 3 "register_operand" ""))]
4483 && !TARGET_DISABLE_INDEXING
4485 && TARGET_NO_SPACE_REGS
4486 && REG_OK_FOR_INDEX_P (operands[1])
4487 && REG_OK_FOR_BASE_P (operands[2])
4488 && FP_REGNO_P (REGNO (operands[3]))"
4489 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4491 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4495 [(set (match_operand:DI 0 "register_operand" "")
4496 (plus:DI (match_operand:DI 1 "register_operand" "")
4497 (match_operand:DI 2 "register_operand" "")))
4498 (set (mem:SF (match_dup 0))
4499 (match_operand:SF 3 "register_operand" ""))]
4501 && !TARGET_DISABLE_INDEXING
4503 && TARGET_NO_SPACE_REGS
4504 && REG_OK_FOR_BASE_P (operands[1])
4505 && REG_OK_FOR_INDEX_P (operands[2])
4506 && FP_REGNO_P (REGNO (operands[3]))"
4507 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4509 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4513 [(set (match_operand:SF 0 "move_dest_operand"
4515 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4517 "(register_operand (operands[0], SFmode)
4518 || reg_or_0_operand (operands[1], SFmode))
4519 && TARGET_SOFT_FLOAT"
4524 [(set_attr "type" "move,load,store")
4525 (set_attr "pa_combine_type" "addmove")
4526 (set_attr "length" "4,4,4")])
4530 ;;- zero extension instructions
4531 ;; We have define_expand for zero extension patterns to make sure the
4532 ;; operands get loaded into registers. The define_insns accept
4533 ;; memory operands. This gives us better overall code than just
4534 ;; having a pattern that does or does not accept memory operands.
4536 (define_expand "zero_extendqihi2"
4537 [(set (match_operand:HI 0 "register_operand" "")
4539 (match_operand:QI 1 "register_operand" "")))]
4544 [(set (match_operand:HI 0 "register_operand" "=r,r")
4546 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4547 "GET_CODE (operands[1]) != CONST_INT"
4549 {extru|extrw,u} %1,31,8,%0
4551 [(set_attr "type" "shift,load")
4552 (set_attr "length" "4,4")])
4554 (define_expand "zero_extendqisi2"
4555 [(set (match_operand:SI 0 "register_operand" "")
4557 (match_operand:QI 1 "register_operand" "")))]
4562 [(set (match_operand:SI 0 "register_operand" "=r,r")
4564 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4565 "GET_CODE (operands[1]) != CONST_INT"
4567 {extru|extrw,u} %1,31,8,%0
4569 [(set_attr "type" "shift,load")
4570 (set_attr "length" "4,4")])
4572 (define_expand "zero_extendhisi2"
4573 [(set (match_operand:SI 0 "register_operand" "")
4575 (match_operand:HI 1 "register_operand" "")))]
4580 [(set (match_operand:SI 0 "register_operand" "=r,r")
4582 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4583 "GET_CODE (operands[1]) != CONST_INT"
4585 {extru|extrw,u} %1,31,16,%0
4587 [(set_attr "type" "shift,load")
4588 (set_attr "length" "4,4")])
4590 (define_expand "zero_extendqidi2"
4591 [(set (match_operand:DI 0 "register_operand" "")
4593 (match_operand:QI 1 "register_operand" "")))]
4598 [(set (match_operand:DI 0 "register_operand" "=r,r")
4600 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4601 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4605 [(set_attr "type" "shift,load")
4606 (set_attr "length" "4,4")])
4608 (define_expand "zero_extendhidi2"
4609 [(set (match_operand:DI 0 "register_operand" "")
4611 (match_operand:HI 1 "register_operand" "")))]
4616 [(set (match_operand:DI 0 "register_operand" "=r,r")
4618 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4619 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4623 [(set_attr "type" "shift,load")
4624 (set_attr "length" "4,4")])
4626 (define_expand "zero_extendsidi2"
4627 [(set (match_operand:DI 0 "register_operand" "")
4629 (match_operand:SI 1 "register_operand" "")))]
4634 [(set (match_operand:DI 0 "register_operand" "=r,r")
4636 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4637 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4641 [(set_attr "type" "shift,load")
4642 (set_attr "length" "4,4")])
4644 ;;- sign extension instructions
4646 (define_insn "extendhisi2"
4647 [(set (match_operand:SI 0 "register_operand" "=r")
4648 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4650 "{extrs|extrw,s} %1,31,16,%0"
4651 [(set_attr "type" "shift")
4652 (set_attr "length" "4")])
4654 (define_insn "extendqihi2"
4655 [(set (match_operand:HI 0 "register_operand" "=r")
4656 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4658 "{extrs|extrw,s} %1,31,8,%0"
4659 [(set_attr "type" "shift")
4660 (set_attr "length" "4")])
4662 (define_insn "extendqisi2"
4663 [(set (match_operand:SI 0 "register_operand" "=r")
4664 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4666 "{extrs|extrw,s} %1,31,8,%0"
4667 [(set_attr "type" "shift")
4668 (set_attr "length" "4")])
4670 (define_insn "extendqidi2"
4671 [(set (match_operand:DI 0 "register_operand" "=r")
4672 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4674 "extrd,s %1,63,8,%0"
4675 [(set_attr "type" "shift")
4676 (set_attr "length" "4")])
4678 (define_insn "extendhidi2"
4679 [(set (match_operand:DI 0 "register_operand" "=r")
4680 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4682 "extrd,s %1,63,16,%0"
4683 [(set_attr "type" "shift")
4684 (set_attr "length" "4")])
4686 (define_insn "extendsidi2"
4687 [(set (match_operand:DI 0 "register_operand" "=r")
4688 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4690 "extrd,s %1,63,32,%0"
4691 [(set_attr "type" "shift")
4692 (set_attr "length" "4")])
4695 ;; Conversions between float and double.
4697 (define_insn "extendsfdf2"
4698 [(set (match_operand:DF 0 "register_operand" "=f")
4700 (match_operand:SF 1 "register_operand" "f")))]
4701 "! TARGET_SOFT_FLOAT"
4702 "{fcnvff|fcnv},sgl,dbl %1,%0"
4703 [(set_attr "type" "fpalu")
4704 (set_attr "length" "4")])
4706 (define_insn "truncdfsf2"
4707 [(set (match_operand:SF 0 "register_operand" "=f")
4709 (match_operand:DF 1 "register_operand" "f")))]
4710 "! TARGET_SOFT_FLOAT"
4711 "{fcnvff|fcnv},dbl,sgl %1,%0"
4712 [(set_attr "type" "fpalu")
4713 (set_attr "length" "4")])
4715 ;; Conversion between fixed point and floating point.
4716 ;; Note that among the fix-to-float insns
4717 ;; the ones that start with SImode come first.
4718 ;; That is so that an operand that is a CONST_INT
4719 ;; (and therefore lacks a specific machine mode).
4720 ;; will be recognized as SImode (which is always valid)
4721 ;; rather than as QImode or HImode.
4723 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4724 ;; to be reloaded by putting the constant into memory.
4725 ;; It must come before the more general floatsisf2 pattern.
4727 [(set (match_operand:SF 0 "register_operand" "=f")
4728 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4729 "! TARGET_SOFT_FLOAT"
4730 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4731 [(set_attr "type" "fpalu")
4732 (set_attr "length" "8")])
4734 (define_insn "floatsisf2"
4735 [(set (match_operand:SF 0 "register_operand" "=f")
4736 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4737 "! TARGET_SOFT_FLOAT"
4738 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4739 [(set_attr "type" "fpalu")
4740 (set_attr "length" "4")])
4742 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4743 ;; to be reloaded by putting the constant into memory.
4744 ;; It must come before the more general floatsidf2 pattern.
4746 [(set (match_operand:DF 0 "register_operand" "=f")
4747 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4748 "! TARGET_SOFT_FLOAT"
4749 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4750 [(set_attr "type" "fpalu")
4751 (set_attr "length" "8")])
4753 (define_insn "floatsidf2"
4754 [(set (match_operand:DF 0 "register_operand" "=f")
4755 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4756 "! TARGET_SOFT_FLOAT"
4757 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4758 [(set_attr "type" "fpalu")
4759 (set_attr "length" "4")])
4761 (define_expand "floatunssisf2"
4762 [(set (subreg:SI (match_dup 2) 4)
4763 (match_operand:SI 1 "register_operand" ""))
4764 (set (subreg:SI (match_dup 2) 0)
4766 (set (match_operand:SF 0 "register_operand" "")
4767 (float:SF (match_dup 2)))]
4768 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4773 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4776 operands[2] = gen_reg_rtx (DImode);
4779 (define_expand "floatunssidf2"
4780 [(set (subreg:SI (match_dup 2) 4)
4781 (match_operand:SI 1 "register_operand" ""))
4782 (set (subreg:SI (match_dup 2) 0)
4784 (set (match_operand:DF 0 "register_operand" "")
4785 (float:DF (match_dup 2)))]
4786 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4791 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4794 operands[2] = gen_reg_rtx (DImode);
4797 (define_insn "floatdisf2"
4798 [(set (match_operand:SF 0 "register_operand" "=f")
4799 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4800 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4801 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4802 [(set_attr "type" "fpalu")
4803 (set_attr "length" "4")])
4805 (define_insn "floatdidf2"
4806 [(set (match_operand:DF 0 "register_operand" "=f")
4807 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4808 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4809 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4810 [(set_attr "type" "fpalu")
4811 (set_attr "length" "4")])
4813 ;; Convert a float to an actual integer.
4814 ;; Truncation is performed as part of the conversion.
4816 (define_insn "fix_truncsfsi2"
4817 [(set (match_operand:SI 0 "register_operand" "=f")
4818 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4819 "! TARGET_SOFT_FLOAT"
4820 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4821 [(set_attr "type" "fpalu")
4822 (set_attr "length" "4")])
4824 (define_insn "fix_truncdfsi2"
4825 [(set (match_operand:SI 0 "register_operand" "=f")
4826 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4827 "! TARGET_SOFT_FLOAT"
4828 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4829 [(set_attr "type" "fpalu")
4830 (set_attr "length" "4")])
4832 (define_insn "fix_truncsfdi2"
4833 [(set (match_operand:DI 0 "register_operand" "=f")
4834 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4835 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4836 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4837 [(set_attr "type" "fpalu")
4838 (set_attr "length" "4")])
4840 (define_insn "fix_truncdfdi2"
4841 [(set (match_operand:DI 0 "register_operand" "=f")
4842 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4843 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4844 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4845 [(set_attr "type" "fpalu")
4846 (set_attr "length" "4")])
4848 (define_insn "floatunssidf2_pa20"
4849 [(set (match_operand:DF 0 "register_operand" "=f")
4850 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4851 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4853 [(set_attr "type" "fpalu")
4854 (set_attr "length" "4")])
4856 (define_insn "floatunssisf2_pa20"
4857 [(set (match_operand:SF 0 "register_operand" "=f")
4858 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4859 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4861 [(set_attr "type" "fpalu")
4862 (set_attr "length" "4")])
4864 (define_insn "floatunsdisf2"
4865 [(set (match_operand:SF 0 "register_operand" "=f")
4866 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4867 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4868 "fcnv,udw,sgl %1,%0"
4869 [(set_attr "type" "fpalu")
4870 (set_attr "length" "4")])
4872 (define_insn "floatunsdidf2"
4873 [(set (match_operand:DF 0 "register_operand" "=f")
4874 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4875 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4876 "fcnv,udw,dbl %1,%0"
4877 [(set_attr "type" "fpalu")
4878 (set_attr "length" "4")])
4880 (define_insn "fixuns_truncsfsi2"
4881 [(set (match_operand:SI 0 "register_operand" "=f")
4882 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4883 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4884 "fcnv,t,sgl,uw %1,%0"
4885 [(set_attr "type" "fpalu")
4886 (set_attr "length" "4")])
4888 (define_insn "fixuns_truncdfsi2"
4889 [(set (match_operand:SI 0 "register_operand" "=f")
4890 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4891 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4892 "fcnv,t,dbl,uw %1,%0"
4893 [(set_attr "type" "fpalu")
4894 (set_attr "length" "4")])
4896 (define_insn "fixuns_truncsfdi2"
4897 [(set (match_operand:DI 0 "register_operand" "=f")
4898 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4899 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4900 "fcnv,t,sgl,udw %1,%0"
4901 [(set_attr "type" "fpalu")
4902 (set_attr "length" "4")])
4904 (define_insn "fixuns_truncdfdi2"
4905 [(set (match_operand:DI 0 "register_operand" "=f")
4906 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4907 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4908 "fcnv,t,dbl,udw %1,%0"
4909 [(set_attr "type" "fpalu")
4910 (set_attr "length" "4")])
4912 ;;- arithmetic instructions
4914 (define_expand "adddi3"
4915 [(set (match_operand:DI 0 "register_operand" "")
4916 (plus:DI (match_operand:DI 1 "register_operand" "")
4917 (match_operand:DI 2 "adddi3_operand" "")))]
4922 [(set (match_operand:DI 0 "register_operand" "=r")
4923 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4924 (match_operand:DI 2 "arith11_operand" "rI")))]
4928 if (GET_CODE (operands[2]) == CONST_INT)
4930 if (INTVAL (operands[2]) >= 0)
4931 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4933 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4936 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4938 [(set_attr "type" "binary")
4939 (set_attr "length" "8")])
4942 [(set (match_operand:DI 0 "register_operand" "=r,r")
4943 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4944 (match_operand:DI 2 "arith_operand" "r,J")))]
4949 [(set_attr "type" "binary,binary")
4950 (set_attr "pa_combine_type" "addmove")
4951 (set_attr "length" "4,4")])
4954 [(set (match_operand:DI 0 "register_operand" "=r")
4955 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4956 (match_operand:DI 2 "register_operand" "r")))]
4959 [(set_attr "type" "binary")
4960 (set_attr "length" "4")])
4963 [(set (match_operand:SI 0 "register_operand" "=r")
4964 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4965 (match_operand:SI 2 "register_operand" "r")))]
4968 [(set_attr "type" "binary")
4969 (set_attr "length" "4")])
4971 (define_expand "addvdi3"
4972 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4973 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
4974 (match_operand:DI 2 "arith11_operand" "")))
4975 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4976 (sign_extend:TI (match_dup 2)))
4977 (sign_extend:TI (plus:DI (match_dup 1)
4984 [(set (match_operand:DI 0 "register_operand" "=r,r")
4985 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
4986 (match_operand:DI 2 "arith11_operand" "r,I")))
4987 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4988 (sign_extend:TI (match_dup 2)))
4989 (sign_extend:TI (plus:DI (match_dup 1)
4995 addi,tsv,* %2,%1,%0"
4996 [(set_attr "type" "binary,binary")
4997 (set_attr "length" "4,4")])
5000 [(set (match_operand:DI 0 "register_operand" "=r")
5001 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5002 (match_operand:DI 2 "arith11_operand" "rI")))
5003 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5004 (sign_extend:TI (match_dup 2)))
5005 (sign_extend:TI (plus:DI (match_dup 1)
5011 if (GET_CODE (operands[2]) == CONST_INT)
5013 if (INTVAL (operands[2]) >= 0)
5014 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5016 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5019 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5021 [(set_attr "type" "binary")
5022 (set_attr "length" "8")])
5024 ;; define_splits to optimize cases of adding a constant integer
5025 ;; to a register when the constant does not fit in 14 bits. */
5027 [(set (match_operand:SI 0 "register_operand" "")
5028 (plus:SI (match_operand:SI 1 "register_operand" "")
5029 (match_operand:SI 2 "const_int_operand" "")))
5030 (clobber (match_operand:SI 4 "register_operand" ""))]
5031 "! cint_ok_for_move (INTVAL (operands[2]))
5032 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5033 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5034 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5037 int val = INTVAL (operands[2]);
5038 int low = (val < 0) ? -0x2000 : 0x1fff;
5039 int rest = val - low;
5041 operands[2] = GEN_INT (rest);
5042 operands[3] = GEN_INT (low);
5046 [(set (match_operand:SI 0 "register_operand" "")
5047 (plus:SI (match_operand:SI 1 "register_operand" "")
5048 (match_operand:SI 2 "const_int_operand" "")))
5049 (clobber (match_operand:SI 4 "register_operand" ""))]
5050 "! cint_ok_for_move (INTVAL (operands[2]))"
5051 [(set (match_dup 4) (match_dup 2))
5052 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5056 HOST_WIDE_INT intval = INTVAL (operands[2]);
5058 /* Try dividing the constant by 2, then 4, and finally 8 to see
5059 if we can get a constant which can be loaded into a register
5060 in a single instruction (cint_ok_for_move).
5062 If that fails, try to negate the constant and subtract it
5063 from our input operand. */
5064 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5066 operands[2] = GEN_INT (intval / 2);
5067 operands[3] = const2_rtx;
5069 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5071 operands[2] = GEN_INT (intval / 4);
5072 operands[3] = GEN_INT (4);
5074 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5076 operands[2] = GEN_INT (intval / 8);
5077 operands[3] = GEN_INT (8);
5079 else if (cint_ok_for_move (-intval))
5081 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5082 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5089 (define_insn "addsi3"
5090 [(set (match_operand:SI 0 "register_operand" "=r,r")
5091 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5092 (match_operand:SI 2 "arith_operand" "r,J")))]
5095 {addl|add,l} %1,%2,%0
5097 [(set_attr "type" "binary,binary")
5098 (set_attr "pa_combine_type" "addmove")
5099 (set_attr "length" "4,4")])
5101 (define_insn "addvsi3"
5102 [(set (match_operand:SI 0 "register_operand" "=r,r")
5103 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5104 (match_operand:SI 2 "arith11_operand" "r,I")))
5105 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5106 (sign_extend:DI (match_dup 2)))
5107 (sign_extend:DI (plus:SI (match_dup 1)
5112 {addo|add,tsv} %2,%1,%0
5113 {addio|addi,tsv} %2,%1,%0"
5114 [(set_attr "type" "binary,binary")
5115 (set_attr "length" "4,4")])
5117 (define_expand "subdi3"
5118 [(set (match_operand:DI 0 "register_operand" "")
5119 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5120 (match_operand:DI 2 "reg_or_0_operand" "")))]
5125 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5126 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5127 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5133 [(set_attr "type" "binary,binary,move")
5134 (set_attr "length" "4,4,4")])
5137 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5138 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5139 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5143 if (GET_CODE (operands[1]) == CONST_INT)
5145 if (INTVAL (operands[1]) >= 0)
5146 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5148 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5151 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5153 [(set_attr "type" "binary")
5154 (set (attr "length")
5155 (if_then_else (eq_attr "alternative" "0")
5157 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5162 (define_expand "subvdi3"
5163 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5164 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5165 (match_operand:DI 2 "reg_or_0_operand" "")))
5166 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5167 (sign_extend:TI (match_dup 2)))
5168 (sign_extend:TI (minus:DI (match_dup 1)
5175 [(set (match_operand:DI 0 "register_operand" "=r,r")
5176 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5177 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5178 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5179 (sign_extend:TI (match_dup 2)))
5180 (sign_extend:TI (minus:DI (match_dup 1)
5185 {subo|sub,tsv} %1,%2,%0
5186 {subio|subi,tsv} %1,%2,%0"
5187 [(set_attr "type" "binary,binary")
5188 (set_attr "length" "4,4")])
5191 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5192 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5193 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5194 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5195 (sign_extend:TI (match_dup 2)))
5196 (sign_extend:TI (minus:DI (match_dup 1)
5202 if (GET_CODE (operands[1]) == CONST_INT)
5204 if (INTVAL (operands[1]) >= 0)
5205 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5207 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5210 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5212 [(set_attr "type" "binary,binary")
5213 (set (attr "length")
5214 (if_then_else (eq_attr "alternative" "0")
5216 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5221 (define_expand "subsi3"
5222 [(set (match_operand:SI 0 "register_operand" "")
5223 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5224 (match_operand:SI 2 "register_operand" "")))]
5229 [(set (match_operand:SI 0 "register_operand" "=r,r")
5230 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5231 (match_operand:SI 2 "register_operand" "r,r")))]
5236 [(set_attr "type" "binary,binary")
5237 (set_attr "length" "4,4")])
5240 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5241 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5242 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5248 [(set_attr "type" "binary,binary,move")
5249 (set_attr "length" "4,4,4")])
5251 (define_insn "subvsi3"
5252 [(set (match_operand:SI 0 "register_operand" "=r,r")
5253 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5254 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5255 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5256 (sign_extend:DI (match_dup 2)))
5257 (sign_extend:DI (minus:SI (match_dup 1)
5262 {subo|sub,tsv} %1,%2,%0
5263 {subio|subi,tsv} %1,%2,%0"
5264 [(set_attr "type" "binary,binary")
5265 (set_attr "length" "4,4")])
5267 ;; Clobbering a "register_operand" instead of a match_scratch
5268 ;; in operand3 of millicode calls avoids spilling %r1 and
5269 ;; produces better code.
5271 ;; The mulsi3 insns set up registers for the millicode call.
5272 (define_expand "mulsi3"
5273 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5274 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5275 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5276 (clobber (match_dup 3))
5277 (clobber (reg:SI 26))
5278 (clobber (reg:SI 25))
5279 (clobber (match_dup 4))])
5280 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5284 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5285 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5287 rtx scratch = gen_reg_rtx (DImode);
5288 operands[1] = force_reg (SImode, operands[1]);
5289 operands[2] = force_reg (SImode, operands[2]);
5290 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5291 emit_insn (gen_movsi (operands[0],
5292 gen_rtx_SUBREG (SImode, scratch,
5293 GET_MODE_SIZE (SImode))));
5296 operands[3] = gen_reg_rtx (SImode);
5299 (define_insn "umulsidi3"
5300 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5301 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5302 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5303 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5305 [(set_attr "type" "fpmuldbl")
5306 (set_attr "length" "4")])
5309 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5310 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5311 (match_operand:DI 2 "uint32_operand" "f")))]
5312 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5314 [(set_attr "type" "fpmuldbl")
5315 (set_attr "length" "4")])
5318 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5319 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5320 (match_operand:DI 2 "uint32_operand" "f")))]
5321 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5323 [(set_attr "type" "fpmuldbl")
5324 (set_attr "length" "4")])
5327 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5328 (clobber (match_operand:SI 0 "register_operand" "=a"))
5329 (clobber (reg:SI 26))
5330 (clobber (reg:SI 25))
5331 (clobber (reg:SI 31))]
5333 "* return output_mul_insn (0, insn);"
5334 [(set_attr "type" "milli")
5335 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5338 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5339 (clobber (match_operand:SI 0 "register_operand" "=a"))
5340 (clobber (reg:SI 26))
5341 (clobber (reg:SI 25))
5342 (clobber (reg:SI 2))]
5344 "* return output_mul_insn (0, insn);"
5345 [(set_attr "type" "milli")
5346 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5348 (define_expand "muldi3"
5349 [(set (match_operand:DI 0 "register_operand" "")
5350 (mult:DI (match_operand:DI 1 "register_operand" "")
5351 (match_operand:DI 2 "register_operand" "")))]
5352 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5355 rtx low_product = gen_reg_rtx (DImode);
5356 rtx cross_product1 = gen_reg_rtx (DImode);
5357 rtx cross_product2 = gen_reg_rtx (DImode);
5358 rtx cross_scratch = gen_reg_rtx (DImode);
5359 rtx cross_product = gen_reg_rtx (DImode);
5360 rtx op1l, op1r, op2l, op2r;
5361 rtx op1shifted, op2shifted;
5363 op1shifted = gen_reg_rtx (DImode);
5364 op2shifted = gen_reg_rtx (DImode);
5365 op1l = gen_reg_rtx (SImode);
5366 op1r = gen_reg_rtx (SImode);
5367 op2l = gen_reg_rtx (SImode);
5368 op2r = gen_reg_rtx (SImode);
5370 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5372 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5374 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5375 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5376 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5377 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5379 /* Emit multiplies for the cross products. */
5380 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5381 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5383 /* Emit a multiply for the low sub-word. */
5384 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5386 /* Sum the cross products and shift them into proper position. */
5387 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5388 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5390 /* Add the cross product to the low product and store the result
5391 into the output operand . */
5392 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5396 ;;; Division and mod.
5397 (define_expand "divsi3"
5398 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5399 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5400 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5401 (clobber (match_dup 3))
5402 (clobber (match_dup 4))
5403 (clobber (reg:SI 26))
5404 (clobber (reg:SI 25))
5405 (clobber (match_dup 5))])
5406 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5410 operands[3] = gen_reg_rtx (SImode);
5413 operands[5] = gen_rtx_REG (SImode, 2);
5414 operands[4] = operands[5];
5418 operands[5] = gen_rtx_REG (SImode, 31);
5419 operands[4] = gen_reg_rtx (SImode);
5421 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5427 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5428 (clobber (match_operand:SI 1 "register_operand" "=a"))
5429 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5430 (clobber (reg:SI 26))
5431 (clobber (reg:SI 25))
5432 (clobber (reg:SI 31))]
5435 return output_div_insn (operands, 0, insn);"
5436 [(set_attr "type" "milli")
5437 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5441 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5442 (clobber (match_operand:SI 1 "register_operand" "=a"))
5443 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5444 (clobber (reg:SI 26))
5445 (clobber (reg:SI 25))
5446 (clobber (reg:SI 2))]
5449 return output_div_insn (operands, 0, insn);"
5450 [(set_attr "type" "milli")
5451 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5453 (define_expand "udivsi3"
5454 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5455 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5456 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5457 (clobber (match_dup 3))
5458 (clobber (match_dup 4))
5459 (clobber (reg:SI 26))
5460 (clobber (reg:SI 25))
5461 (clobber (match_dup 5))])
5462 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5466 operands[3] = gen_reg_rtx (SImode);
5470 operands[5] = gen_rtx_REG (SImode, 2);
5471 operands[4] = operands[5];
5475 operands[5] = gen_rtx_REG (SImode, 31);
5476 operands[4] = gen_reg_rtx (SImode);
5478 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5484 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5485 (clobber (match_operand:SI 1 "register_operand" "=a"))
5486 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5487 (clobber (reg:SI 26))
5488 (clobber (reg:SI 25))
5489 (clobber (reg:SI 31))]
5492 return output_div_insn (operands, 1, insn);"
5493 [(set_attr "type" "milli")
5494 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5498 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5499 (clobber (match_operand:SI 1 "register_operand" "=a"))
5500 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5501 (clobber (reg:SI 26))
5502 (clobber (reg:SI 25))
5503 (clobber (reg:SI 2))]
5506 return output_div_insn (operands, 1, insn);"
5507 [(set_attr "type" "milli")
5508 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5510 (define_expand "modsi3"
5511 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5512 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5513 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5514 (clobber (match_dup 3))
5515 (clobber (match_dup 4))
5516 (clobber (reg:SI 26))
5517 (clobber (reg:SI 25))
5518 (clobber (match_dup 5))])
5519 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5525 operands[5] = gen_rtx_REG (SImode, 2);
5526 operands[4] = operands[5];
5530 operands[5] = gen_rtx_REG (SImode, 31);
5531 operands[4] = gen_reg_rtx (SImode);
5533 operands[3] = gen_reg_rtx (SImode);
5537 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5538 (clobber (match_operand:SI 0 "register_operand" "=a"))
5539 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5540 (clobber (reg:SI 26))
5541 (clobber (reg:SI 25))
5542 (clobber (reg:SI 31))]
5545 return output_mod_insn (0, insn);"
5546 [(set_attr "type" "milli")
5547 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5550 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5551 (clobber (match_operand:SI 0 "register_operand" "=a"))
5552 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5553 (clobber (reg:SI 26))
5554 (clobber (reg:SI 25))
5555 (clobber (reg:SI 2))]
5558 return output_mod_insn (0, insn);"
5559 [(set_attr "type" "milli")
5560 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5562 (define_expand "umodsi3"
5563 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5564 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5565 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5566 (clobber (match_dup 3))
5567 (clobber (match_dup 4))
5568 (clobber (reg:SI 26))
5569 (clobber (reg:SI 25))
5570 (clobber (match_dup 5))])
5571 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5577 operands[5] = gen_rtx_REG (SImode, 2);
5578 operands[4] = operands[5];
5582 operands[5] = gen_rtx_REG (SImode, 31);
5583 operands[4] = gen_reg_rtx (SImode);
5585 operands[3] = gen_reg_rtx (SImode);
5589 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5590 (clobber (match_operand:SI 0 "register_operand" "=a"))
5591 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5592 (clobber (reg:SI 26))
5593 (clobber (reg:SI 25))
5594 (clobber (reg:SI 31))]
5597 return output_mod_insn (1, insn);"
5598 [(set_attr "type" "milli")
5599 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5602 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5603 (clobber (match_operand:SI 0 "register_operand" "=a"))
5604 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5605 (clobber (reg:SI 26))
5606 (clobber (reg:SI 25))
5607 (clobber (reg:SI 2))]
5610 return output_mod_insn (1, insn);"
5611 [(set_attr "type" "milli")
5612 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5614 ;;- and instructions
5615 ;; We define DImode `and` so with DImode `not` we can get
5616 ;; DImode `andn`. Other combinations are possible.
5618 (define_expand "anddi3"
5619 [(set (match_operand:DI 0 "register_operand" "")
5620 (and:DI (match_operand:DI 1 "register_operand" "")
5621 (match_operand:DI 2 "and_operand" "")))]
5625 /* Both operands must be register operands. */
5626 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5631 [(set (match_operand:DI 0 "register_operand" "=r")
5632 (and:DI (match_operand:DI 1 "register_operand" "%r")
5633 (match_operand:DI 2 "register_operand" "r")))]
5635 "and %1,%2,%0\;and %R1,%R2,%R0"
5636 [(set_attr "type" "binary")
5637 (set_attr "length" "8")])
5640 [(set (match_operand:DI 0 "register_operand" "=r,r")
5641 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5642 (match_operand:DI 2 "and_operand" "rO,P")))]
5644 "* return output_64bit_and (operands); "
5645 [(set_attr "type" "binary")
5646 (set_attr "length" "4")])
5648 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5649 ; constant with ldil;ldo.
5650 (define_insn "andsi3"
5651 [(set (match_operand:SI 0 "register_operand" "=r,r")
5652 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5653 (match_operand:SI 2 "and_operand" "rO,P")))]
5655 "* return output_and (operands); "
5656 [(set_attr "type" "binary,shift")
5657 (set_attr "length" "4,4")])
5660 [(set (match_operand:DI 0 "register_operand" "=r")
5661 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5662 (match_operand:DI 2 "register_operand" "r")))]
5664 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5665 [(set_attr "type" "binary")
5666 (set_attr "length" "8")])
5669 [(set (match_operand:DI 0 "register_operand" "=r")
5670 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5671 (match_operand:DI 2 "register_operand" "r")))]
5674 [(set_attr "type" "binary")
5675 (set_attr "length" "4")])
5678 [(set (match_operand:SI 0 "register_operand" "=r")
5679 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5680 (match_operand:SI 2 "register_operand" "r")))]
5683 [(set_attr "type" "binary")
5684 (set_attr "length" "4")])
5686 (define_expand "iordi3"
5687 [(set (match_operand:DI 0 "register_operand" "")
5688 (ior:DI (match_operand:DI 1 "register_operand" "")
5689 (match_operand:DI 2 "ior_operand" "")))]
5693 /* Both operands must be register operands. */
5694 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5699 [(set (match_operand:DI 0 "register_operand" "=r")
5700 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5701 (match_operand:DI 2 "register_operand" "r")))]
5703 "or %1,%2,%0\;or %R1,%R2,%R0"
5704 [(set_attr "type" "binary")
5705 (set_attr "length" "8")])
5708 [(set (match_operand:DI 0 "register_operand" "=r,r")
5709 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5710 (match_operand:DI 2 "ior_operand" "M,i")))]
5712 "* return output_64bit_ior (operands); "
5713 [(set_attr "type" "binary,shift")
5714 (set_attr "length" "4,4")])
5717 [(set (match_operand:DI 0 "register_operand" "=r")
5718 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5719 (match_operand:DI 2 "register_operand" "r")))]
5722 [(set_attr "type" "binary")
5723 (set_attr "length" "4")])
5725 ;; Need a define_expand because we've run out of CONST_OK... characters.
5726 (define_expand "iorsi3"
5727 [(set (match_operand:SI 0 "register_operand" "")
5728 (ior:SI (match_operand:SI 1 "register_operand" "")
5729 (match_operand:SI 2 "arith32_operand" "")))]
5733 if (! (ior_operand (operands[2], SImode)
5734 || register_operand (operands[2], SImode)))
5735 operands[2] = force_reg (SImode, operands[2]);
5739 [(set (match_operand:SI 0 "register_operand" "=r,r")
5740 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5741 (match_operand:SI 2 "ior_operand" "M,i")))]
5743 "* return output_ior (operands); "
5744 [(set_attr "type" "binary,shift")
5745 (set_attr "length" "4,4")])
5748 [(set (match_operand:SI 0 "register_operand" "=r")
5749 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5750 (match_operand:SI 2 "register_operand" "r")))]
5753 [(set_attr "type" "binary")
5754 (set_attr "length" "4")])
5756 (define_expand "xordi3"
5757 [(set (match_operand:DI 0 "register_operand" "")
5758 (xor:DI (match_operand:DI 1 "register_operand" "")
5759 (match_operand:DI 2 "register_operand" "")))]
5766 [(set (match_operand:DI 0 "register_operand" "=r")
5767 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5768 (match_operand:DI 2 "register_operand" "r")))]
5770 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5771 [(set_attr "type" "binary")
5772 (set_attr "length" "8")])
5775 [(set (match_operand:DI 0 "register_operand" "=r")
5776 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5777 (match_operand:DI 2 "register_operand" "r")))]
5780 [(set_attr "type" "binary")
5781 (set_attr "length" "4")])
5783 (define_insn "xorsi3"
5784 [(set (match_operand:SI 0 "register_operand" "=r")
5785 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5786 (match_operand:SI 2 "register_operand" "r")))]
5789 [(set_attr "type" "binary")
5790 (set_attr "length" "4")])
5792 (define_expand "negdi2"
5793 [(set (match_operand:DI 0 "register_operand" "")
5794 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5799 [(set (match_operand:DI 0 "register_operand" "=r")
5800 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5802 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5803 [(set_attr "type" "unary")
5804 (set_attr "length" "8")])
5807 [(set (match_operand:DI 0 "register_operand" "=r")
5808 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5811 [(set_attr "type" "unary")
5812 (set_attr "length" "4")])
5814 (define_expand "negvdi2"
5815 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5816 (neg:DI (match_operand:DI 1 "register_operand" "")))
5817 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5818 (sign_extend:TI (neg:DI (match_dup 1))))
5824 [(set (match_operand:DI 0 "register_operand" "=r")
5825 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5826 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5827 (sign_extend:TI (neg:DI (match_dup 1))))
5830 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
5831 [(set_attr "type" "unary")
5832 (set_attr "length" "8")])
5835 [(set (match_operand:DI 0 "register_operand" "=r")
5836 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5837 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5838 (sign_extend:TI (neg:DI (match_dup 1))))
5841 "sub,tsv %%r0,%1,%0"
5842 [(set_attr "type" "unary")
5843 (set_attr "length" "4")])
5845 (define_insn "negsi2"
5846 [(set (match_operand:SI 0 "register_operand" "=r")
5847 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5850 [(set_attr "type" "unary")
5851 (set_attr "length" "4")])
5853 (define_insn "negvsi2"
5854 [(set (match_operand:SI 0 "register_operand" "=r")
5855 (neg:SI (match_operand:SI 1 "register_operand" "r")))
5856 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
5857 (sign_extend:DI (neg:SI (match_dup 1))))
5860 "{subo|sub,tsv} %%r0,%1,%0"
5861 [(set_attr "type" "unary")
5862 (set_attr "length" "4")])
5864 (define_expand "one_cmpldi2"
5865 [(set (match_operand:DI 0 "register_operand" "")
5866 (not:DI (match_operand:DI 1 "register_operand" "")))]
5873 [(set (match_operand:DI 0 "register_operand" "=r")
5874 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5876 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5877 [(set_attr "type" "unary")
5878 (set_attr "length" "8")])
5881 [(set (match_operand:DI 0 "register_operand" "=r")
5882 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5885 [(set_attr "type" "unary")
5886 (set_attr "length" "4")])
5888 (define_insn "one_cmplsi2"
5889 [(set (match_operand:SI 0 "register_operand" "=r")
5890 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5893 [(set_attr "type" "unary")
5894 (set_attr "length" "4")])
5896 ;; Floating point arithmetic instructions.
5898 (define_insn "adddf3"
5899 [(set (match_operand:DF 0 "register_operand" "=f")
5900 (plus:DF (match_operand:DF 1 "register_operand" "f")
5901 (match_operand:DF 2 "register_operand" "f")))]
5902 "! TARGET_SOFT_FLOAT"
5904 [(set_attr "type" "fpalu")
5905 (set_attr "pa_combine_type" "faddsub")
5906 (set_attr "length" "4")])
5908 (define_insn "addsf3"
5909 [(set (match_operand:SF 0 "register_operand" "=f")
5910 (plus:SF (match_operand:SF 1 "register_operand" "f")
5911 (match_operand:SF 2 "register_operand" "f")))]
5912 "! TARGET_SOFT_FLOAT"
5914 [(set_attr "type" "fpalu")
5915 (set_attr "pa_combine_type" "faddsub")
5916 (set_attr "length" "4")])
5918 (define_insn "subdf3"
5919 [(set (match_operand:DF 0 "register_operand" "=f")
5920 (minus:DF (match_operand:DF 1 "register_operand" "f")
5921 (match_operand:DF 2 "register_operand" "f")))]
5922 "! TARGET_SOFT_FLOAT"
5924 [(set_attr "type" "fpalu")
5925 (set_attr "pa_combine_type" "faddsub")
5926 (set_attr "length" "4")])
5928 (define_insn "subsf3"
5929 [(set (match_operand:SF 0 "register_operand" "=f")
5930 (minus:SF (match_operand:SF 1 "register_operand" "f")
5931 (match_operand:SF 2 "register_operand" "f")))]
5932 "! TARGET_SOFT_FLOAT"
5934 [(set_attr "type" "fpalu")
5935 (set_attr "pa_combine_type" "faddsub")
5936 (set_attr "length" "4")])
5938 (define_insn "muldf3"
5939 [(set (match_operand:DF 0 "register_operand" "=f")
5940 (mult:DF (match_operand:DF 1 "register_operand" "f")
5941 (match_operand:DF 2 "register_operand" "f")))]
5942 "! TARGET_SOFT_FLOAT"
5944 [(set_attr "type" "fpmuldbl")
5945 (set_attr "pa_combine_type" "fmpy")
5946 (set_attr "length" "4")])
5948 (define_insn "mulsf3"
5949 [(set (match_operand:SF 0 "register_operand" "=f")
5950 (mult:SF (match_operand:SF 1 "register_operand" "f")
5951 (match_operand:SF 2 "register_operand" "f")))]
5952 "! TARGET_SOFT_FLOAT"
5954 [(set_attr "type" "fpmulsgl")
5955 (set_attr "pa_combine_type" "fmpy")
5956 (set_attr "length" "4")])
5958 (define_insn "divdf3"
5959 [(set (match_operand:DF 0 "register_operand" "=f")
5960 (div:DF (match_operand:DF 1 "register_operand" "f")
5961 (match_operand:DF 2 "register_operand" "f")))]
5962 "! TARGET_SOFT_FLOAT"
5964 [(set_attr "type" "fpdivdbl")
5965 (set_attr "length" "4")])
5967 (define_insn "divsf3"
5968 [(set (match_operand:SF 0 "register_operand" "=f")
5969 (div:SF (match_operand:SF 1 "register_operand" "f")
5970 (match_operand:SF 2 "register_operand" "f")))]
5971 "! TARGET_SOFT_FLOAT"
5973 [(set_attr "type" "fpdivsgl")
5974 (set_attr "length" "4")])
5976 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5977 ;; negation can be done by subtracting from plus zero. However, this
5978 ;; violates the IEEE standard when negating plus and minus zero.
5979 (define_expand "negdf2"
5980 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5981 (neg:DF (match_operand:DF 1 "register_operand" "")))
5982 (use (match_dup 2))])]
5983 "! TARGET_SOFT_FLOAT"
5985 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5986 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5989 operands[2] = force_reg (DFmode,
5990 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5991 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5996 (define_insn "negdf2_fast"
5997 [(set (match_operand:DF 0 "register_operand" "=f")
5998 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5999 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6003 return \"fneg,dbl %1,%0\";
6005 return \"fsub,dbl %%fr0,%1,%0\";
6007 [(set_attr "type" "fpalu")
6008 (set_attr "length" "4")])
6010 (define_expand "negsf2"
6011 [(parallel [(set (match_operand:SF 0 "register_operand" "")
6012 (neg:SF (match_operand:SF 1 "register_operand" "")))
6013 (use (match_dup 2))])]
6014 "! TARGET_SOFT_FLOAT"
6016 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6017 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6020 operands[2] = force_reg (SFmode,
6021 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
6022 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
6027 (define_insn "negsf2_fast"
6028 [(set (match_operand:SF 0 "register_operand" "=f")
6029 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6030 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6034 return \"fneg,sgl %1,%0\";
6036 return \"fsub,sgl %%fr0,%1,%0\";
6038 [(set_attr "type" "fpalu")
6039 (set_attr "length" "4")])
6041 (define_insn "absdf2"
6042 [(set (match_operand:DF 0 "register_operand" "=f")
6043 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6044 "! TARGET_SOFT_FLOAT"
6046 [(set_attr "type" "fpalu")
6047 (set_attr "length" "4")])
6049 (define_insn "abssf2"
6050 [(set (match_operand:SF 0 "register_operand" "=f")
6051 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6052 "! TARGET_SOFT_FLOAT"
6054 [(set_attr "type" "fpalu")
6055 (set_attr "length" "4")])
6057 (define_insn "sqrtdf2"
6058 [(set (match_operand:DF 0 "register_operand" "=f")
6059 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6060 "! TARGET_SOFT_FLOAT"
6062 [(set_attr "type" "fpsqrtdbl")
6063 (set_attr "length" "4")])
6065 (define_insn "sqrtsf2"
6066 [(set (match_operand:SF 0 "register_operand" "=f")
6067 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6068 "! TARGET_SOFT_FLOAT"
6070 [(set_attr "type" "fpsqrtsgl")
6071 (set_attr "length" "4")])
6073 ;; PA 2.0 floating point instructions
6077 [(set (match_operand:DF 0 "register_operand" "=f")
6078 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6079 (match_operand:DF 2 "register_operand" "f"))
6080 (match_operand:DF 3 "register_operand" "f")))]
6081 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6082 "fmpyfadd,dbl %1,%2,%3,%0"
6083 [(set_attr "type" "fpmuldbl")
6084 (set_attr "length" "4")])
6087 [(set (match_operand:DF 0 "register_operand" "=f")
6088 (plus:DF (match_operand:DF 1 "register_operand" "f")
6089 (mult:DF (match_operand:DF 2 "register_operand" "f")
6090 (match_operand:DF 3 "register_operand" "f"))))]
6091 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6092 "fmpyfadd,dbl %2,%3,%1,%0"
6093 [(set_attr "type" "fpmuldbl")
6094 (set_attr "length" "4")])
6097 [(set (match_operand:SF 0 "register_operand" "=f")
6098 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6099 (match_operand:SF 2 "register_operand" "f"))
6100 (match_operand:SF 3 "register_operand" "f")))]
6101 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6102 "fmpyfadd,sgl %1,%2,%3,%0"
6103 [(set_attr "type" "fpmulsgl")
6104 (set_attr "length" "4")])
6107 [(set (match_operand:SF 0 "register_operand" "=f")
6108 (plus:SF (match_operand:SF 1 "register_operand" "f")
6109 (mult:SF (match_operand:SF 2 "register_operand" "f")
6110 (match_operand:SF 3 "register_operand" "f"))))]
6111 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6112 "fmpyfadd,sgl %2,%3,%1,%0"
6113 [(set_attr "type" "fpmulsgl")
6114 (set_attr "length" "4")])
6116 ; fmpynfadd patterns
6118 [(set (match_operand:DF 0 "register_operand" "=f")
6119 (minus:DF (match_operand:DF 1 "register_operand" "f")
6120 (mult:DF (match_operand:DF 2 "register_operand" "f")
6121 (match_operand:DF 3 "register_operand" "f"))))]
6122 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6123 "fmpynfadd,dbl %2,%3,%1,%0"
6124 [(set_attr "type" "fpmuldbl")
6125 (set_attr "length" "4")])
6128 [(set (match_operand:SF 0 "register_operand" "=f")
6129 (minus:SF (match_operand:SF 1 "register_operand" "f")
6130 (mult:SF (match_operand:SF 2 "register_operand" "f")
6131 (match_operand:SF 3 "register_operand" "f"))))]
6132 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6133 "fmpynfadd,sgl %2,%3,%1,%0"
6134 [(set_attr "type" "fpmulsgl")
6135 (set_attr "length" "4")])
6139 [(set (match_operand:DF 0 "register_operand" "=f")
6140 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6141 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6143 [(set_attr "type" "fpalu")
6144 (set_attr "length" "4")])
6147 [(set (match_operand:SF 0 "register_operand" "=f")
6148 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6149 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6151 [(set_attr "type" "fpalu")
6152 (set_attr "length" "4")])
6154 ;; Generating a fused multiply sequence is a win for this case as it will
6155 ;; reduce the latency for the fused case without impacting the plain
6158 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6159 ;; perform two operations with the result of the first feeding the second.
6161 [(set (match_operand:DF 0 "register_operand" "=f")
6162 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6163 (match_operand:DF 2 "register_operand" "f"))
6164 (match_operand:DF 3 "register_operand" "f")))
6165 (set (match_operand:DF 4 "register_operand" "=&f")
6166 (mult:DF (match_dup 1) (match_dup 2)))]
6167 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6168 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6169 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6171 [(set_attr "type" "fpmuldbl")
6172 (set_attr "length" "8")])
6174 ;; We want to split this up during scheduling since we want both insns
6175 ;; to schedule independently.
6177 [(set (match_operand:DF 0 "register_operand" "")
6178 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6179 (match_operand:DF 2 "register_operand" ""))
6180 (match_operand:DF 3 "register_operand" "")))
6181 (set (match_operand:DF 4 "register_operand" "")
6182 (mult:DF (match_dup 1) (match_dup 2)))]
6183 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6184 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6185 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6190 [(set (match_operand:SF 0 "register_operand" "=f")
6191 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6192 (match_operand:SF 2 "register_operand" "f"))
6193 (match_operand:SF 3 "register_operand" "f")))
6194 (set (match_operand:SF 4 "register_operand" "=&f")
6195 (mult:SF (match_dup 1) (match_dup 2)))]
6196 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6197 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6198 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6200 [(set_attr "type" "fpmuldbl")
6201 (set_attr "length" "8")])
6203 ;; We want to split this up during scheduling since we want both insns
6204 ;; to schedule independently.
6206 [(set (match_operand:SF 0 "register_operand" "")
6207 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6208 (match_operand:SF 2 "register_operand" ""))
6209 (match_operand:SF 3 "register_operand" "")))
6210 (set (match_operand:SF 4 "register_operand" "")
6211 (mult:SF (match_dup 1) (match_dup 2)))]
6212 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6213 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6214 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6218 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6221 [(set (match_operand:DF 0 "register_operand" "=f")
6222 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6223 (match_operand:DF 2 "register_operand" "f"))))]
6224 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6225 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6226 [(set_attr "type" "fpmuldbl")
6227 (set_attr "length" "4")])
6230 [(set (match_operand:SF 0 "register_operand" "=f")
6231 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6232 (match_operand:SF 2 "register_operand" "f"))))]
6233 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6234 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6235 [(set_attr "type" "fpmuldbl")
6236 (set_attr "length" "4")])
6239 [(set (match_operand:DF 0 "register_operand" "=f")
6240 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6241 (match_operand:DF 2 "register_operand" "f"))))
6242 (set (match_operand:DF 3 "register_operand" "=&f")
6243 (mult:DF (match_dup 1) (match_dup 2)))]
6244 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6245 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6246 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6248 [(set_attr "type" "fpmuldbl")
6249 (set_attr "length" "8")])
6252 [(set (match_operand:DF 0 "register_operand" "")
6253 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6254 (match_operand:DF 2 "register_operand" ""))))
6255 (set (match_operand:DF 3 "register_operand" "")
6256 (mult:DF (match_dup 1) (match_dup 2)))]
6257 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6258 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6259 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6263 [(set (match_operand:SF 0 "register_operand" "=f")
6264 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6265 (match_operand:SF 2 "register_operand" "f"))))
6266 (set (match_operand:SF 3 "register_operand" "=&f")
6267 (mult:SF (match_dup 1) (match_dup 2)))]
6268 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6269 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6270 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6272 [(set_attr "type" "fpmuldbl")
6273 (set_attr "length" "8")])
6276 [(set (match_operand:SF 0 "register_operand" "")
6277 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6278 (match_operand:SF 2 "register_operand" ""))))
6279 (set (match_operand:SF 3 "register_operand" "")
6280 (mult:SF (match_dup 1) (match_dup 2)))]
6281 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6282 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6283 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6286 ;; Now fused multiplies with the result of the multiply negated.
6288 [(set (match_operand:DF 0 "register_operand" "=f")
6289 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6290 (match_operand:DF 2 "register_operand" "f")))
6291 (match_operand:DF 3 "register_operand" "f")))]
6292 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6293 "fmpynfadd,dbl %1,%2,%3,%0"
6294 [(set_attr "type" "fpmuldbl")
6295 (set_attr "length" "4")])
6298 [(set (match_operand:SF 0 "register_operand" "=f")
6299 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6300 (match_operand:SF 2 "register_operand" "f")))
6301 (match_operand:SF 3 "register_operand" "f")))]
6302 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6303 "fmpynfadd,sgl %1,%2,%3,%0"
6304 [(set_attr "type" "fpmuldbl")
6305 (set_attr "length" "4")])
6308 [(set (match_operand:DF 0 "register_operand" "=f")
6309 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6310 (match_operand:DF 2 "register_operand" "f")))
6311 (match_operand:DF 3 "register_operand" "f")))
6312 (set (match_operand:DF 4 "register_operand" "=&f")
6313 (mult:DF (match_dup 1) (match_dup 2)))]
6314 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6315 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6316 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6318 [(set_attr "type" "fpmuldbl")
6319 (set_attr "length" "8")])
6322 [(set (match_operand:DF 0 "register_operand" "")
6323 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6324 (match_operand:DF 2 "register_operand" "")))
6325 (match_operand:DF 3 "register_operand" "")))
6326 (set (match_operand:DF 4 "register_operand" "")
6327 (mult:DF (match_dup 1) (match_dup 2)))]
6328 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6329 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6330 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6335 [(set (match_operand:SF 0 "register_operand" "=f")
6336 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6337 (match_operand:SF 2 "register_operand" "f")))
6338 (match_operand:SF 3 "register_operand" "f")))
6339 (set (match_operand:SF 4 "register_operand" "=&f")
6340 (mult:SF (match_dup 1) (match_dup 2)))]
6341 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6342 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6343 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6345 [(set_attr "type" "fpmuldbl")
6346 (set_attr "length" "8")])
6349 [(set (match_operand:SF 0 "register_operand" "")
6350 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6351 (match_operand:SF 2 "register_operand" "")))
6352 (match_operand:SF 3 "register_operand" "")))
6353 (set (match_operand:SF 4 "register_operand" "")
6354 (mult:SF (match_dup 1) (match_dup 2)))]
6355 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6356 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6357 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6362 [(set (match_operand:DF 0 "register_operand" "=f")
6363 (minus:DF (match_operand:DF 3 "register_operand" "f")
6364 (mult:DF (match_operand:DF 1 "register_operand" "f")
6365 (match_operand:DF 2 "register_operand" "f"))))
6366 (set (match_operand:DF 4 "register_operand" "=&f")
6367 (mult:DF (match_dup 1) (match_dup 2)))]
6368 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6369 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6370 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6372 [(set_attr "type" "fpmuldbl")
6373 (set_attr "length" "8")])
6376 [(set (match_operand:DF 0 "register_operand" "")
6377 (minus:DF (match_operand:DF 3 "register_operand" "")
6378 (mult:DF (match_operand:DF 1 "register_operand" "")
6379 (match_operand:DF 2 "register_operand" ""))))
6380 (set (match_operand:DF 4 "register_operand" "")
6381 (mult:DF (match_dup 1) (match_dup 2)))]
6382 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6383 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6384 (set (match_dup 0) (minus:DF (match_dup 3)
6385 (mult:DF (match_dup 1) (match_dup 2))))]
6389 [(set (match_operand:SF 0 "register_operand" "=f")
6390 (minus:SF (match_operand:SF 3 "register_operand" "f")
6391 (mult:SF (match_operand:SF 1 "register_operand" "f")
6392 (match_operand:SF 2 "register_operand" "f"))))
6393 (set (match_operand:SF 4 "register_operand" "=&f")
6394 (mult:SF (match_dup 1) (match_dup 2)))]
6395 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6396 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6397 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6399 [(set_attr "type" "fpmuldbl")
6400 (set_attr "length" "8")])
6403 [(set (match_operand:SF 0 "register_operand" "")
6404 (minus:SF (match_operand:SF 3 "register_operand" "")
6405 (mult:SF (match_operand:SF 1 "register_operand" "")
6406 (match_operand:SF 2 "register_operand" ""))))
6407 (set (match_operand:SF 4 "register_operand" "")
6408 (mult:SF (match_dup 1) (match_dup 2)))]
6409 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6410 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6411 (set (match_dup 0) (minus:SF (match_dup 3)
6412 (mult:SF (match_dup 1) (match_dup 2))))]
6416 [(set (match_operand:DF 0 "register_operand" "=f")
6417 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6418 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6419 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6420 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6422 [(set_attr "type" "fpalu")
6423 (set_attr "length" "8")])
6426 [(set (match_operand:DF 0 "register_operand" "")
6427 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6428 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6429 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6430 [(set (match_dup 2) (abs:DF (match_dup 1)))
6431 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6435 [(set (match_operand:SF 0 "register_operand" "=f")
6436 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6437 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6438 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6439 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6441 [(set_attr "type" "fpalu")
6442 (set_attr "length" "8")])
6445 [(set (match_operand:SF 0 "register_operand" "")
6446 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6447 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6448 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6449 [(set (match_dup 2) (abs:SF (match_dup 1)))
6450 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6453 ;;- Shift instructions
6455 ;; Optimized special case of shifting.
6458 [(set (match_operand:SI 0 "register_operand" "=r")
6459 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6463 [(set_attr "type" "load")
6464 (set_attr "length" "4")])
6467 [(set (match_operand:SI 0 "register_operand" "=r")
6468 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6472 [(set_attr "type" "load")
6473 (set_attr "length" "4")])
6476 [(set (match_operand:SI 0 "register_operand" "=r")
6477 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6478 (match_operand:SI 3 "shadd_operand" ""))
6479 (match_operand:SI 1 "register_operand" "r")))]
6481 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6482 [(set_attr "type" "binary")
6483 (set_attr "length" "4")])
6486 [(set (match_operand:DI 0 "register_operand" "=r")
6487 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6488 (match_operand:DI 3 "shadd_operand" ""))
6489 (match_operand:DI 1 "register_operand" "r")))]
6491 "shladd,l %2,%O3,%1,%0"
6492 [(set_attr "type" "binary")
6493 (set_attr "length" "4")])
6495 (define_expand "ashlsi3"
6496 [(set (match_operand:SI 0 "register_operand" "")
6497 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6498 (match_operand:SI 2 "arith32_operand" "")))]
6502 if (GET_CODE (operands[2]) != CONST_INT)
6504 rtx temp = gen_reg_rtx (SImode);
6505 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6506 if (GET_CODE (operands[1]) == CONST_INT)
6507 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6509 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6512 /* Make sure both inputs are not constants,
6513 there are no patterns for that. */
6514 operands[1] = force_reg (SImode, operands[1]);
6518 [(set (match_operand:SI 0 "register_operand" "=r")
6519 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6520 (match_operand:SI 2 "const_int_operand" "n")))]
6522 "{zdep|depw,z} %1,%P2,%L2,%0"
6523 [(set_attr "type" "shift")
6524 (set_attr "length" "4")])
6526 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6527 ; Doing it like this makes slightly better code since reload can
6528 ; replace a register with a known value in range -16..15 with a
6529 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6530 ; but since we have no more CONST_OK... characters, that is not
6532 (define_insn "zvdep32"
6533 [(set (match_operand:SI 0 "register_operand" "=r,r")
6534 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6535 (minus:SI (const_int 31)
6536 (match_operand:SI 2 "register_operand" "q,q"))))]
6539 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6540 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6541 [(set_attr "type" "shift,shift")
6542 (set_attr "length" "4,4")])
6544 (define_insn "zvdep_imm32"
6545 [(set (match_operand:SI 0 "register_operand" "=r")
6546 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6547 (minus:SI (const_int 31)
6548 (match_operand:SI 2 "register_operand" "q"))))]
6552 int x = INTVAL (operands[1]);
6553 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6554 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6555 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6557 [(set_attr "type" "shift")
6558 (set_attr "length" "4")])
6560 (define_insn "vdepi_ior"
6561 [(set (match_operand:SI 0 "register_operand" "=r")
6562 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6563 (minus:SI (const_int 31)
6564 (match_operand:SI 2 "register_operand" "q")))
6565 (match_operand:SI 3 "register_operand" "0")))]
6566 ; accept ...0001...1, can this be generalized?
6567 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6570 int x = INTVAL (operands[1]);
6571 operands[2] = GEN_INT (exact_log2 (x + 1));
6572 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6574 [(set_attr "type" "shift")
6575 (set_attr "length" "4")])
6577 (define_insn "vdepi_and"
6578 [(set (match_operand:SI 0 "register_operand" "=r")
6579 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6580 (minus:SI (const_int 31)
6581 (match_operand:SI 2 "register_operand" "q")))
6582 (match_operand:SI 3 "register_operand" "0")))]
6583 ; this can be generalized...!
6584 "INTVAL (operands[1]) == -2"
6587 int x = INTVAL (operands[1]);
6588 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6589 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6591 [(set_attr "type" "shift")
6592 (set_attr "length" "4")])
6594 (define_expand "ashldi3"
6595 [(set (match_operand:DI 0 "register_operand" "")
6596 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6597 (match_operand:DI 2 "arith32_operand" "")))]
6601 if (GET_CODE (operands[2]) != CONST_INT)
6603 rtx temp = gen_reg_rtx (DImode);
6604 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6605 if (GET_CODE (operands[1]) == CONST_INT)
6606 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6608 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6611 /* Make sure both inputs are not constants,
6612 there are no patterns for that. */
6613 operands[1] = force_reg (DImode, operands[1]);
6617 [(set (match_operand:DI 0 "register_operand" "=r")
6618 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6619 (match_operand:DI 2 "const_int_operand" "n")))]
6621 "depd,z %1,%p2,%Q2,%0"
6622 [(set_attr "type" "shift")
6623 (set_attr "length" "4")])
6625 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6626 ; Doing it like this makes slightly better code since reload can
6627 ; replace a register with a known value in range -16..15 with a
6628 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6629 ; but since we have no more CONST_OK... characters, that is not
6631 (define_insn "zvdep64"
6632 [(set (match_operand:DI 0 "register_operand" "=r,r")
6633 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6634 (minus:DI (const_int 63)
6635 (match_operand:DI 2 "register_operand" "q,q"))))]
6638 depd,z %1,%%sar,64,%0
6639 depdi,z %1,%%sar,64,%0"
6640 [(set_attr "type" "shift,shift")
6641 (set_attr "length" "4,4")])
6643 (define_insn "zvdep_imm64"
6644 [(set (match_operand:DI 0 "register_operand" "=r")
6645 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6646 (minus:DI (const_int 63)
6647 (match_operand:DI 2 "register_operand" "q"))))]
6651 int x = INTVAL (operands[1]);
6652 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6653 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6654 return \"depdi,z %1,%%sar,%2,%0\";
6656 [(set_attr "type" "shift")
6657 (set_attr "length" "4")])
6660 [(set (match_operand:DI 0 "register_operand" "=r")
6661 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6662 (minus:DI (const_int 63)
6663 (match_operand:DI 2 "register_operand" "q")))
6664 (match_operand:DI 3 "register_operand" "0")))]
6665 ; accept ...0001...1, can this be generalized?
6666 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
6669 int x = INTVAL (operands[1]);
6670 operands[2] = GEN_INT (exact_log2 (x + 1));
6671 return \"depdi -1,%%sar,%2,%0\";
6673 [(set_attr "type" "shift")
6674 (set_attr "length" "4")])
6677 [(set (match_operand:DI 0 "register_operand" "=r")
6678 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6679 (minus:DI (const_int 63)
6680 (match_operand:DI 2 "register_operand" "q")))
6681 (match_operand:DI 3 "register_operand" "0")))]
6682 ; this can be generalized...!
6683 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6686 int x = INTVAL (operands[1]);
6687 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6688 return \"depdi 0,%%sar,%2,%0\";
6690 [(set_attr "type" "shift")
6691 (set_attr "length" "4")])
6693 (define_expand "ashrsi3"
6694 [(set (match_operand:SI 0 "register_operand" "")
6695 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6696 (match_operand:SI 2 "arith32_operand" "")))]
6700 if (GET_CODE (operands[2]) != CONST_INT)
6702 rtx temp = gen_reg_rtx (SImode);
6703 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6704 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6710 [(set (match_operand:SI 0 "register_operand" "=r")
6711 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6712 (match_operand:SI 2 "const_int_operand" "n")))]
6714 "{extrs|extrw,s} %1,%P2,%L2,%0"
6715 [(set_attr "type" "shift")
6716 (set_attr "length" "4")])
6718 (define_insn "vextrs32"
6719 [(set (match_operand:SI 0 "register_operand" "=r")
6720 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6721 (minus:SI (const_int 31)
6722 (match_operand:SI 2 "register_operand" "q"))))]
6724 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6725 [(set_attr "type" "shift")
6726 (set_attr "length" "4")])
6728 (define_expand "ashrdi3"
6729 [(set (match_operand:DI 0 "register_operand" "")
6730 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6731 (match_operand:DI 2 "arith32_operand" "")))]
6735 if (GET_CODE (operands[2]) != CONST_INT)
6737 rtx temp = gen_reg_rtx (DImode);
6738 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6739 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6745 [(set (match_operand:DI 0 "register_operand" "=r")
6746 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6747 (match_operand:DI 2 "const_int_operand" "n")))]
6749 "extrd,s %1,%p2,%Q2,%0"
6750 [(set_attr "type" "shift")
6751 (set_attr "length" "4")])
6753 (define_insn "vextrs64"
6754 [(set (match_operand:DI 0 "register_operand" "=r")
6755 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6756 (minus:DI (const_int 63)
6757 (match_operand:DI 2 "register_operand" "q"))))]
6759 "extrd,s %1,%%sar,64,%0"
6760 [(set_attr "type" "shift")
6761 (set_attr "length" "4")])
6763 (define_insn "lshrsi3"
6764 [(set (match_operand:SI 0 "register_operand" "=r,r")
6765 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6766 (match_operand:SI 2 "arith32_operand" "q,n")))]
6769 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6770 {extru|extrw,u} %1,%P2,%L2,%0"
6771 [(set_attr "type" "shift")
6772 (set_attr "length" "4")])
6774 (define_insn "lshrdi3"
6775 [(set (match_operand:DI 0 "register_operand" "=r,r")
6776 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6777 (match_operand:DI 2 "arith32_operand" "q,n")))]
6780 shrpd %%r0,%1,%%sar,%0
6781 extrd,u %1,%p2,%Q2,%0"
6782 [(set_attr "type" "shift")
6783 (set_attr "length" "4")])
6785 (define_insn "rotrsi3"
6786 [(set (match_operand:SI 0 "register_operand" "=r,r")
6787 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6788 (match_operand:SI 2 "arith32_operand" "q,n")))]
6792 if (GET_CODE (operands[2]) == CONST_INT)
6794 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6795 return \"{shd|shrpw} %1,%1,%2,%0\";
6798 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6800 [(set_attr "type" "shift")
6801 (set_attr "length" "4")])
6803 (define_expand "rotlsi3"
6804 [(set (match_operand:SI 0 "register_operand" "")
6805 (rotate:SI (match_operand:SI 1 "register_operand" "")
6806 (match_operand:SI 2 "arith32_operand" "")))]
6810 if (GET_CODE (operands[2]) != CONST_INT)
6812 rtx temp = gen_reg_rtx (SImode);
6813 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6814 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6817 /* Else expand normally. */
6821 [(set (match_operand:SI 0 "register_operand" "=r")
6822 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6823 (match_operand:SI 2 "const_int_operand" "n")))]
6827 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6828 return \"{shd|shrpw} %1,%1,%2,%0\";
6830 [(set_attr "type" "shift")
6831 (set_attr "length" "4")])
6834 [(set (match_operand:SI 0 "register_operand" "=r")
6835 (match_operator:SI 5 "plus_xor_ior_operator"
6836 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6837 (match_operand:SI 3 "const_int_operand" "n"))
6838 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6839 (match_operand:SI 4 "const_int_operand" "n"))]))]
6840 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6841 "{shd|shrpw} %1,%2,%4,%0"
6842 [(set_attr "type" "shift")
6843 (set_attr "length" "4")])
6846 [(set (match_operand:SI 0 "register_operand" "=r")
6847 (match_operator:SI 5 "plus_xor_ior_operator"
6848 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6849 (match_operand:SI 4 "const_int_operand" "n"))
6850 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6851 (match_operand:SI 3 "const_int_operand" "n"))]))]
6852 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6853 "{shd|shrpw} %1,%2,%4,%0"
6854 [(set_attr "type" "shift")
6855 (set_attr "length" "4")])
6858 [(set (match_operand:SI 0 "register_operand" "=r")
6859 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6860 (match_operand:SI 2 "const_int_operand" ""))
6861 (match_operand:SI 3 "const_int_operand" "")))]
6862 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
6865 int cnt = INTVAL (operands[2]) & 31;
6866 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6867 operands[2] = GEN_INT (31 - cnt);
6868 return \"{zdep|depw,z} %1,%2,%3,%0\";
6870 [(set_attr "type" "shift")
6871 (set_attr "length" "4")])
6873 ;; Unconditional and other jump instructions.
6875 ;; This is used for most returns.
6876 (define_insn "return_internal"
6883 return \"bve%* (%%r2)\";
6884 return \"bv%* %%r0(%%r2)\";
6886 [(set_attr "type" "branch")
6887 (set_attr "length" "4")])
6889 ;; This is used for eh returns which bypass the return stub.
6890 (define_insn "return_external_pic"
6892 (clobber (reg:SI 1))
6894 "!TARGET_NO_SPACE_REGS
6896 && flag_pic && crtl->calls_eh_return"
6897 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6898 [(set_attr "type" "branch")
6899 (set_attr "length" "12")])
6901 (define_expand "prologue"
6904 "hppa_expand_prologue ();DONE;")
6906 (define_expand "sibcall_epilogue"
6911 hppa_expand_epilogue ();
6915 (define_expand "epilogue"
6922 /* Try to use the trivial return first. Else use the full epilogue. */
6923 if (reload_completed
6924 && !frame_pointer_needed
6925 && !df_regs_ever_live_p (2)
6926 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1))
6927 x = gen_return_internal ();
6930 hppa_expand_epilogue ();
6932 /* EH returns bypass the normal return stub. Thus, we must do an
6933 interspace branch to return from functions that call eh_return.
6934 This is only a problem for returns from shared code on ports
6935 using space registers. */
6936 if (!TARGET_NO_SPACE_REGS
6938 && flag_pic && crtl->calls_eh_return)
6939 x = gen_return_external_pic ();
6941 x = gen_return_internal ();
6947 ; Used by hppa_profile_hook to load the starting address of the current
6948 ; function; operand 1 contains the address of the label in operand 3
6949 (define_insn "load_offset_label_address"
6950 [(set (match_operand:SI 0 "register_operand" "=r")
6951 (plus:SI (match_operand:SI 1 "register_operand" "r")
6952 (minus:SI (match_operand:SI 2 "" "")
6953 (label_ref:SI (match_operand 3 "" "")))))]
6956 [(set_attr "type" "multi")
6957 (set_attr "length" "4")])
6959 ; Output a code label and load its address.
6960 (define_insn "lcla1"
6961 [(set (match_operand:SI 0 "register_operand" "=r")
6962 (label_ref:SI (match_operand 1 "" "")))
6967 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6968 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6969 CODE_LABEL_NUMBER (operands[1]));
6972 [(set_attr "type" "multi")
6973 (set_attr "length" "8")])
6975 (define_insn "lcla2"
6976 [(set (match_operand:SI 0 "register_operand" "=r")
6977 (label_ref:SI (match_operand 1 "" "")))
6982 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6983 CODE_LABEL_NUMBER (operands[1]));
6986 [(set_attr "type" "move")
6987 (set_attr "length" "4")])
6989 (define_insn "blockage"
6990 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6993 [(set_attr "length" "0")])
6996 [(set (pc) (label_ref (match_operand 0 "" "")))]
7000 /* An unconditional branch which can reach its target. */
7001 if (get_attr_length (insn) < 16)
7004 return output_lbranch (operands[0], insn, 1);
7006 [(set_attr "type" "uncond_branch")
7007 (set_attr "pa_combine_type" "uncond_branch")
7008 (set (attr "length")
7009 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
7010 (if_then_else (lt (abs (minus (match_dup 0)
7011 (plus (pc) (const_int 8))))
7012 (const_int MAX_12BIT_OFFSET))
7015 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7016 (const_int MAX_17BIT_OFFSET))
7018 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
7020 (eq (symbol_ref "flag_pic") (const_int 0))
7024 ;;; Hope this is only within a function...
7025 (define_insn "indirect_jump"
7026 [(set (pc) (match_operand 0 "register_operand" "r"))]
7027 "GET_MODE (operands[0]) == word_mode"
7029 [(set_attr "type" "branch")
7030 (set_attr "length" "4")])
7032 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7033 ;;; SOM target doesn't allow branching to a label inside a function.
7034 ;;; We also don't correctly compute branch distances for labels
7035 ;;; outside the current function. Thus, we use an indirect jump can't
7036 ;;; be optimized to a direct jump for all targets. We assume that
7037 ;;; the branch target is in the same space (i.e., nested function
7038 ;;; jumping to a label in an outer function in the same translation
7040 (define_expand "nonlocal_goto"
7041 [(use (match_operand 0 "general_operand" ""))
7042 (use (match_operand 1 "general_operand" ""))
7043 (use (match_operand 2 "general_operand" ""))
7044 (use (match_operand 3 "general_operand" ""))]
7047 rtx lab = operands[1];
7048 rtx stack = operands[2];
7049 rtx fp = operands[3];
7051 lab = copy_to_reg (lab);
7053 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
7054 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
7056 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
7057 instead of the hard_frame_pointer_rtx in the save area. As a
7058 result, an extra instruction is needed to adjust for the offset
7059 of the virtual stack variables and the frame pointer. */
7060 if (GET_CODE (fp) != REG)
7061 fp = force_reg (Pmode, fp);
7062 emit_move_insn (virtual_stack_vars_rtx, fp);
7064 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7066 emit_use (hard_frame_pointer_rtx);
7067 emit_use (stack_pointer_rtx);
7069 /* Nonlocal goto jumps are only used between functions in the same
7070 translation unit. Thus, we can avoid the extra overhead of an
7072 emit_jump_insn (gen_indirect_goto (lab));
7077 (define_insn "indirect_goto"
7078 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7079 "GET_MODE (operands[0]) == word_mode"
7081 [(set_attr "type" "branch")
7082 (set_attr "length" "4")])
7084 ;;; This jump is used in branch tables where the insn length is fixed.
7085 ;;; The length of this insn is adjusted if the delay slot is not filled.
7086 (define_insn "short_jump"
7087 [(set (pc) (label_ref (match_operand 0 "" "")))
7091 [(set_attr "type" "btable_branch")
7092 (set_attr "length" "4")])
7094 ;; Subroutines of "casesi".
7095 ;; operand 0 is index
7096 ;; operand 1 is the minimum bound
7097 ;; operand 2 is the maximum bound - minimum bound + 1
7098 ;; operand 3 is CODE_LABEL for the table;
7099 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7101 (define_expand "casesi"
7102 [(match_operand:SI 0 "general_operand" "")
7103 (match_operand:SI 1 "const_int_operand" "")
7104 (match_operand:SI 2 "const_int_operand" "")
7105 (match_operand 3 "" "")
7106 (match_operand 4 "" "")]
7110 if (GET_CODE (operands[0]) != REG)
7111 operands[0] = force_reg (SImode, operands[0]);
7113 if (operands[1] != const0_rtx)
7115 rtx index = gen_reg_rtx (SImode);
7117 operands[1] = GEN_INT (-INTVAL (operands[1]));
7118 if (!INT_14_BITS (operands[1]))
7119 operands[1] = force_reg (SImode, operands[1]);
7120 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7121 operands[0] = index;
7124 if (!INT_5_BITS (operands[2]))
7125 operands[2] = force_reg (SImode, operands[2]);
7127 /* This branch prevents us finding an insn for the delay slot of the
7128 following vectored branch. It might be possible to use the delay
7129 slot if an index value of -1 was used to transfer to the out-of-range
7130 label. In order to do this, we would have to output the -1 vector
7131 element after the delay insn. The casesi output code would have to
7132 check if the casesi insn is in a delay branch sequence and output
7133 the delay insn if one is found. If this was done, then it might
7134 then be worthwhile to split the casesi patterns to improve scheduling.
7135 However, it's not clear that all this extra complexity is worth
7138 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
7139 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
7142 /* In 64bit mode we must make sure to wipe the upper bits of the register
7143 just in case the addition overflowed or we had random bits in the
7144 high part of the register. */
7147 rtx index = gen_reg_rtx (DImode);
7149 emit_insn (gen_extendsidi2 (index, operands[0]));
7150 operands[0] = index;
7153 if (TARGET_BIG_SWITCH)
7156 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
7158 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
7160 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
7163 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7167 ;;; The rtl for this pattern doesn't accurately describe what the insn
7168 ;;; actually does, particularly when case-vector elements are exploded
7169 ;;; in pa_reorg. However, the initial SET in these patterns must show
7170 ;;; the connection of the insn to the following jump table.
7171 (define_insn "casesi0"
7172 [(set (pc) (mem:SI (plus:SI
7173 (mult:SI (match_operand:SI 0 "register_operand" "r")
7175 (label_ref (match_operand 1 "" "")))))]
7177 "blr,n %0,%%r0\;nop"
7178 [(set_attr "type" "multi")
7179 (set_attr "length" "8")])
7181 ;;; 32-bit code, absolute branch table.
7182 (define_insn "casesi32"
7183 [(set (pc) (mem:SI (plus:SI
7184 (mult:SI (match_operand:SI 0 "register_operand" "r")
7186 (label_ref (match_operand 1 "" "")))))
7187 (clobber (match_scratch:SI 2 "=&r"))]
7189 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7190 [(set_attr "type" "multi")
7191 (set_attr "length" "16")])
7193 ;;; 32-bit code, relative branch table.
7194 (define_insn "casesi32p"
7195 [(set (pc) (mem:SI (plus:SI
7196 (mult:SI (match_operand:SI 0 "register_operand" "r")
7198 (label_ref (match_operand 1 "" "")))))
7199 (clobber (match_scratch:SI 2 "=&r"))
7200 (clobber (match_scratch:SI 3 "=&r"))]
7202 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
7203 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7204 [(set_attr "type" "multi")
7205 (set (attr "length")
7206 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7210 ;;; 64-bit code, 32-bit relative branch table.
7211 (define_insn "casesi64p"
7212 [(set (pc) (mem:DI (plus:DI
7213 (mult:DI (match_operand:DI 0 "register_operand" "r")
7215 (label_ref (match_operand 1 "" "")))))
7216 (clobber (match_scratch:DI 2 "=&r"))
7217 (clobber (match_scratch:DI 3 "=&r"))]
7219 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7220 add,l %2,%3,%3\;bv,n %%r0(%3)"
7221 [(set_attr "type" "multi")
7222 (set_attr "length" "24")])
7226 ;;- jump to subroutine
7228 (define_expand "call"
7229 [(parallel [(call (match_operand:SI 0 "" "")
7230 (match_operand 1 "" ""))
7231 (clobber (reg:SI 2))])]
7236 rtx nb = operands[1];
7238 if (TARGET_PORTABLE_RUNTIME)
7239 op = force_reg (SImode, XEXP (operands[0], 0));
7241 op = XEXP (operands[0], 0);
7245 if (!virtuals_instantiated)
7246 emit_move_insn (arg_pointer_rtx,
7247 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7251 /* The loop pass can generate new libcalls after the virtual
7252 registers are instantiated when fpregs are disabled because
7253 the only method that we have for doing DImode multiplication
7254 is with a libcall. This could be trouble if we haven't
7255 allocated enough space for the outgoing arguments. */
7256 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7258 emit_move_insn (arg_pointer_rtx,
7259 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7260 GEN_INT (STACK_POINTER_OFFSET + 64)));
7264 /* Use two different patterns for calls to explicitly named functions
7265 and calls through function pointers. This is necessary as these two
7266 types of calls use different calling conventions, and CSE might try
7267 to change the named call into an indirect call in some cases (using
7268 two patterns keeps CSE from performing this optimization).
7270 We now use even more call patterns as there was a subtle bug in
7271 attempting to restore the pic register after a call using a simple
7272 move insn. During reload, a instruction involving a pseudo register
7273 with no explicit dependence on the PIC register can be converted
7274 to an equivalent load from memory using the PIC register. If we
7275 emit a simple move to restore the PIC register in the initial rtl
7276 generation, then it can potentially be repositioned during scheduling.
7277 and an instruction that eventually uses the PIC register may end up
7278 between the call and the PIC register restore.
7280 This only worked because there is a post call group of instructions
7281 that are scheduled with the call. These instructions are included
7282 in the same basic block as the call. However, calls can throw in
7283 C++ code and a basic block has to terminate at the call if the call
7284 can throw. This results in the PIC register restore being scheduled
7285 independently from the call. So, we now hide the save and restore
7286 of the PIC register in the call pattern until after reload. Then,
7287 we split the moves out. A small side benefit is that we now don't
7288 need to have a use of the PIC register in the return pattern and
7289 the final save/restore operation is not needed.
7291 I elected to just use register %r4 in the PIC patterns instead
7292 of trying to force hppa_pic_save_rtx () to a callee saved register.
7293 This might have required a new register class and constraint. It
7294 was also simpler to just handle the restore from a register than a
7298 rtx r4 = gen_rtx_REG (word_mode, 4);
7299 if (GET_CODE (op) == SYMBOL_REF)
7300 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb, r4));
7303 op = force_reg (word_mode, op);
7304 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb, r4));
7309 if (GET_CODE (op) == SYMBOL_REF)
7313 rtx r4 = gen_rtx_REG (word_mode, 4);
7314 call_insn = emit_call_insn (gen_call_symref_pic (op, nb, r4));
7317 call_insn = emit_call_insn (gen_call_symref (op, nb));
7321 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7322 emit_move_insn (tmpreg, force_reg (word_mode, op));
7325 rtx r4 = gen_rtx_REG (word_mode, 4);
7326 call_insn = emit_call_insn (gen_call_reg_pic (nb, r4));
7329 call_insn = emit_call_insn (gen_call_reg (nb));
7336 ;; We use function calls to set the attribute length of calls and millicode
7337 ;; calls. This is necessary because of the large variety of call sequences.
7338 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7339 ;; we need the same calculation in several places, maintenance becomes a
7342 ;; However, this has a subtle impact on branch shortening. When the
7343 ;; expression used to set the length attribute of an instruction depends
7344 ;; on a relative address (e.g., pc or a branch address), genattrtab
7345 ;; notes that the insn's length is variable, and attempts to determine a
7346 ;; worst-case default length and code to compute an insn's current length.
7348 ;; The use of a function call hides the variable dependence of our calls
7349 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7350 ;; as variable and it only generates code for the default case using our
7351 ;; function call. Because of this, calls and millicode calls have a fixed
7352 ;; length in the branch shortening pass, and some branches will use a longer
7353 ;; code sequence than necessary. However, the length of any given call
7354 ;; will still reflect its final code location and it may be shorter than
7355 ;; the initial length estimate.
7357 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7358 ;; in the set. However, when genattrtab hits a function call in its attempt
7359 ;; to compute the default length, it marks the result as unknown and sets
7360 ;; the default result to MAX_INT ;-( One possible fix that would allow
7361 ;; calls to participate in branch shortening would be to make the call to
7362 ;; insn_default_length a target option. Then, we could massage unknown
7363 ;; results. Another fix might be to change genattrtab so that it just does
7364 ;; the call in the variable case as it already does for the fixed case.
7366 (define_insn "call_symref"
7367 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7368 (match_operand 1 "" "i"))
7369 (clobber (reg:SI 1))
7370 (clobber (reg:SI 2))
7371 (use (const_int 0))]
7372 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7375 output_arg_descriptor (insn);
7376 return output_call (insn, operands[0], 0);
7378 [(set_attr "type" "call")
7379 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7381 (define_insn "call_symref_pic"
7382 [(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
7383 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7384 (match_operand 1 "" "i"))
7385 (clobber (reg:SI 1))
7386 (clobber (reg:SI 2))
7389 (use (const_int 0))]
7390 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7393 ;; Split out the PIC register save and restore after reload. As the
7394 ;; split is done after reload, there are some situations in which we
7395 ;; unnecessarily save and restore %r4. This happens when there is a
7396 ;; single call and the PIC register is not used after the call.
7398 ;; The split has to be done since call_from_call_insn () can't handle
7399 ;; the pattern as is. Noreturn calls are special because they have to
7400 ;; terminate the basic block. The split has to contain more than one
7403 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7404 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7405 (match_operand 1 "" ""))
7406 (clobber (reg:SI 1))
7407 (clobber (reg:SI 2))
7410 (use (const_int 0))])]
7411 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7412 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7413 [(set (match_dup 2) (reg:SI 19))
7414 (parallel [(call (mem:SI (match_dup 0))
7416 (clobber (reg:SI 1))
7417 (clobber (reg:SI 2))
7419 (use (const_int 0))])]
7423 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7424 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7425 (match_operand 1 "" ""))
7426 (clobber (reg:SI 1))
7427 (clobber (reg:SI 2))
7430 (use (const_int 0))])]
7431 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7432 [(set (match_dup 2) (reg:SI 19))
7433 (parallel [(call (mem:SI (match_dup 0))
7435 (clobber (reg:SI 1))
7436 (clobber (reg:SI 2))
7438 (use (const_int 0))])
7439 (set (reg:SI 19) (match_dup 2))]
7442 (define_insn "*call_symref_pic_post_reload"
7443 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7444 (match_operand 1 "" "i"))
7445 (clobber (reg:SI 1))
7446 (clobber (reg:SI 2))
7448 (use (const_int 0))]
7449 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7452 output_arg_descriptor (insn);
7453 return output_call (insn, operands[0], 0);
7455 [(set_attr "type" "call")
7456 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7458 ;; This pattern is split if it is necessary to save and restore the
7460 (define_insn "call_symref_64bit"
7461 [(set (match_operand:DI 2 "register_operand" "=&r") (reg:DI 27))
7462 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7463 (match_operand 1 "" "i"))
7464 (clobber (reg:DI 1))
7465 (clobber (reg:DI 2))
7469 (use (const_int 0))]
7473 ;; Split out the PIC register save and restore after reload. As the
7474 ;; split is done after reload, there are some situations in which we
7475 ;; unnecessarily save and restore %r4. This happens when there is a
7476 ;; single call and the PIC register is not used after the call.
7478 ;; The split has to be done since call_from_call_insn () can't handle
7479 ;; the pattern as is. Noreturn calls are special because they have to
7480 ;; terminate the basic block. The split has to contain more than one
7483 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7484 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7485 (match_operand 1 "" ""))
7486 (clobber (reg:DI 1))
7487 (clobber (reg:DI 2))
7491 (use (const_int 0))])]
7492 "TARGET_64BIT && reload_completed
7493 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7494 [(set (match_dup 2) (reg:DI 27))
7495 (parallel [(call (mem:SI (match_dup 0))
7497 (clobber (reg:DI 1))
7498 (clobber (reg:DI 2))
7501 (use (const_int 0))])]
7505 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7506 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7507 (match_operand 1 "" ""))
7508 (clobber (reg:DI 1))
7509 (clobber (reg:DI 2))
7513 (use (const_int 0))])]
7514 "TARGET_64BIT && reload_completed"
7515 [(set (match_dup 2) (reg:DI 27))
7516 (parallel [(call (mem:SI (match_dup 0))
7518 (clobber (reg:DI 1))
7519 (clobber (reg:DI 2))
7522 (use (const_int 0))])
7523 (set (reg:DI 27) (match_dup 2))]
7526 (define_insn "*call_symref_64bit_post_reload"
7527 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7528 (match_operand 1 "" "i"))
7529 (clobber (reg:DI 1))
7530 (clobber (reg:DI 2))
7533 (use (const_int 0))]
7537 output_arg_descriptor (insn);
7538 return output_call (insn, operands[0], 0);
7540 [(set_attr "type" "call")
7541 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7543 (define_insn "call_reg"
7544 [(call (mem:SI (reg:SI 22))
7545 (match_operand 0 "" "i"))
7546 (clobber (reg:SI 1))
7547 (clobber (reg:SI 2))
7548 (use (const_int 1))]
7552 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7554 [(set_attr "type" "dyncall")
7555 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7557 ;; This pattern is split if it is necessary to save and restore the
7559 (define_insn "call_reg_pic"
7560 [(set (match_operand:SI 1 "register_operand" "=&r") (reg:SI 19))
7561 (call (mem:SI (reg:SI 22))
7562 (match_operand 0 "" "i"))
7563 (clobber (reg:SI 1))
7564 (clobber (reg:SI 2))
7567 (use (const_int 1))]
7571 ;; Split out the PIC register save and restore after reload. As the
7572 ;; split is done after reload, there are some situations in which we
7573 ;; unnecessarily save and restore %r4. This happens when there is a
7574 ;; single call and the PIC register is not used after the call.
7576 ;; The split has to be done since call_from_call_insn () can't handle
7577 ;; the pattern as is. Noreturn calls are special because they have to
7578 ;; terminate the basic block. The split has to contain more than one
7581 [(parallel [(set (match_operand:SI 1 "register_operand" "") (reg:SI 19))
7582 (call (mem:SI (reg:SI 22))
7583 (match_operand 0 "" ""))
7584 (clobber (reg:SI 1))
7585 (clobber (reg:SI 2))
7588 (use (const_int 1))])]
7589 "!TARGET_64BIT && reload_completed
7590 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7591 [(set (match_dup 1) (reg:SI 19))
7592 (parallel [(call (mem:SI (reg:SI 22))
7594 (clobber (reg:SI 1))
7595 (clobber (reg:SI 2))
7597 (use (const_int 1))])]
7601 [(parallel [(set (match_operand:SI 1 "register_operand" "") (reg:SI 19))
7602 (call (mem:SI (reg:SI 22))
7603 (match_operand 0 "" ""))
7604 (clobber (reg:SI 1))
7605 (clobber (reg:SI 2))
7608 (use (const_int 1))])]
7609 "!TARGET_64BIT && reload_completed"
7610 [(set (match_dup 1) (reg:SI 19))
7611 (parallel [(call (mem:SI (reg:SI 22))
7613 (clobber (reg:SI 1))
7614 (clobber (reg:SI 2))
7616 (use (const_int 1))])
7617 (set (reg:SI 19) (match_dup 1))]
7620 (define_insn "*call_reg_pic_post_reload"
7621 [(call (mem:SI (reg:SI 22))
7622 (match_operand 0 "" "i"))
7623 (clobber (reg:SI 1))
7624 (clobber (reg:SI 2))
7626 (use (const_int 1))]
7630 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7632 [(set_attr "type" "dyncall")
7633 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7635 ;; This pattern is split if it is necessary to save and restore the
7637 (define_insn "call_reg_64bit"
7638 [(set (match_operand:DI 2 "register_operand" "=&r") (reg:DI 27))
7639 (call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7640 (match_operand 1 "" "i"))
7641 (clobber (reg:DI 1))
7642 (clobber (reg:DI 2))
7646 (use (const_int 1))]
7650 ;; Split out the PIC register save and restore after reload. As the
7651 ;; split is done after reload, there are some situations in which we
7652 ;; unnecessarily save and restore %r4. This happens when there is a
7653 ;; single call and the PIC register is not used after the call.
7655 ;; The split has to be done since call_from_call_insn () can't handle
7656 ;; the pattern as is. Noreturn calls are special because they have to
7657 ;; terminate the basic block. The split has to contain more than one
7660 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7661 (call (mem:SI (match_operand 0 "register_operand" ""))
7662 (match_operand 1 "" ""))
7663 (clobber (reg:DI 1))
7664 (clobber (reg:DI 2))
7668 (use (const_int 1))])]
7669 "TARGET_64BIT && reload_completed
7670 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7671 [(set (match_dup 2) (reg:DI 27))
7672 (parallel [(call (mem:SI (match_dup 0))
7674 (clobber (reg:DI 1))
7675 (clobber (reg:DI 2))
7678 (use (const_int 1))])]
7682 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7683 (call (mem:SI (match_operand 0 "register_operand" ""))
7684 (match_operand 1 "" ""))
7685 (clobber (reg:DI 1))
7686 (clobber (reg:DI 2))
7690 (use (const_int 1))])]
7691 "TARGET_64BIT && reload_completed"
7692 [(set (match_dup 2) (reg:DI 27))
7693 (parallel [(call (mem:SI (match_dup 0))
7695 (clobber (reg:DI 1))
7696 (clobber (reg:DI 2))
7699 (use (const_int 1))])
7700 (set (reg:DI 27) (match_dup 2))]
7703 (define_insn "*call_reg_64bit_post_reload"
7704 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7705 (match_operand 1 "" "i"))
7706 (clobber (reg:DI 1))
7707 (clobber (reg:DI 2))
7710 (use (const_int 1))]
7714 return output_indirect_call (insn, operands[0]);
7716 [(set_attr "type" "dyncall")
7717 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7719 (define_expand "call_value"
7720 [(parallel [(set (match_operand 0 "" "")
7721 (call (match_operand:SI 1 "" "")
7722 (match_operand 2 "" "")))
7723 (clobber (reg:SI 2))])]
7728 rtx dst = operands[0];
7729 rtx nb = operands[2];
7731 if (TARGET_PORTABLE_RUNTIME)
7732 op = force_reg (SImode, XEXP (operands[1], 0));
7734 op = XEXP (operands[1], 0);
7738 if (!virtuals_instantiated)
7739 emit_move_insn (arg_pointer_rtx,
7740 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7744 /* The loop pass can generate new libcalls after the virtual
7745 registers are instantiated when fpregs are disabled because
7746 the only method that we have for doing DImode multiplication
7747 is with a libcall. This could be trouble if we haven't
7748 allocated enough space for the outgoing arguments. */
7749 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7751 emit_move_insn (arg_pointer_rtx,
7752 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7753 GEN_INT (STACK_POINTER_OFFSET + 64)));
7757 /* Use two different patterns for calls to explicitly named functions
7758 and calls through function pointers. This is necessary as these two
7759 types of calls use different calling conventions, and CSE might try
7760 to change the named call into an indirect call in some cases (using
7761 two patterns keeps CSE from performing this optimization).
7763 We now use even more call patterns as there was a subtle bug in
7764 attempting to restore the pic register after a call using a simple
7765 move insn. During reload, a instruction involving a pseudo register
7766 with no explicit dependence on the PIC register can be converted
7767 to an equivalent load from memory using the PIC register. If we
7768 emit a simple move to restore the PIC register in the initial rtl
7769 generation, then it can potentially be repositioned during scheduling.
7770 and an instruction that eventually uses the PIC register may end up
7771 between the call and the PIC register restore.
7773 This only worked because there is a post call group of instructions
7774 that are scheduled with the call. These instructions are included
7775 in the same basic block as the call. However, calls can throw in
7776 C++ code and a basic block has to terminate at the call if the call
7777 can throw. This results in the PIC register restore being scheduled
7778 independently from the call. So, we now hide the save and restore
7779 of the PIC register in the call pattern until after reload. Then,
7780 we split the moves out. A small side benefit is that we now don't
7781 need to have a use of the PIC register in the return pattern and
7782 the final save/restore operation is not needed.
7784 I elected to just use register %r4 in the PIC patterns instead
7785 of trying to force hppa_pic_save_rtx () to a callee saved register.
7786 This might have required a new register class and constraint. It
7787 was also simpler to just handle the restore from a register than a
7791 rtx r4 = gen_rtx_REG (word_mode, 4);
7792 if (GET_CODE (op) == SYMBOL_REF)
7794 = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb, r4));
7797 op = force_reg (word_mode, op);
7799 = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb, r4));
7804 if (GET_CODE (op) == SYMBOL_REF)
7808 rtx r4 = gen_rtx_REG (word_mode, 4);
7810 = emit_call_insn (gen_call_val_symref_pic (dst, op, nb, r4));
7813 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7817 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7818 emit_move_insn (tmpreg, force_reg (word_mode, op));
7821 rtx r4 = gen_rtx_REG (word_mode, 4);
7822 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb, r4));
7825 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7832 (define_insn "call_val_symref"
7833 [(set (match_operand 0 "" "")
7834 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7835 (match_operand 2 "" "i")))
7836 (clobber (reg:SI 1))
7837 (clobber (reg:SI 2))
7838 (use (const_int 0))]
7839 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7842 output_arg_descriptor (insn);
7843 return output_call (insn, operands[1], 0);
7845 [(set_attr "type" "call")
7846 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7848 (define_insn "call_val_symref_pic"
7849 [(set (match_operand:SI 3 "register_operand" "=&r") (reg:SI 19))
7850 (set (match_operand 0 "" "")
7851 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7852 (match_operand 2 "" "i")))
7853 (clobber (reg:SI 1))
7854 (clobber (reg:SI 2))
7857 (use (const_int 0))]
7858 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7861 ;; Split out the PIC register save and restore after reload. As the
7862 ;; split is done after reload, there are some situations in which we
7863 ;; unnecessarily save and restore %r4. This happens when there is a
7864 ;; single call and the PIC register is not used after the call.
7866 ;; The split has to be done since call_from_call_insn () can't handle
7867 ;; the pattern as is. Noreturn calls are special because they have to
7868 ;; terminate the basic block. The split has to contain more than one
7871 [(parallel [(set (match_operand:SI 3 "register_operand" "") (reg:SI 19))
7872 (set (match_operand 0 "" "")
7873 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7874 (match_operand 2 "" "")))
7875 (clobber (reg:SI 1))
7876 (clobber (reg:SI 2))
7879 (use (const_int 0))])]
7880 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7881 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7882 [(set (match_dup 3) (reg:SI 19))
7883 (parallel [(set (match_dup 0)
7884 (call (mem:SI (match_dup 1))
7886 (clobber (reg:SI 1))
7887 (clobber (reg:SI 2))
7889 (use (const_int 0))])]
7893 [(parallel [(set (match_operand:SI 3 "register_operand" "") (reg:SI 19))
7894 (set (match_operand 0 "" "")
7895 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7896 (match_operand 2 "" "")))
7897 (clobber (reg:SI 1))
7898 (clobber (reg:SI 2))
7901 (use (const_int 0))])]
7902 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7903 [(set (match_dup 3) (reg:SI 19))
7904 (parallel [(set (match_dup 0)
7905 (call (mem:SI (match_dup 1))
7907 (clobber (reg:SI 1))
7908 (clobber (reg:SI 2))
7910 (use (const_int 0))])
7911 (set (reg:SI 19) (match_dup 3))]
7914 (define_insn "*call_val_symref_pic_post_reload"
7915 [(set (match_operand 0 "" "")
7916 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7917 (match_operand 2 "" "i")))
7918 (clobber (reg:SI 1))
7919 (clobber (reg:SI 2))
7921 (use (const_int 0))]
7922 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7925 output_arg_descriptor (insn);
7926 return output_call (insn, operands[1], 0);
7928 [(set_attr "type" "call")
7929 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7931 ;; This pattern is split if it is necessary to save and restore the
7933 (define_insn "call_val_symref_64bit"
7934 [(set (match_operand:DI 3 "register_operand" "=&r") (reg:DI 27))
7935 (set (match_operand 0 "" "")
7936 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7937 (match_operand 2 "" "i")))
7938 (clobber (reg:DI 1))
7939 (clobber (reg:DI 2))
7943 (use (const_int 0))]
7947 ;; Split out the PIC register save and restore after reload. As the
7948 ;; split is done after reload, there are some situations in which we
7949 ;; unnecessarily save and restore %r4. This happens when there is a
7950 ;; single call and the PIC register is not used after the call.
7952 ;; The split has to be done since call_from_call_insn () can't handle
7953 ;; the pattern as is. Noreturn calls are special because they have to
7954 ;; terminate the basic block. The split has to contain more than one
7957 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7958 (set (match_operand 0 "" "")
7959 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7960 (match_operand 2 "" "")))
7961 (clobber (reg:DI 1))
7962 (clobber (reg:DI 2))
7966 (use (const_int 0))])]
7967 "TARGET_64BIT && reload_completed
7968 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7969 [(set (match_dup 3) (reg:DI 27))
7970 (parallel [(set (match_dup 0)
7971 (call (mem:SI (match_dup 1))
7973 (clobber (reg:DI 1))
7974 (clobber (reg:DI 2))
7977 (use (const_int 0))])]
7981 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7982 (set (match_operand 0 "" "")
7983 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7984 (match_operand 2 "" "")))
7985 (clobber (reg:DI 1))
7986 (clobber (reg:DI 2))
7990 (use (const_int 0))])]
7991 "TARGET_64BIT && reload_completed"
7992 [(set (match_dup 3) (reg:DI 27))
7993 (parallel [(set (match_dup 0)
7994 (call (mem:SI (match_dup 1))
7996 (clobber (reg:DI 1))
7997 (clobber (reg:DI 2))
8000 (use (const_int 0))])
8001 (set (reg:DI 27) (match_dup 3))]
8004 (define_insn "*call_val_symref_64bit_post_reload"
8005 [(set (match_operand 0 "" "")
8006 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8007 (match_operand 2 "" "i")))
8008 (clobber (reg:DI 1))
8009 (clobber (reg:DI 2))
8012 (use (const_int 0))]
8016 output_arg_descriptor (insn);
8017 return output_call (insn, operands[1], 0);
8019 [(set_attr "type" "call")
8020 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8022 (define_insn "call_val_reg"
8023 [(set (match_operand 0 "" "")
8024 (call (mem:SI (reg:SI 22))
8025 (match_operand 1 "" "i")))
8026 (clobber (reg:SI 1))
8027 (clobber (reg:SI 2))
8028 (use (const_int 1))]
8032 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8034 [(set_attr "type" "dyncall")
8035 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8037 ;; This pattern is split if it is necessary to save and restore the
8039 (define_insn "call_val_reg_pic"
8040 [(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
8041 (set (match_operand 0 "" "")
8042 (call (mem:SI (reg:SI 22))
8043 (match_operand 1 "" "i")))
8044 (clobber (reg:SI 1))
8045 (clobber (reg:SI 2))
8048 (use (const_int 1))]
8052 ;; Split out the PIC register save and restore after reload. As the
8053 ;; split is done after reload, there are some situations in which we
8054 ;; unnecessarily save and restore %r4. This happens when there is a
8055 ;; single call and the PIC register is not used after the call.
8057 ;; The split has to be done since call_from_call_insn () can't handle
8058 ;; the pattern as is. Noreturn calls are special because they have to
8059 ;; terminate the basic block. The split has to contain more than one
8062 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
8063 (set (match_operand 0 "" "")
8064 (call (mem:SI (reg:SI 22))
8065 (match_operand 1 "" "")))
8066 (clobber (reg:SI 1))
8067 (clobber (reg:SI 2))
8070 (use (const_int 1))])]
8071 "!TARGET_64BIT && reload_completed
8072 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8073 [(set (match_dup 2) (reg:SI 19))
8074 (parallel [(set (match_dup 0)
8075 (call (mem:SI (reg:SI 22))
8077 (clobber (reg:SI 1))
8078 (clobber (reg:SI 2))
8080 (use (const_int 1))])]
8084 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
8085 (set (match_operand 0 "" "")
8086 (call (mem:SI (reg:SI 22))
8087 (match_operand 1 "" "")))
8088 (clobber (reg:SI 1))
8089 (clobber (reg:SI 2))
8092 (use (const_int 1))])]
8093 "!TARGET_64BIT && reload_completed"
8094 [(set (match_dup 2) (reg:SI 19))
8095 (parallel [(set (match_dup 0)
8096 (call (mem:SI (reg:SI 22))
8098 (clobber (reg:SI 1))
8099 (clobber (reg:SI 2))
8101 (use (const_int 1))])
8102 (set (reg:SI 19) (match_dup 2))]
8105 (define_insn "*call_val_reg_pic_post_reload"
8106 [(set (match_operand 0 "" "")
8107 (call (mem:SI (reg:SI 22))
8108 (match_operand 1 "" "i")))
8109 (clobber (reg:SI 1))
8110 (clobber (reg:SI 2))
8112 (use (const_int 1))]
8116 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8118 [(set_attr "type" "dyncall")
8119 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8121 ;; This pattern is split if it is necessary to save and restore the
8123 (define_insn "call_val_reg_64bit"
8124 [(set (match_operand:DI 3 "register_operand" "=&r") (reg:DI 27))
8125 (set (match_operand 0 "" "")
8126 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8127 (match_operand 2 "" "i")))
8128 (clobber (reg:DI 1))
8129 (clobber (reg:DI 2))
8133 (use (const_int 1))]
8137 ;; Split out the PIC register save and restore after reload. As the
8138 ;; split is done after reload, there are some situations in which we
8139 ;; unnecessarily save and restore %r4. This happens when there is a
8140 ;; single call and the PIC register is not used after the call.
8142 ;; The split has to be done since call_from_call_insn () can't handle
8143 ;; the pattern as is. Noreturn calls are special because they have to
8144 ;; terminate the basic block. The split has to contain more than one
8147 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
8148 (set (match_operand 0 "" "")
8149 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8150 (match_operand 2 "" "")))
8151 (clobber (reg:DI 1))
8152 (clobber (reg:DI 2))
8156 (use (const_int 1))])]
8157 "TARGET_64BIT && reload_completed
8158 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8159 [(set (match_dup 3) (reg:DI 27))
8160 (parallel [(set (match_dup 0)
8161 (call (mem:SI (match_dup 1))
8163 (clobber (reg:DI 1))
8164 (clobber (reg:DI 2))
8167 (use (const_int 1))])]
8171 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
8172 (set (match_operand 0 "" "")
8173 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8174 (match_operand 2 "" "")))
8175 (clobber (reg:DI 1))
8176 (clobber (reg:DI 2))
8180 (use (const_int 1))])]
8181 "TARGET_64BIT && reload_completed"
8182 [(set (match_dup 3) (reg:DI 27))
8183 (parallel [(set (match_dup 0)
8184 (call (mem:SI (match_dup 1))
8186 (clobber (reg:DI 1))
8187 (clobber (reg:DI 2))
8190 (use (const_int 1))])
8191 (set (reg:DI 27) (match_dup 3))]
8194 (define_insn "*call_val_reg_64bit_post_reload"
8195 [(set (match_operand 0 "" "")
8196 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8197 (match_operand 2 "" "i")))
8198 (clobber (reg:DI 1))
8199 (clobber (reg:DI 2))
8202 (use (const_int 1))]
8206 return output_indirect_call (insn, operands[1]);
8208 [(set_attr "type" "dyncall")
8209 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8211 ;; Call subroutine returning any type.
8213 (define_expand "untyped_call"
8214 [(parallel [(call (match_operand 0 "" "")
8216 (match_operand 1 "" "")
8217 (match_operand 2 "" "")])]
8223 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8225 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8227 rtx set = XVECEXP (operands[2], 0, i);
8228 emit_move_insn (SET_DEST (set), SET_SRC (set));
8231 /* The optimizer does not know that the call sets the function value
8232 registers we stored in the result block. We avoid problems by
8233 claiming that all hard registers are used and clobbered at this
8235 emit_insn (gen_blockage ());
8240 (define_expand "sibcall"
8241 [(call (match_operand:SI 0 "" "")
8242 (match_operand 1 "" ""))]
8243 "!TARGET_PORTABLE_RUNTIME"
8247 rtx nb = operands[1];
8249 op = XEXP (operands[0], 0);
8253 if (!virtuals_instantiated)
8254 emit_move_insn (arg_pointer_rtx,
8255 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8259 /* The loop pass can generate new libcalls after the virtual
8260 registers are instantiated when fpregs are disabled because
8261 the only method that we have for doing DImode multiplication
8262 is with a libcall. This could be trouble if we haven't
8263 allocated enough space for the outgoing arguments. */
8264 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8266 emit_move_insn (arg_pointer_rtx,
8267 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8268 GEN_INT (STACK_POINTER_OFFSET + 64)));
8272 /* Indirect sibling calls are not allowed. */
8274 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8276 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8278 call_insn = emit_call_insn (call_insn);
8281 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8283 /* We don't have to restore the PIC register. */
8285 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8290 (define_insn "sibcall_internal_symref"
8291 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8292 (match_operand 1 "" "i"))
8293 (clobber (reg:SI 1))
8295 (use (const_int 0))]
8296 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8299 output_arg_descriptor (insn);
8300 return output_call (insn, operands[0], 1);
8302 [(set_attr "type" "call")
8303 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8305 (define_insn "sibcall_internal_symref_64bit"
8306 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8307 (match_operand 1 "" "i"))
8308 (clobber (reg:DI 1))
8310 (use (const_int 0))]
8314 output_arg_descriptor (insn);
8315 return output_call (insn, operands[0], 1);
8317 [(set_attr "type" "call")
8318 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8320 (define_expand "sibcall_value"
8321 [(set (match_operand 0 "" "")
8322 (call (match_operand:SI 1 "" "")
8323 (match_operand 2 "" "")))]
8324 "!TARGET_PORTABLE_RUNTIME"
8328 rtx nb = operands[1];
8330 op = XEXP (operands[1], 0);
8334 if (!virtuals_instantiated)
8335 emit_move_insn (arg_pointer_rtx,
8336 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8340 /* The loop pass can generate new libcalls after the virtual
8341 registers are instantiated when fpregs are disabled because
8342 the only method that we have for doing DImode multiplication
8343 is with a libcall. This could be trouble if we haven't
8344 allocated enough space for the outgoing arguments. */
8345 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8347 emit_move_insn (arg_pointer_rtx,
8348 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8349 GEN_INT (STACK_POINTER_OFFSET + 64)));
8353 /* Indirect sibling calls are not allowed. */
8356 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8359 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8361 call_insn = emit_call_insn (call_insn);
8364 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8366 /* We don't have to restore the PIC register. */
8368 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8373 (define_insn "sibcall_value_internal_symref"
8374 [(set (match_operand 0 "" "")
8375 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8376 (match_operand 2 "" "i")))
8377 (clobber (reg:SI 1))
8379 (use (const_int 0))]
8380 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8383 output_arg_descriptor (insn);
8384 return output_call (insn, operands[1], 1);
8386 [(set_attr "type" "call")
8387 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8389 (define_insn "sibcall_value_internal_symref_64bit"
8390 [(set (match_operand 0 "" "")
8391 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8392 (match_operand 2 "" "i")))
8393 (clobber (reg:DI 1))
8395 (use (const_int 0))]
8399 output_arg_descriptor (insn);
8400 return output_call (insn, operands[1], 1);
8402 [(set_attr "type" "call")
8403 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8409 [(set_attr "type" "move")
8410 (set_attr "length" "4")])
8412 ;; These are just placeholders so we know where branch tables
8414 (define_insn "begin_brtab"
8419 /* Only GAS actually supports this pseudo-op. */
8421 return \".begin_brtab\";
8425 [(set_attr "type" "move")
8426 (set_attr "length" "0")])
8428 (define_insn "end_brtab"
8433 /* Only GAS actually supports this pseudo-op. */
8435 return \".end_brtab\";
8439 [(set_attr "type" "move")
8440 (set_attr "length" "0")])
8442 ;;; EH does longjmp's from and within the data section. Thus,
8443 ;;; an interspace branch is required for the longjmp implementation.
8444 ;;; Registers r1 and r2 are used as scratch registers for the jump
8446 (define_expand "interspace_jump"
8448 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8449 (clobber (match_dup 1))])]
8453 operands[1] = gen_rtx_REG (word_mode, 2);
8457 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8458 (clobber (reg:SI 2))]
8459 "TARGET_PA_20 && !TARGET_64BIT"
8461 [(set_attr "type" "branch")
8462 (set_attr "length" "4")])
8465 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8466 (clobber (reg:SI 2))]
8467 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8469 [(set_attr "type" "branch")
8470 (set_attr "length" "4")])
8473 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8474 (clobber (reg:SI 2))]
8476 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8477 [(set_attr "type" "branch")
8478 (set_attr "length" "12")])
8481 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8482 (clobber (reg:DI 2))]
8485 [(set_attr "type" "branch")
8486 (set_attr "length" "4")])
8488 (define_expand "builtin_longjmp"
8489 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8493 /* The elements of the buffer are, in order: */
8494 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8495 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8496 POINTER_SIZE / BITS_PER_UNIT));
8497 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8498 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8499 rtx pv = gen_rtx_REG (Pmode, 1);
8501 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
8502 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
8504 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8505 instead of the hard_frame_pointer_rtx in the save area. We need
8506 to adjust for the offset between these two values when we have
8507 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8508 pattern, the receiver performs the adjustment. */
8509 #ifdef HAVE_nonlocal_goto
8510 if (HAVE_nonlocal_goto)
8511 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8514 emit_move_insn (hard_frame_pointer_rtx, fp);
8516 /* This bit is the same as expand_builtin_longjmp. */
8517 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8518 emit_use (hard_frame_pointer_rtx);
8519 emit_use (stack_pointer_rtx);
8521 /* Load the label we are jumping through into r1 so that we know
8522 where to look for it when we get back to setjmp's function for
8523 restoring the gp. */
8524 emit_move_insn (pv, lab);
8526 /* Prevent the insns above from being scheduled into the delay slot
8527 of the interspace jump because the space register could change. */
8528 emit_insn (gen_blockage ());
8530 emit_jump_insn (gen_interspace_jump (pv));
8535 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8536 (define_expand "extzv"
8537 [(set (match_operand 0 "register_operand" "")
8538 (zero_extract (match_operand 1 "register_operand" "")
8539 (match_operand 2 "uint32_operand" "")
8540 (match_operand 3 "uint32_operand" "")))]
8544 HOST_WIDE_INT len = INTVAL (operands[2]);
8545 HOST_WIDE_INT pos = INTVAL (operands[3]);
8547 /* PA extraction insns don't support zero length bitfields or fields
8548 extending beyond the left or right-most bits. Also, we reject lengths
8549 equal to a word as they are better handled by the move patterns. */
8550 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8553 /* From mips.md: extract_bit_field doesn't verify that our source
8554 matches the predicate, so check it again here. */
8555 if (!register_operand (operands[1], VOIDmode))
8559 emit_insn (gen_extzv_64 (operands[0], operands[1],
8560 operands[2], operands[3]));
8562 emit_insn (gen_extzv_32 (operands[0], operands[1],
8563 operands[2], operands[3]));
8567 (define_insn "extzv_32"
8568 [(set (match_operand:SI 0 "register_operand" "=r")
8569 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8570 (match_operand:SI 2 "uint5_operand" "")
8571 (match_operand:SI 3 "uint5_operand" "")))]
8573 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8574 [(set_attr "type" "shift")
8575 (set_attr "length" "4")])
8578 [(set (match_operand:SI 0 "register_operand" "=r")
8579 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8581 (match_operand:SI 2 "register_operand" "q")))]
8583 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8584 [(set_attr "type" "shift")
8585 (set_attr "length" "4")])
8587 (define_insn "extzv_64"
8588 [(set (match_operand:DI 0 "register_operand" "=r")
8589 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8590 (match_operand:DI 2 "uint32_operand" "")
8591 (match_operand:DI 3 "uint32_operand" "")))]
8593 "extrd,u %1,%3+%2-1,%2,%0"
8594 [(set_attr "type" "shift")
8595 (set_attr "length" "4")])
8598 [(set (match_operand:DI 0 "register_operand" "=r")
8599 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8601 (match_operand:DI 2 "register_operand" "q")))]
8603 "extrd,u %1,%%sar,1,%0"
8604 [(set_attr "type" "shift")
8605 (set_attr "length" "4")])
8607 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8608 (define_expand "extv"
8609 [(set (match_operand 0 "register_operand" "")
8610 (sign_extract (match_operand 1 "register_operand" "")
8611 (match_operand 2 "uint32_operand" "")
8612 (match_operand 3 "uint32_operand" "")))]
8616 HOST_WIDE_INT len = INTVAL (operands[2]);
8617 HOST_WIDE_INT pos = INTVAL (operands[3]);
8619 /* PA extraction insns don't support zero length bitfields or fields
8620 extending beyond the left or right-most bits. Also, we reject lengths
8621 equal to a word as they are better handled by the move patterns. */
8622 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8625 /* From mips.md: extract_bit_field doesn't verify that our source
8626 matches the predicate, so check it again here. */
8627 if (!register_operand (operands[1], VOIDmode))
8631 emit_insn (gen_extv_64 (operands[0], operands[1],
8632 operands[2], operands[3]));
8634 emit_insn (gen_extv_32 (operands[0], operands[1],
8635 operands[2], operands[3]));
8639 (define_insn "extv_32"
8640 [(set (match_operand:SI 0 "register_operand" "=r")
8641 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8642 (match_operand:SI 2 "uint5_operand" "")
8643 (match_operand:SI 3 "uint5_operand" "")))]
8645 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8646 [(set_attr "type" "shift")
8647 (set_attr "length" "4")])
8650 [(set (match_operand:SI 0 "register_operand" "=r")
8651 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8653 (match_operand:SI 2 "register_operand" "q")))]
8655 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8656 [(set_attr "type" "shift")
8657 (set_attr "length" "4")])
8659 (define_insn "extv_64"
8660 [(set (match_operand:DI 0 "register_operand" "=r")
8661 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8662 (match_operand:DI 2 "uint32_operand" "")
8663 (match_operand:DI 3 "uint32_operand" "")))]
8665 "extrd,s %1,%3+%2-1,%2,%0"
8666 [(set_attr "type" "shift")
8667 (set_attr "length" "4")])
8670 [(set (match_operand:DI 0 "register_operand" "=r")
8671 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8673 (match_operand:DI 2 "register_operand" "q")))]
8675 "extrd,s %1,%%sar,1,%0"
8676 [(set_attr "type" "shift")
8677 (set_attr "length" "4")])
8679 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8680 (define_expand "insv"
8681 [(set (zero_extract (match_operand 0 "register_operand" "")
8682 (match_operand 1 "uint32_operand" "")
8683 (match_operand 2 "uint32_operand" ""))
8684 (match_operand 3 "arith5_operand" ""))]
8688 HOST_WIDE_INT len = INTVAL (operands[1]);
8689 HOST_WIDE_INT pos = INTVAL (operands[2]);
8691 /* PA insertion insns don't support zero length bitfields or fields
8692 extending beyond the left or right-most bits. Also, we reject lengths
8693 equal to a word as they are better handled by the move patterns. */
8694 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8697 /* From mips.md: insert_bit_field doesn't verify that our destination
8698 matches the predicate, so check it again here. */
8699 if (!register_operand (operands[0], VOIDmode))
8703 emit_insn (gen_insv_64 (operands[0], operands[1],
8704 operands[2], operands[3]));
8706 emit_insn (gen_insv_32 (operands[0], operands[1],
8707 operands[2], operands[3]));
8711 (define_insn "insv_32"
8712 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8713 (match_operand:SI 1 "uint5_operand" "")
8714 (match_operand:SI 2 "uint5_operand" ""))
8715 (match_operand:SI 3 "arith5_operand" "r,L"))]
8718 {dep|depw} %3,%2+%1-1,%1,%0
8719 {depi|depwi} %3,%2+%1-1,%1,%0"
8720 [(set_attr "type" "shift,shift")
8721 (set_attr "length" "4,4")])
8723 ;; Optimize insertion of const_int values of type 1...1xxxx.
8725 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8726 (match_operand:SI 1 "uint5_operand" "")
8727 (match_operand:SI 2 "uint5_operand" ""))
8728 (match_operand:SI 3 "const_int_operand" ""))]
8729 "(INTVAL (operands[3]) & 0x10) != 0 &&
8730 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8733 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8734 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8736 [(set_attr "type" "shift")
8737 (set_attr "length" "4")])
8739 (define_insn "insv_64"
8740 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8741 (match_operand:DI 1 "uint32_operand" "")
8742 (match_operand:DI 2 "uint32_operand" ""))
8743 (match_operand:DI 3 "arith32_operand" "r,L"))]
8746 depd %3,%2+%1-1,%1,%0
8747 depdi %3,%2+%1-1,%1,%0"
8748 [(set_attr "type" "shift,shift")
8749 (set_attr "length" "4,4")])
8751 ;; Optimize insertion of const_int values of type 1...1xxxx.
8753 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8754 (match_operand:DI 1 "uint32_operand" "")
8755 (match_operand:DI 2 "uint32_operand" ""))
8756 (match_operand:DI 3 "const_int_operand" ""))]
8757 "(INTVAL (operands[3]) & 0x10) != 0
8759 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8762 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8763 return \"depdi %3,%2+%1-1,%1,%0\";
8765 [(set_attr "type" "shift")
8766 (set_attr "length" "4")])
8769 [(set (match_operand:DI 0 "register_operand" "=r")
8770 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8773 "depd,z %1,31,32,%0"
8774 [(set_attr "type" "shift")
8775 (set_attr "length" "4")])
8777 ;; This insn is used for some loop tests, typically loops reversed when
8778 ;; strength reduction is used. It is actually created when the instruction
8779 ;; combination phase combines the special loop test. Since this insn
8780 ;; is both a jump insn and has an output, it must deal with its own
8781 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8782 ;; to not choose the register alternatives in the event a reload is needed.
8783 (define_insn "decrement_and_branch_until_zero"
8786 (match_operator 2 "comparison_operator"
8788 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8789 (match_operand:SI 1 "int5_operand" "L,L,L"))
8791 (label_ref (match_operand 3 "" ""))
8794 (plus:SI (match_dup 0) (match_dup 1)))
8795 (clobber (match_scratch:SI 4 "=X,r,r"))]
8797 "* return output_dbra (operands, insn, which_alternative); "
8798 ;; Do not expect to understand this the first time through.
8799 [(set_attr "type" "cbranch,multi,multi")
8800 (set (attr "length")
8801 (if_then_else (eq_attr "alternative" "0")
8802 ;; Loop counter in register case
8803 ;; Short branch has length of 4
8804 ;; Long branch has length of 8, 20, 24 or 28
8805 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8806 (const_int MAX_12BIT_OFFSET))
8808 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8809 (const_int MAX_17BIT_OFFSET))
8811 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8813 (eq (symbol_ref "flag_pic") (const_int 0))
8817 ;; Loop counter in FP reg case.
8818 ;; Extra goo to deal with additional reload insns.
8819 (if_then_else (eq_attr "alternative" "1")
8820 (if_then_else (lt (match_dup 3) (pc))
8821 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8822 (const_int MAX_12BIT_OFFSET))
8824 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8825 (const_int MAX_17BIT_OFFSET))
8827 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8829 (eq (symbol_ref "flag_pic") (const_int 0))
8832 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8833 (const_int MAX_12BIT_OFFSET))
8835 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8836 (const_int MAX_17BIT_OFFSET))
8838 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8840 (eq (symbol_ref "flag_pic") (const_int 0))
8844 ;; Loop counter in memory case.
8845 ;; Extra goo to deal with additional reload insns.
8846 (if_then_else (lt (match_dup 3) (pc))
8847 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8848 (const_int MAX_12BIT_OFFSET))
8850 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8851 (const_int MAX_17BIT_OFFSET))
8853 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8855 (eq (symbol_ref "flag_pic") (const_int 0))
8858 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8859 (const_int MAX_12BIT_OFFSET))
8861 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8862 (const_int MAX_17BIT_OFFSET))
8864 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8866 (eq (symbol_ref "flag_pic") (const_int 0))
8868 (const_int 36))))))])
8873 (match_operator 2 "movb_comparison_operator"
8874 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8875 (label_ref (match_operand 3 "" ""))
8877 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8880 "* return output_movb (operands, insn, which_alternative, 0); "
8881 ;; Do not expect to understand this the first time through.
8882 [(set_attr "type" "cbranch,multi,multi,multi")
8883 (set (attr "length")
8884 (if_then_else (eq_attr "alternative" "0")
8885 ;; Loop counter in register case
8886 ;; Short branch has length of 4
8887 ;; Long branch has length of 8, 20, 24 or 28
8888 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8889 (const_int MAX_12BIT_OFFSET))
8891 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8892 (const_int MAX_17BIT_OFFSET))
8894 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8896 (eq (symbol_ref "flag_pic") (const_int 0))
8900 ;; Loop counter in FP reg case.
8901 ;; Extra goo to deal with additional reload insns.
8902 (if_then_else (eq_attr "alternative" "1")
8903 (if_then_else (lt (match_dup 3) (pc))
8904 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8905 (const_int MAX_12BIT_OFFSET))
8907 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8908 (const_int MAX_17BIT_OFFSET))
8910 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8912 (eq (symbol_ref "flag_pic") (const_int 0))
8915 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8916 (const_int MAX_12BIT_OFFSET))
8918 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8919 (const_int MAX_17BIT_OFFSET))
8921 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8923 (eq (symbol_ref "flag_pic") (const_int 0))
8927 ;; Loop counter in memory or sar case.
8928 ;; Extra goo to deal with additional reload insns.
8929 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8930 (const_int MAX_12BIT_OFFSET))
8932 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8933 (const_int MAX_17BIT_OFFSET))
8935 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8937 (eq (symbol_ref "flag_pic") (const_int 0))
8939 (const_int 32)))))])
8941 ;; Handle negated branch.
8945 (match_operator 2 "movb_comparison_operator"
8946 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8948 (label_ref (match_operand 3 "" ""))))
8949 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8952 "* return output_movb (operands, insn, which_alternative, 1); "
8953 ;; Do not expect to understand this the first time through.
8954 [(set_attr "type" "cbranch,multi,multi,multi")
8955 (set (attr "length")
8956 (if_then_else (eq_attr "alternative" "0")
8957 ;; Loop counter in register case
8958 ;; Short branch has length of 4
8959 ;; Long branch has length of 8
8960 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8961 (const_int MAX_12BIT_OFFSET))
8963 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8964 (const_int MAX_17BIT_OFFSET))
8966 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8968 (eq (symbol_ref "flag_pic") (const_int 0))
8972 ;; Loop counter in FP reg case.
8973 ;; Extra goo to deal with additional reload insns.
8974 (if_then_else (eq_attr "alternative" "1")
8975 (if_then_else (lt (match_dup 3) (pc))
8976 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8977 (const_int MAX_12BIT_OFFSET))
8979 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8980 (const_int MAX_17BIT_OFFSET))
8982 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8984 (eq (symbol_ref "flag_pic") (const_int 0))
8987 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8988 (const_int MAX_12BIT_OFFSET))
8990 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8991 (const_int MAX_17BIT_OFFSET))
8993 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8995 (eq (symbol_ref "flag_pic") (const_int 0))
8999 ;; Loop counter in memory or SAR case.
9000 ;; Extra goo to deal with additional reload insns.
9001 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9002 (const_int MAX_12BIT_OFFSET))
9004 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9005 (const_int MAX_17BIT_OFFSET))
9007 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9009 (eq (symbol_ref "flag_pic") (const_int 0))
9011 (const_int 32)))))])
9014 [(set (pc) (label_ref (match_operand 3 "" "" )))
9015 (set (match_operand:SI 0 "ireg_operand" "=r")
9016 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9017 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9018 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9021 return output_parallel_addb (operands, insn);
9023 [(set_attr "type" "parallel_branch")
9024 (set (attr "length")
9025 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9026 (const_int MAX_12BIT_OFFSET))
9028 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9029 (const_int MAX_17BIT_OFFSET))
9031 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9033 (eq (symbol_ref "flag_pic") (const_int 0))
9038 [(set (pc) (label_ref (match_operand 2 "" "" )))
9039 (set (match_operand:SF 0 "ireg_operand" "=r")
9040 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9044 return output_parallel_movb (operands, insn);
9046 [(set_attr "type" "parallel_branch")
9047 (set (attr "length")
9048 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9049 (const_int MAX_12BIT_OFFSET))
9051 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9052 (const_int MAX_17BIT_OFFSET))
9054 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9056 (eq (symbol_ref "flag_pic") (const_int 0))
9061 [(set (pc) (label_ref (match_operand 2 "" "" )))
9062 (set (match_operand:SI 0 "ireg_operand" "=r")
9063 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9067 return output_parallel_movb (operands, insn);
9069 [(set_attr "type" "parallel_branch")
9070 (set (attr "length")
9071 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9072 (const_int MAX_12BIT_OFFSET))
9074 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9075 (const_int MAX_17BIT_OFFSET))
9077 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9079 (eq (symbol_ref "flag_pic") (const_int 0))
9084 [(set (pc) (label_ref (match_operand 2 "" "" )))
9085 (set (match_operand:HI 0 "ireg_operand" "=r")
9086 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9090 return output_parallel_movb (operands, insn);
9092 [(set_attr "type" "parallel_branch")
9093 (set (attr "length")
9094 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9095 (const_int MAX_12BIT_OFFSET))
9097 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9098 (const_int MAX_17BIT_OFFSET))
9100 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9102 (eq (symbol_ref "flag_pic") (const_int 0))
9107 [(set (pc) (label_ref (match_operand 2 "" "" )))
9108 (set (match_operand:QI 0 "ireg_operand" "=r")
9109 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9113 return output_parallel_movb (operands, insn);
9115 [(set_attr "type" "parallel_branch")
9116 (set (attr "length")
9117 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9118 (const_int MAX_12BIT_OFFSET))
9120 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9121 (const_int MAX_17BIT_OFFSET))
9123 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9125 (eq (symbol_ref "flag_pic") (const_int 0))
9130 [(set (match_operand 0 "register_operand" "=f")
9131 (mult (match_operand 1 "register_operand" "f")
9132 (match_operand 2 "register_operand" "f")))
9133 (set (match_operand 3 "register_operand" "+f")
9134 (plus (match_operand 4 "register_operand" "f")
9135 (match_operand 5 "register_operand" "f")))]
9136 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9137 && reload_completed && fmpyaddoperands (operands)"
9140 if (GET_MODE (operands[0]) == DFmode)
9142 if (rtx_equal_p (operands[3], operands[5]))
9143 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9145 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9149 if (rtx_equal_p (operands[3], operands[5]))
9150 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9152 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9155 [(set_attr "type" "fpalu")
9156 (set_attr "length" "4")])
9159 [(set (match_operand 3 "register_operand" "+f")
9160 (plus (match_operand 4 "register_operand" "f")
9161 (match_operand 5 "register_operand" "f")))
9162 (set (match_operand 0 "register_operand" "=f")
9163 (mult (match_operand 1 "register_operand" "f")
9164 (match_operand 2 "register_operand" "f")))]
9165 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9166 && reload_completed && fmpyaddoperands (operands)"
9169 if (GET_MODE (operands[0]) == DFmode)
9171 if (rtx_equal_p (operands[3], operands[5]))
9172 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9174 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9178 if (rtx_equal_p (operands[3], operands[5]))
9179 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9181 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9184 [(set_attr "type" "fpalu")
9185 (set_attr "length" "4")])
9188 [(set (match_operand 0 "register_operand" "=f")
9189 (mult (match_operand 1 "register_operand" "f")
9190 (match_operand 2 "register_operand" "f")))
9191 (set (match_operand 3 "register_operand" "+f")
9192 (minus (match_operand 4 "register_operand" "f")
9193 (match_operand 5 "register_operand" "f")))]
9194 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9195 && reload_completed && fmpysuboperands (operands)"
9198 if (GET_MODE (operands[0]) == DFmode)
9199 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9201 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9203 [(set_attr "type" "fpalu")
9204 (set_attr "length" "4")])
9207 [(set (match_operand 3 "register_operand" "+f")
9208 (minus (match_operand 4 "register_operand" "f")
9209 (match_operand 5 "register_operand" "f")))
9210 (set (match_operand 0 "register_operand" "=f")
9211 (mult (match_operand 1 "register_operand" "f")
9212 (match_operand 2 "register_operand" "f")))]
9213 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9214 && reload_completed && fmpysuboperands (operands)"
9217 if (GET_MODE (operands[0]) == DFmode)
9218 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9220 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9222 [(set_attr "type" "fpalu")
9223 (set_attr "length" "4")])
9225 ;; The following two patterns are used by the trampoline code for nested
9226 ;; functions. They flush the I and D cache lines from the start address
9227 ;; (operand0) to the end address (operand1). No lines are flushed if the
9228 ;; end address is less than the start address (unsigned).
9230 ;; Because the range of memory flushed is variable and the size of a MEM
9231 ;; can only be a CONST_INT, the patterns specify that they perform an
9232 ;; unspecified volatile operation on all memory.
9234 ;; The address range for an icache flush must lie within a single
9235 ;; space on targets with non-equivalent space registers.
9237 ;; Operand 0 contains the start address.
9238 ;; Operand 1 contains the end address.
9239 ;; Operand 2 contains the line length to use.
9240 (define_insn "dcacheflush<P:mode>"
9242 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9243 (use (match_operand 0 "pmode_register_operand" "r"))
9244 (use (match_operand 1 "pmode_register_operand" "r"))
9245 (use (match_operand 2 "pmode_register_operand" "r"))
9246 (clobber (match_scratch:P 3 "=&0"))]
9248 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
9249 [(set_attr "type" "multi")
9250 (set_attr "length" "12")])
9252 (define_insn "icacheflush<P:mode>"
9254 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9255 (use (match_operand 0 "pmode_register_operand" "r"))
9256 (use (match_operand 1 "pmode_register_operand" "r"))
9257 (use (match_operand 2 "pmode_register_operand" "r"))
9258 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9259 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9260 (clobber (match_scratch:P 5 "=&0"))]
9262 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
9263 [(set_attr "type" "multi")
9264 (set_attr "length" "52")])
9266 ;; An out-of-line prologue.
9267 (define_insn "outline_prologue_call"
9268 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9269 (clobber (reg:SI 31))
9270 (clobber (reg:SI 22))
9271 (clobber (reg:SI 21))
9272 (clobber (reg:SI 20))
9273 (clobber (reg:SI 19))
9274 (clobber (reg:SI 1))]
9279 /* We need two different versions depending on whether or not we
9280 need a frame pointer. Also note that we return to the instruction
9281 immediately after the branch rather than two instructions after the
9282 break as normally is the case. */
9283 if (frame_pointer_needed)
9285 /* Must import the magic millicode routine(s). */
9286 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9288 if (TARGET_PORTABLE_RUNTIME)
9290 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9291 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9295 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9299 /* Must import the magic millicode routine(s). */
9300 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9302 if (TARGET_PORTABLE_RUNTIME)
9304 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9305 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9308 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9312 [(set_attr "type" "multi")
9313 (set_attr "length" "8")])
9315 ;; An out-of-line epilogue.
9316 (define_insn "outline_epilogue_call"
9317 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9320 (clobber (reg:SI 31))
9321 (clobber (reg:SI 22))
9322 (clobber (reg:SI 21))
9323 (clobber (reg:SI 20))
9324 (clobber (reg:SI 19))
9325 (clobber (reg:SI 2))
9326 (clobber (reg:SI 1))]
9331 /* We need two different versions depending on whether or not we
9332 need a frame pointer. Also note that we return to the instruction
9333 immediately after the branch rather than two instructions after the
9334 break as normally is the case. */
9335 if (frame_pointer_needed)
9337 /* Must import the magic millicode routine. */
9338 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9340 /* The out-of-line prologue will make sure we return to the right
9342 if (TARGET_PORTABLE_RUNTIME)
9344 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9345 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9349 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9353 /* Must import the magic millicode routine. */
9354 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9356 /* The out-of-line prologue will make sure we return to the right
9358 if (TARGET_PORTABLE_RUNTIME)
9360 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9361 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9364 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9368 [(set_attr "type" "multi")
9369 (set_attr "length" "8")])
9371 ;; Given a function pointer, canonicalize it so it can be
9372 ;; reliably compared to another function pointer. */
9373 (define_expand "canonicalize_funcptr_for_compare"
9374 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9375 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9376 (clobber (match_dup 2))
9377 (clobber (reg:SI 26))
9378 (clobber (reg:SI 22))
9379 (clobber (reg:SI 31))])
9380 (set (match_operand:SI 0 "register_operand" "")
9382 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9387 rtx canonicalize_funcptr_for_compare_libfunc
9388 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9390 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9391 operands[0], LCT_NORMAL, Pmode,
9392 1, operands[1], Pmode);
9396 operands[2] = gen_reg_rtx (SImode);
9397 if (GET_CODE (operands[1]) != REG)
9399 rtx tmp = gen_reg_rtx (Pmode);
9400 emit_move_insn (tmp, operands[1]);
9405 (define_insn "*$$sh_func_adrs"
9406 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9407 (clobber (match_operand:SI 0 "register_operand" "=a"))
9408 (clobber (reg:SI 26))
9409 (clobber (reg:SI 22))
9410 (clobber (reg:SI 31))]
9414 int length = get_attr_length (insn);
9417 xoperands[0] = GEN_INT (length - 8);
9418 xoperands[1] = GEN_INT (length - 16);
9420 /* Must import the magic millicode routine. */
9421 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9423 /* This is absolutely amazing.
9425 First, copy our input parameter into %r29 just in case we don't
9426 need to call $$sh_func_adrs. */
9427 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9428 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9430 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9431 we use %r26 unchanged. */
9432 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9433 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9435 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9436 4096, then again we use %r26 unchanged. */
9437 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9439 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9440 return output_millicode_call (insn,
9441 gen_rtx_SYMBOL_REF (SImode,
9442 \"$$sh_func_adrs\"));
9444 [(set_attr "type" "multi")
9445 (set (attr "length")
9446 (plus (symbol_ref "attr_length_millicode_call (insn)")
9449 ;; On the PA, the PIC register is call clobbered, so it must
9450 ;; be saved & restored around calls by the caller. If the call
9451 ;; doesn't return normally (nonlocal goto, or an exception is
9452 ;; thrown), then the code at the exception handler label must
9453 ;; restore the PIC register.
9454 (define_expand "exception_receiver"
9459 /* On the 64-bit port, we need a blockage because there is
9460 confusion regarding the dependence of the restore on the
9461 frame pointer. As a result, the frame pointer and pic
9462 register restores sometimes are interchanged erroneously. */
9464 emit_insn (gen_blockage ());
9465 /* Restore the PIC register using hppa_pic_save_rtx (). The
9466 PIC register is not saved in the frame in 64-bit ABI. */
9467 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9468 emit_insn (gen_blockage ());
9472 (define_expand "builtin_setjmp_receiver"
9473 [(label_ref (match_operand 0 "" ""))]
9478 emit_insn (gen_blockage ());
9479 /* Restore the PIC register. Hopefully, this will always be from
9480 a stack slot. The only registers that are valid after a
9481 builtin_longjmp are the stack and frame pointers. */
9482 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9483 emit_insn (gen_blockage ());
9487 ;; Allocate new stack space and update the saved stack pointer in the
9488 ;; frame marker. The HP C compilers also copy additional words in the
9489 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9490 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9491 ;; currently don't copy these values.
9493 ;; Since the copy of the frame marker can't be done atomically, I
9494 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9495 ;; The HP compilers appear to raise the stack and copy the frame
9496 ;; marker in a strict instruction sequence. This suggests that the
9497 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9498 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9499 ;; as GAS doesn't support it, or try to keep the instructions emitted
9500 ;; here in strict sequence.
9501 (define_expand "allocate_stack"
9502 [(match_operand 0 "" "")
9503 (match_operand 1 "" "")]
9509 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9510 in operand 0 before adjusting the stack. */
9511 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9512 anti_adjust_stack (operands[1]);
9513 if (TARGET_HPUX_UNWIND_LIBRARY)
9515 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9516 GEN_INT (TARGET_64BIT ? -8 : -4));
9517 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9519 if (!TARGET_64BIT && flag_pic)
9521 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9522 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9527 (define_expand "prefetch"
9528 [(match_operand 0 "address_operand" "")
9529 (match_operand 1 "const_int_operand" "")
9530 (match_operand 2 "const_int_operand" "")]
9533 int locality = INTVAL (operands[2]);
9535 gcc_assert (locality >= 0 && locality <= 3);
9537 /* Change operand[0] to a MEM as we don't have the infrastructure
9538 to output all the supported address modes for ldw/ldd when we use
9539 the address directly. However, we do have it for MEMs. */
9540 operands[0] = gen_rtx_MEM (QImode, operands[0]);
9542 /* If the address isn't valid for the prefetch, replace it. */
9545 if (!prefetch_nocc_operand (operands[0], QImode))
9547 = replace_equiv_address (operands[0],
9548 copy_to_mode_reg (Pmode,
9549 XEXP (operands[0], 0)));
9550 emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
9554 if (!prefetch_cc_operand (operands[0], QImode))
9556 = replace_equiv_address (operands[0],
9557 copy_to_mode_reg (Pmode,
9558 XEXP (operands[0], 0)));
9559 emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
9564 (define_insn "prefetch_cc"
9565 [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
9566 (match_operand:SI 1 "const_int_operand" "n")
9567 (match_operand:SI 2 "const_int_operand" "n"))]
9568 "TARGET_PA_20 && operands[2] == const0_rtx"
9570 /* The SL cache-control completor indicates good spatial locality but
9571 poor temporal locality. The ldw instruction with a target of general
9572 register 0 prefetches a cache line for a read. The ldd instruction
9573 prefetches a cache line for a write. */
9574 static const char * const instr[2] = {
9575 "ldw%M0,sl %0,%%r0",
9578 int read_or_write = INTVAL (operands[1]);
9580 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
9582 return instr [read_or_write];
9584 [(set_attr "type" "load")
9585 (set_attr "length" "4")])
9587 (define_insn "prefetch_nocc"
9588 [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
9589 (match_operand:SI 1 "const_int_operand" "n,n")
9590 (match_operand:SI 2 "const_int_operand" "n,n"))]
9591 "TARGET_PA_20 && operands[2] != const0_rtx"
9593 /* The ldw instruction with a target of general register 0 prefetches
9594 a cache line for a read. The ldd instruction prefetches a cache line
9596 static const char * const instr[2][2] = {
9606 int read_or_write = INTVAL (operands[1]);
9608 gcc_assert (which_alternative == 0 || which_alternative == 1);
9609 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
9611 return instr [which_alternative][read_or_write];
9613 [(set_attr "type" "load")
9614 (set_attr "length" "4")])
9618 (define_insn "tgd_load"
9619 [(set (match_operand:SI 0 "register_operand" "=r")
9620 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9621 (clobber (reg:SI 1))
9626 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9628 [(set_attr "type" "multi")
9629 (set_attr "length" "8")])
9631 (define_insn "tgd_load_pic"
9632 [(set (match_operand:SI 0 "register_operand" "=r")
9633 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
9634 (clobber (reg:SI 1))
9639 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9641 [(set_attr "type" "multi")
9642 (set_attr "length" "8")])
9644 (define_insn "tld_load"
9645 [(set (match_operand:SI 0 "register_operand" "=r")
9646 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
9647 (clobber (reg:SI 1))
9652 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
9654 [(set_attr "type" "multi")
9655 (set_attr "length" "8")])
9657 (define_insn "tld_load_pic"
9658 [(set (match_operand:SI 0 "register_operand" "=r")
9659 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
9660 (clobber (reg:SI 1))
9665 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
9667 [(set_attr "type" "multi")
9668 (set_attr "length" "8")])
9670 (define_insn "tld_offset_load"
9671 [(set (match_operand:SI 0 "register_operand" "=r")
9672 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
9674 (match_operand:SI 2 "register_operand" "r")))
9675 (clobber (reg:SI 1))]
9679 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
9681 [(set_attr "type" "multi")
9682 (set_attr "length" "8")])
9684 (define_insn "tp_load"
9685 [(set (match_operand:SI 0 "register_operand" "=r")
9686 (unspec:SI [(const_int 0)] UNSPEC_TP))]
9689 [(set_attr "type" "multi")
9690 (set_attr "length" "4")])
9692 (define_insn "tie_load"
9693 [(set (match_operand:SI 0 "register_operand" "=r")
9694 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
9695 (clobber (reg:SI 1))
9700 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
9702 [(set_attr "type" "multi")
9703 (set_attr "length" "8")])
9705 (define_insn "tie_load_pic"
9706 [(set (match_operand:SI 0 "register_operand" "=r")
9707 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
9708 (clobber (reg:SI 1))
9713 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
9715 [(set_attr "type" "multi")
9716 (set_attr "length" "8")])
9718 (define_insn "tle_load"
9719 [(set (match_operand:SI 0 "register_operand" "=r")
9720 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
9722 (match_operand:SI 2 "register_operand" "r")))
9723 (clobber (reg:SI 1))]
9725 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
9726 [(set_attr "type" "multi")
9727 (set_attr "length" "8")])