1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
629 ;; placeholders. This is necessary in rare situations when a
630 ;; placeholder is re-emitted (see PR 8705).
632 (define_expand "movccfp"
634 (match_operand 0 "const_int_operand" ""))]
635 "! TARGET_SOFT_FLOAT"
638 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
642 ;; The following patterns are optimization placeholders. In almost
643 ;; all cases, the user of the condition code will be simplified and the
644 ;; original condition code setting insn should be eliminated.
646 (define_insn "*movccfp0"
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,dbl,= %%fr0,%%fr0"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
654 (define_insn "*movccfp1"
657 "! TARGET_SOFT_FLOAT"
658 "fcmp,dbl,!= %%fr0,%%fr0"
659 [(set_attr "length" "4")
660 (set_attr "type" "fpcc")])
665 [(set (match_operand:SI 0 "register_operand" "")
671 /* fp scc patterns rarely match, and are not a win on the PA. */
672 if (hppa_branch_type != CMP_SI)
674 /* set up operands from compare. */
675 operands[1] = hppa_compare_op0;
676 operands[2] = hppa_compare_op1;
677 /* fall through and generate default code */
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
737 [(set (match_operand:SI 0 "register_operand" "")
743 /* fp scc patterns rarely match, and are not a win on the PA. */
744 if (hppa_branch_type != CMP_SI)
746 operands[1] = hppa_compare_op0;
747 operands[2] = hppa_compare_op1;
750 (define_expand "sltu"
751 [(set (match_operand:SI 0 "register_operand" "")
752 (ltu:SI (match_dup 1)
757 if (hppa_branch_type != CMP_SI)
759 operands[1] = hppa_compare_op0;
760 operands[2] = hppa_compare_op1;
763 (define_expand "sgtu"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (gtu:SI (match_dup 1)
770 if (hppa_branch_type != CMP_SI)
772 operands[1] = hppa_compare_op0;
773 operands[2] = hppa_compare_op1;
776 (define_expand "sleu"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (leu:SI (match_dup 1)
783 if (hppa_branch_type != CMP_SI)
785 operands[1] = hppa_compare_op0;
786 operands[2] = hppa_compare_op1;
789 (define_expand "sgeu"
790 [(set (match_operand:SI 0 "register_operand" "")
791 (geu:SI (match_dup 1)
796 if (hppa_branch_type != CMP_SI)
798 operands[1] = hppa_compare_op0;
799 operands[2] = hppa_compare_op1;
802 ;; Instruction canonicalization puts immediate operands second, which
803 ;; is the reverse of what we want.
806 [(set (match_operand:SI 0 "register_operand" "=r")
807 (match_operator:SI 3 "comparison_operator"
808 [(match_operand:SI 1 "register_operand" "r")
809 (match_operand:SI 2 "arith11_operand" "rI")]))]
811 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
812 [(set_attr "type" "binary")
813 (set_attr "length" "8")])
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (match_operator:DI 3 "comparison_operator"
818 [(match_operand:DI 1 "register_operand" "r")
819 (match_operand:DI 2 "arith11_operand" "rI")]))]
821 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
822 [(set_attr "type" "binary")
823 (set_attr "length" "8")])
825 (define_insn "iorscc"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (ior:SI (match_operator:SI 3 "comparison_operator"
828 [(match_operand:SI 1 "register_operand" "r")
829 (match_operand:SI 2 "arith11_operand" "rI")])
830 (match_operator:SI 6 "comparison_operator"
831 [(match_operand:SI 4 "register_operand" "r")
832 (match_operand:SI 5 "arith11_operand" "rI")])))]
834 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "12")])
839 [(set (match_operand:DI 0 "register_operand" "=r")
840 (ior:DI (match_operator:DI 3 "comparison_operator"
841 [(match_operand:DI 1 "register_operand" "r")
842 (match_operand:DI 2 "arith11_operand" "rI")])
843 (match_operator:DI 6 "comparison_operator"
844 [(match_operand:DI 4 "register_operand" "r")
845 (match_operand:DI 5 "arith11_operand" "rI")])))]
847 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "12")])
851 ;; Combiner patterns for common operations performed with the output
852 ;; from an scc insn (negscc and incscc).
853 (define_insn "negscc"
854 [(set (match_operand:SI 0 "register_operand" "=r")
855 (neg:SI (match_operator:SI 3 "comparison_operator"
856 [(match_operand:SI 1 "register_operand" "r")
857 (match_operand:SI 2 "arith11_operand" "rI")])))]
859 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (neg:DI (match_operator:DI 3 "comparison_operator"
866 [(match_operand:DI 1 "register_operand" "r")
867 (match_operand:DI 2 "arith11_operand" "rI")])))]
869 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
870 [(set_attr "type" "binary")
871 (set_attr "length" "8")])
873 ;; Patterns for adding/subtracting the result of a boolean expression from
874 ;; a register. First we have special patterns that make use of the carry
875 ;; bit, and output only two instructions. For the cases we can't in
876 ;; general do in two instructions, the incscc pattern at the end outputs
877 ;; two or three instructions.
880 [(set (match_operand:SI 0 "register_operand" "=r")
881 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
882 (match_operand:SI 3 "arith11_operand" "rI"))
883 (match_operand:SI 1 "register_operand" "r")))]
885 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
886 [(set_attr "type" "binary")
887 (set_attr "length" "8")])
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
892 (match_operand:DI 3 "arith11_operand" "rI"))
893 (match_operand:DI 1 "register_operand" "r")))]
895 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
899 ; This need only accept registers for op3, since canonicalization
900 ; replaces geu with gtu when op3 is an integer.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
904 (match_operand:SI 3 "register_operand" "r"))
905 (match_operand:SI 1 "register_operand" "r")))]
907 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
914 (match_operand:DI 3 "register_operand" "r"))
915 (match_operand:DI 1 "register_operand" "r")))]
917 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 ; Match only integers for op3 here. This is used as canonical form of the
922 ; geu pattern when op3 is an integer. Don't match registers since we can't
923 ; make better code than the general incscc pattern.
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
927 (match_operand:SI 3 "int11_operand" "I"))
928 (match_operand:SI 1 "register_operand" "r")))]
930 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "8")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
937 (match_operand:DI 3 "int11_operand" "I"))
938 (match_operand:DI 1 "register_operand" "r")))]
940 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "8")])
944 (define_insn "incscc"
945 [(set (match_operand:SI 0 "register_operand" "=r,r")
946 (plus:SI (match_operator:SI 4 "comparison_operator"
947 [(match_operand:SI 2 "register_operand" "r,r")
948 (match_operand:SI 3 "arith11_operand" "rI,rI")])
949 (match_operand:SI 1 "register_operand" "0,?r")))]
952 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
953 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
954 [(set_attr "type" "binary,binary")
955 (set_attr "length" "8,12")])
958 [(set (match_operand:DI 0 "register_operand" "=r,r")
959 (plus:DI (match_operator:DI 4 "comparison_operator"
960 [(match_operand:DI 2 "register_operand" "r,r")
961 (match_operand:DI 3 "arith11_operand" "rI,rI")])
962 (match_operand:DI 1 "register_operand" "0,?r")))]
965 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
966 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
967 [(set_attr "type" "binary,binary")
968 (set_attr "length" "8,12")])
971 [(set (match_operand:SI 0 "register_operand" "=r")
972 (minus:SI (match_operand:SI 1 "register_operand" "r")
973 (gtu:SI (match_operand:SI 2 "register_operand" "r")
974 (match_operand:SI 3 "arith11_operand" "rI"))))]
976 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
981 [(set (match_operand:DI 0 "register_operand" "=r")
982 (minus:DI (match_operand:DI 1 "register_operand" "r")
983 (gtu:DI (match_operand:DI 2 "register_operand" "r")
984 (match_operand:DI 3 "arith11_operand" "rI"))))]
986 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
993 (gtu:SI (match_operand:SI 2 "register_operand" "r")
994 (match_operand:SI 3 "arith11_operand" "rI")))
995 (match_operand:SI 4 "register_operand" "r")))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI")))
1006 (match_operand:DI 4 "register_operand" "r")))]
1008 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1009 [(set_attr "type" "binary")
1010 (set_attr "length" "8")])
1012 ; This need only accept registers for op3, since canonicalization
1013 ; replaces ltu with leu when op3 is an integer.
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (minus:SI (match_operand:SI 1 "register_operand" "r")
1017 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1018 (match_operand:SI 3 "register_operand" "r"))))]
1020 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1021 [(set_attr "type" "binary")
1022 (set_attr "length" "8")])
1025 [(set (match_operand:DI 0 "register_operand" "=r")
1026 (minus:DI (match_operand:DI 1 "register_operand" "r")
1027 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1028 (match_operand:DI 3 "register_operand" "r"))))]
1030 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1031 [(set_attr "type" "binary")
1032 (set_attr "length" "8")])
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1037 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1038 (match_operand:SI 3 "register_operand" "r")))
1039 (match_operand:SI 4 "register_operand" "r")))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r")))
1050 (match_operand:DI 4 "register_operand" "r")))]
1052 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1053 [(set_attr "type" "binary")
1054 (set_attr "length" "8")])
1056 ; Match only integers for op3 here. This is used as canonical form of the
1057 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1058 ; make better code than the general incscc pattern.
1060 [(set (match_operand:SI 0 "register_operand" "=r")
1061 (minus:SI (match_operand:SI 1 "register_operand" "r")
1062 (leu:SI (match_operand:SI 2 "register_operand" "r")
1063 (match_operand:SI 3 "int11_operand" "I"))))]
1065 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1066 [(set_attr "type" "binary")
1067 (set_attr "length" "8")])
1070 [(set (match_operand:DI 0 "register_operand" "=r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "r")
1072 (leu:DI (match_operand:DI 2 "register_operand" "r")
1073 (match_operand:DI 3 "int11_operand" "I"))))]
1075 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1076 [(set_attr "type" "binary")
1077 (set_attr "length" "8")])
1080 [(set (match_operand:SI 0 "register_operand" "=r")
1081 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1082 (leu:SI (match_operand:SI 2 "register_operand" "r")
1083 (match_operand:SI 3 "int11_operand" "I")))
1084 (match_operand:SI 4 "register_operand" "r")))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I")))
1095 (match_operand:DI 4 "register_operand" "r")))]
1097 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1098 [(set_attr "type" "binary")
1099 (set_attr "length" "8")])
1101 (define_insn "decscc"
1102 [(set (match_operand:SI 0 "register_operand" "=r,r")
1103 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1104 (match_operator:SI 4 "comparison_operator"
1105 [(match_operand:SI 2 "register_operand" "r,r")
1106 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1109 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1110 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1111 [(set_attr "type" "binary,binary")
1112 (set_attr "length" "8,12")])
1115 [(set (match_operand:DI 0 "register_operand" "=r,r")
1116 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1117 (match_operator:DI 4 "comparison_operator"
1118 [(match_operand:DI 2 "register_operand" "r,r")
1119 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1122 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1123 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1124 [(set_attr "type" "binary,binary")
1125 (set_attr "length" "8,12")])
1127 ; Patterns for max and min. (There is no need for an earlyclobber in the
1128 ; last alternative since the middle alternative will match if op0 == op1.)
1130 (define_insn "sminsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1132 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1133 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1136 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1137 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1138 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1139 [(set_attr "type" "multi,multi,multi")
1140 (set_attr "length" "8,8,8")])
1142 (define_insn "smindi3"
1143 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1144 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1145 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1148 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1149 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1150 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1151 [(set_attr "type" "multi,multi,multi")
1152 (set_attr "length" "8,8,8")])
1154 (define_insn "uminsi3"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1157 (match_operand:SI 2 "arith11_operand" "r,I")))]
1160 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1161 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1162 [(set_attr "type" "multi,multi")
1163 (set_attr "length" "8,8")])
1165 (define_insn "umindi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1168 (match_operand:DI 2 "arith11_operand" "r,I")))]
1171 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1172 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1173 [(set_attr "type" "multi,multi")
1174 (set_attr "length" "8,8")])
1176 (define_insn "smaxsi3"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1178 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1179 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1182 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1183 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1184 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1185 [(set_attr "type" "multi,multi,multi")
1186 (set_attr "length" "8,8,8")])
1188 (define_insn "smaxdi3"
1189 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1190 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1191 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1194 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1195 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1196 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1197 [(set_attr "type" "multi,multi,multi")
1198 (set_attr "length" "8,8,8")])
1200 (define_insn "umaxsi3"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1203 (match_operand:SI 2 "arith11_operand" "r,I")))]
1206 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1207 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1208 [(set_attr "type" "multi,multi")
1209 (set_attr "length" "8,8")])
1211 (define_insn "umaxdi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1214 (match_operand:DI 2 "arith11_operand" "r,I")))]
1217 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1218 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1219 [(set_attr "type" "multi,multi")
1220 (set_attr "length" "8,8")])
1222 (define_insn "abssi2"
1223 [(set (match_operand:SI 0 "register_operand" "=r")
1224 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "8")])
1230 (define_insn "absdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=r")
1232 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1234 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1235 [(set_attr "type" "multi")
1236 (set_attr "length" "8")])
1238 ;;; Experimental conditional move patterns
1240 (define_expand "movsicc"
1241 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operator 1 "comparison_operator"
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 enum rtx_code code = GET_CODE (operands[1]);
1253 if (hppa_branch_type != CMP_SI)
1256 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1257 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1260 /* operands[1] is currently the result of compare_from_rtx. We want to
1261 emit a compare of the original operands. */
1262 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1263 operands[4] = hppa_compare_op0;
1264 operands[5] = hppa_compare_op1;
1267 ;; We used to accept any register for op1.
1269 ;; However, it loses sometimes because the compiler will end up using
1270 ;; different registers for op0 and op1 in some critical cases. local-alloc
1271 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1273 ;; If/when global register allocation supports tying we should allow any
1274 ;; register for op1 again.
1276 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1278 (match_operator 2 "comparison_operator"
1279 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1280 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1281 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1285 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1286 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1287 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1288 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1289 [(set_attr "type" "multi,multi,multi,nullshift")
1290 (set_attr "length" "8,8,8,8")])
1293 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1295 (match_operator 5 "comparison_operator"
1296 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1297 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1298 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1299 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1302 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1303 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1304 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1305 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1306 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1307 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1308 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1309 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1310 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1311 (set_attr "length" "8,8,8,8,8,8,8,8")])
1313 (define_expand "movdicc"
1314 [(set (match_operand:DI 0 "register_operand" "")
1316 (match_operator 1 "comparison_operator"
1319 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1320 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1324 enum rtx_code code = GET_CODE (operands[1]);
1326 if (hppa_branch_type != CMP_SI)
1329 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1330 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1333 /* operands[1] is currently the result of compare_from_rtx. We want to
1334 emit a compare of the original operands. */
1335 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1336 operands[4] = hppa_compare_op0;
1337 operands[5] = hppa_compare_op1;
1340 ; We need the first constraint alternative in order to avoid
1341 ; earlyclobbers on all other alternatives.
1343 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1345 (match_operator 2 "comparison_operator"
1346 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1347 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1348 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1352 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1353 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1354 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1355 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1356 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1357 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1358 (set_attr "length" "8,8,8,8,8")])
1361 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1363 (match_operator 5 "comparison_operator"
1364 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1365 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1366 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1367 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1370 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1371 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1372 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1373 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1374 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1375 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1376 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1377 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1378 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1379 (set_attr "length" "8,8,8,8,8,8,8,8")])
1381 ;; Conditional Branches
1383 (define_expand "beq"
1385 (if_then_else (eq (match_dup 1) (match_dup 2))
1386 (label_ref (match_operand 0 "" ""))
1391 if (hppa_branch_type != CMP_SI)
1393 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1394 emit_bcond_fp (NE, operands[0]);
1397 /* set up operands from compare. */
1398 operands[1] = hppa_compare_op0;
1399 operands[2] = hppa_compare_op1;
1400 /* fall through and generate default code */
1403 (define_expand "bne"
1405 (if_then_else (ne (match_dup 1) (match_dup 2))
1406 (label_ref (match_operand 0 "" ""))
1411 if (hppa_branch_type != CMP_SI)
1413 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1414 emit_bcond_fp (NE, operands[0]);
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1421 (define_expand "bgt"
1423 (if_then_else (gt (match_dup 1) (match_dup 2))
1424 (label_ref (match_operand 0 "" ""))
1429 if (hppa_branch_type != CMP_SI)
1431 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1432 emit_bcond_fp (NE, operands[0]);
1435 operands[1] = hppa_compare_op0;
1436 operands[2] = hppa_compare_op1;
1439 (define_expand "blt"
1441 (if_then_else (lt (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bge"
1459 (if_then_else (ge (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "ble"
1477 (if_then_else (le (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bgtu"
1495 (if_then_else (gtu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bltu"
1509 (if_then_else (ltu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bgeu"
1523 (if_then_else (geu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bleu"
1537 (if_then_else (leu (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 operands[1] = hppa_compare_op0;
1546 operands[2] = hppa_compare_op1;
1549 (define_expand "bltgt"
1551 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1552 (label_ref (match_operand 0 "" ""))
1557 if (hppa_branch_type == CMP_SI)
1559 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1560 emit_bcond_fp (NE, operands[0]);
1564 (define_expand "bunle"
1566 (if_then_else (unle (match_dup 1) (match_dup 2))
1567 (label_ref (match_operand 0 "" ""))
1572 if (hppa_branch_type == CMP_SI)
1574 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1575 emit_bcond_fp (NE, operands[0]);
1579 (define_expand "bunlt"
1581 (if_then_else (unlt (match_dup 1) (match_dup 2))
1582 (label_ref (match_operand 0 "" ""))
1587 if (hppa_branch_type == CMP_SI)
1589 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1590 emit_bcond_fp (NE, operands[0]);
1594 (define_expand "bunge"
1596 (if_then_else (unge (match_dup 1) (match_dup 2))
1597 (label_ref (match_operand 0 "" ""))
1602 if (hppa_branch_type == CMP_SI)
1604 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1605 emit_bcond_fp (NE, operands[0]);
1609 (define_expand "bungt"
1611 (if_then_else (ungt (match_dup 1) (match_dup 2))
1612 (label_ref (match_operand 0 "" ""))
1617 if (hppa_branch_type == CMP_SI)
1619 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1620 emit_bcond_fp (NE, operands[0]);
1624 (define_expand "buneq"
1626 (if_then_else (uneq (match_dup 1) (match_dup 2))
1627 (label_ref (match_operand 0 "" ""))
1632 if (hppa_branch_type == CMP_SI)
1634 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1635 emit_bcond_fp (NE, operands[0]);
1639 (define_expand "bunordered"
1641 (if_then_else (unordered (match_dup 1) (match_dup 2))
1642 (label_ref (match_operand 0 "" ""))
1647 if (hppa_branch_type == CMP_SI)
1649 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1650 emit_bcond_fp (NE, operands[0]);
1654 (define_expand "bordered"
1656 (if_then_else (ordered (match_dup 1) (match_dup 2))
1657 (label_ref (match_operand 0 "" ""))
1662 if (hppa_branch_type == CMP_SI)
1664 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1665 emit_bcond_fp (NE, operands[0]);
1669 ;; Match the branch patterns.
1672 ;; Note a long backward conditional branch with an annulled delay slot
1673 ;; has a length of 12.
1677 (match_operator 3 "comparison_operator"
1678 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1679 (match_operand:SI 2 "arith5_operand" "rL")])
1680 (label_ref (match_operand 0 "" ""))
1685 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1686 get_attr_length (insn), 0, insn);
1688 [(set_attr "type" "cbranch")
1689 (set (attr "length")
1690 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1696 (eq (symbol_ref "flag_pic") (const_int 0))
1700 ;; Match the negated branch.
1705 (match_operator 3 "comparison_operator"
1706 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1707 (match_operand:SI 2 "arith5_operand" "rL")])
1709 (label_ref (match_operand 0 "" ""))))]
1713 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1714 get_attr_length (insn), 1, insn);
1716 [(set_attr "type" "cbranch")
1717 (set (attr "length")
1718 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1721 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1724 (eq (symbol_ref "flag_pic") (const_int 0))
1731 (match_operator 3 "comparison_operator"
1732 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1733 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1734 (label_ref (match_operand 0 "" ""))
1739 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1740 get_attr_length (insn), 0, insn);
1742 [(set_attr "type" "cbranch")
1743 (set (attr "length")
1744 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1750 (eq (symbol_ref "flag_pic") (const_int 0))
1754 ;; Match the negated branch.
1759 (match_operator 3 "comparison_operator"
1760 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1761 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1763 (label_ref (match_operand 0 "" ""))))]
1767 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1768 get_attr_length (insn), 1, insn);
1770 [(set_attr "type" "cbranch")
1771 (set (attr "length")
1772 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1775 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1778 (eq (symbol_ref "flag_pic") (const_int 0))
1784 (match_operator 3 "cmpib_comparison_operator"
1785 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1786 (match_operand:DI 2 "arith5_operand" "rL")])
1787 (label_ref (match_operand 0 "" ""))
1792 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1793 get_attr_length (insn), 0, insn);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "cmpib_comparison_operator"
1813 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1814 (match_operand:DI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1835 ;; Branch on Bit patterns.
1839 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1841 (match_operand:SI 1 "uint5_operand" ""))
1843 (label_ref (match_operand 2 "" ""))
1848 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1849 get_attr_length (insn), 0, insn, 0);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1861 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1863 (match_operand:DI 1 "uint32_operand" ""))
1865 (label_ref (match_operand 2 "" ""))
1870 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1871 get_attr_length (insn), 0, insn, 0);
1873 [(set_attr "type" "cbranch")
1874 (set (attr "length")
1875 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1885 (match_operand:SI 1 "uint5_operand" ""))
1888 (label_ref (match_operand 2 "" ""))))]
1892 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1893 get_attr_length (insn), 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1905 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1907 (match_operand:DI 1 "uint32_operand" ""))
1910 (label_ref (match_operand 2 "" ""))))]
1914 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1915 get_attr_length (insn), 1, insn, 0);
1917 [(set_attr "type" "cbranch")
1918 (set (attr "length")
1919 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1927 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "uint5_operand" ""))
1931 (label_ref (match_operand 2 "" ""))
1936 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1937 get_attr_length (insn), 0, insn, 1);
1939 [(set_attr "type" "cbranch")
1940 (set (attr "length")
1941 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "uint32_operand" ""))
1953 (label_ref (match_operand 2 "" ""))
1958 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1959 get_attr_length (insn), 0, insn, 1);
1961 [(set_attr "type" "cbranch")
1962 (set (attr "length")
1963 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1971 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1973 (match_operand:SI 1 "uint5_operand" ""))
1976 (label_ref (match_operand 2 "" ""))))]
1980 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1981 get_attr_length (insn), 1, insn, 1);
1983 [(set_attr "type" "cbranch")
1984 (set (attr "length")
1985 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1995 (match_operand:DI 1 "uint32_operand" ""))
1998 (label_ref (match_operand 2 "" ""))))]
2002 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2003 get_attr_length (insn), 1, insn, 1);
2005 [(set_attr "type" "cbranch")
2006 (set (attr "length")
2007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 ;; Branch on Variable Bit patterns.
2016 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "q"))
2020 (label_ref (match_operand 2 "" ""))
2025 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2026 get_attr_length (insn), 0, insn, 0);
2028 [(set_attr "type" "cbranch")
2029 (set (attr "length")
2030 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2040 (match_operand:DI 1 "register_operand" "q"))
2042 (label_ref (match_operand 2 "" ""))
2047 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2048 get_attr_length (insn), 0, insn, 0);
2050 [(set_attr "type" "cbranch")
2051 (set (attr "length")
2052 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2060 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "q"))
2065 (label_ref (match_operand 2 "" ""))))]
2069 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2070 get_attr_length (insn), 1, insn, 0);
2072 [(set_attr "type" "cbranch")
2073 (set (attr "length")
2074 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2082 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2084 (match_operand:DI 1 "register_operand" "q"))
2087 (label_ref (match_operand 2 "" ""))))]
2091 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2092 get_attr_length (insn), 1, insn, 0);
2094 [(set_attr "type" "cbranch")
2095 (set (attr "length")
2096 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2104 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2106 (match_operand:SI 1 "register_operand" "q"))
2108 (label_ref (match_operand 2 "" ""))
2113 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2114 get_attr_length (insn), 0, insn, 1);
2116 [(set_attr "type" "cbranch")
2117 (set (attr "length")
2118 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2128 (match_operand:DI 1 "register_operand" "q"))
2130 (label_ref (match_operand 2 "" ""))
2135 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2136 get_attr_length (insn), 0, insn, 1);
2138 [(set_attr "type" "cbranch")
2139 (set (attr "length")
2140 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2150 (match_operand:SI 1 "register_operand" "q"))
2153 (label_ref (match_operand 2 "" ""))))]
2157 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2158 get_attr_length (insn), 1, insn, 1);
2160 [(set_attr "type" "cbranch")
2161 (set (attr "length")
2162 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2170 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2172 (match_operand:DI 1 "register_operand" "q"))
2175 (label_ref (match_operand 2 "" ""))))]
2179 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2180 get_attr_length (insn), 1, insn, 1);
2182 [(set_attr "type" "cbranch")
2183 (set (attr "length")
2184 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 ;; Floating point branches
2191 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2192 (label_ref (match_operand 0 "" ""))
2194 "! TARGET_SOFT_FLOAT"
2197 if (INSN_ANNULLED_BRANCH_P (insn))
2198 return \"ftest\;b,n %0\";
2200 return \"ftest\;b%* %0\";
2202 [(set_attr "type" "fbranch")
2203 (set_attr "length" "8")])
2206 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2208 (label_ref (match_operand 0 "" ""))))]
2209 "! TARGET_SOFT_FLOAT"
2212 if (INSN_ANNULLED_BRANCH_P (insn))
2213 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2215 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2217 [(set_attr "type" "fbranch")
2218 (set_attr "length" "12")])
2220 ;; Move instructions
2222 (define_expand "movsi"
2223 [(set (match_operand:SI 0 "general_operand" "")
2224 (match_operand:SI 1 "general_operand" ""))]
2228 if (emit_move_sequence (operands, SImode, 0))
2232 ;; Reloading an SImode or DImode value requires a scratch register if
2233 ;; going in to or out of float point registers.
2235 (define_expand "reload_insi"
2236 [(set (match_operand:SI 0 "register_operand" "=Z")
2237 (match_operand:SI 1 "non_hard_reg_operand" ""))
2238 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2242 if (emit_move_sequence (operands, SImode, operands[2]))
2245 /* We don't want the clobber emitted, so handle this ourselves. */
2246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2250 (define_expand "reload_outsi"
2251 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2252 (match_operand:SI 1 "register_operand" "Z"))
2253 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2257 if (emit_move_sequence (operands, SImode, operands[2]))
2260 /* We don't want the clobber emitted, so handle this ourselves. */
2261 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2266 [(set (match_operand:SI 0 "move_dest_operand"
2267 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2268 (match_operand:SI 1 "move_src_operand"
2269 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2270 "(register_operand (operands[0], SImode)
2271 || reg_or_0_operand (operands[1], SImode))
2272 && !TARGET_SOFT_FLOAT"
2278 {zdepi|depwi,z} %Z1,%0
2282 {mfctl|mfctl,w} %%sar,%0
2286 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2287 (set_attr "pa_combine_type" "addmove")
2288 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2291 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2292 (match_operand:SI 1 "register_operand" "f"))]
2294 && !TARGET_DISABLE_INDEXING
2295 && reload_completed"
2297 [(set_attr "type" "fpstore")
2298 (set_attr "pa_combine_type" "addmove")
2299 (set_attr "length" "4")])
2301 ; Rewrite RTL using an indexed store. This will allow the insn that
2302 ; computes the address to be deleted if the register it sets is dead.
2304 [(set (match_operand:SI 0 "register_operand" "")
2305 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2307 (match_operand:SI 2 "register_operand" "")))
2308 (set (mem:SI (match_dup 0))
2309 (match_operand:SI 3 "register_operand" ""))]
2311 && REG_OK_FOR_BASE_P (operands[2])
2312 && FP_REGNO_P (REGNO (operands[3]))"
2313 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2315 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2320 [(set (match_operand:SI 0 "register_operand" "")
2321 (plus:SI (match_operand:SI 2 "register_operand" "")
2322 (mult:SI (match_operand:SI 1 "register_operand" "")
2324 (set (mem:SI (match_dup 0))
2325 (match_operand:SI 3 "register_operand" ""))]
2327 && REG_OK_FOR_BASE_P (operands[2])
2328 && FP_REGNO_P (REGNO (operands[3]))"
2329 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2331 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2336 [(set (match_operand:DI 0 "register_operand" "")
2337 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2339 (match_operand:DI 2 "register_operand" "")))
2340 (set (mem:SI (match_dup 0))
2341 (match_operand:SI 3 "register_operand" ""))]
2344 && REG_OK_FOR_BASE_P (operands[2])
2345 && FP_REGNO_P (REGNO (operands[3]))"
2346 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2348 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2353 [(set (match_operand:DI 0 "register_operand" "")
2354 (plus:DI (match_operand:DI 2 "register_operand" "")
2355 (mult:DI (match_operand:DI 1 "register_operand" "")
2357 (set (mem:SI (match_dup 0))
2358 (match_operand:SI 3 "register_operand" ""))]
2361 && REG_OK_FOR_BASE_P (operands[2])
2362 && FP_REGNO_P (REGNO (operands[3]))"
2363 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2365 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2370 [(set (match_operand:SI 0 "register_operand" "")
2371 (plus:SI (match_operand:SI 1 "register_operand" "")
2372 (match_operand:SI 2 "register_operand" "")))
2373 (set (mem:SI (match_dup 0))
2374 (match_operand:SI 3 "register_operand" ""))]
2376 && REG_OK_FOR_BASE_P (operands[1])
2377 && (TARGET_NO_SPACE_REGS
2378 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2379 && FP_REGNO_P (REGNO (operands[3]))"
2380 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2382 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2386 [(set (match_operand:SI 0 "register_operand" "")
2387 (plus:SI (match_operand:SI 1 "register_operand" "")
2388 (match_operand:SI 2 "register_operand" "")))
2389 (set (mem:SI (match_dup 0))
2390 (match_operand:SI 3 "register_operand" ""))]
2392 && REG_OK_FOR_BASE_P (operands[2])
2393 && (TARGET_NO_SPACE_REGS
2394 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2395 && FP_REGNO_P (REGNO (operands[3]))"
2396 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2398 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2402 [(set (match_operand:DI 0 "register_operand" "")
2403 (plus:DI (match_operand:DI 1 "register_operand" "")
2404 (match_operand:DI 2 "register_operand" "")))
2405 (set (mem:SI (match_dup 0))
2406 (match_operand:SI 3 "register_operand" ""))]
2409 && REG_OK_FOR_BASE_P (operands[1])
2410 && (TARGET_NO_SPACE_REGS
2411 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2412 && FP_REGNO_P (REGNO (operands[3]))"
2413 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2415 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2419 [(set (match_operand:DI 0 "register_operand" "")
2420 (plus:DI (match_operand:DI 1 "register_operand" "")
2421 (match_operand:DI 2 "register_operand" "")))
2422 (set (mem:SI (match_dup 0))
2423 (match_operand:SI 3 "register_operand" ""))]
2426 && REG_OK_FOR_BASE_P (operands[2])
2427 && (TARGET_NO_SPACE_REGS
2428 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2429 && FP_REGNO_P (REGNO (operands[3]))"
2430 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2432 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2436 [(set (match_operand:SI 0 "move_dest_operand"
2437 "=r,r,r,r,r,r,Q,!*q,!r")
2438 (match_operand:SI 1 "move_src_operand"
2439 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2440 "(register_operand (operands[0], SImode)
2441 || reg_or_0_operand (operands[1], SImode))
2442 && TARGET_SOFT_FLOAT"
2448 {zdepi|depwi,z} %Z1,%0
2452 {mfctl|mfctl,w} %%sar,%0"
2453 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2454 (set_attr "pa_combine_type" "addmove")
2455 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2457 ;; Load or store with base-register modification.
2459 [(set (match_operand:SI 0 "register_operand" "=r")
2460 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2461 (match_operand:DI 2 "int5_operand" "L"))))
2463 (plus:DI (match_dup 1) (match_dup 2)))]
2466 [(set_attr "type" "load")
2467 (set_attr "length" "4")])
2469 ; And a zero extended variant.
2471 [(set (match_operand:DI 0 "register_operand" "=r")
2472 (zero_extend:DI (mem:SI
2474 (match_operand:DI 1 "register_operand" "+r")
2475 (match_operand:DI 2 "int5_operand" "L")))))
2477 (plus:DI (match_dup 1) (match_dup 2)))]
2480 [(set_attr "type" "load")
2481 (set_attr "length" "4")])
2483 (define_expand "pre_load"
2484 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2485 (mem (plus (match_operand 1 "register_operand" "")
2486 (match_operand 2 "pre_cint_operand" ""))))
2488 (plus (match_dup 1) (match_dup 2)))])]
2494 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2497 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2501 (define_insn "pre_ldw"
2502 [(set (match_operand:SI 0 "register_operand" "=r")
2503 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2504 (match_operand:SI 2 "pre_cint_operand" ""))))
2506 (plus:SI (match_dup 1) (match_dup 2)))]
2510 if (INTVAL (operands[2]) < 0)
2511 return \"{ldwm|ldw,mb} %2(%1),%0\";
2512 return \"{ldws|ldw},mb %2(%1),%0\";
2514 [(set_attr "type" "load")
2515 (set_attr "length" "4")])
2517 (define_insn "pre_ldd"
2518 [(set (match_operand:DI 0 "register_operand" "=r")
2519 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2520 (match_operand:DI 2 "pre_cint_operand" ""))))
2522 (plus:DI (match_dup 1) (match_dup 2)))]
2525 [(set_attr "type" "load")
2526 (set_attr "length" "4")])
2529 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2530 (match_operand:SI 1 "pre_cint_operand" "")))
2531 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2533 (plus:SI (match_dup 0) (match_dup 1)))]
2537 if (INTVAL (operands[1]) < 0)
2538 return \"{stwm|stw,mb} %r2,%1(%0)\";
2539 return \"{stws|stw},mb %r2,%1(%0)\";
2541 [(set_attr "type" "store")
2542 (set_attr "length" "4")])
2545 [(set (match_operand:SI 0 "register_operand" "=r")
2546 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2548 (plus:SI (match_dup 1)
2549 (match_operand:SI 2 "post_cint_operand" "")))]
2553 if (INTVAL (operands[2]) > 0)
2554 return \"{ldwm|ldw,ma} %2(%1),%0\";
2555 return \"{ldws|ldw},ma %2(%1),%0\";
2557 [(set_attr "type" "load")
2558 (set_attr "length" "4")])
2560 (define_expand "post_store"
2561 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2562 (match_operand 1 "reg_or_0_operand" ""))
2565 (match_operand 2 "post_cint_operand" "")))])]
2571 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2574 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2578 (define_insn "post_stw"
2579 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2580 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2582 (plus:SI (match_dup 0)
2583 (match_operand:SI 2 "post_cint_operand" "")))]
2587 if (INTVAL (operands[2]) > 0)
2588 return \"{stwm|stw,ma} %r1,%2(%0)\";
2589 return \"{stws|stw},ma %r1,%2(%0)\";
2591 [(set_attr "type" "store")
2592 (set_attr "length" "4")])
2594 (define_insn "post_std"
2595 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2596 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2598 (plus:DI (match_dup 0)
2599 (match_operand:DI 2 "post_cint_operand" "")))]
2602 [(set_attr "type" "store")
2603 (set_attr "length" "4")])
2605 ;; For loading the address of a label while generating PIC code.
2606 ;; Note since this pattern can be created at reload time (via movsi), all
2607 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2609 [(set (match_operand 0 "pmode_register_operand" "=a")
2610 (match_operand 1 "pic_label_operand" ""))]
2616 xoperands[0] = operands[0];
2617 xoperands[1] = operands[1];
2618 xoperands[2] = gen_label_rtx ();
2620 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2621 CODE_LABEL_NUMBER (xoperands[2]));
2622 output_asm_insn (\"mfia %0\", xoperands);
2624 /* If we're trying to load the address of a label that happens to be
2625 close, then we can use a shorter sequence. */
2626 if (GET_CODE (operands[1]) == LABEL_REF
2627 && INSN_ADDRESSES_SET_P ()
2628 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2629 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2630 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2633 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2634 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2638 [(set_attr "type" "multi")
2639 (set_attr "length" "12")]) ; 8 or 12
2642 [(set (match_operand 0 "pmode_register_operand" "=a")
2643 (match_operand 1 "pic_label_operand" ""))]
2649 xoperands[0] = operands[0];
2650 xoperands[1] = operands[1];
2651 xoperands[2] = gen_label_rtx ();
2653 output_asm_insn (\"bl .+8,%0\", xoperands);
2654 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2655 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2656 CODE_LABEL_NUMBER (xoperands[2]));
2658 /* If we're trying to load the address of a label that happens to be
2659 close, then we can use a shorter sequence. */
2660 if (GET_CODE (operands[1]) == LABEL_REF
2661 && INSN_ADDRESSES_SET_P ()
2662 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2663 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2664 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2667 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2668 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2672 [(set_attr "type" "multi")
2673 (set_attr "length" "16")]) ; 12 or 16
2676 [(set (match_operand:SI 0 "register_operand" "=a")
2677 (plus:SI (match_operand:SI 1 "register_operand" "r")
2678 (high:SI (match_operand 2 "" ""))))]
2679 "symbolic_operand (operands[2], Pmode)
2680 && ! function_label_operand (operands[2], Pmode)
2683 [(set_attr "type" "binary")
2684 (set_attr "length" "4")])
2687 [(set (match_operand:DI 0 "register_operand" "=a")
2688 (plus:DI (match_operand:DI 1 "register_operand" "r")
2689 (high:DI (match_operand 2 "" ""))))]
2690 "symbolic_operand (operands[2], Pmode)
2691 && ! function_label_operand (operands[2], Pmode)
2695 [(set_attr "type" "binary")
2696 (set_attr "length" "4")])
2698 ;; Always use addil rather than ldil;add sequences. This allows the
2699 ;; HP linker to eliminate the dp relocation if the symbolic operand
2700 ;; lives in the TEXT space.
2702 [(set (match_operand:SI 0 "register_operand" "=a")
2703 (high:SI (match_operand 1 "" "")))]
2704 "symbolic_operand (operands[1], Pmode)
2705 && ! function_label_operand (operands[1], Pmode)
2706 && ! read_only_operand (operands[1], Pmode)
2710 if (TARGET_LONG_LOAD_STORE)
2711 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2713 return \"addil LR'%H1,%%r27\";
2715 [(set_attr "type" "binary")
2716 (set (attr "length")
2717 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2722 ;; This is for use in the prologue/epilogue code. We need it
2723 ;; to add large constants to a stack pointer or frame pointer.
2724 ;; Because of the additional %r1 pressure, we probably do not
2725 ;; want to use this in general code, so make it available
2726 ;; only after reload.
2728 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2729 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2730 (high:SI (match_operand 2 "const_int_operand" ""))))]
2734 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2735 [(set_attr "type" "binary,binary")
2736 (set_attr "length" "4,8")])
2739 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2740 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2741 (high:DI (match_operand 2 "const_int_operand" ""))))]
2742 "reload_completed && TARGET_64BIT"
2745 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2746 [(set_attr "type" "binary,binary")
2747 (set_attr "length" "4,8")])
2750 [(set (match_operand:SI 0 "register_operand" "=r")
2751 (high:SI (match_operand 1 "" "")))]
2752 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2753 && !is_function_label_plus_const (operands[1])"
2756 if (symbolic_operand (operands[1], Pmode))
2757 return \"ldil LR'%H1,%0\";
2759 return \"ldil L'%G1,%0\";
2761 [(set_attr "type" "move")
2762 (set_attr "length" "4")])
2765 [(set (match_operand:DI 0 "register_operand" "=r")
2766 (high:DI (match_operand 1 "const_int_operand" "")))]
2769 [(set_attr "type" "move")
2770 (set_attr "length" "4")])
2773 [(set (match_operand:DI 0 "register_operand" "=r")
2774 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2775 (match_operand:DI 2 "const_int_operand" "i")))]
2778 [(set_attr "type" "move")
2779 (set_attr "length" "4")])
2782 [(set (match_operand:SI 0 "register_operand" "=r")
2783 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2784 (match_operand:SI 2 "immediate_operand" "i")))]
2785 "!is_function_label_plus_const (operands[2])"
2788 if (flag_pic && symbolic_operand (operands[2], Pmode))
2790 else if (symbolic_operand (operands[2], Pmode))
2791 return \"ldo RR'%G2(%1),%0\";
2793 return \"ldo R'%G2(%1),%0\";
2795 [(set_attr "type" "move")
2796 (set_attr "length" "4")])
2798 ;; Now that a symbolic_address plus a constant is broken up early
2799 ;; in the compilation phase (for better CSE) we need a special
2800 ;; combiner pattern to load the symbolic address plus the constant
2801 ;; in only 2 instructions. (For cases where the symbolic address
2802 ;; was not a common subexpression.)
2804 [(set (match_operand:SI 0 "register_operand" "")
2805 (match_operand:SI 1 "symbolic_operand" ""))
2806 (clobber (match_operand:SI 2 "register_operand" ""))]
2807 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2808 [(set (match_dup 2) (high:SI (match_dup 1)))
2809 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2812 ;; hppa_legitimize_address goes to a great deal of trouble to
2813 ;; create addresses which use indexing. In some cases, this
2814 ;; is a lose because there isn't any store instructions which
2815 ;; allow indexed addresses (with integer register source).
2817 ;; These define_splits try to turn a 3 insn store into
2818 ;; a 2 insn store with some creative RTL rewriting.
2820 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2821 (match_operand:SI 1 "shadd_operand" ""))
2822 (plus:SI (match_operand:SI 2 "register_operand" "")
2823 (match_operand:SI 3 "const_int_operand" ""))))
2824 (match_operand:SI 4 "register_operand" ""))
2825 (clobber (match_operand:SI 5 "register_operand" ""))]
2827 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2829 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2833 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2834 (match_operand:SI 1 "shadd_operand" ""))
2835 (plus:SI (match_operand:SI 2 "register_operand" "")
2836 (match_operand:SI 3 "const_int_operand" ""))))
2837 (match_operand:HI 4 "register_operand" ""))
2838 (clobber (match_operand:SI 5 "register_operand" ""))]
2840 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2842 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2846 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2847 (match_operand:SI 1 "shadd_operand" ""))
2848 (plus:SI (match_operand:SI 2 "register_operand" "")
2849 (match_operand:SI 3 "const_int_operand" ""))))
2850 (match_operand:QI 4 "register_operand" ""))
2851 (clobber (match_operand:SI 5 "register_operand" ""))]
2853 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2855 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2858 (define_expand "movhi"
2859 [(set (match_operand:HI 0 "general_operand" "")
2860 (match_operand:HI 1 "general_operand" ""))]
2864 if (emit_move_sequence (operands, HImode, 0))
2869 [(set (match_operand:HI 0 "move_dest_operand"
2870 "=r,r,r,r,r,Q,!*q,!r,!*f")
2871 (match_operand:HI 1 "move_src_operand"
2872 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
2873 "register_operand (operands[0], HImode)
2874 || reg_or_0_operand (operands[1], HImode)"
2879 {zdepi|depwi,z} %Z1,%0
2883 {mfctl|mfctl,w} %sar,%0
2885 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
2886 (set_attr "pa_combine_type" "addmove")
2887 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2890 [(set (match_operand:HI 0 "register_operand" "=r")
2891 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2892 (match_operand:SI 2 "int5_operand" "L"))))
2894 (plus:SI (match_dup 1) (match_dup 2)))]
2896 "{ldhs|ldh},mb %2(%1),%0"
2897 [(set_attr "type" "load")
2898 (set_attr "length" "4")])
2901 [(set (match_operand:HI 0 "register_operand" "=r")
2902 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2903 (match_operand:DI 2 "int5_operand" "L"))))
2905 (plus:DI (match_dup 1) (match_dup 2)))]
2908 [(set_attr "type" "load")
2909 (set_attr "length" "4")])
2911 ; And a zero extended variant.
2913 [(set (match_operand:DI 0 "register_operand" "=r")
2914 (zero_extend:DI (mem:HI
2916 (match_operand:DI 1 "register_operand" "+r")
2917 (match_operand:DI 2 "int5_operand" "L")))))
2919 (plus:DI (match_dup 1) (match_dup 2)))]
2922 [(set_attr "type" "load")
2923 (set_attr "length" "4")])
2926 [(set (match_operand:SI 0 "register_operand" "=r")
2927 (zero_extend:SI (mem:HI
2929 (match_operand:SI 1 "register_operand" "+r")
2930 (match_operand:SI 2 "int5_operand" "L")))))
2932 (plus:SI (match_dup 1) (match_dup 2)))]
2934 "{ldhs|ldh},mb %2(%1),%0"
2935 [(set_attr "type" "load")
2936 (set_attr "length" "4")])
2939 [(set (match_operand:SI 0 "register_operand" "=r")
2940 (zero_extend:SI (mem:HI
2942 (match_operand:DI 1 "register_operand" "+r")
2943 (match_operand:DI 2 "int5_operand" "L")))))
2945 (plus:DI (match_dup 1) (match_dup 2)))]
2948 [(set_attr "type" "load")
2949 (set_attr "length" "4")])
2952 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2953 (match_operand:SI 1 "int5_operand" "L")))
2954 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2956 (plus:SI (match_dup 0) (match_dup 1)))]
2958 "{sths|sth},mb %r2,%1(%0)"
2959 [(set_attr "type" "store")
2960 (set_attr "length" "4")])
2963 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2964 (match_operand:DI 1 "int5_operand" "L")))
2965 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2967 (plus:DI (match_dup 0) (match_dup 1)))]
2970 [(set_attr "type" "store")
2971 (set_attr "length" "4")])
2974 [(set (match_operand:HI 0 "register_operand" "=r")
2975 (plus:HI (match_operand:HI 1 "register_operand" "r")
2976 (match_operand 2 "const_int_operand" "J")))]
2979 [(set_attr "type" "binary")
2980 (set_attr "pa_combine_type" "addmove")
2981 (set_attr "length" "4")])
2983 (define_expand "movqi"
2984 [(set (match_operand:QI 0 "general_operand" "")
2985 (match_operand:QI 1 "general_operand" ""))]
2989 if (emit_move_sequence (operands, QImode, 0))
2994 [(set (match_operand:QI 0 "move_dest_operand"
2995 "=r,r,r,r,r,Q,!*q,!r,!*f")
2996 (match_operand:QI 1 "move_src_operand"
2997 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
2998 "register_operand (operands[0], QImode)
2999 || reg_or_0_operand (operands[1], QImode)"
3004 {zdepi|depwi,z} %Z1,%0
3008 {mfctl|mfctl,w} %%sar,%0
3010 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
3011 (set_attr "pa_combine_type" "addmove")
3012 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3015 [(set (match_operand:QI 0 "register_operand" "=r")
3016 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3017 (match_operand:SI 2 "int5_operand" "L"))))
3018 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3020 "{ldbs|ldb},mb %2(%1),%0"
3021 [(set_attr "type" "load")
3022 (set_attr "length" "4")])
3025 [(set (match_operand:QI 0 "register_operand" "=r")
3026 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3027 (match_operand:DI 2 "int5_operand" "L"))))
3028 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3031 [(set_attr "type" "load")
3032 (set_attr "length" "4")])
3034 ; Now the same thing with zero extensions.
3036 [(set (match_operand:DI 0 "register_operand" "=r")
3037 (zero_extend:DI (mem:QI (plus:DI
3038 (match_operand:DI 1 "register_operand" "+r")
3039 (match_operand:DI 2 "int5_operand" "L")))))
3040 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3043 [(set_attr "type" "load")
3044 (set_attr "length" "4")])
3047 [(set (match_operand:SI 0 "register_operand" "=r")
3048 (zero_extend:SI (mem:QI (plus:SI
3049 (match_operand:SI 1 "register_operand" "+r")
3050 (match_operand:SI 2 "int5_operand" "L")))))
3051 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3053 "{ldbs|ldb},mb %2(%1),%0"
3054 [(set_attr "type" "load")
3055 (set_attr "length" "4")])
3058 [(set (match_operand:SI 0 "register_operand" "=r")
3059 (zero_extend:SI (mem:QI (plus:DI
3060 (match_operand:DI 1 "register_operand" "+r")
3061 (match_operand:DI 2 "int5_operand" "L")))))
3062 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3065 [(set_attr "type" "load")
3066 (set_attr "length" "4")])
3069 [(set (match_operand:HI 0 "register_operand" "=r")
3070 (zero_extend:HI (mem:QI (plus:SI
3071 (match_operand:SI 1 "register_operand" "+r")
3072 (match_operand:SI 2 "int5_operand" "L")))))
3073 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3075 "{ldbs|ldb},mb %2(%1),%0"
3076 [(set_attr "type" "load")
3077 (set_attr "length" "4")])
3080 [(set (match_operand:HI 0 "register_operand" "=r")
3081 (zero_extend:HI (mem:QI (plus:DI
3082 (match_operand:DI 1 "register_operand" "+r")
3083 (match_operand:DI 2 "int5_operand" "L")))))
3084 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3087 [(set_attr "type" "load")
3088 (set_attr "length" "4")])
3091 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3092 (match_operand:SI 1 "int5_operand" "L")))
3093 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3095 (plus:SI (match_dup 0) (match_dup 1)))]
3097 "{stbs|stb},mb %r2,%1(%0)"
3098 [(set_attr "type" "store")
3099 (set_attr "length" "4")])
3102 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3103 (match_operand:DI 1 "int5_operand" "L")))
3104 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3106 (plus:DI (match_dup 0) (match_dup 1)))]
3109 [(set_attr "type" "store")
3110 (set_attr "length" "4")])
3112 ;; The definition of this insn does not really explain what it does,
3113 ;; but it should suffice that anything generated as this insn will be
3114 ;; recognized as a movstrsi operation, and that it will not successfully
3115 ;; combine with anything.
3116 (define_expand "movstrsi"
3117 [(parallel [(set (match_operand:BLK 0 "" "")
3118 (match_operand:BLK 1 "" ""))
3119 (clobber (match_dup 4))
3120 (clobber (match_dup 5))
3121 (clobber (match_dup 6))
3122 (clobber (match_dup 7))
3123 (clobber (match_dup 8))
3124 (use (match_operand:SI 2 "arith_operand" ""))
3125 (use (match_operand:SI 3 "const_int_operand" ""))])]
3126 "!TARGET_64BIT && optimize > 0"
3131 /* HP provides very fast block move library routine for the PA;
3132 this routine includes:
3134 4x4 byte at a time block moves,
3135 1x4 byte at a time with alignment checked at runtime with
3136 attempts to align the source and destination as needed
3139 With that in mind, here's the heuristics to try and guess when
3140 the inlined block move will be better than the library block
3143 If the size isn't constant, then always use the library routines.
3145 If the size is large in respect to the known alignment, then use
3146 the library routines.
3148 If the size is small in respect to the known alignment, then open
3149 code the copy (since that will lead to better scheduling).
3151 Else use the block move pattern. */
3153 /* Undetermined size, use the library routine. */
3154 if (GET_CODE (operands[2]) != CONST_INT)
3157 size = INTVAL (operands[2]);
3158 align = INTVAL (operands[3]);
3159 align = align > 4 ? 4 : align;
3161 /* If size/alignment is large, then use the library routines. */
3162 if (size / align > 16)
3165 /* This does happen, but not often enough to worry much about. */
3166 if (size / align < MOVE_RATIO)
3169 /* Fall through means we're going to use our block move pattern. */
3171 = replace_equiv_address (operands[0],
3172 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3174 = replace_equiv_address (operands[1],
3175 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3176 operands[4] = gen_reg_rtx (SImode);
3177 operands[5] = gen_reg_rtx (SImode);
3178 operands[6] = gen_reg_rtx (SImode);
3179 operands[7] = gen_reg_rtx (SImode);
3180 operands[8] = gen_reg_rtx (SImode);
3183 ;; The operand constraints are written like this to support both compile-time
3184 ;; and run-time determined byte counts. The expander and output_block_move
3185 ;; only support compile-time determined counts at this time.
3187 ;; If the count is run-time determined, the register with the byte count
3188 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3190 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3191 ;; broke this semantic for pseudo registers. We can't use match_scratch
3192 ;; as this requires two registers in the class R1_REGS when the MEMs for
3193 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3194 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3195 ;; respectively. We then split or peephole optimize after reload.
3196 (define_insn "movstrsi_prereload"
3197 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3198 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3199 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3200 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3201 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3202 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3203 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3204 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3205 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3208 [(set_attr "type" "multi,multi")])
3211 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3212 (match_operand:BLK 1 "memory_operand" ""))
3213 (clobber (match_operand:SI 2 "register_operand" ""))
3214 (clobber (match_operand:SI 3 "register_operand" ""))
3215 (clobber (match_operand:SI 6 "register_operand" ""))
3216 (clobber (match_operand:SI 7 "register_operand" ""))
3217 (clobber (match_operand:SI 8 "register_operand" ""))
3218 (use (match_operand:SI 4 "arith_operand" ""))
3219 (use (match_operand:SI 5 "const_int_operand" ""))])]
3220 "!TARGET_64BIT && reload_completed && !flag_peephole2
3221 && GET_CODE (operands[0]) == MEM
3222 && register_operand (XEXP (operands[0], 0), SImode)
3223 && GET_CODE (operands[1]) == MEM
3224 && register_operand (XEXP (operands[1], 0), SImode)"
3225 [(set (match_dup 7) (match_dup 9))
3226 (set (match_dup 8) (match_dup 10))
3227 (parallel [(set (match_dup 0) (match_dup 1))
3228 (clobber (match_dup 2))
3229 (clobber (match_dup 3))
3230 (clobber (match_dup 6))
3231 (clobber (match_dup 7))
3232 (clobber (match_dup 8))
3238 operands[9] = XEXP (operands[0], 0);
3239 operands[10] = XEXP (operands[1], 0);
3240 operands[0] = replace_equiv_address (operands[0], operands[7]);
3241 operands[1] = replace_equiv_address (operands[1], operands[8]);
3245 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3246 (match_operand:BLK 1 "memory_operand" ""))
3247 (clobber (match_operand:SI 2 "register_operand" ""))
3248 (clobber (match_operand:SI 3 "register_operand" ""))
3249 (clobber (match_operand:SI 6 "register_operand" ""))
3250 (clobber (match_operand:SI 7 "register_operand" ""))
3251 (clobber (match_operand:SI 8 "register_operand" ""))
3252 (use (match_operand:SI 4 "arith_operand" ""))
3253 (use (match_operand:SI 5 "const_int_operand" ""))])]
3255 && GET_CODE (operands[0]) == MEM
3256 && register_operand (XEXP (operands[0], 0), SImode)
3257 && GET_CODE (operands[1]) == MEM
3258 && register_operand (XEXP (operands[1], 0), SImode)"
3259 [(parallel [(set (match_dup 0) (match_dup 1))
3260 (clobber (match_dup 2))
3261 (clobber (match_dup 3))
3262 (clobber (match_dup 6))
3263 (clobber (match_dup 7))
3264 (clobber (match_dup 8))
3270 rtx addr = XEXP (operands[0], 0);
3271 if (dead_or_set_p (curr_insn, addr))
3275 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3276 operands[0] = replace_equiv_address (operands[0], operands[7]);
3279 addr = XEXP (operands[1], 0);
3280 if (dead_or_set_p (curr_insn, addr))
3284 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3285 operands[1] = replace_equiv_address (operands[1], operands[8]);
3289 (define_insn "movstrsi_postreload"
3290 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3291 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3292 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3293 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3294 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3295 (clobber (match_dup 0))
3296 (clobber (match_dup 1))
3297 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3298 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3300 "!TARGET_64BIT && reload_completed"
3301 "* return output_block_move (operands, !which_alternative);"
3302 [(set_attr "type" "multi,multi")])
3304 (define_expand "movstrdi"
3305 [(parallel [(set (match_operand:BLK 0 "" "")
3306 (match_operand:BLK 1 "" ""))
3307 (clobber (match_dup 4))
3308 (clobber (match_dup 5))
3309 (clobber (match_dup 6))
3310 (clobber (match_dup 7))
3311 (clobber (match_dup 8))
3312 (use (match_operand:DI 2 "arith_operand" ""))
3313 (use (match_operand:DI 3 "const_int_operand" ""))])]
3314 "TARGET_64BIT && optimize > 0"
3319 /* HP provides very fast block move library routine for the PA;
3320 this routine includes:
3322 4x4 byte at a time block moves,
3323 1x4 byte at a time with alignment checked at runtime with
3324 attempts to align the source and destination as needed
3327 With that in mind, here's the heuristics to try and guess when
3328 the inlined block move will be better than the library block
3331 If the size isn't constant, then always use the library routines.
3333 If the size is large in respect to the known alignment, then use
3334 the library routines.
3336 If the size is small in respect to the known alignment, then open
3337 code the copy (since that will lead to better scheduling).
3339 Else use the block move pattern. */
3341 /* Undetermined size, use the library routine. */
3342 if (GET_CODE (operands[2]) != CONST_INT)
3345 size = INTVAL (operands[2]);
3346 align = INTVAL (operands[3]);
3347 align = align > 8 ? 8 : align;
3349 /* If size/alignment is large, then use the library routines. */
3350 if (size / align > 16)
3353 /* This does happen, but not often enough to worry much about. */
3354 if (size / align < MOVE_RATIO)
3357 /* Fall through means we're going to use our block move pattern. */
3359 = replace_equiv_address (operands[0],
3360 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3362 = replace_equiv_address (operands[1],
3363 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3364 operands[4] = gen_reg_rtx (DImode);
3365 operands[5] = gen_reg_rtx (DImode);
3366 operands[6] = gen_reg_rtx (DImode);
3367 operands[7] = gen_reg_rtx (DImode);
3368 operands[8] = gen_reg_rtx (DImode);
3371 ;; The operand constraints are written like this to support both compile-time
3372 ;; and run-time determined byte counts. The expander and output_block_move
3373 ;; only support compile-time determined counts at this time.
3375 ;; If the count is run-time determined, the register with the byte count
3376 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3378 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3379 ;; broke this semantic for pseudo registers. We can't use match_scratch
3380 ;; as this requires two registers in the class R1_REGS when the MEMs for
3381 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3382 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3383 ;; respectively. We then split or peephole optimize after reload.
3384 (define_insn "movstrdi_prereload"
3385 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3386 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3387 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3388 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3389 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3390 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3391 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3392 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3393 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3396 [(set_attr "type" "multi,multi")])
3399 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3400 (match_operand:BLK 1 "memory_operand" ""))
3401 (clobber (match_operand:DI 2 "register_operand" ""))
3402 (clobber (match_operand:DI 3 "register_operand" ""))
3403 (clobber (match_operand:DI 6 "register_operand" ""))
3404 (clobber (match_operand:DI 7 "register_operand" ""))
3405 (clobber (match_operand:DI 8 "register_operand" ""))
3406 (use (match_operand:DI 4 "arith_operand" ""))
3407 (use (match_operand:DI 5 "const_int_operand" ""))])]
3408 "TARGET_64BIT && reload_completed && !flag_peephole2
3409 && GET_CODE (operands[0]) == MEM
3410 && register_operand (XEXP (operands[0], 0), DImode)
3411 && GET_CODE (operands[1]) == MEM
3412 && register_operand (XEXP (operands[1], 0), DImode)"
3413 [(set (match_dup 7) (match_dup 9))
3414 (set (match_dup 8) (match_dup 10))
3415 (parallel [(set (match_dup 0) (match_dup 1))
3416 (clobber (match_dup 2))
3417 (clobber (match_dup 3))
3418 (clobber (match_dup 6))
3419 (clobber (match_dup 7))
3420 (clobber (match_dup 8))
3426 operands[9] = XEXP (operands[0], 0);
3427 operands[10] = XEXP (operands[1], 0);
3428 operands[0] = replace_equiv_address (operands[0], operands[7]);
3429 operands[1] = replace_equiv_address (operands[1], operands[8]);
3433 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3434 (match_operand:BLK 1 "memory_operand" ""))
3435 (clobber (match_operand:DI 2 "register_operand" ""))
3436 (clobber (match_operand:DI 3 "register_operand" ""))
3437 (clobber (match_operand:DI 6 "register_operand" ""))
3438 (clobber (match_operand:DI 7 "register_operand" ""))
3439 (clobber (match_operand:DI 8 "register_operand" ""))
3440 (use (match_operand:DI 4 "arith_operand" ""))
3441 (use (match_operand:DI 5 "const_int_operand" ""))])]
3443 && GET_CODE (operands[0]) == MEM
3444 && register_operand (XEXP (operands[0], 0), DImode)
3445 && GET_CODE (operands[1]) == MEM
3446 && register_operand (XEXP (operands[1], 0), DImode)"
3447 [(parallel [(set (match_dup 0) (match_dup 1))
3448 (clobber (match_dup 2))
3449 (clobber (match_dup 3))
3450 (clobber (match_dup 6))
3451 (clobber (match_dup 7))
3452 (clobber (match_dup 8))
3458 rtx addr = XEXP (operands[0], 0);
3459 if (dead_or_set_p (curr_insn, addr))
3463 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3464 operands[0] = replace_equiv_address (operands[0], operands[7]);
3467 addr = XEXP (operands[1], 0);
3468 if (dead_or_set_p (curr_insn, addr))
3472 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3473 operands[1] = replace_equiv_address (operands[1], operands[8]);
3477 (define_insn "movstrdi_postreload"
3478 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3479 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3480 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3481 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3482 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3483 (clobber (match_dup 0))
3484 (clobber (match_dup 1))
3485 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3486 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3488 "TARGET_64BIT && reload_completed"
3489 "* return output_block_move (operands, !which_alternative);"
3490 [(set_attr "type" "multi,multi")])
3492 (define_expand "clrstrsi"
3493 [(parallel [(set (match_operand:BLK 0 "" "")
3495 (clobber (match_dup 3))
3496 (clobber (match_dup 4))
3497 (use (match_operand:SI 1 "arith_operand" ""))
3498 (use (match_operand:SI 2 "const_int_operand" ""))])]
3499 "!TARGET_64BIT && optimize > 0"
3504 /* Undetermined size, use the library routine. */
3505 if (GET_CODE (operands[1]) != CONST_INT)
3508 size = INTVAL (operands[1]);
3509 align = INTVAL (operands[2]);
3510 align = align > 4 ? 4 : align;
3512 /* If size/alignment is large, then use the library routines. */
3513 if (size / align > 16)
3516 /* This does happen, but not often enough to worry much about. */
3517 if (size / align < MOVE_RATIO)
3520 /* Fall through means we're going to use our block clear pattern. */
3522 = replace_equiv_address (operands[0],
3523 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3524 operands[3] = gen_reg_rtx (SImode);
3525 operands[4] = gen_reg_rtx (SImode);
3528 (define_insn "clrstrsi_prereload"
3529 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3531 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3532 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3533 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3534 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3537 [(set_attr "type" "multi,multi")])
3540 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3542 (clobber (match_operand:SI 1 "register_operand" ""))
3543 (clobber (match_operand:SI 4 "register_operand" ""))
3544 (use (match_operand:SI 2 "arith_operand" ""))
3545 (use (match_operand:SI 3 "const_int_operand" ""))])]
3546 "!TARGET_64BIT && reload_completed && !flag_peephole2
3547 && GET_CODE (operands[0]) == MEM
3548 && register_operand (XEXP (operands[0], 0), SImode)"
3549 [(set (match_dup 4) (match_dup 5))
3550 (parallel [(set (match_dup 0) (const_int 0))
3551 (clobber (match_dup 1))
3552 (clobber (match_dup 4))
3558 operands[5] = XEXP (operands[0], 0);
3559 operands[0] = replace_equiv_address (operands[0], operands[4]);
3563 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3565 (clobber (match_operand:SI 1 "register_operand" ""))
3566 (clobber (match_operand:SI 4 "register_operand" ""))
3567 (use (match_operand:SI 2 "arith_operand" ""))
3568 (use (match_operand:SI 3 "const_int_operand" ""))])]
3570 && GET_CODE (operands[0]) == MEM
3571 && register_operand (XEXP (operands[0], 0), SImode)"
3572 [(parallel [(set (match_dup 0) (const_int 0))
3573 (clobber (match_dup 1))
3574 (clobber (match_dup 4))
3580 rtx addr = XEXP (operands[0], 0);
3581 if (dead_or_set_p (curr_insn, addr))
3585 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3586 operands[0] = replace_equiv_address (operands[0], operands[4]);
3590 (define_insn "clrstrsi_postreload"
3591 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3593 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3594 (clobber (match_dup 0))
3595 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3596 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3598 "!TARGET_64BIT && reload_completed"
3599 "* return output_block_clear (operands, !which_alternative);"
3600 [(set_attr "type" "multi,multi")])
3602 (define_expand "clrstrdi"
3603 [(parallel [(set (match_operand:BLK 0 "" "")
3605 (clobber (match_dup 3))
3606 (clobber (match_dup 4))
3607 (use (match_operand:DI 1 "arith_operand" ""))
3608 (use (match_operand:DI 2 "const_int_operand" ""))])]
3609 "TARGET_64BIT && optimize > 0"
3614 /* Undetermined size, use the library routine. */
3615 if (GET_CODE (operands[1]) != CONST_INT)
3618 size = INTVAL (operands[1]);
3619 align = INTVAL (operands[2]);
3620 align = align > 8 ? 8 : align;
3622 /* If size/alignment is large, then use the library routines. */
3623 if (size / align > 16)
3626 /* This does happen, but not often enough to worry much about. */
3627 if (size / align < MOVE_RATIO)
3630 /* Fall through means we're going to use our block clear pattern. */
3632 = replace_equiv_address (operands[0],
3633 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3634 operands[3] = gen_reg_rtx (DImode);
3635 operands[4] = gen_reg_rtx (DImode);
3638 (define_insn "clrstrdi_prereload"
3639 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3641 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3642 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3643 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3644 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3647 [(set_attr "type" "multi,multi")])
3650 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3652 (clobber (match_operand:DI 1 "register_operand" ""))
3653 (clobber (match_operand:DI 4 "register_operand" ""))
3654 (use (match_operand:DI 2 "arith_operand" ""))
3655 (use (match_operand:DI 3 "const_int_operand" ""))])]
3656 "TARGET_64BIT && reload_completed && !flag_peephole2
3657 && GET_CODE (operands[0]) == MEM
3658 && register_operand (XEXP (operands[0], 0), DImode)"
3659 [(set (match_dup 4) (match_dup 5))
3660 (parallel [(set (match_dup 0) (const_int 0))
3661 (clobber (match_dup 1))
3662 (clobber (match_dup 4))
3668 operands[5] = XEXP (operands[0], 0);
3669 operands[0] = replace_equiv_address (operands[0], operands[4]);
3673 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3675 (clobber (match_operand:DI 1 "register_operand" ""))
3676 (clobber (match_operand:DI 4 "register_operand" ""))
3677 (use (match_operand:DI 2 "arith_operand" ""))
3678 (use (match_operand:DI 3 "const_int_operand" ""))])]
3680 && GET_CODE (operands[0]) == MEM
3681 && register_operand (XEXP (operands[0], 0), DImode)"
3682 [(parallel [(set (match_dup 0) (const_int 0))
3683 (clobber (match_dup 1))
3684 (clobber (match_dup 4))
3690 rtx addr = XEXP (operands[0], 0);
3691 if (dead_or_set_p (curr_insn, addr))
3695 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3696 operands[0] = replace_equiv_address (operands[0], operands[4]);
3700 (define_insn "clrstrdi_postreload"
3701 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3703 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3704 (clobber (match_dup 0))
3705 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3706 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3708 "TARGET_64BIT && reload_completed"
3709 "* return output_block_clear (operands, !which_alternative);"
3710 [(set_attr "type" "multi,multi")])
3712 ;; Floating point move insns
3714 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3715 ;; to be reloaded by putting the constant into memory when
3716 ;; reg is a floating point register.
3718 ;; For integer registers we use ldil;ldo to set the appropriate
3721 ;; This must come before the movdf pattern, and it must be present
3722 ;; to handle obscure reloading cases.
3724 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3725 (match_operand:DF 1 "" "?F,m"))]
3726 "GET_CODE (operands[1]) == CONST_DOUBLE
3727 && operands[1] != CONST0_RTX (DFmode)
3729 && !TARGET_SOFT_FLOAT"
3730 "* return (which_alternative == 0 ? output_move_double (operands)
3731 : \"fldd%F1 %1,%0\");"
3732 [(set_attr "type" "move,fpload")
3733 (set_attr "length" "16,4")])
3735 (define_expand "movdf"
3736 [(set (match_operand:DF 0 "general_operand" "")
3737 (match_operand:DF 1 "general_operand" ""))]
3741 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3742 operands[1] = force_const_mem (DFmode, operands[1]);
3744 if (emit_move_sequence (operands, DFmode, 0))
3748 ;; Reloading an SImode or DImode value requires a scratch register if
3749 ;; going in to or out of float point registers.
3751 (define_expand "reload_indf"
3752 [(set (match_operand:DF 0 "register_operand" "=Z")
3753 (match_operand:DF 1 "non_hard_reg_operand" ""))
3754 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3758 if (emit_move_sequence (operands, DFmode, operands[2]))
3761 /* We don't want the clobber emitted, so handle this ourselves. */
3762 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3766 (define_expand "reload_outdf"
3767 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3768 (match_operand:DF 1 "register_operand" "Z"))
3769 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3773 if (emit_move_sequence (operands, DFmode, operands[2]))
3776 /* We don't want the clobber emitted, so handle this ourselves. */
3777 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3782 [(set (match_operand:DF 0 "move_dest_operand"
3783 "=f,*r,Q,?o,?Q,f,*r,*r")
3784 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3785 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3786 "(register_operand (operands[0], DFmode)
3787 || reg_or_0_operand (operands[1], DFmode))
3788 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3789 && GET_CODE (operands[0]) == MEM)
3791 && !TARGET_SOFT_FLOAT"
3794 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3795 || operands[1] == CONST0_RTX (DFmode))
3796 return output_fp_move_double (operands);
3797 return output_move_double (operands);
3799 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3800 (set_attr "length" "4,8,4,8,16,4,8,16")])
3803 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3804 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3806 && !TARGET_DISABLE_INDEXING
3807 && reload_completed"
3809 [(set_attr "type" "fpstore")
3810 (set_attr "pa_combine_type" "addmove")
3811 (set_attr "length" "4")])
3814 [(set (match_operand:SI 0 "register_operand" "")
3815 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3817 (match_operand:SI 2 "register_operand" "")))
3818 (set (mem:DF (match_dup 0))
3819 (match_operand:DF 3 "register_operand" ""))]
3821 && REG_OK_FOR_BASE_P (operands[2])
3822 && FP_REGNO_P (REGNO (operands[3]))"
3823 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3825 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3830 [(set (match_operand:SI 0 "register_operand" "")
3831 (plus:SI (match_operand:SI 2 "register_operand" "")
3832 (mult:SI (match_operand:SI 1 "register_operand" "")
3834 (set (mem:DF (match_dup 0))
3835 (match_operand:DF 3 "register_operand" ""))]
3837 && REG_OK_FOR_BASE_P (operands[2])
3838 && FP_REGNO_P (REGNO (operands[3]))"
3839 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3841 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3846 [(set (match_operand:DI 0 "register_operand" "")
3847 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3849 (match_operand:DI 2 "register_operand" "")))
3850 (set (mem:DF (match_dup 0))
3851 (match_operand:DF 3 "register_operand" ""))]
3854 && REG_OK_FOR_BASE_P (operands[2])
3855 && FP_REGNO_P (REGNO (operands[3]))"
3856 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3858 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3863 [(set (match_operand:DI 0 "register_operand" "")
3864 (plus:DI (match_operand:DI 2 "register_operand" "")
3865 (mult:DI (match_operand:DI 1 "register_operand" "")
3867 (set (mem:DF (match_dup 0))
3868 (match_operand:DF 3 "register_operand" ""))]
3871 && REG_OK_FOR_BASE_P (operands[2])
3872 && FP_REGNO_P (REGNO (operands[3]))"
3873 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3875 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3880 [(set (match_operand:SI 0 "register_operand" "")
3881 (plus:SI (match_operand:SI 1 "register_operand" "")
3882 (match_operand:SI 2 "register_operand" "")))
3883 (set (mem:DF (match_dup 0))
3884 (match_operand:DF 3 "register_operand" ""))]
3886 && REG_OK_FOR_BASE_P (operands[1])
3887 && (TARGET_NO_SPACE_REGS
3888 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3889 && FP_REGNO_P (REGNO (operands[3]))"
3890 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3892 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3896 [(set (match_operand:SI 0 "register_operand" "")
3897 (plus:SI (match_operand:SI 1 "register_operand" "")
3898 (match_operand:SI 2 "register_operand" "")))
3899 (set (mem:DF (match_dup 0))
3900 (match_operand:DF 3 "register_operand" ""))]
3902 && REG_OK_FOR_BASE_P (operands[2])
3903 && (TARGET_NO_SPACE_REGS
3904 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3905 && FP_REGNO_P (REGNO (operands[3]))"
3906 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3908 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3912 [(set (match_operand:DI 0 "register_operand" "")
3913 (plus:DI (match_operand:DI 1 "register_operand" "")
3914 (match_operand:DI 2 "register_operand" "")))
3915 (set (mem:DF (match_dup 0))
3916 (match_operand:DF 3 "register_operand" ""))]
3919 && REG_OK_FOR_BASE_P (operands[1])
3920 && (TARGET_NO_SPACE_REGS
3921 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3922 && FP_REGNO_P (REGNO (operands[3]))"
3923 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3925 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3929 [(set (match_operand:DI 0 "register_operand" "")
3930 (plus:DI (match_operand:DI 1 "register_operand" "")
3931 (match_operand:DI 2 "register_operand" "")))
3932 (set (mem:DF (match_dup 0))
3933 (match_operand:DF 3 "register_operand" ""))]
3936 && REG_OK_FOR_BASE_P (operands[2])
3937 && (TARGET_NO_SPACE_REGS
3938 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3939 && FP_REGNO_P (REGNO (operands[3]))"
3940 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3942 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3946 [(set (match_operand:DF 0 "move_dest_operand"
3948 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3950 "(register_operand (operands[0], DFmode)
3951 || reg_or_0_operand (operands[1], DFmode))
3953 && TARGET_SOFT_FLOAT"
3956 return output_move_double (operands);
3958 [(set_attr "type" "move,store,store,load,load")
3959 (set_attr "length" "8,8,16,8,16")])
3962 [(set (match_operand:DF 0 "move_dest_operand"
3963 "=!*r,*r,*r,*r,*r,Q,f,f,T")
3964 (match_operand:DF 1 "move_src_operand"
3965 "!*r,J,N,K,RQ,*rM,fM,RT,f"))]
3966 "(register_operand (operands[0], DFmode)
3967 || reg_or_0_operand (operands[1], DFmode))
3968 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3979 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
3980 (set_attr "pa_combine_type" "addmove")
3981 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3984 (define_expand "movdi"
3985 [(set (match_operand:DI 0 "general_operand" "")
3986 (match_operand:DI 1 "general_operand" ""))]
3990 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3991 operands[1] = force_const_mem (DImode, operands[1]);
3993 if (emit_move_sequence (operands, DImode, 0))
3997 (define_expand "reload_indi"
3998 [(set (match_operand:DI 0 "register_operand" "=Z")
3999 (match_operand:DI 1 "non_hard_reg_operand" ""))
4000 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4004 if (emit_move_sequence (operands, DImode, operands[2]))
4007 /* We don't want the clobber emitted, so handle this ourselves. */
4008 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4012 (define_expand "reload_outdi"
4013 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4014 (match_operand:DI 1 "register_operand" "Z"))
4015 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4019 if (emit_move_sequence (operands, DImode, operands[2]))
4022 /* We don't want the clobber emitted, so handle this ourselves. */
4023 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4028 [(set (match_operand:DI 0 "register_operand" "=r")
4029 (high:DI (match_operand 1 "" "")))]
4033 rtx op0 = operands[0];
4034 rtx op1 = operands[1];
4036 if (GET_CODE (op1) == CONST_INT)
4038 operands[0] = operand_subword (op0, 1, 0, DImode);
4039 output_asm_insn (\"ldil L'%1,%0\", operands);
4041 operands[0] = operand_subword (op0, 0, 0, DImode);
4042 if (INTVAL (op1) < 0)
4043 output_asm_insn (\"ldi -1,%0\", operands);
4045 output_asm_insn (\"ldi 0,%0\", operands);
4048 else if (GET_CODE (op1) == CONST_DOUBLE)
4050 operands[0] = operand_subword (op0, 1, 0, DImode);
4051 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4052 output_asm_insn (\"ldil L'%1,%0\", operands);
4054 operands[0] = operand_subword (op0, 0, 0, DImode);
4055 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4056 output_asm_insn (singlemove_string (operands), operands);
4062 [(set_attr "type" "move")
4063 (set_attr "length" "8")])
4066 [(set (match_operand:DI 0 "move_dest_operand"
4067 "=r,o,Q,r,r,r,*f,*f,T")
4068 (match_operand:DI 1 "general_operand"
4069 "rM,r,r,o*R,Q,i,*fM,RT,*f"))]
4070 "(register_operand (operands[0], DImode)
4071 || reg_or_0_operand (operands[1], DImode))
4073 && !TARGET_SOFT_FLOAT"
4076 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4077 || (operands[1] == CONST0_RTX (DImode)))
4078 return output_fp_move_double (operands);
4079 return output_move_double (operands);
4081 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
4082 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
4085 [(set (match_operand:DI 0 "move_dest_operand"
4086 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4087 (match_operand:DI 1 "move_src_operand"
4088 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4089 "(register_operand (operands[0], DImode)
4090 || reg_or_0_operand (operands[1], DImode))
4091 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4101 {mfctl|mfctl,w} %%sar,%0
4105 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4106 (set_attr "pa_combine_type" "addmove")
4107 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4110 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4111 (match_operand:DI 1 "register_operand" "f"))]
4114 && !TARGET_DISABLE_INDEXING
4115 && reload_completed"
4117 [(set_attr "type" "fpstore")
4118 (set_attr "pa_combine_type" "addmove")
4119 (set_attr "length" "4")])
4122 [(set (match_operand:DI 0 "register_operand" "")
4123 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4125 (match_operand:DI 2 "register_operand" "")))
4126 (set (mem:DI (match_dup 0))
4127 (match_operand:DI 3 "register_operand" ""))]
4130 && REG_OK_FOR_BASE_P (operands[2])
4131 && FP_REGNO_P (REGNO (operands[3]))"
4132 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4134 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4139 [(set (match_operand:DI 0 "register_operand" "")
4140 (plus:DI (match_operand:DI 2 "register_operand" "")
4141 (mult:DI (match_operand:DI 1 "register_operand" "")
4143 (set (mem:DI (match_dup 0))
4144 (match_operand:DI 3 "register_operand" ""))]
4147 && REG_OK_FOR_BASE_P (operands[2])
4148 && FP_REGNO_P (REGNO (operands[3]))"
4149 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4151 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4156 [(set (match_operand:DI 0 "register_operand" "")
4157 (plus:DI (match_operand:DI 1 "register_operand" "")
4158 (match_operand:DI 2 "register_operand" "")))
4159 (set (mem:DI (match_dup 0))
4160 (match_operand:DI 3 "register_operand" ""))]
4163 && REG_OK_FOR_BASE_P (operands[1])
4164 && (TARGET_NO_SPACE_REGS
4165 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4166 && FP_REGNO_P (REGNO (operands[3]))"
4167 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4169 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4173 [(set (match_operand:DI 0 "register_operand" "")
4174 (plus:DI (match_operand:DI 1 "register_operand" "")
4175 (match_operand:DI 2 "register_operand" "")))
4176 (set (mem:DI (match_dup 0))
4177 (match_operand:DI 3 "register_operand" ""))]
4180 && REG_OK_FOR_BASE_P (operands[2])
4181 && (TARGET_NO_SPACE_REGS
4182 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4183 && FP_REGNO_P (REGNO (operands[3]))"
4184 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4186 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4190 [(set (match_operand:DI 0 "move_dest_operand"
4192 (match_operand:DI 1 "general_operand"
4194 "(register_operand (operands[0], DImode)
4195 || reg_or_0_operand (operands[1], DImode))
4197 && TARGET_SOFT_FLOAT"
4200 return output_move_double (operands);
4202 [(set_attr "type" "move,store,store,load,load,multi")
4203 (set_attr "length" "8,8,16,8,16,16")])
4206 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4207 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4208 (match_operand:DI 2 "immediate_operand" "i,i")))]
4212 /* Don't output a 64 bit constant, since we can't trust the assembler to
4213 handle it correctly. */
4214 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4215 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4216 if (which_alternative == 1)
4217 output_asm_insn (\"copy %1,%0\", operands);
4218 return \"ldo R'%G2(%R1),%R0\";
4220 [(set_attr "type" "move,move")
4221 (set_attr "length" "4,8")])
4223 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4224 ;; to be reloaded by putting the constant into memory when
4225 ;; reg is a floating point register.
4227 ;; For integer registers we use ldil;ldo to set the appropriate
4230 ;; This must come before the movsf pattern, and it must be present
4231 ;; to handle obscure reloading cases.
4233 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4234 (match_operand:SF 1 "" "?F,m"))]
4235 "GET_CODE (operands[1]) == CONST_DOUBLE
4236 && operands[1] != CONST0_RTX (SFmode)
4237 && ! TARGET_SOFT_FLOAT"
4238 "* return (which_alternative == 0 ? singlemove_string (operands)
4239 : \" fldw%F1 %1,%0\");"
4240 [(set_attr "type" "move,fpload")
4241 (set_attr "length" "8,4")])
4243 (define_expand "movsf"
4244 [(set (match_operand:SF 0 "general_operand" "")
4245 (match_operand:SF 1 "general_operand" ""))]
4249 if (emit_move_sequence (operands, SFmode, 0))
4253 ;; Reloading an SImode or DImode value requires a scratch register if
4254 ;; going in to or out of float point registers.
4256 (define_expand "reload_insf"
4257 [(set (match_operand:SF 0 "register_operand" "=Z")
4258 (match_operand:SF 1 "non_hard_reg_operand" ""))
4259 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4263 if (emit_move_sequence (operands, SFmode, operands[2]))
4266 /* We don't want the clobber emitted, so handle this ourselves. */
4267 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4271 (define_expand "reload_outsf"
4272 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4273 (match_operand:SF 1 "register_operand" "Z"))
4274 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4278 if (emit_move_sequence (operands, SFmode, operands[2]))
4281 /* We don't want the clobber emitted, so handle this ourselves. */
4282 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4287 [(set (match_operand:SF 0 "move_dest_operand"
4289 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4290 "fG,!*rG,RQ,RQ,f,*rG"))]
4291 "(register_operand (operands[0], SFmode)
4292 || reg_or_0_operand (operands[1], SFmode))
4293 && !TARGET_SOFT_FLOAT"
4301 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4302 (set_attr "pa_combine_type" "addmove")
4303 (set_attr "length" "4,4,4,4,4,4")])
4306 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4307 (match_operand:SF 1 "register_operand" "f"))]
4309 && !TARGET_DISABLE_INDEXING
4310 && reload_completed"
4312 [(set_attr "type" "fpstore")
4313 (set_attr "pa_combine_type" "addmove")
4314 (set_attr "length" "4")])
4317 [(set (match_operand:SI 0 "register_operand" "")
4318 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4320 (match_operand:SI 2 "register_operand" "")))
4321 (set (mem:SF (match_dup 0))
4322 (match_operand:SF 3 "register_operand" ""))]
4324 && REG_OK_FOR_BASE_P (operands[2])
4325 && FP_REGNO_P (REGNO (operands[3]))"
4326 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4328 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4333 [(set (match_operand:SI 0 "register_operand" "")
4334 (plus:SI (match_operand:SI 2 "register_operand" "")
4335 (mult:SI (match_operand:SI 1 "register_operand" "")
4337 (set (mem:SF (match_dup 0))
4338 (match_operand:SF 3 "register_operand" ""))]
4340 && REG_OK_FOR_BASE_P (operands[2])
4341 && FP_REGNO_P (REGNO (operands[3]))"
4342 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4344 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4349 [(set (match_operand:DI 0 "register_operand" "")
4350 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4352 (match_operand:DI 2 "register_operand" "")))
4353 (set (mem:SF (match_dup 0))
4354 (match_operand:SF 3 "register_operand" ""))]
4357 && REG_OK_FOR_BASE_P (operands[2])
4358 && FP_REGNO_P (REGNO (operands[3]))"
4359 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4361 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4366 [(set (match_operand:DI 0 "register_operand" "")
4367 (plus:DI (match_operand:DI 2 "register_operand" "")
4368 (mult:DI (match_operand:DI 1 "register_operand" "")
4370 (set (mem:SF (match_dup 0))
4371 (match_operand:SF 3 "register_operand" ""))]
4374 && REG_OK_FOR_BASE_P (operands[2])
4375 && FP_REGNO_P (REGNO (operands[3]))"
4376 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4378 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4383 [(set (match_operand:SI 0 "register_operand" "")
4384 (plus:SI (match_operand:SI 1 "register_operand" "")
4385 (match_operand:SI 2 "register_operand" "")))
4386 (set (mem:SF (match_dup 0))
4387 (match_operand:SF 3 "register_operand" ""))]
4389 && REG_OK_FOR_BASE_P (operands[1])
4390 && (TARGET_NO_SPACE_REGS
4391 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4392 && FP_REGNO_P (REGNO (operands[3]))"
4393 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4395 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4399 [(set (match_operand:SI 0 "register_operand" "")
4400 (plus:SI (match_operand:SI 1 "register_operand" "")
4401 (match_operand:SI 2 "register_operand" "")))
4402 (set (mem:SF (match_dup 0))
4403 (match_operand:SF 3 "register_operand" ""))]
4405 && REG_OK_FOR_BASE_P (operands[2])
4406 && (TARGET_NO_SPACE_REGS
4407 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4408 && FP_REGNO_P (REGNO (operands[3]))"
4409 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4411 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4415 [(set (match_operand:DI 0 "register_operand" "")
4416 (plus:DI (match_operand:DI 1 "register_operand" "")
4417 (match_operand:DI 2 "register_operand" "")))
4418 (set (mem:SF (match_dup 0))
4419 (match_operand:SF 3 "register_operand" ""))]
4422 && REG_OK_FOR_BASE_P (operands[1])
4423 && (TARGET_NO_SPACE_REGS
4424 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4425 && FP_REGNO_P (REGNO (operands[3]))"
4426 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4428 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4432 [(set (match_operand:DI 0 "register_operand" "")
4433 (plus:DI (match_operand:DI 1 "register_operand" "")
4434 (match_operand:DI 2 "register_operand" "")))
4435 (set (mem:SF (match_dup 0))
4436 (match_operand:SF 3 "register_operand" ""))]
4439 && REG_OK_FOR_BASE_P (operands[2])
4440 && (TARGET_NO_SPACE_REGS
4441 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4442 && FP_REGNO_P (REGNO (operands[3]))"
4443 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4445 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4449 [(set (match_operand:SF 0 "move_dest_operand"
4451 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4453 "(register_operand (operands[0], SFmode)
4454 || reg_or_0_operand (operands[1], SFmode))
4455 && TARGET_SOFT_FLOAT"
4460 [(set_attr "type" "move,load,store")
4461 (set_attr "pa_combine_type" "addmove")
4462 (set_attr "length" "4,4,4")])
4466 ;;- zero extension instructions
4467 ;; We have define_expand for zero extension patterns to make sure the
4468 ;; operands get loaded into registers. The define_insns accept
4469 ;; memory operands. This gives us better overall code than just
4470 ;; having a pattern that does or does not accept memory operands.
4472 (define_expand "zero_extendqihi2"
4473 [(set (match_operand:HI 0 "register_operand" "")
4475 (match_operand:QI 1 "register_operand" "")))]
4480 [(set (match_operand:HI 0 "register_operand" "=r,r")
4482 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4483 "GET_CODE (operands[1]) != CONST_INT"
4485 {extru|extrw,u} %1,31,8,%0
4487 [(set_attr "type" "shift,load")
4488 (set_attr "length" "4,4")])
4490 (define_expand "zero_extendqisi2"
4491 [(set (match_operand:SI 0 "register_operand" "")
4493 (match_operand:QI 1 "register_operand" "")))]
4498 [(set (match_operand:SI 0 "register_operand" "=r,r")
4500 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4501 "GET_CODE (operands[1]) != CONST_INT"
4503 {extru|extrw,u} %1,31,8,%0
4505 [(set_attr "type" "shift,load")
4506 (set_attr "length" "4,4")])
4508 (define_expand "zero_extendhisi2"
4509 [(set (match_operand:SI 0 "register_operand" "")
4511 (match_operand:HI 1 "register_operand" "")))]
4516 [(set (match_operand:SI 0 "register_operand" "=r,r")
4518 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4519 "GET_CODE (operands[1]) != CONST_INT"
4521 {extru|extrw,u} %1,31,16,%0
4523 [(set_attr "type" "shift,load")
4524 (set_attr "length" "4,4")])
4526 (define_expand "zero_extendqidi2"
4527 [(set (match_operand:DI 0 "register_operand" "")
4529 (match_operand:QI 1 "register_operand" "")))]
4534 [(set (match_operand:DI 0 "register_operand" "=r,r")
4536 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4537 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4541 [(set_attr "type" "shift,load")
4542 (set_attr "length" "4,4")])
4544 (define_expand "zero_extendhidi2"
4545 [(set (match_operand:DI 0 "register_operand" "")
4547 (match_operand:HI 1 "register_operand" "")))]
4552 [(set (match_operand:DI 0 "register_operand" "=r,r")
4554 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4555 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4559 [(set_attr "type" "shift,load")
4560 (set_attr "length" "4,4")])
4562 (define_expand "zero_extendsidi2"
4563 [(set (match_operand:DI 0 "register_operand" "")
4565 (match_operand:SI 1 "register_operand" "")))]
4570 [(set (match_operand:DI 0 "register_operand" "=r,r")
4572 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4573 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4577 [(set_attr "type" "shift,load")
4578 (set_attr "length" "4,4")])
4580 ;;- sign extension instructions
4582 (define_insn "extendhisi2"
4583 [(set (match_operand:SI 0 "register_operand" "=r")
4584 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4586 "{extrs|extrw,s} %1,31,16,%0"
4587 [(set_attr "type" "shift")
4588 (set_attr "length" "4")])
4590 (define_insn "extendqihi2"
4591 [(set (match_operand:HI 0 "register_operand" "=r")
4592 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4594 "{extrs|extrw,s} %1,31,8,%0"
4595 [(set_attr "type" "shift")
4596 (set_attr "length" "4")])
4598 (define_insn "extendqisi2"
4599 [(set (match_operand:SI 0 "register_operand" "=r")
4600 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4602 "{extrs|extrw,s} %1,31,8,%0"
4603 [(set_attr "type" "shift")
4604 (set_attr "length" "4")])
4606 (define_insn "extendqidi2"
4607 [(set (match_operand:DI 0 "register_operand" "=r")
4608 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4610 "extrd,s %1,63,8,%0"
4611 [(set_attr "type" "shift")
4612 (set_attr "length" "4")])
4614 (define_insn "extendhidi2"
4615 [(set (match_operand:DI 0 "register_operand" "=r")
4616 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4618 "extrd,s %1,63,16,%0"
4619 [(set_attr "type" "shift")
4620 (set_attr "length" "4")])
4622 (define_insn "extendsidi2"
4623 [(set (match_operand:DI 0 "register_operand" "=r")
4624 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4626 "extrd,s %1,63,32,%0"
4627 [(set_attr "type" "shift")
4628 (set_attr "length" "4")])
4631 ;; Conversions between float and double.
4633 (define_insn "extendsfdf2"
4634 [(set (match_operand:DF 0 "register_operand" "=f")
4636 (match_operand:SF 1 "register_operand" "f")))]
4637 "! TARGET_SOFT_FLOAT"
4638 "{fcnvff|fcnv},sgl,dbl %1,%0"
4639 [(set_attr "type" "fpalu")
4640 (set_attr "length" "4")])
4642 (define_insn "truncdfsf2"
4643 [(set (match_operand:SF 0 "register_operand" "=f")
4645 (match_operand:DF 1 "register_operand" "f")))]
4646 "! TARGET_SOFT_FLOAT"
4647 "{fcnvff|fcnv},dbl,sgl %1,%0"
4648 [(set_attr "type" "fpalu")
4649 (set_attr "length" "4")])
4651 ;; Conversion between fixed point and floating point.
4652 ;; Note that among the fix-to-float insns
4653 ;; the ones that start with SImode come first.
4654 ;; That is so that an operand that is a CONST_INT
4655 ;; (and therefore lacks a specific machine mode).
4656 ;; will be recognized as SImode (which is always valid)
4657 ;; rather than as QImode or HImode.
4659 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4660 ;; to be reloaded by putting the constant into memory.
4661 ;; It must come before the more general floatsisf2 pattern.
4663 [(set (match_operand:SF 0 "register_operand" "=f")
4664 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4665 "! TARGET_SOFT_FLOAT"
4666 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4667 [(set_attr "type" "fpalu")
4668 (set_attr "length" "8")])
4670 (define_insn "floatsisf2"
4671 [(set (match_operand:SF 0 "register_operand" "=f")
4672 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4673 "! TARGET_SOFT_FLOAT"
4674 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4675 [(set_attr "type" "fpalu")
4676 (set_attr "length" "4")])
4678 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4679 ;; to be reloaded by putting the constant into memory.
4680 ;; It must come before the more general floatsidf2 pattern.
4682 [(set (match_operand:DF 0 "register_operand" "=f")
4683 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4684 "! TARGET_SOFT_FLOAT"
4685 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4686 [(set_attr "type" "fpalu")
4687 (set_attr "length" "8")])
4689 (define_insn "floatsidf2"
4690 [(set (match_operand:DF 0 "register_operand" "=f")
4691 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4692 "! TARGET_SOFT_FLOAT"
4693 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4694 [(set_attr "type" "fpalu")
4695 (set_attr "length" "4")])
4697 (define_expand "floatunssisf2"
4698 [(set (subreg:SI (match_dup 2) 4)
4699 (match_operand:SI 1 "register_operand" ""))
4700 (set (subreg:SI (match_dup 2) 0)
4702 (set (match_operand:SF 0 "register_operand" "")
4703 (float:SF (match_dup 2)))]
4704 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4709 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4712 operands[2] = gen_reg_rtx (DImode);
4715 (define_expand "floatunssidf2"
4716 [(set (subreg:SI (match_dup 2) 4)
4717 (match_operand:SI 1 "register_operand" ""))
4718 (set (subreg:SI (match_dup 2) 0)
4720 (set (match_operand:DF 0 "register_operand" "")
4721 (float:DF (match_dup 2)))]
4722 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4727 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4730 operands[2] = gen_reg_rtx (DImode);
4733 (define_insn "floatdisf2"
4734 [(set (match_operand:SF 0 "register_operand" "=f")
4735 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4736 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4737 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4738 [(set_attr "type" "fpalu")
4739 (set_attr "length" "4")])
4741 (define_insn "floatdidf2"
4742 [(set (match_operand:DF 0 "register_operand" "=f")
4743 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4744 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4745 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4746 [(set_attr "type" "fpalu")
4747 (set_attr "length" "4")])
4749 ;; Convert a float to an actual integer.
4750 ;; Truncation is performed as part of the conversion.
4752 (define_insn "fix_truncsfsi2"
4753 [(set (match_operand:SI 0 "register_operand" "=f")
4754 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4755 "! TARGET_SOFT_FLOAT"
4756 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4757 [(set_attr "type" "fpalu")
4758 (set_attr "length" "4")])
4760 (define_insn "fix_truncdfsi2"
4761 [(set (match_operand:SI 0 "register_operand" "=f")
4762 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4763 "! TARGET_SOFT_FLOAT"
4764 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4765 [(set_attr "type" "fpalu")
4766 (set_attr "length" "4")])
4768 (define_insn "fix_truncsfdi2"
4769 [(set (match_operand:DI 0 "register_operand" "=f")
4770 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4771 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4772 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4773 [(set_attr "type" "fpalu")
4774 (set_attr "length" "4")])
4776 (define_insn "fix_truncdfdi2"
4777 [(set (match_operand:DI 0 "register_operand" "=f")
4778 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4779 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4780 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4781 [(set_attr "type" "fpalu")
4782 (set_attr "length" "4")])
4784 (define_insn "floatunssidf2_pa20"
4785 [(set (match_operand:DF 0 "register_operand" "=f")
4786 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4787 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4789 [(set_attr "type" "fpalu")
4790 (set_attr "length" "4")])
4792 (define_insn "floatunssisf2_pa20"
4793 [(set (match_operand:SF 0 "register_operand" "=f")
4794 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4795 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4797 [(set_attr "type" "fpalu")
4798 (set_attr "length" "4")])
4800 (define_insn "floatunsdisf2"
4801 [(set (match_operand:SF 0 "register_operand" "=f")
4802 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4803 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4804 "fcnv,udw,sgl %1,%0"
4805 [(set_attr "type" "fpalu")
4806 (set_attr "length" "4")])
4808 (define_insn "floatunsdidf2"
4809 [(set (match_operand:DF 0 "register_operand" "=f")
4810 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4811 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4812 "fcnv,udw,dbl %1,%0"
4813 [(set_attr "type" "fpalu")
4814 (set_attr "length" "4")])
4816 (define_insn "fixuns_truncsfsi2"
4817 [(set (match_operand:SI 0 "register_operand" "=f")
4818 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4819 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4820 "fcnv,t,sgl,uw %1,%0"
4821 [(set_attr "type" "fpalu")
4822 (set_attr "length" "4")])
4824 (define_insn "fixuns_truncdfsi2"
4825 [(set (match_operand:SI 0 "register_operand" "=f")
4826 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4827 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4828 "fcnv,t,dbl,uw %1,%0"
4829 [(set_attr "type" "fpalu")
4830 (set_attr "length" "4")])
4832 (define_insn "fixuns_truncsfdi2"
4833 [(set (match_operand:DI 0 "register_operand" "=f")
4834 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4835 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4836 "fcnv,t,sgl,udw %1,%0"
4837 [(set_attr "type" "fpalu")
4838 (set_attr "length" "4")])
4840 (define_insn "fixuns_truncdfdi2"
4841 [(set (match_operand:DI 0 "register_operand" "=f")
4842 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4843 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4844 "fcnv,t,dbl,udw %1,%0"
4845 [(set_attr "type" "fpalu")
4846 (set_attr "length" "4")])
4848 ;;- arithmetic instructions
4850 (define_expand "adddi3"
4851 [(set (match_operand:DI 0 "register_operand" "")
4852 (plus:DI (match_operand:DI 1 "register_operand" "")
4853 (match_operand:DI 2 "adddi3_operand" "")))]
4858 [(set (match_operand:DI 0 "register_operand" "=r")
4859 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4860 (match_operand:DI 2 "arith11_operand" "rI")))]
4864 if (GET_CODE (operands[2]) == CONST_INT)
4866 if (INTVAL (operands[2]) >= 0)
4867 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4869 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4872 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4874 [(set_attr "type" "binary")
4875 (set_attr "length" "8")])
4878 [(set (match_operand:DI 0 "register_operand" "=r,r")
4879 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4880 (match_operand:DI 2 "arith_operand" "r,J")))]
4885 [(set_attr "type" "binary,binary")
4886 (set_attr "pa_combine_type" "addmove")
4887 (set_attr "length" "4,4")])
4890 [(set (match_operand:DI 0 "register_operand" "=r")
4891 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4892 (match_operand:DI 2 "register_operand" "r")))]
4895 [(set_attr "type" "binary")
4896 (set_attr "length" "4")])
4899 [(set (match_operand:SI 0 "register_operand" "=r")
4900 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4901 (match_operand:SI 2 "register_operand" "r")))]
4904 [(set_attr "type" "binary")
4905 (set_attr "length" "4")])
4907 ;; define_splits to optimize cases of adding a constant integer
4908 ;; to a register when the constant does not fit in 14 bits. */
4910 [(set (match_operand:SI 0 "register_operand" "")
4911 (plus:SI (match_operand:SI 1 "register_operand" "")
4912 (match_operand:SI 2 "const_int_operand" "")))
4913 (clobber (match_operand:SI 4 "register_operand" ""))]
4914 "! cint_ok_for_move (INTVAL (operands[2]))
4915 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4916 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4917 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4920 int val = INTVAL (operands[2]);
4921 int low = (val < 0) ? -0x2000 : 0x1fff;
4922 int rest = val - low;
4924 operands[2] = GEN_INT (rest);
4925 operands[3] = GEN_INT (low);
4929 [(set (match_operand:SI 0 "register_operand" "")
4930 (plus:SI (match_operand:SI 1 "register_operand" "")
4931 (match_operand:SI 2 "const_int_operand" "")))
4932 (clobber (match_operand:SI 4 "register_operand" ""))]
4933 "! cint_ok_for_move (INTVAL (operands[2]))"
4934 [(set (match_dup 4) (match_dup 2))
4935 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4939 HOST_WIDE_INT intval = INTVAL (operands[2]);
4941 /* Try dividing the constant by 2, then 4, and finally 8 to see
4942 if we can get a constant which can be loaded into a register
4943 in a single instruction (cint_ok_for_move).
4945 If that fails, try to negate the constant and subtract it
4946 from our input operand. */
4947 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4949 operands[2] = GEN_INT (intval / 2);
4950 operands[3] = const2_rtx;
4952 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
4954 operands[2] = GEN_INT (intval / 4);
4955 operands[3] = GEN_INT (4);
4957 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
4959 operands[2] = GEN_INT (intval / 8);
4960 operands[3] = GEN_INT (8);
4962 else if (cint_ok_for_move (-intval))
4964 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
4965 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
4972 (define_insn "addsi3"
4973 [(set (match_operand:SI 0 "register_operand" "=r,r")
4974 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
4975 (match_operand:SI 2 "arith_operand" "r,J")))]
4978 {addl|add,l} %1,%2,%0
4980 [(set_attr "type" "binary,binary")
4981 (set_attr "pa_combine_type" "addmove")
4982 (set_attr "length" "4,4")])
4984 (define_expand "subdi3"
4985 [(set (match_operand:DI 0 "register_operand" "")
4986 (minus:DI (match_operand:DI 1 "register_operand" "")
4987 (match_operand:DI 2 "register_operand" "")))]
4992 [(set (match_operand:DI 0 "register_operand" "=r")
4993 (minus:DI (match_operand:DI 1 "register_operand" "r")
4994 (match_operand:DI 2 "register_operand" "r")))]
4996 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
4997 [(set_attr "type" "binary")
4998 (set_attr "length" "8")])
5001 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5002 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5003 (match_operand:DI 2 "register_operand" "r,r,!r")))]
5009 [(set_attr "type" "binary,binary,move")
5010 (set_attr "length" "4,4,4")])
5012 (define_expand "subsi3"
5013 [(set (match_operand:SI 0 "register_operand" "")
5014 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5015 (match_operand:SI 2 "register_operand" "")))]
5020 [(set (match_operand:SI 0 "register_operand" "=r,r")
5021 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5022 (match_operand:SI 2 "register_operand" "r,r")))]
5027 [(set_attr "type" "binary,binary")
5028 (set_attr "length" "4,4")])
5031 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5032 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5033 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5039 [(set_attr "type" "binary,binary,move")
5040 (set_attr "length" "4,4,4")])
5042 ;; Clobbering a "register_operand" instead of a match_scratch
5043 ;; in operand3 of millicode calls avoids spilling %r1 and
5044 ;; produces better code.
5046 ;; The mulsi3 insns set up registers for the millicode call.
5047 (define_expand "mulsi3"
5048 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5049 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5050 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5051 (clobber (match_dup 3))
5052 (clobber (reg:SI 26))
5053 (clobber (reg:SI 25))
5054 (clobber (match_dup 4))])
5055 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5059 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5060 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5062 rtx scratch = gen_reg_rtx (DImode);
5063 operands[1] = force_reg (SImode, operands[1]);
5064 operands[2] = force_reg (SImode, operands[2]);
5065 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5066 emit_insn (gen_movsi (operands[0],
5067 gen_rtx_SUBREG (SImode, scratch,
5068 GET_MODE_SIZE (SImode))));
5071 operands[3] = gen_reg_rtx (SImode);
5074 (define_insn "umulsidi3"
5075 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5076 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5077 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5078 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5080 [(set_attr "type" "fpmuldbl")
5081 (set_attr "length" "4")])
5084 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5085 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5086 (match_operand:DI 2 "uint32_operand" "f")))]
5087 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5089 [(set_attr "type" "fpmuldbl")
5090 (set_attr "length" "4")])
5093 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5094 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5095 (match_operand:DI 2 "uint32_operand" "f")))]
5096 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5098 [(set_attr "type" "fpmuldbl")
5099 (set_attr "length" "4")])
5102 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5103 (clobber (match_operand:SI 0 "register_operand" "=a"))
5104 (clobber (reg:SI 26))
5105 (clobber (reg:SI 25))
5106 (clobber (reg:SI 31))]
5108 "* return output_mul_insn (0, insn);"
5109 [(set_attr "type" "milli")
5110 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5113 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5114 (clobber (match_operand:SI 0 "register_operand" "=a"))
5115 (clobber (reg:SI 26))
5116 (clobber (reg:SI 25))
5117 (clobber (reg:SI 2))]
5119 "* return output_mul_insn (0, insn);"
5120 [(set_attr "type" "milli")
5121 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5123 (define_expand "muldi3"
5124 [(set (match_operand:DI 0 "register_operand" "")
5125 (mult:DI (match_operand:DI 1 "register_operand" "")
5126 (match_operand:DI 2 "register_operand" "")))]
5127 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5130 rtx low_product = gen_reg_rtx (DImode);
5131 rtx cross_product1 = gen_reg_rtx (DImode);
5132 rtx cross_product2 = gen_reg_rtx (DImode);
5133 rtx cross_scratch = gen_reg_rtx (DImode);
5134 rtx cross_product = gen_reg_rtx (DImode);
5135 rtx op1l, op1r, op2l, op2r;
5136 rtx op1shifted, op2shifted;
5138 op1shifted = gen_reg_rtx (DImode);
5139 op2shifted = gen_reg_rtx (DImode);
5140 op1l = gen_reg_rtx (SImode);
5141 op1r = gen_reg_rtx (SImode);
5142 op2l = gen_reg_rtx (SImode);
5143 op2r = gen_reg_rtx (SImode);
5145 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5147 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5149 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5150 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5151 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5152 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5154 /* Emit multiplies for the cross products. */
5155 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5156 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5158 /* Emit a multiply for the low sub-word. */
5159 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5161 /* Sum the cross products and shift them into proper position. */
5162 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5163 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5165 /* Add the cross product to the low product and store the result
5166 into the output operand . */
5167 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5171 ;;; Division and mod.
5172 (define_expand "divsi3"
5173 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5174 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5175 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5176 (clobber (match_dup 3))
5177 (clobber (match_dup 4))
5178 (clobber (reg:SI 26))
5179 (clobber (reg:SI 25))
5180 (clobber (match_dup 5))])
5181 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5185 operands[3] = gen_reg_rtx (SImode);
5188 operands[5] = gen_rtx_REG (SImode, 2);
5189 operands[4] = operands[5];
5193 operands[5] = gen_rtx_REG (SImode, 31);
5194 operands[4] = gen_reg_rtx (SImode);
5196 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5202 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5203 (clobber (match_operand:SI 1 "register_operand" "=a"))
5204 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5205 (clobber (reg:SI 26))
5206 (clobber (reg:SI 25))
5207 (clobber (reg:SI 31))]
5210 return output_div_insn (operands, 0, insn);"
5211 [(set_attr "type" "milli")
5212 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5216 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5217 (clobber (match_operand:SI 1 "register_operand" "=a"))
5218 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5219 (clobber (reg:SI 26))
5220 (clobber (reg:SI 25))
5221 (clobber (reg:SI 2))]
5224 return output_div_insn (operands, 0, insn);"
5225 [(set_attr "type" "milli")
5226 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5228 (define_expand "udivsi3"
5229 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5230 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5231 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5232 (clobber (match_dup 3))
5233 (clobber (match_dup 4))
5234 (clobber (reg:SI 26))
5235 (clobber (reg:SI 25))
5236 (clobber (match_dup 5))])
5237 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5241 operands[3] = gen_reg_rtx (SImode);
5245 operands[5] = gen_rtx_REG (SImode, 2);
5246 operands[4] = operands[5];
5250 operands[5] = gen_rtx_REG (SImode, 31);
5251 operands[4] = gen_reg_rtx (SImode);
5253 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5259 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5260 (clobber (match_operand:SI 1 "register_operand" "=a"))
5261 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5262 (clobber (reg:SI 26))
5263 (clobber (reg:SI 25))
5264 (clobber (reg:SI 31))]
5267 return output_div_insn (operands, 1, insn);"
5268 [(set_attr "type" "milli")
5269 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5273 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5274 (clobber (match_operand:SI 1 "register_operand" "=a"))
5275 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5276 (clobber (reg:SI 26))
5277 (clobber (reg:SI 25))
5278 (clobber (reg:SI 2))]
5281 return output_div_insn (operands, 1, insn);"
5282 [(set_attr "type" "milli")
5283 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5285 (define_expand "modsi3"
5286 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5287 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5288 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5289 (clobber (match_dup 3))
5290 (clobber (match_dup 4))
5291 (clobber (reg:SI 26))
5292 (clobber (reg:SI 25))
5293 (clobber (match_dup 5))])
5294 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5300 operands[5] = gen_rtx_REG (SImode, 2);
5301 operands[4] = operands[5];
5305 operands[5] = gen_rtx_REG (SImode, 31);
5306 operands[4] = gen_reg_rtx (SImode);
5308 operands[3] = gen_reg_rtx (SImode);
5312 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5313 (clobber (match_operand:SI 0 "register_operand" "=a"))
5314 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5315 (clobber (reg:SI 26))
5316 (clobber (reg:SI 25))
5317 (clobber (reg:SI 31))]
5320 return output_mod_insn (0, insn);"
5321 [(set_attr "type" "milli")
5322 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5325 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5326 (clobber (match_operand:SI 0 "register_operand" "=a"))
5327 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5328 (clobber (reg:SI 26))
5329 (clobber (reg:SI 25))
5330 (clobber (reg:SI 2))]
5333 return output_mod_insn (0, insn);"
5334 [(set_attr "type" "milli")
5335 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5337 (define_expand "umodsi3"
5338 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5339 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5340 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5341 (clobber (match_dup 3))
5342 (clobber (match_dup 4))
5343 (clobber (reg:SI 26))
5344 (clobber (reg:SI 25))
5345 (clobber (match_dup 5))])
5346 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5352 operands[5] = gen_rtx_REG (SImode, 2);
5353 operands[4] = operands[5];
5357 operands[5] = gen_rtx_REG (SImode, 31);
5358 operands[4] = gen_reg_rtx (SImode);
5360 operands[3] = gen_reg_rtx (SImode);
5364 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5365 (clobber (match_operand:SI 0 "register_operand" "=a"))
5366 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5367 (clobber (reg:SI 26))
5368 (clobber (reg:SI 25))
5369 (clobber (reg:SI 31))]
5372 return output_mod_insn (1, insn);"
5373 [(set_attr "type" "milli")
5374 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5377 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5378 (clobber (match_operand:SI 0 "register_operand" "=a"))
5379 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5380 (clobber (reg:SI 26))
5381 (clobber (reg:SI 25))
5382 (clobber (reg:SI 2))]
5385 return output_mod_insn (1, insn);"
5386 [(set_attr "type" "milli")
5387 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5389 ;;- and instructions
5390 ;; We define DImode `and` so with DImode `not` we can get
5391 ;; DImode `andn`. Other combinations are possible.
5393 (define_expand "anddi3"
5394 [(set (match_operand:DI 0 "register_operand" "")
5395 (and:DI (match_operand:DI 1 "and_operand" "")
5396 (match_operand:DI 2 "and_operand" "")))]
5402 /* One operand must be a register operand. */
5403 if (!register_operand (operands[1], DImode)
5404 && !register_operand (operands[2], DImode))
5409 /* Both operands must be register operands. */
5410 if (!register_operand (operands[1], DImode)
5411 || !register_operand (operands[2], DImode))
5417 [(set (match_operand:DI 0 "register_operand" "=r")
5418 (and:DI (match_operand:DI 1 "register_operand" "%r")
5419 (match_operand:DI 2 "register_operand" "r")))]
5421 "and %1,%2,%0\;and %R1,%R2,%R0"
5422 [(set_attr "type" "binary")
5423 (set_attr "length" "8")])
5426 [(set (match_operand:DI 0 "register_operand" "=r,r")
5427 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5428 (match_operand:DI 2 "and_operand" "rO,P")))]
5430 "* return output_64bit_and (operands); "
5431 [(set_attr "type" "binary")
5432 (set_attr "length" "4")])
5434 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5435 ; constant with ldil;ldo.
5436 (define_insn "andsi3"
5437 [(set (match_operand:SI 0 "register_operand" "=r,r")
5438 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5439 (match_operand:SI 2 "and_operand" "rO,P")))]
5441 "* return output_and (operands); "
5442 [(set_attr "type" "binary,shift")
5443 (set_attr "length" "4,4")])
5446 [(set (match_operand:DI 0 "register_operand" "=r")
5447 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5448 (match_operand:DI 2 "register_operand" "r")))]
5450 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5451 [(set_attr "type" "binary")
5452 (set_attr "length" "8")])
5455 [(set (match_operand:DI 0 "register_operand" "=r")
5456 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5457 (match_operand:DI 2 "register_operand" "r")))]
5460 [(set_attr "type" "binary")
5461 (set_attr "length" "4")])
5464 [(set (match_operand:SI 0 "register_operand" "=r")
5465 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5466 (match_operand:SI 2 "register_operand" "r")))]
5469 [(set_attr "type" "binary")
5470 (set_attr "length" "4")])
5472 (define_expand "iordi3"
5473 [(set (match_operand:DI 0 "register_operand" "")
5474 (ior:DI (match_operand:DI 1 "ior_operand" "")
5475 (match_operand:DI 2 "ior_operand" "")))]
5481 /* One operand must be a register operand. */
5482 if (!register_operand (operands[1], DImode)
5483 && !register_operand (operands[2], DImode))
5488 /* Both operands must be register operands. */
5489 if (!register_operand (operands[1], DImode)
5490 || !register_operand (operands[2], DImode))
5496 [(set (match_operand:DI 0 "register_operand" "=r")
5497 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5498 (match_operand:DI 2 "register_operand" "r")))]
5500 "or %1,%2,%0\;or %R1,%R2,%R0"
5501 [(set_attr "type" "binary")
5502 (set_attr "length" "8")])
5505 [(set (match_operand:DI 0 "register_operand" "=r,r")
5506 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5507 (match_operand:DI 2 "ior_operand" "M,i")))]
5509 "* return output_64bit_ior (operands); "
5510 [(set_attr "type" "binary,shift")
5511 (set_attr "length" "4,4")])
5514 [(set (match_operand:DI 0 "register_operand" "=r")
5515 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5516 (match_operand:DI 2 "register_operand" "r")))]
5519 [(set_attr "type" "binary")
5520 (set_attr "length" "4")])
5522 ;; Need a define_expand because we've run out of CONST_OK... characters.
5523 (define_expand "iorsi3"
5524 [(set (match_operand:SI 0 "register_operand" "")
5525 (ior:SI (match_operand:SI 1 "register_operand" "")
5526 (match_operand:SI 2 "arith32_operand" "")))]
5530 if (! (ior_operand (operands[2], SImode)
5531 || register_operand (operands[2], SImode)))
5532 operands[2] = force_reg (SImode, operands[2]);
5536 [(set (match_operand:SI 0 "register_operand" "=r,r")
5537 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5538 (match_operand:SI 2 "ior_operand" "M,i")))]
5540 "* return output_ior (operands); "
5541 [(set_attr "type" "binary,shift")
5542 (set_attr "length" "4,4")])
5545 [(set (match_operand:SI 0 "register_operand" "=r")
5546 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5547 (match_operand:SI 2 "register_operand" "r")))]
5550 [(set_attr "type" "binary")
5551 (set_attr "length" "4")])
5553 (define_expand "xordi3"
5554 [(set (match_operand:DI 0 "register_operand" "")
5555 (xor:DI (match_operand:DI 1 "register_operand" "")
5556 (match_operand:DI 2 "register_operand" "")))]
5563 [(set (match_operand:DI 0 "register_operand" "=r")
5564 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5565 (match_operand:DI 2 "register_operand" "r")))]
5567 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5568 [(set_attr "type" "binary")
5569 (set_attr "length" "8")])
5572 [(set (match_operand:DI 0 "register_operand" "=r")
5573 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5574 (match_operand:DI 2 "register_operand" "r")))]
5577 [(set_attr "type" "binary")
5578 (set_attr "length" "4")])
5580 (define_insn "xorsi3"
5581 [(set (match_operand:SI 0 "register_operand" "=r")
5582 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5583 (match_operand:SI 2 "register_operand" "r")))]
5586 [(set_attr "type" "binary")
5587 (set_attr "length" "4")])
5589 (define_expand "negdi2"
5590 [(set (match_operand:DI 0 "register_operand" "")
5591 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5596 [(set (match_operand:DI 0 "register_operand" "=r")
5597 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5599 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5600 [(set_attr "type" "unary")
5601 (set_attr "length" "8")])
5604 [(set (match_operand:DI 0 "register_operand" "=r")
5605 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5608 [(set_attr "type" "unary")
5609 (set_attr "length" "4")])
5611 (define_insn "negsi2"
5612 [(set (match_operand:SI 0 "register_operand" "=r")
5613 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5616 [(set_attr "type" "unary")
5617 (set_attr "length" "4")])
5619 (define_expand "one_cmpldi2"
5620 [(set (match_operand:DI 0 "register_operand" "")
5621 (not:DI (match_operand:DI 1 "register_operand" "")))]
5628 [(set (match_operand:DI 0 "register_operand" "=r")
5629 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5631 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5632 [(set_attr "type" "unary")
5633 (set_attr "length" "8")])
5636 [(set (match_operand:DI 0 "register_operand" "=r")
5637 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5640 [(set_attr "type" "unary")
5641 (set_attr "length" "4")])
5643 (define_insn "one_cmplsi2"
5644 [(set (match_operand:SI 0 "register_operand" "=r")
5645 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5648 [(set_attr "type" "unary")
5649 (set_attr "length" "4")])
5651 ;; Floating point arithmetic instructions.
5653 (define_insn "adddf3"
5654 [(set (match_operand:DF 0 "register_operand" "=f")
5655 (plus:DF (match_operand:DF 1 "register_operand" "f")
5656 (match_operand:DF 2 "register_operand" "f")))]
5657 "! TARGET_SOFT_FLOAT"
5659 [(set_attr "type" "fpalu")
5660 (set_attr "pa_combine_type" "faddsub")
5661 (set_attr "length" "4")])
5663 (define_insn "addsf3"
5664 [(set (match_operand:SF 0 "register_operand" "=f")
5665 (plus:SF (match_operand:SF 1 "register_operand" "f")
5666 (match_operand:SF 2 "register_operand" "f")))]
5667 "! TARGET_SOFT_FLOAT"
5669 [(set_attr "type" "fpalu")
5670 (set_attr "pa_combine_type" "faddsub")
5671 (set_attr "length" "4")])
5673 (define_insn "subdf3"
5674 [(set (match_operand:DF 0 "register_operand" "=f")
5675 (minus:DF (match_operand:DF 1 "register_operand" "f")
5676 (match_operand:DF 2 "register_operand" "f")))]
5677 "! TARGET_SOFT_FLOAT"
5679 [(set_attr "type" "fpalu")
5680 (set_attr "pa_combine_type" "faddsub")
5681 (set_attr "length" "4")])
5683 (define_insn "subsf3"
5684 [(set (match_operand:SF 0 "register_operand" "=f")
5685 (minus:SF (match_operand:SF 1 "register_operand" "f")
5686 (match_operand:SF 2 "register_operand" "f")))]
5687 "! TARGET_SOFT_FLOAT"
5689 [(set_attr "type" "fpalu")
5690 (set_attr "pa_combine_type" "faddsub")
5691 (set_attr "length" "4")])
5693 (define_insn "muldf3"
5694 [(set (match_operand:DF 0 "register_operand" "=f")
5695 (mult:DF (match_operand:DF 1 "register_operand" "f")
5696 (match_operand:DF 2 "register_operand" "f")))]
5697 "! TARGET_SOFT_FLOAT"
5699 [(set_attr "type" "fpmuldbl")
5700 (set_attr "pa_combine_type" "fmpy")
5701 (set_attr "length" "4")])
5703 (define_insn "mulsf3"
5704 [(set (match_operand:SF 0 "register_operand" "=f")
5705 (mult:SF (match_operand:SF 1 "register_operand" "f")
5706 (match_operand:SF 2 "register_operand" "f")))]
5707 "! TARGET_SOFT_FLOAT"
5709 [(set_attr "type" "fpmulsgl")
5710 (set_attr "pa_combine_type" "fmpy")
5711 (set_attr "length" "4")])
5713 (define_insn "divdf3"
5714 [(set (match_operand:DF 0 "register_operand" "=f")
5715 (div:DF (match_operand:DF 1 "register_operand" "f")
5716 (match_operand:DF 2 "register_operand" "f")))]
5717 "! TARGET_SOFT_FLOAT"
5719 [(set_attr "type" "fpdivdbl")
5720 (set_attr "length" "4")])
5722 (define_insn "divsf3"
5723 [(set (match_operand:SF 0 "register_operand" "=f")
5724 (div:SF (match_operand:SF 1 "register_operand" "f")
5725 (match_operand:SF 2 "register_operand" "f")))]
5726 "! TARGET_SOFT_FLOAT"
5728 [(set_attr "type" "fpdivsgl")
5729 (set_attr "length" "4")])
5731 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5732 ;; negation can be done by subtracting from plus zero. However, this
5733 ;; violates the IEEE standard when negating plus and minus zero.
5734 (define_expand "negdf2"
5735 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5736 (neg:DF (match_operand:DF 1 "register_operand" "")))
5737 (use (match_dup 2))])]
5738 "! TARGET_SOFT_FLOAT"
5740 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5741 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5744 operands[2] = force_reg (DFmode,
5745 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5746 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5751 (define_insn "negdf2_fast"
5752 [(set (match_operand:DF 0 "register_operand" "=f")
5753 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5754 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5758 return \"fneg,dbl %1,%0\";
5760 return \"fsub,dbl %%fr0,%1,%0\";
5762 [(set_attr "type" "fpalu")
5763 (set_attr "length" "4")])
5765 (define_expand "negsf2"
5766 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5767 (neg:SF (match_operand:SF 1 "register_operand" "")))
5768 (use (match_dup 2))])]
5769 "! TARGET_SOFT_FLOAT"
5771 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5772 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5775 operands[2] = force_reg (SFmode,
5776 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5777 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5782 (define_insn "negsf2_fast"
5783 [(set (match_operand:SF 0 "register_operand" "=f")
5784 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5785 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5789 return \"fneg,sgl %1,%0\";
5791 return \"fsub,sgl %%fr0,%1,%0\";
5793 [(set_attr "type" "fpalu")
5794 (set_attr "length" "4")])
5796 (define_insn "absdf2"
5797 [(set (match_operand:DF 0 "register_operand" "=f")
5798 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5799 "! TARGET_SOFT_FLOAT"
5801 [(set_attr "type" "fpalu")
5802 (set_attr "length" "4")])
5804 (define_insn "abssf2"
5805 [(set (match_operand:SF 0 "register_operand" "=f")
5806 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5807 "! TARGET_SOFT_FLOAT"
5809 [(set_attr "type" "fpalu")
5810 (set_attr "length" "4")])
5812 (define_insn "sqrtdf2"
5813 [(set (match_operand:DF 0 "register_operand" "=f")
5814 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5815 "! TARGET_SOFT_FLOAT"
5817 [(set_attr "type" "fpsqrtdbl")
5818 (set_attr "length" "4")])
5820 (define_insn "sqrtsf2"
5821 [(set (match_operand:SF 0 "register_operand" "=f")
5822 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5823 "! TARGET_SOFT_FLOAT"
5825 [(set_attr "type" "fpsqrtsgl")
5826 (set_attr "length" "4")])
5828 ;; PA 2.0 floating point instructions
5832 [(set (match_operand:DF 0 "register_operand" "=f")
5833 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5834 (match_operand:DF 2 "register_operand" "f"))
5835 (match_operand:DF 3 "register_operand" "f")))]
5836 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5837 "fmpyfadd,dbl %1,%2,%3,%0"
5838 [(set_attr "type" "fpmuldbl")
5839 (set_attr "length" "4")])
5842 [(set (match_operand:DF 0 "register_operand" "=f")
5843 (plus:DF (match_operand:DF 1 "register_operand" "f")
5844 (mult:DF (match_operand:DF 2 "register_operand" "f")
5845 (match_operand:DF 3 "register_operand" "f"))))]
5846 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5847 "fmpyfadd,dbl %2,%3,%1,%0"
5848 [(set_attr "type" "fpmuldbl")
5849 (set_attr "length" "4")])
5852 [(set (match_operand:SF 0 "register_operand" "=f")
5853 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5854 (match_operand:SF 2 "register_operand" "f"))
5855 (match_operand:SF 3 "register_operand" "f")))]
5856 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5857 "fmpyfadd,sgl %1,%2,%3,%0"
5858 [(set_attr "type" "fpmulsgl")
5859 (set_attr "length" "4")])
5862 [(set (match_operand:SF 0 "register_operand" "=f")
5863 (plus:SF (match_operand:SF 1 "register_operand" "f")
5864 (mult:SF (match_operand:SF 2 "register_operand" "f")
5865 (match_operand:SF 3 "register_operand" "f"))))]
5866 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5867 "fmpyfadd,sgl %2,%3,%1,%0"
5868 [(set_attr "type" "fpmulsgl")
5869 (set_attr "length" "4")])
5871 ; fmpynfadd patterns
5873 [(set (match_operand:DF 0 "register_operand" "=f")
5874 (minus:DF (match_operand:DF 1 "register_operand" "f")
5875 (mult:DF (match_operand:DF 2 "register_operand" "f")
5876 (match_operand:DF 3 "register_operand" "f"))))]
5877 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5878 "fmpynfadd,dbl %2,%3,%1,%0"
5879 [(set_attr "type" "fpmuldbl")
5880 (set_attr "length" "4")])
5883 [(set (match_operand:SF 0 "register_operand" "=f")
5884 (minus:SF (match_operand:SF 1 "register_operand" "f")
5885 (mult:SF (match_operand:SF 2 "register_operand" "f")
5886 (match_operand:SF 3 "register_operand" "f"))))]
5887 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5888 "fmpynfadd,sgl %2,%3,%1,%0"
5889 [(set_attr "type" "fpmulsgl")
5890 (set_attr "length" "4")])
5894 [(set (match_operand:DF 0 "register_operand" "=f")
5895 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
5896 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5898 [(set_attr "type" "fpalu")
5899 (set_attr "length" "4")])
5902 [(set (match_operand:SF 0 "register_operand" "=f")
5903 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
5904 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5906 [(set_attr "type" "fpalu")
5907 (set_attr "length" "4")])
5909 ;; Generating a fused multiply sequence is a win for this case as it will
5910 ;; reduce the latency for the fused case without impacting the plain
5913 ;; Similar possibilities exist for fnegabs, shadd and other insns which
5914 ;; perform two operations with the result of the first feeding the second.
5916 [(set (match_operand:DF 0 "register_operand" "=f")
5917 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5918 (match_operand:DF 2 "register_operand" "f"))
5919 (match_operand:DF 3 "register_operand" "f")))
5920 (set (match_operand:DF 4 "register_operand" "=&f")
5921 (mult:DF (match_dup 1) (match_dup 2)))]
5922 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5923 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5924 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5926 [(set_attr "type" "fpmuldbl")
5927 (set_attr "length" "8")])
5929 ;; We want to split this up during scheduling since we want both insns
5930 ;; to schedule independently.
5932 [(set (match_operand:DF 0 "register_operand" "")
5933 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5934 (match_operand:DF 2 "register_operand" ""))
5935 (match_operand:DF 3 "register_operand" "")))
5936 (set (match_operand:DF 4 "register_operand" "")
5937 (mult:DF (match_dup 1) (match_dup 2)))]
5938 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5939 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5940 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
5945 [(set (match_operand:SF 0 "register_operand" "=f")
5946 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5947 (match_operand:SF 2 "register_operand" "f"))
5948 (match_operand:SF 3 "register_operand" "f")))
5949 (set (match_operand:SF 4 "register_operand" "=&f")
5950 (mult:SF (match_dup 1) (match_dup 2)))]
5951 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5952 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5953 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5955 [(set_attr "type" "fpmuldbl")
5956 (set_attr "length" "8")])
5958 ;; We want to split this up during scheduling since we want both insns
5959 ;; to schedule independently.
5961 [(set (match_operand:SF 0 "register_operand" "")
5962 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5963 (match_operand:SF 2 "register_operand" ""))
5964 (match_operand:SF 3 "register_operand" "")))
5965 (set (match_operand:SF 4 "register_operand" "")
5966 (mult:SF (match_dup 1) (match_dup 2)))]
5967 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5968 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5969 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
5973 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
5976 [(set (match_operand:DF 0 "register_operand" "=f")
5977 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5978 (match_operand:DF 2 "register_operand" "f"))))]
5979 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5980 "fmpynfadd,dbl %1,%2,%%fr0,%0"
5981 [(set_attr "type" "fpmuldbl")
5982 (set_attr "length" "4")])
5985 [(set (match_operand:SF 0 "register_operand" "=f")
5986 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5987 (match_operand:SF 2 "register_operand" "f"))))]
5988 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5989 "fmpynfadd,sgl %1,%2,%%fr0,%0"
5990 [(set_attr "type" "fpmuldbl")
5991 (set_attr "length" "4")])
5994 [(set (match_operand:DF 0 "register_operand" "=f")
5995 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5996 (match_operand:DF 2 "register_operand" "f"))))
5997 (set (match_operand:DF 3 "register_operand" "=&f")
5998 (mult:DF (match_dup 1) (match_dup 2)))]
5999 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6000 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6001 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6003 [(set_attr "type" "fpmuldbl")
6004 (set_attr "length" "8")])
6007 [(set (match_operand:DF 0 "register_operand" "")
6008 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6009 (match_operand:DF 2 "register_operand" ""))))
6010 (set (match_operand:DF 3 "register_operand" "")
6011 (mult:DF (match_dup 1) (match_dup 2)))]
6012 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6013 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6014 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6018 [(set (match_operand:SF 0 "register_operand" "=f")
6019 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6020 (match_operand:SF 2 "register_operand" "f"))))
6021 (set (match_operand:SF 3 "register_operand" "=&f")
6022 (mult:SF (match_dup 1) (match_dup 2)))]
6023 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6024 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6025 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6027 [(set_attr "type" "fpmuldbl")
6028 (set_attr "length" "8")])
6031 [(set (match_operand:SF 0 "register_operand" "")
6032 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6033 (match_operand:SF 2 "register_operand" ""))))
6034 (set (match_operand:SF 3 "register_operand" "")
6035 (mult:SF (match_dup 1) (match_dup 2)))]
6036 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6037 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6038 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6041 ;; Now fused multiplies with the result of the multiply negated.
6043 [(set (match_operand:DF 0 "register_operand" "=f")
6044 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6045 (match_operand:DF 2 "register_operand" "f")))
6046 (match_operand:DF 3 "register_operand" "f")))]
6047 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6048 "fmpynfadd,dbl %1,%2,%3,%0"
6049 [(set_attr "type" "fpmuldbl")
6050 (set_attr "length" "4")])
6053 [(set (match_operand:SF 0 "register_operand" "=f")
6054 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6055 (match_operand:SF 2 "register_operand" "f")))
6056 (match_operand:SF 3 "register_operand" "f")))]
6057 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6058 "fmpynfadd,sgl %1,%2,%3,%0"
6059 [(set_attr "type" "fpmuldbl")
6060 (set_attr "length" "4")])
6063 [(set (match_operand:DF 0 "register_operand" "=f")
6064 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6065 (match_operand:DF 2 "register_operand" "f")))
6066 (match_operand:DF 3 "register_operand" "f")))
6067 (set (match_operand:DF 4 "register_operand" "=&f")
6068 (mult:DF (match_dup 1) (match_dup 2)))]
6069 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6070 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6071 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6073 [(set_attr "type" "fpmuldbl")
6074 (set_attr "length" "8")])
6077 [(set (match_operand:DF 0 "register_operand" "")
6078 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6079 (match_operand:DF 2 "register_operand" "")))
6080 (match_operand:DF 3 "register_operand" "")))
6081 (set (match_operand:DF 4 "register_operand" "")
6082 (mult:DF (match_dup 1) (match_dup 2)))]
6083 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6084 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6085 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6090 [(set (match_operand:SF 0 "register_operand" "=f")
6091 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6092 (match_operand:SF 2 "register_operand" "f")))
6093 (match_operand:SF 3 "register_operand" "f")))
6094 (set (match_operand:SF 4 "register_operand" "=&f")
6095 (mult:SF (match_dup 1) (match_dup 2)))]
6096 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6097 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6098 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6100 [(set_attr "type" "fpmuldbl")
6101 (set_attr "length" "8")])
6104 [(set (match_operand:SF 0 "register_operand" "")
6105 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6106 (match_operand:SF 2 "register_operand" "")))
6107 (match_operand:SF 3 "register_operand" "")))
6108 (set (match_operand:SF 4 "register_operand" "")
6109 (mult:SF (match_dup 1) (match_dup 2)))]
6110 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6111 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6112 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6117 [(set (match_operand:DF 0 "register_operand" "=f")
6118 (minus:DF (match_operand:DF 3 "register_operand" "f")
6119 (mult:DF (match_operand:DF 1 "register_operand" "f")
6120 (match_operand:DF 2 "register_operand" "f"))))
6121 (set (match_operand:DF 4 "register_operand" "=&f")
6122 (mult:DF (match_dup 1) (match_dup 2)))]
6123 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6124 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6125 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6127 [(set_attr "type" "fpmuldbl")
6128 (set_attr "length" "8")])
6131 [(set (match_operand:DF 0 "register_operand" "")
6132 (minus:DF (match_operand:DF 3 "register_operand" "")
6133 (mult:DF (match_operand:DF 1 "register_operand" "")
6134 (match_operand:DF 2 "register_operand" ""))))
6135 (set (match_operand:DF 4 "register_operand" "")
6136 (mult:DF (match_dup 1) (match_dup 2)))]
6137 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6138 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6139 (set (match_dup 0) (minus:DF (match_dup 3)
6140 (mult:DF (match_dup 1) (match_dup 2))))]
6144 [(set (match_operand:SF 0 "register_operand" "=f")
6145 (minus:SF (match_operand:SF 3 "register_operand" "f")
6146 (mult:SF (match_operand:SF 1 "register_operand" "f")
6147 (match_operand:SF 2 "register_operand" "f"))))
6148 (set (match_operand:SF 4 "register_operand" "=&f")
6149 (mult:SF (match_dup 1) (match_dup 2)))]
6150 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6151 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6152 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6154 [(set_attr "type" "fpmuldbl")
6155 (set_attr "length" "8")])
6158 [(set (match_operand:SF 0 "register_operand" "")
6159 (minus:SF (match_operand:SF 3 "register_operand" "")
6160 (mult:SF (match_operand:SF 1 "register_operand" "")
6161 (match_operand:SF 2 "register_operand" ""))))
6162 (set (match_operand:SF 4 "register_operand" "")
6163 (mult:SF (match_dup 1) (match_dup 2)))]
6164 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6165 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6166 (set (match_dup 0) (minus:SF (match_dup 3)
6167 (mult:SF (match_dup 1) (match_dup 2))))]
6171 [(set (match_operand:DF 0 "register_operand" "=f")
6172 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6173 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6174 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6175 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6177 [(set_attr "type" "fpalu")
6178 (set_attr "length" "8")])
6181 [(set (match_operand:DF 0 "register_operand" "")
6182 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6183 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6184 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6185 [(set (match_dup 2) (abs:DF (match_dup 1)))
6186 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6190 [(set (match_operand:SF 0 "register_operand" "=f")
6191 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6192 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6193 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6194 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6196 [(set_attr "type" "fpalu")
6197 (set_attr "length" "8")])
6200 [(set (match_operand:SF 0 "register_operand" "")
6201 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6202 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6203 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6204 [(set (match_dup 2) (abs:SF (match_dup 1)))
6205 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6208 ;;- Shift instructions
6210 ;; Optimized special case of shifting.
6213 [(set (match_operand:SI 0 "register_operand" "=r")
6214 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6218 [(set_attr "type" "load")
6219 (set_attr "length" "4")])
6222 [(set (match_operand:SI 0 "register_operand" "=r")
6223 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6227 [(set_attr "type" "load")
6228 (set_attr "length" "4")])
6231 [(set (match_operand:SI 0 "register_operand" "=r")
6232 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6233 (match_operand:SI 3 "shadd_operand" ""))
6234 (match_operand:SI 1 "register_operand" "r")))]
6236 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6237 [(set_attr "type" "binary")
6238 (set_attr "length" "4")])
6241 [(set (match_operand:DI 0 "register_operand" "=r")
6242 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6243 (match_operand:DI 3 "shadd_operand" ""))
6244 (match_operand:DI 1 "register_operand" "r")))]
6246 "shladd,l %2,%O3,%1,%0"
6247 [(set_attr "type" "binary")
6248 (set_attr "length" "4")])
6250 (define_expand "ashlsi3"
6251 [(set (match_operand:SI 0 "register_operand" "")
6252 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6253 (match_operand:SI 2 "arith32_operand" "")))]
6257 if (GET_CODE (operands[2]) != CONST_INT)
6259 rtx temp = gen_reg_rtx (SImode);
6260 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6261 if (GET_CODE (operands[1]) == CONST_INT)
6262 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6264 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6267 /* Make sure both inputs are not constants,
6268 there are no patterns for that. */
6269 operands[1] = force_reg (SImode, operands[1]);
6273 [(set (match_operand:SI 0 "register_operand" "=r")
6274 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6275 (match_operand:SI 2 "const_int_operand" "n")))]
6277 "{zdep|depw,z} %1,%P2,%L2,%0"
6278 [(set_attr "type" "shift")
6279 (set_attr "length" "4")])
6281 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6282 ; Doing it like this makes slightly better code since reload can
6283 ; replace a register with a known value in range -16..15 with a
6284 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6285 ; but since we have no more CONST_OK... characters, that is not
6287 (define_insn "zvdep32"
6288 [(set (match_operand:SI 0 "register_operand" "=r,r")
6289 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6290 (minus:SI (const_int 31)
6291 (match_operand:SI 2 "register_operand" "q,q"))))]
6294 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6295 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6296 [(set_attr "type" "shift,shift")
6297 (set_attr "length" "4,4")])
6299 (define_insn "zvdep_imm32"
6300 [(set (match_operand:SI 0 "register_operand" "=r")
6301 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6302 (minus:SI (const_int 31)
6303 (match_operand:SI 2 "register_operand" "q"))))]
6307 int x = INTVAL (operands[1]);
6308 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6309 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6310 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6312 [(set_attr "type" "shift")
6313 (set_attr "length" "4")])
6315 (define_insn "vdepi_ior"
6316 [(set (match_operand:SI 0 "register_operand" "=r")
6317 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6318 (minus:SI (const_int 31)
6319 (match_operand:SI 2 "register_operand" "q")))
6320 (match_operand:SI 3 "register_operand" "0")))]
6321 ; accept ...0001...1, can this be generalized?
6322 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6325 int x = INTVAL (operands[1]);
6326 operands[2] = GEN_INT (exact_log2 (x + 1));
6327 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6329 [(set_attr "type" "shift")
6330 (set_attr "length" "4")])
6332 (define_insn "vdepi_and"
6333 [(set (match_operand:SI 0 "register_operand" "=r")
6334 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6335 (minus:SI (const_int 31)
6336 (match_operand:SI 2 "register_operand" "q")))
6337 (match_operand:SI 3 "register_operand" "0")))]
6338 ; this can be generalized...!
6339 "INTVAL (operands[1]) == -2"
6342 int x = INTVAL (operands[1]);
6343 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6344 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6346 [(set_attr "type" "shift")
6347 (set_attr "length" "4")])
6349 (define_expand "ashldi3"
6350 [(set (match_operand:DI 0 "register_operand" "")
6351 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6352 (match_operand:DI 2 "arith32_operand" "")))]
6356 if (GET_CODE (operands[2]) != CONST_INT)
6358 rtx temp = gen_reg_rtx (DImode);
6359 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6360 if (GET_CODE (operands[1]) == CONST_INT)
6361 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6363 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6366 /* Make sure both inputs are not constants,
6367 there are no patterns for that. */
6368 operands[1] = force_reg (DImode, operands[1]);
6372 [(set (match_operand:DI 0 "register_operand" "=r")
6373 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6374 (match_operand:DI 2 "const_int_operand" "n")))]
6376 "depd,z %1,%p2,%Q2,%0"
6377 [(set_attr "type" "shift")
6378 (set_attr "length" "4")])
6380 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6381 ; Doing it like this makes slightly better code since reload can
6382 ; replace a register with a known value in range -16..15 with a
6383 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6384 ; but since we have no more CONST_OK... characters, that is not
6386 (define_insn "zvdep64"
6387 [(set (match_operand:DI 0 "register_operand" "=r,r")
6388 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6389 (minus:DI (const_int 63)
6390 (match_operand:DI 2 "register_operand" "q,q"))))]
6393 depd,z %1,%%sar,64,%0
6394 depdi,z %1,%%sar,64,%0"
6395 [(set_attr "type" "shift,shift")
6396 (set_attr "length" "4,4")])
6398 (define_insn "zvdep_imm64"
6399 [(set (match_operand:DI 0 "register_operand" "=r")
6400 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6401 (minus:DI (const_int 63)
6402 (match_operand:DI 2 "register_operand" "q"))))]
6406 int x = INTVAL (operands[1]);
6407 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6408 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6409 return \"depdi,z %1,%%sar,%2,%0\";
6411 [(set_attr "type" "shift")
6412 (set_attr "length" "4")])
6415 [(set (match_operand:DI 0 "register_operand" "=r")
6416 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6417 (minus:DI (const_int 63)
6418 (match_operand:DI 2 "register_operand" "q")))
6419 (match_operand:DI 3 "register_operand" "0")))]
6420 ; accept ...0001...1, can this be generalized?
6421 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6424 int x = INTVAL (operands[1]);
6425 operands[2] = GEN_INT (exact_log2 (x + 1));
6426 return \"depdi -1,%%sar,%2,%0\";
6428 [(set_attr "type" "shift")
6429 (set_attr "length" "4")])
6432 [(set (match_operand:DI 0 "register_operand" "=r")
6433 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6434 (minus:DI (const_int 63)
6435 (match_operand:DI 2 "register_operand" "q")))
6436 (match_operand:DI 3 "register_operand" "0")))]
6437 ; this can be generalized...!
6438 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6441 int x = INTVAL (operands[1]);
6442 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6443 return \"depdi 0,%%sar,%2,%0\";
6445 [(set_attr "type" "shift")
6446 (set_attr "length" "4")])
6448 (define_expand "ashrsi3"
6449 [(set (match_operand:SI 0 "register_operand" "")
6450 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6451 (match_operand:SI 2 "arith32_operand" "")))]
6455 if (GET_CODE (operands[2]) != CONST_INT)
6457 rtx temp = gen_reg_rtx (SImode);
6458 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6459 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6465 [(set (match_operand:SI 0 "register_operand" "=r")
6466 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6467 (match_operand:SI 2 "const_int_operand" "n")))]
6469 "{extrs|extrw,s} %1,%P2,%L2,%0"
6470 [(set_attr "type" "shift")
6471 (set_attr "length" "4")])
6473 (define_insn "vextrs32"
6474 [(set (match_operand:SI 0 "register_operand" "=r")
6475 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6476 (minus:SI (const_int 31)
6477 (match_operand:SI 2 "register_operand" "q"))))]
6479 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6480 [(set_attr "type" "shift")
6481 (set_attr "length" "4")])
6483 (define_expand "ashrdi3"
6484 [(set (match_operand:DI 0 "register_operand" "")
6485 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6486 (match_operand:DI 2 "arith32_operand" "")))]
6490 if (GET_CODE (operands[2]) != CONST_INT)
6492 rtx temp = gen_reg_rtx (DImode);
6493 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6494 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6500 [(set (match_operand:DI 0 "register_operand" "=r")
6501 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6502 (match_operand:DI 2 "const_int_operand" "n")))]
6504 "extrd,s %1,%p2,%Q2,%0"
6505 [(set_attr "type" "shift")
6506 (set_attr "length" "4")])
6508 (define_insn "vextrs64"
6509 [(set (match_operand:DI 0 "register_operand" "=r")
6510 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6511 (minus:DI (const_int 63)
6512 (match_operand:DI 2 "register_operand" "q"))))]
6514 "extrd,s %1,%%sar,64,%0"
6515 [(set_attr "type" "shift")
6516 (set_attr "length" "4")])
6518 (define_insn "lshrsi3"
6519 [(set (match_operand:SI 0 "register_operand" "=r,r")
6520 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6521 (match_operand:SI 2 "arith32_operand" "q,n")))]
6524 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6525 {extru|extrw,u} %1,%P2,%L2,%0"
6526 [(set_attr "type" "shift")
6527 (set_attr "length" "4")])
6529 (define_insn "lshrdi3"
6530 [(set (match_operand:DI 0 "register_operand" "=r,r")
6531 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6532 (match_operand:DI 2 "arith32_operand" "q,n")))]
6535 shrpd %%r0,%1,%%sar,%0
6536 extrd,u %1,%p2,%Q2,%0"
6537 [(set_attr "type" "shift")
6538 (set_attr "length" "4")])
6540 (define_insn "rotrsi3"
6541 [(set (match_operand:SI 0 "register_operand" "=r,r")
6542 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6543 (match_operand:SI 2 "arith32_operand" "q,n")))]
6547 if (GET_CODE (operands[2]) == CONST_INT)
6549 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6550 return \"{shd|shrpw} %1,%1,%2,%0\";
6553 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6555 [(set_attr "type" "shift")
6556 (set_attr "length" "4")])
6558 (define_expand "rotlsi3"
6559 [(set (match_operand:SI 0 "register_operand" "")
6560 (rotate:SI (match_operand:SI 1 "register_operand" "")
6561 (match_operand:SI 2 "arith32_operand" "")))]
6565 if (GET_CODE (operands[2]) != CONST_INT)
6567 rtx temp = gen_reg_rtx (SImode);
6568 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6569 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6572 /* Else expand normally. */
6576 [(set (match_operand:SI 0 "register_operand" "=r")
6577 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6578 (match_operand:SI 2 "const_int_operand" "n")))]
6582 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6583 return \"{shd|shrpw} %1,%1,%2,%0\";
6585 [(set_attr "type" "shift")
6586 (set_attr "length" "4")])
6589 [(set (match_operand:SI 0 "register_operand" "=r")
6590 (match_operator:SI 5 "plus_xor_ior_operator"
6591 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6592 (match_operand:SI 3 "const_int_operand" "n"))
6593 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6594 (match_operand:SI 4 "const_int_operand" "n"))]))]
6595 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6596 "{shd|shrpw} %1,%2,%4,%0"
6597 [(set_attr "type" "shift")
6598 (set_attr "length" "4")])
6601 [(set (match_operand:SI 0 "register_operand" "=r")
6602 (match_operator:SI 5 "plus_xor_ior_operator"
6603 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6604 (match_operand:SI 4 "const_int_operand" "n"))
6605 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6606 (match_operand:SI 3 "const_int_operand" "n"))]))]
6607 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6608 "{shd|shrpw} %1,%2,%4,%0"
6609 [(set_attr "type" "shift")
6610 (set_attr "length" "4")])
6613 [(set (match_operand:SI 0 "register_operand" "=r")
6614 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6615 (match_operand:SI 2 "const_int_operand" ""))
6616 (match_operand:SI 3 "const_int_operand" "")))]
6617 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
6620 int cnt = INTVAL (operands[2]) & 31;
6621 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6622 operands[2] = GEN_INT (31 - cnt);
6623 return \"{zdep|depw,z} %1,%2,%3,%0\";
6625 [(set_attr "type" "shift")
6626 (set_attr "length" "4")])
6628 ;; Unconditional and other jump instructions.
6630 ;; This can only be used in a leaf function, so we do
6631 ;; not need to use the PIC register when generating PIC code.
6632 (define_insn "return"
6636 "hppa_can_use_return_insn_p ()"
6640 return \"bve%* (%%r2)\";
6641 return \"bv%* %%r0(%%r2)\";
6643 [(set_attr "type" "branch")
6644 (set_attr "length" "4")])
6646 ;; Emit a different pattern for functions which have non-trivial
6647 ;; epilogues so as not to confuse jump and reorg.
6648 (define_insn "return_internal"
6656 return \"bve%* (%%r2)\";
6657 return \"bv%* %%r0(%%r2)\";
6659 [(set_attr "type" "branch")
6660 (set_attr "length" "4")])
6662 ;; This is used for eh returns which bypass the return stub.
6663 (define_insn "return_external_pic"
6665 (clobber (reg:SI 1))
6667 "!TARGET_NO_SPACE_REGS
6669 && flag_pic && current_function_calls_eh_return"
6670 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6671 [(set_attr "type" "branch")
6672 (set_attr "length" "12")])
6674 (define_expand "prologue"
6677 "hppa_expand_prologue ();DONE;")
6679 (define_expand "sibcall_epilogue"
6684 hppa_expand_epilogue ();
6688 (define_expand "epilogue"
6693 /* Try to use the trivial return first. Else use the full
6695 if (hppa_can_use_return_insn_p ())
6696 emit_jump_insn (gen_return ());
6701 hppa_expand_epilogue ();
6703 /* EH returns bypass the normal return stub. Thus, we must do an
6704 interspace branch to return from functions that call eh_return.
6705 This is only a problem for returns from shared code on ports
6706 using space registers. */
6707 if (!TARGET_NO_SPACE_REGS
6709 && flag_pic && current_function_calls_eh_return)
6710 x = gen_return_external_pic ();
6712 x = gen_return_internal ();
6719 ; Used by hppa_profile_hook to load the starting address of the current
6720 ; function; operand 1 contains the address of the label in operand 3
6721 (define_insn "load_offset_label_address"
6722 [(set (match_operand:SI 0 "register_operand" "=r")
6723 (plus:SI (match_operand:SI 1 "register_operand" "r")
6724 (minus:SI (match_operand:SI 2 "" "")
6725 (label_ref:SI (match_operand 3 "" "")))))]
6728 [(set_attr "type" "multi")
6729 (set_attr "length" "4")])
6731 ; Output a code label and load its address.
6732 (define_insn "lcla1"
6733 [(set (match_operand:SI 0 "register_operand" "=r")
6734 (label_ref:SI (match_operand 1 "" "")))
6739 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6740 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6741 CODE_LABEL_NUMBER (operands[1]));
6744 [(set_attr "type" "multi")
6745 (set_attr "length" "8")])
6747 (define_insn "lcla2"
6748 [(set (match_operand:SI 0 "register_operand" "=r")
6749 (label_ref:SI (match_operand 1 "" "")))
6754 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6755 CODE_LABEL_NUMBER (operands[1]));
6758 [(set_attr "type" "move")
6759 (set_attr "length" "4")])
6761 (define_insn "blockage"
6762 [(unspec_volatile [(const_int 2)] 0)]
6765 [(set_attr "length" "0")])
6768 [(set (pc) (label_ref (match_operand 0 "" "")))]
6772 /* An unconditional branch which can reach its target. */
6773 if (get_attr_length (insn) != 24
6774 && get_attr_length (insn) != 16)
6777 return output_lbranch (operands[0], insn);
6779 [(set_attr "type" "uncond_branch")
6780 (set_attr "pa_combine_type" "uncond_branch")
6781 (set (attr "length")
6782 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6783 (if_then_else (lt (abs (minus (match_dup 0)
6784 (plus (pc) (const_int 8))))
6788 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6790 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6795 ;;; Hope this is only within a function...
6796 (define_insn "indirect_jump"
6797 [(set (pc) (match_operand 0 "register_operand" "r"))]
6798 "GET_MODE (operands[0]) == word_mode"
6800 [(set_attr "type" "branch")
6801 (set_attr "length" "4")])
6803 ;;; This jump is used in branch tables where the insn length is fixed.
6804 ;;; The length of this insn is adjusted if the delay slot is not filled.
6805 (define_insn "short_jump"
6806 [(set (pc) (label_ref (match_operand 0 "" "")))
6810 [(set_attr "type" "btable_branch")
6811 (set_attr "length" "4")])
6813 ;; Subroutines of "casesi".
6814 ;; operand 0 is index
6815 ;; operand 1 is the minimum bound
6816 ;; operand 2 is the maximum bound - minimum bound + 1
6817 ;; operand 3 is CODE_LABEL for the table;
6818 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6820 (define_expand "casesi"
6821 [(match_operand:SI 0 "general_operand" "")
6822 (match_operand:SI 1 "const_int_operand" "")
6823 (match_operand:SI 2 "const_int_operand" "")
6824 (match_operand 3 "" "")
6825 (match_operand 4 "" "")]
6829 if (GET_CODE (operands[0]) != REG)
6830 operands[0] = force_reg (SImode, operands[0]);
6832 if (operands[1] != const0_rtx)
6834 rtx index = gen_reg_rtx (SImode);
6836 operands[1] = GEN_INT (-INTVAL (operands[1]));
6837 if (!INT_14_BITS (operands[1]))
6838 operands[1] = force_reg (SImode, operands[1]);
6839 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6840 operands[0] = index;
6843 /* In 64bit mode we must make sure to wipe the upper bits of the register
6844 just in case the addition overflowed or we had random bits in the
6845 high part of the register. */
6848 rtx index = gen_reg_rtx (DImode);
6850 emit_insn (gen_extendsidi2 (index, operands[0]));
6851 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
6854 if (!INT_5_BITS (operands[2]))
6855 operands[2] = force_reg (SImode, operands[2]);
6857 /* This branch prevents us finding an insn for the delay slot of the
6858 following vectored branch. It might be possible to use the delay
6859 slot if an index value of -1 was used to transfer to the out-of-range
6860 label. In order to do this, we would have to output the -1 vector
6861 element after the delay insn. The casesi output code would have to
6862 check if the casesi insn is in a delay branch sequence and output
6863 the delay insn if one is found. If this was done, then it might
6864 then be worthwhile to split the casesi patterns to improve scheduling.
6865 However, it's not clear that all this extra complexity is worth
6867 emit_insn (gen_cmpsi (operands[0], operands[2]));
6868 emit_jump_insn (gen_bgtu (operands[4]));
6870 if (TARGET_BIG_SWITCH)
6874 rtx tmp1 = gen_reg_rtx (DImode);
6875 rtx tmp2 = gen_reg_rtx (DImode);
6877 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
6882 rtx tmp1 = gen_reg_rtx (SImode);
6886 rtx tmp2 = gen_reg_rtx (SImode);
6888 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
6892 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
6896 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6900 ;;; The rtl for this pattern doesn't accurately describe what the insn
6901 ;;; actually does, particularly when case-vector elements are exploded
6902 ;;; in pa_reorg. However, the initial SET in these patterns must show
6903 ;;; the connection of the insn to the following jump table.
6904 (define_insn "casesi0"
6905 [(set (pc) (mem:SI (plus:SI
6906 (mult:SI (match_operand:SI 0 "register_operand" "r")
6908 (label_ref (match_operand 1 "" "")))))]
6910 "blr,n %0,%%r0\;nop"
6911 [(set_attr "type" "multi")
6912 (set_attr "length" "8")])
6914 ;;; 32-bit code, absolute branch table.
6915 (define_insn "casesi32"
6916 [(set (pc) (mem:SI (plus:SI
6917 (mult:SI (match_operand:SI 0 "register_operand" "r")
6919 (label_ref (match_operand 1 "" "")))))
6920 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
6921 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6922 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6923 [(set_attr "type" "multi")
6924 (set_attr "length" "16")])
6926 ;;; 32-bit code, relative branch table.
6927 (define_insn "casesi32p"
6928 [(set (pc) (mem:SI (plus:SI
6929 (mult:SI (match_operand:SI 0 "register_operand" "r")
6931 (label_ref (match_operand 1 "" "")))))
6932 (clobber (match_operand:SI 2 "register_operand" "=&a"))
6933 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
6934 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6935 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
6936 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
6937 [(set_attr "type" "multi")
6938 (set (attr "length")
6939 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
6943 ;;; 64-bit code, 32-bit relative branch table.
6944 (define_insn "casesi64p"
6945 [(set (pc) (mem:DI (plus:DI
6946 (mult:DI (sign_extend:DI
6947 (match_operand:SI 0 "register_operand" "r"))
6949 (label_ref (match_operand 1 "" "")))))
6950 (clobber (match_operand:DI 2 "register_operand" "=&r"))
6951 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
6952 "TARGET_64BIT && TARGET_BIG_SWITCH"
6953 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
6954 add,l %2,%3,%3\;bv,n %%r0(%3)"
6955 [(set_attr "type" "multi")
6956 (set_attr "length" "24")])
6960 ;;- jump to subroutine
6962 (define_expand "call"
6963 [(parallel [(call (match_operand:SI 0 "" "")
6964 (match_operand 1 "" ""))
6965 (clobber (reg:SI 2))])]
6970 rtx nb = operands[1];
6972 if (TARGET_PORTABLE_RUNTIME)
6973 op = force_reg (SImode, XEXP (operands[0], 0));
6975 op = XEXP (operands[0], 0);
6979 if (!virtuals_instantiated)
6980 emit_move_insn (arg_pointer_rtx,
6981 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6985 /* The loop pass can generate new libcalls after the virtual
6986 registers are instantiated when fpregs are disabled because
6987 the only method that we have for doing DImode multiplication
6988 is with a libcall. This could be trouble if we haven't
6989 allocated enough space for the outgoing arguments. */
6990 if (INTVAL (nb) > current_function_outgoing_args_size)
6993 emit_move_insn (arg_pointer_rtx,
6994 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6995 GEN_INT (STACK_POINTER_OFFSET + 64)));
6999 /* Use two different patterns for calls to explicitly named functions
7000 and calls through function pointers. This is necessary as these two
7001 types of calls use different calling conventions, and CSE might try
7002 to change the named call into an indirect call in some cases (using
7003 two patterns keeps CSE from performing this optimization).
7005 We now use even more call patterns as there was a subtle bug in
7006 attempting to restore the pic register after a call using a simple
7007 move insn. During reload, a instruction involving a pseudo register
7008 with no explicit dependence on the PIC register can be converted
7009 to an equivalent load from memory using the PIC register. If we
7010 emit a simple move to restore the PIC register in the initial rtl
7011 generation, then it can potentially be repositioned during scheduling.
7012 and an instruction that eventually uses the PIC register may end up
7013 between the call and the PIC register restore.
7015 This only worked because there is a post call group of instructions
7016 that are scheduled with the call. These instructions are included
7017 in the same basic block as the call. However, calls can throw in
7018 C++ code and a basic block has to terminate at the call if the call
7019 can throw. This results in the PIC register restore being scheduled
7020 independently from the call. So, we now hide the save and restore
7021 of the PIC register in the call pattern until after reload. Then,
7022 we split the moves out. A small side benefit is that we now don't
7023 need to have a use of the PIC register in the return pattern and
7024 the final save/restore operation is not needed.
7026 I elected to just clobber %r4 in the PIC patterns and use it instead
7027 of trying to force hppa_pic_save_rtx () to a callee saved register.
7028 This might have required a new register class and constraint. It
7029 was also simpler to just handle the restore from a register than a
7033 if (GET_CODE (op) == SYMBOL_REF)
7034 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7037 op = force_reg (word_mode, op);
7038 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7043 if (GET_CODE (op) == SYMBOL_REF)
7046 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7048 call_insn = emit_call_insn (gen_call_symref (op, nb));
7052 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7054 emit_move_insn (tmpreg, force_reg (word_mode, op));
7056 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7058 call_insn = emit_call_insn (gen_call_reg (nb));
7065 ;; We use function calls to set the attribute length of calls and millicode
7066 ;; calls. This is necessary because of the large variety of call sequences.
7067 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7068 ;; we need the same calculation in several places, maintenance becomes a
7071 ;; However, this has a subtle impact on branch shortening. When the
7072 ;; expression used to set the length attribute of an instruction depends
7073 ;; on a relative address (e.g., pc or a branch address), genattrtab
7074 ;; notes that the insn's length is variable, and attempts to determine a
7075 ;; worst-case default length and code to compute an insn's current length.
7077 ;; The use of a function call hides the variable dependence of our calls
7078 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7079 ;; as variable and it only generates code for the default case using our
7080 ;; function call. Because of this, calls and millicode calls have a fixed
7081 ;; length in the branch shortening pass, and some branches will use a longer
7082 ;; code sequence than necessary. However, the length of any given call
7083 ;; will still reflect its final code location and it may be shorter than
7084 ;; the initial length estimate.
7086 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7087 ;; in the set. However, when genattrtab hits a function call in its attempt
7088 ;; to compute the default length, it marks the result as unknown and sets
7089 ;; the default result to MAX_INT ;-( One possible fix that would allow
7090 ;; calls to participate in branch shortening would be to make the call to
7091 ;; insn_default_length a target option. Then, we could massage unknown
7092 ;; results. Another fix might be to change genattrtab so that it just does
7093 ;; the call in the variable case as it already does for the fixed case.
7095 (define_insn "call_symref"
7096 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7097 (match_operand 1 "" "i"))
7098 (clobber (reg:SI 1))
7099 (clobber (reg:SI 2))
7100 (use (const_int 0))]
7101 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7104 output_arg_descriptor (insn);
7105 return output_call (insn, operands[0], 0);
7107 [(set_attr "type" "call")
7108 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7110 (define_insn "call_symref_pic"
7111 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7112 (match_operand 1 "" "i"))
7113 (clobber (reg:SI 1))
7114 (clobber (reg:SI 2))
7115 (clobber (reg:SI 4))
7117 (use (const_int 0))]
7118 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7121 output_arg_descriptor (insn);
7122 return output_call (insn, operands[0], 0);
7124 [(set_attr "type" "call")
7125 (set (attr "length")
7126 (plus (symbol_ref "attr_length_call (insn, 0)")
7127 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7129 ;; Split out the PIC register save and restore after reload. This is
7130 ;; done only if the function returns. As the split is done after reload,
7131 ;; there are some situations in which we unnecessarily save and restore
7132 ;; %r4. This happens when there is a single call and the PIC register
7133 ;; is "dead" after the call. This isn't easy to fix as the usage of
7134 ;; the PIC register isn't completely determined until the reload pass.
7136 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7137 (match_operand 1 "" ""))
7138 (clobber (reg:SI 1))
7139 (clobber (reg:SI 2))
7140 (clobber (reg:SI 4))
7142 (use (const_int 0))])]
7143 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7145 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7146 [(set (reg:SI 4) (reg:SI 19))
7147 (parallel [(call (mem:SI (match_dup 0))
7149 (clobber (reg:SI 1))
7150 (clobber (reg:SI 2))
7152 (use (const_int 0))])
7153 (set (reg:SI 19) (reg:SI 4))]
7156 ;; Remove the clobber of register 4 when optimizing. This has to be
7157 ;; done with a peephole optimization rather than a split because the
7158 ;; split sequence for a call must be longer than one instruction.
7160 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7161 (match_operand 1 "" ""))
7162 (clobber (reg:SI 1))
7163 (clobber (reg:SI 2))
7164 (clobber (reg:SI 4))
7166 (use (const_int 0))])]
7167 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7168 [(parallel [(call (mem:SI (match_dup 0))
7170 (clobber (reg:SI 1))
7171 (clobber (reg:SI 2))
7173 (use (const_int 0))])]
7176 (define_insn "*call_symref_pic_post_reload"
7177 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7178 (match_operand 1 "" "i"))
7179 (clobber (reg:SI 1))
7180 (clobber (reg:SI 2))
7182 (use (const_int 0))]
7183 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7186 output_arg_descriptor (insn);
7187 return output_call (insn, operands[0], 0);
7189 [(set_attr "type" "call")
7190 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7192 ;; This pattern is split if it is necessary to save and restore the
7194 (define_insn "call_symref_64bit"
7195 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7196 (match_operand 1 "" "i"))
7197 (clobber (reg:DI 1))
7198 (clobber (reg:DI 2))
7199 (clobber (reg:DI 4))
7202 (use (const_int 0))]
7206 output_arg_descriptor (insn);
7207 return output_call (insn, operands[0], 0);
7209 [(set_attr "type" "call")
7210 (set (attr "length")
7211 (plus (symbol_ref "attr_length_call (insn, 0)")
7212 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7214 ;; Split out the PIC register save and restore after reload. This is
7215 ;; done only if the function returns. As the split is done after reload,
7216 ;; there are some situations in which we unnecessarily save and restore
7217 ;; %r4. This happens when there is a single call and the PIC register
7218 ;; is "dead" after the call. This isn't easy to fix as the usage of
7219 ;; the PIC register isn't completely determined until the reload pass.
7221 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7222 (match_operand 1 "" ""))
7223 (clobber (reg:DI 1))
7224 (clobber (reg:DI 2))
7225 (clobber (reg:DI 4))
7228 (use (const_int 0))])]
7231 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7232 [(set (reg:DI 4) (reg:DI 27))
7233 (parallel [(call (mem:SI (match_dup 0))
7235 (clobber (reg:DI 1))
7236 (clobber (reg:DI 2))
7239 (use (const_int 0))])
7240 (set (reg:DI 27) (reg:DI 4))]
7243 ;; Remove the clobber of register 4 when optimizing. This has to be
7244 ;; done with a peephole optimization rather than a split because the
7245 ;; split sequence for a call must be longer than one instruction.
7247 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7248 (match_operand 1 "" ""))
7249 (clobber (reg:DI 1))
7250 (clobber (reg:DI 2))
7251 (clobber (reg:DI 4))
7254 (use (const_int 0))])]
7255 "TARGET_64BIT && reload_completed"
7256 [(parallel [(call (mem:SI (match_dup 0))
7258 (clobber (reg:DI 1))
7259 (clobber (reg:DI 2))
7262 (use (const_int 0))])]
7265 (define_insn "*call_symref_64bit_post_reload"
7266 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7267 (match_operand 1 "" "i"))
7268 (clobber (reg:DI 1))
7269 (clobber (reg:DI 2))
7272 (use (const_int 0))]
7276 output_arg_descriptor (insn);
7277 return output_call (insn, operands[0], 0);
7279 [(set_attr "type" "call")
7280 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7282 (define_insn "call_reg"
7283 [(call (mem:SI (reg:SI 22))
7284 (match_operand 0 "" "i"))
7285 (clobber (reg:SI 1))
7286 (clobber (reg:SI 2))
7287 (use (const_int 1))]
7291 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7293 [(set_attr "type" "dyncall")
7294 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7296 ;; This pattern is split if it is necessary to save and restore the
7298 (define_insn "call_reg_pic"
7299 [(call (mem:SI (reg:SI 22))
7300 (match_operand 0 "" "i"))
7301 (clobber (reg:SI 1))
7302 (clobber (reg:SI 2))
7303 (clobber (reg:SI 4))
7305 (use (const_int 1))]
7309 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7311 [(set_attr "type" "dyncall")
7312 (set (attr "length")
7313 (plus (symbol_ref "attr_length_indirect_call (insn)")
7314 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7316 ;; Split out the PIC register save and restore after reload. This is
7317 ;; done only if the function returns. As the split is done after reload,
7318 ;; there are some situations in which we unnecessarily save and restore
7319 ;; %r4. This happens when there is a single call and the PIC register
7320 ;; is "dead" after the call. This isn't easy to fix as the usage of
7321 ;; the PIC register isn't completely determined until the reload pass.
7323 [(parallel [(call (mem:SI (reg:SI 22))
7324 (match_operand 0 "" ""))
7325 (clobber (reg:SI 1))
7326 (clobber (reg:SI 2))
7327 (clobber (reg:SI 4))
7329 (use (const_int 1))])]
7332 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7333 [(set (reg:SI 4) (reg:SI 19))
7334 (parallel [(call (mem:SI (reg:SI 22))
7336 (clobber (reg:SI 1))
7337 (clobber (reg:SI 2))
7339 (use (const_int 1))])
7340 (set (reg:SI 19) (reg:SI 4))]
7343 ;; Remove the clobber of register 4 when optimizing. This has to be
7344 ;; done with a peephole optimization rather than a split because the
7345 ;; split sequence for a call must be longer than one instruction.
7347 [(parallel [(call (mem:SI (reg:SI 22))
7348 (match_operand 0 "" ""))
7349 (clobber (reg:SI 1))
7350 (clobber (reg:SI 2))
7351 (clobber (reg:SI 4))
7353 (use (const_int 1))])]
7354 "!TARGET_64BIT && reload_completed"
7355 [(parallel [(call (mem:SI (reg:SI 22))
7357 (clobber (reg:SI 1))
7358 (clobber (reg:SI 2))
7360 (use (const_int 1))])]
7363 (define_insn "*call_reg_pic_post_reload"
7364 [(call (mem:SI (reg:SI 22))
7365 (match_operand 0 "" "i"))
7366 (clobber (reg:SI 1))
7367 (clobber (reg:SI 2))
7369 (use (const_int 1))]
7373 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7375 [(set_attr "type" "dyncall")
7376 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7378 ;; This pattern is split if it is necessary to save and restore the
7380 (define_insn "call_reg_64bit"
7381 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7382 (match_operand 1 "" "i"))
7383 (clobber (reg:DI 2))
7384 (clobber (reg:DI 4))
7387 (use (const_int 1))]
7391 return output_indirect_call (insn, operands[0]);
7393 [(set_attr "type" "dyncall")
7394 (set (attr "length")
7395 (plus (symbol_ref "attr_length_indirect_call (insn)")
7396 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7398 ;; Split out the PIC register save and restore after reload. This is
7399 ;; done only if the function returns. As the split is done after reload,
7400 ;; there are some situations in which we unnecessarily save and restore
7401 ;; %r4. This happens when there is a single call and the PIC register
7402 ;; is "dead" after the call. This isn't easy to fix as the usage of
7403 ;; the PIC register isn't completely determined until the reload pass.
7405 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7406 (match_operand 1 "" ""))
7407 (clobber (reg:DI 2))
7408 (clobber (reg:DI 4))
7411 (use (const_int 1))])]
7414 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7415 [(set (reg:DI 4) (reg:DI 27))
7416 (parallel [(call (mem:SI (match_dup 0))
7418 (clobber (reg:DI 2))
7421 (use (const_int 1))])
7422 (set (reg:DI 27) (reg:DI 4))]
7425 ;; Remove the clobber of register 4 when optimizing. This has to be
7426 ;; done with a peephole optimization rather than a split because the
7427 ;; split sequence for a call must be longer than one instruction.
7429 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7430 (match_operand 1 "" ""))
7431 (clobber (reg:DI 2))
7432 (clobber (reg:DI 4))
7435 (use (const_int 1))])]
7436 "TARGET_64BIT && reload_completed"
7437 [(parallel [(call (mem:SI (match_dup 0))
7439 (clobber (reg:DI 2))
7442 (use (const_int 1))])]
7445 (define_insn "*call_reg_64bit_post_reload"
7446 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7447 (match_operand 1 "" "i"))
7448 (clobber (reg:DI 2))
7451 (use (const_int 1))]
7455 return output_indirect_call (insn, operands[0]);
7457 [(set_attr "type" "dyncall")
7458 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7460 (define_expand "call_value"
7461 [(parallel [(set (match_operand 0 "" "")
7462 (call (match_operand:SI 1 "" "")
7463 (match_operand 2 "" "")))
7464 (clobber (reg:SI 2))])]
7469 rtx dst = operands[0];
7470 rtx nb = operands[2];
7472 if (TARGET_PORTABLE_RUNTIME)
7473 op = force_reg (SImode, XEXP (operands[1], 0));
7475 op = XEXP (operands[1], 0);
7479 if (!virtuals_instantiated)
7480 emit_move_insn (arg_pointer_rtx,
7481 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7485 /* The loop pass can generate new libcalls after the virtual
7486 registers are instantiated when fpregs are disabled because
7487 the only method that we have for doing DImode multiplication
7488 is with a libcall. This could be trouble if we haven't
7489 allocated enough space for the outgoing arguments. */
7490 if (INTVAL (nb) > current_function_outgoing_args_size)
7493 emit_move_insn (arg_pointer_rtx,
7494 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7495 GEN_INT (STACK_POINTER_OFFSET + 64)));
7499 /* Use two different patterns for calls to explicitly named functions
7500 and calls through function pointers. This is necessary as these two
7501 types of calls use different calling conventions, and CSE might try
7502 to change the named call into an indirect call in some cases (using
7503 two patterns keeps CSE from performing this optimization).
7505 We now use even more call patterns as there was a subtle bug in
7506 attempting to restore the pic register after a call using a simple
7507 move insn. During reload, a instruction involving a pseudo register
7508 with no explicit dependence on the PIC register can be converted
7509 to an equivalent load from memory using the PIC register. If we
7510 emit a simple move to restore the PIC register in the initial rtl
7511 generation, then it can potentially be repositioned during scheduling.
7512 and an instruction that eventually uses the PIC register may end up
7513 between the call and the PIC register restore.
7515 This only worked because there is a post call group of instructions
7516 that are scheduled with the call. These instructions are included
7517 in the same basic block as the call. However, calls can throw in
7518 C++ code and a basic block has to terminate at the call if the call
7519 can throw. This results in the PIC register restore being scheduled
7520 independently from the call. So, we now hide the save and restore
7521 of the PIC register in the call pattern until after reload. Then,
7522 we split the moves out. A small side benefit is that we now don't
7523 need to have a use of the PIC register in the return pattern and
7524 the final save/restore operation is not needed.
7526 I elected to just clobber %r4 in the PIC patterns and use it instead
7527 of trying to force hppa_pic_save_rtx () to a callee saved register.
7528 This might have required a new register class and constraint. It
7529 was also simpler to just handle the restore from a register than a
7533 if (GET_CODE (op) == SYMBOL_REF)
7534 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
7537 op = force_reg (word_mode, op);
7538 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
7543 if (GET_CODE (op) == SYMBOL_REF)
7546 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
7548 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7552 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7554 emit_move_insn (tmpreg, force_reg (word_mode, op));
7556 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
7558 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7565 (define_insn "call_val_symref"
7566 [(set (match_operand 0 "" "")
7567 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7568 (match_operand 2 "" "i")))
7569 (clobber (reg:SI 1))
7570 (clobber (reg:SI 2))
7571 (use (const_int 0))]
7572 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7575 output_arg_descriptor (insn);
7576 return output_call (insn, operands[1], 0);
7578 [(set_attr "type" "call")
7579 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7581 (define_insn "call_val_symref_pic"
7582 [(set (match_operand 0 "" "")
7583 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7584 (match_operand 2 "" "i")))
7585 (clobber (reg:SI 1))
7586 (clobber (reg:SI 2))
7587 (clobber (reg:SI 4))
7589 (use (const_int 0))]
7590 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7593 output_arg_descriptor (insn);
7594 return output_call (insn, operands[1], 0);
7596 [(set_attr "type" "call")
7597 (set (attr "length")
7598 (plus (symbol_ref "attr_length_call (insn, 0)")
7599 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7601 ;; Split out the PIC register save and restore after reload. This is
7602 ;; done only if the function returns. As the split is done after reload,
7603 ;; there are some situations in which we unnecessarily save and restore
7604 ;; %r4. This happens when there is a single call and the PIC register
7605 ;; is "dead" after the call. This isn't easy to fix as the usage of
7606 ;; the PIC register isn't completely determined until the reload pass.
7608 [(parallel [(set (match_operand 0 "" "")
7609 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7610 (match_operand 2 "" "")))
7611 (clobber (reg:SI 1))
7612 (clobber (reg:SI 2))
7613 (clobber (reg:SI 4))
7615 (use (const_int 0))])]
7616 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7618 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7619 [(set (reg:SI 4) (reg:SI 19))
7620 (parallel [(set (match_dup 0)
7621 (call (mem:SI (match_dup 1))
7623 (clobber (reg:SI 1))
7624 (clobber (reg:SI 2))
7626 (use (const_int 0))])
7627 (set (reg:SI 19) (reg:SI 4))]
7630 ;; Remove the clobber of register 4 when optimizing. This has to be
7631 ;; done with a peephole optimization rather than a split because the
7632 ;; split sequence for a call must be longer than one instruction.
7634 [(parallel [(set (match_operand 0 "" "")
7635 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7636 (match_operand 2 "" "")))
7637 (clobber (reg:SI 1))
7638 (clobber (reg:SI 2))
7639 (clobber (reg:SI 4))
7641 (use (const_int 0))])]
7642 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7643 [(parallel [(set (match_dup 0)
7644 (call (mem:SI (match_dup 1))
7646 (clobber (reg:SI 1))
7647 (clobber (reg:SI 2))
7649 (use (const_int 0))])]
7652 (define_insn "*call_val_symref_pic_post_reload"
7653 [(set (match_operand 0 "" "")
7654 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7655 (match_operand 2 "" "i")))
7656 (clobber (reg:SI 1))
7657 (clobber (reg:SI 2))
7659 (use (const_int 0))]
7660 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7663 output_arg_descriptor (insn);
7664 return output_call (insn, operands[1], 0);
7666 [(set_attr "type" "call")
7667 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7669 ;; This pattern is split if it is necessary to save and restore the
7671 (define_insn "call_val_symref_64bit"
7672 [(set (match_operand 0 "" "")
7673 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7674 (match_operand 2 "" "i")))
7675 (clobber (reg:DI 1))
7676 (clobber (reg:DI 2))
7677 (clobber (reg:DI 4))
7680 (use (const_int 0))]
7684 output_arg_descriptor (insn);
7685 return output_call (insn, operands[1], 0);
7687 [(set_attr "type" "call")
7688 (set (attr "length")
7689 (plus (symbol_ref "attr_length_call (insn, 0)")
7690 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7692 ;; Split out the PIC register save and restore after reload. This is
7693 ;; done only if the function returns. As the split is done after reload,
7694 ;; there are some situations in which we unnecessarily save and restore
7695 ;; %r4. This happens when there is a single call and the PIC register
7696 ;; is "dead" after the call. This isn't easy to fix as the usage of
7697 ;; the PIC register isn't completely determined until the reload pass.
7699 [(parallel [(set (match_operand 0 "" "")
7700 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7701 (match_operand 2 "" "")))
7702 (clobber (reg:DI 1))
7703 (clobber (reg:DI 2))
7704 (clobber (reg:DI 4))
7707 (use (const_int 0))])]
7710 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7711 [(set (reg:DI 4) (reg:DI 27))
7712 (parallel [(set (match_dup 0)
7713 (call (mem:SI (match_dup 1))
7715 (clobber (reg:DI 1))
7716 (clobber (reg:DI 2))
7719 (use (const_int 0))])
7720 (set (reg:DI 27) (reg:DI 4))]
7723 ;; Remove the clobber of register 4 when optimizing. This has to be
7724 ;; done with a peephole optimization rather than a split because the
7725 ;; split sequence for a call must be longer than one instruction.
7727 [(parallel [(set (match_operand 0 "" "")
7728 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7729 (match_operand 2 "" "")))
7730 (clobber (reg:DI 1))
7731 (clobber (reg:DI 2))
7732 (clobber (reg:DI 4))
7735 (use (const_int 0))])]
7736 "TARGET_64BIT && reload_completed"
7737 [(parallel [(set (match_dup 0)
7738 (call (mem:SI (match_dup 1))
7740 (clobber (reg:DI 1))
7741 (clobber (reg:DI 2))
7744 (use (const_int 0))])]
7747 (define_insn "*call_val_symref_64bit_post_reload"
7748 [(set (match_operand 0 "" "")
7749 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7750 (match_operand 2 "" "i")))
7751 (clobber (reg:DI 1))
7752 (clobber (reg:DI 2))
7755 (use (const_int 0))]
7759 output_arg_descriptor (insn);
7760 return output_call (insn, operands[1], 0);
7762 [(set_attr "type" "call")
7763 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7765 (define_insn "call_val_reg"
7766 [(set (match_operand 0 "" "")
7767 (call (mem:SI (reg:SI 22))
7768 (match_operand 1 "" "i")))
7769 (clobber (reg:SI 1))
7770 (clobber (reg:SI 2))
7771 (use (const_int 1))]
7775 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7777 [(set_attr "type" "dyncall")
7778 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7780 ;; This pattern is split if it is necessary to save and restore the
7782 (define_insn "call_val_reg_pic"
7783 [(set (match_operand 0 "" "")
7784 (call (mem:SI (reg:SI 22))
7785 (match_operand 1 "" "i")))
7786 (clobber (reg:SI 1))
7787 (clobber (reg:SI 2))
7788 (clobber (reg:SI 4))
7790 (use (const_int 1))]
7794 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7796 [(set_attr "type" "dyncall")
7797 (set (attr "length")
7798 (plus (symbol_ref "attr_length_indirect_call (insn)")
7799 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7801 ;; Split out the PIC register save and restore after reload. This is
7802 ;; done only if the function returns. As the split is done after reload,
7803 ;; there are some situations in which we unnecessarily save and restore
7804 ;; %r4. This happens when there is a single call and the PIC register
7805 ;; is "dead" after the call. This isn't easy to fix as the usage of
7806 ;; the PIC register isn't completely determined until the reload pass.
7808 [(parallel [(set (match_operand 0 "" "")
7809 (call (mem:SI (reg:SI 22))
7810 (match_operand 1 "" "")))
7811 (clobber (reg:SI 1))
7812 (clobber (reg:SI 2))
7813 (clobber (reg:SI 4))
7815 (use (const_int 1))])]
7818 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7819 [(set (reg:SI 4) (reg:SI 19))
7820 (parallel [(set (match_dup 0)
7821 (call (mem:SI (reg:SI 22))
7823 (clobber (reg:SI 1))
7824 (clobber (reg:SI 2))
7826 (use (const_int 1))])
7827 (set (reg:SI 19) (reg:SI 4))]
7830 ;; Remove the clobber of register 4 when optimizing. This has to be
7831 ;; done with a peephole optimization rather than a split because the
7832 ;; split sequence for a call must be longer than one instruction.
7834 [(parallel [(set (match_operand 0 "" "")
7835 (call (mem:SI (reg:SI 22))
7836 (match_operand 1 "" "")))
7837 (clobber (reg:SI 1))
7838 (clobber (reg:SI 2))
7839 (clobber (reg:SI 4))
7841 (use (const_int 1))])]
7842 "!TARGET_64BIT && reload_completed"
7843 [(parallel [(set (match_dup 0)
7844 (call (mem:SI (reg:SI 22))
7846 (clobber (reg:SI 1))
7847 (clobber (reg:SI 2))
7849 (use (const_int 1))])]
7852 (define_insn "*call_val_reg_pic_post_reload"
7853 [(set (match_operand 0 "" "")
7854 (call (mem:SI (reg:SI 22))
7855 (match_operand 1 "" "i")))
7856 (clobber (reg:SI 1))
7857 (clobber (reg:SI 2))
7859 (use (const_int 1))]
7863 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7865 [(set_attr "type" "dyncall")
7866 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7868 ;; This pattern is split if it is necessary to save and restore the
7870 (define_insn "call_val_reg_64bit"
7871 [(set (match_operand 0 "" "")
7872 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7873 (match_operand 2 "" "i")))
7874 (clobber (reg:DI 2))
7875 (clobber (reg:DI 4))
7878 (use (const_int 1))]
7882 return output_indirect_call (insn, operands[1]);
7884 [(set_attr "type" "dyncall")
7885 (set (attr "length")
7886 (plus (symbol_ref "attr_length_indirect_call (insn)")
7887 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7889 ;; Split out the PIC register save and restore after reload. This is
7890 ;; done only if the function returns. As the split is done after reload,
7891 ;; there are some situations in which we unnecessarily save and restore
7892 ;; %r4. This happens when there is a single call and the PIC register
7893 ;; is "dead" after the call. This isn't easy to fix as the usage of
7894 ;; the PIC register isn't completely determined until the reload pass.
7896 [(parallel [(set (match_operand 0 "" "")
7897 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7898 (match_operand 2 "" "")))
7899 (clobber (reg:DI 2))
7900 (clobber (reg:DI 4))
7903 (use (const_int 1))])]
7906 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7907 [(set (reg:DI 4) (reg:DI 27))
7908 (parallel [(set (match_dup 0)
7909 (call (mem:SI (match_dup 1))
7911 (clobber (reg:DI 2))
7914 (use (const_int 1))])
7915 (set (reg:DI 27) (reg:DI 4))]
7918 ;; Remove the clobber of register 4 when optimizing. This has to be
7919 ;; done with a peephole optimization rather than a split because the
7920 ;; split sequence for a call must be longer than one instruction.
7922 [(parallel [(set (match_operand 0 "" "")
7923 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7924 (match_operand 2 "" "")))
7925 (clobber (reg:DI 2))
7926 (clobber (reg:DI 4))
7929 (use (const_int 1))])]
7930 "TARGET_64BIT && reload_completed"
7931 [(parallel [(set (match_dup 0)
7932 (call (mem:SI (match_dup 1))
7934 (clobber (reg:DI 2))
7937 (use (const_int 1))])]
7940 (define_insn "*call_val_reg_64bit_post_reload"
7941 [(set (match_operand 0 "" "")
7942 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7943 (match_operand 2 "" "i")))
7944 (clobber (reg:DI 2))
7947 (use (const_int 1))]
7951 return output_indirect_call (insn, operands[1]);
7953 [(set_attr "type" "dyncall")
7954 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7956 ;; Call subroutine returning any type.
7958 (define_expand "untyped_call"
7959 [(parallel [(call (match_operand 0 "" "")
7961 (match_operand 1 "" "")
7962 (match_operand 2 "" "")])]
7968 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7970 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7972 rtx set = XVECEXP (operands[2], 0, i);
7973 emit_move_insn (SET_DEST (set), SET_SRC (set));
7976 /* The optimizer does not know that the call sets the function value
7977 registers we stored in the result block. We avoid problems by
7978 claiming that all hard registers are used and clobbered at this
7980 emit_insn (gen_blockage ());
7985 (define_expand "sibcall"
7986 [(call (match_operand:SI 0 "" "")
7987 (match_operand 1 "" ""))]
7988 "!TARGET_PORTABLE_RUNTIME"
7992 rtx nb = operands[1];
7994 op = XEXP (operands[0], 0);
7998 if (!virtuals_instantiated)
7999 emit_move_insn (arg_pointer_rtx,
8000 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8004 /* The loop pass can generate new libcalls after the virtual
8005 registers are instantiated when fpregs are disabled because
8006 the only method that we have for doing DImode multiplication
8007 is with a libcall. This could be trouble if we haven't
8008 allocated enough space for the outgoing arguments. */
8009 if (INTVAL (nb) > current_function_outgoing_args_size)
8012 emit_move_insn (arg_pointer_rtx,
8013 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8014 GEN_INT (STACK_POINTER_OFFSET + 64)));
8018 /* Indirect sibling calls are not allowed. */
8020 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8022 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8024 call_insn = emit_call_insn (call_insn);
8027 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8029 /* We don't have to restore the PIC register. */
8031 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8036 (define_insn "sibcall_internal_symref"
8037 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8038 (match_operand 1 "" "i"))
8039 (clobber (reg:SI 1))
8041 (use (const_int 0))]
8042 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8045 output_arg_descriptor (insn);
8046 return output_call (insn, operands[0], 1);
8048 [(set_attr "type" "call")
8049 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8051 (define_insn "sibcall_internal_symref_64bit"
8052 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8053 (match_operand 1 "" "i"))
8054 (clobber (reg:DI 1))
8056 (use (const_int 0))]
8060 output_arg_descriptor (insn);
8061 return output_call (insn, operands[0], 1);
8063 [(set_attr "type" "call")
8064 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8066 (define_expand "sibcall_value"
8067 [(set (match_operand 0 "" "")
8068 (call (match_operand:SI 1 "" "")
8069 (match_operand 2 "" "")))]
8070 "!TARGET_PORTABLE_RUNTIME"
8074 rtx nb = operands[1];
8076 op = XEXP (operands[1], 0);
8080 if (!virtuals_instantiated)
8081 emit_move_insn (arg_pointer_rtx,
8082 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8086 /* The loop pass can generate new libcalls after the virtual
8087 registers are instantiated when fpregs are disabled because
8088 the only method that we have for doing DImode multiplication
8089 is with a libcall. This could be trouble if we haven't
8090 allocated enough space for the outgoing arguments. */
8091 if (INTVAL (nb) > current_function_outgoing_args_size)
8094 emit_move_insn (arg_pointer_rtx,
8095 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8096 GEN_INT (STACK_POINTER_OFFSET + 64)));
8100 /* Indirect sibling calls are not allowed. */
8103 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8106 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8108 call_insn = emit_call_insn (call_insn);
8111 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8113 /* We don't have to restore the PIC register. */
8115 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8120 (define_insn "sibcall_value_internal_symref"
8121 [(set (match_operand 0 "" "")
8122 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8123 (match_operand 2 "" "i")))
8124 (clobber (reg:SI 1))
8126 (use (const_int 0))]
8127 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8130 output_arg_descriptor (insn);
8131 return output_call (insn, operands[1], 1);
8133 [(set_attr "type" "call")
8134 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8136 (define_insn "sibcall_value_internal_symref_64bit"
8137 [(set (match_operand 0 "" "")
8138 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8139 (match_operand 2 "" "i")))
8140 (clobber (reg:DI 1))
8142 (use (const_int 0))]
8146 output_arg_descriptor (insn);
8147 return output_call (insn, operands[1], 1);
8149 [(set_attr "type" "call")
8150 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8156 [(set_attr "type" "move")
8157 (set_attr "length" "4")])
8159 ;; These are just placeholders so we know where branch tables
8161 (define_insn "begin_brtab"
8166 /* Only GAS actually supports this pseudo-op. */
8168 return \".begin_brtab\";
8172 [(set_attr "type" "move")
8173 (set_attr "length" "0")])
8175 (define_insn "end_brtab"
8180 /* Only GAS actually supports this pseudo-op. */
8182 return \".end_brtab\";
8186 [(set_attr "type" "move")
8187 (set_attr "length" "0")])
8189 ;;; EH does longjmp's from and within the data section. Thus,
8190 ;;; an interspace branch is required for the longjmp implementation.
8191 ;;; Registers r1 and r2 are used as scratch registers for the jump
8193 (define_expand "interspace_jump"
8195 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8196 (clobber (match_dup 1))])]
8200 operands[1] = gen_rtx_REG (word_mode, 2);
8204 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8205 (clobber (reg:SI 2))]
8206 "TARGET_PA_20 && !TARGET_64BIT"
8208 [(set_attr "type" "branch")
8209 (set_attr "length" "4")])
8212 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8213 (clobber (reg:SI 2))]
8214 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8216 [(set_attr "type" "branch")
8217 (set_attr "length" "4")])
8220 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8221 (clobber (reg:SI 2))]
8223 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
8224 [(set_attr "type" "branch")
8225 (set_attr "length" "12")])
8228 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8229 (clobber (reg:DI 2))]
8232 [(set_attr "type" "branch")
8233 (set_attr "length" "4")])
8235 (define_expand "builtin_longjmp"
8236 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
8240 /* The elements of the buffer are, in order: */
8241 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8242 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8243 POINTER_SIZE / BITS_PER_UNIT));
8244 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8245 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8246 rtx pv = gen_rtx_REG (Pmode, 1);
8248 /* This bit is the same as expand_builtin_longjmp. */
8249 emit_move_insn (hard_frame_pointer_rtx, fp);
8250 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8251 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8252 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8254 /* Load the label we are jumping through into r1 so that we know
8255 where to look for it when we get back to setjmp's function for
8256 restoring the gp. */
8257 emit_move_insn (pv, lab);
8259 /* Prevent the insns above from being scheduled into the delay slot
8260 of the interspace jump because the space register could change. */
8261 emit_insn (gen_blockage ());
8263 emit_jump_insn (gen_interspace_jump (pv));
8268 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8269 (define_expand "extzv"
8270 [(set (match_operand 0 "register_operand" "")
8271 (zero_extract (match_operand 1 "register_operand" "")
8272 (match_operand 2 "uint32_operand" "")
8273 (match_operand 3 "uint32_operand" "")))]
8277 HOST_WIDE_INT len = INTVAL (operands[2]);
8278 HOST_WIDE_INT pos = INTVAL (operands[3]);
8280 /* PA extraction insns don't support zero length bitfields or fields
8281 extending beyond the left or right-most bits. Also, we reject lengths
8282 equal to a word as they are better handled by the move patterns. */
8283 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8286 /* From mips.md: extract_bit_field doesn't verify that our source
8287 matches the predicate, so check it again here. */
8288 if (!register_operand (operands[1], VOIDmode))
8292 emit_insn (gen_extzv_64 (operands[0], operands[1],
8293 operands[2], operands[3]));
8295 emit_insn (gen_extzv_32 (operands[0], operands[1],
8296 operands[2], operands[3]));
8300 (define_insn "extzv_32"
8301 [(set (match_operand:SI 0 "register_operand" "=r")
8302 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8303 (match_operand:SI 2 "uint5_operand" "")
8304 (match_operand:SI 3 "uint5_operand" "")))]
8306 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8307 [(set_attr "type" "shift")
8308 (set_attr "length" "4")])
8311 [(set (match_operand:SI 0 "register_operand" "=r")
8312 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8314 (match_operand:SI 2 "register_operand" "q")))]
8316 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8317 [(set_attr "type" "shift")
8318 (set_attr "length" "4")])
8320 (define_insn "extzv_64"
8321 [(set (match_operand:DI 0 "register_operand" "=r")
8322 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8323 (match_operand:DI 2 "uint32_operand" "")
8324 (match_operand:DI 3 "uint32_operand" "")))]
8326 "extrd,u %1,%3+%2-1,%2,%0"
8327 [(set_attr "type" "shift")
8328 (set_attr "length" "4")])
8331 [(set (match_operand:DI 0 "register_operand" "=r")
8332 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8334 (match_operand:DI 2 "register_operand" "q")))]
8336 "extrd,u %1,%%sar,1,%0"
8337 [(set_attr "type" "shift")
8338 (set_attr "length" "4")])
8340 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8341 (define_expand "extv"
8342 [(set (match_operand 0 "register_operand" "")
8343 (sign_extract (match_operand 1 "register_operand" "")
8344 (match_operand 2 "uint32_operand" "")
8345 (match_operand 3 "uint32_operand" "")))]
8349 HOST_WIDE_INT len = INTVAL (operands[2]);
8350 HOST_WIDE_INT pos = INTVAL (operands[3]);
8352 /* PA extraction insns don't support zero length bitfields or fields
8353 extending beyond the left or right-most bits. Also, we reject lengths
8354 equal to a word as they are better handled by the move patterns. */
8355 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8358 /* From mips.md: extract_bit_field doesn't verify that our source
8359 matches the predicate, so check it again here. */
8360 if (!register_operand (operands[1], VOIDmode))
8364 emit_insn (gen_extv_64 (operands[0], operands[1],
8365 operands[2], operands[3]));
8367 emit_insn (gen_extv_32 (operands[0], operands[1],
8368 operands[2], operands[3]));
8372 (define_insn "extv_32"
8373 [(set (match_operand:SI 0 "register_operand" "=r")
8374 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8375 (match_operand:SI 2 "uint5_operand" "")
8376 (match_operand:SI 3 "uint5_operand" "")))]
8378 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8379 [(set_attr "type" "shift")
8380 (set_attr "length" "4")])
8383 [(set (match_operand:SI 0 "register_operand" "=r")
8384 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8386 (match_operand:SI 2 "register_operand" "q")))]
8388 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8389 [(set_attr "type" "shift")
8390 (set_attr "length" "4")])
8392 (define_insn "extv_64"
8393 [(set (match_operand:DI 0 "register_operand" "=r")
8394 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8395 (match_operand:DI 2 "uint32_operand" "")
8396 (match_operand:DI 3 "uint32_operand" "")))]
8398 "extrd,s %1,%3+%2-1,%2,%0"
8399 [(set_attr "type" "shift")
8400 (set_attr "length" "4")])
8403 [(set (match_operand:DI 0 "register_operand" "=r")
8404 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8406 (match_operand:DI 2 "register_operand" "q")))]
8408 "extrd,s %1,%%sar,1,%0"
8409 [(set_attr "type" "shift")
8410 (set_attr "length" "4")])
8412 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8413 (define_expand "insv"
8414 [(set (zero_extract (match_operand 0 "register_operand" "")
8415 (match_operand 1 "uint32_operand" "")
8416 (match_operand 2 "uint32_operand" ""))
8417 (match_operand 3 "arith5_operand" ""))]
8421 HOST_WIDE_INT len = INTVAL (operands[1]);
8422 HOST_WIDE_INT pos = INTVAL (operands[2]);
8424 /* PA insertion insns don't support zero length bitfields or fields
8425 extending beyond the left or right-most bits. Also, we reject lengths
8426 equal to a word as they are better handled by the move patterns. */
8427 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8430 /* From mips.md: insert_bit_field doesn't verify that our destination
8431 matches the predicate, so check it again here. */
8432 if (!register_operand (operands[0], VOIDmode))
8436 emit_insn (gen_insv_64 (operands[0], operands[1],
8437 operands[2], operands[3]));
8439 emit_insn (gen_insv_32 (operands[0], operands[1],
8440 operands[2], operands[3]));
8444 (define_insn "insv_32"
8445 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8446 (match_operand:SI 1 "uint5_operand" "")
8447 (match_operand:SI 2 "uint5_operand" ""))
8448 (match_operand:SI 3 "arith5_operand" "r,L"))]
8451 {dep|depw} %3,%2+%1-1,%1,%0
8452 {depi|depwi} %3,%2+%1-1,%1,%0"
8453 [(set_attr "type" "shift,shift")
8454 (set_attr "length" "4,4")])
8456 ;; Optimize insertion of const_int values of type 1...1xxxx.
8458 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8459 (match_operand:SI 1 "uint5_operand" "")
8460 (match_operand:SI 2 "uint5_operand" ""))
8461 (match_operand:SI 3 "const_int_operand" ""))]
8462 "(INTVAL (operands[3]) & 0x10) != 0 &&
8463 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8466 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8467 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8469 [(set_attr "type" "shift")
8470 (set_attr "length" "4")])
8472 (define_insn "insv_64"
8473 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8474 (match_operand:DI 1 "uint32_operand" "")
8475 (match_operand:DI 2 "uint32_operand" ""))
8476 (match_operand:DI 3 "arith32_operand" "r,L"))]
8479 depd %3,%2+%1-1,%1,%0
8480 depdi %3,%2+%1-1,%1,%0"
8481 [(set_attr "type" "shift,shift")
8482 (set_attr "length" "4,4")])
8484 ;; Optimize insertion of const_int values of type 1...1xxxx.
8486 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8487 (match_operand:DI 1 "uint32_operand" "")
8488 (match_operand:DI 2 "uint32_operand" ""))
8489 (match_operand:DI 3 "const_int_operand" ""))]
8490 "(INTVAL (operands[3]) & 0x10) != 0
8492 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8495 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8496 return \"depdi %3,%2+%1-1,%1,%0\";
8498 [(set_attr "type" "shift")
8499 (set_attr "length" "4")])
8502 [(set (match_operand:DI 0 "register_operand" "=r")
8503 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8506 "depd,z %1,31,32,%0"
8507 [(set_attr "type" "shift")
8508 (set_attr "length" "4")])
8510 ;; This insn is used for some loop tests, typically loops reversed when
8511 ;; strength reduction is used. It is actually created when the instruction
8512 ;; combination phase combines the special loop test. Since this insn
8513 ;; is both a jump insn and has an output, it must deal with its own
8514 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8515 ;; to not choose the register alternatives in the event a reload is needed.
8516 (define_insn "decrement_and_branch_until_zero"
8519 (match_operator 2 "comparison_operator"
8521 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8522 (match_operand:SI 1 "int5_operand" "L,L,L"))
8524 (label_ref (match_operand 3 "" ""))
8527 (plus:SI (match_dup 0) (match_dup 1)))
8528 (clobber (match_scratch:SI 4 "=X,r,r"))]
8530 "* return output_dbra (operands, insn, which_alternative); "
8531 ;; Do not expect to understand this the first time through.
8532 [(set_attr "type" "cbranch,multi,multi")
8533 (set (attr "length")
8534 (if_then_else (eq_attr "alternative" "0")
8535 ;; Loop counter in register case
8536 ;; Short branch has length of 4
8537 ;; Long branch has length of 8
8538 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8543 ;; Loop counter in FP reg case.
8544 ;; Extra goo to deal with additional reload insns.
8545 (if_then_else (eq_attr "alternative" "1")
8546 (if_then_else (lt (match_dup 3) (pc))
8548 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8553 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8557 ;; Loop counter in memory case.
8558 ;; Extra goo to deal with additional reload insns.
8559 (if_then_else (lt (match_dup 3) (pc))
8561 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8566 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8569 (const_int 16))))))])
8574 (match_operator 2 "movb_comparison_operator"
8575 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8576 (label_ref (match_operand 3 "" ""))
8578 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8581 "* return output_movb (operands, insn, which_alternative, 0); "
8582 ;; Do not expect to understand this the first time through.
8583 [(set_attr "type" "cbranch,multi,multi,multi")
8584 (set (attr "length")
8585 (if_then_else (eq_attr "alternative" "0")
8586 ;; Loop counter in register case
8587 ;; Short branch has length of 4
8588 ;; Long branch has length of 8
8589 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8594 ;; Loop counter in FP reg case.
8595 ;; Extra goo to deal with additional reload insns.
8596 (if_then_else (eq_attr "alternative" "1")
8597 (if_then_else (lt (match_dup 3) (pc))
8599 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8604 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8608 ;; Loop counter in memory or sar case.
8609 ;; Extra goo to deal with additional reload insns.
8611 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8614 (const_int 12)))))])
8616 ;; Handle negated branch.
8620 (match_operator 2 "movb_comparison_operator"
8621 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8623 (label_ref (match_operand 3 "" ""))))
8624 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8627 "* return output_movb (operands, insn, which_alternative, 1); "
8628 ;; Do not expect to understand this the first time through.
8629 [(set_attr "type" "cbranch,multi,multi,multi")
8630 (set (attr "length")
8631 (if_then_else (eq_attr "alternative" "0")
8632 ;; Loop counter in register case
8633 ;; Short branch has length of 4
8634 ;; Long branch has length of 8
8635 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8640 ;; Loop counter in FP reg case.
8641 ;; Extra goo to deal with additional reload insns.
8642 (if_then_else (eq_attr "alternative" "1")
8643 (if_then_else (lt (match_dup 3) (pc))
8645 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8650 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8654 ;; Loop counter in memory or SAR case.
8655 ;; Extra goo to deal with additional reload insns.
8657 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8660 (const_int 12)))))])
8663 [(set (pc) (label_ref (match_operand 3 "" "" )))
8664 (set (match_operand:SI 0 "ireg_operand" "=r")
8665 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8666 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8667 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8670 return output_parallel_addb (operands, get_attr_length (insn));
8672 [(set_attr "type" "parallel_branch")
8673 (set (attr "length")
8674 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8680 [(set (pc) (label_ref (match_operand 2 "" "" )))
8681 (set (match_operand:SF 0 "ireg_operand" "=r")
8682 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8686 return output_parallel_movb (operands, get_attr_length (insn));
8688 [(set_attr "type" "parallel_branch")
8689 (set (attr "length")
8690 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8696 [(set (pc) (label_ref (match_operand 2 "" "" )))
8697 (set (match_operand:SI 0 "ireg_operand" "=r")
8698 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8702 return output_parallel_movb (operands, get_attr_length (insn));
8704 [(set_attr "type" "parallel_branch")
8705 (set (attr "length")
8706 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8712 [(set (pc) (label_ref (match_operand 2 "" "" )))
8713 (set (match_operand:HI 0 "ireg_operand" "=r")
8714 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8718 return output_parallel_movb (operands, get_attr_length (insn));
8720 [(set_attr "type" "parallel_branch")
8721 (set (attr "length")
8722 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8728 [(set (pc) (label_ref (match_operand 2 "" "" )))
8729 (set (match_operand:QI 0 "ireg_operand" "=r")
8730 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8734 return output_parallel_movb (operands, get_attr_length (insn));
8736 [(set_attr "type" "parallel_branch")
8737 (set (attr "length")
8738 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8744 [(set (match_operand 0 "register_operand" "=f")
8745 (mult (match_operand 1 "register_operand" "f")
8746 (match_operand 2 "register_operand" "f")))
8747 (set (match_operand 3 "register_operand" "+f")
8748 (plus (match_operand 4 "register_operand" "f")
8749 (match_operand 5 "register_operand" "f")))]
8750 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8751 && reload_completed && fmpyaddoperands (operands)"
8754 if (GET_MODE (operands[0]) == DFmode)
8756 if (rtx_equal_p (operands[3], operands[5]))
8757 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8759 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8763 if (rtx_equal_p (operands[3], operands[5]))
8764 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8766 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8769 [(set_attr "type" "fpalu")
8770 (set_attr "length" "4")])
8773 [(set (match_operand 3 "register_operand" "+f")
8774 (plus (match_operand 4 "register_operand" "f")
8775 (match_operand 5 "register_operand" "f")))
8776 (set (match_operand 0 "register_operand" "=f")
8777 (mult (match_operand 1 "register_operand" "f")
8778 (match_operand 2 "register_operand" "f")))]
8779 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8780 && reload_completed && fmpyaddoperands (operands)"
8783 if (GET_MODE (operands[0]) == DFmode)
8785 if (rtx_equal_p (operands[3], operands[5]))
8786 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8788 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8792 if (rtx_equal_p (operands[3], operands[5]))
8793 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8795 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8798 [(set_attr "type" "fpalu")
8799 (set_attr "length" "4")])
8802 [(set (match_operand 0 "register_operand" "=f")
8803 (mult (match_operand 1 "register_operand" "f")
8804 (match_operand 2 "register_operand" "f")))
8805 (set (match_operand 3 "register_operand" "+f")
8806 (minus (match_operand 4 "register_operand" "f")
8807 (match_operand 5 "register_operand" "f")))]
8808 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8809 && reload_completed && fmpysuboperands (operands)"
8812 if (GET_MODE (operands[0]) == DFmode)
8813 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8815 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8817 [(set_attr "type" "fpalu")
8818 (set_attr "length" "4")])
8821 [(set (match_operand 3 "register_operand" "+f")
8822 (minus (match_operand 4 "register_operand" "f")
8823 (match_operand 5 "register_operand" "f")))
8824 (set (match_operand 0 "register_operand" "=f")
8825 (mult (match_operand 1 "register_operand" "f")
8826 (match_operand 2 "register_operand" "f")))]
8827 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8828 && reload_completed && fmpysuboperands (operands)"
8831 if (GET_MODE (operands[0]) == DFmode)
8832 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8834 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8836 [(set_attr "type" "fpalu")
8837 (set_attr "length" "4")])
8839 ;; Clean up turds left by reload.
8841 [(set (match_operand 0 "move_dest_operand" "")
8842 (match_operand 1 "register_operand" "fr"))
8843 (set (match_operand 2 "register_operand" "fr")
8846 && GET_CODE (operands[0]) == MEM
8847 && ! MEM_VOLATILE_P (operands[0])
8848 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8849 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8850 && GET_MODE (operands[0]) == DFmode
8851 && GET_CODE (operands[1]) == REG
8852 && GET_CODE (operands[2]) == REG
8853 && ! side_effects_p (XEXP (operands[0], 0))
8854 && REGNO_REG_CLASS (REGNO (operands[1]))
8855 == REGNO_REG_CLASS (REGNO (operands[2]))"
8860 if (FP_REG_P (operands[1]))
8861 output_asm_insn (output_fp_move_double (operands), operands);
8863 output_asm_insn (output_move_double (operands), operands);
8865 if (rtx_equal_p (operands[1], operands[2]))
8868 xoperands[0] = operands[2];
8869 xoperands[1] = operands[1];
8871 if (FP_REG_P (xoperands[1]))
8872 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8874 output_asm_insn (output_move_double (xoperands), xoperands);
8880 [(set (match_operand 0 "register_operand" "fr")
8881 (match_operand 1 "move_src_operand" ""))
8882 (set (match_operand 2 "register_operand" "fr")
8885 && GET_CODE (operands[1]) == MEM
8886 && ! MEM_VOLATILE_P (operands[1])
8887 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8888 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8889 && GET_MODE (operands[0]) == DFmode
8890 && GET_CODE (operands[0]) == REG
8891 && GET_CODE (operands[2]) == REG
8892 && ! side_effects_p (XEXP (operands[1], 0))
8893 && REGNO_REG_CLASS (REGNO (operands[0]))
8894 == REGNO_REG_CLASS (REGNO (operands[2]))"
8899 if (FP_REG_P (operands[0]))
8900 output_asm_insn (output_fp_move_double (operands), operands);
8902 output_asm_insn (output_move_double (operands), operands);
8904 xoperands[0] = operands[2];
8905 xoperands[1] = operands[0];
8907 if (FP_REG_P (xoperands[1]))
8908 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8910 output_asm_insn (output_move_double (xoperands), xoperands);
8915 ;; Flush the I and D cache lines from the start address (operand0)
8916 ;; to the end address (operand1). No lines are flushed if the end
8917 ;; address is less than the start address (unsigned).
8919 ;; Because the range of memory flushed is variable and the size of
8920 ;; a MEM can only be a CONST_INT, the patterns specify that they
8921 ;; perform an unspecified volatile operation on all memory.
8923 ;; The address range for an icache flush must lie within a single
8924 ;; space on targets with non-equivalent space registers.
8926 ;; This is used by the trampoline code for nested functions.
8928 ;; Operand 0 contains the start address.
8929 ;; Operand 1 contains the end address.
8930 ;; Operand 2 contains the line length to use.
8931 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
8932 (define_insn "dcacheflush"
8934 (unspec_volatile [(mem:BLK (scratch))] 0)
8935 (use (match_operand 0 "pmode_register_operand" "r"))
8936 (use (match_operand 1 "pmode_register_operand" "r"))
8937 (use (match_operand 2 "pmode_register_operand" "r"))
8938 (clobber (match_scratch 3 "=&0"))]
8943 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8945 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8947 [(set_attr "type" "multi")
8948 (set_attr "length" "12")])
8950 (define_insn "icacheflush"
8952 (unspec_volatile [(mem:BLK (scratch))] 0)
8953 (use (match_operand 0 "pmode_register_operand" "r"))
8954 (use (match_operand 1 "pmode_register_operand" "r"))
8955 (use (match_operand 2 "pmode_register_operand" "r"))
8956 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
8957 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
8958 (clobber (match_scratch 5 "=&0"))]
8963 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8965 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8967 [(set_attr "type" "multi")
8968 (set_attr "length" "52")])
8970 ;; An out-of-line prologue.
8971 (define_insn "outline_prologue_call"
8972 [(unspec_volatile [(const_int 0)] 0)
8973 (clobber (reg:SI 31))
8974 (clobber (reg:SI 22))
8975 (clobber (reg:SI 21))
8976 (clobber (reg:SI 20))
8977 (clobber (reg:SI 19))
8978 (clobber (reg:SI 1))]
8982 extern int frame_pointer_needed;
8984 /* We need two different versions depending on whether or not we
8985 need a frame pointer. Also note that we return to the instruction
8986 immediately after the branch rather than two instructions after the
8987 break as normally is the case. */
8988 if (frame_pointer_needed)
8990 /* Must import the magic millicode routine(s). */
8991 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
8993 if (TARGET_PORTABLE_RUNTIME)
8995 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
8996 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9000 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9004 /* Must import the magic millicode routine(s). */
9005 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9007 if (TARGET_PORTABLE_RUNTIME)
9009 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9010 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9013 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9017 [(set_attr "type" "multi")
9018 (set_attr "length" "8")])
9020 ;; An out-of-line epilogue.
9021 (define_insn "outline_epilogue_call"
9022 [(unspec_volatile [(const_int 1)] 0)
9025 (clobber (reg:SI 31))
9026 (clobber (reg:SI 22))
9027 (clobber (reg:SI 21))
9028 (clobber (reg:SI 20))
9029 (clobber (reg:SI 19))
9030 (clobber (reg:SI 2))
9031 (clobber (reg:SI 1))]
9035 extern int frame_pointer_needed;
9037 /* We need two different versions depending on whether or not we
9038 need a frame pointer. Also note that we return to the instruction
9039 immediately after the branch rather than two instructions after the
9040 break as normally is the case. */
9041 if (frame_pointer_needed)
9043 /* Must import the magic millicode routine. */
9044 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9046 /* The out-of-line prologue will make sure we return to the right
9048 if (TARGET_PORTABLE_RUNTIME)
9050 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9051 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9055 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9059 /* Must import the magic millicode routine. */
9060 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9062 /* The out-of-line prologue will make sure we return to the right
9064 if (TARGET_PORTABLE_RUNTIME)
9066 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9067 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9070 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9074 [(set_attr "type" "multi")
9075 (set_attr "length" "8")])
9077 ;; Given a function pointer, canonicalize it so it can be
9078 ;; reliably compared to another function pointer. */
9079 (define_expand "canonicalize_funcptr_for_compare"
9080 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9081 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9082 (clobber (match_dup 2))
9083 (clobber (reg:SI 26))
9084 (clobber (reg:SI 22))
9085 (clobber (reg:SI 31))])
9086 (set (match_operand:SI 0 "register_operand" "")
9088 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9093 rtx canonicalize_funcptr_for_compare_libfunc
9094 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9096 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9097 operands[0], LCT_NORMAL, Pmode,
9098 1, operands[1], Pmode);
9102 operands[2] = gen_reg_rtx (SImode);
9103 if (GET_CODE (operands[1]) != REG)
9105 rtx tmp = gen_reg_rtx (Pmode);
9106 emit_move_insn (tmp, operands[1]);
9112 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9113 (clobber (match_operand:SI 0 "register_operand" "=a"))
9114 (clobber (reg:SI 26))
9115 (clobber (reg:SI 22))
9116 (clobber (reg:SI 31))]
9120 int length = get_attr_length (insn);
9123 xoperands[0] = GEN_INT (length - 8);
9124 xoperands[1] = GEN_INT (length - 16);
9126 /* Must import the magic millicode routine. */
9127 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9129 /* This is absolutely amazing.
9131 First, copy our input parameter into %r29 just in case we don't
9132 need to call $$sh_func_adrs. */
9133 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9134 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9136 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9137 we use %r26 unchanged. */
9138 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9139 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9141 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9142 4096, then again we use %r26 unchanged. */
9143 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9145 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9146 return output_millicode_call (insn,
9147 gen_rtx_SYMBOL_REF (SImode,
9148 \"$$sh_func_adrs\"));
9150 [(set_attr "type" "multi")
9151 (set (attr "length")
9152 (plus (symbol_ref "attr_length_millicode_call (insn)")
9155 ;; On the PA, the PIC register is call clobbered, so it must
9156 ;; be saved & restored around calls by the caller. If the call
9157 ;; doesn't return normally (nonlocal goto, or an exception is
9158 ;; thrown), then the code at the exception handler label must
9159 ;; restore the PIC register.
9160 (define_expand "exception_receiver"
9165 /* On the 64-bit port, we need a blockage because there is
9166 confusion regarding the dependence of the restore on the
9167 frame pointer. As a result, the frame pointer and pic
9168 register restores sometimes are interchanged erroneously. */
9170 emit_insn (gen_blockage ());
9171 /* Restore the PIC register using hppa_pic_save_rtx (). The
9172 PIC register is not saved in the frame in 64-bit ABI. */
9173 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9174 emit_insn (gen_blockage ());
9178 (define_expand "builtin_setjmp_receiver"
9179 [(label_ref (match_operand 0 "" ""))]
9184 emit_insn (gen_blockage ());
9185 /* Restore the PIC register. Hopefully, this will always be from
9186 a stack slot. The only registers that are valid after a
9187 builtin_longjmp are the stack and frame pointers. */
9188 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9189 emit_insn (gen_blockage ());
9193 ;; Allocate new stack space and update the saved stack pointer in the
9194 ;; frame marker. The HP C compilers also copy additional words in the
9195 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9196 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9197 ;; currently don't copy these values.
9199 ;; Since the copy of the frame marker can't be done atomically, I
9200 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9201 ;; The HP compilers appear to raise the stack and copy the frame
9202 ;; marker in a strict instruction sequence. This suggests that the
9203 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9204 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9205 ;; as GAS doesn't support it, or try to keep the instructions emitted
9206 ;; here in strict sequence.
9207 (define_expand "allocate_stack"
9208 [(match_operand 0 "" "")
9209 (match_operand 1 "" "")]
9215 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9216 in operand 0 before adjusting the stack. */
9217 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9218 anti_adjust_stack (operands[1]);
9219 if (TARGET_HPUX_UNWIND_LIBRARY)
9221 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9222 GEN_INT (TARGET_64BIT ? -8 : -4));
9223 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9225 if (!TARGET_64BIT && flag_pic)
9227 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9228 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);