1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
629 ;; placeholders. This is necessary in rare situations when a
630 ;; placeholder is re-emitted (see PR 8705).
632 (define_expand "movccfp"
634 (match_operand 0 "const_int_operand" ""))]
635 "! TARGET_SOFT_FLOAT"
638 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
642 ;; The following patterns are optimization placeholders. In almost
643 ;; all cases, the user of the condition code will be simplified and the
644 ;; original condition code setting insn should be eliminated.
646 (define_insn "*movccfp0"
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,dbl,= %%fr0,%%fr0"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
654 (define_insn "*movccfp1"
657 "! TARGET_SOFT_FLOAT"
658 "fcmp,dbl,!= %%fr0,%%fr0"
659 [(set_attr "length" "4")
660 (set_attr "type" "fpcc")])
665 [(set (match_operand:SI 0 "register_operand" "")
671 /* fp scc patterns rarely match, and are not a win on the PA. */
672 if (hppa_branch_type != CMP_SI)
674 /* set up operands from compare. */
675 operands[1] = hppa_compare_op0;
676 operands[2] = hppa_compare_op1;
677 /* fall through and generate default code */
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
737 [(set (match_operand:SI 0 "register_operand" "")
743 /* fp scc patterns rarely match, and are not a win on the PA. */
744 if (hppa_branch_type != CMP_SI)
746 operands[1] = hppa_compare_op0;
747 operands[2] = hppa_compare_op1;
750 (define_expand "sltu"
751 [(set (match_operand:SI 0 "register_operand" "")
752 (ltu:SI (match_dup 1)
757 if (hppa_branch_type != CMP_SI)
759 operands[1] = hppa_compare_op0;
760 operands[2] = hppa_compare_op1;
763 (define_expand "sgtu"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (gtu:SI (match_dup 1)
770 if (hppa_branch_type != CMP_SI)
772 operands[1] = hppa_compare_op0;
773 operands[2] = hppa_compare_op1;
776 (define_expand "sleu"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (leu:SI (match_dup 1)
783 if (hppa_branch_type != CMP_SI)
785 operands[1] = hppa_compare_op0;
786 operands[2] = hppa_compare_op1;
789 (define_expand "sgeu"
790 [(set (match_operand:SI 0 "register_operand" "")
791 (geu:SI (match_dup 1)
796 if (hppa_branch_type != CMP_SI)
798 operands[1] = hppa_compare_op0;
799 operands[2] = hppa_compare_op1;
802 ;; Instruction canonicalization puts immediate operands second, which
803 ;; is the reverse of what we want.
806 [(set (match_operand:SI 0 "register_operand" "=r")
807 (match_operator:SI 3 "comparison_operator"
808 [(match_operand:SI 1 "register_operand" "r")
809 (match_operand:SI 2 "arith11_operand" "rI")]))]
811 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
812 [(set_attr "type" "binary")
813 (set_attr "length" "8")])
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (match_operator:DI 3 "comparison_operator"
818 [(match_operand:DI 1 "register_operand" "r")
819 (match_operand:DI 2 "arith11_operand" "rI")]))]
821 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
822 [(set_attr "type" "binary")
823 (set_attr "length" "8")])
825 (define_insn "iorscc"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (ior:SI (match_operator:SI 3 "comparison_operator"
828 [(match_operand:SI 1 "register_operand" "r")
829 (match_operand:SI 2 "arith11_operand" "rI")])
830 (match_operator:SI 6 "comparison_operator"
831 [(match_operand:SI 4 "register_operand" "r")
832 (match_operand:SI 5 "arith11_operand" "rI")])))]
834 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "12")])
839 [(set (match_operand:DI 0 "register_operand" "=r")
840 (ior:DI (match_operator:DI 3 "comparison_operator"
841 [(match_operand:DI 1 "register_operand" "r")
842 (match_operand:DI 2 "arith11_operand" "rI")])
843 (match_operator:DI 6 "comparison_operator"
844 [(match_operand:DI 4 "register_operand" "r")
845 (match_operand:DI 5 "arith11_operand" "rI")])))]
847 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "12")])
851 ;; Combiner patterns for common operations performed with the output
852 ;; from an scc insn (negscc and incscc).
853 (define_insn "negscc"
854 [(set (match_operand:SI 0 "register_operand" "=r")
855 (neg:SI (match_operator:SI 3 "comparison_operator"
856 [(match_operand:SI 1 "register_operand" "r")
857 (match_operand:SI 2 "arith11_operand" "rI")])))]
859 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (neg:DI (match_operator:DI 3 "comparison_operator"
866 [(match_operand:DI 1 "register_operand" "r")
867 (match_operand:DI 2 "arith11_operand" "rI")])))]
869 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
870 [(set_attr "type" "binary")
871 (set_attr "length" "8")])
873 ;; Patterns for adding/subtracting the result of a boolean expression from
874 ;; a register. First we have special patterns that make use of the carry
875 ;; bit, and output only two instructions. For the cases we can't in
876 ;; general do in two instructions, the incscc pattern at the end outputs
877 ;; two or three instructions.
880 [(set (match_operand:SI 0 "register_operand" "=r")
881 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
882 (match_operand:SI 3 "arith11_operand" "rI"))
883 (match_operand:SI 1 "register_operand" "r")))]
885 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
886 [(set_attr "type" "binary")
887 (set_attr "length" "8")])
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
892 (match_operand:DI 3 "arith11_operand" "rI"))
893 (match_operand:DI 1 "register_operand" "r")))]
895 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
899 ; This need only accept registers for op3, since canonicalization
900 ; replaces geu with gtu when op3 is an integer.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
904 (match_operand:SI 3 "register_operand" "r"))
905 (match_operand:SI 1 "register_operand" "r")))]
907 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
914 (match_operand:DI 3 "register_operand" "r"))
915 (match_operand:DI 1 "register_operand" "r")))]
917 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 ; Match only integers for op3 here. This is used as canonical form of the
922 ; geu pattern when op3 is an integer. Don't match registers since we can't
923 ; make better code than the general incscc pattern.
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
927 (match_operand:SI 3 "int11_operand" "I"))
928 (match_operand:SI 1 "register_operand" "r")))]
930 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "8")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
937 (match_operand:DI 3 "int11_operand" "I"))
938 (match_operand:DI 1 "register_operand" "r")))]
940 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "8")])
944 (define_insn "incscc"
945 [(set (match_operand:SI 0 "register_operand" "=r,r")
946 (plus:SI (match_operator:SI 4 "comparison_operator"
947 [(match_operand:SI 2 "register_operand" "r,r")
948 (match_operand:SI 3 "arith11_operand" "rI,rI")])
949 (match_operand:SI 1 "register_operand" "0,?r")))]
952 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
953 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
954 [(set_attr "type" "binary,binary")
955 (set_attr "length" "8,12")])
958 [(set (match_operand:DI 0 "register_operand" "=r,r")
959 (plus:DI (match_operator:DI 4 "comparison_operator"
960 [(match_operand:DI 2 "register_operand" "r,r")
961 (match_operand:DI 3 "arith11_operand" "rI,rI")])
962 (match_operand:DI 1 "register_operand" "0,?r")))]
965 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
966 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
967 [(set_attr "type" "binary,binary")
968 (set_attr "length" "8,12")])
971 [(set (match_operand:SI 0 "register_operand" "=r")
972 (minus:SI (match_operand:SI 1 "register_operand" "r")
973 (gtu:SI (match_operand:SI 2 "register_operand" "r")
974 (match_operand:SI 3 "arith11_operand" "rI"))))]
976 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
981 [(set (match_operand:DI 0 "register_operand" "=r")
982 (minus:DI (match_operand:DI 1 "register_operand" "r")
983 (gtu:DI (match_operand:DI 2 "register_operand" "r")
984 (match_operand:DI 3 "arith11_operand" "rI"))))]
986 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
993 (gtu:SI (match_operand:SI 2 "register_operand" "r")
994 (match_operand:SI 3 "arith11_operand" "rI")))
995 (match_operand:SI 4 "register_operand" "r")))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI")))
1006 (match_operand:DI 4 "register_operand" "r")))]
1008 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1009 [(set_attr "type" "binary")
1010 (set_attr "length" "8")])
1012 ; This need only accept registers for op3, since canonicalization
1013 ; replaces ltu with leu when op3 is an integer.
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (minus:SI (match_operand:SI 1 "register_operand" "r")
1017 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1018 (match_operand:SI 3 "register_operand" "r"))))]
1020 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1021 [(set_attr "type" "binary")
1022 (set_attr "length" "8")])
1025 [(set (match_operand:DI 0 "register_operand" "=r")
1026 (minus:DI (match_operand:DI 1 "register_operand" "r")
1027 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1028 (match_operand:DI 3 "register_operand" "r"))))]
1030 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1031 [(set_attr "type" "binary")
1032 (set_attr "length" "8")])
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1037 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1038 (match_operand:SI 3 "register_operand" "r")))
1039 (match_operand:SI 4 "register_operand" "r")))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r")))
1050 (match_operand:DI 4 "register_operand" "r")))]
1052 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1053 [(set_attr "type" "binary")
1054 (set_attr "length" "8")])
1056 ; Match only integers for op3 here. This is used as canonical form of the
1057 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1058 ; make better code than the general incscc pattern.
1060 [(set (match_operand:SI 0 "register_operand" "=r")
1061 (minus:SI (match_operand:SI 1 "register_operand" "r")
1062 (leu:SI (match_operand:SI 2 "register_operand" "r")
1063 (match_operand:SI 3 "int11_operand" "I"))))]
1065 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1066 [(set_attr "type" "binary")
1067 (set_attr "length" "8")])
1070 [(set (match_operand:DI 0 "register_operand" "=r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "r")
1072 (leu:DI (match_operand:DI 2 "register_operand" "r")
1073 (match_operand:DI 3 "int11_operand" "I"))))]
1075 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1076 [(set_attr "type" "binary")
1077 (set_attr "length" "8")])
1080 [(set (match_operand:SI 0 "register_operand" "=r")
1081 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1082 (leu:SI (match_operand:SI 2 "register_operand" "r")
1083 (match_operand:SI 3 "int11_operand" "I")))
1084 (match_operand:SI 4 "register_operand" "r")))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I")))
1095 (match_operand:DI 4 "register_operand" "r")))]
1097 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1098 [(set_attr "type" "binary")
1099 (set_attr "length" "8")])
1101 (define_insn "decscc"
1102 [(set (match_operand:SI 0 "register_operand" "=r,r")
1103 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1104 (match_operator:SI 4 "comparison_operator"
1105 [(match_operand:SI 2 "register_operand" "r,r")
1106 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1109 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1110 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1111 [(set_attr "type" "binary,binary")
1112 (set_attr "length" "8,12")])
1115 [(set (match_operand:DI 0 "register_operand" "=r,r")
1116 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1117 (match_operator:DI 4 "comparison_operator"
1118 [(match_operand:DI 2 "register_operand" "r,r")
1119 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1122 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1123 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1124 [(set_attr "type" "binary,binary")
1125 (set_attr "length" "8,12")])
1127 ; Patterns for max and min. (There is no need for an earlyclobber in the
1128 ; last alternative since the middle alternative will match if op0 == op1.)
1130 (define_insn "sminsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1132 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1133 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1136 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1137 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1138 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1139 [(set_attr "type" "multi,multi,multi")
1140 (set_attr "length" "8,8,8")])
1142 (define_insn "smindi3"
1143 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1144 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1145 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1148 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1149 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1150 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1151 [(set_attr "type" "multi,multi,multi")
1152 (set_attr "length" "8,8,8")])
1154 (define_insn "uminsi3"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1157 (match_operand:SI 2 "arith11_operand" "r,I")))]
1160 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1161 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1162 [(set_attr "type" "multi,multi")
1163 (set_attr "length" "8,8")])
1165 (define_insn "umindi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1168 (match_operand:DI 2 "arith11_operand" "r,I")))]
1171 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1172 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1173 [(set_attr "type" "multi,multi")
1174 (set_attr "length" "8,8")])
1176 (define_insn "smaxsi3"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1178 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1179 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1182 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1183 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1184 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1185 [(set_attr "type" "multi,multi,multi")
1186 (set_attr "length" "8,8,8")])
1188 (define_insn "smaxdi3"
1189 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1190 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1191 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1194 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1195 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1196 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1197 [(set_attr "type" "multi,multi,multi")
1198 (set_attr "length" "8,8,8")])
1200 (define_insn "umaxsi3"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1203 (match_operand:SI 2 "arith11_operand" "r,I")))]
1206 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1207 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1208 [(set_attr "type" "multi,multi")
1209 (set_attr "length" "8,8")])
1211 (define_insn "umaxdi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1214 (match_operand:DI 2 "arith11_operand" "r,I")))]
1217 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1218 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1219 [(set_attr "type" "multi,multi")
1220 (set_attr "length" "8,8")])
1222 (define_insn "abssi2"
1223 [(set (match_operand:SI 0 "register_operand" "=r")
1224 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "8")])
1230 (define_insn "absdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=r")
1232 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1234 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1235 [(set_attr "type" "multi")
1236 (set_attr "length" "8")])
1238 ;;; Experimental conditional move patterns
1240 (define_expand "movsicc"
1241 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operator 1 "comparison_operator"
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 enum rtx_code code = GET_CODE (operands[1]);
1253 if (hppa_branch_type != CMP_SI)
1256 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1257 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1260 /* operands[1] is currently the result of compare_from_rtx. We want to
1261 emit a compare of the original operands. */
1262 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1263 operands[4] = hppa_compare_op0;
1264 operands[5] = hppa_compare_op1;
1267 ;; We used to accept any register for op1.
1269 ;; However, it loses sometimes because the compiler will end up using
1270 ;; different registers for op0 and op1 in some critical cases. local-alloc
1271 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1273 ;; If/when global register allocation supports tying we should allow any
1274 ;; register for op1 again.
1276 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1278 (match_operator 2 "comparison_operator"
1279 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1280 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1281 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1285 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1286 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1287 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1288 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1289 [(set_attr "type" "multi,multi,multi,nullshift")
1290 (set_attr "length" "8,8,8,8")])
1293 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1295 (match_operator 5 "comparison_operator"
1296 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1297 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1298 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1299 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1302 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1303 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1304 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1305 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1306 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1307 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1308 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1309 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1310 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1311 (set_attr "length" "8,8,8,8,8,8,8,8")])
1313 (define_expand "movdicc"
1314 [(set (match_operand:DI 0 "register_operand" "")
1316 (match_operator 1 "comparison_operator"
1319 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1320 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1324 enum rtx_code code = GET_CODE (operands[1]);
1326 if (hppa_branch_type != CMP_SI)
1329 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1330 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1333 /* operands[1] is currently the result of compare_from_rtx. We want to
1334 emit a compare of the original operands. */
1335 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1336 operands[4] = hppa_compare_op0;
1337 operands[5] = hppa_compare_op1;
1340 ; We need the first constraint alternative in order to avoid
1341 ; earlyclobbers on all other alternatives.
1343 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1345 (match_operator 2 "comparison_operator"
1346 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1347 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1348 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1352 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1353 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1354 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1355 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1356 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1357 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1358 (set_attr "length" "8,8,8,8,8")])
1361 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1363 (match_operator 5 "comparison_operator"
1364 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1365 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1366 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1367 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1370 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1371 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1372 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1373 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1374 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1375 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1376 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1377 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1378 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1379 (set_attr "length" "8,8,8,8,8,8,8,8")])
1381 ;; Conditional Branches
1383 (define_expand "beq"
1385 (if_then_else (eq (match_dup 1) (match_dup 2))
1386 (label_ref (match_operand 0 "" ""))
1391 if (hppa_branch_type != CMP_SI)
1393 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1394 emit_bcond_fp (NE, operands[0]);
1397 /* set up operands from compare. */
1398 operands[1] = hppa_compare_op0;
1399 operands[2] = hppa_compare_op1;
1400 /* fall through and generate default code */
1403 (define_expand "bne"
1405 (if_then_else (ne (match_dup 1) (match_dup 2))
1406 (label_ref (match_operand 0 "" ""))
1411 if (hppa_branch_type != CMP_SI)
1413 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1414 emit_bcond_fp (NE, operands[0]);
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1421 (define_expand "bgt"
1423 (if_then_else (gt (match_dup 1) (match_dup 2))
1424 (label_ref (match_operand 0 "" ""))
1429 if (hppa_branch_type != CMP_SI)
1431 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1432 emit_bcond_fp (NE, operands[0]);
1435 operands[1] = hppa_compare_op0;
1436 operands[2] = hppa_compare_op1;
1439 (define_expand "blt"
1441 (if_then_else (lt (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bge"
1459 (if_then_else (ge (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "ble"
1477 (if_then_else (le (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bgtu"
1495 (if_then_else (gtu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bltu"
1509 (if_then_else (ltu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bgeu"
1523 (if_then_else (geu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bleu"
1537 (if_then_else (leu (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 operands[1] = hppa_compare_op0;
1546 operands[2] = hppa_compare_op1;
1549 (define_expand "bltgt"
1551 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1552 (label_ref (match_operand 0 "" ""))
1557 if (hppa_branch_type == CMP_SI)
1559 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1560 emit_bcond_fp (NE, operands[0]);
1564 (define_expand "bunle"
1566 (if_then_else (unle (match_dup 1) (match_dup 2))
1567 (label_ref (match_operand 0 "" ""))
1572 if (hppa_branch_type == CMP_SI)
1574 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1575 emit_bcond_fp (NE, operands[0]);
1579 (define_expand "bunlt"
1581 (if_then_else (unlt (match_dup 1) (match_dup 2))
1582 (label_ref (match_operand 0 "" ""))
1587 if (hppa_branch_type == CMP_SI)
1589 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1590 emit_bcond_fp (NE, operands[0]);
1594 (define_expand "bunge"
1596 (if_then_else (unge (match_dup 1) (match_dup 2))
1597 (label_ref (match_operand 0 "" ""))
1602 if (hppa_branch_type == CMP_SI)
1604 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1605 emit_bcond_fp (NE, operands[0]);
1609 (define_expand "bungt"
1611 (if_then_else (ungt (match_dup 1) (match_dup 2))
1612 (label_ref (match_operand 0 "" ""))
1617 if (hppa_branch_type == CMP_SI)
1619 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1620 emit_bcond_fp (NE, operands[0]);
1624 (define_expand "buneq"
1626 (if_then_else (uneq (match_dup 1) (match_dup 2))
1627 (label_ref (match_operand 0 "" ""))
1632 if (hppa_branch_type == CMP_SI)
1634 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1635 emit_bcond_fp (NE, operands[0]);
1639 (define_expand "bunordered"
1641 (if_then_else (unordered (match_dup 1) (match_dup 2))
1642 (label_ref (match_operand 0 "" ""))
1647 if (hppa_branch_type == CMP_SI)
1649 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1650 emit_bcond_fp (NE, operands[0]);
1654 (define_expand "bordered"
1656 (if_then_else (ordered (match_dup 1) (match_dup 2))
1657 (label_ref (match_operand 0 "" ""))
1662 if (hppa_branch_type == CMP_SI)
1664 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1665 emit_bcond_fp (NE, operands[0]);
1669 ;; Match the branch patterns.
1672 ;; Note a long backward conditional branch with an annulled delay slot
1673 ;; has a length of 12.
1677 (match_operator 3 "comparison_operator"
1678 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1679 (match_operand:SI 2 "arith5_operand" "rL")])
1680 (label_ref (match_operand 0 "" ""))
1685 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1686 get_attr_length (insn), 0, insn);
1688 [(set_attr "type" "cbranch")
1689 (set (attr "length")
1690 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1696 (eq (symbol_ref "flag_pic") (const_int 0))
1700 ;; Match the negated branch.
1705 (match_operator 3 "comparison_operator"
1706 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1707 (match_operand:SI 2 "arith5_operand" "rL")])
1709 (label_ref (match_operand 0 "" ""))))]
1713 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1714 get_attr_length (insn), 1, insn);
1716 [(set_attr "type" "cbranch")
1717 (set (attr "length")
1718 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1721 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1724 (eq (symbol_ref "flag_pic") (const_int 0))
1731 (match_operator 3 "comparison_operator"
1732 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1733 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1734 (label_ref (match_operand 0 "" ""))
1739 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1740 get_attr_length (insn), 0, insn);
1742 [(set_attr "type" "cbranch")
1743 (set (attr "length")
1744 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1750 (eq (symbol_ref "flag_pic") (const_int 0))
1754 ;; Match the negated branch.
1759 (match_operator 3 "comparison_operator"
1760 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1761 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1763 (label_ref (match_operand 0 "" ""))))]
1767 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1768 get_attr_length (insn), 1, insn);
1770 [(set_attr "type" "cbranch")
1771 (set (attr "length")
1772 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1775 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1778 (eq (symbol_ref "flag_pic") (const_int 0))
1784 (match_operator 3 "cmpib_comparison_operator"
1785 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1786 (match_operand:DI 2 "arith5_operand" "rL")])
1787 (label_ref (match_operand 0 "" ""))
1792 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1793 get_attr_length (insn), 0, insn);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "cmpib_comparison_operator"
1813 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1814 (match_operand:DI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1835 ;; Branch on Bit patterns.
1839 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1841 (match_operand:SI 1 "uint5_operand" ""))
1843 (label_ref (match_operand 2 "" ""))
1848 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1849 get_attr_length (insn), 0, insn, 0);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1861 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1863 (match_operand:DI 1 "uint32_operand" ""))
1865 (label_ref (match_operand 2 "" ""))
1870 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1871 get_attr_length (insn), 0, insn, 0);
1873 [(set_attr "type" "cbranch")
1874 (set (attr "length")
1875 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1885 (match_operand:SI 1 "uint5_operand" ""))
1888 (label_ref (match_operand 2 "" ""))))]
1892 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1893 get_attr_length (insn), 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1905 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1907 (match_operand:DI 1 "uint32_operand" ""))
1910 (label_ref (match_operand 2 "" ""))))]
1914 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1915 get_attr_length (insn), 1, insn, 0);
1917 [(set_attr "type" "cbranch")
1918 (set (attr "length")
1919 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1927 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "uint5_operand" ""))
1931 (label_ref (match_operand 2 "" ""))
1936 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1937 get_attr_length (insn), 0, insn, 1);
1939 [(set_attr "type" "cbranch")
1940 (set (attr "length")
1941 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "uint32_operand" ""))
1953 (label_ref (match_operand 2 "" ""))
1958 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1959 get_attr_length (insn), 0, insn, 1);
1961 [(set_attr "type" "cbranch")
1962 (set (attr "length")
1963 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1971 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1973 (match_operand:SI 1 "uint5_operand" ""))
1976 (label_ref (match_operand 2 "" ""))))]
1980 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1981 get_attr_length (insn), 1, insn, 1);
1983 [(set_attr "type" "cbranch")
1984 (set (attr "length")
1985 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1995 (match_operand:DI 1 "uint32_operand" ""))
1998 (label_ref (match_operand 2 "" ""))))]
2002 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2003 get_attr_length (insn), 1, insn, 1);
2005 [(set_attr "type" "cbranch")
2006 (set (attr "length")
2007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 ;; Branch on Variable Bit patterns.
2016 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "q"))
2020 (label_ref (match_operand 2 "" ""))
2025 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2026 get_attr_length (insn), 0, insn, 0);
2028 [(set_attr "type" "cbranch")
2029 (set (attr "length")
2030 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2040 (match_operand:DI 1 "register_operand" "q"))
2042 (label_ref (match_operand 2 "" ""))
2047 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2048 get_attr_length (insn), 0, insn, 0);
2050 [(set_attr "type" "cbranch")
2051 (set (attr "length")
2052 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2060 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "q"))
2065 (label_ref (match_operand 2 "" ""))))]
2069 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2070 get_attr_length (insn), 1, insn, 0);
2072 [(set_attr "type" "cbranch")
2073 (set (attr "length")
2074 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2082 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2084 (match_operand:DI 1 "register_operand" "q"))
2087 (label_ref (match_operand 2 "" ""))))]
2091 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2092 get_attr_length (insn), 1, insn, 0);
2094 [(set_attr "type" "cbranch")
2095 (set (attr "length")
2096 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2104 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2106 (match_operand:SI 1 "register_operand" "q"))
2108 (label_ref (match_operand 2 "" ""))
2113 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2114 get_attr_length (insn), 0, insn, 1);
2116 [(set_attr "type" "cbranch")
2117 (set (attr "length")
2118 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2128 (match_operand:DI 1 "register_operand" "q"))
2130 (label_ref (match_operand 2 "" ""))
2135 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2136 get_attr_length (insn), 0, insn, 1);
2138 [(set_attr "type" "cbranch")
2139 (set (attr "length")
2140 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2150 (match_operand:SI 1 "register_operand" "q"))
2153 (label_ref (match_operand 2 "" ""))))]
2157 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2158 get_attr_length (insn), 1, insn, 1);
2160 [(set_attr "type" "cbranch")
2161 (set (attr "length")
2162 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2170 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2172 (match_operand:DI 1 "register_operand" "q"))
2175 (label_ref (match_operand 2 "" ""))))]
2179 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2180 get_attr_length (insn), 1, insn, 1);
2182 [(set_attr "type" "cbranch")
2183 (set (attr "length")
2184 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 ;; Floating point branches
2191 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2192 (label_ref (match_operand 0 "" ""))
2194 "! TARGET_SOFT_FLOAT"
2197 if (INSN_ANNULLED_BRANCH_P (insn))
2198 return \"ftest\;b,n %0\";
2200 return \"ftest\;b%* %0\";
2202 [(set_attr "type" "fbranch")
2203 (set_attr "length" "8")])
2206 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2208 (label_ref (match_operand 0 "" ""))))]
2209 "! TARGET_SOFT_FLOAT"
2212 if (INSN_ANNULLED_BRANCH_P (insn))
2213 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2215 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2217 [(set_attr "type" "fbranch")
2218 (set_attr "length" "12")])
2220 ;; Move instructions
2222 (define_expand "movsi"
2223 [(set (match_operand:SI 0 "general_operand" "")
2224 (match_operand:SI 1 "general_operand" ""))]
2228 if (emit_move_sequence (operands, SImode, 0))
2232 ;; Reloading an SImode or DImode value requires a scratch register if
2233 ;; going in to or out of float point registers.
2235 (define_expand "reload_insi"
2236 [(set (match_operand:SI 0 "register_operand" "=Z")
2237 (match_operand:SI 1 "non_hard_reg_operand" ""))
2238 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2242 if (emit_move_sequence (operands, SImode, operands[2]))
2245 /* We don't want the clobber emitted, so handle this ourselves. */
2246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2250 (define_expand "reload_outsi"
2251 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2252 (match_operand:SI 1 "register_operand" "Z"))
2253 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2257 if (emit_move_sequence (operands, SImode, operands[2]))
2260 /* We don't want the clobber emitted, so handle this ourselves. */
2261 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2266 [(set (match_operand:SI 0 "move_dest_operand"
2267 "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
2268 (match_operand:SI 1 "move_src_operand"
2269 "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
2270 "(register_operand (operands[0], SImode)
2271 || reg_or_0_operand (operands[1], SImode))
2272 && !TARGET_SOFT_FLOAT"
2278 {zdepi|depwi,z} %Z1,%0
2285 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2286 (set_attr "pa_combine_type" "addmove")
2287 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
2290 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2291 (match_operand:SI 1 "register_operand" "f"))]
2293 && !TARGET_DISABLE_INDEXING
2294 && reload_completed"
2296 [(set_attr "type" "fpstore")
2297 (set_attr "pa_combine_type" "addmove")
2298 (set_attr "length" "4")])
2300 ; Rewrite RTL using an indexed store. This will allow the insn that
2301 ; computes the address to be deleted if the register it sets is dead.
2303 [(set (match_operand:SI 0 "register_operand" "")
2304 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2306 (match_operand:SI 2 "register_operand" "")))
2307 (set (mem:SI (match_dup 0))
2308 (match_operand:SI 3 "reg_or_0_operand" ""))]
2310 && REG_OK_FOR_BASE_P (operands[2])
2311 && FP_REGNO_P (REGNO (operands[3]))"
2312 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2314 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2319 [(set (match_operand:SI 0 "register_operand" "")
2320 (plus:SI (match_operand:SI 2 "register_operand" "")
2321 (mult:SI (match_operand:SI 1 "register_operand" "")
2323 (set (mem:SI (match_dup 0))
2324 (match_operand:SI 3 "register_operand" ""))]
2326 && REG_OK_FOR_BASE_P (operands[2])
2327 && FP_REGNO_P (REGNO (operands[3]))"
2328 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2330 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2335 [(set (match_operand:DI 0 "register_operand" "")
2336 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2338 (match_operand:DI 2 "register_operand" "")))
2339 (set (mem:SI (match_dup 0))
2340 (match_operand:SI 3 "register_operand" ""))]
2343 && REG_OK_FOR_BASE_P (operands[2])
2344 && FP_REGNO_P (REGNO (operands[3]))"
2345 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2347 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2352 [(set (match_operand:DI 0 "register_operand" "")
2353 (plus:DI (match_operand:DI 2 "register_operand" "")
2354 (mult:DI (match_operand:DI 1 "register_operand" "")
2356 (set (mem:SI (match_dup 0))
2357 (match_operand:SI 3 "register_operand" ""))]
2360 && REG_OK_FOR_BASE_P (operands[2])
2361 && FP_REGNO_P (REGNO (operands[3]))"
2362 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2364 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2369 [(set (match_operand:SI 0 "register_operand" "")
2370 (plus:SI (match_operand:SI 1 "register_operand" "")
2371 (match_operand:SI 2 "register_operand" "")))
2372 (set (mem:SI (match_dup 0))
2373 (match_operand:SI 3 "register_operand" ""))]
2375 && REG_OK_FOR_BASE_P (operands[1])
2376 && (TARGET_NO_SPACE_REGS
2377 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2378 && FP_REGNO_P (REGNO (operands[3]))"
2379 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2381 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2385 [(set (match_operand:SI 0 "register_operand" "")
2386 (plus:SI (match_operand:SI 1 "register_operand" "")
2387 (match_operand:SI 2 "register_operand" "")))
2388 (set (mem:SI (match_dup 0))
2389 (match_operand:SI 3 "register_operand" ""))]
2391 && REG_OK_FOR_BASE_P (operands[2])
2392 && (TARGET_NO_SPACE_REGS
2393 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2394 && FP_REGNO_P (REGNO (operands[3]))"
2395 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2397 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2401 [(set (match_operand:DI 0 "register_operand" "")
2402 (plus:DI (match_operand:DI 1 "register_operand" "")
2403 (match_operand:DI 2 "register_operand" "")))
2404 (set (mem:SI (match_dup 0))
2405 (match_operand:SI 3 "register_operand" ""))]
2408 && REG_OK_FOR_BASE_P (operands[1])
2409 && (TARGET_NO_SPACE_REGS
2410 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2411 && FP_REGNO_P (REGNO (operands[3]))"
2412 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2414 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2418 [(set (match_operand:DI 0 "register_operand" "")
2419 (plus:DI (match_operand:DI 1 "register_operand" "")
2420 (match_operand:DI 2 "register_operand" "")))
2421 (set (mem:SI (match_dup 0))
2422 (match_operand:SI 3 "register_operand" ""))]
2425 && REG_OK_FOR_BASE_P (operands[2])
2426 && (TARGET_NO_SPACE_REGS
2427 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2428 && FP_REGNO_P (REGNO (operands[3]))"
2429 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2431 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2435 [(set (match_operand:SI 0 "move_dest_operand"
2436 "=r,r,r,r,r,r,Q,!*q")
2437 (match_operand:SI 1 "move_src_operand"
2438 "A,r,J,N,K,RQ,rM,!rM"))]
2439 "(register_operand (operands[0], SImode)
2440 || reg_or_0_operand (operands[1], SImode))
2441 && TARGET_SOFT_FLOAT"
2447 {zdepi|depwi,z} %Z1,%0
2451 [(set_attr "type" "load,move,move,move,move,load,store,move")
2452 (set_attr "pa_combine_type" "addmove")
2453 (set_attr "length" "4,4,4,4,4,4,4,4")])
2455 ;; Load or store with base-register modification.
2457 [(set (match_operand:SI 0 "register_operand" "=r")
2458 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2459 (match_operand:DI 2 "int5_operand" "L"))))
2461 (plus:DI (match_dup 1) (match_dup 2)))]
2464 [(set_attr "type" "load")
2465 (set_attr "length" "4")])
2467 ; And a zero extended variant.
2469 [(set (match_operand:DI 0 "register_operand" "=r")
2470 (zero_extend:DI (mem:SI
2472 (match_operand:DI 1 "register_operand" "+r")
2473 (match_operand:DI 2 "int5_operand" "L")))))
2475 (plus:DI (match_dup 1) (match_dup 2)))]
2478 [(set_attr "type" "load")
2479 (set_attr "length" "4")])
2481 (define_expand "pre_load"
2482 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2483 (mem (plus (match_operand 1 "register_operand" "")
2484 (match_operand 2 "pre_cint_operand" ""))))
2486 (plus (match_dup 1) (match_dup 2)))])]
2492 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2495 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2499 (define_insn "pre_ldw"
2500 [(set (match_operand:SI 0 "register_operand" "=r")
2501 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2502 (match_operand:SI 2 "pre_cint_operand" ""))))
2504 (plus:SI (match_dup 1) (match_dup 2)))]
2508 if (INTVAL (operands[2]) < 0)
2509 return \"{ldwm|ldw,mb} %2(%1),%0\";
2510 return \"{ldws|ldw},mb %2(%1),%0\";
2512 [(set_attr "type" "load")
2513 (set_attr "length" "4")])
2515 (define_insn "pre_ldd"
2516 [(set (match_operand:DI 0 "register_operand" "=r")
2517 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2518 (match_operand:DI 2 "pre_cint_operand" ""))))
2520 (plus:DI (match_dup 1) (match_dup 2)))]
2523 [(set_attr "type" "load")
2524 (set_attr "length" "4")])
2527 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2528 (match_operand:SI 1 "pre_cint_operand" "")))
2529 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2531 (plus:SI (match_dup 0) (match_dup 1)))]
2535 if (INTVAL (operands[1]) < 0)
2536 return \"{stwm|stw,mb} %r2,%1(%0)\";
2537 return \"{stws|stw},mb %r2,%1(%0)\";
2539 [(set_attr "type" "store")
2540 (set_attr "length" "4")])
2543 [(set (match_operand:SI 0 "register_operand" "=r")
2544 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2546 (plus:SI (match_dup 1)
2547 (match_operand:SI 2 "post_cint_operand" "")))]
2551 if (INTVAL (operands[2]) > 0)
2552 return \"{ldwm|ldw,ma} %2(%1),%0\";
2553 return \"{ldws|ldw},ma %2(%1),%0\";
2555 [(set_attr "type" "load")
2556 (set_attr "length" "4")])
2558 (define_expand "post_store"
2559 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2560 (match_operand 1 "reg_or_0_operand" ""))
2563 (match_operand 2 "post_cint_operand" "")))])]
2569 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2572 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2576 (define_insn "post_stw"
2577 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2578 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2580 (plus:SI (match_dup 0)
2581 (match_operand:SI 2 "post_cint_operand" "")))]
2585 if (INTVAL (operands[2]) > 0)
2586 return \"{stwm|stw,ma} %r1,%2(%0)\";
2587 return \"{stws|stw},ma %r1,%2(%0)\";
2589 [(set_attr "type" "store")
2590 (set_attr "length" "4")])
2592 (define_insn "post_std"
2593 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2594 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2596 (plus:DI (match_dup 0)
2597 (match_operand:DI 2 "post_cint_operand" "")))]
2600 [(set_attr "type" "store")
2601 (set_attr "length" "4")])
2603 ;; For loading the address of a label while generating PIC code.
2604 ;; Note since this pattern can be created at reload time (via movsi), all
2605 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2607 [(set (match_operand 0 "pmode_register_operand" "=r")
2608 (match_operand 1 "pic_label_operand" ""))]
2613 extern FILE *asm_out_file;
2615 xoperands[0] = operands[0];
2616 xoperands[1] = operands[1];
2617 xoperands[2] = gen_label_rtx ();
2619 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2620 CODE_LABEL_NUMBER (xoperands[2]));
2621 output_asm_insn (\"mfia %0\", xoperands);
2623 /* If we're trying to load the address of a label that happens to be
2624 close, then we can use a shorter sequence. */
2625 if (GET_CODE (operands[1]) == LABEL_REF
2626 && INSN_ADDRESSES_SET_P ()
2627 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2628 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2629 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2632 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2633 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2637 [(set_attr "type" "multi")
2638 (set_attr "length" "12")]) ; 8 or 12
2641 [(set (match_operand 0 "pmode_register_operand" "=a")
2642 (match_operand 1 "pic_label_operand" ""))]
2647 extern FILE *asm_out_file;
2649 xoperands[0] = operands[0];
2650 xoperands[1] = operands[1];
2651 xoperands[2] = gen_label_rtx ();
2653 output_asm_insn (\"bl .+8,%0\", xoperands);
2654 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2655 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2656 CODE_LABEL_NUMBER (xoperands[2]));
2658 /* If we're trying to load the address of a label that happens to be
2659 close, then we can use a shorter sequence. */
2660 if (GET_CODE (operands[1]) == LABEL_REF
2661 && INSN_ADDRESSES_SET_P ()
2662 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2663 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2664 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2667 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2668 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2672 [(set_attr "type" "multi")
2673 (set_attr "length" "16")]) ; 12 or 16
2676 [(set (match_operand:SI 0 "register_operand" "=a")
2677 (plus:SI (match_operand:SI 1 "register_operand" "r")
2678 (high:SI (match_operand 2 "" ""))))]
2679 "symbolic_operand (operands[2], Pmode)
2680 && ! function_label_operand (operands[2], Pmode)
2683 [(set_attr "type" "binary")
2684 (set_attr "length" "4")])
2687 [(set (match_operand:DI 0 "register_operand" "=a")
2688 (plus:DI (match_operand:DI 1 "register_operand" "r")
2689 (high:DI (match_operand 2 "" ""))))]
2690 "symbolic_operand (operands[2], Pmode)
2691 && ! function_label_operand (operands[2], Pmode)
2695 [(set_attr "type" "binary")
2696 (set_attr "length" "4")])
2698 ;; Always use addil rather than ldil;add sequences. This allows the
2699 ;; HP linker to eliminate the dp relocation if the symbolic operand
2700 ;; lives in the TEXT space.
2702 [(set (match_operand:SI 0 "register_operand" "=a")
2703 (high:SI (match_operand 1 "" "")))]
2704 "symbolic_operand (operands[1], Pmode)
2705 && ! function_label_operand (operands[1], Pmode)
2706 && ! read_only_operand (operands[1], Pmode)
2710 if (TARGET_LONG_LOAD_STORE)
2711 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2713 return \"addil LR'%H1,%%r27\";
2715 [(set_attr "type" "binary")
2716 (set (attr "length")
2717 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2722 ;; This is for use in the prologue/epilogue code. We need it
2723 ;; to add large constants to a stack pointer or frame pointer.
2724 ;; Because of the additional %r1 pressure, we probably do not
2725 ;; want to use this in general code, so make it available
2726 ;; only after reload.
2728 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2729 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2730 (high:SI (match_operand 2 "const_int_operand" ""))))]
2734 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2735 [(set_attr "type" "binary,binary")
2736 (set_attr "length" "4,8")])
2739 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2740 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2741 (high:DI (match_operand 2 "const_int_operand" ""))))]
2742 "reload_completed && TARGET_64BIT"
2745 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2746 [(set_attr "type" "binary,binary")
2747 (set_attr "length" "4,8")])
2750 [(set (match_operand:SI 0 "register_operand" "=r")
2751 (high:SI (match_operand 1 "" "")))]
2752 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2753 && !is_function_label_plus_const (operands[1])"
2756 if (symbolic_operand (operands[1], Pmode))
2757 return \"ldil LR'%H1,%0\";
2759 return \"ldil L'%G1,%0\";
2761 [(set_attr "type" "move")
2762 (set_attr "length" "4")])
2765 [(set (match_operand:DI 0 "register_operand" "=r")
2766 (high:DI (match_operand 1 "const_int_operand" "")))]
2769 [(set_attr "type" "move")
2770 (set_attr "length" "4")])
2773 [(set (match_operand:DI 0 "register_operand" "=r")
2774 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2775 (match_operand:DI 2 "const_int_operand" "i")))]
2778 [(set_attr "type" "move")
2779 (set_attr "length" "4")])
2782 [(set (match_operand:SI 0 "register_operand" "=r")
2783 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2784 (match_operand:SI 2 "immediate_operand" "i")))]
2785 "!is_function_label_plus_const (operands[2])"
2788 if (flag_pic && symbolic_operand (operands[2], Pmode))
2790 else if (symbolic_operand (operands[2], Pmode))
2791 return \"ldo RR'%G2(%1),%0\";
2793 return \"ldo R'%G2(%1),%0\";
2795 [(set_attr "type" "move")
2796 (set_attr "length" "4")])
2798 ;; Now that a symbolic_address plus a constant is broken up early
2799 ;; in the compilation phase (for better CSE) we need a special
2800 ;; combiner pattern to load the symbolic address plus the constant
2801 ;; in only 2 instructions. (For cases where the symbolic address
2802 ;; was not a common subexpression.)
2804 [(set (match_operand:SI 0 "register_operand" "")
2805 (match_operand:SI 1 "symbolic_operand" ""))
2806 (clobber (match_operand:SI 2 "register_operand" ""))]
2807 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2808 [(set (match_dup 2) (high:SI (match_dup 1)))
2809 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2812 ;; hppa_legitimize_address goes to a great deal of trouble to
2813 ;; create addresses which use indexing. In some cases, this
2814 ;; is a lose because there isn't any store instructions which
2815 ;; allow indexed addresses (with integer register source).
2817 ;; These define_splits try to turn a 3 insn store into
2818 ;; a 2 insn store with some creative RTL rewriting.
2820 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2821 (match_operand:SI 1 "shadd_operand" ""))
2822 (plus:SI (match_operand:SI 2 "register_operand" "")
2823 (match_operand:SI 3 "const_int_operand" ""))))
2824 (match_operand:SI 4 "register_operand" ""))
2825 (clobber (match_operand:SI 5 "register_operand" ""))]
2827 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2829 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2833 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2834 (match_operand:SI 1 "shadd_operand" ""))
2835 (plus:SI (match_operand:SI 2 "register_operand" "")
2836 (match_operand:SI 3 "const_int_operand" ""))))
2837 (match_operand:HI 4 "register_operand" ""))
2838 (clobber (match_operand:SI 5 "register_operand" ""))]
2840 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2842 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2846 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2847 (match_operand:SI 1 "shadd_operand" ""))
2848 (plus:SI (match_operand:SI 2 "register_operand" "")
2849 (match_operand:SI 3 "const_int_operand" ""))))
2850 (match_operand:QI 4 "register_operand" ""))
2851 (clobber (match_operand:SI 5 "register_operand" ""))]
2853 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2855 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2858 (define_expand "movhi"
2859 [(set (match_operand:HI 0 "general_operand" "")
2860 (match_operand:HI 1 "general_operand" ""))]
2864 if (emit_move_sequence (operands, HImode, 0))
2869 [(set (match_operand:HI 0 "move_dest_operand"
2870 "=r,r,r,r,r,Q,!*q,!*f")
2871 (match_operand:HI 1 "move_src_operand"
2872 "r,J,N,K,RQ,rM,!rM,!*fM"))]
2873 "register_operand (operands[0], HImode)
2874 || reg_or_0_operand (operands[1], HImode)"
2879 {zdepi|depwi,z} %Z1,%0
2884 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2885 (set_attr "pa_combine_type" "addmove")
2886 (set_attr "length" "4,4,4,4,4,4,4,4")])
2889 [(set (match_operand:HI 0 "register_operand" "=r")
2890 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2891 (match_operand:SI 2 "int5_operand" "L"))))
2893 (plus:SI (match_dup 1) (match_dup 2)))]
2895 "{ldhs|ldh},mb %2(%1),%0"
2896 [(set_attr "type" "load")
2897 (set_attr "length" "4")])
2900 [(set (match_operand:HI 0 "register_operand" "=r")
2901 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2902 (match_operand:DI 2 "int5_operand" "L"))))
2904 (plus:DI (match_dup 1) (match_dup 2)))]
2907 [(set_attr "type" "load")
2908 (set_attr "length" "4")])
2910 ; And a zero extended variant.
2912 [(set (match_operand:DI 0 "register_operand" "=r")
2913 (zero_extend:DI (mem:HI
2915 (match_operand:DI 1 "register_operand" "+r")
2916 (match_operand:DI 2 "int5_operand" "L")))))
2918 (plus:DI (match_dup 1) (match_dup 2)))]
2921 [(set_attr "type" "load")
2922 (set_attr "length" "4")])
2925 [(set (match_operand:SI 0 "register_operand" "=r")
2926 (zero_extend:SI (mem:HI
2928 (match_operand:SI 1 "register_operand" "+r")
2929 (match_operand:SI 2 "int5_operand" "L")))))
2931 (plus:SI (match_dup 1) (match_dup 2)))]
2933 "{ldhs|ldh},mb %2(%1),%0"
2934 [(set_attr "type" "load")
2935 (set_attr "length" "4")])
2938 [(set (match_operand:SI 0 "register_operand" "=r")
2939 (zero_extend:SI (mem:HI
2941 (match_operand:DI 1 "register_operand" "+r")
2942 (match_operand:DI 2 "int5_operand" "L")))))
2944 (plus:DI (match_dup 1) (match_dup 2)))]
2947 [(set_attr "type" "load")
2948 (set_attr "length" "4")])
2951 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2952 (match_operand:SI 1 "int5_operand" "L")))
2953 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2955 (plus:SI (match_dup 0) (match_dup 1)))]
2957 "{sths|sth},mb %r2,%1(%0)"
2958 [(set_attr "type" "store")
2959 (set_attr "length" "4")])
2962 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2963 (match_operand:DI 1 "int5_operand" "L")))
2964 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2966 (plus:DI (match_dup 0) (match_dup 1)))]
2969 [(set_attr "type" "store")
2970 (set_attr "length" "4")])
2973 [(set (match_operand:HI 0 "register_operand" "=r")
2974 (plus:HI (match_operand:HI 1 "register_operand" "r")
2975 (match_operand 2 "const_int_operand" "J")))]
2978 [(set_attr "type" "binary")
2979 (set_attr "pa_combine_type" "addmove")
2980 (set_attr "length" "4")])
2982 (define_expand "movqi"
2983 [(set (match_operand:QI 0 "general_operand" "")
2984 (match_operand:QI 1 "general_operand" ""))]
2988 if (emit_move_sequence (operands, QImode, 0))
2993 [(set (match_operand:QI 0 "move_dest_operand"
2994 "=r,r,r,r,r,Q,!*q,!*f")
2995 (match_operand:QI 1 "move_src_operand"
2996 "r,J,N,K,RQ,rM,!rM,!*fM"))]
2997 "register_operand (operands[0], QImode)
2998 || reg_or_0_operand (operands[1], QImode)"
3003 {zdepi|depwi,z} %Z1,%0
3008 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
3009 (set_attr "pa_combine_type" "addmove")
3010 (set_attr "length" "4,4,4,4,4,4,4,4")])
3013 [(set (match_operand:QI 0 "register_operand" "=r")
3014 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3015 (match_operand:SI 2 "int5_operand" "L"))))
3016 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3018 "{ldbs|ldb},mb %2(%1),%0"
3019 [(set_attr "type" "load")
3020 (set_attr "length" "4")])
3023 [(set (match_operand:QI 0 "register_operand" "=r")
3024 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3025 (match_operand:DI 2 "int5_operand" "L"))))
3026 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3029 [(set_attr "type" "load")
3030 (set_attr "length" "4")])
3032 ; Now the same thing with zero extensions.
3034 [(set (match_operand:DI 0 "register_operand" "=r")
3035 (zero_extend:DI (mem:QI (plus:DI
3036 (match_operand:DI 1 "register_operand" "+r")
3037 (match_operand:DI 2 "int5_operand" "L")))))
3038 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3041 [(set_attr "type" "load")
3042 (set_attr "length" "4")])
3045 [(set (match_operand:SI 0 "register_operand" "=r")
3046 (zero_extend:SI (mem:QI (plus:SI
3047 (match_operand:SI 1 "register_operand" "+r")
3048 (match_operand:SI 2 "int5_operand" "L")))))
3049 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3051 "{ldbs|ldb},mb %2(%1),%0"
3052 [(set_attr "type" "load")
3053 (set_attr "length" "4")])
3056 [(set (match_operand:SI 0 "register_operand" "=r")
3057 (zero_extend:SI (mem:QI (plus:DI
3058 (match_operand:DI 1 "register_operand" "+r")
3059 (match_operand:DI 2 "int5_operand" "L")))))
3060 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3063 [(set_attr "type" "load")
3064 (set_attr "length" "4")])
3067 [(set (match_operand:HI 0 "register_operand" "=r")
3068 (zero_extend:HI (mem:QI (plus:SI
3069 (match_operand:SI 1 "register_operand" "+r")
3070 (match_operand:SI 2 "int5_operand" "L")))))
3071 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3073 "{ldbs|ldb},mb %2(%1),%0"
3074 [(set_attr "type" "load")
3075 (set_attr "length" "4")])
3078 [(set (match_operand:HI 0 "register_operand" "=r")
3079 (zero_extend:HI (mem:QI (plus:DI
3080 (match_operand:DI 1 "register_operand" "+r")
3081 (match_operand:DI 2 "int5_operand" "L")))))
3082 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3085 [(set_attr "type" "load")
3086 (set_attr "length" "4")])
3089 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3090 (match_operand:SI 1 "int5_operand" "L")))
3091 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3093 (plus:SI (match_dup 0) (match_dup 1)))]
3095 "{stbs|stb},mb %r2,%1(%0)"
3096 [(set_attr "type" "store")
3097 (set_attr "length" "4")])
3100 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3101 (match_operand:DI 1 "int5_operand" "L")))
3102 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3104 (plus:DI (match_dup 0) (match_dup 1)))]
3107 [(set_attr "type" "store")
3108 (set_attr "length" "4")])
3110 ;; The definition of this insn does not really explain what it does,
3111 ;; but it should suffice that anything generated as this insn will be
3112 ;; recognized as a movstrsi operation, and that it will not successfully
3113 ;; combine with anything.
3114 (define_expand "movstrsi"
3115 [(parallel [(set (match_operand:BLK 0 "" "")
3116 (match_operand:BLK 1 "" ""))
3117 (clobber (match_dup 4))
3118 (clobber (match_dup 5))
3119 (clobber (match_dup 6))
3120 (clobber (match_dup 7))
3121 (clobber (match_dup 8))
3122 (use (match_operand:SI 2 "arith_operand" ""))
3123 (use (match_operand:SI 3 "const_int_operand" ""))])]
3124 "!TARGET_64BIT && optimize > 0"
3129 /* HP provides very fast block move library routine for the PA;
3130 this routine includes:
3132 4x4 byte at a time block moves,
3133 1x4 byte at a time with alignment checked at runtime with
3134 attempts to align the source and destination as needed
3137 With that in mind, here's the heuristics to try and guess when
3138 the inlined block move will be better than the library block
3141 If the size isn't constant, then always use the library routines.
3143 If the size is large in respect to the known alignment, then use
3144 the library routines.
3146 If the size is small in respect to the known alignment, then open
3147 code the copy (since that will lead to better scheduling).
3149 Else use the block move pattern. */
3151 /* Undetermined size, use the library routine. */
3152 if (GET_CODE (operands[2]) != CONST_INT)
3155 size = INTVAL (operands[2]);
3156 align = INTVAL (operands[3]);
3157 align = align > 4 ? 4 : align;
3159 /* If size/alignment is large, then use the library routines. */
3160 if (size / align > 16)
3163 /* This does happen, but not often enough to worry much about. */
3164 if (size / align < MOVE_RATIO)
3167 /* Fall through means we're going to use our block move pattern. */
3169 = replace_equiv_address (operands[0],
3170 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3172 = replace_equiv_address (operands[1],
3173 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3174 operands[4] = gen_reg_rtx (SImode);
3175 operands[5] = gen_reg_rtx (SImode);
3176 operands[6] = gen_reg_rtx (SImode);
3177 operands[7] = gen_reg_rtx (SImode);
3178 operands[8] = gen_reg_rtx (SImode);
3181 ;; The operand constraints are written like this to support both compile-time
3182 ;; and run-time determined byte counts. The expander and output_block_move
3183 ;; only support compile-time determined counts at this time.
3185 ;; If the count is run-time determined, the register with the byte count
3186 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3188 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3189 ;; broke this semantic for pseudo registers. We can't use match_scratch
3190 ;; as this requires two registers in the class R1_REGS when the MEMs for
3191 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3192 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3193 ;; respectively. We then split or peephole optimize after reload.
3194 (define_insn "movstrsi_prereload"
3195 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3196 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3197 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
3198 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3199 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3200 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3201 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3202 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3203 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3206 [(set_attr "type" "multi,multi")])
3209 [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3210 (mem:BLK (match_operand:SI 1 "register_operand" "")))
3211 (clobber (match_operand:SI 2 "register_operand" ""))
3212 (clobber (match_operand:SI 3 "register_operand" ""))
3213 (clobber (match_operand:SI 6 "register_operand" ""))
3214 (clobber (match_operand:SI 7 "register_operand" ""))
3215 (clobber (match_operand:SI 8 "register_operand" ""))
3216 (use (match_operand:SI 4 "arith_operand" ""))
3217 (use (match_operand:SI 5 "const_int_operand" ""))])]
3218 "!TARGET_64BIT && reload_completed && !flag_peephole2"
3219 [(set (match_dup 7) (match_dup 0))
3220 (set (match_dup 8) (match_dup 1))
3221 (parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
3222 (clobber (match_dup 2))
3223 (clobber (match_dup 3))
3224 (clobber (match_dup 6))
3225 (clobber (match_dup 7))
3226 (clobber (match_dup 8))
3233 [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3234 (mem:BLK (match_operand:SI 1 "register_operand" "")))
3235 (clobber (match_operand:SI 2 "register_operand" ""))
3236 (clobber (match_operand:SI 3 "register_operand" ""))
3237 (clobber (match_operand:SI 6 "register_operand" ""))
3238 (clobber (match_operand:SI 7 "register_operand" ""))
3239 (clobber (match_operand:SI 8 "register_operand" ""))
3240 (use (match_operand:SI 4 "arith_operand" ""))
3241 (use (match_operand:SI 5 "const_int_operand" ""))])]
3243 [(parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
3244 (clobber (match_dup 2))
3245 (clobber (match_dup 3))
3246 (clobber (match_dup 6))
3247 (clobber (match_dup 7))
3248 (clobber (match_dup 8))
3254 if (dead_or_set_p (curr_insn, operands[0]))
3255 operands[7] = operands[0];
3257 emit_insn (gen_rtx_SET (VOIDmode, operands[7], operands[0]));
3259 if (dead_or_set_p (curr_insn, operands[1]))
3260 operands[8] = operands[1];
3262 emit_insn (gen_rtx_SET (VOIDmode, operands[8], operands[1]));
3265 (define_insn "movstrsi_postreload"
3266 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3267 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3268 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
3269 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3270 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3271 (clobber (match_dup 0))
3272 (clobber (match_dup 1))
3273 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3274 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3276 "!TARGET_64BIT && reload_completed"
3277 "* return output_block_move (operands, !which_alternative);"
3278 [(set_attr "type" "multi,multi")])
3280 (define_expand "movstrdi"
3281 [(parallel [(set (match_operand:BLK 0 "" "")
3282 (match_operand:BLK 1 "" ""))
3283 (clobber (match_dup 4))
3284 (clobber (match_dup 5))
3285 (clobber (match_dup 6))
3286 (clobber (match_dup 7))
3287 (clobber (match_dup 8))
3288 (use (match_operand:DI 2 "arith_operand" ""))
3289 (use (match_operand:DI 3 "const_int_operand" ""))])]
3290 "TARGET_64BIT && optimize > 0"
3295 /* HP provides very fast block move library routine for the PA;
3296 this routine includes:
3298 4x4 byte at a time block moves,
3299 1x4 byte at a time with alignment checked at runtime with
3300 attempts to align the source and destination as needed
3303 With that in mind, here's the heuristics to try and guess when
3304 the inlined block move will be better than the library block
3307 If the size isn't constant, then always use the library routines.
3309 If the size is large in respect to the known alignment, then use
3310 the library routines.
3312 If the size is small in respect to the known alignment, then open
3313 code the copy (since that will lead to better scheduling).
3315 Else use the block move pattern. */
3317 /* Undetermined size, use the library routine. */
3318 if (GET_CODE (operands[2]) != CONST_INT)
3321 size = INTVAL (operands[2]);
3322 align = INTVAL (operands[3]);
3323 align = align > 8 ? 8 : align;
3325 /* If size/alignment is large, then use the library routines. */
3326 if (size / align > 16)
3329 /* This does happen, but not often enough to worry much about. */
3330 if (size / align < MOVE_RATIO)
3333 /* Fall through means we're going to use our block move pattern. */
3335 = replace_equiv_address (operands[0],
3336 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3338 = replace_equiv_address (operands[1],
3339 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3340 operands[4] = gen_reg_rtx (DImode);
3341 operands[5] = gen_reg_rtx (DImode);
3342 operands[6] = gen_reg_rtx (DImode);
3343 operands[7] = gen_reg_rtx (DImode);
3344 operands[8] = gen_reg_rtx (DImode);
3347 ;; The operand constraints are written like this to support both compile-time
3348 ;; and run-time determined byte counts. The expander and output_block_move
3349 ;; only support compile-time determined counts at this time.
3351 ;; If the count is run-time determined, the register with the byte count
3352 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3354 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3355 ;; broke this semantic for pseudo registers. We can't use match_scratch
3356 ;; as this requires two registers in the class R1_REGS when the MEMs for
3357 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3358 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3359 ;; respectively. We then split or peephole optimize after reload.
3360 (define_insn "movstrdi_prereload"
3361 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3362 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3363 (clobber (match_operand:DI 2 "register_operand" "=r,r")) ;loop cnt/tmp
3364 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3365 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3366 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3367 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3368 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3369 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3372 [(set_attr "type" "multi,multi")])
3375 [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
3376 (mem:BLK (match_operand:DI 1 "register_operand" "")))
3377 (clobber (match_operand:DI 2 "register_operand" ""))
3378 (clobber (match_operand:DI 3 "register_operand" ""))
3379 (clobber (match_operand:DI 6 "register_operand" ""))
3380 (clobber (match_operand:DI 7 "register_operand" ""))
3381 (clobber (match_operand:DI 8 "register_operand" ""))
3382 (use (match_operand:DI 4 "arith_operand" ""))
3383 (use (match_operand:DI 5 "const_int_operand" ""))])]
3384 "TARGET_64BIT && reload_completed && !flag_peephole2"
3385 [(set (match_dup 7) (match_dup 0))
3386 (set (match_dup 8) (match_dup 1))
3387 (parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
3388 (clobber (match_dup 2))
3389 (clobber (match_dup 3))
3390 (clobber (match_dup 6))
3391 (clobber (match_dup 7))
3392 (clobber (match_dup 8))
3399 [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
3400 (mem:BLK (match_operand:DI 1 "register_operand" "")))
3401 (clobber (match_operand:DI 2 "register_operand" ""))
3402 (clobber (match_operand:DI 3 "register_operand" ""))
3403 (clobber (match_operand:DI 6 "register_operand" ""))
3404 (clobber (match_operand:DI 7 "register_operand" ""))
3405 (clobber (match_operand:DI 8 "register_operand" ""))
3406 (use (match_operand:DI 4 "arith_operand" ""))
3407 (use (match_operand:DI 5 "const_int_operand" ""))])]
3409 [(parallel [(set (mem:BLK (match_dup 7)) (mem:BLK (match_dup 8)))
3410 (clobber (match_dup 2))
3411 (clobber (match_dup 3))
3412 (clobber (match_dup 6))
3413 (clobber (match_dup 7))
3414 (clobber (match_dup 8))
3420 if (dead_or_set_p (curr_insn, operands[0]))
3421 operands[7] = operands[0];
3423 emit_insn (gen_rtx_SET (VOIDmode, operands[7], operands[0]));
3425 if (dead_or_set_p (curr_insn, operands[1]))
3426 operands[8] = operands[1];
3428 emit_insn (gen_rtx_SET (VOIDmode, operands[8], operands[1]));
3431 (define_insn "movstrdi_postreload"
3432 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3433 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3434 (clobber (match_operand:DI 2 "register_operand" "=r,r")) ;loop cnt/tmp
3435 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3436 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3437 (clobber (match_dup 0))
3438 (clobber (match_dup 1))
3439 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3440 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3442 "TARGET_64BIT && reload_completed"
3443 "* return output_block_move (operands, !which_alternative);"
3444 [(set_attr "type" "multi,multi")])
3446 (define_expand "clrstrsi"
3447 [(parallel [(set (match_operand:BLK 0 "" "")
3449 (clobber (match_dup 3))
3450 (clobber (match_dup 4))
3451 (use (match_operand:SI 1 "arith_operand" ""))
3452 (use (match_operand:SI 2 "const_int_operand" ""))])]
3453 "!TARGET_64BIT && optimize > 0"
3458 /* Undetermined size, use the library routine. */
3459 if (GET_CODE (operands[1]) != CONST_INT)
3462 size = INTVAL (operands[1]);
3463 align = INTVAL (operands[2]);
3464 align = align > 4 ? 4 : align;
3466 /* If size/alignment is large, then use the library routines. */
3467 if (size / align > 16)
3470 /* This does happen, but not often enough to worry much about. */
3471 if (size / align < MOVE_RATIO)
3474 /* Fall through means we're going to use our block clear pattern. */
3476 = replace_equiv_address (operands[0],
3477 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3478 operands[3] = gen_reg_rtx (SImode);
3479 operands[4] = gen_reg_rtx (SImode);
3482 (define_insn "clrstrsi_prereload"
3483 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3485 (clobber (match_operand:SI 1 "register_operand" "=r,r")) ;loop cnt/tmp
3486 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3487 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3488 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3491 [(set_attr "type" "multi,multi")])
3494 [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3496 (clobber (match_operand:SI 1 "register_operand" ""))
3497 (clobber (match_operand:SI 4 "register_operand" ""))
3498 (use (match_operand:SI 2 "arith_operand" ""))
3499 (use (match_operand:SI 3 "const_int_operand" ""))])]
3500 "!TARGET_64BIT && reload_completed && !flag_peephole2"
3501 [(set (match_dup 4) (match_dup 0))
3502 (parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
3503 (clobber (match_dup 1))
3504 (clobber (match_dup 4))
3511 [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3513 (clobber (match_operand:SI 1 "register_operand" ""))
3514 (clobber (match_operand:SI 4 "register_operand" ""))
3515 (use (match_operand:SI 2 "arith_operand" ""))
3516 (use (match_operand:SI 3 "const_int_operand" ""))])]
3518 [(parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
3519 (clobber (match_dup 1))
3520 (clobber (match_dup 4))
3526 if (dead_or_set_p (curr_insn, operands[0]))
3527 operands[4] = operands[0];
3529 emit_insn (gen_rtx_SET (VOIDmode, operands[4], operands[0]));
3532 (define_insn "clrstrsi_postreload"
3533 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3535 (clobber (match_operand:SI 1 "register_operand" "=r,r")) ;loop cnt/tmp
3536 (clobber (match_dup 0))
3537 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3538 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3540 "!TARGET_64BIT && reload_completed"
3541 "* return output_block_clear (operands, !which_alternative);"
3542 [(set_attr "type" "multi,multi")])
3544 (define_expand "clrstrdi"
3545 [(parallel [(set (match_operand:BLK 0 "" "")
3547 (clobber (match_dup 3))
3548 (clobber (match_dup 4))
3549 (use (match_operand:DI 1 "arith_operand" ""))
3550 (use (match_operand:DI 2 "const_int_operand" ""))])]
3551 "TARGET_64BIT && optimize > 0"
3556 /* Undetermined size, use the library routine. */
3557 if (GET_CODE (operands[1]) != CONST_INT)
3560 size = INTVAL (operands[1]);
3561 align = INTVAL (operands[2]);
3562 align = align > 8 ? 8 : align;
3564 /* If size/alignment is large, then use the library routines. */
3565 if (size / align > 16)
3568 /* This does happen, but not often enough to worry much about. */
3569 if (size / align < MOVE_RATIO)
3572 /* Fall through means we're going to use our block clear pattern. */
3574 = replace_equiv_address (operands[0],
3575 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3576 operands[3] = gen_reg_rtx (DImode);
3577 operands[4] = gen_reg_rtx (DImode);
3580 (define_insn "clrstrdi_prereload"
3581 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3583 (clobber (match_operand:DI 1 "register_operand" "=r,r")) ;loop cnt/tmp
3584 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3585 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3586 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3589 [(set_attr "type" "multi,multi")])
3592 [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
3594 (clobber (match_operand:DI 1 "register_operand" ""))
3595 (clobber (match_operand:DI 4 "register_operand" ""))
3596 (use (match_operand:DI 2 "arith_operand" ""))
3597 (use (match_operand:DI 3 "const_int_operand" ""))])]
3598 "TARGET_64BIT && reload_completed && !flag_peephole2"
3599 [(set (match_dup 4) (match_dup 0))
3600 (parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
3601 (clobber (match_dup 1))
3602 (clobber (match_dup 4))
3609 [(parallel [(set (mem:BLK (match_operand:DI 0 "register_operand" ""))
3611 (clobber (match_operand:DI 1 "register_operand" ""))
3612 (clobber (match_operand:DI 4 "register_operand" ""))
3613 (use (match_operand:DI 2 "arith_operand" ""))
3614 (use (match_operand:DI 3 "const_int_operand" ""))])]
3616 [(parallel [(set (mem:BLK (match_dup 4)) (const_int 0))
3617 (clobber (match_dup 1))
3618 (clobber (match_dup 4))
3624 if (dead_or_set_p (curr_insn, operands[0]))
3625 operands[4] = operands[0];
3627 emit_insn (gen_rtx_SET (VOIDmode, operands[4], operands[0]));
3630 (define_insn "clrstrdi_postreload"
3631 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3633 (clobber (match_operand:DI 1 "register_operand" "=r,r")) ;loop cnt/tmp
3634 (clobber (match_dup 0))
3635 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3636 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3638 "TARGET_64BIT && reload_completed"
3639 "* return output_block_clear (operands, !which_alternative);"
3640 [(set_attr "type" "multi,multi")])
3642 ;; Floating point move insns
3644 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3645 ;; to be reloaded by putting the constant into memory when
3646 ;; reg is a floating point register.
3648 ;; For integer registers we use ldil;ldo to set the appropriate
3651 ;; This must come before the movdf pattern, and it must be present
3652 ;; to handle obscure reloading cases.
3654 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3655 (match_operand:DF 1 "" "?F,m"))]
3656 "GET_CODE (operands[1]) == CONST_DOUBLE
3657 && operands[1] != CONST0_RTX (DFmode)
3659 && !TARGET_SOFT_FLOAT"
3660 "* return (which_alternative == 0 ? output_move_double (operands)
3661 : \"fldd%F1 %1,%0\");"
3662 [(set_attr "type" "move,fpload")
3663 (set_attr "length" "16,4")])
3665 (define_expand "movdf"
3666 [(set (match_operand:DF 0 "general_operand" "")
3667 (match_operand:DF 1 "general_operand" ""))]
3671 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3672 operands[1] = force_const_mem (DFmode, operands[1]);
3674 if (emit_move_sequence (operands, DFmode, 0))
3678 ;; Reloading an SImode or DImode value requires a scratch register if
3679 ;; going in to or out of float point registers.
3681 (define_expand "reload_indf"
3682 [(set (match_operand:DF 0 "register_operand" "=Z")
3683 (match_operand:DF 1 "non_hard_reg_operand" ""))
3684 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3688 if (emit_move_sequence (operands, DFmode, operands[2]))
3691 /* We don't want the clobber emitted, so handle this ourselves. */
3692 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3696 (define_expand "reload_outdf"
3697 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3698 (match_operand:DF 1 "register_operand" "Z"))
3699 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3703 if (emit_move_sequence (operands, DFmode, operands[2]))
3706 /* We don't want the clobber emitted, so handle this ourselves. */
3707 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3712 [(set (match_operand:DF 0 "move_dest_operand"
3713 "=f,*r,Q,?o,?Q,f,*r,*r")
3714 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3715 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3716 "(register_operand (operands[0], DFmode)
3717 || reg_or_0_operand (operands[1], DFmode))
3718 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3719 && GET_CODE (operands[0]) == MEM)
3721 && !TARGET_SOFT_FLOAT"
3724 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3725 || operands[1] == CONST0_RTX (DFmode))
3726 return output_fp_move_double (operands);
3727 return output_move_double (operands);
3729 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3730 (set_attr "length" "4,8,4,8,16,4,8,16")])
3733 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3734 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3736 && !TARGET_DISABLE_INDEXING
3737 && reload_completed"
3739 [(set_attr "type" "fpstore")
3740 (set_attr "pa_combine_type" "addmove")
3741 (set_attr "length" "4")])
3744 [(set (match_operand:SI 0 "register_operand" "")
3745 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3747 (match_operand:SI 2 "register_operand" "")))
3748 (set (mem:DF (match_dup 0))
3749 (match_operand:DF 3 "register_operand" ""))]
3751 && REG_OK_FOR_BASE_P (operands[2])
3752 && FP_REGNO_P (REGNO (operands[3]))"
3753 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3755 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3760 [(set (match_operand:SI 0 "register_operand" "")
3761 (plus:SI (match_operand:SI 2 "register_operand" "")
3762 (mult:SI (match_operand:SI 1 "register_operand" "")
3764 (set (mem:DF (match_dup 0))
3765 (match_operand:DF 3 "register_operand" ""))]
3767 && REG_OK_FOR_BASE_P (operands[2])
3768 && FP_REGNO_P (REGNO (operands[3]))"
3769 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3771 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3776 [(set (match_operand:DI 0 "register_operand" "")
3777 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3779 (match_operand:DI 2 "register_operand" "")))
3780 (set (mem:DF (match_dup 0))
3781 (match_operand:DF 3 "register_operand" ""))]
3784 && REG_OK_FOR_BASE_P (operands[2])
3785 && FP_REGNO_P (REGNO (operands[3]))"
3786 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3788 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3793 [(set (match_operand:DI 0 "register_operand" "")
3794 (plus:DI (match_operand:DI 2 "register_operand" "")
3795 (mult:DI (match_operand:DI 1 "register_operand" "")
3797 (set (mem:DF (match_dup 0))
3798 (match_operand:DF 3 "register_operand" ""))]
3801 && REG_OK_FOR_BASE_P (operands[2])
3802 && FP_REGNO_P (REGNO (operands[3]))"
3803 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3805 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3810 [(set (match_operand:SI 0 "register_operand" "")
3811 (plus:SI (match_operand:SI 1 "register_operand" "")
3812 (match_operand:SI 2 "register_operand" "")))
3813 (set (mem:DF (match_dup 0))
3814 (match_operand:DF 3 "register_operand" ""))]
3816 && REG_OK_FOR_BASE_P (operands[1])
3817 && (TARGET_NO_SPACE_REGS
3818 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3819 && FP_REGNO_P (REGNO (operands[3]))"
3820 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3822 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3826 [(set (match_operand:SI 0 "register_operand" "")
3827 (plus:SI (match_operand:SI 1 "register_operand" "")
3828 (match_operand:SI 2 "register_operand" "")))
3829 (set (mem:DF (match_dup 0))
3830 (match_operand:DF 3 "register_operand" ""))]
3832 && REG_OK_FOR_BASE_P (operands[2])
3833 && (TARGET_NO_SPACE_REGS
3834 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3835 && FP_REGNO_P (REGNO (operands[3]))"
3836 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3838 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3842 [(set (match_operand:DI 0 "register_operand" "")
3843 (plus:DI (match_operand:DI 1 "register_operand" "")
3844 (match_operand:DI 2 "register_operand" "")))
3845 (set (mem:DF (match_dup 0))
3846 (match_operand:DF 3 "register_operand" ""))]
3849 && REG_OK_FOR_BASE_P (operands[1])
3850 && (TARGET_NO_SPACE_REGS
3851 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3852 && FP_REGNO_P (REGNO (operands[3]))"
3853 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3855 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3859 [(set (match_operand:DI 0 "register_operand" "")
3860 (plus:DI (match_operand:DI 1 "register_operand" "")
3861 (match_operand:DI 2 "register_operand" "")))
3862 (set (mem:DF (match_dup 0))
3863 (match_operand:DF 3 "register_operand" ""))]
3866 && REG_OK_FOR_BASE_P (operands[2])
3867 && (TARGET_NO_SPACE_REGS
3868 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3869 && FP_REGNO_P (REGNO (operands[3]))"
3870 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3872 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3876 [(set (match_operand:DF 0 "move_dest_operand"
3878 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3880 "(register_operand (operands[0], DFmode)
3881 || reg_or_0_operand (operands[1], DFmode))
3883 && TARGET_SOFT_FLOAT"
3886 return output_move_double (operands);
3888 [(set_attr "type" "move,store,store,load,load")
3889 (set_attr "length" "8,8,16,8,16")])
3892 [(set (match_operand:DF 0 "move_dest_operand"
3893 "=!*r,*r,*r,*r,*r,Q,!*q,f,f,T")
3894 (match_operand:DF 1 "move_src_operand"
3895 "!*r,J,N,K,RQ,*rM,!*rM,fM,RT,f"))]
3896 "(register_operand (operands[0], DFmode)
3897 || reg_or_0_operand (operands[1], DFmode))
3898 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3910 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3911 (set_attr "pa_combine_type" "addmove")
3912 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3915 (define_expand "movdi"
3916 [(set (match_operand:DI 0 "general_operand" "")
3917 (match_operand:DI 1 "general_operand" ""))]
3921 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3922 operands[1] = force_const_mem (DImode, operands[1]);
3924 if (emit_move_sequence (operands, DImode, 0))
3928 (define_expand "reload_indi"
3929 [(set (match_operand:DI 0 "register_operand" "=Z")
3930 (match_operand:DI 1 "non_hard_reg_operand" ""))
3931 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3935 if (emit_move_sequence (operands, DImode, operands[2]))
3938 /* We don't want the clobber emitted, so handle this ourselves. */
3939 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3943 (define_expand "reload_outdi"
3944 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
3945 (match_operand:DI 1 "register_operand" "Z"))
3946 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3950 if (emit_move_sequence (operands, DImode, operands[2]))
3953 /* We don't want the clobber emitted, so handle this ourselves. */
3954 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3959 [(set (match_operand:DI 0 "register_operand" "=r")
3960 (high:DI (match_operand 1 "" "")))]
3964 rtx op0 = operands[0];
3965 rtx op1 = operands[1];
3967 if (GET_CODE (op1) == CONST_INT)
3969 operands[0] = operand_subword (op0, 1, 0, DImode);
3970 output_asm_insn (\"ldil L'%1,%0\", operands);
3972 operands[0] = operand_subword (op0, 0, 0, DImode);
3973 if (INTVAL (op1) < 0)
3974 output_asm_insn (\"ldi -1,%0\", operands);
3976 output_asm_insn (\"ldi 0,%0\", operands);
3979 else if (GET_CODE (op1) == CONST_DOUBLE)
3981 operands[0] = operand_subword (op0, 1, 0, DImode);
3982 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3983 output_asm_insn (\"ldil L'%1,%0\", operands);
3985 operands[0] = operand_subword (op0, 0, 0, DImode);
3986 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3987 output_asm_insn (singlemove_string (operands), operands);
3993 [(set_attr "type" "move")
3994 (set_attr "length" "8")])
3997 [(set (match_operand:DI 0 "move_dest_operand"
3998 "=r,o,Q,r,r,r,*f,*f,T")
3999 (match_operand:DI 1 "general_operand"
4000 "rM,r,r,o*R,Q,i,*fM,RT,*f"))]
4001 "(register_operand (operands[0], DImode)
4002 || reg_or_0_operand (operands[1], DImode))
4004 && !TARGET_SOFT_FLOAT"
4007 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4008 || (operands[1] == CONST0_RTX (DImode)))
4009 return output_fp_move_double (operands);
4010 return output_move_double (operands);
4012 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
4013 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
4016 [(set (match_operand:DI 0 "move_dest_operand"
4017 "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
4018 (match_operand:DI 1 "move_src_operand"
4019 "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
4020 "(register_operand (operands[0], DImode)
4021 || reg_or_0_operand (operands[1], DImode))
4022 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4035 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
4036 (set_attr "pa_combine_type" "addmove")
4037 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
4040 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4041 (match_operand:DI 1 "register_operand" "f"))]
4044 && !TARGET_DISABLE_INDEXING
4045 && reload_completed"
4047 [(set_attr "type" "fpstore")
4048 (set_attr "pa_combine_type" "addmove")
4049 (set_attr "length" "4")])
4052 [(set (match_operand:DI 0 "register_operand" "")
4053 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4055 (match_operand:DI 2 "register_operand" "")))
4056 (set (mem:DI (match_dup 0))
4057 (match_operand:DI 3 "register_operand" ""))]
4060 && REG_OK_FOR_BASE_P (operands[2])
4061 && FP_REGNO_P (REGNO (operands[3]))"
4062 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4064 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4069 [(set (match_operand:DI 0 "register_operand" "")
4070 (plus:DI (match_operand:DI 2 "register_operand" "")
4071 (mult:DI (match_operand:DI 1 "register_operand" "")
4073 (set (mem:DI (match_dup 0))
4074 (match_operand:DI 3 "register_operand" ""))]
4077 && REG_OK_FOR_BASE_P (operands[2])
4078 && FP_REGNO_P (REGNO (operands[3]))"
4079 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4081 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4086 [(set (match_operand:DI 0 "register_operand" "")
4087 (plus:DI (match_operand:DI 1 "register_operand" "")
4088 (match_operand:DI 2 "register_operand" "")))
4089 (set (mem:DI (match_dup 0))
4090 (match_operand:DI 3 "register_operand" ""))]
4093 && REG_OK_FOR_BASE_P (operands[1])
4094 && (TARGET_NO_SPACE_REGS
4095 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4096 && FP_REGNO_P (REGNO (operands[3]))"
4097 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4099 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4103 [(set (match_operand:DI 0 "register_operand" "")
4104 (plus:DI (match_operand:DI 1 "register_operand" "")
4105 (match_operand:DI 2 "register_operand" "")))
4106 (set (mem:DI (match_dup 0))
4107 (match_operand:DI 3 "register_operand" ""))]
4110 && REG_OK_FOR_BASE_P (operands[2])
4111 && (TARGET_NO_SPACE_REGS
4112 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4113 && FP_REGNO_P (REGNO (operands[3]))"
4114 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4116 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4120 [(set (match_operand:DI 0 "move_dest_operand"
4122 (match_operand:DI 1 "general_operand"
4124 "(register_operand (operands[0], DImode)
4125 || reg_or_0_operand (operands[1], DImode))
4127 && TARGET_SOFT_FLOAT"
4130 return output_move_double (operands);
4132 [(set_attr "type" "move,store,store,load,load,multi")
4133 (set_attr "length" "8,8,16,8,16,16")])
4136 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4137 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4138 (match_operand:DI 2 "immediate_operand" "i,i")))]
4142 /* Don't output a 64 bit constant, since we can't trust the assembler to
4143 handle it correctly. */
4144 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4145 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4146 if (which_alternative == 1)
4147 output_asm_insn (\"copy %1,%0\", operands);
4148 return \"ldo R'%G2(%R1),%R0\";
4150 [(set_attr "type" "move,move")
4151 (set_attr "length" "4,8")])
4153 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4154 ;; to be reloaded by putting the constant into memory when
4155 ;; reg is a floating point register.
4157 ;; For integer registers we use ldil;ldo to set the appropriate
4160 ;; This must come before the movsf pattern, and it must be present
4161 ;; to handle obscure reloading cases.
4163 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4164 (match_operand:SF 1 "" "?F,m"))]
4165 "GET_CODE (operands[1]) == CONST_DOUBLE
4166 && operands[1] != CONST0_RTX (SFmode)
4167 && ! TARGET_SOFT_FLOAT"
4168 "* return (which_alternative == 0 ? singlemove_string (operands)
4169 : \" fldw%F1 %1,%0\");"
4170 [(set_attr "type" "move,fpload")
4171 (set_attr "length" "8,4")])
4173 (define_expand "movsf"
4174 [(set (match_operand:SF 0 "general_operand" "")
4175 (match_operand:SF 1 "general_operand" ""))]
4179 if (emit_move_sequence (operands, SFmode, 0))
4183 ;; Reloading an SImode or DImode value requires a scratch register if
4184 ;; going in to or out of float point registers.
4186 (define_expand "reload_insf"
4187 [(set (match_operand:SF 0 "register_operand" "=Z")
4188 (match_operand:SF 1 "non_hard_reg_operand" ""))
4189 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4193 if (emit_move_sequence (operands, SFmode, operands[2]))
4196 /* We don't want the clobber emitted, so handle this ourselves. */
4197 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4201 (define_expand "reload_outsf"
4202 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4203 (match_operand:SF 1 "register_operand" "Z"))
4204 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4208 if (emit_move_sequence (operands, SFmode, operands[2]))
4211 /* We don't want the clobber emitted, so handle this ourselves. */
4212 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4217 [(set (match_operand:SF 0 "move_dest_operand"
4219 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4220 "fG,!*rG,RQ,RQ,f,*rG"))]
4221 "(register_operand (operands[0], SFmode)
4222 || reg_or_0_operand (operands[1], SFmode))
4223 && !TARGET_SOFT_FLOAT"
4231 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4232 (set_attr "pa_combine_type" "addmove")
4233 (set_attr "length" "4,4,4,4,4,4")])
4236 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4237 (match_operand:SF 1 "register_operand" "f"))]
4239 && !TARGET_DISABLE_INDEXING
4240 && reload_completed"
4242 [(set_attr "type" "fpstore")
4243 (set_attr "pa_combine_type" "addmove")
4244 (set_attr "length" "4")])
4247 [(set (match_operand:SI 0 "register_operand" "")
4248 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4250 (match_operand:SI 2 "register_operand" "")))
4251 (set (mem:SF (match_dup 0))
4252 (match_operand:SF 3 "register_operand" ""))]
4254 && REG_OK_FOR_BASE_P (operands[2])
4255 && FP_REGNO_P (REGNO (operands[3]))"
4256 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4258 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4263 [(set (match_operand:SI 0 "register_operand" "")
4264 (plus:SI (match_operand:SI 2 "register_operand" "")
4265 (mult:SI (match_operand:SI 1 "register_operand" "")
4267 (set (mem:SF (match_dup 0))
4268 (match_operand:SF 3 "register_operand" ""))]
4270 && REG_OK_FOR_BASE_P (operands[2])
4271 && FP_REGNO_P (REGNO (operands[3]))"
4272 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4274 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4279 [(set (match_operand:DI 0 "register_operand" "")
4280 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4282 (match_operand:DI 2 "register_operand" "")))
4283 (set (mem:SF (match_dup 0))
4284 (match_operand:SF 3 "register_operand" ""))]
4287 && REG_OK_FOR_BASE_P (operands[2])
4288 && FP_REGNO_P (REGNO (operands[3]))"
4289 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4291 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4296 [(set (match_operand:DI 0 "register_operand" "")
4297 (plus:DI (match_operand:DI 2 "register_operand" "")
4298 (mult:DI (match_operand:DI 1 "register_operand" "")
4300 (set (mem:SF (match_dup 0))
4301 (match_operand:SF 3 "register_operand" ""))]
4304 && REG_OK_FOR_BASE_P (operands[2])
4305 && FP_REGNO_P (REGNO (operands[3]))"
4306 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4308 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4313 [(set (match_operand:SI 0 "register_operand" "")
4314 (plus:SI (match_operand:SI 1 "register_operand" "")
4315 (match_operand:SI 2 "register_operand" "")))
4316 (set (mem:SF (match_dup 0))
4317 (match_operand:SF 3 "register_operand" ""))]
4319 && REG_OK_FOR_BASE_P (operands[1])
4320 && (TARGET_NO_SPACE_REGS
4321 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4322 && FP_REGNO_P (REGNO (operands[3]))"
4323 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4325 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4329 [(set (match_operand:SI 0 "register_operand" "")
4330 (plus:SI (match_operand:SI 1 "register_operand" "")
4331 (match_operand:SI 2 "register_operand" "")))
4332 (set (mem:SF (match_dup 0))
4333 (match_operand:SF 3 "register_operand" ""))]
4335 && REG_OK_FOR_BASE_P (operands[2])
4336 && (TARGET_NO_SPACE_REGS
4337 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4338 && FP_REGNO_P (REGNO (operands[3]))"
4339 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4341 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4345 [(set (match_operand:DI 0 "register_operand" "")
4346 (plus:DI (match_operand:DI 1 "register_operand" "")
4347 (match_operand:DI 2 "register_operand" "")))
4348 (set (mem:SF (match_dup 0))
4349 (match_operand:SF 3 "register_operand" ""))]
4352 && REG_OK_FOR_BASE_P (operands[1])
4353 && (TARGET_NO_SPACE_REGS
4354 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4355 && FP_REGNO_P (REGNO (operands[3]))"
4356 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4358 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4362 [(set (match_operand:DI 0 "register_operand" "")
4363 (plus:DI (match_operand:DI 1 "register_operand" "")
4364 (match_operand:DI 2 "register_operand" "")))
4365 (set (mem:SF (match_dup 0))
4366 (match_operand:SF 3 "register_operand" ""))]
4369 && REG_OK_FOR_BASE_P (operands[2])
4370 && (TARGET_NO_SPACE_REGS
4371 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4372 && FP_REGNO_P (REGNO (operands[3]))"
4373 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4375 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4379 [(set (match_operand:SF 0 "move_dest_operand"
4381 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4383 "(register_operand (operands[0], SFmode)
4384 || reg_or_0_operand (operands[1], SFmode))
4385 && TARGET_SOFT_FLOAT"
4390 [(set_attr "type" "move,load,store")
4391 (set_attr "pa_combine_type" "addmove")
4392 (set_attr "length" "4,4,4")])
4396 ;;- zero extension instructions
4397 ;; We have define_expand for zero extension patterns to make sure the
4398 ;; operands get loaded into registers. The define_insns accept
4399 ;; memory operands. This gives us better overall code than just
4400 ;; having a pattern that does or does not accept memory operands.
4402 (define_expand "zero_extendqihi2"
4403 [(set (match_operand:HI 0 "register_operand" "")
4405 (match_operand:QI 1 "register_operand" "")))]
4410 [(set (match_operand:HI 0 "register_operand" "=r,r")
4412 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4413 "GET_CODE (operands[1]) != CONST_INT"
4415 {extru|extrw,u} %1,31,8,%0
4417 [(set_attr "type" "shift,load")
4418 (set_attr "length" "4,4")])
4420 (define_expand "zero_extendqisi2"
4421 [(set (match_operand:SI 0 "register_operand" "")
4423 (match_operand:QI 1 "register_operand" "")))]
4428 [(set (match_operand:SI 0 "register_operand" "=r,r")
4430 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4431 "GET_CODE (operands[1]) != CONST_INT"
4433 {extru|extrw,u} %1,31,8,%0
4435 [(set_attr "type" "shift,load")
4436 (set_attr "length" "4,4")])
4438 (define_expand "zero_extendhisi2"
4439 [(set (match_operand:SI 0 "register_operand" "")
4441 (match_operand:HI 1 "register_operand" "")))]
4446 [(set (match_operand:SI 0 "register_operand" "=r,r")
4448 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4449 "GET_CODE (operands[1]) != CONST_INT"
4451 {extru|extrw,u} %1,31,16,%0
4453 [(set_attr "type" "shift,load")
4454 (set_attr "length" "4,4")])
4456 (define_expand "zero_extendqidi2"
4457 [(set (match_operand:DI 0 "register_operand" "")
4459 (match_operand:QI 1 "register_operand" "")))]
4464 [(set (match_operand:DI 0 "register_operand" "=r,r")
4466 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4467 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4471 [(set_attr "type" "shift,load")
4472 (set_attr "length" "4,4")])
4474 (define_expand "zero_extendhidi2"
4475 [(set (match_operand:DI 0 "register_operand" "")
4477 (match_operand:HI 1 "register_operand" "")))]
4482 [(set (match_operand:DI 0 "register_operand" "=r,r")
4484 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4485 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4489 [(set_attr "type" "shift,load")
4490 (set_attr "length" "4,4")])
4492 (define_expand "zero_extendsidi2"
4493 [(set (match_operand:DI 0 "register_operand" "")
4495 (match_operand:SI 1 "register_operand" "")))]
4500 [(set (match_operand:DI 0 "register_operand" "=r,r")
4502 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4503 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4507 [(set_attr "type" "shift,load")
4508 (set_attr "length" "4,4")])
4510 ;;- sign extension instructions
4512 (define_insn "extendhisi2"
4513 [(set (match_operand:SI 0 "register_operand" "=r")
4514 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4516 "{extrs|extrw,s} %1,31,16,%0"
4517 [(set_attr "type" "shift")
4518 (set_attr "length" "4")])
4520 (define_insn "extendqihi2"
4521 [(set (match_operand:HI 0 "register_operand" "=r")
4522 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4524 "{extrs|extrw,s} %1,31,8,%0"
4525 [(set_attr "type" "shift")
4526 (set_attr "length" "4")])
4528 (define_insn "extendqisi2"
4529 [(set (match_operand:SI 0 "register_operand" "=r")
4530 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4532 "{extrs|extrw,s} %1,31,8,%0"
4533 [(set_attr "type" "shift")
4534 (set_attr "length" "4")])
4536 (define_insn "extendqidi2"
4537 [(set (match_operand:DI 0 "register_operand" "=r")
4538 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4540 "extrd,s %1,63,8,%0"
4541 [(set_attr "type" "shift")
4542 (set_attr "length" "4")])
4544 (define_insn "extendhidi2"
4545 [(set (match_operand:DI 0 "register_operand" "=r")
4546 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4548 "extrd,s %1,63,16,%0"
4549 [(set_attr "type" "shift")
4550 (set_attr "length" "4")])
4552 (define_insn "extendsidi2"
4553 [(set (match_operand:DI 0 "register_operand" "=r")
4554 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4556 "extrd,s %1,63,32,%0"
4557 [(set_attr "type" "shift")
4558 (set_attr "length" "4")])
4561 ;; Conversions between float and double.
4563 (define_insn "extendsfdf2"
4564 [(set (match_operand:DF 0 "register_operand" "=f")
4566 (match_operand:SF 1 "register_operand" "f")))]
4567 "! TARGET_SOFT_FLOAT"
4568 "{fcnvff|fcnv},sgl,dbl %1,%0"
4569 [(set_attr "type" "fpalu")
4570 (set_attr "length" "4")])
4572 (define_insn "truncdfsf2"
4573 [(set (match_operand:SF 0 "register_operand" "=f")
4575 (match_operand:DF 1 "register_operand" "f")))]
4576 "! TARGET_SOFT_FLOAT"
4577 "{fcnvff|fcnv},dbl,sgl %1,%0"
4578 [(set_attr "type" "fpalu")
4579 (set_attr "length" "4")])
4581 ;; Conversion between fixed point and floating point.
4582 ;; Note that among the fix-to-float insns
4583 ;; the ones that start with SImode come first.
4584 ;; That is so that an operand that is a CONST_INT
4585 ;; (and therefore lacks a specific machine mode).
4586 ;; will be recognized as SImode (which is always valid)
4587 ;; rather than as QImode or HImode.
4589 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4590 ;; to be reloaded by putting the constant into memory.
4591 ;; It must come before the more general floatsisf2 pattern.
4593 [(set (match_operand:SF 0 "register_operand" "=f")
4594 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4595 "! TARGET_SOFT_FLOAT"
4596 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4597 [(set_attr "type" "fpalu")
4598 (set_attr "length" "8")])
4600 (define_insn "floatsisf2"
4601 [(set (match_operand:SF 0 "register_operand" "=f")
4602 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4603 "! TARGET_SOFT_FLOAT"
4604 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4605 [(set_attr "type" "fpalu")
4606 (set_attr "length" "4")])
4608 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4609 ;; to be reloaded by putting the constant into memory.
4610 ;; It must come before the more general floatsidf2 pattern.
4612 [(set (match_operand:DF 0 "register_operand" "=f")
4613 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4614 "! TARGET_SOFT_FLOAT"
4615 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4616 [(set_attr "type" "fpalu")
4617 (set_attr "length" "8")])
4619 (define_insn "floatsidf2"
4620 [(set (match_operand:DF 0 "register_operand" "=f")
4621 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4622 "! TARGET_SOFT_FLOAT"
4623 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4624 [(set_attr "type" "fpalu")
4625 (set_attr "length" "4")])
4627 (define_expand "floatunssisf2"
4628 [(set (subreg:SI (match_dup 2) 4)
4629 (match_operand:SI 1 "register_operand" ""))
4630 (set (subreg:SI (match_dup 2) 0)
4632 (set (match_operand:SF 0 "register_operand" "")
4633 (float:SF (match_dup 2)))]
4634 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4639 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4642 operands[2] = gen_reg_rtx (DImode);
4645 (define_expand "floatunssidf2"
4646 [(set (subreg:SI (match_dup 2) 4)
4647 (match_operand:SI 1 "register_operand" ""))
4648 (set (subreg:SI (match_dup 2) 0)
4650 (set (match_operand:DF 0 "register_operand" "")
4651 (float:DF (match_dup 2)))]
4652 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4657 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4660 operands[2] = gen_reg_rtx (DImode);
4663 (define_insn "floatdisf2"
4664 [(set (match_operand:SF 0 "register_operand" "=f")
4665 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4666 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4667 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4668 [(set_attr "type" "fpalu")
4669 (set_attr "length" "4")])
4671 (define_insn "floatdidf2"
4672 [(set (match_operand:DF 0 "register_operand" "=f")
4673 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4674 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4675 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4676 [(set_attr "type" "fpalu")
4677 (set_attr "length" "4")])
4679 ;; Convert a float to an actual integer.
4680 ;; Truncation is performed as part of the conversion.
4682 (define_insn "fix_truncsfsi2"
4683 [(set (match_operand:SI 0 "register_operand" "=f")
4684 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4685 "! TARGET_SOFT_FLOAT"
4686 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4687 [(set_attr "type" "fpalu")
4688 (set_attr "length" "4")])
4690 (define_insn "fix_truncdfsi2"
4691 [(set (match_operand:SI 0 "register_operand" "=f")
4692 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4693 "! TARGET_SOFT_FLOAT"
4694 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4695 [(set_attr "type" "fpalu")
4696 (set_attr "length" "4")])
4698 (define_insn "fix_truncsfdi2"
4699 [(set (match_operand:DI 0 "register_operand" "=f")
4700 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4701 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4702 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4703 [(set_attr "type" "fpalu")
4704 (set_attr "length" "4")])
4706 (define_insn "fix_truncdfdi2"
4707 [(set (match_operand:DI 0 "register_operand" "=f")
4708 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4709 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4710 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4711 [(set_attr "type" "fpalu")
4712 (set_attr "length" "4")])
4714 (define_insn "floatunssidf2_pa20"
4715 [(set (match_operand:DF 0 "register_operand" "=f")
4716 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4717 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4719 [(set_attr "type" "fpalu")
4720 (set_attr "length" "4")])
4722 (define_insn "floatunssisf2_pa20"
4723 [(set (match_operand:SF 0 "register_operand" "=f")
4724 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4725 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4727 [(set_attr "type" "fpalu")
4728 (set_attr "length" "4")])
4730 (define_insn "floatunsdisf2"
4731 [(set (match_operand:SF 0 "register_operand" "=f")
4732 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4733 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4734 "fcnv,udw,sgl %1,%0"
4735 [(set_attr "type" "fpalu")
4736 (set_attr "length" "4")])
4738 (define_insn "floatunsdidf2"
4739 [(set (match_operand:DF 0 "register_operand" "=f")
4740 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4741 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4742 "fcnv,udw,dbl %1,%0"
4743 [(set_attr "type" "fpalu")
4744 (set_attr "length" "4")])
4746 (define_insn "fixuns_truncsfsi2"
4747 [(set (match_operand:SI 0 "register_operand" "=f")
4748 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4749 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4750 "fcnv,t,sgl,uw %1,%0"
4751 [(set_attr "type" "fpalu")
4752 (set_attr "length" "4")])
4754 (define_insn "fixuns_truncdfsi2"
4755 [(set (match_operand:SI 0 "register_operand" "=f")
4756 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4757 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4758 "fcnv,t,dbl,uw %1,%0"
4759 [(set_attr "type" "fpalu")
4760 (set_attr "length" "4")])
4762 (define_insn "fixuns_truncsfdi2"
4763 [(set (match_operand:DI 0 "register_operand" "=f")
4764 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4765 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4766 "fcnv,t,sgl,udw %1,%0"
4767 [(set_attr "type" "fpalu")
4768 (set_attr "length" "4")])
4770 (define_insn "fixuns_truncdfdi2"
4771 [(set (match_operand:DI 0 "register_operand" "=f")
4772 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4773 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4774 "fcnv,t,dbl,udw %1,%0"
4775 [(set_attr "type" "fpalu")
4776 (set_attr "length" "4")])
4778 ;;- arithmetic instructions
4780 (define_expand "adddi3"
4781 [(set (match_operand:DI 0 "register_operand" "")
4782 (plus:DI (match_operand:DI 1 "register_operand" "")
4783 (match_operand:DI 2 "adddi3_operand" "")))]
4788 [(set (match_operand:DI 0 "register_operand" "=r")
4789 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4790 (match_operand:DI 2 "arith11_operand" "rI")))]
4794 if (GET_CODE (operands[2]) == CONST_INT)
4796 if (INTVAL (operands[2]) >= 0)
4797 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4799 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4802 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4804 [(set_attr "type" "binary")
4805 (set_attr "length" "8")])
4808 [(set (match_operand:DI 0 "register_operand" "=r,r")
4809 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4810 (match_operand:DI 2 "arith_operand" "r,J")))]
4815 [(set_attr "type" "binary,binary")
4816 (set_attr "pa_combine_type" "addmove")
4817 (set_attr "length" "4,4")])
4820 [(set (match_operand:DI 0 "register_operand" "=r")
4821 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4822 (match_operand:DI 2 "register_operand" "r")))]
4825 [(set_attr "type" "binary")
4826 (set_attr "length" "4")])
4829 [(set (match_operand:SI 0 "register_operand" "=r")
4830 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4831 (match_operand:SI 2 "register_operand" "r")))]
4834 [(set_attr "type" "binary")
4835 (set_attr "length" "4")])
4837 ;; define_splits to optimize cases of adding a constant integer
4838 ;; to a register when the constant does not fit in 14 bits. */
4840 [(set (match_operand:SI 0 "register_operand" "")
4841 (plus:SI (match_operand:SI 1 "register_operand" "")
4842 (match_operand:SI 2 "const_int_operand" "")))
4843 (clobber (match_operand:SI 4 "register_operand" ""))]
4844 "! cint_ok_for_move (INTVAL (operands[2]))
4845 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4846 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4847 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4850 int val = INTVAL (operands[2]);
4851 int low = (val < 0) ? -0x2000 : 0x1fff;
4852 int rest = val - low;
4854 operands[2] = GEN_INT (rest);
4855 operands[3] = GEN_INT (low);
4859 [(set (match_operand:SI 0 "register_operand" "")
4860 (plus:SI (match_operand:SI 1 "register_operand" "")
4861 (match_operand:SI 2 "const_int_operand" "")))
4862 (clobber (match_operand:SI 4 "register_operand" ""))]
4863 "! cint_ok_for_move (INTVAL (operands[2]))"
4864 [(set (match_dup 4) (match_dup 2))
4865 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4869 HOST_WIDE_INT intval = INTVAL (operands[2]);
4871 /* Try dividing the constant by 2, then 4, and finally 8 to see
4872 if we can get a constant which can be loaded into a register
4873 in a single instruction (cint_ok_for_move).
4875 If that fails, try to negate the constant and subtract it
4876 from our input operand. */
4877 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4879 operands[2] = GEN_INT (intval / 2);
4880 operands[3] = GEN_INT (2);
4882 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
4884 operands[2] = GEN_INT (intval / 4);
4885 operands[3] = GEN_INT (4);
4887 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
4889 operands[2] = GEN_INT (intval / 8);
4890 operands[3] = GEN_INT (8);
4892 else if (cint_ok_for_move (-intval))
4894 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
4895 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
4902 (define_insn "addsi3"
4903 [(set (match_operand:SI 0 "register_operand" "=r,r")
4904 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
4905 (match_operand:SI 2 "arith_operand" "r,J")))]
4908 {addl|add,l} %1,%2,%0
4910 [(set_attr "type" "binary,binary")
4911 (set_attr "pa_combine_type" "addmove")
4912 (set_attr "length" "4,4")])
4914 (define_expand "subdi3"
4915 [(set (match_operand:DI 0 "register_operand" "")
4916 (minus:DI (match_operand:DI 1 "register_operand" "")
4917 (match_operand:DI 2 "register_operand" "")))]
4922 [(set (match_operand:DI 0 "register_operand" "=r")
4923 (minus:DI (match_operand:DI 1 "register_operand" "r")
4924 (match_operand:DI 2 "register_operand" "r")))]
4926 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
4927 [(set_attr "type" "binary")
4928 (set_attr "length" "8")])
4931 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
4932 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
4933 (match_operand:DI 2 "register_operand" "r,r,!r")))]
4939 [(set_attr "type" "binary,binary,move")
4940 (set_attr "length" "4,4,4")])
4942 (define_expand "subsi3"
4943 [(set (match_operand:SI 0 "register_operand" "")
4944 (minus:SI (match_operand:SI 1 "arith11_operand" "")
4945 (match_operand:SI 2 "register_operand" "")))]
4950 [(set (match_operand:SI 0 "register_operand" "=r,r")
4951 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
4952 (match_operand:SI 2 "register_operand" "r,r")))]
4957 [(set_attr "type" "binary,binary")
4958 (set_attr "length" "4,4")])
4961 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
4962 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
4963 (match_operand:SI 2 "register_operand" "r,r,!r")))]
4969 [(set_attr "type" "binary,binary,move")
4970 (set_attr "length" "4,4,4")])
4972 ;; Clobbering a "register_operand" instead of a match_scratch
4973 ;; in operand3 of millicode calls avoids spilling %r1 and
4974 ;; produces better code.
4976 ;; The mulsi3 insns set up registers for the millicode call.
4977 (define_expand "mulsi3"
4978 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
4979 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
4980 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4981 (clobber (match_dup 3))
4982 (clobber (reg:SI 26))
4983 (clobber (reg:SI 25))
4984 (clobber (match_dup 4))])
4985 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4989 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4990 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
4992 rtx scratch = gen_reg_rtx (DImode);
4993 operands[1] = force_reg (SImode, operands[1]);
4994 operands[2] = force_reg (SImode, operands[2]);
4995 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
4996 emit_insn (gen_movsi (operands[0],
4997 gen_rtx_SUBREG (SImode, scratch,
4998 GET_MODE_SIZE (SImode))));
5001 operands[3] = gen_reg_rtx (SImode);
5004 (define_insn "umulsidi3"
5005 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5006 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5007 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5008 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5010 [(set_attr "type" "fpmuldbl")
5011 (set_attr "length" "4")])
5014 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5015 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5016 (match_operand:DI 2 "uint32_operand" "f")))]
5017 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5019 [(set_attr "type" "fpmuldbl")
5020 (set_attr "length" "4")])
5023 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5024 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5025 (match_operand:DI 2 "uint32_operand" "f")))]
5026 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5028 [(set_attr "type" "fpmuldbl")
5029 (set_attr "length" "4")])
5032 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5033 (clobber (match_operand:SI 0 "register_operand" "=a"))
5034 (clobber (reg:SI 26))
5035 (clobber (reg:SI 25))
5036 (clobber (reg:SI 31))]
5038 "* return output_mul_insn (0, insn);"
5039 [(set_attr "type" "milli")
5040 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5043 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5044 (clobber (match_operand:SI 0 "register_operand" "=a"))
5045 (clobber (reg:SI 26))
5046 (clobber (reg:SI 25))
5047 (clobber (reg:SI 2))]
5049 "* return output_mul_insn (0, insn);"
5050 [(set_attr "type" "milli")
5051 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5053 (define_expand "muldi3"
5054 [(set (match_operand:DI 0 "register_operand" "")
5055 (mult:DI (match_operand:DI 1 "register_operand" "")
5056 (match_operand:DI 2 "register_operand" "")))]
5057 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5060 rtx low_product = gen_reg_rtx (DImode);
5061 rtx cross_product1 = gen_reg_rtx (DImode);
5062 rtx cross_product2 = gen_reg_rtx (DImode);
5063 rtx cross_scratch = gen_reg_rtx (DImode);
5064 rtx cross_product = gen_reg_rtx (DImode);
5065 rtx op1l, op1r, op2l, op2r;
5066 rtx op1shifted, op2shifted;
5068 op1shifted = gen_reg_rtx (DImode);
5069 op2shifted = gen_reg_rtx (DImode);
5070 op1l = gen_reg_rtx (SImode);
5071 op1r = gen_reg_rtx (SImode);
5072 op2l = gen_reg_rtx (SImode);
5073 op2r = gen_reg_rtx (SImode);
5075 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5077 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5079 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5080 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5081 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5082 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5084 /* Emit multiplies for the cross products. */
5085 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5086 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5088 /* Emit a multiply for the low sub-word. */
5089 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5091 /* Sum the cross products and shift them into proper position. */
5092 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5093 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5095 /* Add the cross product to the low product and store the result
5096 into the output operand . */
5097 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5101 ;;; Division and mod.
5102 (define_expand "divsi3"
5103 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5104 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5105 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5106 (clobber (match_dup 3))
5107 (clobber (match_dup 4))
5108 (clobber (reg:SI 26))
5109 (clobber (reg:SI 25))
5110 (clobber (match_dup 5))])
5111 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5115 operands[3] = gen_reg_rtx (SImode);
5118 operands[5] = gen_rtx_REG (SImode, 2);
5119 operands[4] = operands[5];
5123 operands[5] = gen_rtx_REG (SImode, 31);
5124 operands[4] = gen_reg_rtx (SImode);
5126 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5132 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5133 (clobber (match_operand:SI 1 "register_operand" "=a"))
5134 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5135 (clobber (reg:SI 26))
5136 (clobber (reg:SI 25))
5137 (clobber (reg:SI 31))]
5140 return output_div_insn (operands, 0, insn);"
5141 [(set_attr "type" "milli")
5142 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5146 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5147 (clobber (match_operand:SI 1 "register_operand" "=a"))
5148 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5149 (clobber (reg:SI 26))
5150 (clobber (reg:SI 25))
5151 (clobber (reg:SI 2))]
5154 return output_div_insn (operands, 0, insn);"
5155 [(set_attr "type" "milli")
5156 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5158 (define_expand "udivsi3"
5159 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5160 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5161 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5162 (clobber (match_dup 3))
5163 (clobber (match_dup 4))
5164 (clobber (reg:SI 26))
5165 (clobber (reg:SI 25))
5166 (clobber (match_dup 5))])
5167 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5171 operands[3] = gen_reg_rtx (SImode);
5175 operands[5] = gen_rtx_REG (SImode, 2);
5176 operands[4] = operands[5];
5180 operands[5] = gen_rtx_REG (SImode, 31);
5181 operands[4] = gen_reg_rtx (SImode);
5183 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5189 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5190 (clobber (match_operand:SI 1 "register_operand" "=a"))
5191 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5192 (clobber (reg:SI 26))
5193 (clobber (reg:SI 25))
5194 (clobber (reg:SI 31))]
5197 return output_div_insn (operands, 1, insn);"
5198 [(set_attr "type" "milli")
5199 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5203 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5204 (clobber (match_operand:SI 1 "register_operand" "=a"))
5205 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5206 (clobber (reg:SI 26))
5207 (clobber (reg:SI 25))
5208 (clobber (reg:SI 2))]
5211 return output_div_insn (operands, 1, insn);"
5212 [(set_attr "type" "milli")
5213 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5215 (define_expand "modsi3"
5216 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5217 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5218 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5219 (clobber (match_dup 3))
5220 (clobber (match_dup 4))
5221 (clobber (reg:SI 26))
5222 (clobber (reg:SI 25))
5223 (clobber (match_dup 5))])
5224 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5230 operands[5] = gen_rtx_REG (SImode, 2);
5231 operands[4] = operands[5];
5235 operands[5] = gen_rtx_REG (SImode, 31);
5236 operands[4] = gen_reg_rtx (SImode);
5238 operands[3] = gen_reg_rtx (SImode);
5242 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5243 (clobber (match_operand:SI 0 "register_operand" "=a"))
5244 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5245 (clobber (reg:SI 26))
5246 (clobber (reg:SI 25))
5247 (clobber (reg:SI 31))]
5250 return output_mod_insn (0, insn);"
5251 [(set_attr "type" "milli")
5252 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5255 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5256 (clobber (match_operand:SI 0 "register_operand" "=a"))
5257 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5258 (clobber (reg:SI 26))
5259 (clobber (reg:SI 25))
5260 (clobber (reg:SI 2))]
5263 return output_mod_insn (0, insn);"
5264 [(set_attr "type" "milli")
5265 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5267 (define_expand "umodsi3"
5268 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5269 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5270 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5271 (clobber (match_dup 3))
5272 (clobber (match_dup 4))
5273 (clobber (reg:SI 26))
5274 (clobber (reg:SI 25))
5275 (clobber (match_dup 5))])
5276 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5282 operands[5] = gen_rtx_REG (SImode, 2);
5283 operands[4] = operands[5];
5287 operands[5] = gen_rtx_REG (SImode, 31);
5288 operands[4] = gen_reg_rtx (SImode);
5290 operands[3] = gen_reg_rtx (SImode);
5294 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5295 (clobber (match_operand:SI 0 "register_operand" "=a"))
5296 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5297 (clobber (reg:SI 26))
5298 (clobber (reg:SI 25))
5299 (clobber (reg:SI 31))]
5302 return output_mod_insn (1, insn);"
5303 [(set_attr "type" "milli")
5304 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5307 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5308 (clobber (match_operand:SI 0 "register_operand" "=a"))
5309 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5310 (clobber (reg:SI 26))
5311 (clobber (reg:SI 25))
5312 (clobber (reg:SI 2))]
5315 return output_mod_insn (1, insn);"
5316 [(set_attr "type" "milli")
5317 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5319 ;;- and instructions
5320 ;; We define DImode `and` so with DImode `not` we can get
5321 ;; DImode `andn`. Other combinations are possible.
5323 (define_expand "anddi3"
5324 [(set (match_operand:DI 0 "register_operand" "")
5325 (and:DI (match_operand:DI 1 "arith_double_operand" "")
5326 (match_operand:DI 2 "arith_double_operand" "")))]
5330 if (! register_operand (operands[1], DImode)
5331 || ! register_operand (operands[2], DImode))
5332 /* Let GCC break this into word-at-a-time operations. */
5337 [(set (match_operand:DI 0 "register_operand" "=r")
5338 (and:DI (match_operand:DI 1 "register_operand" "%r")
5339 (match_operand:DI 2 "register_operand" "r")))]
5341 "and %1,%2,%0\;and %R1,%R2,%R0"
5342 [(set_attr "type" "binary")
5343 (set_attr "length" "8")])
5346 [(set (match_operand:DI 0 "register_operand" "=r,r")
5347 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5348 (match_operand:DI 2 "and_operand" "rO,P")))]
5350 "* return output_64bit_and (operands); "
5351 [(set_attr "type" "binary")
5352 (set_attr "length" "4")])
5354 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5355 ; constant with ldil;ldo.
5356 (define_insn "andsi3"
5357 [(set (match_operand:SI 0 "register_operand" "=r,r")
5358 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5359 (match_operand:SI 2 "and_operand" "rO,P")))]
5361 "* return output_and (operands); "
5362 [(set_attr "type" "binary,shift")
5363 (set_attr "length" "4,4")])
5366 [(set (match_operand:DI 0 "register_operand" "=r")
5367 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5368 (match_operand:DI 2 "register_operand" "r")))]
5370 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5371 [(set_attr "type" "binary")
5372 (set_attr "length" "8")])
5375 [(set (match_operand:DI 0 "register_operand" "=r")
5376 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5377 (match_operand:DI 2 "register_operand" "r")))]
5380 [(set_attr "type" "binary")
5381 (set_attr "length" "4")])
5384 [(set (match_operand:SI 0 "register_operand" "=r")
5385 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5386 (match_operand:SI 2 "register_operand" "r")))]
5389 [(set_attr "type" "binary")
5390 (set_attr "length" "4")])
5392 (define_expand "iordi3"
5393 [(set (match_operand:DI 0 "register_operand" "")
5394 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
5395 (match_operand:DI 2 "arith_double_operand" "")))]
5399 if (! register_operand (operands[1], DImode)
5400 || ! register_operand (operands[2], DImode))
5401 /* Let GCC break this into word-at-a-time operations. */
5406 [(set (match_operand:DI 0 "register_operand" "=r")
5407 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5408 (match_operand:DI 2 "register_operand" "r")))]
5410 "or %1,%2,%0\;or %R1,%R2,%R0"
5411 [(set_attr "type" "binary")
5412 (set_attr "length" "8")])
5415 [(set (match_operand:DI 0 "register_operand" "=r,r")
5416 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5417 (match_operand:DI 2 "ior_operand" "M,i")))]
5419 "* return output_64bit_ior (operands); "
5420 [(set_attr "type" "binary,shift")
5421 (set_attr "length" "4,4")])
5424 [(set (match_operand:DI 0 "register_operand" "=r")
5425 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5426 (match_operand:DI 2 "register_operand" "r")))]
5429 [(set_attr "type" "binary")
5430 (set_attr "length" "4")])
5432 ;; Need a define_expand because we've run out of CONST_OK... characters.
5433 (define_expand "iorsi3"
5434 [(set (match_operand:SI 0 "register_operand" "")
5435 (ior:SI (match_operand:SI 1 "register_operand" "")
5436 (match_operand:SI 2 "arith32_operand" "")))]
5440 if (! (ior_operand (operands[2], SImode)
5441 || register_operand (operands[2], SImode)))
5442 operands[2] = force_reg (SImode, operands[2]);
5446 [(set (match_operand:SI 0 "register_operand" "=r,r")
5447 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5448 (match_operand:SI 2 "ior_operand" "M,i")))]
5450 "* return output_ior (operands); "
5451 [(set_attr "type" "binary,shift")
5452 (set_attr "length" "4,4")])
5455 [(set (match_operand:SI 0 "register_operand" "=r")
5456 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5457 (match_operand:SI 2 "register_operand" "r")))]
5460 [(set_attr "type" "binary")
5461 (set_attr "length" "4")])
5463 (define_expand "xordi3"
5464 [(set (match_operand:DI 0 "register_operand" "")
5465 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
5466 (match_operand:DI 2 "arith_double_operand" "")))]
5470 if (! register_operand (operands[1], DImode)
5471 || ! register_operand (operands[2], DImode))
5472 /* Let GCC break this into word-at-a-time operations. */
5477 [(set (match_operand:DI 0 "register_operand" "=r")
5478 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5479 (match_operand:DI 2 "register_operand" "r")))]
5481 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5482 [(set_attr "type" "binary")
5483 (set_attr "length" "8")])
5486 [(set (match_operand:DI 0 "register_operand" "=r")
5487 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5488 (match_operand:DI 2 "register_operand" "r")))]
5491 [(set_attr "type" "binary")
5492 (set_attr "length" "4")])
5494 (define_insn "xorsi3"
5495 [(set (match_operand:SI 0 "register_operand" "=r")
5496 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5497 (match_operand:SI 2 "register_operand" "r")))]
5500 [(set_attr "type" "binary")
5501 (set_attr "length" "4")])
5503 (define_expand "negdi2"
5504 [(set (match_operand:DI 0 "register_operand" "")
5505 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5510 [(set (match_operand:DI 0 "register_operand" "=r")
5511 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5513 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5514 [(set_attr "type" "unary")
5515 (set_attr "length" "8")])
5518 [(set (match_operand:DI 0 "register_operand" "=r")
5519 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5522 [(set_attr "type" "unary")
5523 (set_attr "length" "4")])
5525 (define_insn "negsi2"
5526 [(set (match_operand:SI 0 "register_operand" "=r")
5527 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5530 [(set_attr "type" "unary")
5531 (set_attr "length" "4")])
5533 (define_expand "one_cmpldi2"
5534 [(set (match_operand:DI 0 "register_operand" "")
5535 (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
5539 if (! register_operand (operands[1], DImode))
5544 [(set (match_operand:DI 0 "register_operand" "=r")
5545 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5547 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5548 [(set_attr "type" "unary")
5549 (set_attr "length" "8")])
5552 [(set (match_operand:DI 0 "register_operand" "=r")
5553 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5556 [(set_attr "type" "unary")
5557 (set_attr "length" "4")])
5559 (define_insn "one_cmplsi2"
5560 [(set (match_operand:SI 0 "register_operand" "=r")
5561 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5564 [(set_attr "type" "unary")
5565 (set_attr "length" "4")])
5567 ;; Floating point arithmetic instructions.
5569 (define_insn "adddf3"
5570 [(set (match_operand:DF 0 "register_operand" "=f")
5571 (plus:DF (match_operand:DF 1 "register_operand" "f")
5572 (match_operand:DF 2 "register_operand" "f")))]
5573 "! TARGET_SOFT_FLOAT"
5575 [(set_attr "type" "fpalu")
5576 (set_attr "pa_combine_type" "faddsub")
5577 (set_attr "length" "4")])
5579 (define_insn "addsf3"
5580 [(set (match_operand:SF 0 "register_operand" "=f")
5581 (plus:SF (match_operand:SF 1 "register_operand" "f")
5582 (match_operand:SF 2 "register_operand" "f")))]
5583 "! TARGET_SOFT_FLOAT"
5585 [(set_attr "type" "fpalu")
5586 (set_attr "pa_combine_type" "faddsub")
5587 (set_attr "length" "4")])
5589 (define_insn "subdf3"
5590 [(set (match_operand:DF 0 "register_operand" "=f")
5591 (minus:DF (match_operand:DF 1 "register_operand" "f")
5592 (match_operand:DF 2 "register_operand" "f")))]
5593 "! TARGET_SOFT_FLOAT"
5595 [(set_attr "type" "fpalu")
5596 (set_attr "pa_combine_type" "faddsub")
5597 (set_attr "length" "4")])
5599 (define_insn "subsf3"
5600 [(set (match_operand:SF 0 "register_operand" "=f")
5601 (minus:SF (match_operand:SF 1 "register_operand" "f")
5602 (match_operand:SF 2 "register_operand" "f")))]
5603 "! TARGET_SOFT_FLOAT"
5605 [(set_attr "type" "fpalu")
5606 (set_attr "pa_combine_type" "faddsub")
5607 (set_attr "length" "4")])
5609 (define_insn "muldf3"
5610 [(set (match_operand:DF 0 "register_operand" "=f")
5611 (mult:DF (match_operand:DF 1 "register_operand" "f")
5612 (match_operand:DF 2 "register_operand" "f")))]
5613 "! TARGET_SOFT_FLOAT"
5615 [(set_attr "type" "fpmuldbl")
5616 (set_attr "pa_combine_type" "fmpy")
5617 (set_attr "length" "4")])
5619 (define_insn "mulsf3"
5620 [(set (match_operand:SF 0 "register_operand" "=f")
5621 (mult:SF (match_operand:SF 1 "register_operand" "f")
5622 (match_operand:SF 2 "register_operand" "f")))]
5623 "! TARGET_SOFT_FLOAT"
5625 [(set_attr "type" "fpmulsgl")
5626 (set_attr "pa_combine_type" "fmpy")
5627 (set_attr "length" "4")])
5629 (define_insn "divdf3"
5630 [(set (match_operand:DF 0 "register_operand" "=f")
5631 (div:DF (match_operand:DF 1 "register_operand" "f")
5632 (match_operand:DF 2 "register_operand" "f")))]
5633 "! TARGET_SOFT_FLOAT"
5635 [(set_attr "type" "fpdivdbl")
5636 (set_attr "length" "4")])
5638 (define_insn "divsf3"
5639 [(set (match_operand:SF 0 "register_operand" "=f")
5640 (div:SF (match_operand:SF 1 "register_operand" "f")
5641 (match_operand:SF 2 "register_operand" "f")))]
5642 "! TARGET_SOFT_FLOAT"
5644 [(set_attr "type" "fpdivsgl")
5645 (set_attr "length" "4")])
5647 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5648 ;; negation can be done by subtracting from plus zero. However, this
5649 ;; violates the IEEE standard when negating plus and minus zero.
5650 (define_expand "negdf2"
5651 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5652 (neg:DF (match_operand:DF 1 "register_operand" "")))
5653 (use (match_dup 2))])]
5654 "! TARGET_SOFT_FLOAT"
5656 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5657 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5660 operands[2] = force_reg (DFmode,
5661 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5662 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5667 (define_insn "negdf2_fast"
5668 [(set (match_operand:DF 0 "register_operand" "=f")
5669 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5670 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5674 return \"fneg,dbl %1,%0\";
5676 return \"fsub,dbl %%fr0,%1,%0\";
5678 [(set_attr "type" "fpalu")
5679 (set_attr "length" "4")])
5681 (define_expand "negsf2"
5682 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5683 (neg:SF (match_operand:SF 1 "register_operand" "")))
5684 (use (match_dup 2))])]
5685 "! TARGET_SOFT_FLOAT"
5687 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5688 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5691 operands[2] = force_reg (SFmode,
5692 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5693 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5698 (define_insn "negsf2_fast"
5699 [(set (match_operand:SF 0 "register_operand" "=f")
5700 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5701 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5705 return \"fneg,sgl %1,%0\";
5707 return \"fsub,sgl %%fr0,%1,%0\";
5709 [(set_attr "type" "fpalu")
5710 (set_attr "length" "4")])
5712 (define_insn "absdf2"
5713 [(set (match_operand:DF 0 "register_operand" "=f")
5714 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5715 "! TARGET_SOFT_FLOAT"
5717 [(set_attr "type" "fpalu")
5718 (set_attr "length" "4")])
5720 (define_insn "abssf2"
5721 [(set (match_operand:SF 0 "register_operand" "=f")
5722 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5723 "! TARGET_SOFT_FLOAT"
5725 [(set_attr "type" "fpalu")
5726 (set_attr "length" "4")])
5728 (define_insn "sqrtdf2"
5729 [(set (match_operand:DF 0 "register_operand" "=f")
5730 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5731 "! TARGET_SOFT_FLOAT"
5733 [(set_attr "type" "fpsqrtdbl")
5734 (set_attr "length" "4")])
5736 (define_insn "sqrtsf2"
5737 [(set (match_operand:SF 0 "register_operand" "=f")
5738 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5739 "! TARGET_SOFT_FLOAT"
5741 [(set_attr "type" "fpsqrtsgl")
5742 (set_attr "length" "4")])
5744 ;; PA 2.0 floating point instructions
5748 [(set (match_operand:DF 0 "register_operand" "=f")
5749 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5750 (match_operand:DF 2 "register_operand" "f"))
5751 (match_operand:DF 3 "register_operand" "f")))]
5752 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5753 "fmpyfadd,dbl %1,%2,%3,%0"
5754 [(set_attr "type" "fpmuldbl")
5755 (set_attr "length" "4")])
5758 [(set (match_operand:DF 0 "register_operand" "=f")
5759 (plus:DF (match_operand:DF 1 "register_operand" "f")
5760 (mult:DF (match_operand:DF 2 "register_operand" "f")
5761 (match_operand:DF 3 "register_operand" "f"))))]
5762 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5763 "fmpyfadd,dbl %2,%3,%1,%0"
5764 [(set_attr "type" "fpmuldbl")
5765 (set_attr "length" "4")])
5768 [(set (match_operand:SF 0 "register_operand" "=f")
5769 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5770 (match_operand:SF 2 "register_operand" "f"))
5771 (match_operand:SF 3 "register_operand" "f")))]
5772 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5773 "fmpyfadd,sgl %1,%2,%3,%0"
5774 [(set_attr "type" "fpmulsgl")
5775 (set_attr "length" "4")])
5778 [(set (match_operand:SF 0 "register_operand" "=f")
5779 (plus:SF (match_operand:SF 1 "register_operand" "f")
5780 (mult:SF (match_operand:SF 2 "register_operand" "f")
5781 (match_operand:SF 3 "register_operand" "f"))))]
5782 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5783 "fmpyfadd,sgl %2,%3,%1,%0"
5784 [(set_attr "type" "fpmulsgl")
5785 (set_attr "length" "4")])
5787 ; fmpynfadd patterns
5789 [(set (match_operand:DF 0 "register_operand" "=f")
5790 (minus:DF (match_operand:DF 1 "register_operand" "f")
5791 (mult:DF (match_operand:DF 2 "register_operand" "f")
5792 (match_operand:DF 3 "register_operand" "f"))))]
5793 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5794 "fmpynfadd,dbl %2,%3,%1,%0"
5795 [(set_attr "type" "fpmuldbl")
5796 (set_attr "length" "4")])
5799 [(set (match_operand:SF 0 "register_operand" "=f")
5800 (minus:SF (match_operand:SF 1 "register_operand" "f")
5801 (mult:SF (match_operand:SF 2 "register_operand" "f")
5802 (match_operand:SF 3 "register_operand" "f"))))]
5803 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5804 "fmpynfadd,sgl %2,%3,%1,%0"
5805 [(set_attr "type" "fpmulsgl")
5806 (set_attr "length" "4")])
5810 [(set (match_operand:DF 0 "register_operand" "=f")
5811 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
5812 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5814 [(set_attr "type" "fpalu")
5815 (set_attr "length" "4")])
5818 [(set (match_operand:SF 0 "register_operand" "=f")
5819 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
5820 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5822 [(set_attr "type" "fpalu")
5823 (set_attr "length" "4")])
5825 ;; Generating a fused multiply sequence is a win for this case as it will
5826 ;; reduce the latency for the fused case without impacting the plain
5829 ;; Similar possibilities exist for fnegabs, shadd and other insns which
5830 ;; perform two operations with the result of the first feeding the second.
5832 [(set (match_operand:DF 0 "register_operand" "=f")
5833 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5834 (match_operand:DF 2 "register_operand" "f"))
5835 (match_operand:DF 3 "register_operand" "f")))
5836 (set (match_operand:DF 4 "register_operand" "=&f")
5837 (mult:DF (match_dup 1) (match_dup 2)))]
5838 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5839 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5840 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5842 [(set_attr "type" "fpmuldbl")
5843 (set_attr "length" "8")])
5845 ;; We want to split this up during scheduling since we want both insns
5846 ;; to schedule independently.
5848 [(set (match_operand:DF 0 "register_operand" "")
5849 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5850 (match_operand:DF 2 "register_operand" ""))
5851 (match_operand:DF 3 "register_operand" "")))
5852 (set (match_operand:DF 4 "register_operand" "")
5853 (mult:DF (match_dup 1) (match_dup 2)))]
5854 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5855 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5856 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
5861 [(set (match_operand:SF 0 "register_operand" "=f")
5862 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5863 (match_operand:SF 2 "register_operand" "f"))
5864 (match_operand:SF 3 "register_operand" "f")))
5865 (set (match_operand:SF 4 "register_operand" "=&f")
5866 (mult:SF (match_dup 1) (match_dup 2)))]
5867 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5868 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5869 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5871 [(set_attr "type" "fpmuldbl")
5872 (set_attr "length" "8")])
5874 ;; We want to split this up during scheduling since we want both insns
5875 ;; to schedule independently.
5877 [(set (match_operand:SF 0 "register_operand" "")
5878 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5879 (match_operand:SF 2 "register_operand" ""))
5880 (match_operand:SF 3 "register_operand" "")))
5881 (set (match_operand:SF 4 "register_operand" "")
5882 (mult:SF (match_dup 1) (match_dup 2)))]
5883 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5884 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5885 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
5889 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
5892 [(set (match_operand:DF 0 "register_operand" "=f")
5893 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5894 (match_operand:DF 2 "register_operand" "f"))))]
5895 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5896 "fmpynfadd,dbl %1,%2,%%fr0,%0"
5897 [(set_attr "type" "fpmuldbl")
5898 (set_attr "length" "4")])
5901 [(set (match_operand:SF 0 "register_operand" "=f")
5902 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5903 (match_operand:SF 2 "register_operand" "f"))))]
5904 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5905 "fmpynfadd,sgl %1,%2,%%fr0,%0"
5906 [(set_attr "type" "fpmuldbl")
5907 (set_attr "length" "4")])
5910 [(set (match_operand:DF 0 "register_operand" "=f")
5911 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5912 (match_operand:DF 2 "register_operand" "f"))))
5913 (set (match_operand:DF 3 "register_operand" "=&f")
5914 (mult:DF (match_dup 1) (match_dup 2)))]
5915 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5916 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5917 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5919 [(set_attr "type" "fpmuldbl")
5920 (set_attr "length" "8")])
5923 [(set (match_operand:DF 0 "register_operand" "")
5924 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5925 (match_operand:DF 2 "register_operand" ""))))
5926 (set (match_operand:DF 3 "register_operand" "")
5927 (mult:DF (match_dup 1) (match_dup 2)))]
5928 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5929 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
5930 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
5934 [(set (match_operand:SF 0 "register_operand" "=f")
5935 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5936 (match_operand:SF 2 "register_operand" "f"))))
5937 (set (match_operand:SF 3 "register_operand" "=&f")
5938 (mult:SF (match_dup 1) (match_dup 2)))]
5939 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5940 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5941 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5943 [(set_attr "type" "fpmuldbl")
5944 (set_attr "length" "8")])
5947 [(set (match_operand:SF 0 "register_operand" "")
5948 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5949 (match_operand:SF 2 "register_operand" ""))))
5950 (set (match_operand:SF 3 "register_operand" "")
5951 (mult:SF (match_dup 1) (match_dup 2)))]
5952 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5953 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
5954 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
5957 ;; Now fused multiplies with the result of the multiply negated.
5959 [(set (match_operand:DF 0 "register_operand" "=f")
5960 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5961 (match_operand:DF 2 "register_operand" "f")))
5962 (match_operand:DF 3 "register_operand" "f")))]
5963 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5964 "fmpynfadd,dbl %1,%2,%3,%0"
5965 [(set_attr "type" "fpmuldbl")
5966 (set_attr "length" "4")])
5969 [(set (match_operand:SF 0 "register_operand" "=f")
5970 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5971 (match_operand:SF 2 "register_operand" "f")))
5972 (match_operand:SF 3 "register_operand" "f")))]
5973 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5974 "fmpynfadd,sgl %1,%2,%3,%0"
5975 [(set_attr "type" "fpmuldbl")
5976 (set_attr "length" "4")])
5979 [(set (match_operand:DF 0 "register_operand" "=f")
5980 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5981 (match_operand:DF 2 "register_operand" "f")))
5982 (match_operand:DF 3 "register_operand" "f")))
5983 (set (match_operand:DF 4 "register_operand" "=&f")
5984 (mult:DF (match_dup 1) (match_dup 2)))]
5985 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5986 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5987 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5989 [(set_attr "type" "fpmuldbl")
5990 (set_attr "length" "8")])
5993 [(set (match_operand:DF 0 "register_operand" "")
5994 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5995 (match_operand:DF 2 "register_operand" "")))
5996 (match_operand:DF 3 "register_operand" "")))
5997 (set (match_operand:DF 4 "register_operand" "")
5998 (mult:DF (match_dup 1) (match_dup 2)))]
5999 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6000 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6001 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6006 [(set (match_operand:SF 0 "register_operand" "=f")
6007 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6008 (match_operand:SF 2 "register_operand" "f")))
6009 (match_operand:SF 3 "register_operand" "f")))
6010 (set (match_operand:SF 4 "register_operand" "=&f")
6011 (mult:SF (match_dup 1) (match_dup 2)))]
6012 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6013 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6014 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6016 [(set_attr "type" "fpmuldbl")
6017 (set_attr "length" "8")])
6020 [(set (match_operand:SF 0 "register_operand" "")
6021 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6022 (match_operand:SF 2 "register_operand" "")))
6023 (match_operand:SF 3 "register_operand" "")))
6024 (set (match_operand:SF 4 "register_operand" "")
6025 (mult:SF (match_dup 1) (match_dup 2)))]
6026 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6027 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6028 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6033 [(set (match_operand:DF 0 "register_operand" "=f")
6034 (minus:DF (match_operand:DF 3 "register_operand" "f")
6035 (mult:DF (match_operand:DF 1 "register_operand" "f")
6036 (match_operand:DF 2 "register_operand" "f"))))
6037 (set (match_operand:DF 4 "register_operand" "=&f")
6038 (mult:DF (match_dup 1) (match_dup 2)))]
6039 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6040 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6041 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6043 [(set_attr "type" "fpmuldbl")
6044 (set_attr "length" "8")])
6047 [(set (match_operand:DF 0 "register_operand" "")
6048 (minus:DF (match_operand:DF 3 "register_operand" "")
6049 (mult:DF (match_operand:DF 1 "register_operand" "")
6050 (match_operand:DF 2 "register_operand" ""))))
6051 (set (match_operand:DF 4 "register_operand" "")
6052 (mult:DF (match_dup 1) (match_dup 2)))]
6053 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6054 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6055 (set (match_dup 0) (minus:DF (match_dup 3)
6056 (mult:DF (match_dup 1) (match_dup 2))))]
6060 [(set (match_operand:SF 0 "register_operand" "=f")
6061 (minus:SF (match_operand:SF 3 "register_operand" "f")
6062 (mult:SF (match_operand:SF 1 "register_operand" "f")
6063 (match_operand:SF 2 "register_operand" "f"))))
6064 (set (match_operand:SF 4 "register_operand" "=&f")
6065 (mult:SF (match_dup 1) (match_dup 2)))]
6066 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6067 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6068 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6070 [(set_attr "type" "fpmuldbl")
6071 (set_attr "length" "8")])
6074 [(set (match_operand:SF 0 "register_operand" "")
6075 (minus:SF (match_operand:SF 3 "register_operand" "")
6076 (mult:SF (match_operand:SF 1 "register_operand" "")
6077 (match_operand:SF 2 "register_operand" ""))))
6078 (set (match_operand:SF 4 "register_operand" "")
6079 (mult:SF (match_dup 1) (match_dup 2)))]
6080 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6081 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6082 (set (match_dup 0) (minus:SF (match_dup 3)
6083 (mult:SF (match_dup 1) (match_dup 2))))]
6087 [(set (match_operand:DF 0 "register_operand" "=f")
6088 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6089 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6090 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6091 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6093 [(set_attr "type" "fpalu")
6094 (set_attr "length" "8")])
6097 [(set (match_operand:DF 0 "register_operand" "")
6098 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6099 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6100 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6101 [(set (match_dup 2) (abs:DF (match_dup 1)))
6102 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6106 [(set (match_operand:SF 0 "register_operand" "=f")
6107 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6108 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6109 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6110 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6112 [(set_attr "type" "fpalu")
6113 (set_attr "length" "8")])
6116 [(set (match_operand:SF 0 "register_operand" "")
6117 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6118 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6119 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6120 [(set (match_dup 2) (abs:SF (match_dup 1)))
6121 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6124 ;;- Shift instructions
6126 ;; Optimized special case of shifting.
6129 [(set (match_operand:SI 0 "register_operand" "=r")
6130 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6134 [(set_attr "type" "load")
6135 (set_attr "length" "4")])
6138 [(set (match_operand:SI 0 "register_operand" "=r")
6139 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6143 [(set_attr "type" "load")
6144 (set_attr "length" "4")])
6147 [(set (match_operand:SI 0 "register_operand" "=r")
6148 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6149 (match_operand:SI 3 "shadd_operand" ""))
6150 (match_operand:SI 1 "register_operand" "r")))]
6152 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6153 [(set_attr "type" "binary")
6154 (set_attr "length" "4")])
6157 [(set (match_operand:DI 0 "register_operand" "=r")
6158 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6159 (match_operand:DI 3 "shadd_operand" ""))
6160 (match_operand:DI 1 "register_operand" "r")))]
6162 "shladd,l %2,%O3,%1,%0"
6163 [(set_attr "type" "binary")
6164 (set_attr "length" "4")])
6166 (define_expand "ashlsi3"
6167 [(set (match_operand:SI 0 "register_operand" "")
6168 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6169 (match_operand:SI 2 "arith32_operand" "")))]
6173 if (GET_CODE (operands[2]) != CONST_INT)
6175 rtx temp = gen_reg_rtx (SImode);
6176 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6177 if (GET_CODE (operands[1]) == CONST_INT)
6178 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6180 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6183 /* Make sure both inputs are not constants,
6184 there are no patterns for that. */
6185 operands[1] = force_reg (SImode, operands[1]);
6189 [(set (match_operand:SI 0 "register_operand" "=r")
6190 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6191 (match_operand:SI 2 "const_int_operand" "n")))]
6193 "{zdep|depw,z} %1,%P2,%L2,%0"
6194 [(set_attr "type" "shift")
6195 (set_attr "length" "4")])
6197 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6198 ; Doing it like this makes slightly better code since reload can
6199 ; replace a register with a known value in range -16..15 with a
6200 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6201 ; but since we have no more CONST_OK... characters, that is not
6203 (define_insn "zvdep32"
6204 [(set (match_operand:SI 0 "register_operand" "=r,r")
6205 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6206 (minus:SI (const_int 31)
6207 (match_operand:SI 2 "register_operand" "q,q"))))]
6210 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6211 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6212 [(set_attr "type" "shift,shift")
6213 (set_attr "length" "4,4")])
6215 (define_insn "zvdep_imm32"
6216 [(set (match_operand:SI 0 "register_operand" "=r")
6217 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6218 (minus:SI (const_int 31)
6219 (match_operand:SI 2 "register_operand" "q"))))]
6223 int x = INTVAL (operands[1]);
6224 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6225 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6226 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6228 [(set_attr "type" "shift")
6229 (set_attr "length" "4")])
6231 (define_insn "vdepi_ior"
6232 [(set (match_operand:SI 0 "register_operand" "=r")
6233 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6234 (minus:SI (const_int 31)
6235 (match_operand:SI 2 "register_operand" "q")))
6236 (match_operand:SI 3 "register_operand" "0")))]
6237 ; accept ...0001...1, can this be generalized?
6238 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6241 int x = INTVAL (operands[1]);
6242 operands[2] = GEN_INT (exact_log2 (x + 1));
6243 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6245 [(set_attr "type" "shift")
6246 (set_attr "length" "4")])
6248 (define_insn "vdepi_and"
6249 [(set (match_operand:SI 0 "register_operand" "=r")
6250 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6251 (minus:SI (const_int 31)
6252 (match_operand:SI 2 "register_operand" "q")))
6253 (match_operand:SI 3 "register_operand" "0")))]
6254 ; this can be generalized...!
6255 "INTVAL (operands[1]) == -2"
6258 int x = INTVAL (operands[1]);
6259 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6260 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6262 [(set_attr "type" "shift")
6263 (set_attr "length" "4")])
6265 (define_expand "ashldi3"
6266 [(set (match_operand:DI 0 "register_operand" "")
6267 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6268 (match_operand:DI 2 "arith32_operand" "")))]
6272 if (GET_CODE (operands[2]) != CONST_INT)
6274 rtx temp = gen_reg_rtx (DImode);
6275 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6276 if (GET_CODE (operands[1]) == CONST_INT)
6277 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6279 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6282 /* Make sure both inputs are not constants,
6283 there are no patterns for that. */
6284 operands[1] = force_reg (DImode, operands[1]);
6288 [(set (match_operand:DI 0 "register_operand" "=r")
6289 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6290 (match_operand:DI 2 "const_int_operand" "n")))]
6292 "depd,z %1,%p2,%Q2,%0"
6293 [(set_attr "type" "shift")
6294 (set_attr "length" "4")])
6296 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6297 ; Doing it like this makes slightly better code since reload can
6298 ; replace a register with a known value in range -16..15 with a
6299 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6300 ; but since we have no more CONST_OK... characters, that is not
6302 (define_insn "zvdep64"
6303 [(set (match_operand:DI 0 "register_operand" "=r,r")
6304 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6305 (minus:DI (const_int 63)
6306 (match_operand:DI 2 "register_operand" "q,q"))))]
6309 depd,z %1,%%sar,64,%0
6310 depdi,z %1,%%sar,64,%0"
6311 [(set_attr "type" "shift,shift")
6312 (set_attr "length" "4,4")])
6314 (define_insn "zvdep_imm64"
6315 [(set (match_operand:DI 0 "register_operand" "=r")
6316 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6317 (minus:DI (const_int 63)
6318 (match_operand:DI 2 "register_operand" "q"))))]
6322 int x = INTVAL (operands[1]);
6323 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6324 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6325 return \"depdi,z %1,%%sar,%2,%0\";
6327 [(set_attr "type" "shift")
6328 (set_attr "length" "4")])
6331 [(set (match_operand:DI 0 "register_operand" "=r")
6332 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6333 (minus:DI (const_int 63)
6334 (match_operand:DI 2 "register_operand" "q")))
6335 (match_operand:DI 3 "register_operand" "0")))]
6336 ; accept ...0001...1, can this be generalized?
6337 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6340 int x = INTVAL (operands[1]);
6341 operands[2] = GEN_INT (exact_log2 (x + 1));
6342 return \"depdi -1,%%sar,%2,%0\";
6344 [(set_attr "type" "shift")
6345 (set_attr "length" "4")])
6348 [(set (match_operand:DI 0 "register_operand" "=r")
6349 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6350 (minus:DI (const_int 63)
6351 (match_operand:DI 2 "register_operand" "q")))
6352 (match_operand:DI 3 "register_operand" "0")))]
6353 ; this can be generalized...!
6354 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6357 int x = INTVAL (operands[1]);
6358 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6359 return \"depdi 0,%%sar,%2,%0\";
6361 [(set_attr "type" "shift")
6362 (set_attr "length" "4")])
6364 (define_expand "ashrsi3"
6365 [(set (match_operand:SI 0 "register_operand" "")
6366 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6367 (match_operand:SI 2 "arith32_operand" "")))]
6371 if (GET_CODE (operands[2]) != CONST_INT)
6373 rtx temp = gen_reg_rtx (SImode);
6374 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6375 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6381 [(set (match_operand:SI 0 "register_operand" "=r")
6382 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6383 (match_operand:SI 2 "const_int_operand" "n")))]
6385 "{extrs|extrw,s} %1,%P2,%L2,%0"
6386 [(set_attr "type" "shift")
6387 (set_attr "length" "4")])
6389 (define_insn "vextrs32"
6390 [(set (match_operand:SI 0 "register_operand" "=r")
6391 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6392 (minus:SI (const_int 31)
6393 (match_operand:SI 2 "register_operand" "q"))))]
6395 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6396 [(set_attr "type" "shift")
6397 (set_attr "length" "4")])
6399 (define_expand "ashrdi3"
6400 [(set (match_operand:DI 0 "register_operand" "")
6401 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6402 (match_operand:DI 2 "arith32_operand" "")))]
6406 if (GET_CODE (operands[2]) != CONST_INT)
6408 rtx temp = gen_reg_rtx (DImode);
6409 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6410 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6416 [(set (match_operand:DI 0 "register_operand" "=r")
6417 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6418 (match_operand:DI 2 "const_int_operand" "n")))]
6420 "extrd,s %1,%p2,%Q2,%0"
6421 [(set_attr "type" "shift")
6422 (set_attr "length" "4")])
6424 (define_insn "vextrs64"
6425 [(set (match_operand:DI 0 "register_operand" "=r")
6426 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6427 (minus:DI (const_int 63)
6428 (match_operand:DI 2 "register_operand" "q"))))]
6430 "extrd,s %1,%%sar,64,%0"
6431 [(set_attr "type" "shift")
6432 (set_attr "length" "4")])
6434 (define_insn "lshrsi3"
6435 [(set (match_operand:SI 0 "register_operand" "=r,r")
6436 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6437 (match_operand:SI 2 "arith32_operand" "q,n")))]
6440 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6441 {extru|extrw,u} %1,%P2,%L2,%0"
6442 [(set_attr "type" "shift")
6443 (set_attr "length" "4")])
6445 (define_insn "lshrdi3"
6446 [(set (match_operand:DI 0 "register_operand" "=r,r")
6447 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6448 (match_operand:DI 2 "arith32_operand" "q,n")))]
6451 shrpd %%r0,%1,%%sar,%0
6452 extrd,u %1,%p2,%Q2,%0"
6453 [(set_attr "type" "shift")
6454 (set_attr "length" "4")])
6456 (define_insn "rotrsi3"
6457 [(set (match_operand:SI 0 "register_operand" "=r,r")
6458 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6459 (match_operand:SI 2 "arith32_operand" "q,n")))]
6463 if (GET_CODE (operands[2]) == CONST_INT)
6465 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6466 return \"{shd|shrpw} %1,%1,%2,%0\";
6469 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6471 [(set_attr "type" "shift")
6472 (set_attr "length" "4")])
6474 (define_expand "rotlsi3"
6475 [(set (match_operand:SI 0 "register_operand" "")
6476 (rotate:SI (match_operand:SI 1 "register_operand" "")
6477 (match_operand:SI 2 "arith32_operand" "")))]
6481 if (GET_CODE (operands[2]) != CONST_INT)
6483 rtx temp = gen_reg_rtx (SImode);
6484 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6485 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6488 /* Else expand normally. */
6492 [(set (match_operand:SI 0 "register_operand" "=r")
6493 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6494 (match_operand:SI 2 "const_int_operand" "n")))]
6498 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6499 return \"{shd|shrpw} %1,%1,%2,%0\";
6501 [(set_attr "type" "shift")
6502 (set_attr "length" "4")])
6505 [(set (match_operand:SI 0 "register_operand" "=r")
6506 (match_operator:SI 5 "plus_xor_ior_operator"
6507 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6508 (match_operand:SI 3 "const_int_operand" "n"))
6509 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6510 (match_operand:SI 4 "const_int_operand" "n"))]))]
6511 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6512 "{shd|shrpw} %1,%2,%4,%0"
6513 [(set_attr "type" "shift")
6514 (set_attr "length" "4")])
6517 [(set (match_operand:SI 0 "register_operand" "=r")
6518 (match_operator:SI 5 "plus_xor_ior_operator"
6519 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6520 (match_operand:SI 4 "const_int_operand" "n"))
6521 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6522 (match_operand:SI 3 "const_int_operand" "n"))]))]
6523 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6524 "{shd|shrpw} %1,%2,%4,%0"
6525 [(set_attr "type" "shift")
6526 (set_attr "length" "4")])
6529 [(set (match_operand:SI 0 "register_operand" "=r")
6530 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6531 (match_operand:SI 2 "const_int_operand" ""))
6532 (match_operand:SI 3 "const_int_operand" "")))]
6533 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
6536 int cnt = INTVAL (operands[2]) & 31;
6537 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6538 operands[2] = GEN_INT (31 - cnt);
6539 return \"{zdep|depw,z} %1,%2,%3,%0\";
6541 [(set_attr "type" "shift")
6542 (set_attr "length" "4")])
6544 ;; Unconditional and other jump instructions.
6546 ;; This can only be used in a leaf function, so we do
6547 ;; not need to use the PIC register when generating PIC code.
6548 (define_insn "return"
6552 "hppa_can_use_return_insn_p ()"
6556 return \"bve%* (%%r2)\";
6557 return \"bv%* %%r0(%%r2)\";
6559 [(set_attr "type" "branch")
6560 (set_attr "length" "4")])
6562 ;; Emit a different pattern for functions which have non-trivial
6563 ;; epilogues so as not to confuse jump and reorg.
6564 (define_insn "return_internal"
6572 return \"bve%* (%%r2)\";
6573 return \"bv%* %%r0(%%r2)\";
6575 [(set_attr "type" "branch")
6576 (set_attr "length" "4")])
6578 ;; This is used for eh returns which bypass the return stub.
6579 (define_insn "return_external_pic"
6581 (clobber (reg:SI 1))
6583 "!TARGET_NO_SPACE_REGS
6585 && flag_pic && current_function_calls_eh_return"
6586 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6587 [(set_attr "type" "branch")
6588 (set_attr "length" "12")])
6590 (define_expand "prologue"
6593 "hppa_expand_prologue ();DONE;")
6595 (define_expand "sibcall_epilogue"
6600 hppa_expand_epilogue ();
6604 (define_expand "epilogue"
6609 /* Try to use the trivial return first. Else use the full
6611 if (hppa_can_use_return_insn_p ())
6612 emit_jump_insn (gen_return ());
6617 hppa_expand_epilogue ();
6619 /* EH returns bypass the normal return stub. Thus, we must do an
6620 interspace branch to return from functions that call eh_return.
6621 This is only a problem for returns from shared code on ports
6622 using space registers. */
6623 if (!TARGET_NO_SPACE_REGS
6625 && flag_pic && current_function_calls_eh_return)
6626 x = gen_return_external_pic ();
6628 x = gen_return_internal ();
6635 ; Used by hppa_profile_hook to load the starting address of the current
6636 ; function; operand 1 contains the address of the label in operand 3
6637 (define_insn "load_offset_label_address"
6638 [(set (match_operand:SI 0 "register_operand" "=r")
6639 (plus:SI (match_operand:SI 1 "register_operand" "r")
6640 (minus:SI (match_operand:SI 2 "" "")
6641 (label_ref:SI (match_operand 3 "" "")))))]
6644 [(set_attr "type" "multi")
6645 (set_attr "length" "4")])
6647 ; Output a code label and load its address.
6648 (define_insn "lcla1"
6649 [(set (match_operand:SI 0 "register_operand" "=r")
6650 (label_ref:SI (match_operand 1 "" "")))
6655 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6656 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6657 CODE_LABEL_NUMBER (operands[1]));
6660 [(set_attr "type" "multi")
6661 (set_attr "length" "8")])
6663 (define_insn "lcla2"
6664 [(set (match_operand:SI 0 "register_operand" "=r")
6665 (label_ref:SI (match_operand 1 "" "")))
6670 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6671 CODE_LABEL_NUMBER (operands[1]));
6674 [(set_attr "type" "move")
6675 (set_attr "length" "4")])
6677 (define_insn "blockage"
6678 [(unspec_volatile [(const_int 2)] 0)]
6681 [(set_attr "length" "0")])
6684 [(set (pc) (label_ref (match_operand 0 "" "")))]
6688 /* An unconditional branch which can reach its target. */
6689 if (get_attr_length (insn) != 24
6690 && get_attr_length (insn) != 16)
6693 return output_lbranch (operands[0], insn);
6695 [(set_attr "type" "uncond_branch")
6696 (set_attr "pa_combine_type" "uncond_branch")
6697 (set (attr "length")
6698 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6699 (if_then_else (lt (abs (minus (match_dup 0)
6700 (plus (pc) (const_int 8))))
6704 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6706 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6711 ;;; Hope this is only within a function...
6712 (define_insn "indirect_jump"
6713 [(set (pc) (match_operand 0 "register_operand" "r"))]
6714 "GET_MODE (operands[0]) == word_mode"
6716 [(set_attr "type" "branch")
6717 (set_attr "length" "4")])
6719 ;;; This jump is used in branch tables where the insn length is fixed.
6720 ;;; The length of this insn is adjusted if the delay slot is not filled.
6721 (define_insn "short_jump"
6722 [(set (pc) (label_ref (match_operand 0 "" "")))
6726 [(set_attr "type" "btable_branch")
6727 (set_attr "length" "4")])
6729 ;; Subroutines of "casesi".
6730 ;; operand 0 is index
6731 ;; operand 1 is the minimum bound
6732 ;; operand 2 is the maximum bound - minimum bound + 1
6733 ;; operand 3 is CODE_LABEL for the table;
6734 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6736 (define_expand "casesi"
6737 [(match_operand:SI 0 "general_operand" "")
6738 (match_operand:SI 1 "const_int_operand" "")
6739 (match_operand:SI 2 "const_int_operand" "")
6740 (match_operand 3 "" "")
6741 (match_operand 4 "" "")]
6745 if (GET_CODE (operands[0]) != REG)
6746 operands[0] = force_reg (SImode, operands[0]);
6748 if (operands[1] != const0_rtx)
6750 rtx index = gen_reg_rtx (SImode);
6752 operands[1] = GEN_INT (-INTVAL (operands[1]));
6753 if (!INT_14_BITS (operands[1]))
6754 operands[1] = force_reg (SImode, operands[1]);
6755 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6756 operands[0] = index;
6759 /* In 64bit mode we must make sure to wipe the upper bits of the register
6760 just in case the addition overflowed or we had random bits in the
6761 high part of the register. */
6764 rtx index = gen_reg_rtx (DImode);
6766 emit_insn (gen_extendsidi2 (index, operands[0]));
6767 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
6770 if (!INT_5_BITS (operands[2]))
6771 operands[2] = force_reg (SImode, operands[2]);
6773 /* This branch prevents us finding an insn for the delay slot of the
6774 following vectored branch. It might be possible to use the delay
6775 slot if an index value of -1 was used to transfer to the out-of-range
6776 label. In order to do this, we would have to output the -1 vector
6777 element after the delay insn. The casesi output code would have to
6778 check if the casesi insn is in a delay branch sequence and output
6779 the delay insn if one is found. If this was done, then it might
6780 then be worthwhile to split the casesi patterns to improve scheduling.
6781 However, it's not clear that all this extra complexity is worth
6783 emit_insn (gen_cmpsi (operands[0], operands[2]));
6784 emit_jump_insn (gen_bgtu (operands[4]));
6786 if (TARGET_BIG_SWITCH)
6790 rtx tmp1 = gen_reg_rtx (DImode);
6791 rtx tmp2 = gen_reg_rtx (DImode);
6793 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
6798 rtx tmp1 = gen_reg_rtx (SImode);
6802 rtx tmp2 = gen_reg_rtx (SImode);
6804 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
6808 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
6812 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6816 ;;; The rtl for this pattern doesn't accurately describe what the insn
6817 ;;; actually does, particularly when case-vector elements are exploded
6818 ;;; in pa_reorg. However, the initial SET in these patterns must show
6819 ;;; the connection of the insn to the following jump table.
6820 (define_insn "casesi0"
6821 [(set (pc) (mem:SI (plus:SI
6822 (mult:SI (match_operand:SI 0 "register_operand" "r")
6824 (label_ref (match_operand 1 "" "")))))]
6826 "blr,n %0,%%r0\;nop"
6827 [(set_attr "type" "multi")
6828 (set_attr "length" "8")])
6830 ;;; 32-bit code, absolute branch table.
6831 (define_insn "casesi32"
6832 [(set (pc) (mem:SI (plus:SI
6833 (mult:SI (match_operand:SI 0 "register_operand" "r")
6835 (label_ref (match_operand 1 "" "")))))
6836 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
6837 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6838 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6839 [(set_attr "type" "multi")
6840 (set_attr "length" "16")])
6842 ;;; 32-bit code, relative branch table.
6843 (define_insn "casesi32p"
6844 [(set (pc) (mem:SI (plus:SI
6845 (mult:SI (match_operand:SI 0 "register_operand" "r")
6847 (label_ref (match_operand 1 "" "")))))
6848 (clobber (match_operand:SI 2 "register_operand" "=&a"))
6849 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
6850 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6851 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
6852 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
6853 [(set_attr "type" "multi")
6854 (set (attr "length")
6855 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
6859 ;;; 64-bit code, 32-bit relative branch table.
6860 (define_insn "casesi64p"
6861 [(set (pc) (mem:DI (plus:DI
6862 (mult:DI (sign_extend:DI
6863 (match_operand:SI 0 "register_operand" "r"))
6865 (label_ref (match_operand 1 "" "")))))
6866 (clobber (match_operand:DI 2 "register_operand" "=&r"))
6867 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
6868 "TARGET_64BIT && TARGET_BIG_SWITCH"
6869 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
6870 add,l %2,%3,%3\;bv,n %%r0(%3)"
6871 [(set_attr "type" "multi")
6872 (set_attr "length" "24")])
6876 ;;- jump to subroutine
6878 (define_expand "call"
6879 [(parallel [(call (match_operand:SI 0 "" "")
6880 (match_operand 1 "" ""))
6881 (clobber (reg:SI 2))])]
6886 rtx nb = operands[1];
6888 if (TARGET_PORTABLE_RUNTIME)
6889 op = force_reg (SImode, XEXP (operands[0], 0));
6891 op = XEXP (operands[0], 0);
6895 if (!virtuals_instantiated)
6896 emit_move_insn (arg_pointer_rtx,
6897 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6901 /* The loop pass can generate new libcalls after the virtual
6902 registers are instantiated when fpregs are disabled because
6903 the only method that we have for doing DImode multiplication
6904 is with a libcall. This could be trouble if we haven't
6905 allocated enough space for the outgoing arguments. */
6906 if (INTVAL (nb) > current_function_outgoing_args_size)
6909 emit_move_insn (arg_pointer_rtx,
6910 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6911 GEN_INT (STACK_POINTER_OFFSET + 64)));
6915 /* Use two different patterns for calls to explicitly named functions
6916 and calls through function pointers. This is necessary as these two
6917 types of calls use different calling conventions, and CSE might try
6918 to change the named call into an indirect call in some cases (using
6919 two patterns keeps CSE from performing this optimization).
6921 We now use even more call patterns as there was a subtle bug in
6922 attempting to restore the pic register after a call using a simple
6923 move insn. During reload, a instruction involving a pseudo register
6924 with no explicit dependence on the PIC register can be converted
6925 to an equivalent load from memory using the PIC register. If we
6926 emit a simple move to restore the PIC register in the initial rtl
6927 generation, then it can potentially be repositioned during scheduling.
6928 and an instruction that eventually uses the PIC register may end up
6929 between the call and the PIC register restore.
6931 This only worked because there is a post call group of instructions
6932 that are scheduled with the call. These instructions are included
6933 in the same basic block as the call. However, calls can throw in
6934 C++ code and a basic block has to terminate at the call if the call
6935 can throw. This results in the PIC register restore being scheduled
6936 independently from the call. So, we now hide the save and restore
6937 of the PIC register in the call pattern until after reload. Then,
6938 we split the moves out. A small side benefit is that we now don't
6939 need to have a use of the PIC register in the return pattern and
6940 the final save/restore operation is not needed.
6942 I elected to just clobber %r4 in the PIC patterns and use it instead
6943 of trying to force hppa_pic_save_rtx () to a callee saved register.
6944 This might have required a new register class and constraint. It
6945 was also simpler to just handle the restore from a register than a
6949 if (GET_CODE (op) == SYMBOL_REF)
6950 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
6953 op = force_reg (word_mode, op);
6954 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
6959 if (GET_CODE (op) == SYMBOL_REF)
6962 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
6964 call_insn = emit_call_insn (gen_call_symref (op, nb));
6968 rtx tmpreg = gen_rtx_REG (word_mode, 22);
6970 emit_move_insn (tmpreg, force_reg (word_mode, op));
6972 call_insn = emit_call_insn (gen_call_reg_pic (nb));
6974 call_insn = emit_call_insn (gen_call_reg (nb));
6981 ;; We use function calls to set the attribute length of calls and millicode
6982 ;; calls. This is necessary because of the large variety of call sequences.
6983 ;; Implementing the calculation in rtl is difficult as well as ugly. As
6984 ;; we need the same calculation in several places, maintenance becomes a
6987 ;; However, this has a subtle impact on branch shortening. When the
6988 ;; expression used to set the length attribute of an instruction depends
6989 ;; on a relative address (e.g., pc or a branch address), genattrtab
6990 ;; notes that the insn's length is variable, and attempts to determine a
6991 ;; worst-case default length and code to compute an insn's current length.
6993 ;; The use of a function call hides the variable dependence of our calls
6994 ;; and millicode calls. The result is genattrtab doesn't treat the operation
6995 ;; as variable and it only generates code for the default case using our
6996 ;; function call. Because of this, calls and millicode calls have a fixed
6997 ;; length in the branch shortening pass, and some branches will use a longer
6998 ;; code sequence than necessary. However, the length of any given call
6999 ;; will still reflect its final code location and it may be shorter than
7000 ;; the initial length estimate.
7002 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7003 ;; in the set. However, when genattrtab hits a function call in its attempt
7004 ;; to compute the default length, it marks the result as unknown and sets
7005 ;; the default result to MAX_INT ;-( One possible fix that would allow
7006 ;; calls to participate in branch shortening would be to make the call to
7007 ;; insn_default_length a target option. Then, we could massage unknown
7008 ;; results. Another fix might be to change genattrtab so that it just does
7009 ;; the call in the variable case as it already does for the fixed case.
7011 (define_insn "call_symref"
7012 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7013 (match_operand 1 "" "i"))
7014 (clobber (reg:SI 1))
7015 (clobber (reg:SI 2))
7016 (use (const_int 0))]
7017 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7020 output_arg_descriptor (insn);
7021 return output_call (insn, operands[0], 0);
7023 [(set_attr "type" "call")
7024 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7026 (define_insn "call_symref_pic"
7027 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7028 (match_operand 1 "" "i"))
7029 (clobber (reg:SI 1))
7030 (clobber (reg:SI 2))
7031 (clobber (reg:SI 4))
7033 (use (const_int 0))]
7034 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7037 output_arg_descriptor (insn);
7038 return output_call (insn, operands[0], 0);
7040 [(set_attr "type" "call")
7041 (set (attr "length")
7042 (plus (symbol_ref "attr_length_call (insn, 0)")
7043 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7045 ;; Split out the PIC register save and restore after reload. This is
7046 ;; done only if the function returns. As the split is done after reload,
7047 ;; there are some situations in which we unnecessarily save and restore
7048 ;; %r4. This happens when there is a single call and the PIC register
7049 ;; is "dead" after the call. This isn't easy to fix as the usage of
7050 ;; the PIC register isn't completely determined until the reload pass.
7052 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7053 (match_operand 1 "" ""))
7054 (clobber (reg:SI 1))
7055 (clobber (reg:SI 2))
7056 (clobber (reg:SI 4))
7058 (use (const_int 0))])]
7059 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7061 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7062 [(set (reg:SI 4) (reg:SI 19))
7063 (parallel [(call (mem:SI (match_dup 0))
7065 (clobber (reg:SI 1))
7066 (clobber (reg:SI 2))
7068 (use (const_int 0))])
7069 (set (reg:SI 19) (reg:SI 4))]
7072 ;; Remove the clobber of register 4 when optimizing. This has to be
7073 ;; done with a peephole optimization rather than a split because the
7074 ;; split sequence for a call must be longer than one instruction.
7076 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7077 (match_operand 1 "" ""))
7078 (clobber (reg:SI 1))
7079 (clobber (reg:SI 2))
7080 (clobber (reg:SI 4))
7082 (use (const_int 0))])]
7083 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7084 [(parallel [(call (mem:SI (match_dup 0))
7086 (clobber (reg:SI 1))
7087 (clobber (reg:SI 2))
7089 (use (const_int 0))])]
7092 (define_insn "*call_symref_pic_post_reload"
7093 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7094 (match_operand 1 "" "i"))
7095 (clobber (reg:SI 1))
7096 (clobber (reg:SI 2))
7098 (use (const_int 0))]
7099 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7102 output_arg_descriptor (insn);
7103 return output_call (insn, operands[0], 0);
7105 [(set_attr "type" "call")
7106 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7108 ;; This pattern is split if it is necessary to save and restore the
7110 (define_insn "call_symref_64bit"
7111 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7112 (match_operand 1 "" "i"))
7113 (clobber (reg:DI 1))
7114 (clobber (reg:DI 2))
7115 (clobber (reg:DI 4))
7118 (use (const_int 0))]
7122 output_arg_descriptor (insn);
7123 return output_call (insn, operands[0], 0);
7125 [(set_attr "type" "call")
7126 (set (attr "length")
7127 (plus (symbol_ref "attr_length_call (insn, 0)")
7128 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7130 ;; Split out the PIC register save and restore after reload. This is
7131 ;; done only if the function returns. As the split is done after reload,
7132 ;; there are some situations in which we unnecessarily save and restore
7133 ;; %r4. This happens when there is a single call and the PIC register
7134 ;; is "dead" after the call. This isn't easy to fix as the usage of
7135 ;; the PIC register isn't completely determined until the reload pass.
7137 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7138 (match_operand 1 "" ""))
7139 (clobber (reg:DI 1))
7140 (clobber (reg:DI 2))
7141 (clobber (reg:DI 4))
7144 (use (const_int 0))])]
7147 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7148 [(set (reg:DI 4) (reg:DI 27))
7149 (parallel [(call (mem:SI (match_dup 0))
7151 (clobber (reg:DI 1))
7152 (clobber (reg:DI 2))
7155 (use (const_int 0))])
7156 (set (reg:DI 27) (reg:DI 4))]
7159 ;; Remove the clobber of register 4 when optimizing. This has to be
7160 ;; done with a peephole optimization rather than a split because the
7161 ;; split sequence for a call must be longer than one instruction.
7163 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7164 (match_operand 1 "" ""))
7165 (clobber (reg:DI 1))
7166 (clobber (reg:DI 2))
7167 (clobber (reg:DI 4))
7170 (use (const_int 0))])]
7171 "TARGET_64BIT && reload_completed"
7172 [(parallel [(call (mem:SI (match_dup 0))
7174 (clobber (reg:DI 1))
7175 (clobber (reg:DI 2))
7178 (use (const_int 0))])]
7181 (define_insn "*call_symref_64bit_post_reload"
7182 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7183 (match_operand 1 "" "i"))
7184 (clobber (reg:DI 1))
7185 (clobber (reg:DI 2))
7188 (use (const_int 0))]
7192 output_arg_descriptor (insn);
7193 return output_call (insn, operands[0], 0);
7195 [(set_attr "type" "call")
7196 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7198 (define_insn "call_reg"
7199 [(call (mem:SI (reg:SI 22))
7200 (match_operand 0 "" "i"))
7201 (clobber (reg:SI 1))
7202 (clobber (reg:SI 2))
7203 (use (const_int 1))]
7207 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7209 [(set_attr "type" "dyncall")
7210 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7212 ;; This pattern is split if it is necessary to save and restore the
7214 (define_insn "call_reg_pic"
7215 [(call (mem:SI (reg:SI 22))
7216 (match_operand 0 "" "i"))
7217 (clobber (reg:SI 1))
7218 (clobber (reg:SI 2))
7219 (clobber (reg:SI 4))
7221 (use (const_int 1))]
7225 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7227 [(set_attr "type" "dyncall")
7228 (set (attr "length")
7229 (plus (symbol_ref "attr_length_indirect_call (insn)")
7230 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7232 ;; Split out the PIC register save and restore after reload. This is
7233 ;; done only if the function returns. As the split is done after reload,
7234 ;; there are some situations in which we unnecessarily save and restore
7235 ;; %r4. This happens when there is a single call and the PIC register
7236 ;; is "dead" after the call. This isn't easy to fix as the usage of
7237 ;; the PIC register isn't completely determined until the reload pass.
7239 [(parallel [(call (mem:SI (reg:SI 22))
7240 (match_operand 0 "" ""))
7241 (clobber (reg:SI 1))
7242 (clobber (reg:SI 2))
7243 (clobber (reg:SI 4))
7245 (use (const_int 1))])]
7248 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7249 [(set (reg:SI 4) (reg:SI 19))
7250 (parallel [(call (mem:SI (reg:SI 22))
7252 (clobber (reg:SI 1))
7253 (clobber (reg:SI 2))
7255 (use (const_int 1))])
7256 (set (reg:SI 19) (reg:SI 4))]
7259 ;; Remove the clobber of register 4 when optimizing. This has to be
7260 ;; done with a peephole optimization rather than a split because the
7261 ;; split sequence for a call must be longer than one instruction.
7263 [(parallel [(call (mem:SI (reg:SI 22))
7264 (match_operand 0 "" ""))
7265 (clobber (reg:SI 1))
7266 (clobber (reg:SI 2))
7267 (clobber (reg:SI 4))
7269 (use (const_int 1))])]
7270 "!TARGET_64BIT && reload_completed"
7271 [(parallel [(call (mem:SI (reg:SI 22))
7273 (clobber (reg:SI 1))
7274 (clobber (reg:SI 2))
7276 (use (const_int 1))])]
7279 (define_insn "*call_reg_pic_post_reload"
7280 [(call (mem:SI (reg:SI 22))
7281 (match_operand 0 "" "i"))
7282 (clobber (reg:SI 1))
7283 (clobber (reg:SI 2))
7285 (use (const_int 1))]
7289 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7291 [(set_attr "type" "dyncall")
7292 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7294 ;; This pattern is split if it is necessary to save and restore the
7296 (define_insn "call_reg_64bit"
7297 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7298 (match_operand 1 "" "i"))
7299 (clobber (reg:DI 2))
7300 (clobber (reg:DI 4))
7303 (use (const_int 1))]
7307 return output_indirect_call (insn, operands[0]);
7309 [(set_attr "type" "dyncall")
7310 (set (attr "length")
7311 (plus (symbol_ref "attr_length_indirect_call (insn)")
7312 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7314 ;; Split out the PIC register save and restore after reload. This is
7315 ;; done only if the function returns. As the split is done after reload,
7316 ;; there are some situations in which we unnecessarily save and restore
7317 ;; %r4. This happens when there is a single call and the PIC register
7318 ;; is "dead" after the call. This isn't easy to fix as the usage of
7319 ;; the PIC register isn't completely determined until the reload pass.
7321 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7322 (match_operand 1 "" ""))
7323 (clobber (reg:DI 2))
7324 (clobber (reg:DI 4))
7327 (use (const_int 1))])]
7330 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7331 [(set (reg:DI 4) (reg:DI 27))
7332 (parallel [(call (mem:SI (match_dup 0))
7334 (clobber (reg:DI 2))
7337 (use (const_int 1))])
7338 (set (reg:DI 27) (reg:DI 4))]
7341 ;; Remove the clobber of register 4 when optimizing. This has to be
7342 ;; done with a peephole optimization rather than a split because the
7343 ;; split sequence for a call must be longer than one instruction.
7345 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7346 (match_operand 1 "" ""))
7347 (clobber (reg:DI 2))
7348 (clobber (reg:DI 4))
7351 (use (const_int 1))])]
7352 "TARGET_64BIT && reload_completed"
7353 [(parallel [(call (mem:SI (match_dup 0))
7355 (clobber (reg:DI 2))
7358 (use (const_int 1))])]
7361 (define_insn "*call_reg_64bit_post_reload"
7362 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7363 (match_operand 1 "" "i"))
7364 (clobber (reg:DI 2))
7367 (use (const_int 1))]
7371 return output_indirect_call (insn, operands[0]);
7373 [(set_attr "type" "dyncall")
7374 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7376 (define_expand "call_value"
7377 [(parallel [(set (match_operand 0 "" "")
7378 (call (match_operand:SI 1 "" "")
7379 (match_operand 2 "" "")))
7380 (clobber (reg:SI 2))])]
7385 rtx dst = operands[0];
7386 rtx nb = operands[2];
7388 if (TARGET_PORTABLE_RUNTIME)
7389 op = force_reg (SImode, XEXP (operands[1], 0));
7391 op = XEXP (operands[1], 0);
7395 if (!virtuals_instantiated)
7396 emit_move_insn (arg_pointer_rtx,
7397 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7401 /* The loop pass can generate new libcalls after the virtual
7402 registers are instantiated when fpregs are disabled because
7403 the only method that we have for doing DImode multiplication
7404 is with a libcall. This could be trouble if we haven't
7405 allocated enough space for the outgoing arguments. */
7406 if (INTVAL (nb) > current_function_outgoing_args_size)
7409 emit_move_insn (arg_pointer_rtx,
7410 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7411 GEN_INT (STACK_POINTER_OFFSET + 64)));
7415 /* Use two different patterns for calls to explicitly named functions
7416 and calls through function pointers. This is necessary as these two
7417 types of calls use different calling conventions, and CSE might try
7418 to change the named call into an indirect call in some cases (using
7419 two patterns keeps CSE from performing this optimization).
7421 We now use even more call patterns as there was a subtle bug in
7422 attempting to restore the pic register after a call using a simple
7423 move insn. During reload, a instruction involving a pseudo register
7424 with no explicit dependence on the PIC register can be converted
7425 to an equivalent load from memory using the PIC register. If we
7426 emit a simple move to restore the PIC register in the initial rtl
7427 generation, then it can potentially be repositioned during scheduling.
7428 and an instruction that eventually uses the PIC register may end up
7429 between the call and the PIC register restore.
7431 This only worked because there is a post call group of instructions
7432 that are scheduled with the call. These instructions are included
7433 in the same basic block as the call. However, calls can throw in
7434 C++ code and a basic block has to terminate at the call if the call
7435 can throw. This results in the PIC register restore being scheduled
7436 independently from the call. So, we now hide the save and restore
7437 of the PIC register in the call pattern until after reload. Then,
7438 we split the moves out. A small side benefit is that we now don't
7439 need to have a use of the PIC register in the return pattern and
7440 the final save/restore operation is not needed.
7442 I elected to just clobber %r4 in the PIC patterns and use it instead
7443 of trying to force hppa_pic_save_rtx () to a callee saved register.
7444 This might have required a new register class and constraint. It
7445 was also simpler to just handle the restore from a register than a
7449 if (GET_CODE (op) == SYMBOL_REF)
7450 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
7453 op = force_reg (word_mode, op);
7454 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
7459 if (GET_CODE (op) == SYMBOL_REF)
7462 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
7464 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7468 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7470 emit_move_insn (tmpreg, force_reg (word_mode, op));
7472 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
7474 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7481 (define_insn "call_val_symref"
7482 [(set (match_operand 0 "" "")
7483 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7484 (match_operand 2 "" "i")))
7485 (clobber (reg:SI 1))
7486 (clobber (reg:SI 2))
7487 (use (const_int 0))]
7488 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7491 output_arg_descriptor (insn);
7492 return output_call (insn, operands[1], 0);
7494 [(set_attr "type" "call")
7495 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7497 (define_insn "call_val_symref_pic"
7498 [(set (match_operand 0 "" "")
7499 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7500 (match_operand 2 "" "i")))
7501 (clobber (reg:SI 1))
7502 (clobber (reg:SI 2))
7503 (clobber (reg:SI 4))
7505 (use (const_int 0))]
7506 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7509 output_arg_descriptor (insn);
7510 return output_call (insn, operands[1], 0);
7512 [(set_attr "type" "call")
7513 (set (attr "length")
7514 (plus (symbol_ref "attr_length_call (insn, 0)")
7515 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7517 ;; Split out the PIC register save and restore after reload. This is
7518 ;; done only if the function returns. As the split is done after reload,
7519 ;; there are some situations in which we unnecessarily save and restore
7520 ;; %r4. This happens when there is a single call and the PIC register
7521 ;; is "dead" after the call. This isn't easy to fix as the usage of
7522 ;; the PIC register isn't completely determined until the reload pass.
7524 [(parallel [(set (match_operand 0 "" "")
7525 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7526 (match_operand 2 "" "")))
7527 (clobber (reg:SI 1))
7528 (clobber (reg:SI 2))
7529 (clobber (reg:SI 4))
7531 (use (const_int 0))])]
7532 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7534 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7535 [(set (reg:SI 4) (reg:SI 19))
7536 (parallel [(set (match_dup 0)
7537 (call (mem:SI (match_dup 1))
7539 (clobber (reg:SI 1))
7540 (clobber (reg:SI 2))
7542 (use (const_int 0))])
7543 (set (reg:SI 19) (reg:SI 4))]
7546 ;; Remove the clobber of register 4 when optimizing. This has to be
7547 ;; done with a peephole optimization rather than a split because the
7548 ;; split sequence for a call must be longer than one instruction.
7550 [(parallel [(set (match_operand 0 "" "")
7551 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7552 (match_operand 2 "" "")))
7553 (clobber (reg:SI 1))
7554 (clobber (reg:SI 2))
7555 (clobber (reg:SI 4))
7557 (use (const_int 0))])]
7558 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7559 [(parallel [(set (match_dup 0)
7560 (call (mem:SI (match_dup 1))
7562 (clobber (reg:SI 1))
7563 (clobber (reg:SI 2))
7565 (use (const_int 0))])]
7568 (define_insn "*call_val_symref_pic_post_reload"
7569 [(set (match_operand 0 "" "")
7570 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7571 (match_operand 2 "" "i")))
7572 (clobber (reg:SI 1))
7573 (clobber (reg:SI 2))
7575 (use (const_int 0))]
7576 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7579 output_arg_descriptor (insn);
7580 return output_call (insn, operands[1], 0);
7582 [(set_attr "type" "call")
7583 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7585 ;; This pattern is split if it is necessary to save and restore the
7587 (define_insn "call_val_symref_64bit"
7588 [(set (match_operand 0 "" "")
7589 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7590 (match_operand 2 "" "i")))
7591 (clobber (reg:DI 1))
7592 (clobber (reg:DI 2))
7593 (clobber (reg:DI 4))
7596 (use (const_int 0))]
7600 output_arg_descriptor (insn);
7601 return output_call (insn, operands[1], 0);
7603 [(set_attr "type" "call")
7604 (set (attr "length")
7605 (plus (symbol_ref "attr_length_call (insn, 0)")
7606 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7608 ;; Split out the PIC register save and restore after reload. This is
7609 ;; done only if the function returns. As the split is done after reload,
7610 ;; there are some situations in which we unnecessarily save and restore
7611 ;; %r4. This happens when there is a single call and the PIC register
7612 ;; is "dead" after the call. This isn't easy to fix as the usage of
7613 ;; the PIC register isn't completely determined until the reload pass.
7615 [(parallel [(set (match_operand 0 "" "")
7616 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7617 (match_operand 2 "" "")))
7618 (clobber (reg:DI 1))
7619 (clobber (reg:DI 2))
7620 (clobber (reg:DI 4))
7623 (use (const_int 0))])]
7626 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7627 [(set (reg:DI 4) (reg:DI 27))
7628 (parallel [(set (match_dup 0)
7629 (call (mem:SI (match_dup 1))
7631 (clobber (reg:DI 1))
7632 (clobber (reg:DI 2))
7635 (use (const_int 0))])
7636 (set (reg:DI 27) (reg:DI 4))]
7639 ;; Remove the clobber of register 4 when optimizing. This has to be
7640 ;; done with a peephole optimization rather than a split because the
7641 ;; split sequence for a call must be longer than one instruction.
7643 [(parallel [(set (match_operand 0 "" "")
7644 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7645 (match_operand 2 "" "")))
7646 (clobber (reg:DI 1))
7647 (clobber (reg:DI 2))
7648 (clobber (reg:DI 4))
7651 (use (const_int 0))])]
7652 "TARGET_64BIT && reload_completed"
7653 [(parallel [(set (match_dup 0)
7654 (call (mem:SI (match_dup 1))
7656 (clobber (reg:DI 1))
7657 (clobber (reg:DI 2))
7660 (use (const_int 0))])]
7663 (define_insn "*call_val_symref_64bit_post_reload"
7664 [(set (match_operand 0 "" "")
7665 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7666 (match_operand 2 "" "i")))
7667 (clobber (reg:DI 1))
7668 (clobber (reg:DI 2))
7671 (use (const_int 0))]
7675 output_arg_descriptor (insn);
7676 return output_call (insn, operands[1], 0);
7678 [(set_attr "type" "call")
7679 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7681 (define_insn "call_val_reg"
7682 [(set (match_operand 0 "" "")
7683 (call (mem:SI (reg:SI 22))
7684 (match_operand 1 "" "i")))
7685 (clobber (reg:SI 1))
7686 (clobber (reg:SI 2))
7687 (use (const_int 1))]
7691 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7693 [(set_attr "type" "dyncall")
7694 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7696 ;; This pattern is split if it is necessary to save and restore the
7698 (define_insn "call_val_reg_pic"
7699 [(set (match_operand 0 "" "")
7700 (call (mem:SI (reg:SI 22))
7701 (match_operand 1 "" "i")))
7702 (clobber (reg:SI 1))
7703 (clobber (reg:SI 2))
7704 (clobber (reg:SI 4))
7706 (use (const_int 1))]
7710 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7712 [(set_attr "type" "dyncall")
7713 (set (attr "length")
7714 (plus (symbol_ref "attr_length_indirect_call (insn)")
7715 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7717 ;; Split out the PIC register save and restore after reload. This is
7718 ;; done only if the function returns. As the split is done after reload,
7719 ;; there are some situations in which we unnecessarily save and restore
7720 ;; %r4. This happens when there is a single call and the PIC register
7721 ;; is "dead" after the call. This isn't easy to fix as the usage of
7722 ;; the PIC register isn't completely determined until the reload pass.
7724 [(parallel [(set (match_operand 0 "" "")
7725 (call (mem:SI (reg:SI 22))
7726 (match_operand 1 "" "")))
7727 (clobber (reg:SI 1))
7728 (clobber (reg:SI 2))
7729 (clobber (reg:SI 4))
7731 (use (const_int 1))])]
7734 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7735 [(set (reg:SI 4) (reg:SI 19))
7736 (parallel [(set (match_dup 0)
7737 (call (mem:SI (reg:SI 22))
7739 (clobber (reg:SI 1))
7740 (clobber (reg:SI 2))
7742 (use (const_int 1))])
7743 (set (reg:SI 19) (reg:SI 4))]
7746 ;; Remove the clobber of register 4 when optimizing. This has to be
7747 ;; done with a peephole optimization rather than a split because the
7748 ;; split sequence for a call must be longer than one instruction.
7750 [(parallel [(set (match_operand 0 "" "")
7751 (call (mem:SI (reg:SI 22))
7752 (match_operand 1 "" "")))
7753 (clobber (reg:SI 1))
7754 (clobber (reg:SI 2))
7755 (clobber (reg:SI 4))
7757 (use (const_int 1))])]
7758 "!TARGET_64BIT && reload_completed"
7759 [(parallel [(set (match_dup 0)
7760 (call (mem:SI (reg:SI 22))
7762 (clobber (reg:SI 1))
7763 (clobber (reg:SI 2))
7765 (use (const_int 1))])]
7768 (define_insn "*call_val_reg_pic_post_reload"
7769 [(set (match_operand 0 "" "")
7770 (call (mem:SI (reg:SI 22))
7771 (match_operand 1 "" "i")))
7772 (clobber (reg:SI 1))
7773 (clobber (reg:SI 2))
7775 (use (const_int 1))]
7779 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7781 [(set_attr "type" "dyncall")
7782 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7784 ;; This pattern is split if it is necessary to save and restore the
7786 (define_insn "call_val_reg_64bit"
7787 [(set (match_operand 0 "" "")
7788 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7789 (match_operand 2 "" "i")))
7790 (clobber (reg:DI 2))
7791 (clobber (reg:DI 4))
7794 (use (const_int 1))]
7798 return output_indirect_call (insn, operands[1]);
7800 [(set_attr "type" "dyncall")
7801 (set (attr "length")
7802 (plus (symbol_ref "attr_length_indirect_call (insn)")
7803 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7805 ;; Split out the PIC register save and restore after reload. This is
7806 ;; done only if the function returns. As the split is done after reload,
7807 ;; there are some situations in which we unnecessarily save and restore
7808 ;; %r4. This happens when there is a single call and the PIC register
7809 ;; is "dead" after the call. This isn't easy to fix as the usage of
7810 ;; the PIC register isn't completely determined until the reload pass.
7812 [(parallel [(set (match_operand 0 "" "")
7813 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7814 (match_operand 2 "" "")))
7815 (clobber (reg:DI 2))
7816 (clobber (reg:DI 4))
7819 (use (const_int 1))])]
7822 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7823 [(set (reg:DI 4) (reg:DI 27))
7824 (parallel [(set (match_dup 0)
7825 (call (mem:SI (match_dup 1))
7827 (clobber (reg:DI 2))
7830 (use (const_int 1))])
7831 (set (reg:DI 27) (reg:DI 4))]
7834 ;; Remove the clobber of register 4 when optimizing. This has to be
7835 ;; done with a peephole optimization rather than a split because the
7836 ;; split sequence for a call must be longer than one instruction.
7838 [(parallel [(set (match_operand 0 "" "")
7839 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7840 (match_operand 2 "" "")))
7841 (clobber (reg:DI 2))
7842 (clobber (reg:DI 4))
7845 (use (const_int 1))])]
7846 "TARGET_64BIT && reload_completed"
7847 [(parallel [(set (match_dup 0)
7848 (call (mem:SI (match_dup 1))
7850 (clobber (reg:DI 2))
7853 (use (const_int 1))])]
7856 (define_insn "*call_val_reg_64bit_post_reload"
7857 [(set (match_operand 0 "" "")
7858 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7859 (match_operand 2 "" "i")))
7860 (clobber (reg:DI 2))
7863 (use (const_int 1))]
7867 return output_indirect_call (insn, operands[1]);
7869 [(set_attr "type" "dyncall")
7870 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7872 ;; Call subroutine returning any type.
7874 (define_expand "untyped_call"
7875 [(parallel [(call (match_operand 0 "" "")
7877 (match_operand 1 "" "")
7878 (match_operand 2 "" "")])]
7884 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7886 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7888 rtx set = XVECEXP (operands[2], 0, i);
7889 emit_move_insn (SET_DEST (set), SET_SRC (set));
7892 /* The optimizer does not know that the call sets the function value
7893 registers we stored in the result block. We avoid problems by
7894 claiming that all hard registers are used and clobbered at this
7896 emit_insn (gen_blockage ());
7901 (define_expand "sibcall"
7902 [(call (match_operand:SI 0 "" "")
7903 (match_operand 1 "" ""))]
7904 "!TARGET_PORTABLE_RUNTIME"
7908 rtx nb = operands[1];
7910 op = XEXP (operands[0], 0);
7914 if (!virtuals_instantiated)
7915 emit_move_insn (arg_pointer_rtx,
7916 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7920 /* The loop pass can generate new libcalls after the virtual
7921 registers are instantiated when fpregs are disabled because
7922 the only method that we have for doing DImode multiplication
7923 is with a libcall. This could be trouble if we haven't
7924 allocated enough space for the outgoing arguments. */
7925 if (INTVAL (nb) > current_function_outgoing_args_size)
7928 emit_move_insn (arg_pointer_rtx,
7929 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7930 GEN_INT (STACK_POINTER_OFFSET + 64)));
7934 /* Indirect sibling calls are not allowed. */
7936 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
7938 call_insn = gen_sibcall_internal_symref (op, operands[1]);
7940 call_insn = emit_call_insn (call_insn);
7943 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
7945 /* We don't have to restore the PIC register. */
7947 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
7952 (define_insn "sibcall_internal_symref"
7953 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7954 (match_operand 1 "" "i"))
7955 (clobber (reg:SI 1))
7957 (use (const_int 0))]
7958 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7961 output_arg_descriptor (insn);
7962 return output_call (insn, operands[0], 1);
7964 [(set_attr "type" "call")
7965 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
7967 (define_insn "sibcall_internal_symref_64bit"
7968 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7969 (match_operand 1 "" "i"))
7970 (clobber (reg:DI 1))
7972 (use (const_int 0))]
7976 output_arg_descriptor (insn);
7977 return output_call (insn, operands[0], 1);
7979 [(set_attr "type" "call")
7980 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
7982 (define_expand "sibcall_value"
7983 [(set (match_operand 0 "" "")
7984 (call (match_operand:SI 1 "" "")
7985 (match_operand 2 "" "")))]
7986 "!TARGET_PORTABLE_RUNTIME"
7990 rtx nb = operands[1];
7992 op = XEXP (operands[1], 0);
7996 if (!virtuals_instantiated)
7997 emit_move_insn (arg_pointer_rtx,
7998 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8002 /* The loop pass can generate new libcalls after the virtual
8003 registers are instantiated when fpregs are disabled because
8004 the only method that we have for doing DImode multiplication
8005 is with a libcall. This could be trouble if we haven't
8006 allocated enough space for the outgoing arguments. */
8007 if (INTVAL (nb) > current_function_outgoing_args_size)
8010 emit_move_insn (arg_pointer_rtx,
8011 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8012 GEN_INT (STACK_POINTER_OFFSET + 64)));
8016 /* Indirect sibling calls are not allowed. */
8019 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8022 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8024 call_insn = emit_call_insn (call_insn);
8027 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8029 /* We don't have to restore the PIC register. */
8031 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8036 (define_insn "sibcall_value_internal_symref"
8037 [(set (match_operand 0 "" "")
8038 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8039 (match_operand 2 "" "i")))
8040 (clobber (reg:SI 1))
8042 (use (const_int 0))]
8043 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8046 output_arg_descriptor (insn);
8047 return output_call (insn, operands[1], 1);
8049 [(set_attr "type" "call")
8050 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8052 (define_insn "sibcall_value_internal_symref_64bit"
8053 [(set (match_operand 0 "" "")
8054 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8055 (match_operand 2 "" "i")))
8056 (clobber (reg:DI 1))
8058 (use (const_int 0))]
8062 output_arg_descriptor (insn);
8063 return output_call (insn, operands[1], 1);
8065 [(set_attr "type" "call")
8066 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8072 [(set_attr "type" "move")
8073 (set_attr "length" "4")])
8075 ;; These are just placeholders so we know where branch tables
8077 (define_insn "begin_brtab"
8082 /* Only GAS actually supports this pseudo-op. */
8084 return \".begin_brtab\";
8088 [(set_attr "type" "move")
8089 (set_attr "length" "0")])
8091 (define_insn "end_brtab"
8096 /* Only GAS actually supports this pseudo-op. */
8098 return \".end_brtab\";
8102 [(set_attr "type" "move")
8103 (set_attr "length" "0")])
8105 ;;; EH does longjmp's from and within the data section. Thus,
8106 ;;; an interspace branch is required for the longjmp implementation.
8107 ;;; Registers r1 and r2 are used as scratch registers for the jump
8109 (define_expand "interspace_jump"
8111 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8112 (clobber (match_dup 1))])]
8116 operands[1] = gen_rtx_REG (word_mode, 2);
8120 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8121 (clobber (reg:SI 2))]
8122 "TARGET_PA_20 && !TARGET_64BIT"
8124 [(set_attr "type" "branch")
8125 (set_attr "length" "4")])
8128 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8129 (clobber (reg:SI 2))]
8130 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8132 [(set_attr "type" "branch")
8133 (set_attr "length" "4")])
8136 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8137 (clobber (reg:SI 2))]
8139 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
8140 [(set_attr "type" "branch")
8141 (set_attr "length" "12")])
8144 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8145 (clobber (reg:DI 2))]
8148 [(set_attr "type" "branch")
8149 (set_attr "length" "4")])
8151 (define_expand "builtin_longjmp"
8152 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
8156 /* The elements of the buffer are, in order: */
8157 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8158 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8159 POINTER_SIZE / BITS_PER_UNIT));
8160 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8161 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8162 rtx pv = gen_rtx_REG (Pmode, 1);
8164 /* This bit is the same as expand_builtin_longjmp. */
8165 emit_move_insn (hard_frame_pointer_rtx, fp);
8166 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8167 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8168 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8170 /* Load the label we are jumping through into r1 so that we know
8171 where to look for it when we get back to setjmp's function for
8172 restoring the gp. */
8173 emit_move_insn (pv, lab);
8175 /* Prevent the insns above from being scheduled into the delay slot
8176 of the interspace jump because the space register could change. */
8177 emit_insn (gen_blockage ());
8179 emit_jump_insn (gen_interspace_jump (pv));
8184 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8185 (define_expand "extzv"
8186 [(set (match_operand 0 "register_operand" "")
8187 (zero_extract (match_operand 1 "register_operand" "")
8188 (match_operand 2 "uint32_operand" "")
8189 (match_operand 3 "uint32_operand" "")))]
8193 HOST_WIDE_INT len = INTVAL (operands[2]);
8194 HOST_WIDE_INT pos = INTVAL (operands[3]);
8196 /* PA extraction insns don't support zero length bitfields or fields
8197 extending beyond the left or right-most bits. Also, we reject lengths
8198 equal to a word as they are better handled by the move patterns. */
8199 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8202 /* From mips.md: extract_bit_field doesn't verify that our source
8203 matches the predicate, so check it again here. */
8204 if (!register_operand (operands[1], VOIDmode))
8208 emit_insn (gen_extzv_64 (operands[0], operands[1],
8209 operands[2], operands[3]));
8211 emit_insn (gen_extzv_32 (operands[0], operands[1],
8212 operands[2], operands[3]));
8216 (define_insn "extzv_32"
8217 [(set (match_operand:SI 0 "register_operand" "=r")
8218 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8219 (match_operand:SI 2 "uint5_operand" "")
8220 (match_operand:SI 3 "uint5_operand" "")))]
8222 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8223 [(set_attr "type" "shift")
8224 (set_attr "length" "4")])
8227 [(set (match_operand:SI 0 "register_operand" "=r")
8228 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8230 (match_operand:SI 2 "register_operand" "q")))]
8232 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8233 [(set_attr "type" "shift")
8234 (set_attr "length" "4")])
8236 (define_insn "extzv_64"
8237 [(set (match_operand:DI 0 "register_operand" "=r")
8238 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8239 (match_operand:DI 2 "uint32_operand" "")
8240 (match_operand:DI 3 "uint32_operand" "")))]
8242 "extrd,u %1,%3+%2-1,%2,%0"
8243 [(set_attr "type" "shift")
8244 (set_attr "length" "4")])
8247 [(set (match_operand:DI 0 "register_operand" "=r")
8248 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8250 (match_operand:DI 2 "register_operand" "q")))]
8252 "extrd,u %1,%%sar,1,%0"
8253 [(set_attr "type" "shift")
8254 (set_attr "length" "4")])
8256 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8257 (define_expand "extv"
8258 [(set (match_operand 0 "register_operand" "")
8259 (sign_extract (match_operand 1 "register_operand" "")
8260 (match_operand 2 "uint32_operand" "")
8261 (match_operand 3 "uint32_operand" "")))]
8265 HOST_WIDE_INT len = INTVAL (operands[2]);
8266 HOST_WIDE_INT pos = INTVAL (operands[3]);
8268 /* PA extraction insns don't support zero length bitfields or fields
8269 extending beyond the left or right-most bits. Also, we reject lengths
8270 equal to a word as they are better handled by the move patterns. */
8271 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8274 /* From mips.md: extract_bit_field doesn't verify that our source
8275 matches the predicate, so check it again here. */
8276 if (!register_operand (operands[1], VOIDmode))
8280 emit_insn (gen_extv_64 (operands[0], operands[1],
8281 operands[2], operands[3]));
8283 emit_insn (gen_extv_32 (operands[0], operands[1],
8284 operands[2], operands[3]));
8288 (define_insn "extv_32"
8289 [(set (match_operand:SI 0 "register_operand" "=r")
8290 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8291 (match_operand:SI 2 "uint5_operand" "")
8292 (match_operand:SI 3 "uint5_operand" "")))]
8294 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8295 [(set_attr "type" "shift")
8296 (set_attr "length" "4")])
8299 [(set (match_operand:SI 0 "register_operand" "=r")
8300 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8302 (match_operand:SI 2 "register_operand" "q")))]
8304 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8305 [(set_attr "type" "shift")
8306 (set_attr "length" "4")])
8308 (define_insn "extv_64"
8309 [(set (match_operand:DI 0 "register_operand" "=r")
8310 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8311 (match_operand:DI 2 "uint32_operand" "")
8312 (match_operand:DI 3 "uint32_operand" "")))]
8314 "extrd,s %1,%3+%2-1,%2,%0"
8315 [(set_attr "type" "shift")
8316 (set_attr "length" "4")])
8319 [(set (match_operand:DI 0 "register_operand" "=r")
8320 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8322 (match_operand:DI 2 "register_operand" "q")))]
8324 "extrd,s %1,%%sar,1,%0"
8325 [(set_attr "type" "shift")
8326 (set_attr "length" "4")])
8328 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8329 (define_expand "insv"
8330 [(set (zero_extract (match_operand 0 "register_operand" "")
8331 (match_operand 1 "uint32_operand" "")
8332 (match_operand 2 "uint32_operand" ""))
8333 (match_operand 3 "arith5_operand" ""))]
8337 HOST_WIDE_INT len = INTVAL (operands[1]);
8338 HOST_WIDE_INT pos = INTVAL (operands[2]);
8340 /* PA insertion insns don't support zero length bitfields or fields
8341 extending beyond the left or right-most bits. Also, we reject lengths
8342 equal to a word as they are better handled by the move patterns. */
8343 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8346 /* From mips.md: insert_bit_field doesn't verify that our destination
8347 matches the predicate, so check it again here. */
8348 if (!register_operand (operands[0], VOIDmode))
8352 emit_insn (gen_insv_64 (operands[0], operands[1],
8353 operands[2], operands[3]));
8355 emit_insn (gen_insv_32 (operands[0], operands[1],
8356 operands[2], operands[3]));
8360 (define_insn "insv_32"
8361 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8362 (match_operand:SI 1 "uint5_operand" "")
8363 (match_operand:SI 2 "uint5_operand" ""))
8364 (match_operand:SI 3 "arith5_operand" "r,L"))]
8367 {dep|depw} %3,%2+%1-1,%1,%0
8368 {depi|depwi} %3,%2+%1-1,%1,%0"
8369 [(set_attr "type" "shift,shift")
8370 (set_attr "length" "4,4")])
8372 ;; Optimize insertion of const_int values of type 1...1xxxx.
8374 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8375 (match_operand:SI 1 "uint5_operand" "")
8376 (match_operand:SI 2 "uint5_operand" ""))
8377 (match_operand:SI 3 "const_int_operand" ""))]
8378 "(INTVAL (operands[3]) & 0x10) != 0 &&
8379 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8382 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8383 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8385 [(set_attr "type" "shift")
8386 (set_attr "length" "4")])
8388 (define_insn "insv_64"
8389 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8390 (match_operand:DI 1 "uint32_operand" "")
8391 (match_operand:DI 2 "uint32_operand" ""))
8392 (match_operand:DI 3 "arith32_operand" "r,L"))]
8395 depd %3,%2+%1-1,%1,%0
8396 depdi %3,%2+%1-1,%1,%0"
8397 [(set_attr "type" "shift,shift")
8398 (set_attr "length" "4,4")])
8400 ;; Optimize insertion of const_int values of type 1...1xxxx.
8402 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8403 (match_operand:DI 1 "uint32_operand" "")
8404 (match_operand:DI 2 "uint32_operand" ""))
8405 (match_operand:DI 3 "const_int_operand" ""))]
8406 "(INTVAL (operands[3]) & 0x10) != 0
8408 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8411 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8412 return \"depdi %3,%2+%1-1,%1,%0\";
8414 [(set_attr "type" "shift")
8415 (set_attr "length" "4")])
8418 [(set (match_operand:DI 0 "register_operand" "=r")
8419 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8422 "depd,z %1,31,32,%0"
8423 [(set_attr "type" "shift")
8424 (set_attr "length" "4")])
8426 ;; This insn is used for some loop tests, typically loops reversed when
8427 ;; strength reduction is used. It is actually created when the instruction
8428 ;; combination phase combines the special loop test. Since this insn
8429 ;; is both a jump insn and has an output, it must deal with its own
8430 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8431 ;; to not choose the register alternatives in the event a reload is needed.
8432 (define_insn "decrement_and_branch_until_zero"
8435 (match_operator 2 "comparison_operator"
8437 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8438 (match_operand:SI 1 "int5_operand" "L,L,L"))
8440 (label_ref (match_operand 3 "" ""))
8443 (plus:SI (match_dup 0) (match_dup 1)))
8444 (clobber (match_scratch:SI 4 "=X,r,r"))]
8446 "* return output_dbra (operands, insn, which_alternative); "
8447 ;; Do not expect to understand this the first time through.
8448 [(set_attr "type" "cbranch,multi,multi")
8449 (set (attr "length")
8450 (if_then_else (eq_attr "alternative" "0")
8451 ;; Loop counter in register case
8452 ;; Short branch has length of 4
8453 ;; Long branch has length of 8
8454 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8459 ;; Loop counter in FP reg case.
8460 ;; Extra goo to deal with additional reload insns.
8461 (if_then_else (eq_attr "alternative" "1")
8462 (if_then_else (lt (match_dup 3) (pc))
8464 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8469 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8473 ;; Loop counter in memory case.
8474 ;; Extra goo to deal with additional reload insns.
8475 (if_then_else (lt (match_dup 3) (pc))
8477 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8482 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8485 (const_int 16))))))])
8490 (match_operator 2 "movb_comparison_operator"
8491 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8492 (label_ref (match_operand 3 "" ""))
8494 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8497 "* return output_movb (operands, insn, which_alternative, 0); "
8498 ;; Do not expect to understand this the first time through.
8499 [(set_attr "type" "cbranch,multi,multi,multi")
8500 (set (attr "length")
8501 (if_then_else (eq_attr "alternative" "0")
8502 ;; Loop counter in register case
8503 ;; Short branch has length of 4
8504 ;; Long branch has length of 8
8505 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8510 ;; Loop counter in FP reg case.
8511 ;; Extra goo to deal with additional reload insns.
8512 (if_then_else (eq_attr "alternative" "1")
8513 (if_then_else (lt (match_dup 3) (pc))
8515 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8520 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8524 ;; Loop counter in memory or sar case.
8525 ;; Extra goo to deal with additional reload insns.
8527 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8530 (const_int 12)))))])
8532 ;; Handle negated branch.
8536 (match_operator 2 "movb_comparison_operator"
8537 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8539 (label_ref (match_operand 3 "" ""))))
8540 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8543 "* return output_movb (operands, insn, which_alternative, 1); "
8544 ;; Do not expect to understand this the first time through.
8545 [(set_attr "type" "cbranch,multi,multi,multi")
8546 (set (attr "length")
8547 (if_then_else (eq_attr "alternative" "0")
8548 ;; Loop counter in register case
8549 ;; Short branch has length of 4
8550 ;; Long branch has length of 8
8551 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8556 ;; Loop counter in FP reg case.
8557 ;; Extra goo to deal with additional reload insns.
8558 (if_then_else (eq_attr "alternative" "1")
8559 (if_then_else (lt (match_dup 3) (pc))
8561 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8566 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8570 ;; Loop counter in memory or SAR case.
8571 ;; Extra goo to deal with additional reload insns.
8573 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8576 (const_int 12)))))])
8579 [(set (pc) (label_ref (match_operand 3 "" "" )))
8580 (set (match_operand:SI 0 "ireg_operand" "=r")
8581 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8582 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8583 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8586 return output_parallel_addb (operands, get_attr_length (insn));
8588 [(set_attr "type" "parallel_branch")
8589 (set (attr "length")
8590 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8596 [(set (pc) (label_ref (match_operand 2 "" "" )))
8597 (set (match_operand:SF 0 "ireg_operand" "=r")
8598 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8602 return output_parallel_movb (operands, get_attr_length (insn));
8604 [(set_attr "type" "parallel_branch")
8605 (set (attr "length")
8606 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8612 [(set (pc) (label_ref (match_operand 2 "" "" )))
8613 (set (match_operand:SI 0 "ireg_operand" "=r")
8614 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8618 return output_parallel_movb (operands, get_attr_length (insn));
8620 [(set_attr "type" "parallel_branch")
8621 (set (attr "length")
8622 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8628 [(set (pc) (label_ref (match_operand 2 "" "" )))
8629 (set (match_operand:HI 0 "ireg_operand" "=r")
8630 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8634 return output_parallel_movb (operands, get_attr_length (insn));
8636 [(set_attr "type" "parallel_branch")
8637 (set (attr "length")
8638 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8644 [(set (pc) (label_ref (match_operand 2 "" "" )))
8645 (set (match_operand:QI 0 "ireg_operand" "=r")
8646 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8650 return output_parallel_movb (operands, get_attr_length (insn));
8652 [(set_attr "type" "parallel_branch")
8653 (set (attr "length")
8654 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8660 [(set (match_operand 0 "register_operand" "=f")
8661 (mult (match_operand 1 "register_operand" "f")
8662 (match_operand 2 "register_operand" "f")))
8663 (set (match_operand 3 "register_operand" "+f")
8664 (plus (match_operand 4 "register_operand" "f")
8665 (match_operand 5 "register_operand" "f")))]
8666 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8667 && reload_completed && fmpyaddoperands (operands)"
8670 if (GET_MODE (operands[0]) == DFmode)
8672 if (rtx_equal_p (operands[3], operands[5]))
8673 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8675 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8679 if (rtx_equal_p (operands[3], operands[5]))
8680 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8682 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8685 [(set_attr "type" "fpalu")
8686 (set_attr "length" "4")])
8689 [(set (match_operand 3 "register_operand" "+f")
8690 (plus (match_operand 4 "register_operand" "f")
8691 (match_operand 5 "register_operand" "f")))
8692 (set (match_operand 0 "register_operand" "=f")
8693 (mult (match_operand 1 "register_operand" "f")
8694 (match_operand 2 "register_operand" "f")))]
8695 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8696 && reload_completed && fmpyaddoperands (operands)"
8699 if (GET_MODE (operands[0]) == DFmode)
8701 if (rtx_equal_p (operands[3], operands[5]))
8702 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8704 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8708 if (rtx_equal_p (operands[3], operands[5]))
8709 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8711 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8714 [(set_attr "type" "fpalu")
8715 (set_attr "length" "4")])
8718 [(set (match_operand 0 "register_operand" "=f")
8719 (mult (match_operand 1 "register_operand" "f")
8720 (match_operand 2 "register_operand" "f")))
8721 (set (match_operand 3 "register_operand" "+f")
8722 (minus (match_operand 4 "register_operand" "f")
8723 (match_operand 5 "register_operand" "f")))]
8724 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8725 && reload_completed && fmpysuboperands (operands)"
8728 if (GET_MODE (operands[0]) == DFmode)
8729 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8731 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8733 [(set_attr "type" "fpalu")
8734 (set_attr "length" "4")])
8737 [(set (match_operand 3 "register_operand" "+f")
8738 (minus (match_operand 4 "register_operand" "f")
8739 (match_operand 5 "register_operand" "f")))
8740 (set (match_operand 0 "register_operand" "=f")
8741 (mult (match_operand 1 "register_operand" "f")
8742 (match_operand 2 "register_operand" "f")))]
8743 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8744 && reload_completed && fmpysuboperands (operands)"
8747 if (GET_MODE (operands[0]) == DFmode)
8748 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8750 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8752 [(set_attr "type" "fpalu")
8753 (set_attr "length" "4")])
8755 ;; Clean up turds left by reload.
8757 [(set (match_operand 0 "move_dest_operand" "")
8758 (match_operand 1 "register_operand" "fr"))
8759 (set (match_operand 2 "register_operand" "fr")
8762 && GET_CODE (operands[0]) == MEM
8763 && ! MEM_VOLATILE_P (operands[0])
8764 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8765 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8766 && GET_MODE (operands[0]) == DFmode
8767 && GET_CODE (operands[1]) == REG
8768 && GET_CODE (operands[2]) == REG
8769 && ! side_effects_p (XEXP (operands[0], 0))
8770 && REGNO_REG_CLASS (REGNO (operands[1]))
8771 == REGNO_REG_CLASS (REGNO (operands[2]))"
8776 if (FP_REG_P (operands[1]))
8777 output_asm_insn (output_fp_move_double (operands), operands);
8779 output_asm_insn (output_move_double (operands), operands);
8781 if (rtx_equal_p (operands[1], operands[2]))
8784 xoperands[0] = operands[2];
8785 xoperands[1] = operands[1];
8787 if (FP_REG_P (xoperands[1]))
8788 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8790 output_asm_insn (output_move_double (xoperands), xoperands);
8796 [(set (match_operand 0 "register_operand" "fr")
8797 (match_operand 1 "move_src_operand" ""))
8798 (set (match_operand 2 "register_operand" "fr")
8801 && GET_CODE (operands[1]) == MEM
8802 && ! MEM_VOLATILE_P (operands[1])
8803 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8804 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8805 && GET_MODE (operands[0]) == DFmode
8806 && GET_CODE (operands[0]) == REG
8807 && GET_CODE (operands[2]) == REG
8808 && ! side_effects_p (XEXP (operands[1], 0))
8809 && REGNO_REG_CLASS (REGNO (operands[0]))
8810 == REGNO_REG_CLASS (REGNO (operands[2]))"
8815 if (FP_REG_P (operands[0]))
8816 output_asm_insn (output_fp_move_double (operands), operands);
8818 output_asm_insn (output_move_double (operands), operands);
8820 xoperands[0] = operands[2];
8821 xoperands[1] = operands[0];
8823 if (FP_REG_P (xoperands[1]))
8824 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8826 output_asm_insn (output_move_double (xoperands), xoperands);
8831 ;; Flush the I and D cache line found at the address in operand 0.
8832 ;; This is used by the trampoline code for nested functions.
8833 ;; So long as the trampoline itself is less than 32 bytes this
8836 (define_insn "dcacheflush"
8837 [(unspec_volatile [(const_int 1)] 0)
8838 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
8839 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))]
8841 "fdc 0(%0)\;fdc 0(%1)\;sync"
8842 [(set_attr "type" "multi")
8843 (set_attr "length" "12")])
8845 (define_insn "icacheflush"
8846 [(unspec_volatile [(const_int 2)] 0)
8847 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
8848 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))
8849 (use (match_operand 2 "pmode_register_operand" "r"))
8850 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
8851 (clobber (match_operand 4 "pmode_register_operand" "=&r"))]
8853 "mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
8854 [(set_attr "type" "multi")
8855 (set_attr "length" "52")])
8857 ;; An out-of-line prologue.
8858 (define_insn "outline_prologue_call"
8859 [(unspec_volatile [(const_int 0)] 0)
8860 (clobber (reg:SI 31))
8861 (clobber (reg:SI 22))
8862 (clobber (reg:SI 21))
8863 (clobber (reg:SI 20))
8864 (clobber (reg:SI 19))
8865 (clobber (reg:SI 1))]
8869 extern int frame_pointer_needed;
8871 /* We need two different versions depending on whether or not we
8872 need a frame pointer. Also note that we return to the instruction
8873 immediately after the branch rather than two instructions after the
8874 break as normally is the case. */
8875 if (frame_pointer_needed)
8877 /* Must import the magic millicode routine(s). */
8878 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
8880 if (TARGET_PORTABLE_RUNTIME)
8882 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
8883 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
8887 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
8891 /* Must import the magic millicode routine(s). */
8892 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
8894 if (TARGET_PORTABLE_RUNTIME)
8896 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
8897 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
8900 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
8904 [(set_attr "type" "multi")
8905 (set_attr "length" "8")])
8907 ;; An out-of-line epilogue.
8908 (define_insn "outline_epilogue_call"
8909 [(unspec_volatile [(const_int 1)] 0)
8912 (clobber (reg:SI 31))
8913 (clobber (reg:SI 22))
8914 (clobber (reg:SI 21))
8915 (clobber (reg:SI 20))
8916 (clobber (reg:SI 19))
8917 (clobber (reg:SI 2))
8918 (clobber (reg:SI 1))]
8922 extern int frame_pointer_needed;
8924 /* We need two different versions depending on whether or not we
8925 need a frame pointer. Also note that we return to the instruction
8926 immediately after the branch rather than two instructions after the
8927 break as normally is the case. */
8928 if (frame_pointer_needed)
8930 /* Must import the magic millicode routine. */
8931 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
8933 /* The out-of-line prologue will make sure we return to the right
8935 if (TARGET_PORTABLE_RUNTIME)
8937 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
8938 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
8942 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
8946 /* Must import the magic millicode routine. */
8947 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
8949 /* The out-of-line prologue will make sure we return to the right
8951 if (TARGET_PORTABLE_RUNTIME)
8953 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
8954 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
8957 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
8961 [(set_attr "type" "multi")
8962 (set_attr "length" "8")])
8964 ;; Given a function pointer, canonicalize it so it can be
8965 ;; reliably compared to another function pointer. */
8966 (define_expand "canonicalize_funcptr_for_compare"
8967 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
8968 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
8969 (clobber (match_dup 2))
8970 (clobber (reg:SI 26))
8971 (clobber (reg:SI 22))
8972 (clobber (reg:SI 31))])
8973 (set (match_operand:SI 0 "register_operand" "")
8975 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8980 rtx canonicalize_funcptr_for_compare_libfunc
8981 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
8983 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
8984 operands[0], LCT_NORMAL, Pmode,
8985 1, operands[1], Pmode);
8989 operands[2] = gen_reg_rtx (SImode);
8990 if (GET_CODE (operands[1]) != REG)
8992 rtx tmp = gen_reg_rtx (Pmode);
8993 emit_move_insn (tmp, operands[1]);
8999 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9000 (clobber (match_operand:SI 0 "register_operand" "=a"))
9001 (clobber (reg:SI 26))
9002 (clobber (reg:SI 22))
9003 (clobber (reg:SI 31))]
9007 int length = get_attr_length (insn);
9010 xoperands[0] = GEN_INT (length - 8);
9011 xoperands[1] = GEN_INT (length - 16);
9013 /* Must import the magic millicode routine. */
9014 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9016 /* This is absolutely amazing.
9018 First, copy our input parameter into %r29 just in case we don't
9019 need to call $$sh_func_adrs. */
9020 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9021 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9023 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9024 we use %r26 unchanged. */
9025 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9026 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9028 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9029 4096, then again we use %r26 unchanged. */
9030 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9032 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9033 return output_millicode_call (insn,
9034 gen_rtx_SYMBOL_REF (SImode,
9035 \"$$sh_func_adrs\"));
9037 [(set_attr "type" "multi")
9038 (set (attr "length")
9039 (plus (symbol_ref "attr_length_millicode_call (insn)")
9042 ;; On the PA, the PIC register is call clobbered, so it must
9043 ;; be saved & restored around calls by the caller. If the call
9044 ;; doesn't return normally (nonlocal goto, or an exception is
9045 ;; thrown), then the code at the exception handler label must
9046 ;; restore the PIC register.
9047 (define_expand "exception_receiver"
9052 /* On the 64-bit port, we need a blockage because there is
9053 confusion regarding the dependence of the restore on the
9054 frame pointer. As a result, the frame pointer and pic
9055 register restores sometimes are interchanged erroneously. */
9057 emit_insn (gen_blockage ());
9058 /* Restore the PIC register using hppa_pic_save_rtx (). The
9059 PIC register is not saved in the frame in 64-bit ABI. */
9060 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9061 emit_insn (gen_blockage ());
9065 (define_expand "builtin_setjmp_receiver"
9066 [(label_ref (match_operand 0 "" ""))]
9071 emit_insn (gen_blockage ());
9072 /* Restore the PIC register. Hopefully, this will always be from
9073 a stack slot. The only registers that are valid after a
9074 builtin_longjmp are the stack and frame pointers. */
9075 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9076 emit_insn (gen_blockage ());
9080 ;; Allocate new stack space and update the saved stack pointer in the
9081 ;; frame marker. The HP C compilers also copy additional words in the
9082 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9083 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9084 ;; currently don't copy these values.
9086 ;; Since the copy of the frame marker can't be done atomically, I
9087 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9088 ;; The HP compilers appear to raise the stack and copy the frame
9089 ;; marker in a strict instruction sequence. This suggests that the
9090 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9091 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9092 ;; as GAS doesn't support it, or try to keep the instructions emitted
9093 ;; here in strict sequence.
9094 (define_expand "allocate_stack"
9095 [(match_operand 0 "" "")
9096 (match_operand 1 "" "")]
9102 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9103 in operand 0 before adjusting the stack. */
9104 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9105 anti_adjust_stack (operands[1]);
9106 if (TARGET_HPUX_UNWIND_LIBRARY)
9108 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9109 GEN_INT (TARGET_64BIT ? -8 : -4));
9110 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9112 if (!TARGET_64BIT && flag_pic)
9114 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9115 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);