1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 enum cmp_type /* comparison type */
27 CMP_SI, /* compare integers */
28 CMP_SF, /* compare single precision floats */
29 CMP_DF, /* compare double precision floats */
30 CMP_MAX /* max comparison type */
33 /* For long call handling. */
34 extern unsigned long total_code_bytes;
36 /* Which processor to schedule for. */
48 /* For -mschedule= option. */
49 extern const char *pa_cpu_string;
50 extern enum processor_type pa_cpu;
52 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
54 /* Which architecture to generate code for. */
56 enum architecture_type
65 /* For -march= option. */
66 extern const char *pa_arch_string;
67 extern enum architecture_type pa_arch;
69 /* Print subsidiary information on the compiler version in use. */
71 #define TARGET_VERSION fputs (" (hppa)", stderr);
73 /* Run-time compilation parameters selecting different hardware subsets. */
75 extern int target_flags;
77 /* compile code for HP-PA 1.1 ("Snake"). */
81 /* Disable all FP registers (they all become fixed). This may be necessary
82 for compiling kernels which perform lazy context switching of FP regs.
83 Note if you use this option and try to perform floating point operations
84 the compiler will abort! */
86 #define MASK_DISABLE_FPREGS 2
87 #define TARGET_DISABLE_FPREGS (target_flags & MASK_DISABLE_FPREGS)
89 /* Generate code which assumes that all space register are equivalent.
90 Triggers aggressive unscaled index addressing and faster
91 builtin_return_address. */
92 #define MASK_NO_SPACE_REGS 4
93 #define TARGET_NO_SPACE_REGS (target_flags & MASK_NO_SPACE_REGS)
95 /* Allow unconditional jumps in the delay slots of call instructions. */
96 #define MASK_JUMP_IN_DELAY 8
97 #define TARGET_JUMP_IN_DELAY (target_flags & MASK_JUMP_IN_DELAY)
99 /* Disable indexed addressing modes. */
100 #define MASK_DISABLE_INDEXING 32
101 #define TARGET_DISABLE_INDEXING (target_flags & MASK_DISABLE_INDEXING)
103 /* Emit code which follows the new portable runtime calling conventions
104 HP wants everyone to use for ELF objects. If at all possible you want
105 to avoid this since it's a performance loss for non-prototyped code.
107 Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline
108 long-call stubs which is quite expensive. */
109 #define MASK_PORTABLE_RUNTIME 64
110 #define TARGET_PORTABLE_RUNTIME (target_flags & MASK_PORTABLE_RUNTIME)
112 /* Emit directives only understood by GAS. This allows parameter
113 relocations to work for static functions. There is no way
114 to make them work the HP assembler at this time. */
116 #define TARGET_GAS (target_flags & MASK_GAS)
118 /* Emit code for processors which do not have an FPU. */
119 #define MASK_SOFT_FLOAT 256
120 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
122 /* Use 3-insn load/store sequences for access to large data segments
123 in shared libraries on hpux10. */
124 #define MASK_LONG_LOAD_STORE 512
125 #define TARGET_LONG_LOAD_STORE (target_flags & MASK_LONG_LOAD_STORE)
127 /* Use a faster sequence for indirect calls. This assumes that calls
128 through function pointers will never cross a space boundary, and
129 that the executable is not dynamically linked. Such assumptions
130 are generally safe for building kernels and statically linked
131 executables. Code compiled with this option will fail miserably if
132 the executable is dynamically linked or uses nested functions! */
133 #define MASK_FAST_INDIRECT_CALLS 1024
134 #define TARGET_FAST_INDIRECT_CALLS (target_flags & MASK_FAST_INDIRECT_CALLS)
136 /* Generate code with big switch statements to avoid out of range branches
137 occurring within the switch table. */
138 #define MASK_BIG_SWITCH 2048
139 #define TARGET_BIG_SWITCH (target_flags & MASK_BIG_SWITCH)
141 /* Generate code for the HPPA 2.0 architecture. TARGET_PA_11 should also be
142 true when this is true. */
143 #define MASK_PA_20 4096
145 /* Generate cpp defines for server I/O. */
146 #define MASK_SIO 8192
147 #define TARGET_SIO (target_flags & MASK_SIO)
149 /* Assume GNU linker by default. */
150 #define MASK_GNU_LD 16384
151 #ifndef TARGET_GNU_LD
152 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
155 /* Force generation of long calls. */
156 #define MASK_LONG_CALLS 32768
157 #ifndef TARGET_LONG_CALLS
158 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
162 #define TARGET_PA_10 (target_flags & (MASK_PA_11 | MASK_PA_20) == 0)
166 #define TARGET_PA_11 (target_flags & MASK_PA_11)
170 #define TARGET_PA_20 (target_flags & MASK_PA_20)
173 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
175 #define TARGET_64BIT 0
178 /* Generate code for ELF32 ABI. */
180 #define TARGET_ELF32 0
183 /* Generate code for SOM 32bit ABI. */
188 /* The following three defines are potential target switches. The current
189 defines are optimal given the current capabilities of GAS and GNU ld. */
191 /* Define to a C expression evaluating to true to use long absolute calls.
192 Currently, only the HP assembler and SOM linker support long absolute
193 calls. They are used only in non-pic code. */
194 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
196 /* Define to a C expression evaluating to true to use long pic symbol
197 difference calls. This is a call variant similar to the long pic
198 pc-relative call. Long pic symbol difference calls are only used with
199 the HP SOM linker. Currently, only the HP assembler supports these
200 calls. GAS doesn't allow an arbitrary difference of two symbols. */
201 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
203 /* Define to a C expression evaluating to true to use long pic
204 pc-relative calls. Long pic pc-relative calls are only used with
205 GAS. Currently, they are usable for calls within a module but
206 not for external calls. */
207 #define TARGET_LONG_PIC_PCREL_CALL 0
209 /* Define to a C expression evaluating to true to use SOM secondary
210 definition symbols for weak support. Linker support for secondary
211 definition symbols is buggy prior to HP-UX 11.X. */
212 #define TARGET_SOM_SDEF 0
214 /* Define to a C expression evaluating to true to save the entry value
215 of SP in the current frame marker. This is normally unnecessary.
216 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
217 HP compilers don't use this flag but it is supported by the assembler.
218 We set this flag to indicate that register %r3 has been saved at the
219 start of the frame. Thus, when the HP unwind library is used, we
220 need to generate additional code to save SP into the frame marker. */
221 #define TARGET_HPUX_UNWIND_LIBRARY 0
223 /* Macro to define tables used to set the flags. This is a
224 list in braces of target switches with each switch being
225 { "NAME", VALUE, "HELP_STRING" }. VALUE is the bits to set,
226 or minus the bits to clear. An empty string NAME is used to
227 identify the default VALUE. Do not mark empty strings for
230 #define TARGET_SWITCHES \
231 {{ "snake", MASK_PA_11, \
232 N_("Generate PA1.1 code") }, \
233 { "nosnake", -(MASK_PA_11 | MASK_PA_20), \
234 N_("Generate PA1.0 code") }, \
235 { "pa-risc-1-0", -(MASK_PA_11 | MASK_PA_20), \
236 N_("Generate PA1.0 code") }, \
237 { "pa-risc-1-1", MASK_PA_11, \
238 N_("Generate PA1.1 code") }, \
239 { "pa-risc-2-0", MASK_PA_20, \
240 N_("Generate PA2.0 code (requires binutils 2.10 or later)") }, \
241 { "disable-fpregs", MASK_DISABLE_FPREGS, \
242 N_("Disable FP regs") }, \
243 { "no-disable-fpregs", -MASK_DISABLE_FPREGS, \
244 N_("Do not disable FP regs") }, \
245 { "no-space-regs", MASK_NO_SPACE_REGS, \
246 N_("Disable space regs") }, \
247 { "space-regs", -MASK_NO_SPACE_REGS, \
248 N_("Do not disable space regs") }, \
249 { "jump-in-delay", MASK_JUMP_IN_DELAY, \
250 N_("Put jumps in call delay slots") }, \
251 { "no-jump-in-delay", -MASK_JUMP_IN_DELAY, \
252 N_("Do not put jumps in call delay slots") }, \
253 { "disable-indexing", MASK_DISABLE_INDEXING, \
254 N_("Disable indexed addressing") }, \
255 { "no-disable-indexing", -MASK_DISABLE_INDEXING, \
256 N_("Do not disable indexed addressing") }, \
257 { "portable-runtime", MASK_PORTABLE_RUNTIME, \
258 N_("Use portable calling conventions") }, \
259 { "no-portable-runtime", -MASK_PORTABLE_RUNTIME, \
260 N_("Do not use portable calling conventions") }, \
262 N_("Assume code will be assembled by GAS") }, \
263 { "no-gas", -MASK_GAS, \
264 N_("Do not assume code will be assembled by GAS") }, \
265 { "soft-float", MASK_SOFT_FLOAT, \
266 N_("Use software floating point") }, \
267 { "no-soft-float", -MASK_SOFT_FLOAT, \
268 N_("Do not use software floating point") }, \
269 { "long-load-store", MASK_LONG_LOAD_STORE, \
270 N_("Emit long load/store sequences") }, \
271 { "no-long-load-store", -MASK_LONG_LOAD_STORE, \
272 N_("Do not emit long load/store sequences") }, \
273 { "fast-indirect-calls", MASK_FAST_INDIRECT_CALLS, \
274 N_("Generate fast indirect calls") }, \
275 { "no-fast-indirect-calls", -MASK_FAST_INDIRECT_CALLS, \
276 N_("Do not generate fast indirect calls") }, \
277 { "big-switch", MASK_BIG_SWITCH, \
278 N_("Generate code for huge switch statements") }, \
279 { "no-big-switch", -MASK_BIG_SWITCH, \
280 N_("Do not generate code for huge switch statements") }, \
281 { "long-calls", MASK_LONG_CALLS, \
282 N_("Always generate long calls") }, \
283 { "no-long-calls", -MASK_LONG_CALLS, \
284 N_("Generate long calls only when needed") }, \
286 N_("Enable linker optimizations") }, \
288 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
291 #ifndef TARGET_DEFAULT
292 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
295 #ifndef TARGET_CPU_DEFAULT
296 #define TARGET_CPU_DEFAULT 0
299 #ifndef SUBTARGET_SWITCHES
300 #define SUBTARGET_SWITCHES
303 #ifndef TARGET_SCHED_DEFAULT
304 #define TARGET_SCHED_DEFAULT "8000"
307 #define TARGET_OPTIONS \
309 { "schedule=", &pa_cpu_string, \
310 N_("Specify CPU for scheduling purposes"), 0}, \
311 { "arch=", &pa_arch_string, \
312 N_("Specify architecture for code generation. Values are 1.0, 1.1, and 2.0. 2.0 requires gas snapshot 19990413 or later."), 0}\
315 /* Support for a compile-time default CPU, et cetera. The rules are:
316 --with-schedule is ignored if -mschedule is specified.
317 --with-arch is ignored if -march is specified. */
318 #define OPTION_DEFAULT_SPECS \
319 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
320 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
322 /* Specify the dialect of assembler to use. New mnemonics is dialect one
323 and the old mnemonics are dialect zero. */
324 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
326 #define OVERRIDE_OPTIONS override_options ()
328 /* Override some settings from dbxelf.h. */
330 /* We do not have to be compatible with dbx, so we enable gdb extensions
332 #define DEFAULT_GDB_EXTENSIONS 1
334 /* This used to be zero (no max length), but big enums and such can
335 cause huge strings which killed gas.
337 We also have to avoid lossage in dbxout.c -- it does not compute the
338 string size accurately, so we are real conservative here. */
339 #undef DBX_CONTIN_LENGTH
340 #define DBX_CONTIN_LENGTH 3000
342 /* Only labels should ever begin in column zero. */
343 #define ASM_STABS_OP "\t.stabs\t"
344 #define ASM_STABN_OP "\t.stabn\t"
346 /* GDB always assumes the current function's frame begins at the value
347 of the stack pointer upon entry to the current function. Accessing
348 local variables and parameters passed on the stack is done using the
349 base of the frame + an offset provided by GCC.
351 For functions which have frame pointers this method works fine;
352 the (frame pointer) == (stack pointer at function entry) and GCC provides
353 an offset relative to the frame pointer.
355 This loses for functions without a frame pointer; GCC provides an offset
356 which is relative to the stack pointer after adjusting for the function's
357 frame size. GDB would prefer the offset to be relative to the value of
358 the stack pointer at the function's entry. Yuk! */
359 #define DEBUGGER_AUTO_OFFSET(X) \
360 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
361 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
363 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
364 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
365 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
367 #define TARGET_CPU_CPP_BUILTINS() \
369 builtin_assert("cpu=hppa"); \
370 builtin_assert("machine=hppa"); \
371 builtin_define("__hppa"); \
372 builtin_define("__hppa__"); \
374 builtin_define("_PA_RISC2_0"); \
375 else if (TARGET_PA_11) \
376 builtin_define("_PA_RISC1_1"); \
378 builtin_define("_PA_RISC1_0"); \
381 /* An old set of OS defines for various BSD-like systems. */
382 #define TARGET_OS_CPP_BUILTINS() \
385 builtin_define_std ("REVARGV"); \
386 builtin_define_std ("hp800"); \
387 builtin_define_std ("hp9000"); \
388 builtin_define_std ("hp9k8"); \
389 if (!c_dialect_cxx () && !flag_iso) \
390 builtin_define ("hppa"); \
391 builtin_define_std ("spectrum"); \
392 builtin_define_std ("unix"); \
393 builtin_assert ("system=bsd"); \
394 builtin_assert ("system=unix"); \
398 #define CC1_SPEC "%{pg:} %{p:}"
400 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
402 /* We don't want -lg. */
404 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
407 /* This macro defines command-line switches that modify the default
410 The definition is be an initializer for an array of structures. Each
411 array element has have three elements: the switch name, one of the
412 enumeration codes ADD or DELETE to indicate whether the string should be
413 inserted or deleted, and the string to be inserted or deleted. */
414 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
416 /* Make gcc agree with <machine/ansi.h> */
418 #define SIZE_TYPE "unsigned int"
419 #define PTRDIFF_TYPE "int"
420 #define WCHAR_TYPE "unsigned int"
421 #define WCHAR_TYPE_SIZE 32
423 /* Show we can debug even without a frame pointer. */
424 #define CAN_DEBUG_WITHOUT_FP
426 /* target machine storage layout */
428 /* Define this macro if it is advisable to hold scalars in registers
429 in a wider mode than that declared by the program. In such cases,
430 the value is constrained to be within the bounds of the declared
431 type, but kept valid in the wider mode. The signedness of the
432 extension may differ from that of the type. */
434 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
435 if (GET_MODE_CLASS (MODE) == MODE_INT \
436 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
439 /* Define this if most significant bit is lowest numbered
440 in instructions that operate on numbered bit-fields. */
441 #define BITS_BIG_ENDIAN 1
443 /* Define this if most significant byte of a word is the lowest numbered. */
444 /* That is true on the HP-PA. */
445 #define BYTES_BIG_ENDIAN 1
447 /* Define this if most significant word of a multiword number is lowest
449 #define WORDS_BIG_ENDIAN 1
451 #define MAX_BITS_PER_WORD 64
453 /* Width of a word, in units (bytes). */
454 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
455 #define MIN_UNITS_PER_WORD 4
457 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
458 #define PARM_BOUNDARY BITS_PER_WORD
460 /* Largest alignment required for any stack parameter, in bits.
461 Don't define this if it is equal to PARM_BOUNDARY */
462 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
464 /* Boundary (in *bits*) on which stack pointer is always aligned;
465 certain optimizations in combine depend on this.
467 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
468 the stack on the 32 and 64-bit ports, respectively. However, we
469 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
470 in main. Thus, we treat the former as the preferred alignment. */
471 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
472 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
474 /* Allocation boundary (in *bits*) for the code of a function. */
475 #define FUNCTION_BOUNDARY BITS_PER_WORD
477 /* Alignment of field after `int : 0' in a structure. */
478 #define EMPTY_FIELD_BOUNDARY 32
480 /* Every structure's size must be a multiple of this. */
481 #define STRUCTURE_SIZE_BOUNDARY 8
483 /* A bit-field declared as `int' forces `int' alignment for the struct. */
484 #define PCC_BITFIELD_TYPE_MATTERS 1
486 /* No data type wants to be aligned rounder than this. */
487 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
489 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
490 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
491 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
493 /* Make arrays of chars word-aligned for the same reasons. */
494 #define DATA_ALIGNMENT(TYPE, ALIGN) \
495 (TREE_CODE (TYPE) == ARRAY_TYPE \
496 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
497 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
499 /* Set this nonzero if move instructions will actually fail to work
500 when given unaligned data. */
501 #define STRICT_ALIGNMENT 1
503 /* Value is 1 if it is a good idea to tie two pseudo registers
504 when one has mode MODE1 and one has mode MODE2.
505 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
506 for any hard reg, then this must be 0 for correct output. */
507 #define MODES_TIEABLE_P(MODE1, MODE2) \
508 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
510 /* Specify the registers used for certain standard purposes.
511 The values of these macros are register numbers. */
513 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
514 /* #define PC_REGNUM */
516 /* Register to use for pushing function arguments. */
517 #define STACK_POINTER_REGNUM 30
519 /* Base register for access to local variables of the function. */
520 #define FRAME_POINTER_REGNUM 3
522 /* Value should be nonzero if functions must have frame pointers. */
523 #define FRAME_POINTER_REQUIRED \
524 (current_function_calls_alloca)
526 /* C statement to store the difference between the frame pointer
527 and the stack pointer values immediately after the function prologue.
529 Note, we always pretend that this is a leaf function because if
530 it's not, there's no point in trying to eliminate the
531 frame pointer. If it is a leaf function, we guessed right! */
532 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
533 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
535 /* Base register for access to arguments of the function. */
536 #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
538 /* Register in which static-chain is passed to a function. */
539 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
541 /* Register used to address the offset table for position-independent
543 #define PIC_OFFSET_TABLE_REGNUM \
544 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
546 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
548 /* Function to return the rtx used to save the pic offset table register
549 across function calls. */
550 extern struct rtx_def *hppa_pic_save_rtx (void);
552 #define DEFAULT_PCC_STRUCT_RETURN 0
554 /* Register in which address to store a structure value
555 is passed to a function. */
556 #define PA_STRUCT_VALUE_REGNUM 28
558 /* Describe how we implement __builtin_eh_return. */
559 #define EH_RETURN_DATA_REGNO(N) \
560 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
561 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
562 #define EH_RETURN_HANDLER_RTX \
563 gen_rtx_MEM (word_mode, \
564 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
565 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
568 /* Offset from the argument pointer register value to the top of
569 stack. This is different from FIRST_PARM_OFFSET because of the
571 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
573 /* The letters I, J, K, L and M in a register constraint string
574 can be used to stand for particular ranges of immediate operands.
575 This macro defines what the ranges are.
576 C is the letter, and VALUE is a constant value.
577 Return 1 if VALUE is in the range specified by C.
579 `I' is used for the 11 bit constants.
580 `J' is used for the 14 bit constants.
581 `K' is used for values that can be moved with a zdepi insn.
582 `L' is used for the 5 bit constants.
584 `N' is used for values with the least significant 11 bits equal to zero
585 and when sign extended from 32 to 64 bits the
586 value does not change.
587 `O' is used for numbers n such that n+1 is a power of 2.
590 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
591 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \
592 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \
593 : (C) == 'K' ? zdepi_cint_p (VALUE) \
594 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \
595 : (C) == 'M' ? (VALUE) == 0 \
596 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \
597 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
598 == (HOST_WIDE_INT) -1 << 31)) \
599 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \
600 : (C) == 'P' ? and_mask_p (VALUE) \
603 /* Similar, but for floating or large integer constants, and defining letters
604 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
606 For PA, `G' is the floating-point constant zero. `H' is undefined. */
608 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
609 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
610 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
613 /* The class value for index registers, and the one for base regs. */
614 #define INDEX_REG_CLASS GENERAL_REGS
615 #define BASE_REG_CLASS GENERAL_REGS
617 #define FP_REG_CLASS_P(CLASS) \
618 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
620 /* True if register is floating-point. */
621 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
623 /* Given an rtx X being reloaded into a reg required to be
624 in class CLASS, return the class of reg to actually use.
625 In general this is just CLASS; but on some machines
626 in some cases it is preferable to use a more restrictive class. */
627 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
629 /* Return the register class of a scratch register needed to copy
630 IN into a register in CLASS in MODE, or a register in CLASS in MODE
631 to IN. If it can be done directly NO_REGS is returned.
633 Avoid doing any work for the common case calls. */
634 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
635 ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \
636 && REGNO (IN) < FIRST_PSEUDO_REGISTER) \
637 ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
639 #define MAYBE_FP_REG_CLASS_P(CLASS) \
640 reg_classes_intersect_p ((CLASS), FP_REGS)
642 /* On the PA it is not possible to directly move data between
643 GENERAL_REGS and FP_REGS. */
644 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
645 (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
646 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))
648 /* Return the stack location to use for secondary memory needed reloads. */
649 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
650 gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
653 /* Stack layout; function entry, exit and calling. */
655 /* Define this if pushing a word on the stack
656 makes the stack pointer a smaller address. */
657 /* #define STACK_GROWS_DOWNWARD */
659 /* Believe it or not. */
660 #define ARGS_GROW_DOWNWARD
662 /* Define this if the nominal address of the stack frame
663 is at the high-address end of the local variables;
664 that is, each additional local variable allocated
665 goes at a more negative offset in the frame. */
666 /* #define FRAME_GROWS_DOWNWARD */
668 /* Offset within stack frame to start allocating local variables at.
669 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
670 first local allocated. Otherwise, it is the offset to the BEGINNING
671 of the first local allocated.
673 On the 32-bit ports, we reserve one slot for the previous frame
674 pointer and one fill slot. The fill slot is for compatibility
675 with HP compiled programs. On the 64-bit ports, we reserve one
676 slot for the previous frame pointer. */
677 #define STARTING_FRAME_OFFSET 8
679 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
680 of the stack. The default is to align it to STACK_BOUNDARY. */
681 #define STACK_ALIGNMENT_NEEDED 0
683 /* If we generate an insn to push BYTES bytes,
684 this says how many the stack pointer really advances by.
685 On the HP-PA, don't define this because there are no push insns. */
686 /* #define PUSH_ROUNDING(BYTES) */
688 /* Offset of first parameter from the argument pointer register value.
689 This value will be negated because the arguments grow down.
690 Also note that on STACK_GROWS_UPWARD machines (such as this one)
691 this is the distance from the frame pointer to the end of the first
692 argument, not it's beginning. To get the real offset of the first
693 argument, the size of the argument must be added. */
695 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
697 /* When a parameter is passed in a register, stack space is still
699 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
701 /* Define this if the above stack space is to be considered part of the
702 space allocated by the caller. */
703 #define OUTGOING_REG_PARM_STACK_SPACE
705 /* Keep the stack pointer constant throughout the function.
706 This is both an optimization and a necessity: longjmp
707 doesn't behave itself when the stack pointer moves within
709 #define ACCUMULATE_OUTGOING_ARGS 1
711 /* The weird HPPA calling conventions require a minimum of 48 bytes on
712 the stack: 16 bytes for register saves, and 32 bytes for magic.
713 This is the difference between the logical top of stack and the
716 On the 64-bit port, the HP C compiler allocates a 48-byte frame
717 marker, although the runtime documentation only describes a 16
718 byte marker. For compatibility, we allocate 48 bytes. */
719 #define STACK_POINTER_OFFSET \
720 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
722 #define STACK_DYNAMIC_OFFSET(FNDECL) \
724 ? (STACK_POINTER_OFFSET) \
725 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
727 /* Value is 1 if returning from a function call automatically
728 pops the arguments described by the number-of-args field in the call.
729 FUNDECL is the declaration node of the function (as a tree),
730 FUNTYPE is the data type of the function (as a tree),
731 or for a library call it is an identifier node for the subroutine name. */
733 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
735 /* Define how to find the value returned by a function.
736 VALTYPE is the data type of the value (as a tree).
737 If the precise function being called is known, FUNC is its FUNCTION_DECL;
738 otherwise, FUNC is 0. */
740 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
742 /* Define how to find the value returned by a library function
743 assuming the value has mode MODE. */
745 #define LIBCALL_VALUE(MODE) \
747 (! TARGET_SOFT_FLOAT \
748 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
750 /* 1 if N is a possible register number for a function value
751 as seen by the caller. */
753 #define FUNCTION_VALUE_REGNO_P(N) \
754 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
757 /* Define a data type for recording info about an argument list
758 during the scan of that argument list. This data type should
759 hold all necessary information about the function itself
760 and about the args processed so far, enough to enable macros
761 such as FUNCTION_ARG to determine where the next arg should go.
763 On the HP-PA, the WORDS field holds the number of words
764 of arguments scanned so far (including the invisible argument,
765 if any, which holds the structure-value-address). Thus, 4 or
766 more means all following args should go on the stack.
768 The INCOMING field tracks whether this is an "incoming" or
771 The INDIRECT field indicates whether this is is an indirect
774 The NARGS_PROTOTYPE field indicates that an argument does not
775 have a prototype when it less than or equal to 0. */
777 struct hppa_args {int words, nargs_prototype, incoming, indirect; };
779 #define CUMULATIVE_ARGS struct hppa_args
781 /* Initialize a variable CUM of type CUMULATIVE_ARGS
782 for a call to a function whose data type is FNTYPE.
783 For a library call, FNTYPE is 0. */
785 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
787 (CUM).incoming = 0, \
788 (CUM).indirect = (FNTYPE) && !(FNDECL), \
789 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
790 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
791 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
792 || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
797 /* Similar, but when scanning the definition of a procedure. We always
798 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
800 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
802 (CUM).incoming = 1, \
803 (CUM).indirect = 0, \
804 (CUM).nargs_prototype = 1000
806 /* Figure out the size in words of the function argument. The size
807 returned by this macro should always be greater than zero because
808 we pass variable and zero sized objects by reference. */
810 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
811 ((((MODE) != BLKmode \
812 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
813 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
815 /* Update the data in CUM to advance over an argument
816 of mode MODE and data type TYPE.
817 (TYPE is null for libcalls where that information may not be available.) */
819 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
820 { (CUM).nargs_prototype--; \
821 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
822 + (((CUM).words & 01) && (TYPE) != 0 \
823 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
826 /* Determine where to put an argument to a function.
827 Value is zero to push the argument on the stack,
828 or a hard register in which to store the argument.
830 MODE is the argument's machine mode.
831 TYPE is the data type of the argument (as a tree).
832 This is null for libcalls where that information may
834 CUM is a variable of type CUMULATIVE_ARGS which gives info about
835 the preceding args and about the function being called.
836 NAMED is nonzero if this argument is a named parameter
837 (otherwise it is an extra parameter matching an ellipsis).
839 On the HP-PA the first four words of args are normally in registers
840 and the rest are pushed. But any arg that won't entirely fit in regs
843 Arguments passed in registers are either 1 or 2 words long.
845 The caller must make a distinction between calls to explicitly named
846 functions and calls through pointers to functions -- the conventions
847 are different! Calls through pointers to functions only use general
848 registers for the first four argument words.
850 Of course all this is different for the portable runtime model
851 HP wants everyone to use for ELF. Ugh. Here's a quick description
852 of how it's supposed to work.
854 1) callee side remains unchanged. It expects integer args to be
855 in the integer registers, float args in the float registers and
856 unnamed args in integer registers.
858 2) caller side now depends on if the function being called has
859 a prototype in scope (rather than if it's being called indirectly).
861 2a) If there is a prototype in scope, then arguments are passed
862 according to their type (ints in integer registers, floats in float
863 registers, unnamed args in integer registers.
865 2b) If there is no prototype in scope, then floating point arguments
866 are passed in both integer and float registers. egad.
868 FYI: The portable parameter passing conventions are almost exactly like
869 the standard parameter passing conventions on the RS6000. That's why
870 you'll see lots of similar code in rs6000.h. */
872 /* If defined, a C expression which determines whether, and in which
873 direction, to pad out an argument with extra space. */
874 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
876 /* Specify padding for the last element of a block move between registers
879 The 64-bit runtime specifies that objects need to be left justified
880 (i.e., the normal justification for a big endian target). The 32-bit
881 runtime specifies right justification for objects smaller than 64 bits.
882 We use a DImode register in the parallel for 5 to 7 byte structures
883 so that there is only one element. This allows the object to be
885 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) (TARGET_64BIT ? upward : downward)
887 /* Do not expect to understand this without reading it several times. I'm
888 tempted to try and simply it, but I worry about breaking something. */
890 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
891 function_arg (&CUM, MODE, TYPE, NAMED)
893 /* For an arg passed partly in registers and partly in memory,
894 this is the number of registers used.
895 For args passed entirely in registers or entirely in memory, zero. */
897 /* For PA32 there are never split arguments. PA64, on the other hand, can
898 pass arguments partially in registers and partially in memory. */
899 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
900 (TARGET_64BIT ? function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) : 0)
902 /* If defined, a C expression that gives the alignment boundary, in
903 bits, of an argument with the specified mode and type. If it is
904 not defined, `PARM_BOUNDARY' is used for all arguments. */
906 /* Arguments larger than one word are double word aligned. */
908 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
910 ? (integer_zerop (TYPE_SIZE (TYPE)) \
911 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
912 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
913 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
914 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
916 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) 1
919 extern GTY(()) rtx hppa_compare_op0;
920 extern GTY(()) rtx hppa_compare_op1;
921 extern enum cmp_type hppa_branch_type;
923 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
924 as assembly via FUNCTION_PROFILER. Just output a local label.
925 We can't use the function label because the GAS SOM target can't
926 handle the difference of a global symbol and a local symbol. */
928 #ifndef FUNC_BEGIN_PROLOG_LABEL
929 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
932 #define FUNCTION_PROFILER(FILE, LABEL) \
933 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
935 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
936 void hppa_profile_hook (int label_no);
938 /* The profile counter if emitted must come before the prologue. */
939 #define PROFILE_BEFORE_PROLOGUE 1
941 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
942 the stack pointer does not matter. The value is tested only in
943 functions that have frame pointers.
944 No definition is equivalent to always zero. */
946 extern int may_call_alloca;
948 #define EXIT_IGNORE_STACK \
949 (get_frame_size () != 0 \
950 || current_function_calls_alloca || current_function_outgoing_args_size)
952 /* Output assembler code for a block containing the constant parts
953 of a trampoline, leaving space for the variable parts.\
955 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
956 and then branches to the specified routine.
958 This code template is copied from text segment to stack location
959 and then patched with INITIALIZE_TRAMPOLINE to contain
960 valid values, and then entered as a subroutine.
962 It is best to keep this as small as possible to avoid having to
963 flush multiple lines in the cache. */
965 #define TRAMPOLINE_TEMPLATE(FILE) \
969 fputs ("\tldw 36(%r22),%r21\n", FILE); \
970 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
971 if (ASSEMBLER_DIALECT == 0) \
972 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
974 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
975 fputs ("\tldw 4(%r21),%r19\n", FILE); \
976 fputs ("\tldw 0(%r21),%r21\n", FILE); \
979 fputs ("\tbve (%r21)\n", FILE); \
980 fputs ("\tldw 40(%r22),%r29\n", FILE); \
981 fputs ("\t.word 0\n", FILE); \
982 fputs ("\t.word 0\n", FILE); \
986 fputs ("\tldsid (%r21),%r1\n", FILE); \
987 fputs ("\tmtsp %r1,%sr0\n", FILE); \
988 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
989 fputs ("\tldw 40(%r22),%r29\n", FILE); \
991 fputs ("\t.word 0\n", FILE); \
992 fputs ("\t.word 0\n", FILE); \
993 fputs ("\t.word 0\n", FILE); \
994 fputs ("\t.word 0\n", FILE); \
998 fputs ("\t.dword 0\n", FILE); \
999 fputs ("\t.dword 0\n", FILE); \
1000 fputs ("\t.dword 0\n", FILE); \
1001 fputs ("\t.dword 0\n", FILE); \
1002 fputs ("\tmfia %r31\n", FILE); \
1003 fputs ("\tldd 24(%r31),%r1\n", FILE); \
1004 fputs ("\tldd 24(%r1),%r27\n", FILE); \
1005 fputs ("\tldd 16(%r1),%r1\n", FILE); \
1006 fputs ("\tbve (%r1)\n", FILE); \
1007 fputs ("\tldd 32(%r31),%r31\n", FILE); \
1008 fputs ("\t.dword 0 ; fptr\n", FILE); \
1009 fputs ("\t.dword 0 ; static link\n", FILE); \
1013 /* Length in units of the trampoline for entering a nested function. */
1015 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
1017 /* Length in units of the trampoline instruction code. */
1019 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
1021 /* Minimum length of a cache line. A length of 16 will work on all
1022 PA-RISC processors. All PA 1.1 processors have a cache line of
1023 32 bytes. Most but not all PA 2.0 processors have a cache line
1024 of 64 bytes. As cache flushes are expensive and we don't support
1025 PA 1.0, we use a minimum length of 32. */
1027 #define MIN_CACHELINE_SIZE 32
1029 /* Emit RTL insns to initialize the variable parts of a trampoline.
1030 FNADDR is an RTX for the address of the function's pure code.
1031 CXT is an RTX for the static chain value for the function.
1033 Move the function address to the trampoline template at offset 36.
1034 Move the static chain value to trampoline template at offset 40.
1035 Move the trampoline address to trampoline template at offset 44.
1036 Move r19 to trampoline template at offset 48. The latter two
1037 words create a plabel for the indirect call to the trampoline.
1039 A similar sequence is used for the 64-bit port but the plabel is
1040 at the beginning of the trampoline.
1042 Finally, the cache entries for the trampoline code are flushed.
1043 This is necessary to ensure that the trampoline instruction sequence
1044 is written to memory prior to any attempts at prefetching the code
1047 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1049 rtx start_addr = gen_reg_rtx (Pmode); \
1050 rtx end_addr = gen_reg_rtx (Pmode); \
1051 rtx line_length = gen_reg_rtx (Pmode); \
1054 if (!TARGET_64BIT) \
1056 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
1057 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
1058 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
1059 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
1061 /* Create a fat pointer for the trampoline. */ \
1062 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
1063 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
1064 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
1065 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1066 gen_rtx_REG (Pmode, 19)); \
1068 /* fdc and fic only use registers for the address to flush, \
1069 they do not accept integer displacements. We align the \
1070 start and end addresses to the beginning of their respective \
1071 cache lines to minimize the number of lines flushed. */ \
1072 tmp = force_reg (Pmode, (TRAMP)); \
1073 emit_insn (gen_andsi3 (start_addr, tmp, \
1074 GEN_INT (-MIN_CACHELINE_SIZE))); \
1075 tmp = force_reg (Pmode, \
1076 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1077 emit_insn (gen_andsi3 (end_addr, tmp, \
1078 GEN_INT (-MIN_CACHELINE_SIZE))); \
1079 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1080 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1081 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1082 gen_reg_rtx (Pmode), \
1083 gen_reg_rtx (Pmode))); \
1087 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
1088 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
1089 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
1090 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
1092 /* Create a fat pointer for the trampoline. */ \
1093 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
1094 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1095 force_reg (Pmode, plus_constant ((TRAMP), 32))); \
1096 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
1097 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1098 gen_rtx_REG (Pmode, 27)); \
1100 /* fdc and fic only use registers for the address to flush, \
1101 they do not accept integer displacements. We align the \
1102 start and end addresses to the beginning of their respective \
1103 cache lines to minimize the number of lines flushed. */ \
1104 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1105 emit_insn (gen_anddi3 (start_addr, tmp, \
1106 GEN_INT (-MIN_CACHELINE_SIZE))); \
1107 tmp = force_reg (Pmode, \
1108 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1109 emit_insn (gen_anddi3 (end_addr, tmp, \
1110 GEN_INT (-MIN_CACHELINE_SIZE))); \
1111 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1112 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1113 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1114 gen_reg_rtx (Pmode), \
1115 gen_reg_rtx (Pmode))); \
1119 /* Perform any machine-specific adjustment in the address of the trampoline.
1120 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
1121 Adjust the trampoline address to point to the plabel at offset 44. */
1123 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
1124 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
1126 /* Implement `va_start' for varargs and stdarg. */
1128 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1129 hppa_va_start (valist, nextarg)
1131 /* Addressing modes, and classification of registers for them.
1133 Using autoincrement addressing modes on PA8000 class machines is
1136 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
1137 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
1139 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
1140 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
1142 /* Macros to check register numbers against specific register classes. */
1144 /* These assume that REGNO is a hard or pseudo reg number.
1145 They give nonzero only if REGNO is a hard reg of the suitable class
1146 or a pseudo reg currently allocated to a suitable hard reg.
1147 Since they use reg_renumber, they are safe only once reg_renumber
1148 has been allocated, which happens in local-alloc.c. */
1150 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1151 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1152 #define REGNO_OK_FOR_BASE_P(REGNO) \
1153 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1154 #define REGNO_OK_FOR_FP_P(REGNO) \
1155 (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))
1157 /* Now macros that check whether X is a register and also,
1158 strictly, whether it is in a specified class.
1160 These macros are specific to the HP-PA, and may be used only
1161 in code for printing assembler insns and in conditions for
1162 define_optimization. */
1164 /* 1 if X is an fp register. */
1166 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1168 /* Maximum number of registers that can appear in a valid memory address. */
1170 #define MAX_REGS_PER_ADDRESS 2
1172 /* Recognize any constant value that is a valid address except
1173 for symbolic addresses. We get better CSE by rejecting them
1174 here and allowing hppa_legitimize_address to break them up. We
1175 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1177 #define CONSTANT_ADDRESS_P(X) \
1178 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1179 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1180 || GET_CODE (X) == HIGH) \
1181 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1183 /* A C expression that is nonzero if we are using the new HP assembler. */
1185 #ifndef NEW_HP_ASSEMBLER
1186 #define NEW_HP_ASSEMBLER 0
1189 /* The macros below define the immediate range for CONST_INTS on
1190 the 64-bit port. Constants in this range can be loaded in three
1191 instructions using a ldil/ldo/depdi sequence. Constants outside
1192 this range are forced to the constant pool prior to reload. */
1194 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
1195 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
1196 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
1197 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
1199 /* A C expression that is nonzero if X is a legitimate constant for an
1202 We include all constant integers and constant doubles, but not
1203 floating-point, except for floating-point zero. We reject LABEL_REFs
1204 if we're not using gas or the new HP assembler.
1206 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
1207 that need more than three instructions to load prior to reload. This
1208 limit is somewhat arbitrary. It takes three instructions to load a
1209 CONST_INT from memory but two are memory accesses. It may be better
1210 to increase the allowed range for CONST_INTS. We may also be able
1211 to handle CONST_DOUBLES. */
1213 #define LEGITIMATE_CONSTANT_P(X) \
1214 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1215 || (X) == CONST0_RTX (GET_MODE (X))) \
1216 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \
1217 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \
1218 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \
1219 && !(HOST_BITS_PER_WIDE_INT <= 32 \
1220 || (reload_in_progress || reload_completed) \
1221 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
1222 || cint_ok_for_move (INTVAL (X)))) \
1223 && !function_label_operand (X, VOIDmode))
1225 /* Subroutines for EXTRA_CONSTRAINT.
1227 Return 1 iff OP is a pseudo which did not get a hard register and
1228 we are running the reload pass. */
1229 #define IS_RELOADING_PSEUDO_P(OP) \
1230 ((reload_in_progress \
1231 && GET_CODE (OP) == REG \
1232 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1233 && reg_renumber [REGNO (OP)] < 0))
1235 /* Return 1 iff OP is a scaled or unscaled index address. */
1236 #define IS_INDEX_ADDR_P(OP) \
1237 (GET_CODE (OP) == PLUS \
1238 && GET_MODE (OP) == Pmode \
1239 && (GET_CODE (XEXP (OP, 0)) == MULT \
1240 || GET_CODE (XEXP (OP, 1)) == MULT \
1241 || (REG_P (XEXP (OP, 0)) \
1242 && REG_P (XEXP (OP, 1)))))
1244 /* Return 1 iff OP is a LO_SUM DLT address. */
1245 #define IS_LO_SUM_DLT_ADDR_P(OP) \
1246 (GET_CODE (OP) == LO_SUM \
1247 && GET_MODE (OP) == Pmode \
1248 && REG_P (XEXP (OP, 0)) \
1249 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
1250 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
1252 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1254 `A' is a LO_SUM DLT memory operand.
1256 `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
1257 memory operand. Note that an unassigned pseudo register is such a
1258 memory operand. Needed because reload will generate these things
1259 and then not re-recognize the insn, causing constrain_operands to
1262 `R' is a scaled/unscaled indexed memory operand.
1264 `S' is the constant 31.
1266 `T' is for floating-point loads and stores.
1268 `U' is the constant 63. */
1270 #define EXTRA_CONSTRAINT(OP, C) \
1272 (IS_RELOADING_PSEUDO_P (OP) \
1273 || (GET_CODE (OP) == MEM \
1274 && (reload_in_progress \
1275 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))) \
1276 && !symbolic_memory_operand (OP, VOIDmode) \
1277 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1278 && !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \
1280 (GET_CODE (OP) == MEM \
1281 && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \
1283 (GET_CODE (OP) == MEM \
1284 && IS_INDEX_ADDR_P (XEXP (OP, 0))) \
1286 (GET_CODE (OP) == MEM \
1287 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1288 && !IS_INDEX_ADDR_P (XEXP (OP, 0)) \
1289 /* Floating-point loads and stores are used to load \
1290 integer values as well as floating-point values. \
1291 They don't have the same set of REG+D address modes \
1292 as integer loads and stores. PA 1.x supports only \
1293 short displacements. PA 2.0 supports long displacements \
1294 but the base register needs to be aligned. \
1296 The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and \
1297 DFmode test the validity of an address for use in a \
1298 floating point load or store. So, we use SFmode/DFmode \
1299 to see if the address is valid for a floating-point \
1300 load/store operation. */ \
1301 && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4 \
1306 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \
1308 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0))))))
1311 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1312 and check its validity for a certain class.
1313 We have two alternate definitions for each of them.
1314 The usual definition accepts all pseudo regs; the other rejects
1315 them unless they have been allocated suitable hard regs.
1316 The symbol REG_OK_STRICT causes the latter definition to be used.
1318 Most source files want to accept pseudo regs in the hope that
1319 they will get allocated to the class that the insn wants them to be in.
1320 Source files for reload pass need to be strict.
1321 After reload, it makes no difference, since pseudo regs have
1322 been eliminated by then. */
1324 #ifndef REG_OK_STRICT
1326 /* Nonzero if X is a hard reg that can be used as an index
1327 or if it is a pseudo reg. */
1328 #define REG_OK_FOR_INDEX_P(X) \
1329 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1330 /* Nonzero if X is a hard reg that can be used as a base reg
1331 or if it is a pseudo reg. */
1332 #define REG_OK_FOR_BASE_P(X) \
1333 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1337 /* Nonzero if X is a hard reg that can be used as an index. */
1338 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1339 /* Nonzero if X is a hard reg that can be used as a base reg. */
1340 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1344 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1345 valid memory address for an instruction. The MODE argument is the
1346 machine mode for the MEM expression that wants to use this address.
1348 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
1349 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
1350 available with floating point loads and stores, and integer loads.
1351 We get better code by allowing indexed addresses in the initial
1354 The acceptance of indexed addresses as legitimate implies that we
1355 must provide patterns for doing indexed integer stores, or the move
1356 expanders must force the address of an indexed store to a register.
1357 We have adopted the latter approach.
1359 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
1360 the base register is a valid pointer for indexed instructions.
1361 On targets that have non-equivalent space registers, we have to
1362 know at the time of assembler output which register in a REG+REG
1363 pair is the base register. The REG_POINTER flag is sometimes lost
1364 in reload and the following passes, so it can't be relied on during
1365 code generation. Thus, we either have to canonicalize the order
1366 of the registers in REG+REG indexed addresses, or treat REG+REG
1367 addresses separately and provide patterns for both permutations.
1369 The latter approach requires several hundred additional lines of
1370 code in pa.md. The downside to canonicalizing is that a PLUS
1371 in the wrong order can't combine to form to make a scaled indexed
1372 memory operand. As we won't need to canonicalize the operands if
1373 the REG_POINTER lossage can be fixed, it seems better canonicalize.
1375 We initially break out scaled indexed addresses in canonical order
1376 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
1377 scaled indexed addresses during RTL generation. However, fold_rtx
1378 has its own opinion on how the operands of a PLUS should be ordered.
1379 If one of the operands is equivalent to a constant, it will make
1380 that operand the second operand. As the base register is likely to
1381 be equivalent to a SYMBOL_REF, we have made it the second operand.
1383 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
1384 operands are in the order INDEX+BASE on targets with non-equivalent
1385 space registers, and in any order on targets with equivalent space
1386 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
1388 We treat a SYMBOL_REF as legitimate if it is part of the current
1389 function's constant-pool, because such addresses can actually be
1390 output as REG+SMALLINT.
1392 Note we only allow 5 bit immediates for access to a constant address;
1393 doing so avoids losing for loading/storing a FP register at an address
1394 which will not fit in 5 bits. */
1396 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1397 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1399 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1400 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1402 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1403 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1405 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1406 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1408 #if HOST_BITS_PER_WIDE_INT > 32
1409 #define VAL_32_BITS_P(X) \
1410 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
1411 < (unsigned HOST_WIDE_INT) 2 << 31)
1413 #define VAL_32_BITS_P(X) 1
1415 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
1417 /* These are the modes that we allow for scaled indexing. */
1418 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
1419 ((TARGET_64BIT && (MODE) == DImode) \
1420 || (MODE) == SImode \
1421 || (MODE) == HImode \
1422 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1424 /* These are the modes that we allow for unscaled indexing. */
1425 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1426 ((TARGET_64BIT && (MODE) == DImode) \
1427 || (MODE) == SImode \
1428 || (MODE) == HImode \
1429 || (MODE) == QImode \
1430 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1432 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1434 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1435 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1436 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1437 && REG_P (XEXP (X, 0)) \
1438 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1440 else if (GET_CODE (X) == PLUS) \
1442 rtx base = 0, index = 0; \
1443 if (REG_P (XEXP (X, 1)) \
1444 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1445 base = XEXP (X, 1), index = XEXP (X, 0); \
1446 else if (REG_P (XEXP (X, 0)) \
1447 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1448 base = XEXP (X, 0), index = XEXP (X, 1); \
1450 && GET_CODE (index) == CONST_INT \
1451 && ((INT_14_BITS (index) \
1452 && (((MODE) != DImode \
1453 && (MODE) != SFmode \
1454 && (MODE) != DFmode) \
1455 /* The base register for DImode loads and stores \
1456 with long displacements must be aligned because \
1457 the lower three bits in the displacement are \
1458 assumed to be zero. */ \
1459 || ((MODE) == DImode \
1461 || (INTVAL (index) % 8) == 0)) \
1462 /* Similarly, the base register for SFmode/DFmode \
1463 loads and stores with long displacements must \
1466 FIXME: the ELF32 linker clobbers the LSB of \
1467 the FP register number in PA 2.0 floating-point \
1468 insns with long displacements. This is because \
1469 R_PARISC_DPREL14WR and other relocations like \
1470 it are not supported. For now, we reject long \
1471 displacements on this target. */ \
1472 || (((MODE) == SFmode || (MODE) == DFmode) \
1473 && (TARGET_SOFT_FLOAT \
1476 && (INTVAL (index) \
1477 % GET_MODE_SIZE (MODE)) == 0))))) \
1478 || INT_5_BITS (index))) \
1480 if (!TARGET_DISABLE_INDEXING \
1481 /* Only accept the "canonical" INDEX+BASE operand order \
1482 on targets with non-equivalent space registers. */ \
1483 && (TARGET_NO_SPACE_REGS \
1484 ? (base && REG_P (index)) \
1485 : (base == XEXP (X, 1) && REG_P (index) \
1486 && REG_POINTER (base) && !REG_POINTER (index))) \
1487 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1488 && REG_OK_FOR_INDEX_P (index) \
1489 && borx_reg_operand (base, Pmode) \
1490 && borx_reg_operand (index, Pmode)) \
1492 if (!TARGET_DISABLE_INDEXING \
1494 && GET_CODE (index) == MULT \
1495 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1496 && REG_P (XEXP (index, 0)) \
1497 && GET_MODE (XEXP (index, 0)) == Pmode \
1498 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1499 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1500 && INTVAL (XEXP (index, 1)) \
1501 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1502 && borx_reg_operand (base, Pmode)) \
1505 else if (GET_CODE (X) == LO_SUM \
1506 && GET_CODE (XEXP (X, 0)) == REG \
1507 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1508 && CONSTANT_P (XEXP (X, 1)) \
1509 && (TARGET_SOFT_FLOAT \
1510 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1513 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1514 || ((MODE) != SFmode \
1515 && (MODE) != DFmode))) \
1517 else if (GET_CODE (X) == LO_SUM \
1518 && GET_CODE (XEXP (X, 0)) == SUBREG \
1519 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1520 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1521 && CONSTANT_P (XEXP (X, 1)) \
1522 && (TARGET_SOFT_FLOAT \
1523 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1526 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1527 || ((MODE) != SFmode \
1528 && (MODE) != DFmode))) \
1530 else if (GET_CODE (X) == LABEL_REF \
1531 || (GET_CODE (X) == CONST_INT \
1532 && INT_5_BITS (X))) \
1534 /* Needed for -fPIC */ \
1535 else if (GET_CODE (X) == LO_SUM \
1536 && GET_CODE (XEXP (X, 0)) == REG \
1537 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1538 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1539 && (TARGET_SOFT_FLOAT \
1540 || (TARGET_PA_20 && !TARGET_ELF32) \
1541 || ((MODE) != SFmode \
1542 && (MODE) != DFmode))) \
1546 /* Look for machine dependent ways to make the invalid address AD a
1549 For the PA, transform:
1551 memory(X + <large int>)
1555 if (<large int> & mask) >= 16
1556 Y = (<large int> & ~mask) + mask + 1 Round up.
1558 Y = (<large int> & ~mask) Round down.
1560 memory (Z + (<large int> - Y));
1562 This makes reload inheritance and reload_cse work better since Z
1565 There may be more opportunities to improve code with this hook. */
1566 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1568 long offset, newoffset, mask; \
1569 rtx new, temp = NULL_RTX; \
1571 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1572 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
1574 if (optimize && GET_CODE (AD) == PLUS) \
1575 temp = simplify_binary_operation (PLUS, Pmode, \
1576 XEXP (AD, 0), XEXP (AD, 1)); \
1578 new = temp ? temp : AD; \
1581 && GET_CODE (new) == PLUS \
1582 && GET_CODE (XEXP (new, 0)) == REG \
1583 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1585 offset = INTVAL (XEXP ((new), 1)); \
1587 /* Choose rounding direction. Round up if we are >= halfway. */ \
1588 if ((offset & mask) >= ((mask + 1) / 2)) \
1589 newoffset = (offset & ~mask) + mask + 1; \
1591 newoffset = offset & ~mask; \
1593 /* Ensure that long displacements are aligned. */ \
1594 if (!VAL_5_BITS_P (newoffset) \
1595 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1596 newoffset &= ~(GET_MODE_SIZE (MODE) -1); \
1598 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1600 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1601 GEN_INT (newoffset)); \
1602 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1603 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1604 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1614 /* Try machine-dependent ways of modifying an illegitimate address
1615 to be legitimate. If we find one, return the new, valid address.
1616 This macro is used in only one place: `memory_address' in explow.c.
1618 OLDX is the address as it was before break_out_memory_refs was called.
1619 In some cases it is useful to look at this to decide what needs to be done.
1621 MODE and WIN are passed so that this macro can use
1622 GO_IF_LEGITIMATE_ADDRESS.
1624 It is always safe for this macro to do nothing. It exists to recognize
1625 opportunities to optimize the output. */
1627 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1628 { rtx orig_x = (X); \
1629 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1630 if ((X) != orig_x && memory_address_p (MODE, X)) \
1633 /* Go to LABEL if ADDR (a legitimate address expression)
1634 has an effect that depends on the machine mode it is used for. */
1636 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1637 if (GET_CODE (ADDR) == PRE_DEC \
1638 || GET_CODE (ADDR) == POST_DEC \
1639 || GET_CODE (ADDR) == PRE_INC \
1640 || GET_CODE (ADDR) == POST_INC) \
1643 #define TARGET_ASM_SELECT_SECTION pa_select_section
1645 /* Return a nonzero value if DECL has a section attribute. */
1646 #define IN_NAMED_SECTION_P(DECL) \
1647 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1648 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1650 /* Define this macro if references to a symbol must be treated
1651 differently depending on something about the variable or
1652 function named by the symbol (such as what section it is in).
1654 The macro definition, if any, is executed immediately after the
1655 rtl for DECL or other node is created.
1656 The value of the rtl will be a `mem' whose address is a
1659 The usual thing for this macro to do is to a flag in the
1660 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1661 name string in the `symbol_ref' (if one bit is not enough
1664 On the HP-PA we use this to indicate if a symbol is in text or
1665 data space. Also, function labels need special treatment. */
1667 #define TEXT_SPACE_P(DECL)\
1668 (TREE_CODE (DECL) == FUNCTION_DECL \
1669 || (TREE_CODE (DECL) == VAR_DECL \
1670 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1671 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1673 || (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c'))
1675 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1677 /* Specify the machine mode that this machine uses for the index in the
1678 tablejump instruction. For small tables, an element consists of a
1679 ia-relative branch and its delay slot. When -mbig-switch is specified,
1680 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1681 for both 32 and 64-bit pic code. */
1682 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1684 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1685 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1687 /* Define this as 1 if `char' should by default be signed; else as 0. */
1688 #define DEFAULT_SIGNED_CHAR 1
1690 /* Max number of bytes we can move from memory to memory
1691 in one reasonably fast instruction. */
1694 /* Higher than the default as we prefer to use simple move insns
1695 (better scheduling and delay slot filling) and because our
1696 built-in block move is really a 2X unrolled loop.
1698 Believe it or not, this has to be big enough to allow for copying all
1699 arguments passed in registers to avoid infinite recursion during argument
1700 setup for a function call. Why? Consider how we copy the stack slots
1701 reserved for parameters when they may be trashed by a call. */
1702 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1704 /* Define if operations between registers always perform the operation
1705 on the full register even if a narrower mode is specified. */
1706 #define WORD_REGISTER_OPERATIONS
1708 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1709 will either zero-extend or sign-extend. The value of this macro should
1710 be the code that says which one of the two operations is implicitly
1711 done, NIL if none. */
1712 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1714 /* Nonzero if access to memory by bytes is slow and undesirable. */
1715 #define SLOW_BYTE_ACCESS 1
1717 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1718 is done just by pretending it is already truncated. */
1719 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1721 /* Specify the machine mode that pointers have.
1722 After generation of rtl, the compiler makes no further distinction
1723 between pointers and any other objects of this machine mode. */
1724 #define Pmode word_mode
1726 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1727 return the mode to be used for the comparison. For floating-point, CCFPmode
1728 should be used. CC_NOOVmode should be used when the first operand is a
1729 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1731 #define SELECT_CC_MODE(OP,X,Y) \
1732 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1734 /* A function address in a call instruction
1735 is a byte address (for indexing purposes)
1736 so give the MEM rtx a byte's mode. */
1737 #define FUNCTION_MODE SImode
1739 /* Define this if addresses of constant functions
1740 shouldn't be put through pseudo regs where they can be cse'd.
1741 Desirable on machines where ordinary constants are expensive
1742 but a CALL with constant address is cheap. */
1743 #define NO_FUNCTION_CSE
1745 /* Define this to be nonzero if shift instructions ignore all but the low-order
1747 #define SHIFT_COUNT_TRUNCATED 1
1749 /* Compute extra cost of moving data between one register class
1752 Make moves from SAR so expensive they should never happen. We used to
1753 have 0xffff here, but that generates overflow in rare cases.
1755 Copies involving a FP register and a non-FP register are relatively
1756 expensive because they must go through memory.
1758 Other copies are reasonably cheap. */
1759 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1760 (CLASS1 == SHIFT_REGS ? 0x100 \
1761 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1762 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1765 /* Adjust the cost of branches. */
1766 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1768 /* Handling the special cases is going to get too complicated for a macro,
1769 just call `pa_adjust_insn_length' to do the real work. */
1770 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1771 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1773 /* Millicode insns are actually function calls with some special
1774 constraints on arguments and register usage.
1776 Millicode calls always expect their arguments in the integer argument
1777 registers, and always return their result in %r29 (ret1). They
1778 are expected to clobber their arguments, %r1, %r29, and the return
1779 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1781 This macro tells reorg that the references to arguments and
1782 millicode calls do not appear to happen until after the millicode call.
1783 This allows reorg to put insns which set the argument registers into the
1784 delay slot of the millicode call -- thus they act more like traditional
1787 Note we can not consider side effects of the insn to be delayed because
1788 the branch and link insn will clobber the return pointer. If we happened
1789 to use the return pointer in the delay slot of the call, then we lose.
1791 get_attr_type will try to recognize the given insn, so make sure to
1792 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1794 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1797 /* Control the assembler format that we output. */
1799 /* A C string constant describing how to begin a comment in the target
1800 assembler language. The compiler assumes that the comment will end at
1801 the end of the line. */
1803 #define ASM_COMMENT_START ";"
1805 /* Output to assembler file text saying following lines
1806 may contain character constants, extra white space, comments, etc. */
1808 #define ASM_APP_ON ""
1810 /* Output to assembler file text saying following lines
1811 no longer contain unusual constructs. */
1813 #define ASM_APP_OFF ""
1815 /* This is how to output the definition of a user-level label named NAME,
1816 such as the label on a static function or variable NAME. */
1818 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1819 do { assemble_name (FILE, NAME); \
1820 fputc ('\n', FILE); } while (0)
1822 /* This is how to output a reference to a user-level label named NAME.
1823 `assemble_name' uses this. */
1825 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1827 const char *xname = (NAME); \
1828 if (FUNCTION_NAME_P (NAME)) \
1830 if (xname[0] == '*') \
1833 fputs (user_label_prefix, FILE); \
1834 fputs (xname, FILE); \
1837 /* This is how to store into the string LABEL
1838 the symbol_ref name of an internal numbered label where
1839 PREFIX is the class of label and NUM is the number within the class.
1840 This is suitable for output with `assemble_name'. */
1842 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1843 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1845 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1847 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1848 output_ascii ((FILE), (P), (SIZE))
1850 /* Jump tables are always placed in the text section. Technically, it
1851 is possible to put them in the readonly data section when -mbig-switch
1852 is specified. This has the benefit of getting the table out of .text
1853 and reducing branch lengths as a result. The downside is that an
1854 additional insn (addil) is needed to access the table when generating
1855 PIC code. The address difference table also has to use 32-bit
1856 pc-relative relocations. Currently, GAS does not support these
1857 relocations, although it is easily modified to do this operation.
1858 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1859 when using ELF GAS. A simple difference can be used when using
1860 SOM GAS or the HP assembler. The final downside is GDB complains
1861 about the nesting of the label for the table when debugging. */
1863 #define JUMP_TABLES_IN_TEXT_SECTION 1
1865 /* This is how to output an element of a case-vector that is absolute. */
1867 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1868 if (TARGET_BIG_SWITCH) \
1869 fprintf (FILE, "\t.word L$%04d\n", VALUE); \
1871 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1873 /* This is how to output an element of a case-vector that is relative.
1874 Since we always place jump tables in the text section, the difference
1875 is absolute and requires no relocation. */
1877 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1878 if (TARGET_BIG_SWITCH) \
1879 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
1881 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1883 /* This is how to output an assembler line that says to advance the
1884 location counter to a multiple of 2**LOG bytes. */
1886 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1887 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1889 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1890 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1891 (unsigned HOST_WIDE_INT)(SIZE))
1893 /* This says how to output an assembler line to define a global common symbol
1894 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1896 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNED) \
1898 assemble_name ((FILE), (NAME)); \
1899 fprintf ((FILE), "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1900 MAX ((unsigned HOST_WIDE_INT)(SIZE), \
1901 ((unsigned HOST_WIDE_INT)(ALIGNED) / BITS_PER_UNIT)));}
1903 /* This says how to output an assembler line to define a local common symbol
1904 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1906 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1908 fprintf ((FILE), "\t.align %d\n", ((ALIGNED) / BITS_PER_UNIT)); \
1909 assemble_name ((FILE), (NAME)); \
1910 fprintf ((FILE), "\n\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1911 (unsigned HOST_WIDE_INT)(SIZE));}
1913 #define ASM_PN_FORMAT "%s___%lu"
1915 /* All HP assemblers use "!" to separate logical lines. */
1916 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
1918 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1919 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1921 /* Print operand X (an rtx) in assembler syntax to file FILE.
1922 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1923 For `%' followed by punctuation, CODE is the punctuation and X is null.
1925 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1926 and an immediate zero should be represented as `r0'.
1928 Several % codes are defined:
1930 C compare conditions
1931 N extract conditions
1932 M modifier to handle preincrement addressing for memory refs.
1933 F modifier to handle preincrement addressing for fp memory refs */
1935 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1938 /* Print a memory address as an operand to reference that memory location. */
1940 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1941 { register rtx addr = ADDR; \
1942 register rtx base; \
1944 switch (GET_CODE (addr)) \
1947 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1950 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1951 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); \
1952 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1953 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); \
1956 fprintf (FILE, "%d(%s)", offset, reg_names [REGNO (base)]); \
1959 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1960 fputs ("R'", FILE); \
1961 else if (flag_pic == 0) \
1962 fputs ("RR'", FILE); \
1964 fputs ("RT'", FILE); \
1965 output_global_address (FILE, XEXP (addr, 1), 0); \
1966 fputs ("(", FILE); \
1967 output_operand (XEXP (addr, 0), 0); \
1968 fputs (")", FILE); \
1971 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
1974 output_addr_const (FILE, addr); \
1978 /* Find the return address associated with the frame given by
1980 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1981 (return_addr_rtx (COUNT, FRAMEADDR))
1983 /* Used to mask out junk bits from the return address, such as
1984 processor state, interrupt status, condition codes and the like. */
1985 #define MASK_RETURN_ADDR \
1986 /* The privilege level is in the two low order bits, mask em out \
1987 of the return address. */ \
1990 /* The number of Pmode words for the setjmp buffer. */
1991 #define JMP_BUF_SIZE 50
1993 #define PREDICATE_CODES \
1994 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
1995 {"call_operand_address", {LABEL_REF, SYMBOL_REF, CONST_INT, \
1996 CONST_DOUBLE, CONST, HIGH}}, \
1997 {"indexed_memory_operand", {SUBREG, MEM}}, \
1998 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
1999 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2000 {"reg_before_reload_operand", {REG, MEM}}, \
2001 {"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, MEM, CONST_INT, \
2003 {"move_dest_operand", {SUBREG, REG, MEM}}, \
2004 {"move_src_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2005 {"prefetch_operand", {MEM}}, \
2006 {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
2007 {"pic_label_operand", {LABEL_REF, CONST}}, \
2008 {"fp_reg_operand", {REG}}, \
2009 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2010 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2011 {"pre_cint_operand", {CONST_INT}}, \
2012 {"post_cint_operand", {CONST_INT}}, \
2013 {"arith_double_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2014 {"ireg_or_int5_operand", {CONST_INT, REG}}, \
2015 {"int5_operand", {CONST_INT}}, \
2016 {"uint5_operand", {CONST_INT}}, \
2017 {"int11_operand", {CONST_INT}}, \
2018 {"uint32_operand", {CONST_INT, \
2019 HOST_BITS_PER_WIDE_INT > 32 ? 0 : CONST_DOUBLE}}, \
2020 {"arith5_operand", {SUBREG, REG, CONST_INT}}, \
2021 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2022 {"ior_operand", {CONST_INT}}, \
2023 {"lhs_lshift_cint_operand", {CONST_INT}}, \
2024 {"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \
2025 {"arith32_operand", {SUBREG, REG, CONST_INT}}, \
2026 {"pc_or_label_operand", {PC, LABEL_REF}}, \
2027 {"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \
2028 {"shadd_operand", {CONST_INT}}, \
2029 {"div_operand", {REG, CONST_INT}}, \
2030 {"ireg_operand", {REG}}, \
2031 {"cmpib_comparison_operator", {EQ, NE, LT, LE, LEU, \
2033 {"movb_comparison_operator", {EQ, NE, LT, GE}},
2035 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
2036 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
2037 "__canonicalize_funcptr_for_compare"
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