1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 enum cmp_type /* comparison type */
27 CMP_SI, /* compare integers */
28 CMP_SF, /* compare single precision floats */
29 CMP_DF, /* compare double precision floats */
30 CMP_MAX /* max comparison type */
33 /* For long call handling. */
34 extern unsigned int total_code_bytes;
36 /* Which processor to schedule for. */
48 /* For -mschedule= option. */
49 extern const char *pa_cpu_string;
50 extern enum processor_type pa_cpu;
52 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
54 /* Which architecture to generate code for. */
56 enum architecture_type
65 /* For -march= option. */
66 extern const char *pa_arch_string;
67 extern enum architecture_type pa_arch;
69 /* Print subsidiary information on the compiler version in use. */
71 #define TARGET_VERSION fputs (" (hppa)", stderr);
73 /* Run-time compilation parameters selecting different hardware subsets. */
75 extern int target_flags;
77 /* compile code for HP-PA 1.1 ("Snake") */
82 #define TARGET_PA_11 (target_flags & MASK_PA_11)
85 /* Disable all FP registers (they all become fixed). This may be necessary
86 for compiling kernels which perform lazy context switching of FP regs.
87 Note if you use this option and try to perform floating point operations
88 the compiler will abort! */
90 #define MASK_DISABLE_FPREGS 2
91 #define TARGET_DISABLE_FPREGS (target_flags & MASK_DISABLE_FPREGS)
93 /* Generate code which assumes that all space register are equivalent.
94 Triggers aggressive unscaled index addressing and faster
95 builtin_return_address. */
96 #define MASK_NO_SPACE_REGS 4
97 #define TARGET_NO_SPACE_REGS (target_flags & MASK_NO_SPACE_REGS)
99 /* Allow unconditional jumps in the delay slots of call instructions. */
100 #define MASK_JUMP_IN_DELAY 8
101 #define TARGET_JUMP_IN_DELAY (target_flags & MASK_JUMP_IN_DELAY)
103 /* Disable indexed addressing modes. */
104 #define MASK_DISABLE_INDEXING 32
105 #define TARGET_DISABLE_INDEXING (target_flags & MASK_DISABLE_INDEXING)
107 /* Emit code which follows the new portable runtime calling conventions
108 HP wants everyone to use for ELF objects. If at all possible you want
109 to avoid this since it's a performance loss for non-prototyped code.
111 Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline
112 long-call stubs which is quite expensive. */
113 #define MASK_PORTABLE_RUNTIME 64
114 #define TARGET_PORTABLE_RUNTIME (target_flags & MASK_PORTABLE_RUNTIME)
116 /* Emit directives only understood by GAS. This allows parameter
117 relocations to work for static functions. There is no way
118 to make them work the HP assembler at this time. */
120 #define TARGET_GAS (target_flags & MASK_GAS)
122 /* Emit code for processors which do not have an FPU. */
123 #define MASK_SOFT_FLOAT 256
124 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
126 /* Use 3-insn load/store sequences for access to large data segments
127 in shared libraries on hpux10. */
128 #define MASK_LONG_LOAD_STORE 512
129 #define TARGET_LONG_LOAD_STORE (target_flags & MASK_LONG_LOAD_STORE)
131 /* Use a faster sequence for indirect calls. This assumes that calls
132 through function pointers will never cross a space boundary, and
133 that the executable is not dynamically linked. Such assumptions
134 are generally safe for building kernels and statically linked
135 executables. Code compiled with this option will fail miserably if
136 the executable is dynamically linked or uses nested functions! */
137 #define MASK_FAST_INDIRECT_CALLS 1024
138 #define TARGET_FAST_INDIRECT_CALLS (target_flags & MASK_FAST_INDIRECT_CALLS)
140 /* Generate code with big switch statements to avoid out of range branches
141 occurring within the switch table. */
142 #define MASK_BIG_SWITCH 2048
143 #define TARGET_BIG_SWITCH (target_flags & MASK_BIG_SWITCH)
146 /* Generate code for the HPPA 2.0 architecture. TARGET_PA_11 should also be
147 true when this is true. */
148 #define MASK_PA_20 4096
150 #define TARGET_PA_20 (target_flags & MASK_PA_20)
153 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
155 #define TARGET_64BIT 0
158 /* Generate code for ELF32 ABI. */
160 #define TARGET_ELF32 0
163 /* Generate code for SOM 32bit ABI. */
168 /* Macro to define tables used to set the flags.
169 This is a list in braces of pairs in braces,
170 each pair being { "NAME", VALUE }
171 where VALUE is the bits to set or minus the bits to clear.
172 An empty string NAME is used to identify the default VALUE. */
174 #define TARGET_SWITCHES \
175 {{"snake", MASK_PA_11, "Generate PA1.1 code"}, \
176 {"nosnake", -(MASK_PA_11 | MASK_PA_20), "Generate PA1.0 code"}, \
177 {"pa-risc-1-0", -(MASK_PA_11 | MASK_PA_20), "Generate PA1.0 code"}, \
178 {"pa-risc-1-1", MASK_PA_11, "Generate PA1.1 code"}, \
179 {"pa-risc-2-0", MASK_PA_20, "Generate PA2.0 code. This option requires binutils 2.10 or later"}, \
180 {"disable-fpregs", MASK_DISABLE_FPREGS, "Disable FP regs"}, \
181 {"no-disable-fpregs", -MASK_DISABLE_FPREGS, "Do not disable FP regs"},\
182 {"no-space-regs", MASK_NO_SPACE_REGS, "Disable space regs"}, \
183 {"space-regs", -MASK_NO_SPACE_REGS, "Do not disable space regs"}, \
184 {"jump-in-delay", MASK_JUMP_IN_DELAY, "Put jumps in call delay slots"},\
185 {"no-jump-in-delay", -MASK_JUMP_IN_DELAY, "Do not put jumps in call delay slots"}, \
186 {"disable-indexing", MASK_DISABLE_INDEXING, "Disable indexed addressing"},\
187 {"no-disable-indexing", -MASK_DISABLE_INDEXING, "Do not disable indexed addressing"},\
188 {"portable-runtime", MASK_PORTABLE_RUNTIME, "Use portable calling conventions"}, \
189 {"no-portable-runtime", -MASK_PORTABLE_RUNTIME, "Do not use portable calling conventions"},\
190 {"gas", MASK_GAS, "Assume code will be assembled by GAS"}, \
191 {"no-gas", -MASK_GAS, "Do not assume code will be assembled by GAS"}, \
192 {"soft-float", MASK_SOFT_FLOAT, "Use software floating point"}, \
193 {"no-soft-float", -MASK_SOFT_FLOAT, "Do not use software floating point"}, \
194 {"long-load-store", MASK_LONG_LOAD_STORE, "Emit long load/store sequences"}, \
195 {"no-long-load-store", -MASK_LONG_LOAD_STORE, "Do not emit long load/store sequences"},\
196 {"fast-indirect-calls", MASK_FAST_INDIRECT_CALLS, "Generate fast indirect calls"},\
197 {"no-fast-indirect-calls", -MASK_FAST_INDIRECT_CALLS, "Do not generate fast indirect calls"},\
198 {"big-switch", MASK_BIG_SWITCH, "Generate code for huge switch statements"}, \
199 {"no-big-switch", -MASK_BIG_SWITCH, "Do not generate code for huge switch statements"}, \
200 {"linker-opt", 0, "Enable linker optimizations"}, \
201 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, NULL}}
203 #ifndef TARGET_DEFAULT
204 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY)
207 #ifndef TARGET_CPU_DEFAULT
208 #define TARGET_CPU_DEFAULT 0
211 #define TARGET_OPTIONS \
213 { "schedule=", &pa_cpu_string, "Specify CPU for scheduling purposes" },\
214 { "arch=", &pa_arch_string, "Specify architecture for code generation. Values are 1.0, 1.1, and 2.0. 2.0 requires gas snapshot 19990413 or later." }\
217 /* Specify the dialect of assembler to use. New mnemonics is dialect one
218 and the old mnemonics are dialect zero. */
219 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
221 #define OVERRIDE_OPTIONS override_options ()
223 /* stabs-in-som is nearly identical to stabs-in-elf. To avoid useless
224 code duplication we simply include this file and override as needed. */
227 /* We do not have to be compatible with dbx, so we enable gdb extensions
229 #define DEFAULT_GDB_EXTENSIONS 1
231 /* This used to be zero (no max length), but big enums and such can
232 cause huge strings which killed gas.
234 We also have to avoid lossage in dbxout.c -- it does not compute the
235 string size accurately, so we are real conservative here. */
236 #undef DBX_CONTIN_LENGTH
237 #define DBX_CONTIN_LENGTH 3000
239 /* Only labels should ever begin in column zero. */
240 #define ASM_STABS_OP "\t.stabs\t"
241 #define ASM_STABN_OP "\t.stabn\t"
243 /* GDB always assumes the current function's frame begins at the value
244 of the stack pointer upon entry to the current function. Accessing
245 local variables and parameters passed on the stack is done using the
246 base of the frame + an offset provided by GCC.
248 For functions which have frame pointers this method works fine;
249 the (frame pointer) == (stack pointer at function entry) and GCC provides
250 an offset relative to the frame pointer.
252 This loses for functions without a frame pointer; GCC provides an offset
253 which is relative to the stack pointer after adjusting for the function's
254 frame size. GDB would prefer the offset to be relative to the value of
255 the stack pointer at the function's entry. Yuk! */
256 #define DEBUGGER_AUTO_OFFSET(X) \
257 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
258 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
260 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
261 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
262 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
264 #define CPP_PA10_SPEC ""
265 #define CPP_PA11_SPEC "-D_PA_RISC1_1 -D__hp9000s700"
266 #define CPP_PA20_SPEC "-D_PA_RISC2_0 -D__hp9000s800"
267 #define CPP_64BIT_SPEC "-D__LP64__ -D__LONG_MAX__=9223372036854775807L"
269 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_PA_11) == 0
270 #define CPP_CPU_DEFAULT_SPEC "%(cpp_pa10)"
273 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_PA_11) != 0
274 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_PA_20) != 0
275 #define CPP_CPU_DEFAULT_SPEC "%(cpp_pa11) %(cpp_pa20)"
277 #define CPP_CPU_DEFAULT_SPEC "%(cpp_pa11)"
282 #define CPP_64BIT_DEFAULT_SPEC "%(cpp_64bit)"
284 #define CPP_64BIT_DEFAULT_SPEC ""
287 /* This macro defines names of additional specifications to put in the
288 specs that can be used in various specifications like CC1_SPEC. Its
289 definition is an initializer with a subgrouping for each command option.
291 Each subgrouping contains a string constant, that defines the
292 specification name, and a string constant that used by the GNU CC driver
295 Do not define this macro if it does not need to do anything. */
297 #ifndef SUBTARGET_EXTRA_SPECS
298 #define SUBTARGET_EXTRA_SPECS
301 #define EXTRA_SPECS \
302 { "cpp_pa10", CPP_PA10_SPEC}, \
303 { "cpp_pa11", CPP_PA11_SPEC}, \
304 { "cpp_pa20", CPP_PA20_SPEC}, \
305 { "cpp_64bit", CPP_64BIT_SPEC}, \
306 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
307 { "cpp_64bit_default", CPP_64BIT_DEFAULT_SPEC }, \
308 SUBTARGET_EXTRA_SPECS
311 %{mpa-risc-1-0:%(cpp_pa10)} \
312 %{mpa-risc-1-1:%(cpp_pa11)} \
313 %{msnake:%(cpp_pa11)} \
314 %{mpa-risc-2-0:%(cpp_pa20)} \
315 %{!mpa-risc-1-0:%{!mpa-risc-1-1:%{!mpa-risc-2-0:%{!msnake:%(cpp_cpu_default)}}}} \
316 %{m64bit:%(cpp_64bit)} \
317 %{!m64bit:%(cpp_64bit_default)} \
318 %{!ansi: -D_HPUX_SOURCE -D_HIUX_SOURCE -D__STDC_EXT__ -D_INCLUDE_LONGLONG} \
319 %{threads: -D_REENTRANT -D_DCE_THREADS}"
321 #define CPLUSPLUS_CPP_SPEC "\
322 -D_HPUX_SOURCE -D_HIUX_SOURCE -D__STDC_EXT__ -D_INCLUDE_LONGLONG \
323 %{mpa-risc-1-0:%(cpp_pa10)} \
324 %{mpa-risc-1-1:%(cpp_pa11)} \
325 %{msnake:%(cpp_pa11)} \
326 %{mpa-risc-2-0:%(cpp_pa20)} \
327 %{!mpa-risc-1-0:%{!mpa-risc-1-1:%{!mpa-risc-2-0:%{!msnake:%(cpp_cpu_default)}}}} \
328 %{m64bit:%(cpp_64bit)} \
329 %{!m64bit:%(cpp_64bit_default)} \
330 %{threads: -D_REENTRANT -D_DCE_THREADS}"
332 /* Defines for a K&R CC */
334 #define CC1_SPEC "%{pg:} %{p:}"
336 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
338 /* We don't want -lg. */
340 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
343 /* This macro defines command-line switches that modify the default
346 The definition is be an initializer for an array of structures. Each
347 array element has have three elements: the switch name, one of the
348 enumeration codes ADD or DELETE to indicate whether the string should be
349 inserted or deleted, and the string to be inserted or deleted. */
350 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
352 /* Make gcc agree with <machine/ansi.h> */
354 #define SIZE_TYPE "unsigned int"
355 #define PTRDIFF_TYPE "int"
356 #define WCHAR_TYPE "unsigned int"
357 #define WCHAR_TYPE_SIZE 32
359 /* Show we can debug even without a frame pointer. */
360 #define CAN_DEBUG_WITHOUT_FP
362 /* Machine dependent reorg pass. */
363 #define MACHINE_DEPENDENT_REORG(X) pa_reorg(X)
365 /* Names to predefine in the preprocessor for this target machine. */
367 #define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -Dunix -Dhp9000 -Dhp800 -Dspectrum -DREVARGV -Asystem=unix -Asystem=bsd -Acpu=hppa -Amachine=hppa"
369 /* target machine storage layout */
371 /* Define this macro if it is advisable to hold scalars in registers
372 in a wider mode than that declared by the program. In such cases,
373 the value is constrained to be within the bounds of the declared
374 type, but kept valid in the wider mode. The signedness of the
375 extension may differ from that of the type. */
377 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
378 if (GET_MODE_CLASS (MODE) == MODE_INT \
379 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
382 /* Define this if most significant bit is lowest numbered
383 in instructions that operate on numbered bit-fields. */
384 #define BITS_BIG_ENDIAN 1
386 /* Define this if most significant byte of a word is the lowest numbered. */
387 /* That is true on the HP-PA. */
388 #define BYTES_BIG_ENDIAN 1
390 /* Define this if most significant word of a multiword number is lowest
392 #define WORDS_BIG_ENDIAN 1
394 #define MAX_BITS_PER_WORD 64
395 #define MAX_LONG_TYPE_SIZE 32
397 /* Width of a word, in units (bytes). */
398 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
399 #define MIN_UNITS_PER_WORD 4
401 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
402 #define PARM_BOUNDARY BITS_PER_WORD
404 /* Largest alignment required for any stack parameter, in bits.
405 Don't define this if it is equal to PARM_BOUNDARY */
406 #define MAX_PARM_BOUNDARY 64
408 /* Boundary (in *bits*) on which stack pointer is always aligned;
409 certain optimizations in combine depend on this.
411 GCC for the PA always rounds its stacks to a 512bit boundary,
412 but that happens late in the compilation process. */
413 #define STACK_BOUNDARY (TARGET_64BIT ? 128 : 64)
415 #define PREFERRED_STACK_BOUNDARY 512
417 /* Allocation boundary (in *bits*) for the code of a function. */
418 #define FUNCTION_BOUNDARY (TARGET_64BIT ? 64 : 32)
420 /* Alignment of field after `int : 0' in a structure. */
421 #define EMPTY_FIELD_BOUNDARY 32
423 /* Every structure's size must be a multiple of this. */
424 #define STRUCTURE_SIZE_BOUNDARY 8
426 /* A bitfield declared as `int' forces `int' alignment for the struct. */
427 #define PCC_BITFIELD_TYPE_MATTERS 1
429 /* No data type wants to be aligned rounder than this. This is set
430 to 128 bits to allow for lock semaphores in the stack frame.*/
431 #define BIGGEST_ALIGNMENT 128
433 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
434 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
435 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
437 /* Make arrays of chars word-aligned for the same reasons. */
438 #define DATA_ALIGNMENT(TYPE, ALIGN) \
439 (TREE_CODE (TYPE) == ARRAY_TYPE \
440 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
441 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
444 /* Set this nonzero if move instructions will actually fail to work
445 when given unaligned data. */
446 #define STRICT_ALIGNMENT 1
448 /* Generate calls to memcpy, memcmp and memset. */
449 #define TARGET_MEM_FUNCTIONS
451 /* Value is 1 if it is a good idea to tie two pseudo registers
452 when one has mode MODE1 and one has mode MODE2.
453 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
454 for any hard reg, then this must be 0 for correct output. */
455 #define MODES_TIEABLE_P(MODE1, MODE2) \
456 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
458 /* Specify the registers used for certain standard purposes.
459 The values of these macros are register numbers. */
461 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
462 /* #define PC_REGNUM */
464 /* Register to use for pushing function arguments. */
465 #define STACK_POINTER_REGNUM 30
467 /* Base register for access to local variables of the function. */
468 #define FRAME_POINTER_REGNUM 3
470 /* Value should be nonzero if functions must have frame pointers. */
471 #define FRAME_POINTER_REQUIRED \
472 (current_function_calls_alloca)
474 /* C statement to store the difference between the frame pointer
475 and the stack pointer values immediately after the function prologue.
477 Note, we always pretend that this is a leaf function because if
478 it's not, there's no point in trying to eliminate the
479 frame pointer. If it is a leaf function, we guessed right! */
480 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
481 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
483 /* Base register for access to arguments of the function. */
484 #define ARG_POINTER_REGNUM 3
486 /* Register in which static-chain is passed to a function. */
487 #define STATIC_CHAIN_REGNUM 29
489 /* Register which holds offset table for position-independent
492 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? 27 : 19)
493 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
495 /* Function to return the rtx used to save the pic offset table register
496 across function calls. */
497 extern struct rtx_def *hppa_pic_save_rtx PARAMS ((void));
499 #define DEFAULT_PCC_STRUCT_RETURN 0
501 /* SOM ABI says that objects larger than 64 bits are returned in memory.
502 PA64 ABI says that objects larger than 128 bits are returned in memory.
503 Note, int_size_in_bytes can return -1 if the size of the object is
504 variable or larger than the maximum value that can be expressed as
506 #define RETURN_IN_MEMORY(TYPE) \
507 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > (TARGET_64BIT ? 16 : 8))
509 /* Register in which address to store a structure value
510 is passed to a function. */
511 #define STRUCT_VALUE_REGNUM 28
513 /* Describe how we implement __builtin_eh_return. */
514 /* FIXME: What's a good choice for the EH data registers on TARGET_64BIT? */
515 #define EH_RETURN_DATA_REGNO(N) \
517 ? ((N) < 4 ? (N) + 4 : INVALID_REGNUM) \
518 : ((N) < 3 ? (N) + 20 : (N) == 4 ? 31 : INVALID_REGNUM))
519 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
520 #define EH_RETURN_HANDLER_RTX \
521 gen_rtx_MEM (word_mode, \
522 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
523 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
526 /* Offset from the argument pointer register value to the top of
527 stack. This is different from FIRST_PARM_OFFSET because of the
529 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
531 /* The letters I, J, K, L and M in a register constraint string
532 can be used to stand for particular ranges of immediate operands.
533 This macro defines what the ranges are.
534 C is the letter, and VALUE is a constant value.
535 Return 1 if VALUE is in the range specified by C.
537 `I' is used for the 11 bit constants.
538 `J' is used for the 14 bit constants.
539 `K' is used for values that can be moved with a zdepi insn.
540 `L' is used for the 5 bit constants.
542 `N' is used for values with the least significant 11 bits equal to zero
543 and when sign extended from 32 to 64 bits the
544 value does not change.
545 `O' is used for numbers n such that n+1 is a power of 2.
548 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
549 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \
550 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \
551 : (C) == 'K' ? zdepi_cint_p (VALUE) \
552 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \
553 : (C) == 'M' ? (VALUE) == 0 \
554 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \
555 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
556 == (HOST_WIDE_INT) -1 << 31)) \
557 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \
558 : (C) == 'P' ? and_mask_p (VALUE) \
561 /* Similar, but for floating or large integer constants, and defining letters
562 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
564 For PA, `G' is the floating-point constant zero. `H' is undefined. */
566 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
567 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
568 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
571 /* The class value for index registers, and the one for base regs. */
572 #define INDEX_REG_CLASS GENERAL_REGS
573 #define BASE_REG_CLASS GENERAL_REGS
575 #define FP_REG_CLASS_P(CLASS) \
576 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
578 /* True if register is floating-point. */
579 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
581 /* Given an rtx X being reloaded into a reg required to be
582 in class CLASS, return the class of reg to actually use.
583 In general this is just CLASS; but on some machines
584 in some cases it is preferable to use a more restrictive class. */
585 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
587 /* Return the register class of a scratch register needed to copy IN into
588 or out of a register in CLASS in MODE. If it can be done directly
591 Avoid doing any work for the common case calls. */
593 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
594 ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \
595 && REGNO (IN) < FIRST_PSEUDO_REGISTER) \
596 ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
598 /* On the PA it is not possible to directly move data between
599 GENERAL_REGS and FP_REGS. */
600 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
601 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
603 /* Return the stack location to use for secondary memory needed reloads. */
604 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
605 gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
608 /* Stack layout; function entry, exit and calling. */
610 /* Define this if pushing a word on the stack
611 makes the stack pointer a smaller address. */
612 /* #define STACK_GROWS_DOWNWARD */
614 /* Believe it or not. */
615 #define ARGS_GROW_DOWNWARD
617 /* Define this if the nominal address of the stack frame
618 is at the high-address end of the local variables;
619 that is, each additional local variable allocated
620 goes at a more negative offset in the frame. */
621 /* #define FRAME_GROWS_DOWNWARD */
623 /* Offset within stack frame to start allocating local variables at.
624 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
625 first local allocated. Otherwise, it is the offset to the BEGINNING
626 of the first local allocated. */
627 #define STARTING_FRAME_OFFSET 8
629 /* If we generate an insn to push BYTES bytes,
630 this says how many the stack pointer really advances by.
631 On the HP-PA, don't define this because there are no push insns. */
632 /* #define PUSH_ROUNDING(BYTES) */
634 /* Offset of first parameter from the argument pointer register value.
635 This value will be negated because the arguments grow down.
636 Also note that on STACK_GROWS_UPWARD machines (such as this one)
637 this is the distance from the frame pointer to the end of the first
638 argument, not it's beginning. To get the real offset of the first
639 argument, the size of the argument must be added. */
641 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
643 /* When a parameter is passed in a register, stack space is still
645 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
647 /* Define this if the above stack space is to be considered part of the
648 space allocated by the caller. */
649 #define OUTGOING_REG_PARM_STACK_SPACE
651 /* Keep the stack pointer constant throughout the function.
652 This is both an optimization and a necessity: longjmp
653 doesn't behave itself when the stack pointer moves within
655 #define ACCUMULATE_OUTGOING_ARGS 1
657 /* The weird HPPA calling conventions require a minimum of 48 bytes on
658 the stack: 16 bytes for register saves, and 32 bytes for magic.
659 This is the difference between the logical top of stack and the
661 #define STACK_POINTER_OFFSET \
662 (TARGET_64BIT ? -(current_function_outgoing_args_size + 16): -32)
664 #define STACK_DYNAMIC_OFFSET(FNDECL) \
666 ? (STACK_POINTER_OFFSET) \
667 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
669 /* Value is 1 if returning from a function call automatically
670 pops the arguments described by the number-of-args field in the call.
671 FUNDECL is the declaration node of the function (as a tree),
672 FUNTYPE is the data type of the function (as a tree),
673 or for a library call it is an identifier node for the subroutine name. */
675 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
677 /* Define how to find the value returned by a function.
678 VALTYPE is the data type of the value (as a tree).
679 If the precise function being called is known, FUNC is its FUNCTION_DECL;
680 otherwise, FUNC is 0. */
682 /* On the HP-PA the value is found in register(s) 28(-29), unless
683 the mode is SF or DF. Then the value is returned in fr4 (32, ) */
685 /* This must perform the same promotions as PROMOTE_MODE, else
686 PROMOTE_FUNCTION_RETURN will not work correctly. */
687 #define FUNCTION_VALUE(VALTYPE, FUNC) \
688 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
689 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
690 || POINTER_TYPE_P (VALTYPE)) \
691 ? word_mode : TYPE_MODE (VALTYPE), \
692 TREE_CODE (VALTYPE) == REAL_TYPE && !TARGET_SOFT_FLOAT ? 32 : 28)
694 /* Define how to find the value returned by a library function
695 assuming the value has mode MODE. */
697 #define LIBCALL_VALUE(MODE) \
699 (! TARGET_SOFT_FLOAT \
700 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
702 /* 1 if N is a possible register number for a function value
703 as seen by the caller. */
705 #define FUNCTION_VALUE_REGNO_P(N) \
706 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
709 /* Define a data type for recording info about an argument list
710 during the scan of that argument list. This data type should
711 hold all necessary information about the function itself
712 and about the args processed so far, enough to enable macros
713 such as FUNCTION_ARG to determine where the next arg should go.
715 On the HP-PA, this is a single integer, which is a number of words
716 of arguments scanned so far (including the invisible argument,
717 if any, which holds the structure-value-address).
718 Thus 4 or more means all following args should go on the stack. */
720 struct hppa_args {int words, nargs_prototype, indirect; };
722 #define CUMULATIVE_ARGS struct hppa_args
724 /* Initialize a variable CUM of type CUMULATIVE_ARGS
725 for a call to a function whose data type is FNTYPE.
726 For a library call, FNTYPE is 0. */
728 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
730 (CUM).indirect = INDIRECT, \
731 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
732 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
733 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
734 || RETURN_IN_MEMORY (TREE_TYPE (FNTYPE)))) \
739 /* Similar, but when scanning the definition of a procedure. We always
740 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
742 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
744 (CUM).indirect = 0, \
745 (CUM).nargs_prototype = 1000
747 /* Figure out the size in words of the function argument. */
749 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
750 ((((MODE) != BLKmode \
751 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
752 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
754 /* Update the data in CUM to advance over an argument
755 of mode MODE and data type TYPE.
756 (TYPE is null for libcalls where that information may not be available.) */
758 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
759 { (CUM).nargs_prototype--; \
760 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
761 + (((CUM).words & 01) && (TYPE) != 0 \
762 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
765 /* Determine where to put an argument to a function.
766 Value is zero to push the argument on the stack,
767 or a hard register in which to store the argument.
769 MODE is the argument's machine mode.
770 TYPE is the data type of the argument (as a tree).
771 This is null for libcalls where that information may
773 CUM is a variable of type CUMULATIVE_ARGS which gives info about
774 the preceding args and about the function being called.
775 NAMED is nonzero if this argument is a named parameter
776 (otherwise it is an extra parameter matching an ellipsis).
778 On the HP-PA the first four words of args are normally in registers
779 and the rest are pushed. But any arg that won't entirely fit in regs
782 Arguments passed in registers are either 1 or 2 words long.
784 The caller must make a distinction between calls to explicitly named
785 functions and calls through pointers to functions -- the conventions
786 are different! Calls through pointers to functions only use general
787 registers for the first four argument words.
789 Of course all this is different for the portable runtime model
790 HP wants everyone to use for ELF. Ugh. Here's a quick description
791 of how it's supposed to work.
793 1) callee side remains unchanged. It expects integer args to be
794 in the integer registers, float args in the float registers and
795 unnamed args in integer registers.
797 2) caller side now depends on if the function being called has
798 a prototype in scope (rather than if it's being called indirectly).
800 2a) If there is a prototype in scope, then arguments are passed
801 according to their type (ints in integer registers, floats in float
802 registers, unnamed args in integer registers.
804 2b) If there is no prototype in scope, then floating point arguments
805 are passed in both integer and float registers. egad.
807 FYI: The portable parameter passing conventions are almost exactly like
808 the standard parameter passing conventions on the RS6000. That's why
809 you'll see lots of similar code in rs6000.h. */
811 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
813 /* Do not expect to understand this without reading it several times. I'm
814 tempted to try and simply it, but I worry about breaking something. */
816 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
817 function_arg (&CUM, MODE, TYPE, NAMED, 0)
819 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
820 function_arg (&CUM, MODE, TYPE, NAMED, 1)
822 /* For an arg passed partly in registers and partly in memory,
823 this is the number of registers used.
824 For args passed entirely in registers or entirely in memory, zero. */
826 /* For PA32 there are never split arguments. PA64, on the other hand, can
827 pass arguments partially in registers and partially in memory. */
828 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
829 (TARGET_64BIT ? function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) : 0)
831 /* If defined, a C expression that gives the alignment boundary, in
832 bits, of an argument with the specified mode and type. If it is
833 not defined, `PARM_BOUNDARY' is used for all arguments. */
835 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
837 ? ((integer_zerop (TYPE_SIZE (TYPE)) \
838 || ! TREE_CONSTANT (TYPE_SIZE (TYPE))) \
840 : (((int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) \
841 / UNITS_PER_WORD) * BITS_PER_WORD) \
842 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
843 ? PARM_BOUNDARY : GET_MODE_ALIGNMENT(MODE)))
845 /* Arguments larger than eight bytes are passed by invisible reference */
847 /* PA64 does not pass anything by invisible reference. */
848 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
851 : (((TYPE) && int_size_in_bytes (TYPE) > 8) \
852 || ((MODE) && GET_MODE_SIZE (MODE) > 8)))
854 /* PA64 does not pass anything by invisible reference.
855 This should be undef'ed for 64bit, but we'll see if this works. The
856 problem is that we can't test TARGET_64BIT from the preprocessor. */
857 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
860 : (((TYPE) && int_size_in_bytes (TYPE) > 8) \
861 || ((MODE) && GET_MODE_SIZE (MODE) > 8)))
864 extern struct rtx_def *hppa_compare_op0, *hppa_compare_op1;
865 extern enum cmp_type hppa_branch_type;
867 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
868 pa_asm_output_mi_thunk (FILE, THUNK_FNDECL, DELTA, FUNCTION)
870 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
871 as assembly via FUNCTION_PROFILER. Just output a local label.
872 We can't use the function label because the GAS SOM target can't
873 handle the difference of a global symbol and a local symbol. */
875 #ifndef FUNC_BEGIN_PROLOG_LABEL
876 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
879 #define FUNCTION_PROFILER(FILE, LABEL) \
880 ASM_OUTPUT_INTERNAL_LABEL (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
882 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
883 void hppa_profile_hook PARAMS ((int label_no));
885 /* The profile counter if emitted must come before the prologue. */
886 #define PROFILE_BEFORE_PROLOGUE 1
888 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
889 the stack pointer does not matter. The value is tested only in
890 functions that have frame pointers.
891 No definition is equivalent to always zero. */
893 extern int may_call_alloca;
895 #define EXIT_IGNORE_STACK \
896 (get_frame_size () != 0 \
897 || current_function_calls_alloca || current_function_outgoing_args_size)
899 /* Output assembler code for a block containing the constant parts
900 of a trampoline, leaving space for the variable parts.\
902 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
903 and then branches to the specified routine.
905 This code template is copied from text segment to stack location
906 and then patched with INITIALIZE_TRAMPOLINE to contain
907 valid values, and then entered as a subroutine.
909 It is best to keep this as small as possible to avoid having to
910 flush multiple lines in the cache. */
912 #define TRAMPOLINE_TEMPLATE(FILE) \
914 if (! TARGET_64BIT) \
916 fputs ("\tldw 36(%r22),%r21\n", FILE); \
917 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
918 if (ASSEMBLER_DIALECT == 0) \
919 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
921 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
922 fputs ("\tldw 4(%r21),%r19\n", FILE); \
923 fputs ("\tldw 0(%r21),%r21\n", FILE); \
924 fputs ("\tldsid (%r21),%r1\n", FILE); \
925 fputs ("\tmtsp %r1,%sr0\n", FILE); \
926 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
927 fputs ("\tldw 40(%r22),%r29\n", FILE); \
928 fputs ("\t.word 0\n", FILE); \
929 fputs ("\t.word 0\n", FILE); \
930 fputs ("\t.word 0\n", FILE); \
931 fputs ("\t.word 0\n", FILE); \
935 fputs ("\t.dword 0\n", FILE); \
936 fputs ("\t.dword 0\n", FILE); \
937 fputs ("\t.dword 0\n", FILE); \
938 fputs ("\t.dword 0\n", FILE); \
939 fputs ("\tmfia %r31\n", FILE); \
940 fputs ("\tldd 24(%r31),%r1\n", FILE); \
941 fputs ("\tldd 24(%r1),%r27\n", FILE); \
942 fputs ("\tldd 16(%r1),%r1\n", FILE); \
943 fputs ("\tbve (%r1)\n", FILE); \
944 fputs ("\tldd 32(%r31),%r31\n", FILE); \
945 fputs ("\t.dword 0 ; fptr\n", FILE); \
946 fputs ("\t.dword 0 ; static link\n", FILE); \
950 /* Length in units of the trampoline for entering a nested function.
952 Flush the cache entries corresponding to the first and last addresses
953 of the trampoline. This is necessary as the trampoline may cross two
956 If the code part of the trampoline ever grows to > 32 bytes, then it
957 will become necessary to hack on the cacheflush pattern in pa.md. */
959 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
961 /* Emit RTL insns to initialize the variable parts of a trampoline.
962 FNADDR is an RTX for the address of the function's pure code.
963 CXT is an RTX for the static chain value for the function.
965 Move the function address to the trampoline template at offset 36.
966 Move the static chain value to trampoline template at offset 40.
967 Move the trampoline address to trampoline template at offset 44.
968 Move r19 to trampoline template at offset 48. The latter two
969 words create a plabel for the indirect call to the trampoline. */
971 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
973 if (! TARGET_64BIT) \
975 rtx start_addr, end_addr; \
977 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
978 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (FNADDR)); \
979 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
980 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (CXT)); \
981 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
982 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (TRAMP)); \
983 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
984 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), \
985 gen_rtx_REG (Pmode, 19)); \
986 /* fdc and fic only use registers for the address to flush, \
987 they do not accept integer displacements. */ \
988 start_addr = force_reg (Pmode, (TRAMP)); \
989 end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
990 emit_insn (gen_dcacheflush (start_addr, end_addr)); \
991 end_addr = force_reg (Pmode, plus_constant (start_addr, 32)); \
992 emit_insn (gen_icacheflush (start_addr, end_addr, start_addr, \
993 gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\
997 rtx start_addr, end_addr; \
999 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
1000 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (FNADDR)); \
1001 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
1002 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (CXT)); \
1003 /* Create a fat pointer for the trampoline. */ \
1004 end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1005 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
1006 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr); \
1007 end_addr = gen_rtx_REG (Pmode, 27); \
1008 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
1009 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr); \
1010 /* fdc and fic only use registers for the address to flush, \
1011 they do not accept integer displacements. */ \
1012 start_addr = force_reg (Pmode, (TRAMP)); \
1013 end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1014 emit_insn (gen_dcacheflush (start_addr, end_addr)); \
1015 end_addr = force_reg (Pmode, plus_constant (start_addr, 32)); \
1016 emit_insn (gen_icacheflush (start_addr, end_addr, start_addr, \
1017 gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\
1021 /* Perform any machine-specific adjustment in the address of the trampoline.
1022 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
1023 Adjust the trampoline address to point to the plabel at offset 44. */
1025 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
1026 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
1028 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
1029 reference the 4 integer arg registers and 4 fp arg registers.
1030 Ordinarily they are not call used registers, but they are for
1031 _builtin_saveregs, so we must make this explicit. */
1033 #define EXPAND_BUILTIN_SAVEREGS() hppa_builtin_saveregs ()
1035 /* Implement `va_start' for varargs and stdarg. */
1037 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1038 hppa_va_start (stdarg, valist, nextarg)
1040 /* Implement `va_arg'. */
1042 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1043 hppa_va_arg (valist, type)
1045 /* Addressing modes, and classification of registers for them.
1047 Using autoincrement addressing modes on PA8000 class machines is
1050 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
1051 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
1053 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
1054 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
1056 /* Macros to check register numbers against specific register classes. */
1058 /* These assume that REGNO is a hard or pseudo reg number.
1059 They give nonzero only if REGNO is a hard reg of the suitable class
1060 or a pseudo reg currently allocated to a suitable hard reg.
1061 Since they use reg_renumber, they are safe only once reg_renumber
1062 has been allocated, which happens in local-alloc.c. */
1064 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1065 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1066 #define REGNO_OK_FOR_BASE_P(REGNO) \
1067 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1068 #define REGNO_OK_FOR_FP_P(REGNO) \
1069 (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))
1071 /* Now macros that check whether X is a register and also,
1072 strictly, whether it is in a specified class.
1074 These macros are specific to the HP-PA, and may be used only
1075 in code for printing assembler insns and in conditions for
1076 define_optimization. */
1078 /* 1 if X is an fp register. */
1080 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1082 /* Maximum number of registers that can appear in a valid memory address. */
1084 #define MAX_REGS_PER_ADDRESS 2
1086 /* Recognize any constant value that is a valid address except
1087 for symbolic addresses. We get better CSE by rejecting them
1088 here and allowing hppa_legitimize_address to break them up. We
1089 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1091 #define CONSTANT_ADDRESS_P(X) \
1092 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1093 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1094 || GET_CODE (X) == HIGH) \
1095 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1097 /* Include all constant integers and constant doubles, but not
1098 floating-point, except for floating-point zero.
1100 Reject LABEL_REFs if we're not using gas or the new HP assembler.
1102 ?!? For now also reject CONST_DOUBLES in 64bit mode. This will need
1104 #ifndef NEW_HP_ASSEMBLER
1105 #define NEW_HP_ASSEMBLER 0
1107 #define LEGITIMATE_CONSTANT_P(X) \
1108 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1109 || (X) == CONST0_RTX (GET_MODE (X))) \
1110 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \
1111 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \
1112 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \
1113 && !(HOST_BITS_PER_WIDE_INT <= 32 \
1114 || (INTVAL (X) >= (HOST_WIDE_INT) -32 << 31 \
1115 && INTVAL (X) < (HOST_WIDE_INT) 32 << 31) \
1116 || cint_ok_for_move (INTVAL (X)))) \
1117 && !function_label_operand (X, VOIDmode))
1119 /* Subroutine for EXTRA_CONSTRAINT.
1121 Return 1 iff OP is a pseudo which did not get a hard register and
1122 we are running the reload pass. */
1124 #define IS_RELOADING_PSEUDO_P(OP) \
1125 ((reload_in_progress \
1126 && GET_CODE (OP) == REG \
1127 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1128 && reg_renumber [REGNO (OP)] < 0))
1130 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1132 For the HPPA, `Q' means that this is a memory operand but not a
1133 symbolic memory operand. Note that an unassigned pseudo register
1134 is such a memory operand. Needed because reload will generate
1135 these things in insns and then not re-recognize the insns, causing
1136 constrain_operands to fail.
1138 `R' is used for scaled indexed addresses.
1140 `S' is the constant 31.
1142 `T' is for fp loads and stores. */
1143 #define EXTRA_CONSTRAINT(OP, C) \
1145 (IS_RELOADING_PSEUDO_P (OP) \
1146 || (GET_CODE (OP) == MEM \
1147 && (memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
1148 || reload_in_progress) \
1149 && ! symbolic_memory_operand (OP, VOIDmode) \
1150 && !(GET_CODE (XEXP (OP, 0)) == PLUS \
1151 && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
1152 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT))))\
1154 (GET_CODE (OP) == MEM \
1155 && GET_CODE (XEXP (OP, 0)) == PLUS \
1156 && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT \
1157 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT) \
1158 && (move_operand (OP, GET_MODE (OP)) \
1159 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
1160 || reload_in_progress)) \
1162 (GET_CODE (OP) == MEM \
1163 /* Using DFmode forces only short displacements \
1164 to be recognized as valid in reg+d addresses. \
1165 However, this is not necessary for PA2.0 since\
1166 it has long FP loads/stores. */ \
1167 && memory_address_p ((TARGET_PA_20 \
1171 && GET_CODE (XEXP (OP, 0)) != LO_SUM \
1172 && !(GET_CODE (XEXP (OP, 0)) == PLUS \
1173 && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
1174 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT)))\
1176 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) \
1178 (GET_CODE (OP) == MEM \
1179 && GET_CODE (XEXP (OP, 0)) == LO_SUM \
1180 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
1181 && REG_OK_FOR_BASE_P (XEXP (XEXP (OP, 0), 0)) \
1182 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == UNSPEC \
1183 && GET_MODE (XEXP (OP, 0)) == Pmode) \
1185 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) : 0))))))
1188 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1189 and check its validity for a certain class.
1190 We have two alternate definitions for each of them.
1191 The usual definition accepts all pseudo regs; the other rejects
1192 them unless they have been allocated suitable hard regs.
1193 The symbol REG_OK_STRICT causes the latter definition to be used.
1195 Most source files want to accept pseudo regs in the hope that
1196 they will get allocated to the class that the insn wants them to be in.
1197 Source files for reload pass need to be strict.
1198 After reload, it makes no difference, since pseudo regs have
1199 been eliminated by then. */
1201 #ifndef REG_OK_STRICT
1203 /* Nonzero if X is a hard reg that can be used as an index
1204 or if it is a pseudo reg. */
1205 #define REG_OK_FOR_INDEX_P(X) \
1206 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1207 /* Nonzero if X is a hard reg that can be used as a base reg
1208 or if it is a pseudo reg. */
1209 #define REG_OK_FOR_BASE_P(X) \
1210 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1214 /* Nonzero if X is a hard reg that can be used as an index. */
1215 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1216 /* Nonzero if X is a hard reg that can be used as a base reg. */
1217 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1221 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1222 that is a valid memory address for an instruction.
1223 The MODE argument is the machine mode for the MEM expression
1224 that wants to use this address.
1226 On the HP-PA, the actual legitimate addresses must be
1227 REG+REG, REG+(REG*SCALE) or REG+SMALLINT.
1228 But we can treat a SYMBOL_REF as legitimate if it is part of this
1229 function's constant-pool, because such addresses can actually
1230 be output as REG+SMALLINT.
1232 Note we only allow 5 bit immediates for access to a constant address;
1233 doing so avoids losing for loading/storing a FP register at an address
1234 which will not fit in 5 bits. */
1236 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1237 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1239 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1240 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1242 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1243 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1245 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1246 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1248 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1250 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1251 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1252 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1253 && REG_P (XEXP (X, 0)) \
1254 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1256 else if (GET_CODE (X) == PLUS) \
1258 rtx base = 0, index = 0; \
1259 if (REG_P (XEXP (X, 0)) \
1260 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1261 base = XEXP (X, 0), index = XEXP (X, 1); \
1262 else if (REG_P (XEXP (X, 1)) \
1263 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1264 base = XEXP (X, 1), index = XEXP (X, 0); \
1266 if (GET_CODE (index) == CONST_INT \
1267 && ((INT_14_BITS (index) \
1268 && (TARGET_SOFT_FLOAT \
1270 && ((MODE == SFmode \
1271 && (INTVAL (index) % 4) == 0)\
1272 || (MODE == DFmode \
1273 && (INTVAL (index) % 8) == 0)))\
1274 || ((MODE) != SFmode && (MODE) != DFmode))) \
1275 || INT_5_BITS (index))) \
1277 if (! TARGET_SOFT_FLOAT \
1278 && ! TARGET_DISABLE_INDEXING \
1280 && ((MODE) == SFmode || (MODE) == DFmode) \
1281 && GET_CODE (index) == MULT \
1282 && GET_CODE (XEXP (index, 0)) == REG \
1283 && REG_OK_FOR_BASE_P (XEXP (index, 0)) \
1284 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1285 && INTVAL (XEXP (index, 1)) == ((MODE) == SFmode ? 4 : 8))\
1288 else if (GET_CODE (X) == LO_SUM \
1289 && GET_CODE (XEXP (X, 0)) == REG \
1290 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1291 && CONSTANT_P (XEXP (X, 1)) \
1292 && (TARGET_SOFT_FLOAT \
1293 /* We can allow symbolic LO_SUM addresses\
1296 && GET_CODE (XEXP (X, 1)) != CONST_INT)\
1297 || ((MODE) != SFmode \
1298 && (MODE) != DFmode))) \
1300 else if (GET_CODE (X) == LO_SUM \
1301 && GET_CODE (XEXP (X, 0)) == SUBREG \
1302 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG\
1303 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0)))\
1304 && CONSTANT_P (XEXP (X, 1)) \
1305 && (TARGET_SOFT_FLOAT \
1306 /* We can allow symbolic LO_SUM addresses\
1309 && GET_CODE (XEXP (X, 1)) != CONST_INT)\
1310 || ((MODE) != SFmode \
1311 && (MODE) != DFmode))) \
1313 else if (GET_CODE (X) == LABEL_REF \
1314 || (GET_CODE (X) == CONST_INT \
1315 && INT_5_BITS (X))) \
1317 /* Needed for -fPIC */ \
1318 else if (GET_CODE (X) == LO_SUM \
1319 && GET_CODE (XEXP (X, 0)) == REG \
1320 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1321 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1322 && (TARGET_SOFT_FLOAT \
1324 || ((MODE) != SFmode \
1325 && (MODE) != DFmode))) \
1329 /* Look for machine dependent ways to make the invalid address AD a
1332 For the PA, transform:
1334 memory(X + <large int>)
1338 if (<large int> & mask) >= 16
1339 Y = (<large int> & ~mask) + mask + 1 Round up.
1341 Y = (<large int> & ~mask) Round down.
1343 memory (Z + (<large int> - Y));
1345 This makes reload inheritance and reload_cse work better since Z
1348 There may be more opportunities to improve code with this hook. */
1349 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1351 int offset, newoffset, mask; \
1352 rtx new, temp = NULL_RTX; \
1354 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1355 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff); \
1358 && GET_CODE (AD) == PLUS) \
1359 temp = simplify_binary_operation (PLUS, Pmode, \
1360 XEXP (AD, 0), XEXP (AD, 1)); \
1362 new = temp ? temp : AD; \
1365 && GET_CODE (new) == PLUS \
1366 && GET_CODE (XEXP (new, 0)) == REG \
1367 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1369 offset = INTVAL (XEXP ((new), 1)); \
1371 /* Choose rounding direction. Round up if we are >= halfway. */ \
1372 if ((offset & mask) >= ((mask + 1) / 2)) \
1373 newoffset = (offset & ~mask) + mask + 1; \
1375 newoffset = offset & ~mask; \
1377 if (newoffset != 0 \
1378 && VAL_14_BITS_P (newoffset)) \
1381 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1382 GEN_INT (newoffset)); \
1383 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1384 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1385 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1395 /* Try machine-dependent ways of modifying an illegitimate address
1396 to be legitimate. If we find one, return the new, valid address.
1397 This macro is used in only one place: `memory_address' in explow.c.
1399 OLDX is the address as it was before break_out_memory_refs was called.
1400 In some cases it is useful to look at this to decide what needs to be done.
1402 MODE and WIN are passed so that this macro can use
1403 GO_IF_LEGITIMATE_ADDRESS.
1405 It is always safe for this macro to do nothing. It exists to recognize
1406 opportunities to optimize the output. */
1408 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1409 { rtx orig_x = (X); \
1410 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1411 if ((X) != orig_x && memory_address_p (MODE, X)) \
1414 /* Go to LABEL if ADDR (a legitimate address expression)
1415 has an effect that depends on the machine mode it is used for. */
1417 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1418 if (GET_CODE (ADDR) == PRE_DEC \
1419 || GET_CODE (ADDR) == POST_DEC \
1420 || GET_CODE (ADDR) == PRE_INC \
1421 || GET_CODE (ADDR) == POST_INC) \
1424 #define TARGET_ASM_SELECT_SECTION pa_select_section
1426 /* Define this macro if references to a symbol must be treated
1427 differently depending on something about the variable or
1428 function named by the symbol (such as what section it is in).
1430 The macro definition, if any, is executed immediately after the
1431 rtl for DECL or other node is created.
1432 The value of the rtl will be a `mem' whose address is a
1435 The usual thing for this macro to do is to a flag in the
1436 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1437 name string in the `symbol_ref' (if one bit is not enough
1440 On the HP-PA we use this to indicate if a symbol is in text or
1441 data space. Also, function labels need special treatment. */
1443 #define TEXT_SPACE_P(DECL)\
1444 (TREE_CODE (DECL) == FUNCTION_DECL \
1445 || (TREE_CODE (DECL) == VAR_DECL \
1446 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1447 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1449 || (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c' \
1450 && !(TREE_CODE (DECL) == STRING_CST && flag_writable_strings)))
1452 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1454 /* Specify the machine mode that this machine uses
1455 for the index in the tablejump instruction. */
1456 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? TImode : DImode)
1458 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
1459 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1461 /* Define this as 1 if `char' should by default be signed; else as 0. */
1462 #define DEFAULT_SIGNED_CHAR 1
1464 /* Max number of bytes we can move from memory to memory
1465 in one reasonably fast instruction. */
1468 /* Higher than the default as we prefer to use simple move insns
1469 (better scheduling and delay slot filling) and because our
1470 built-in block move is really a 2X unrolled loop.
1472 Believe it or not, this has to be big enough to allow for copying all
1473 arguments passed in registers to avoid infinite recursion during argument
1474 setup for a function call. Why? Consider how we copy the stack slots
1475 reserved for parameters when they may be trashed by a call. */
1476 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1478 /* Define if operations between registers always perform the operation
1479 on the full register even if a narrower mode is specified. */
1480 #define WORD_REGISTER_OPERATIONS
1482 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1483 will either zero-extend or sign-extend. The value of this macro should
1484 be the code that says which one of the two operations is implicitly
1485 done, NIL if none. */
1486 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1488 /* Nonzero if access to memory by bytes is slow and undesirable. */
1489 #define SLOW_BYTE_ACCESS 1
1491 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1492 is done just by pretending it is already truncated. */
1493 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1495 /* We assume that the store-condition-codes instructions store 0 for false
1496 and some other value for true. This is the value stored for true. */
1498 #define STORE_FLAG_VALUE 1
1500 /* When a prototype says `char' or `short', really pass an `int'. */
1501 #define PROMOTE_PROTOTYPES 1
1502 #define PROMOTE_FUNCTION_RETURN 1
1504 /* Specify the machine mode that pointers have.
1505 After generation of rtl, the compiler makes no further distinction
1506 between pointers and any other objects of this machine mode. */
1507 #define Pmode word_mode
1509 /* Add any extra modes needed to represent the condition code.
1511 HPPA floating comparisons produce condition codes. */
1512 #define EXTRA_CC_MODES CC(CCFPmode, "CCFP")
1514 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1515 return the mode to be used for the comparison. For floating-point, CCFPmode
1516 should be used. CC_NOOVmode should be used when the first operand is a
1517 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1519 #define SELECT_CC_MODE(OP,X,Y) \
1520 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1522 /* A function address in a call instruction
1523 is a byte address (for indexing purposes)
1524 so give the MEM rtx a byte's mode. */
1525 #define FUNCTION_MODE SImode
1527 /* Define this if addresses of constant functions
1528 shouldn't be put through pseudo regs where they can be cse'd.
1529 Desirable on machines where ordinary constants are expensive
1530 but a CALL with constant address is cheap. */
1531 #define NO_FUNCTION_CSE
1533 /* Define this to be nonzero if shift instructions ignore all but the low-order
1535 #define SHIFT_COUNT_TRUNCATED 1
1537 /* Compute the cost of computing a constant rtl expression RTX
1538 whose rtx-code is CODE. The body of this macro is a portion
1539 of a switch statement. If the code is computed here,
1540 return it with a return statement. Otherwise, break from the switch. */
1542 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1544 if (INTVAL (RTX) == 0) return 0; \
1545 if (INT_14_BITS (RTX)) return 1; \
1552 case CONST_DOUBLE: \
1553 if ((RTX == CONST0_RTX (DFmode) || RTX == CONST0_RTX (SFmode)) \
1554 && OUTER_CODE != SET) \
1559 #define ADDRESS_COST(RTX) \
1560 (GET_CODE (RTX) == REG ? 1 : hppa_address_cost (RTX))
1562 /* Compute extra cost of moving data between one register class
1565 Make moves from SAR so expensive they should never happen. We used to
1566 have 0xffff here, but that generates overflow in rare cases.
1568 Copies involving a FP register and a non-FP register are relatively
1569 expensive because they must go through memory.
1571 Other copies are reasonably cheap. */
1572 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1573 (CLASS1 == SHIFT_REGS ? 0x100 \
1574 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1575 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1579 /* Provide the costs of a rtl expression. This is in the body of a
1580 switch on CODE. The purpose for the cost of MULT is to encourage
1581 `synth_mult' to find a synthetic multiply when reasonable. */
1583 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1585 if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1586 return COSTS_N_INSNS (3); \
1587 return (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT) \
1588 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (20); \
1590 if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1591 return COSTS_N_INSNS (14); \
1595 return COSTS_N_INSNS (60); \
1596 case PLUS: /* this includes shNadd insns */ \
1598 if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1599 return COSTS_N_INSNS (3); \
1600 return COSTS_N_INSNS (1); \
1604 return COSTS_N_INSNS (1);
1606 /* Adjust the cost of branches. */
1607 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1609 /* Handling the special cases is going to get too complicated for a macro,
1610 just call `pa_adjust_insn_length' to do the real work. */
1611 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1612 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1614 /* Millicode insns are actually function calls with some special
1615 constraints on arguments and register usage.
1617 Millicode calls always expect their arguments in the integer argument
1618 registers, and always return their result in %r29 (ret1). They
1619 are expected to clobber their arguments, %r1, %r29, and the return
1620 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1622 This macro tells reorg that the references to arguments and
1623 millicode calls do not appear to happen until after the millicode call.
1624 This allows reorg to put insns which set the argument registers into the
1625 delay slot of the millicode call -- thus they act more like traditional
1628 Note we can not consider side effects of the insn to be delayed because
1629 the branch and link insn will clobber the return pointer. If we happened
1630 to use the return pointer in the delay slot of the call, then we lose.
1632 get_attr_type will try to recognize the given insn, so make sure to
1633 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1635 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1638 /* Control the assembler format that we output. */
1640 /* Output to assembler file text saying following lines
1641 may contain character constants, extra white space, comments, etc. */
1643 #define ASM_APP_ON ""
1645 /* Output to assembler file text saying following lines
1646 no longer contain unusual constructs. */
1648 #define ASM_APP_OFF ""
1650 /* Output deferred plabels at the end of the file. */
1652 #define ASM_FILE_END(FILE) output_deferred_plabels (FILE)
1654 /* This is how to output the definition of a user-level label named NAME,
1655 such as the label on a static function or variable NAME. */
1657 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1658 do { assemble_name (FILE, NAME); \
1659 fputc ('\n', FILE); } while (0)
1661 /* This is how to output a reference to a user-level label named NAME.
1662 `assemble_name' uses this. */
1664 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1665 fprintf ((FILE), "%s", (NAME) + (FUNCTION_NAME_P (NAME) ? 1 : 0))
1667 /* This is how to output an internal numbered label where
1668 PREFIX is the class of label and NUM is the number within the class. */
1670 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1671 {fprintf (FILE, "%c$%s%04d\n", (PREFIX)[0], (PREFIX) + 1, NUM);}
1673 /* This is how to store into the string LABEL
1674 the symbol_ref name of an internal numbered label where
1675 PREFIX is the class of label and NUM is the number within the class.
1676 This is suitable for output with `assemble_name'. */
1678 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1679 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1681 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
1683 /* We only handle DATA objects here, functions are globalized in \
1684 ASM_DECLARE_FUNCTION_NAME. */ \
1685 if (! FUNCTION_NAME_P (NAME)) \
1687 fputs ("\t.EXPORT ", FILE); \
1688 assemble_name (FILE, NAME); \
1689 fputs (",DATA\n", FILE); \
1693 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1694 output_ascii ((FILE), (P), (SIZE))
1696 /* This is how to output an element of a case-vector that is absolute.
1697 Note that this method makes filling these branch delay slots
1700 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1701 if (TARGET_BIG_SWITCH) \
1702 fprintf (FILE, "\tstw %%r1,-16(%%r30)\n\tldil LR'L$%04d,%%r1\n\tbe RR'L$%04d(%%sr4,%%r1)\n\tldw -16(%%r30),%%r1\n", VALUE, VALUE); \
1704 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1706 /* Jump tables are executable code and live in the TEXT section on the PA. */
1707 #define JUMP_TABLES_IN_TEXT_SECTION 1
1709 /* This is how to output an element of a case-vector that is relative.
1710 This must be defined correctly as it is used when generating PIC code.
1712 I believe it safe to use the same definition as ASM_OUTPUT_ADDR_VEC_ELT
1713 on the PA since ASM_OUTPUT_ADDR_VEC_ELT uses pc-relative jump instructions
1714 rather than a table of absolute addresses. */
1716 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1717 if (TARGET_BIG_SWITCH) \
1718 fprintf (FILE, "\tstw %%r1,-16(%%r30)\n\tldw T'L$%04d(%%r19),%%r1\n\tbv %%r0(%%r1)\n\tldw -16(%%r30),%%r1\n", VALUE); \
1720 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1722 /* This is how to output an assembler line
1723 that says to advance the location counter
1724 to a multiple of 2**LOG bytes. */
1726 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1727 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1729 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1730 fprintf (FILE, "\t.blockz %d\n", (SIZE))
1732 /* This says how to output an assembler line to define a global common symbol
1733 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1735 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNED) \
1737 assemble_name ((FILE), (NAME)); \
1738 fputs ("\t.comm ", (FILE)); \
1739 fprintf ((FILE), "%d\n", MAX ((SIZE), ((ALIGNED) / BITS_PER_UNIT)));}
1741 /* This says how to output an assembler line to define a local common symbol
1742 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1744 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1746 fprintf ((FILE), "\t.align %d\n", ((ALIGNED) / BITS_PER_UNIT)); \
1747 assemble_name ((FILE), (NAME)); \
1748 fprintf ((FILE), "\n\t.block %d\n", (SIZE));}
1750 /* Store in OUTPUT a string (made with alloca) containing
1751 an assembler-name for a local static variable named NAME.
1752 LABELNO is an integer which is different for each call. */
1754 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1755 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \
1756 sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
1758 /* All HP assemblers use "!" to separate logical lines. */
1759 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
1761 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1762 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1764 /* Print operand X (an rtx) in assembler syntax to file FILE.
1765 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1766 For `%' followed by punctuation, CODE is the punctuation and X is null.
1768 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1769 and an immediate zero should be represented as `r0'.
1771 Several % codes are defined:
1773 C compare conditions
1774 N extract conditions
1775 M modifier to handle preincrement addressing for memory refs.
1776 F modifier to handle preincrement addressing for fp memory refs */
1778 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1781 /* Print a memory address as an operand to reference that memory location. */
1783 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1784 { register rtx addr = ADDR; \
1785 register rtx base; \
1787 switch (GET_CODE (addr)) \
1790 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1793 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1794 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); \
1795 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1796 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); \
1799 fprintf (FILE, "%d(%s)", offset, reg_names [REGNO (base)]); \
1802 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1803 fputs ("R'", FILE); \
1804 else if (flag_pic == 0) \
1805 fputs ("RR'", FILE); \
1807 fputs ("RT'", FILE); \
1808 output_global_address (FILE, XEXP (addr, 1), 0); \
1809 fputs ("(", FILE); \
1810 output_operand (XEXP (addr, 0), 0); \
1811 fputs (")", FILE); \
1814 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); \
1815 fprintf (FILE, "(%%r0)"); \
1818 output_addr_const (FILE, addr); \
1822 /* Find the return address associated with the frame given by
1824 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1825 (return_addr_rtx (COUNT, FRAMEADDR))
1827 /* Used to mask out junk bits from the return address, such as
1828 processor state, interrupt status, condition codes and the like. */
1829 #define MASK_RETURN_ADDR \
1830 /* The privilege level is in the two low order bits, mask em out \
1831 of the return address. */ \
1834 /* The number of Pmode words for the setjmp buffer. */
1835 #define JMP_BUF_SIZE 50
1837 /* Only direct calls to static functions are allowed to be sibling (tail)
1840 This restriction is necessary because some linker generated stubs will
1841 store return pointers into rp' in some cases which might clobber a
1842 live value already in rp'.
1844 In a sibcall the current function and the target function share stack
1845 space. Thus if the path to the current function and the path to the
1846 target function save a value in rp', they save the value into the
1847 same stack slot, which has undesirable consequences.
1849 Because of the deferred binding nature of shared libraries any function
1850 with external scope could be in a different load module and thus require
1851 rp' to be saved when calling that function. So sibcall optimizations
1852 can only be safe for static function.
1854 Note that GCC never needs return value relocations, so we don't have to
1855 worry about static calls with return value relocations (which require
1858 It is safe to perform a sibcall optimization when the target function
1859 will never return. */
1860 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1862 && ! TARGET_PORTABLE_RUNTIME \
1864 && ! TREE_PUBLIC (DECL))
1866 #define PREDICATE_CODES \
1867 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1868 {"call_operand_address", {LABEL_REF, SYMBOL_REF, CONST_INT, \
1869 CONST_DOUBLE, CONST, HIGH, CONSTANT_P_RTX}}, \
1870 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
1871 {"symbolic_memory_operand", {SUBREG, MEM}}, \
1872 {"reg_before_reload_operand", {REG, MEM}}, \
1873 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
1874 {"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, MEM, CONST_INT, \
1876 {"move_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}}, \
1877 {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
1878 {"pic_label_operand", {LABEL_REF, CONST}}, \
1879 {"fp_reg_operand", {REG}}, \
1880 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1881 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
1882 {"pre_cint_operand", {CONST_INT}}, \
1883 {"post_cint_operand", {CONST_INT}}, \
1884 {"arith_double_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1885 {"ireg_or_int5_operand", {CONST_INT, REG}}, \
1886 {"int5_operand", {CONST_INT}}, \
1887 {"uint5_operand", {CONST_INT}}, \
1888 {"int11_operand", {CONST_INT}}, \
1889 {"uint32_operand", {CONST_INT, \
1890 HOST_BITS_PER_WIDE_INT > 32 ? 0 : CONST_DOUBLE}}, \
1891 {"arith5_operand", {SUBREG, REG, CONST_INT}}, \
1892 {"and_operand", {SUBREG, REG, CONST_INT}}, \
1893 {"ior_operand", {CONST_INT}}, \
1894 {"lhs_lshift_cint_operand", {CONST_INT}}, \
1895 {"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \
1896 {"arith32_operand", {SUBREG, REG, CONST_INT}}, \
1897 {"pc_or_label_operand", {PC, LABEL_REF}}, \
1898 {"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \
1899 {"shadd_operand", {CONST_INT}}, \
1900 {"basereg_operand", {REG}}, \
1901 {"div_operand", {REG, CONST_INT}}, \
1902 {"ireg_operand", {REG}}, \
1903 {"cmpib_comparison_operator", {EQ, NE, LT, LE, LEU, \
1905 {"movb_comparison_operator", {EQ, NE, LT, GE}},
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