1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 enum cmp_type /* comparison type */
27 CMP_SI, /* compare integers */
28 CMP_SF, /* compare single precision floats */
29 CMP_DF, /* compare double precision floats */
30 CMP_MAX /* max comparison type */
33 /* For long call handling. */
34 extern unsigned long total_code_bytes;
36 /* Which processor to schedule for. */
48 /* Which architecture to generate code for. */
50 enum architecture_type
59 /* For -march= option. */
60 extern const char *pa_arch_string;
61 extern enum architecture_type pa_arch;
63 /* For -mfixed-range= option. */
64 extern const char *pa_fixed_range_string;
66 /* For -mschedule= option. */
67 extern const char *pa_cpu_string;
68 extern enum processor_type pa_cpu;
70 /* For -munix= option. */
71 extern const char *pa_unix_string;
72 extern int flag_pa_unix;
74 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
76 /* Print subsidiary information on the compiler version in use. */
78 #define TARGET_VERSION fputs (" (hppa)", stderr);
80 /* Run-time compilation parameters selecting different hardware subsets. */
82 extern int target_flags;
84 /* compile code for HP-PA 1.1 ("Snake"). */
88 /* Disable all FP registers (they all become fixed). This may be necessary
89 for compiling kernels which perform lazy context switching of FP regs.
90 Note if you use this option and try to perform floating point operations
91 the compiler will abort! */
93 #define MASK_DISABLE_FPREGS 2
94 #define TARGET_DISABLE_FPREGS (target_flags & MASK_DISABLE_FPREGS)
96 /* Generate code which assumes that all space register are equivalent.
97 Triggers aggressive unscaled index addressing and faster
98 builtin_return_address. */
99 #define MASK_NO_SPACE_REGS 4
100 #define TARGET_NO_SPACE_REGS (target_flags & MASK_NO_SPACE_REGS)
102 /* Allow unconditional jumps in the delay slots of call instructions. */
103 #define MASK_JUMP_IN_DELAY 8
104 #define TARGET_JUMP_IN_DELAY (target_flags & MASK_JUMP_IN_DELAY)
106 /* Disable indexed addressing modes. */
107 #define MASK_DISABLE_INDEXING 32
108 #define TARGET_DISABLE_INDEXING (target_flags & MASK_DISABLE_INDEXING)
110 /* Emit code which follows the new portable runtime calling conventions
111 HP wants everyone to use for ELF objects. If at all possible you want
112 to avoid this since it's a performance loss for non-prototyped code.
114 Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline
115 long-call stubs which is quite expensive. */
116 #define MASK_PORTABLE_RUNTIME 64
117 #define TARGET_PORTABLE_RUNTIME (target_flags & MASK_PORTABLE_RUNTIME)
119 /* Emit directives only understood by GAS. This allows parameter
120 relocations to work for static functions. There is no way
121 to make them work the HP assembler at this time. */
123 #define TARGET_GAS (target_flags & MASK_GAS)
125 /* Emit code for processors which do not have an FPU. */
126 #define MASK_SOFT_FLOAT 256
127 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
129 /* Use 3-insn load/store sequences for access to large data segments
130 in shared libraries on hpux10. */
131 #define MASK_LONG_LOAD_STORE 512
132 #define TARGET_LONG_LOAD_STORE (target_flags & MASK_LONG_LOAD_STORE)
134 /* Use a faster sequence for indirect calls. This assumes that calls
135 through function pointers will never cross a space boundary, and
136 that the executable is not dynamically linked. Such assumptions
137 are generally safe for building kernels and statically linked
138 executables. Code compiled with this option will fail miserably if
139 the executable is dynamically linked or uses nested functions! */
140 #define MASK_FAST_INDIRECT_CALLS 1024
141 #define TARGET_FAST_INDIRECT_CALLS (target_flags & MASK_FAST_INDIRECT_CALLS)
143 /* Generate code with big switch statements to avoid out of range branches
144 occurring within the switch table. */
145 #define MASK_BIG_SWITCH 2048
146 #define TARGET_BIG_SWITCH (target_flags & MASK_BIG_SWITCH)
148 /* Generate code for the HPPA 2.0 architecture. TARGET_PA_11 should also be
149 true when this is true. */
150 #define MASK_PA_20 4096
152 /* Generate cpp defines for server I/O. */
153 #define MASK_SIO 8192
154 #define TARGET_SIO (target_flags & MASK_SIO)
156 /* Assume GNU linker by default. */
157 #define MASK_GNU_LD 16384
158 #ifndef TARGET_GNU_LD
159 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
162 /* Force generation of long calls. */
163 #define MASK_LONG_CALLS 32768
164 #ifndef TARGET_LONG_CALLS
165 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
169 #define TARGET_PA_10 (target_flags & (MASK_PA_11 | MASK_PA_20) == 0)
173 #define TARGET_PA_11 (target_flags & MASK_PA_11)
177 #define TARGET_PA_20 (target_flags & MASK_PA_20)
180 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
182 #define TARGET_64BIT 0
185 /* Generate code for ELF32 ABI. */
187 #define TARGET_ELF32 0
190 /* Generate code for SOM 32bit ABI. */
195 /* HP-UX UNIX features. */
197 #define TARGET_HPUX 0
200 /* HP-UX 10.10 UNIX 95 features. */
201 #ifndef TARGET_HPUX_10_10
202 #define TARGET_HPUX_10_10 0
205 /* HP-UX 11i multibyte and UNIX 98 extensions. */
206 #ifndef TARGET_HPUX_11_11
207 #define TARGET_HPUX_11_11 0
210 /* The following three defines are potential target switches. The current
211 defines are optimal given the current capabilities of GAS and GNU ld. */
213 /* Define to a C expression evaluating to true to use long absolute calls.
214 Currently, only the HP assembler and SOM linker support long absolute
215 calls. They are used only in non-pic code. */
216 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
218 /* Define to a C expression evaluating to true to use long pic symbol
219 difference calls. This is a call variant similar to the long pic
220 pc-relative call. Long pic symbol difference calls are only used with
221 the HP SOM linker. Currently, only the HP assembler supports these
222 calls. GAS doesn't allow an arbitrary difference of two symbols. */
223 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
225 /* Define to a C expression evaluating to true to use long pic
226 pc-relative calls. Long pic pc-relative calls are only used with
227 GAS. Currently, they are usable for calls within a module but
228 not for external calls. */
229 #define TARGET_LONG_PIC_PCREL_CALL 0
231 /* Define to a C expression evaluating to true to use SOM secondary
232 definition symbols for weak support. Linker support for secondary
233 definition symbols is buggy prior to HP-UX 11.X. */
234 #define TARGET_SOM_SDEF 0
236 /* Define to a C expression evaluating to true to save the entry value
237 of SP in the current frame marker. This is normally unnecessary.
238 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
239 HP compilers don't use this flag but it is supported by the assembler.
240 We set this flag to indicate that register %r3 has been saved at the
241 start of the frame. Thus, when the HP unwind library is used, we
242 need to generate additional code to save SP into the frame marker. */
243 #define TARGET_HPUX_UNWIND_LIBRARY 0
245 /* Macro to define tables used to set the flags. This is a
246 list in braces of target switches with each switch being
247 { "NAME", VALUE, "HELP_STRING" }. VALUE is the bits to set,
248 or minus the bits to clear. An empty string NAME is used to
249 identify the default VALUE. Do not mark empty strings for
252 #define TARGET_SWITCHES \
253 {{ "snake", MASK_PA_11, \
254 N_("Generate PA1.1 code") }, \
255 { "nosnake", -(MASK_PA_11 | MASK_PA_20), \
256 N_("Generate PA1.0 code") }, \
257 { "pa-risc-1-0", -(MASK_PA_11 | MASK_PA_20), \
258 N_("Generate PA1.0 code") }, \
259 { "pa-risc-1-1", MASK_PA_11, \
260 N_("Generate PA1.1 code") }, \
261 { "pa-risc-2-0", MASK_PA_20, \
262 N_("Generate PA2.0 code (requires binutils 2.10 or later)") }, \
263 { "disable-fpregs", MASK_DISABLE_FPREGS, \
264 N_("Disable FP regs") }, \
265 { "no-disable-fpregs", -MASK_DISABLE_FPREGS, \
266 N_("Do not disable FP regs") }, \
267 { "no-space-regs", MASK_NO_SPACE_REGS, \
268 N_("Disable space regs") }, \
269 { "space-regs", -MASK_NO_SPACE_REGS, \
270 N_("Do not disable space regs") }, \
271 { "jump-in-delay", MASK_JUMP_IN_DELAY, \
272 N_("Put jumps in call delay slots") }, \
273 { "no-jump-in-delay", -MASK_JUMP_IN_DELAY, \
274 N_("Do not put jumps in call delay slots") }, \
275 { "disable-indexing", MASK_DISABLE_INDEXING, \
276 N_("Disable indexed addressing") }, \
277 { "no-disable-indexing", -MASK_DISABLE_INDEXING, \
278 N_("Do not disable indexed addressing") }, \
279 { "portable-runtime", MASK_PORTABLE_RUNTIME, \
280 N_("Use portable calling conventions") }, \
281 { "no-portable-runtime", -MASK_PORTABLE_RUNTIME, \
282 N_("Do not use portable calling conventions") }, \
284 N_("Assume code will be assembled by GAS") }, \
285 { "no-gas", -MASK_GAS, \
286 N_("Do not assume code will be assembled by GAS") }, \
287 { "soft-float", MASK_SOFT_FLOAT, \
288 N_("Use software floating point") }, \
289 { "no-soft-float", -MASK_SOFT_FLOAT, \
290 N_("Do not use software floating point") }, \
291 { "long-load-store", MASK_LONG_LOAD_STORE, \
292 N_("Emit long load/store sequences") }, \
293 { "no-long-load-store", -MASK_LONG_LOAD_STORE, \
294 N_("Do not emit long load/store sequences") }, \
295 { "fast-indirect-calls", MASK_FAST_INDIRECT_CALLS, \
296 N_("Generate fast indirect calls") }, \
297 { "no-fast-indirect-calls", -MASK_FAST_INDIRECT_CALLS, \
298 N_("Do not generate fast indirect calls") }, \
299 { "big-switch", MASK_BIG_SWITCH, \
300 N_("Generate code for huge switch statements") }, \
301 { "no-big-switch", -MASK_BIG_SWITCH, \
302 N_("Do not generate code for huge switch statements") }, \
303 { "long-calls", MASK_LONG_CALLS, \
304 N_("Always generate long calls") }, \
305 { "no-long-calls", -MASK_LONG_CALLS, \
306 N_("Generate long calls only when needed") }, \
308 N_("Enable linker optimizations") }, \
310 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
313 #ifndef TARGET_DEFAULT
314 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
317 #ifndef TARGET_CPU_DEFAULT
318 #define TARGET_CPU_DEFAULT 0
321 #ifndef SUBTARGET_SWITCHES
322 #define SUBTARGET_SWITCHES
325 #ifndef TARGET_SCHED_DEFAULT
326 #define TARGET_SCHED_DEFAULT "8000"
329 #define TARGET_OPTIONS \
331 { "arch=", &pa_arch_string, \
332 N_("Specify PA-RISC architecture for code generation.\n" \
333 "Values are 1.0, 1.1 and 2.0."), 0}, \
334 { "fixed-range=", &pa_fixed_range_string, \
335 N_("Specify range of registers to make fixed."), 0}, \
336 { "schedule=", &pa_cpu_string, \
337 N_("Specify CPU for scheduling purposes."), 0}, \
341 #ifndef SUBTARGET_OPTIONS
342 #define SUBTARGET_OPTIONS
345 /* Support for a compile-time default CPU, et cetera. The rules are:
346 --with-schedule is ignored if -mschedule is specified.
347 --with-arch is ignored if -march is specified. */
348 #define OPTION_DEFAULT_SPECS \
349 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
350 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
352 /* Specify the dialect of assembler to use. New mnemonics is dialect one
353 and the old mnemonics are dialect zero. */
354 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
356 #define OVERRIDE_OPTIONS override_options ()
358 /* Override some settings from dbxelf.h. */
360 /* We do not have to be compatible with dbx, so we enable gdb extensions
362 #define DEFAULT_GDB_EXTENSIONS 1
364 /* This used to be zero (no max length), but big enums and such can
365 cause huge strings which killed gas.
367 We also have to avoid lossage in dbxout.c -- it does not compute the
368 string size accurately, so we are real conservative here. */
369 #undef DBX_CONTIN_LENGTH
370 #define DBX_CONTIN_LENGTH 3000
372 /* Only labels should ever begin in column zero. */
373 #define ASM_STABS_OP "\t.stabs\t"
374 #define ASM_STABN_OP "\t.stabn\t"
376 /* GDB always assumes the current function's frame begins at the value
377 of the stack pointer upon entry to the current function. Accessing
378 local variables and parameters passed on the stack is done using the
379 base of the frame + an offset provided by GCC.
381 For functions which have frame pointers this method works fine;
382 the (frame pointer) == (stack pointer at function entry) and GCC provides
383 an offset relative to the frame pointer.
385 This loses for functions without a frame pointer; GCC provides an offset
386 which is relative to the stack pointer after adjusting for the function's
387 frame size. GDB would prefer the offset to be relative to the value of
388 the stack pointer at the function's entry. Yuk! */
389 #define DEBUGGER_AUTO_OFFSET(X) \
390 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
391 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
393 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
394 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
395 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
397 #define TARGET_CPU_CPP_BUILTINS() \
399 builtin_assert("cpu=hppa"); \
400 builtin_assert("machine=hppa"); \
401 builtin_define("__hppa"); \
402 builtin_define("__hppa__"); \
404 builtin_define("_PA_RISC2_0"); \
405 else if (TARGET_PA_11) \
406 builtin_define("_PA_RISC1_1"); \
408 builtin_define("_PA_RISC1_0"); \
411 /* An old set of OS defines for various BSD-like systems. */
412 #define TARGET_OS_CPP_BUILTINS() \
415 builtin_define_std ("REVARGV"); \
416 builtin_define_std ("hp800"); \
417 builtin_define_std ("hp9000"); \
418 builtin_define_std ("hp9k8"); \
419 if (!c_dialect_cxx () && !flag_iso) \
420 builtin_define ("hppa"); \
421 builtin_define_std ("spectrum"); \
422 builtin_define_std ("unix"); \
423 builtin_assert ("system=bsd"); \
424 builtin_assert ("system=unix"); \
428 #define CC1_SPEC "%{pg:} %{p:}"
430 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
432 /* We don't want -lg. */
434 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
437 /* This macro defines command-line switches that modify the default
440 The definition is be an initializer for an array of structures. Each
441 array element has have three elements: the switch name, one of the
442 enumeration codes ADD or DELETE to indicate whether the string should be
443 inserted or deleted, and the string to be inserted or deleted. */
444 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
446 /* Make gcc agree with <machine/ansi.h> */
448 #define SIZE_TYPE "unsigned int"
449 #define PTRDIFF_TYPE "int"
450 #define WCHAR_TYPE "unsigned int"
451 #define WCHAR_TYPE_SIZE 32
453 /* Show we can debug even without a frame pointer. */
454 #define CAN_DEBUG_WITHOUT_FP
456 /* target machine storage layout */
457 typedef struct machine_function GTY(())
459 /* Flag indicating that a .NSUBSPA directive has been output for
464 /* Define this macro if it is advisable to hold scalars in registers
465 in a wider mode than that declared by the program. In such cases,
466 the value is constrained to be within the bounds of the declared
467 type, but kept valid in the wider mode. The signedness of the
468 extension may differ from that of the type. */
470 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
471 if (GET_MODE_CLASS (MODE) == MODE_INT \
472 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
475 /* Define this if most significant bit is lowest numbered
476 in instructions that operate on numbered bit-fields. */
477 #define BITS_BIG_ENDIAN 1
479 /* Define this if most significant byte of a word is the lowest numbered. */
480 /* That is true on the HP-PA. */
481 #define BYTES_BIG_ENDIAN 1
483 /* Define this if most significant word of a multiword number is lowest
485 #define WORDS_BIG_ENDIAN 1
487 #define MAX_BITS_PER_WORD 64
489 /* Width of a word, in units (bytes). */
490 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
491 #define MIN_UNITS_PER_WORD 4
493 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
494 #define PARM_BOUNDARY BITS_PER_WORD
496 /* Largest alignment required for any stack parameter, in bits.
497 Don't define this if it is equal to PARM_BOUNDARY */
498 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
500 /* Boundary (in *bits*) on which stack pointer is always aligned;
501 certain optimizations in combine depend on this.
503 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
504 the stack on the 32 and 64-bit ports, respectively. However, we
505 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
506 in main. Thus, we treat the former as the preferred alignment. */
507 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
508 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
510 /* Allocation boundary (in *bits*) for the code of a function. */
511 #define FUNCTION_BOUNDARY BITS_PER_WORD
513 /* Alignment of field after `int : 0' in a structure. */
514 #define EMPTY_FIELD_BOUNDARY 32
516 /* Every structure's size must be a multiple of this. */
517 #define STRUCTURE_SIZE_BOUNDARY 8
519 /* A bit-field declared as `int' forces `int' alignment for the struct. */
520 #define PCC_BITFIELD_TYPE_MATTERS 1
522 /* No data type wants to be aligned rounder than this. */
523 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
525 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
526 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
527 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
529 /* Make arrays of chars word-aligned for the same reasons. */
530 #define DATA_ALIGNMENT(TYPE, ALIGN) \
531 (TREE_CODE (TYPE) == ARRAY_TYPE \
532 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
533 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
535 /* Set this nonzero if move instructions will actually fail to work
536 when given unaligned data. */
537 #define STRICT_ALIGNMENT 1
539 /* Value is 1 if it is a good idea to tie two pseudo registers
540 when one has mode MODE1 and one has mode MODE2.
541 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
542 for any hard reg, then this must be 0 for correct output. */
543 #define MODES_TIEABLE_P(MODE1, MODE2) \
544 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
546 /* Specify the registers used for certain standard purposes.
547 The values of these macros are register numbers. */
549 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
550 /* #define PC_REGNUM */
552 /* Register to use for pushing function arguments. */
553 #define STACK_POINTER_REGNUM 30
555 /* Base register for access to local variables of the function. */
556 #define FRAME_POINTER_REGNUM 3
558 /* Value should be nonzero if functions must have frame pointers. */
559 #define FRAME_POINTER_REQUIRED \
560 (current_function_calls_alloca)
562 /* C statement to store the difference between the frame pointer
563 and the stack pointer values immediately after the function prologue.
565 Note, we always pretend that this is a leaf function because if
566 it's not, there's no point in trying to eliminate the
567 frame pointer. If it is a leaf function, we guessed right! */
568 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
569 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
571 /* Base register for access to arguments of the function. */
572 #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
574 /* Register in which static-chain is passed to a function. */
575 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
577 /* Register used to address the offset table for position-independent
579 #define PIC_OFFSET_TABLE_REGNUM \
580 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
582 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
584 /* Function to return the rtx used to save the pic offset table register
585 across function calls. */
586 extern struct rtx_def *hppa_pic_save_rtx (void);
588 #define DEFAULT_PCC_STRUCT_RETURN 0
590 /* Register in which address to store a structure value
591 is passed to a function. */
592 #define PA_STRUCT_VALUE_REGNUM 28
594 /* Describe how we implement __builtin_eh_return. */
595 #define EH_RETURN_DATA_REGNO(N) \
596 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
597 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
598 #define EH_RETURN_HANDLER_RTX \
599 gen_rtx_MEM (word_mode, \
600 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
601 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
604 /* Offset from the argument pointer register value to the top of
605 stack. This is different from FIRST_PARM_OFFSET because of the
607 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
609 /* The letters I, J, K, L and M in a register constraint string
610 can be used to stand for particular ranges of immediate operands.
611 This macro defines what the ranges are.
612 C is the letter, and VALUE is a constant value.
613 Return 1 if VALUE is in the range specified by C.
615 `I' is used for the 11 bit constants.
616 `J' is used for the 14 bit constants.
617 `K' is used for values that can be moved with a zdepi insn.
618 `L' is used for the 5 bit constants.
620 `N' is used for values with the least significant 11 bits equal to zero
621 and when sign extended from 32 to 64 bits the
622 value does not change.
623 `O' is used for numbers n such that n+1 is a power of 2.
626 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
627 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \
628 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \
629 : (C) == 'K' ? zdepi_cint_p (VALUE) \
630 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \
631 : (C) == 'M' ? (VALUE) == 0 \
632 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \
633 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
634 == (HOST_WIDE_INT) -1 << 31)) \
635 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \
636 : (C) == 'P' ? and_mask_p (VALUE) \
639 /* Similar, but for floating or large integer constants, and defining letters
640 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
642 For PA, `G' is the floating-point constant zero. `H' is undefined. */
644 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
645 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
646 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
649 /* The class value for index registers, and the one for base regs. */
650 #define INDEX_REG_CLASS GENERAL_REGS
651 #define BASE_REG_CLASS GENERAL_REGS
653 #define FP_REG_CLASS_P(CLASS) \
654 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
656 /* True if register is floating-point. */
657 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
659 /* Given an rtx X being reloaded into a reg required to be
660 in class CLASS, return the class of reg to actually use.
661 In general this is just CLASS; but on some machines
662 in some cases it is preferable to use a more restrictive class. */
663 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
665 /* Return the register class of a scratch register needed to copy
666 IN into a register in CLASS in MODE, or a register in CLASS in MODE
667 to IN. If it can be done directly NO_REGS is returned.
669 Avoid doing any work for the common case calls. */
670 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
671 ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \
672 && REGNO (IN) < FIRST_PSEUDO_REGISTER) \
673 ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
675 #define MAYBE_FP_REG_CLASS_P(CLASS) \
676 reg_classes_intersect_p ((CLASS), FP_REGS)
678 /* On the PA it is not possible to directly move data between
679 GENERAL_REGS and FP_REGS. */
680 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
681 (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
682 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))
684 /* Return the stack location to use for secondary memory needed reloads. */
685 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
686 gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
689 /* Stack layout; function entry, exit and calling. */
691 /* Define this if pushing a word on the stack
692 makes the stack pointer a smaller address. */
693 /* #define STACK_GROWS_DOWNWARD */
695 /* Believe it or not. */
696 #define ARGS_GROW_DOWNWARD
698 /* Define this if the nominal address of the stack frame
699 is at the high-address end of the local variables;
700 that is, each additional local variable allocated
701 goes at a more negative offset in the frame. */
702 /* #define FRAME_GROWS_DOWNWARD */
704 /* Offset within stack frame to start allocating local variables at.
705 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
706 first local allocated. Otherwise, it is the offset to the BEGINNING
707 of the first local allocated.
709 On the 32-bit ports, we reserve one slot for the previous frame
710 pointer and one fill slot. The fill slot is for compatibility
711 with HP compiled programs. On the 64-bit ports, we reserve one
712 slot for the previous frame pointer. */
713 #define STARTING_FRAME_OFFSET 8
715 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
716 of the stack. The default is to align it to STACK_BOUNDARY. */
717 #define STACK_ALIGNMENT_NEEDED 0
719 /* If we generate an insn to push BYTES bytes,
720 this says how many the stack pointer really advances by.
721 On the HP-PA, don't define this because there are no push insns. */
722 /* #define PUSH_ROUNDING(BYTES) */
724 /* Offset of first parameter from the argument pointer register value.
725 This value will be negated because the arguments grow down.
726 Also note that on STACK_GROWS_UPWARD machines (such as this one)
727 this is the distance from the frame pointer to the end of the first
728 argument, not it's beginning. To get the real offset of the first
729 argument, the size of the argument must be added. */
731 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
733 /* When a parameter is passed in a register, stack space is still
735 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
737 /* Define this if the above stack space is to be considered part of the
738 space allocated by the caller. */
739 #define OUTGOING_REG_PARM_STACK_SPACE
741 /* Keep the stack pointer constant throughout the function.
742 This is both an optimization and a necessity: longjmp
743 doesn't behave itself when the stack pointer moves within
745 #define ACCUMULATE_OUTGOING_ARGS 1
747 /* The weird HPPA calling conventions require a minimum of 48 bytes on
748 the stack: 16 bytes for register saves, and 32 bytes for magic.
749 This is the difference between the logical top of stack and the
752 On the 64-bit port, the HP C compiler allocates a 48-byte frame
753 marker, although the runtime documentation only describes a 16
754 byte marker. For compatibility, we allocate 48 bytes. */
755 #define STACK_POINTER_OFFSET \
756 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
758 #define STACK_DYNAMIC_OFFSET(FNDECL) \
760 ? (STACK_POINTER_OFFSET) \
761 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
763 /* Value is 1 if returning from a function call automatically
764 pops the arguments described by the number-of-args field in the call.
765 FUNDECL is the declaration node of the function (as a tree),
766 FUNTYPE is the data type of the function (as a tree),
767 or for a library call it is an identifier node for the subroutine name. */
769 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
771 /* Define how to find the value returned by a function.
772 VALTYPE is the data type of the value (as a tree).
773 If the precise function being called is known, FUNC is its FUNCTION_DECL;
774 otherwise, FUNC is 0. */
776 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
778 /* Define how to find the value returned by a library function
779 assuming the value has mode MODE. */
781 #define LIBCALL_VALUE(MODE) \
783 (! TARGET_SOFT_FLOAT \
784 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
786 /* 1 if N is a possible register number for a function value
787 as seen by the caller. */
789 #define FUNCTION_VALUE_REGNO_P(N) \
790 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
793 /* Define a data type for recording info about an argument list
794 during the scan of that argument list. This data type should
795 hold all necessary information about the function itself
796 and about the args processed so far, enough to enable macros
797 such as FUNCTION_ARG to determine where the next arg should go.
799 On the HP-PA, the WORDS field holds the number of words
800 of arguments scanned so far (including the invisible argument,
801 if any, which holds the structure-value-address). Thus, 4 or
802 more means all following args should go on the stack.
804 The INCOMING field tracks whether this is an "incoming" or
807 The INDIRECT field indicates whether this is is an indirect
810 The NARGS_PROTOTYPE field indicates that an argument does not
811 have a prototype when it less than or equal to 0. */
813 struct hppa_args {int words, nargs_prototype, incoming, indirect; };
815 #define CUMULATIVE_ARGS struct hppa_args
817 /* Initialize a variable CUM of type CUMULATIVE_ARGS
818 for a call to a function whose data type is FNTYPE.
819 For a library call, FNTYPE is 0. */
821 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
823 (CUM).incoming = 0, \
824 (CUM).indirect = (FNTYPE) && !(FNDECL), \
825 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
826 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
827 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
828 || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
833 /* Similar, but when scanning the definition of a procedure. We always
834 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
836 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
838 (CUM).incoming = 1, \
839 (CUM).indirect = 0, \
840 (CUM).nargs_prototype = 1000
842 /* Figure out the size in words of the function argument. The size
843 returned by this macro should always be greater than zero because
844 we pass variable and zero sized objects by reference. */
846 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
847 ((((MODE) != BLKmode \
848 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
849 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
851 /* Update the data in CUM to advance over an argument
852 of mode MODE and data type TYPE.
853 (TYPE is null for libcalls where that information may not be available.) */
855 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
856 { (CUM).nargs_prototype--; \
857 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
858 + (((CUM).words & 01) && (TYPE) != 0 \
859 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
862 /* Determine where to put an argument to a function.
863 Value is zero to push the argument on the stack,
864 or a hard register in which to store the argument.
866 MODE is the argument's machine mode.
867 TYPE is the data type of the argument (as a tree).
868 This is null for libcalls where that information may
870 CUM is a variable of type CUMULATIVE_ARGS which gives info about
871 the preceding args and about the function being called.
872 NAMED is nonzero if this argument is a named parameter
873 (otherwise it is an extra parameter matching an ellipsis).
875 On the HP-PA the first four words of args are normally in registers
876 and the rest are pushed. But any arg that won't entirely fit in regs
879 Arguments passed in registers are either 1 or 2 words long.
881 The caller must make a distinction between calls to explicitly named
882 functions and calls through pointers to functions -- the conventions
883 are different! Calls through pointers to functions only use general
884 registers for the first four argument words.
886 Of course all this is different for the portable runtime model
887 HP wants everyone to use for ELF. Ugh. Here's a quick description
888 of how it's supposed to work.
890 1) callee side remains unchanged. It expects integer args to be
891 in the integer registers, float args in the float registers and
892 unnamed args in integer registers.
894 2) caller side now depends on if the function being called has
895 a prototype in scope (rather than if it's being called indirectly).
897 2a) If there is a prototype in scope, then arguments are passed
898 according to their type (ints in integer registers, floats in float
899 registers, unnamed args in integer registers.
901 2b) If there is no prototype in scope, then floating point arguments
902 are passed in both integer and float registers. egad.
904 FYI: The portable parameter passing conventions are almost exactly like
905 the standard parameter passing conventions on the RS6000. That's why
906 you'll see lots of similar code in rs6000.h. */
908 /* If defined, a C expression which determines whether, and in which
909 direction, to pad out an argument with extra space. */
910 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
912 /* Specify padding for the last element of a block move between registers
915 The 64-bit runtime specifies that objects need to be left justified
916 (i.e., the normal justification for a big endian target). The 32-bit
917 runtime specifies right justification for objects smaller than 64 bits.
918 We use a DImode register in the parallel for 5 to 7 byte structures
919 so that there is only one element. This allows the object to be
921 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) (TARGET_64BIT ? upward : downward)
923 /* Do not expect to understand this without reading it several times. I'm
924 tempted to try and simply it, but I worry about breaking something. */
926 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
927 function_arg (&CUM, MODE, TYPE, NAMED)
929 /* For an arg passed partly in registers and partly in memory,
930 this is the number of registers used.
931 For args passed entirely in registers or entirely in memory, zero. */
933 /* For PA32 there are never split arguments. PA64, on the other hand, can
934 pass arguments partially in registers and partially in memory. */
935 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
936 (TARGET_64BIT ? function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) : 0)
938 /* If defined, a C expression that gives the alignment boundary, in
939 bits, of an argument with the specified mode and type. If it is
940 not defined, `PARM_BOUNDARY' is used for all arguments. */
942 /* Arguments larger than one word are double word aligned. */
944 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
946 ? (integer_zerop (TYPE_SIZE (TYPE)) \
947 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
948 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
949 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
950 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
953 extern GTY(()) rtx hppa_compare_op0;
954 extern GTY(()) rtx hppa_compare_op1;
955 extern enum cmp_type hppa_branch_type;
957 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
958 as assembly via FUNCTION_PROFILER. Just output a local label.
959 We can't use the function label because the GAS SOM target can't
960 handle the difference of a global symbol and a local symbol. */
962 #ifndef FUNC_BEGIN_PROLOG_LABEL
963 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
966 #define FUNCTION_PROFILER(FILE, LABEL) \
967 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
969 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
970 void hppa_profile_hook (int label_no);
972 /* The profile counter if emitted must come before the prologue. */
973 #define PROFILE_BEFORE_PROLOGUE 1
975 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
976 the stack pointer does not matter. The value is tested only in
977 functions that have frame pointers.
978 No definition is equivalent to always zero. */
980 extern int may_call_alloca;
982 #define EXIT_IGNORE_STACK \
983 (get_frame_size () != 0 \
984 || current_function_calls_alloca || current_function_outgoing_args_size)
986 /* Output assembler code for a block containing the constant parts
987 of a trampoline, leaving space for the variable parts.\
989 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
990 and then branches to the specified routine.
992 This code template is copied from text segment to stack location
993 and then patched with INITIALIZE_TRAMPOLINE to contain
994 valid values, and then entered as a subroutine.
996 It is best to keep this as small as possible to avoid having to
997 flush multiple lines in the cache. */
999 #define TRAMPOLINE_TEMPLATE(FILE) \
1001 if (!TARGET_64BIT) \
1003 fputs ("\tldw 36(%r22),%r21\n", FILE); \
1004 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
1005 if (ASSEMBLER_DIALECT == 0) \
1006 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
1008 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
1009 fputs ("\tldw 4(%r21),%r19\n", FILE); \
1010 fputs ("\tldw 0(%r21),%r21\n", FILE); \
1013 fputs ("\tbve (%r21)\n", FILE); \
1014 fputs ("\tldw 40(%r22),%r29\n", FILE); \
1015 fputs ("\t.word 0\n", FILE); \
1016 fputs ("\t.word 0\n", FILE); \
1020 fputs ("\tldsid (%r21),%r1\n", FILE); \
1021 fputs ("\tmtsp %r1,%sr0\n", FILE); \
1022 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
1023 fputs ("\tldw 40(%r22),%r29\n", FILE); \
1025 fputs ("\t.word 0\n", FILE); \
1026 fputs ("\t.word 0\n", FILE); \
1027 fputs ("\t.word 0\n", FILE); \
1028 fputs ("\t.word 0\n", FILE); \
1032 fputs ("\t.dword 0\n", FILE); \
1033 fputs ("\t.dword 0\n", FILE); \
1034 fputs ("\t.dword 0\n", FILE); \
1035 fputs ("\t.dword 0\n", FILE); \
1036 fputs ("\tmfia %r31\n", FILE); \
1037 fputs ("\tldd 24(%r31),%r1\n", FILE); \
1038 fputs ("\tldd 24(%r1),%r27\n", FILE); \
1039 fputs ("\tldd 16(%r1),%r1\n", FILE); \
1040 fputs ("\tbve (%r1)\n", FILE); \
1041 fputs ("\tldd 32(%r31),%r31\n", FILE); \
1042 fputs ("\t.dword 0 ; fptr\n", FILE); \
1043 fputs ("\t.dword 0 ; static link\n", FILE); \
1047 /* Length in units of the trampoline for entering a nested function. */
1049 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
1051 /* Length in units of the trampoline instruction code. */
1053 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
1055 /* Minimum length of a cache line. A length of 16 will work on all
1056 PA-RISC processors. All PA 1.1 processors have a cache line of
1057 32 bytes. Most but not all PA 2.0 processors have a cache line
1058 of 64 bytes. As cache flushes are expensive and we don't support
1059 PA 1.0, we use a minimum length of 32. */
1061 #define MIN_CACHELINE_SIZE 32
1063 /* Emit RTL insns to initialize the variable parts of a trampoline.
1064 FNADDR is an RTX for the address of the function's pure code.
1065 CXT is an RTX for the static chain value for the function.
1067 Move the function address to the trampoline template at offset 36.
1068 Move the static chain value to trampoline template at offset 40.
1069 Move the trampoline address to trampoline template at offset 44.
1070 Move r19 to trampoline template at offset 48. The latter two
1071 words create a plabel for the indirect call to the trampoline.
1073 A similar sequence is used for the 64-bit port but the plabel is
1074 at the beginning of the trampoline.
1076 Finally, the cache entries for the trampoline code are flushed.
1077 This is necessary to ensure that the trampoline instruction sequence
1078 is written to memory prior to any attempts at prefetching the code
1081 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1083 rtx start_addr = gen_reg_rtx (Pmode); \
1084 rtx end_addr = gen_reg_rtx (Pmode); \
1085 rtx line_length = gen_reg_rtx (Pmode); \
1088 if (!TARGET_64BIT) \
1090 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
1091 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
1092 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
1093 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
1095 /* Create a fat pointer for the trampoline. */ \
1096 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
1097 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
1098 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
1099 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1100 gen_rtx_REG (Pmode, 19)); \
1102 /* fdc and fic only use registers for the address to flush, \
1103 they do not accept integer displacements. We align the \
1104 start and end addresses to the beginning of their respective \
1105 cache lines to minimize the number of lines flushed. */ \
1106 tmp = force_reg (Pmode, (TRAMP)); \
1107 emit_insn (gen_andsi3 (start_addr, tmp, \
1108 GEN_INT (-MIN_CACHELINE_SIZE))); \
1109 tmp = force_reg (Pmode, \
1110 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1111 emit_insn (gen_andsi3 (end_addr, tmp, \
1112 GEN_INT (-MIN_CACHELINE_SIZE))); \
1113 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1114 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1115 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1116 gen_reg_rtx (Pmode), \
1117 gen_reg_rtx (Pmode))); \
1121 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
1122 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
1123 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
1124 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
1126 /* Create a fat pointer for the trampoline. */ \
1127 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
1128 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1129 force_reg (Pmode, plus_constant ((TRAMP), 32))); \
1130 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
1131 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1132 gen_rtx_REG (Pmode, 27)); \
1134 /* fdc and fic only use registers for the address to flush, \
1135 they do not accept integer displacements. We align the \
1136 start and end addresses to the beginning of their respective \
1137 cache lines to minimize the number of lines flushed. */ \
1138 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1139 emit_insn (gen_anddi3 (start_addr, tmp, \
1140 GEN_INT (-MIN_CACHELINE_SIZE))); \
1141 tmp = force_reg (Pmode, \
1142 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1143 emit_insn (gen_anddi3 (end_addr, tmp, \
1144 GEN_INT (-MIN_CACHELINE_SIZE))); \
1145 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1146 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1147 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1148 gen_reg_rtx (Pmode), \
1149 gen_reg_rtx (Pmode))); \
1153 /* Perform any machine-specific adjustment in the address of the trampoline.
1154 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
1155 Adjust the trampoline address to point to the plabel at offset 44. */
1157 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
1158 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
1160 /* Implement `va_start' for varargs and stdarg. */
1162 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1163 hppa_va_start (valist, nextarg)
1165 /* Addressing modes, and classification of registers for them.
1167 Using autoincrement addressing modes on PA8000 class machines is
1170 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
1171 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
1173 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
1174 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
1176 /* Macros to check register numbers against specific register classes. */
1178 /* These assume that REGNO is a hard or pseudo reg number.
1179 They give nonzero only if REGNO is a hard reg of the suitable class
1180 or a pseudo reg currently allocated to a suitable hard reg.
1181 Since they use reg_renumber, they are safe only once reg_renumber
1182 has been allocated, which happens in local-alloc.c. */
1184 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1185 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1186 #define REGNO_OK_FOR_BASE_P(REGNO) \
1187 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1188 #define REGNO_OK_FOR_FP_P(REGNO) \
1189 (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))
1191 /* Now macros that check whether X is a register and also,
1192 strictly, whether it is in a specified class.
1194 These macros are specific to the HP-PA, and may be used only
1195 in code for printing assembler insns and in conditions for
1196 define_optimization. */
1198 /* 1 if X is an fp register. */
1200 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1202 /* Maximum number of registers that can appear in a valid memory address. */
1204 #define MAX_REGS_PER_ADDRESS 2
1206 /* Recognize any constant value that is a valid address except
1207 for symbolic addresses. We get better CSE by rejecting them
1208 here and allowing hppa_legitimize_address to break them up. We
1209 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1211 #define CONSTANT_ADDRESS_P(X) \
1212 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1213 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1214 || GET_CODE (X) == HIGH) \
1215 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1217 /* A C expression that is nonzero if we are using the new HP assembler. */
1219 #ifndef NEW_HP_ASSEMBLER
1220 #define NEW_HP_ASSEMBLER 0
1223 /* The macros below define the immediate range for CONST_INTS on
1224 the 64-bit port. Constants in this range can be loaded in three
1225 instructions using a ldil/ldo/depdi sequence. Constants outside
1226 this range are forced to the constant pool prior to reload. */
1228 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
1229 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
1230 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
1231 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
1233 /* A C expression that is nonzero if X is a legitimate constant for an
1236 We include all constant integers and constant doubles, but not
1237 floating-point, except for floating-point zero. We reject LABEL_REFs
1238 if we're not using gas or the new HP assembler.
1240 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
1241 that need more than three instructions to load prior to reload. This
1242 limit is somewhat arbitrary. It takes three instructions to load a
1243 CONST_INT from memory but two are memory accesses. It may be better
1244 to increase the allowed range for CONST_INTS. We may also be able
1245 to handle CONST_DOUBLES. */
1247 #define LEGITIMATE_CONSTANT_P(X) \
1248 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1249 || (X) == CONST0_RTX (GET_MODE (X))) \
1250 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \
1251 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \
1252 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \
1253 && !(HOST_BITS_PER_WIDE_INT <= 32 \
1254 || (reload_in_progress || reload_completed) \
1255 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
1256 || cint_ok_for_move (INTVAL (X)))) \
1257 && !function_label_operand (X, VOIDmode))
1259 /* Subroutines for EXTRA_CONSTRAINT.
1261 Return 1 iff OP is a pseudo which did not get a hard register and
1262 we are running the reload pass. */
1263 #define IS_RELOADING_PSEUDO_P(OP) \
1264 ((reload_in_progress \
1265 && GET_CODE (OP) == REG \
1266 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1267 && reg_renumber [REGNO (OP)] < 0))
1269 /* Return 1 iff OP is a scaled or unscaled index address. */
1270 #define IS_INDEX_ADDR_P(OP) \
1271 (GET_CODE (OP) == PLUS \
1272 && GET_MODE (OP) == Pmode \
1273 && (GET_CODE (XEXP (OP, 0)) == MULT \
1274 || GET_CODE (XEXP (OP, 1)) == MULT \
1275 || (REG_P (XEXP (OP, 0)) \
1276 && REG_P (XEXP (OP, 1)))))
1278 /* Return 1 iff OP is a LO_SUM DLT address. */
1279 #define IS_LO_SUM_DLT_ADDR_P(OP) \
1280 (GET_CODE (OP) == LO_SUM \
1281 && GET_MODE (OP) == Pmode \
1282 && REG_P (XEXP (OP, 0)) \
1283 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
1284 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
1286 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1288 `A' is a LO_SUM DLT memory operand.
1290 `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
1291 memory operand. Note that an unassigned pseudo register is such a
1292 memory operand. Needed because reload will generate these things
1293 and then not re-recognize the insn, causing constrain_operands to
1296 `R' is a scaled/unscaled indexed memory operand.
1298 `S' is the constant 31.
1300 `T' is for floating-point loads and stores.
1302 `U' is the constant 63. */
1304 #define EXTRA_CONSTRAINT(OP, C) \
1306 (IS_RELOADING_PSEUDO_P (OP) \
1307 || (GET_CODE (OP) == MEM \
1308 && (reload_in_progress \
1309 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))) \
1310 && !symbolic_memory_operand (OP, VOIDmode) \
1311 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1312 && !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \
1314 (GET_CODE (OP) == MEM \
1315 && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \
1317 (GET_CODE (OP) == MEM \
1318 && IS_INDEX_ADDR_P (XEXP (OP, 0))) \
1320 (GET_CODE (OP) == MEM \
1321 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1322 && !IS_INDEX_ADDR_P (XEXP (OP, 0)) \
1323 /* Floating-point loads and stores are used to load \
1324 integer values as well as floating-point values. \
1325 They don't have the same set of REG+D address modes \
1326 as integer loads and stores. PA 1.x supports only \
1327 short displacements. PA 2.0 supports long displacements \
1328 but the base register needs to be aligned. \
1330 The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and \
1331 DFmode test the validity of an address for use in a \
1332 floating point load or store. So, we use SFmode/DFmode \
1333 to see if the address is valid for a floating-point \
1334 load/store operation. */ \
1335 && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4 \
1340 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \
1342 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0))))))
1345 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1346 and check its validity for a certain class.
1347 We have two alternate definitions for each of them.
1348 The usual definition accepts all pseudo regs; the other rejects
1349 them unless they have been allocated suitable hard regs.
1350 The symbol REG_OK_STRICT causes the latter definition to be used.
1352 Most source files want to accept pseudo regs in the hope that
1353 they will get allocated to the class that the insn wants them to be in.
1354 Source files for reload pass need to be strict.
1355 After reload, it makes no difference, since pseudo regs have
1356 been eliminated by then. */
1358 #ifndef REG_OK_STRICT
1360 /* Nonzero if X is a hard reg that can be used as an index
1361 or if it is a pseudo reg. */
1362 #define REG_OK_FOR_INDEX_P(X) \
1363 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1364 /* Nonzero if X is a hard reg that can be used as a base reg
1365 or if it is a pseudo reg. */
1366 #define REG_OK_FOR_BASE_P(X) \
1367 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1371 /* Nonzero if X is a hard reg that can be used as an index. */
1372 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1373 /* Nonzero if X is a hard reg that can be used as a base reg. */
1374 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1378 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1379 valid memory address for an instruction. The MODE argument is the
1380 machine mode for the MEM expression that wants to use this address.
1382 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
1383 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
1384 available with floating point loads and stores, and integer loads.
1385 We get better code by allowing indexed addresses in the initial
1388 The acceptance of indexed addresses as legitimate implies that we
1389 must provide patterns for doing indexed integer stores, or the move
1390 expanders must force the address of an indexed store to a register.
1391 We have adopted the latter approach.
1393 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
1394 the base register is a valid pointer for indexed instructions.
1395 On targets that have non-equivalent space registers, we have to
1396 know at the time of assembler output which register in a REG+REG
1397 pair is the base register. The REG_POINTER flag is sometimes lost
1398 in reload and the following passes, so it can't be relied on during
1399 code generation. Thus, we either have to canonicalize the order
1400 of the registers in REG+REG indexed addresses, or treat REG+REG
1401 addresses separately and provide patterns for both permutations.
1403 The latter approach requires several hundred additional lines of
1404 code in pa.md. The downside to canonicalizing is that a PLUS
1405 in the wrong order can't combine to form to make a scaled indexed
1406 memory operand. As we won't need to canonicalize the operands if
1407 the REG_POINTER lossage can be fixed, it seems better canonicalize.
1409 We initially break out scaled indexed addresses in canonical order
1410 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
1411 scaled indexed addresses during RTL generation. However, fold_rtx
1412 has its own opinion on how the operands of a PLUS should be ordered.
1413 If one of the operands is equivalent to a constant, it will make
1414 that operand the second operand. As the base register is likely to
1415 be equivalent to a SYMBOL_REF, we have made it the second operand.
1417 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
1418 operands are in the order INDEX+BASE on targets with non-equivalent
1419 space registers, and in any order on targets with equivalent space
1420 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
1422 We treat a SYMBOL_REF as legitimate if it is part of the current
1423 function's constant-pool, because such addresses can actually be
1424 output as REG+SMALLINT.
1426 Note we only allow 5 bit immediates for access to a constant address;
1427 doing so avoids losing for loading/storing a FP register at an address
1428 which will not fit in 5 bits. */
1430 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1431 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1433 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1434 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1436 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1437 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1439 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1440 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1442 #if HOST_BITS_PER_WIDE_INT > 32
1443 #define VAL_32_BITS_P(X) \
1444 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
1445 < (unsigned HOST_WIDE_INT) 2 << 31)
1447 #define VAL_32_BITS_P(X) 1
1449 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
1451 /* These are the modes that we allow for scaled indexing. */
1452 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
1453 ((TARGET_64BIT && (MODE) == DImode) \
1454 || (MODE) == SImode \
1455 || (MODE) == HImode \
1456 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1458 /* These are the modes that we allow for unscaled indexing. */
1459 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1460 ((TARGET_64BIT && (MODE) == DImode) \
1461 || (MODE) == SImode \
1462 || (MODE) == HImode \
1463 || (MODE) == QImode \
1464 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1466 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1468 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1469 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1470 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1471 && REG_P (XEXP (X, 0)) \
1472 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1474 else if (GET_CODE (X) == PLUS) \
1476 rtx base = 0, index = 0; \
1477 if (REG_P (XEXP (X, 1)) \
1478 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1479 base = XEXP (X, 1), index = XEXP (X, 0); \
1480 else if (REG_P (XEXP (X, 0)) \
1481 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1482 base = XEXP (X, 0), index = XEXP (X, 1); \
1484 && GET_CODE (index) == CONST_INT \
1485 && ((INT_14_BITS (index) \
1486 && (((MODE) != DImode \
1487 && (MODE) != SFmode \
1488 && (MODE) != DFmode) \
1489 /* The base register for DImode loads and stores \
1490 with long displacements must be aligned because \
1491 the lower three bits in the displacement are \
1492 assumed to be zero. */ \
1493 || ((MODE) == DImode \
1495 || (INTVAL (index) % 8) == 0)) \
1496 /* Similarly, the base register for SFmode/DFmode \
1497 loads and stores with long displacements must \
1500 FIXME: the ELF32 linker clobbers the LSB of \
1501 the FP register number in PA 2.0 floating-point \
1502 insns with long displacements. This is because \
1503 R_PARISC_DPREL14WR and other relocations like \
1504 it are not supported. For now, we reject long \
1505 displacements on this target. */ \
1506 || (((MODE) == SFmode || (MODE) == DFmode) \
1507 && (TARGET_SOFT_FLOAT \
1510 && (INTVAL (index) \
1511 % GET_MODE_SIZE (MODE)) == 0))))) \
1512 || INT_5_BITS (index))) \
1514 if (!TARGET_DISABLE_INDEXING \
1515 /* Only accept the "canonical" INDEX+BASE operand order \
1516 on targets with non-equivalent space registers. */ \
1517 && (TARGET_NO_SPACE_REGS \
1518 ? (base && REG_P (index)) \
1519 : (base == XEXP (X, 1) && REG_P (index) \
1520 && REG_POINTER (base) && !REG_POINTER (index))) \
1521 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1522 && REG_OK_FOR_INDEX_P (index) \
1523 && borx_reg_operand (base, Pmode) \
1524 && borx_reg_operand (index, Pmode)) \
1526 if (!TARGET_DISABLE_INDEXING \
1528 && GET_CODE (index) == MULT \
1529 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1530 && REG_P (XEXP (index, 0)) \
1531 && GET_MODE (XEXP (index, 0)) == Pmode \
1532 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1533 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1534 && INTVAL (XEXP (index, 1)) \
1535 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1536 && borx_reg_operand (base, Pmode)) \
1539 else if (GET_CODE (X) == LO_SUM \
1540 && GET_CODE (XEXP (X, 0)) == REG \
1541 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1542 && CONSTANT_P (XEXP (X, 1)) \
1543 && (TARGET_SOFT_FLOAT \
1544 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1547 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1548 || ((MODE) != SFmode \
1549 && (MODE) != DFmode))) \
1551 else if (GET_CODE (X) == LO_SUM \
1552 && GET_CODE (XEXP (X, 0)) == SUBREG \
1553 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1554 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1555 && CONSTANT_P (XEXP (X, 1)) \
1556 && (TARGET_SOFT_FLOAT \
1557 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1560 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1561 || ((MODE) != SFmode \
1562 && (MODE) != DFmode))) \
1564 else if (GET_CODE (X) == LABEL_REF \
1565 || (GET_CODE (X) == CONST_INT \
1566 && INT_5_BITS (X))) \
1568 /* Needed for -fPIC */ \
1569 else if (GET_CODE (X) == LO_SUM \
1570 && GET_CODE (XEXP (X, 0)) == REG \
1571 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1572 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1573 && (TARGET_SOFT_FLOAT \
1574 || (TARGET_PA_20 && !TARGET_ELF32) \
1575 || ((MODE) != SFmode \
1576 && (MODE) != DFmode))) \
1580 /* Look for machine dependent ways to make the invalid address AD a
1583 For the PA, transform:
1585 memory(X + <large int>)
1589 if (<large int> & mask) >= 16
1590 Y = (<large int> & ~mask) + mask + 1 Round up.
1592 Y = (<large int> & ~mask) Round down.
1594 memory (Z + (<large int> - Y));
1596 This makes reload inheritance and reload_cse work better since Z
1599 There may be more opportunities to improve code with this hook. */
1600 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1602 long offset, newoffset, mask; \
1603 rtx new, temp = NULL_RTX; \
1605 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1606 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
1608 if (optimize && GET_CODE (AD) == PLUS) \
1609 temp = simplify_binary_operation (PLUS, Pmode, \
1610 XEXP (AD, 0), XEXP (AD, 1)); \
1612 new = temp ? temp : AD; \
1615 && GET_CODE (new) == PLUS \
1616 && GET_CODE (XEXP (new, 0)) == REG \
1617 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1619 offset = INTVAL (XEXP ((new), 1)); \
1621 /* Choose rounding direction. Round up if we are >= halfway. */ \
1622 if ((offset & mask) >= ((mask + 1) / 2)) \
1623 newoffset = (offset & ~mask) + mask + 1; \
1625 newoffset = offset & ~mask; \
1627 /* Ensure that long displacements are aligned. */ \
1628 if (!VAL_5_BITS_P (newoffset) \
1629 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1630 newoffset &= ~(GET_MODE_SIZE (MODE) -1); \
1632 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1634 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1635 GEN_INT (newoffset)); \
1636 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1637 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1638 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1648 /* Try machine-dependent ways of modifying an illegitimate address
1649 to be legitimate. If we find one, return the new, valid address.
1650 This macro is used in only one place: `memory_address' in explow.c.
1652 OLDX is the address as it was before break_out_memory_refs was called.
1653 In some cases it is useful to look at this to decide what needs to be done.
1655 MODE and WIN are passed so that this macro can use
1656 GO_IF_LEGITIMATE_ADDRESS.
1658 It is always safe for this macro to do nothing. It exists to recognize
1659 opportunities to optimize the output. */
1661 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1662 { rtx orig_x = (X); \
1663 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1664 if ((X) != orig_x && memory_address_p (MODE, X)) \
1667 /* Go to LABEL if ADDR (a legitimate address expression)
1668 has an effect that depends on the machine mode it is used for. */
1670 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1671 if (GET_CODE (ADDR) == PRE_DEC \
1672 || GET_CODE (ADDR) == POST_DEC \
1673 || GET_CODE (ADDR) == PRE_INC \
1674 || GET_CODE (ADDR) == POST_INC) \
1677 #define TARGET_ASM_SELECT_SECTION pa_select_section
1679 /* Return a nonzero value if DECL has a section attribute. */
1680 #define IN_NAMED_SECTION_P(DECL) \
1681 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1682 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1684 /* The following extra sections and extra section functions are only used
1685 for SOM, but they must be provided unconditionally because pa.c's calls
1686 to the functions might not get optimized out when other object formats
1689 #define EXTRA_SECTIONS \
1690 in_som_readonly_data, \
1691 in_som_one_only_readonly_data, \
1692 in_som_one_only_data
1694 #define EXTRA_SECTION_FUNCTIONS \
1695 SOM_READONLY_DATA_SECTION_FUNCTION \
1696 SOM_ONE_ONLY_READONLY_DATA_SECTION_FUNCTION \
1697 SOM_ONE_ONLY_DATA_SECTION_FUNCTION \
1698 FORGET_SECTION_FUNCTION
1700 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
1701 is not being generated. */
1702 #define SOM_READONLY_DATA_SECTION_FUNCTION \
1704 som_readonly_data_section (void) \
1708 if (in_section != in_som_readonly_data) \
1710 in_section = in_som_readonly_data; \
1711 fputs ("\t.SPACE $TEXT$\n\t.SUBSPA $LIT$\n", asm_out_file); \
1715 /* When secondary definitions are not supported, SOM makes readonly data one
1716 only by creating a new $LIT$ subspace in $TEXT$ with the comdat flag. */
1717 #define SOM_ONE_ONLY_READONLY_DATA_SECTION_FUNCTION \
1719 som_one_only_readonly_data_section (void) \
1723 in_section = in_som_one_only_readonly_data; \
1724 fputs ("\t.SPACE $TEXT$\n" \
1725 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=16,COMDAT\n",\
1729 /* When secondary definitions are not supported, SOM makes data one only by
1730 creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
1731 #define SOM_ONE_ONLY_DATA_SECTION_FUNCTION \
1733 som_one_only_data_section (void) \
1737 in_section = in_som_one_only_data; \
1738 fputs ("\t.SPACE $PRIVATE$\n" \
1739 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31,SORT=24,COMDAT\n", \
1743 #define FORGET_SECTION_FUNCTION \
1745 forget_section (void) \
1747 in_section = no_section; \
1750 /* Define this macro if references to a symbol must be treated
1751 differently depending on something about the variable or
1752 function named by the symbol (such as what section it is in).
1754 The macro definition, if any, is executed immediately after the
1755 rtl for DECL or other node is created.
1756 The value of the rtl will be a `mem' whose address is a
1759 The usual thing for this macro to do is to a flag in the
1760 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1761 name string in the `symbol_ref' (if one bit is not enough
1764 On the HP-PA we use this to indicate if a symbol is in text or
1765 data space. Also, function labels need special treatment. */
1767 #define TEXT_SPACE_P(DECL)\
1768 (TREE_CODE (DECL) == FUNCTION_DECL \
1769 || (TREE_CODE (DECL) == VAR_DECL \
1770 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1771 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1773 || (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c'))
1775 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1777 /* Specify the machine mode that this machine uses for the index in the
1778 tablejump instruction. For small tables, an element consists of a
1779 ia-relative branch and its delay slot. When -mbig-switch is specified,
1780 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1781 for both 32 and 64-bit pic code. */
1782 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1784 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1785 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1787 /* Define this as 1 if `char' should by default be signed; else as 0. */
1788 #define DEFAULT_SIGNED_CHAR 1
1790 /* Max number of bytes we can move from memory to memory
1791 in one reasonably fast instruction. */
1794 /* Higher than the default as we prefer to use simple move insns
1795 (better scheduling and delay slot filling) and because our
1796 built-in block move is really a 2X unrolled loop.
1798 Believe it or not, this has to be big enough to allow for copying all
1799 arguments passed in registers to avoid infinite recursion during argument
1800 setup for a function call. Why? Consider how we copy the stack slots
1801 reserved for parameters when they may be trashed by a call. */
1802 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1804 /* Define if operations between registers always perform the operation
1805 on the full register even if a narrower mode is specified. */
1806 #define WORD_REGISTER_OPERATIONS
1808 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1809 will either zero-extend or sign-extend. The value of this macro should
1810 be the code that says which one of the two operations is implicitly
1811 done, UNKNOWN if none. */
1812 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1814 /* Nonzero if access to memory by bytes is slow and undesirable. */
1815 #define SLOW_BYTE_ACCESS 1
1817 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1818 is done just by pretending it is already truncated. */
1819 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1821 /* Specify the machine mode that pointers have.
1822 After generation of rtl, the compiler makes no further distinction
1823 between pointers and any other objects of this machine mode. */
1824 #define Pmode word_mode
1826 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1827 return the mode to be used for the comparison. For floating-point, CCFPmode
1828 should be used. CC_NOOVmode should be used when the first operand is a
1829 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1831 #define SELECT_CC_MODE(OP,X,Y) \
1832 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1834 /* A function address in a call instruction
1835 is a byte address (for indexing purposes)
1836 so give the MEM rtx a byte's mode. */
1837 #define FUNCTION_MODE SImode
1839 /* Define this if addresses of constant functions
1840 shouldn't be put through pseudo regs where they can be cse'd.
1841 Desirable on machines where ordinary constants are expensive
1842 but a CALL with constant address is cheap. */
1843 #define NO_FUNCTION_CSE
1845 /* Define this to be nonzero if shift instructions ignore all but the low-order
1847 #define SHIFT_COUNT_TRUNCATED 1
1849 /* Compute extra cost of moving data between one register class
1852 Make moves from SAR so expensive they should never happen. We used to
1853 have 0xffff here, but that generates overflow in rare cases.
1855 Copies involving a FP register and a non-FP register are relatively
1856 expensive because they must go through memory.
1858 Other copies are reasonably cheap. */
1859 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1860 (CLASS1 == SHIFT_REGS ? 0x100 \
1861 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1862 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1865 /* Adjust the cost of branches. */
1866 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1868 /* Handling the special cases is going to get too complicated for a macro,
1869 just call `pa_adjust_insn_length' to do the real work. */
1870 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1871 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1873 /* Millicode insns are actually function calls with some special
1874 constraints on arguments and register usage.
1876 Millicode calls always expect their arguments in the integer argument
1877 registers, and always return their result in %r29 (ret1). They
1878 are expected to clobber their arguments, %r1, %r29, and the return
1879 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1881 This macro tells reorg that the references to arguments and
1882 millicode calls do not appear to happen until after the millicode call.
1883 This allows reorg to put insns which set the argument registers into the
1884 delay slot of the millicode call -- thus they act more like traditional
1887 Note we cannot consider side effects of the insn to be delayed because
1888 the branch and link insn will clobber the return pointer. If we happened
1889 to use the return pointer in the delay slot of the call, then we lose.
1891 get_attr_type will try to recognize the given insn, so make sure to
1892 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1894 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1897 /* Control the assembler format that we output. */
1899 /* A C string constant describing how to begin a comment in the target
1900 assembler language. The compiler assumes that the comment will end at
1901 the end of the line. */
1903 #define ASM_COMMENT_START ";"
1905 /* Output to assembler file text saying following lines
1906 may contain character constants, extra white space, comments, etc. */
1908 #define ASM_APP_ON ""
1910 /* Output to assembler file text saying following lines
1911 no longer contain unusual constructs. */
1913 #define ASM_APP_OFF ""
1915 /* This is how to output the definition of a user-level label named NAME,
1916 such as the label on a static function or variable NAME. */
1918 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1919 do { assemble_name (FILE, NAME); \
1920 fputc ('\n', FILE); } while (0)
1922 /* This is how to output a reference to a user-level label named NAME.
1923 `assemble_name' uses this. */
1925 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1927 const char *xname = (NAME); \
1928 if (FUNCTION_NAME_P (NAME)) \
1930 if (xname[0] == '*') \
1933 fputs (user_label_prefix, FILE); \
1934 fputs (xname, FILE); \
1937 /* This is how to store into the string LABEL
1938 the symbol_ref name of an internal numbered label where
1939 PREFIX is the class of label and NUM is the number within the class.
1940 This is suitable for output with `assemble_name'. */
1942 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1943 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1945 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1947 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1948 output_ascii ((FILE), (P), (SIZE))
1950 /* Jump tables are always placed in the text section. Technically, it
1951 is possible to put them in the readonly data section when -mbig-switch
1952 is specified. This has the benefit of getting the table out of .text
1953 and reducing branch lengths as a result. The downside is that an
1954 additional insn (addil) is needed to access the table when generating
1955 PIC code. The address difference table also has to use 32-bit
1956 pc-relative relocations. Currently, GAS does not support these
1957 relocations, although it is easily modified to do this operation.
1958 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1959 when using ELF GAS. A simple difference can be used when using
1960 SOM GAS or the HP assembler. The final downside is GDB complains
1961 about the nesting of the label for the table when debugging. */
1963 #define JUMP_TABLES_IN_TEXT_SECTION 1
1965 /* This is how to output an element of a case-vector that is absolute. */
1967 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1968 if (TARGET_BIG_SWITCH) \
1969 fprintf (FILE, "\t.word L$%04d\n", VALUE); \
1971 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1973 /* This is how to output an element of a case-vector that is relative.
1974 Since we always place jump tables in the text section, the difference
1975 is absolute and requires no relocation. */
1977 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1978 if (TARGET_BIG_SWITCH) \
1979 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
1981 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1983 /* This is how to output an assembler line that says to advance the
1984 location counter to a multiple of 2**LOG bytes. */
1986 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1987 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1989 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1990 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1991 (unsigned HOST_WIDE_INT)(SIZE))
1993 /* This says how to output an assembler line to define an uninitialized
1994 global variable with size SIZE (in bytes) and alignment ALIGN (in bits).
1995 This macro exists to properly support languages like C++ which do not
1996 have common data. */
1998 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1999 pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN)
2001 /* This says how to output an assembler line to define a global common symbol
2002 with size SIZE (in bytes) and alignment ALIGN (in bits). */
2004 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
2005 pa_asm_output_aligned_common (FILE, NAME, SIZE, ALIGN)
2007 /* This says how to output an assembler line to define a local common symbol
2008 with size SIZE (in bytes) and alignment ALIGN (in bits). This macro
2009 controls how the assembler definitions of uninitialized static variables
2012 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
2013 pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
2016 #define ASM_PN_FORMAT "%s___%lu"
2018 /* All HP assemblers use "!" to separate logical lines. */
2019 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
2021 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2022 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
2024 /* Print operand X (an rtx) in assembler syntax to file FILE.
2025 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2026 For `%' followed by punctuation, CODE is the punctuation and X is null.
2028 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
2029 and an immediate zero should be represented as `r0'.
2031 Several % codes are defined:
2033 C compare conditions
2034 N extract conditions
2035 M modifier to handle preincrement addressing for memory refs.
2036 F modifier to handle preincrement addressing for fp memory refs */
2038 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2041 /* Print a memory address as an operand to reference that memory location. */
2043 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2044 { register rtx addr = ADDR; \
2045 register rtx base; \
2047 switch (GET_CODE (addr)) \
2050 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
2053 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2054 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); \
2055 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2056 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); \
2059 fprintf (FILE, "%d(%s)", offset, reg_names [REGNO (base)]); \
2062 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
2063 fputs ("R'", FILE); \
2064 else if (flag_pic == 0) \
2065 fputs ("RR'", FILE); \
2067 fputs ("RT'", FILE); \
2068 output_global_address (FILE, XEXP (addr, 1), 0); \
2069 fputs ("(", FILE); \
2070 output_operand (XEXP (addr, 0), 0); \
2071 fputs (")", FILE); \
2074 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
2077 output_addr_const (FILE, addr); \
2081 /* Find the return address associated with the frame given by
2083 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
2084 (return_addr_rtx (COUNT, FRAMEADDR))
2086 /* Used to mask out junk bits from the return address, such as
2087 processor state, interrupt status, condition codes and the like. */
2088 #define MASK_RETURN_ADDR \
2089 /* The privilege level is in the two low order bits, mask em out \
2090 of the return address. */ \
2093 /* The number of Pmode words for the setjmp buffer. */
2094 #define JMP_BUF_SIZE 50
2096 #define PREDICATE_CODES \
2097 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2098 {"call_operand_address", {LABEL_REF, SYMBOL_REF, CONST_INT, \
2099 CONST_DOUBLE, CONST, HIGH}}, \
2100 {"indexed_memory_operand", {SUBREG, MEM}}, \
2101 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2102 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2103 {"reg_before_reload_operand", {REG, MEM}}, \
2104 {"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, MEM, CONST_INT, \
2106 {"move_dest_operand", {SUBREG, REG, MEM}}, \
2107 {"move_src_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2108 {"prefetch_operand", {MEM}}, \
2109 {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
2110 {"pic_label_operand", {LABEL_REF, CONST}}, \
2111 {"fp_reg_operand", {REG}}, \
2112 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2113 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2114 {"pre_cint_operand", {CONST_INT}}, \
2115 {"post_cint_operand", {CONST_INT}}, \
2116 {"arith_double_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2117 {"ireg_or_int5_operand", {CONST_INT, REG}}, \
2118 {"int5_operand", {CONST_INT}}, \
2119 {"uint5_operand", {CONST_INT}}, \
2120 {"int11_operand", {CONST_INT}}, \
2121 {"uint32_operand", {CONST_INT, \
2122 HOST_BITS_PER_WIDE_INT > 32 ? 0 : CONST_DOUBLE}}, \
2123 {"arith5_operand", {SUBREG, REG, CONST_INT}}, \
2124 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2125 {"ior_operand", {CONST_INT}}, \
2126 {"lhs_lshift_cint_operand", {CONST_INT}}, \
2127 {"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \
2128 {"arith32_operand", {SUBREG, REG, CONST_INT}}, \
2129 {"pc_or_label_operand", {PC, LABEL_REF}}, \
2130 {"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \
2131 {"shadd_operand", {CONST_INT}}, \
2132 {"div_operand", {REG, CONST_INT}}, \
2133 {"ireg_operand", {REG}}, \
2134 {"cmpib_comparison_operator", {EQ, NE, LT, LE, LEU, \
2136 {"movb_comparison_operator", {EQ, NE, LT, GE}},
2138 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
2139 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
2140 "__canonicalize_funcptr_for_compare"
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