1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "integrate.h"
52 #include "target-def.h"
54 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
56 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
57 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
60 hppa_use_dfa_pipeline_interface ()
65 /* Return nonzero if there is a bypass for the output of
66 OUT_INSN and the fp store IN_INSN. */
68 hppa_fpstore_bypass_p (out_insn, in_insn)
69 rtx out_insn, in_insn;
71 enum machine_mode store_mode;
72 enum machine_mode other_mode;
75 if (recog_memoized (in_insn) < 0
76 || get_attr_type (in_insn) != TYPE_FPSTORE
77 || recog_memoized (out_insn) < 0)
80 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
82 set = single_set (out_insn);
86 other_mode = GET_MODE (SET_SRC (set));
88 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
92 #ifndef DO_FRAME_NOTES
93 #ifdef INCOMING_RETURN_ADDR_RTX
94 #define DO_FRAME_NOTES 1
96 #define DO_FRAME_NOTES 0
100 static int hppa_address_cost PARAMS ((rtx));
101 static bool hppa_rtx_costs PARAMS ((rtx, int, int, int *));
102 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
103 static void pa_combine_instructions PARAMS ((rtx));
104 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
105 static int forward_branch_p PARAMS ((rtx));
106 static int shadd_constant_p PARAMS ((int));
107 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
108 static int compute_movstrsi_length PARAMS ((rtx));
109 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
110 static void remove_useless_addtr_insns PARAMS ((rtx, int));
111 static void store_reg PARAMS ((int, int, int));
112 static void store_reg_modify PARAMS ((int, int, int));
113 static void load_reg PARAMS ((int, int, int));
114 static void set_reg_plus_d PARAMS ((int, int, int, int));
115 static void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
116 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
117 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
118 static int pa_adjust_priority PARAMS ((rtx, int));
119 static int pa_issue_rate PARAMS ((void));
120 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
122 static void pa_encode_section_info PARAMS ((tree, int));
123 static const char *pa_strip_name_encoding PARAMS ((const char *));
124 static bool pa_function_ok_for_sibcall PARAMS ((tree, tree));
125 static void pa_globalize_label PARAMS ((FILE *, const char *))
127 static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
128 HOST_WIDE_INT, tree));
129 #if !defined(USE_COLLECT2)
130 static void pa_asm_out_constructor PARAMS ((rtx, int));
131 static void pa_asm_out_destructor PARAMS ((rtx, int));
133 static void pa_init_builtins PARAMS ((void));
134 static void copy_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
135 static int length_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
136 static struct deferred_plabel *get_plabel PARAMS ((const char *))
139 /* Save the operands last given to a compare for use when we
140 generate a scc or bcc insn. */
141 rtx hppa_compare_op0, hppa_compare_op1;
142 enum cmp_type hppa_branch_type;
144 /* Which cpu we are scheduling for. */
145 enum processor_type pa_cpu;
147 /* String to hold which cpu we are scheduling for. */
148 const char *pa_cpu_string;
150 /* Which architecture we are generating code for. */
151 enum architecture_type pa_arch;
153 /* String to hold which architecture we are generating code for. */
154 const char *pa_arch_string;
156 /* Counts for the number of callee-saved general and floating point
157 registers which were saved by the current function's prologue. */
158 static int gr_saved, fr_saved;
160 static rtx find_addr_reg PARAMS ((rtx));
162 /* Keep track of the number of bytes we have output in the CODE subspaces
163 during this compilation so we'll know when to emit inline long-calls. */
164 unsigned long total_code_bytes;
166 /* Variables to handle plabels that we discover are necessary at assembly
167 output time. They are output after the current function. */
168 struct deferred_plabel GTY(())
173 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
175 static size_t n_deferred_plabels = 0;
177 /* Initialize the GCC target structure. */
179 #undef TARGET_ASM_ALIGNED_HI_OP
180 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
181 #undef TARGET_ASM_ALIGNED_SI_OP
182 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
183 #undef TARGET_ASM_ALIGNED_DI_OP
184 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
185 #undef TARGET_ASM_UNALIGNED_HI_OP
186 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
187 #undef TARGET_ASM_UNALIGNED_SI_OP
188 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
189 #undef TARGET_ASM_UNALIGNED_DI_OP
190 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
191 #undef TARGET_ASM_INTEGER
192 #define TARGET_ASM_INTEGER pa_assemble_integer
194 #undef TARGET_ASM_FUNCTION_PROLOGUE
195 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
196 #undef TARGET_ASM_FUNCTION_EPILOGUE
197 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
199 #undef TARGET_SCHED_ADJUST_COST
200 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
201 #undef TARGET_SCHED_ADJUST_PRIORITY
202 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
203 #undef TARGET_SCHED_ISSUE_RATE
204 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
206 #undef TARGET_ENCODE_SECTION_INFO
207 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
208 #undef TARGET_STRIP_NAME_ENCODING
209 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
211 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
212 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
214 #undef TARGET_ASM_OUTPUT_MI_THUNK
215 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
216 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
217 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
219 #if !defined(USE_COLLECT2)
220 #undef TARGET_ASM_CONSTRUCTOR
221 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
222 #undef TARGET_ASM_DESTRUCTOR
223 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
226 #undef TARGET_INIT_BUILTINS
227 #define TARGET_INIT_BUILTINS pa_init_builtins
229 #undef TARGET_RTX_COSTS
230 #define TARGET_RTX_COSTS hppa_rtx_costs
231 #undef TARGET_ADDRESS_COST
232 #define TARGET_ADDRESS_COST hppa_address_cost
234 struct gcc_target targetm = TARGET_INITIALIZER;
239 if (pa_cpu_string == NULL)
240 pa_cpu_string = TARGET_SCHED_DEFAULT;
242 if (! strcmp (pa_cpu_string, "8000"))
244 pa_cpu_string = "8000";
245 pa_cpu = PROCESSOR_8000;
247 else if (! strcmp (pa_cpu_string, "7100"))
249 pa_cpu_string = "7100";
250 pa_cpu = PROCESSOR_7100;
252 else if (! strcmp (pa_cpu_string, "700"))
254 pa_cpu_string = "700";
255 pa_cpu = PROCESSOR_700;
257 else if (! strcmp (pa_cpu_string, "7100LC"))
259 pa_cpu_string = "7100LC";
260 pa_cpu = PROCESSOR_7100LC;
262 else if (! strcmp (pa_cpu_string, "7200"))
264 pa_cpu_string = "7200";
265 pa_cpu = PROCESSOR_7200;
267 else if (! strcmp (pa_cpu_string, "7300"))
269 pa_cpu_string = "7300";
270 pa_cpu = PROCESSOR_7300;
274 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
277 /* Set the instruction set architecture. */
278 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
280 pa_arch_string = "1.0";
281 pa_arch = ARCHITECTURE_10;
282 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
284 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
286 pa_arch_string = "1.1";
287 pa_arch = ARCHITECTURE_11;
288 target_flags &= ~MASK_PA_20;
289 target_flags |= MASK_PA_11;
291 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
293 pa_arch_string = "2.0";
294 pa_arch = ARCHITECTURE_20;
295 target_flags |= MASK_PA_11 | MASK_PA_20;
297 else if (pa_arch_string)
299 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
302 /* Unconditional branches in the delay slot are not compatible with dwarf2
303 call frame information. There is no benefit in using this optimization
304 on PA8000 and later processors. */
305 if (pa_cpu >= PROCESSOR_8000
306 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
307 || flag_unwind_tables)
308 target_flags &= ~MASK_JUMP_IN_DELAY;
310 if (flag_pic && TARGET_PORTABLE_RUNTIME)
312 warning ("PIC code generation is not supported in the portable runtime model\n");
315 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
317 warning ("PIC code generation is not compatible with fast indirect calls\n");
320 if (! TARGET_GAS && write_symbols != NO_DEBUG)
322 warning ("-g is only supported when using GAS on this processor,");
323 warning ("-g option disabled");
324 write_symbols = NO_DEBUG;
327 /* We only support the "big PIC" model now. And we always generate PIC
328 code when in 64bit mode. */
329 if (flag_pic == 1 || TARGET_64BIT)
332 /* We can't guarantee that .dword is available for 32-bit targets. */
333 if (UNITS_PER_WORD == 4)
334 targetm.asm_out.aligned_op.di = NULL;
336 /* The unaligned ops are only available when using GAS. */
339 targetm.asm_out.unaligned_op.hi = NULL;
340 targetm.asm_out.unaligned_op.si = NULL;
341 targetm.asm_out.unaligned_op.di = NULL;
348 #ifdef DONT_HAVE_FPUTC_UNLOCKED
349 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
353 /* Return nonzero only if OP is a register of mode MODE,
356 reg_or_0_operand (op, mode)
358 enum machine_mode mode;
360 return (op == CONST0_RTX (mode) || register_operand (op, mode));
363 /* Return nonzero if OP is suitable for use in a call to a named
366 For 2.5 try to eliminate either call_operand_address or
367 function_label_operand, they perform very similar functions. */
369 call_operand_address (op, mode)
371 enum machine_mode mode ATTRIBUTE_UNUSED;
373 return (GET_MODE (op) == word_mode
374 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
377 /* Return 1 if X contains a symbolic expression. We know these
378 expressions will have one of a few well defined forms, so
379 we need only check those forms. */
381 symbolic_expression_p (x)
385 /* Strip off any HIGH. */
386 if (GET_CODE (x) == HIGH)
389 return (symbolic_operand (x, VOIDmode));
393 symbolic_operand (op, mode)
395 enum machine_mode mode ATTRIBUTE_UNUSED;
397 switch (GET_CODE (op))
404 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
405 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
406 && GET_CODE (XEXP (op, 1)) == CONST_INT);
412 /* Return truth value of statement that OP is a symbolic memory
413 operand of mode MODE. */
416 symbolic_memory_operand (op, mode)
418 enum machine_mode mode ATTRIBUTE_UNUSED;
420 if (GET_CODE (op) == SUBREG)
421 op = SUBREG_REG (op);
422 if (GET_CODE (op) != MEM)
425 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
426 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
429 /* Return 1 if the operand is either a register or a memory operand that is
433 reg_or_nonsymb_mem_operand (op, mode)
435 enum machine_mode mode;
437 if (register_operand (op, mode))
440 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
446 /* Return 1 if the operand is either a register, zero, or a memory operand
447 that is not symbolic. */
450 reg_or_0_or_nonsymb_mem_operand (op, mode)
452 enum machine_mode mode;
454 if (register_operand (op, mode))
457 if (op == CONST0_RTX (mode))
460 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
466 /* Return 1 if the operand is a register operand or a non-symbolic memory
467 operand after reload. This predicate is used for branch patterns that
468 internally handle register reloading. We need to accept non-symbolic
469 memory operands after reload to ensure that the pattern is still valid
470 if reload didn't find a hard register for the operand. */
473 reg_before_reload_operand (op, mode)
475 enum machine_mode mode;
477 /* Don't accept a SUBREG since it will need a reload. */
478 if (GET_CODE (op) == SUBREG)
481 if (register_operand (op, mode))
485 && memory_operand (op, mode)
486 && ! symbolic_memory_operand (op, mode))
492 /* Accept any constant that can be moved in one instruction into a
495 cint_ok_for_move (intval)
496 HOST_WIDE_INT intval;
498 /* OK if ldo, ldil, or zdepi, can be used. */
499 return (CONST_OK_FOR_LETTER_P (intval, 'J')
500 || CONST_OK_FOR_LETTER_P (intval, 'N')
501 || CONST_OK_FOR_LETTER_P (intval, 'K'));
504 /* Accept anything that can be moved in one instruction into a general
507 move_operand (op, mode)
509 enum machine_mode mode;
511 if (register_operand (op, mode))
514 if (GET_CODE (op) == CONSTANT_P_RTX)
517 if (GET_CODE (op) == CONST_INT)
518 return cint_ok_for_move (INTVAL (op));
520 if (GET_CODE (op) == SUBREG)
521 op = SUBREG_REG (op);
522 if (GET_CODE (op) != MEM)
527 /* We consider a LO_SUM DLT reference a move_operand now since it has
528 been merged into the normal movsi/movdi patterns. */
529 if (GET_CODE (op) == LO_SUM
530 && GET_CODE (XEXP (op, 0)) == REG
531 && REG_OK_FOR_BASE_P (XEXP (op, 0))
532 && GET_CODE (XEXP (op, 1)) == UNSPEC
533 && GET_MODE (op) == Pmode)
536 /* Since move_operand is only used for source operands, we can always
537 allow scaled indexing! */
538 if (! TARGET_DISABLE_INDEXING
539 && GET_CODE (op) == PLUS
540 && ((GET_CODE (XEXP (op, 0)) == MULT
541 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
542 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
543 && INTVAL (XEXP (XEXP (op, 0), 1))
544 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
545 && GET_CODE (XEXP (op, 1)) == REG)
546 || (GET_CODE (XEXP (op, 1)) == MULT
547 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
548 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
549 && INTVAL (XEXP (XEXP (op, 1), 1))
550 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
551 && GET_CODE (XEXP (op, 0)) == REG)))
554 return memory_address_p (mode, op);
557 /* Accept REG and any CONST_INT that can be moved in one instruction into a
560 reg_or_cint_move_operand (op, mode)
562 enum machine_mode mode;
564 if (register_operand (op, mode))
567 if (GET_CODE (op) == CONST_INT)
568 return cint_ok_for_move (INTVAL (op));
574 pic_label_operand (op, mode)
576 enum machine_mode mode ATTRIBUTE_UNUSED;
581 switch (GET_CODE (op))
587 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
588 && GET_CODE (XEXP (op, 1)) == CONST_INT);
595 fp_reg_operand (op, mode)
597 enum machine_mode mode ATTRIBUTE_UNUSED;
599 return reg_renumber && FP_REG_P (op);
604 /* Return truth value of whether OP can be used as an operand in a
605 three operand arithmetic insn that accepts registers of mode MODE
606 or 14-bit signed integers. */
608 arith_operand (op, mode)
610 enum machine_mode mode;
612 return (register_operand (op, mode)
613 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
616 /* Return truth value of whether OP can be used as an operand in a
617 three operand arithmetic insn that accepts registers of mode MODE
618 or 11-bit signed integers. */
620 arith11_operand (op, mode)
622 enum machine_mode mode;
624 return (register_operand (op, mode)
625 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
628 /* Return truth value of whether OP can be used as an operand in a
631 adddi3_operand (op, mode)
633 enum machine_mode mode;
635 return (register_operand (op, mode)
636 || (GET_CODE (op) == CONST_INT
637 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
640 /* A constant integer suitable for use in a PRE_MODIFY memory
643 pre_cint_operand (op, mode)
645 enum machine_mode mode ATTRIBUTE_UNUSED;
647 return (GET_CODE (op) == CONST_INT
648 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
651 /* A constant integer suitable for use in a POST_MODIFY memory
654 post_cint_operand (op, mode)
656 enum machine_mode mode ATTRIBUTE_UNUSED;
658 return (GET_CODE (op) == CONST_INT
659 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
663 arith_double_operand (op, mode)
665 enum machine_mode mode;
667 return (register_operand (op, mode)
668 || (GET_CODE (op) == CONST_DOUBLE
669 && GET_MODE (op) == mode
670 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
671 && ((CONST_DOUBLE_HIGH (op) >= 0)
672 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
675 /* Return truth value of whether OP is an integer which fits the
676 range constraining immediate operands in three-address insns, or
677 is an integer register. */
680 ireg_or_int5_operand (op, mode)
682 enum machine_mode mode ATTRIBUTE_UNUSED;
684 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
685 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
688 /* Return nonzero if OP is an integer register, else return zero. */
690 ireg_operand (op, mode)
692 enum machine_mode mode ATTRIBUTE_UNUSED;
694 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
697 /* Return truth value of whether OP is an integer which fits the
698 range constraining immediate operands in three-address insns. */
701 int5_operand (op, mode)
703 enum machine_mode mode ATTRIBUTE_UNUSED;
705 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
709 uint5_operand (op, mode)
711 enum machine_mode mode ATTRIBUTE_UNUSED;
713 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
717 int11_operand (op, mode)
719 enum machine_mode mode ATTRIBUTE_UNUSED;
721 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
725 uint32_operand (op, mode)
727 enum machine_mode mode ATTRIBUTE_UNUSED;
729 #if HOST_BITS_PER_WIDE_INT > 32
730 /* All allowed constants will fit a CONST_INT. */
731 return (GET_CODE (op) == CONST_INT
732 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
734 return (GET_CODE (op) == CONST_INT
735 || (GET_CODE (op) == CONST_DOUBLE
736 && CONST_DOUBLE_HIGH (op) == 0));
741 arith5_operand (op, mode)
743 enum machine_mode mode;
745 return register_operand (op, mode) || int5_operand (op, mode);
748 /* True iff zdepi can be used to generate this CONST_INT.
749 zdepi first sign extends a 5 bit signed number to a given field
750 length, then places this field anywhere in a zero. */
753 unsigned HOST_WIDE_INT x;
755 unsigned HOST_WIDE_INT lsb_mask, t;
757 /* This might not be obvious, but it's at least fast.
758 This function is critical; we don't have the time loops would take. */
760 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
761 /* Return true iff t is a power of two. */
762 return ((t & (t - 1)) == 0);
765 /* True iff depi or extru can be used to compute (reg & mask).
766 Accept bit pattern like these:
772 unsigned HOST_WIDE_INT mask;
775 mask += mask & -mask;
776 return (mask & (mask - 1)) == 0;
779 /* True iff depi or extru can be used to compute (reg & OP). */
781 and_operand (op, mode)
783 enum machine_mode mode;
785 return (register_operand (op, mode)
786 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
789 /* True iff depi can be used to compute (reg | MASK). */
792 unsigned HOST_WIDE_INT mask;
794 mask += mask & -mask;
795 return (mask & (mask - 1)) == 0;
798 /* True iff depi can be used to compute (reg | OP). */
800 ior_operand (op, mode)
802 enum machine_mode mode ATTRIBUTE_UNUSED;
804 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
808 lhs_lshift_operand (op, mode)
810 enum machine_mode mode;
812 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
815 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
816 Such values can be the left hand side x in (x << r), using the zvdepi
819 lhs_lshift_cint_operand (op, mode)
821 enum machine_mode mode ATTRIBUTE_UNUSED;
823 unsigned HOST_WIDE_INT x;
824 if (GET_CODE (op) != CONST_INT)
826 x = INTVAL (op) >> 4;
827 return (x & (x + 1)) == 0;
831 arith32_operand (op, mode)
833 enum machine_mode mode;
835 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
839 pc_or_label_operand (op, mode)
841 enum machine_mode mode ATTRIBUTE_UNUSED;
843 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
846 /* Legitimize PIC addresses. If the address is already
847 position-independent, we return ORIG. Newly generated
848 position-independent addresses go to REG. If we need more
849 than one register, we lose. */
852 legitimize_pic_address (orig, mode, reg)
854 enum machine_mode mode;
858 /* Labels need special handling. */
859 if (pic_label_operand (orig, mode))
861 /* We do not want to go through the movXX expanders here since that
862 would create recursion.
864 Nor do we really want to call a generator for a named pattern
865 since that requires multiple patterns if we want to support
868 So instead we just emit the raw set, which avoids the movXX
869 expanders completely. */
870 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
871 current_function_uses_pic_offset_table = 1;
874 if (GET_CODE (orig) == SYMBOL_REF)
880 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
881 gen_rtx_HIGH (word_mode, orig)));
883 = gen_rtx_MEM (Pmode,
884 gen_rtx_LO_SUM (Pmode, reg,
885 gen_rtx_UNSPEC (Pmode,
889 current_function_uses_pic_offset_table = 1;
890 RTX_UNCHANGING_P (pic_ref) = 1;
891 emit_move_insn (reg, pic_ref);
894 else if (GET_CODE (orig) == CONST)
898 if (GET_CODE (XEXP (orig, 0)) == PLUS
899 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
905 if (GET_CODE (XEXP (orig, 0)) == PLUS)
907 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
908 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
909 base == reg ? 0 : reg);
912 if (GET_CODE (orig) == CONST_INT)
914 if (INT_14_BITS (orig))
915 return plus_constant (base, INTVAL (orig));
916 orig = force_reg (Pmode, orig);
918 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
919 /* Likewise, should we set special REG_NOTEs here? */
924 /* Try machine-dependent ways of modifying an illegitimate address
925 to be legitimate. If we find one, return the new, valid address.
926 This macro is used in only one place: `memory_address' in explow.c.
928 OLDX is the address as it was before break_out_memory_refs was called.
929 In some cases it is useful to look at this to decide what needs to be done.
931 MODE and WIN are passed so that this macro can use
932 GO_IF_LEGITIMATE_ADDRESS.
934 It is always safe for this macro to do nothing. It exists to recognize
935 opportunities to optimize the output.
937 For the PA, transform:
939 memory(X + <large int>)
943 if (<large int> & mask) >= 16
944 Y = (<large int> & ~mask) + mask + 1 Round up.
946 Y = (<large int> & ~mask) Round down.
948 memory (Z + (<large int> - Y));
950 This is for CSE to find several similar references, and only use one Z.
952 X can either be a SYMBOL_REF or REG, but because combine can not
953 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
954 D will not fit in 14 bits.
956 MODE_FLOAT references allow displacements which fit in 5 bits, so use
959 MODE_INT references allow displacements which fit in 14 bits, so use
962 This relies on the fact that most mode MODE_FLOAT references will use FP
963 registers and most mode MODE_INT references will use integer registers.
964 (In the rare case of an FP register used in an integer MODE, we depend
965 on secondary reloads to clean things up.)
968 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
969 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
970 addressing modes to be used).
972 Put X and Z into registers. Then put the entire expression into
976 hppa_legitimize_address (x, oldx, mode)
977 rtx x, oldx ATTRIBUTE_UNUSED;
978 enum machine_mode mode;
983 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
985 /* Strip off CONST. */
986 if (GET_CODE (x) == CONST)
989 /* Special case. Get the SYMBOL_REF into a register and use indexing.
990 That should always be safe. */
991 if (GET_CODE (x) == PLUS
992 && GET_CODE (XEXP (x, 0)) == REG
993 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
995 rtx reg = force_reg (Pmode, XEXP (x, 1));
996 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
999 /* Note we must reject symbols which represent function addresses
1000 since the assembler/linker can't handle arithmetic on plabels. */
1001 if (GET_CODE (x) == PLUS
1002 && GET_CODE (XEXP (x, 1)) == CONST_INT
1003 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1004 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1005 || GET_CODE (XEXP (x, 0)) == REG))
1007 rtx int_part, ptr_reg;
1009 int offset = INTVAL (XEXP (x, 1));
1012 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1013 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1015 /* Choose which way to round the offset. Round up if we
1016 are >= halfway to the next boundary. */
1017 if ((offset & mask) >= ((mask + 1) / 2))
1018 newoffset = (offset & ~ mask) + mask + 1;
1020 newoffset = (offset & ~ mask);
1022 /* If the newoffset will not fit in 14 bits (ldo), then
1023 handling this would take 4 or 5 instructions (2 to load
1024 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1025 add the new offset and the SYMBOL_REF.) Combine can
1026 not handle 4->2 or 5->2 combinations, so do not create
1028 if (! VAL_14_BITS_P (newoffset)
1029 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1031 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1034 gen_rtx_HIGH (Pmode, const_part));
1037 gen_rtx_LO_SUM (Pmode,
1038 tmp_reg, const_part));
1042 if (! VAL_14_BITS_P (newoffset))
1043 int_part = force_reg (Pmode, GEN_INT (newoffset));
1045 int_part = GEN_INT (newoffset);
1047 ptr_reg = force_reg (Pmode,
1048 gen_rtx_PLUS (Pmode,
1049 force_reg (Pmode, XEXP (x, 0)),
1052 return plus_constant (ptr_reg, offset - newoffset);
1055 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1057 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1058 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1059 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1060 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1061 || GET_CODE (XEXP (x, 1)) == SUBREG)
1062 && GET_CODE (XEXP (x, 1)) != CONST)
1064 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1068 if (GET_CODE (reg1) != REG)
1069 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1071 reg2 = XEXP (XEXP (x, 0), 0);
1072 if (GET_CODE (reg2) != REG)
1073 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1075 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1076 gen_rtx_MULT (Pmode,
1082 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1084 Only do so for floating point modes since this is more speculative
1085 and we lose if it's an integer store. */
1086 if (GET_CODE (x) == PLUS
1087 && GET_CODE (XEXP (x, 0)) == PLUS
1088 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1089 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1090 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1091 && (mode == SFmode || mode == DFmode))
1094 /* First, try and figure out what to use as a base register. */
1095 rtx reg1, reg2, base, idx, orig_base;
1097 reg1 = XEXP (XEXP (x, 0), 1);
1102 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1103 then emit_move_sequence will turn on REG_POINTER so we'll know
1104 it's a base register below. */
1105 if (GET_CODE (reg1) != REG)
1106 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1108 if (GET_CODE (reg2) != REG)
1109 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1111 /* Figure out what the base and index are. */
1113 if (GET_CODE (reg1) == REG
1114 && REG_POINTER (reg1))
1117 orig_base = XEXP (XEXP (x, 0), 1);
1118 idx = gen_rtx_PLUS (Pmode,
1119 gen_rtx_MULT (Pmode,
1120 XEXP (XEXP (XEXP (x, 0), 0), 0),
1121 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1124 else if (GET_CODE (reg2) == REG
1125 && REG_POINTER (reg2))
1128 orig_base = XEXP (x, 1);
1135 /* If the index adds a large constant, try to scale the
1136 constant so that it can be loaded with only one insn. */
1137 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1138 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1139 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1140 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1142 /* Divide the CONST_INT by the scale factor, then add it to A. */
1143 int val = INTVAL (XEXP (idx, 1));
1145 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1146 reg1 = XEXP (XEXP (idx, 0), 0);
1147 if (GET_CODE (reg1) != REG)
1148 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1150 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1152 /* We can now generate a simple scaled indexed address. */
1155 (Pmode, gen_rtx_PLUS (Pmode,
1156 gen_rtx_MULT (Pmode, reg1,
1157 XEXP (XEXP (idx, 0), 1)),
1161 /* If B + C is still a valid base register, then add them. */
1162 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1163 && INTVAL (XEXP (idx, 1)) <= 4096
1164 && INTVAL (XEXP (idx, 1)) >= -4096)
1166 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1169 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1171 reg2 = XEXP (XEXP (idx, 0), 0);
1172 if (GET_CODE (reg2) != CONST_INT)
1173 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1175 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1176 gen_rtx_MULT (Pmode,
1182 /* Get the index into a register, then add the base + index and
1183 return a register holding the result. */
1185 /* First get A into a register. */
1186 reg1 = XEXP (XEXP (idx, 0), 0);
1187 if (GET_CODE (reg1) != REG)
1188 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1190 /* And get B into a register. */
1191 reg2 = XEXP (idx, 1);
1192 if (GET_CODE (reg2) != REG)
1193 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1195 reg1 = force_reg (Pmode,
1196 gen_rtx_PLUS (Pmode,
1197 gen_rtx_MULT (Pmode, reg1,
1198 XEXP (XEXP (idx, 0), 1)),
1201 /* Add the result to our base register and return. */
1202 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1206 /* Uh-oh. We might have an address for x[n-100000]. This needs
1207 special handling to avoid creating an indexed memory address
1208 with x-100000 as the base.
1210 If the constant part is small enough, then it's still safe because
1211 there is a guard page at the beginning and end of the data segment.
1213 Scaled references are common enough that we want to try and rearrange the
1214 terms so that we can use indexing for these addresses too. Only
1215 do the optimization for floatint point modes. */
1217 if (GET_CODE (x) == PLUS
1218 && symbolic_expression_p (XEXP (x, 1)))
1220 /* Ugly. We modify things here so that the address offset specified
1221 by the index expression is computed first, then added to x to form
1222 the entire address. */
1224 rtx regx1, regx2, regy1, regy2, y;
1226 /* Strip off any CONST. */
1228 if (GET_CODE (y) == CONST)
1231 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1233 /* See if this looks like
1234 (plus (mult (reg) (shadd_const))
1235 (const (plus (symbol_ref) (const_int))))
1237 Where const_int is small. In that case the const
1238 expression is a valid pointer for indexing.
1240 If const_int is big, but can be divided evenly by shadd_const
1241 and added to (reg). This allows more scaled indexed addresses. */
1242 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1243 && GET_CODE (XEXP (x, 0)) == MULT
1244 && GET_CODE (XEXP (y, 1)) == CONST_INT
1245 && INTVAL (XEXP (y, 1)) >= -4096
1246 && INTVAL (XEXP (y, 1)) <= 4095
1247 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1248 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1250 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1254 if (GET_CODE (reg1) != REG)
1255 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1257 reg2 = XEXP (XEXP (x, 0), 0);
1258 if (GET_CODE (reg2) != REG)
1259 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1261 return force_reg (Pmode,
1262 gen_rtx_PLUS (Pmode,
1263 gen_rtx_MULT (Pmode,
1268 else if ((mode == DFmode || mode == SFmode)
1269 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1270 && GET_CODE (XEXP (x, 0)) == MULT
1271 && GET_CODE (XEXP (y, 1)) == CONST_INT
1272 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1273 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1274 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1277 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1278 / INTVAL (XEXP (XEXP (x, 0), 1))));
1279 regx2 = XEXP (XEXP (x, 0), 0);
1280 if (GET_CODE (regx2) != REG)
1281 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1282 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1286 gen_rtx_PLUS (Pmode,
1287 gen_rtx_MULT (Pmode, regx2,
1288 XEXP (XEXP (x, 0), 1)),
1289 force_reg (Pmode, XEXP (y, 0))));
1291 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1292 && INTVAL (XEXP (y, 1)) >= -4096
1293 && INTVAL (XEXP (y, 1)) <= 4095)
1295 /* This is safe because of the guard page at the
1296 beginning and end of the data space. Just
1297 return the original address. */
1302 /* Doesn't look like one we can optimize. */
1303 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1304 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1305 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1306 regx1 = force_reg (Pmode,
1307 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1309 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1317 /* For the HPPA, REG and REG+CONST is cost 0
1318 and addresses involving symbolic constants are cost 2.
1320 PIC addresses are very expensive.
1322 It is no coincidence that this has the same structure
1323 as GO_IF_LEGITIMATE_ADDRESS. */
1326 hppa_address_cost (X)
1329 switch (GET_CODE (X))
1342 /* Compute a (partial) cost for rtx X. Return true if the complete
1343 cost has been computed, and false if subexpressions should be
1344 scanned. In either case, *TOTAL contains the cost result. */
1347 hppa_rtx_costs (x, code, outer_code, total)
1349 int code, outer_code;
1355 if (INTVAL (x) == 0)
1357 else if (INT_14_BITS (x))
1374 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1375 && outer_code != SET)
1382 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1383 *total = COSTS_N_INSNS (3);
1384 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1385 *total = COSTS_N_INSNS (8);
1387 *total = COSTS_N_INSNS (20);
1391 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1393 *total = COSTS_N_INSNS (14);
1401 *total = COSTS_N_INSNS (60);
1404 case PLUS: /* this includes shNadd insns */
1406 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1407 *total = COSTS_N_INSNS (3);
1409 *total = COSTS_N_INSNS (1);
1415 *total = COSTS_N_INSNS (1);
1423 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1424 new rtx with the correct mode. */
1426 force_mode (mode, orig)
1427 enum machine_mode mode;
1430 if (mode == GET_MODE (orig))
1433 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1436 return gen_rtx_REG (mode, REGNO (orig));
1439 /* Emit insns to move operands[1] into operands[0].
1441 Return 1 if we have written out everything that needs to be done to
1442 do the move. Otherwise, return 0 and the caller will emit the move
1445 Note SCRATCH_REG may not be in the proper mode depending on how it
1446 will be used. This routine is resposible for creating a new copy
1447 of SCRATCH_REG in the proper mode. */
1450 emit_move_sequence (operands, mode, scratch_reg)
1452 enum machine_mode mode;
1455 register rtx operand0 = operands[0];
1456 register rtx operand1 = operands[1];
1460 && reload_in_progress && GET_CODE (operand0) == REG
1461 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1462 operand0 = reg_equiv_mem[REGNO (operand0)];
1463 else if (scratch_reg
1464 && reload_in_progress && GET_CODE (operand0) == SUBREG
1465 && GET_CODE (SUBREG_REG (operand0)) == REG
1466 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1468 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1469 the code which tracks sets/uses for delete_output_reload. */
1470 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1471 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1472 SUBREG_BYTE (operand0));
1473 operand0 = alter_subreg (&temp);
1477 && reload_in_progress && GET_CODE (operand1) == REG
1478 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1479 operand1 = reg_equiv_mem[REGNO (operand1)];
1480 else if (scratch_reg
1481 && reload_in_progress && GET_CODE (operand1) == SUBREG
1482 && GET_CODE (SUBREG_REG (operand1)) == REG
1483 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1485 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1486 the code which tracks sets/uses for delete_output_reload. */
1487 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1488 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1489 SUBREG_BYTE (operand1));
1490 operand1 = alter_subreg (&temp);
1493 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1494 && ((tem = find_replacement (&XEXP (operand0, 0)))
1495 != XEXP (operand0, 0)))
1496 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1497 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1498 && ((tem = find_replacement (&XEXP (operand1, 0)))
1499 != XEXP (operand1, 0)))
1500 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1502 /* Handle secondary reloads for loads/stores of FP registers from
1503 REG+D addresses where D does not fit in 5 bits, including
1504 (subreg (mem (addr))) cases. */
1505 if (fp_reg_operand (operand0, mode)
1506 && ((GET_CODE (operand1) == MEM
1507 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1508 || ((GET_CODE (operand1) == SUBREG
1509 && GET_CODE (XEXP (operand1, 0)) == MEM
1510 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1513 if (GET_CODE (operand1) == SUBREG)
1514 operand1 = XEXP (operand1, 0);
1516 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1517 it in WORD_MODE regardless of what mode it was originally given
1519 scratch_reg = force_mode (word_mode, scratch_reg);
1521 /* D might not fit in 14 bits either; for such cases load D into
1523 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1525 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1526 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1528 XEXP (XEXP (operand1, 0), 0),
1532 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1533 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1534 gen_rtx_MEM (mode, scratch_reg)));
1537 else if (fp_reg_operand (operand1, mode)
1538 && ((GET_CODE (operand0) == MEM
1539 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1540 || ((GET_CODE (operand0) == SUBREG)
1541 && GET_CODE (XEXP (operand0, 0)) == MEM
1542 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1545 if (GET_CODE (operand0) == SUBREG)
1546 operand0 = XEXP (operand0, 0);
1548 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1549 it in WORD_MODE regardless of what mode it was originally given
1551 scratch_reg = force_mode (word_mode, scratch_reg);
1553 /* D might not fit in 14 bits either; for such cases load D into
1555 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1557 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1558 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1561 XEXP (XEXP (operand0, 0),
1566 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1567 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1571 /* Handle secondary reloads for loads of FP registers from constant
1572 expressions by forcing the constant into memory.
1574 use scratch_reg to hold the address of the memory location.
1576 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1577 NO_REGS when presented with a const_int and a register class
1578 containing only FP registers. Doing so unfortunately creates
1579 more problems than it solves. Fix this for 2.5. */
1580 else if (fp_reg_operand (operand0, mode)
1581 && CONSTANT_P (operand1)
1586 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1587 it in WORD_MODE regardless of what mode it was originally given
1589 scratch_reg = force_mode (word_mode, scratch_reg);
1591 /* Force the constant into memory and put the address of the
1592 memory location into scratch_reg. */
1593 xoperands[0] = scratch_reg;
1594 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1595 emit_move_sequence (xoperands, Pmode, 0);
1597 /* Now load the destination register. */
1598 emit_insn (gen_rtx_SET (mode, operand0,
1599 gen_rtx_MEM (mode, scratch_reg)));
1602 /* Handle secondary reloads for SAR. These occur when trying to load
1603 the SAR from memory, FP register, or with a constant. */
1604 else if (GET_CODE (operand0) == REG
1605 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1606 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1607 && (GET_CODE (operand1) == MEM
1608 || GET_CODE (operand1) == CONST_INT
1609 || (GET_CODE (operand1) == REG
1610 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1613 /* D might not fit in 14 bits either; for such cases load D into
1615 if (GET_CODE (operand1) == MEM
1616 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1618 /* We are reloading the address into the scratch register, so we
1619 want to make sure the scratch register is a full register. */
1620 scratch_reg = force_mode (word_mode, scratch_reg);
1622 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1623 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1626 XEXP (XEXP (operand1, 0),
1630 /* Now we are going to load the scratch register from memory,
1631 we want to load it in the same width as the original MEM,
1632 which must be the same as the width of the ultimate destination,
1634 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1636 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1641 /* We want to load the scratch register using the same mode as
1642 the ultimate destination. */
1643 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1645 emit_move_insn (scratch_reg, operand1);
1648 /* And emit the insn to set the ultimate destination. We know that
1649 the scratch register has the same mode as the destination at this
1651 emit_move_insn (operand0, scratch_reg);
1654 /* Handle most common case: storing into a register. */
1655 else if (register_operand (operand0, mode))
1657 if (register_operand (operand1, mode)
1658 || (GET_CODE (operand1) == CONST_INT
1659 && cint_ok_for_move (INTVAL (operand1)))
1660 || (operand1 == CONST0_RTX (mode))
1661 || (GET_CODE (operand1) == HIGH
1662 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1663 /* Only `general_operands' can come here, so MEM is ok. */
1664 || GET_CODE (operand1) == MEM)
1666 /* Run this case quickly. */
1667 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1671 else if (GET_CODE (operand0) == MEM)
1673 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1674 && !(reload_in_progress || reload_completed))
1676 rtx temp = gen_reg_rtx (DFmode);
1678 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1679 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1682 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1684 /* Run this case quickly. */
1685 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1688 if (! (reload_in_progress || reload_completed))
1690 operands[0] = validize_mem (operand0);
1691 operands[1] = operand1 = force_reg (mode, operand1);
1695 /* Simplify the source if we need to.
1696 Note we do have to handle function labels here, even though we do
1697 not consider them legitimate constants. Loop optimizations can
1698 call the emit_move_xxx with one as a source. */
1699 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1700 || function_label_operand (operand1, mode)
1701 || (GET_CODE (operand1) == HIGH
1702 && symbolic_operand (XEXP (operand1, 0), mode)))
1706 if (GET_CODE (operand1) == HIGH)
1709 operand1 = XEXP (operand1, 0);
1711 if (symbolic_operand (operand1, mode))
1713 /* Argh. The assembler and linker can't handle arithmetic
1716 So we force the plabel into memory, load operand0 from
1717 the memory location, then add in the constant part. */
1718 if ((GET_CODE (operand1) == CONST
1719 && GET_CODE (XEXP (operand1, 0)) == PLUS
1720 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1721 || function_label_operand (operand1, mode))
1723 rtx temp, const_part;
1725 /* Figure out what (if any) scratch register to use. */
1726 if (reload_in_progress || reload_completed)
1728 scratch_reg = scratch_reg ? scratch_reg : operand0;
1729 /* SCRATCH_REG will hold an address and maybe the actual
1730 data. We want it in WORD_MODE regardless of what mode it
1731 was originally given to us. */
1732 scratch_reg = force_mode (word_mode, scratch_reg);
1735 scratch_reg = gen_reg_rtx (Pmode);
1737 if (GET_CODE (operand1) == CONST)
1739 /* Save away the constant part of the expression. */
1740 const_part = XEXP (XEXP (operand1, 0), 1);
1741 if (GET_CODE (const_part) != CONST_INT)
1744 /* Force the function label into memory. */
1745 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1749 /* No constant part. */
1750 const_part = NULL_RTX;
1752 /* Force the function label into memory. */
1753 temp = force_const_mem (mode, operand1);
1757 /* Get the address of the memory location. PIC-ify it if
1759 temp = XEXP (temp, 0);
1761 temp = legitimize_pic_address (temp, mode, scratch_reg);
1763 /* Put the address of the memory location into our destination
1766 emit_move_sequence (operands, mode, scratch_reg);
1768 /* Now load from the memory location into our destination
1770 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1771 emit_move_sequence (operands, mode, scratch_reg);
1773 /* And add back in the constant part. */
1774 if (const_part != NULL_RTX)
1775 expand_inc (operand0, const_part);
1784 if (reload_in_progress || reload_completed)
1786 temp = scratch_reg ? scratch_reg : operand0;
1787 /* TEMP will hold an address and maybe the actual
1788 data. We want it in WORD_MODE regardless of what mode it
1789 was originally given to us. */
1790 temp = force_mode (word_mode, temp);
1793 temp = gen_reg_rtx (Pmode);
1795 /* (const (plus (symbol) (const_int))) must be forced to
1796 memory during/after reload if the const_int will not fit
1798 if (GET_CODE (operand1) == CONST
1799 && GET_CODE (XEXP (operand1, 0)) == PLUS
1800 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1801 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1802 && (reload_completed || reload_in_progress)
1805 operands[1] = force_const_mem (mode, operand1);
1806 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1808 emit_move_sequence (operands, mode, temp);
1812 operands[1] = legitimize_pic_address (operand1, mode, temp);
1813 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1816 /* On the HPPA, references to data space are supposed to use dp,
1817 register 27, but showing it in the RTL inhibits various cse
1818 and loop optimizations. */
1823 if (reload_in_progress || reload_completed)
1825 temp = scratch_reg ? scratch_reg : operand0;
1826 /* TEMP will hold an address and maybe the actual
1827 data. We want it in WORD_MODE regardless of what mode it
1828 was originally given to us. */
1829 temp = force_mode (word_mode, temp);
1832 temp = gen_reg_rtx (mode);
1834 /* Loading a SYMBOL_REF into a register makes that register
1835 safe to be used as the base in an indexed address.
1837 Don't mark hard registers though. That loses. */
1838 if (GET_CODE (operand0) == REG
1839 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1840 REG_POINTER (operand0) = 1;
1841 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1842 REG_POINTER (temp) = 1;
1844 set = gen_rtx_SET (mode, operand0, temp);
1846 set = gen_rtx_SET (VOIDmode,
1848 gen_rtx_LO_SUM (mode, temp, operand1));
1850 emit_insn (gen_rtx_SET (VOIDmode,
1852 gen_rtx_HIGH (mode, operand1)));
1858 else if (GET_CODE (operand1) != CONST_INT
1859 || ! cint_ok_for_move (INTVAL (operand1)))
1861 rtx extend = NULL_RTX;
1864 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1865 && HOST_BITS_PER_WIDE_INT > 32
1866 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1868 HOST_WIDE_INT val = INTVAL (operand1);
1871 /* Extract the low order 32 bits of the value and sign extend.
1872 If the new value is the same as the original value, we can
1873 can use the original value as-is. If the new value is
1874 different, we use it and insert the most-significant 32-bits
1875 of the original value into the final result. */
1876 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1877 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1880 #if HOST_BITS_PER_WIDE_INT > 32
1881 extend = GEN_INT (val >> 32);
1883 operand1 = GEN_INT (nval);
1887 if (reload_in_progress || reload_completed)
1890 temp = gen_reg_rtx (mode);
1892 /* We don't directly split DImode constants on 32-bit targets
1893 because PLUS uses an 11-bit immediate and the insn sequence
1894 generated is not as efficient as the one using HIGH/LO_SUM. */
1895 if (GET_CODE (operand1) == CONST_INT
1896 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1898 /* Directly break constant into high and low parts. This
1899 provides better optimization opportunities because various
1900 passes recognize constants split with PLUS but not LO_SUM.
1901 We use a 14-bit signed low part except when the addition
1902 of 0x4000 to the high part might change the sign of the
1904 HOST_WIDE_INT value = INTVAL (operand1);
1905 HOST_WIDE_INT low = value & 0x3fff;
1906 HOST_WIDE_INT high = value & ~ 0x3fff;
1910 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1918 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1919 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1923 emit_insn (gen_rtx_SET (VOIDmode, temp,
1924 gen_rtx_HIGH (mode, operand1)));
1925 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1928 emit_move_insn (operands[0], operands[1]);
1930 if (extend != NULL_RTX)
1931 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1937 /* Now have insn-emit do whatever it normally does. */
1941 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1942 it will need a link/runtime reloc). */
1950 switch (TREE_CODE (exp))
1957 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1958 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1963 case NON_LVALUE_EXPR:
1964 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1970 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1971 if (TREE_VALUE (link) != 0)
1972 reloc |= reloc_needed (TREE_VALUE (link));
1985 /* Does operand (which is a symbolic_operand) live in text space?
1986 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1990 read_only_operand (operand, mode)
1992 enum machine_mode mode ATTRIBUTE_UNUSED;
1994 if (GET_CODE (operand) == CONST)
1995 operand = XEXP (XEXP (operand, 0), 0);
1998 if (GET_CODE (operand) == SYMBOL_REF)
1999 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2003 if (GET_CODE (operand) == SYMBOL_REF)
2004 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2010 /* Return the best assembler insn template
2011 for moving operands[1] into operands[0] as a fullword. */
2013 singlemove_string (operands)
2016 HOST_WIDE_INT intval;
2018 if (GET_CODE (operands[0]) == MEM)
2019 return "stw %r1,%0";
2020 if (GET_CODE (operands[1]) == MEM)
2022 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2027 if (GET_MODE (operands[1]) != SFmode)
2030 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2032 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2033 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2035 operands[1] = GEN_INT (i);
2036 /* Fall through to CONST_INT case. */
2038 if (GET_CODE (operands[1]) == CONST_INT)
2040 intval = INTVAL (operands[1]);
2042 if (VAL_14_BITS_P (intval))
2044 else if ((intval & 0x7ff) == 0)
2045 return "ldil L'%1,%0";
2046 else if (zdepi_cint_p (intval))
2047 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2049 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2051 return "copy %1,%0";
2055 /* Compute position (in OP[1]) and width (in OP[2])
2056 useful for copying IMM to a register using the zdepi
2057 instructions. Store the immediate value to insert in OP[0]. */
2059 compute_zdepwi_operands (imm, op)
2060 unsigned HOST_WIDE_INT imm;
2065 /* Find the least significant set bit in IMM. */
2066 for (lsb = 0; lsb < 32; lsb++)
2073 /* Choose variants based on *sign* of the 5-bit field. */
2074 if ((imm & 0x10) == 0)
2075 len = (lsb <= 28) ? 4 : 32 - lsb;
2078 /* Find the width of the bitstring in IMM. */
2079 for (len = 5; len < 32; len++)
2081 if ((imm & (1 << len)) == 0)
2085 /* Sign extend IMM as a 5-bit value. */
2086 imm = (imm & 0xf) - 0x10;
2094 /* Compute position (in OP[1]) and width (in OP[2])
2095 useful for copying IMM to a register using the depdi,z
2096 instructions. Store the immediate value to insert in OP[0]. */
2098 compute_zdepdi_operands (imm, op)
2099 unsigned HOST_WIDE_INT imm;
2102 HOST_WIDE_INT lsb, len;
2104 /* Find the least significant set bit in IMM. */
2105 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2112 /* Choose variants based on *sign* of the 5-bit field. */
2113 if ((imm & 0x10) == 0)
2114 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2115 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2118 /* Find the width of the bitstring in IMM. */
2119 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2121 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2125 /* Sign extend IMM as a 5-bit value. */
2126 imm = (imm & 0xf) - 0x10;
2134 /* Output assembler code to perform a doubleword move insn
2135 with operands OPERANDS. */
2138 output_move_double (operands)
2141 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2143 rtx addreg0 = 0, addreg1 = 0;
2145 /* First classify both operands. */
2147 if (REG_P (operands[0]))
2149 else if (offsettable_memref_p (operands[0]))
2151 else if (GET_CODE (operands[0]) == MEM)
2156 if (REG_P (operands[1]))
2158 else if (CONSTANT_P (operands[1]))
2160 else if (offsettable_memref_p (operands[1]))
2162 else if (GET_CODE (operands[1]) == MEM)
2167 /* Check for the cases that the operand constraints are not
2168 supposed to allow to happen. Abort if we get one,
2169 because generating code for these cases is painful. */
2171 if (optype0 != REGOP && optype1 != REGOP)
2174 /* Handle auto decrementing and incrementing loads and stores
2175 specifically, since the structure of the function doesn't work
2176 for them without major modification. Do it better when we learn
2177 this port about the general inc/dec addressing of PA.
2178 (This was written by tege. Chide him if it doesn't work.) */
2180 if (optype0 == MEMOP)
2182 /* We have to output the address syntax ourselves, since print_operand
2183 doesn't deal with the addresses we want to use. Fix this later. */
2185 rtx addr = XEXP (operands[0], 0);
2186 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2188 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2190 operands[0] = XEXP (addr, 0);
2191 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2194 if (!reg_overlap_mentioned_p (high_reg, addr))
2196 /* No overlap between high target register and address
2197 register. (We do this in a non-obvious way to
2198 save a register file writeback) */
2199 if (GET_CODE (addr) == POST_INC)
2200 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2201 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2206 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2208 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2210 operands[0] = XEXP (addr, 0);
2211 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2214 if (!reg_overlap_mentioned_p (high_reg, addr))
2216 /* No overlap between high target register and address
2217 register. (We do this in a non-obvious way to
2218 save a register file writeback) */
2219 if (GET_CODE (addr) == PRE_INC)
2220 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2221 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2227 if (optype1 == MEMOP)
2229 /* We have to output the address syntax ourselves, since print_operand
2230 doesn't deal with the addresses we want to use. Fix this later. */
2232 rtx addr = XEXP (operands[1], 0);
2233 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2235 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2237 operands[1] = XEXP (addr, 0);
2238 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2241 if (!reg_overlap_mentioned_p (high_reg, addr))
2243 /* No overlap between high target register and address
2244 register. (We do this in a non-obvious way to
2245 save a register file writeback) */
2246 if (GET_CODE (addr) == POST_INC)
2247 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2248 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2252 /* This is an undefined situation. We should load into the
2253 address register *and* update that register. Probably
2254 we don't need to handle this at all. */
2255 if (GET_CODE (addr) == POST_INC)
2256 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2257 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2260 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2262 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2264 operands[1] = XEXP (addr, 0);
2265 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2268 if (!reg_overlap_mentioned_p (high_reg, addr))
2270 /* No overlap between high target register and address
2271 register. (We do this in a non-obvious way to
2272 save a register file writeback) */
2273 if (GET_CODE (addr) == PRE_INC)
2274 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2275 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2279 /* This is an undefined situation. We should load into the
2280 address register *and* update that register. Probably
2281 we don't need to handle this at all. */
2282 if (GET_CODE (addr) == PRE_INC)
2283 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2284 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2287 else if (GET_CODE (addr) == PLUS
2288 && GET_CODE (XEXP (addr, 0)) == MULT)
2290 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2292 if (!reg_overlap_mentioned_p (high_reg, addr))
2296 xoperands[0] = high_reg;
2297 xoperands[1] = XEXP (addr, 1);
2298 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2299 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2300 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2302 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2308 xoperands[0] = high_reg;
2309 xoperands[1] = XEXP (addr, 1);
2310 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2311 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2312 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2314 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2319 /* If an operand is an unoffsettable memory ref, find a register
2320 we can increment temporarily to make it refer to the second word. */
2322 if (optype0 == MEMOP)
2323 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2325 if (optype1 == MEMOP)
2326 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2328 /* Ok, we can do one word at a time.
2329 Normally we do the low-numbered word first.
2331 In either case, set up in LATEHALF the operands to use
2332 for the high-numbered word and in some cases alter the
2333 operands in OPERANDS to be suitable for the low-numbered word. */
2335 if (optype0 == REGOP)
2336 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2337 else if (optype0 == OFFSOP)
2338 latehalf[0] = adjust_address (operands[0], SImode, 4);
2340 latehalf[0] = operands[0];
2342 if (optype1 == REGOP)
2343 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2344 else if (optype1 == OFFSOP)
2345 latehalf[1] = adjust_address (operands[1], SImode, 4);
2346 else if (optype1 == CNSTOP)
2347 split_double (operands[1], &operands[1], &latehalf[1]);
2349 latehalf[1] = operands[1];
2351 /* If the first move would clobber the source of the second one,
2352 do them in the other order.
2354 This can happen in two cases:
2356 mem -> register where the first half of the destination register
2357 is the same register used in the memory's address. Reload
2358 can create such insns.
2360 mem in this case will be either register indirect or register
2361 indirect plus a valid offset.
2363 register -> register move where REGNO(dst) == REGNO(src + 1)
2364 someone (Tim/Tege?) claimed this can happen for parameter loads.
2366 Handle mem -> register case first. */
2367 if (optype0 == REGOP
2368 && (optype1 == MEMOP || optype1 == OFFSOP)
2369 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2372 /* Do the late half first. */
2374 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2375 output_asm_insn (singlemove_string (latehalf), latehalf);
2379 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2380 return singlemove_string (operands);
2383 /* Now handle register -> register case. */
2384 if (optype0 == REGOP && optype1 == REGOP
2385 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2387 output_asm_insn (singlemove_string (latehalf), latehalf);
2388 return singlemove_string (operands);
2391 /* Normal case: do the two words, low-numbered first. */
2393 output_asm_insn (singlemove_string (operands), operands);
2395 /* Make any unoffsettable addresses point at high-numbered word. */
2397 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2399 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2402 output_asm_insn (singlemove_string (latehalf), latehalf);
2404 /* Undo the adds we just did. */
2406 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2408 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2414 output_fp_move_double (operands)
2417 if (FP_REG_P (operands[0]))
2419 if (FP_REG_P (operands[1])
2420 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2421 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2423 output_asm_insn ("fldd%F1 %1,%0", operands);
2425 else if (FP_REG_P (operands[1]))
2427 output_asm_insn ("fstd%F0 %1,%0", operands);
2429 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2431 if (GET_CODE (operands[0]) == REG)
2434 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2435 xoperands[0] = operands[0];
2436 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2438 /* This is a pain. You have to be prepared to deal with an
2439 arbitrary address here including pre/post increment/decrement.
2441 so avoid this in the MD. */
2449 /* Return a REG that occurs in ADDR with coefficient 1.
2450 ADDR can be effectively incremented by incrementing REG. */
2453 find_addr_reg (addr)
2456 while (GET_CODE (addr) == PLUS)
2458 if (GET_CODE (XEXP (addr, 0)) == REG)
2459 addr = XEXP (addr, 0);
2460 else if (GET_CODE (XEXP (addr, 1)) == REG)
2461 addr = XEXP (addr, 1);
2462 else if (CONSTANT_P (XEXP (addr, 0)))
2463 addr = XEXP (addr, 1);
2464 else if (CONSTANT_P (XEXP (addr, 1)))
2465 addr = XEXP (addr, 0);
2469 if (GET_CODE (addr) == REG)
2474 /* Emit code to perform a block move.
2476 OPERANDS[0] is the destination pointer as a REG, clobbered.
2477 OPERANDS[1] is the source pointer as a REG, clobbered.
2478 OPERANDS[2] is a register for temporary storage.
2479 OPERANDS[4] is the size as a CONST_INT
2480 OPERANDS[3] is a register for temporary storage.
2481 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2482 OPERANDS[6] is another temporary register. */
2485 output_block_move (operands, size_is_constant)
2487 int size_is_constant ATTRIBUTE_UNUSED;
2489 int align = INTVAL (operands[5]);
2490 unsigned long n_bytes = INTVAL (operands[4]);
2492 /* We can't move more than four bytes at a time because the PA
2493 has no longer integer move insns. (Could use fp mem ops?) */
2497 /* Note that we know each loop below will execute at least twice
2498 (else we would have open-coded the copy). */
2502 /* Pre-adjust the loop counter. */
2503 operands[4] = GEN_INT (n_bytes - 8);
2504 output_asm_insn ("ldi %4,%2", operands);
2507 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2508 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2509 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2510 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2511 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2513 /* Handle the residual. There could be up to 7 bytes of
2514 residual to copy! */
2515 if (n_bytes % 8 != 0)
2517 operands[4] = GEN_INT (n_bytes % 4);
2518 if (n_bytes % 8 >= 4)
2519 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2520 if (n_bytes % 4 != 0)
2521 output_asm_insn ("ldw 0(%1),%6", operands);
2522 if (n_bytes % 8 >= 4)
2523 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2524 if (n_bytes % 4 != 0)
2525 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2530 /* Pre-adjust the loop counter. */
2531 operands[4] = GEN_INT (n_bytes - 4);
2532 output_asm_insn ("ldi %4,%2", operands);
2535 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2536 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2537 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2538 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2539 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2541 /* Handle the residual. */
2542 if (n_bytes % 4 != 0)
2544 if (n_bytes % 4 >= 2)
2545 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2546 if (n_bytes % 2 != 0)
2547 output_asm_insn ("ldb 0(%1),%6", operands);
2548 if (n_bytes % 4 >= 2)
2549 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2550 if (n_bytes % 2 != 0)
2551 output_asm_insn ("stb %6,0(%0)", operands);
2556 /* Pre-adjust the loop counter. */
2557 operands[4] = GEN_INT (n_bytes - 2);
2558 output_asm_insn ("ldi %4,%2", operands);
2561 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2562 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2563 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2564 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2565 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2567 /* Handle the residual. */
2568 if (n_bytes % 2 != 0)
2570 output_asm_insn ("ldb 0(%1),%3", operands);
2571 output_asm_insn ("stb %3,0(%0)", operands);
2580 /* Count the number of insns necessary to handle this block move.
2582 Basic structure is the same as emit_block_move, except that we
2583 count insns rather than emit them. */
2586 compute_movstrsi_length (insn)
2589 rtx pat = PATTERN (insn);
2590 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2591 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2592 unsigned int n_insns = 0;
2594 /* We can't move more than four bytes at a time because the PA
2595 has no longer integer move insns. (Could use fp mem ops?) */
2599 /* The basic copying loop. */
2603 if (n_bytes % (2 * align) != 0)
2605 if ((n_bytes % (2 * align)) >= align)
2608 if ((n_bytes % align) != 0)
2612 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2618 output_and (operands)
2621 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2623 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2624 int ls0, ls1, ms0, p, len;
2626 for (ls0 = 0; ls0 < 32; ls0++)
2627 if ((mask & (1 << ls0)) == 0)
2630 for (ls1 = ls0; ls1 < 32; ls1++)
2631 if ((mask & (1 << ls1)) != 0)
2634 for (ms0 = ls1; ms0 < 32; ms0++)
2635 if ((mask & (1 << ms0)) == 0)
2648 operands[2] = GEN_INT (len);
2649 return "{extru|extrw,u} %1,31,%2,%0";
2653 /* We could use this `depi' for the case above as well, but `depi'
2654 requires one more register file access than an `extru'. */
2659 operands[2] = GEN_INT (p);
2660 operands[3] = GEN_INT (len);
2661 return "{depi|depwi} 0,%2,%3,%0";
2665 return "and %1,%2,%0";
2668 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2669 storing the result in operands[0]. */
2671 output_64bit_and (operands)
2674 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2676 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2677 int ls0, ls1, ms0, p, len;
2679 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2680 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2683 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2684 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2687 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2688 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2691 if (ms0 != HOST_BITS_PER_WIDE_INT)
2694 if (ls1 == HOST_BITS_PER_WIDE_INT)
2701 operands[2] = GEN_INT (len);
2702 return "extrd,u %1,63,%2,%0";
2706 /* We could use this `depi' for the case above as well, but `depi'
2707 requires one more register file access than an `extru'. */
2712 operands[2] = GEN_INT (p);
2713 operands[3] = GEN_INT (len);
2714 return "depdi 0,%2,%3,%0";
2718 return "and %1,%2,%0";
2722 output_ior (operands)
2725 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2726 int bs0, bs1, p, len;
2728 if (INTVAL (operands[2]) == 0)
2729 return "copy %1,%0";
2731 for (bs0 = 0; bs0 < 32; bs0++)
2732 if ((mask & (1 << bs0)) != 0)
2735 for (bs1 = bs0; bs1 < 32; bs1++)
2736 if ((mask & (1 << bs1)) == 0)
2739 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2745 operands[2] = GEN_INT (p);
2746 operands[3] = GEN_INT (len);
2747 return "{depi|depwi} -1,%2,%3,%0";
2750 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2751 storing the result in operands[0]. */
2753 output_64bit_ior (operands)
2756 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2757 int bs0, bs1, p, len;
2759 if (INTVAL (operands[2]) == 0)
2760 return "copy %1,%0";
2762 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2763 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2766 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2767 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2770 if (bs1 != HOST_BITS_PER_WIDE_INT
2771 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2777 operands[2] = GEN_INT (p);
2778 operands[3] = GEN_INT (len);
2779 return "depdi -1,%2,%3,%0";
2782 /* Target hook for assembling integer objects. This code handles
2783 aligned SI and DI integers specially, since function references must
2784 be preceded by P%. */
2787 pa_assemble_integer (x, size, aligned_p)
2792 if (size == UNITS_PER_WORD && aligned_p
2793 && function_label_operand (x, VOIDmode))
2795 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2796 output_addr_const (asm_out_file, x);
2797 fputc ('\n', asm_out_file);
2800 return default_assemble_integer (x, size, aligned_p);
2803 /* Output an ascii string. */
2805 output_ascii (file, p, size)
2812 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2814 /* The HP assembler can only take strings of 256 characters at one
2815 time. This is a limitation on input line length, *not* the
2816 length of the string. Sigh. Even worse, it seems that the
2817 restriction is in number of input characters (see \xnn &
2818 \whatever). So we have to do this very carefully. */
2820 fputs ("\t.STRING \"", file);
2823 for (i = 0; i < size; i += 4)
2827 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2829 register unsigned int c = (unsigned char) p[i + io];
2831 if (c == '\"' || c == '\\')
2832 partial_output[co++] = '\\';
2833 if (c >= ' ' && c < 0177)
2834 partial_output[co++] = c;
2838 partial_output[co++] = '\\';
2839 partial_output[co++] = 'x';
2840 hexd = c / 16 - 0 + '0';
2842 hexd -= '9' - 'a' + 1;
2843 partial_output[co++] = hexd;
2844 hexd = c % 16 - 0 + '0';
2846 hexd -= '9' - 'a' + 1;
2847 partial_output[co++] = hexd;
2850 if (chars_output + co > 243)
2852 fputs ("\"\n\t.STRING \"", file);
2855 fwrite (partial_output, 1, (size_t) co, file);
2859 fputs ("\"\n", file);
2862 /* Try to rewrite floating point comparisons & branches to avoid
2863 useless add,tr insns.
2865 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2866 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2867 first attempt to remove useless add,tr insns. It is zero
2868 for the second pass as reorg sometimes leaves bogus REG_DEAD
2871 When CHECK_NOTES is zero we can only eliminate add,tr insns
2872 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2875 remove_useless_addtr_insns (insns, check_notes)
2880 static int pass = 0;
2882 /* This is fairly cheap, so always run it when optimizing. */
2886 int fbranch_count = 0;
2888 /* Walk all the insns in this function looking for fcmp & fbranch
2889 instructions. Keep track of how many of each we find. */
2890 insns = get_insns ();
2891 for (insn = insns; insn; insn = next_insn (insn))
2895 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2896 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2899 tmp = PATTERN (insn);
2901 /* It must be a set. */
2902 if (GET_CODE (tmp) != SET)
2905 /* If the destination is CCFP, then we've found an fcmp insn. */
2906 tmp = SET_DEST (tmp);
2907 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2913 tmp = PATTERN (insn);
2914 /* If this is an fbranch instruction, bump the fbranch counter. */
2915 if (GET_CODE (tmp) == SET
2916 && SET_DEST (tmp) == pc_rtx
2917 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2918 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2919 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2920 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2928 /* Find all floating point compare + branch insns. If possible,
2929 reverse the comparison & the branch to avoid add,tr insns. */
2930 for (insn = insns; insn; insn = next_insn (insn))
2934 /* Ignore anything that isn't an INSN. */
2935 if (GET_CODE (insn) != INSN)
2938 tmp = PATTERN (insn);
2940 /* It must be a set. */
2941 if (GET_CODE (tmp) != SET)
2944 /* The destination must be CCFP, which is register zero. */
2945 tmp = SET_DEST (tmp);
2946 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2949 /* INSN should be a set of CCFP.
2951 See if the result of this insn is used in a reversed FP
2952 conditional branch. If so, reverse our condition and
2953 the branch. Doing so avoids useless add,tr insns. */
2954 next = next_insn (insn);
2957 /* Jumps, calls and labels stop our search. */
2958 if (GET_CODE (next) == JUMP_INSN
2959 || GET_CODE (next) == CALL_INSN
2960 || GET_CODE (next) == CODE_LABEL)
2963 /* As does another fcmp insn. */
2964 if (GET_CODE (next) == INSN
2965 && GET_CODE (PATTERN (next)) == SET
2966 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2967 && REGNO (SET_DEST (PATTERN (next))) == 0)
2970 next = next_insn (next);
2973 /* Is NEXT_INSN a branch? */
2975 && GET_CODE (next) == JUMP_INSN)
2977 rtx pattern = PATTERN (next);
2979 /* If it a reversed fp conditional branch (eg uses add,tr)
2980 and CCFP dies, then reverse our conditional and the branch
2981 to avoid the add,tr. */
2982 if (GET_CODE (pattern) == SET
2983 && SET_DEST (pattern) == pc_rtx
2984 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2985 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2986 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2987 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2988 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2989 && (fcmp_count == fbranch_count
2991 && find_regno_note (next, REG_DEAD, 0))))
2993 /* Reverse the branch. */
2994 tmp = XEXP (SET_SRC (pattern), 1);
2995 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2996 XEXP (SET_SRC (pattern), 2) = tmp;
2997 INSN_CODE (next) = -1;
2999 /* Reverse our condition. */
3000 tmp = PATTERN (insn);
3001 PUT_CODE (XEXP (tmp, 1),
3002 (reverse_condition_maybe_unordered
3003 (GET_CODE (XEXP (tmp, 1)))));
3013 /* You may have trouble believing this, but this is the 32 bit HP-PA
3018 Variable arguments (optional; any number may be allocated)
3020 SP-(4*(N+9)) arg word N
3025 Fixed arguments (must be allocated; may remain unused)
3034 SP-32 External Data Pointer (DP)
3036 SP-24 External/stub RP (RP')
3040 SP-8 Calling Stub RP (RP'')
3045 SP-0 Stack Pointer (points to next available address)
3049 /* This function saves registers as follows. Registers marked with ' are
3050 this function's registers (as opposed to the previous function's).
3051 If a frame_pointer isn't needed, r4 is saved as a general register;
3052 the space for the frame pointer is still allocated, though, to keep
3058 SP (FP') Previous FP
3059 SP + 4 Alignment filler (sigh)
3060 SP + 8 Space for locals reserved here.
3064 SP + n All call saved register used.
3068 SP + o All call saved fp registers used.
3072 SP + p (SP') points to next available address.
3076 /* Global variables set by output_function_prologue(). */
3077 /* Size of frame. Need to know this to emit return insns from
3079 static int actual_fsize;
3080 static int local_fsize, save_fregs;
3082 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3083 Handle case where DISP > 8k by using the add_high_const patterns.
3085 Note in DISP > 8k case, we will leave the high part of the address
3086 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3089 store_reg (reg, disp, base)
3090 int reg, disp, base;
3092 rtx insn, dest, src, basereg;
3094 src = gen_rtx_REG (word_mode, reg);
3095 basereg = gen_rtx_REG (Pmode, base);
3096 if (VAL_14_BITS_P (disp))
3098 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3099 insn = emit_move_insn (dest, src);
3103 rtx delta = GEN_INT (disp);
3104 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3105 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3106 emit_move_insn (tmpreg, high);
3107 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3108 insn = emit_move_insn (dest, src);
3112 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3113 gen_rtx_SET (VOIDmode,
3114 gen_rtx_MEM (word_mode,
3115 gen_rtx_PLUS (word_mode, basereg,
3123 RTX_FRAME_RELATED_P (insn) = 1;
3126 /* Emit RTL to store REG at the memory location specified by BASE and then
3127 add MOD to BASE. MOD must be <= 8k. */
3130 store_reg_modify (base, reg, mod)
3133 rtx insn, basereg, srcreg, delta;
3135 if (! VAL_14_BITS_P (mod))
3138 basereg = gen_rtx_REG (Pmode, base);
3139 srcreg = gen_rtx_REG (word_mode, reg);
3140 delta = GEN_INT (mod);
3142 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3145 RTX_FRAME_RELATED_P (insn) = 1;
3147 /* RTX_FRAME_RELATED_P must be set on each frame related set
3148 in a parallel with more than one element. Don't set
3149 RTX_FRAME_RELATED_P in the first set if reg is temporary
3150 register 1. The effect of this operation is recorded in
3151 the initial copy. */
3154 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3155 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3159 /* The first element of a PARALLEL is always processed if it is
3160 a SET. Thus, we need an expression list for this case. */
3162 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3163 gen_rtx_SET (VOIDmode, basereg,
3164 gen_rtx_PLUS (word_mode, basereg, delta)),
3170 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3171 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3172 whether to add a frame note or not.
3174 In the DISP > 8k case, we leave the high part of the address in %r1.
3175 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3178 set_reg_plus_d (reg, base, disp, note)
3179 int reg, base, disp, note;
3183 if (VAL_14_BITS_P (disp))
3185 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3186 plus_constant (gen_rtx_REG (Pmode, base), disp));
3190 rtx basereg = gen_rtx_REG (Pmode, base);
3191 rtx delta = GEN_INT (disp);
3193 emit_move_insn (gen_rtx_REG (Pmode, 1),
3194 gen_rtx_PLUS (Pmode, basereg,
3195 gen_rtx_HIGH (Pmode, delta)));
3196 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3197 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3201 if (DO_FRAME_NOTES && note)
3202 RTX_FRAME_RELATED_P (insn) = 1;
3206 compute_frame_size (size, fregs_live)
3213 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3214 be consistent with the rounding and size calculation done here.
3215 Change them at the same time. */
3217 /* We do our own stack alignment. First, round the size of the
3218 stack locals up to a word boundary. */
3219 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3221 /* Space for previous frame pointer + filler. If any frame is
3222 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3223 waste some space here for the sake of HP compatibility. The
3224 first slot is only used when the frame pointer is needed. */
3225 if (size || frame_pointer_needed)
3226 size += STARTING_FRAME_OFFSET;
3228 /* If the current function calls __builtin_eh_return, then we need
3229 to allocate stack space for registers that will hold data for
3230 the exception handler. */
3231 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3235 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3237 size += i * UNITS_PER_WORD;
3240 /* Account for space used by the callee general register saves. */
3241 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3242 if (regs_ever_live[i])
3243 size += UNITS_PER_WORD;
3245 /* Account for space used by the callee floating point register saves. */
3246 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3247 if (regs_ever_live[i]
3248 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3252 /* We always save both halves of the FP register, so always
3253 increment the frame size by 8 bytes. */
3257 /* If any of the floating registers are saved, account for the
3258 alignment needed for the floating point register save block. */
3261 size = (size + 7) & ~7;
3266 /* The various ABIs include space for the outgoing parameters in the
3267 size of the current function's stack frame. We don't need to align
3268 for the outgoing arguments as their alignment is set by the final
3269 rounding for the frame as a whole. */
3270 size += current_function_outgoing_args_size;
3272 /* Allocate space for the fixed frame marker. This space must be
3273 allocated for any function that makes calls or allocates
3275 if (!current_function_is_leaf || size)
3276 size += TARGET_64BIT ? 48 : 32;
3278 /* Finally, round to the preferred stack boundary. */
3279 return ((size + PREFERRED_STACK_BOUNDARY / 8 - 1)
3280 & ~(PREFERRED_STACK_BOUNDARY / 8 - 1));
3283 /* Generate the assembly code for function entry. FILE is a stdio
3284 stream to output the code to. SIZE is an int: how many units of
3285 temporary storage to allocate.
3287 Refer to the array `regs_ever_live' to determine which registers to
3288 save; `regs_ever_live[I]' is nonzero if register number I is ever
3289 used in the function. This function is responsible for knowing
3290 which registers should not be saved even if used. */
3292 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3293 of memory. If any fpu reg is used in the function, we allocate
3294 such a block here, at the bottom of the frame, just in case it's needed.
3296 If this function is a leaf procedure, then we may choose not
3297 to do a "save" insn. The decision about whether or not
3298 to do this is made in regclass.c. */
3301 pa_output_function_prologue (file, size)
3303 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3305 /* The function's label and associated .PROC must never be
3306 separated and must be output *after* any profiling declarations
3307 to avoid changing spaces/subspaces within a procedure. */
3308 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3309 fputs ("\t.PROC\n", file);
3311 /* hppa_expand_prologue does the dirty work now. We just need
3312 to output the assembler directives which denote the start
3314 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3315 if (regs_ever_live[2])
3316 fputs (",CALLS,SAVE_RP", file);
3318 fputs (",NO_CALLS", file);
3320 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3321 at the beginning of the frame and that it is used as the frame
3322 pointer for the frame. We do this because our current frame
3323 layout doesn't conform to that specified in the the HP runtime
3324 documentation and we need a way to indicate to programs such as
3325 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3326 isn't used by HP compilers but is supported by the assembler.
3327 However, SAVE_SP is supposed to indicate that the previous stack
3328 pointer has been saved in the frame marker. */
3329 if (frame_pointer_needed)
3330 fputs (",SAVE_SP", file);
3332 /* Pass on information about the number of callee register saves
3333 performed in the prologue.
3335 The compiler is supposed to pass the highest register number
3336 saved, the assembler then has to adjust that number before
3337 entering it into the unwind descriptor (to account for any
3338 caller saved registers with lower register numbers than the
3339 first callee saved register). */
3341 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3344 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3346 fputs ("\n\t.ENTRY\n", file);
3348 remove_useless_addtr_insns (get_insns (), 0);
3352 hppa_expand_prologue ()
3354 int merge_sp_adjust_with_store = 0;
3355 int size = get_frame_size ();
3363 /* Compute total size for frame pointer, filler, locals and rounding to
3364 the next word boundary. Similar code appears in compute_frame_size
3365 and must be changed in tandem with this code. */
3366 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3367 if (local_fsize || frame_pointer_needed)
3368 local_fsize += STARTING_FRAME_OFFSET;
3370 actual_fsize = compute_frame_size (size, &save_fregs);
3372 /* Compute a few things we will use often. */
3373 tmpreg = gen_rtx_REG (word_mode, 1);
3375 /* Save RP first. The calling conventions manual states RP will
3376 always be stored into the caller's frame at sp - 20 or sp - 16
3377 depending on which ABI is in use. */
3378 if (regs_ever_live[2] || current_function_calls_eh_return)
3379 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3381 /* Allocate the local frame and set up the frame pointer if needed. */
3382 if (actual_fsize != 0)
3384 if (frame_pointer_needed)
3386 /* Copy the old frame pointer temporarily into %r1. Set up the
3387 new stack pointer, then store away the saved old frame pointer
3388 into the stack at sp and at the same time update the stack
3389 pointer by actual_fsize bytes. Two versions, first
3390 handles small (<8k) frames. The second handles large (>=8k)
3392 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3395 /* We need to record the frame pointer save here since the
3396 new frame pointer is set in the following insn. */
3397 RTX_FRAME_RELATED_P (insn) = 1;
3399 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3400 gen_rtx_SET (VOIDmode,
3401 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3406 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3408 RTX_FRAME_RELATED_P (insn) = 1;
3410 if (VAL_14_BITS_P (actual_fsize))
3411 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3414 /* It is incorrect to store the saved frame pointer at *sp,
3415 then increment sp (writes beyond the current stack boundary).
3417 So instead use stwm to store at *sp and post-increment the
3418 stack pointer as an atomic operation. Then increment sp to
3419 finish allocating the new frame. */
3420 int adjust1 = 8192 - 64;
3421 int adjust2 = actual_fsize - adjust1;
3423 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3424 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3428 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3429 we need to store the previous stack pointer (frame pointer)
3430 into the frame marker on targets that use the HP unwind
3431 library. This allows the HP unwind library to be used to
3432 unwind GCC frames. However, we are not fully compatible
3433 with the HP library because our frame layout differs from
3434 that specified in the HP runtime specification.
3436 We don't want a frame note on this instruction as the frame
3437 marker moves during dynamic stack allocation.
3439 This instruction also serves as a blockage to prevent
3440 register spills from being scheduled before the stack
3441 pointer is raised. This is necessary as we store
3442 registers using the frame pointer as a base register,
3443 and the frame pointer is set before sp is raised. */
3444 if (TARGET_HPUX_UNWIND_LIBRARY)
3446 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3447 GEN_INT (TARGET_64BIT ? -8 : -4));
3449 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3453 emit_insn (gen_blockage ());
3455 /* no frame pointer needed. */
3458 /* In some cases we can perform the first callee register save
3459 and allocating the stack frame at the same time. If so, just
3460 make a note of it and defer allocating the frame until saving
3461 the callee registers. */
3462 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3463 merge_sp_adjust_with_store = 1;
3464 /* Can not optimize. Adjust the stack frame by actual_fsize
3467 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3472 /* Normal register save.
3474 Do not save the frame pointer in the frame_pointer_needed case. It
3475 was done earlier. */
3476 if (frame_pointer_needed)
3478 offset = local_fsize;
3480 /* Saving the EH return data registers in the frame is the simplest
3481 way to get the frame unwind information emitted. We put them
3482 just before the general registers. */
3483 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3485 unsigned int i, regno;
3489 regno = EH_RETURN_DATA_REGNO (i);
3490 if (regno == INVALID_REGNUM)
3493 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3494 offset += UNITS_PER_WORD;
3498 for (i = 18; i >= 4; i--)
3499 if (regs_ever_live[i] && ! call_used_regs[i])
3501 store_reg (i, offset, FRAME_POINTER_REGNUM);
3502 offset += UNITS_PER_WORD;
3505 /* Account for %r3 which is saved in a special place. */
3508 /* No frame pointer needed. */
3511 offset = local_fsize - actual_fsize;
3513 /* Saving the EH return data registers in the frame is the simplest
3514 way to get the frame unwind information emitted. */
3515 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3517 unsigned int i, regno;
3521 regno = EH_RETURN_DATA_REGNO (i);
3522 if (regno == INVALID_REGNUM)
3525 /* If merge_sp_adjust_with_store is nonzero, then we can
3526 optimize the first save. */
3527 if (merge_sp_adjust_with_store)
3529 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3530 merge_sp_adjust_with_store = 0;
3533 store_reg (regno, offset, STACK_POINTER_REGNUM);
3534 offset += UNITS_PER_WORD;
3538 for (i = 18; i >= 3; i--)
3539 if (regs_ever_live[i] && ! call_used_regs[i])
3541 /* If merge_sp_adjust_with_store is nonzero, then we can
3542 optimize the first GR save. */
3543 if (merge_sp_adjust_with_store)
3545 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3546 merge_sp_adjust_with_store = 0;
3549 store_reg (i, offset, STACK_POINTER_REGNUM);
3550 offset += UNITS_PER_WORD;
3554 /* If we wanted to merge the SP adjustment with a GR save, but we never
3555 did any GR saves, then just emit the adjustment here. */
3556 if (merge_sp_adjust_with_store)
3557 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3561 /* The hppa calling conventions say that %r19, the pic offset
3562 register, is saved at sp - 32 (in this function's frame)
3563 when generating PIC code. FIXME: What is the correct thing
3564 to do for functions which make no calls and allocate no
3565 frame? Do we need to allocate a frame, or can we just omit
3566 the save? For now we'll just omit the save. */
3567 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3568 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3570 /* Align pointer properly (doubleword boundary). */
3571 offset = (offset + 7) & ~7;
3573 /* Floating point register store. */
3578 /* First get the frame or stack pointer to the start of the FP register
3580 if (frame_pointer_needed)
3582 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3583 base = frame_pointer_rtx;
3587 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3588 base = stack_pointer_rtx;
3591 /* Now actually save the FP registers. */
3592 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3594 if (regs_ever_live[i]
3595 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3597 rtx addr, insn, reg;
3598 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3599 reg = gen_rtx_REG (DFmode, i);
3600 insn = emit_move_insn (addr, reg);
3603 RTX_FRAME_RELATED_P (insn) = 1;
3606 rtx mem = gen_rtx_MEM (DFmode,
3607 plus_constant (base, offset));
3609 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3610 gen_rtx_SET (VOIDmode, mem, reg),
3615 rtx meml = gen_rtx_MEM (SFmode,
3616 plus_constant (base, offset));
3617 rtx memr = gen_rtx_MEM (SFmode,
3618 plus_constant (base, offset + 4));
3619 rtx regl = gen_rtx_REG (SFmode, i);
3620 rtx regr = gen_rtx_REG (SFmode, i + 1);
3621 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3622 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3625 RTX_FRAME_RELATED_P (setl) = 1;
3626 RTX_FRAME_RELATED_P (setr) = 1;
3627 vec = gen_rtvec (2, setl, setr);
3629 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3630 gen_rtx_SEQUENCE (VOIDmode, vec),
3634 offset += GET_MODE_SIZE (DFmode);
3640 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3641 prevent insns with frame notes being scheduled in the delay slot
3642 of calls. This causes problems because the dwarf2 output code
3643 processes the insn list serially. For now, limit the migration
3644 of prologue insns with a blockage. */
3646 emit_insn (gen_blockage ());
3649 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3650 Handle case where DISP > 8k by using the add_high_const patterns. */
3653 load_reg (reg, disp, base)
3654 int reg, disp, base;
3656 rtx src, dest, basereg;
3658 dest = gen_rtx_REG (word_mode, reg);
3659 basereg = gen_rtx_REG (Pmode, base);
3660 if (VAL_14_BITS_P (disp))
3662 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3663 emit_move_insn (dest, src);
3667 rtx delta = GEN_INT (disp);
3668 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3669 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3670 emit_move_insn (tmpreg, high);
3671 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3672 emit_move_insn (dest, src);
3676 /* This function generates the assembly code for function exit.
3677 Args are as for output_function_prologue ().
3679 The function epilogue should not depend on the current stack
3680 pointer! It should use the frame pointer only. This is mandatory
3681 because of alloca; we also take advantage of it to omit stack
3682 adjustments before returning. */
3685 pa_output_function_epilogue (file, size)
3687 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3689 int last_address = 0;
3690 rtx insn = get_last_insn ();
3692 /* hppa_expand_epilogue does the dirty work now. We just need
3693 to output the assembler directives which denote the end
3696 To make debuggers happy, emit a nop if the epilogue was completely
3697 eliminated due to a volatile call as the last insn in the
3698 current function. That way the return address (in %r2) will
3699 always point to a valid instruction in the current function. */
3701 /* Get the last real insn. */
3702 if (GET_CODE (insn) == NOTE)
3703 insn = prev_real_insn (insn);
3705 /* If it is a sequence, then look inside. */
3706 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3707 insn = XVECEXP (PATTERN (insn), 0, 0);
3709 /* If insn is a CALL_INSN, then it must be a call to a volatile
3710 function (otherwise there would be epilogue insns). */
3711 if (insn && GET_CODE (insn) == CALL_INSN)
3713 fputs ("\tnop\n", file);
3717 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3719 /* Finally, update the total number of code bytes output so far. */
3720 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3721 && !flag_function_sections)
3723 if (INSN_ADDRESSES_SET_P ())
3725 unsigned long old_total = total_code_bytes;
3727 insn = get_last_nonnote_insn ();
3728 last_address += INSN_ADDRESSES (INSN_UID (insn));
3730 last_address += insn_default_length (insn);
3732 total_code_bytes += last_address;
3733 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3735 /* Be prepared to handle overflows. */
3736 if (old_total > total_code_bytes)
3737 total_code_bytes = -1;
3740 total_code_bytes = -1;
3745 hppa_expand_epilogue ()
3749 int merge_sp_adjust_with_load = 0;
3752 /* We will use this often. */
3753 tmpreg = gen_rtx_REG (word_mode, 1);
3755 /* Try to restore RP early to avoid load/use interlocks when
3756 RP gets used in the return (bv) instruction. This appears to still
3757 be necessary even when we schedule the prologue and epilogue. */
3758 if (regs_ever_live [2] || current_function_calls_eh_return)
3760 ret_off = TARGET_64BIT ? -16 : -20;
3761 if (frame_pointer_needed)
3763 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3768 /* No frame pointer, and stack is smaller than 8k. */
3769 if (VAL_14_BITS_P (ret_off - actual_fsize))
3771 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3777 /* General register restores. */
3778 if (frame_pointer_needed)
3780 offset = local_fsize;
3782 /* If the current function calls __builtin_eh_return, then we need
3783 to restore the saved EH data registers. */
3784 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3786 unsigned int i, regno;
3790 regno = EH_RETURN_DATA_REGNO (i);
3791 if (regno == INVALID_REGNUM)
3794 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3795 offset += UNITS_PER_WORD;
3799 for (i = 18; i >= 4; i--)
3800 if (regs_ever_live[i] && ! call_used_regs[i])
3802 load_reg (i, offset, FRAME_POINTER_REGNUM);
3803 offset += UNITS_PER_WORD;
3808 offset = local_fsize - actual_fsize;
3810 /* If the current function calls __builtin_eh_return, then we need
3811 to restore the saved EH data registers. */
3812 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3814 unsigned int i, regno;
3818 regno = EH_RETURN_DATA_REGNO (i);
3819 if (regno == INVALID_REGNUM)
3822 /* Only for the first load.
3823 merge_sp_adjust_with_load holds the register load
3824 with which we will merge the sp adjustment. */
3825 if (merge_sp_adjust_with_load == 0
3827 && VAL_14_BITS_P (-actual_fsize))
3828 merge_sp_adjust_with_load = regno;
3830 load_reg (regno, offset, STACK_POINTER_REGNUM);
3831 offset += UNITS_PER_WORD;
3835 for (i = 18; i >= 3; i--)
3837 if (regs_ever_live[i] && ! call_used_regs[i])
3839 /* Only for the first load.
3840 merge_sp_adjust_with_load holds the register load
3841 with which we will merge the sp adjustment. */
3842 if (merge_sp_adjust_with_load == 0
3844 && VAL_14_BITS_P (-actual_fsize))
3845 merge_sp_adjust_with_load = i;
3847 load_reg (i, offset, STACK_POINTER_REGNUM);
3848 offset += UNITS_PER_WORD;
3853 /* Align pointer properly (doubleword boundary). */
3854 offset = (offset + 7) & ~7;
3856 /* FP register restores. */
3859 /* Adjust the register to index off of. */
3860 if (frame_pointer_needed)
3861 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3863 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3865 /* Actually do the restores now. */
3866 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3867 if (regs_ever_live[i]
3868 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3870 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3871 rtx dest = gen_rtx_REG (DFmode, i);
3872 emit_move_insn (dest, src);
3876 /* Emit a blockage insn here to keep these insns from being moved to
3877 an earlier spot in the epilogue, or into the main instruction stream.
3879 This is necessary as we must not cut the stack back before all the
3880 restores are finished. */
3881 emit_insn (gen_blockage ());
3883 /* Reset stack pointer (and possibly frame pointer). The stack
3884 pointer is initially set to fp + 64 to avoid a race condition. */
3885 if (frame_pointer_needed)
3887 rtx delta = GEN_INT (-64);
3889 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3890 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3892 /* If we were deferring a callee register restore, do it now. */
3893 else if (merge_sp_adjust_with_load)
3895 rtx delta = GEN_INT (-actual_fsize);
3896 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3898 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3900 else if (actual_fsize != 0)
3901 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3904 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3905 frame greater than 8k), do so now. */
3907 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3909 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3911 rtx sa = EH_RETURN_STACKADJ_RTX;
3913 emit_insn (gen_blockage ());
3914 emit_insn (TARGET_64BIT
3915 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3916 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3921 hppa_pic_save_rtx ()
3923 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3927 hppa_profile_hook (label_no)
3930 rtx begin_label_rtx, call_insn;
3931 char begin_label_name[16];
3933 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3935 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3938 emit_move_insn (arg_pointer_rtx,
3939 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3942 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3944 #ifndef NO_PROFILE_COUNTERS
3946 rtx count_label_rtx, addr, r24;
3947 char count_label_name[16];
3949 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3950 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3952 addr = force_reg (Pmode, count_label_rtx);
3953 r24 = gen_rtx_REG (Pmode, 24);
3954 emit_move_insn (r24, addr);
3956 /* %r25 is set from within the output pattern. */
3958 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3959 GEN_INT (TARGET_64BIT ? 24 : 12),
3962 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3965 /* %r25 is set from within the output pattern. */
3967 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3968 GEN_INT (TARGET_64BIT ? 16 : 8),
3972 /* Indicate the _mcount call cannot throw, nor will it execute a
3974 REG_NOTES (call_insn)
3975 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3979 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3981 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3983 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3987 /* Fetch the return address for the frame COUNT steps up from
3988 the current frame, after the prologue. FRAMEADDR is the
3989 frame pointer of the COUNT frame.
3991 We want to ignore any export stub remnants here. To handle this,
3992 we examine the code at the return address, and if it is an export
3993 stub, we return a memory rtx for the stub return address stored
3996 The value returned is used in two different ways:
3998 1. To find a function's caller.
4000 2. To change the return address for a function.
4002 This function handles most instances of case 1; however, it will
4003 fail if there are two levels of stubs to execute on the return
4004 path. The only way I believe that can happen is if the return value
4005 needs a parameter relocation, which never happens for C code.
4007 This function handles most instances of case 2; however, it will
4008 fail if we did not originally have stub code on the return path
4009 but will need stub code on the new return path. This can happen if
4010 the caller & callee are both in the main program, but the new
4011 return location is in a shared library. */
4014 return_addr_rtx (count, frameaddr)
4026 rp = get_hard_reg_initial_val (Pmode, 2);
4028 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4031 saved_rp = gen_reg_rtx (Pmode);
4032 emit_move_insn (saved_rp, rp);
4034 /* Get pointer to the instruction stream. We have to mask out the
4035 privilege level from the two low order bits of the return address
4036 pointer here so that ins will point to the start of the first
4037 instruction that would have been executed if we returned. */
4038 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4039 label = gen_label_rtx ();
4041 /* Check the instruction stream at the normal return address for the
4044 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4045 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4046 0x00011820 | stub+16: mtsp r1,sr0
4047 0xe0400002 | stub+20: be,n 0(sr0,rp)
4049 If it is an export stub, than our return address is really in
4052 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4053 NULL_RTX, SImode, 1);
4054 emit_jump_insn (gen_bne (label));
4056 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4057 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4058 emit_jump_insn (gen_bne (label));
4060 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4061 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4062 emit_jump_insn (gen_bne (label));
4064 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4065 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4067 /* If there is no export stub then just use the value saved from
4068 the return pointer register. */
4070 emit_jump_insn (gen_bne (label));
4072 /* Here we know that our return address points to an export
4073 stub. We don't want to return the address of the export stub,
4074 but rather the return address of the export stub. That return
4075 address is stored at -24[frameaddr]. */
4077 emit_move_insn (saved_rp,
4079 memory_address (Pmode,
4080 plus_constant (frameaddr,
4087 /* This is only valid once reload has completed because it depends on
4088 knowing exactly how much (if any) frame there is and...
4090 It's only valid if there is no frame marker to de-allocate and...
4092 It's only valid if %r2 hasn't been saved into the caller's frame
4093 (we're not profiling and %r2 isn't live anywhere). */
4095 hppa_can_use_return_insn_p ()
4097 return (reload_completed
4098 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4099 && ! regs_ever_live[2]
4100 && ! frame_pointer_needed);
4104 emit_bcond_fp (code, operand0)
4108 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4109 gen_rtx_IF_THEN_ELSE (VOIDmode,
4110 gen_rtx_fmt_ee (code,
4112 gen_rtx_REG (CCFPmode, 0),
4114 gen_rtx_LABEL_REF (VOIDmode, operand0),
4120 gen_cmp_fp (code, operand0, operand1)
4122 rtx operand0, operand1;
4124 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4125 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4128 /* Adjust the cost of a scheduling dependency. Return the new cost of
4129 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4132 pa_adjust_cost (insn, link, dep_insn, cost)
4138 enum attr_type attr_type;
4140 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4141 true dependencies as they are described with bypasses now. */
4142 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4145 if (! recog_memoized (insn))
4148 attr_type = get_attr_type (insn);
4150 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4152 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4155 if (attr_type == TYPE_FPLOAD)
4157 rtx pat = PATTERN (insn);
4158 rtx dep_pat = PATTERN (dep_insn);
4159 if (GET_CODE (pat) == PARALLEL)
4161 /* This happens for the fldXs,mb patterns. */
4162 pat = XVECEXP (pat, 0, 0);
4164 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4165 /* If this happens, we have to extend this to schedule
4166 optimally. Return 0 for now. */
4169 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4171 if (! recog_memoized (dep_insn))
4173 switch (get_attr_type (dep_insn))
4180 case TYPE_FPSQRTSGL:
4181 case TYPE_FPSQRTDBL:
4182 /* A fpload can't be issued until one cycle before a
4183 preceding arithmetic operation has finished if
4184 the target of the fpload is any of the sources
4185 (or destination) of the arithmetic operation. */
4186 return insn_default_latency (dep_insn) - 1;
4193 else if (attr_type == TYPE_FPALU)
4195 rtx pat = PATTERN (insn);
4196 rtx dep_pat = PATTERN (dep_insn);
4197 if (GET_CODE (pat) == PARALLEL)
4199 /* This happens for the fldXs,mb patterns. */
4200 pat = XVECEXP (pat, 0, 0);
4202 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4203 /* If this happens, we have to extend this to schedule
4204 optimally. Return 0 for now. */
4207 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4209 if (! recog_memoized (dep_insn))
4211 switch (get_attr_type (dep_insn))
4215 case TYPE_FPSQRTSGL:
4216 case TYPE_FPSQRTDBL:
4217 /* An ALU flop can't be issued until two cycles before a
4218 preceding divide or sqrt operation has finished if
4219 the target of the ALU flop is any of the sources
4220 (or destination) of the divide or sqrt operation. */
4221 return insn_default_latency (dep_insn) - 2;
4229 /* For other anti dependencies, the cost is 0. */
4232 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4234 /* Output dependency; DEP_INSN writes a register that INSN writes some
4236 if (attr_type == TYPE_FPLOAD)
4238 rtx pat = PATTERN (insn);
4239 rtx dep_pat = PATTERN (dep_insn);
4240 if (GET_CODE (pat) == PARALLEL)
4242 /* This happens for the fldXs,mb patterns. */
4243 pat = XVECEXP (pat, 0, 0);
4245 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4246 /* If this happens, we have to extend this to schedule
4247 optimally. Return 0 for now. */
4250 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4252 if (! recog_memoized (dep_insn))
4254 switch (get_attr_type (dep_insn))
4261 case TYPE_FPSQRTSGL:
4262 case TYPE_FPSQRTDBL:
4263 /* A fpload can't be issued until one cycle before a
4264 preceding arithmetic operation has finished if
4265 the target of the fpload is the destination of the
4266 arithmetic operation.
4268 Exception: For PA7100LC, PA7200 and PA7300, the cost
4269 is 3 cycles, unless they bundle together. We also
4270 pay the penalty if the second insn is a fpload. */
4271 return insn_default_latency (dep_insn) - 1;
4278 else if (attr_type == TYPE_FPALU)
4280 rtx pat = PATTERN (insn);
4281 rtx dep_pat = PATTERN (dep_insn);
4282 if (GET_CODE (pat) == PARALLEL)
4284 /* This happens for the fldXs,mb patterns. */
4285 pat = XVECEXP (pat, 0, 0);
4287 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4288 /* If this happens, we have to extend this to schedule
4289 optimally. Return 0 for now. */
4292 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4294 if (! recog_memoized (dep_insn))
4296 switch (get_attr_type (dep_insn))
4300 case TYPE_FPSQRTSGL:
4301 case TYPE_FPSQRTDBL:
4302 /* An ALU flop can't be issued until two cycles before a
4303 preceding divide or sqrt operation has finished if
4304 the target of the ALU flop is also the target of
4305 the divide or sqrt operation. */
4306 return insn_default_latency (dep_insn) - 2;
4314 /* For other output dependencies, the cost is 0. */
4321 /* Adjust scheduling priorities. We use this to try and keep addil
4322 and the next use of %r1 close together. */
4324 pa_adjust_priority (insn, priority)
4328 rtx set = single_set (insn);
4332 src = SET_SRC (set);
4333 dest = SET_DEST (set);
4334 if (GET_CODE (src) == LO_SUM
4335 && symbolic_operand (XEXP (src, 1), VOIDmode)
4336 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4339 else if (GET_CODE (src) == MEM
4340 && GET_CODE (XEXP (src, 0)) == LO_SUM
4341 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4342 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4345 else if (GET_CODE (dest) == MEM
4346 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4347 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4348 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4354 /* The 700 can only issue a single insn at a time.
4355 The 7XXX processors can issue two insns at a time.
4356 The 8000 can issue 4 insns at a time. */
4362 case PROCESSOR_700: return 1;
4363 case PROCESSOR_7100: return 2;
4364 case PROCESSOR_7100LC: return 2;
4365 case PROCESSOR_7200: return 2;
4366 case PROCESSOR_7300: return 2;
4367 case PROCESSOR_8000: return 4;
4376 /* Return any length adjustment needed by INSN which already has its length
4377 computed as LENGTH. Return zero if no adjustment is necessary.
4379 For the PA: function calls, millicode calls, and backwards short
4380 conditional branches with unfilled delay slots need an adjustment by +1
4381 (to account for the NOP which will be inserted into the instruction stream).
4383 Also compute the length of an inline block move here as it is too
4384 complicated to express as a length attribute in pa.md. */
4386 pa_adjust_insn_length (insn, length)
4390 rtx pat = PATTERN (insn);
4392 /* Call insns which are *not* indirect and have unfilled delay slots. */
4393 if (GET_CODE (insn) == CALL_INSN)
4396 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4397 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4399 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4400 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4406 /* Jumps inside switch tables which have unfilled delay slots
4407 also need adjustment. */
4408 else if (GET_CODE (insn) == JUMP_INSN
4409 && simplejump_p (insn)
4410 && GET_MODE (insn) == SImode)
4412 /* Millicode insn with an unfilled delay slot. */
4413 else if (GET_CODE (insn) == INSN
4414 && GET_CODE (pat) != SEQUENCE
4415 && GET_CODE (pat) != USE
4416 && GET_CODE (pat) != CLOBBER
4417 && get_attr_type (insn) == TYPE_MILLI)
4419 /* Block move pattern. */
4420 else if (GET_CODE (insn) == INSN
4421 && GET_CODE (pat) == PARALLEL
4422 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4423 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4424 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4425 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4426 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4427 return compute_movstrsi_length (insn) - 4;
4428 /* Conditional branch with an unfilled delay slot. */
4429 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4431 /* Adjust a short backwards conditional with an unfilled delay slot. */
4432 if (GET_CODE (pat) == SET
4434 && ! forward_branch_p (insn))
4436 else if (GET_CODE (pat) == PARALLEL
4437 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4440 /* Adjust dbra insn with short backwards conditional branch with
4441 unfilled delay slot -- only for case where counter is in a
4442 general register register. */
4443 else if (GET_CODE (pat) == PARALLEL
4444 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4445 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4446 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4448 && ! forward_branch_p (insn))
4456 /* Print operand X (an rtx) in assembler syntax to file FILE.
4457 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4458 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4461 print_operand (file, x, code)
4469 /* Output a 'nop' if there's nothing for the delay slot. */
4470 if (dbr_sequence_length () == 0)
4471 fputs ("\n\tnop", file);
4474 /* Output a nullification completer if there's nothing for the */
4475 /* delay slot or nullification is requested. */
4476 if (dbr_sequence_length () == 0 ||
4478 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4482 /* Print out the second register name of a register pair.
4483 I.e., R (6) => 7. */
4484 fputs (reg_names[REGNO (x) + 1], file);
4487 /* A register or zero. */
4489 || (x == CONST0_RTX (DFmode))
4490 || (x == CONST0_RTX (SFmode)))
4492 fputs ("%r0", file);
4498 /* A register or zero (floating point). */
4500 || (x == CONST0_RTX (DFmode))
4501 || (x == CONST0_RTX (SFmode)))
4503 fputs ("%fr0", file);
4512 xoperands[0] = XEXP (XEXP (x, 0), 0);
4513 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4514 output_global_address (file, xoperands[1], 0);
4515 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4519 case 'C': /* Plain (C)ondition */
4521 switch (GET_CODE (x))
4524 fputs ("=", file); break;
4526 fputs ("<>", file); break;
4528 fputs (">", file); break;
4530 fputs (">=", file); break;
4532 fputs (">>=", file); break;
4534 fputs (">>", file); break;
4536 fputs ("<", file); break;
4538 fputs ("<=", file); break;
4540 fputs ("<<=", file); break;
4542 fputs ("<<", file); break;
4547 case 'N': /* Condition, (N)egated */
4548 switch (GET_CODE (x))
4551 fputs ("<>", file); break;
4553 fputs ("=", file); break;
4555 fputs ("<=", file); break;
4557 fputs ("<", file); break;
4559 fputs ("<<", file); break;
4561 fputs ("<<=", file); break;
4563 fputs (">=", file); break;
4565 fputs (">", file); break;
4567 fputs (">>", file); break;
4569 fputs (">>=", file); break;
4574 /* For floating point comparisons. Note that the output
4575 predicates are the complement of the desired mode. */
4577 switch (GET_CODE (x))
4580 fputs ("!=", file); break;
4582 fputs ("=", file); break;
4584 fputs ("!>", file); break;
4586 fputs ("!>=", file); break;
4588 fputs ("!<", file); break;
4590 fputs ("!<=", file); break;
4592 fputs ("!<>", file); break;
4594 fputs (">", file); break;
4596 fputs (">=", file); break;
4598 fputs ("<", file); break;
4600 fputs ("<=", file); break;
4602 fputs ("<>", file); break;
4604 fputs ("<=>", file); break;
4606 fputs ("!<=>", file); break;
4611 case 'S': /* Condition, operands are (S)wapped. */
4612 switch (GET_CODE (x))
4615 fputs ("=", file); break;
4617 fputs ("<>", file); break;
4619 fputs ("<", file); break;
4621 fputs ("<=", file); break;
4623 fputs ("<<=", file); break;
4625 fputs ("<<", file); break;
4627 fputs (">", file); break;
4629 fputs (">=", file); break;
4631 fputs (">>=", file); break;
4633 fputs (">>", file); break;
4638 case 'B': /* Condition, (B)oth swapped and negate. */
4639 switch (GET_CODE (x))
4642 fputs ("<>", file); break;
4644 fputs ("=", file); break;
4646 fputs (">=", file); break;
4648 fputs (">", file); break;
4650 fputs (">>", file); break;
4652 fputs (">>=", file); break;
4654 fputs ("<=", file); break;
4656 fputs ("<", file); break;
4658 fputs ("<<", file); break;
4660 fputs ("<<=", file); break;
4666 if (GET_CODE (x) == CONST_INT)
4668 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4673 if (GET_CODE (x) == CONST_INT)
4675 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4680 if (GET_CODE (x) == CONST_INT)
4682 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4687 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4689 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4694 if (GET_CODE (x) == CONST_INT)
4696 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4701 if (GET_CODE (x) == CONST_INT)
4703 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4708 if (GET_CODE (x) == CONST_INT)
4713 switch (GET_CODE (XEXP (x, 0)))
4717 if (ASSEMBLER_DIALECT == 0)
4718 fputs ("s,mb", file);
4720 fputs (",mb", file);
4724 if (ASSEMBLER_DIALECT == 0)
4725 fputs ("s,ma", file);
4727 fputs (",ma", file);
4730 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4731 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4733 if (ASSEMBLER_DIALECT == 0)
4734 fputs ("x,s", file);
4738 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4742 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4748 output_global_address (file, x, 0);
4751 output_global_address (file, x, 1);
4753 case 0: /* Don't do anything special */
4758 compute_zdepwi_operands (INTVAL (x), op);
4759 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4765 compute_zdepdi_operands (INTVAL (x), op);
4766 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4770 /* We can get here from a .vtable_inherit due to our
4771 CONSTANT_ADDRESS_P rejecting perfectly good constant
4777 if (GET_CODE (x) == REG)
4779 fputs (reg_names [REGNO (x)], file);
4780 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4786 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4787 && (REGNO (x) & 1) == 0)
4790 else if (GET_CODE (x) == MEM)
4792 int size = GET_MODE_SIZE (GET_MODE (x));
4793 rtx base = NULL_RTX;
4794 switch (GET_CODE (XEXP (x, 0)))
4798 base = XEXP (XEXP (x, 0), 0);
4799 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4803 base = XEXP (XEXP (x, 0), 0);
4804 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4807 if (GET_CODE (XEXP (x, 0)) == PLUS
4808 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4809 fprintf (file, "%s(%s)",
4810 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4811 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4812 else if (GET_CODE (XEXP (x, 0)) == PLUS
4813 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4814 fprintf (file, "%s(%s)",
4815 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4816 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4818 output_address (XEXP (x, 0));
4823 output_addr_const (file, x);
4826 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4829 output_global_address (file, x, round_constant)
4835 /* Imagine (high (const (plus ...))). */
4836 if (GET_CODE (x) == HIGH)
4839 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4840 assemble_name (file, XSTR (x, 0));
4841 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4843 assemble_name (file, XSTR (x, 0));
4844 fputs ("-$global$", file);
4846 else if (GET_CODE (x) == CONST)
4848 const char *sep = "";
4849 int offset = 0; /* assembler wants -$global$ at end */
4850 rtx base = NULL_RTX;
4852 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4854 base = XEXP (XEXP (x, 0), 0);
4855 output_addr_const (file, base);
4857 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4858 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4861 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4863 base = XEXP (XEXP (x, 0), 1);
4864 output_addr_const (file, base);
4866 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4867 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4870 /* How bogus. The compiler is apparently responsible for
4871 rounding the constant if it uses an LR field selector.
4873 The linker and/or assembler seem a better place since
4874 they have to do this kind of thing already.
4876 If we fail to do this, HP's optimizing linker may eliminate
4877 an addil, but not update the ldw/stw/ldo instruction that
4878 uses the result of the addil. */
4880 offset = ((offset + 0x1000) & ~0x1fff);
4882 if (GET_CODE (XEXP (x, 0)) == PLUS)
4892 else if (GET_CODE (XEXP (x, 0)) == MINUS
4893 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4897 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4898 fputs ("-$global$", file);
4900 fprintf (file, "%s%d", sep, offset);
4903 output_addr_const (file, x);
4906 static struct deferred_plabel *
4912 /* See if we have already put this function on the list of deferred
4913 plabels. This list is generally small, so a liner search is not
4914 too ugly. If it proves too slow replace it with something faster. */
4915 for (i = 0; i < n_deferred_plabels; i++)
4916 if (strcmp (fname, deferred_plabels[i].name) == 0)
4919 /* If the deferred plabel list is empty, or this entry was not found
4920 on the list, create a new entry on the list. */
4921 if (deferred_plabels == NULL || i == n_deferred_plabels)
4923 const char *real_name;
4925 if (deferred_plabels == 0)
4926 deferred_plabels = (struct deferred_plabel *)
4927 ggc_alloc (sizeof (struct deferred_plabel));
4929 deferred_plabels = (struct deferred_plabel *)
4930 ggc_realloc (deferred_plabels,
4931 ((n_deferred_plabels + 1)
4932 * sizeof (struct deferred_plabel)));
4934 i = n_deferred_plabels++;
4935 deferred_plabels[i].internal_label = gen_label_rtx ();
4936 deferred_plabels[i].name = ggc_strdup (fname);
4938 /* Gross. We have just implicitly taken the address of this function,
4940 real_name = (*targetm.strip_name_encoding) (fname);
4941 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
4944 return &deferred_plabels[i];
4948 output_deferred_plabels (file)
4952 /* If we have deferred plabels, then we need to switch into the data
4953 section and align it to a 4 byte boundary before we output the
4954 deferred plabels. */
4955 if (n_deferred_plabels)
4958 ASM_OUTPUT_ALIGN (file, TARGET_64BIT ? 3 : 2);
4961 /* Now output the deferred plabels. */
4962 for (i = 0; i < n_deferred_plabels; i++)
4964 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4965 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4966 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4970 /* HP's millicode routines mean something special to the assembler.
4971 Keep track of which ones we have used. */
4973 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
4974 static void import_milli PARAMS ((enum millicodes));
4975 static char imported[(int) end1000];
4976 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
4977 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4978 #define MILLI_START 10
4982 enum millicodes code;
4984 char str[sizeof (import_string)];
4986 if (!imported[(int) code])
4988 imported[(int) code] = 1;
4989 strcpy (str, import_string);
4990 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4991 output_asm_insn (str, 0);
4995 /* The register constraints have put the operands and return value in
4996 the proper registers. */
4999 output_mul_insn (unsignedp, insn)
5000 int unsignedp ATTRIBUTE_UNUSED;
5003 import_milli (mulI);
5004 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5007 /* Emit the rtl for doing a division by a constant. */
5009 /* Do magic division millicodes exist for this value? */
5010 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5013 /* We'll use an array to keep track of the magic millicodes and
5014 whether or not we've used them already. [n][0] is signed, [n][1] is
5017 static int div_milli[16][2];
5020 div_operand (op, mode)
5022 enum machine_mode mode;
5024 return (mode == SImode
5025 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5026 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5027 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5031 emit_hpdiv_const (operands, unsignedp)
5035 if (GET_CODE (operands[2]) == CONST_INT
5036 && INTVAL (operands[2]) > 0
5037 && INTVAL (operands[2]) < 16
5038 && magic_milli[INTVAL (operands[2])])
5040 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5042 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5045 (PARALLEL, VOIDmode,
5046 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5047 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5049 gen_rtx_REG (SImode, 26),
5051 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5052 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5053 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5054 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5055 gen_rtx_CLOBBER (VOIDmode, ret))));
5056 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5063 output_div_insn (operands, unsignedp, insn)
5070 /* If the divisor is a constant, try to use one of the special
5072 if (GET_CODE (operands[0]) == CONST_INT)
5074 static char buf[100];
5075 divisor = INTVAL (operands[0]);
5076 if (!div_milli[divisor][unsignedp])
5078 div_milli[divisor][unsignedp] = 1;
5080 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5082 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5086 sprintf (buf, "$$divU_");
5087 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
5088 return output_millicode_call (insn,
5089 gen_rtx_SYMBOL_REF (SImode, buf));
5093 sprintf (buf, "$$divI_");
5094 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
5095 return output_millicode_call (insn,
5096 gen_rtx_SYMBOL_REF (SImode, buf));
5099 /* Divisor isn't a special constant. */
5104 import_milli (divU);
5105 return output_millicode_call (insn,
5106 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5110 import_milli (divI);
5111 return output_millicode_call (insn,
5112 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5117 /* Output a $$rem millicode to do mod. */
5120 output_mod_insn (unsignedp, insn)
5126 import_milli (remU);
5127 return output_millicode_call (insn,
5128 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5132 import_milli (remI);
5133 return output_millicode_call (insn,
5134 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5139 output_arg_descriptor (call_insn)
5142 const char *arg_regs[4];
5143 enum machine_mode arg_mode;
5145 int i, output_flag = 0;
5148 /* We neither need nor want argument location descriptors for the
5149 64bit runtime environment or the ELF32 environment. */
5150 if (TARGET_64BIT || TARGET_ELF32)
5153 for (i = 0; i < 4; i++)
5156 /* Specify explicitly that no argument relocations should take place
5157 if using the portable runtime calling conventions. */
5158 if (TARGET_PORTABLE_RUNTIME)
5160 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5165 if (GET_CODE (call_insn) != CALL_INSN)
5167 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5169 rtx use = XEXP (link, 0);
5171 if (! (GET_CODE (use) == USE
5172 && GET_CODE (XEXP (use, 0)) == REG
5173 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5176 arg_mode = GET_MODE (XEXP (use, 0));
5177 regno = REGNO (XEXP (use, 0));
5178 if (regno >= 23 && regno <= 26)
5180 arg_regs[26 - regno] = "GR";
5181 if (arg_mode == DImode)
5182 arg_regs[25 - regno] = "GR";
5184 else if (regno >= 32 && regno <= 39)
5186 if (arg_mode == SFmode)
5187 arg_regs[(regno - 32) / 2] = "FR";
5190 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5191 arg_regs[(regno - 34) / 2] = "FR";
5192 arg_regs[(regno - 34) / 2 + 1] = "FU";
5194 arg_regs[(regno - 34) / 2] = "FU";
5195 arg_regs[(regno - 34) / 2 + 1] = "FR";
5200 fputs ("\t.CALL ", asm_out_file);
5201 for (i = 0; i < 4; i++)
5206 fputc (',', asm_out_file);
5207 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5210 fputc ('\n', asm_out_file);
5213 /* Return the class of any secondary reload register that is needed to
5214 move IN into a register in class CLASS using mode MODE.
5216 Profiling has showed this routine and its descendants account for
5217 a significant amount of compile time (~7%). So it has been
5218 optimized to reduce redundant computations and eliminate useless
5221 It might be worthwhile to try and make this a leaf function too. */
5224 secondary_reload_class (class, mode, in)
5225 enum reg_class class;
5226 enum machine_mode mode;
5229 int regno, is_symbolic;
5231 /* Trying to load a constant into a FP register during PIC code
5232 generation will require %r1 as a scratch register. */
5234 && GET_MODE_CLASS (mode) == MODE_INT
5235 && FP_REG_CLASS_P (class)
5236 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5239 /* Profiling showed the PA port spends about 1.3% of its compilation
5240 time in true_regnum from calls inside secondary_reload_class. */
5242 if (GET_CODE (in) == REG)
5245 if (regno >= FIRST_PSEUDO_REGISTER)
5246 regno = true_regnum (in);
5248 else if (GET_CODE (in) == SUBREG)
5249 regno = true_regnum (in);
5253 /* If we have something like (mem (mem (...)), we can safely assume the
5254 inner MEM will end up in a general register after reloading, so there's
5255 no need for a secondary reload. */
5256 if (GET_CODE (in) == MEM
5257 && GET_CODE (XEXP (in, 0)) == MEM)
5260 /* Handle out of range displacement for integer mode loads/stores of
5262 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5263 && GET_MODE_CLASS (mode) == MODE_INT
5264 && FP_REG_CLASS_P (class))
5265 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5266 return GENERAL_REGS;
5268 /* A SAR<->FP register copy requires a secondary register (GPR) as
5269 well as secondary memory. */
5270 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5271 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5272 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5273 return GENERAL_REGS;
5275 if (GET_CODE (in) == HIGH)
5278 /* Profiling has showed GCC spends about 2.6% of its compilation
5279 time in symbolic_operand from calls inside secondary_reload_class.
5281 We use an inline copy and only compute its return value once to avoid
5283 switch (GET_CODE (in))
5293 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5294 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5295 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5305 && read_only_operand (in, VOIDmode))
5308 if (class != R1_REGS && is_symbolic)
5315 function_arg_padding (mode, type)
5316 enum machine_mode mode;
5320 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5322 /* Return none if justification is not required. */
5324 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5325 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5328 /* The directions set here are ignored when a BLKmode argument larger
5329 than a word is placed in a register. Different code is used for
5330 the stack and registers. This makes it difficult to have a
5331 consistent data representation for both the stack and registers.
5332 For both runtimes, the justification and padding for arguments on
5333 the stack and in registers should be identical. */
5335 /* The 64-bit runtime specifies left justification for aggregates. */
5338 /* The 32-bit runtime architecture specifies right justification.
5339 When the argument is passed on the stack, the argument is padded
5340 with garbage on the left. The HP compiler pads with zeros. */
5344 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5351 /* Do what is necessary for `va_start'. We look at the current function
5352 to determine if stdargs or varargs is used and fill in an initial
5353 va_list. A pointer to this constructor is returned. */
5356 hppa_builtin_saveregs ()
5359 tree fntype = TREE_TYPE (current_function_decl);
5360 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5361 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5362 != void_type_node)))
5363 ? UNITS_PER_WORD : 0);
5366 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5368 offset = current_function_arg_offset_rtx;
5374 /* Adjust for varargs/stdarg differences. */
5376 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5378 offset = current_function_arg_offset_rtx;
5380 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5381 from the incoming arg pointer and growing to larger addresses. */
5382 for (i = 26, off = -64; i >= 19; i--, off += 8)
5383 emit_move_insn (gen_rtx_MEM (word_mode,
5384 plus_constant (arg_pointer_rtx, off)),
5385 gen_rtx_REG (word_mode, i));
5387 /* The incoming args pointer points just beyond the flushback area;
5388 normally this is not a serious concern. However, when we are doing
5389 varargs/stdargs we want to make the arg pointer point to the start
5390 of the incoming argument area. */
5391 emit_move_insn (virtual_incoming_args_rtx,
5392 plus_constant (arg_pointer_rtx, -64));
5394 /* Now return a pointer to the first anonymous argument. */
5395 return copy_to_reg (expand_binop (Pmode, add_optab,
5396 virtual_incoming_args_rtx,
5397 offset, 0, 0, OPTAB_LIB_WIDEN));
5400 /* Store general registers on the stack. */
5401 dest = gen_rtx_MEM (BLKmode,
5402 plus_constant (current_function_internal_arg_pointer,
5404 set_mem_alias_set (dest, get_varargs_alias_set ());
5405 set_mem_align (dest, BITS_PER_WORD);
5406 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5408 /* move_block_from_reg will emit code to store the argument registers
5409 individually as scalar stores.
5411 However, other insns may later load from the same addresses for
5412 a structure load (passing a struct to a varargs routine).
5414 The alias code assumes that such aliasing can never happen, so we
5415 have to keep memory referencing insns from moving up beyond the
5416 last argument register store. So we emit a blockage insn here. */
5417 emit_insn (gen_blockage ());
5419 return copy_to_reg (expand_binop (Pmode, add_optab,
5420 current_function_internal_arg_pointer,
5421 offset, 0, 0, OPTAB_LIB_WIDEN));
5425 hppa_va_start (valist, nextarg)
5429 nextarg = expand_builtin_saveregs ();
5430 std_expand_builtin_va_start (valist, nextarg);
5434 hppa_va_arg (valist, type)
5437 HOST_WIDE_INT size = int_size_in_bytes (type);
5443 /* Every argument in PA64 is supposed to be passed by value
5444 (including large structs). However, as a GCC extension, we
5445 pass zero and variable sized arguments by reference. Empty
5446 structures are a GCC extension not supported by the HP
5447 compilers. Thus, passing them by reference isn't likely
5448 to conflict with the ABI. For variable sized arguments,
5449 GCC doesn't have the infrastructure to allocate these to
5452 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5454 if (size > UNITS_PER_WORD)
5456 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5457 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5458 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5459 build_int_2 (-2 * UNITS_PER_WORD, -1));
5460 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5461 TREE_SIDE_EFFECTS (t) = 1;
5462 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5466 return std_expand_builtin_va_arg (valist, type);
5469 ptr = build_pointer_type (type);
5471 /* Args grow upward. */
5472 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5473 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5474 TREE_SIDE_EFFECTS (t) = 1;
5476 pptr = build_pointer_type (ptr);
5477 t = build1 (NOP_EXPR, pptr, t);
5478 TREE_SIDE_EFFECTS (t) = 1;
5480 t = build1 (INDIRECT_REF, ptr, t);
5481 TREE_SIDE_EFFECTS (t) = 1;
5484 else /* !TARGET_64BIT */
5486 ptr = build_pointer_type (type);
5488 /* "Large" and variable sized types are passed by reference. */
5489 if (size > 8 || size <= 0)
5491 /* Args grow downward. */
5492 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5493 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5494 TREE_SIDE_EFFECTS (t) = 1;
5496 pptr = build_pointer_type (ptr);
5497 t = build1 (NOP_EXPR, pptr, t);
5498 TREE_SIDE_EFFECTS (t) = 1;
5500 t = build1 (INDIRECT_REF, ptr, t);
5501 TREE_SIDE_EFFECTS (t) = 1;
5505 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5506 build_int_2 (-size, -1));
5508 /* Copied from va-pa.h, but we probably don't need to align to
5509 word size, since we generate and preserve that invariant. */
5510 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5511 build_int_2 ((size > 4 ? -8 : -4), -1));
5513 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5514 TREE_SIDE_EFFECTS (t) = 1;
5516 ofs = (8 - size) % 4;
5519 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
5520 build_int_2 (ofs, 0));
5521 TREE_SIDE_EFFECTS (t) = 1;
5524 t = build1 (NOP_EXPR, ptr, t);
5525 TREE_SIDE_EFFECTS (t) = 1;
5530 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
5535 /* This routine handles all the normal conditional branch sequences we
5536 might need to generate. It handles compare immediate vs compare
5537 register, nullification of delay slots, varying length branches,
5538 negated branches, and all combinations of the above. It returns the
5539 output appropriate to emit the branch corresponding to all given
5543 output_cbranch (operands, nullify, length, negated, insn)
5545 int nullify, length, negated;
5548 static char buf[100];
5552 /* A conditional branch to the following instruction (eg the delay slot)
5553 is asking for a disaster. This can happen when not optimizing and
5554 when jump optimization fails.
5556 While it is usually safe to emit nothing, this can fail if the
5557 preceding instruction is a nullified branch with an empty delay
5558 slot and the same branch target as this branch. We could check
5559 for this but jump optimization should eliminate nop jumps. It
5560 is always safe to emit a nop. */
5561 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5564 /* If this is a long branch with its delay slot unfilled, set `nullify'
5565 as it can nullify the delay slot and save a nop. */
5566 if (length == 8 && dbr_sequence_length () == 0)
5569 /* If this is a short forward conditional branch which did not get
5570 its delay slot filled, the delay slot can still be nullified. */
5571 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5572 nullify = forward_branch_p (insn);
5574 /* A forward branch over a single nullified insn can be done with a
5575 comclr instruction. This avoids a single cycle penalty due to
5576 mis-predicted branch if we fall through (branch not taken). */
5578 && next_real_insn (insn) != 0
5579 && get_attr_length (next_real_insn (insn)) == 4
5580 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5586 /* All short conditional branches except backwards with an unfilled
5590 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5592 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5593 if (GET_MODE (operands[1]) == DImode)
5596 strcat (buf, "%B3");
5598 strcat (buf, "%S3");
5600 strcat (buf, " %2,%r1,%%r0");
5602 strcat (buf, ",n %2,%r1,%0");
5604 strcat (buf, " %2,%r1,%0");
5607 /* All long conditionals. Note a short backward branch with an
5608 unfilled delay slot is treated just like a long backward branch
5609 with an unfilled delay slot. */
5611 /* Handle weird backwards branch with a filled delay slot
5612 with is nullified. */
5613 if (dbr_sequence_length () != 0
5614 && ! forward_branch_p (insn)
5617 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5618 if (GET_MODE (operands[1]) == DImode)
5621 strcat (buf, "%S3");
5623 strcat (buf, "%B3");
5624 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5626 /* Handle short backwards branch with an unfilled delay slot.
5627 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5628 taken and untaken branches. */
5629 else if (dbr_sequence_length () == 0
5630 && ! forward_branch_p (insn)
5631 && INSN_ADDRESSES_SET_P ()
5632 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5633 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5635 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5636 if (GET_MODE (operands[1]) == DImode)
5639 strcat (buf, "%B3 %2,%r1,%0%#");
5641 strcat (buf, "%S3 %2,%r1,%0%#");
5645 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5646 if (GET_MODE (operands[1]) == DImode)
5649 strcat (buf, "%S3");
5651 strcat (buf, "%B3");
5653 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5655 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5661 xoperands[0] = operands[0];
5662 xoperands[1] = operands[1];
5663 xoperands[2] = operands[2];
5664 xoperands[3] = operands[3];
5666 /* The reversed conditional branch must branch over one additional
5667 instruction if the delay slot is filled. If the delay slot
5668 is empty, the instruction after the reversed condition branch
5669 must be nullified. */
5670 nullify = dbr_sequence_length () == 0;
5671 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
5673 /* Create a reversed conditional branch which branches around
5674 the following insns. */
5675 if (GET_MODE (operands[1]) != DImode)
5681 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
5684 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
5690 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
5693 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
5702 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
5705 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
5711 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
5714 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
5718 output_asm_insn (buf, xoperands);
5719 return output_lbranch (operands[0], insn);
5727 /* This routine handles long unconditional branches that exceed the
5728 maximum range of a simple branch instruction. */
5731 output_lbranch (dest, insn)
5736 xoperands[0] = dest;
5738 /* First, free up the delay slot. */
5739 if (dbr_sequence_length () != 0)
5741 /* We can't handle a jump in the delay slot. */
5742 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
5745 final_scan_insn (NEXT_INSN (insn), asm_out_file,
5748 /* Now delete the delay insn. */
5749 PUT_CODE (NEXT_INSN (insn), NOTE);
5750 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5751 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5754 /* Output an insn to save %r1. The runtime documentation doesn't
5755 specify whether the "Clean Up" slot in the callers frame can
5756 be clobbered by the callee. It isn't copied by HP's builtin
5757 alloca, so this suggests that it can be clobbered if necessary.
5758 The "Static Link" location is copied by HP builtin alloca, so
5759 we avoid using it. Using the cleanup slot might be a problem
5760 if we have to interoperate with languages that pass cleanup
5761 information. However, it should be possible to handle these
5762 situations with GCC's asm feature.
5764 The "Current RP" slot is reserved for the called procedure, so
5765 we try to use it when we don't have a frame of our own. It's
5766 rather unlikely that we won't have a frame when we need to emit
5769 Really the way to go long term is a register scavenger; goto
5770 the target of the jump and find a register which we can use
5771 as a scratch to hold the value in %r1. Then, we wouldn't have
5772 to free up the delay slot or clobber a slot that may be needed
5773 for other purposes. */
5776 if (actual_fsize == 0 && !regs_ever_live[2])
5777 /* Use the return pointer slot in the frame marker. */
5778 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
5780 /* Use the slot at -40 in the frame marker since HP builtin
5781 alloca doesn't copy it. */
5782 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
5786 if (actual_fsize == 0 && !regs_ever_live[2])
5787 /* Use the return pointer slot in the frame marker. */
5788 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
5790 /* Use the "Clean Up" slot in the frame marker. In GCC,
5791 the only other use of this location is for copying a
5792 floating point double argument from a floating-point
5793 register to two general registers. The copy is done
5794 as an "atomic" operation when outputing a call, so it
5795 won't interfere with our using the location here. */
5796 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
5801 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5802 if (TARGET_SOM || !TARGET_GAS)
5804 xoperands[1] = gen_label_rtx ();
5805 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
5806 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5807 CODE_LABEL_NUMBER (xoperands[1]));
5808 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
5812 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5813 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
5815 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5818 /* Now output a very long branch to the original target. */
5819 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
5821 /* Now restore the value of %r1 in the delay slot. */
5824 if (actual_fsize == 0 && !regs_ever_live[2])
5825 return "ldd -16(%%r30),%%r1";
5827 return "ldd -40(%%r30),%%r1";
5831 if (actual_fsize == 0 && !regs_ever_live[2])
5832 return "ldw -20(%%r30),%%r1";
5834 return "ldw -12(%%r30),%%r1";
5838 /* This routine handles all the branch-on-bit conditional branch sequences we
5839 might need to generate. It handles nullification of delay slots,
5840 varying length branches, negated branches and all combinations of the
5841 above. it returns the appropriate output template to emit the branch. */
5844 output_bb (operands, nullify, length, negated, insn, which)
5845 rtx *operands ATTRIBUTE_UNUSED;
5846 int nullify, length, negated;
5850 static char buf[100];
5853 /* A conditional branch to the following instruction (eg the delay slot) is
5854 asking for a disaster. I do not think this can happen as this pattern
5855 is only used when optimizing; jump optimization should eliminate the
5856 jump. But be prepared just in case. */
5858 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5861 /* If this is a long branch with its delay slot unfilled, set `nullify'
5862 as it can nullify the delay slot and save a nop. */
5863 if (length == 8 && dbr_sequence_length () == 0)
5866 /* If this is a short forward conditional branch which did not get
5867 its delay slot filled, the delay slot can still be nullified. */
5868 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5869 nullify = forward_branch_p (insn);
5871 /* A forward branch over a single nullified insn can be done with a
5872 extrs instruction. This avoids a single cycle penalty due to
5873 mis-predicted branch if we fall through (branch not taken). */
5876 && next_real_insn (insn) != 0
5877 && get_attr_length (next_real_insn (insn)) == 4
5878 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5885 /* All short conditional branches except backwards with an unfilled
5889 strcpy (buf, "{extrs,|extrw,s,}");
5891 strcpy (buf, "bb,");
5892 if (useskip && GET_MODE (operands[0]) == DImode)
5893 strcpy (buf, "extrd,s,*");
5894 else if (GET_MODE (operands[0]) == DImode)
5895 strcpy (buf, "bb,*");
5896 if ((which == 0 && negated)
5897 || (which == 1 && ! negated))
5902 strcat (buf, " %0,%1,1,%%r0");
5903 else if (nullify && negated)
5904 strcat (buf, ",n %0,%1,%3");
5905 else if (nullify && ! negated)
5906 strcat (buf, ",n %0,%1,%2");
5907 else if (! nullify && negated)
5908 strcat (buf, "%0,%1,%3");
5909 else if (! nullify && ! negated)
5910 strcat (buf, " %0,%1,%2");
5913 /* All long conditionals. Note a short backward branch with an
5914 unfilled delay slot is treated just like a long backward branch
5915 with an unfilled delay slot. */
5917 /* Handle weird backwards branch with a filled delay slot
5918 with is nullified. */
5919 if (dbr_sequence_length () != 0
5920 && ! forward_branch_p (insn)
5923 strcpy (buf, "bb,");
5924 if (GET_MODE (operands[0]) == DImode)
5926 if ((which == 0 && negated)
5927 || (which == 1 && ! negated))
5932 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5934 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5936 /* Handle short backwards branch with an unfilled delay slot.
5937 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5938 taken and untaken branches. */
5939 else if (dbr_sequence_length () == 0
5940 && ! forward_branch_p (insn)
5941 && INSN_ADDRESSES_SET_P ()
5942 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5943 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5945 strcpy (buf, "bb,");
5946 if (GET_MODE (operands[0]) == DImode)
5948 if ((which == 0 && negated)
5949 || (which == 1 && ! negated))
5954 strcat (buf, " %0,%1,%3%#");
5956 strcat (buf, " %0,%1,%2%#");
5960 strcpy (buf, "{extrs,|extrw,s,}");
5961 if (GET_MODE (operands[0]) == DImode)
5962 strcpy (buf, "extrd,s,*");
5963 if ((which == 0 && negated)
5964 || (which == 1 && ! negated))
5968 if (nullify && negated)
5969 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5970 else if (nullify && ! negated)
5971 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5973 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5975 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5985 /* This routine handles all the branch-on-variable-bit conditional branch
5986 sequences we might need to generate. It handles nullification of delay
5987 slots, varying length branches, negated branches and all combinations
5988 of the above. it returns the appropriate output template to emit the
5992 output_bvb (operands, nullify, length, negated, insn, which)
5993 rtx *operands ATTRIBUTE_UNUSED;
5994 int nullify, length, negated;
5998 static char buf[100];
6001 /* A conditional branch to the following instruction (eg the delay slot) is
6002 asking for a disaster. I do not think this can happen as this pattern
6003 is only used when optimizing; jump optimization should eliminate the
6004 jump. But be prepared just in case. */
6006 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6009 /* If this is a long branch with its delay slot unfilled, set `nullify'
6010 as it can nullify the delay slot and save a nop. */
6011 if (length == 8 && dbr_sequence_length () == 0)
6014 /* If this is a short forward conditional branch which did not get
6015 its delay slot filled, the delay slot can still be nullified. */
6016 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6017 nullify = forward_branch_p (insn);
6019 /* A forward branch over a single nullified insn can be done with a
6020 extrs instruction. This avoids a single cycle penalty due to
6021 mis-predicted branch if we fall through (branch not taken). */
6024 && next_real_insn (insn) != 0
6025 && get_attr_length (next_real_insn (insn)) == 4
6026 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6033 /* All short conditional branches except backwards with an unfilled
6037 strcpy (buf, "{vextrs,|extrw,s,}");
6039 strcpy (buf, "{bvb,|bb,}");
6040 if (useskip && GET_MODE (operands[0]) == DImode)
6041 strcpy (buf, "extrd,s,*}");
6042 else if (GET_MODE (operands[0]) == DImode)
6043 strcpy (buf, "bb,*");
6044 if ((which == 0 && negated)
6045 || (which == 1 && ! negated))
6050 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6051 else if (nullify && negated)
6052 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6053 else if (nullify && ! negated)
6054 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6055 else if (! nullify && negated)
6056 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6057 else if (! nullify && ! negated)
6058 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6061 /* All long conditionals. Note a short backward branch with an
6062 unfilled delay slot is treated just like a long backward branch
6063 with an unfilled delay slot. */
6065 /* Handle weird backwards branch with a filled delay slot
6066 with is nullified. */
6067 if (dbr_sequence_length () != 0
6068 && ! forward_branch_p (insn)
6071 strcpy (buf, "{bvb,|bb,}");
6072 if (GET_MODE (operands[0]) == DImode)
6074 if ((which == 0 && negated)
6075 || (which == 1 && ! negated))
6080 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6082 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6084 /* Handle short backwards branch with an unfilled delay slot.
6085 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6086 taken and untaken branches. */
6087 else if (dbr_sequence_length () == 0
6088 && ! forward_branch_p (insn)
6089 && INSN_ADDRESSES_SET_P ()
6090 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6091 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6093 strcpy (buf, "{bvb,|bb,}");
6094 if (GET_MODE (operands[0]) == DImode)
6096 if ((which == 0 && negated)
6097 || (which == 1 && ! negated))
6102 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6104 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6108 strcpy (buf, "{vextrs,|extrw,s,}");
6109 if (GET_MODE (operands[0]) == DImode)
6110 strcpy (buf, "extrd,s,*");
6111 if ((which == 0 && negated)
6112 || (which == 1 && ! negated))
6116 if (nullify && negated)
6117 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6118 else if (nullify && ! negated)
6119 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6121 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6123 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6133 /* Return the output template for emitting a dbra type insn.
6135 Note it may perform some output operations on its own before
6136 returning the final output string. */
6138 output_dbra (operands, insn, which_alternative)
6141 int which_alternative;
6144 /* A conditional branch to the following instruction (eg the delay slot) is
6145 asking for a disaster. Be prepared! */
6147 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6149 if (which_alternative == 0)
6150 return "ldo %1(%0),%0";
6151 else if (which_alternative == 1)
6153 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6154 output_asm_insn ("ldw -16(%%r30),%4", operands);
6155 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6156 return "{fldws|fldw} -16(%%r30),%0";
6160 output_asm_insn ("ldw %0,%4", operands);
6161 return "ldo %1(%4),%4\n\tstw %4,%0";
6165 if (which_alternative == 0)
6167 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6168 int length = get_attr_length (insn);
6170 /* If this is a long branch with its delay slot unfilled, set `nullify'
6171 as it can nullify the delay slot and save a nop. */
6172 if (length == 8 && dbr_sequence_length () == 0)
6175 /* If this is a short forward conditional branch which did not get
6176 its delay slot filled, the delay slot can still be nullified. */
6177 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6178 nullify = forward_branch_p (insn);
6180 /* Handle short versions first. */
6181 if (length == 4 && nullify)
6182 return "addib,%C2,n %1,%0,%3";
6183 else if (length == 4 && ! nullify)
6184 return "addib,%C2 %1,%0,%3";
6185 else if (length == 8)
6187 /* Handle weird backwards branch with a fulled delay slot
6188 which is nullified. */
6189 if (dbr_sequence_length () != 0
6190 && ! forward_branch_p (insn)
6192 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6193 /* Handle short backwards branch with an unfilled delay slot.
6194 Using a addb;nop rather than addi;bl saves 1 cycle for both
6195 taken and untaken branches. */
6196 else if (dbr_sequence_length () == 0
6197 && ! forward_branch_p (insn)
6198 && INSN_ADDRESSES_SET_P ()
6199 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6200 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6201 return "addib,%C2 %1,%0,%3%#";
6203 /* Handle normal cases. */
6205 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6207 return "addi,%N2 %1,%0,%0\n\tb %3";
6212 /* Deal with gross reload from FP register case. */
6213 else if (which_alternative == 1)
6215 /* Move loop counter from FP register to MEM then into a GR,
6216 increment the GR, store the GR into MEM, and finally reload
6217 the FP register from MEM from within the branch's delay slot. */
6218 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6220 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6221 if (get_attr_length (insn) == 24)
6222 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6224 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6226 /* Deal with gross reload from memory case. */
6229 /* Reload loop counter from memory, the store back to memory
6230 happens in the branch's delay slot. */
6231 output_asm_insn ("ldw %0,%4", operands);
6232 if (get_attr_length (insn) == 12)
6233 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6235 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6239 /* Return the output template for emitting a dbra type insn.
6241 Note it may perform some output operations on its own before
6242 returning the final output string. */
6244 output_movb (operands, insn, which_alternative, reverse_comparison)
6247 int which_alternative;
6248 int reverse_comparison;
6251 /* A conditional branch to the following instruction (eg the delay slot) is
6252 asking for a disaster. Be prepared! */
6254 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6256 if (which_alternative == 0)
6257 return "copy %1,%0";
6258 else if (which_alternative == 1)
6260 output_asm_insn ("stw %1,-16(%%r30)", operands);
6261 return "{fldws|fldw} -16(%%r30),%0";
6263 else if (which_alternative == 2)
6269 /* Support the second variant. */
6270 if (reverse_comparison)
6271 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6273 if (which_alternative == 0)
6275 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6276 int length = get_attr_length (insn);
6278 /* If this is a long branch with its delay slot unfilled, set `nullify'
6279 as it can nullify the delay slot and save a nop. */
6280 if (length == 8 && dbr_sequence_length () == 0)
6283 /* If this is a short forward conditional branch which did not get
6284 its delay slot filled, the delay slot can still be nullified. */
6285 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6286 nullify = forward_branch_p (insn);
6288 /* Handle short versions first. */
6289 if (length == 4 && nullify)
6290 return "movb,%C2,n %1,%0,%3";
6291 else if (length == 4 && ! nullify)
6292 return "movb,%C2 %1,%0,%3";
6293 else if (length == 8)
6295 /* Handle weird backwards branch with a filled delay slot
6296 which is nullified. */
6297 if (dbr_sequence_length () != 0
6298 && ! forward_branch_p (insn)
6300 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6302 /* Handle short backwards branch with an unfilled delay slot.
6303 Using a movb;nop rather than or;bl saves 1 cycle for both
6304 taken and untaken branches. */
6305 else if (dbr_sequence_length () == 0
6306 && ! forward_branch_p (insn)
6307 && INSN_ADDRESSES_SET_P ()
6308 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6309 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6310 return "movb,%C2 %1,%0,%3%#";
6311 /* Handle normal cases. */
6313 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6315 return "or,%N2 %1,%%r0,%0\n\tb %3";
6320 /* Deal with gross reload from FP register case. */
6321 else if (which_alternative == 1)
6323 /* Move loop counter from FP register to MEM then into a GR,
6324 increment the GR, store the GR into MEM, and finally reload
6325 the FP register from MEM from within the branch's delay slot. */
6326 output_asm_insn ("stw %1,-16(%%r30)", operands);
6327 if (get_attr_length (insn) == 12)
6328 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6330 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6332 /* Deal with gross reload from memory case. */
6333 else if (which_alternative == 2)
6335 /* Reload loop counter from memory, the store back to memory
6336 happens in the branch's delay slot. */
6337 if (get_attr_length (insn) == 8)
6338 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6340 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6342 /* Handle SAR as a destination. */
6345 if (get_attr_length (insn) == 8)
6346 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6348 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6352 /* Copy any FP arguments in INSN into integer registers. */
6360 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6362 int arg_mode, regno;
6363 rtx use = XEXP (link, 0);
6365 if (! (GET_CODE (use) == USE
6366 && GET_CODE (XEXP (use, 0)) == REG
6367 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6370 arg_mode = GET_MODE (XEXP (use, 0));
6371 regno = REGNO (XEXP (use, 0));
6373 /* Is it a floating point register? */
6374 if (regno >= 32 && regno <= 39)
6376 /* Copy the FP register into an integer register via memory. */
6377 if (arg_mode == SFmode)
6379 xoperands[0] = XEXP (use, 0);
6380 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6381 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6382 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6386 xoperands[0] = XEXP (use, 0);
6387 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6388 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6389 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6390 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6396 /* Compute length of the FP argument copy sequence for INSN. */
6398 length_fp_args (insn)
6404 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6406 int arg_mode, regno;
6407 rtx use = XEXP (link, 0);
6409 if (! (GET_CODE (use) == USE
6410 && GET_CODE (XEXP (use, 0)) == REG
6411 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6414 arg_mode = GET_MODE (XEXP (use, 0));
6415 regno = REGNO (XEXP (use, 0));
6417 /* Is it a floating point register? */
6418 if (regno >= 32 && regno <= 39)
6420 if (arg_mode == SFmode)
6430 /* Return the attribute length for the millicode call instruction INSN.
6431 The length must match the code generated by output_millicode_call.
6432 We include the delay slot in the returned length as it is better to
6433 over estimate the length than to under estimate it. */
6436 attr_length_millicode_call (insn)
6439 unsigned long distance = -1;
6441 if (INSN_ADDRESSES_SET_P ())
6443 distance = (total_code_bytes + insn_current_reference_address (insn));
6444 if (distance < total_code_bytes)
6450 if (!TARGET_LONG_CALLS && distance < 7600000)
6455 else if (TARGET_PORTABLE_RUNTIME)
6459 if (!TARGET_LONG_CALLS && distance < 240000)
6462 if (TARGET_LONG_ABS_CALL && !flag_pic)
6469 /* INSN is a function call. It may have an unconditional jump
6472 CALL_DEST is the routine we are calling. */
6475 output_millicode_call (insn, call_dest)
6479 int attr_length = get_attr_length (insn);
6480 int seq_length = dbr_sequence_length ();
6485 xoperands[0] = call_dest;
6486 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6488 /* Handle the common case where we are sure that the branch will
6489 reach the beginning of the $CODE$ subspace. The within reach
6490 form of the $$sh_func_adrs call has a length of 28. Because
6491 it has an attribute type of multi, it never has a nonzero
6492 sequence length. The length of the $$sh_func_adrs is the same
6493 as certain out of reach PIC calls to other routines. */
6494 if (!TARGET_LONG_CALLS
6495 && ((seq_length == 0
6496 && (attr_length == 12
6497 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6498 || (seq_length != 0 && attr_length == 8)))
6500 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6506 /* It might seem that one insn could be saved by accessing
6507 the millicode function using the linkage table. However,
6508 this doesn't work in shared libraries and other dynamically
6509 loaded objects. Using a pc-relative sequence also avoids
6510 problems related to the implicit use of the gp register. */
6511 output_asm_insn ("b,l .+8,%%r1", xoperands);
6515 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6516 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6520 xoperands[1] = gen_label_rtx ();
6521 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6522 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6523 CODE_LABEL_NUMBER (xoperands[1]));
6524 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6527 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6529 else if (TARGET_PORTABLE_RUNTIME)
6531 /* Pure portable runtime doesn't allow be/ble; we also don't
6532 have PIC support in the assembler/linker, so this sequence
6535 /* Get the address of our target into %r1. */
6536 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6537 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6539 /* Get our return address into %r31. */
6540 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6541 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6543 /* Jump to our target address in %r1. */
6544 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6548 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6550 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6552 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6556 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6557 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6559 if (TARGET_SOM || !TARGET_GAS)
6561 /* The HP assembler can generate relocations for the
6562 difference of two symbols. GAS can do this for a
6563 millicode symbol but not an arbitrary external
6564 symbol when generating SOM output. */
6565 xoperands[1] = gen_label_rtx ();
6566 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6567 CODE_LABEL_NUMBER (xoperands[1]));
6568 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6569 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6573 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6574 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6578 /* Jump to our target address in %r1. */
6579 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6583 if (seq_length == 0)
6584 output_asm_insn ("nop", xoperands);
6586 /* We are done if there isn't a jump in the delay slot. */
6587 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6590 /* This call has an unconditional jump in its delay slot. */
6591 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6593 /* See if the return address can be adjusted. Use the containing
6594 sequence insn's address. */
6595 if (INSN_ADDRESSES_SET_P ())
6597 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6598 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6599 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6601 if (VAL_14_BITS_P (distance))
6603 xoperands[1] = gen_label_rtx ();
6604 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6605 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6606 CODE_LABEL_NUMBER (xoperands[1]));
6609 /* ??? This branch may not reach its target. */
6610 output_asm_insn ("nop\n\tb,n %0", xoperands);
6613 /* ??? This branch may not reach its target. */
6614 output_asm_insn ("nop\n\tb,n %0", xoperands);
6616 /* Delete the jump. */
6617 PUT_CODE (NEXT_INSN (insn), NOTE);
6618 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6619 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6624 /* Return the attribute length of the call instruction INSN. The SIBCALL
6625 flag indicates whether INSN is a regular call or a sibling call. The
6626 length must match the code generated by output_call. We include the delay
6627 slot in the returned length as it is better to over estimate the length
6628 than to under estimate it. */
6631 attr_length_call (insn, sibcall)
6635 unsigned long distance = -1;
6637 if (INSN_ADDRESSES_SET_P ())
6639 distance = (total_code_bytes + insn_current_reference_address (insn));
6640 if (distance < total_code_bytes)
6646 if (!TARGET_LONG_CALLS
6647 && ((!sibcall && distance < 7600000) || distance < 240000))
6650 return (sibcall ? 28 : 24);
6654 if (!TARGET_LONG_CALLS
6655 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
6656 || distance < 240000))
6659 if (TARGET_LONG_ABS_CALL && !flag_pic)
6662 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6663 || (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6675 length += length_fp_args (insn);
6681 return (length + 32);
6683 if (!TARGET_NO_SPACE_REGS)
6689 return (length + 32);
6694 /* INSN is a function call. It may have an unconditional jump
6697 CALL_DEST is the routine we are calling. */
6700 output_call (insn, call_dest, sibcall)
6705 int delay_insn_deleted = 0;
6706 int delay_slot_filled = 0;
6707 int seq_length = dbr_sequence_length ();
6710 xoperands[0] = call_dest;
6712 /* Handle the common case where we're sure that the branch will reach
6713 the beginning of the $CODE$ subspace. */
6714 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
6716 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6717 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
6723 /* ??? As far as I can tell, the HP linker doesn't support the
6724 long pc-relative sequence described in the 64-bit runtime
6725 architecture. So, we use a slightly longer indirect call. */
6726 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6728 xoperands[0] = p->internal_label;
6729 xoperands[1] = gen_label_rtx ();
6731 /* If this isn't a sibcall, we put the load of %r27 into the
6732 delay slot. We can't do this in a sibcall as we don't
6733 have a second call-clobbered scratch register available. */
6735 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6738 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6741 /* Now delete the delay insn. */
6742 PUT_CODE (NEXT_INSN (insn), NOTE);
6743 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6744 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6745 delay_insn_deleted = 1;
6748 output_asm_insn ("addil LT'%0,%%r27", xoperands);
6749 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
6750 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
6754 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6755 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
6756 output_asm_insn ("bve (%%r1)", xoperands);
6760 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
6761 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
6762 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6763 delay_slot_filled = 1;
6768 int indirect_call = 0;
6770 /* Emit a long call. There are several different sequences
6771 of increasing length and complexity. In most cases,
6772 they don't allow an instruction in the delay slot. */
6773 if (!(TARGET_LONG_ABS_CALL && !flag_pic)
6774 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6775 && !(TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6779 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6781 && (!TARGET_PA_20 || indirect_call))
6783 /* A non-jump insn in the delay slot. By definition we can
6784 emit this insn before the call (and in fact before argument
6786 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6788 /* Now delete the delay insn. */
6789 PUT_CODE (NEXT_INSN (insn), NOTE);
6790 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6791 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6792 delay_insn_deleted = 1;
6795 if (TARGET_LONG_ABS_CALL && !flag_pic)
6797 /* This is the best sequence for making long calls in
6798 non-pic code. Unfortunately, GNU ld doesn't provide
6799 the stub needed for external calls, and GAS's support
6800 for this with the SOM linker is buggy. */
6801 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6803 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
6807 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
6810 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6812 output_asm_insn ("copy %%r31,%%r2", xoperands);
6813 delay_slot_filled = 1;
6818 if (TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6820 /* The HP assembler and linker can handle relocations
6821 for the difference of two symbols. GAS and the HP
6822 linker can't do this when one of the symbols is
6824 xoperands[1] = gen_label_rtx ();
6825 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6826 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6827 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6828 CODE_LABEL_NUMBER (xoperands[1]));
6829 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6831 else if (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL)
6833 /* GAS currently can't generate the relocations that
6834 are needed for the SOM linker under HP-UX using this
6835 sequence. The GNU linker doesn't generate the stubs
6836 that are needed for external calls on TARGET_ELF32
6837 with this sequence. For now, we have to use a
6838 longer plabel sequence when using GAS. */
6839 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6840 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
6842 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
6847 /* Emit a long plabel-based call sequence. This is
6848 essentially an inline implementation of $$dyncall.
6849 We don't actually try to call $$dyncall as this is
6850 as difficult as calling the function itself. */
6851 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6853 xoperands[0] = p->internal_label;
6854 xoperands[1] = gen_label_rtx ();
6856 /* Since the call is indirect, FP arguments in registers
6857 need to be copied to the general registers. Then, the
6858 argument relocation stub will copy them back. */
6860 copy_fp_args (insn);
6864 output_asm_insn ("addil LT'%0,%%r19", xoperands);
6865 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
6866 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
6870 output_asm_insn ("addil LR'%0-$global$,%%r27",
6872 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
6876 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
6877 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
6878 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
6879 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
6881 if (!sibcall && !TARGET_PA_20)
6883 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
6884 if (TARGET_NO_SPACE_REGS)
6885 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
6887 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
6894 output_asm_insn ("bve (%%r1)", xoperands);
6899 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6900 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
6901 delay_slot_filled = 1;
6904 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6909 if (!TARGET_NO_SPACE_REGS)
6910 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
6915 if (TARGET_NO_SPACE_REGS)
6916 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
6918 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
6922 if (TARGET_NO_SPACE_REGS)
6923 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
6925 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
6928 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
6930 output_asm_insn ("copy %%r31,%%r2", xoperands);
6931 delay_slot_filled = 1;
6938 if (seq_length == 0 || (delay_insn_deleted && !delay_slot_filled))
6939 output_asm_insn ("nop", xoperands);
6941 /* We are done if there isn't a jump in the delay slot. */
6943 || delay_insn_deleted
6944 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6947 /* A sibcall should never have a branch in the delay slot. */
6951 /* This call has an unconditional jump in its delay slot. */
6952 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6954 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
6956 /* See if the return address can be adjusted. Use the containing
6957 sequence insn's address. */
6958 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6959 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6960 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6962 if (VAL_14_BITS_P (distance))
6964 xoperands[1] = gen_label_rtx ();
6965 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
6966 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6967 CODE_LABEL_NUMBER (xoperands[1]));
6970 /* ??? This branch may not reach its target. */
6971 output_asm_insn ("nop\n\tb,n %0", xoperands);
6974 /* ??? This branch may not reach its target. */
6975 output_asm_insn ("b,n %0", xoperands);
6977 /* Delete the jump. */
6978 PUT_CODE (NEXT_INSN (insn), NOTE);
6979 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6980 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6985 /* Return the attribute length of the indirect call instruction INSN.
6986 The length must match the code generated by output_indirect call.
6987 The returned length includes the delay slot. Currently, the delay
6988 slot of an indirect call sequence is not exposed and it is used by
6989 the sequence itself. */
6992 attr_length_indirect_call (insn)
6995 unsigned long distance = -1;
6997 if (INSN_ADDRESSES_SET_P ())
6999 distance = (total_code_bytes + insn_current_reference_address (insn));
7000 if (distance < total_code_bytes)
7007 if (TARGET_FAST_INDIRECT_CALLS
7008 || (!TARGET_PORTABLE_RUNTIME
7009 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7015 if (TARGET_PORTABLE_RUNTIME)
7018 /* Out of reach, can use ble. */
7023 output_indirect_call (insn, call_dest)
7031 xoperands[0] = call_dest;
7032 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7033 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7037 /* First the special case for kernels, level 0 systems, etc. */
7038 if (TARGET_FAST_INDIRECT_CALLS)
7039 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7041 /* Now the normal case -- we can reach $$dyncall directly or
7042 we're sure that we can get there via a long-branch stub.
7044 No need to check target flags as the length uniquely identifies
7045 the remaining cases. */
7046 if (attr_length_indirect_call (insn) == 8)
7047 return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7049 /* Long millicode call, but we are not generating PIC or portable runtime
7051 if (attr_length_indirect_call (insn) == 12)
7052 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7054 /* Long millicode call for portable runtime. */
7055 if (attr_length_indirect_call (insn) == 20)
7056 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7058 /* We need a long PIC call to $$dyncall. */
7059 xoperands[0] = NULL_RTX;
7060 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7061 if (TARGET_SOM || !TARGET_GAS)
7063 xoperands[0] = gen_label_rtx ();
7064 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7065 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7066 CODE_LABEL_NUMBER (xoperands[0]));
7067 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7071 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7072 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7075 output_asm_insn ("blr %%r0,%%r2", xoperands);
7076 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7080 /* Return the total length of the save and restore instructions needed for
7081 the data linkage table pointer (i.e., the PIC register) across the call
7082 instruction INSN. No-return calls do not require a save and restore.
7083 In addition, we may be able to avoid the save and restore for calls
7084 within the same translation unit. */
7087 attr_length_save_restore_dltp (insn)
7090 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7096 /* In HPUX 8.0's shared library scheme, special relocations are needed
7097 for function labels if they might be passed to a function
7098 in a shared library (because shared libraries don't live in code
7099 space), and special magic is needed to construct their address. */
7102 hppa_encode_label (sym)
7105 const char *str = XSTR (sym, 0);
7106 int len = strlen (str) + 1;
7109 p = newstr = alloca (len + 1);
7113 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7117 pa_encode_section_info (decl, first)
7121 if (first && TEXT_SPACE_P (decl))
7124 if (TREE_CODE (decl) == FUNCTION_DECL
7125 || TREE_CODE (decl) == VAR_DECL)
7126 rtl = DECL_RTL (decl);
7128 rtl = TREE_CST_RTL (decl);
7129 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7130 if (TREE_CODE (decl) == FUNCTION_DECL)
7131 hppa_encode_label (XEXP (DECL_RTL (decl), 0));
7135 /* This is sort of inverse to pa_encode_section_info. */
7138 pa_strip_name_encoding (str)
7141 str += (*str == '@');
7142 str += (*str == '*');
7147 function_label_operand (op, mode)
7149 enum machine_mode mode ATTRIBUTE_UNUSED;
7151 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7154 /* Returns 1 if OP is a function label involved in a simple addition
7155 with a constant. Used to keep certain patterns from matching
7156 during instruction combination. */
7158 is_function_label_plus_const (op)
7161 /* Strip off any CONST. */
7162 if (GET_CODE (op) == CONST)
7165 return (GET_CODE (op) == PLUS
7166 && function_label_operand (XEXP (op, 0), Pmode)
7167 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7170 /* Output assembly code for a thunk to FUNCTION. */
7173 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
7176 HOST_WIDE_INT delta;
7177 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
7180 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
7181 static unsigned int current_thunk_number;
7184 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7185 lab = (*targetm.strip_name_encoding) (label);
7186 target_name = (*targetm.strip_name_encoding) (target_name);
7187 /* FIXME: total_code_bytes is not handled correctly in files with
7189 pa_output_function_prologue (file, 0);
7190 if (VAL_14_BITS_P (delta))
7192 if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic)
7194 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7195 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7196 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7197 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7198 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7199 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7200 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7201 if (TARGET_NO_SPACE_REGS)
7202 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7205 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
7206 fprintf (file, "\tmtsp %%r1,%%sr0\n");
7207 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7209 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7210 fprintf (file, "(%%r26),%%r26\n");
7214 fprintf (file, "\tb %s\n\tldo ", target_name);
7215 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7216 fprintf (file, "(%%r26),%%r26\n");
7221 if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic)
7223 fprintf (file, "\taddil L'");
7224 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7225 fprintf (file, ",%%r26\n\tldo R'");
7226 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7227 fprintf (file, "(%%r1),%%r26\n");
7228 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7229 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7230 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7231 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7232 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7233 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7234 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7235 if (TARGET_NO_SPACE_REGS)
7236 fprintf (file, "\tbe 0(%%sr4,%%r22)");
7239 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
7240 fprintf (file, "\tmtsp %%r1,%%sr0\n");
7241 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
7246 fprintf (file, "\taddil L'");
7247 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7248 fprintf (file, ",%%r26\n\tb %s\n\tldo R'", target_name);
7249 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
7250 fprintf (file, "(%%r1),%%r26\n");
7254 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7255 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
7258 fprintf (file, "\t.align 4\n");
7259 (*targetm.asm_out.internal_label) (file, "LTHN", current_thunk_number);
7260 fprintf (file, "\t.word P'%s\n", target_name);
7261 function_section (thunk_fndecl);
7263 current_thunk_number++;
7266 /* Only direct calls to static functions are allowed to be sibling (tail)
7269 This restriction is necessary because some linker generated stubs will
7270 store return pointers into rp' in some cases which might clobber a
7271 live value already in rp'.
7273 In a sibcall the current function and the target function share stack
7274 space. Thus if the path to the current function and the path to the
7275 target function save a value in rp', they save the value into the
7276 same stack slot, which has undesirable consequences.
7278 Because of the deferred binding nature of shared libraries any function
7279 with external scope could be in a different load module and thus require
7280 rp' to be saved when calling that function. So sibcall optimizations
7281 can only be safe for static function.
7283 Note that GCC never needs return value relocations, so we don't have to
7284 worry about static calls with return value relocations (which require
7287 It is safe to perform a sibcall optimization when the target function
7288 will never return. */
7290 pa_function_ok_for_sibcall (decl, exp)
7292 tree exp ATTRIBUTE_UNUSED;
7294 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7295 single subspace mode and the call is not indirect. As far as I know,
7296 there is no operating system support for the multiple subspace mode.
7297 It might be possible to support indirect calls if we didn't use
7298 $$dyncall (see the indirect sequence generated in output_call). */
7300 return (decl != NULL_TREE);
7302 /* Sibcalls are not ok because the arg pointer register is not a fixed
7303 register. This prevents the sibcall optimization from occuring. In
7304 addition, there are problems with stub placement using GNU ld. This
7305 is because a normal sibcall branch uses a 17-bit relocation while
7306 a regular call branch uses a 22-bit relocation. As a result, more
7307 care needs to be taken in the placement of long-branch stubs. */
7312 && !TARGET_PORTABLE_RUNTIME
7313 && !TREE_PUBLIC (decl));
7316 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7317 use in fmpyadd instructions. */
7319 fmpyaddoperands (operands)
7322 enum machine_mode mode = GET_MODE (operands[0]);
7324 /* Must be a floating point mode. */
7325 if (mode != SFmode && mode != DFmode)
7328 /* All modes must be the same. */
7329 if (! (mode == GET_MODE (operands[1])
7330 && mode == GET_MODE (operands[2])
7331 && mode == GET_MODE (operands[3])
7332 && mode == GET_MODE (operands[4])
7333 && mode == GET_MODE (operands[5])))
7336 /* All operands must be registers. */
7337 if (! (GET_CODE (operands[1]) == REG
7338 && GET_CODE (operands[2]) == REG
7339 && GET_CODE (operands[3]) == REG
7340 && GET_CODE (operands[4]) == REG
7341 && GET_CODE (operands[5]) == REG))
7344 /* Only 2 real operands to the addition. One of the input operands must
7345 be the same as the output operand. */
7346 if (! rtx_equal_p (operands[3], operands[4])
7347 && ! rtx_equal_p (operands[3], operands[5]))
7350 /* Inout operand of add can not conflict with any operands from multiply. */
7351 if (rtx_equal_p (operands[3], operands[0])
7352 || rtx_equal_p (operands[3], operands[1])
7353 || rtx_equal_p (operands[3], operands[2]))
7356 /* multiply can not feed into addition operands. */
7357 if (rtx_equal_p (operands[4], operands[0])
7358 || rtx_equal_p (operands[5], operands[0]))
7361 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7363 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7364 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7365 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7366 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7367 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7368 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7371 /* Passed. Operands are suitable for fmpyadd. */
7375 #if !defined(USE_COLLECT2)
7377 pa_asm_out_constructor (symbol, priority)
7381 if (!function_label_operand (symbol, VOIDmode))
7382 hppa_encode_label (symbol);
7384 #ifdef CTORS_SECTION_ASM_OP
7385 default_ctor_section_asm_out_constructor (symbol, priority);
7387 # ifdef TARGET_ASM_NAMED_SECTION
7388 default_named_section_asm_out_constructor (symbol, priority);
7390 default_stabs_asm_out_constructor (symbol, priority);
7396 pa_asm_out_destructor (symbol, priority)
7400 if (!function_label_operand (symbol, VOIDmode))
7401 hppa_encode_label (symbol);
7403 #ifdef DTORS_SECTION_ASM_OP
7404 default_dtor_section_asm_out_destructor (symbol, priority);
7406 # ifdef TARGET_ASM_NAMED_SECTION
7407 default_named_section_asm_out_destructor (symbol, priority);
7409 default_stabs_asm_out_destructor (symbol, priority);
7415 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7416 use in fmpysub instructions. */
7418 fmpysuboperands (operands)
7421 enum machine_mode mode = GET_MODE (operands[0]);
7423 /* Must be a floating point mode. */
7424 if (mode != SFmode && mode != DFmode)
7427 /* All modes must be the same. */
7428 if (! (mode == GET_MODE (operands[1])
7429 && mode == GET_MODE (operands[2])
7430 && mode == GET_MODE (operands[3])
7431 && mode == GET_MODE (operands[4])
7432 && mode == GET_MODE (operands[5])))
7435 /* All operands must be registers. */
7436 if (! (GET_CODE (operands[1]) == REG
7437 && GET_CODE (operands[2]) == REG
7438 && GET_CODE (operands[3]) == REG
7439 && GET_CODE (operands[4]) == REG
7440 && GET_CODE (operands[5]) == REG))
7443 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
7444 operation, so operands[4] must be the same as operand[3]. */
7445 if (! rtx_equal_p (operands[3], operands[4]))
7448 /* multiply can not feed into subtraction. */
7449 if (rtx_equal_p (operands[5], operands[0]))
7452 /* Inout operand of sub can not conflict with any operands from multiply. */
7453 if (rtx_equal_p (operands[3], operands[0])
7454 || rtx_equal_p (operands[3], operands[1])
7455 || rtx_equal_p (operands[3], operands[2]))
7458 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7460 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7461 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7462 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7463 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7464 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7465 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7468 /* Passed. Operands are suitable for fmpysub. */
7473 plus_xor_ior_operator (op, mode)
7475 enum machine_mode mode ATTRIBUTE_UNUSED;
7477 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
7478 || GET_CODE (op) == IOR);
7481 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
7482 constants for shadd instructions. */
7484 shadd_constant_p (val)
7487 if (val == 2 || val == 4 || val == 8)
7493 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
7494 the valid constant for shadd instructions. */
7496 shadd_operand (op, mode)
7498 enum machine_mode mode ATTRIBUTE_UNUSED;
7500 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
7503 /* Return 1 if OP is valid as a base register in a reg + reg address. */
7506 basereg_operand (op, mode)
7508 enum machine_mode mode;
7510 /* cse will create some unscaled indexed addresses, however; it
7511 generally isn't a win on the PA, so avoid creating unscaled
7512 indexed addresses until after cse is finished. */
7513 if (!cse_not_expected)
7516 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
7517 we don't have to worry about the braindamaged implicit space
7518 register selection from the basereg. */
7519 if (TARGET_NO_SPACE_REGS)
7520 return (GET_CODE (op) == REG);
7522 /* While it's always safe to index off the frame pointer, it's not
7523 always profitable, particularly when the frame pointer is being
7525 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
7528 return (GET_CODE (op) == REG
7530 && register_operand (op, mode));
7533 /* Return 1 if this operand is anything other than a hard register. */
7536 non_hard_reg_operand (op, mode)
7538 enum machine_mode mode ATTRIBUTE_UNUSED;
7540 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
7543 /* Return 1 if INSN branches forward. Should be using insn_addresses
7544 to avoid walking through all the insns... */
7546 forward_branch_p (insn)
7549 rtx label = JUMP_LABEL (insn);
7556 insn = NEXT_INSN (insn);
7559 return (insn == label);
7562 /* Return 1 if OP is an equality comparison, else return 0. */
7564 eq_neq_comparison_operator (op, mode)
7566 enum machine_mode mode ATTRIBUTE_UNUSED;
7568 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
7571 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
7573 movb_comparison_operator (op, mode)
7575 enum machine_mode mode ATTRIBUTE_UNUSED;
7577 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
7578 || GET_CODE (op) == LT || GET_CODE (op) == GE);
7581 /* Return 1 if INSN is in the delay slot of a call instruction. */
7583 jump_in_call_delay (insn)
7587 if (GET_CODE (insn) != JUMP_INSN)
7590 if (PREV_INSN (insn)
7591 && PREV_INSN (PREV_INSN (insn))
7592 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
7594 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
7596 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
7597 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
7604 /* Output an unconditional move and branch insn. */
7607 output_parallel_movb (operands, length)
7611 /* These are the cases in which we win. */
7613 return "mov%I1b,tr %1,%0,%2";
7615 /* None of these cases wins, but they don't lose either. */
7616 if (dbr_sequence_length () == 0)
7618 /* Nothing in the delay slot, fake it by putting the combined
7619 insn (the copy or add) in the delay slot of a bl. */
7620 if (GET_CODE (operands[1]) == CONST_INT)
7621 return "b %2\n\tldi %1,%0";
7623 return "b %2\n\tcopy %1,%0";
7627 /* Something in the delay slot, but we've got a long branch. */
7628 if (GET_CODE (operands[1]) == CONST_INT)
7629 return "ldi %1,%0\n\tb %2";
7631 return "copy %1,%0\n\tb %2";
7635 /* Output an unconditional add and branch insn. */
7638 output_parallel_addb (operands, length)
7642 /* To make life easy we want operand0 to be the shared input/output
7643 operand and operand1 to be the readonly operand. */
7644 if (operands[0] == operands[1])
7645 operands[1] = operands[2];
7647 /* These are the cases in which we win. */
7649 return "add%I1b,tr %1,%0,%3";
7651 /* None of these cases win, but they don't lose either. */
7652 if (dbr_sequence_length () == 0)
7654 /* Nothing in the delay slot, fake it by putting the combined
7655 insn (the copy or add) in the delay slot of a bl. */
7656 return "b %3\n\tadd%I1 %1,%0,%0";
7660 /* Something in the delay slot, but we've got a long branch. */
7661 return "add%I1 %1,%0,%0\n\tb %3";
7665 /* Return nonzero if INSN (a jump insn) immediately follows a call
7666 to a named function. This is used to avoid filling the delay slot
7667 of the jump since it can usually be eliminated by modifying RP in
7668 the delay slot of the call. */
7671 following_call (insn)
7674 if (! TARGET_JUMP_IN_DELAY)
7677 /* Find the previous real insn, skipping NOTEs. */
7678 insn = PREV_INSN (insn);
7679 while (insn && GET_CODE (insn) == NOTE)
7680 insn = PREV_INSN (insn);
7682 /* Check for CALL_INSNs and millicode calls. */
7684 && ((GET_CODE (insn) == CALL_INSN
7685 && get_attr_type (insn) != TYPE_DYNCALL)
7686 || (GET_CODE (insn) == INSN
7687 && GET_CODE (PATTERN (insn)) != SEQUENCE
7688 && GET_CODE (PATTERN (insn)) != USE
7689 && GET_CODE (PATTERN (insn)) != CLOBBER
7690 && get_attr_type (insn) == TYPE_MILLI)))
7696 /* We use this hook to perform a PA specific optimization which is difficult
7697 to do in earlier passes.
7699 We want the delay slots of branches within jump tables to be filled.
7700 None of the compiler passes at the moment even has the notion that a
7701 PA jump table doesn't contain addresses, but instead contains actual
7704 Because we actually jump into the table, the addresses of each entry
7705 must stay constant in relation to the beginning of the table (which
7706 itself must stay constant relative to the instruction to jump into
7707 it). I don't believe we can guarantee earlier passes of the compiler
7708 will adhere to those rules.
7710 So, late in the compilation process we find all the jump tables, and
7711 expand them into real code -- eg each entry in the jump table vector
7712 will get an appropriate label followed by a jump to the final target.
7714 Reorg and the final jump pass can then optimize these branches and
7715 fill their delay slots. We end up with smaller, more efficient code.
7717 The jump instructions within the table are special; we must be able
7718 to identify them during assembly output (if the jumps don't get filled
7719 we need to emit a nop rather than nullifying the delay slot)). We
7720 identify jumps in switch tables by marking the SET with DImode.
7722 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
7723 insns. This serves two purposes, first it prevents jump.c from
7724 noticing that the last N entries in the table jump to the instruction
7725 immediately after the table and deleting the jumps. Second, those
7726 insns mark where we should emit .begin_brtab and .end_brtab directives
7727 when using GAS (allows for better link time optimizations). */
7735 remove_useless_addtr_insns (insns, 1);
7737 if (pa_cpu < PROCESSOR_8000)
7738 pa_combine_instructions (get_insns ());
7741 /* This is fairly cheap, so always run it if optimizing. */
7742 if (optimize > 0 && !TARGET_BIG_SWITCH)
7744 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
7745 insns = get_insns ();
7746 for (insn = insns; insn; insn = NEXT_INSN (insn))
7748 rtx pattern, tmp, location;
7749 unsigned int length, i;
7751 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
7752 if (GET_CODE (insn) != JUMP_INSN
7753 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7754 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7757 /* Emit marker for the beginning of the branch table. */
7758 emit_insn_before (gen_begin_brtab (), insn);
7760 pattern = PATTERN (insn);
7761 location = PREV_INSN (insn);
7762 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
7764 for (i = 0; i < length; i++)
7766 /* Emit a label before each jump to keep jump.c from
7767 removing this code. */
7768 tmp = gen_label_rtx ();
7769 LABEL_NUSES (tmp) = 1;
7770 emit_label_after (tmp, location);
7771 location = NEXT_INSN (location);
7773 if (GET_CODE (pattern) == ADDR_VEC)
7775 /* Emit the jump itself. */
7776 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7777 tmp = emit_jump_insn_after (tmp, location);
7778 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7779 /* It is easy to rely on the branch table markers
7780 during assembly output to trigger the correct code
7781 for a switch table jump with an unfilled delay slot,
7783 However, that requires state and assumes that we look
7786 We can't make such assumptions when computing the length
7787 of instructions. Ugh. We could walk the insn chain to
7788 determine if this instruction is in a branch table, but
7789 that can get rather expensive, particularly during the
7790 branch shortening phase of the compiler.
7792 So instead we mark this jump as being special. This is
7793 far from ideal and knows that no code after this will
7794 muck around with the mode of the JUMP_INSN itself. */
7795 PUT_MODE (tmp, SImode);
7796 LABEL_NUSES (JUMP_LABEL (tmp))++;
7797 location = NEXT_INSN (location);
7801 /* Emit the jump itself. */
7802 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7803 tmp = emit_jump_insn_after (tmp, location);
7804 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7805 /* It is easy to rely on the branch table markers
7806 during assembly output to trigger the correct code
7807 for a switch table jump with an unfilled delay slot,
7809 However, that requires state and assumes that we look
7812 We can't make such assumptions when computing the length
7813 of instructions. Ugh. We could walk the insn chain to
7814 determine if this instruction is in a branch table, but
7815 that can get rather expensive, particularly during the
7816 branch shortening phase of the compiler.
7818 So instead we mark this jump as being special. This is
7819 far from ideal and knows that no code after this will
7820 muck around with the mode of the JUMP_INSN itself. */
7821 PUT_MODE (tmp, SImode);
7822 LABEL_NUSES (JUMP_LABEL (tmp))++;
7823 location = NEXT_INSN (location);
7826 /* Emit a BARRIER after the jump. */
7827 emit_barrier_after (location);
7828 location = NEXT_INSN (location);
7831 /* Emit marker for the end of the branch table. */
7832 emit_insn_before (gen_end_brtab (), location);
7833 location = NEXT_INSN (location);
7834 emit_barrier_after (location);
7836 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7842 /* Sill need an end_brtab insn. */
7843 insns = get_insns ();
7844 for (insn = insns; insn; insn = NEXT_INSN (insn))
7846 /* Find an ADDR_VEC insn. */
7847 if (GET_CODE (insn) != JUMP_INSN
7848 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7849 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7852 /* Now generate markers for the beginning and end of the
7854 emit_insn_before (gen_begin_brtab (), insn);
7855 emit_insn_after (gen_end_brtab (), insn);
7860 /* The PA has a number of odd instructions which can perform multiple
7861 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7862 it may be profitable to combine two instructions into one instruction
7863 with two outputs. It's not profitable PA2.0 machines because the
7864 two outputs would take two slots in the reorder buffers.
7866 This routine finds instructions which can be combined and combines
7867 them. We only support some of the potential combinations, and we
7868 only try common ways to find suitable instructions.
7870 * addb can add two registers or a register and a small integer
7871 and jump to a nearby (+-8k) location. Normally the jump to the
7872 nearby location is conditional on the result of the add, but by
7873 using the "true" condition we can make the jump unconditional.
7874 Thus addb can perform two independent operations in one insn.
7876 * movb is similar to addb in that it can perform a reg->reg
7877 or small immediate->reg copy and jump to a nearby (+-8k location).
7879 * fmpyadd and fmpysub can perform a FP multiply and either an
7880 FP add or FP sub if the operands of the multiply and add/sub are
7881 independent (there are other minor restrictions). Note both
7882 the fmpy and fadd/fsub can in theory move to better spots according
7883 to data dependencies, but for now we require the fmpy stay at a
7886 * Many of the memory operations can perform pre & post updates
7887 of index registers. GCC's pre/post increment/decrement addressing
7888 is far too simple to take advantage of all the possibilities. This
7889 pass may not be suitable since those insns may not be independent.
7891 * comclr can compare two ints or an int and a register, nullify
7892 the following instruction and zero some other register. This
7893 is more difficult to use as it's harder to find an insn which
7894 will generate a comclr than finding something like an unconditional
7895 branch. (conditional moves & long branches create comclr insns).
7897 * Most arithmetic operations can conditionally skip the next
7898 instruction. They can be viewed as "perform this operation
7899 and conditionally jump to this nearby location" (where nearby
7900 is an insns away). These are difficult to use due to the
7901 branch length restrictions. */
7904 pa_combine_instructions (insns)
7905 rtx insns ATTRIBUTE_UNUSED;
7909 /* This can get expensive since the basic algorithm is on the
7910 order of O(n^2) (or worse). Only do it for -O2 or higher
7911 levels of optimization. */
7915 /* Walk down the list of insns looking for "anchor" insns which
7916 may be combined with "floating" insns. As the name implies,
7917 "anchor" instructions don't move, while "floating" insns may
7919 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7920 new = make_insn_raw (new);
7922 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7924 enum attr_pa_combine_type anchor_attr;
7925 enum attr_pa_combine_type floater_attr;
7927 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7928 Also ignore any special USE insns. */
7929 if ((GET_CODE (anchor) != INSN
7930 && GET_CODE (anchor) != JUMP_INSN
7931 && GET_CODE (anchor) != CALL_INSN)
7932 || GET_CODE (PATTERN (anchor)) == USE
7933 || GET_CODE (PATTERN (anchor)) == CLOBBER
7934 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7935 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7938 anchor_attr = get_attr_pa_combine_type (anchor);
7939 /* See if anchor is an insn suitable for combination. */
7940 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7941 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7942 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7943 && ! forward_branch_p (anchor)))
7947 for (floater = PREV_INSN (anchor);
7949 floater = PREV_INSN (floater))
7951 if (GET_CODE (floater) == NOTE
7952 || (GET_CODE (floater) == INSN
7953 && (GET_CODE (PATTERN (floater)) == USE
7954 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7957 /* Anything except a regular INSN will stop our search. */
7958 if (GET_CODE (floater) != INSN
7959 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7960 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7966 /* See if FLOATER is suitable for combination with the
7968 floater_attr = get_attr_pa_combine_type (floater);
7969 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7970 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7971 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7972 && floater_attr == PA_COMBINE_TYPE_FMPY))
7974 /* If ANCHOR and FLOATER can be combined, then we're
7975 done with this pass. */
7976 if (pa_can_combine_p (new, anchor, floater, 0,
7977 SET_DEST (PATTERN (floater)),
7978 XEXP (SET_SRC (PATTERN (floater)), 0),
7979 XEXP (SET_SRC (PATTERN (floater)), 1)))
7983 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7984 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7986 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7988 if (pa_can_combine_p (new, anchor, floater, 0,
7989 SET_DEST (PATTERN (floater)),
7990 XEXP (SET_SRC (PATTERN (floater)), 0),
7991 XEXP (SET_SRC (PATTERN (floater)), 1)))
7996 if (pa_can_combine_p (new, anchor, floater, 0,
7997 SET_DEST (PATTERN (floater)),
7998 SET_SRC (PATTERN (floater)),
7999 SET_SRC (PATTERN (floater))))
8005 /* If we didn't find anything on the backwards scan try forwards. */
8007 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8008 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8010 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8012 if (GET_CODE (floater) == NOTE
8013 || (GET_CODE (floater) == INSN
8014 && (GET_CODE (PATTERN (floater)) == USE
8015 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8019 /* Anything except a regular INSN will stop our search. */
8020 if (GET_CODE (floater) != INSN
8021 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8022 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8028 /* See if FLOATER is suitable for combination with the
8030 floater_attr = get_attr_pa_combine_type (floater);
8031 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8032 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8033 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8034 && floater_attr == PA_COMBINE_TYPE_FMPY))
8036 /* If ANCHOR and FLOATER can be combined, then we're
8037 done with this pass. */
8038 if (pa_can_combine_p (new, anchor, floater, 1,
8039 SET_DEST (PATTERN (floater)),
8040 XEXP (SET_SRC (PATTERN (floater)),
8042 XEXP (SET_SRC (PATTERN (floater)),
8049 /* FLOATER will be nonzero if we found a suitable floating
8050 insn for combination with ANCHOR. */
8052 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8053 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8055 /* Emit the new instruction and delete the old anchor. */
8056 emit_insn_before (gen_rtx_PARALLEL
8058 gen_rtvec (2, PATTERN (anchor),
8059 PATTERN (floater))),
8062 PUT_CODE (anchor, NOTE);
8063 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8064 NOTE_SOURCE_FILE (anchor) = 0;
8066 /* Emit a special USE insn for FLOATER, then delete
8067 the floating insn. */
8068 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8069 delete_insn (floater);
8074 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8077 /* Emit the new_jump instruction and delete the old anchor. */
8079 = emit_jump_insn_before (gen_rtx_PARALLEL
8081 gen_rtvec (2, PATTERN (anchor),
8082 PATTERN (floater))),
8085 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8086 PUT_CODE (anchor, NOTE);
8087 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8088 NOTE_SOURCE_FILE (anchor) = 0;
8090 /* Emit a special USE insn for FLOATER, then delete
8091 the floating insn. */
8092 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8093 delete_insn (floater);
8101 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
8102 rtx new, anchor, floater;
8104 rtx dest, src1, src2;
8106 int insn_code_number;
8109 /* Create a PARALLEL with the patterns of ANCHOR and
8110 FLOATER, try to recognize it, then test constraints
8111 for the resulting pattern.
8113 If the pattern doesn't match or the constraints
8114 aren't met keep searching for a suitable floater
8116 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8117 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8118 INSN_CODE (new) = -1;
8119 insn_code_number = recog_memoized (new);
8120 if (insn_code_number < 0
8121 || (extract_insn (new), ! constrain_operands (1)))
8135 /* There's up to three operands to consider. One
8136 output and two inputs.
8138 The output must not be used between FLOATER & ANCHOR
8139 exclusive. The inputs must not be set between
8140 FLOATER and ANCHOR exclusive. */
8142 if (reg_used_between_p (dest, start, end))
8145 if (reg_set_between_p (src1, start, end))
8148 if (reg_set_between_p (src2, start, end))
8151 /* If we get here, then everything is good. */
8155 /* Return nonzero if references for INSN are delayed.
8157 Millicode insns are actually function calls with some special
8158 constraints on arguments and register usage.
8160 Millicode calls always expect their arguments in the integer argument
8161 registers, and always return their result in %r29 (ret1). They
8162 are expected to clobber their arguments, %r1, %r29, and the return
8163 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8165 This function tells reorg that the references to arguments and
8166 millicode calls do not appear to happen until after the millicode call.
8167 This allows reorg to put insns which set the argument registers into the
8168 delay slot of the millicode call -- thus they act more like traditional
8171 Note we can not consider side effects of the insn to be delayed because
8172 the branch and link insn will clobber the return pointer. If we happened
8173 to use the return pointer in the delay slot of the call, then we lose.
8175 get_attr_type will try to recognize the given insn, so make sure to
8176 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8179 insn_refs_are_delayed (insn)
8182 return ((GET_CODE (insn) == INSN
8183 && GET_CODE (PATTERN (insn)) != SEQUENCE
8184 && GET_CODE (PATTERN (insn)) != USE
8185 && GET_CODE (PATTERN (insn)) != CLOBBER
8186 && get_attr_type (insn) == TYPE_MILLI));
8189 /* On the HP-PA the value is found in register(s) 28(-29), unless
8190 the mode is SF or DF. Then the value is returned in fr4 (32).
8192 This must perform the same promotions as PROMOTE_MODE, else
8193 PROMOTE_FUNCTION_RETURN will not work correctly.
8195 Small structures must be returned in a PARALLEL on PA64 in order
8196 to match the HP Compiler ABI. */
8199 function_value (valtype, func)
8201 tree func ATTRIBUTE_UNUSED;
8203 enum machine_mode valmode;
8205 /* Aggregates with a size less than or equal to 128 bits are returned
8206 in GR 28(-29). They are left justified. The pad bits are undefined.
8207 Larger aggregates are returned in memory. */
8208 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8212 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8214 for (i = 0; i < ub; i++)
8216 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8217 gen_rtx_REG (DImode, 28 + i),
8222 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8225 if ((INTEGRAL_TYPE_P (valtype)
8226 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8227 || POINTER_TYPE_P (valtype))
8228 valmode = word_mode;
8230 valmode = TYPE_MODE (valtype);
8232 if (TREE_CODE (valtype) == REAL_TYPE
8233 && TYPE_MODE (valtype) != TFmode
8234 && !TARGET_SOFT_FLOAT)
8235 return gen_rtx_REG (valmode, 32);
8237 return gen_rtx_REG (valmode, 28);
8240 /* Return the location of a parameter that is passed in a register or NULL
8241 if the parameter has any component that is passed in memory.
8243 This is new code and will be pushed to into the net sources after
8246 ??? We might want to restructure this so that it looks more like other
8249 function_arg (cum, mode, type, named)
8250 CUMULATIVE_ARGS *cum;
8251 enum machine_mode mode;
8253 int named ATTRIBUTE_UNUSED;
8255 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8262 if (mode == VOIDmode)
8265 arg_size = FUNCTION_ARG_SIZE (mode, type);
8267 /* If this arg would be passed partially or totally on the stack, then
8268 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8269 handle arguments which are split between regs and stack slots if
8270 the ABI mandates split arguments. */
8273 /* The 32-bit ABI does not split arguments. */
8274 if (cum->words + arg_size > max_arg_words)
8280 alignment = cum->words & 1;
8281 if (cum->words + alignment >= max_arg_words)
8285 /* The 32bit ABIs and the 64bit ABIs are rather different,
8286 particularly in their handling of FP registers. We might
8287 be able to cleverly share code between them, but I'm not
8288 going to bother in the hope that splitting them up results
8289 in code that is more easily understood. */
8293 /* Advance the base registers to their current locations.
8295 Remember, gprs grow towards smaller register numbers while
8296 fprs grow to higher register numbers. Also remember that
8297 although FP regs are 32-bit addressable, we pretend that
8298 the registers are 64-bits wide. */
8299 gpr_reg_base = 26 - cum->words;
8300 fpr_reg_base = 32 + cum->words;
8302 /* Arguments wider than one word and small aggregates need special
8306 || (type && AGGREGATE_TYPE_P (type)))
8308 /* Double-extended precision (80-bit), quad-precision (128-bit)
8309 and aggregates including complex numbers are aligned on
8310 128-bit boundaries. The first eight 64-bit argument slots
8311 are associated one-to-one, with general registers r26
8312 through r19, and also with floating-point registers fr4
8313 through fr11. Arguments larger than one word are always
8314 passed in general registers.
8316 Using a PARALLEL with a word mode register results in left
8317 justified data on a big-endian target. */
8320 int i, offset = 0, ub = arg_size;
8322 /* Align the base register. */
8323 gpr_reg_base -= alignment;
8325 ub = MIN (ub, max_arg_words - cum->words - alignment);
8326 for (i = 0; i < ub; i++)
8328 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8329 gen_rtx_REG (DImode, gpr_reg_base),
8335 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8340 /* If the argument is larger than a word, then we know precisely
8341 which registers we must use. */
8355 /* Structures 5 to 8 bytes in size are passed in the general
8356 registers in the same manner as other non floating-point
8357 objects. The data is right-justified and zero-extended
8360 This is magic. Normally, using a PARALLEL results in left
8361 justified data on a big-endian target. However, using a
8362 single double-word register provides the required right
8363 justication for 5 to 8 byte structures. This has nothing
8364 to do with the direction of padding specified for the argument.
8365 It has to do with how the data is widened and shifted into
8366 and from the register.
8368 Aside from adding load_multiple and store_multiple patterns,
8369 this is the only way that I have found to obtain right
8370 justification of BLKmode data when it has a size greater
8371 than one word. Splitting the operation into two SImode loads
8372 or returning a DImode REG results in left justified data. */
8373 if (mode == BLKmode)
8375 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8376 gen_rtx_REG (DImode, gpr_reg_base),
8378 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8383 /* We have a single word (32 bits). A simple computation
8384 will get us the register #s we need. */
8385 gpr_reg_base = 26 - cum->words;
8386 fpr_reg_base = 32 + 2 * cum->words;
8390 /* Determine if the argument needs to be passed in both general and
8391 floating point registers. */
8392 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8393 /* If we are doing soft-float with portable runtime, then there
8394 is no need to worry about FP regs. */
8395 && !TARGET_SOFT_FLOAT
8396 /* The parameter must be some kind of float, else we can just
8397 pass it in integer registers. */
8398 && FLOAT_MODE_P (mode)
8399 /* The target function must not have a prototype. */
8400 && cum->nargs_prototype <= 0
8401 /* libcalls do not need to pass items in both FP and general
8403 && type != NULL_TREE
8404 /* All this hair applies to "outgoing" args only. This includes
8405 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8407 /* Also pass outgoing floating arguments in both registers in indirect
8408 calls with the 32 bit ABI and the HP assembler since there is no
8409 way to the specify argument locations in static functions. */
8414 && FLOAT_MODE_P (mode)))
8420 gen_rtx_EXPR_LIST (VOIDmode,
8421 gen_rtx_REG (mode, fpr_reg_base),
8423 gen_rtx_EXPR_LIST (VOIDmode,
8424 gen_rtx_REG (mode, gpr_reg_base),
8429 /* See if we should pass this parameter in a general register. */
8430 if (TARGET_SOFT_FLOAT
8431 /* Indirect calls in the normal 32bit ABI require all arguments
8432 to be passed in general registers. */
8433 || (!TARGET_PORTABLE_RUNTIME
8437 /* If the parameter is not a floating point parameter, then
8438 it belongs in GPRs. */
8439 || !FLOAT_MODE_P (mode))
8440 retval = gen_rtx_REG (mode, gpr_reg_base);
8442 retval = gen_rtx_REG (mode, fpr_reg_base);
8448 /* If this arg would be passed totally in registers or totally on the stack,
8449 then this routine should return zero. It is currently called only for
8450 the 64-bit target. */
8452 function_arg_partial_nregs (cum, mode, type, named)
8453 CUMULATIVE_ARGS *cum;
8454 enum machine_mode mode;
8456 int named ATTRIBUTE_UNUSED;
8458 unsigned int max_arg_words = 8;
8459 unsigned int offset = 0;
8461 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8464 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8465 /* Arg fits fully into registers. */
8467 else if (cum->words + offset >= max_arg_words)
8468 /* Arg fully on the stack. */
8472 return max_arg_words - cum->words - offset;
8476 /* Return 1 if this is a comparison operator. This allows the use of
8477 MATCH_OPERATOR to recognize all the branch insns. */
8480 cmpib_comparison_operator (op, mode)
8482 enum machine_mode mode;
8484 return ((mode == VOIDmode || GET_MODE (op) == mode)
8485 && (GET_CODE (op) == EQ
8486 || GET_CODE (op) == NE
8487 || GET_CODE (op) == GT
8488 || GET_CODE (op) == GTU
8489 || GET_CODE (op) == GE
8490 || GET_CODE (op) == LT
8491 || GET_CODE (op) == LE
8492 || GET_CODE (op) == LEU));
8495 /* On hpux10, the linker will give an error if we have a reference
8496 in the read-only data section to a symbol defined in a shared
8497 library. Therefore, expressions that might require a reloc can
8498 not be placed in the read-only data section. */
8501 pa_select_section (exp, reloc, align)
8504 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
8506 if (TREE_CODE (exp) == VAR_DECL
8507 && TREE_READONLY (exp)
8508 && !TREE_THIS_VOLATILE (exp)
8509 && DECL_INITIAL (exp)
8510 && (DECL_INITIAL (exp) == error_mark_node
8511 || TREE_CONSTANT (DECL_INITIAL (exp)))
8513 readonly_data_section ();
8514 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
8515 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
8517 readonly_data_section ();
8523 pa_globalize_label (stream, name)
8527 /* We only handle DATA objects here, functions are globalized in
8528 ASM_DECLARE_FUNCTION_NAME. */
8529 if (! FUNCTION_NAME_P (name))
8531 fputs ("\t.EXPORT ", stream);
8532 assemble_name (stream, name);
8533 fputs (",DATA\n", stream);