1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static int hppa_address_cost (rtx);
88 static bool hppa_rtx_costs (rtx, int, int, int *);
89 static inline rtx force_mode (enum machine_mode, rtx);
90 static void pa_reorg (void);
91 static void pa_combine_instructions (void);
92 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
93 static int forward_branch_p (rtx);
94 static int shadd_constant_p (int);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
127 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static struct deferred_plabel *get_plabel (const char *)
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 #ifdef HPUX_LONG_DOUBLE_LIBRARY
141 static void pa_hpux_init_libfuncs (void);
143 static rtx pa_struct_value_rtx (tree, int);
144 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
146 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
148 static struct machine_function * pa_init_machine_status (void);
151 /* Save the operands last given to a compare for use when we
152 generate a scc or bcc insn. */
153 rtx hppa_compare_op0, hppa_compare_op1;
154 enum cmp_type hppa_branch_type;
156 /* Which architecture we are generating code for. */
157 enum architecture_type pa_arch;
159 /* String to hold which architecture we are generating code for. */
160 const char *pa_arch_string;
162 /* String used with the -mfixed-range= option. */
163 const char *pa_fixed_range_string;
165 /* Which cpu we are scheduling for. */
166 enum processor_type pa_cpu;
168 /* String to hold which cpu we are scheduling for. */
169 const char *pa_cpu_string;
171 /* String used with the -munix= option. */
172 const char *pa_unix_string;
174 /* The UNIX standard to use for predefines and linking. */
177 /* Counts for the number of callee-saved general and floating point
178 registers which were saved by the current function's prologue. */
179 static int gr_saved, fr_saved;
181 static rtx find_addr_reg (rtx);
183 /* Keep track of the number of bytes we have output in the CODE subspace
184 during this compilation so we'll know when to emit inline long-calls. */
185 unsigned long total_code_bytes;
187 /* The last address of the previous function plus the number of bytes in
188 associated thunks that have been output. This is used to determine if
189 a thunk can use an IA-relative branch to reach its target function. */
190 static int last_address;
192 /* Variables to handle plabels that we discover are necessary at assembly
193 output time. They are output after the current function. */
194 struct deferred_plabel GTY(())
199 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
201 static size_t n_deferred_plabels = 0;
204 /* Initialize the GCC target structure. */
206 #undef TARGET_ASM_ALIGNED_HI_OP
207 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
208 #undef TARGET_ASM_ALIGNED_SI_OP
209 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
210 #undef TARGET_ASM_ALIGNED_DI_OP
211 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
212 #undef TARGET_ASM_UNALIGNED_HI_OP
213 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
214 #undef TARGET_ASM_UNALIGNED_SI_OP
215 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
216 #undef TARGET_ASM_UNALIGNED_DI_OP
217 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
218 #undef TARGET_ASM_INTEGER
219 #define TARGET_ASM_INTEGER pa_assemble_integer
221 #undef TARGET_ASM_FUNCTION_PROLOGUE
222 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
223 #undef TARGET_ASM_FUNCTION_EPILOGUE
224 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
226 #undef TARGET_SCHED_ADJUST_COST
227 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
228 #undef TARGET_SCHED_ADJUST_PRIORITY
229 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
230 #undef TARGET_SCHED_ISSUE_RATE
231 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
233 #undef TARGET_ENCODE_SECTION_INFO
234 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
235 #undef TARGET_STRIP_NAME_ENCODING
236 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
238 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
239 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
241 #undef TARGET_ASM_OUTPUT_MI_THUNK
242 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
243 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
244 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
246 #undef TARGET_ASM_FILE_END
247 #define TARGET_ASM_FILE_END output_deferred_plabels
249 #if !defined(USE_COLLECT2)
250 #undef TARGET_ASM_CONSTRUCTOR
251 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
252 #undef TARGET_ASM_DESTRUCTOR
253 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
256 #undef TARGET_INIT_BUILTINS
257 #define TARGET_INIT_BUILTINS pa_init_builtins
259 #undef TARGET_RTX_COSTS
260 #define TARGET_RTX_COSTS hppa_rtx_costs
261 #undef TARGET_ADDRESS_COST
262 #define TARGET_ADDRESS_COST hppa_address_cost
264 #undef TARGET_MACHINE_DEPENDENT_REORG
265 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
267 #ifdef HPUX_LONG_DOUBLE_LIBRARY
268 #undef TARGET_INIT_LIBFUNCS
269 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
272 #undef TARGET_PROMOTE_FUNCTION_RETURN
273 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
274 #undef TARGET_PROMOTE_PROTOTYPES
275 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
277 #undef TARGET_STRUCT_VALUE_RTX
278 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
279 #undef TARGET_RETURN_IN_MEMORY
280 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
281 #undef TARGET_MUST_PASS_IN_STACK
282 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
283 #undef TARGET_PASS_BY_REFERENCE
284 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
285 #undef TARGET_CALLEE_COPIES
286 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
287 #undef TARGET_ARG_PARTIAL_BYTES
288 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
290 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
291 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
292 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
293 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
295 struct gcc_target targetm = TARGET_INITIALIZER;
297 /* Parse the -mfixed-range= option string. */
300 fix_range (const char *const_str)
303 char *str, *dash, *comma;
305 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
306 REG2 are either register names or register numbers. The effect
307 of this option is to mark the registers in the range from REG1 to
308 REG2 as ``fixed'' so they won't be used by the compiler. This is
309 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
311 i = strlen (const_str);
312 str = (char *) alloca (i + 1);
313 memcpy (str, const_str, i + 1);
317 dash = strchr (str, '-');
320 warning ("value of -mfixed-range must have form REG1-REG2");
325 comma = strchr (dash + 1, ',');
329 first = decode_reg_name (str);
332 warning ("unknown register name: %s", str);
336 last = decode_reg_name (dash + 1);
339 warning ("unknown register name: %s", dash + 1);
347 warning ("%s-%s is an empty range", str, dash + 1);
351 for (i = first; i <= last; ++i)
352 fixed_regs[i] = call_used_regs[i] = 1;
361 /* Check if all floating point registers have been fixed. */
362 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
367 target_flags |= MASK_DISABLE_FPREGS;
371 override_options (void)
373 if (pa_cpu_string == NULL)
374 pa_cpu_string = TARGET_SCHED_DEFAULT;
376 if (! strcmp (pa_cpu_string, "8000"))
378 pa_cpu_string = "8000";
379 pa_cpu = PROCESSOR_8000;
381 else if (! strcmp (pa_cpu_string, "7100"))
383 pa_cpu_string = "7100";
384 pa_cpu = PROCESSOR_7100;
386 else if (! strcmp (pa_cpu_string, "700"))
388 pa_cpu_string = "700";
389 pa_cpu = PROCESSOR_700;
391 else if (! strcmp (pa_cpu_string, "7100LC"))
393 pa_cpu_string = "7100LC";
394 pa_cpu = PROCESSOR_7100LC;
396 else if (! strcmp (pa_cpu_string, "7200"))
398 pa_cpu_string = "7200";
399 pa_cpu = PROCESSOR_7200;
401 else if (! strcmp (pa_cpu_string, "7300"))
403 pa_cpu_string = "7300";
404 pa_cpu = PROCESSOR_7300;
408 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
411 /* Set the instruction architecture. */
412 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
414 pa_arch_string = "1.0";
415 pa_arch = ARCHITECTURE_10;
416 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
418 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
420 pa_arch_string = "1.1";
421 pa_arch = ARCHITECTURE_11;
422 target_flags &= ~MASK_PA_20;
423 target_flags |= MASK_PA_11;
425 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
427 pa_arch_string = "2.0";
428 pa_arch = ARCHITECTURE_20;
429 target_flags |= MASK_PA_11 | MASK_PA_20;
431 else if (pa_arch_string)
433 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
438 /* Set the default UNIX standard for HP-UX. This affects the
439 predefines and startfiles used for the target. */
440 if (pa_unix_string == NULL)
442 = TARGET_HPUX_11_11 ? "98" : (TARGET_HPUX_10_10 ? "95" : "93");
444 if (!strcmp (pa_unix_string, "93"))
446 else if (!strcmp (pa_unix_string, "95"))
448 else if (TARGET_HPUX_11_11)
450 if (!strcmp (pa_unix_string, "98"))
453 warning ("unknown -munix= option (%s).\n"
454 "Valid options are 93, 95 and 98.\n",
457 else if (TARGET_HPUX_10_10)
458 warning ("unknown -munix= option (%s)."
459 "\nValid options are 93 and 95.\n",
462 warning ("unknown -munix= option (%s).\nValid option is 93.\n",
466 if (pa_fixed_range_string)
467 fix_range (pa_fixed_range_string);
469 /* Unconditional branches in the delay slot are not compatible with dwarf2
470 call frame information. There is no benefit in using this optimization
471 on PA8000 and later processors. */
472 if (pa_cpu >= PROCESSOR_8000
473 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
474 || flag_unwind_tables)
475 target_flags &= ~MASK_JUMP_IN_DELAY;
477 if (flag_pic && TARGET_PORTABLE_RUNTIME)
479 warning ("PIC code generation is not supported in the portable runtime model\n");
482 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
484 warning ("PIC code generation is not compatible with fast indirect calls\n");
487 if (! TARGET_GAS && write_symbols != NO_DEBUG)
489 warning ("-g is only supported when using GAS on this processor,");
490 warning ("-g option disabled");
491 write_symbols = NO_DEBUG;
494 /* We only support the "big PIC" model now. And we always generate PIC
495 code when in 64bit mode. */
496 if (flag_pic == 1 || TARGET_64BIT)
499 /* We can't guarantee that .dword is available for 32-bit targets. */
500 if (UNITS_PER_WORD == 4)
501 targetm.asm_out.aligned_op.di = NULL;
503 /* The unaligned ops are only available when using GAS. */
506 targetm.asm_out.unaligned_op.hi = NULL;
507 targetm.asm_out.unaligned_op.si = NULL;
508 targetm.asm_out.unaligned_op.di = NULL;
511 init_machine_status = pa_init_machine_status;
515 pa_init_builtins (void)
517 #ifdef DONT_HAVE_FPUTC_UNLOCKED
518 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
519 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
523 /* Function to init struct machine_function.
524 This will be called, via a pointer variable,
525 from push_function_context. */
527 static struct machine_function *
528 pa_init_machine_status (void)
530 return ggc_alloc_cleared (sizeof (machine_function));
533 /* If FROM is a probable pointer register, mark TO as a probable
534 pointer register with the same pointer alignment as FROM. */
537 copy_reg_pointer (rtx to, rtx from)
539 if (REG_POINTER (from))
540 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
543 /* Return nonzero only if OP is a register of mode MODE,
546 reg_or_0_operand (rtx op, enum machine_mode mode)
548 return (op == CONST0_RTX (mode) || register_operand (op, mode));
551 /* Return nonzero if OP is suitable for use in a call to a named
554 For 2.5 try to eliminate either call_operand_address or
555 function_label_operand, they perform very similar functions. */
557 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
559 return (GET_MODE (op) == word_mode
560 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
563 /* Return 1 if X contains a symbolic expression. We know these
564 expressions will have one of a few well defined forms, so
565 we need only check those forms. */
567 symbolic_expression_p (rtx x)
570 /* Strip off any HIGH. */
571 if (GET_CODE (x) == HIGH)
574 return (symbolic_operand (x, VOIDmode));
578 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
580 switch (GET_CODE (op))
587 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
588 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
589 && GET_CODE (XEXP (op, 1)) == CONST_INT);
595 /* Return truth value of statement that OP is a symbolic memory
596 operand of mode MODE. */
599 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
601 if (GET_CODE (op) == SUBREG)
602 op = SUBREG_REG (op);
603 if (GET_CODE (op) != MEM)
606 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
607 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
610 /* Return 1 if the operand is either a register, zero, or a memory operand
611 that is not symbolic. */
614 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
616 if (register_operand (op, mode))
619 if (op == CONST0_RTX (mode))
622 if (GET_CODE (op) == SUBREG)
623 op = SUBREG_REG (op);
625 if (GET_CODE (op) != MEM)
628 /* Until problems with management of the REG_POINTER flag are resolved,
629 we need to delay creating move insns with unscaled indexed addresses
630 until CSE is not expected. */
631 if (!TARGET_NO_SPACE_REGS
633 && GET_CODE (XEXP (op, 0)) == PLUS
634 && REG_P (XEXP (XEXP (op, 0), 0))
635 && REG_P (XEXP (XEXP (op, 0), 1)))
638 return (!symbolic_memory_operand (op, mode)
639 && memory_address_p (mode, XEXP (op, 0)));
642 /* Return 1 if the operand is a register operand or a non-symbolic memory
643 operand after reload. This predicate is used for branch patterns that
644 internally handle register reloading. We need to accept non-symbolic
645 memory operands after reload to ensure that the pattern is still valid
646 if reload didn't find a hard register for the operand. */
649 reg_before_reload_operand (rtx op, enum machine_mode mode)
651 /* Don't accept a SUBREG since it will need a reload. */
652 if (GET_CODE (op) == SUBREG)
655 if (register_operand (op, mode))
659 && memory_operand (op, mode)
660 && !symbolic_memory_operand (op, mode))
666 /* Accept any constant that can be moved in one instruction into a
669 cint_ok_for_move (HOST_WIDE_INT intval)
671 /* OK if ldo, ldil, or zdepi, can be used. */
672 return (CONST_OK_FOR_LETTER_P (intval, 'J')
673 || CONST_OK_FOR_LETTER_P (intval, 'N')
674 || CONST_OK_FOR_LETTER_P (intval, 'K'));
677 /* Return 1 iff OP is an indexed memory operand. */
679 indexed_memory_operand (rtx op, enum machine_mode mode)
681 if (GET_MODE (op) != mode)
684 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
685 if (reload_completed && GET_CODE (op) == SUBREG)
686 op = SUBREG_REG (op);
688 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
693 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
696 /* Accept anything that can be used as a destination operand for a
697 move instruction. We don't accept indexed memory operands since
698 they are supported only for floating point stores. */
700 move_dest_operand (rtx op, enum machine_mode mode)
702 if (register_operand (op, mode))
705 if (GET_MODE (op) != mode)
708 if (GET_CODE (op) == SUBREG)
709 op = SUBREG_REG (op);
711 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
716 return (memory_address_p (mode, op)
717 && !IS_INDEX_ADDR_P (op)
718 && !IS_LO_SUM_DLT_ADDR_P (op));
721 /* Accept anything that can be used as a source operand for a move
724 move_src_operand (rtx op, enum machine_mode mode)
726 if (register_operand (op, mode))
729 if (GET_CODE (op) == CONST_INT)
730 return cint_ok_for_move (INTVAL (op));
732 if (GET_MODE (op) != mode)
735 if (GET_CODE (op) == SUBREG)
736 op = SUBREG_REG (op);
738 if (GET_CODE (op) != MEM)
741 /* Until problems with management of the REG_POINTER flag are resolved,
742 we need to delay creating move insns with unscaled indexed addresses
743 until CSE is not expected. */
744 if (!TARGET_NO_SPACE_REGS
746 && GET_CODE (XEXP (op, 0)) == PLUS
747 && REG_P (XEXP (XEXP (op, 0), 0))
748 && REG_P (XEXP (XEXP (op, 0), 1)))
751 return memory_address_p (mode, XEXP (op, 0));
754 /* Accept anything that can be used as the source operand for a prefetch
757 prefetch_operand (rtx op, enum machine_mode mode)
759 if (GET_CODE (op) != MEM)
762 /* Until problems with management of the REG_POINTER flag are resolved,
763 we need to delay creating prefetch insns with unscaled indexed addresses
764 until CSE is not expected. */
765 if (!TARGET_NO_SPACE_REGS
767 && GET_CODE (XEXP (op, 0)) == PLUS
768 && REG_P (XEXP (XEXP (op, 0), 0))
769 && REG_P (XEXP (XEXP (op, 0), 1)))
772 return memory_address_p (mode, XEXP (op, 0));
775 /* Accept REG and any CONST_INT that can be moved in one instruction into a
778 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
780 if (register_operand (op, mode))
783 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
787 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
792 switch (GET_CODE (op))
798 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
799 && GET_CODE (XEXP (op, 1)) == CONST_INT);
806 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
808 return reg_renumber && FP_REG_P (op);
813 /* Return truth value of whether OP can be used as an operand in a
814 three operand arithmetic insn that accepts registers of mode MODE
815 or 14-bit signed integers. */
817 arith_operand (rtx op, enum machine_mode mode)
819 return (register_operand (op, mode)
820 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
823 /* Return truth value of whether OP can be used as an operand in a
824 three operand arithmetic insn that accepts registers of mode MODE
825 or 11-bit signed integers. */
827 arith11_operand (rtx op, enum machine_mode mode)
829 return (register_operand (op, mode)
830 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
833 /* Return truth value of whether OP can be used as an operand in a
836 adddi3_operand (rtx op, enum machine_mode mode)
838 return (register_operand (op, mode)
839 || (GET_CODE (op) == CONST_INT
840 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
843 /* A constant integer suitable for use in a PRE_MODIFY memory
846 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
848 return (GET_CODE (op) == CONST_INT
849 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
852 /* A constant integer suitable for use in a POST_MODIFY memory
855 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
857 return (GET_CODE (op) == CONST_INT
858 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
862 arith_double_operand (rtx op, enum machine_mode mode)
864 return (register_operand (op, mode)
865 || (GET_CODE (op) == CONST_DOUBLE
866 && GET_MODE (op) == mode
867 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
868 && ((CONST_DOUBLE_HIGH (op) >= 0)
869 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
872 /* Return truth value of whether OP is an integer which fits the
873 range constraining immediate operands in three-address insns, or
874 is an integer register. */
877 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
879 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
880 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
883 /* Return nonzero if OP is an integer register, else return zero. */
885 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
887 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
890 /* Return truth value of whether OP is an integer which fits the
891 range constraining immediate operands in three-address insns. */
894 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
896 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
900 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
902 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
906 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
908 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
912 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
914 #if HOST_BITS_PER_WIDE_INT > 32
915 /* All allowed constants will fit a CONST_INT. */
916 return (GET_CODE (op) == CONST_INT
917 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
919 return (GET_CODE (op) == CONST_INT
920 || (GET_CODE (op) == CONST_DOUBLE
921 && CONST_DOUBLE_HIGH (op) == 0));
926 arith5_operand (rtx op, enum machine_mode mode)
928 return register_operand (op, mode) || int5_operand (op, mode);
931 /* True iff zdepi can be used to generate this CONST_INT.
932 zdepi first sign extends a 5 bit signed number to a given field
933 length, then places this field anywhere in a zero. */
935 zdepi_cint_p (unsigned HOST_WIDE_INT x)
937 unsigned HOST_WIDE_INT lsb_mask, t;
939 /* This might not be obvious, but it's at least fast.
940 This function is critical; we don't have the time loops would take. */
942 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
943 /* Return true iff t is a power of two. */
944 return ((t & (t - 1)) == 0);
947 /* True iff depi or extru can be used to compute (reg & mask).
948 Accept bit pattern like these:
953 and_mask_p (unsigned HOST_WIDE_INT mask)
956 mask += mask & -mask;
957 return (mask & (mask - 1)) == 0;
960 /* True iff depi or extru can be used to compute (reg & OP). */
962 and_operand (rtx op, enum machine_mode mode)
964 return (register_operand (op, mode)
965 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
968 /* True iff depi can be used to compute (reg | MASK). */
970 ior_mask_p (unsigned HOST_WIDE_INT mask)
972 mask += mask & -mask;
973 return (mask & (mask - 1)) == 0;
976 /* True iff depi can be used to compute (reg | OP). */
978 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
980 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
984 lhs_lshift_operand (rtx op, enum machine_mode mode)
986 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
989 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
990 Such values can be the left hand side x in (x << r), using the zvdepi
993 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
995 unsigned HOST_WIDE_INT x;
996 if (GET_CODE (op) != CONST_INT)
998 x = INTVAL (op) >> 4;
999 return (x & (x + 1)) == 0;
1003 arith32_operand (rtx op, enum machine_mode mode)
1005 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
1009 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1011 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
1014 /* Legitimize PIC addresses. If the address is already
1015 position-independent, we return ORIG. Newly generated
1016 position-independent addresses go to REG. If we need more
1017 than one register, we lose. */
1020 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
1024 /* Labels need special handling. */
1025 if (pic_label_operand (orig, mode))
1027 /* We do not want to go through the movXX expanders here since that
1028 would create recursion.
1030 Nor do we really want to call a generator for a named pattern
1031 since that requires multiple patterns if we want to support
1032 multiple word sizes.
1034 So instead we just emit the raw set, which avoids the movXX
1035 expanders completely. */
1036 mark_reg_pointer (reg, BITS_PER_UNIT);
1037 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
1038 current_function_uses_pic_offset_table = 1;
1041 if (GET_CODE (orig) == SYMBOL_REF)
1048 /* Before reload, allocate a temporary register for the intermediate
1049 result. This allows the sequence to be deleted when the final
1050 result is unused and the insns are trivially dead. */
1051 tmp_reg = ((reload_in_progress || reload_completed)
1052 ? reg : gen_reg_rtx (Pmode));
1054 emit_move_insn (tmp_reg,
1055 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
1056 gen_rtx_HIGH (word_mode, orig)));
1058 = gen_const_mem (Pmode,
1059 gen_rtx_LO_SUM (Pmode, tmp_reg,
1060 gen_rtx_UNSPEC (Pmode,
1061 gen_rtvec (1, orig),
1062 UNSPEC_DLTIND14R)));
1064 current_function_uses_pic_offset_table = 1;
1065 mark_reg_pointer (reg, BITS_PER_UNIT);
1066 insn = emit_move_insn (reg, pic_ref);
1068 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
1069 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
1073 else if (GET_CODE (orig) == CONST)
1077 if (GET_CODE (XEXP (orig, 0)) == PLUS
1078 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1084 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1086 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1087 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1088 base == reg ? 0 : reg);
1093 if (GET_CODE (orig) == CONST_INT)
1095 if (INT_14_BITS (orig))
1096 return plus_constant (base, INTVAL (orig));
1097 orig = force_reg (Pmode, orig);
1099 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1100 /* Likewise, should we set special REG_NOTEs here? */
1106 /* Try machine-dependent ways of modifying an illegitimate address
1107 to be legitimate. If we find one, return the new, valid address.
1108 This macro is used in only one place: `memory_address' in explow.c.
1110 OLDX is the address as it was before break_out_memory_refs was called.
1111 In some cases it is useful to look at this to decide what needs to be done.
1113 MODE and WIN are passed so that this macro can use
1114 GO_IF_LEGITIMATE_ADDRESS.
1116 It is always safe for this macro to do nothing. It exists to recognize
1117 opportunities to optimize the output.
1119 For the PA, transform:
1121 memory(X + <large int>)
1125 if (<large int> & mask) >= 16
1126 Y = (<large int> & ~mask) + mask + 1 Round up.
1128 Y = (<large int> & ~mask) Round down.
1130 memory (Z + (<large int> - Y));
1132 This is for CSE to find several similar references, and only use one Z.
1134 X can either be a SYMBOL_REF or REG, but because combine cannot
1135 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1136 D will not fit in 14 bits.
1138 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1141 MODE_INT references allow displacements which fit in 14 bits, so use
1144 This relies on the fact that most mode MODE_FLOAT references will use FP
1145 registers and most mode MODE_INT references will use integer registers.
1146 (In the rare case of an FP register used in an integer MODE, we depend
1147 on secondary reloads to clean things up.)
1150 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1151 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1152 addressing modes to be used).
1154 Put X and Z into registers. Then put the entire expression into
1158 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1159 enum machine_mode mode)
1163 /* We need to canonicalize the order of operands in unscaled indexed
1164 addresses since the code that checks if an address is valid doesn't
1165 always try both orders. */
1166 if (!TARGET_NO_SPACE_REGS
1167 && GET_CODE (x) == PLUS
1168 && GET_MODE (x) == Pmode
1169 && REG_P (XEXP (x, 0))
1170 && REG_P (XEXP (x, 1))
1171 && REG_POINTER (XEXP (x, 0))
1172 && !REG_POINTER (XEXP (x, 1)))
1173 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1176 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1178 /* Strip off CONST. */
1179 if (GET_CODE (x) == CONST)
1182 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1183 That should always be safe. */
1184 if (GET_CODE (x) == PLUS
1185 && GET_CODE (XEXP (x, 0)) == REG
1186 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1188 rtx reg = force_reg (Pmode, XEXP (x, 1));
1189 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1192 /* Note we must reject symbols which represent function addresses
1193 since the assembler/linker can't handle arithmetic on plabels. */
1194 if (GET_CODE (x) == PLUS
1195 && GET_CODE (XEXP (x, 1)) == CONST_INT
1196 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1197 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1198 || GET_CODE (XEXP (x, 0)) == REG))
1200 rtx int_part, ptr_reg;
1202 int offset = INTVAL (XEXP (x, 1));
1205 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1206 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1208 /* Choose which way to round the offset. Round up if we
1209 are >= halfway to the next boundary. */
1210 if ((offset & mask) >= ((mask + 1) / 2))
1211 newoffset = (offset & ~ mask) + mask + 1;
1213 newoffset = (offset & ~ mask);
1215 /* If the newoffset will not fit in 14 bits (ldo), then
1216 handling this would take 4 or 5 instructions (2 to load
1217 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1218 add the new offset and the SYMBOL_REF.) Combine can
1219 not handle 4->2 or 5->2 combinations, so do not create
1221 if (! VAL_14_BITS_P (newoffset)
1222 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1224 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1227 gen_rtx_HIGH (Pmode, const_part));
1230 gen_rtx_LO_SUM (Pmode,
1231 tmp_reg, const_part));
1235 if (! VAL_14_BITS_P (newoffset))
1236 int_part = force_reg (Pmode, GEN_INT (newoffset));
1238 int_part = GEN_INT (newoffset);
1240 ptr_reg = force_reg (Pmode,
1241 gen_rtx_PLUS (Pmode,
1242 force_reg (Pmode, XEXP (x, 0)),
1245 return plus_constant (ptr_reg, offset - newoffset);
1248 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1250 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1251 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1252 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1253 && (OBJECT_P (XEXP (x, 1))
1254 || GET_CODE (XEXP (x, 1)) == SUBREG)
1255 && GET_CODE (XEXP (x, 1)) != CONST)
1257 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1261 if (GET_CODE (reg1) != REG)
1262 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1264 reg2 = XEXP (XEXP (x, 0), 0);
1265 if (GET_CODE (reg2) != REG)
1266 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1268 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1269 gen_rtx_MULT (Pmode,
1275 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1277 Only do so for floating point modes since this is more speculative
1278 and we lose if it's an integer store. */
1279 if (GET_CODE (x) == PLUS
1280 && GET_CODE (XEXP (x, 0)) == PLUS
1281 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1282 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1283 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1284 && (mode == SFmode || mode == DFmode))
1287 /* First, try and figure out what to use as a base register. */
1288 rtx reg1, reg2, base, idx, orig_base;
1290 reg1 = XEXP (XEXP (x, 0), 1);
1295 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1296 then emit_move_sequence will turn on REG_POINTER so we'll know
1297 it's a base register below. */
1298 if (GET_CODE (reg1) != REG)
1299 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1301 if (GET_CODE (reg2) != REG)
1302 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1304 /* Figure out what the base and index are. */
1306 if (GET_CODE (reg1) == REG
1307 && REG_POINTER (reg1))
1310 orig_base = XEXP (XEXP (x, 0), 1);
1311 idx = gen_rtx_PLUS (Pmode,
1312 gen_rtx_MULT (Pmode,
1313 XEXP (XEXP (XEXP (x, 0), 0), 0),
1314 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1317 else if (GET_CODE (reg2) == REG
1318 && REG_POINTER (reg2))
1321 orig_base = XEXP (x, 1);
1328 /* If the index adds a large constant, try to scale the
1329 constant so that it can be loaded with only one insn. */
1330 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1331 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1332 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1333 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1335 /* Divide the CONST_INT by the scale factor, then add it to A. */
1336 int val = INTVAL (XEXP (idx, 1));
1338 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1339 reg1 = XEXP (XEXP (idx, 0), 0);
1340 if (GET_CODE (reg1) != REG)
1341 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1343 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1345 /* We can now generate a simple scaled indexed address. */
1348 (Pmode, gen_rtx_PLUS (Pmode,
1349 gen_rtx_MULT (Pmode, reg1,
1350 XEXP (XEXP (idx, 0), 1)),
1354 /* If B + C is still a valid base register, then add them. */
1355 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1356 && INTVAL (XEXP (idx, 1)) <= 4096
1357 && INTVAL (XEXP (idx, 1)) >= -4096)
1359 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1362 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1364 reg2 = XEXP (XEXP (idx, 0), 0);
1365 if (GET_CODE (reg2) != CONST_INT)
1366 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1368 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1369 gen_rtx_MULT (Pmode,
1375 /* Get the index into a register, then add the base + index and
1376 return a register holding the result. */
1378 /* First get A into a register. */
1379 reg1 = XEXP (XEXP (idx, 0), 0);
1380 if (GET_CODE (reg1) != REG)
1381 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1383 /* And get B into a register. */
1384 reg2 = XEXP (idx, 1);
1385 if (GET_CODE (reg2) != REG)
1386 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1388 reg1 = force_reg (Pmode,
1389 gen_rtx_PLUS (Pmode,
1390 gen_rtx_MULT (Pmode, reg1,
1391 XEXP (XEXP (idx, 0), 1)),
1394 /* Add the result to our base register and return. */
1395 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1399 /* Uh-oh. We might have an address for x[n-100000]. This needs
1400 special handling to avoid creating an indexed memory address
1401 with x-100000 as the base.
1403 If the constant part is small enough, then it's still safe because
1404 there is a guard page at the beginning and end of the data segment.
1406 Scaled references are common enough that we want to try and rearrange the
1407 terms so that we can use indexing for these addresses too. Only
1408 do the optimization for floatint point modes. */
1410 if (GET_CODE (x) == PLUS
1411 && symbolic_expression_p (XEXP (x, 1)))
1413 /* Ugly. We modify things here so that the address offset specified
1414 by the index expression is computed first, then added to x to form
1415 the entire address. */
1417 rtx regx1, regx2, regy1, regy2, y;
1419 /* Strip off any CONST. */
1421 if (GET_CODE (y) == CONST)
1424 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1426 /* See if this looks like
1427 (plus (mult (reg) (shadd_const))
1428 (const (plus (symbol_ref) (const_int))))
1430 Where const_int is small. In that case the const
1431 expression is a valid pointer for indexing.
1433 If const_int is big, but can be divided evenly by shadd_const
1434 and added to (reg). This allows more scaled indexed addresses. */
1435 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1436 && GET_CODE (XEXP (x, 0)) == MULT
1437 && GET_CODE (XEXP (y, 1)) == CONST_INT
1438 && INTVAL (XEXP (y, 1)) >= -4096
1439 && INTVAL (XEXP (y, 1)) <= 4095
1440 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1441 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1443 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1447 if (GET_CODE (reg1) != REG)
1448 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1450 reg2 = XEXP (XEXP (x, 0), 0);
1451 if (GET_CODE (reg2) != REG)
1452 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1454 return force_reg (Pmode,
1455 gen_rtx_PLUS (Pmode,
1456 gen_rtx_MULT (Pmode,
1461 else if ((mode == DFmode || mode == SFmode)
1462 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1463 && GET_CODE (XEXP (x, 0)) == MULT
1464 && GET_CODE (XEXP (y, 1)) == CONST_INT
1465 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1466 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1467 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1470 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1471 / INTVAL (XEXP (XEXP (x, 0), 1))));
1472 regx2 = XEXP (XEXP (x, 0), 0);
1473 if (GET_CODE (regx2) != REG)
1474 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1475 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1479 gen_rtx_PLUS (Pmode,
1480 gen_rtx_MULT (Pmode, regx2,
1481 XEXP (XEXP (x, 0), 1)),
1482 force_reg (Pmode, XEXP (y, 0))));
1484 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1485 && INTVAL (XEXP (y, 1)) >= -4096
1486 && INTVAL (XEXP (y, 1)) <= 4095)
1488 /* This is safe because of the guard page at the
1489 beginning and end of the data space. Just
1490 return the original address. */
1495 /* Doesn't look like one we can optimize. */
1496 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1497 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1498 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1499 regx1 = force_reg (Pmode,
1500 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1502 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1510 /* For the HPPA, REG and REG+CONST is cost 0
1511 and addresses involving symbolic constants are cost 2.
1513 PIC addresses are very expensive.
1515 It is no coincidence that this has the same structure
1516 as GO_IF_LEGITIMATE_ADDRESS. */
1519 hppa_address_cost (rtx X)
1521 switch (GET_CODE (X))
1534 /* Compute a (partial) cost for rtx X. Return true if the complete
1535 cost has been computed, and false if subexpressions should be
1536 scanned. In either case, *TOTAL contains the cost result. */
1539 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1544 if (INTVAL (x) == 0)
1546 else if (INT_14_BITS (x))
1563 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1564 && outer_code != SET)
1571 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1572 *total = COSTS_N_INSNS (3);
1573 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1574 *total = COSTS_N_INSNS (8);
1576 *total = COSTS_N_INSNS (20);
1580 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1582 *total = COSTS_N_INSNS (14);
1590 *total = COSTS_N_INSNS (60);
1593 case PLUS: /* this includes shNadd insns */
1595 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1596 *total = COSTS_N_INSNS (3);
1598 *total = COSTS_N_INSNS (1);
1604 *total = COSTS_N_INSNS (1);
1612 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1613 new rtx with the correct mode. */
1615 force_mode (enum machine_mode mode, rtx orig)
1617 if (mode == GET_MODE (orig))
1620 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1623 return gen_rtx_REG (mode, REGNO (orig));
1626 /* Emit insns to move operands[1] into operands[0].
1628 Return 1 if we have written out everything that needs to be done to
1629 do the move. Otherwise, return 0 and the caller will emit the move
1632 Note SCRATCH_REG may not be in the proper mode depending on how it
1633 will be used. This routine is responsible for creating a new copy
1634 of SCRATCH_REG in the proper mode. */
1637 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1639 register rtx operand0 = operands[0];
1640 register rtx operand1 = operands[1];
1643 /* We can only handle indexed addresses in the destination operand
1644 of floating point stores. Thus, we need to break out indexed
1645 addresses from the destination operand. */
1646 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1648 /* This is only safe up to the beginning of life analysis. */
1652 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1653 operand0 = replace_equiv_address (operand0, tem);
1656 /* On targets with non-equivalent space registers, break out unscaled
1657 indexed addresses from the source operand before the final CSE.
1658 We have to do this because the REG_POINTER flag is not correctly
1659 carried through various optimization passes and CSE may substitute
1660 a pseudo without the pointer set for one with the pointer set. As
1661 a result, we loose various opportunities to create insns with
1662 unscaled indexed addresses. */
1663 if (!TARGET_NO_SPACE_REGS
1664 && !cse_not_expected
1665 && GET_CODE (operand1) == MEM
1666 && GET_CODE (XEXP (operand1, 0)) == PLUS
1667 && REG_P (XEXP (XEXP (operand1, 0), 0))
1668 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1670 = replace_equiv_address (operand1,
1671 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1674 && reload_in_progress && GET_CODE (operand0) == REG
1675 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1676 operand0 = reg_equiv_mem[REGNO (operand0)];
1677 else if (scratch_reg
1678 && reload_in_progress && GET_CODE (operand0) == SUBREG
1679 && GET_CODE (SUBREG_REG (operand0)) == REG
1680 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1682 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1683 the code which tracks sets/uses for delete_output_reload. */
1684 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1685 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1686 SUBREG_BYTE (operand0));
1687 operand0 = alter_subreg (&temp);
1691 && reload_in_progress && GET_CODE (operand1) == REG
1692 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1693 operand1 = reg_equiv_mem[REGNO (operand1)];
1694 else if (scratch_reg
1695 && reload_in_progress && GET_CODE (operand1) == SUBREG
1696 && GET_CODE (SUBREG_REG (operand1)) == REG
1697 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1699 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1700 the code which tracks sets/uses for delete_output_reload. */
1701 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1702 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1703 SUBREG_BYTE (operand1));
1704 operand1 = alter_subreg (&temp);
1707 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1708 && ((tem = find_replacement (&XEXP (operand0, 0)))
1709 != XEXP (operand0, 0)))
1710 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1712 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1713 && ((tem = find_replacement (&XEXP (operand1, 0)))
1714 != XEXP (operand1, 0)))
1715 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1717 /* Handle secondary reloads for loads/stores of FP registers from
1718 REG+D addresses where D does not fit in 5 or 14 bits, including
1719 (subreg (mem (addr))) cases. */
1721 && fp_reg_operand (operand0, mode)
1722 && ((GET_CODE (operand1) == MEM
1723 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1724 XEXP (operand1, 0)))
1725 || ((GET_CODE (operand1) == SUBREG
1726 && GET_CODE (XEXP (operand1, 0)) == MEM
1727 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1729 XEXP (XEXP (operand1, 0), 0))))))
1731 if (GET_CODE (operand1) == SUBREG)
1732 operand1 = XEXP (operand1, 0);
1734 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1735 it in WORD_MODE regardless of what mode it was originally given
1737 scratch_reg = force_mode (word_mode, scratch_reg);
1739 /* D might not fit in 14 bits either; for such cases load D into
1741 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1743 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1744 emit_move_insn (scratch_reg,
1745 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1747 XEXP (XEXP (operand1, 0), 0),
1751 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1752 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1753 gen_rtx_MEM (mode, scratch_reg)));
1756 else if (scratch_reg
1757 && fp_reg_operand (operand1, mode)
1758 && ((GET_CODE (operand0) == MEM
1759 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1761 XEXP (operand0, 0)))
1762 || ((GET_CODE (operand0) == SUBREG)
1763 && GET_CODE (XEXP (operand0, 0)) == MEM
1764 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1766 XEXP (XEXP (operand0, 0), 0)))))
1768 if (GET_CODE (operand0) == SUBREG)
1769 operand0 = XEXP (operand0, 0);
1771 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1772 it in WORD_MODE regardless of what mode it was originally given
1774 scratch_reg = force_mode (word_mode, scratch_reg);
1776 /* D might not fit in 14 bits either; for such cases load D into
1778 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1780 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1781 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1784 XEXP (XEXP (operand0, 0),
1789 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1790 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1794 /* Handle secondary reloads for loads of FP registers from constant
1795 expressions by forcing the constant into memory.
1797 Use scratch_reg to hold the address of the memory location.
1799 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1800 NO_REGS when presented with a const_int and a register class
1801 containing only FP registers. Doing so unfortunately creates
1802 more problems than it solves. Fix this for 2.5. */
1803 else if (scratch_reg
1804 && CONSTANT_P (operand1)
1805 && fp_reg_operand (operand0, mode))
1809 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1810 it in WORD_MODE regardless of what mode it was originally given
1812 scratch_reg = force_mode (word_mode, scratch_reg);
1814 /* Force the constant into memory and put the address of the
1815 memory location into scratch_reg. */
1816 xoperands[0] = scratch_reg;
1817 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1818 emit_move_sequence (xoperands, Pmode, 0);
1820 /* Now load the destination register. */
1821 emit_insn (gen_rtx_SET (mode, operand0,
1822 gen_rtx_MEM (mode, scratch_reg)));
1825 /* Handle secondary reloads for SAR. These occur when trying to load
1826 the SAR from memory, FP register, or with a constant. */
1827 else if (scratch_reg
1828 && GET_CODE (operand0) == REG
1829 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1830 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1831 && (GET_CODE (operand1) == MEM
1832 || GET_CODE (operand1) == CONST_INT
1833 || (GET_CODE (operand1) == REG
1834 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1836 /* D might not fit in 14 bits either; for such cases load D into
1838 if (GET_CODE (operand1) == MEM
1839 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1841 /* We are reloading the address into the scratch register, so we
1842 want to make sure the scratch register is a full register. */
1843 scratch_reg = force_mode (word_mode, scratch_reg);
1845 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1846 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1849 XEXP (XEXP (operand1, 0),
1853 /* Now we are going to load the scratch register from memory,
1854 we want to load it in the same width as the original MEM,
1855 which must be the same as the width of the ultimate destination,
1857 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1859 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1864 /* We want to load the scratch register using the same mode as
1865 the ultimate destination. */
1866 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1868 emit_move_insn (scratch_reg, operand1);
1871 /* And emit the insn to set the ultimate destination. We know that
1872 the scratch register has the same mode as the destination at this
1874 emit_move_insn (operand0, scratch_reg);
1877 /* Handle the most common case: storing into a register. */
1878 else if (register_operand (operand0, mode))
1880 if (register_operand (operand1, mode)
1881 || (GET_CODE (operand1) == CONST_INT
1882 && cint_ok_for_move (INTVAL (operand1)))
1883 || (operand1 == CONST0_RTX (mode))
1884 || (GET_CODE (operand1) == HIGH
1885 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1886 /* Only `general_operands' can come here, so MEM is ok. */
1887 || GET_CODE (operand1) == MEM)
1889 /* Various sets are created during RTL generation which don't
1890 have the REG_POINTER flag correctly set. After the CSE pass,
1891 instruction recognition can fail if we don't consistently
1892 set this flag when performing register copies. This should
1893 also improve the opportunities for creating insns that use
1894 unscaled indexing. */
1895 if (REG_P (operand0) && REG_P (operand1))
1897 if (REG_POINTER (operand1)
1898 && !REG_POINTER (operand0)
1899 && !HARD_REGISTER_P (operand0))
1900 copy_reg_pointer (operand0, operand1);
1901 else if (REG_POINTER (operand0)
1902 && !REG_POINTER (operand1)
1903 && !HARD_REGISTER_P (operand1))
1904 copy_reg_pointer (operand1, operand0);
1907 /* When MEMs are broken out, the REG_POINTER flag doesn't
1908 get set. In some cases, we can set the REG_POINTER flag
1909 from the declaration for the MEM. */
1910 if (REG_P (operand0)
1911 && GET_CODE (operand1) == MEM
1912 && !REG_POINTER (operand0))
1914 tree decl = MEM_EXPR (operand1);
1916 /* Set the register pointer flag and register alignment
1917 if the declaration for this memory reference is a
1918 pointer type. Fortran indirect argument references
1921 && !(flag_argument_noalias > 1
1922 && TREE_CODE (decl) == INDIRECT_REF
1923 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1927 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1929 if (TREE_CODE (decl) == COMPONENT_REF)
1930 decl = TREE_OPERAND (decl, 1);
1932 type = TREE_TYPE (decl);
1933 if (TREE_CODE (type) == ARRAY_TYPE)
1934 type = get_inner_array_type (type);
1936 if (POINTER_TYPE_P (type))
1940 type = TREE_TYPE (type);
1941 /* Using TYPE_ALIGN_OK is rather conservative as
1942 only the ada frontend actually sets it. */
1943 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1945 mark_reg_pointer (operand0, align);
1950 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1954 else if (GET_CODE (operand0) == MEM)
1956 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1957 && !(reload_in_progress || reload_completed))
1959 rtx temp = gen_reg_rtx (DFmode);
1961 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1962 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1965 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1967 /* Run this case quickly. */
1968 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1971 if (! (reload_in_progress || reload_completed))
1973 operands[0] = validize_mem (operand0);
1974 operands[1] = operand1 = force_reg (mode, operand1);
1978 /* Simplify the source if we need to.
1979 Note we do have to handle function labels here, even though we do
1980 not consider them legitimate constants. Loop optimizations can
1981 call the emit_move_xxx with one as a source. */
1982 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1983 || function_label_operand (operand1, mode)
1984 || (GET_CODE (operand1) == HIGH
1985 && symbolic_operand (XEXP (operand1, 0), mode)))
1989 if (GET_CODE (operand1) == HIGH)
1992 operand1 = XEXP (operand1, 0);
1994 if (symbolic_operand (operand1, mode))
1996 /* Argh. The assembler and linker can't handle arithmetic
1999 So we force the plabel into memory, load operand0 from
2000 the memory location, then add in the constant part. */
2001 if ((GET_CODE (operand1) == CONST
2002 && GET_CODE (XEXP (operand1, 0)) == PLUS
2003 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
2004 || function_label_operand (operand1, mode))
2006 rtx temp, const_part;
2008 /* Figure out what (if any) scratch register to use. */
2009 if (reload_in_progress || reload_completed)
2011 scratch_reg = scratch_reg ? scratch_reg : operand0;
2012 /* SCRATCH_REG will hold an address and maybe the actual
2013 data. We want it in WORD_MODE regardless of what mode it
2014 was originally given to us. */
2015 scratch_reg = force_mode (word_mode, scratch_reg);
2018 scratch_reg = gen_reg_rtx (Pmode);
2020 if (GET_CODE (operand1) == CONST)
2022 /* Save away the constant part of the expression. */
2023 const_part = XEXP (XEXP (operand1, 0), 1);
2024 if (GET_CODE (const_part) != CONST_INT)
2027 /* Force the function label into memory. */
2028 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
2032 /* No constant part. */
2033 const_part = NULL_RTX;
2035 /* Force the function label into memory. */
2036 temp = force_const_mem (mode, operand1);
2040 /* Get the address of the memory location. PIC-ify it if
2042 temp = XEXP (temp, 0);
2044 temp = legitimize_pic_address (temp, mode, scratch_reg);
2046 /* Put the address of the memory location into our destination
2049 emit_move_sequence (operands, mode, scratch_reg);
2051 /* Now load from the memory location into our destination
2053 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
2054 emit_move_sequence (operands, mode, scratch_reg);
2056 /* And add back in the constant part. */
2057 if (const_part != NULL_RTX)
2058 expand_inc (operand0, const_part);
2067 if (reload_in_progress || reload_completed)
2069 temp = scratch_reg ? scratch_reg : operand0;
2070 /* TEMP will hold an address and maybe the actual
2071 data. We want it in WORD_MODE regardless of what mode it
2072 was originally given to us. */
2073 temp = force_mode (word_mode, temp);
2076 temp = gen_reg_rtx (Pmode);
2078 /* (const (plus (symbol) (const_int))) must be forced to
2079 memory during/after reload if the const_int will not fit
2081 if (GET_CODE (operand1) == CONST
2082 && GET_CODE (XEXP (operand1, 0)) == PLUS
2083 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
2084 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
2085 && (reload_completed || reload_in_progress)
2088 operands[1] = force_const_mem (mode, operand1);
2089 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
2091 operands[1] = gen_rtx_MEM (mode, operands[1]);
2092 emit_move_sequence (operands, mode, temp);
2096 operands[1] = legitimize_pic_address (operand1, mode, temp);
2097 if (REG_P (operand0) && REG_P (operands[1]))
2098 copy_reg_pointer (operand0, operands[1]);
2099 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2102 /* On the HPPA, references to data space are supposed to use dp,
2103 register 27, but showing it in the RTL inhibits various cse
2104 and loop optimizations. */
2109 if (reload_in_progress || reload_completed)
2111 temp = scratch_reg ? scratch_reg : operand0;
2112 /* TEMP will hold an address and maybe the actual
2113 data. We want it in WORD_MODE regardless of what mode it
2114 was originally given to us. */
2115 temp = force_mode (word_mode, temp);
2118 temp = gen_reg_rtx (mode);
2120 /* Loading a SYMBOL_REF into a register makes that register
2121 safe to be used as the base in an indexed address.
2123 Don't mark hard registers though. That loses. */
2124 if (GET_CODE (operand0) == REG
2125 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2126 mark_reg_pointer (operand0, BITS_PER_UNIT);
2127 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2128 mark_reg_pointer (temp, BITS_PER_UNIT);
2131 set = gen_rtx_SET (mode, operand0, temp);
2133 set = gen_rtx_SET (VOIDmode,
2135 gen_rtx_LO_SUM (mode, temp, operand1));
2137 emit_insn (gen_rtx_SET (VOIDmode,
2139 gen_rtx_HIGH (mode, operand1)));
2145 else if (GET_CODE (operand1) != CONST_INT
2146 || !cint_ok_for_move (INTVAL (operand1)))
2150 HOST_WIDE_INT value = 0;
2151 HOST_WIDE_INT insv = 0;
2154 if (GET_CODE (operand1) == CONST_INT)
2155 value = INTVAL (operand1);
2158 && GET_CODE (operand1) == CONST_INT
2159 && HOST_BITS_PER_WIDE_INT > 32
2160 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2164 /* Extract the low order 32 bits of the value and sign extend.
2165 If the new value is the same as the original value, we can
2166 can use the original value as-is. If the new value is
2167 different, we use it and insert the most-significant 32-bits
2168 of the original value into the final result. */
2169 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2170 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2173 #if HOST_BITS_PER_WIDE_INT > 32
2174 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2178 operand1 = GEN_INT (nval);
2182 if (reload_in_progress || reload_completed)
2183 temp = scratch_reg ? scratch_reg : operand0;
2185 temp = gen_reg_rtx (mode);
2187 /* We don't directly split DImode constants on 32-bit targets
2188 because PLUS uses an 11-bit immediate and the insn sequence
2189 generated is not as efficient as the one using HIGH/LO_SUM. */
2190 if (GET_CODE (operand1) == CONST_INT
2191 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2194 /* Directly break constant into high and low parts. This
2195 provides better optimization opportunities because various
2196 passes recognize constants split with PLUS but not LO_SUM.
2197 We use a 14-bit signed low part except when the addition
2198 of 0x4000 to the high part might change the sign of the
2200 HOST_WIDE_INT low = value & 0x3fff;
2201 HOST_WIDE_INT high = value & ~ 0x3fff;
2205 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2213 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2214 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2218 emit_insn (gen_rtx_SET (VOIDmode, temp,
2219 gen_rtx_HIGH (mode, operand1)));
2220 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2223 insn = emit_move_insn (operands[0], operands[1]);
2225 /* Now insert the most significant 32 bits of the value
2226 into the register. When we don't have a second register
2227 available, it could take up to nine instructions to load
2228 a 64-bit integer constant. Prior to reload, we force
2229 constants that would take more than three instructions
2230 to load to the constant pool. During and after reload,
2231 we have to handle all possible values. */
2234 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2235 register and the value to be inserted is outside the
2236 range that can be loaded with three depdi instructions. */
2237 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2239 operand1 = GEN_INT (insv);
2241 emit_insn (gen_rtx_SET (VOIDmode, temp,
2242 gen_rtx_HIGH (mode, operand1)));
2243 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2244 emit_insn (gen_insv (operand0, GEN_INT (32),
2249 int len = 5, pos = 27;
2251 /* Insert the bits using the depdi instruction. */
2254 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2255 HOST_WIDE_INT sign = v5 < 0;
2257 /* Left extend the insertion. */
2258 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2259 while (pos > 0 && (insv & 1) == sign)
2261 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2266 emit_insn (gen_insv (operand0, GEN_INT (len),
2267 GEN_INT (pos), GEN_INT (v5)));
2269 len = pos > 0 && pos < 5 ? pos : 5;
2276 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2281 /* Now have insn-emit do whatever it normally does. */
2285 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2286 it will need a link/runtime reloc). */
2289 reloc_needed (tree exp)
2293 switch (TREE_CODE (exp))
2300 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2301 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2306 case NON_LVALUE_EXPR:
2307 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2313 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2314 if (TREE_VALUE (link) != 0)
2315 reloc |= reloc_needed (TREE_VALUE (link));
2328 /* Does operand (which is a symbolic_operand) live in text space?
2329 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2333 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2335 if (GET_CODE (operand) == CONST)
2336 operand = XEXP (XEXP (operand, 0), 0);
2339 if (GET_CODE (operand) == SYMBOL_REF)
2340 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2344 if (GET_CODE (operand) == SYMBOL_REF)
2345 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2351 /* Return the best assembler insn template
2352 for moving operands[1] into operands[0] as a fullword. */
2354 singlemove_string (rtx *operands)
2356 HOST_WIDE_INT intval;
2358 if (GET_CODE (operands[0]) == MEM)
2359 return "stw %r1,%0";
2360 if (GET_CODE (operands[1]) == MEM)
2362 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2367 if (GET_MODE (operands[1]) != SFmode)
2370 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2372 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2373 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2375 operands[1] = GEN_INT (i);
2376 /* Fall through to CONST_INT case. */
2378 if (GET_CODE (operands[1]) == CONST_INT)
2380 intval = INTVAL (operands[1]);
2382 if (VAL_14_BITS_P (intval))
2384 else if ((intval & 0x7ff) == 0)
2385 return "ldil L'%1,%0";
2386 else if (zdepi_cint_p (intval))
2387 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2389 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2391 return "copy %1,%0";
2395 /* Compute position (in OP[1]) and width (in OP[2])
2396 useful for copying IMM to a register using the zdepi
2397 instructions. Store the immediate value to insert in OP[0]. */
2399 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2403 /* Find the least significant set bit in IMM. */
2404 for (lsb = 0; lsb < 32; lsb++)
2411 /* Choose variants based on *sign* of the 5-bit field. */
2412 if ((imm & 0x10) == 0)
2413 len = (lsb <= 28) ? 4 : 32 - lsb;
2416 /* Find the width of the bitstring in IMM. */
2417 for (len = 5; len < 32; len++)
2419 if ((imm & (1 << len)) == 0)
2423 /* Sign extend IMM as a 5-bit value. */
2424 imm = (imm & 0xf) - 0x10;
2432 /* Compute position (in OP[1]) and width (in OP[2])
2433 useful for copying IMM to a register using the depdi,z
2434 instructions. Store the immediate value to insert in OP[0]. */
2436 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2438 HOST_WIDE_INT lsb, len;
2440 /* Find the least significant set bit in IMM. */
2441 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2448 /* Choose variants based on *sign* of the 5-bit field. */
2449 if ((imm & 0x10) == 0)
2450 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2451 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2454 /* Find the width of the bitstring in IMM. */
2455 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2457 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2461 /* Sign extend IMM as a 5-bit value. */
2462 imm = (imm & 0xf) - 0x10;
2470 /* Output assembler code to perform a doubleword move insn
2471 with operands OPERANDS. */
2474 output_move_double (rtx *operands)
2476 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2478 rtx addreg0 = 0, addreg1 = 0;
2480 /* First classify both operands. */
2482 if (REG_P (operands[0]))
2484 else if (offsettable_memref_p (operands[0]))
2486 else if (GET_CODE (operands[0]) == MEM)
2491 if (REG_P (operands[1]))
2493 else if (CONSTANT_P (operands[1]))
2495 else if (offsettable_memref_p (operands[1]))
2497 else if (GET_CODE (operands[1]) == MEM)
2502 /* Check for the cases that the operand constraints are not
2503 supposed to allow to happen. Abort if we get one,
2504 because generating code for these cases is painful. */
2506 if (optype0 != REGOP && optype1 != REGOP)
2509 /* Handle auto decrementing and incrementing loads and stores
2510 specifically, since the structure of the function doesn't work
2511 for them without major modification. Do it better when we learn
2512 this port about the general inc/dec addressing of PA.
2513 (This was written by tege. Chide him if it doesn't work.) */
2515 if (optype0 == MEMOP)
2517 /* We have to output the address syntax ourselves, since print_operand
2518 doesn't deal with the addresses we want to use. Fix this later. */
2520 rtx addr = XEXP (operands[0], 0);
2521 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2523 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2525 operands[0] = XEXP (addr, 0);
2526 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2529 if (!reg_overlap_mentioned_p (high_reg, addr))
2531 /* No overlap between high target register and address
2532 register. (We do this in a non-obvious way to
2533 save a register file writeback) */
2534 if (GET_CODE (addr) == POST_INC)
2535 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2536 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2541 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2543 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2545 operands[0] = XEXP (addr, 0);
2546 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2549 if (!reg_overlap_mentioned_p (high_reg, addr))
2551 /* No overlap between high target register and address
2552 register. (We do this in a non-obvious way to
2553 save a register file writeback) */
2554 if (GET_CODE (addr) == PRE_INC)
2555 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2556 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2562 if (optype1 == MEMOP)
2564 /* We have to output the address syntax ourselves, since print_operand
2565 doesn't deal with the addresses we want to use. Fix this later. */
2567 rtx addr = XEXP (operands[1], 0);
2568 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2570 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2572 operands[1] = XEXP (addr, 0);
2573 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2576 if (!reg_overlap_mentioned_p (high_reg, addr))
2578 /* No overlap between high target register and address
2579 register. (We do this in a non-obvious way to
2580 save a register file writeback) */
2581 if (GET_CODE (addr) == POST_INC)
2582 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2583 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2587 /* This is an undefined situation. We should load into the
2588 address register *and* update that register. Probably
2589 we don't need to handle this at all. */
2590 if (GET_CODE (addr) == POST_INC)
2591 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2592 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2595 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2597 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2599 operands[1] = XEXP (addr, 0);
2600 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2603 if (!reg_overlap_mentioned_p (high_reg, addr))
2605 /* No overlap between high target register and address
2606 register. (We do this in a non-obvious way to
2607 save a register file writeback) */
2608 if (GET_CODE (addr) == PRE_INC)
2609 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2610 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2614 /* This is an undefined situation. We should load into the
2615 address register *and* update that register. Probably
2616 we don't need to handle this at all. */
2617 if (GET_CODE (addr) == PRE_INC)
2618 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2619 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2622 else if (GET_CODE (addr) == PLUS
2623 && GET_CODE (XEXP (addr, 0)) == MULT)
2625 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2627 if (!reg_overlap_mentioned_p (high_reg, addr))
2631 xoperands[0] = high_reg;
2632 xoperands[1] = XEXP (addr, 1);
2633 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2634 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2635 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2637 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2643 xoperands[0] = high_reg;
2644 xoperands[1] = XEXP (addr, 1);
2645 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2646 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2647 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2649 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2654 /* If an operand is an unoffsettable memory ref, find a register
2655 we can increment temporarily to make it refer to the second word. */
2657 if (optype0 == MEMOP)
2658 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2660 if (optype1 == MEMOP)
2661 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2663 /* Ok, we can do one word at a time.
2664 Normally we do the low-numbered word first.
2666 In either case, set up in LATEHALF the operands to use
2667 for the high-numbered word and in some cases alter the
2668 operands in OPERANDS to be suitable for the low-numbered word. */
2670 if (optype0 == REGOP)
2671 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2672 else if (optype0 == OFFSOP)
2673 latehalf[0] = adjust_address (operands[0], SImode, 4);
2675 latehalf[0] = operands[0];
2677 if (optype1 == REGOP)
2678 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2679 else if (optype1 == OFFSOP)
2680 latehalf[1] = adjust_address (operands[1], SImode, 4);
2681 else if (optype1 == CNSTOP)
2682 split_double (operands[1], &operands[1], &latehalf[1]);
2684 latehalf[1] = operands[1];
2686 /* If the first move would clobber the source of the second one,
2687 do them in the other order.
2689 This can happen in two cases:
2691 mem -> register where the first half of the destination register
2692 is the same register used in the memory's address. Reload
2693 can create such insns.
2695 mem in this case will be either register indirect or register
2696 indirect plus a valid offset.
2698 register -> register move where REGNO(dst) == REGNO(src + 1)
2699 someone (Tim/Tege?) claimed this can happen for parameter loads.
2701 Handle mem -> register case first. */
2702 if (optype0 == REGOP
2703 && (optype1 == MEMOP || optype1 == OFFSOP)
2704 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2707 /* Do the late half first. */
2709 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2710 output_asm_insn (singlemove_string (latehalf), latehalf);
2714 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2715 return singlemove_string (operands);
2718 /* Now handle register -> register case. */
2719 if (optype0 == REGOP && optype1 == REGOP
2720 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2722 output_asm_insn (singlemove_string (latehalf), latehalf);
2723 return singlemove_string (operands);
2726 /* Normal case: do the two words, low-numbered first. */
2728 output_asm_insn (singlemove_string (operands), operands);
2730 /* Make any unoffsettable addresses point at high-numbered word. */
2732 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2734 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2737 output_asm_insn (singlemove_string (latehalf), latehalf);
2739 /* Undo the adds we just did. */
2741 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2743 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2749 output_fp_move_double (rtx *operands)
2751 if (FP_REG_P (operands[0]))
2753 if (FP_REG_P (operands[1])
2754 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2755 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2757 output_asm_insn ("fldd%F1 %1,%0", operands);
2759 else if (FP_REG_P (operands[1]))
2761 output_asm_insn ("fstd%F0 %1,%0", operands);
2763 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2765 if (GET_CODE (operands[0]) == REG)
2768 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2769 xoperands[0] = operands[0];
2770 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2772 /* This is a pain. You have to be prepared to deal with an
2773 arbitrary address here including pre/post increment/decrement.
2775 so avoid this in the MD. */
2783 /* Return a REG that occurs in ADDR with coefficient 1.
2784 ADDR can be effectively incremented by incrementing REG. */
2787 find_addr_reg (rtx addr)
2789 while (GET_CODE (addr) == PLUS)
2791 if (GET_CODE (XEXP (addr, 0)) == REG)
2792 addr = XEXP (addr, 0);
2793 else if (GET_CODE (XEXP (addr, 1)) == REG)
2794 addr = XEXP (addr, 1);
2795 else if (CONSTANT_P (XEXP (addr, 0)))
2796 addr = XEXP (addr, 1);
2797 else if (CONSTANT_P (XEXP (addr, 1)))
2798 addr = XEXP (addr, 0);
2802 if (GET_CODE (addr) == REG)
2807 /* Emit code to perform a block move.
2809 OPERANDS[0] is the destination pointer as a REG, clobbered.
2810 OPERANDS[1] is the source pointer as a REG, clobbered.
2811 OPERANDS[2] is a register for temporary storage.
2812 OPERANDS[3] is a register for temporary storage.
2813 OPERANDS[4] is the size as a CONST_INT
2814 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2815 OPERANDS[6] is another temporary register. */
2818 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2820 int align = INTVAL (operands[5]);
2821 unsigned long n_bytes = INTVAL (operands[4]);
2823 /* We can't move more than a word at a time because the PA
2824 has no longer integer move insns. (Could use fp mem ops?) */
2825 if (align > (TARGET_64BIT ? 8 : 4))
2826 align = (TARGET_64BIT ? 8 : 4);
2828 /* Note that we know each loop below will execute at least twice
2829 (else we would have open-coded the copy). */
2833 /* Pre-adjust the loop counter. */
2834 operands[4] = GEN_INT (n_bytes - 16);
2835 output_asm_insn ("ldi %4,%2", operands);
2838 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2839 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2840 output_asm_insn ("std,ma %3,8(%0)", operands);
2841 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2842 output_asm_insn ("std,ma %6,8(%0)", operands);
2844 /* Handle the residual. There could be up to 7 bytes of
2845 residual to copy! */
2846 if (n_bytes % 16 != 0)
2848 operands[4] = GEN_INT (n_bytes % 8);
2849 if (n_bytes % 16 >= 8)
2850 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2851 if (n_bytes % 8 != 0)
2852 output_asm_insn ("ldd 0(%1),%6", operands);
2853 if (n_bytes % 16 >= 8)
2854 output_asm_insn ("std,ma %3,8(%0)", operands);
2855 if (n_bytes % 8 != 0)
2856 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2861 /* Pre-adjust the loop counter. */
2862 operands[4] = GEN_INT (n_bytes - 8);
2863 output_asm_insn ("ldi %4,%2", operands);
2866 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2867 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2868 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2869 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2870 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2872 /* Handle the residual. There could be up to 7 bytes of
2873 residual to copy! */
2874 if (n_bytes % 8 != 0)
2876 operands[4] = GEN_INT (n_bytes % 4);
2877 if (n_bytes % 8 >= 4)
2878 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2879 if (n_bytes % 4 != 0)
2880 output_asm_insn ("ldw 0(%1),%6", operands);
2881 if (n_bytes % 8 >= 4)
2882 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2883 if (n_bytes % 4 != 0)
2884 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2889 /* Pre-adjust the loop counter. */
2890 operands[4] = GEN_INT (n_bytes - 4);
2891 output_asm_insn ("ldi %4,%2", operands);
2894 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2895 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2896 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2897 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2898 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2900 /* Handle the residual. */
2901 if (n_bytes % 4 != 0)
2903 if (n_bytes % 4 >= 2)
2904 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2905 if (n_bytes % 2 != 0)
2906 output_asm_insn ("ldb 0(%1),%6", operands);
2907 if (n_bytes % 4 >= 2)
2908 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2909 if (n_bytes % 2 != 0)
2910 output_asm_insn ("stb %6,0(%0)", operands);
2915 /* Pre-adjust the loop counter. */
2916 operands[4] = GEN_INT (n_bytes - 2);
2917 output_asm_insn ("ldi %4,%2", operands);
2920 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2921 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2922 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2923 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2924 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2926 /* Handle the residual. */
2927 if (n_bytes % 2 != 0)
2929 output_asm_insn ("ldb 0(%1),%3", operands);
2930 output_asm_insn ("stb %3,0(%0)", operands);
2939 /* Count the number of insns necessary to handle this block move.
2941 Basic structure is the same as emit_block_move, except that we
2942 count insns rather than emit them. */
2945 compute_movmem_length (rtx insn)
2947 rtx pat = PATTERN (insn);
2948 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2949 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2950 unsigned int n_insns = 0;
2952 /* We can't move more than four bytes at a time because the PA
2953 has no longer integer move insns. (Could use fp mem ops?) */
2954 if (align > (TARGET_64BIT ? 8 : 4))
2955 align = (TARGET_64BIT ? 8 : 4);
2957 /* The basic copying loop. */
2961 if (n_bytes % (2 * align) != 0)
2963 if ((n_bytes % (2 * align)) >= align)
2966 if ((n_bytes % align) != 0)
2970 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2974 /* Emit code to perform a block clear.
2976 OPERANDS[0] is the destination pointer as a REG, clobbered.
2977 OPERANDS[1] is a register for temporary storage.
2978 OPERANDS[2] is the size as a CONST_INT
2979 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2982 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2984 int align = INTVAL (operands[3]);
2985 unsigned long n_bytes = INTVAL (operands[2]);
2987 /* We can't clear more than a word at a time because the PA
2988 has no longer integer move insns. */
2989 if (align > (TARGET_64BIT ? 8 : 4))
2990 align = (TARGET_64BIT ? 8 : 4);
2992 /* Note that we know each loop below will execute at least twice
2993 (else we would have open-coded the copy). */
2997 /* Pre-adjust the loop counter. */
2998 operands[2] = GEN_INT (n_bytes - 16);
2999 output_asm_insn ("ldi %2,%1", operands);
3002 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3003 output_asm_insn ("addib,>= -16,%1,.-4", operands);
3004 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3006 /* Handle the residual. There could be up to 7 bytes of
3007 residual to copy! */
3008 if (n_bytes % 16 != 0)
3010 operands[2] = GEN_INT (n_bytes % 8);
3011 if (n_bytes % 16 >= 8)
3012 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3013 if (n_bytes % 8 != 0)
3014 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
3019 /* Pre-adjust the loop counter. */
3020 operands[2] = GEN_INT (n_bytes - 8);
3021 output_asm_insn ("ldi %2,%1", operands);
3024 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3025 output_asm_insn ("addib,>= -8,%1,.-4", operands);
3026 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3028 /* Handle the residual. There could be up to 7 bytes of
3029 residual to copy! */
3030 if (n_bytes % 8 != 0)
3032 operands[2] = GEN_INT (n_bytes % 4);
3033 if (n_bytes % 8 >= 4)
3034 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3035 if (n_bytes % 4 != 0)
3036 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
3041 /* Pre-adjust the loop counter. */
3042 operands[2] = GEN_INT (n_bytes - 4);
3043 output_asm_insn ("ldi %2,%1", operands);
3046 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3047 output_asm_insn ("addib,>= -4,%1,.-4", operands);
3048 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3050 /* Handle the residual. */
3051 if (n_bytes % 4 != 0)
3053 if (n_bytes % 4 >= 2)
3054 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3055 if (n_bytes % 2 != 0)
3056 output_asm_insn ("stb %%r0,0(%0)", operands);
3061 /* Pre-adjust the loop counter. */
3062 operands[2] = GEN_INT (n_bytes - 2);
3063 output_asm_insn ("ldi %2,%1", operands);
3066 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3067 output_asm_insn ("addib,>= -2,%1,.-4", operands);
3068 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3070 /* Handle the residual. */
3071 if (n_bytes % 2 != 0)
3072 output_asm_insn ("stb %%r0,0(%0)", operands);
3081 /* Count the number of insns necessary to handle this block move.
3083 Basic structure is the same as emit_block_move, except that we
3084 count insns rather than emit them. */
3087 compute_clrmem_length (rtx insn)
3089 rtx pat = PATTERN (insn);
3090 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
3091 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
3092 unsigned int n_insns = 0;
3094 /* We can't clear more than a word at a time because the PA
3095 has no longer integer move insns. */
3096 if (align > (TARGET_64BIT ? 8 : 4))
3097 align = (TARGET_64BIT ? 8 : 4);
3099 /* The basic loop. */
3103 if (n_bytes % (2 * align) != 0)
3105 if ((n_bytes % (2 * align)) >= align)
3108 if ((n_bytes % align) != 0)
3112 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3118 output_and (rtx *operands)
3120 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3122 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3123 int ls0, ls1, ms0, p, len;
3125 for (ls0 = 0; ls0 < 32; ls0++)
3126 if ((mask & (1 << ls0)) == 0)
3129 for (ls1 = ls0; ls1 < 32; ls1++)
3130 if ((mask & (1 << ls1)) != 0)
3133 for (ms0 = ls1; ms0 < 32; ms0++)
3134 if ((mask & (1 << ms0)) == 0)
3147 operands[2] = GEN_INT (len);
3148 return "{extru|extrw,u} %1,31,%2,%0";
3152 /* We could use this `depi' for the case above as well, but `depi'
3153 requires one more register file access than an `extru'. */
3158 operands[2] = GEN_INT (p);
3159 operands[3] = GEN_INT (len);
3160 return "{depi|depwi} 0,%2,%3,%0";
3164 return "and %1,%2,%0";
3167 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3168 storing the result in operands[0]. */
3170 output_64bit_and (rtx *operands)
3172 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3174 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3175 int ls0, ls1, ms0, p, len;
3177 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3178 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3181 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3182 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3185 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3186 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3189 if (ms0 != HOST_BITS_PER_WIDE_INT)
3192 if (ls1 == HOST_BITS_PER_WIDE_INT)
3199 operands[2] = GEN_INT (len);
3200 return "extrd,u %1,63,%2,%0";
3204 /* We could use this `depi' for the case above as well, but `depi'
3205 requires one more register file access than an `extru'. */
3210 operands[2] = GEN_INT (p);
3211 operands[3] = GEN_INT (len);
3212 return "depdi 0,%2,%3,%0";
3216 return "and %1,%2,%0";
3220 output_ior (rtx *operands)
3222 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3223 int bs0, bs1, p, len;
3225 if (INTVAL (operands[2]) == 0)
3226 return "copy %1,%0";
3228 for (bs0 = 0; bs0 < 32; bs0++)
3229 if ((mask & (1 << bs0)) != 0)
3232 for (bs1 = bs0; bs1 < 32; bs1++)
3233 if ((mask & (1 << bs1)) == 0)
3236 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3242 operands[2] = GEN_INT (p);
3243 operands[3] = GEN_INT (len);
3244 return "{depi|depwi} -1,%2,%3,%0";
3247 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3248 storing the result in operands[0]. */
3250 output_64bit_ior (rtx *operands)
3252 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3253 int bs0, bs1, p, len;
3255 if (INTVAL (operands[2]) == 0)
3256 return "copy %1,%0";
3258 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3259 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3262 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3263 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3266 if (bs1 != HOST_BITS_PER_WIDE_INT
3267 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3273 operands[2] = GEN_INT (p);
3274 operands[3] = GEN_INT (len);
3275 return "depdi -1,%2,%3,%0";
3278 /* Target hook for assembling integer objects. This code handles
3279 aligned SI and DI integers specially, since function references must
3280 be preceded by P%. */
3283 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3285 if (size == UNITS_PER_WORD && aligned_p
3286 && function_label_operand (x, VOIDmode))
3288 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3289 output_addr_const (asm_out_file, x);
3290 fputc ('\n', asm_out_file);
3293 return default_assemble_integer (x, size, aligned_p);
3296 /* Output an ascii string. */
3298 output_ascii (FILE *file, const char *p, int size)
3302 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3304 /* The HP assembler can only take strings of 256 characters at one
3305 time. This is a limitation on input line length, *not* the
3306 length of the string. Sigh. Even worse, it seems that the
3307 restriction is in number of input characters (see \xnn &
3308 \whatever). So we have to do this very carefully. */
3310 fputs ("\t.STRING \"", file);
3313 for (i = 0; i < size; i += 4)
3317 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3319 register unsigned int c = (unsigned char) p[i + io];
3321 if (c == '\"' || c == '\\')
3322 partial_output[co++] = '\\';
3323 if (c >= ' ' && c < 0177)
3324 partial_output[co++] = c;
3328 partial_output[co++] = '\\';
3329 partial_output[co++] = 'x';
3330 hexd = c / 16 - 0 + '0';
3332 hexd -= '9' - 'a' + 1;
3333 partial_output[co++] = hexd;
3334 hexd = c % 16 - 0 + '0';
3336 hexd -= '9' - 'a' + 1;
3337 partial_output[co++] = hexd;
3340 if (chars_output + co > 243)
3342 fputs ("\"\n\t.STRING \"", file);
3345 fwrite (partial_output, 1, (size_t) co, file);
3349 fputs ("\"\n", file);
3352 /* Try to rewrite floating point comparisons & branches to avoid
3353 useless add,tr insns.
3355 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3356 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3357 first attempt to remove useless add,tr insns. It is zero
3358 for the second pass as reorg sometimes leaves bogus REG_DEAD
3361 When CHECK_NOTES is zero we can only eliminate add,tr insns
3362 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3365 remove_useless_addtr_insns (int check_notes)
3368 static int pass = 0;
3370 /* This is fairly cheap, so always run it when optimizing. */
3374 int fbranch_count = 0;
3376 /* Walk all the insns in this function looking for fcmp & fbranch
3377 instructions. Keep track of how many of each we find. */
3378 for (insn = get_insns (); insn; insn = next_insn (insn))
3382 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3383 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3386 tmp = PATTERN (insn);
3388 /* It must be a set. */
3389 if (GET_CODE (tmp) != SET)
3392 /* If the destination is CCFP, then we've found an fcmp insn. */
3393 tmp = SET_DEST (tmp);
3394 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3400 tmp = PATTERN (insn);
3401 /* If this is an fbranch instruction, bump the fbranch counter. */
3402 if (GET_CODE (tmp) == SET
3403 && SET_DEST (tmp) == pc_rtx
3404 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3405 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3406 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3407 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3415 /* Find all floating point compare + branch insns. If possible,
3416 reverse the comparison & the branch to avoid add,tr insns. */
3417 for (insn = get_insns (); insn; insn = next_insn (insn))
3421 /* Ignore anything that isn't an INSN. */
3422 if (GET_CODE (insn) != INSN)
3425 tmp = PATTERN (insn);
3427 /* It must be a set. */
3428 if (GET_CODE (tmp) != SET)
3431 /* The destination must be CCFP, which is register zero. */
3432 tmp = SET_DEST (tmp);
3433 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3436 /* INSN should be a set of CCFP.
3438 See if the result of this insn is used in a reversed FP
3439 conditional branch. If so, reverse our condition and
3440 the branch. Doing so avoids useless add,tr insns. */
3441 next = next_insn (insn);
3444 /* Jumps, calls and labels stop our search. */
3445 if (GET_CODE (next) == JUMP_INSN
3446 || GET_CODE (next) == CALL_INSN
3447 || GET_CODE (next) == CODE_LABEL)
3450 /* As does another fcmp insn. */
3451 if (GET_CODE (next) == INSN
3452 && GET_CODE (PATTERN (next)) == SET
3453 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3454 && REGNO (SET_DEST (PATTERN (next))) == 0)
3457 next = next_insn (next);
3460 /* Is NEXT_INSN a branch? */
3462 && GET_CODE (next) == JUMP_INSN)
3464 rtx pattern = PATTERN (next);
3466 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3467 and CCFP dies, then reverse our conditional and the branch
3468 to avoid the add,tr. */
3469 if (GET_CODE (pattern) == SET
3470 && SET_DEST (pattern) == pc_rtx
3471 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3472 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3473 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3474 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3475 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3476 && (fcmp_count == fbranch_count
3478 && find_regno_note (next, REG_DEAD, 0))))
3480 /* Reverse the branch. */
3481 tmp = XEXP (SET_SRC (pattern), 1);
3482 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3483 XEXP (SET_SRC (pattern), 2) = tmp;
3484 INSN_CODE (next) = -1;
3486 /* Reverse our condition. */
3487 tmp = PATTERN (insn);
3488 PUT_CODE (XEXP (tmp, 1),
3489 (reverse_condition_maybe_unordered
3490 (GET_CODE (XEXP (tmp, 1)))));
3500 /* You may have trouble believing this, but this is the 32 bit HP-PA
3505 Variable arguments (optional; any number may be allocated)
3507 SP-(4*(N+9)) arg word N
3512 Fixed arguments (must be allocated; may remain unused)
3521 SP-32 External Data Pointer (DP)
3523 SP-24 External/stub RP (RP')
3527 SP-8 Calling Stub RP (RP'')
3532 SP-0 Stack Pointer (points to next available address)
3536 /* This function saves registers as follows. Registers marked with ' are
3537 this function's registers (as opposed to the previous function's).
3538 If a frame_pointer isn't needed, r4 is saved as a general register;
3539 the space for the frame pointer is still allocated, though, to keep
3545 SP (FP') Previous FP
3546 SP + 4 Alignment filler (sigh)
3547 SP + 8 Space for locals reserved here.
3551 SP + n All call saved register used.
3555 SP + o All call saved fp registers used.
3559 SP + p (SP') points to next available address.
3563 /* Global variables set by output_function_prologue(). */
3564 /* Size of frame. Need to know this to emit return insns from
3566 static HOST_WIDE_INT actual_fsize, local_fsize;
3567 static int save_fregs;
3569 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3570 Handle case where DISP > 8k by using the add_high_const patterns.
3572 Note in DISP > 8k case, we will leave the high part of the address
3573 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3576 store_reg (int reg, HOST_WIDE_INT disp, int base)
3578 rtx insn, dest, src, basereg;
3580 src = gen_rtx_REG (word_mode, reg);
3581 basereg = gen_rtx_REG (Pmode, base);
3582 if (VAL_14_BITS_P (disp))
3584 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3585 insn = emit_move_insn (dest, src);
3587 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3589 rtx delta = GEN_INT (disp);
3590 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3592 emit_move_insn (tmpreg, delta);
3593 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3594 dest = gen_rtx_MEM (word_mode, tmpreg);
3595 insn = emit_move_insn (dest, src);
3599 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3600 gen_rtx_SET (VOIDmode,
3601 gen_rtx_MEM (word_mode,
3602 gen_rtx_PLUS (word_mode, basereg,
3610 rtx delta = GEN_INT (disp);
3611 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3612 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3614 emit_move_insn (tmpreg, high);
3615 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3616 insn = emit_move_insn (dest, src);
3620 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3621 gen_rtx_SET (VOIDmode,
3622 gen_rtx_MEM (word_mode,
3623 gen_rtx_PLUS (word_mode, basereg,
3631 RTX_FRAME_RELATED_P (insn) = 1;
3634 /* Emit RTL to store REG at the memory location specified by BASE and then
3635 add MOD to BASE. MOD must be <= 8k. */
3638 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3640 rtx insn, basereg, srcreg, delta;
3642 if (!VAL_14_BITS_P (mod))
3645 basereg = gen_rtx_REG (Pmode, base);
3646 srcreg = gen_rtx_REG (word_mode, reg);
3647 delta = GEN_INT (mod);
3649 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3652 RTX_FRAME_RELATED_P (insn) = 1;
3654 /* RTX_FRAME_RELATED_P must be set on each frame related set
3655 in a parallel with more than one element. Don't set
3656 RTX_FRAME_RELATED_P in the first set if reg is temporary
3657 register 1. The effect of this operation is recorded in
3658 the initial copy. */
3661 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3662 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3666 /* The first element of a PARALLEL is always processed if it is
3667 a SET. Thus, we need an expression list for this case. */
3669 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3670 gen_rtx_SET (VOIDmode, basereg,
3671 gen_rtx_PLUS (word_mode, basereg, delta)),
3677 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3678 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3679 whether to add a frame note or not.
3681 In the DISP > 8k case, we leave the high part of the address in %r1.
3682 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3685 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3689 if (VAL_14_BITS_P (disp))
3691 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3692 plus_constant (gen_rtx_REG (Pmode, base), disp));
3694 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3696 rtx basereg = gen_rtx_REG (Pmode, base);
3697 rtx delta = GEN_INT (disp);
3698 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3700 emit_move_insn (tmpreg, delta);
3701 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3702 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3706 rtx basereg = gen_rtx_REG (Pmode, base);
3707 rtx delta = GEN_INT (disp);
3708 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3710 emit_move_insn (tmpreg,
3711 gen_rtx_PLUS (Pmode, basereg,
3712 gen_rtx_HIGH (Pmode, delta)));
3713 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3714 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3717 if (DO_FRAME_NOTES && note)
3718 RTX_FRAME_RELATED_P (insn) = 1;
3722 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3727 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3728 be consistent with the rounding and size calculation done here.
3729 Change them at the same time. */
3731 /* We do our own stack alignment. First, round the size of the
3732 stack locals up to a word boundary. */
3733 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3735 /* Space for previous frame pointer + filler. If any frame is
3736 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3737 waste some space here for the sake of HP compatibility. The
3738 first slot is only used when the frame pointer is needed. */
3739 if (size || frame_pointer_needed)
3740 size += STARTING_FRAME_OFFSET;
3742 /* If the current function calls __builtin_eh_return, then we need
3743 to allocate stack space for registers that will hold data for
3744 the exception handler. */
3745 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3749 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3751 size += i * UNITS_PER_WORD;
3754 /* Account for space used by the callee general register saves. */
3755 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3756 if (regs_ever_live[i])
3757 size += UNITS_PER_WORD;
3759 /* Account for space used by the callee floating point register saves. */
3760 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3761 if (regs_ever_live[i]
3762 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3766 /* We always save both halves of the FP register, so always
3767 increment the frame size by 8 bytes. */
3771 /* If any of the floating registers are saved, account for the
3772 alignment needed for the floating point register save block. */
3775 size = (size + 7) & ~7;
3780 /* The various ABIs include space for the outgoing parameters in the
3781 size of the current function's stack frame. We don't need to align
3782 for the outgoing arguments as their alignment is set by the final
3783 rounding for the frame as a whole. */
3784 size += current_function_outgoing_args_size;
3786 /* Allocate space for the fixed frame marker. This space must be
3787 allocated for any function that makes calls or allocates
3789 if (!current_function_is_leaf || size)
3790 size += TARGET_64BIT ? 48 : 32;
3792 /* Finally, round to the preferred stack boundary. */
3793 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3794 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3797 /* Generate the assembly code for function entry. FILE is a stdio
3798 stream to output the code to. SIZE is an int: how many units of
3799 temporary storage to allocate.
3801 Refer to the array `regs_ever_live' to determine which registers to
3802 save; `regs_ever_live[I]' is nonzero if register number I is ever
3803 used in the function. This function is responsible for knowing
3804 which registers should not be saved even if used. */
3806 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3807 of memory. If any fpu reg is used in the function, we allocate
3808 such a block here, at the bottom of the frame, just in case it's needed.
3810 If this function is a leaf procedure, then we may choose not
3811 to do a "save" insn. The decision about whether or not
3812 to do this is made in regclass.c. */
3815 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3817 /* The function's label and associated .PROC must never be
3818 separated and must be output *after* any profiling declarations
3819 to avoid changing spaces/subspaces within a procedure. */
3820 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3821 fputs ("\t.PROC\n", file);
3823 /* hppa_expand_prologue does the dirty work now. We just need
3824 to output the assembler directives which denote the start
3826 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3827 if (regs_ever_live[2])
3828 fputs (",CALLS,SAVE_RP", file);
3830 fputs (",NO_CALLS", file);
3832 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3833 at the beginning of the frame and that it is used as the frame
3834 pointer for the frame. We do this because our current frame
3835 layout doesn't conform to that specified in the the HP runtime
3836 documentation and we need a way to indicate to programs such as
3837 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3838 isn't used by HP compilers but is supported by the assembler.
3839 However, SAVE_SP is supposed to indicate that the previous stack
3840 pointer has been saved in the frame marker. */
3841 if (frame_pointer_needed)
3842 fputs (",SAVE_SP", file);
3844 /* Pass on information about the number of callee register saves
3845 performed in the prologue.
3847 The compiler is supposed to pass the highest register number
3848 saved, the assembler then has to adjust that number before
3849 entering it into the unwind descriptor (to account for any
3850 caller saved registers with lower register numbers than the
3851 first callee saved register). */
3853 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3856 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3858 fputs ("\n\t.ENTRY\n", file);
3860 remove_useless_addtr_insns (0);
3864 hppa_expand_prologue (void)
3866 int merge_sp_adjust_with_store = 0;
3867 HOST_WIDE_INT size = get_frame_size ();
3868 HOST_WIDE_INT offset;
3876 /* Compute total size for frame pointer, filler, locals and rounding to
3877 the next word boundary. Similar code appears in compute_frame_size
3878 and must be changed in tandem with this code. */
3879 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3880 if (local_fsize || frame_pointer_needed)
3881 local_fsize += STARTING_FRAME_OFFSET;
3883 actual_fsize = compute_frame_size (size, &save_fregs);
3885 /* Compute a few things we will use often. */
3886 tmpreg = gen_rtx_REG (word_mode, 1);
3888 /* Save RP first. The calling conventions manual states RP will
3889 always be stored into the caller's frame at sp - 20 or sp - 16
3890 depending on which ABI is in use. */
3891 if (regs_ever_live[2] || current_function_calls_eh_return)
3892 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3894 /* Allocate the local frame and set up the frame pointer if needed. */
3895 if (actual_fsize != 0)
3897 if (frame_pointer_needed)
3899 /* Copy the old frame pointer temporarily into %r1. Set up the
3900 new stack pointer, then store away the saved old frame pointer
3901 into the stack at sp and at the same time update the stack
3902 pointer by actual_fsize bytes. Two versions, first
3903 handles small (<8k) frames. The second handles large (>=8k)
3905 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3908 /* We need to record the frame pointer save here since the
3909 new frame pointer is set in the following insn. */
3910 RTX_FRAME_RELATED_P (insn) = 1;
3912 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3913 gen_rtx_SET (VOIDmode,
3914 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3919 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3921 RTX_FRAME_RELATED_P (insn) = 1;
3923 if (VAL_14_BITS_P (actual_fsize))
3924 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3927 /* It is incorrect to store the saved frame pointer at *sp,
3928 then increment sp (writes beyond the current stack boundary).
3930 So instead use stwm to store at *sp and post-increment the
3931 stack pointer as an atomic operation. Then increment sp to
3932 finish allocating the new frame. */
3933 HOST_WIDE_INT adjust1 = 8192 - 64;
3934 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3936 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3937 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3941 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3942 we need to store the previous stack pointer (frame pointer)
3943 into the frame marker on targets that use the HP unwind
3944 library. This allows the HP unwind library to be used to
3945 unwind GCC frames. However, we are not fully compatible
3946 with the HP library because our frame layout differs from
3947 that specified in the HP runtime specification.
3949 We don't want a frame note on this instruction as the frame
3950 marker moves during dynamic stack allocation.
3952 This instruction also serves as a blockage to prevent
3953 register spills from being scheduled before the stack
3954 pointer is raised. This is necessary as we store
3955 registers using the frame pointer as a base register,
3956 and the frame pointer is set before sp is raised. */
3957 if (TARGET_HPUX_UNWIND_LIBRARY)
3959 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3960 GEN_INT (TARGET_64BIT ? -8 : -4));
3962 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3966 emit_insn (gen_blockage ());
3968 /* no frame pointer needed. */
3971 /* In some cases we can perform the first callee register save
3972 and allocating the stack frame at the same time. If so, just
3973 make a note of it and defer allocating the frame until saving
3974 the callee registers. */
3975 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3976 merge_sp_adjust_with_store = 1;
3977 /* Can not optimize. Adjust the stack frame by actual_fsize
3980 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3985 /* Normal register save.
3987 Do not save the frame pointer in the frame_pointer_needed case. It
3988 was done earlier. */
3989 if (frame_pointer_needed)
3991 offset = local_fsize;
3993 /* Saving the EH return data registers in the frame is the simplest
3994 way to get the frame unwind information emitted. We put them
3995 just before the general registers. */
3996 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3998 unsigned int i, regno;
4002 regno = EH_RETURN_DATA_REGNO (i);
4003 if (regno == INVALID_REGNUM)
4006 store_reg (regno, offset, FRAME_POINTER_REGNUM);
4007 offset += UNITS_PER_WORD;
4011 for (i = 18; i >= 4; i--)
4012 if (regs_ever_live[i] && ! call_used_regs[i])
4014 store_reg (i, offset, FRAME_POINTER_REGNUM);
4015 offset += UNITS_PER_WORD;
4018 /* Account for %r3 which is saved in a special place. */
4021 /* No frame pointer needed. */
4024 offset = local_fsize - actual_fsize;
4026 /* Saving the EH return data registers in the frame is the simplest
4027 way to get the frame unwind information emitted. */
4028 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4030 unsigned int i, regno;
4034 regno = EH_RETURN_DATA_REGNO (i);
4035 if (regno == INVALID_REGNUM)
4038 /* If merge_sp_adjust_with_store is nonzero, then we can
4039 optimize the first save. */
4040 if (merge_sp_adjust_with_store)
4042 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
4043 merge_sp_adjust_with_store = 0;
4046 store_reg (regno, offset, STACK_POINTER_REGNUM);
4047 offset += UNITS_PER_WORD;
4051 for (i = 18; i >= 3; i--)
4052 if (regs_ever_live[i] && ! call_used_regs[i])
4054 /* If merge_sp_adjust_with_store is nonzero, then we can
4055 optimize the first GR save. */
4056 if (merge_sp_adjust_with_store)
4058 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
4059 merge_sp_adjust_with_store = 0;
4062 store_reg (i, offset, STACK_POINTER_REGNUM);
4063 offset += UNITS_PER_WORD;
4067 /* If we wanted to merge the SP adjustment with a GR save, but we never
4068 did any GR saves, then just emit the adjustment here. */
4069 if (merge_sp_adjust_with_store)
4070 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4074 /* The hppa calling conventions say that %r19, the pic offset
4075 register, is saved at sp - 32 (in this function's frame)
4076 when generating PIC code. FIXME: What is the correct thing
4077 to do for functions which make no calls and allocate no
4078 frame? Do we need to allocate a frame, or can we just omit
4079 the save? For now we'll just omit the save.
4081 We don't want a note on this insn as the frame marker can
4082 move if there is a dynamic stack allocation. */
4083 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
4085 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
4087 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
4091 /* Align pointer properly (doubleword boundary). */
4092 offset = (offset + 7) & ~7;
4094 /* Floating point register store. */
4099 /* First get the frame or stack pointer to the start of the FP register
4101 if (frame_pointer_needed)
4103 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4104 base = frame_pointer_rtx;
4108 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4109 base = stack_pointer_rtx;
4112 /* Now actually save the FP registers. */
4113 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4115 if (regs_ever_live[i]
4116 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4118 rtx addr, insn, reg;
4119 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4120 reg = gen_rtx_REG (DFmode, i);
4121 insn = emit_move_insn (addr, reg);
4124 RTX_FRAME_RELATED_P (insn) = 1;
4127 rtx mem = gen_rtx_MEM (DFmode,
4128 plus_constant (base, offset));
4130 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4131 gen_rtx_SET (VOIDmode, mem, reg),
4136 rtx meml = gen_rtx_MEM (SFmode,
4137 plus_constant (base, offset));
4138 rtx memr = gen_rtx_MEM (SFmode,
4139 plus_constant (base, offset + 4));
4140 rtx regl = gen_rtx_REG (SFmode, i);
4141 rtx regr = gen_rtx_REG (SFmode, i + 1);
4142 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4143 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4146 RTX_FRAME_RELATED_P (setl) = 1;
4147 RTX_FRAME_RELATED_P (setr) = 1;
4148 vec = gen_rtvec (2, setl, setr);
4150 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4151 gen_rtx_SEQUENCE (VOIDmode, vec),
4155 offset += GET_MODE_SIZE (DFmode);
4162 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4163 Handle case where DISP > 8k by using the add_high_const patterns. */
4166 load_reg (int reg, HOST_WIDE_INT disp, int base)
4168 rtx dest = gen_rtx_REG (word_mode, reg);
4169 rtx basereg = gen_rtx_REG (Pmode, base);
4172 if (VAL_14_BITS_P (disp))
4173 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4174 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4176 rtx delta = GEN_INT (disp);
4177 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4179 emit_move_insn (tmpreg, delta);
4180 if (TARGET_DISABLE_INDEXING)
4182 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4183 src = gen_rtx_MEM (word_mode, tmpreg);
4186 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4190 rtx delta = GEN_INT (disp);
4191 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4192 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4194 emit_move_insn (tmpreg, high);
4195 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4198 emit_move_insn (dest, src);
4201 /* Update the total code bytes output to the text section. */
4204 update_total_code_bytes (int nbytes)
4206 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4207 && !IN_NAMED_SECTION_P (cfun->decl))
4209 if (INSN_ADDRESSES_SET_P ())
4211 unsigned long old_total = total_code_bytes;
4213 total_code_bytes += nbytes;
4215 /* Be prepared to handle overflows. */
4216 if (old_total > total_code_bytes)
4217 total_code_bytes = -1;
4220 total_code_bytes = -1;
4224 /* This function generates the assembly code for function exit.
4225 Args are as for output_function_prologue ().
4227 The function epilogue should not depend on the current stack
4228 pointer! It should use the frame pointer only. This is mandatory
4229 because of alloca; we also take advantage of it to omit stack
4230 adjustments before returning. */
4233 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4235 rtx insn = get_last_insn ();
4239 /* hppa_expand_epilogue does the dirty work now. We just need
4240 to output the assembler directives which denote the end
4243 To make debuggers happy, emit a nop if the epilogue was completely
4244 eliminated due to a volatile call as the last insn in the
4245 current function. That way the return address (in %r2) will
4246 always point to a valid instruction in the current function. */
4248 /* Get the last real insn. */
4249 if (GET_CODE (insn) == NOTE)
4250 insn = prev_real_insn (insn);
4252 /* If it is a sequence, then look inside. */
4253 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4254 insn = XVECEXP (PATTERN (insn), 0, 0);
4256 /* If insn is a CALL_INSN, then it must be a call to a volatile
4257 function (otherwise there would be epilogue insns). */
4258 if (insn && GET_CODE (insn) == CALL_INSN)
4260 fputs ("\tnop\n", file);
4264 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4266 if (TARGET_SOM && TARGET_GAS)
4268 /* We done with this subspace except possibly for some additional
4269 debug information. Forget that we are in this subspace to ensure
4270 that the next function is output in its own subspace. */
4274 if (INSN_ADDRESSES_SET_P ())
4276 insn = get_last_nonnote_insn ();
4277 last_address += INSN_ADDRESSES (INSN_UID (insn));
4279 last_address += insn_default_length (insn);
4280 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4281 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4284 /* Finally, update the total number of code bytes output so far. */
4285 update_total_code_bytes (last_address);
4289 hppa_expand_epilogue (void)
4292 HOST_WIDE_INT offset;
4293 HOST_WIDE_INT ret_off = 0;
4295 int merge_sp_adjust_with_load = 0;
4297 /* We will use this often. */
4298 tmpreg = gen_rtx_REG (word_mode, 1);
4300 /* Try to restore RP early to avoid load/use interlocks when
4301 RP gets used in the return (bv) instruction. This appears to still
4302 be necessary even when we schedule the prologue and epilogue. */
4303 if (regs_ever_live [2] || current_function_calls_eh_return)
4305 ret_off = TARGET_64BIT ? -16 : -20;
4306 if (frame_pointer_needed)
4308 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4313 /* No frame pointer, and stack is smaller than 8k. */
4314 if (VAL_14_BITS_P (ret_off - actual_fsize))
4316 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4322 /* General register restores. */
4323 if (frame_pointer_needed)
4325 offset = local_fsize;
4327 /* If the current function calls __builtin_eh_return, then we need
4328 to restore the saved EH data registers. */
4329 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4331 unsigned int i, regno;
4335 regno = EH_RETURN_DATA_REGNO (i);
4336 if (regno == INVALID_REGNUM)
4339 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4340 offset += UNITS_PER_WORD;
4344 for (i = 18; i >= 4; i--)
4345 if (regs_ever_live[i] && ! call_used_regs[i])
4347 load_reg (i, offset, FRAME_POINTER_REGNUM);
4348 offset += UNITS_PER_WORD;
4353 offset = local_fsize - actual_fsize;
4355 /* If the current function calls __builtin_eh_return, then we need
4356 to restore the saved EH data registers. */
4357 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4359 unsigned int i, regno;
4363 regno = EH_RETURN_DATA_REGNO (i);
4364 if (regno == INVALID_REGNUM)
4367 /* Only for the first load.
4368 merge_sp_adjust_with_load holds the register load
4369 with which we will merge the sp adjustment. */
4370 if (merge_sp_adjust_with_load == 0
4372 && VAL_14_BITS_P (-actual_fsize))
4373 merge_sp_adjust_with_load = regno;
4375 load_reg (regno, offset, STACK_POINTER_REGNUM);
4376 offset += UNITS_PER_WORD;
4380 for (i = 18; i >= 3; i--)
4382 if (regs_ever_live[i] && ! call_used_regs[i])
4384 /* Only for the first load.
4385 merge_sp_adjust_with_load holds the register load
4386 with which we will merge the sp adjustment. */
4387 if (merge_sp_adjust_with_load == 0
4389 && VAL_14_BITS_P (-actual_fsize))
4390 merge_sp_adjust_with_load = i;
4392 load_reg (i, offset, STACK_POINTER_REGNUM);
4393 offset += UNITS_PER_WORD;
4398 /* Align pointer properly (doubleword boundary). */
4399 offset = (offset + 7) & ~7;
4401 /* FP register restores. */
4404 /* Adjust the register to index off of. */
4405 if (frame_pointer_needed)
4406 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4408 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4410 /* Actually do the restores now. */
4411 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4412 if (regs_ever_live[i]
4413 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4415 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4416 rtx dest = gen_rtx_REG (DFmode, i);
4417 emit_move_insn (dest, src);
4421 /* Emit a blockage insn here to keep these insns from being moved to
4422 an earlier spot in the epilogue, or into the main instruction stream.
4424 This is necessary as we must not cut the stack back before all the
4425 restores are finished. */
4426 emit_insn (gen_blockage ());
4428 /* Reset stack pointer (and possibly frame pointer). The stack
4429 pointer is initially set to fp + 64 to avoid a race condition. */
4430 if (frame_pointer_needed)
4432 rtx delta = GEN_INT (-64);
4434 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4435 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4437 /* If we were deferring a callee register restore, do it now. */
4438 else if (merge_sp_adjust_with_load)
4440 rtx delta = GEN_INT (-actual_fsize);
4441 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4443 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4445 else if (actual_fsize != 0)
4446 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4449 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4450 frame greater than 8k), do so now. */
4452 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4454 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4456 rtx sa = EH_RETURN_STACKADJ_RTX;
4458 emit_insn (gen_blockage ());
4459 emit_insn (TARGET_64BIT
4460 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4461 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4466 hppa_pic_save_rtx (void)
4468 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4472 hppa_profile_hook (int label_no)
4474 /* We use SImode for the address of the function in both 32 and
4475 64-bit code to avoid having to provide DImode versions of the
4476 lcla2 and load_offset_label_address insn patterns. */
4477 rtx reg = gen_reg_rtx (SImode);
4478 rtx label_rtx = gen_label_rtx ();
4479 rtx begin_label_rtx, call_insn;
4480 char begin_label_name[16];
4482 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4484 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4487 emit_move_insn (arg_pointer_rtx,
4488 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4491 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4493 /* The address of the function is loaded into %r25 with a instruction-
4494 relative sequence that avoids the use of relocations. The sequence
4495 is split so that the load_offset_label_address instruction can
4496 occupy the delay slot of the call to _mcount. */
4498 emit_insn (gen_lcla2 (reg, label_rtx));
4500 emit_insn (gen_lcla1 (reg, label_rtx));
4502 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4503 reg, begin_label_rtx, label_rtx));
4505 #ifndef NO_PROFILE_COUNTERS
4507 rtx count_label_rtx, addr, r24;
4508 char count_label_name[16];
4510 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4511 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4513 addr = force_reg (Pmode, count_label_rtx);
4514 r24 = gen_rtx_REG (Pmode, 24);
4515 emit_move_insn (r24, addr);
4518 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4519 gen_rtx_SYMBOL_REF (Pmode,
4521 GEN_INT (TARGET_64BIT ? 24 : 12)));
4523 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4528 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4529 gen_rtx_SYMBOL_REF (Pmode,
4531 GEN_INT (TARGET_64BIT ? 16 : 8)));
4535 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4536 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4538 /* Indicate the _mcount call cannot throw, nor will it execute a
4540 REG_NOTES (call_insn)
4541 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4544 /* Fetch the return address for the frame COUNT steps up from
4545 the current frame, after the prologue. FRAMEADDR is the
4546 frame pointer of the COUNT frame.
4548 We want to ignore any export stub remnants here. To handle this,
4549 we examine the code at the return address, and if it is an export
4550 stub, we return a memory rtx for the stub return address stored
4553 The value returned is used in two different ways:
4555 1. To find a function's caller.
4557 2. To change the return address for a function.
4559 This function handles most instances of case 1; however, it will
4560 fail if there are two levels of stubs to execute on the return
4561 path. The only way I believe that can happen is if the return value
4562 needs a parameter relocation, which never happens for C code.
4564 This function handles most instances of case 2; however, it will
4565 fail if we did not originally have stub code on the return path
4566 but will need stub code on the new return path. This can happen if
4567 the caller & callee are both in the main program, but the new
4568 return location is in a shared library. */
4571 return_addr_rtx (int count, rtx frameaddr)
4581 rp = get_hard_reg_initial_val (Pmode, 2);
4583 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4586 saved_rp = gen_reg_rtx (Pmode);
4587 emit_move_insn (saved_rp, rp);
4589 /* Get pointer to the instruction stream. We have to mask out the
4590 privilege level from the two low order bits of the return address
4591 pointer here so that ins will point to the start of the first
4592 instruction that would have been executed if we returned. */
4593 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4594 label = gen_label_rtx ();
4596 /* Check the instruction stream at the normal return address for the
4599 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4600 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4601 0x00011820 | stub+16: mtsp r1,sr0
4602 0xe0400002 | stub+20: be,n 0(sr0,rp)
4604 If it is an export stub, than our return address is really in
4607 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4608 NULL_RTX, SImode, 1);
4609 emit_jump_insn (gen_bne (label));
4611 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4612 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4613 emit_jump_insn (gen_bne (label));
4615 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4616 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4617 emit_jump_insn (gen_bne (label));
4619 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4620 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4622 /* If there is no export stub then just use the value saved from
4623 the return pointer register. */
4625 emit_jump_insn (gen_bne (label));
4627 /* Here we know that our return address points to an export
4628 stub. We don't want to return the address of the export stub,
4629 but rather the return address of the export stub. That return
4630 address is stored at -24[frameaddr]. */
4632 emit_move_insn (saved_rp,
4634 memory_address (Pmode,
4635 plus_constant (frameaddr,
4642 /* This is only valid once reload has completed because it depends on
4643 knowing exactly how much (if any) frame there is and...
4645 It's only valid if there is no frame marker to de-allocate and...
4647 It's only valid if %r2 hasn't been saved into the caller's frame
4648 (we're not profiling and %r2 isn't live anywhere). */
4650 hppa_can_use_return_insn_p (void)
4652 return (reload_completed
4653 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4654 && ! regs_ever_live[2]
4655 && ! frame_pointer_needed);
4659 emit_bcond_fp (enum rtx_code code, rtx operand0)
4661 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4662 gen_rtx_IF_THEN_ELSE (VOIDmode,
4663 gen_rtx_fmt_ee (code,
4665 gen_rtx_REG (CCFPmode, 0),
4667 gen_rtx_LABEL_REF (VOIDmode, operand0),
4673 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4675 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4676 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4679 /* Adjust the cost of a scheduling dependency. Return the new cost of
4680 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4683 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4685 enum attr_type attr_type;
4687 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4688 true dependencies as they are described with bypasses now. */
4689 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4692 if (! recog_memoized (insn))
4695 attr_type = get_attr_type (insn);
4697 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4699 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4702 if (attr_type == TYPE_FPLOAD)
4704 rtx pat = PATTERN (insn);
4705 rtx dep_pat = PATTERN (dep_insn);
4706 if (GET_CODE (pat) == PARALLEL)
4708 /* This happens for the fldXs,mb patterns. */
4709 pat = XVECEXP (pat, 0, 0);
4711 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4712 /* If this happens, we have to extend this to schedule
4713 optimally. Return 0 for now. */
4716 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4718 if (! recog_memoized (dep_insn))
4720 switch (get_attr_type (dep_insn))
4727 case TYPE_FPSQRTSGL:
4728 case TYPE_FPSQRTDBL:
4729 /* A fpload can't be issued until one cycle before a
4730 preceding arithmetic operation has finished if
4731 the target of the fpload is any of the sources
4732 (or destination) of the arithmetic operation. */
4733 return insn_default_latency (dep_insn) - 1;
4740 else if (attr_type == TYPE_FPALU)
4742 rtx pat = PATTERN (insn);
4743 rtx dep_pat = PATTERN (dep_insn);
4744 if (GET_CODE (pat) == PARALLEL)
4746 /* This happens for the fldXs,mb patterns. */
4747 pat = XVECEXP (pat, 0, 0);
4749 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4750 /* If this happens, we have to extend this to schedule
4751 optimally. Return 0 for now. */
4754 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4756 if (! recog_memoized (dep_insn))
4758 switch (get_attr_type (dep_insn))
4762 case TYPE_FPSQRTSGL:
4763 case TYPE_FPSQRTDBL:
4764 /* An ALU flop can't be issued until two cycles before a
4765 preceding divide or sqrt operation has finished if
4766 the target of the ALU flop is any of the sources
4767 (or destination) of the divide or sqrt operation. */
4768 return insn_default_latency (dep_insn) - 2;
4776 /* For other anti dependencies, the cost is 0. */
4779 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4781 /* Output dependency; DEP_INSN writes a register that INSN writes some
4783 if (attr_type == TYPE_FPLOAD)
4785 rtx pat = PATTERN (insn);
4786 rtx dep_pat = PATTERN (dep_insn);
4787 if (GET_CODE (pat) == PARALLEL)
4789 /* This happens for the fldXs,mb patterns. */
4790 pat = XVECEXP (pat, 0, 0);
4792 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4793 /* If this happens, we have to extend this to schedule
4794 optimally. Return 0 for now. */
4797 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4799 if (! recog_memoized (dep_insn))
4801 switch (get_attr_type (dep_insn))
4808 case TYPE_FPSQRTSGL:
4809 case TYPE_FPSQRTDBL:
4810 /* A fpload can't be issued until one cycle before a
4811 preceding arithmetic operation has finished if
4812 the target of the fpload is the destination of the
4813 arithmetic operation.
4815 Exception: For PA7100LC, PA7200 and PA7300, the cost
4816 is 3 cycles, unless they bundle together. We also
4817 pay the penalty if the second insn is a fpload. */
4818 return insn_default_latency (dep_insn) - 1;
4825 else if (attr_type == TYPE_FPALU)
4827 rtx pat = PATTERN (insn);
4828 rtx dep_pat = PATTERN (dep_insn);
4829 if (GET_CODE (pat) == PARALLEL)
4831 /* This happens for the fldXs,mb patterns. */
4832 pat = XVECEXP (pat, 0, 0);
4834 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4835 /* If this happens, we have to extend this to schedule
4836 optimally. Return 0 for now. */
4839 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4841 if (! recog_memoized (dep_insn))
4843 switch (get_attr_type (dep_insn))
4847 case TYPE_FPSQRTSGL:
4848 case TYPE_FPSQRTDBL:
4849 /* An ALU flop can't be issued until two cycles before a
4850 preceding divide or sqrt operation has finished if
4851 the target of the ALU flop is also the target of
4852 the divide or sqrt operation. */
4853 return insn_default_latency (dep_insn) - 2;
4861 /* For other output dependencies, the cost is 0. */
4868 /* Adjust scheduling priorities. We use this to try and keep addil
4869 and the next use of %r1 close together. */
4871 pa_adjust_priority (rtx insn, int priority)
4873 rtx set = single_set (insn);
4877 src = SET_SRC (set);
4878 dest = SET_DEST (set);
4879 if (GET_CODE (src) == LO_SUM
4880 && symbolic_operand (XEXP (src, 1), VOIDmode)
4881 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4884 else if (GET_CODE (src) == MEM
4885 && GET_CODE (XEXP (src, 0)) == LO_SUM
4886 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4887 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4890 else if (GET_CODE (dest) == MEM
4891 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4892 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4893 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4899 /* The 700 can only issue a single insn at a time.
4900 The 7XXX processors can issue two insns at a time.
4901 The 8000 can issue 4 insns at a time. */
4903 pa_issue_rate (void)
4907 case PROCESSOR_700: return 1;
4908 case PROCESSOR_7100: return 2;
4909 case PROCESSOR_7100LC: return 2;
4910 case PROCESSOR_7200: return 2;
4911 case PROCESSOR_7300: return 2;
4912 case PROCESSOR_8000: return 4;
4921 /* Return any length adjustment needed by INSN which already has its length
4922 computed as LENGTH. Return zero if no adjustment is necessary.
4924 For the PA: function calls, millicode calls, and backwards short
4925 conditional branches with unfilled delay slots need an adjustment by +1
4926 (to account for the NOP which will be inserted into the instruction stream).
4928 Also compute the length of an inline block move here as it is too
4929 complicated to express as a length attribute in pa.md. */
4931 pa_adjust_insn_length (rtx insn, int length)
4933 rtx pat = PATTERN (insn);
4935 /* Jumps inside switch tables which have unfilled delay slots need
4937 if (GET_CODE (insn) == JUMP_INSN
4938 && GET_CODE (pat) == PARALLEL
4939 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4941 /* Millicode insn with an unfilled delay slot. */
4942 else if (GET_CODE (insn) == INSN
4943 && GET_CODE (pat) != SEQUENCE
4944 && GET_CODE (pat) != USE
4945 && GET_CODE (pat) != CLOBBER
4946 && get_attr_type (insn) == TYPE_MILLI)
4948 /* Block move pattern. */
4949 else if (GET_CODE (insn) == INSN
4950 && GET_CODE (pat) == PARALLEL
4951 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4952 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4953 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4954 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4955 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4956 return compute_movmem_length (insn) - 4;
4957 /* Block clear pattern. */
4958 else if (GET_CODE (insn) == INSN
4959 && GET_CODE (pat) == PARALLEL
4960 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4961 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4962 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4963 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4964 return compute_clrmem_length (insn) - 4;
4965 /* Conditional branch with an unfilled delay slot. */
4966 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4968 /* Adjust a short backwards conditional with an unfilled delay slot. */
4969 if (GET_CODE (pat) == SET
4971 && ! forward_branch_p (insn))
4973 else if (GET_CODE (pat) == PARALLEL
4974 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4977 /* Adjust dbra insn with short backwards conditional branch with
4978 unfilled delay slot -- only for case where counter is in a
4979 general register register. */
4980 else if (GET_CODE (pat) == PARALLEL
4981 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4982 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4983 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4985 && ! forward_branch_p (insn))
4993 /* Print operand X (an rtx) in assembler syntax to file FILE.
4994 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4995 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4998 print_operand (FILE *file, rtx x, int code)
5003 /* Output a 'nop' if there's nothing for the delay slot. */
5004 if (dbr_sequence_length () == 0)
5005 fputs ("\n\tnop", file);
5008 /* Output a nullification completer if there's nothing for the */
5009 /* delay slot or nullification is requested. */
5010 if (dbr_sequence_length () == 0 ||
5012 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
5016 /* Print out the second register name of a register pair.
5017 I.e., R (6) => 7. */
5018 fputs (reg_names[REGNO (x) + 1], file);
5021 /* A register or zero. */
5023 || (x == CONST0_RTX (DFmode))
5024 || (x == CONST0_RTX (SFmode)))
5026 fputs ("%r0", file);
5032 /* A register or zero (floating point). */
5034 || (x == CONST0_RTX (DFmode))
5035 || (x == CONST0_RTX (SFmode)))
5037 fputs ("%fr0", file);
5046 xoperands[0] = XEXP (XEXP (x, 0), 0);
5047 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
5048 output_global_address (file, xoperands[1], 0);
5049 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
5053 case 'C': /* Plain (C)ondition */
5055 switch (GET_CODE (x))
5058 fputs ("=", file); break;
5060 fputs ("<>", file); break;
5062 fputs (">", file); break;
5064 fputs (">=", file); break;
5066 fputs (">>=", file); break;
5068 fputs (">>", file); break;
5070 fputs ("<", file); break;
5072 fputs ("<=", file); break;
5074 fputs ("<<=", file); break;
5076 fputs ("<<", file); break;
5081 case 'N': /* Condition, (N)egated */
5082 switch (GET_CODE (x))
5085 fputs ("<>", file); break;
5087 fputs ("=", file); break;
5089 fputs ("<=", file); break;
5091 fputs ("<", file); break;
5093 fputs ("<<", file); break;
5095 fputs ("<<=", file); break;
5097 fputs (">=", file); break;
5099 fputs (">", file); break;
5101 fputs (">>", file); break;
5103 fputs (">>=", file); break;
5108 /* For floating point comparisons. Note that the output
5109 predicates are the complement of the desired mode. The
5110 conditions for GT, GE, LT, LE and LTGT cause an invalid
5111 operation exception if the result is unordered and this
5112 exception is enabled in the floating-point status register. */
5114 switch (GET_CODE (x))
5117 fputs ("!=", file); break;
5119 fputs ("=", file); break;
5121 fputs ("!>", file); break;
5123 fputs ("!>=", file); break;
5125 fputs ("!<", file); break;
5127 fputs ("!<=", file); break;
5129 fputs ("!<>", file); break;
5131 fputs ("!?<=", file); break;
5133 fputs ("!?<", file); break;
5135 fputs ("!?>=", file); break;
5137 fputs ("!?>", file); break;
5139 fputs ("!?=", file); break;
5141 fputs ("!?", file); break;
5143 fputs ("?", file); break;
5148 case 'S': /* Condition, operands are (S)wapped. */
5149 switch (GET_CODE (x))
5152 fputs ("=", file); break;
5154 fputs ("<>", file); break;
5156 fputs ("<", file); break;
5158 fputs ("<=", file); break;
5160 fputs ("<<=", file); break;
5162 fputs ("<<", file); break;
5164 fputs (">", file); break;
5166 fputs (">=", file); break;
5168 fputs (">>=", file); break;
5170 fputs (">>", file); break;
5175 case 'B': /* Condition, (B)oth swapped and negate. */
5176 switch (GET_CODE (x))
5179 fputs ("<>", file); break;
5181 fputs ("=", file); break;
5183 fputs (">=", file); break;
5185 fputs (">", file); break;
5187 fputs (">>", file); break;
5189 fputs (">>=", file); break;
5191 fputs ("<=", file); break;
5193 fputs ("<", file); break;
5195 fputs ("<<", file); break;
5197 fputs ("<<=", file); break;
5203 if (GET_CODE (x) == CONST_INT)
5205 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5210 if (GET_CODE (x) == CONST_INT)
5212 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5217 if (GET_CODE (x) == CONST_INT)
5219 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5224 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5226 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5231 if (GET_CODE (x) == CONST_INT)
5233 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5238 if (GET_CODE (x) == CONST_INT)
5240 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5245 if (GET_CODE (x) == CONST_INT)
5250 switch (GET_CODE (XEXP (x, 0)))
5254 if (ASSEMBLER_DIALECT == 0)
5255 fputs ("s,mb", file);
5257 fputs (",mb", file);
5261 if (ASSEMBLER_DIALECT == 0)
5262 fputs ("s,ma", file);
5264 fputs (",ma", file);
5267 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5268 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5270 if (ASSEMBLER_DIALECT == 0)
5273 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5274 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5276 if (ASSEMBLER_DIALECT == 0)
5277 fputs ("x,s", file);
5281 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5285 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5291 output_global_address (file, x, 0);
5294 output_global_address (file, x, 1);
5296 case 0: /* Don't do anything special */
5301 compute_zdepwi_operands (INTVAL (x), op);
5302 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5308 compute_zdepdi_operands (INTVAL (x), op);
5309 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5313 /* We can get here from a .vtable_inherit due to our
5314 CONSTANT_ADDRESS_P rejecting perfectly good constant
5320 if (GET_CODE (x) == REG)
5322 fputs (reg_names [REGNO (x)], file);
5323 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5329 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5330 && (REGNO (x) & 1) == 0)
5333 else if (GET_CODE (x) == MEM)
5335 int size = GET_MODE_SIZE (GET_MODE (x));
5336 rtx base = NULL_RTX;
5337 switch (GET_CODE (XEXP (x, 0)))
5341 base = XEXP (XEXP (x, 0), 0);
5342 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5346 base = XEXP (XEXP (x, 0), 0);
5347 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5350 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5351 fprintf (file, "%s(%s)",
5352 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5353 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5354 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5355 fprintf (file, "%s(%s)",
5356 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5357 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5358 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5359 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5361 /* Because the REG_POINTER flag can get lost during reload,
5362 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5363 index and base registers in the combined move patterns. */
5364 rtx base = XEXP (XEXP (x, 0), 1);
5365 rtx index = XEXP (XEXP (x, 0), 0);
5367 fprintf (file, "%s(%s)",
5368 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5371 output_address (XEXP (x, 0));
5374 output_address (XEXP (x, 0));
5379 output_addr_const (file, x);
5382 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5385 output_global_address (FILE *file, rtx x, int round_constant)
5388 /* Imagine (high (const (plus ...))). */
5389 if (GET_CODE (x) == HIGH)
5392 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5393 assemble_name (file, XSTR (x, 0));
5394 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5396 assemble_name (file, XSTR (x, 0));
5397 fputs ("-$global$", file);
5399 else if (GET_CODE (x) == CONST)
5401 const char *sep = "";
5402 int offset = 0; /* assembler wants -$global$ at end */
5403 rtx base = NULL_RTX;
5405 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5407 base = XEXP (XEXP (x, 0), 0);
5408 output_addr_const (file, base);
5410 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5411 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5414 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5416 base = XEXP (XEXP (x, 0), 1);
5417 output_addr_const (file, base);
5419 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5420 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5423 /* How bogus. The compiler is apparently responsible for
5424 rounding the constant if it uses an LR field selector.
5426 The linker and/or assembler seem a better place since
5427 they have to do this kind of thing already.
5429 If we fail to do this, HP's optimizing linker may eliminate
5430 an addil, but not update the ldw/stw/ldo instruction that
5431 uses the result of the addil. */
5433 offset = ((offset + 0x1000) & ~0x1fff);
5435 if (GET_CODE (XEXP (x, 0)) == PLUS)
5445 else if (GET_CODE (XEXP (x, 0)) == MINUS
5446 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5450 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5451 fputs ("-$global$", file);
5453 fprintf (file, "%s%d", sep, offset);
5456 output_addr_const (file, x);
5459 /* Output boilerplate text to appear at the beginning of the file.
5460 There are several possible versions. */
5461 #define aputs(x) fputs(x, asm_out_file)
5463 pa_file_start_level (void)
5466 aputs ("\t.LEVEL 2.0w\n");
5467 else if (TARGET_PA_20)
5468 aputs ("\t.LEVEL 2.0\n");
5469 else if (TARGET_PA_11)
5470 aputs ("\t.LEVEL 1.1\n");
5472 aputs ("\t.LEVEL 1.0\n");
5476 pa_file_start_space (int sortspace)
5478 aputs ("\t.SPACE $PRIVATE$");
5481 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5482 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5483 "\n\t.SPACE $TEXT$");
5486 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5487 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5491 pa_file_start_file (int want_version)
5493 if (write_symbols != NO_DEBUG)
5495 output_file_directive (asm_out_file, main_input_filename);
5497 aputs ("\t.version\t\"01.01\"\n");
5502 pa_file_start_mcount (const char *aswhat)
5505 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5509 pa_elf_file_start (void)
5511 pa_file_start_level ();
5512 pa_file_start_mcount ("ENTRY");
5513 pa_file_start_file (0);
5517 pa_som_file_start (void)
5519 pa_file_start_level ();
5520 pa_file_start_space (0);
5521 aputs ("\t.IMPORT $global$,DATA\n"
5522 "\t.IMPORT $$dyncall,MILLICODE\n");
5523 pa_file_start_mcount ("CODE");
5524 pa_file_start_file (0);
5528 pa_linux_file_start (void)
5530 pa_file_start_file (1);
5531 pa_file_start_level ();
5532 pa_file_start_mcount ("CODE");
5536 pa_hpux64_gas_file_start (void)
5538 pa_file_start_level ();
5539 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5541 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5543 pa_file_start_file (1);
5547 pa_hpux64_hpas_file_start (void)
5549 pa_file_start_level ();
5550 pa_file_start_space (1);
5551 pa_file_start_mcount ("CODE");
5552 pa_file_start_file (0);
5556 static struct deferred_plabel *
5557 get_plabel (const char *fname)
5561 /* See if we have already put this function on the list of deferred
5562 plabels. This list is generally small, so a liner search is not
5563 too ugly. If it proves too slow replace it with something faster. */
5564 for (i = 0; i < n_deferred_plabels; i++)
5565 if (strcmp (fname, deferred_plabels[i].name) == 0)
5568 /* If the deferred plabel list is empty, or this entry was not found
5569 on the list, create a new entry on the list. */
5570 if (deferred_plabels == NULL || i == n_deferred_plabels)
5572 const char *real_name;
5574 if (deferred_plabels == 0)
5575 deferred_plabels = (struct deferred_plabel *)
5576 ggc_alloc (sizeof (struct deferred_plabel));
5578 deferred_plabels = (struct deferred_plabel *)
5579 ggc_realloc (deferred_plabels,
5580 ((n_deferred_plabels + 1)
5581 * sizeof (struct deferred_plabel)));
5583 i = n_deferred_plabels++;
5584 deferred_plabels[i].internal_label = gen_label_rtx ();
5585 deferred_plabels[i].name = ggc_strdup (fname);
5587 /* Gross. We have just implicitly taken the address of this function,
5589 real_name = (*targetm.strip_name_encoding) (fname);
5590 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5593 return &deferred_plabels[i];
5597 output_deferred_plabels (void)
5600 /* If we have deferred plabels, then we need to switch into the data
5601 section and align it to a 4 byte boundary before we output the
5602 deferred plabels. */
5603 if (n_deferred_plabels)
5606 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5609 /* Now output the deferred plabels. */
5610 for (i = 0; i < n_deferred_plabels; i++)
5612 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5613 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5614 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5615 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5619 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5620 /* Initialize optabs to point to HPUX long double emulation routines. */
5622 pa_hpux_init_libfuncs (void)
5624 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5625 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5626 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5627 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5628 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5629 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5630 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5631 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5632 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5634 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5635 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5636 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5637 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5638 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5639 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5640 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5642 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5643 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5644 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5645 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5647 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5648 ? "__U_Qfcnvfxt_quad_to_sgl"
5649 : "_U_Qfcnvfxt_quad_to_sgl");
5650 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5651 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5652 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5654 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5655 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5659 /* HP's millicode routines mean something special to the assembler.
5660 Keep track of which ones we have used. */
5662 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5663 static void import_milli (enum millicodes);
5664 static char imported[(int) end1000];
5665 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5666 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5667 #define MILLI_START 10
5670 import_milli (enum millicodes code)
5672 char str[sizeof (import_string)];
5674 if (!imported[(int) code])
5676 imported[(int) code] = 1;
5677 strcpy (str, import_string);
5678 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5679 output_asm_insn (str, 0);
5683 /* The register constraints have put the operands and return value in
5684 the proper registers. */
5687 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5689 import_milli (mulI);
5690 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5693 /* Emit the rtl for doing a division by a constant. */
5695 /* Do magic division millicodes exist for this value? */
5696 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5699 /* We'll use an array to keep track of the magic millicodes and
5700 whether or not we've used them already. [n][0] is signed, [n][1] is
5703 static int div_milli[16][2];
5706 div_operand (rtx op, enum machine_mode mode)
5708 return (mode == SImode
5709 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5710 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5711 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5715 emit_hpdiv_const (rtx *operands, int unsignedp)
5717 if (GET_CODE (operands[2]) == CONST_INT
5718 && INTVAL (operands[2]) > 0
5719 && INTVAL (operands[2]) < 16
5720 && magic_milli[INTVAL (operands[2])])
5722 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5724 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5728 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5729 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5731 gen_rtx_REG (SImode, 26),
5733 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5734 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5735 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5736 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5737 gen_rtx_CLOBBER (VOIDmode, ret))));
5738 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5745 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5749 /* If the divisor is a constant, try to use one of the special
5751 if (GET_CODE (operands[0]) == CONST_INT)
5753 static char buf[100];
5754 divisor = INTVAL (operands[0]);
5755 if (!div_milli[divisor][unsignedp])
5757 div_milli[divisor][unsignedp] = 1;
5759 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5761 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5765 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5766 INTVAL (operands[0]));
5767 return output_millicode_call (insn,
5768 gen_rtx_SYMBOL_REF (SImode, buf));
5772 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5773 INTVAL (operands[0]));
5774 return output_millicode_call (insn,
5775 gen_rtx_SYMBOL_REF (SImode, buf));
5778 /* Divisor isn't a special constant. */
5783 import_milli (divU);
5784 return output_millicode_call (insn,
5785 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5789 import_milli (divI);
5790 return output_millicode_call (insn,
5791 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5796 /* Output a $$rem millicode to do mod. */
5799 output_mod_insn (int unsignedp, rtx insn)
5803 import_milli (remU);
5804 return output_millicode_call (insn,
5805 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5809 import_milli (remI);
5810 return output_millicode_call (insn,
5811 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5816 output_arg_descriptor (rtx call_insn)
5818 const char *arg_regs[4];
5819 enum machine_mode arg_mode;
5821 int i, output_flag = 0;
5824 /* We neither need nor want argument location descriptors for the
5825 64bit runtime environment or the ELF32 environment. */
5826 if (TARGET_64BIT || TARGET_ELF32)
5829 for (i = 0; i < 4; i++)
5832 /* Specify explicitly that no argument relocations should take place
5833 if using the portable runtime calling conventions. */
5834 if (TARGET_PORTABLE_RUNTIME)
5836 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5841 if (GET_CODE (call_insn) != CALL_INSN)
5843 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5845 rtx use = XEXP (link, 0);
5847 if (! (GET_CODE (use) == USE
5848 && GET_CODE (XEXP (use, 0)) == REG
5849 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5852 arg_mode = GET_MODE (XEXP (use, 0));
5853 regno = REGNO (XEXP (use, 0));
5854 if (regno >= 23 && regno <= 26)
5856 arg_regs[26 - regno] = "GR";
5857 if (arg_mode == DImode)
5858 arg_regs[25 - regno] = "GR";
5860 else if (regno >= 32 && regno <= 39)
5862 if (arg_mode == SFmode)
5863 arg_regs[(regno - 32) / 2] = "FR";
5866 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5867 arg_regs[(regno - 34) / 2] = "FR";
5868 arg_regs[(regno - 34) / 2 + 1] = "FU";
5870 arg_regs[(regno - 34) / 2] = "FU";
5871 arg_regs[(regno - 34) / 2 + 1] = "FR";
5876 fputs ("\t.CALL ", asm_out_file);
5877 for (i = 0; i < 4; i++)
5882 fputc (',', asm_out_file);
5883 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5886 fputc ('\n', asm_out_file);
5889 /* Return the class of any secondary reload register that is needed to
5890 move IN into a register in class CLASS using mode MODE.
5892 Profiling has showed this routine and its descendants account for
5893 a significant amount of compile time (~7%). So it has been
5894 optimized to reduce redundant computations and eliminate useless
5897 It might be worthwhile to try and make this a leaf function too. */
5900 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5902 int regno, is_symbolic;
5904 /* Trying to load a constant into a FP register during PIC code
5905 generation will require %r1 as a scratch register. */
5907 && GET_MODE_CLASS (mode) == MODE_INT
5908 && FP_REG_CLASS_P (class)
5909 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5912 /* Profiling showed the PA port spends about 1.3% of its compilation
5913 time in true_regnum from calls inside secondary_reload_class. */
5915 if (GET_CODE (in) == REG)
5918 if (regno >= FIRST_PSEUDO_REGISTER)
5919 regno = true_regnum (in);
5921 else if (GET_CODE (in) == SUBREG)
5922 regno = true_regnum (in);
5926 /* If we have something like (mem (mem (...)), we can safely assume the
5927 inner MEM will end up in a general register after reloading, so there's
5928 no need for a secondary reload. */
5929 if (GET_CODE (in) == MEM
5930 && GET_CODE (XEXP (in, 0)) == MEM)
5933 /* Handle out of range displacement for integer mode loads/stores of
5935 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5936 && GET_MODE_CLASS (mode) == MODE_INT
5937 && FP_REG_CLASS_P (class))
5938 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5939 return GENERAL_REGS;
5941 /* A SAR<->FP register copy requires a secondary register (GPR) as
5942 well as secondary memory. */
5943 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5944 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5945 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5946 return GENERAL_REGS;
5948 if (GET_CODE (in) == HIGH)
5951 /* Profiling has showed GCC spends about 2.6% of its compilation
5952 time in symbolic_operand from calls inside secondary_reload_class.
5954 We use an inline copy and only compute its return value once to avoid
5956 switch (GET_CODE (in))
5966 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5967 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5968 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5978 && read_only_operand (in, VOIDmode))
5981 if (class != R1_REGS && is_symbolic)
5987 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5988 by invisible reference. As a GCC extension, we also pass anything
5989 with a zero or variable size by reference.
5991 The 64-bit runtime does not describe passing any types by invisible
5992 reference. The internals of GCC can't currently handle passing
5993 empty structures, and zero or variable length arrays when they are
5994 not passed entirely on the stack or by reference. Thus, as a GCC
5995 extension, we pass these types by reference. The HP compiler doesn't
5996 support these types, so hopefully there shouldn't be any compatibility
5997 issues. This may have to be revisited when HP releases a C99 compiler
5998 or updates the ABI. */
6001 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
6002 enum machine_mode mode, tree type,
6003 bool named ATTRIBUTE_UNUSED)
6008 size = int_size_in_bytes (type);
6010 size = GET_MODE_SIZE (mode);
6015 return size <= 0 || size > 8;
6019 function_arg_padding (enum machine_mode mode, tree type)
6022 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
6024 /* Return none if justification is not required. */
6026 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
6027 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
6030 /* The directions set here are ignored when a BLKmode argument larger
6031 than a word is placed in a register. Different code is used for
6032 the stack and registers. This makes it difficult to have a
6033 consistent data representation for both the stack and registers.
6034 For both runtimes, the justification and padding for arguments on
6035 the stack and in registers should be identical. */
6037 /* The 64-bit runtime specifies left justification for aggregates. */
6040 /* The 32-bit runtime architecture specifies right justification.
6041 When the argument is passed on the stack, the argument is padded
6042 with garbage on the left. The HP compiler pads with zeros. */
6046 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6053 /* Do what is necessary for `va_start'. We look at the current function
6054 to determine if stdargs or varargs is used and fill in an initial
6055 va_list. A pointer to this constructor is returned. */
6058 hppa_builtin_saveregs (void)
6061 tree fntype = TREE_TYPE (current_function_decl);
6062 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
6063 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6064 != void_type_node)))
6065 ? UNITS_PER_WORD : 0);
6068 offset = plus_constant (current_function_arg_offset_rtx, argadj);
6070 offset = current_function_arg_offset_rtx;
6076 /* Adjust for varargs/stdarg differences. */
6078 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
6080 offset = current_function_arg_offset_rtx;
6082 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6083 from the incoming arg pointer and growing to larger addresses. */
6084 for (i = 26, off = -64; i >= 19; i--, off += 8)
6085 emit_move_insn (gen_rtx_MEM (word_mode,
6086 plus_constant (arg_pointer_rtx, off)),
6087 gen_rtx_REG (word_mode, i));
6089 /* The incoming args pointer points just beyond the flushback area;
6090 normally this is not a serious concern. However, when we are doing
6091 varargs/stdargs we want to make the arg pointer point to the start
6092 of the incoming argument area. */
6093 emit_move_insn (virtual_incoming_args_rtx,
6094 plus_constant (arg_pointer_rtx, -64));
6096 /* Now return a pointer to the first anonymous argument. */
6097 return copy_to_reg (expand_binop (Pmode, add_optab,
6098 virtual_incoming_args_rtx,
6099 offset, 0, 0, OPTAB_LIB_WIDEN));
6102 /* Store general registers on the stack. */
6103 dest = gen_rtx_MEM (BLKmode,
6104 plus_constant (current_function_internal_arg_pointer,
6106 set_mem_alias_set (dest, get_varargs_alias_set ());
6107 set_mem_align (dest, BITS_PER_WORD);
6108 move_block_from_reg (23, dest, 4);
6110 /* move_block_from_reg will emit code to store the argument registers
6111 individually as scalar stores.
6113 However, other insns may later load from the same addresses for
6114 a structure load (passing a struct to a varargs routine).
6116 The alias code assumes that such aliasing can never happen, so we
6117 have to keep memory referencing insns from moving up beyond the
6118 last argument register store. So we emit a blockage insn here. */
6119 emit_insn (gen_blockage ());
6121 return copy_to_reg (expand_binop (Pmode, add_optab,
6122 current_function_internal_arg_pointer,
6123 offset, 0, 0, OPTAB_LIB_WIDEN));
6127 hppa_va_start (tree valist, rtx nextarg)
6129 nextarg = expand_builtin_saveregs ();
6130 std_expand_builtin_va_start (valist, nextarg);
6134 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
6138 /* Args grow upward. We can use the generic routines. */
6139 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6141 else /* !TARGET_64BIT */
6143 tree ptr = build_pointer_type (type);
6146 unsigned int size, ofs;
6149 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6153 ptr = build_pointer_type (type);
6155 size = int_size_in_bytes (type);
6156 valist_type = TREE_TYPE (valist);
6158 /* Args grow down. Not handled by generic routines. */
6160 u = fold_convert (valist_type, size_in_bytes (type));
6161 t = build (MINUS_EXPR, valist_type, valist, u);
6163 /* Copied from va-pa.h, but we probably don't need to align to
6164 word size, since we generate and preserve that invariant. */
6165 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
6166 t = build (BIT_AND_EXPR, valist_type, t, u);
6168 t = build (MODIFY_EXPR, valist_type, valist, t);
6170 ofs = (8 - size) % 4;
6173 u = fold_convert (valist_type, size_int (ofs));
6174 t = build (PLUS_EXPR, valist_type, t, u);
6177 t = fold_convert (ptr, t);
6178 t = build_fold_indirect_ref (t);
6181 t = build_fold_indirect_ref (t);
6187 /* This routine handles all the normal conditional branch sequences we
6188 might need to generate. It handles compare immediate vs compare
6189 register, nullification of delay slots, varying length branches,
6190 negated branches, and all combinations of the above. It returns the
6191 output appropriate to emit the branch corresponding to all given
6195 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6197 static char buf[100];
6201 /* A conditional branch to the following instruction (e.g. the delay slot)
6202 is asking for a disaster. This can happen when not optimizing and
6203 when jump optimization fails.
6205 While it is usually safe to emit nothing, this can fail if the
6206 preceding instruction is a nullified branch with an empty delay
6207 slot and the same branch target as this branch. We could check
6208 for this but jump optimization should eliminate nop jumps. It
6209 is always safe to emit a nop. */
6210 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6213 /* The doubleword form of the cmpib instruction doesn't have the LEU
6214 and GTU conditions while the cmpb instruction does. Since we accept
6215 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6216 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6217 operands[2] = gen_rtx_REG (DImode, 0);
6219 /* If this is a long branch with its delay slot unfilled, set `nullify'
6220 as it can nullify the delay slot and save a nop. */
6221 if (length == 8 && dbr_sequence_length () == 0)
6224 /* If this is a short forward conditional branch which did not get
6225 its delay slot filled, the delay slot can still be nullified. */
6226 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6227 nullify = forward_branch_p (insn);
6229 /* A forward branch over a single nullified insn can be done with a
6230 comclr instruction. This avoids a single cycle penalty due to
6231 mis-predicted branch if we fall through (branch not taken). */
6233 && next_real_insn (insn) != 0
6234 && get_attr_length (next_real_insn (insn)) == 4
6235 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6241 /* All short conditional branches except backwards with an unfilled
6245 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6247 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6248 if (GET_MODE (operands[1]) == DImode)
6251 strcat (buf, "%B3");
6253 strcat (buf, "%S3");
6255 strcat (buf, " %2,%r1,%%r0");
6257 strcat (buf, ",n %2,%r1,%0");
6259 strcat (buf, " %2,%r1,%0");
6262 /* All long conditionals. Note a short backward branch with an
6263 unfilled delay slot is treated just like a long backward branch
6264 with an unfilled delay slot. */
6266 /* Handle weird backwards branch with a filled delay slot
6267 with is nullified. */
6268 if (dbr_sequence_length () != 0
6269 && ! forward_branch_p (insn)
6272 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6273 if (GET_MODE (operands[1]) == DImode)
6276 strcat (buf, "%S3");
6278 strcat (buf, "%B3");
6279 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6281 /* Handle short backwards branch with an unfilled delay slot.
6282 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6283 taken and untaken branches. */
6284 else if (dbr_sequence_length () == 0
6285 && ! forward_branch_p (insn)
6286 && INSN_ADDRESSES_SET_P ()
6287 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6288 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6290 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6291 if (GET_MODE (operands[1]) == DImode)
6294 strcat (buf, "%B3 %2,%r1,%0%#");
6296 strcat (buf, "%S3 %2,%r1,%0%#");
6300 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6301 if (GET_MODE (operands[1]) == DImode)
6304 strcat (buf, "%S3");
6306 strcat (buf, "%B3");
6308 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6310 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6316 xoperands[0] = operands[0];
6317 xoperands[1] = operands[1];
6318 xoperands[2] = operands[2];
6319 xoperands[3] = operands[3];
6321 /* The reversed conditional branch must branch over one additional
6322 instruction if the delay slot is filled. If the delay slot
6323 is empty, the instruction after the reversed condition branch
6324 must be nullified. */
6325 nullify = dbr_sequence_length () == 0;
6326 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6328 /* Create a reversed conditional branch which branches around
6329 the following insns. */
6330 if (GET_MODE (operands[1]) != DImode)
6336 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6339 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6345 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6348 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6357 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6360 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6366 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6369 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6373 output_asm_insn (buf, xoperands);
6374 return output_lbranch (operands[0], insn);
6382 /* This routine handles long unconditional branches that exceed the
6383 maximum range of a simple branch instruction. */
6386 output_lbranch (rtx dest, rtx insn)
6390 xoperands[0] = dest;
6392 /* First, free up the delay slot. */
6393 if (dbr_sequence_length () != 0)
6395 /* We can't handle a jump in the delay slot. */
6396 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6399 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6400 optimize, 0, 0, NULL);
6402 /* Now delete the delay insn. */
6403 PUT_CODE (NEXT_INSN (insn), NOTE);
6404 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6405 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6408 /* Output an insn to save %r1. The runtime documentation doesn't
6409 specify whether the "Clean Up" slot in the callers frame can
6410 be clobbered by the callee. It isn't copied by HP's builtin
6411 alloca, so this suggests that it can be clobbered if necessary.
6412 The "Static Link" location is copied by HP builtin alloca, so
6413 we avoid using it. Using the cleanup slot might be a problem
6414 if we have to interoperate with languages that pass cleanup
6415 information. However, it should be possible to handle these
6416 situations with GCC's asm feature.
6418 The "Current RP" slot is reserved for the called procedure, so
6419 we try to use it when we don't have a frame of our own. It's
6420 rather unlikely that we won't have a frame when we need to emit
6423 Really the way to go long term is a register scavenger; goto
6424 the target of the jump and find a register which we can use
6425 as a scratch to hold the value in %r1. Then, we wouldn't have
6426 to free up the delay slot or clobber a slot that may be needed
6427 for other purposes. */
6430 if (actual_fsize == 0 && !regs_ever_live[2])
6431 /* Use the return pointer slot in the frame marker. */
6432 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6434 /* Use the slot at -40 in the frame marker since HP builtin
6435 alloca doesn't copy it. */
6436 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6440 if (actual_fsize == 0 && !regs_ever_live[2])
6441 /* Use the return pointer slot in the frame marker. */
6442 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6444 /* Use the "Clean Up" slot in the frame marker. In GCC,
6445 the only other use of this location is for copying a
6446 floating point double argument from a floating-point
6447 register to two general registers. The copy is done
6448 as an "atomic" operation when outputting a call, so it
6449 won't interfere with our using the location here. */
6450 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6453 if (TARGET_PORTABLE_RUNTIME)
6455 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6456 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6457 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6461 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6462 if (TARGET_SOM || !TARGET_GAS)
6464 xoperands[1] = gen_label_rtx ();
6465 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6466 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6467 CODE_LABEL_NUMBER (xoperands[1]));
6468 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6472 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6473 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6475 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6478 /* Now output a very long branch to the original target. */
6479 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6481 /* Now restore the value of %r1 in the delay slot. */
6484 if (actual_fsize == 0 && !regs_ever_live[2])
6485 return "ldd -16(%%r30),%%r1";
6487 return "ldd -40(%%r30),%%r1";
6491 if (actual_fsize == 0 && !regs_ever_live[2])
6492 return "ldw -20(%%r30),%%r1";
6494 return "ldw -12(%%r30),%%r1";
6498 /* This routine handles all the branch-on-bit conditional branch sequences we
6499 might need to generate. It handles nullification of delay slots,
6500 varying length branches, negated branches and all combinations of the
6501 above. it returns the appropriate output template to emit the branch. */
6504 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6505 int negated, rtx insn, int which)
6507 static char buf[100];
6510 /* A conditional branch to the following instruction (e.g. the delay slot) is
6511 asking for a disaster. I do not think this can happen as this pattern
6512 is only used when optimizing; jump optimization should eliminate the
6513 jump. But be prepared just in case. */
6515 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6518 /* If this is a long branch with its delay slot unfilled, set `nullify'
6519 as it can nullify the delay slot and save a nop. */
6520 if (length == 8 && dbr_sequence_length () == 0)
6523 /* If this is a short forward conditional branch which did not get
6524 its delay slot filled, the delay slot can still be nullified. */
6525 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6526 nullify = forward_branch_p (insn);
6528 /* A forward branch over a single nullified insn can be done with a
6529 extrs instruction. This avoids a single cycle penalty due to
6530 mis-predicted branch if we fall through (branch not taken). */
6533 && next_real_insn (insn) != 0
6534 && get_attr_length (next_real_insn (insn)) == 4
6535 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6542 /* All short conditional branches except backwards with an unfilled
6546 strcpy (buf, "{extrs,|extrw,s,}");
6548 strcpy (buf, "bb,");
6549 if (useskip && GET_MODE (operands[0]) == DImode)
6550 strcpy (buf, "extrd,s,*");
6551 else if (GET_MODE (operands[0]) == DImode)
6552 strcpy (buf, "bb,*");
6553 if ((which == 0 && negated)
6554 || (which == 1 && ! negated))
6559 strcat (buf, " %0,%1,1,%%r0");
6560 else if (nullify && negated)
6561 strcat (buf, ",n %0,%1,%3");
6562 else if (nullify && ! negated)
6563 strcat (buf, ",n %0,%1,%2");
6564 else if (! nullify && negated)
6565 strcat (buf, "%0,%1,%3");
6566 else if (! nullify && ! negated)
6567 strcat (buf, " %0,%1,%2");
6570 /* All long conditionals. Note a short backward branch with an
6571 unfilled delay slot is treated just like a long backward branch
6572 with an unfilled delay slot. */
6574 /* Handle weird backwards branch with a filled delay slot
6575 with is nullified. */
6576 if (dbr_sequence_length () != 0
6577 && ! forward_branch_p (insn)
6580 strcpy (buf, "bb,");
6581 if (GET_MODE (operands[0]) == DImode)
6583 if ((which == 0 && negated)
6584 || (which == 1 && ! negated))
6589 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6591 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6593 /* Handle short backwards branch with an unfilled delay slot.
6594 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6595 taken and untaken branches. */
6596 else if (dbr_sequence_length () == 0
6597 && ! forward_branch_p (insn)
6598 && INSN_ADDRESSES_SET_P ()
6599 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6600 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6602 strcpy (buf, "bb,");
6603 if (GET_MODE (operands[0]) == DImode)
6605 if ((which == 0 && negated)
6606 || (which == 1 && ! negated))
6611 strcat (buf, " %0,%1,%3%#");
6613 strcat (buf, " %0,%1,%2%#");
6617 strcpy (buf, "{extrs,|extrw,s,}");
6618 if (GET_MODE (operands[0]) == DImode)
6619 strcpy (buf, "extrd,s,*");
6620 if ((which == 0 && negated)
6621 || (which == 1 && ! negated))
6625 if (nullify && negated)
6626 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6627 else if (nullify && ! negated)
6628 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6630 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6632 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6642 /* This routine handles all the branch-on-variable-bit conditional branch
6643 sequences we might need to generate. It handles nullification of delay
6644 slots, varying length branches, negated branches and all combinations
6645 of the above. it returns the appropriate output template to emit the
6649 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6650 int negated, rtx insn, int which)
6652 static char buf[100];
6655 /* A conditional branch to the following instruction (e.g. the delay slot) is
6656 asking for a disaster. I do not think this can happen as this pattern
6657 is only used when optimizing; jump optimization should eliminate the
6658 jump. But be prepared just in case. */
6660 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6663 /* If this is a long branch with its delay slot unfilled, set `nullify'
6664 as it can nullify the delay slot and save a nop. */
6665 if (length == 8 && dbr_sequence_length () == 0)
6668 /* If this is a short forward conditional branch which did not get
6669 its delay slot filled, the delay slot can still be nullified. */
6670 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6671 nullify = forward_branch_p (insn);
6673 /* A forward branch over a single nullified insn can be done with a
6674 extrs instruction. This avoids a single cycle penalty due to
6675 mis-predicted branch if we fall through (branch not taken). */
6678 && next_real_insn (insn) != 0
6679 && get_attr_length (next_real_insn (insn)) == 4
6680 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6687 /* All short conditional branches except backwards with an unfilled
6691 strcpy (buf, "{vextrs,|extrw,s,}");
6693 strcpy (buf, "{bvb,|bb,}");
6694 if (useskip && GET_MODE (operands[0]) == DImode)
6695 strcpy (buf, "extrd,s,*");
6696 else if (GET_MODE (operands[0]) == DImode)
6697 strcpy (buf, "bb,*");
6698 if ((which == 0 && negated)
6699 || (which == 1 && ! negated))
6704 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6705 else if (nullify && negated)
6706 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6707 else if (nullify && ! negated)
6708 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6709 else if (! nullify && negated)
6710 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6711 else if (! nullify && ! negated)
6712 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6715 /* All long conditionals. Note a short backward branch with an
6716 unfilled delay slot is treated just like a long backward branch
6717 with an unfilled delay slot. */
6719 /* Handle weird backwards branch with a filled delay slot
6720 with is nullified. */
6721 if (dbr_sequence_length () != 0
6722 && ! forward_branch_p (insn)
6725 strcpy (buf, "{bvb,|bb,}");
6726 if (GET_MODE (operands[0]) == DImode)
6728 if ((which == 0 && negated)
6729 || (which == 1 && ! negated))
6734 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6736 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6738 /* Handle short backwards branch with an unfilled delay slot.
6739 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6740 taken and untaken branches. */
6741 else if (dbr_sequence_length () == 0
6742 && ! forward_branch_p (insn)
6743 && INSN_ADDRESSES_SET_P ()
6744 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6745 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6747 strcpy (buf, "{bvb,|bb,}");
6748 if (GET_MODE (operands[0]) == DImode)
6750 if ((which == 0 && negated)
6751 || (which == 1 && ! negated))
6756 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6758 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6762 strcpy (buf, "{vextrs,|extrw,s,}");
6763 if (GET_MODE (operands[0]) == DImode)
6764 strcpy (buf, "extrd,s,*");
6765 if ((which == 0 && negated)
6766 || (which == 1 && ! negated))
6770 if (nullify && negated)
6771 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6772 else if (nullify && ! negated)
6773 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6775 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6777 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6787 /* Return the output template for emitting a dbra type insn.
6789 Note it may perform some output operations on its own before
6790 returning the final output string. */
6792 output_dbra (rtx *operands, rtx insn, int which_alternative)
6795 /* A conditional branch to the following instruction (e.g. the delay slot) is
6796 asking for a disaster. Be prepared! */
6798 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6800 if (which_alternative == 0)
6801 return "ldo %1(%0),%0";
6802 else if (which_alternative == 1)
6804 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6805 output_asm_insn ("ldw -16(%%r30),%4", operands);
6806 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6807 return "{fldws|fldw} -16(%%r30),%0";
6811 output_asm_insn ("ldw %0,%4", operands);
6812 return "ldo %1(%4),%4\n\tstw %4,%0";
6816 if (which_alternative == 0)
6818 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6819 int length = get_attr_length (insn);
6821 /* If this is a long branch with its delay slot unfilled, set `nullify'
6822 as it can nullify the delay slot and save a nop. */
6823 if (length == 8 && dbr_sequence_length () == 0)
6826 /* If this is a short forward conditional branch which did not get
6827 its delay slot filled, the delay slot can still be nullified. */
6828 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6829 nullify = forward_branch_p (insn);
6831 /* Handle short versions first. */
6832 if (length == 4 && nullify)
6833 return "addib,%C2,n %1,%0,%3";
6834 else if (length == 4 && ! nullify)
6835 return "addib,%C2 %1,%0,%3";
6836 else if (length == 8)
6838 /* Handle weird backwards branch with a fulled delay slot
6839 which is nullified. */
6840 if (dbr_sequence_length () != 0
6841 && ! forward_branch_p (insn)
6843 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6844 /* Handle short backwards branch with an unfilled delay slot.
6845 Using a addb;nop rather than addi;bl saves 1 cycle for both
6846 taken and untaken branches. */
6847 else if (dbr_sequence_length () == 0
6848 && ! forward_branch_p (insn)
6849 && INSN_ADDRESSES_SET_P ()
6850 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6851 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6852 return "addib,%C2 %1,%0,%3%#";
6854 /* Handle normal cases. */
6856 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6858 return "addi,%N2 %1,%0,%0\n\tb %3";
6863 /* Deal with gross reload from FP register case. */
6864 else if (which_alternative == 1)
6866 /* Move loop counter from FP register to MEM then into a GR,
6867 increment the GR, store the GR into MEM, and finally reload
6868 the FP register from MEM from within the branch's delay slot. */
6869 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6871 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6872 if (get_attr_length (insn) == 24)
6873 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6875 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6877 /* Deal with gross reload from memory case. */
6880 /* Reload loop counter from memory, the store back to memory
6881 happens in the branch's delay slot. */
6882 output_asm_insn ("ldw %0,%4", operands);
6883 if (get_attr_length (insn) == 12)
6884 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6886 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6890 /* Return the output template for emitting a dbra type insn.
6892 Note it may perform some output operations on its own before
6893 returning the final output string. */
6895 output_movb (rtx *operands, rtx insn, int which_alternative,
6896 int reverse_comparison)
6899 /* A conditional branch to the following instruction (e.g. the delay slot) is
6900 asking for a disaster. Be prepared! */
6902 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6904 if (which_alternative == 0)
6905 return "copy %1,%0";
6906 else if (which_alternative == 1)
6908 output_asm_insn ("stw %1,-16(%%r30)", operands);
6909 return "{fldws|fldw} -16(%%r30),%0";
6911 else if (which_alternative == 2)
6917 /* Support the second variant. */
6918 if (reverse_comparison)
6919 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6921 if (which_alternative == 0)
6923 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6924 int length = get_attr_length (insn);
6926 /* If this is a long branch with its delay slot unfilled, set `nullify'
6927 as it can nullify the delay slot and save a nop. */
6928 if (length == 8 && dbr_sequence_length () == 0)
6931 /* If this is a short forward conditional branch which did not get
6932 its delay slot filled, the delay slot can still be nullified. */
6933 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6934 nullify = forward_branch_p (insn);
6936 /* Handle short versions first. */
6937 if (length == 4 && nullify)
6938 return "movb,%C2,n %1,%0,%3";
6939 else if (length == 4 && ! nullify)
6940 return "movb,%C2 %1,%0,%3";
6941 else if (length == 8)
6943 /* Handle weird backwards branch with a filled delay slot
6944 which is nullified. */
6945 if (dbr_sequence_length () != 0
6946 && ! forward_branch_p (insn)
6948 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6950 /* Handle short backwards branch with an unfilled delay slot.
6951 Using a movb;nop rather than or;bl saves 1 cycle for both
6952 taken and untaken branches. */
6953 else if (dbr_sequence_length () == 0
6954 && ! forward_branch_p (insn)
6955 && INSN_ADDRESSES_SET_P ()
6956 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6957 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6958 return "movb,%C2 %1,%0,%3%#";
6959 /* Handle normal cases. */
6961 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6963 return "or,%N2 %1,%%r0,%0\n\tb %3";
6968 /* Deal with gross reload from FP register case. */
6969 else if (which_alternative == 1)
6971 /* Move loop counter from FP register to MEM then into a GR,
6972 increment the GR, store the GR into MEM, and finally reload
6973 the FP register from MEM from within the branch's delay slot. */
6974 output_asm_insn ("stw %1,-16(%%r30)", operands);
6975 if (get_attr_length (insn) == 12)
6976 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6978 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6980 /* Deal with gross reload from memory case. */
6981 else if (which_alternative == 2)
6983 /* Reload loop counter from memory, the store back to memory
6984 happens in the branch's delay slot. */
6985 if (get_attr_length (insn) == 8)
6986 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6988 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6990 /* Handle SAR as a destination. */
6993 if (get_attr_length (insn) == 8)
6994 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6996 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7000 /* Copy any FP arguments in INSN into integer registers. */
7002 copy_fp_args (rtx insn)
7007 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7009 int arg_mode, regno;
7010 rtx use = XEXP (link, 0);
7012 if (! (GET_CODE (use) == USE
7013 && GET_CODE (XEXP (use, 0)) == REG
7014 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7017 arg_mode = GET_MODE (XEXP (use, 0));
7018 regno = REGNO (XEXP (use, 0));
7020 /* Is it a floating point register? */
7021 if (regno >= 32 && regno <= 39)
7023 /* Copy the FP register into an integer register via memory. */
7024 if (arg_mode == SFmode)
7026 xoperands[0] = XEXP (use, 0);
7027 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7028 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7029 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7033 xoperands[0] = XEXP (use, 0);
7034 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7035 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7036 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7037 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7043 /* Compute length of the FP argument copy sequence for INSN. */
7045 length_fp_args (rtx insn)
7050 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7052 int arg_mode, regno;
7053 rtx use = XEXP (link, 0);
7055 if (! (GET_CODE (use) == USE
7056 && GET_CODE (XEXP (use, 0)) == REG
7057 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7060 arg_mode = GET_MODE (XEXP (use, 0));
7061 regno = REGNO (XEXP (use, 0));
7063 /* Is it a floating point register? */
7064 if (regno >= 32 && regno <= 39)
7066 if (arg_mode == SFmode)
7076 /* Return the attribute length for the millicode call instruction INSN.
7077 The length must match the code generated by output_millicode_call.
7078 We include the delay slot in the returned length as it is better to
7079 over estimate the length than to under estimate it. */
7082 attr_length_millicode_call (rtx insn)
7084 unsigned long distance = -1;
7085 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7087 if (INSN_ADDRESSES_SET_P ())
7089 distance = (total + insn_current_reference_address (insn));
7090 if (distance < total)
7096 if (!TARGET_LONG_CALLS && distance < 7600000)
7101 else if (TARGET_PORTABLE_RUNTIME)
7105 if (!TARGET_LONG_CALLS && distance < 240000)
7108 if (TARGET_LONG_ABS_CALL && !flag_pic)
7115 /* INSN is a function call. It may have an unconditional jump
7118 CALL_DEST is the routine we are calling. */
7121 output_millicode_call (rtx insn, rtx call_dest)
7123 int attr_length = get_attr_length (insn);
7124 int seq_length = dbr_sequence_length ();
7129 xoperands[0] = call_dest;
7130 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7132 /* Handle the common case where we are sure that the branch will
7133 reach the beginning of the $CODE$ subspace. The within reach
7134 form of the $$sh_func_adrs call has a length of 28. Because
7135 it has an attribute type of multi, it never has a nonzero
7136 sequence length. The length of the $$sh_func_adrs is the same
7137 as certain out of reach PIC calls to other routines. */
7138 if (!TARGET_LONG_CALLS
7139 && ((seq_length == 0
7140 && (attr_length == 12
7141 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7142 || (seq_length != 0 && attr_length == 8)))
7144 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7150 /* It might seem that one insn could be saved by accessing
7151 the millicode function using the linkage table. However,
7152 this doesn't work in shared libraries and other dynamically
7153 loaded objects. Using a pc-relative sequence also avoids
7154 problems related to the implicit use of the gp register. */
7155 output_asm_insn ("b,l .+8,%%r1", xoperands);
7159 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7160 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7164 xoperands[1] = gen_label_rtx ();
7165 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7166 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7167 CODE_LABEL_NUMBER (xoperands[1]));
7168 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7171 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7173 else if (TARGET_PORTABLE_RUNTIME)
7175 /* Pure portable runtime doesn't allow be/ble; we also don't
7176 have PIC support in the assembler/linker, so this sequence
7179 /* Get the address of our target into %r1. */
7180 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7181 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7183 /* Get our return address into %r31. */
7184 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7185 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7187 /* Jump to our target address in %r1. */
7188 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7192 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7194 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7196 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7200 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7201 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7203 if (TARGET_SOM || !TARGET_GAS)
7205 /* The HP assembler can generate relocations for the
7206 difference of two symbols. GAS can do this for a
7207 millicode symbol but not an arbitrary external
7208 symbol when generating SOM output. */
7209 xoperands[1] = gen_label_rtx ();
7210 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7211 CODE_LABEL_NUMBER (xoperands[1]));
7212 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7213 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7217 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7218 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7222 /* Jump to our target address in %r1. */
7223 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7227 if (seq_length == 0)
7228 output_asm_insn ("nop", xoperands);
7230 /* We are done if there isn't a jump in the delay slot. */
7231 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7234 /* This call has an unconditional jump in its delay slot. */
7235 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7237 /* See if the return address can be adjusted. Use the containing
7238 sequence insn's address. */
7239 if (INSN_ADDRESSES_SET_P ())
7241 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7242 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7243 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7245 if (VAL_14_BITS_P (distance))
7247 xoperands[1] = gen_label_rtx ();
7248 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7249 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7250 CODE_LABEL_NUMBER (xoperands[1]));
7253 /* ??? This branch may not reach its target. */
7254 output_asm_insn ("nop\n\tb,n %0", xoperands);
7257 /* ??? This branch may not reach its target. */
7258 output_asm_insn ("nop\n\tb,n %0", xoperands);
7260 /* Delete the jump. */
7261 PUT_CODE (NEXT_INSN (insn), NOTE);
7262 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7263 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7268 /* Return the attribute length of the call instruction INSN. The SIBCALL
7269 flag indicates whether INSN is a regular call or a sibling call. The
7270 length returned must be longer than the code actually generated by
7271 output_call. Since branch shortening is done before delay branch
7272 sequencing, there is no way to determine whether or not the delay
7273 slot will be filled during branch shortening. Even when the delay
7274 slot is filled, we may have to add a nop if the delay slot contains
7275 a branch that can't reach its target. Thus, we always have to include
7276 the delay slot in the length estimate. This used to be done in
7277 pa_adjust_insn_length but we do it here now as some sequences always
7278 fill the delay slot and we can save four bytes in the estimate for
7282 attr_length_call (rtx insn, int sibcall)
7288 rtx pat = PATTERN (insn);
7289 unsigned long distance = -1;
7291 if (INSN_ADDRESSES_SET_P ())
7293 unsigned long total;
7295 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7296 distance = (total + insn_current_reference_address (insn));
7297 if (distance < total)
7301 /* Determine if this is a local call. */
7302 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7303 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7305 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7307 call_decl = SYMBOL_REF_DECL (call_dest);
7308 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7310 /* pc-relative branch. */
7311 if (!TARGET_LONG_CALLS
7312 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7313 || distance < 240000))
7316 /* 64-bit plabel sequence. */
7317 else if (TARGET_64BIT && !local_call)
7318 length += sibcall ? 28 : 24;
7320 /* non-pic long absolute branch sequence. */
7321 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7324 /* long pc-relative branch sequence. */
7325 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7326 || (TARGET_64BIT && !TARGET_GAS)
7327 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7331 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7335 /* 32-bit plabel sequence. */
7341 length += length_fp_args (insn);
7351 if (!TARGET_NO_SPACE_REGS)
7359 /* INSN is a function call. It may have an unconditional jump
7362 CALL_DEST is the routine we are calling. */
7365 output_call (rtx insn, rtx call_dest, int sibcall)
7367 int delay_insn_deleted = 0;
7368 int delay_slot_filled = 0;
7369 int seq_length = dbr_sequence_length ();
7370 tree call_decl = SYMBOL_REF_DECL (call_dest);
7371 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7374 xoperands[0] = call_dest;
7376 /* Handle the common case where we're sure that the branch will reach
7377 the beginning of the "$CODE$" subspace. This is the beginning of
7378 the current function if we are in a named section. */
7379 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7381 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7382 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7386 if (TARGET_64BIT && !local_call)
7388 /* ??? As far as I can tell, the HP linker doesn't support the
7389 long pc-relative sequence described in the 64-bit runtime
7390 architecture. So, we use a slightly longer indirect call. */
7391 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7393 xoperands[0] = p->internal_label;
7394 xoperands[1] = gen_label_rtx ();
7396 /* If this isn't a sibcall, we put the load of %r27 into the
7397 delay slot. We can't do this in a sibcall as we don't
7398 have a second call-clobbered scratch register available. */
7400 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7403 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7404 optimize, 0, 0, NULL);
7406 /* Now delete the delay insn. */
7407 PUT_CODE (NEXT_INSN (insn), NOTE);
7408 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7409 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7410 delay_insn_deleted = 1;
7413 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7414 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7415 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7419 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7420 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7421 output_asm_insn ("bve (%%r1)", xoperands);
7425 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7426 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7427 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7428 delay_slot_filled = 1;
7433 int indirect_call = 0;
7435 /* Emit a long call. There are several different sequences
7436 of increasing length and complexity. In most cases,
7437 they don't allow an instruction in the delay slot. */
7438 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7439 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7440 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7445 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7447 && (!TARGET_PA_20 || indirect_call))
7449 /* A non-jump insn in the delay slot. By definition we can
7450 emit this insn before the call (and in fact before argument
7452 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7455 /* Now delete the delay insn. */
7456 PUT_CODE (NEXT_INSN (insn), NOTE);
7457 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7458 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7459 delay_insn_deleted = 1;
7462 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7464 /* This is the best sequence for making long calls in
7465 non-pic code. Unfortunately, GNU ld doesn't provide
7466 the stub needed for external calls, and GAS's support
7467 for this with the SOM linker is buggy. It is safe
7468 to use this for local calls. */
7469 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7471 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7475 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7478 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7480 output_asm_insn ("copy %%r31,%%r2", xoperands);
7481 delay_slot_filled = 1;
7486 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7487 || (TARGET_64BIT && !TARGET_GAS))
7489 /* The HP assembler and linker can handle relocations
7490 for the difference of two symbols. GAS and the HP
7491 linker can't do this when one of the symbols is
7493 xoperands[1] = gen_label_rtx ();
7494 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7495 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7496 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7497 CODE_LABEL_NUMBER (xoperands[1]));
7498 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7500 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7502 /* GAS currently can't generate the relocations that
7503 are needed for the SOM linker under HP-UX using this
7504 sequence. The GNU linker doesn't generate the stubs
7505 that are needed for external calls on TARGET_ELF32
7506 with this sequence. For now, we have to use a
7507 longer plabel sequence when using GAS. */
7508 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7509 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7511 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7516 /* Emit a long plabel-based call sequence. This is
7517 essentially an inline implementation of $$dyncall.
7518 We don't actually try to call $$dyncall as this is
7519 as difficult as calling the function itself. */
7520 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7522 xoperands[0] = p->internal_label;
7523 xoperands[1] = gen_label_rtx ();
7525 /* Since the call is indirect, FP arguments in registers
7526 need to be copied to the general registers. Then, the
7527 argument relocation stub will copy them back. */
7529 copy_fp_args (insn);
7533 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7534 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7535 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7539 output_asm_insn ("addil LR'%0-$global$,%%r27",
7541 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7545 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7546 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7547 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7548 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7550 if (!sibcall && !TARGET_PA_20)
7552 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7553 if (TARGET_NO_SPACE_REGS)
7554 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7556 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7563 output_asm_insn ("bve (%%r1)", xoperands);
7568 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7569 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7570 delay_slot_filled = 1;
7573 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7578 if (!TARGET_NO_SPACE_REGS)
7579 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7584 if (TARGET_NO_SPACE_REGS)
7585 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7587 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7591 if (TARGET_NO_SPACE_REGS)
7592 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7594 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7597 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7599 output_asm_insn ("copy %%r31,%%r2", xoperands);
7600 delay_slot_filled = 1;
7607 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7608 output_asm_insn ("nop", xoperands);
7610 /* We are done if there isn't a jump in the delay slot. */
7612 || delay_insn_deleted
7613 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7616 /* A sibcall should never have a branch in the delay slot. */
7620 /* This call has an unconditional jump in its delay slot. */
7621 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7623 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7625 /* See if the return address can be adjusted. Use the containing
7626 sequence insn's address. */
7627 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7628 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7629 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7631 if (VAL_14_BITS_P (distance))
7633 xoperands[1] = gen_label_rtx ();
7634 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7635 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7636 CODE_LABEL_NUMBER (xoperands[1]));
7639 output_asm_insn ("nop\n\tb,n %0", xoperands);
7642 output_asm_insn ("b,n %0", xoperands);
7644 /* Delete the jump. */
7645 PUT_CODE (NEXT_INSN (insn), NOTE);
7646 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7647 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7652 /* Return the attribute length of the indirect call instruction INSN.
7653 The length must match the code generated by output_indirect call.
7654 The returned length includes the delay slot. Currently, the delay
7655 slot of an indirect call sequence is not exposed and it is used by
7656 the sequence itself. */
7659 attr_length_indirect_call (rtx insn)
7661 unsigned long distance = -1;
7662 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7664 if (INSN_ADDRESSES_SET_P ())
7666 distance = (total + insn_current_reference_address (insn));
7667 if (distance < total)
7674 if (TARGET_FAST_INDIRECT_CALLS
7675 || (!TARGET_PORTABLE_RUNTIME
7676 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7682 if (TARGET_PORTABLE_RUNTIME)
7685 /* Out of reach, can use ble. */
7690 output_indirect_call (rtx insn, rtx call_dest)
7696 xoperands[0] = call_dest;
7697 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7698 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7702 /* First the special case for kernels, level 0 systems, etc. */
7703 if (TARGET_FAST_INDIRECT_CALLS)
7704 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7706 /* Now the normal case -- we can reach $$dyncall directly or
7707 we're sure that we can get there via a long-branch stub.
7709 No need to check target flags as the length uniquely identifies
7710 the remaining cases. */
7711 if (attr_length_indirect_call (insn) == 8)
7713 /* The HP linker substitutes a BLE for millicode calls using
7714 the short PIC PCREL form. Thus, we must use %r31 as the
7715 link register when generating PA 1.x code. */
7717 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7719 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7722 /* Long millicode call, but we are not generating PIC or portable runtime
7724 if (attr_length_indirect_call (insn) == 12)
7725 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7727 /* Long millicode call for portable runtime. */
7728 if (attr_length_indirect_call (insn) == 20)
7729 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7731 /* We need a long PIC call to $$dyncall. */
7732 xoperands[0] = NULL_RTX;
7733 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7734 if (TARGET_SOM || !TARGET_GAS)
7736 xoperands[0] = gen_label_rtx ();
7737 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7738 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7739 CODE_LABEL_NUMBER (xoperands[0]));
7740 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7744 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7745 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7748 output_asm_insn ("blr %%r0,%%r2", xoperands);
7749 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7753 /* Return the total length of the save and restore instructions needed for
7754 the data linkage table pointer (i.e., the PIC register) across the call
7755 instruction INSN. No-return calls do not require a save and restore.
7756 In addition, we may be able to avoid the save and restore for calls
7757 within the same translation unit. */
7760 attr_length_save_restore_dltp (rtx insn)
7762 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7768 /* In HPUX 8.0's shared library scheme, special relocations are needed
7769 for function labels if they might be passed to a function
7770 in a shared library (because shared libraries don't live in code
7771 space), and special magic is needed to construct their address. */
7774 hppa_encode_label (rtx sym)
7776 const char *str = XSTR (sym, 0);
7777 int len = strlen (str) + 1;
7780 p = newstr = alloca (len + 1);
7784 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7788 pa_encode_section_info (tree decl, rtx rtl, int first)
7790 if (first && TEXT_SPACE_P (decl))
7792 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7793 if (TREE_CODE (decl) == FUNCTION_DECL)
7794 hppa_encode_label (XEXP (rtl, 0));
7798 /* This is sort of inverse to pa_encode_section_info. */
7801 pa_strip_name_encoding (const char *str)
7803 str += (*str == '@');
7804 str += (*str == '*');
7809 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7811 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7814 /* Returns 1 if OP is a function label involved in a simple addition
7815 with a constant. Used to keep certain patterns from matching
7816 during instruction combination. */
7818 is_function_label_plus_const (rtx op)
7820 /* Strip off any CONST. */
7821 if (GET_CODE (op) == CONST)
7824 return (GET_CODE (op) == PLUS
7825 && function_label_operand (XEXP (op, 0), Pmode)
7826 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7829 /* Output assembly code for a thunk to FUNCTION. */
7832 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7833 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7836 const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7837 const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
7838 int val_14 = VAL_14_BITS_P (delta);
7840 static unsigned int current_thunk_number;
7843 ASM_OUTPUT_LABEL (file, tname);
7844 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7846 fname = (*targetm.strip_name_encoding) (fname);
7847 tname = (*targetm.strip_name_encoding) (tname);
7849 /* Output the thunk. We know that the function is in the same
7850 translation unit (i.e., the same space) as the thunk, and that
7851 thunks are output after their method. Thus, we don't need an
7852 external branch to reach the function. With SOM and GAS,
7853 functions and thunks are effectively in different sections.
7854 Thus, we can always use a IA-relative branch and the linker
7855 will add a long branch stub if necessary.
7857 However, we have to be careful when generating PIC code on the
7858 SOM port to ensure that the sequence does not transfer to an
7859 import stub for the target function as this could clobber the
7860 return value saved at SP-24. This would also apply to the
7861 32-bit linux port if the multi-space model is implemented. */
7862 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7863 && !(flag_pic && TREE_PUBLIC (function))
7864 && (TARGET_GAS || last_address < 262132))
7865 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7866 && ((targetm.have_named_sections
7867 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7868 /* The GNU 64-bit linker has rather poor stub management.
7869 So, we use a long branch from thunks that aren't in
7870 the same section as the target function. */
7872 && (DECL_SECTION_NAME (thunk_fndecl)
7873 != DECL_SECTION_NAME (function)))
7874 || ((DECL_SECTION_NAME (thunk_fndecl)
7875 == DECL_SECTION_NAME (function))
7876 && last_address < 262132)))
7877 || (!targetm.have_named_sections && last_address < 262132))))
7881 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7882 "(%%r26),%%r26\n", fname, delta);
7887 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7889 fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7890 "(%%r1),%%r26\n", fname, delta);
7894 else if (TARGET_64BIT)
7896 /* We only have one call-clobbered scratch register, so we can't
7897 make use of the delay slot if delta doesn't fit in 14 bits. */
7899 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7900 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7901 "(%%r1),%%r26\n", delta, delta);
7903 fprintf (file, "\tb,l .+8,%%r1\n");
7907 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7908 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname);
7912 int off = val_14 ? 8 : 16;
7913 fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off);
7914 fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off);
7919 fprintf (file, "\tbv %%r0(%%r1)\n\tldo ");
7920 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7925 fprintf (file, "\tbv,n %%r0(%%r1)\n");
7929 else if (TARGET_PORTABLE_RUNTIME)
7931 fprintf (file, "\tldil L'%s,%%r1\n", fname);
7932 fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname);
7936 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7937 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7942 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7944 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7945 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7949 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7951 /* The function is accessible from outside this module. The only
7952 way to avoid an import stub between the thunk and function is to
7953 call the function directly with an indirect sequence similar to
7954 that used by $$dyncall. This is possible because $$dyncall acts
7955 as the import stub in an indirect call. */
7958 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7959 lab = (*targetm.strip_name_encoding) (label);
7961 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7962 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7963 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7964 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7965 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7966 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7967 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7970 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7976 fprintf (file, "\tbve (%%r22)\n\tldo ");
7981 if (TARGET_NO_SPACE_REGS)
7983 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7988 fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
7989 fprintf (file, "\tmtsp %%r21,%%sr0\n");
7990 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7996 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7998 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
8003 fprintf (file, "\tb,l .+8,%%r1\n");
8005 fprintf (file, "\tbl .+8,%%r1\n");
8007 if (TARGET_SOM || !TARGET_GAS)
8009 fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname);
8010 fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname);
8014 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
8015 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname);
8020 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
8021 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
8026 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
8028 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
8029 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
8036 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta);
8038 fprintf (file, "\tldil L'%s,%%r22\n", fname);
8039 fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname);
8043 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
8048 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
8053 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8055 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8058 fprintf (file, "\t.align 4\n");
8059 ASM_OUTPUT_LABEL (file, label);
8060 fprintf (file, "\t.word P'%s\n", fname);
8062 else if (TARGET_SOM && TARGET_GAS)
8065 current_thunk_number++;
8066 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8067 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8068 last_address += nbytes;
8069 update_total_code_bytes (nbytes);
8072 /* Only direct calls to static functions are allowed to be sibling (tail)
8075 This restriction is necessary because some linker generated stubs will
8076 store return pointers into rp' in some cases which might clobber a
8077 live value already in rp'.
8079 In a sibcall the current function and the target function share stack
8080 space. Thus if the path to the current function and the path to the
8081 target function save a value in rp', they save the value into the
8082 same stack slot, which has undesirable consequences.
8084 Because of the deferred binding nature of shared libraries any function
8085 with external scope could be in a different load module and thus require
8086 rp' to be saved when calling that function. So sibcall optimizations
8087 can only be safe for static function.
8089 Note that GCC never needs return value relocations, so we don't have to
8090 worry about static calls with return value relocations (which require
8093 It is safe to perform a sibcall optimization when the target function
8094 will never return. */
8096 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8098 if (TARGET_PORTABLE_RUNTIME)
8101 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8102 single subspace mode and the call is not indirect. As far as I know,
8103 there is no operating system support for the multiple subspace mode.
8104 It might be possible to support indirect calls if we didn't use
8105 $$dyncall (see the indirect sequence generated in output_call). */
8107 return (decl != NULL_TREE);
8109 /* Sibcalls are not ok because the arg pointer register is not a fixed
8110 register. This prevents the sibcall optimization from occurring. In
8111 addition, there are problems with stub placement using GNU ld. This
8112 is because a normal sibcall branch uses a 17-bit relocation while
8113 a regular call branch uses a 22-bit relocation. As a result, more
8114 care needs to be taken in the placement of long-branch stubs. */
8118 /* Sibcalls are only ok within a translation unit. */
8119 return (decl && !TREE_PUBLIC (decl));
8122 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8123 use in fmpyadd instructions. */
8125 fmpyaddoperands (rtx *operands)
8127 enum machine_mode mode = GET_MODE (operands[0]);
8129 /* Must be a floating point mode. */
8130 if (mode != SFmode && mode != DFmode)
8133 /* All modes must be the same. */
8134 if (! (mode == GET_MODE (operands[1])
8135 && mode == GET_MODE (operands[2])
8136 && mode == GET_MODE (operands[3])
8137 && mode == GET_MODE (operands[4])
8138 && mode == GET_MODE (operands[5])))
8141 /* All operands must be registers. */
8142 if (! (GET_CODE (operands[1]) == REG
8143 && GET_CODE (operands[2]) == REG
8144 && GET_CODE (operands[3]) == REG
8145 && GET_CODE (operands[4]) == REG
8146 && GET_CODE (operands[5]) == REG))
8149 /* Only 2 real operands to the addition. One of the input operands must
8150 be the same as the output operand. */
8151 if (! rtx_equal_p (operands[3], operands[4])
8152 && ! rtx_equal_p (operands[3], operands[5]))
8155 /* Inout operand of add cannot conflict with any operands from multiply. */
8156 if (rtx_equal_p (operands[3], operands[0])
8157 || rtx_equal_p (operands[3], operands[1])
8158 || rtx_equal_p (operands[3], operands[2]))
8161 /* multiply cannot feed into addition operands. */
8162 if (rtx_equal_p (operands[4], operands[0])
8163 || rtx_equal_p (operands[5], operands[0]))
8166 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8168 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8169 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8170 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8171 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8172 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8173 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8176 /* Passed. Operands are suitable for fmpyadd. */
8180 #if !defined(USE_COLLECT2)
8182 pa_asm_out_constructor (rtx symbol, int priority)
8184 if (!function_label_operand (symbol, VOIDmode))
8185 hppa_encode_label (symbol);
8187 #ifdef CTORS_SECTION_ASM_OP
8188 default_ctor_section_asm_out_constructor (symbol, priority);
8190 # ifdef TARGET_ASM_NAMED_SECTION
8191 default_named_section_asm_out_constructor (symbol, priority);
8193 default_stabs_asm_out_constructor (symbol, priority);
8199 pa_asm_out_destructor (rtx symbol, int priority)
8201 if (!function_label_operand (symbol, VOIDmode))
8202 hppa_encode_label (symbol);
8204 #ifdef DTORS_SECTION_ASM_OP
8205 default_dtor_section_asm_out_destructor (symbol, priority);
8207 # ifdef TARGET_ASM_NAMED_SECTION
8208 default_named_section_asm_out_destructor (symbol, priority);
8210 default_stabs_asm_out_destructor (symbol, priority);
8216 /* This function places uninitialized global data in the bss section.
8217 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8218 function on the SOM port to prevent uninitialized global data from
8219 being placed in the data section. */
8222 pa_asm_output_aligned_bss (FILE *stream,
8224 unsigned HOST_WIDE_INT size,
8228 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8230 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8231 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8234 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8235 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8238 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8239 ASM_OUTPUT_LABEL (stream, name);
8240 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8243 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8244 that doesn't allow the alignment of global common storage to be directly
8245 specified. The SOM linker aligns common storage based on the rounded
8246 value of the NUM_BYTES parameter in the .comm directive. It's not
8247 possible to use the .align directive as it doesn't affect the alignment
8248 of the label associated with a .comm directive. */
8251 pa_asm_output_aligned_common (FILE *stream,
8253 unsigned HOST_WIDE_INT size,
8258 assemble_name (stream, name);
8259 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8260 MAX (size, align / BITS_PER_UNIT));
8263 /* We can't use .comm for local common storage as the SOM linker effectively
8264 treats the symbol as universal and uses the same storage for local symbols
8265 with the same name in different object files. The .block directive
8266 reserves an uninitialized block of storage. However, it's not common
8267 storage. Fortunately, GCC never requests common storage with the same
8268 name in any given translation unit. */
8271 pa_asm_output_aligned_local (FILE *stream,
8273 unsigned HOST_WIDE_INT size,
8277 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8280 fprintf (stream, "%s", LOCAL_ASM_OP);
8281 assemble_name (stream, name);
8282 fprintf (stream, "\n");
8285 ASM_OUTPUT_LABEL (stream, name);
8286 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8289 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8290 use in fmpysub instructions. */
8292 fmpysuboperands (rtx *operands)
8294 enum machine_mode mode = GET_MODE (operands[0]);
8296 /* Must be a floating point mode. */
8297 if (mode != SFmode && mode != DFmode)
8300 /* All modes must be the same. */
8301 if (! (mode == GET_MODE (operands[1])
8302 && mode == GET_MODE (operands[2])
8303 && mode == GET_MODE (operands[3])
8304 && mode == GET_MODE (operands[4])
8305 && mode == GET_MODE (operands[5])))
8308 /* All operands must be registers. */
8309 if (! (GET_CODE (operands[1]) == REG
8310 && GET_CODE (operands[2]) == REG
8311 && GET_CODE (operands[3]) == REG
8312 && GET_CODE (operands[4]) == REG
8313 && GET_CODE (operands[5]) == REG))
8316 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8317 operation, so operands[4] must be the same as operand[3]. */
8318 if (! rtx_equal_p (operands[3], operands[4]))
8321 /* multiply cannot feed into subtraction. */
8322 if (rtx_equal_p (operands[5], operands[0]))
8325 /* Inout operand of sub cannot conflict with any operands from multiply. */
8326 if (rtx_equal_p (operands[3], operands[0])
8327 || rtx_equal_p (operands[3], operands[1])
8328 || rtx_equal_p (operands[3], operands[2]))
8331 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8333 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8334 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8335 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8336 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8337 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8338 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8341 /* Passed. Operands are suitable for fmpysub. */
8346 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8348 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8349 || GET_CODE (op) == IOR);
8352 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8353 constants for shadd instructions. */
8355 shadd_constant_p (int val)
8357 if (val == 2 || val == 4 || val == 8)
8363 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8364 the valid constant for shadd instructions. */
8366 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8368 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8371 /* Return 1 if OP is valid as a base or index register in a
8375 borx_reg_operand (rtx op, enum machine_mode mode)
8377 if (GET_CODE (op) != REG)
8380 /* We must reject virtual registers as the only expressions that
8381 can be instantiated are REG and REG+CONST. */
8382 if (op == virtual_incoming_args_rtx
8383 || op == virtual_stack_vars_rtx
8384 || op == virtual_stack_dynamic_rtx
8385 || op == virtual_outgoing_args_rtx
8386 || op == virtual_cfa_rtx)
8389 /* While it's always safe to index off the frame pointer, it's not
8390 profitable to do so when the frame pointer is being eliminated. */
8391 if (!reload_completed
8392 && flag_omit_frame_pointer
8393 && !current_function_calls_alloca
8394 && op == frame_pointer_rtx)
8397 return register_operand (op, mode);
8400 /* Return 1 if this operand is anything other than a hard register. */
8403 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8405 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8408 /* Return 1 if INSN branches forward. Should be using insn_addresses
8409 to avoid walking through all the insns... */
8411 forward_branch_p (rtx insn)
8413 rtx label = JUMP_LABEL (insn);
8420 insn = NEXT_INSN (insn);
8423 return (insn == label);
8426 /* Return 1 if OP is an equality comparison, else return 0. */
8428 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8430 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8433 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8435 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8437 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8438 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8441 /* Return 1 if INSN is in the delay slot of a call instruction. */
8443 jump_in_call_delay (rtx insn)
8446 if (GET_CODE (insn) != JUMP_INSN)
8449 if (PREV_INSN (insn)
8450 && PREV_INSN (PREV_INSN (insn))
8451 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8453 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8455 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8456 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8463 /* Output an unconditional move and branch insn. */
8466 output_parallel_movb (rtx *operands, int length)
8468 /* These are the cases in which we win. */
8470 return "mov%I1b,tr %1,%0,%2";
8472 /* None of these cases wins, but they don't lose either. */
8473 if (dbr_sequence_length () == 0)
8475 /* Nothing in the delay slot, fake it by putting the combined
8476 insn (the copy or add) in the delay slot of a bl. */
8477 if (GET_CODE (operands[1]) == CONST_INT)
8478 return "b %2\n\tldi %1,%0";
8480 return "b %2\n\tcopy %1,%0";
8484 /* Something in the delay slot, but we've got a long branch. */
8485 if (GET_CODE (operands[1]) == CONST_INT)
8486 return "ldi %1,%0\n\tb %2";
8488 return "copy %1,%0\n\tb %2";
8492 /* Output an unconditional add and branch insn. */
8495 output_parallel_addb (rtx *operands, int length)
8497 /* To make life easy we want operand0 to be the shared input/output
8498 operand and operand1 to be the readonly operand. */
8499 if (operands[0] == operands[1])
8500 operands[1] = operands[2];
8502 /* These are the cases in which we win. */
8504 return "add%I1b,tr %1,%0,%3";
8506 /* None of these cases win, but they don't lose either. */
8507 if (dbr_sequence_length () == 0)
8509 /* Nothing in the delay slot, fake it by putting the combined
8510 insn (the copy or add) in the delay slot of a bl. */
8511 return "b %3\n\tadd%I1 %1,%0,%0";
8515 /* Something in the delay slot, but we've got a long branch. */
8516 return "add%I1 %1,%0,%0\n\tb %3";
8520 /* Return nonzero if INSN (a jump insn) immediately follows a call
8521 to a named function. This is used to avoid filling the delay slot
8522 of the jump since it can usually be eliminated by modifying RP in
8523 the delay slot of the call. */
8526 following_call (rtx insn)
8528 if (! TARGET_JUMP_IN_DELAY)
8531 /* Find the previous real insn, skipping NOTEs. */
8532 insn = PREV_INSN (insn);
8533 while (insn && GET_CODE (insn) == NOTE)
8534 insn = PREV_INSN (insn);
8536 /* Check for CALL_INSNs and millicode calls. */
8538 && ((GET_CODE (insn) == CALL_INSN
8539 && get_attr_type (insn) != TYPE_DYNCALL)
8540 || (GET_CODE (insn) == INSN
8541 && GET_CODE (PATTERN (insn)) != SEQUENCE
8542 && GET_CODE (PATTERN (insn)) != USE
8543 && GET_CODE (PATTERN (insn)) != CLOBBER
8544 && get_attr_type (insn) == TYPE_MILLI)))
8550 /* We use this hook to perform a PA specific optimization which is difficult
8551 to do in earlier passes.
8553 We want the delay slots of branches within jump tables to be filled.
8554 None of the compiler passes at the moment even has the notion that a
8555 PA jump table doesn't contain addresses, but instead contains actual
8558 Because we actually jump into the table, the addresses of each entry
8559 must stay constant in relation to the beginning of the table (which
8560 itself must stay constant relative to the instruction to jump into
8561 it). I don't believe we can guarantee earlier passes of the compiler
8562 will adhere to those rules.
8564 So, late in the compilation process we find all the jump tables, and
8565 expand them into real code -- e.g. each entry in the jump table vector
8566 will get an appropriate label followed by a jump to the final target.
8568 Reorg and the final jump pass can then optimize these branches and
8569 fill their delay slots. We end up with smaller, more efficient code.
8571 The jump instructions within the table are special; we must be able
8572 to identify them during assembly output (if the jumps don't get filled
8573 we need to emit a nop rather than nullifying the delay slot)). We
8574 identify jumps in switch tables by using insns with the attribute
8575 type TYPE_BTABLE_BRANCH.
8577 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8578 insns. This serves two purposes, first it prevents jump.c from
8579 noticing that the last N entries in the table jump to the instruction
8580 immediately after the table and deleting the jumps. Second, those
8581 insns mark where we should emit .begin_brtab and .end_brtab directives
8582 when using GAS (allows for better link time optimizations). */
8589 remove_useless_addtr_insns (1);
8591 if (pa_cpu < PROCESSOR_8000)
8592 pa_combine_instructions ();
8595 /* This is fairly cheap, so always run it if optimizing. */
8596 if (optimize > 0 && !TARGET_BIG_SWITCH)
8598 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8599 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8601 rtx pattern, tmp, location, label;
8602 unsigned int length, i;
8604 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8605 if (GET_CODE (insn) != JUMP_INSN
8606 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8607 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8610 /* Emit marker for the beginning of the branch table. */
8611 emit_insn_before (gen_begin_brtab (), insn);
8613 pattern = PATTERN (insn);
8614 location = PREV_INSN (insn);
8615 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8617 for (i = 0; i < length; i++)
8619 /* Emit a label before each jump to keep jump.c from
8620 removing this code. */
8621 tmp = gen_label_rtx ();
8622 LABEL_NUSES (tmp) = 1;
8623 emit_label_after (tmp, location);
8624 location = NEXT_INSN (location);
8626 if (GET_CODE (pattern) == ADDR_VEC)
8627 label = XEXP (XVECEXP (pattern, 0, i), 0);
8629 label = XEXP (XVECEXP (pattern, 1, i), 0);
8631 tmp = gen_short_jump (label);
8633 /* Emit the jump itself. */
8634 tmp = emit_jump_insn_after (tmp, location);
8635 JUMP_LABEL (tmp) = label;
8636 LABEL_NUSES (label)++;
8637 location = NEXT_INSN (location);
8639 /* Emit a BARRIER after the jump. */
8640 emit_barrier_after (location);
8641 location = NEXT_INSN (location);
8644 /* Emit marker for the end of the branch table. */
8645 emit_insn_before (gen_end_brtab (), location);
8646 location = NEXT_INSN (location);
8647 emit_barrier_after (location);
8649 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8655 /* Still need brtab marker insns. FIXME: the presence of these
8656 markers disables output of the branch table to readonly memory,
8657 and any alignment directives that might be needed. Possibly,
8658 the begin_brtab insn should be output before the label for the
8659 table. This doesn't matter at the moment since the tables are
8660 always output in the text section. */
8661 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8663 /* Find an ADDR_VEC insn. */
8664 if (GET_CODE (insn) != JUMP_INSN
8665 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8666 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8669 /* Now generate markers for the beginning and end of the
8671 emit_insn_before (gen_begin_brtab (), insn);
8672 emit_insn_after (gen_end_brtab (), insn);
8677 /* The PA has a number of odd instructions which can perform multiple
8678 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8679 it may be profitable to combine two instructions into one instruction
8680 with two outputs. It's not profitable PA2.0 machines because the
8681 two outputs would take two slots in the reorder buffers.
8683 This routine finds instructions which can be combined and combines
8684 them. We only support some of the potential combinations, and we
8685 only try common ways to find suitable instructions.
8687 * addb can add two registers or a register and a small integer
8688 and jump to a nearby (+-8k) location. Normally the jump to the
8689 nearby location is conditional on the result of the add, but by
8690 using the "true" condition we can make the jump unconditional.
8691 Thus addb can perform two independent operations in one insn.
8693 * movb is similar to addb in that it can perform a reg->reg
8694 or small immediate->reg copy and jump to a nearby (+-8k location).
8696 * fmpyadd and fmpysub can perform a FP multiply and either an
8697 FP add or FP sub if the operands of the multiply and add/sub are
8698 independent (there are other minor restrictions). Note both
8699 the fmpy and fadd/fsub can in theory move to better spots according
8700 to data dependencies, but for now we require the fmpy stay at a
8703 * Many of the memory operations can perform pre & post updates
8704 of index registers. GCC's pre/post increment/decrement addressing
8705 is far too simple to take advantage of all the possibilities. This
8706 pass may not be suitable since those insns may not be independent.
8708 * comclr can compare two ints or an int and a register, nullify
8709 the following instruction and zero some other register. This
8710 is more difficult to use as it's harder to find an insn which
8711 will generate a comclr than finding something like an unconditional
8712 branch. (conditional moves & long branches create comclr insns).
8714 * Most arithmetic operations can conditionally skip the next
8715 instruction. They can be viewed as "perform this operation
8716 and conditionally jump to this nearby location" (where nearby
8717 is an insns away). These are difficult to use due to the
8718 branch length restrictions. */
8721 pa_combine_instructions (void)
8725 /* This can get expensive since the basic algorithm is on the
8726 order of O(n^2) (or worse). Only do it for -O2 or higher
8727 levels of optimization. */
8731 /* Walk down the list of insns looking for "anchor" insns which
8732 may be combined with "floating" insns. As the name implies,
8733 "anchor" instructions don't move, while "floating" insns may
8735 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8736 new = make_insn_raw (new);
8738 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8740 enum attr_pa_combine_type anchor_attr;
8741 enum attr_pa_combine_type floater_attr;
8743 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8744 Also ignore any special USE insns. */
8745 if ((GET_CODE (anchor) != INSN
8746 && GET_CODE (anchor) != JUMP_INSN
8747 && GET_CODE (anchor) != CALL_INSN)
8748 || GET_CODE (PATTERN (anchor)) == USE
8749 || GET_CODE (PATTERN (anchor)) == CLOBBER
8750 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8751 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8754 anchor_attr = get_attr_pa_combine_type (anchor);
8755 /* See if anchor is an insn suitable for combination. */
8756 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8757 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8758 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8759 && ! forward_branch_p (anchor)))
8763 for (floater = PREV_INSN (anchor);
8765 floater = PREV_INSN (floater))
8767 if (GET_CODE (floater) == NOTE
8768 || (GET_CODE (floater) == INSN
8769 && (GET_CODE (PATTERN (floater)) == USE
8770 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8773 /* Anything except a regular INSN will stop our search. */
8774 if (GET_CODE (floater) != INSN
8775 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8776 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8782 /* See if FLOATER is suitable for combination with the
8784 floater_attr = get_attr_pa_combine_type (floater);
8785 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8786 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8787 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8788 && floater_attr == PA_COMBINE_TYPE_FMPY))
8790 /* If ANCHOR and FLOATER can be combined, then we're
8791 done with this pass. */
8792 if (pa_can_combine_p (new, anchor, floater, 0,
8793 SET_DEST (PATTERN (floater)),
8794 XEXP (SET_SRC (PATTERN (floater)), 0),
8795 XEXP (SET_SRC (PATTERN (floater)), 1)))
8799 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8800 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8802 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8804 if (pa_can_combine_p (new, anchor, floater, 0,
8805 SET_DEST (PATTERN (floater)),
8806 XEXP (SET_SRC (PATTERN (floater)), 0),
8807 XEXP (SET_SRC (PATTERN (floater)), 1)))
8812 if (pa_can_combine_p (new, anchor, floater, 0,
8813 SET_DEST (PATTERN (floater)),
8814 SET_SRC (PATTERN (floater)),
8815 SET_SRC (PATTERN (floater))))
8821 /* If we didn't find anything on the backwards scan try forwards. */
8823 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8824 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8826 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8828 if (GET_CODE (floater) == NOTE
8829 || (GET_CODE (floater) == INSN
8830 && (GET_CODE (PATTERN (floater)) == USE
8831 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8835 /* Anything except a regular INSN will stop our search. */
8836 if (GET_CODE (floater) != INSN
8837 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8838 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8844 /* See if FLOATER is suitable for combination with the
8846 floater_attr = get_attr_pa_combine_type (floater);
8847 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8848 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8849 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8850 && floater_attr == PA_COMBINE_TYPE_FMPY))
8852 /* If ANCHOR and FLOATER can be combined, then we're
8853 done with this pass. */
8854 if (pa_can_combine_p (new, anchor, floater, 1,
8855 SET_DEST (PATTERN (floater)),
8856 XEXP (SET_SRC (PATTERN (floater)),
8858 XEXP (SET_SRC (PATTERN (floater)),
8865 /* FLOATER will be nonzero if we found a suitable floating
8866 insn for combination with ANCHOR. */
8868 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8869 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8871 /* Emit the new instruction and delete the old anchor. */
8872 emit_insn_before (gen_rtx_PARALLEL
8874 gen_rtvec (2, PATTERN (anchor),
8875 PATTERN (floater))),
8878 PUT_CODE (anchor, NOTE);
8879 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8880 NOTE_SOURCE_FILE (anchor) = 0;
8882 /* Emit a special USE insn for FLOATER, then delete
8883 the floating insn. */
8884 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8885 delete_insn (floater);
8890 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8893 /* Emit the new_jump instruction and delete the old anchor. */
8895 = emit_jump_insn_before (gen_rtx_PARALLEL
8897 gen_rtvec (2, PATTERN (anchor),
8898 PATTERN (floater))),
8901 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8902 PUT_CODE (anchor, NOTE);
8903 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8904 NOTE_SOURCE_FILE (anchor) = 0;
8906 /* Emit a special USE insn for FLOATER, then delete
8907 the floating insn. */
8908 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8909 delete_insn (floater);
8917 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8920 int insn_code_number;
8923 /* Create a PARALLEL with the patterns of ANCHOR and
8924 FLOATER, try to recognize it, then test constraints
8925 for the resulting pattern.
8927 If the pattern doesn't match or the constraints
8928 aren't met keep searching for a suitable floater
8930 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8931 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8932 INSN_CODE (new) = -1;
8933 insn_code_number = recog_memoized (new);
8934 if (insn_code_number < 0
8935 || (extract_insn (new), ! constrain_operands (1)))
8949 /* There's up to three operands to consider. One
8950 output and two inputs.
8952 The output must not be used between FLOATER & ANCHOR
8953 exclusive. The inputs must not be set between
8954 FLOATER and ANCHOR exclusive. */
8956 if (reg_used_between_p (dest, start, end))
8959 if (reg_set_between_p (src1, start, end))
8962 if (reg_set_between_p (src2, start, end))
8965 /* If we get here, then everything is good. */
8969 /* Return nonzero if references for INSN are delayed.
8971 Millicode insns are actually function calls with some special
8972 constraints on arguments and register usage.
8974 Millicode calls always expect their arguments in the integer argument
8975 registers, and always return their result in %r29 (ret1). They
8976 are expected to clobber their arguments, %r1, %r29, and the return
8977 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8979 This function tells reorg that the references to arguments and
8980 millicode calls do not appear to happen until after the millicode call.
8981 This allows reorg to put insns which set the argument registers into the
8982 delay slot of the millicode call -- thus they act more like traditional
8985 Note we cannot consider side effects of the insn to be delayed because
8986 the branch and link insn will clobber the return pointer. If we happened
8987 to use the return pointer in the delay slot of the call, then we lose.
8989 get_attr_type will try to recognize the given insn, so make sure to
8990 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8993 insn_refs_are_delayed (rtx insn)
8995 return ((GET_CODE (insn) == INSN
8996 && GET_CODE (PATTERN (insn)) != SEQUENCE
8997 && GET_CODE (PATTERN (insn)) != USE
8998 && GET_CODE (PATTERN (insn)) != CLOBBER
8999 && get_attr_type (insn) == TYPE_MILLI));
9002 /* On the HP-PA the value is found in register(s) 28(-29), unless
9003 the mode is SF or DF. Then the value is returned in fr4 (32).
9005 This must perform the same promotions as PROMOTE_MODE, else
9006 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
9008 Small structures must be returned in a PARALLEL on PA64 in order
9009 to match the HP Compiler ABI. */
9012 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
9014 enum machine_mode valmode;
9016 /* Aggregates with a size less than or equal to 128 bits are returned
9017 in GR 28(-29). They are left justified. The pad bits are undefined.
9018 Larger aggregates are returned in memory. */
9019 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
9023 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9025 for (i = 0; i < ub; i++)
9027 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9028 gen_rtx_REG (DImode, 28 + i),
9033 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9036 if ((INTEGRAL_TYPE_P (valtype)
9037 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
9038 || POINTER_TYPE_P (valtype))
9039 valmode = word_mode;
9041 valmode = TYPE_MODE (valtype);
9043 if (TREE_CODE (valtype) == REAL_TYPE
9044 && TYPE_MODE (valtype) != TFmode
9045 && !TARGET_SOFT_FLOAT)
9046 return gen_rtx_REG (valmode, 32);
9048 return gen_rtx_REG (valmode, 28);
9051 /* Return the location of a parameter that is passed in a register or NULL
9052 if the parameter has any component that is passed in memory.
9054 This is new code and will be pushed to into the net sources after
9057 ??? We might want to restructure this so that it looks more like other
9060 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
9061 int named ATTRIBUTE_UNUSED)
9063 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9070 if (mode == VOIDmode)
9073 arg_size = FUNCTION_ARG_SIZE (mode, type);
9075 /* If this arg would be passed partially or totally on the stack, then
9076 this routine should return zero. pa_arg_partial_bytes will
9077 handle arguments which are split between regs and stack slots if
9078 the ABI mandates split arguments. */
9081 /* The 32-bit ABI does not split arguments. */
9082 if (cum->words + arg_size > max_arg_words)
9088 alignment = cum->words & 1;
9089 if (cum->words + alignment >= max_arg_words)
9093 /* The 32bit ABIs and the 64bit ABIs are rather different,
9094 particularly in their handling of FP registers. We might
9095 be able to cleverly share code between them, but I'm not
9096 going to bother in the hope that splitting them up results
9097 in code that is more easily understood. */
9101 /* Advance the base registers to their current locations.
9103 Remember, gprs grow towards smaller register numbers while
9104 fprs grow to higher register numbers. Also remember that
9105 although FP regs are 32-bit addressable, we pretend that
9106 the registers are 64-bits wide. */
9107 gpr_reg_base = 26 - cum->words;
9108 fpr_reg_base = 32 + cum->words;
9110 /* Arguments wider than one word and small aggregates need special
9114 || (type && AGGREGATE_TYPE_P (type)))
9116 /* Double-extended precision (80-bit), quad-precision (128-bit)
9117 and aggregates including complex numbers are aligned on
9118 128-bit boundaries. The first eight 64-bit argument slots
9119 are associated one-to-one, with general registers r26
9120 through r19, and also with floating-point registers fr4
9121 through fr11. Arguments larger than one word are always
9122 passed in general registers.
9124 Using a PARALLEL with a word mode register results in left
9125 justified data on a big-endian target. */
9128 int i, offset = 0, ub = arg_size;
9130 /* Align the base register. */
9131 gpr_reg_base -= alignment;
9133 ub = MIN (ub, max_arg_words - cum->words - alignment);
9134 for (i = 0; i < ub; i++)
9136 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9137 gen_rtx_REG (DImode, gpr_reg_base),
9143 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9148 /* If the argument is larger than a word, then we know precisely
9149 which registers we must use. */
9163 /* Structures 5 to 8 bytes in size are passed in the general
9164 registers in the same manner as other non floating-point
9165 objects. The data is right-justified and zero-extended
9166 to 64 bits. This is opposite to the normal justification
9167 used on big endian targets and requires special treatment.
9168 We now define BLOCK_REG_PADDING to pad these objects. */
9169 if (mode == BLKmode)
9171 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9172 gen_rtx_REG (DImode, gpr_reg_base),
9174 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
9179 /* We have a single word (32 bits). A simple computation
9180 will get us the register #s we need. */
9181 gpr_reg_base = 26 - cum->words;
9182 fpr_reg_base = 32 + 2 * cum->words;
9186 /* Determine if the argument needs to be passed in both general and
9187 floating point registers. */
9188 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9189 /* If we are doing soft-float with portable runtime, then there
9190 is no need to worry about FP regs. */
9191 && !TARGET_SOFT_FLOAT
9192 /* The parameter must be some kind of float, else we can just
9193 pass it in integer registers. */
9194 && FLOAT_MODE_P (mode)
9195 /* The target function must not have a prototype. */
9196 && cum->nargs_prototype <= 0
9197 /* libcalls do not need to pass items in both FP and general
9199 && type != NULL_TREE
9200 /* All this hair applies to "outgoing" args only. This includes
9201 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9203 /* Also pass outgoing floating arguments in both registers in indirect
9204 calls with the 32 bit ABI and the HP assembler since there is no
9205 way to the specify argument locations in static functions. */
9210 && FLOAT_MODE_P (mode)))
9216 gen_rtx_EXPR_LIST (VOIDmode,
9217 gen_rtx_REG (mode, fpr_reg_base),
9219 gen_rtx_EXPR_LIST (VOIDmode,
9220 gen_rtx_REG (mode, gpr_reg_base),
9225 /* See if we should pass this parameter in a general register. */
9226 if (TARGET_SOFT_FLOAT
9227 /* Indirect calls in the normal 32bit ABI require all arguments
9228 to be passed in general registers. */
9229 || (!TARGET_PORTABLE_RUNTIME
9233 /* If the parameter is not a floating point parameter, then
9234 it belongs in GPRs. */
9235 || !FLOAT_MODE_P (mode))
9236 retval = gen_rtx_REG (mode, gpr_reg_base);
9238 retval = gen_rtx_REG (mode, fpr_reg_base);
9244 /* If this arg would be passed totally in registers or totally on the stack,
9245 then this routine should return zero. */
9248 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9249 tree type, bool named ATTRIBUTE_UNUSED)
9251 unsigned int max_arg_words = 8;
9252 unsigned int offset = 0;
9257 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9260 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9261 /* Arg fits fully into registers. */
9263 else if (cum->words + offset >= max_arg_words)
9264 /* Arg fully on the stack. */
9268 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9272 /* Return 1 if this is a comparison operator. This allows the use of
9273 MATCH_OPERATOR to recognize all the branch insns. */
9276 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9278 return ((mode == VOIDmode || GET_MODE (op) == mode)
9279 && (GET_CODE (op) == EQ
9280 || GET_CODE (op) == NE
9281 || GET_CODE (op) == GT
9282 || GET_CODE (op) == GTU
9283 || GET_CODE (op) == GE
9284 || GET_CODE (op) == LT
9285 || GET_CODE (op) == LE
9286 || GET_CODE (op) == LEU));
9289 /* Return a string to output before text in the current function.
9291 This function is only used with SOM. Because we don't support
9292 named subspaces, we can only create a new subspace or switch back
9293 to the default text subspace. */
9295 som_text_section_asm_op (void)
9302 if (cfun && !cfun->machine->in_nsubspa)
9304 /* We only want to emit a .nsubspa directive once at the
9305 start of the function. */
9306 cfun->machine->in_nsubspa = 1;
9308 /* Create a new subspace for the text. This provides
9309 better stub placement and one-only functions. */
9311 && DECL_ONE_ONLY (cfun->decl)
9312 && !DECL_WEAK (cfun->decl))
9314 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
9316 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
9320 /* There isn't a current function or the body of the current
9321 function has been completed. So, we are changing to the
9322 text section to output debugging information. Do this in
9323 the default text section. We need to forget that we are
9324 in the text section so that the function text_section in
9325 varasm.c will call us the next time around. */
9330 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
9333 /* On hpux10, the linker will give an error if we have a reference
9334 in the read-only data section to a symbol defined in a shared
9335 library. Therefore, expressions that might require a reloc can
9336 not be placed in the read-only data section. */
9339 pa_select_section (tree exp, int reloc,
9340 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9342 if (TREE_CODE (exp) == VAR_DECL
9343 && TREE_READONLY (exp)
9344 && !TREE_THIS_VOLATILE (exp)
9345 && DECL_INITIAL (exp)
9346 && (DECL_INITIAL (exp) == error_mark_node
9347 || TREE_CONSTANT (DECL_INITIAL (exp)))
9351 && DECL_ONE_ONLY (exp)
9352 && !DECL_WEAK (exp))
9353 som_one_only_readonly_data_section ();
9355 readonly_data_section ();
9357 else if (CONSTANT_CLASS_P (exp) && !reloc)
9358 readonly_data_section ();
9360 && TREE_CODE (exp) == VAR_DECL
9361 && DECL_ONE_ONLY (exp)
9362 && !DECL_WEAK (exp))
9363 som_one_only_data_section ();
9369 pa_globalize_label (FILE *stream, const char *name)
9371 /* We only handle DATA objects here, functions are globalized in
9372 ASM_DECLARE_FUNCTION_NAME. */
9373 if (! FUNCTION_NAME_P (name))
9375 fputs ("\t.EXPORT ", stream);
9376 assemble_name (stream, name);
9377 fputs (",DATA\n", stream);
9381 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9384 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9385 int incoming ATTRIBUTE_UNUSED)
9387 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9390 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9393 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9395 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9396 PA64 ABI says that objects larger than 128 bits are returned in memory.
9397 Note, int_size_in_bytes can return -1 if the size of the object is
9398 variable or larger than the maximum value that can be expressed as
9399 a HOST_WIDE_INT. It can also return zero for an empty type. The
9400 simplest way to handle variable and empty types is to pass them in
9401 memory. This avoids problems in defining the boundaries of argument
9402 slots, allocating registers, etc. */
9403 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9404 || int_size_in_bytes (type) <= 0);