1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static bool pa_handle_option (size_t, const char *, int);
88 static int hppa_address_cost (rtx);
89 static bool hppa_rtx_costs (rtx, int, int, int *);
90 static inline rtx force_mode (enum machine_mode, rtx);
91 static void pa_reorg (void);
92 static void pa_combine_instructions (void);
93 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
94 static int forward_branch_p (rtx);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
111 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
113 static void pa_encode_section_info (tree, rtx, int);
114 static const char *pa_strip_name_encoding (const char *);
115 static bool pa_function_ok_for_sibcall (tree, tree);
116 static void pa_globalize_label (FILE *, const char *)
118 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
119 HOST_WIDE_INT, tree);
120 #if !defined(USE_COLLECT2)
121 static void pa_asm_out_constructor (rtx, int);
122 static void pa_asm_out_destructor (rtx, int);
124 static void pa_init_builtins (void);
125 static rtx hppa_builtin_saveregs (void);
126 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
127 static bool pa_scalar_mode_supported_p (enum machine_mode);
128 static bool pa_commutative_p (rtx x, int outer_code);
129 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
130 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
134 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
135 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
139 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
140 static void output_deferred_plabels (void);
141 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
142 #ifdef ASM_OUTPUT_EXTERNAL_REAL
143 static void pa_hpux_file_end (void);
145 #ifdef HPUX_LONG_DOUBLE_LIBRARY
146 static void pa_hpux_init_libfuncs (void);
148 static rtx pa_struct_value_rtx (tree, int);
149 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
151 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
153 static struct machine_function * pa_init_machine_status (void);
154 static enum reg_class pa_secondary_reload (bool, rtx, enum reg_class,
156 secondary_reload_info *);
159 /* The following extra sections are only used for SOM. */
160 static GTY(()) section *som_readonly_data_section;
161 static GTY(()) section *som_one_only_readonly_data_section;
162 static GTY(()) section *som_one_only_data_section;
164 /* Save the operands last given to a compare for use when we
165 generate a scc or bcc insn. */
166 rtx hppa_compare_op0, hppa_compare_op1;
167 enum cmp_type hppa_branch_type;
169 /* Which cpu we are scheduling for. */
170 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
172 /* The UNIX standard to use for predefines and linking. */
173 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
175 /* Counts for the number of callee-saved general and floating point
176 registers which were saved by the current function's prologue. */
177 static int gr_saved, fr_saved;
179 static rtx find_addr_reg (rtx);
181 /* Keep track of the number of bytes we have output in the CODE subspace
182 during this compilation so we'll know when to emit inline long-calls. */
183 unsigned long total_code_bytes;
185 /* The last address of the previous function plus the number of bytes in
186 associated thunks that have been output. This is used to determine if
187 a thunk can use an IA-relative branch to reach its target function. */
188 static int last_address;
190 /* Variables to handle plabels that we discover are necessary at assembly
191 output time. They are output after the current function. */
192 struct deferred_plabel GTY(())
197 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
199 static size_t n_deferred_plabels = 0;
202 /* Initialize the GCC target structure. */
204 #undef TARGET_ASM_ALIGNED_HI_OP
205 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
206 #undef TARGET_ASM_ALIGNED_SI_OP
207 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
208 #undef TARGET_ASM_ALIGNED_DI_OP
209 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
210 #undef TARGET_ASM_UNALIGNED_HI_OP
211 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
212 #undef TARGET_ASM_UNALIGNED_SI_OP
213 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
214 #undef TARGET_ASM_UNALIGNED_DI_OP
215 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
216 #undef TARGET_ASM_INTEGER
217 #define TARGET_ASM_INTEGER pa_assemble_integer
219 #undef TARGET_ASM_FUNCTION_PROLOGUE
220 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
221 #undef TARGET_ASM_FUNCTION_EPILOGUE
222 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
224 #undef TARGET_SCHED_ADJUST_COST
225 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
226 #undef TARGET_SCHED_ADJUST_PRIORITY
227 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
228 #undef TARGET_SCHED_ISSUE_RATE
229 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
231 #undef TARGET_ENCODE_SECTION_INFO
232 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
233 #undef TARGET_STRIP_NAME_ENCODING
234 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
236 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
237 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
239 #undef TARGET_COMMUTATIVE_P
240 #define TARGET_COMMUTATIVE_P pa_commutative_p
242 #undef TARGET_ASM_OUTPUT_MI_THUNK
243 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
244 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
245 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
247 #undef TARGET_ASM_FILE_END
248 #ifdef ASM_OUTPUT_EXTERNAL_REAL
249 #define TARGET_ASM_FILE_END pa_hpux_file_end
251 #define TARGET_ASM_FILE_END output_deferred_plabels
254 #if !defined(USE_COLLECT2)
255 #undef TARGET_ASM_CONSTRUCTOR
256 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
257 #undef TARGET_ASM_DESTRUCTOR
258 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
261 #undef TARGET_DEFAULT_TARGET_FLAGS
262 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
263 #undef TARGET_HANDLE_OPTION
264 #define TARGET_HANDLE_OPTION pa_handle_option
266 #undef TARGET_INIT_BUILTINS
267 #define TARGET_INIT_BUILTINS pa_init_builtins
269 #undef TARGET_RTX_COSTS
270 #define TARGET_RTX_COSTS hppa_rtx_costs
271 #undef TARGET_ADDRESS_COST
272 #define TARGET_ADDRESS_COST hppa_address_cost
274 #undef TARGET_MACHINE_DEPENDENT_REORG
275 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
277 #ifdef HPUX_LONG_DOUBLE_LIBRARY
278 #undef TARGET_INIT_LIBFUNCS
279 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
282 #undef TARGET_PROMOTE_FUNCTION_RETURN
283 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
284 #undef TARGET_PROMOTE_PROTOTYPES
285 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
287 #undef TARGET_STRUCT_VALUE_RTX
288 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
289 #undef TARGET_RETURN_IN_MEMORY
290 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
291 #undef TARGET_MUST_PASS_IN_STACK
292 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
293 #undef TARGET_PASS_BY_REFERENCE
294 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
295 #undef TARGET_CALLEE_COPIES
296 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
297 #undef TARGET_ARG_PARTIAL_BYTES
298 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
300 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
301 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
302 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
303 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
305 #undef TARGET_SCALAR_MODE_SUPPORTED_P
306 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
308 #undef TARGET_CANNOT_FORCE_CONST_MEM
309 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
311 #undef TARGET_SECONDARY_RELOAD
312 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
314 struct gcc_target targetm = TARGET_INITIALIZER;
316 /* Parse the -mfixed-range= option string. */
319 fix_range (const char *const_str)
322 char *str, *dash, *comma;
324 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
325 REG2 are either register names or register numbers. The effect
326 of this option is to mark the registers in the range from REG1 to
327 REG2 as ``fixed'' so they won't be used by the compiler. This is
328 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
330 i = strlen (const_str);
331 str = (char *) alloca (i + 1);
332 memcpy (str, const_str, i + 1);
336 dash = strchr (str, '-');
339 warning (0, "value of -mfixed-range must have form REG1-REG2");
344 comma = strchr (dash + 1, ',');
348 first = decode_reg_name (str);
351 warning (0, "unknown register name: %s", str);
355 last = decode_reg_name (dash + 1);
358 warning (0, "unknown register name: %s", dash + 1);
366 warning (0, "%s-%s is an empty range", str, dash + 1);
370 for (i = first; i <= last; ++i)
371 fixed_regs[i] = call_used_regs[i] = 1;
380 /* Check if all floating point registers have been fixed. */
381 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
386 target_flags |= MASK_DISABLE_FPREGS;
389 /* Implement TARGET_HANDLE_OPTION. */
392 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
397 case OPT_mpa_risc_1_0:
399 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
403 case OPT_mpa_risc_1_1:
405 target_flags &= ~MASK_PA_20;
406 target_flags |= MASK_PA_11;
409 case OPT_mpa_risc_2_0:
411 target_flags |= MASK_PA_11 | MASK_PA_20;
415 if (strcmp (arg, "8000") == 0)
416 pa_cpu = PROCESSOR_8000;
417 else if (strcmp (arg, "7100") == 0)
418 pa_cpu = PROCESSOR_7100;
419 else if (strcmp (arg, "700") == 0)
420 pa_cpu = PROCESSOR_700;
421 else if (strcmp (arg, "7100LC") == 0)
422 pa_cpu = PROCESSOR_7100LC;
423 else if (strcmp (arg, "7200") == 0)
424 pa_cpu = PROCESSOR_7200;
425 else if (strcmp (arg, "7300") == 0)
426 pa_cpu = PROCESSOR_7300;
431 case OPT_mfixed_range_:
441 #if TARGET_HPUX_10_10
447 #if TARGET_HPUX_11_11
459 override_options (void)
461 /* Unconditional branches in the delay slot are not compatible with dwarf2
462 call frame information. There is no benefit in using this optimization
463 on PA8000 and later processors. */
464 if (pa_cpu >= PROCESSOR_8000
465 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
466 || flag_unwind_tables)
467 target_flags &= ~MASK_JUMP_IN_DELAY;
469 if (flag_pic && TARGET_PORTABLE_RUNTIME)
471 warning (0, "PIC code generation is not supported in the portable runtime model");
474 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
476 warning (0, "PIC code generation is not compatible with fast indirect calls");
479 if (! TARGET_GAS && write_symbols != NO_DEBUG)
481 warning (0, "-g is only supported when using GAS on this processor,");
482 warning (0, "-g option disabled");
483 write_symbols = NO_DEBUG;
486 /* We only support the "big PIC" model now. And we always generate PIC
487 code when in 64bit mode. */
488 if (flag_pic == 1 || TARGET_64BIT)
491 /* We can't guarantee that .dword is available for 32-bit targets. */
492 if (UNITS_PER_WORD == 4)
493 targetm.asm_out.aligned_op.di = NULL;
495 /* The unaligned ops are only available when using GAS. */
498 targetm.asm_out.unaligned_op.hi = NULL;
499 targetm.asm_out.unaligned_op.si = NULL;
500 targetm.asm_out.unaligned_op.di = NULL;
503 init_machine_status = pa_init_machine_status;
507 pa_init_builtins (void)
509 #ifdef DONT_HAVE_FPUTC_UNLOCKED
510 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] =
511 built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
512 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED]
513 = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
517 /* Function to init struct machine_function.
518 This will be called, via a pointer variable,
519 from push_function_context. */
521 static struct machine_function *
522 pa_init_machine_status (void)
524 return ggc_alloc_cleared (sizeof (machine_function));
527 /* If FROM is a probable pointer register, mark TO as a probable
528 pointer register with the same pointer alignment as FROM. */
531 copy_reg_pointer (rtx to, rtx from)
533 if (REG_POINTER (from))
534 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
537 /* Return 1 if X contains a symbolic expression. We know these
538 expressions will have one of a few well defined forms, so
539 we need only check those forms. */
541 symbolic_expression_p (rtx x)
544 /* Strip off any HIGH. */
545 if (GET_CODE (x) == HIGH)
548 return (symbolic_operand (x, VOIDmode));
551 /* Accept any constant that can be moved in one instruction into a
554 cint_ok_for_move (HOST_WIDE_INT intval)
556 /* OK if ldo, ldil, or zdepi, can be used. */
557 return (CONST_OK_FOR_LETTER_P (intval, 'J')
558 || CONST_OK_FOR_LETTER_P (intval, 'N')
559 || CONST_OK_FOR_LETTER_P (intval, 'K'));
562 /* Return truth value of whether OP can be used as an operand in a
565 adddi3_operand (rtx op, enum machine_mode mode)
567 return (register_operand (op, mode)
568 || (GET_CODE (op) == CONST_INT
569 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
572 /* True iff zdepi can be used to generate this CONST_INT.
573 zdepi first sign extends a 5 bit signed number to a given field
574 length, then places this field anywhere in a zero. */
576 zdepi_cint_p (unsigned HOST_WIDE_INT x)
578 unsigned HOST_WIDE_INT lsb_mask, t;
580 /* This might not be obvious, but it's at least fast.
581 This function is critical; we don't have the time loops would take. */
583 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
584 /* Return true iff t is a power of two. */
585 return ((t & (t - 1)) == 0);
588 /* True iff depi or extru can be used to compute (reg & mask).
589 Accept bit pattern like these:
594 and_mask_p (unsigned HOST_WIDE_INT mask)
597 mask += mask & -mask;
598 return (mask & (mask - 1)) == 0;
601 /* True iff depi can be used to compute (reg | MASK). */
603 ior_mask_p (unsigned HOST_WIDE_INT mask)
605 mask += mask & -mask;
606 return (mask & (mask - 1)) == 0;
609 /* Legitimize PIC addresses. If the address is already
610 position-independent, we return ORIG. Newly generated
611 position-independent addresses go to REG. If we need more
612 than one register, we lose. */
615 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
619 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
621 /* Labels need special handling. */
622 if (pic_label_operand (orig, mode))
624 /* We do not want to go through the movXX expanders here since that
625 would create recursion.
627 Nor do we really want to call a generator for a named pattern
628 since that requires multiple patterns if we want to support
631 So instead we just emit the raw set, which avoids the movXX
632 expanders completely. */
633 mark_reg_pointer (reg, BITS_PER_UNIT);
634 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
635 current_function_uses_pic_offset_table = 1;
638 if (GET_CODE (orig) == SYMBOL_REF)
644 /* Before reload, allocate a temporary register for the intermediate
645 result. This allows the sequence to be deleted when the final
646 result is unused and the insns are trivially dead. */
647 tmp_reg = ((reload_in_progress || reload_completed)
648 ? reg : gen_reg_rtx (Pmode));
650 emit_move_insn (tmp_reg,
651 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
652 gen_rtx_HIGH (word_mode, orig)));
654 = gen_const_mem (Pmode,
655 gen_rtx_LO_SUM (Pmode, tmp_reg,
656 gen_rtx_UNSPEC (Pmode,
660 current_function_uses_pic_offset_table = 1;
661 mark_reg_pointer (reg, BITS_PER_UNIT);
662 insn = emit_move_insn (reg, pic_ref);
664 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
665 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
669 else if (GET_CODE (orig) == CONST)
673 if (GET_CODE (XEXP (orig, 0)) == PLUS
674 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
678 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
680 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
681 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
682 base == reg ? 0 : reg);
684 if (GET_CODE (orig) == CONST_INT)
686 if (INT_14_BITS (orig))
687 return plus_constant (base, INTVAL (orig));
688 orig = force_reg (Pmode, orig);
690 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
691 /* Likewise, should we set special REG_NOTEs here? */
697 static GTY(()) rtx gen_tls_tga;
700 gen_tls_get_addr (void)
703 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
708 hppa_tls_call (rtx arg)
712 ret = gen_reg_rtx (Pmode);
713 emit_library_call_value (gen_tls_get_addr (), ret,
714 LCT_CONST, Pmode, 1, arg, Pmode);
720 legitimize_tls_address (rtx addr)
722 rtx ret, insn, tmp, t1, t2, tp;
723 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
727 case TLS_MODEL_GLOBAL_DYNAMIC:
728 tmp = gen_reg_rtx (Pmode);
729 emit_insn (gen_tgd_load (tmp, addr));
730 ret = hppa_tls_call (tmp);
733 case TLS_MODEL_LOCAL_DYNAMIC:
734 ret = gen_reg_rtx (Pmode);
735 tmp = gen_reg_rtx (Pmode);
737 emit_insn (gen_tld_load (tmp, addr));
738 t1 = hppa_tls_call (tmp);
741 t2 = gen_reg_rtx (Pmode);
742 emit_libcall_block (insn, t2, t1,
743 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
745 emit_insn (gen_tld_offset_load (ret, addr, t2));
748 case TLS_MODEL_INITIAL_EXEC:
749 tp = gen_reg_rtx (Pmode);
750 tmp = gen_reg_rtx (Pmode);
751 ret = gen_reg_rtx (Pmode);
752 emit_insn (gen_tp_load (tp));
753 emit_insn (gen_tie_load (tmp, addr));
754 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
757 case TLS_MODEL_LOCAL_EXEC:
758 tp = gen_reg_rtx (Pmode);
759 ret = gen_reg_rtx (Pmode);
760 emit_insn (gen_tp_load (tp));
761 emit_insn (gen_tle_load (ret, addr, tp));
771 /* Try machine-dependent ways of modifying an illegitimate address
772 to be legitimate. If we find one, return the new, valid address.
773 This macro is used in only one place: `memory_address' in explow.c.
775 OLDX is the address as it was before break_out_memory_refs was called.
776 In some cases it is useful to look at this to decide what needs to be done.
778 MODE and WIN are passed so that this macro can use
779 GO_IF_LEGITIMATE_ADDRESS.
781 It is always safe for this macro to do nothing. It exists to recognize
782 opportunities to optimize the output.
784 For the PA, transform:
786 memory(X + <large int>)
790 if (<large int> & mask) >= 16
791 Y = (<large int> & ~mask) + mask + 1 Round up.
793 Y = (<large int> & ~mask) Round down.
795 memory (Z + (<large int> - Y));
797 This is for CSE to find several similar references, and only use one Z.
799 X can either be a SYMBOL_REF or REG, but because combine cannot
800 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
801 D will not fit in 14 bits.
803 MODE_FLOAT references allow displacements which fit in 5 bits, so use
806 MODE_INT references allow displacements which fit in 14 bits, so use
809 This relies on the fact that most mode MODE_FLOAT references will use FP
810 registers and most mode MODE_INT references will use integer registers.
811 (In the rare case of an FP register used in an integer MODE, we depend
812 on secondary reloads to clean things up.)
815 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
816 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
817 addressing modes to be used).
819 Put X and Z into registers. Then put the entire expression into
823 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
824 enum machine_mode mode)
828 /* We need to canonicalize the order of operands in unscaled indexed
829 addresses since the code that checks if an address is valid doesn't
830 always try both orders. */
831 if (!TARGET_NO_SPACE_REGS
832 && GET_CODE (x) == PLUS
833 && GET_MODE (x) == Pmode
834 && REG_P (XEXP (x, 0))
835 && REG_P (XEXP (x, 1))
836 && REG_POINTER (XEXP (x, 0))
837 && !REG_POINTER (XEXP (x, 1)))
838 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
840 if (PA_SYMBOL_REF_TLS_P (x))
841 return legitimize_tls_address (x);
843 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
845 /* Strip off CONST. */
846 if (GET_CODE (x) == CONST)
849 /* Special case. Get the SYMBOL_REF into a register and use indexing.
850 That should always be safe. */
851 if (GET_CODE (x) == PLUS
852 && GET_CODE (XEXP (x, 0)) == REG
853 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
855 rtx reg = force_reg (Pmode, XEXP (x, 1));
856 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
859 /* Note we must reject symbols which represent function addresses
860 since the assembler/linker can't handle arithmetic on plabels. */
861 if (GET_CODE (x) == PLUS
862 && GET_CODE (XEXP (x, 1)) == CONST_INT
863 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
864 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
865 || GET_CODE (XEXP (x, 0)) == REG))
867 rtx int_part, ptr_reg;
869 int offset = INTVAL (XEXP (x, 1));
872 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
873 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
875 /* Choose which way to round the offset. Round up if we
876 are >= halfway to the next boundary. */
877 if ((offset & mask) >= ((mask + 1) / 2))
878 newoffset = (offset & ~ mask) + mask + 1;
880 newoffset = (offset & ~ mask);
882 /* If the newoffset will not fit in 14 bits (ldo), then
883 handling this would take 4 or 5 instructions (2 to load
884 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
885 add the new offset and the SYMBOL_REF.) Combine can
886 not handle 4->2 or 5->2 combinations, so do not create
888 if (! VAL_14_BITS_P (newoffset)
889 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
891 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
894 gen_rtx_HIGH (Pmode, const_part));
897 gen_rtx_LO_SUM (Pmode,
898 tmp_reg, const_part));
902 if (! VAL_14_BITS_P (newoffset))
903 int_part = force_reg (Pmode, GEN_INT (newoffset));
905 int_part = GEN_INT (newoffset);
907 ptr_reg = force_reg (Pmode,
909 force_reg (Pmode, XEXP (x, 0)),
912 return plus_constant (ptr_reg, offset - newoffset);
915 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
917 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
919 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
920 && (OBJECT_P (XEXP (x, 1))
921 || GET_CODE (XEXP (x, 1)) == SUBREG)
922 && GET_CODE (XEXP (x, 1)) != CONST)
924 int val = INTVAL (XEXP (XEXP (x, 0), 1));
928 if (GET_CODE (reg1) != REG)
929 reg1 = force_reg (Pmode, force_operand (reg1, 0));
931 reg2 = XEXP (XEXP (x, 0), 0);
932 if (GET_CODE (reg2) != REG)
933 reg2 = force_reg (Pmode, force_operand (reg2, 0));
935 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
942 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
944 Only do so for floating point modes since this is more speculative
945 and we lose if it's an integer store. */
946 if (GET_CODE (x) == PLUS
947 && GET_CODE (XEXP (x, 0)) == PLUS
948 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
949 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
950 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
951 && (mode == SFmode || mode == DFmode))
954 /* First, try and figure out what to use as a base register. */
955 rtx reg1, reg2, base, idx, orig_base;
957 reg1 = XEXP (XEXP (x, 0), 1);
962 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
963 then emit_move_sequence will turn on REG_POINTER so we'll know
964 it's a base register below. */
965 if (GET_CODE (reg1) != REG)
966 reg1 = force_reg (Pmode, force_operand (reg1, 0));
968 if (GET_CODE (reg2) != REG)
969 reg2 = force_reg (Pmode, force_operand (reg2, 0));
971 /* Figure out what the base and index are. */
973 if (GET_CODE (reg1) == REG
974 && REG_POINTER (reg1))
977 orig_base = XEXP (XEXP (x, 0), 1);
978 idx = gen_rtx_PLUS (Pmode,
980 XEXP (XEXP (XEXP (x, 0), 0), 0),
981 XEXP (XEXP (XEXP (x, 0), 0), 1)),
984 else if (GET_CODE (reg2) == REG
985 && REG_POINTER (reg2))
988 orig_base = XEXP (x, 1);
995 /* If the index adds a large constant, try to scale the
996 constant so that it can be loaded with only one insn. */
997 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
998 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
999 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1000 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1002 /* Divide the CONST_INT by the scale factor, then add it to A. */
1003 int val = INTVAL (XEXP (idx, 1));
1005 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1006 reg1 = XEXP (XEXP (idx, 0), 0);
1007 if (GET_CODE (reg1) != REG)
1008 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1010 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1012 /* We can now generate a simple scaled indexed address. */
1015 (Pmode, gen_rtx_PLUS (Pmode,
1016 gen_rtx_MULT (Pmode, reg1,
1017 XEXP (XEXP (idx, 0), 1)),
1021 /* If B + C is still a valid base register, then add them. */
1022 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1023 && INTVAL (XEXP (idx, 1)) <= 4096
1024 && INTVAL (XEXP (idx, 1)) >= -4096)
1026 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1029 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1031 reg2 = XEXP (XEXP (idx, 0), 0);
1032 if (GET_CODE (reg2) != CONST_INT)
1033 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1035 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1036 gen_rtx_MULT (Pmode,
1042 /* Get the index into a register, then add the base + index and
1043 return a register holding the result. */
1045 /* First get A into a register. */
1046 reg1 = XEXP (XEXP (idx, 0), 0);
1047 if (GET_CODE (reg1) != REG)
1048 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1050 /* And get B into a register. */
1051 reg2 = XEXP (idx, 1);
1052 if (GET_CODE (reg2) != REG)
1053 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1055 reg1 = force_reg (Pmode,
1056 gen_rtx_PLUS (Pmode,
1057 gen_rtx_MULT (Pmode, reg1,
1058 XEXP (XEXP (idx, 0), 1)),
1061 /* Add the result to our base register and return. */
1062 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1066 /* Uh-oh. We might have an address for x[n-100000]. This needs
1067 special handling to avoid creating an indexed memory address
1068 with x-100000 as the base.
1070 If the constant part is small enough, then it's still safe because
1071 there is a guard page at the beginning and end of the data segment.
1073 Scaled references are common enough that we want to try and rearrange the
1074 terms so that we can use indexing for these addresses too. Only
1075 do the optimization for floatint point modes. */
1077 if (GET_CODE (x) == PLUS
1078 && symbolic_expression_p (XEXP (x, 1)))
1080 /* Ugly. We modify things here so that the address offset specified
1081 by the index expression is computed first, then added to x to form
1082 the entire address. */
1084 rtx regx1, regx2, regy1, regy2, y;
1086 /* Strip off any CONST. */
1088 if (GET_CODE (y) == CONST)
1091 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1093 /* See if this looks like
1094 (plus (mult (reg) (shadd_const))
1095 (const (plus (symbol_ref) (const_int))))
1097 Where const_int is small. In that case the const
1098 expression is a valid pointer for indexing.
1100 If const_int is big, but can be divided evenly by shadd_const
1101 and added to (reg). This allows more scaled indexed addresses. */
1102 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1103 && GET_CODE (XEXP (x, 0)) == MULT
1104 && GET_CODE (XEXP (y, 1)) == CONST_INT
1105 && INTVAL (XEXP (y, 1)) >= -4096
1106 && INTVAL (XEXP (y, 1)) <= 4095
1107 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1108 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1110 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1114 if (GET_CODE (reg1) != REG)
1115 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1117 reg2 = XEXP (XEXP (x, 0), 0);
1118 if (GET_CODE (reg2) != REG)
1119 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1121 return force_reg (Pmode,
1122 gen_rtx_PLUS (Pmode,
1123 gen_rtx_MULT (Pmode,
1128 else if ((mode == DFmode || mode == SFmode)
1129 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1130 && GET_CODE (XEXP (x, 0)) == MULT
1131 && GET_CODE (XEXP (y, 1)) == CONST_INT
1132 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1133 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1134 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1137 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1138 / INTVAL (XEXP (XEXP (x, 0), 1))));
1139 regx2 = XEXP (XEXP (x, 0), 0);
1140 if (GET_CODE (regx2) != REG)
1141 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1142 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1146 gen_rtx_PLUS (Pmode,
1147 gen_rtx_MULT (Pmode, regx2,
1148 XEXP (XEXP (x, 0), 1)),
1149 force_reg (Pmode, XEXP (y, 0))));
1151 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1152 && INTVAL (XEXP (y, 1)) >= -4096
1153 && INTVAL (XEXP (y, 1)) <= 4095)
1155 /* This is safe because of the guard page at the
1156 beginning and end of the data space. Just
1157 return the original address. */
1162 /* Doesn't look like one we can optimize. */
1163 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1164 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1165 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1166 regx1 = force_reg (Pmode,
1167 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1169 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1177 /* For the HPPA, REG and REG+CONST is cost 0
1178 and addresses involving symbolic constants are cost 2.
1180 PIC addresses are very expensive.
1182 It is no coincidence that this has the same structure
1183 as GO_IF_LEGITIMATE_ADDRESS. */
1186 hppa_address_cost (rtx X)
1188 switch (GET_CODE (X))
1201 /* Compute a (partial) cost for rtx X. Return true if the complete
1202 cost has been computed, and false if subexpressions should be
1203 scanned. In either case, *TOTAL contains the cost result. */
1206 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1211 if (INTVAL (x) == 0)
1213 else if (INT_14_BITS (x))
1230 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1231 && outer_code != SET)
1238 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1239 *total = COSTS_N_INSNS (3);
1240 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1241 *total = COSTS_N_INSNS (8);
1243 *total = COSTS_N_INSNS (20);
1247 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1249 *total = COSTS_N_INSNS (14);
1257 *total = COSTS_N_INSNS (60);
1260 case PLUS: /* this includes shNadd insns */
1262 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1263 *total = COSTS_N_INSNS (3);
1265 *total = COSTS_N_INSNS (1);
1271 *total = COSTS_N_INSNS (1);
1279 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1280 new rtx with the correct mode. */
1282 force_mode (enum machine_mode mode, rtx orig)
1284 if (mode == GET_MODE (orig))
1287 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1289 return gen_rtx_REG (mode, REGNO (orig));
1292 /* Return 1 if *X is a thread-local symbol. */
1295 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1297 return PA_SYMBOL_REF_TLS_P (*x);
1300 /* Return 1 if X contains a thread-local symbol. */
1303 pa_tls_referenced_p (rtx x)
1305 if (!TARGET_HAVE_TLS)
1308 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1311 /* Emit insns to move operands[1] into operands[0].
1313 Return 1 if we have written out everything that needs to be done to
1314 do the move. Otherwise, return 0 and the caller will emit the move
1317 Note SCRATCH_REG may not be in the proper mode depending on how it
1318 will be used. This routine is responsible for creating a new copy
1319 of SCRATCH_REG in the proper mode. */
1322 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1324 register rtx operand0 = operands[0];
1325 register rtx operand1 = operands[1];
1328 /* We can only handle indexed addresses in the destination operand
1329 of floating point stores. Thus, we need to break out indexed
1330 addresses from the destination operand. */
1331 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1333 /* This is only safe up to the beginning of life analysis. */
1334 gcc_assert (!no_new_pseudos);
1336 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1337 operand0 = replace_equiv_address (operand0, tem);
1340 /* On targets with non-equivalent space registers, break out unscaled
1341 indexed addresses from the source operand before the final CSE.
1342 We have to do this because the REG_POINTER flag is not correctly
1343 carried through various optimization passes and CSE may substitute
1344 a pseudo without the pointer set for one with the pointer set. As
1345 a result, we loose various opportunities to create insns with
1346 unscaled indexed addresses. */
1347 if (!TARGET_NO_SPACE_REGS
1348 && !cse_not_expected
1349 && GET_CODE (operand1) == MEM
1350 && GET_CODE (XEXP (operand1, 0)) == PLUS
1351 && REG_P (XEXP (XEXP (operand1, 0), 0))
1352 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1354 = replace_equiv_address (operand1,
1355 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1358 && reload_in_progress && GET_CODE (operand0) == REG
1359 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1360 operand0 = reg_equiv_mem[REGNO (operand0)];
1361 else if (scratch_reg
1362 && reload_in_progress && GET_CODE (operand0) == SUBREG
1363 && GET_CODE (SUBREG_REG (operand0)) == REG
1364 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1366 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1367 the code which tracks sets/uses for delete_output_reload. */
1368 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1369 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1370 SUBREG_BYTE (operand0));
1371 operand0 = alter_subreg (&temp);
1375 && reload_in_progress && GET_CODE (operand1) == REG
1376 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1377 operand1 = reg_equiv_mem[REGNO (operand1)];
1378 else if (scratch_reg
1379 && reload_in_progress && GET_CODE (operand1) == SUBREG
1380 && GET_CODE (SUBREG_REG (operand1)) == REG
1381 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1383 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1384 the code which tracks sets/uses for delete_output_reload. */
1385 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1386 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1387 SUBREG_BYTE (operand1));
1388 operand1 = alter_subreg (&temp);
1391 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1392 && ((tem = find_replacement (&XEXP (operand0, 0)))
1393 != XEXP (operand0, 0)))
1394 operand0 = replace_equiv_address (operand0, tem);
1396 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1397 && ((tem = find_replacement (&XEXP (operand1, 0)))
1398 != XEXP (operand1, 0)))
1399 operand1 = replace_equiv_address (operand1, tem);
1401 /* Handle secondary reloads for loads/stores of FP registers from
1402 REG+D addresses where D does not fit in 5 or 14 bits, including
1403 (subreg (mem (addr))) cases. */
1405 && fp_reg_operand (operand0, mode)
1406 && ((GET_CODE (operand1) == MEM
1407 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1408 XEXP (operand1, 0)))
1409 || ((GET_CODE (operand1) == SUBREG
1410 && GET_CODE (XEXP (operand1, 0)) == MEM
1411 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1413 XEXP (XEXP (operand1, 0), 0))))))
1415 if (GET_CODE (operand1) == SUBREG)
1416 operand1 = XEXP (operand1, 0);
1418 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1419 it in WORD_MODE regardless of what mode it was originally given
1421 scratch_reg = force_mode (word_mode, scratch_reg);
1423 /* D might not fit in 14 bits either; for such cases load D into
1425 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1427 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1428 emit_move_insn (scratch_reg,
1429 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1431 XEXP (XEXP (operand1, 0), 0),
1435 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1436 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1437 replace_equiv_address (operand1, scratch_reg)));
1440 else if (scratch_reg
1441 && fp_reg_operand (operand1, mode)
1442 && ((GET_CODE (operand0) == MEM
1443 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1445 XEXP (operand0, 0)))
1446 || ((GET_CODE (operand0) == SUBREG)
1447 && GET_CODE (XEXP (operand0, 0)) == MEM
1448 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1450 XEXP (XEXP (operand0, 0), 0)))))
1452 if (GET_CODE (operand0) == SUBREG)
1453 operand0 = XEXP (operand0, 0);
1455 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1456 it in WORD_MODE regardless of what mode it was originally given
1458 scratch_reg = force_mode (word_mode, scratch_reg);
1460 /* D might not fit in 14 bits either; for such cases load D into
1462 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1464 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1465 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1468 XEXP (XEXP (operand0, 0),
1473 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1474 emit_insn (gen_rtx_SET (VOIDmode,
1475 replace_equiv_address (operand0, scratch_reg),
1479 /* Handle secondary reloads for loads of FP registers from constant
1480 expressions by forcing the constant into memory.
1482 Use scratch_reg to hold the address of the memory location.
1484 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1485 NO_REGS when presented with a const_int and a register class
1486 containing only FP registers. Doing so unfortunately creates
1487 more problems than it solves. Fix this for 2.5. */
1488 else if (scratch_reg
1489 && CONSTANT_P (operand1)
1490 && fp_reg_operand (operand0, mode))
1492 rtx const_mem, xoperands[2];
1494 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1495 it in WORD_MODE regardless of what mode it was originally given
1497 scratch_reg = force_mode (word_mode, scratch_reg);
1499 /* Force the constant into memory and put the address of the
1500 memory location into scratch_reg. */
1501 const_mem = force_const_mem (mode, operand1);
1502 xoperands[0] = scratch_reg;
1503 xoperands[1] = XEXP (const_mem, 0);
1504 emit_move_sequence (xoperands, Pmode, 0);
1506 /* Now load the destination register. */
1507 emit_insn (gen_rtx_SET (mode, operand0,
1508 replace_equiv_address (const_mem, scratch_reg)));
1511 /* Handle secondary reloads for SAR. These occur when trying to load
1512 the SAR from memory, FP register, or with a constant. */
1513 else if (scratch_reg
1514 && GET_CODE (operand0) == REG
1515 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1516 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1517 && (GET_CODE (operand1) == MEM
1518 || GET_CODE (operand1) == CONST_INT
1519 || (GET_CODE (operand1) == REG
1520 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1522 /* D might not fit in 14 bits either; for such cases load D into
1524 if (GET_CODE (operand1) == MEM
1525 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1527 /* We are reloading the address into the scratch register, so we
1528 want to make sure the scratch register is a full register. */
1529 scratch_reg = force_mode (word_mode, scratch_reg);
1531 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1532 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1535 XEXP (XEXP (operand1, 0),
1539 /* Now we are going to load the scratch register from memory,
1540 we want to load it in the same width as the original MEM,
1541 which must be the same as the width of the ultimate destination,
1543 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1545 emit_move_insn (scratch_reg,
1546 replace_equiv_address (operand1, scratch_reg));
1550 /* We want to load the scratch register using the same mode as
1551 the ultimate destination. */
1552 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1554 emit_move_insn (scratch_reg, operand1);
1557 /* And emit the insn to set the ultimate destination. We know that
1558 the scratch register has the same mode as the destination at this
1560 emit_move_insn (operand0, scratch_reg);
1563 /* Handle the most common case: storing into a register. */
1564 else if (register_operand (operand0, mode))
1566 if (register_operand (operand1, mode)
1567 || (GET_CODE (operand1) == CONST_INT
1568 && cint_ok_for_move (INTVAL (operand1)))
1569 || (operand1 == CONST0_RTX (mode))
1570 || (GET_CODE (operand1) == HIGH
1571 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1572 /* Only `general_operands' can come here, so MEM is ok. */
1573 || GET_CODE (operand1) == MEM)
1575 /* Various sets are created during RTL generation which don't
1576 have the REG_POINTER flag correctly set. After the CSE pass,
1577 instruction recognition can fail if we don't consistently
1578 set this flag when performing register copies. This should
1579 also improve the opportunities for creating insns that use
1580 unscaled indexing. */
1581 if (REG_P (operand0) && REG_P (operand1))
1583 if (REG_POINTER (operand1)
1584 && !REG_POINTER (operand0)
1585 && !HARD_REGISTER_P (operand0))
1586 copy_reg_pointer (operand0, operand1);
1587 else if (REG_POINTER (operand0)
1588 && !REG_POINTER (operand1)
1589 && !HARD_REGISTER_P (operand1))
1590 copy_reg_pointer (operand1, operand0);
1593 /* When MEMs are broken out, the REG_POINTER flag doesn't
1594 get set. In some cases, we can set the REG_POINTER flag
1595 from the declaration for the MEM. */
1596 if (REG_P (operand0)
1597 && GET_CODE (operand1) == MEM
1598 && !REG_POINTER (operand0))
1600 tree decl = MEM_EXPR (operand1);
1602 /* Set the register pointer flag and register alignment
1603 if the declaration for this memory reference is a
1604 pointer type. Fortran indirect argument references
1607 && !(flag_argument_noalias > 1
1608 && TREE_CODE (decl) == INDIRECT_REF
1609 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1613 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1615 if (TREE_CODE (decl) == COMPONENT_REF)
1616 decl = TREE_OPERAND (decl, 1);
1618 type = TREE_TYPE (decl);
1619 if (TREE_CODE (type) == ARRAY_TYPE)
1620 type = get_inner_array_type (type);
1622 if (POINTER_TYPE_P (type))
1626 type = TREE_TYPE (type);
1627 /* Using TYPE_ALIGN_OK is rather conservative as
1628 only the ada frontend actually sets it. */
1629 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1631 mark_reg_pointer (operand0, align);
1636 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1640 else if (GET_CODE (operand0) == MEM)
1642 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1643 && !(reload_in_progress || reload_completed))
1645 rtx temp = gen_reg_rtx (DFmode);
1647 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1648 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1651 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1653 /* Run this case quickly. */
1654 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1657 if (! (reload_in_progress || reload_completed))
1659 operands[0] = validize_mem (operand0);
1660 operands[1] = operand1 = force_reg (mode, operand1);
1664 /* Simplify the source if we need to.
1665 Note we do have to handle function labels here, even though we do
1666 not consider them legitimate constants. Loop optimizations can
1667 call the emit_move_xxx with one as a source. */
1668 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1669 || function_label_operand (operand1, mode)
1670 || (GET_CODE (operand1) == HIGH
1671 && symbolic_operand (XEXP (operand1, 0), mode)))
1675 if (GET_CODE (operand1) == HIGH)
1678 operand1 = XEXP (operand1, 0);
1680 if (symbolic_operand (operand1, mode))
1682 /* Argh. The assembler and linker can't handle arithmetic
1685 So we force the plabel into memory, load operand0 from
1686 the memory location, then add in the constant part. */
1687 if ((GET_CODE (operand1) == CONST
1688 && GET_CODE (XEXP (operand1, 0)) == PLUS
1689 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1690 || function_label_operand (operand1, mode))
1692 rtx temp, const_part;
1694 /* Figure out what (if any) scratch register to use. */
1695 if (reload_in_progress || reload_completed)
1697 scratch_reg = scratch_reg ? scratch_reg : operand0;
1698 /* SCRATCH_REG will hold an address and maybe the actual
1699 data. We want it in WORD_MODE regardless of what mode it
1700 was originally given to us. */
1701 scratch_reg = force_mode (word_mode, scratch_reg);
1704 scratch_reg = gen_reg_rtx (Pmode);
1706 if (GET_CODE (operand1) == CONST)
1708 /* Save away the constant part of the expression. */
1709 const_part = XEXP (XEXP (operand1, 0), 1);
1710 gcc_assert (GET_CODE (const_part) == CONST_INT);
1712 /* Force the function label into memory. */
1713 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1717 /* No constant part. */
1718 const_part = NULL_RTX;
1720 /* Force the function label into memory. */
1721 temp = force_const_mem (mode, operand1);
1725 /* Get the address of the memory location. PIC-ify it if
1727 temp = XEXP (temp, 0);
1729 temp = legitimize_pic_address (temp, mode, scratch_reg);
1731 /* Put the address of the memory location into our destination
1734 emit_move_sequence (operands, mode, scratch_reg);
1736 /* Now load from the memory location into our destination
1738 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1739 emit_move_sequence (operands, mode, scratch_reg);
1741 /* And add back in the constant part. */
1742 if (const_part != NULL_RTX)
1743 expand_inc (operand0, const_part);
1752 if (reload_in_progress || reload_completed)
1754 temp = scratch_reg ? scratch_reg : operand0;
1755 /* TEMP will hold an address and maybe the actual
1756 data. We want it in WORD_MODE regardless of what mode it
1757 was originally given to us. */
1758 temp = force_mode (word_mode, temp);
1761 temp = gen_reg_rtx (Pmode);
1763 /* (const (plus (symbol) (const_int))) must be forced to
1764 memory during/after reload if the const_int will not fit
1766 if (GET_CODE (operand1) == CONST
1767 && GET_CODE (XEXP (operand1, 0)) == PLUS
1768 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1769 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1770 && (reload_completed || reload_in_progress)
1773 rtx const_mem = force_const_mem (mode, operand1);
1774 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1776 operands[1] = replace_equiv_address (const_mem, operands[1]);
1777 emit_move_sequence (operands, mode, temp);
1781 operands[1] = legitimize_pic_address (operand1, mode, temp);
1782 if (REG_P (operand0) && REG_P (operands[1]))
1783 copy_reg_pointer (operand0, operands[1]);
1784 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1787 /* On the HPPA, references to data space are supposed to use dp,
1788 register 27, but showing it in the RTL inhibits various cse
1789 and loop optimizations. */
1794 if (reload_in_progress || reload_completed)
1796 temp = scratch_reg ? scratch_reg : operand0;
1797 /* TEMP will hold an address and maybe the actual
1798 data. We want it in WORD_MODE regardless of what mode it
1799 was originally given to us. */
1800 temp = force_mode (word_mode, temp);
1803 temp = gen_reg_rtx (mode);
1805 /* Loading a SYMBOL_REF into a register makes that register
1806 safe to be used as the base in an indexed address.
1808 Don't mark hard registers though. That loses. */
1809 if (GET_CODE (operand0) == REG
1810 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1811 mark_reg_pointer (operand0, BITS_PER_UNIT);
1812 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1813 mark_reg_pointer (temp, BITS_PER_UNIT);
1816 set = gen_rtx_SET (mode, operand0, temp);
1818 set = gen_rtx_SET (VOIDmode,
1820 gen_rtx_LO_SUM (mode, temp, operand1));
1822 emit_insn (gen_rtx_SET (VOIDmode,
1824 gen_rtx_HIGH (mode, operand1)));
1830 else if (pa_tls_referenced_p (operand1))
1835 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
1837 addend = XEXP (XEXP (tmp, 0), 1);
1838 tmp = XEXP (XEXP (tmp, 0), 0);
1841 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
1842 tmp = legitimize_tls_address (tmp);
1845 tmp = gen_rtx_PLUS (mode, tmp, addend);
1846 tmp = force_operand (tmp, operands[0]);
1850 else if (GET_CODE (operand1) != CONST_INT
1851 || !cint_ok_for_move (INTVAL (operand1)))
1855 HOST_WIDE_INT value = 0;
1856 HOST_WIDE_INT insv = 0;
1859 if (GET_CODE (operand1) == CONST_INT)
1860 value = INTVAL (operand1);
1863 && GET_CODE (operand1) == CONST_INT
1864 && HOST_BITS_PER_WIDE_INT > 32
1865 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1869 /* Extract the low order 32 bits of the value and sign extend.
1870 If the new value is the same as the original value, we can
1871 can use the original value as-is. If the new value is
1872 different, we use it and insert the most-significant 32-bits
1873 of the original value into the final result. */
1874 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1875 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1878 #if HOST_BITS_PER_WIDE_INT > 32
1879 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1883 operand1 = GEN_INT (nval);
1887 if (reload_in_progress || reload_completed)
1888 temp = scratch_reg ? scratch_reg : operand0;
1890 temp = gen_reg_rtx (mode);
1892 /* We don't directly split DImode constants on 32-bit targets
1893 because PLUS uses an 11-bit immediate and the insn sequence
1894 generated is not as efficient as the one using HIGH/LO_SUM. */
1895 if (GET_CODE (operand1) == CONST_INT
1896 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
1897 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1900 /* Directly break constant into high and low parts. This
1901 provides better optimization opportunities because various
1902 passes recognize constants split with PLUS but not LO_SUM.
1903 We use a 14-bit signed low part except when the addition
1904 of 0x4000 to the high part might change the sign of the
1906 HOST_WIDE_INT low = value & 0x3fff;
1907 HOST_WIDE_INT high = value & ~ 0x3fff;
1911 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1919 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1920 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1924 emit_insn (gen_rtx_SET (VOIDmode, temp,
1925 gen_rtx_HIGH (mode, operand1)));
1926 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1929 insn = emit_move_insn (operands[0], operands[1]);
1931 /* Now insert the most significant 32 bits of the value
1932 into the register. When we don't have a second register
1933 available, it could take up to nine instructions to load
1934 a 64-bit integer constant. Prior to reload, we force
1935 constants that would take more than three instructions
1936 to load to the constant pool. During and after reload,
1937 we have to handle all possible values. */
1940 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
1941 register and the value to be inserted is outside the
1942 range that can be loaded with three depdi instructions. */
1943 if (temp != operand0 && (insv >= 16384 || insv < -16384))
1945 operand1 = GEN_INT (insv);
1947 emit_insn (gen_rtx_SET (VOIDmode, temp,
1948 gen_rtx_HIGH (mode, operand1)));
1949 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
1950 emit_insn (gen_insv (operand0, GEN_INT (32),
1955 int len = 5, pos = 27;
1957 /* Insert the bits using the depdi instruction. */
1960 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
1961 HOST_WIDE_INT sign = v5 < 0;
1963 /* Left extend the insertion. */
1964 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
1965 while (pos > 0 && (insv & 1) == sign)
1967 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
1972 emit_insn (gen_insv (operand0, GEN_INT (len),
1973 GEN_INT (pos), GEN_INT (v5)));
1975 len = pos > 0 && pos < 5 ? pos : 5;
1982 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
1987 /* Now have insn-emit do whatever it normally does. */
1991 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1992 it will need a link/runtime reloc). */
1995 reloc_needed (tree exp)
1999 switch (TREE_CODE (exp))
2006 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2007 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2012 case NON_LVALUE_EXPR:
2013 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2019 unsigned HOST_WIDE_INT ix;
2021 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2023 reloc |= reloc_needed (value);
2036 /* Does operand (which is a symbolic_operand) live in text space?
2037 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2041 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2043 if (GET_CODE (operand) == CONST)
2044 operand = XEXP (XEXP (operand, 0), 0);
2047 if (GET_CODE (operand) == SYMBOL_REF)
2048 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2052 if (GET_CODE (operand) == SYMBOL_REF)
2053 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2059 /* Return the best assembler insn template
2060 for moving operands[1] into operands[0] as a fullword. */
2062 singlemove_string (rtx *operands)
2064 HOST_WIDE_INT intval;
2066 if (GET_CODE (operands[0]) == MEM)
2067 return "stw %r1,%0";
2068 if (GET_CODE (operands[1]) == MEM)
2070 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2075 gcc_assert (GET_MODE (operands[1]) == SFmode);
2077 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2079 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2080 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2082 operands[1] = GEN_INT (i);
2083 /* Fall through to CONST_INT case. */
2085 if (GET_CODE (operands[1]) == CONST_INT)
2087 intval = INTVAL (operands[1]);
2089 if (VAL_14_BITS_P (intval))
2091 else if ((intval & 0x7ff) == 0)
2092 return "ldil L'%1,%0";
2093 else if (zdepi_cint_p (intval))
2094 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2096 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2098 return "copy %1,%0";
2102 /* Compute position (in OP[1]) and width (in OP[2])
2103 useful for copying IMM to a register using the zdepi
2104 instructions. Store the immediate value to insert in OP[0]. */
2106 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2110 /* Find the least significant set bit in IMM. */
2111 for (lsb = 0; lsb < 32; lsb++)
2118 /* Choose variants based on *sign* of the 5-bit field. */
2119 if ((imm & 0x10) == 0)
2120 len = (lsb <= 28) ? 4 : 32 - lsb;
2123 /* Find the width of the bitstring in IMM. */
2124 for (len = 5; len < 32; len++)
2126 if ((imm & (1 << len)) == 0)
2130 /* Sign extend IMM as a 5-bit value. */
2131 imm = (imm & 0xf) - 0x10;
2139 /* Compute position (in OP[1]) and width (in OP[2])
2140 useful for copying IMM to a register using the depdi,z
2141 instructions. Store the immediate value to insert in OP[0]. */
2143 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2145 HOST_WIDE_INT lsb, len;
2147 /* Find the least significant set bit in IMM. */
2148 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2155 /* Choose variants based on *sign* of the 5-bit field. */
2156 if ((imm & 0x10) == 0)
2157 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2158 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2161 /* Find the width of the bitstring in IMM. */
2162 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2164 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2168 /* Sign extend IMM as a 5-bit value. */
2169 imm = (imm & 0xf) - 0x10;
2177 /* Output assembler code to perform a doubleword move insn
2178 with operands OPERANDS. */
2181 output_move_double (rtx *operands)
2183 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2185 rtx addreg0 = 0, addreg1 = 0;
2187 /* First classify both operands. */
2189 if (REG_P (operands[0]))
2191 else if (offsettable_memref_p (operands[0]))
2193 else if (GET_CODE (operands[0]) == MEM)
2198 if (REG_P (operands[1]))
2200 else if (CONSTANT_P (operands[1]))
2202 else if (offsettable_memref_p (operands[1]))
2204 else if (GET_CODE (operands[1]) == MEM)
2209 /* Check for the cases that the operand constraints are not
2210 supposed to allow to happen. */
2211 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2213 /* Handle copies between general and floating registers. */
2215 if (optype0 == REGOP && optype1 == REGOP
2216 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2218 if (FP_REG_P (operands[0]))
2220 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2221 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2222 return "{fldds|fldd} -16(%%sp),%0";
2226 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2227 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2228 return "{ldws|ldw} -12(%%sp),%R0";
2232 /* Handle auto decrementing and incrementing loads and stores
2233 specifically, since the structure of the function doesn't work
2234 for them without major modification. Do it better when we learn
2235 this port about the general inc/dec addressing of PA.
2236 (This was written by tege. Chide him if it doesn't work.) */
2238 if (optype0 == MEMOP)
2240 /* We have to output the address syntax ourselves, since print_operand
2241 doesn't deal with the addresses we want to use. Fix this later. */
2243 rtx addr = XEXP (operands[0], 0);
2244 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2246 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2248 operands[0] = XEXP (addr, 0);
2249 gcc_assert (GET_CODE (operands[1]) == REG
2250 && GET_CODE (operands[0]) == REG);
2252 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2254 /* No overlap between high target register and address
2255 register. (We do this in a non-obvious way to
2256 save a register file writeback) */
2257 if (GET_CODE (addr) == POST_INC)
2258 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2259 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2261 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2263 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2265 operands[0] = XEXP (addr, 0);
2266 gcc_assert (GET_CODE (operands[1]) == REG
2267 && GET_CODE (operands[0]) == REG);
2269 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2270 /* No overlap between high target register and address
2271 register. (We do this in a non-obvious way to save a
2272 register file writeback) */
2273 if (GET_CODE (addr) == PRE_INC)
2274 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2275 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2278 if (optype1 == MEMOP)
2280 /* We have to output the address syntax ourselves, since print_operand
2281 doesn't deal with the addresses we want to use. Fix this later. */
2283 rtx addr = XEXP (operands[1], 0);
2284 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2286 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2288 operands[1] = XEXP (addr, 0);
2289 gcc_assert (GET_CODE (operands[0]) == REG
2290 && GET_CODE (operands[1]) == REG);
2292 if (!reg_overlap_mentioned_p (high_reg, addr))
2294 /* No overlap between high target register and address
2295 register. (We do this in a non-obvious way to
2296 save a register file writeback) */
2297 if (GET_CODE (addr) == POST_INC)
2298 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2299 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2303 /* This is an undefined situation. We should load into the
2304 address register *and* update that register. Probably
2305 we don't need to handle this at all. */
2306 if (GET_CODE (addr) == POST_INC)
2307 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2308 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2311 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2313 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2315 operands[1] = XEXP (addr, 0);
2316 gcc_assert (GET_CODE (operands[0]) == REG
2317 && GET_CODE (operands[1]) == REG);
2319 if (!reg_overlap_mentioned_p (high_reg, addr))
2321 /* No overlap between high target register and address
2322 register. (We do this in a non-obvious way to
2323 save a register file writeback) */
2324 if (GET_CODE (addr) == PRE_INC)
2325 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2326 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2330 /* This is an undefined situation. We should load into the
2331 address register *and* update that register. Probably
2332 we don't need to handle this at all. */
2333 if (GET_CODE (addr) == PRE_INC)
2334 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2335 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2338 else if (GET_CODE (addr) == PLUS
2339 && GET_CODE (XEXP (addr, 0)) == MULT)
2341 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2343 if (!reg_overlap_mentioned_p (high_reg, addr))
2347 xoperands[0] = high_reg;
2348 xoperands[1] = XEXP (addr, 1);
2349 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2350 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2351 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2353 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2359 xoperands[0] = high_reg;
2360 xoperands[1] = XEXP (addr, 1);
2361 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2362 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2363 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2365 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2370 /* If an operand is an unoffsettable memory ref, find a register
2371 we can increment temporarily to make it refer to the second word. */
2373 if (optype0 == MEMOP)
2374 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2376 if (optype1 == MEMOP)
2377 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2379 /* Ok, we can do one word at a time.
2380 Normally we do the low-numbered word first.
2382 In either case, set up in LATEHALF the operands to use
2383 for the high-numbered word and in some cases alter the
2384 operands in OPERANDS to be suitable for the low-numbered word. */
2386 if (optype0 == REGOP)
2387 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2388 else if (optype0 == OFFSOP)
2389 latehalf[0] = adjust_address (operands[0], SImode, 4);
2391 latehalf[0] = operands[0];
2393 if (optype1 == REGOP)
2394 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2395 else if (optype1 == OFFSOP)
2396 latehalf[1] = adjust_address (operands[1], SImode, 4);
2397 else if (optype1 == CNSTOP)
2398 split_double (operands[1], &operands[1], &latehalf[1]);
2400 latehalf[1] = operands[1];
2402 /* If the first move would clobber the source of the second one,
2403 do them in the other order.
2405 This can happen in two cases:
2407 mem -> register where the first half of the destination register
2408 is the same register used in the memory's address. Reload
2409 can create such insns.
2411 mem in this case will be either register indirect or register
2412 indirect plus a valid offset.
2414 register -> register move where REGNO(dst) == REGNO(src + 1)
2415 someone (Tim/Tege?) claimed this can happen for parameter loads.
2417 Handle mem -> register case first. */
2418 if (optype0 == REGOP
2419 && (optype1 == MEMOP || optype1 == OFFSOP)
2420 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2423 /* Do the late half first. */
2425 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2426 output_asm_insn (singlemove_string (latehalf), latehalf);
2430 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2431 return singlemove_string (operands);
2434 /* Now handle register -> register case. */
2435 if (optype0 == REGOP && optype1 == REGOP
2436 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2438 output_asm_insn (singlemove_string (latehalf), latehalf);
2439 return singlemove_string (operands);
2442 /* Normal case: do the two words, low-numbered first. */
2444 output_asm_insn (singlemove_string (operands), operands);
2446 /* Make any unoffsettable addresses point at high-numbered word. */
2448 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2450 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2453 output_asm_insn (singlemove_string (latehalf), latehalf);
2455 /* Undo the adds we just did. */
2457 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2459 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2465 output_fp_move_double (rtx *operands)
2467 if (FP_REG_P (operands[0]))
2469 if (FP_REG_P (operands[1])
2470 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2471 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2473 output_asm_insn ("fldd%F1 %1,%0", operands);
2475 else if (FP_REG_P (operands[1]))
2477 output_asm_insn ("fstd%F0 %1,%0", operands);
2483 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2485 /* This is a pain. You have to be prepared to deal with an
2486 arbitrary address here including pre/post increment/decrement.
2488 so avoid this in the MD. */
2489 gcc_assert (GET_CODE (operands[0]) == REG);
2491 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2492 xoperands[0] = operands[0];
2493 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2498 /* Return a REG that occurs in ADDR with coefficient 1.
2499 ADDR can be effectively incremented by incrementing REG. */
2502 find_addr_reg (rtx addr)
2504 while (GET_CODE (addr) == PLUS)
2506 if (GET_CODE (XEXP (addr, 0)) == REG)
2507 addr = XEXP (addr, 0);
2508 else if (GET_CODE (XEXP (addr, 1)) == REG)
2509 addr = XEXP (addr, 1);
2510 else if (CONSTANT_P (XEXP (addr, 0)))
2511 addr = XEXP (addr, 1);
2512 else if (CONSTANT_P (XEXP (addr, 1)))
2513 addr = XEXP (addr, 0);
2517 gcc_assert (GET_CODE (addr) == REG);
2521 /* Emit code to perform a block move.
2523 OPERANDS[0] is the destination pointer as a REG, clobbered.
2524 OPERANDS[1] is the source pointer as a REG, clobbered.
2525 OPERANDS[2] is a register for temporary storage.
2526 OPERANDS[3] is a register for temporary storage.
2527 OPERANDS[4] is the size as a CONST_INT
2528 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2529 OPERANDS[6] is another temporary register. */
2532 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2534 int align = INTVAL (operands[5]);
2535 unsigned long n_bytes = INTVAL (operands[4]);
2537 /* We can't move more than a word at a time because the PA
2538 has no longer integer move insns. (Could use fp mem ops?) */
2539 if (align > (TARGET_64BIT ? 8 : 4))
2540 align = (TARGET_64BIT ? 8 : 4);
2542 /* Note that we know each loop below will execute at least twice
2543 (else we would have open-coded the copy). */
2547 /* Pre-adjust the loop counter. */
2548 operands[4] = GEN_INT (n_bytes - 16);
2549 output_asm_insn ("ldi %4,%2", operands);
2552 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2553 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2554 output_asm_insn ("std,ma %3,8(%0)", operands);
2555 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2556 output_asm_insn ("std,ma %6,8(%0)", operands);
2558 /* Handle the residual. There could be up to 7 bytes of
2559 residual to copy! */
2560 if (n_bytes % 16 != 0)
2562 operands[4] = GEN_INT (n_bytes % 8);
2563 if (n_bytes % 16 >= 8)
2564 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2565 if (n_bytes % 8 != 0)
2566 output_asm_insn ("ldd 0(%1),%6", operands);
2567 if (n_bytes % 16 >= 8)
2568 output_asm_insn ("std,ma %3,8(%0)", operands);
2569 if (n_bytes % 8 != 0)
2570 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2575 /* Pre-adjust the loop counter. */
2576 operands[4] = GEN_INT (n_bytes - 8);
2577 output_asm_insn ("ldi %4,%2", operands);
2580 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2581 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2582 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2583 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2584 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2586 /* Handle the residual. There could be up to 7 bytes of
2587 residual to copy! */
2588 if (n_bytes % 8 != 0)
2590 operands[4] = GEN_INT (n_bytes % 4);
2591 if (n_bytes % 8 >= 4)
2592 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2593 if (n_bytes % 4 != 0)
2594 output_asm_insn ("ldw 0(%1),%6", operands);
2595 if (n_bytes % 8 >= 4)
2596 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2597 if (n_bytes % 4 != 0)
2598 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2603 /* Pre-adjust the loop counter. */
2604 operands[4] = GEN_INT (n_bytes - 4);
2605 output_asm_insn ("ldi %4,%2", operands);
2608 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2609 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2610 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2611 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2612 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2614 /* Handle the residual. */
2615 if (n_bytes % 4 != 0)
2617 if (n_bytes % 4 >= 2)
2618 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2619 if (n_bytes % 2 != 0)
2620 output_asm_insn ("ldb 0(%1),%6", operands);
2621 if (n_bytes % 4 >= 2)
2622 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2623 if (n_bytes % 2 != 0)
2624 output_asm_insn ("stb %6,0(%0)", operands);
2629 /* Pre-adjust the loop counter. */
2630 operands[4] = GEN_INT (n_bytes - 2);
2631 output_asm_insn ("ldi %4,%2", operands);
2634 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2635 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2636 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2637 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2638 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2640 /* Handle the residual. */
2641 if (n_bytes % 2 != 0)
2643 output_asm_insn ("ldb 0(%1),%3", operands);
2644 output_asm_insn ("stb %3,0(%0)", operands);
2653 /* Count the number of insns necessary to handle this block move.
2655 Basic structure is the same as emit_block_move, except that we
2656 count insns rather than emit them. */
2659 compute_movmem_length (rtx insn)
2661 rtx pat = PATTERN (insn);
2662 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2663 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2664 unsigned int n_insns = 0;
2666 /* We can't move more than four bytes at a time because the PA
2667 has no longer integer move insns. (Could use fp mem ops?) */
2668 if (align > (TARGET_64BIT ? 8 : 4))
2669 align = (TARGET_64BIT ? 8 : 4);
2671 /* The basic copying loop. */
2675 if (n_bytes % (2 * align) != 0)
2677 if ((n_bytes % (2 * align)) >= align)
2680 if ((n_bytes % align) != 0)
2684 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2688 /* Emit code to perform a block clear.
2690 OPERANDS[0] is the destination pointer as a REG, clobbered.
2691 OPERANDS[1] is a register for temporary storage.
2692 OPERANDS[2] is the size as a CONST_INT
2693 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2696 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2698 int align = INTVAL (operands[3]);
2699 unsigned long n_bytes = INTVAL (operands[2]);
2701 /* We can't clear more than a word at a time because the PA
2702 has no longer integer move insns. */
2703 if (align > (TARGET_64BIT ? 8 : 4))
2704 align = (TARGET_64BIT ? 8 : 4);
2706 /* Note that we know each loop below will execute at least twice
2707 (else we would have open-coded the copy). */
2711 /* Pre-adjust the loop counter. */
2712 operands[2] = GEN_INT (n_bytes - 16);
2713 output_asm_insn ("ldi %2,%1", operands);
2716 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2717 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2718 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2720 /* Handle the residual. There could be up to 7 bytes of
2721 residual to copy! */
2722 if (n_bytes % 16 != 0)
2724 operands[2] = GEN_INT (n_bytes % 8);
2725 if (n_bytes % 16 >= 8)
2726 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2727 if (n_bytes % 8 != 0)
2728 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2733 /* Pre-adjust the loop counter. */
2734 operands[2] = GEN_INT (n_bytes - 8);
2735 output_asm_insn ("ldi %2,%1", operands);
2738 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2739 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2740 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2742 /* Handle the residual. There could be up to 7 bytes of
2743 residual to copy! */
2744 if (n_bytes % 8 != 0)
2746 operands[2] = GEN_INT (n_bytes % 4);
2747 if (n_bytes % 8 >= 4)
2748 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2749 if (n_bytes % 4 != 0)
2750 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2755 /* Pre-adjust the loop counter. */
2756 operands[2] = GEN_INT (n_bytes - 4);
2757 output_asm_insn ("ldi %2,%1", operands);
2760 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2761 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2762 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2764 /* Handle the residual. */
2765 if (n_bytes % 4 != 0)
2767 if (n_bytes % 4 >= 2)
2768 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2769 if (n_bytes % 2 != 0)
2770 output_asm_insn ("stb %%r0,0(%0)", operands);
2775 /* Pre-adjust the loop counter. */
2776 operands[2] = GEN_INT (n_bytes - 2);
2777 output_asm_insn ("ldi %2,%1", operands);
2780 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2781 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2782 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2784 /* Handle the residual. */
2785 if (n_bytes % 2 != 0)
2786 output_asm_insn ("stb %%r0,0(%0)", operands);
2795 /* Count the number of insns necessary to handle this block move.
2797 Basic structure is the same as emit_block_move, except that we
2798 count insns rather than emit them. */
2801 compute_clrmem_length (rtx insn)
2803 rtx pat = PATTERN (insn);
2804 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2805 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2806 unsigned int n_insns = 0;
2808 /* We can't clear more than a word at a time because the PA
2809 has no longer integer move insns. */
2810 if (align > (TARGET_64BIT ? 8 : 4))
2811 align = (TARGET_64BIT ? 8 : 4);
2813 /* The basic loop. */
2817 if (n_bytes % (2 * align) != 0)
2819 if ((n_bytes % (2 * align)) >= align)
2822 if ((n_bytes % align) != 0)
2826 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2832 output_and (rtx *operands)
2834 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2836 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2837 int ls0, ls1, ms0, p, len;
2839 for (ls0 = 0; ls0 < 32; ls0++)
2840 if ((mask & (1 << ls0)) == 0)
2843 for (ls1 = ls0; ls1 < 32; ls1++)
2844 if ((mask & (1 << ls1)) != 0)
2847 for (ms0 = ls1; ms0 < 32; ms0++)
2848 if ((mask & (1 << ms0)) == 0)
2851 gcc_assert (ms0 == 32);
2859 operands[2] = GEN_INT (len);
2860 return "{extru|extrw,u} %1,31,%2,%0";
2864 /* We could use this `depi' for the case above as well, but `depi'
2865 requires one more register file access than an `extru'. */
2870 operands[2] = GEN_INT (p);
2871 operands[3] = GEN_INT (len);
2872 return "{depi|depwi} 0,%2,%3,%0";
2876 return "and %1,%2,%0";
2879 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2880 storing the result in operands[0]. */
2882 output_64bit_and (rtx *operands)
2884 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2886 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2887 int ls0, ls1, ms0, p, len;
2889 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2890 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2893 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2894 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2897 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2898 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2901 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2903 if (ls1 == HOST_BITS_PER_WIDE_INT)
2909 operands[2] = GEN_INT (len);
2910 return "extrd,u %1,63,%2,%0";
2914 /* We could use this `depi' for the case above as well, but `depi'
2915 requires one more register file access than an `extru'. */
2920 operands[2] = GEN_INT (p);
2921 operands[3] = GEN_INT (len);
2922 return "depdi 0,%2,%3,%0";
2926 return "and %1,%2,%0";
2930 output_ior (rtx *operands)
2932 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2933 int bs0, bs1, p, len;
2935 if (INTVAL (operands[2]) == 0)
2936 return "copy %1,%0";
2938 for (bs0 = 0; bs0 < 32; bs0++)
2939 if ((mask & (1 << bs0)) != 0)
2942 for (bs1 = bs0; bs1 < 32; bs1++)
2943 if ((mask & (1 << bs1)) == 0)
2946 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2951 operands[2] = GEN_INT (p);
2952 operands[3] = GEN_INT (len);
2953 return "{depi|depwi} -1,%2,%3,%0";
2956 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2957 storing the result in operands[0]. */
2959 output_64bit_ior (rtx *operands)
2961 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2962 int bs0, bs1, p, len;
2964 if (INTVAL (operands[2]) == 0)
2965 return "copy %1,%0";
2967 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2968 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2971 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2972 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2975 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
2976 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2981 operands[2] = GEN_INT (p);
2982 operands[3] = GEN_INT (len);
2983 return "depdi -1,%2,%3,%0";
2986 /* Target hook for assembling integer objects. This code handles
2987 aligned SI and DI integers specially since function references
2988 must be preceded by P%. */
2991 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
2993 if (size == UNITS_PER_WORD
2995 && function_label_operand (x, VOIDmode))
2997 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2998 output_addr_const (asm_out_file, x);
2999 fputc ('\n', asm_out_file);
3002 return default_assemble_integer (x, size, aligned_p);
3005 /* Output an ascii string. */
3007 output_ascii (FILE *file, const char *p, int size)
3011 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3013 /* The HP assembler can only take strings of 256 characters at one
3014 time. This is a limitation on input line length, *not* the
3015 length of the string. Sigh. Even worse, it seems that the
3016 restriction is in number of input characters (see \xnn &
3017 \whatever). So we have to do this very carefully. */
3019 fputs ("\t.STRING \"", file);
3022 for (i = 0; i < size; i += 4)
3026 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3028 register unsigned int c = (unsigned char) p[i + io];
3030 if (c == '\"' || c == '\\')
3031 partial_output[co++] = '\\';
3032 if (c >= ' ' && c < 0177)
3033 partial_output[co++] = c;
3037 partial_output[co++] = '\\';
3038 partial_output[co++] = 'x';
3039 hexd = c / 16 - 0 + '0';
3041 hexd -= '9' - 'a' + 1;
3042 partial_output[co++] = hexd;
3043 hexd = c % 16 - 0 + '0';
3045 hexd -= '9' - 'a' + 1;
3046 partial_output[co++] = hexd;
3049 if (chars_output + co > 243)
3051 fputs ("\"\n\t.STRING \"", file);
3054 fwrite (partial_output, 1, (size_t) co, file);
3058 fputs ("\"\n", file);
3061 /* Try to rewrite floating point comparisons & branches to avoid
3062 useless add,tr insns.
3064 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3065 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3066 first attempt to remove useless add,tr insns. It is zero
3067 for the second pass as reorg sometimes leaves bogus REG_DEAD
3070 When CHECK_NOTES is zero we can only eliminate add,tr insns
3071 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3074 remove_useless_addtr_insns (int check_notes)
3077 static int pass = 0;
3079 /* This is fairly cheap, so always run it when optimizing. */
3083 int fbranch_count = 0;
3085 /* Walk all the insns in this function looking for fcmp & fbranch
3086 instructions. Keep track of how many of each we find. */
3087 for (insn = get_insns (); insn; insn = next_insn (insn))
3091 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3092 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3095 tmp = PATTERN (insn);
3097 /* It must be a set. */
3098 if (GET_CODE (tmp) != SET)
3101 /* If the destination is CCFP, then we've found an fcmp insn. */
3102 tmp = SET_DEST (tmp);
3103 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3109 tmp = PATTERN (insn);
3110 /* If this is an fbranch instruction, bump the fbranch counter. */
3111 if (GET_CODE (tmp) == SET
3112 && SET_DEST (tmp) == pc_rtx
3113 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3114 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3115 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3116 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3124 /* Find all floating point compare + branch insns. If possible,
3125 reverse the comparison & the branch to avoid add,tr insns. */
3126 for (insn = get_insns (); insn; insn = next_insn (insn))
3130 /* Ignore anything that isn't an INSN. */
3131 if (GET_CODE (insn) != INSN)
3134 tmp = PATTERN (insn);
3136 /* It must be a set. */
3137 if (GET_CODE (tmp) != SET)
3140 /* The destination must be CCFP, which is register zero. */
3141 tmp = SET_DEST (tmp);
3142 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3145 /* INSN should be a set of CCFP.
3147 See if the result of this insn is used in a reversed FP
3148 conditional branch. If so, reverse our condition and
3149 the branch. Doing so avoids useless add,tr insns. */
3150 next = next_insn (insn);
3153 /* Jumps, calls and labels stop our search. */
3154 if (GET_CODE (next) == JUMP_INSN
3155 || GET_CODE (next) == CALL_INSN
3156 || GET_CODE (next) == CODE_LABEL)
3159 /* As does another fcmp insn. */
3160 if (GET_CODE (next) == INSN
3161 && GET_CODE (PATTERN (next)) == SET
3162 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3163 && REGNO (SET_DEST (PATTERN (next))) == 0)
3166 next = next_insn (next);
3169 /* Is NEXT_INSN a branch? */
3171 && GET_CODE (next) == JUMP_INSN)
3173 rtx pattern = PATTERN (next);
3175 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3176 and CCFP dies, then reverse our conditional and the branch
3177 to avoid the add,tr. */
3178 if (GET_CODE (pattern) == SET
3179 && SET_DEST (pattern) == pc_rtx
3180 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3181 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3182 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3183 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3184 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3185 && (fcmp_count == fbranch_count
3187 && find_regno_note (next, REG_DEAD, 0))))
3189 /* Reverse the branch. */
3190 tmp = XEXP (SET_SRC (pattern), 1);
3191 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3192 XEXP (SET_SRC (pattern), 2) = tmp;
3193 INSN_CODE (next) = -1;
3195 /* Reverse our condition. */
3196 tmp = PATTERN (insn);
3197 PUT_CODE (XEXP (tmp, 1),
3198 (reverse_condition_maybe_unordered
3199 (GET_CODE (XEXP (tmp, 1)))));
3209 /* You may have trouble believing this, but this is the 32 bit HP-PA
3214 Variable arguments (optional; any number may be allocated)
3216 SP-(4*(N+9)) arg word N
3221 Fixed arguments (must be allocated; may remain unused)
3230 SP-32 External Data Pointer (DP)
3232 SP-24 External/stub RP (RP')
3236 SP-8 Calling Stub RP (RP'')
3241 SP-0 Stack Pointer (points to next available address)
3245 /* This function saves registers as follows. Registers marked with ' are
3246 this function's registers (as opposed to the previous function's).
3247 If a frame_pointer isn't needed, r4 is saved as a general register;
3248 the space for the frame pointer is still allocated, though, to keep
3254 SP (FP') Previous FP
3255 SP + 4 Alignment filler (sigh)
3256 SP + 8 Space for locals reserved here.
3260 SP + n All call saved register used.
3264 SP + o All call saved fp registers used.
3268 SP + p (SP') points to next available address.
3272 /* Global variables set by output_function_prologue(). */
3273 /* Size of frame. Need to know this to emit return insns from
3275 static HOST_WIDE_INT actual_fsize, local_fsize;
3276 static int save_fregs;
3278 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3279 Handle case where DISP > 8k by using the add_high_const patterns.
3281 Note in DISP > 8k case, we will leave the high part of the address
3282 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3285 store_reg (int reg, HOST_WIDE_INT disp, int base)
3287 rtx insn, dest, src, basereg;
3289 src = gen_rtx_REG (word_mode, reg);
3290 basereg = gen_rtx_REG (Pmode, base);
3291 if (VAL_14_BITS_P (disp))
3293 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3294 insn = emit_move_insn (dest, src);
3296 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3298 rtx delta = GEN_INT (disp);
3299 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3301 emit_move_insn (tmpreg, delta);
3302 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3306 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3307 gen_rtx_SET (VOIDmode, tmpreg,
3308 gen_rtx_PLUS (Pmode, basereg, delta)),
3310 RTX_FRAME_RELATED_P (insn) = 1;
3312 dest = gen_rtx_MEM (word_mode, tmpreg);
3313 insn = emit_move_insn (dest, src);
3317 rtx delta = GEN_INT (disp);
3318 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3319 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3321 emit_move_insn (tmpreg, high);
3322 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3323 insn = emit_move_insn (dest, src);
3327 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3328 gen_rtx_SET (VOIDmode,
3329 gen_rtx_MEM (word_mode,
3330 gen_rtx_PLUS (word_mode, basereg,
3338 RTX_FRAME_RELATED_P (insn) = 1;
3341 /* Emit RTL to store REG at the memory location specified by BASE and then
3342 add MOD to BASE. MOD must be <= 8k. */
3345 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3347 rtx insn, basereg, srcreg, delta;
3349 gcc_assert (VAL_14_BITS_P (mod));
3351 basereg = gen_rtx_REG (Pmode, base);
3352 srcreg = gen_rtx_REG (word_mode, reg);
3353 delta = GEN_INT (mod);
3355 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3358 RTX_FRAME_RELATED_P (insn) = 1;
3360 /* RTX_FRAME_RELATED_P must be set on each frame related set
3361 in a parallel with more than one element. */
3362 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3363 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3367 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3368 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3369 whether to add a frame note or not.
3371 In the DISP > 8k case, we leave the high part of the address in %r1.
3372 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3375 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3379 if (VAL_14_BITS_P (disp))
3381 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3382 plus_constant (gen_rtx_REG (Pmode, base), disp));
3384 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3386 rtx basereg = gen_rtx_REG (Pmode, base);
3387 rtx delta = GEN_INT (disp);
3388 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3390 emit_move_insn (tmpreg, delta);
3391 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3392 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3395 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3396 gen_rtx_SET (VOIDmode, tmpreg,
3397 gen_rtx_PLUS (Pmode, basereg, delta)),
3402 rtx basereg = gen_rtx_REG (Pmode, base);
3403 rtx delta = GEN_INT (disp);
3404 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3406 emit_move_insn (tmpreg,
3407 gen_rtx_PLUS (Pmode, basereg,
3408 gen_rtx_HIGH (Pmode, delta)));
3409 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3410 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3413 if (DO_FRAME_NOTES && note)
3414 RTX_FRAME_RELATED_P (insn) = 1;
3418 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3423 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3424 be consistent with the rounding and size calculation done here.
3425 Change them at the same time. */
3427 /* We do our own stack alignment. First, round the size of the
3428 stack locals up to a word boundary. */
3429 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3431 /* Space for previous frame pointer + filler. If any frame is
3432 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3433 waste some space here for the sake of HP compatibility. The
3434 first slot is only used when the frame pointer is needed. */
3435 if (size || frame_pointer_needed)
3436 size += STARTING_FRAME_OFFSET;
3438 /* If the current function calls __builtin_eh_return, then we need
3439 to allocate stack space for registers that will hold data for
3440 the exception handler. */
3441 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3445 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3447 size += i * UNITS_PER_WORD;
3450 /* Account for space used by the callee general register saves. */
3451 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3452 if (regs_ever_live[i])
3453 size += UNITS_PER_WORD;
3455 /* Account for space used by the callee floating point register saves. */
3456 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3457 if (regs_ever_live[i]
3458 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3462 /* We always save both halves of the FP register, so always
3463 increment the frame size by 8 bytes. */
3467 /* If any of the floating registers are saved, account for the
3468 alignment needed for the floating point register save block. */
3471 size = (size + 7) & ~7;
3476 /* The various ABIs include space for the outgoing parameters in the
3477 size of the current function's stack frame. We don't need to align
3478 for the outgoing arguments as their alignment is set by the final
3479 rounding for the frame as a whole. */
3480 size += current_function_outgoing_args_size;
3482 /* Allocate space for the fixed frame marker. This space must be
3483 allocated for any function that makes calls or allocates
3485 if (!current_function_is_leaf || size)
3486 size += TARGET_64BIT ? 48 : 32;
3488 /* Finally, round to the preferred stack boundary. */
3489 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3490 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3493 /* Generate the assembly code for function entry. FILE is a stdio
3494 stream to output the code to. SIZE is an int: how many units of
3495 temporary storage to allocate.
3497 Refer to the array `regs_ever_live' to determine which registers to
3498 save; `regs_ever_live[I]' is nonzero if register number I is ever
3499 used in the function. This function is responsible for knowing
3500 which registers should not be saved even if used. */
3502 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3503 of memory. If any fpu reg is used in the function, we allocate
3504 such a block here, at the bottom of the frame, just in case it's needed.
3506 If this function is a leaf procedure, then we may choose not
3507 to do a "save" insn. The decision about whether or not
3508 to do this is made in regclass.c. */
3511 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3513 /* The function's label and associated .PROC must never be
3514 separated and must be output *after* any profiling declarations
3515 to avoid changing spaces/subspaces within a procedure. */
3516 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3517 fputs ("\t.PROC\n", file);
3519 /* hppa_expand_prologue does the dirty work now. We just need
3520 to output the assembler directives which denote the start
3522 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3523 if (regs_ever_live[2])
3524 fputs (",CALLS,SAVE_RP", file);
3526 fputs (",NO_CALLS", file);
3528 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3529 at the beginning of the frame and that it is used as the frame
3530 pointer for the frame. We do this because our current frame
3531 layout doesn't conform to that specified in the HP runtime
3532 documentation and we need a way to indicate to programs such as
3533 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3534 isn't used by HP compilers but is supported by the assembler.
3535 However, SAVE_SP is supposed to indicate that the previous stack
3536 pointer has been saved in the frame marker. */
3537 if (frame_pointer_needed)
3538 fputs (",SAVE_SP", file);
3540 /* Pass on information about the number of callee register saves
3541 performed in the prologue.
3543 The compiler is supposed to pass the highest register number
3544 saved, the assembler then has to adjust that number before
3545 entering it into the unwind descriptor (to account for any
3546 caller saved registers with lower register numbers than the
3547 first callee saved register). */
3549 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3552 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3554 fputs ("\n\t.ENTRY\n", file);
3556 remove_useless_addtr_insns (0);
3560 hppa_expand_prologue (void)
3562 int merge_sp_adjust_with_store = 0;
3563 HOST_WIDE_INT size = get_frame_size ();
3564 HOST_WIDE_INT offset;
3572 /* Compute total size for frame pointer, filler, locals and rounding to
3573 the next word boundary. Similar code appears in compute_frame_size
3574 and must be changed in tandem with this code. */
3575 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3576 if (local_fsize || frame_pointer_needed)
3577 local_fsize += STARTING_FRAME_OFFSET;
3579 actual_fsize = compute_frame_size (size, &save_fregs);
3581 /* Compute a few things we will use often. */
3582 tmpreg = gen_rtx_REG (word_mode, 1);
3584 /* Save RP first. The calling conventions manual states RP will
3585 always be stored into the caller's frame at sp - 20 or sp - 16
3586 depending on which ABI is in use. */
3587 if (regs_ever_live[2] || current_function_calls_eh_return)
3588 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3590 /* Allocate the local frame and set up the frame pointer if needed. */
3591 if (actual_fsize != 0)
3593 if (frame_pointer_needed)
3595 /* Copy the old frame pointer temporarily into %r1. Set up the
3596 new stack pointer, then store away the saved old frame pointer
3597 into the stack at sp and at the same time update the stack
3598 pointer by actual_fsize bytes. Two versions, first
3599 handles small (<8k) frames. The second handles large (>=8k)
3601 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3603 RTX_FRAME_RELATED_P (insn) = 1;
3605 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3607 RTX_FRAME_RELATED_P (insn) = 1;
3609 if (VAL_14_BITS_P (actual_fsize))
3610 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3613 /* It is incorrect to store the saved frame pointer at *sp,
3614 then increment sp (writes beyond the current stack boundary).
3616 So instead use stwm to store at *sp and post-increment the
3617 stack pointer as an atomic operation. Then increment sp to
3618 finish allocating the new frame. */
3619 HOST_WIDE_INT adjust1 = 8192 - 64;
3620 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3622 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3623 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3627 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3628 we need to store the previous stack pointer (frame pointer)
3629 into the frame marker on targets that use the HP unwind
3630 library. This allows the HP unwind library to be used to
3631 unwind GCC frames. However, we are not fully compatible
3632 with the HP library because our frame layout differs from
3633 that specified in the HP runtime specification.
3635 We don't want a frame note on this instruction as the frame
3636 marker moves during dynamic stack allocation.
3638 This instruction also serves as a blockage to prevent
3639 register spills from being scheduled before the stack
3640 pointer is raised. This is necessary as we store
3641 registers using the frame pointer as a base register,
3642 and the frame pointer is set before sp is raised. */
3643 if (TARGET_HPUX_UNWIND_LIBRARY)
3645 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3646 GEN_INT (TARGET_64BIT ? -8 : -4));
3648 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3652 emit_insn (gen_blockage ());
3654 /* no frame pointer needed. */
3657 /* In some cases we can perform the first callee register save
3658 and allocating the stack frame at the same time. If so, just
3659 make a note of it and defer allocating the frame until saving
3660 the callee registers. */
3661 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3662 merge_sp_adjust_with_store = 1;
3663 /* Can not optimize. Adjust the stack frame by actual_fsize
3666 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3671 /* Normal register save.
3673 Do not save the frame pointer in the frame_pointer_needed case. It
3674 was done earlier. */
3675 if (frame_pointer_needed)
3677 offset = local_fsize;
3679 /* Saving the EH return data registers in the frame is the simplest
3680 way to get the frame unwind information emitted. We put them
3681 just before the general registers. */
3682 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3684 unsigned int i, regno;
3688 regno = EH_RETURN_DATA_REGNO (i);
3689 if (regno == INVALID_REGNUM)
3692 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3693 offset += UNITS_PER_WORD;
3697 for (i = 18; i >= 4; i--)
3698 if (regs_ever_live[i] && ! call_used_regs[i])
3700 store_reg (i, offset, FRAME_POINTER_REGNUM);
3701 offset += UNITS_PER_WORD;
3704 /* Account for %r3 which is saved in a special place. */
3707 /* No frame pointer needed. */
3710 offset = local_fsize - actual_fsize;
3712 /* Saving the EH return data registers in the frame is the simplest
3713 way to get the frame unwind information emitted. */
3714 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3716 unsigned int i, regno;
3720 regno = EH_RETURN_DATA_REGNO (i);
3721 if (regno == INVALID_REGNUM)
3724 /* If merge_sp_adjust_with_store is nonzero, then we can
3725 optimize the first save. */
3726 if (merge_sp_adjust_with_store)
3728 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3729 merge_sp_adjust_with_store = 0;
3732 store_reg (regno, offset, STACK_POINTER_REGNUM);
3733 offset += UNITS_PER_WORD;
3737 for (i = 18; i >= 3; i--)
3738 if (regs_ever_live[i] && ! call_used_regs[i])
3740 /* If merge_sp_adjust_with_store is nonzero, then we can
3741 optimize the first GR save. */
3742 if (merge_sp_adjust_with_store)
3744 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3745 merge_sp_adjust_with_store = 0;
3748 store_reg (i, offset, STACK_POINTER_REGNUM);
3749 offset += UNITS_PER_WORD;
3753 /* If we wanted to merge the SP adjustment with a GR save, but we never
3754 did any GR saves, then just emit the adjustment here. */
3755 if (merge_sp_adjust_with_store)
3756 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3760 /* The hppa calling conventions say that %r19, the pic offset
3761 register, is saved at sp - 32 (in this function's frame)
3762 when generating PIC code. FIXME: What is the correct thing
3763 to do for functions which make no calls and allocate no
3764 frame? Do we need to allocate a frame, or can we just omit
3765 the save? For now we'll just omit the save.
3767 We don't want a note on this insn as the frame marker can
3768 move if there is a dynamic stack allocation. */
3769 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3771 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3773 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3777 /* Align pointer properly (doubleword boundary). */
3778 offset = (offset + 7) & ~7;
3780 /* Floating point register store. */
3785 /* First get the frame or stack pointer to the start of the FP register
3787 if (frame_pointer_needed)
3789 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3790 base = frame_pointer_rtx;
3794 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3795 base = stack_pointer_rtx;
3798 /* Now actually save the FP registers. */
3799 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3801 if (regs_ever_live[i]
3802 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3804 rtx addr, insn, reg;
3805 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3806 reg = gen_rtx_REG (DFmode, i);
3807 insn = emit_move_insn (addr, reg);
3810 RTX_FRAME_RELATED_P (insn) = 1;
3813 rtx mem = gen_rtx_MEM (DFmode,
3814 plus_constant (base, offset));
3816 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3817 gen_rtx_SET (VOIDmode, mem, reg),
3822 rtx meml = gen_rtx_MEM (SFmode,
3823 plus_constant (base, offset));
3824 rtx memr = gen_rtx_MEM (SFmode,
3825 plus_constant (base, offset + 4));
3826 rtx regl = gen_rtx_REG (SFmode, i);
3827 rtx regr = gen_rtx_REG (SFmode, i + 1);
3828 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3829 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3832 RTX_FRAME_RELATED_P (setl) = 1;
3833 RTX_FRAME_RELATED_P (setr) = 1;
3834 vec = gen_rtvec (2, setl, setr);
3836 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3837 gen_rtx_SEQUENCE (VOIDmode, vec),
3841 offset += GET_MODE_SIZE (DFmode);
3848 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3849 Handle case where DISP > 8k by using the add_high_const patterns. */
3852 load_reg (int reg, HOST_WIDE_INT disp, int base)
3854 rtx dest = gen_rtx_REG (word_mode, reg);
3855 rtx basereg = gen_rtx_REG (Pmode, base);
3858 if (VAL_14_BITS_P (disp))
3859 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3860 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3862 rtx delta = GEN_INT (disp);
3863 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3865 emit_move_insn (tmpreg, delta);
3866 if (TARGET_DISABLE_INDEXING)
3868 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3869 src = gen_rtx_MEM (word_mode, tmpreg);
3872 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3876 rtx delta = GEN_INT (disp);
3877 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3878 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3880 emit_move_insn (tmpreg, high);
3881 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3884 emit_move_insn (dest, src);
3887 /* Update the total code bytes output to the text section. */
3890 update_total_code_bytes (int nbytes)
3892 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3893 && !IN_NAMED_SECTION_P (cfun->decl))
3895 if (INSN_ADDRESSES_SET_P ())
3897 unsigned long old_total = total_code_bytes;
3899 total_code_bytes += nbytes;
3901 /* Be prepared to handle overflows. */
3902 if (old_total > total_code_bytes)
3903 total_code_bytes = -1;
3906 total_code_bytes = -1;
3910 /* This function generates the assembly code for function exit.
3911 Args are as for output_function_prologue ().
3913 The function epilogue should not depend on the current stack
3914 pointer! It should use the frame pointer only. This is mandatory
3915 because of alloca; we also take advantage of it to omit stack
3916 adjustments before returning. */
3919 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3921 rtx insn = get_last_insn ();
3925 /* hppa_expand_epilogue does the dirty work now. We just need
3926 to output the assembler directives which denote the end
3929 To make debuggers happy, emit a nop if the epilogue was completely
3930 eliminated due to a volatile call as the last insn in the
3931 current function. That way the return address (in %r2) will
3932 always point to a valid instruction in the current function. */
3934 /* Get the last real insn. */
3935 if (GET_CODE (insn) == NOTE)
3936 insn = prev_real_insn (insn);
3938 /* If it is a sequence, then look inside. */
3939 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3940 insn = XVECEXP (PATTERN (insn), 0, 0);
3942 /* If insn is a CALL_INSN, then it must be a call to a volatile
3943 function (otherwise there would be epilogue insns). */
3944 if (insn && GET_CODE (insn) == CALL_INSN)
3946 fputs ("\tnop\n", file);
3950 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3952 if (TARGET_SOM && TARGET_GAS)
3954 /* We done with this subspace except possibly for some additional
3955 debug information. Forget that we are in this subspace to ensure
3956 that the next function is output in its own subspace. */
3958 cfun->machine->in_nsubspa = 2;
3961 if (INSN_ADDRESSES_SET_P ())
3963 insn = get_last_nonnote_insn ();
3964 last_address += INSN_ADDRESSES (INSN_UID (insn));
3966 last_address += insn_default_length (insn);
3967 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
3968 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
3971 /* Finally, update the total number of code bytes output so far. */
3972 update_total_code_bytes (last_address);
3976 hppa_expand_epilogue (void)
3979 HOST_WIDE_INT offset;
3980 HOST_WIDE_INT ret_off = 0;
3982 int merge_sp_adjust_with_load = 0;
3984 /* We will use this often. */
3985 tmpreg = gen_rtx_REG (word_mode, 1);
3987 /* Try to restore RP early to avoid load/use interlocks when
3988 RP gets used in the return (bv) instruction. This appears to still
3989 be necessary even when we schedule the prologue and epilogue. */
3990 if (regs_ever_live [2] || current_function_calls_eh_return)
3992 ret_off = TARGET_64BIT ? -16 : -20;
3993 if (frame_pointer_needed)
3995 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4000 /* No frame pointer, and stack is smaller than 8k. */
4001 if (VAL_14_BITS_P (ret_off - actual_fsize))
4003 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4009 /* General register restores. */
4010 if (frame_pointer_needed)
4012 offset = local_fsize;
4014 /* If the current function calls __builtin_eh_return, then we need
4015 to restore the saved EH data registers. */
4016 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4018 unsigned int i, regno;
4022 regno = EH_RETURN_DATA_REGNO (i);
4023 if (regno == INVALID_REGNUM)
4026 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4027 offset += UNITS_PER_WORD;
4031 for (i = 18; i >= 4; i--)
4032 if (regs_ever_live[i] && ! call_used_regs[i])
4034 load_reg (i, offset, FRAME_POINTER_REGNUM);
4035 offset += UNITS_PER_WORD;
4040 offset = local_fsize - actual_fsize;
4042 /* If the current function calls __builtin_eh_return, then we need
4043 to restore the saved EH data registers. */
4044 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4046 unsigned int i, regno;
4050 regno = EH_RETURN_DATA_REGNO (i);
4051 if (regno == INVALID_REGNUM)
4054 /* Only for the first load.
4055 merge_sp_adjust_with_load holds the register load
4056 with which we will merge the sp adjustment. */
4057 if (merge_sp_adjust_with_load == 0
4059 && VAL_14_BITS_P (-actual_fsize))
4060 merge_sp_adjust_with_load = regno;
4062 load_reg (regno, offset, STACK_POINTER_REGNUM);
4063 offset += UNITS_PER_WORD;
4067 for (i = 18; i >= 3; i--)
4069 if (regs_ever_live[i] && ! call_used_regs[i])
4071 /* Only for the first load.
4072 merge_sp_adjust_with_load holds the register load
4073 with which we will merge the sp adjustment. */
4074 if (merge_sp_adjust_with_load == 0
4076 && VAL_14_BITS_P (-actual_fsize))
4077 merge_sp_adjust_with_load = i;
4079 load_reg (i, offset, STACK_POINTER_REGNUM);
4080 offset += UNITS_PER_WORD;
4085 /* Align pointer properly (doubleword boundary). */
4086 offset = (offset + 7) & ~7;
4088 /* FP register restores. */
4091 /* Adjust the register to index off of. */
4092 if (frame_pointer_needed)
4093 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4095 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4097 /* Actually do the restores now. */
4098 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4099 if (regs_ever_live[i]
4100 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4102 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4103 rtx dest = gen_rtx_REG (DFmode, i);
4104 emit_move_insn (dest, src);
4108 /* Emit a blockage insn here to keep these insns from being moved to
4109 an earlier spot in the epilogue, or into the main instruction stream.
4111 This is necessary as we must not cut the stack back before all the
4112 restores are finished. */
4113 emit_insn (gen_blockage ());
4115 /* Reset stack pointer (and possibly frame pointer). The stack
4116 pointer is initially set to fp + 64 to avoid a race condition. */
4117 if (frame_pointer_needed)
4119 rtx delta = GEN_INT (-64);
4121 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4122 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4124 /* If we were deferring a callee register restore, do it now. */
4125 else if (merge_sp_adjust_with_load)
4127 rtx delta = GEN_INT (-actual_fsize);
4128 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4130 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4132 else if (actual_fsize != 0)
4133 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4136 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4137 frame greater than 8k), do so now. */
4139 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4141 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4143 rtx sa = EH_RETURN_STACKADJ_RTX;
4145 emit_insn (gen_blockage ());
4146 emit_insn (TARGET_64BIT
4147 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4148 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4153 hppa_pic_save_rtx (void)
4155 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4158 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4159 #define NO_DEFERRED_PROFILE_COUNTERS 0
4163 /* Vector of funcdef numbers. */
4164 static VEC(int,heap) *funcdef_nos;
4166 /* Output deferred profile counters. */
4168 output_deferred_profile_counters (void)
4173 if (VEC_empty (int, funcdef_nos))
4176 switch_to_section (data_section);
4177 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4178 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4180 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4182 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4183 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4186 VEC_free (int, heap, funcdef_nos);
4190 hppa_profile_hook (int label_no)
4192 /* We use SImode for the address of the function in both 32 and
4193 64-bit code to avoid having to provide DImode versions of the
4194 lcla2 and load_offset_label_address insn patterns. */
4195 rtx reg = gen_reg_rtx (SImode);
4196 rtx label_rtx = gen_label_rtx ();
4197 rtx begin_label_rtx, call_insn;
4198 char begin_label_name[16];
4200 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4202 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4205 emit_move_insn (arg_pointer_rtx,
4206 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4209 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4211 /* The address of the function is loaded into %r25 with a instruction-
4212 relative sequence that avoids the use of relocations. The sequence
4213 is split so that the load_offset_label_address instruction can
4214 occupy the delay slot of the call to _mcount. */
4216 emit_insn (gen_lcla2 (reg, label_rtx));
4218 emit_insn (gen_lcla1 (reg, label_rtx));
4220 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4221 reg, begin_label_rtx, label_rtx));
4223 #if !NO_DEFERRED_PROFILE_COUNTERS
4225 rtx count_label_rtx, addr, r24;
4226 char count_label_name[16];
4228 VEC_safe_push (int, heap, funcdef_nos, label_no);
4229 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4230 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4232 addr = force_reg (Pmode, count_label_rtx);
4233 r24 = gen_rtx_REG (Pmode, 24);
4234 emit_move_insn (r24, addr);
4237 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4238 gen_rtx_SYMBOL_REF (Pmode,
4240 GEN_INT (TARGET_64BIT ? 24 : 12)));
4242 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4247 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4248 gen_rtx_SYMBOL_REF (Pmode,
4250 GEN_INT (TARGET_64BIT ? 16 : 8)));
4254 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4255 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4257 /* Indicate the _mcount call cannot throw, nor will it execute a
4259 REG_NOTES (call_insn)
4260 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4263 /* Fetch the return address for the frame COUNT steps up from
4264 the current frame, after the prologue. FRAMEADDR is the
4265 frame pointer of the COUNT frame.
4267 We want to ignore any export stub remnants here. To handle this,
4268 we examine the code at the return address, and if it is an export
4269 stub, we return a memory rtx for the stub return address stored
4272 The value returned is used in two different ways:
4274 1. To find a function's caller.
4276 2. To change the return address for a function.
4278 This function handles most instances of case 1; however, it will
4279 fail if there are two levels of stubs to execute on the return
4280 path. The only way I believe that can happen is if the return value
4281 needs a parameter relocation, which never happens for C code.
4283 This function handles most instances of case 2; however, it will
4284 fail if we did not originally have stub code on the return path
4285 but will need stub code on the new return path. This can happen if
4286 the caller & callee are both in the main program, but the new
4287 return location is in a shared library. */
4290 return_addr_rtx (int count, rtx frameaddr)
4300 rp = get_hard_reg_initial_val (Pmode, 2);
4302 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4305 saved_rp = gen_reg_rtx (Pmode);
4306 emit_move_insn (saved_rp, rp);
4308 /* Get pointer to the instruction stream. We have to mask out the
4309 privilege level from the two low order bits of the return address
4310 pointer here so that ins will point to the start of the first
4311 instruction that would have been executed if we returned. */
4312 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4313 label = gen_label_rtx ();
4315 /* Check the instruction stream at the normal return address for the
4318 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4319 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4320 0x00011820 | stub+16: mtsp r1,sr0
4321 0xe0400002 | stub+20: be,n 0(sr0,rp)
4323 If it is an export stub, than our return address is really in
4326 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4327 NULL_RTX, SImode, 1);
4328 emit_jump_insn (gen_bne (label));
4330 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4331 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4332 emit_jump_insn (gen_bne (label));
4334 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4335 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4336 emit_jump_insn (gen_bne (label));
4338 /* 0xe0400002 must be specified as -532676606 so that it won't be
4339 rejected as an invalid immediate operand on 64-bit hosts. */
4340 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4341 GEN_INT (-532676606), NE, NULL_RTX, SImode, 1);
4343 /* If there is no export stub then just use the value saved from
4344 the return pointer register. */
4346 emit_jump_insn (gen_bne (label));
4348 /* Here we know that our return address points to an export
4349 stub. We don't want to return the address of the export stub,
4350 but rather the return address of the export stub. That return
4351 address is stored at -24[frameaddr]. */
4353 emit_move_insn (saved_rp,
4355 memory_address (Pmode,
4356 plus_constant (frameaddr,
4363 /* This is only valid once reload has completed because it depends on
4364 knowing exactly how much (if any) frame there is and...
4366 It's only valid if there is no frame marker to de-allocate and...
4368 It's only valid if %r2 hasn't been saved into the caller's frame
4369 (we're not profiling and %r2 isn't live anywhere). */
4371 hppa_can_use_return_insn_p (void)
4373 return (reload_completed
4374 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4375 && ! regs_ever_live[2]
4376 && ! frame_pointer_needed);
4380 emit_bcond_fp (enum rtx_code code, rtx operand0)
4382 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4383 gen_rtx_IF_THEN_ELSE (VOIDmode,
4384 gen_rtx_fmt_ee (code,
4386 gen_rtx_REG (CCFPmode, 0),
4388 gen_rtx_LABEL_REF (VOIDmode, operand0),
4394 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4396 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4397 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4400 /* Adjust the cost of a scheduling dependency. Return the new cost of
4401 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4404 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4406 enum attr_type attr_type;
4408 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4409 true dependencies as they are described with bypasses now. */
4410 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4413 if (! recog_memoized (insn))
4416 attr_type = get_attr_type (insn);
4418 switch (REG_NOTE_KIND (link))
4421 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4424 if (attr_type == TYPE_FPLOAD)
4426 rtx pat = PATTERN (insn);
4427 rtx dep_pat = PATTERN (dep_insn);
4428 if (GET_CODE (pat) == PARALLEL)
4430 /* This happens for the fldXs,mb patterns. */
4431 pat = XVECEXP (pat, 0, 0);
4433 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4434 /* If this happens, we have to extend this to schedule
4435 optimally. Return 0 for now. */
4438 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4440 if (! recog_memoized (dep_insn))
4442 switch (get_attr_type (dep_insn))
4449 case TYPE_FPSQRTSGL:
4450 case TYPE_FPSQRTDBL:
4451 /* A fpload can't be issued until one cycle before a
4452 preceding arithmetic operation has finished if
4453 the target of the fpload is any of the sources
4454 (or destination) of the arithmetic operation. */
4455 return insn_default_latency (dep_insn) - 1;
4462 else if (attr_type == TYPE_FPALU)
4464 rtx pat = PATTERN (insn);
4465 rtx dep_pat = PATTERN (dep_insn);
4466 if (GET_CODE (pat) == PARALLEL)
4468 /* This happens for the fldXs,mb patterns. */
4469 pat = XVECEXP (pat, 0, 0);
4471 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4472 /* If this happens, we have to extend this to schedule
4473 optimally. Return 0 for now. */
4476 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4478 if (! recog_memoized (dep_insn))
4480 switch (get_attr_type (dep_insn))
4484 case TYPE_FPSQRTSGL:
4485 case TYPE_FPSQRTDBL:
4486 /* An ALU flop can't be issued until two cycles before a
4487 preceding divide or sqrt operation has finished if
4488 the target of the ALU flop is any of the sources
4489 (or destination) of the divide or sqrt operation. */
4490 return insn_default_latency (dep_insn) - 2;
4498 /* For other anti dependencies, the cost is 0. */
4501 case REG_DEP_OUTPUT:
4502 /* Output dependency; DEP_INSN writes a register that INSN writes some
4504 if (attr_type == TYPE_FPLOAD)
4506 rtx pat = PATTERN (insn);
4507 rtx dep_pat = PATTERN (dep_insn);
4508 if (GET_CODE (pat) == PARALLEL)
4510 /* This happens for the fldXs,mb patterns. */
4511 pat = XVECEXP (pat, 0, 0);
4513 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4514 /* If this happens, we have to extend this to schedule
4515 optimally. Return 0 for now. */
4518 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4520 if (! recog_memoized (dep_insn))
4522 switch (get_attr_type (dep_insn))
4529 case TYPE_FPSQRTSGL:
4530 case TYPE_FPSQRTDBL:
4531 /* A fpload can't be issued until one cycle before a
4532 preceding arithmetic operation has finished if
4533 the target of the fpload is the destination of the
4534 arithmetic operation.
4536 Exception: For PA7100LC, PA7200 and PA7300, the cost
4537 is 3 cycles, unless they bundle together. We also
4538 pay the penalty if the second insn is a fpload. */
4539 return insn_default_latency (dep_insn) - 1;
4546 else if (attr_type == TYPE_FPALU)
4548 rtx pat = PATTERN (insn);
4549 rtx dep_pat = PATTERN (dep_insn);
4550 if (GET_CODE (pat) == PARALLEL)
4552 /* This happens for the fldXs,mb patterns. */
4553 pat = XVECEXP (pat, 0, 0);
4555 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4556 /* If this happens, we have to extend this to schedule
4557 optimally. Return 0 for now. */
4560 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4562 if (! recog_memoized (dep_insn))
4564 switch (get_attr_type (dep_insn))
4568 case TYPE_FPSQRTSGL:
4569 case TYPE_FPSQRTDBL:
4570 /* An ALU flop can't be issued until two cycles before a
4571 preceding divide or sqrt operation has finished if
4572 the target of the ALU flop is also the target of
4573 the divide or sqrt operation. */
4574 return insn_default_latency (dep_insn) - 2;
4582 /* For other output dependencies, the cost is 0. */
4590 /* Adjust scheduling priorities. We use this to try and keep addil
4591 and the next use of %r1 close together. */
4593 pa_adjust_priority (rtx insn, int priority)
4595 rtx set = single_set (insn);
4599 src = SET_SRC (set);
4600 dest = SET_DEST (set);
4601 if (GET_CODE (src) == LO_SUM
4602 && symbolic_operand (XEXP (src, 1), VOIDmode)
4603 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4606 else if (GET_CODE (src) == MEM
4607 && GET_CODE (XEXP (src, 0)) == LO_SUM
4608 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4609 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4612 else if (GET_CODE (dest) == MEM
4613 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4614 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4615 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4621 /* The 700 can only issue a single insn at a time.
4622 The 7XXX processors can issue two insns at a time.
4623 The 8000 can issue 4 insns at a time. */
4625 pa_issue_rate (void)
4629 case PROCESSOR_700: return 1;
4630 case PROCESSOR_7100: return 2;
4631 case PROCESSOR_7100LC: return 2;
4632 case PROCESSOR_7200: return 2;
4633 case PROCESSOR_7300: return 2;
4634 case PROCESSOR_8000: return 4;
4643 /* Return any length adjustment needed by INSN which already has its length
4644 computed as LENGTH. Return zero if no adjustment is necessary.
4646 For the PA: function calls, millicode calls, and backwards short
4647 conditional branches with unfilled delay slots need an adjustment by +1
4648 (to account for the NOP which will be inserted into the instruction stream).
4650 Also compute the length of an inline block move here as it is too
4651 complicated to express as a length attribute in pa.md. */
4653 pa_adjust_insn_length (rtx insn, int length)
4655 rtx pat = PATTERN (insn);
4657 /* Jumps inside switch tables which have unfilled delay slots need
4659 if (GET_CODE (insn) == JUMP_INSN
4660 && GET_CODE (pat) == PARALLEL
4661 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4663 /* Millicode insn with an unfilled delay slot. */
4664 else if (GET_CODE (insn) == INSN
4665 && GET_CODE (pat) != SEQUENCE
4666 && GET_CODE (pat) != USE
4667 && GET_CODE (pat) != CLOBBER
4668 && get_attr_type (insn) == TYPE_MILLI)
4670 /* Block move pattern. */
4671 else if (GET_CODE (insn) == INSN
4672 && GET_CODE (pat) == PARALLEL
4673 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4674 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4675 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4676 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4677 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4678 return compute_movmem_length (insn) - 4;
4679 /* Block clear pattern. */
4680 else if (GET_CODE (insn) == INSN
4681 && GET_CODE (pat) == PARALLEL
4682 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4683 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4684 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4685 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4686 return compute_clrmem_length (insn) - 4;
4687 /* Conditional branch with an unfilled delay slot. */
4688 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4690 /* Adjust a short backwards conditional with an unfilled delay slot. */
4691 if (GET_CODE (pat) == SET
4693 && ! forward_branch_p (insn))
4695 else if (GET_CODE (pat) == PARALLEL
4696 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4699 /* Adjust dbra insn with short backwards conditional branch with
4700 unfilled delay slot -- only for case where counter is in a
4701 general register register. */
4702 else if (GET_CODE (pat) == PARALLEL
4703 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4704 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4705 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4707 && ! forward_branch_p (insn))
4715 /* Print operand X (an rtx) in assembler syntax to file FILE.
4716 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4717 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4720 print_operand (FILE *file, rtx x, int code)
4725 /* Output a 'nop' if there's nothing for the delay slot. */
4726 if (dbr_sequence_length () == 0)
4727 fputs ("\n\tnop", file);
4730 /* Output a nullification completer if there's nothing for the */
4731 /* delay slot or nullification is requested. */
4732 if (dbr_sequence_length () == 0 ||
4734 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4738 /* Print out the second register name of a register pair.
4739 I.e., R (6) => 7. */
4740 fputs (reg_names[REGNO (x) + 1], file);
4743 /* A register or zero. */
4745 || (x == CONST0_RTX (DFmode))
4746 || (x == CONST0_RTX (SFmode)))
4748 fputs ("%r0", file);
4754 /* A register or zero (floating point). */
4756 || (x == CONST0_RTX (DFmode))
4757 || (x == CONST0_RTX (SFmode)))
4759 fputs ("%fr0", file);
4768 xoperands[0] = XEXP (XEXP (x, 0), 0);
4769 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4770 output_global_address (file, xoperands[1], 0);
4771 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4775 case 'C': /* Plain (C)ondition */
4777 switch (GET_CODE (x))
4780 fputs ("=", file); break;
4782 fputs ("<>", file); break;
4784 fputs (">", file); break;
4786 fputs (">=", file); break;
4788 fputs (">>=", file); break;
4790 fputs (">>", file); break;
4792 fputs ("<", file); break;
4794 fputs ("<=", file); break;
4796 fputs ("<<=", file); break;
4798 fputs ("<<", file); break;
4803 case 'N': /* Condition, (N)egated */
4804 switch (GET_CODE (x))
4807 fputs ("<>", file); break;
4809 fputs ("=", file); break;
4811 fputs ("<=", file); break;
4813 fputs ("<", file); break;
4815 fputs ("<<", file); break;
4817 fputs ("<<=", file); break;
4819 fputs (">=", file); break;
4821 fputs (">", file); break;
4823 fputs (">>", file); break;
4825 fputs (">>=", file); break;
4830 /* For floating point comparisons. Note that the output
4831 predicates are the complement of the desired mode. The
4832 conditions for GT, GE, LT, LE and LTGT cause an invalid
4833 operation exception if the result is unordered and this
4834 exception is enabled in the floating-point status register. */
4836 switch (GET_CODE (x))
4839 fputs ("!=", file); break;
4841 fputs ("=", file); break;
4843 fputs ("!>", file); break;
4845 fputs ("!>=", file); break;
4847 fputs ("!<", file); break;
4849 fputs ("!<=", file); break;
4851 fputs ("!<>", file); break;
4853 fputs ("!?<=", file); break;
4855 fputs ("!?<", file); break;
4857 fputs ("!?>=", file); break;
4859 fputs ("!?>", file); break;
4861 fputs ("!?=", file); break;
4863 fputs ("!?", file); break;
4865 fputs ("?", file); break;
4870 case 'S': /* Condition, operands are (S)wapped. */
4871 switch (GET_CODE (x))
4874 fputs ("=", file); break;
4876 fputs ("<>", file); break;
4878 fputs ("<", file); break;
4880 fputs ("<=", file); break;
4882 fputs ("<<=", file); break;
4884 fputs ("<<", file); break;
4886 fputs (">", file); break;
4888 fputs (">=", file); break;
4890 fputs (">>=", file); break;
4892 fputs (">>", file); break;
4897 case 'B': /* Condition, (B)oth swapped and negate. */
4898 switch (GET_CODE (x))
4901 fputs ("<>", file); break;
4903 fputs ("=", file); break;
4905 fputs (">=", file); break;
4907 fputs (">", file); break;
4909 fputs (">>", file); break;
4911 fputs (">>=", file); break;
4913 fputs ("<=", file); break;
4915 fputs ("<", file); break;
4917 fputs ("<<", file); break;
4919 fputs ("<<=", file); break;
4925 gcc_assert (GET_CODE (x) == CONST_INT);
4926 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4929 gcc_assert (GET_CODE (x) == CONST_INT);
4930 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4933 gcc_assert (GET_CODE (x) == CONST_INT);
4934 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4937 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
4938 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4941 gcc_assert (GET_CODE (x) == CONST_INT);
4942 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4945 gcc_assert (GET_CODE (x) == CONST_INT);
4946 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4949 if (GET_CODE (x) == CONST_INT)
4954 switch (GET_CODE (XEXP (x, 0)))
4958 if (ASSEMBLER_DIALECT == 0)
4959 fputs ("s,mb", file);
4961 fputs (",mb", file);
4965 if (ASSEMBLER_DIALECT == 0)
4966 fputs ("s,ma", file);
4968 fputs (",ma", file);
4971 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4972 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4974 if (ASSEMBLER_DIALECT == 0)
4977 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4978 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4980 if (ASSEMBLER_DIALECT == 0)
4981 fputs ("x,s", file);
4985 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4989 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4995 output_global_address (file, x, 0);
4998 output_global_address (file, x, 1);
5000 case 0: /* Don't do anything special */
5005 compute_zdepwi_operands (INTVAL (x), op);
5006 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5012 compute_zdepdi_operands (INTVAL (x), op);
5013 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5017 /* We can get here from a .vtable_inherit due to our
5018 CONSTANT_ADDRESS_P rejecting perfectly good constant
5024 if (GET_CODE (x) == REG)
5026 fputs (reg_names [REGNO (x)], file);
5027 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5033 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5034 && (REGNO (x) & 1) == 0)
5037 else if (GET_CODE (x) == MEM)
5039 int size = GET_MODE_SIZE (GET_MODE (x));
5040 rtx base = NULL_RTX;
5041 switch (GET_CODE (XEXP (x, 0)))
5045 base = XEXP (XEXP (x, 0), 0);
5046 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5050 base = XEXP (XEXP (x, 0), 0);
5051 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5054 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5055 fprintf (file, "%s(%s)",
5056 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5057 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5058 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5059 fprintf (file, "%s(%s)",
5060 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5061 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5062 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5063 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5065 /* Because the REG_POINTER flag can get lost during reload,
5066 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5067 index and base registers in the combined move patterns. */
5068 rtx base = XEXP (XEXP (x, 0), 1);
5069 rtx index = XEXP (XEXP (x, 0), 0);
5071 fprintf (file, "%s(%s)",
5072 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5075 output_address (XEXP (x, 0));
5078 output_address (XEXP (x, 0));
5083 output_addr_const (file, x);
5086 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5089 output_global_address (FILE *file, rtx x, int round_constant)
5092 /* Imagine (high (const (plus ...))). */
5093 if (GET_CODE (x) == HIGH)
5096 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5097 output_addr_const (file, x);
5098 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5100 output_addr_const (file, x);
5101 fputs ("-$global$", file);
5103 else if (GET_CODE (x) == CONST)
5105 const char *sep = "";
5106 int offset = 0; /* assembler wants -$global$ at end */
5107 rtx base = NULL_RTX;
5109 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5112 base = XEXP (XEXP (x, 0), 0);
5113 output_addr_const (file, base);
5116 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5122 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5125 base = XEXP (XEXP (x, 0), 1);
5126 output_addr_const (file, base);
5129 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5135 /* How bogus. The compiler is apparently responsible for
5136 rounding the constant if it uses an LR field selector.
5138 The linker and/or assembler seem a better place since
5139 they have to do this kind of thing already.
5141 If we fail to do this, HP's optimizing linker may eliminate
5142 an addil, but not update the ldw/stw/ldo instruction that
5143 uses the result of the addil. */
5145 offset = ((offset + 0x1000) & ~0x1fff);
5147 switch (GET_CODE (XEXP (x, 0)))
5160 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5168 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5169 fputs ("-$global$", file);
5171 fprintf (file, "%s%d", sep, offset);
5174 output_addr_const (file, x);
5177 /* Output boilerplate text to appear at the beginning of the file.
5178 There are several possible versions. */
5179 #define aputs(x) fputs(x, asm_out_file)
5181 pa_file_start_level (void)
5184 aputs ("\t.LEVEL 2.0w\n");
5185 else if (TARGET_PA_20)
5186 aputs ("\t.LEVEL 2.0\n");
5187 else if (TARGET_PA_11)
5188 aputs ("\t.LEVEL 1.1\n");
5190 aputs ("\t.LEVEL 1.0\n");
5194 pa_file_start_space (int sortspace)
5196 aputs ("\t.SPACE $PRIVATE$");
5199 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5200 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5201 "\n\t.SPACE $TEXT$");
5204 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5205 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5209 pa_file_start_file (int want_version)
5211 if (write_symbols != NO_DEBUG)
5213 output_file_directive (asm_out_file, main_input_filename);
5215 aputs ("\t.version\t\"01.01\"\n");
5220 pa_file_start_mcount (const char *aswhat)
5223 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5227 pa_elf_file_start (void)
5229 pa_file_start_level ();
5230 pa_file_start_mcount ("ENTRY");
5231 pa_file_start_file (0);
5235 pa_som_file_start (void)
5237 pa_file_start_level ();
5238 pa_file_start_space (0);
5239 aputs ("\t.IMPORT $global$,DATA\n"
5240 "\t.IMPORT $$dyncall,MILLICODE\n");
5241 pa_file_start_mcount ("CODE");
5242 pa_file_start_file (0);
5246 pa_linux_file_start (void)
5248 pa_file_start_file (1);
5249 pa_file_start_level ();
5250 pa_file_start_mcount ("CODE");
5254 pa_hpux64_gas_file_start (void)
5256 pa_file_start_level ();
5257 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5259 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5261 pa_file_start_file (1);
5265 pa_hpux64_hpas_file_start (void)
5267 pa_file_start_level ();
5268 pa_file_start_space (1);
5269 pa_file_start_mcount ("CODE");
5270 pa_file_start_file (0);
5274 /* Search the deferred plabel list for SYMBOL and return its internal
5275 label. If an entry for SYMBOL is not found, a new entry is created. */
5278 get_deferred_plabel (rtx symbol)
5280 const char *fname = XSTR (symbol, 0);
5283 /* See if we have already put this function on the list of deferred
5284 plabels. This list is generally small, so a liner search is not
5285 too ugly. If it proves too slow replace it with something faster. */
5286 for (i = 0; i < n_deferred_plabels; i++)
5287 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5290 /* If the deferred plabel list is empty, or this entry was not found
5291 on the list, create a new entry on the list. */
5292 if (deferred_plabels == NULL || i == n_deferred_plabels)
5296 if (deferred_plabels == 0)
5297 deferred_plabels = (struct deferred_plabel *)
5298 ggc_alloc (sizeof (struct deferred_plabel));
5300 deferred_plabels = (struct deferred_plabel *)
5301 ggc_realloc (deferred_plabels,
5302 ((n_deferred_plabels + 1)
5303 * sizeof (struct deferred_plabel)));
5305 i = n_deferred_plabels++;
5306 deferred_plabels[i].internal_label = gen_label_rtx ();
5307 deferred_plabels[i].symbol = symbol;
5309 /* Gross. We have just implicitly taken the address of this
5310 function. Mark it in the same manner as assemble_name. */
5311 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5313 mark_referenced (id);
5316 return deferred_plabels[i].internal_label;
5320 output_deferred_plabels (void)
5324 /* If we have some deferred plabels, then we need to switch into the
5325 data or readonly data section, and align it to a 4 byte boundary
5326 before outputting the deferred plabels. */
5327 if (n_deferred_plabels)
5329 switch_to_section (flag_pic ? data_section : readonly_data_section);
5330 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5333 /* Now output the deferred plabels. */
5334 for (i = 0; i < n_deferred_plabels; i++)
5336 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5337 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5338 assemble_integer (deferred_plabels[i].symbol,
5339 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5343 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5344 /* Initialize optabs to point to HPUX long double emulation routines. */
5346 pa_hpux_init_libfuncs (void)
5348 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5349 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5350 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5351 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5352 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5353 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5354 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5355 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5356 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5358 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5359 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5360 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5361 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5362 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5363 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5364 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5366 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5367 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5368 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5369 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5371 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5372 ? "__U_Qfcnvfxt_quad_to_sgl"
5373 : "_U_Qfcnvfxt_quad_to_sgl");
5374 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5375 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5376 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5378 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5379 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5380 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad");
5381 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad");
5385 /* HP's millicode routines mean something special to the assembler.
5386 Keep track of which ones we have used. */
5388 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5389 static void import_milli (enum millicodes);
5390 static char imported[(int) end1000];
5391 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5392 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5393 #define MILLI_START 10
5396 import_milli (enum millicodes code)
5398 char str[sizeof (import_string)];
5400 if (!imported[(int) code])
5402 imported[(int) code] = 1;
5403 strcpy (str, import_string);
5404 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5405 output_asm_insn (str, 0);
5409 /* The register constraints have put the operands and return value in
5410 the proper registers. */
5413 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5415 import_milli (mulI);
5416 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5419 /* Emit the rtl for doing a division by a constant. */
5421 /* Do magic division millicodes exist for this value? */
5422 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5424 /* We'll use an array to keep track of the magic millicodes and
5425 whether or not we've used them already. [n][0] is signed, [n][1] is
5428 static int div_milli[16][2];
5431 emit_hpdiv_const (rtx *operands, int unsignedp)
5433 if (GET_CODE (operands[2]) == CONST_INT
5434 && INTVAL (operands[2]) > 0
5435 && INTVAL (operands[2]) < 16
5436 && magic_milli[INTVAL (operands[2])])
5438 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5440 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5444 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5445 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5447 gen_rtx_REG (SImode, 26),
5449 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5450 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5451 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5452 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5453 gen_rtx_CLOBBER (VOIDmode, ret))));
5454 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5461 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5465 /* If the divisor is a constant, try to use one of the special
5467 if (GET_CODE (operands[0]) == CONST_INT)
5469 static char buf[100];
5470 divisor = INTVAL (operands[0]);
5471 if (!div_milli[divisor][unsignedp])
5473 div_milli[divisor][unsignedp] = 1;
5475 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5477 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5481 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5482 INTVAL (operands[0]));
5483 return output_millicode_call (insn,
5484 gen_rtx_SYMBOL_REF (SImode, buf));
5488 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5489 INTVAL (operands[0]));
5490 return output_millicode_call (insn,
5491 gen_rtx_SYMBOL_REF (SImode, buf));
5494 /* Divisor isn't a special constant. */
5499 import_milli (divU);
5500 return output_millicode_call (insn,
5501 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5505 import_milli (divI);
5506 return output_millicode_call (insn,
5507 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5512 /* Output a $$rem millicode to do mod. */
5515 output_mod_insn (int unsignedp, rtx insn)
5519 import_milli (remU);
5520 return output_millicode_call (insn,
5521 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5525 import_milli (remI);
5526 return output_millicode_call (insn,
5527 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5532 output_arg_descriptor (rtx call_insn)
5534 const char *arg_regs[4];
5535 enum machine_mode arg_mode;
5537 int i, output_flag = 0;
5540 /* We neither need nor want argument location descriptors for the
5541 64bit runtime environment or the ELF32 environment. */
5542 if (TARGET_64BIT || TARGET_ELF32)
5545 for (i = 0; i < 4; i++)
5548 /* Specify explicitly that no argument relocations should take place
5549 if using the portable runtime calling conventions. */
5550 if (TARGET_PORTABLE_RUNTIME)
5552 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5557 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5558 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5559 link; link = XEXP (link, 1))
5561 rtx use = XEXP (link, 0);
5563 if (! (GET_CODE (use) == USE
5564 && GET_CODE (XEXP (use, 0)) == REG
5565 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5568 arg_mode = GET_MODE (XEXP (use, 0));
5569 regno = REGNO (XEXP (use, 0));
5570 if (regno >= 23 && regno <= 26)
5572 arg_regs[26 - regno] = "GR";
5573 if (arg_mode == DImode)
5574 arg_regs[25 - regno] = "GR";
5576 else if (regno >= 32 && regno <= 39)
5578 if (arg_mode == SFmode)
5579 arg_regs[(regno - 32) / 2] = "FR";
5582 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5583 arg_regs[(regno - 34) / 2] = "FR";
5584 arg_regs[(regno - 34) / 2 + 1] = "FU";
5586 arg_regs[(regno - 34) / 2] = "FU";
5587 arg_regs[(regno - 34) / 2 + 1] = "FR";
5592 fputs ("\t.CALL ", asm_out_file);
5593 for (i = 0; i < 4; i++)
5598 fputc (',', asm_out_file);
5599 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5602 fputc ('\n', asm_out_file);
5605 static enum reg_class
5606 pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
5607 enum machine_mode mode, secondary_reload_info *sri)
5609 int is_symbolic, regno;
5611 /* Handle the easy stuff first. */
5612 if (class == R1_REGS)
5618 if (class == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5624 /* If we have something like (mem (mem (...)), we can safely assume the
5625 inner MEM will end up in a general register after reloading, so there's
5626 no need for a secondary reload. */
5627 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5630 /* Trying to load a constant into a FP register during PIC code
5631 generation requires %r1 as a scratch register. */
5633 && (mode == SImode || mode == DImode)
5634 && FP_REG_CLASS_P (class)
5635 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5637 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5638 : CODE_FOR_reload_indi_r1);
5642 /* Profiling showed the PA port spends about 1.3% of its compilation
5643 time in true_regnum from calls inside pa_secondary_reload_class. */
5644 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5645 regno = true_regnum (x);
5647 /* Handle out of range displacement for integer mode loads/stores of
5649 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5650 && GET_MODE_CLASS (mode) == MODE_INT
5651 && FP_REG_CLASS_P (class))
5652 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5654 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5658 /* A SAR<->FP register copy requires a secondary register (GPR) as
5659 well as secondary memory. */
5660 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5661 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5662 || (class == SHIFT_REGS
5663 && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5665 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5669 /* Secondary reloads of symbolic operands require %r1 as a scratch
5670 register when we're generating PIC code and the operand isn't
5672 if (GET_CODE (x) == HIGH)
5675 /* Profiling has showed GCC spends about 2.6% of its compilation
5676 time in symbolic_operand from calls inside pa_secondary_reload_class.
5677 So, we use an inline copy to avoid useless work. */
5678 switch (GET_CODE (x))
5683 is_symbolic = !SYMBOL_REF_TLS_MODEL (x);
5690 is_symbolic = (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5691 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
5692 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
5693 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5700 if (is_symbolic && (flag_pic || !read_only_operand (x, VOIDmode)))
5702 gcc_assert (mode == SImode || mode == DImode);
5703 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5704 : CODE_FOR_reload_indi_r1);
5710 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5711 by invisible reference. As a GCC extension, we also pass anything
5712 with a zero or variable size by reference.
5714 The 64-bit runtime does not describe passing any types by invisible
5715 reference. The internals of GCC can't currently handle passing
5716 empty structures, and zero or variable length arrays when they are
5717 not passed entirely on the stack or by reference. Thus, as a GCC
5718 extension, we pass these types by reference. The HP compiler doesn't
5719 support these types, so hopefully there shouldn't be any compatibility
5720 issues. This may have to be revisited when HP releases a C99 compiler
5721 or updates the ABI. */
5724 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5725 enum machine_mode mode, tree type,
5726 bool named ATTRIBUTE_UNUSED)
5731 size = int_size_in_bytes (type);
5733 size = GET_MODE_SIZE (mode);
5738 return size <= 0 || size > 8;
5742 function_arg_padding (enum machine_mode mode, tree type)
5745 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5747 /* Return none if justification is not required. */
5749 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5750 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5753 /* The directions set here are ignored when a BLKmode argument larger
5754 than a word is placed in a register. Different code is used for
5755 the stack and registers. This makes it difficult to have a
5756 consistent data representation for both the stack and registers.
5757 For both runtimes, the justification and padding for arguments on
5758 the stack and in registers should be identical. */
5760 /* The 64-bit runtime specifies left justification for aggregates. */
5763 /* The 32-bit runtime architecture specifies right justification.
5764 When the argument is passed on the stack, the argument is padded
5765 with garbage on the left. The HP compiler pads with zeros. */
5769 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5776 /* Do what is necessary for `va_start'. We look at the current function
5777 to determine if stdargs or varargs is used and fill in an initial
5778 va_list. A pointer to this constructor is returned. */
5781 hppa_builtin_saveregs (void)
5784 tree fntype = TREE_TYPE (current_function_decl);
5785 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5786 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5787 != void_type_node)))
5788 ? UNITS_PER_WORD : 0);
5791 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5793 offset = current_function_arg_offset_rtx;
5799 /* Adjust for varargs/stdarg differences. */
5801 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5803 offset = current_function_arg_offset_rtx;
5805 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5806 from the incoming arg pointer and growing to larger addresses. */
5807 for (i = 26, off = -64; i >= 19; i--, off += 8)
5808 emit_move_insn (gen_rtx_MEM (word_mode,
5809 plus_constant (arg_pointer_rtx, off)),
5810 gen_rtx_REG (word_mode, i));
5812 /* The incoming args pointer points just beyond the flushback area;
5813 normally this is not a serious concern. However, when we are doing
5814 varargs/stdargs we want to make the arg pointer point to the start
5815 of the incoming argument area. */
5816 emit_move_insn (virtual_incoming_args_rtx,
5817 plus_constant (arg_pointer_rtx, -64));
5819 /* Now return a pointer to the first anonymous argument. */
5820 return copy_to_reg (expand_binop (Pmode, add_optab,
5821 virtual_incoming_args_rtx,
5822 offset, 0, 0, OPTAB_LIB_WIDEN));
5825 /* Store general registers on the stack. */
5826 dest = gen_rtx_MEM (BLKmode,
5827 plus_constant (current_function_internal_arg_pointer,
5829 set_mem_alias_set (dest, get_varargs_alias_set ());
5830 set_mem_align (dest, BITS_PER_WORD);
5831 move_block_from_reg (23, dest, 4);
5833 /* move_block_from_reg will emit code to store the argument registers
5834 individually as scalar stores.
5836 However, other insns may later load from the same addresses for
5837 a structure load (passing a struct to a varargs routine).
5839 The alias code assumes that such aliasing can never happen, so we
5840 have to keep memory referencing insns from moving up beyond the
5841 last argument register store. So we emit a blockage insn here. */
5842 emit_insn (gen_blockage ());
5844 return copy_to_reg (expand_binop (Pmode, add_optab,
5845 current_function_internal_arg_pointer,
5846 offset, 0, 0, OPTAB_LIB_WIDEN));
5850 hppa_va_start (tree valist, rtx nextarg)
5852 nextarg = expand_builtin_saveregs ();
5853 std_expand_builtin_va_start (valist, nextarg);
5857 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5861 /* Args grow upward. We can use the generic routines. */
5862 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5864 else /* !TARGET_64BIT */
5866 tree ptr = build_pointer_type (type);
5869 unsigned int size, ofs;
5872 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5876 ptr = build_pointer_type (type);
5878 size = int_size_in_bytes (type);
5879 valist_type = TREE_TYPE (valist);
5881 /* Args grow down. Not handled by generic routines. */
5883 u = fold_convert (valist_type, size_in_bytes (type));
5884 t = build2 (MINUS_EXPR, valist_type, valist, u);
5886 /* Copied from va-pa.h, but we probably don't need to align to
5887 word size, since we generate and preserve that invariant. */
5888 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
5889 t = build2 (BIT_AND_EXPR, valist_type, t, u);
5891 t = build2 (MODIFY_EXPR, valist_type, valist, t);
5893 ofs = (8 - size) % 4;
5896 u = fold_convert (valist_type, size_int (ofs));
5897 t = build2 (PLUS_EXPR, valist_type, t, u);
5900 t = fold_convert (ptr, t);
5901 t = build_va_arg_indirect_ref (t);
5904 t = build_va_arg_indirect_ref (t);
5910 /* True if MODE is valid for the target. By "valid", we mean able to
5911 be manipulated in non-trivial ways. In particular, this means all
5912 the arithmetic is supported.
5914 Currently, TImode is not valid as the HP 64-bit runtime documentation
5915 doesn't document the alignment and calling conventions for this type.
5916 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
5917 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
5920 pa_scalar_mode_supported_p (enum machine_mode mode)
5922 int precision = GET_MODE_PRECISION (mode);
5924 switch (GET_MODE_CLASS (mode))
5926 case MODE_PARTIAL_INT:
5928 if (precision == CHAR_TYPE_SIZE)
5930 if (precision == SHORT_TYPE_SIZE)
5932 if (precision == INT_TYPE_SIZE)
5934 if (precision == LONG_TYPE_SIZE)
5936 if (precision == LONG_LONG_TYPE_SIZE)
5941 if (precision == FLOAT_TYPE_SIZE)
5943 if (precision == DOUBLE_TYPE_SIZE)
5945 if (precision == LONG_DOUBLE_TYPE_SIZE)
5949 case MODE_DECIMAL_FLOAT:
5957 /* This routine handles all the normal conditional branch sequences we
5958 might need to generate. It handles compare immediate vs compare
5959 register, nullification of delay slots, varying length branches,
5960 negated branches, and all combinations of the above. It returns the
5961 output appropriate to emit the branch corresponding to all given
5965 output_cbranch (rtx *operands, int negated, rtx insn)
5967 static char buf[100];
5969 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5970 int length = get_attr_length (insn);
5973 /* A conditional branch to the following instruction (e.g. the delay slot)
5974 is asking for a disaster. This can happen when not optimizing and
5975 when jump optimization fails.
5977 While it is usually safe to emit nothing, this can fail if the
5978 preceding instruction is a nullified branch with an empty delay
5979 slot and the same branch target as this branch. We could check
5980 for this but jump optimization should eliminate nop jumps. It
5981 is always safe to emit a nop. */
5982 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5985 /* The doubleword form of the cmpib instruction doesn't have the LEU
5986 and GTU conditions while the cmpb instruction does. Since we accept
5987 zero for cmpb, we must ensure that we use cmpb for the comparison. */
5988 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
5989 operands[2] = gen_rtx_REG (DImode, 0);
5990 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
5991 operands[1] = gen_rtx_REG (DImode, 0);
5993 /* If this is a long branch with its delay slot unfilled, set `nullify'
5994 as it can nullify the delay slot and save a nop. */
5995 if (length == 8 && dbr_sequence_length () == 0)
5998 /* If this is a short forward conditional branch which did not get
5999 its delay slot filled, the delay slot can still be nullified. */
6000 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6001 nullify = forward_branch_p (insn);
6003 /* A forward branch over a single nullified insn can be done with a
6004 comclr instruction. This avoids a single cycle penalty due to
6005 mis-predicted branch if we fall through (branch not taken). */
6007 && next_real_insn (insn) != 0
6008 && get_attr_length (next_real_insn (insn)) == 4
6009 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6015 /* All short conditional branches except backwards with an unfilled
6019 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6021 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6022 if (GET_MODE (operands[1]) == DImode)
6025 strcat (buf, "%B3");
6027 strcat (buf, "%S3");
6029 strcat (buf, " %2,%r1,%%r0");
6031 strcat (buf, ",n %2,%r1,%0");
6033 strcat (buf, " %2,%r1,%0");
6036 /* All long conditionals. Note a short backward branch with an
6037 unfilled delay slot is treated just like a long backward branch
6038 with an unfilled delay slot. */
6040 /* Handle weird backwards branch with a filled delay slot
6041 which is nullified. */
6042 if (dbr_sequence_length () != 0
6043 && ! forward_branch_p (insn)
6046 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6047 if (GET_MODE (operands[1]) == DImode)
6050 strcat (buf, "%S3");
6052 strcat (buf, "%B3");
6053 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6055 /* Handle short backwards branch with an unfilled delay slot.
6056 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6057 taken and untaken branches. */
6058 else if (dbr_sequence_length () == 0
6059 && ! forward_branch_p (insn)
6060 && INSN_ADDRESSES_SET_P ()
6061 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6062 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6064 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6065 if (GET_MODE (operands[1]) == DImode)
6068 strcat (buf, "%B3 %2,%r1,%0%#");
6070 strcat (buf, "%S3 %2,%r1,%0%#");
6074 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6075 if (GET_MODE (operands[1]) == DImode)
6078 strcat (buf, "%S3");
6080 strcat (buf, "%B3");
6082 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6084 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6089 /* The reversed conditional branch must branch over one additional
6090 instruction if the delay slot is filled and needs to be extracted
6091 by output_lbranch. If the delay slot is empty or this is a
6092 nullified forward branch, the instruction after the reversed
6093 condition branch must be nullified. */
6094 if (dbr_sequence_length () == 0
6095 || (nullify && forward_branch_p (insn)))
6099 operands[4] = GEN_INT (length);
6104 operands[4] = GEN_INT (length + 4);
6107 /* Create a reversed conditional branch which branches around
6108 the following insns. */
6109 if (GET_MODE (operands[1]) != DImode)
6115 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6118 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6124 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6127 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6136 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6139 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6145 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6148 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6152 output_asm_insn (buf, operands);
6153 return output_lbranch (operands[0], insn, xdelay);
6158 /* This routine handles output of long unconditional branches that
6159 exceed the maximum range of a simple branch instruction. Since
6160 we don't have a register available for the branch, we save register
6161 %r1 in the frame marker, load the branch destination DEST into %r1,
6162 execute the branch, and restore %r1 in the delay slot of the branch.
6164 Since long branches may have an insn in the delay slot and the
6165 delay slot is used to restore %r1, we in general need to extract
6166 this insn and execute it before the branch. However, to facilitate
6167 use of this function by conditional branches, we also provide an
6168 option to not extract the delay insn so that it will be emitted
6169 after the long branch. So, if there is an insn in the delay slot,
6170 it is extracted if XDELAY is nonzero.
6172 The lengths of the various long-branch sequences are 20, 16 and 24
6173 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6176 output_lbranch (rtx dest, rtx insn, int xdelay)
6180 xoperands[0] = dest;
6182 /* First, free up the delay slot. */
6183 if (xdelay && dbr_sequence_length () != 0)
6185 /* We can't handle a jump in the delay slot. */
6186 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6188 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6191 /* Now delete the delay insn. */
6192 PUT_CODE (NEXT_INSN (insn), NOTE);
6193 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6194 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6197 /* Output an insn to save %r1. The runtime documentation doesn't
6198 specify whether the "Clean Up" slot in the callers frame can
6199 be clobbered by the callee. It isn't copied by HP's builtin
6200 alloca, so this suggests that it can be clobbered if necessary.
6201 The "Static Link" location is copied by HP builtin alloca, so
6202 we avoid using it. Using the cleanup slot might be a problem
6203 if we have to interoperate with languages that pass cleanup
6204 information. However, it should be possible to handle these
6205 situations with GCC's asm feature.
6207 The "Current RP" slot is reserved for the called procedure, so
6208 we try to use it when we don't have a frame of our own. It's
6209 rather unlikely that we won't have a frame when we need to emit
6212 Really the way to go long term is a register scavenger; goto
6213 the target of the jump and find a register which we can use
6214 as a scratch to hold the value in %r1. Then, we wouldn't have
6215 to free up the delay slot or clobber a slot that may be needed
6216 for other purposes. */
6219 if (actual_fsize == 0 && !regs_ever_live[2])
6220 /* Use the return pointer slot in the frame marker. */
6221 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6223 /* Use the slot at -40 in the frame marker since HP builtin
6224 alloca doesn't copy it. */
6225 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6229 if (actual_fsize == 0 && !regs_ever_live[2])
6230 /* Use the return pointer slot in the frame marker. */
6231 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6233 /* Use the "Clean Up" slot in the frame marker. In GCC,
6234 the only other use of this location is for copying a
6235 floating point double argument from a floating-point
6236 register to two general registers. The copy is done
6237 as an "atomic" operation when outputting a call, so it
6238 won't interfere with our using the location here. */
6239 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6242 if (TARGET_PORTABLE_RUNTIME)
6244 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6245 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6246 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6250 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6251 if (TARGET_SOM || !TARGET_GAS)
6253 xoperands[1] = gen_label_rtx ();
6254 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6255 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6256 CODE_LABEL_NUMBER (xoperands[1]));
6257 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6261 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6262 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6264 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6267 /* Now output a very long branch to the original target. */
6268 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6270 /* Now restore the value of %r1 in the delay slot. */
6273 if (actual_fsize == 0 && !regs_ever_live[2])
6274 return "ldd -16(%%r30),%%r1";
6276 return "ldd -40(%%r30),%%r1";
6280 if (actual_fsize == 0 && !regs_ever_live[2])
6281 return "ldw -20(%%r30),%%r1";
6283 return "ldw -12(%%r30),%%r1";
6287 /* This routine handles all the branch-on-bit conditional branch sequences we
6288 might need to generate. It handles nullification of delay slots,
6289 varying length branches, negated branches and all combinations of the
6290 above. it returns the appropriate output template to emit the branch. */
6293 output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6295 static char buf[100];
6297 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6298 int length = get_attr_length (insn);
6301 /* A conditional branch to the following instruction (e.g. the delay slot) is
6302 asking for a disaster. I do not think this can happen as this pattern
6303 is only used when optimizing; jump optimization should eliminate the
6304 jump. But be prepared just in case. */
6306 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6309 /* If this is a long branch with its delay slot unfilled, set `nullify'
6310 as it can nullify the delay slot and save a nop. */
6311 if (length == 8 && dbr_sequence_length () == 0)
6314 /* If this is a short forward conditional branch which did not get
6315 its delay slot filled, the delay slot can still be nullified. */
6316 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6317 nullify = forward_branch_p (insn);
6319 /* A forward branch over a single nullified insn can be done with a
6320 extrs instruction. This avoids a single cycle penalty due to
6321 mis-predicted branch if we fall through (branch not taken). */
6324 && next_real_insn (insn) != 0
6325 && get_attr_length (next_real_insn (insn)) == 4
6326 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6333 /* All short conditional branches except backwards with an unfilled
6337 strcpy (buf, "{extrs,|extrw,s,}");
6339 strcpy (buf, "bb,");
6340 if (useskip && GET_MODE (operands[0]) == DImode)
6341 strcpy (buf, "extrd,s,*");
6342 else if (GET_MODE (operands[0]) == DImode)
6343 strcpy (buf, "bb,*");
6344 if ((which == 0 && negated)
6345 || (which == 1 && ! negated))
6350 strcat (buf, " %0,%1,1,%%r0");
6351 else if (nullify && negated)
6352 strcat (buf, ",n %0,%1,%3");
6353 else if (nullify && ! negated)
6354 strcat (buf, ",n %0,%1,%2");
6355 else if (! nullify && negated)
6356 strcat (buf, "%0,%1,%3");
6357 else if (! nullify && ! negated)
6358 strcat (buf, " %0,%1,%2");
6361 /* All long conditionals. Note a short backward branch with an
6362 unfilled delay slot is treated just like a long backward branch
6363 with an unfilled delay slot. */
6365 /* Handle weird backwards branch with a filled delay slot
6366 which is nullified. */
6367 if (dbr_sequence_length () != 0
6368 && ! forward_branch_p (insn)
6371 strcpy (buf, "bb,");
6372 if (GET_MODE (operands[0]) == DImode)
6374 if ((which == 0 && negated)
6375 || (which == 1 && ! negated))
6380 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6382 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6384 /* Handle short backwards branch with an unfilled delay slot.
6385 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6386 taken and untaken branches. */
6387 else if (dbr_sequence_length () == 0
6388 && ! forward_branch_p (insn)
6389 && INSN_ADDRESSES_SET_P ()
6390 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6391 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6393 strcpy (buf, "bb,");
6394 if (GET_MODE (operands[0]) == DImode)
6396 if ((which == 0 && negated)
6397 || (which == 1 && ! negated))
6402 strcat (buf, " %0,%1,%3%#");
6404 strcat (buf, " %0,%1,%2%#");
6408 if (GET_MODE (operands[0]) == DImode)
6409 strcpy (buf, "extrd,s,*");
6411 strcpy (buf, "{extrs,|extrw,s,}");
6412 if ((which == 0 && negated)
6413 || (which == 1 && ! negated))
6417 if (nullify && negated)
6418 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6419 else if (nullify && ! negated)
6420 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6422 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6424 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6429 /* The reversed conditional branch must branch over one additional
6430 instruction if the delay slot is filled and needs to be extracted
6431 by output_lbranch. If the delay slot is empty or this is a
6432 nullified forward branch, the instruction after the reversed
6433 condition branch must be nullified. */
6434 if (dbr_sequence_length () == 0
6435 || (nullify && forward_branch_p (insn)))
6439 operands[4] = GEN_INT (length);
6444 operands[4] = GEN_INT (length + 4);
6447 if (GET_MODE (operands[0]) == DImode)
6448 strcpy (buf, "bb,*");
6450 strcpy (buf, "bb,");
6451 if ((which == 0 && negated)
6452 || (which == 1 && !negated))
6457 strcat (buf, ",n %0,%1,.+%4");
6459 strcat (buf, " %0,%1,.+%4");
6460 output_asm_insn (buf, operands);
6461 return output_lbranch (negated ? operands[3] : operands[2],
6467 /* This routine handles all the branch-on-variable-bit conditional branch
6468 sequences we might need to generate. It handles nullification of delay
6469 slots, varying length branches, negated branches and all combinations
6470 of the above. it returns the appropriate output template to emit the
6474 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6476 static char buf[100];
6478 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6479 int length = get_attr_length (insn);
6482 /* A conditional branch to the following instruction (e.g. the delay slot) is
6483 asking for a disaster. I do not think this can happen as this pattern
6484 is only used when optimizing; jump optimization should eliminate the
6485 jump. But be prepared just in case. */
6487 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6490 /* If this is a long branch with its delay slot unfilled, set `nullify'
6491 as it can nullify the delay slot and save a nop. */
6492 if (length == 8 && dbr_sequence_length () == 0)
6495 /* If this is a short forward conditional branch which did not get
6496 its delay slot filled, the delay slot can still be nullified. */
6497 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6498 nullify = forward_branch_p (insn);
6500 /* A forward branch over a single nullified insn can be done with a
6501 extrs instruction. This avoids a single cycle penalty due to
6502 mis-predicted branch if we fall through (branch not taken). */
6505 && next_real_insn (insn) != 0
6506 && get_attr_length (next_real_insn (insn)) == 4
6507 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6514 /* All short conditional branches except backwards with an unfilled
6518 strcpy (buf, "{vextrs,|extrw,s,}");
6520 strcpy (buf, "{bvb,|bb,}");
6521 if (useskip && GET_MODE (operands[0]) == DImode)
6522 strcpy (buf, "extrd,s,*");
6523 else if (GET_MODE (operands[0]) == DImode)
6524 strcpy (buf, "bb,*");
6525 if ((which == 0 && negated)
6526 || (which == 1 && ! negated))
6531 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6532 else if (nullify && negated)
6533 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6534 else if (nullify && ! negated)
6535 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6536 else if (! nullify && negated)
6537 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6538 else if (! nullify && ! negated)
6539 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6542 /* All long conditionals. Note a short backward branch with an
6543 unfilled delay slot is treated just like a long backward branch
6544 with an unfilled delay slot. */
6546 /* Handle weird backwards branch with a filled delay slot
6547 which is nullified. */
6548 if (dbr_sequence_length () != 0
6549 && ! forward_branch_p (insn)
6552 strcpy (buf, "{bvb,|bb,}");
6553 if (GET_MODE (operands[0]) == DImode)
6555 if ((which == 0 && negated)
6556 || (which == 1 && ! negated))
6561 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6563 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6565 /* Handle short backwards branch with an unfilled delay slot.
6566 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6567 taken and untaken branches. */
6568 else if (dbr_sequence_length () == 0
6569 && ! forward_branch_p (insn)
6570 && INSN_ADDRESSES_SET_P ()
6571 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6572 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6574 strcpy (buf, "{bvb,|bb,}");
6575 if (GET_MODE (operands[0]) == DImode)
6577 if ((which == 0 && negated)
6578 || (which == 1 && ! negated))
6583 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6585 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6589 strcpy (buf, "{vextrs,|extrw,s,}");
6590 if (GET_MODE (operands[0]) == DImode)
6591 strcpy (buf, "extrd,s,*");
6592 if ((which == 0 && negated)
6593 || (which == 1 && ! negated))
6597 if (nullify && negated)
6598 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6599 else if (nullify && ! negated)
6600 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6602 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6604 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6609 /* The reversed conditional branch must branch over one additional
6610 instruction if the delay slot is filled and needs to be extracted
6611 by output_lbranch. If the delay slot is empty or this is a
6612 nullified forward branch, the instruction after the reversed
6613 condition branch must be nullified. */
6614 if (dbr_sequence_length () == 0
6615 || (nullify && forward_branch_p (insn)))
6619 operands[4] = GEN_INT (length);
6624 operands[4] = GEN_INT (length + 4);
6627 if (GET_MODE (operands[0]) == DImode)
6628 strcpy (buf, "bb,*");
6630 strcpy (buf, "{bvb,|bb,}");
6631 if ((which == 0 && negated)
6632 || (which == 1 && !negated))
6637 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
6639 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
6640 output_asm_insn (buf, operands);
6641 return output_lbranch (negated ? operands[3] : operands[2],
6647 /* Return the output template for emitting a dbra type insn.
6649 Note it may perform some output operations on its own before
6650 returning the final output string. */
6652 output_dbra (rtx *operands, rtx insn, int which_alternative)
6654 int length = get_attr_length (insn);
6656 /* A conditional branch to the following instruction (e.g. the delay slot) is
6657 asking for a disaster. Be prepared! */
6659 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6661 if (which_alternative == 0)
6662 return "ldo %1(%0),%0";
6663 else if (which_alternative == 1)
6665 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6666 output_asm_insn ("ldw -16(%%r30),%4", operands);
6667 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6668 return "{fldws|fldw} -16(%%r30),%0";
6672 output_asm_insn ("ldw %0,%4", operands);
6673 return "ldo %1(%4),%4\n\tstw %4,%0";
6677 if (which_alternative == 0)
6679 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6682 /* If this is a long branch with its delay slot unfilled, set `nullify'
6683 as it can nullify the delay slot and save a nop. */
6684 if (length == 8 && dbr_sequence_length () == 0)
6687 /* If this is a short forward conditional branch which did not get
6688 its delay slot filled, the delay slot can still be nullified. */
6689 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6690 nullify = forward_branch_p (insn);
6696 return "addib,%C2,n %1,%0,%3";
6698 return "addib,%C2 %1,%0,%3";
6701 /* Handle weird backwards branch with a fulled delay slot
6702 which is nullified. */
6703 if (dbr_sequence_length () != 0
6704 && ! forward_branch_p (insn)
6706 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6707 /* Handle short backwards branch with an unfilled delay slot.
6708 Using a addb;nop rather than addi;bl saves 1 cycle for both
6709 taken and untaken branches. */
6710 else if (dbr_sequence_length () == 0
6711 && ! forward_branch_p (insn)
6712 && INSN_ADDRESSES_SET_P ()
6713 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6714 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6715 return "addib,%C2 %1,%0,%3%#";
6717 /* Handle normal cases. */
6719 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6721 return "addi,%N2 %1,%0,%0\n\tb %3";
6724 /* The reversed conditional branch must branch over one additional
6725 instruction if the delay slot is filled and needs to be extracted
6726 by output_lbranch. If the delay slot is empty or this is a
6727 nullified forward branch, the instruction after the reversed
6728 condition branch must be nullified. */
6729 if (dbr_sequence_length () == 0
6730 || (nullify && forward_branch_p (insn)))
6734 operands[4] = GEN_INT (length);
6739 operands[4] = GEN_INT (length + 4);
6743 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
6745 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
6747 return output_lbranch (operands[3], insn, xdelay);
6751 /* Deal with gross reload from FP register case. */
6752 else if (which_alternative == 1)
6754 /* Move loop counter from FP register to MEM then into a GR,
6755 increment the GR, store the GR into MEM, and finally reload
6756 the FP register from MEM from within the branch's delay slot. */
6757 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6759 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6761 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6762 else if (length == 28)
6763 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6766 operands[5] = GEN_INT (length - 16);
6767 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
6768 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
6769 return output_lbranch (operands[3], insn, 0);
6772 /* Deal with gross reload from memory case. */
6775 /* Reload loop counter from memory, the store back to memory
6776 happens in the branch's delay slot. */
6777 output_asm_insn ("ldw %0,%4", operands);
6779 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6780 else if (length == 16)
6781 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6784 operands[5] = GEN_INT (length - 4);
6785 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
6786 return output_lbranch (operands[3], insn, 0);
6791 /* Return the output template for emitting a movb type insn.
6793 Note it may perform some output operations on its own before
6794 returning the final output string. */
6796 output_movb (rtx *operands, rtx insn, int which_alternative,
6797 int reverse_comparison)
6799 int length = get_attr_length (insn);
6801 /* A conditional branch to the following instruction (e.g. the delay slot) is
6802 asking for a disaster. Be prepared! */
6804 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6806 if (which_alternative == 0)
6807 return "copy %1,%0";
6808 else if (which_alternative == 1)
6810 output_asm_insn ("stw %1,-16(%%r30)", operands);
6811 return "{fldws|fldw} -16(%%r30),%0";
6813 else if (which_alternative == 2)
6819 /* Support the second variant. */
6820 if (reverse_comparison)
6821 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6823 if (which_alternative == 0)
6825 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6828 /* If this is a long branch with its delay slot unfilled, set `nullify'
6829 as it can nullify the delay slot and save a nop. */
6830 if (length == 8 && dbr_sequence_length () == 0)
6833 /* If this is a short forward conditional branch which did not get
6834 its delay slot filled, the delay slot can still be nullified. */
6835 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6836 nullify = forward_branch_p (insn);
6842 return "movb,%C2,n %1,%0,%3";
6844 return "movb,%C2 %1,%0,%3";
6847 /* Handle weird backwards branch with a filled delay slot
6848 which is nullified. */
6849 if (dbr_sequence_length () != 0
6850 && ! forward_branch_p (insn)
6852 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6854 /* Handle short backwards branch with an unfilled delay slot.
6855 Using a movb;nop rather than or;bl saves 1 cycle for both
6856 taken and untaken branches. */
6857 else if (dbr_sequence_length () == 0
6858 && ! forward_branch_p (insn)
6859 && INSN_ADDRESSES_SET_P ()
6860 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6861 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6862 return "movb,%C2 %1,%0,%3%#";
6863 /* Handle normal cases. */
6865 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6867 return "or,%N2 %1,%%r0,%0\n\tb %3";
6870 /* The reversed conditional branch must branch over one additional
6871 instruction if the delay slot is filled and needs to be extracted
6872 by output_lbranch. If the delay slot is empty or this is a
6873 nullified forward branch, the instruction after the reversed
6874 condition branch must be nullified. */
6875 if (dbr_sequence_length () == 0
6876 || (nullify && forward_branch_p (insn)))
6880 operands[4] = GEN_INT (length);
6885 operands[4] = GEN_INT (length + 4);
6889 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
6891 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
6893 return output_lbranch (operands[3], insn, xdelay);
6896 /* Deal with gross reload for FP destination register case. */
6897 else if (which_alternative == 1)
6899 /* Move source register to MEM, perform the branch test, then
6900 finally load the FP register from MEM from within the branch's
6902 output_asm_insn ("stw %1,-16(%%r30)", operands);
6904 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6905 else if (length == 16)
6906 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6909 operands[4] = GEN_INT (length - 4);
6910 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
6911 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
6912 return output_lbranch (operands[3], insn, 0);
6915 /* Deal with gross reload from memory case. */
6916 else if (which_alternative == 2)
6918 /* Reload loop counter from memory, the store back to memory
6919 happens in the branch's delay slot. */
6921 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6922 else if (length == 12)
6923 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6926 operands[4] = GEN_INT (length);
6927 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
6929 return output_lbranch (operands[3], insn, 0);
6932 /* Handle SAR as a destination. */
6936 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6937 else if (length == 12)
6938 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6941 operands[4] = GEN_INT (length);
6942 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
6944 return output_lbranch (operands[3], insn, 0);
6949 /* Copy any FP arguments in INSN into integer registers. */
6951 copy_fp_args (rtx insn)
6956 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6958 int arg_mode, regno;
6959 rtx use = XEXP (link, 0);
6961 if (! (GET_CODE (use) == USE
6962 && GET_CODE (XEXP (use, 0)) == REG
6963 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6966 arg_mode = GET_MODE (XEXP (use, 0));
6967 regno = REGNO (XEXP (use, 0));
6969 /* Is it a floating point register? */
6970 if (regno >= 32 && regno <= 39)
6972 /* Copy the FP register into an integer register via memory. */
6973 if (arg_mode == SFmode)
6975 xoperands[0] = XEXP (use, 0);
6976 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6977 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6978 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6982 xoperands[0] = XEXP (use, 0);
6983 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6984 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6985 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6986 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6992 /* Compute length of the FP argument copy sequence for INSN. */
6994 length_fp_args (rtx insn)
6999 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7001 int arg_mode, regno;
7002 rtx use = XEXP (link, 0);
7004 if (! (GET_CODE (use) == USE
7005 && GET_CODE (XEXP (use, 0)) == REG
7006 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7009 arg_mode = GET_MODE (XEXP (use, 0));
7010 regno = REGNO (XEXP (use, 0));
7012 /* Is it a floating point register? */
7013 if (regno >= 32 && regno <= 39)
7015 if (arg_mode == SFmode)
7025 /* Return the attribute length for the millicode call instruction INSN.
7026 The length must match the code generated by output_millicode_call.
7027 We include the delay slot in the returned length as it is better to
7028 over estimate the length than to under estimate it. */
7031 attr_length_millicode_call (rtx insn)
7033 unsigned long distance = -1;
7034 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7036 if (INSN_ADDRESSES_SET_P ())
7038 distance = (total + insn_current_reference_address (insn));
7039 if (distance < total)
7045 if (!TARGET_LONG_CALLS && distance < 7600000)
7050 else if (TARGET_PORTABLE_RUNTIME)
7054 if (!TARGET_LONG_CALLS && distance < 240000)
7057 if (TARGET_LONG_ABS_CALL && !flag_pic)
7064 /* INSN is a function call. It may have an unconditional jump
7067 CALL_DEST is the routine we are calling. */
7070 output_millicode_call (rtx insn, rtx call_dest)
7072 int attr_length = get_attr_length (insn);
7073 int seq_length = dbr_sequence_length ();
7078 xoperands[0] = call_dest;
7079 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7081 /* Handle the common case where we are sure that the branch will
7082 reach the beginning of the $CODE$ subspace. The within reach
7083 form of the $$sh_func_adrs call has a length of 28. Because
7084 it has an attribute type of multi, it never has a nonzero
7085 sequence length. The length of the $$sh_func_adrs is the same
7086 as certain out of reach PIC calls to other routines. */
7087 if (!TARGET_LONG_CALLS
7088 && ((seq_length == 0
7089 && (attr_length == 12
7090 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7091 || (seq_length != 0 && attr_length == 8)))
7093 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7099 /* It might seem that one insn could be saved by accessing
7100 the millicode function using the linkage table. However,
7101 this doesn't work in shared libraries and other dynamically
7102 loaded objects. Using a pc-relative sequence also avoids
7103 problems related to the implicit use of the gp register. */
7104 output_asm_insn ("b,l .+8,%%r1", xoperands);
7108 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7109 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7113 xoperands[1] = gen_label_rtx ();
7114 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7115 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7116 CODE_LABEL_NUMBER (xoperands[1]));
7117 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7120 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7122 else if (TARGET_PORTABLE_RUNTIME)
7124 /* Pure portable runtime doesn't allow be/ble; we also don't
7125 have PIC support in the assembler/linker, so this sequence
7128 /* Get the address of our target into %r1. */
7129 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7130 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7132 /* Get our return address into %r31. */
7133 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7134 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7136 /* Jump to our target address in %r1. */
7137 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7141 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7143 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7145 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7149 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7150 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7152 if (TARGET_SOM || !TARGET_GAS)
7154 /* The HP assembler can generate relocations for the
7155 difference of two symbols. GAS can do this for a
7156 millicode symbol but not an arbitrary external
7157 symbol when generating SOM output. */
7158 xoperands[1] = gen_label_rtx ();
7159 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7160 CODE_LABEL_NUMBER (xoperands[1]));
7161 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7162 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7166 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7167 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7171 /* Jump to our target address in %r1. */
7172 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7176 if (seq_length == 0)
7177 output_asm_insn ("nop", xoperands);
7179 /* We are done if there isn't a jump in the delay slot. */
7180 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7183 /* This call has an unconditional jump in its delay slot. */
7184 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7186 /* See if the return address can be adjusted. Use the containing
7187 sequence insn's address. */
7188 if (INSN_ADDRESSES_SET_P ())
7190 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7191 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7192 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7194 if (VAL_14_BITS_P (distance))
7196 xoperands[1] = gen_label_rtx ();
7197 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7198 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7199 CODE_LABEL_NUMBER (xoperands[1]));
7202 /* ??? This branch may not reach its target. */
7203 output_asm_insn ("nop\n\tb,n %0", xoperands);
7206 /* ??? This branch may not reach its target. */
7207 output_asm_insn ("nop\n\tb,n %0", xoperands);
7209 /* Delete the jump. */
7210 PUT_CODE (NEXT_INSN (insn), NOTE);
7211 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7212 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7217 /* Return the attribute length of the call instruction INSN. The SIBCALL
7218 flag indicates whether INSN is a regular call or a sibling call. The
7219 length returned must be longer than the code actually generated by
7220 output_call. Since branch shortening is done before delay branch
7221 sequencing, there is no way to determine whether or not the delay
7222 slot will be filled during branch shortening. Even when the delay
7223 slot is filled, we may have to add a nop if the delay slot contains
7224 a branch that can't reach its target. Thus, we always have to include
7225 the delay slot in the length estimate. This used to be done in
7226 pa_adjust_insn_length but we do it here now as some sequences always
7227 fill the delay slot and we can save four bytes in the estimate for
7231 attr_length_call (rtx insn, int sibcall)
7237 rtx pat = PATTERN (insn);
7238 unsigned long distance = -1;
7240 if (INSN_ADDRESSES_SET_P ())
7242 unsigned long total;
7244 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7245 distance = (total + insn_current_reference_address (insn));
7246 if (distance < total)
7250 /* Determine if this is a local call. */
7251 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7252 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7254 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7256 call_decl = SYMBOL_REF_DECL (call_dest);
7257 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7259 /* pc-relative branch. */
7260 if (!TARGET_LONG_CALLS
7261 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7262 || distance < 240000))
7265 /* 64-bit plabel sequence. */
7266 else if (TARGET_64BIT && !local_call)
7267 length += sibcall ? 28 : 24;
7269 /* non-pic long absolute branch sequence. */
7270 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7273 /* long pc-relative branch sequence. */
7274 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7275 || (TARGET_64BIT && !TARGET_GAS)
7276 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7280 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7284 /* 32-bit plabel sequence. */
7290 length += length_fp_args (insn);
7300 if (!TARGET_NO_SPACE_REGS)
7308 /* INSN is a function call. It may have an unconditional jump
7311 CALL_DEST is the routine we are calling. */
7314 output_call (rtx insn, rtx call_dest, int sibcall)
7316 int delay_insn_deleted = 0;
7317 int delay_slot_filled = 0;
7318 int seq_length = dbr_sequence_length ();
7319 tree call_decl = SYMBOL_REF_DECL (call_dest);
7320 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7323 xoperands[0] = call_dest;
7325 /* Handle the common case where we're sure that the branch will reach
7326 the beginning of the "$CODE$" subspace. This is the beginning of
7327 the current function if we are in a named section. */
7328 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7330 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7331 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7335 if (TARGET_64BIT && !local_call)
7337 /* ??? As far as I can tell, the HP linker doesn't support the
7338 long pc-relative sequence described in the 64-bit runtime
7339 architecture. So, we use a slightly longer indirect call. */
7340 xoperands[0] = get_deferred_plabel (call_dest);
7341 xoperands[1] = gen_label_rtx ();
7343 /* If this isn't a sibcall, we put the load of %r27 into the
7344 delay slot. We can't do this in a sibcall as we don't
7345 have a second call-clobbered scratch register available. */
7347 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7350 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7353 /* Now delete the delay insn. */
7354 PUT_CODE (NEXT_INSN (insn), NOTE);
7355 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7356 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7357 delay_insn_deleted = 1;
7360 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7361 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7362 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7366 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7367 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7368 output_asm_insn ("bve (%%r1)", xoperands);
7372 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7373 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7374 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7375 delay_slot_filled = 1;
7380 int indirect_call = 0;
7382 /* Emit a long call. There are several different sequences
7383 of increasing length and complexity. In most cases,
7384 they don't allow an instruction in the delay slot. */
7385 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7386 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7387 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7392 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7394 && (!TARGET_PA_20 || indirect_call))
7396 /* A non-jump insn in the delay slot. By definition we can
7397 emit this insn before the call (and in fact before argument
7399 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7402 /* Now delete the delay insn. */
7403 PUT_CODE (NEXT_INSN (insn), NOTE);
7404 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7405 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7406 delay_insn_deleted = 1;
7409 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7411 /* This is the best sequence for making long calls in
7412 non-pic code. Unfortunately, GNU ld doesn't provide
7413 the stub needed for external calls, and GAS's support
7414 for this with the SOM linker is buggy. It is safe
7415 to use this for local calls. */
7416 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7418 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7422 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7425 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7427 output_asm_insn ("copy %%r31,%%r2", xoperands);
7428 delay_slot_filled = 1;
7433 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7434 || (TARGET_64BIT && !TARGET_GAS))
7436 /* The HP assembler and linker can handle relocations
7437 for the difference of two symbols. GAS and the HP
7438 linker can't do this when one of the symbols is
7440 xoperands[1] = gen_label_rtx ();
7441 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7442 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7443 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7444 CODE_LABEL_NUMBER (xoperands[1]));
7445 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7447 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7449 /* GAS currently can't generate the relocations that
7450 are needed for the SOM linker under HP-UX using this
7451 sequence. The GNU linker doesn't generate the stubs
7452 that are needed for external calls on TARGET_ELF32
7453 with this sequence. For now, we have to use a
7454 longer plabel sequence when using GAS. */
7455 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7456 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7458 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7463 /* Emit a long plabel-based call sequence. This is
7464 essentially an inline implementation of $$dyncall.
7465 We don't actually try to call $$dyncall as this is
7466 as difficult as calling the function itself. */
7467 xoperands[0] = get_deferred_plabel (call_dest);
7468 xoperands[1] = gen_label_rtx ();
7470 /* Since the call is indirect, FP arguments in registers
7471 need to be copied to the general registers. Then, the
7472 argument relocation stub will copy them back. */
7474 copy_fp_args (insn);
7478 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7479 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7480 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7484 output_asm_insn ("addil LR'%0-$global$,%%r27",
7486 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7490 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7491 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7492 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7493 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7495 if (!sibcall && !TARGET_PA_20)
7497 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7498 if (TARGET_NO_SPACE_REGS)
7499 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7501 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7508 output_asm_insn ("bve (%%r1)", xoperands);
7513 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7514 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7515 delay_slot_filled = 1;
7518 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7523 if (!TARGET_NO_SPACE_REGS)
7524 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7529 if (TARGET_NO_SPACE_REGS)
7530 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7532 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7536 if (TARGET_NO_SPACE_REGS)
7537 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7539 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7542 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7544 output_asm_insn ("copy %%r31,%%r2", xoperands);
7545 delay_slot_filled = 1;
7552 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7553 output_asm_insn ("nop", xoperands);
7555 /* We are done if there isn't a jump in the delay slot. */
7557 || delay_insn_deleted
7558 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7561 /* A sibcall should never have a branch in the delay slot. */
7562 gcc_assert (!sibcall);
7564 /* This call has an unconditional jump in its delay slot. */
7565 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7567 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7569 /* See if the return address can be adjusted. Use the containing
7570 sequence insn's address. */
7571 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7572 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7573 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7575 if (VAL_14_BITS_P (distance))
7577 xoperands[1] = gen_label_rtx ();
7578 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7579 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7580 CODE_LABEL_NUMBER (xoperands[1]));
7583 output_asm_insn ("nop\n\tb,n %0", xoperands);
7586 output_asm_insn ("b,n %0", xoperands);
7588 /* Delete the jump. */
7589 PUT_CODE (NEXT_INSN (insn), NOTE);
7590 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7591 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7596 /* Return the attribute length of the indirect call instruction INSN.
7597 The length must match the code generated by output_indirect call.
7598 The returned length includes the delay slot. Currently, the delay
7599 slot of an indirect call sequence is not exposed and it is used by
7600 the sequence itself. */
7603 attr_length_indirect_call (rtx insn)
7605 unsigned long distance = -1;
7606 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7608 if (INSN_ADDRESSES_SET_P ())
7610 distance = (total + insn_current_reference_address (insn));
7611 if (distance < total)
7618 if (TARGET_FAST_INDIRECT_CALLS
7619 || (!TARGET_PORTABLE_RUNTIME
7620 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
7621 || distance < 240000)))
7627 if (TARGET_PORTABLE_RUNTIME)
7630 /* Out of reach, can use ble. */
7635 output_indirect_call (rtx insn, rtx call_dest)
7641 xoperands[0] = call_dest;
7642 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7643 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7647 /* First the special case for kernels, level 0 systems, etc. */
7648 if (TARGET_FAST_INDIRECT_CALLS)
7649 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7651 /* Now the normal case -- we can reach $$dyncall directly or
7652 we're sure that we can get there via a long-branch stub.
7654 No need to check target flags as the length uniquely identifies
7655 the remaining cases. */
7656 if (attr_length_indirect_call (insn) == 8)
7658 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
7659 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
7660 variant of the B,L instruction can't be used on the SOM target. */
7661 if (TARGET_PA_20 && !TARGET_SOM)
7662 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7664 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7667 /* Long millicode call, but we are not generating PIC or portable runtime
7669 if (attr_length_indirect_call (insn) == 12)
7670 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7672 /* Long millicode call for portable runtime. */
7673 if (attr_length_indirect_call (insn) == 20)
7674 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7676 /* We need a long PIC call to $$dyncall. */
7677 xoperands[0] = NULL_RTX;
7678 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7679 if (TARGET_SOM || !TARGET_GAS)
7681 xoperands[0] = gen_label_rtx ();
7682 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7683 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7684 CODE_LABEL_NUMBER (xoperands[0]));
7685 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7689 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7690 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7693 output_asm_insn ("blr %%r0,%%r2", xoperands);
7694 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7698 /* Return the total length of the save and restore instructions needed for
7699 the data linkage table pointer (i.e., the PIC register) across the call
7700 instruction INSN. No-return calls do not require a save and restore.
7701 In addition, we may be able to avoid the save and restore for calls
7702 within the same translation unit. */
7705 attr_length_save_restore_dltp (rtx insn)
7707 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7713 /* In HPUX 8.0's shared library scheme, special relocations are needed
7714 for function labels if they might be passed to a function
7715 in a shared library (because shared libraries don't live in code
7716 space), and special magic is needed to construct their address. */
7719 hppa_encode_label (rtx sym)
7721 const char *str = XSTR (sym, 0);
7722 int len = strlen (str) + 1;
7725 p = newstr = alloca (len + 1);
7729 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7733 pa_encode_section_info (tree decl, rtx rtl, int first)
7735 default_encode_section_info (decl, rtl, first);
7737 if (first && TEXT_SPACE_P (decl))
7739 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7740 if (TREE_CODE (decl) == FUNCTION_DECL)
7741 hppa_encode_label (XEXP (rtl, 0));
7745 /* This is sort of inverse to pa_encode_section_info. */
7748 pa_strip_name_encoding (const char *str)
7750 str += (*str == '@');
7751 str += (*str == '*');
7756 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7758 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7761 /* Returns 1 if OP is a function label involved in a simple addition
7762 with a constant. Used to keep certain patterns from matching
7763 during instruction combination. */
7765 is_function_label_plus_const (rtx op)
7767 /* Strip off any CONST. */
7768 if (GET_CODE (op) == CONST)
7771 return (GET_CODE (op) == PLUS
7772 && function_label_operand (XEXP (op, 0), Pmode)
7773 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7776 /* Output assembly code for a thunk to FUNCTION. */
7779 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7780 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7783 static unsigned int current_thunk_number;
7784 int val_14 = VAL_14_BITS_P (delta);
7789 xoperands[0] = XEXP (DECL_RTL (function), 0);
7790 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7791 xoperands[2] = GEN_INT (delta);
7793 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7794 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7796 /* Output the thunk. We know that the function is in the same
7797 translation unit (i.e., the same space) as the thunk, and that
7798 thunks are output after their method. Thus, we don't need an
7799 external branch to reach the function. With SOM and GAS,
7800 functions and thunks are effectively in different sections.
7801 Thus, we can always use a IA-relative branch and the linker
7802 will add a long branch stub if necessary.
7804 However, we have to be careful when generating PIC code on the
7805 SOM port to ensure that the sequence does not transfer to an
7806 import stub for the target function as this could clobber the
7807 return value saved at SP-24. This would also apply to the
7808 32-bit linux port if the multi-space model is implemented. */
7809 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7810 && !(flag_pic && TREE_PUBLIC (function))
7811 && (TARGET_GAS || last_address < 262132))
7812 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7813 && ((targetm.have_named_sections
7814 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7815 /* The GNU 64-bit linker has rather poor stub management.
7816 So, we use a long branch from thunks that aren't in
7817 the same section as the target function. */
7819 && (DECL_SECTION_NAME (thunk_fndecl)
7820 != DECL_SECTION_NAME (function)))
7821 || ((DECL_SECTION_NAME (thunk_fndecl)
7822 == DECL_SECTION_NAME (function))
7823 && last_address < 262132)))
7824 || (!targetm.have_named_sections && last_address < 262132))))
7827 output_asm_insn ("addil L'%2,%%r26", xoperands);
7829 output_asm_insn ("b %0", xoperands);
7833 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7838 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7842 else if (TARGET_64BIT)
7844 /* We only have one call-clobbered scratch register, so we can't
7845 make use of the delay slot if delta doesn't fit in 14 bits. */
7848 output_asm_insn ("addil L'%2,%%r26", xoperands);
7849 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7852 output_asm_insn ("b,l .+8,%%r1", xoperands);
7856 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7857 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7861 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7862 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7867 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7868 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7873 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7877 else if (TARGET_PORTABLE_RUNTIME)
7879 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7880 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7883 output_asm_insn ("addil L'%2,%%r26", xoperands);
7885 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7889 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7894 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7898 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7900 /* The function is accessible from outside this module. The only
7901 way to avoid an import stub between the thunk and function is to
7902 call the function directly with an indirect sequence similar to
7903 that used by $$dyncall. This is possible because $$dyncall acts
7904 as the import stub in an indirect call. */
7905 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7906 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7907 output_asm_insn ("addil LT'%3,%%r19", xoperands);
7908 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
7909 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7910 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
7911 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
7912 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
7913 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7917 output_asm_insn ("addil L'%2,%%r26", xoperands);
7923 output_asm_insn ("bve (%%r22)", xoperands);
7926 else if (TARGET_NO_SPACE_REGS)
7928 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
7933 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
7934 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
7935 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
7940 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7942 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7946 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7948 if (TARGET_SOM || !TARGET_GAS)
7950 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
7951 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
7955 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7956 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
7960 output_asm_insn ("addil L'%2,%%r26", xoperands);
7962 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7966 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7971 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7978 output_asm_insn ("addil L'%2,%%r26", xoperands);
7980 output_asm_insn ("ldil L'%0,%%r22", xoperands);
7981 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
7985 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7990 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7995 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7997 if (TARGET_SOM && TARGET_GAS)
7999 /* We done with this subspace except possibly for some additional
8000 debug information. Forget that we are in this subspace to ensure
8001 that the next function is output in its own subspace. */
8003 cfun->machine->in_nsubspa = 2;
8006 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8008 switch_to_section (data_section);
8009 output_asm_insn (".align 4", xoperands);
8010 ASM_OUTPUT_LABEL (file, label);
8011 output_asm_insn (".word P'%0", xoperands);
8014 current_thunk_number++;
8015 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8016 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8017 last_address += nbytes;
8018 update_total_code_bytes (nbytes);
8021 /* Only direct calls to static functions are allowed to be sibling (tail)
8024 This restriction is necessary because some linker generated stubs will
8025 store return pointers into rp' in some cases which might clobber a
8026 live value already in rp'.
8028 In a sibcall the current function and the target function share stack
8029 space. Thus if the path to the current function and the path to the
8030 target function save a value in rp', they save the value into the
8031 same stack slot, which has undesirable consequences.
8033 Because of the deferred binding nature of shared libraries any function
8034 with external scope could be in a different load module and thus require
8035 rp' to be saved when calling that function. So sibcall optimizations
8036 can only be safe for static function.
8038 Note that GCC never needs return value relocations, so we don't have to
8039 worry about static calls with return value relocations (which require
8042 It is safe to perform a sibcall optimization when the target function
8043 will never return. */
8045 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8047 if (TARGET_PORTABLE_RUNTIME)
8050 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8051 single subspace mode and the call is not indirect. As far as I know,
8052 there is no operating system support for the multiple subspace mode.
8053 It might be possible to support indirect calls if we didn't use
8054 $$dyncall (see the indirect sequence generated in output_call). */
8056 return (decl != NULL_TREE);
8058 /* Sibcalls are not ok because the arg pointer register is not a fixed
8059 register. This prevents the sibcall optimization from occurring. In
8060 addition, there are problems with stub placement using GNU ld. This
8061 is because a normal sibcall branch uses a 17-bit relocation while
8062 a regular call branch uses a 22-bit relocation. As a result, more
8063 care needs to be taken in the placement of long-branch stubs. */
8067 /* Sibcalls are only ok within a translation unit. */
8068 return (decl && !TREE_PUBLIC (decl));
8071 /* ??? Addition is not commutative on the PA due to the weird implicit
8072 space register selection rules for memory addresses. Therefore, we
8073 don't consider a + b == b + a, as this might be inside a MEM. */
8075 pa_commutative_p (rtx x, int outer_code)
8077 return (COMMUTATIVE_P (x)
8078 && (TARGET_NO_SPACE_REGS
8079 || (outer_code != UNKNOWN && outer_code != MEM)
8080 || GET_CODE (x) != PLUS));
8083 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8084 use in fmpyadd instructions. */
8086 fmpyaddoperands (rtx *operands)
8088 enum machine_mode mode = GET_MODE (operands[0]);
8090 /* Must be a floating point mode. */
8091 if (mode != SFmode && mode != DFmode)
8094 /* All modes must be the same. */
8095 if (! (mode == GET_MODE (operands[1])
8096 && mode == GET_MODE (operands[2])
8097 && mode == GET_MODE (operands[3])
8098 && mode == GET_MODE (operands[4])
8099 && mode == GET_MODE (operands[5])))
8102 /* All operands must be registers. */
8103 if (! (GET_CODE (operands[1]) == REG
8104 && GET_CODE (operands[2]) == REG
8105 && GET_CODE (operands[3]) == REG
8106 && GET_CODE (operands[4]) == REG
8107 && GET_CODE (operands[5]) == REG))
8110 /* Only 2 real operands to the addition. One of the input operands must
8111 be the same as the output operand. */
8112 if (! rtx_equal_p (operands[3], operands[4])
8113 && ! rtx_equal_p (operands[3], operands[5]))
8116 /* Inout operand of add cannot conflict with any operands from multiply. */
8117 if (rtx_equal_p (operands[3], operands[0])
8118 || rtx_equal_p (operands[3], operands[1])
8119 || rtx_equal_p (operands[3], operands[2]))
8122 /* multiply cannot feed into addition operands. */
8123 if (rtx_equal_p (operands[4], operands[0])
8124 || rtx_equal_p (operands[5], operands[0]))
8127 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8129 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8130 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8131 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8132 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8133 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8134 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8137 /* Passed. Operands are suitable for fmpyadd. */
8141 #if !defined(USE_COLLECT2)
8143 pa_asm_out_constructor (rtx symbol, int priority)
8145 if (!function_label_operand (symbol, VOIDmode))
8146 hppa_encode_label (symbol);
8148 #ifdef CTORS_SECTION_ASM_OP
8149 default_ctor_section_asm_out_constructor (symbol, priority);
8151 # ifdef TARGET_ASM_NAMED_SECTION
8152 default_named_section_asm_out_constructor (symbol, priority);
8154 default_stabs_asm_out_constructor (symbol, priority);
8160 pa_asm_out_destructor (rtx symbol, int priority)
8162 if (!function_label_operand (symbol, VOIDmode))
8163 hppa_encode_label (symbol);
8165 #ifdef DTORS_SECTION_ASM_OP
8166 default_dtor_section_asm_out_destructor (symbol, priority);
8168 # ifdef TARGET_ASM_NAMED_SECTION
8169 default_named_section_asm_out_destructor (symbol, priority);
8171 default_stabs_asm_out_destructor (symbol, priority);
8177 /* This function places uninitialized global data in the bss section.
8178 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8179 function on the SOM port to prevent uninitialized global data from
8180 being placed in the data section. */
8183 pa_asm_output_aligned_bss (FILE *stream,
8185 unsigned HOST_WIDE_INT size,
8188 switch_to_section (bss_section);
8189 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8191 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8192 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8195 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8196 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8199 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8200 ASM_OUTPUT_LABEL (stream, name);
8201 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8204 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8205 that doesn't allow the alignment of global common storage to be directly
8206 specified. The SOM linker aligns common storage based on the rounded
8207 value of the NUM_BYTES parameter in the .comm directive. It's not
8208 possible to use the .align directive as it doesn't affect the alignment
8209 of the label associated with a .comm directive. */
8212 pa_asm_output_aligned_common (FILE *stream,
8214 unsigned HOST_WIDE_INT size,
8217 unsigned int max_common_align;
8219 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8220 if (align > max_common_align)
8222 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8223 "for global common data. Using %u",
8224 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8225 align = max_common_align;
8228 switch_to_section (bss_section);
8230 assemble_name (stream, name);
8231 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8232 MAX (size, align / BITS_PER_UNIT));
8235 /* We can't use .comm for local common storage as the SOM linker effectively
8236 treats the symbol as universal and uses the same storage for local symbols
8237 with the same name in different object files. The .block directive
8238 reserves an uninitialized block of storage. However, it's not common
8239 storage. Fortunately, GCC never requests common storage with the same
8240 name in any given translation unit. */
8243 pa_asm_output_aligned_local (FILE *stream,
8245 unsigned HOST_WIDE_INT size,
8248 switch_to_section (bss_section);
8249 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8252 fprintf (stream, "%s", LOCAL_ASM_OP);
8253 assemble_name (stream, name);
8254 fprintf (stream, "\n");
8257 ASM_OUTPUT_LABEL (stream, name);
8258 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8261 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8262 use in fmpysub instructions. */
8264 fmpysuboperands (rtx *operands)
8266 enum machine_mode mode = GET_MODE (operands[0]);
8268 /* Must be a floating point mode. */
8269 if (mode != SFmode && mode != DFmode)
8272 /* All modes must be the same. */
8273 if (! (mode == GET_MODE (operands[1])
8274 && mode == GET_MODE (operands[2])
8275 && mode == GET_MODE (operands[3])
8276 && mode == GET_MODE (operands[4])
8277 && mode == GET_MODE (operands[5])))
8280 /* All operands must be registers. */
8281 if (! (GET_CODE (operands[1]) == REG
8282 && GET_CODE (operands[2]) == REG
8283 && GET_CODE (operands[3]) == REG
8284 && GET_CODE (operands[4]) == REG
8285 && GET_CODE (operands[5]) == REG))
8288 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8289 operation, so operands[4] must be the same as operand[3]. */
8290 if (! rtx_equal_p (operands[3], operands[4]))
8293 /* multiply cannot feed into subtraction. */
8294 if (rtx_equal_p (operands[5], operands[0]))
8297 /* Inout operand of sub cannot conflict with any operands from multiply. */
8298 if (rtx_equal_p (operands[3], operands[0])
8299 || rtx_equal_p (operands[3], operands[1])
8300 || rtx_equal_p (operands[3], operands[2]))
8303 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8305 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8306 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8307 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8308 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8309 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8310 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8313 /* Passed. Operands are suitable for fmpysub. */
8317 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8318 constants for shadd instructions. */
8320 shadd_constant_p (int val)
8322 if (val == 2 || val == 4 || val == 8)
8328 /* Return 1 if OP is valid as a base or index register in a
8332 borx_reg_operand (rtx op, enum machine_mode mode)
8334 if (GET_CODE (op) != REG)
8337 /* We must reject virtual registers as the only expressions that
8338 can be instantiated are REG and REG+CONST. */
8339 if (op == virtual_incoming_args_rtx
8340 || op == virtual_stack_vars_rtx
8341 || op == virtual_stack_dynamic_rtx
8342 || op == virtual_outgoing_args_rtx
8343 || op == virtual_cfa_rtx)
8346 /* While it's always safe to index off the frame pointer, it's not
8347 profitable to do so when the frame pointer is being eliminated. */
8348 if (!reload_completed
8349 && flag_omit_frame_pointer
8350 && !current_function_calls_alloca
8351 && op == frame_pointer_rtx)
8354 return register_operand (op, mode);
8357 /* Return 1 if this operand is anything other than a hard register. */
8360 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8362 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8365 /* Return 1 if INSN branches forward. Should be using insn_addresses
8366 to avoid walking through all the insns... */
8368 forward_branch_p (rtx insn)
8370 rtx label = JUMP_LABEL (insn);
8377 insn = NEXT_INSN (insn);
8380 return (insn == label);
8383 /* Return 1 if OP is an equality comparison, else return 0. */
8385 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8387 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8390 /* Return 1 if INSN is in the delay slot of a call instruction. */
8392 jump_in_call_delay (rtx insn)
8395 if (GET_CODE (insn) != JUMP_INSN)
8398 if (PREV_INSN (insn)
8399 && PREV_INSN (PREV_INSN (insn))
8400 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8402 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8404 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8405 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8412 /* Output an unconditional move and branch insn. */
8415 output_parallel_movb (rtx *operands, rtx insn)
8417 int length = get_attr_length (insn);
8419 /* These are the cases in which we win. */
8421 return "mov%I1b,tr %1,%0,%2";
8423 /* None of the following cases win, but they don't lose either. */
8426 if (dbr_sequence_length () == 0)
8428 /* Nothing in the delay slot, fake it by putting the combined
8429 insn (the copy or add) in the delay slot of a bl. */
8430 if (GET_CODE (operands[1]) == CONST_INT)
8431 return "b %2\n\tldi %1,%0";
8433 return "b %2\n\tcopy %1,%0";
8437 /* Something in the delay slot, but we've got a long branch. */
8438 if (GET_CODE (operands[1]) == CONST_INT)
8439 return "ldi %1,%0\n\tb %2";
8441 return "copy %1,%0\n\tb %2";
8445 if (GET_CODE (operands[1]) == CONST_INT)
8446 output_asm_insn ("ldi %1,%0", operands);
8448 output_asm_insn ("copy %1,%0", operands);
8449 return output_lbranch (operands[2], insn, 1);
8452 /* Output an unconditional add and branch insn. */
8455 output_parallel_addb (rtx *operands, rtx insn)
8457 int length = get_attr_length (insn);
8459 /* To make life easy we want operand0 to be the shared input/output
8460 operand and operand1 to be the readonly operand. */
8461 if (operands[0] == operands[1])
8462 operands[1] = operands[2];
8464 /* These are the cases in which we win. */
8466 return "add%I1b,tr %1,%0,%3";
8468 /* None of the following cases win, but they don't lose either. */
8471 if (dbr_sequence_length () == 0)
8472 /* Nothing in the delay slot, fake it by putting the combined
8473 insn (the copy or add) in the delay slot of a bl. */
8474 return "b %3\n\tadd%I1 %1,%0,%0";
8476 /* Something in the delay slot, but we've got a long branch. */
8477 return "add%I1 %1,%0,%0\n\tb %3";
8480 output_asm_insn ("add%I1 %1,%0,%0", operands);
8481 return output_lbranch (operands[3], insn, 1);
8484 /* Return nonzero if INSN (a jump insn) immediately follows a call
8485 to a named function. This is used to avoid filling the delay slot
8486 of the jump since it can usually be eliminated by modifying RP in
8487 the delay slot of the call. */
8490 following_call (rtx insn)
8492 if (! TARGET_JUMP_IN_DELAY)
8495 /* Find the previous real insn, skipping NOTEs. */
8496 insn = PREV_INSN (insn);
8497 while (insn && GET_CODE (insn) == NOTE)
8498 insn = PREV_INSN (insn);
8500 /* Check for CALL_INSNs and millicode calls. */
8502 && ((GET_CODE (insn) == CALL_INSN
8503 && get_attr_type (insn) != TYPE_DYNCALL)
8504 || (GET_CODE (insn) == INSN
8505 && GET_CODE (PATTERN (insn)) != SEQUENCE
8506 && GET_CODE (PATTERN (insn)) != USE
8507 && GET_CODE (PATTERN (insn)) != CLOBBER
8508 && get_attr_type (insn) == TYPE_MILLI)))
8514 /* We use this hook to perform a PA specific optimization which is difficult
8515 to do in earlier passes.
8517 We want the delay slots of branches within jump tables to be filled.
8518 None of the compiler passes at the moment even has the notion that a
8519 PA jump table doesn't contain addresses, but instead contains actual
8522 Because we actually jump into the table, the addresses of each entry
8523 must stay constant in relation to the beginning of the table (which
8524 itself must stay constant relative to the instruction to jump into
8525 it). I don't believe we can guarantee earlier passes of the compiler
8526 will adhere to those rules.
8528 So, late in the compilation process we find all the jump tables, and
8529 expand them into real code -- e.g. each entry in the jump table vector
8530 will get an appropriate label followed by a jump to the final target.
8532 Reorg and the final jump pass can then optimize these branches and
8533 fill their delay slots. We end up with smaller, more efficient code.
8535 The jump instructions within the table are special; we must be able
8536 to identify them during assembly output (if the jumps don't get filled
8537 we need to emit a nop rather than nullifying the delay slot)). We
8538 identify jumps in switch tables by using insns with the attribute
8539 type TYPE_BTABLE_BRANCH.
8541 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8542 insns. This serves two purposes, first it prevents jump.c from
8543 noticing that the last N entries in the table jump to the instruction
8544 immediately after the table and deleting the jumps. Second, those
8545 insns mark where we should emit .begin_brtab and .end_brtab directives
8546 when using GAS (allows for better link time optimizations). */
8553 remove_useless_addtr_insns (1);
8555 if (pa_cpu < PROCESSOR_8000)
8556 pa_combine_instructions ();
8559 /* This is fairly cheap, so always run it if optimizing. */
8560 if (optimize > 0 && !TARGET_BIG_SWITCH)
8562 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8563 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8565 rtx pattern, tmp, location, label;
8566 unsigned int length, i;
8568 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8569 if (GET_CODE (insn) != JUMP_INSN
8570 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8571 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8574 /* Emit marker for the beginning of the branch table. */
8575 emit_insn_before (gen_begin_brtab (), insn);
8577 pattern = PATTERN (insn);
8578 location = PREV_INSN (insn);
8579 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8581 for (i = 0; i < length; i++)
8583 /* Emit a label before each jump to keep jump.c from
8584 removing this code. */
8585 tmp = gen_label_rtx ();
8586 LABEL_NUSES (tmp) = 1;
8587 emit_label_after (tmp, location);
8588 location = NEXT_INSN (location);
8590 if (GET_CODE (pattern) == ADDR_VEC)
8591 label = XEXP (XVECEXP (pattern, 0, i), 0);
8593 label = XEXP (XVECEXP (pattern, 1, i), 0);
8595 tmp = gen_short_jump (label);
8597 /* Emit the jump itself. */
8598 tmp = emit_jump_insn_after (tmp, location);
8599 JUMP_LABEL (tmp) = label;
8600 LABEL_NUSES (label)++;
8601 location = NEXT_INSN (location);
8603 /* Emit a BARRIER after the jump. */
8604 emit_barrier_after (location);
8605 location = NEXT_INSN (location);
8608 /* Emit marker for the end of the branch table. */
8609 emit_insn_before (gen_end_brtab (), location);
8610 location = NEXT_INSN (location);
8611 emit_barrier_after (location);
8613 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8619 /* Still need brtab marker insns. FIXME: the presence of these
8620 markers disables output of the branch table to readonly memory,
8621 and any alignment directives that might be needed. Possibly,
8622 the begin_brtab insn should be output before the label for the
8623 table. This doesn't matter at the moment since the tables are
8624 always output in the text section. */
8625 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8627 /* Find an ADDR_VEC insn. */
8628 if (GET_CODE (insn) != JUMP_INSN
8629 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8630 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8633 /* Now generate markers for the beginning and end of the
8635 emit_insn_before (gen_begin_brtab (), insn);
8636 emit_insn_after (gen_end_brtab (), insn);
8641 /* The PA has a number of odd instructions which can perform multiple
8642 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8643 it may be profitable to combine two instructions into one instruction
8644 with two outputs. It's not profitable PA2.0 machines because the
8645 two outputs would take two slots in the reorder buffers.
8647 This routine finds instructions which can be combined and combines
8648 them. We only support some of the potential combinations, and we
8649 only try common ways to find suitable instructions.
8651 * addb can add two registers or a register and a small integer
8652 and jump to a nearby (+-8k) location. Normally the jump to the
8653 nearby location is conditional on the result of the add, but by
8654 using the "true" condition we can make the jump unconditional.
8655 Thus addb can perform two independent operations in one insn.
8657 * movb is similar to addb in that it can perform a reg->reg
8658 or small immediate->reg copy and jump to a nearby (+-8k location).
8660 * fmpyadd and fmpysub can perform a FP multiply and either an
8661 FP add or FP sub if the operands of the multiply and add/sub are
8662 independent (there are other minor restrictions). Note both
8663 the fmpy and fadd/fsub can in theory move to better spots according
8664 to data dependencies, but for now we require the fmpy stay at a
8667 * Many of the memory operations can perform pre & post updates
8668 of index registers. GCC's pre/post increment/decrement addressing
8669 is far too simple to take advantage of all the possibilities. This
8670 pass may not be suitable since those insns may not be independent.
8672 * comclr can compare two ints or an int and a register, nullify
8673 the following instruction and zero some other register. This
8674 is more difficult to use as it's harder to find an insn which
8675 will generate a comclr than finding something like an unconditional
8676 branch. (conditional moves & long branches create comclr insns).
8678 * Most arithmetic operations can conditionally skip the next
8679 instruction. They can be viewed as "perform this operation
8680 and conditionally jump to this nearby location" (where nearby
8681 is an insns away). These are difficult to use due to the
8682 branch length restrictions. */
8685 pa_combine_instructions (void)
8689 /* This can get expensive since the basic algorithm is on the
8690 order of O(n^2) (or worse). Only do it for -O2 or higher
8691 levels of optimization. */
8695 /* Walk down the list of insns looking for "anchor" insns which
8696 may be combined with "floating" insns. As the name implies,
8697 "anchor" instructions don't move, while "floating" insns may
8699 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8700 new = make_insn_raw (new);
8702 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8704 enum attr_pa_combine_type anchor_attr;
8705 enum attr_pa_combine_type floater_attr;
8707 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8708 Also ignore any special USE insns. */
8709 if ((GET_CODE (anchor) != INSN
8710 && GET_CODE (anchor) != JUMP_INSN
8711 && GET_CODE (anchor) != CALL_INSN)
8712 || GET_CODE (PATTERN (anchor)) == USE
8713 || GET_CODE (PATTERN (anchor)) == CLOBBER
8714 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8715 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8718 anchor_attr = get_attr_pa_combine_type (anchor);
8719 /* See if anchor is an insn suitable for combination. */
8720 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8721 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8722 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8723 && ! forward_branch_p (anchor)))
8727 for (floater = PREV_INSN (anchor);
8729 floater = PREV_INSN (floater))
8731 if (GET_CODE (floater) == NOTE
8732 || (GET_CODE (floater) == INSN
8733 && (GET_CODE (PATTERN (floater)) == USE
8734 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8737 /* Anything except a regular INSN will stop our search. */
8738 if (GET_CODE (floater) != INSN
8739 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8740 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8746 /* See if FLOATER is suitable for combination with the
8748 floater_attr = get_attr_pa_combine_type (floater);
8749 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8750 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8751 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8752 && floater_attr == PA_COMBINE_TYPE_FMPY))
8754 /* If ANCHOR and FLOATER can be combined, then we're
8755 done with this pass. */
8756 if (pa_can_combine_p (new, anchor, floater, 0,
8757 SET_DEST (PATTERN (floater)),
8758 XEXP (SET_SRC (PATTERN (floater)), 0),
8759 XEXP (SET_SRC (PATTERN (floater)), 1)))
8763 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8764 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8766 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8768 if (pa_can_combine_p (new, anchor, floater, 0,
8769 SET_DEST (PATTERN (floater)),
8770 XEXP (SET_SRC (PATTERN (floater)), 0),
8771 XEXP (SET_SRC (PATTERN (floater)), 1)))
8776 if (pa_can_combine_p (new, anchor, floater, 0,
8777 SET_DEST (PATTERN (floater)),
8778 SET_SRC (PATTERN (floater)),
8779 SET_SRC (PATTERN (floater))))
8785 /* If we didn't find anything on the backwards scan try forwards. */
8787 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8788 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8790 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8792 if (GET_CODE (floater) == NOTE
8793 || (GET_CODE (floater) == INSN
8794 && (GET_CODE (PATTERN (floater)) == USE
8795 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8799 /* Anything except a regular INSN will stop our search. */
8800 if (GET_CODE (floater) != INSN
8801 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8802 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8808 /* See if FLOATER is suitable for combination with the
8810 floater_attr = get_attr_pa_combine_type (floater);
8811 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8812 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8813 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8814 && floater_attr == PA_COMBINE_TYPE_FMPY))
8816 /* If ANCHOR and FLOATER can be combined, then we're
8817 done with this pass. */
8818 if (pa_can_combine_p (new, anchor, floater, 1,
8819 SET_DEST (PATTERN (floater)),
8820 XEXP (SET_SRC (PATTERN (floater)),
8822 XEXP (SET_SRC (PATTERN (floater)),
8829 /* FLOATER will be nonzero if we found a suitable floating
8830 insn for combination with ANCHOR. */
8832 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8833 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8835 /* Emit the new instruction and delete the old anchor. */
8836 emit_insn_before (gen_rtx_PARALLEL
8838 gen_rtvec (2, PATTERN (anchor),
8839 PATTERN (floater))),
8842 PUT_CODE (anchor, NOTE);
8843 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8844 NOTE_SOURCE_FILE (anchor) = 0;
8846 /* Emit a special USE insn for FLOATER, then delete
8847 the floating insn. */
8848 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8849 delete_insn (floater);
8854 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8857 /* Emit the new_jump instruction and delete the old anchor. */
8859 = emit_jump_insn_before (gen_rtx_PARALLEL
8861 gen_rtvec (2, PATTERN (anchor),
8862 PATTERN (floater))),
8865 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8866 PUT_CODE (anchor, NOTE);
8867 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8868 NOTE_SOURCE_FILE (anchor) = 0;
8870 /* Emit a special USE insn for FLOATER, then delete
8871 the floating insn. */
8872 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8873 delete_insn (floater);
8881 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8884 int insn_code_number;
8887 /* Create a PARALLEL with the patterns of ANCHOR and
8888 FLOATER, try to recognize it, then test constraints
8889 for the resulting pattern.
8891 If the pattern doesn't match or the constraints
8892 aren't met keep searching for a suitable floater
8894 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8895 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8896 INSN_CODE (new) = -1;
8897 insn_code_number = recog_memoized (new);
8898 if (insn_code_number < 0
8899 || (extract_insn (new), ! constrain_operands (1)))
8913 /* There's up to three operands to consider. One
8914 output and two inputs.
8916 The output must not be used between FLOATER & ANCHOR
8917 exclusive. The inputs must not be set between
8918 FLOATER and ANCHOR exclusive. */
8920 if (reg_used_between_p (dest, start, end))
8923 if (reg_set_between_p (src1, start, end))
8926 if (reg_set_between_p (src2, start, end))
8929 /* If we get here, then everything is good. */
8933 /* Return nonzero if references for INSN are delayed.
8935 Millicode insns are actually function calls with some special
8936 constraints on arguments and register usage.
8938 Millicode calls always expect their arguments in the integer argument
8939 registers, and always return their result in %r29 (ret1). They
8940 are expected to clobber their arguments, %r1, %r29, and the return
8941 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8943 This function tells reorg that the references to arguments and
8944 millicode calls do not appear to happen until after the millicode call.
8945 This allows reorg to put insns which set the argument registers into the
8946 delay slot of the millicode call -- thus they act more like traditional
8949 Note we cannot consider side effects of the insn to be delayed because
8950 the branch and link insn will clobber the return pointer. If we happened
8951 to use the return pointer in the delay slot of the call, then we lose.
8953 get_attr_type will try to recognize the given insn, so make sure to
8954 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8957 insn_refs_are_delayed (rtx insn)
8959 return ((GET_CODE (insn) == INSN
8960 && GET_CODE (PATTERN (insn)) != SEQUENCE
8961 && GET_CODE (PATTERN (insn)) != USE
8962 && GET_CODE (PATTERN (insn)) != CLOBBER
8963 && get_attr_type (insn) == TYPE_MILLI));
8966 /* On the HP-PA the value is found in register(s) 28(-29), unless
8967 the mode is SF or DF. Then the value is returned in fr4 (32).
8969 This must perform the same promotions as PROMOTE_MODE, else
8970 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8972 Small structures must be returned in a PARALLEL on PA64 in order
8973 to match the HP Compiler ABI. */
8976 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8978 enum machine_mode valmode;
8980 if (AGGREGATE_TYPE_P (valtype)
8981 || TREE_CODE (valtype) == COMPLEX_TYPE
8982 || TREE_CODE (valtype) == VECTOR_TYPE)
8986 /* Aggregates with a size less than or equal to 128 bits are
8987 returned in GR 28(-29). They are left justified. The pad
8988 bits are undefined. Larger aggregates are returned in
8992 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8994 for (i = 0; i < ub; i++)
8996 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8997 gen_rtx_REG (DImode, 28 + i),
9002 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9004 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9006 /* Aggregates 5 to 8 bytes in size are returned in general
9007 registers r28-r29 in the same manner as other non
9008 floating-point objects. The data is right-justified and
9009 zero-extended to 64 bits. This is opposite to the normal
9010 justification used on big endian targets and requires
9011 special treatment. */
9012 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9013 gen_rtx_REG (DImode, 28), const0_rtx);
9014 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9018 if ((INTEGRAL_TYPE_P (valtype)
9019 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
9020 || POINTER_TYPE_P (valtype))
9021 valmode = word_mode;
9023 valmode = TYPE_MODE (valtype);
9025 if (TREE_CODE (valtype) == REAL_TYPE
9026 && !AGGREGATE_TYPE_P (valtype)
9027 && TYPE_MODE (valtype) != TFmode
9028 && !TARGET_SOFT_FLOAT)
9029 return gen_rtx_REG (valmode, 32);
9031 return gen_rtx_REG (valmode, 28);
9034 /* Return the location of a parameter that is passed in a register or NULL
9035 if the parameter has any component that is passed in memory.
9037 This is new code and will be pushed to into the net sources after
9040 ??? We might want to restructure this so that it looks more like other
9043 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
9044 int named ATTRIBUTE_UNUSED)
9046 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9053 if (mode == VOIDmode)
9056 arg_size = FUNCTION_ARG_SIZE (mode, type);
9058 /* If this arg would be passed partially or totally on the stack, then
9059 this routine should return zero. pa_arg_partial_bytes will
9060 handle arguments which are split between regs and stack slots if
9061 the ABI mandates split arguments. */
9064 /* The 32-bit ABI does not split arguments. */
9065 if (cum->words + arg_size > max_arg_words)
9071 alignment = cum->words & 1;
9072 if (cum->words + alignment >= max_arg_words)
9076 /* The 32bit ABIs and the 64bit ABIs are rather different,
9077 particularly in their handling of FP registers. We might
9078 be able to cleverly share code between them, but I'm not
9079 going to bother in the hope that splitting them up results
9080 in code that is more easily understood. */
9084 /* Advance the base registers to their current locations.
9086 Remember, gprs grow towards smaller register numbers while
9087 fprs grow to higher register numbers. Also remember that
9088 although FP regs are 32-bit addressable, we pretend that
9089 the registers are 64-bits wide. */
9090 gpr_reg_base = 26 - cum->words;
9091 fpr_reg_base = 32 + cum->words;
9093 /* Arguments wider than one word and small aggregates need special
9097 || (type && (AGGREGATE_TYPE_P (type)
9098 || TREE_CODE (type) == COMPLEX_TYPE
9099 || TREE_CODE (type) == VECTOR_TYPE)))
9101 /* Double-extended precision (80-bit), quad-precision (128-bit)
9102 and aggregates including complex numbers are aligned on
9103 128-bit boundaries. The first eight 64-bit argument slots
9104 are associated one-to-one, with general registers r26
9105 through r19, and also with floating-point registers fr4
9106 through fr11. Arguments larger than one word are always
9107 passed in general registers.
9109 Using a PARALLEL with a word mode register results in left
9110 justified data on a big-endian target. */
9113 int i, offset = 0, ub = arg_size;
9115 /* Align the base register. */
9116 gpr_reg_base -= alignment;
9118 ub = MIN (ub, max_arg_words - cum->words - alignment);
9119 for (i = 0; i < ub; i++)
9121 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9122 gen_rtx_REG (DImode, gpr_reg_base),
9128 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9133 /* If the argument is larger than a word, then we know precisely
9134 which registers we must use. */
9148 /* Structures 5 to 8 bytes in size are passed in the general
9149 registers in the same manner as other non floating-point
9150 objects. The data is right-justified and zero-extended
9151 to 64 bits. This is opposite to the normal justification
9152 used on big endian targets and requires special treatment.
9153 We now define BLOCK_REG_PADDING to pad these objects.
9154 Aggregates, complex and vector types are passed in the same
9155 manner as structures. */
9157 || (type && (AGGREGATE_TYPE_P (type)
9158 || TREE_CODE (type) == COMPLEX_TYPE
9159 || TREE_CODE (type) == VECTOR_TYPE)))
9161 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9162 gen_rtx_REG (DImode, gpr_reg_base),
9164 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9169 /* We have a single word (32 bits). A simple computation
9170 will get us the register #s we need. */
9171 gpr_reg_base = 26 - cum->words;
9172 fpr_reg_base = 32 + 2 * cum->words;
9176 /* Determine if the argument needs to be passed in both general and
9177 floating point registers. */
9178 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9179 /* If we are doing soft-float with portable runtime, then there
9180 is no need to worry about FP regs. */
9181 && !TARGET_SOFT_FLOAT
9182 /* The parameter must be some kind of scalar float, else we just
9183 pass it in integer registers. */
9184 && GET_MODE_CLASS (mode) == MODE_FLOAT
9185 /* The target function must not have a prototype. */
9186 && cum->nargs_prototype <= 0
9187 /* libcalls do not need to pass items in both FP and general
9189 && type != NULL_TREE
9190 /* All this hair applies to "outgoing" args only. This includes
9191 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9193 /* Also pass outgoing floating arguments in both registers in indirect
9194 calls with the 32 bit ABI and the HP assembler since there is no
9195 way to the specify argument locations in static functions. */
9200 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9206 gen_rtx_EXPR_LIST (VOIDmode,
9207 gen_rtx_REG (mode, fpr_reg_base),
9209 gen_rtx_EXPR_LIST (VOIDmode,
9210 gen_rtx_REG (mode, gpr_reg_base),
9215 /* See if we should pass this parameter in a general register. */
9216 if (TARGET_SOFT_FLOAT
9217 /* Indirect calls in the normal 32bit ABI require all arguments
9218 to be passed in general registers. */
9219 || (!TARGET_PORTABLE_RUNTIME
9223 /* If the parameter is not a scalar floating-point parameter,
9224 then it belongs in GPRs. */
9225 || GET_MODE_CLASS (mode) != MODE_FLOAT
9226 /* Structure with single SFmode field belongs in GPR. */
9227 || (type && AGGREGATE_TYPE_P (type)))
9228 retval = gen_rtx_REG (mode, gpr_reg_base);
9230 retval = gen_rtx_REG (mode, fpr_reg_base);
9236 /* If this arg would be passed totally in registers or totally on the stack,
9237 then this routine should return zero. */
9240 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9241 tree type, bool named ATTRIBUTE_UNUSED)
9243 unsigned int max_arg_words = 8;
9244 unsigned int offset = 0;
9249 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9252 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9253 /* Arg fits fully into registers. */
9255 else if (cum->words + offset >= max_arg_words)
9256 /* Arg fully on the stack. */
9260 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9264 /* A get_unnamed_section callback for switching to the text section.
9266 This function is only used with SOM. Because we don't support
9267 named subspaces, we can only create a new subspace or switch back
9268 to the default text subspace. */
9271 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9273 gcc_assert (TARGET_SOM);
9276 if (cfun && !cfun->machine->in_nsubspa)
9278 /* We only want to emit a .nsubspa directive once at the
9279 start of the function. */
9280 cfun->machine->in_nsubspa = 1;
9282 /* Create a new subspace for the text. This provides
9283 better stub placement and one-only functions. */
9285 && DECL_ONE_ONLY (cfun->decl)
9286 && !DECL_WEAK (cfun->decl))
9288 output_section_asm_op ("\t.SPACE $TEXT$\n"
9289 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9290 "ACCESS=44,SORT=24,COMDAT");
9296 /* There isn't a current function or the body of the current
9297 function has been completed. So, we are changing to the
9298 text section to output debugging information. Thus, we
9299 need to forget that we are in the text section so that
9300 varasm.c will call us when text_section is selected again. */
9301 gcc_assert (!cfun || cfun->machine->in_nsubspa == 2);
9304 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9307 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9310 /* A get_unnamed_section callback for switching to comdat data
9311 sections. This function is only used with SOM. */
9314 som_output_comdat_data_section_asm_op (const void *data)
9317 output_section_asm_op (data);
9320 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9323 pa_som_asm_init_sections (void)
9326 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9328 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9329 is not being generated. */
9330 som_readonly_data_section
9331 = get_unnamed_section (0, output_section_asm_op,
9332 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9334 /* When secondary definitions are not supported, SOM makes readonly
9335 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9337 som_one_only_readonly_data_section
9338 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9340 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9341 "ACCESS=0x2c,SORT=16,COMDAT");
9344 /* When secondary definitions are not supported, SOM makes data one-only
9345 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9346 som_one_only_data_section
9347 = get_unnamed_section (SECTION_WRITE,
9348 som_output_comdat_data_section_asm_op,
9349 "\t.SPACE $PRIVATE$\n"
9350 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9351 "ACCESS=31,SORT=24,COMDAT");
9353 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9354 which reference data within the $TEXT$ space (for example constant
9355 strings in the $LIT$ subspace).
9357 The assemblers (GAS and HP as) both have problems with handling
9358 the difference of two symbols which is the other correct way to
9359 reference constant data during PIC code generation.
9361 So, there's no way to reference constant data which is in the
9362 $TEXT$ space during PIC generation. Instead place all constant
9363 data into the $PRIVATE$ subspace (this reduces sharing, but it
9364 works correctly). */
9365 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9367 /* We must not have a reference to an external symbol defined in a
9368 shared library in a readonly section, else the SOM linker will
9371 So, we force exception information into the data section. */
9372 exception_section = data_section;
9375 /* On hpux10, the linker will give an error if we have a reference
9376 in the read-only data section to a symbol defined in a shared
9377 library. Therefore, expressions that might require a reloc can
9378 not be placed in the read-only data section. */
9381 pa_select_section (tree exp, int reloc,
9382 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9384 if (TREE_CODE (exp) == VAR_DECL
9385 && TREE_READONLY (exp)
9386 && !TREE_THIS_VOLATILE (exp)
9387 && DECL_INITIAL (exp)
9388 && (DECL_INITIAL (exp) == error_mark_node
9389 || TREE_CONSTANT (DECL_INITIAL (exp)))
9393 && DECL_ONE_ONLY (exp)
9394 && !DECL_WEAK (exp))
9395 return som_one_only_readonly_data_section;
9397 return readonly_data_section;
9399 else if (CONSTANT_CLASS_P (exp) && !reloc)
9400 return readonly_data_section;
9402 && TREE_CODE (exp) == VAR_DECL
9403 && DECL_ONE_ONLY (exp)
9404 && !DECL_WEAK (exp))
9405 return som_one_only_data_section;
9407 return data_section;
9411 pa_globalize_label (FILE *stream, const char *name)
9413 /* We only handle DATA objects here, functions are globalized in
9414 ASM_DECLARE_FUNCTION_NAME. */
9415 if (! FUNCTION_NAME_P (name))
9417 fputs ("\t.EXPORT ", stream);
9418 assemble_name (stream, name);
9419 fputs (",DATA\n", stream);
9423 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9426 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9427 int incoming ATTRIBUTE_UNUSED)
9429 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9432 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9435 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9437 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9438 PA64 ABI says that objects larger than 128 bits are returned in memory.
9439 Note, int_size_in_bytes can return -1 if the size of the object is
9440 variable or larger than the maximum value that can be expressed as
9441 a HOST_WIDE_INT. It can also return zero for an empty type. The
9442 simplest way to handle variable and empty types is to pass them in
9443 memory. This avoids problems in defining the boundaries of argument
9444 slots, allocating registers, etc. */
9445 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9446 || int_size_in_bytes (type) <= 0);
9449 /* Structure to hold declaration and name of external symbols that are
9450 emitted by GCC. We generate a vector of these symbols and output them
9451 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9452 This avoids putting out names that are never really used. */
9454 typedef struct extern_symbol GTY(())
9460 /* Define gc'd vector type for extern_symbol. */
9461 DEF_VEC_O(extern_symbol);
9462 DEF_VEC_ALLOC_O(extern_symbol,gc);
9464 /* Vector of extern_symbol pointers. */
9465 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9467 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9468 /* Mark DECL (name NAME) as an external reference (assembler output
9469 file FILE). This saves the names to output at the end of the file
9470 if actually referenced. */
9473 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9475 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9477 gcc_assert (file == asm_out_file);
9482 /* Output text required at the end of an assembler file.
9483 This includes deferred plabels and .import directives for
9484 all external symbols that were actually referenced. */
9487 pa_hpux_file_end (void)
9492 if (!NO_DEFERRED_PROFILE_COUNTERS)
9493 output_deferred_profile_counters ();
9495 output_deferred_plabels ();
9497 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9499 tree decl = p->decl;
9501 if (!TREE_ASM_WRITTEN (decl)
9502 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9503 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9506 VEC_free (extern_symbol, gc, extern_symbols);