1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static int hppa_address_cost (rtx);
88 static bool hppa_rtx_costs (rtx, int, int, int *);
89 static inline rtx force_mode (enum machine_mode, rtx);
90 static void pa_reorg (void);
91 static void pa_combine_instructions (void);
92 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
93 static int forward_branch_p (rtx);
94 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
95 static int compute_movmem_length (rtx);
96 static int compute_clrmem_length (rtx);
97 static bool pa_assemble_integer (rtx, unsigned int, int);
98 static void remove_useless_addtr_insns (int);
99 static void store_reg (int, HOST_WIDE_INT, int);
100 static void store_reg_modify (int, int, HOST_WIDE_INT);
101 static void load_reg (int, HOST_WIDE_INT, int);
102 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
103 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
104 static void update_total_code_bytes (int);
105 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
106 static int pa_adjust_cost (rtx, rtx, rtx, int);
107 static int pa_adjust_priority (rtx, int);
108 static int pa_issue_rate (void);
109 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
111 static void pa_encode_section_info (tree, rtx, int);
112 static const char *pa_strip_name_encoding (const char *);
113 static bool pa_function_ok_for_sibcall (tree, tree);
114 static void pa_globalize_label (FILE *, const char *)
116 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
117 HOST_WIDE_INT, tree);
118 #if !defined(USE_COLLECT2)
119 static void pa_asm_out_constructor (rtx, int);
120 static void pa_asm_out_destructor (rtx, int);
122 static void pa_init_builtins (void);
123 static rtx hppa_builtin_saveregs (void);
124 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
125 static bool pa_scalar_mode_supported_p (enum machine_mode);
126 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
127 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static struct deferred_plabel *get_plabel (rtx) ATTRIBUTE_UNUSED;
129 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
130 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
133 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
134 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
138 static void output_deferred_plabels (void);
139 #ifdef ASM_OUTPUT_EXTERNAL_REAL
140 static void pa_hpux_file_end (void);
142 #ifdef HPUX_LONG_DOUBLE_LIBRARY
143 static void pa_hpux_init_libfuncs (void);
145 static rtx pa_struct_value_rtx (tree, int);
146 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
148 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
150 static struct machine_function * pa_init_machine_status (void);
153 /* Save the operands last given to a compare for use when we
154 generate a scc or bcc insn. */
155 rtx hppa_compare_op0, hppa_compare_op1;
156 enum cmp_type hppa_branch_type;
158 /* Which architecture we are generating code for. */
159 enum architecture_type pa_arch;
161 /* String to hold which architecture we are generating code for. */
162 const char *pa_arch_string;
164 /* String used with the -mfixed-range= option. */
165 const char *pa_fixed_range_string;
167 /* Which cpu we are scheduling for. */
168 enum processor_type pa_cpu;
170 /* String to hold which cpu we are scheduling for. */
171 const char *pa_cpu_string;
173 /* String used with the -munix= option. */
174 const char *pa_unix_string;
176 /* The UNIX standard to use for predefines and linking. */
179 /* Counts for the number of callee-saved general and floating point
180 registers which were saved by the current function's prologue. */
181 static int gr_saved, fr_saved;
183 static rtx find_addr_reg (rtx);
185 /* Keep track of the number of bytes we have output in the CODE subspace
186 during this compilation so we'll know when to emit inline long-calls. */
187 unsigned long total_code_bytes;
189 /* The last address of the previous function plus the number of bytes in
190 associated thunks that have been output. This is used to determine if
191 a thunk can use an IA-relative branch to reach its target function. */
192 static int last_address;
194 /* Variables to handle plabels that we discover are necessary at assembly
195 output time. They are output after the current function. */
196 struct deferred_plabel GTY(())
201 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
203 static size_t n_deferred_plabels = 0;
206 /* Initialize the GCC target structure. */
208 #undef TARGET_ASM_ALIGNED_HI_OP
209 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
210 #undef TARGET_ASM_ALIGNED_SI_OP
211 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
212 #undef TARGET_ASM_ALIGNED_DI_OP
213 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
214 #undef TARGET_ASM_UNALIGNED_HI_OP
215 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
216 #undef TARGET_ASM_UNALIGNED_SI_OP
217 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
218 #undef TARGET_ASM_UNALIGNED_DI_OP
219 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
220 #undef TARGET_ASM_INTEGER
221 #define TARGET_ASM_INTEGER pa_assemble_integer
223 #undef TARGET_ASM_FUNCTION_PROLOGUE
224 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
225 #undef TARGET_ASM_FUNCTION_EPILOGUE
226 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
228 #undef TARGET_SCHED_ADJUST_COST
229 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
230 #undef TARGET_SCHED_ADJUST_PRIORITY
231 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
232 #undef TARGET_SCHED_ISSUE_RATE
233 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
235 #undef TARGET_ENCODE_SECTION_INFO
236 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
237 #undef TARGET_STRIP_NAME_ENCODING
238 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
240 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
241 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
243 #undef TARGET_ASM_OUTPUT_MI_THUNK
244 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
245 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
246 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
248 #undef TARGET_ASM_FILE_END
249 #ifdef ASM_OUTPUT_EXTERNAL_REAL
250 #define TARGET_ASM_FILE_END pa_hpux_file_end
252 #define TARGET_ASM_FILE_END output_deferred_plabels
255 #if !defined(USE_COLLECT2)
256 #undef TARGET_ASM_CONSTRUCTOR
257 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
258 #undef TARGET_ASM_DESTRUCTOR
259 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
262 #undef TARGET_INIT_BUILTINS
263 #define TARGET_INIT_BUILTINS pa_init_builtins
265 #undef TARGET_RTX_COSTS
266 #define TARGET_RTX_COSTS hppa_rtx_costs
267 #undef TARGET_ADDRESS_COST
268 #define TARGET_ADDRESS_COST hppa_address_cost
270 #undef TARGET_MACHINE_DEPENDENT_REORG
271 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
273 #ifdef HPUX_LONG_DOUBLE_LIBRARY
274 #undef TARGET_INIT_LIBFUNCS
275 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
278 #undef TARGET_PROMOTE_FUNCTION_RETURN
279 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
280 #undef TARGET_PROMOTE_PROTOTYPES
281 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
283 #undef TARGET_STRUCT_VALUE_RTX
284 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
285 #undef TARGET_RETURN_IN_MEMORY
286 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
287 #undef TARGET_MUST_PASS_IN_STACK
288 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
289 #undef TARGET_PASS_BY_REFERENCE
290 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
291 #undef TARGET_CALLEE_COPIES
292 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
293 #undef TARGET_ARG_PARTIAL_BYTES
294 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
296 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
297 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
298 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
299 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
301 #undef TARGET_SCALAR_MODE_SUPPORTED_P
302 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
304 struct gcc_target targetm = TARGET_INITIALIZER;
306 /* Parse the -mfixed-range= option string. */
309 fix_range (const char *const_str)
312 char *str, *dash, *comma;
314 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
315 REG2 are either register names or register numbers. The effect
316 of this option is to mark the registers in the range from REG1 to
317 REG2 as ``fixed'' so they won't be used by the compiler. This is
318 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
320 i = strlen (const_str);
321 str = (char *) alloca (i + 1);
322 memcpy (str, const_str, i + 1);
326 dash = strchr (str, '-');
329 warning ("value of -mfixed-range must have form REG1-REG2");
334 comma = strchr (dash + 1, ',');
338 first = decode_reg_name (str);
341 warning ("unknown register name: %s", str);
345 last = decode_reg_name (dash + 1);
348 warning ("unknown register name: %s", dash + 1);
356 warning ("%s-%s is an empty range", str, dash + 1);
360 for (i = first; i <= last; ++i)
361 fixed_regs[i] = call_used_regs[i] = 1;
370 /* Check if all floating point registers have been fixed. */
371 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
376 target_flags |= MASK_DISABLE_FPREGS;
380 override_options (void)
382 if (pa_cpu_string == NULL)
383 pa_cpu_string = TARGET_SCHED_DEFAULT;
385 if (! strcmp (pa_cpu_string, "8000"))
387 pa_cpu_string = "8000";
388 pa_cpu = PROCESSOR_8000;
390 else if (! strcmp (pa_cpu_string, "7100"))
392 pa_cpu_string = "7100";
393 pa_cpu = PROCESSOR_7100;
395 else if (! strcmp (pa_cpu_string, "700"))
397 pa_cpu_string = "700";
398 pa_cpu = PROCESSOR_700;
400 else if (! strcmp (pa_cpu_string, "7100LC"))
402 pa_cpu_string = "7100LC";
403 pa_cpu = PROCESSOR_7100LC;
405 else if (! strcmp (pa_cpu_string, "7200"))
407 pa_cpu_string = "7200";
408 pa_cpu = PROCESSOR_7200;
410 else if (! strcmp (pa_cpu_string, "7300"))
412 pa_cpu_string = "7300";
413 pa_cpu = PROCESSOR_7300;
417 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
420 /* Set the instruction architecture. */
421 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
423 pa_arch_string = "1.0";
424 pa_arch = ARCHITECTURE_10;
425 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
427 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
429 pa_arch_string = "1.1";
430 pa_arch = ARCHITECTURE_11;
431 target_flags &= ~MASK_PA_20;
432 target_flags |= MASK_PA_11;
434 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
436 pa_arch_string = "2.0";
437 pa_arch = ARCHITECTURE_20;
438 target_flags |= MASK_PA_11 | MASK_PA_20;
440 else if (pa_arch_string)
442 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
447 /* Set the default UNIX standard for HP-UX. This affects the
448 predefines and startfiles used for the target. */
449 if (pa_unix_string == NULL)
451 = TARGET_HPUX_11_11 ? "98" : (TARGET_HPUX_10_10 ? "95" : "93");
453 if (!strcmp (pa_unix_string, "93"))
455 else if (!strcmp (pa_unix_string, "95"))
457 else if (TARGET_HPUX_11_11)
459 if (!strcmp (pa_unix_string, "98"))
462 warning ("unknown -munix= option (%s).\n"
463 "Valid options are 93, 95 and 98.\n",
466 else if (TARGET_HPUX_10_10)
467 warning ("unknown -munix= option (%s)."
468 "\nValid options are 93 and 95.\n",
471 warning ("unknown -munix= option (%s).\nValid option is 93.\n",
475 if (pa_fixed_range_string)
476 fix_range (pa_fixed_range_string);
478 /* Unconditional branches in the delay slot are not compatible with dwarf2
479 call frame information. There is no benefit in using this optimization
480 on PA8000 and later processors. */
481 if (pa_cpu >= PROCESSOR_8000
482 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
483 || flag_unwind_tables)
484 target_flags &= ~MASK_JUMP_IN_DELAY;
486 if (flag_pic && TARGET_PORTABLE_RUNTIME)
488 warning ("PIC code generation is not supported in the portable runtime model\n");
491 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
493 warning ("PIC code generation is not compatible with fast indirect calls\n");
496 if (! TARGET_GAS && write_symbols != NO_DEBUG)
498 warning ("-g is only supported when using GAS on this processor,");
499 warning ("-g option disabled");
500 write_symbols = NO_DEBUG;
503 /* We only support the "big PIC" model now. And we always generate PIC
504 code when in 64bit mode. */
505 if (flag_pic == 1 || TARGET_64BIT)
508 /* We can't guarantee that .dword is available for 32-bit targets. */
509 if (UNITS_PER_WORD == 4)
510 targetm.asm_out.aligned_op.di = NULL;
512 /* The unaligned ops are only available when using GAS. */
515 targetm.asm_out.unaligned_op.hi = NULL;
516 targetm.asm_out.unaligned_op.si = NULL;
517 targetm.asm_out.unaligned_op.di = NULL;
520 init_machine_status = pa_init_machine_status;
524 pa_init_builtins (void)
526 #ifdef DONT_HAVE_FPUTC_UNLOCKED
527 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
528 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
532 /* Function to init struct machine_function.
533 This will be called, via a pointer variable,
534 from push_function_context. */
536 static struct machine_function *
537 pa_init_machine_status (void)
539 return ggc_alloc_cleared (sizeof (machine_function));
542 /* If FROM is a probable pointer register, mark TO as a probable
543 pointer register with the same pointer alignment as FROM. */
546 copy_reg_pointer (rtx to, rtx from)
548 if (REG_POINTER (from))
549 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
552 /* Return 1 if X contains a symbolic expression. We know these
553 expressions will have one of a few well defined forms, so
554 we need only check those forms. */
556 symbolic_expression_p (rtx x)
559 /* Strip off any HIGH. */
560 if (GET_CODE (x) == HIGH)
563 return (symbolic_operand (x, VOIDmode));
566 /* Accept any constant that can be moved in one instruction into a
569 cint_ok_for_move (HOST_WIDE_INT intval)
571 /* OK if ldo, ldil, or zdepi, can be used. */
572 return (CONST_OK_FOR_LETTER_P (intval, 'J')
573 || CONST_OK_FOR_LETTER_P (intval, 'N')
574 || CONST_OK_FOR_LETTER_P (intval, 'K'));
577 /* Return truth value of whether OP can be used as an operand in a
580 adddi3_operand (rtx op, enum machine_mode mode)
582 return (register_operand (op, mode)
583 || (GET_CODE (op) == CONST_INT
584 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
587 /* True iff zdepi can be used to generate this CONST_INT.
588 zdepi first sign extends a 5 bit signed number to a given field
589 length, then places this field anywhere in a zero. */
591 zdepi_cint_p (unsigned HOST_WIDE_INT x)
593 unsigned HOST_WIDE_INT lsb_mask, t;
595 /* This might not be obvious, but it's at least fast.
596 This function is critical; we don't have the time loops would take. */
598 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
599 /* Return true iff t is a power of two. */
600 return ((t & (t - 1)) == 0);
603 /* True iff depi or extru can be used to compute (reg & mask).
604 Accept bit pattern like these:
609 and_mask_p (unsigned HOST_WIDE_INT mask)
612 mask += mask & -mask;
613 return (mask & (mask - 1)) == 0;
616 /* True iff depi can be used to compute (reg | MASK). */
618 ior_mask_p (unsigned HOST_WIDE_INT mask)
620 mask += mask & -mask;
621 return (mask & (mask - 1)) == 0;
624 /* Legitimize PIC addresses. If the address is already
625 position-independent, we return ORIG. Newly generated
626 position-independent addresses go to REG. If we need more
627 than one register, we lose. */
630 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
634 /* Labels need special handling. */
635 if (pic_label_operand (orig, mode))
637 /* We do not want to go through the movXX expanders here since that
638 would create recursion.
640 Nor do we really want to call a generator for a named pattern
641 since that requires multiple patterns if we want to support
644 So instead we just emit the raw set, which avoids the movXX
645 expanders completely. */
646 mark_reg_pointer (reg, BITS_PER_UNIT);
647 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
648 current_function_uses_pic_offset_table = 1;
651 if (GET_CODE (orig) == SYMBOL_REF)
657 /* Before reload, allocate a temporary register for the intermediate
658 result. This allows the sequence to be deleted when the final
659 result is unused and the insns are trivially dead. */
660 tmp_reg = ((reload_in_progress || reload_completed)
661 ? reg : gen_reg_rtx (Pmode));
663 emit_move_insn (tmp_reg,
664 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
665 gen_rtx_HIGH (word_mode, orig)));
667 = gen_const_mem (Pmode,
668 gen_rtx_LO_SUM (Pmode, tmp_reg,
669 gen_rtx_UNSPEC (Pmode,
673 current_function_uses_pic_offset_table = 1;
674 mark_reg_pointer (reg, BITS_PER_UNIT);
675 insn = emit_move_insn (reg, pic_ref);
677 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
678 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
682 else if (GET_CODE (orig) == CONST)
686 if (GET_CODE (XEXP (orig, 0)) == PLUS
687 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
691 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
693 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
694 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
695 base == reg ? 0 : reg);
697 if (GET_CODE (orig) == CONST_INT)
699 if (INT_14_BITS (orig))
700 return plus_constant (base, INTVAL (orig));
701 orig = force_reg (Pmode, orig);
703 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
704 /* Likewise, should we set special REG_NOTEs here? */
710 /* Try machine-dependent ways of modifying an illegitimate address
711 to be legitimate. If we find one, return the new, valid address.
712 This macro is used in only one place: `memory_address' in explow.c.
714 OLDX is the address as it was before break_out_memory_refs was called.
715 In some cases it is useful to look at this to decide what needs to be done.
717 MODE and WIN are passed so that this macro can use
718 GO_IF_LEGITIMATE_ADDRESS.
720 It is always safe for this macro to do nothing. It exists to recognize
721 opportunities to optimize the output.
723 For the PA, transform:
725 memory(X + <large int>)
729 if (<large int> & mask) >= 16
730 Y = (<large int> & ~mask) + mask + 1 Round up.
732 Y = (<large int> & ~mask) Round down.
734 memory (Z + (<large int> - Y));
736 This is for CSE to find several similar references, and only use one Z.
738 X can either be a SYMBOL_REF or REG, but because combine cannot
739 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
740 D will not fit in 14 bits.
742 MODE_FLOAT references allow displacements which fit in 5 bits, so use
745 MODE_INT references allow displacements which fit in 14 bits, so use
748 This relies on the fact that most mode MODE_FLOAT references will use FP
749 registers and most mode MODE_INT references will use integer registers.
750 (In the rare case of an FP register used in an integer MODE, we depend
751 on secondary reloads to clean things up.)
754 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
755 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
756 addressing modes to be used).
758 Put X and Z into registers. Then put the entire expression into
762 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
763 enum machine_mode mode)
767 /* We need to canonicalize the order of operands in unscaled indexed
768 addresses since the code that checks if an address is valid doesn't
769 always try both orders. */
770 if (!TARGET_NO_SPACE_REGS
771 && GET_CODE (x) == PLUS
772 && GET_MODE (x) == Pmode
773 && REG_P (XEXP (x, 0))
774 && REG_P (XEXP (x, 1))
775 && REG_POINTER (XEXP (x, 0))
776 && !REG_POINTER (XEXP (x, 1)))
777 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
780 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
782 /* Strip off CONST. */
783 if (GET_CODE (x) == CONST)
786 /* Special case. Get the SYMBOL_REF into a register and use indexing.
787 That should always be safe. */
788 if (GET_CODE (x) == PLUS
789 && GET_CODE (XEXP (x, 0)) == REG
790 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
792 rtx reg = force_reg (Pmode, XEXP (x, 1));
793 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
796 /* Note we must reject symbols which represent function addresses
797 since the assembler/linker can't handle arithmetic on plabels. */
798 if (GET_CODE (x) == PLUS
799 && GET_CODE (XEXP (x, 1)) == CONST_INT
800 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
801 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
802 || GET_CODE (XEXP (x, 0)) == REG))
804 rtx int_part, ptr_reg;
806 int offset = INTVAL (XEXP (x, 1));
809 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
810 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
812 /* Choose which way to round the offset. Round up if we
813 are >= halfway to the next boundary. */
814 if ((offset & mask) >= ((mask + 1) / 2))
815 newoffset = (offset & ~ mask) + mask + 1;
817 newoffset = (offset & ~ mask);
819 /* If the newoffset will not fit in 14 bits (ldo), then
820 handling this would take 4 or 5 instructions (2 to load
821 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
822 add the new offset and the SYMBOL_REF.) Combine can
823 not handle 4->2 or 5->2 combinations, so do not create
825 if (! VAL_14_BITS_P (newoffset)
826 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
828 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
831 gen_rtx_HIGH (Pmode, const_part));
834 gen_rtx_LO_SUM (Pmode,
835 tmp_reg, const_part));
839 if (! VAL_14_BITS_P (newoffset))
840 int_part = force_reg (Pmode, GEN_INT (newoffset));
842 int_part = GEN_INT (newoffset);
844 ptr_reg = force_reg (Pmode,
846 force_reg (Pmode, XEXP (x, 0)),
849 return plus_constant (ptr_reg, offset - newoffset);
852 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
854 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
855 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
856 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
857 && (OBJECT_P (XEXP (x, 1))
858 || GET_CODE (XEXP (x, 1)) == SUBREG)
859 && GET_CODE (XEXP (x, 1)) != CONST)
861 int val = INTVAL (XEXP (XEXP (x, 0), 1));
865 if (GET_CODE (reg1) != REG)
866 reg1 = force_reg (Pmode, force_operand (reg1, 0));
868 reg2 = XEXP (XEXP (x, 0), 0);
869 if (GET_CODE (reg2) != REG)
870 reg2 = force_reg (Pmode, force_operand (reg2, 0));
872 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
879 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
881 Only do so for floating point modes since this is more speculative
882 and we lose if it's an integer store. */
883 if (GET_CODE (x) == PLUS
884 && GET_CODE (XEXP (x, 0)) == PLUS
885 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
886 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
887 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
888 && (mode == SFmode || mode == DFmode))
891 /* First, try and figure out what to use as a base register. */
892 rtx reg1, reg2, base, idx, orig_base;
894 reg1 = XEXP (XEXP (x, 0), 1);
899 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
900 then emit_move_sequence will turn on REG_POINTER so we'll know
901 it's a base register below. */
902 if (GET_CODE (reg1) != REG)
903 reg1 = force_reg (Pmode, force_operand (reg1, 0));
905 if (GET_CODE (reg2) != REG)
906 reg2 = force_reg (Pmode, force_operand (reg2, 0));
908 /* Figure out what the base and index are. */
910 if (GET_CODE (reg1) == REG
911 && REG_POINTER (reg1))
914 orig_base = XEXP (XEXP (x, 0), 1);
915 idx = gen_rtx_PLUS (Pmode,
917 XEXP (XEXP (XEXP (x, 0), 0), 0),
918 XEXP (XEXP (XEXP (x, 0), 0), 1)),
921 else if (GET_CODE (reg2) == REG
922 && REG_POINTER (reg2))
925 orig_base = XEXP (x, 1);
932 /* If the index adds a large constant, try to scale the
933 constant so that it can be loaded with only one insn. */
934 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
935 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
936 / INTVAL (XEXP (XEXP (idx, 0), 1)))
937 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
939 /* Divide the CONST_INT by the scale factor, then add it to A. */
940 int val = INTVAL (XEXP (idx, 1));
942 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
943 reg1 = XEXP (XEXP (idx, 0), 0);
944 if (GET_CODE (reg1) != REG)
945 reg1 = force_reg (Pmode, force_operand (reg1, 0));
947 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
949 /* We can now generate a simple scaled indexed address. */
952 (Pmode, gen_rtx_PLUS (Pmode,
953 gen_rtx_MULT (Pmode, reg1,
954 XEXP (XEXP (idx, 0), 1)),
958 /* If B + C is still a valid base register, then add them. */
959 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
960 && INTVAL (XEXP (idx, 1)) <= 4096
961 && INTVAL (XEXP (idx, 1)) >= -4096)
963 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
966 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
968 reg2 = XEXP (XEXP (idx, 0), 0);
969 if (GET_CODE (reg2) != CONST_INT)
970 reg2 = force_reg (Pmode, force_operand (reg2, 0));
972 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
979 /* Get the index into a register, then add the base + index and
980 return a register holding the result. */
982 /* First get A into a register. */
983 reg1 = XEXP (XEXP (idx, 0), 0);
984 if (GET_CODE (reg1) != REG)
985 reg1 = force_reg (Pmode, force_operand (reg1, 0));
987 /* And get B into a register. */
988 reg2 = XEXP (idx, 1);
989 if (GET_CODE (reg2) != REG)
990 reg2 = force_reg (Pmode, force_operand (reg2, 0));
992 reg1 = force_reg (Pmode,
994 gen_rtx_MULT (Pmode, reg1,
995 XEXP (XEXP (idx, 0), 1)),
998 /* Add the result to our base register and return. */
999 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1003 /* Uh-oh. We might have an address for x[n-100000]. This needs
1004 special handling to avoid creating an indexed memory address
1005 with x-100000 as the base.
1007 If the constant part is small enough, then it's still safe because
1008 there is a guard page at the beginning and end of the data segment.
1010 Scaled references are common enough that we want to try and rearrange the
1011 terms so that we can use indexing for these addresses too. Only
1012 do the optimization for floatint point modes. */
1014 if (GET_CODE (x) == PLUS
1015 && symbolic_expression_p (XEXP (x, 1)))
1017 /* Ugly. We modify things here so that the address offset specified
1018 by the index expression is computed first, then added to x to form
1019 the entire address. */
1021 rtx regx1, regx2, regy1, regy2, y;
1023 /* Strip off any CONST. */
1025 if (GET_CODE (y) == CONST)
1028 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1030 /* See if this looks like
1031 (plus (mult (reg) (shadd_const))
1032 (const (plus (symbol_ref) (const_int))))
1034 Where const_int is small. In that case the const
1035 expression is a valid pointer for indexing.
1037 If const_int is big, but can be divided evenly by shadd_const
1038 and added to (reg). This allows more scaled indexed addresses. */
1039 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1040 && GET_CODE (XEXP (x, 0)) == MULT
1041 && GET_CODE (XEXP (y, 1)) == CONST_INT
1042 && INTVAL (XEXP (y, 1)) >= -4096
1043 && INTVAL (XEXP (y, 1)) <= 4095
1044 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1045 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1047 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1051 if (GET_CODE (reg1) != REG)
1052 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1054 reg2 = XEXP (XEXP (x, 0), 0);
1055 if (GET_CODE (reg2) != REG)
1056 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1058 return force_reg (Pmode,
1059 gen_rtx_PLUS (Pmode,
1060 gen_rtx_MULT (Pmode,
1065 else if ((mode == DFmode || mode == SFmode)
1066 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1067 && GET_CODE (XEXP (x, 0)) == MULT
1068 && GET_CODE (XEXP (y, 1)) == CONST_INT
1069 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1070 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1071 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1074 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1075 / INTVAL (XEXP (XEXP (x, 0), 1))));
1076 regx2 = XEXP (XEXP (x, 0), 0);
1077 if (GET_CODE (regx2) != REG)
1078 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1079 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1083 gen_rtx_PLUS (Pmode,
1084 gen_rtx_MULT (Pmode, regx2,
1085 XEXP (XEXP (x, 0), 1)),
1086 force_reg (Pmode, XEXP (y, 0))));
1088 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1089 && INTVAL (XEXP (y, 1)) >= -4096
1090 && INTVAL (XEXP (y, 1)) <= 4095)
1092 /* This is safe because of the guard page at the
1093 beginning and end of the data space. Just
1094 return the original address. */
1099 /* Doesn't look like one we can optimize. */
1100 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1101 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1102 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1103 regx1 = force_reg (Pmode,
1104 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1106 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1114 /* For the HPPA, REG and REG+CONST is cost 0
1115 and addresses involving symbolic constants are cost 2.
1117 PIC addresses are very expensive.
1119 It is no coincidence that this has the same structure
1120 as GO_IF_LEGITIMATE_ADDRESS. */
1123 hppa_address_cost (rtx X)
1125 switch (GET_CODE (X))
1138 /* Compute a (partial) cost for rtx X. Return true if the complete
1139 cost has been computed, and false if subexpressions should be
1140 scanned. In either case, *TOTAL contains the cost result. */
1143 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1148 if (INTVAL (x) == 0)
1150 else if (INT_14_BITS (x))
1167 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1168 && outer_code != SET)
1175 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1176 *total = COSTS_N_INSNS (3);
1177 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1178 *total = COSTS_N_INSNS (8);
1180 *total = COSTS_N_INSNS (20);
1184 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1186 *total = COSTS_N_INSNS (14);
1194 *total = COSTS_N_INSNS (60);
1197 case PLUS: /* this includes shNadd insns */
1199 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1200 *total = COSTS_N_INSNS (3);
1202 *total = COSTS_N_INSNS (1);
1208 *total = COSTS_N_INSNS (1);
1216 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1217 new rtx with the correct mode. */
1219 force_mode (enum machine_mode mode, rtx orig)
1221 if (mode == GET_MODE (orig))
1224 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1226 return gen_rtx_REG (mode, REGNO (orig));
1229 /* Emit insns to move operands[1] into operands[0].
1231 Return 1 if we have written out everything that needs to be done to
1232 do the move. Otherwise, return 0 and the caller will emit the move
1235 Note SCRATCH_REG may not be in the proper mode depending on how it
1236 will be used. This routine is responsible for creating a new copy
1237 of SCRATCH_REG in the proper mode. */
1240 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1242 register rtx operand0 = operands[0];
1243 register rtx operand1 = operands[1];
1246 /* We can only handle indexed addresses in the destination operand
1247 of floating point stores. Thus, we need to break out indexed
1248 addresses from the destination operand. */
1249 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1251 /* This is only safe up to the beginning of life analysis. */
1252 gcc_assert (!no_new_pseudos);
1254 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1255 operand0 = replace_equiv_address (operand0, tem);
1258 /* On targets with non-equivalent space registers, break out unscaled
1259 indexed addresses from the source operand before the final CSE.
1260 We have to do this because the REG_POINTER flag is not correctly
1261 carried through various optimization passes and CSE may substitute
1262 a pseudo without the pointer set for one with the pointer set. As
1263 a result, we loose various opportunities to create insns with
1264 unscaled indexed addresses. */
1265 if (!TARGET_NO_SPACE_REGS
1266 && !cse_not_expected
1267 && GET_CODE (operand1) == MEM
1268 && GET_CODE (XEXP (operand1, 0)) == PLUS
1269 && REG_P (XEXP (XEXP (operand1, 0), 0))
1270 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1272 = replace_equiv_address (operand1,
1273 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1276 && reload_in_progress && GET_CODE (operand0) == REG
1277 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1278 operand0 = reg_equiv_mem[REGNO (operand0)];
1279 else if (scratch_reg
1280 && reload_in_progress && GET_CODE (operand0) == SUBREG
1281 && GET_CODE (SUBREG_REG (operand0)) == REG
1282 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1284 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1285 the code which tracks sets/uses for delete_output_reload. */
1286 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1287 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1288 SUBREG_BYTE (operand0));
1289 operand0 = alter_subreg (&temp);
1293 && reload_in_progress && GET_CODE (operand1) == REG
1294 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1295 operand1 = reg_equiv_mem[REGNO (operand1)];
1296 else if (scratch_reg
1297 && reload_in_progress && GET_CODE (operand1) == SUBREG
1298 && GET_CODE (SUBREG_REG (operand1)) == REG
1299 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1301 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1302 the code which tracks sets/uses for delete_output_reload. */
1303 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1304 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1305 SUBREG_BYTE (operand1));
1306 operand1 = alter_subreg (&temp);
1309 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1310 && ((tem = find_replacement (&XEXP (operand0, 0)))
1311 != XEXP (operand0, 0)))
1312 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1314 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1315 && ((tem = find_replacement (&XEXP (operand1, 0)))
1316 != XEXP (operand1, 0)))
1317 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1319 /* Handle secondary reloads for loads/stores of FP registers from
1320 REG+D addresses where D does not fit in 5 or 14 bits, including
1321 (subreg (mem (addr))) cases. */
1323 && fp_reg_operand (operand0, mode)
1324 && ((GET_CODE (operand1) == MEM
1325 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1326 XEXP (operand1, 0)))
1327 || ((GET_CODE (operand1) == SUBREG
1328 && GET_CODE (XEXP (operand1, 0)) == MEM
1329 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1331 XEXP (XEXP (operand1, 0), 0))))))
1333 if (GET_CODE (operand1) == SUBREG)
1334 operand1 = XEXP (operand1, 0);
1336 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1337 it in WORD_MODE regardless of what mode it was originally given
1339 scratch_reg = force_mode (word_mode, scratch_reg);
1341 /* D might not fit in 14 bits either; for such cases load D into
1343 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1345 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1346 emit_move_insn (scratch_reg,
1347 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1349 XEXP (XEXP (operand1, 0), 0),
1353 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1354 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1355 gen_rtx_MEM (mode, scratch_reg)));
1358 else if (scratch_reg
1359 && fp_reg_operand (operand1, mode)
1360 && ((GET_CODE (operand0) == MEM
1361 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1363 XEXP (operand0, 0)))
1364 || ((GET_CODE (operand0) == SUBREG)
1365 && GET_CODE (XEXP (operand0, 0)) == MEM
1366 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1368 XEXP (XEXP (operand0, 0), 0)))))
1370 if (GET_CODE (operand0) == SUBREG)
1371 operand0 = XEXP (operand0, 0);
1373 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1374 it in WORD_MODE regardless of what mode it was originally given
1376 scratch_reg = force_mode (word_mode, scratch_reg);
1378 /* D might not fit in 14 bits either; for such cases load D into
1380 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1382 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1383 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1386 XEXP (XEXP (operand0, 0),
1391 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1392 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1396 /* Handle secondary reloads for loads of FP registers from constant
1397 expressions by forcing the constant into memory.
1399 Use scratch_reg to hold the address of the memory location.
1401 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1402 NO_REGS when presented with a const_int and a register class
1403 containing only FP registers. Doing so unfortunately creates
1404 more problems than it solves. Fix this for 2.5. */
1405 else if (scratch_reg
1406 && CONSTANT_P (operand1)
1407 && fp_reg_operand (operand0, mode))
1411 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1412 it in WORD_MODE regardless of what mode it was originally given
1414 scratch_reg = force_mode (word_mode, scratch_reg);
1416 /* Force the constant into memory and put the address of the
1417 memory location into scratch_reg. */
1418 xoperands[0] = scratch_reg;
1419 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1420 emit_move_sequence (xoperands, Pmode, 0);
1422 /* Now load the destination register. */
1423 emit_insn (gen_rtx_SET (mode, operand0,
1424 gen_rtx_MEM (mode, scratch_reg)));
1427 /* Handle secondary reloads for SAR. These occur when trying to load
1428 the SAR from memory, FP register, or with a constant. */
1429 else if (scratch_reg
1430 && GET_CODE (operand0) == REG
1431 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1432 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1433 && (GET_CODE (operand1) == MEM
1434 || GET_CODE (operand1) == CONST_INT
1435 || (GET_CODE (operand1) == REG
1436 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1438 /* D might not fit in 14 bits either; for such cases load D into
1440 if (GET_CODE (operand1) == MEM
1441 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1443 /* We are reloading the address into the scratch register, so we
1444 want to make sure the scratch register is a full register. */
1445 scratch_reg = force_mode (word_mode, scratch_reg);
1447 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1448 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1451 XEXP (XEXP (operand1, 0),
1455 /* Now we are going to load the scratch register from memory,
1456 we want to load it in the same width as the original MEM,
1457 which must be the same as the width of the ultimate destination,
1459 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1461 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1466 /* We want to load the scratch register using the same mode as
1467 the ultimate destination. */
1468 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1470 emit_move_insn (scratch_reg, operand1);
1473 /* And emit the insn to set the ultimate destination. We know that
1474 the scratch register has the same mode as the destination at this
1476 emit_move_insn (operand0, scratch_reg);
1479 /* Handle the most common case: storing into a register. */
1480 else if (register_operand (operand0, mode))
1482 if (register_operand (operand1, mode)
1483 || (GET_CODE (operand1) == CONST_INT
1484 && cint_ok_for_move (INTVAL (operand1)))
1485 || (operand1 == CONST0_RTX (mode))
1486 || (GET_CODE (operand1) == HIGH
1487 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1488 /* Only `general_operands' can come here, so MEM is ok. */
1489 || GET_CODE (operand1) == MEM)
1491 /* Various sets are created during RTL generation which don't
1492 have the REG_POINTER flag correctly set. After the CSE pass,
1493 instruction recognition can fail if we don't consistently
1494 set this flag when performing register copies. This should
1495 also improve the opportunities for creating insns that use
1496 unscaled indexing. */
1497 if (REG_P (operand0) && REG_P (operand1))
1499 if (REG_POINTER (operand1)
1500 && !REG_POINTER (operand0)
1501 && !HARD_REGISTER_P (operand0))
1502 copy_reg_pointer (operand0, operand1);
1503 else if (REG_POINTER (operand0)
1504 && !REG_POINTER (operand1)
1505 && !HARD_REGISTER_P (operand1))
1506 copy_reg_pointer (operand1, operand0);
1509 /* When MEMs are broken out, the REG_POINTER flag doesn't
1510 get set. In some cases, we can set the REG_POINTER flag
1511 from the declaration for the MEM. */
1512 if (REG_P (operand0)
1513 && GET_CODE (operand1) == MEM
1514 && !REG_POINTER (operand0))
1516 tree decl = MEM_EXPR (operand1);
1518 /* Set the register pointer flag and register alignment
1519 if the declaration for this memory reference is a
1520 pointer type. Fortran indirect argument references
1523 && !(flag_argument_noalias > 1
1524 && TREE_CODE (decl) == INDIRECT_REF
1525 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1529 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1531 if (TREE_CODE (decl) == COMPONENT_REF)
1532 decl = TREE_OPERAND (decl, 1);
1534 type = TREE_TYPE (decl);
1535 if (TREE_CODE (type) == ARRAY_TYPE)
1536 type = get_inner_array_type (type);
1538 if (POINTER_TYPE_P (type))
1542 type = TREE_TYPE (type);
1543 /* Using TYPE_ALIGN_OK is rather conservative as
1544 only the ada frontend actually sets it. */
1545 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1547 mark_reg_pointer (operand0, align);
1552 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1556 else if (GET_CODE (operand0) == MEM)
1558 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1559 && !(reload_in_progress || reload_completed))
1561 rtx temp = gen_reg_rtx (DFmode);
1563 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1564 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1567 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1569 /* Run this case quickly. */
1570 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1573 if (! (reload_in_progress || reload_completed))
1575 operands[0] = validize_mem (operand0);
1576 operands[1] = operand1 = force_reg (mode, operand1);
1580 /* Simplify the source if we need to.
1581 Note we do have to handle function labels here, even though we do
1582 not consider them legitimate constants. Loop optimizations can
1583 call the emit_move_xxx with one as a source. */
1584 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1585 || function_label_operand (operand1, mode)
1586 || (GET_CODE (operand1) == HIGH
1587 && symbolic_operand (XEXP (operand1, 0), mode)))
1591 if (GET_CODE (operand1) == HIGH)
1594 operand1 = XEXP (operand1, 0);
1596 if (symbolic_operand (operand1, mode))
1598 /* Argh. The assembler and linker can't handle arithmetic
1601 So we force the plabel into memory, load operand0 from
1602 the memory location, then add in the constant part. */
1603 if ((GET_CODE (operand1) == CONST
1604 && GET_CODE (XEXP (operand1, 0)) == PLUS
1605 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1606 || function_label_operand (operand1, mode))
1608 rtx temp, const_part;
1610 /* Figure out what (if any) scratch register to use. */
1611 if (reload_in_progress || reload_completed)
1613 scratch_reg = scratch_reg ? scratch_reg : operand0;
1614 /* SCRATCH_REG will hold an address and maybe the actual
1615 data. We want it in WORD_MODE regardless of what mode it
1616 was originally given to us. */
1617 scratch_reg = force_mode (word_mode, scratch_reg);
1620 scratch_reg = gen_reg_rtx (Pmode);
1622 if (GET_CODE (operand1) == CONST)
1624 /* Save away the constant part of the expression. */
1625 const_part = XEXP (XEXP (operand1, 0), 1);
1626 gcc_assert (GET_CODE (const_part) == CONST_INT);
1628 /* Force the function label into memory. */
1629 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1633 /* No constant part. */
1634 const_part = NULL_RTX;
1636 /* Force the function label into memory. */
1637 temp = force_const_mem (mode, operand1);
1641 /* Get the address of the memory location. PIC-ify it if
1643 temp = XEXP (temp, 0);
1645 temp = legitimize_pic_address (temp, mode, scratch_reg);
1647 /* Put the address of the memory location into our destination
1650 emit_move_sequence (operands, mode, scratch_reg);
1652 /* Now load from the memory location into our destination
1654 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1655 emit_move_sequence (operands, mode, scratch_reg);
1657 /* And add back in the constant part. */
1658 if (const_part != NULL_RTX)
1659 expand_inc (operand0, const_part);
1668 if (reload_in_progress || reload_completed)
1670 temp = scratch_reg ? scratch_reg : operand0;
1671 /* TEMP will hold an address and maybe the actual
1672 data. We want it in WORD_MODE regardless of what mode it
1673 was originally given to us. */
1674 temp = force_mode (word_mode, temp);
1677 temp = gen_reg_rtx (Pmode);
1679 /* (const (plus (symbol) (const_int))) must be forced to
1680 memory during/after reload if the const_int will not fit
1682 if (GET_CODE (operand1) == CONST
1683 && GET_CODE (XEXP (operand1, 0)) == PLUS
1684 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1685 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1686 && (reload_completed || reload_in_progress)
1689 operands[1] = force_const_mem (mode, operand1);
1690 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1692 operands[1] = gen_rtx_MEM (mode, operands[1]);
1693 emit_move_sequence (operands, mode, temp);
1697 operands[1] = legitimize_pic_address (operand1, mode, temp);
1698 if (REG_P (operand0) && REG_P (operands[1]))
1699 copy_reg_pointer (operand0, operands[1]);
1700 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1703 /* On the HPPA, references to data space are supposed to use dp,
1704 register 27, but showing it in the RTL inhibits various cse
1705 and loop optimizations. */
1710 if (reload_in_progress || reload_completed)
1712 temp = scratch_reg ? scratch_reg : operand0;
1713 /* TEMP will hold an address and maybe the actual
1714 data. We want it in WORD_MODE regardless of what mode it
1715 was originally given to us. */
1716 temp = force_mode (word_mode, temp);
1719 temp = gen_reg_rtx (mode);
1721 /* Loading a SYMBOL_REF into a register makes that register
1722 safe to be used as the base in an indexed address.
1724 Don't mark hard registers though. That loses. */
1725 if (GET_CODE (operand0) == REG
1726 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1727 mark_reg_pointer (operand0, BITS_PER_UNIT);
1728 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1729 mark_reg_pointer (temp, BITS_PER_UNIT);
1732 set = gen_rtx_SET (mode, operand0, temp);
1734 set = gen_rtx_SET (VOIDmode,
1736 gen_rtx_LO_SUM (mode, temp, operand1));
1738 emit_insn (gen_rtx_SET (VOIDmode,
1740 gen_rtx_HIGH (mode, operand1)));
1746 else if (GET_CODE (operand1) != CONST_INT
1747 || !cint_ok_for_move (INTVAL (operand1)))
1751 HOST_WIDE_INT value = 0;
1752 HOST_WIDE_INT insv = 0;
1755 if (GET_CODE (operand1) == CONST_INT)
1756 value = INTVAL (operand1);
1759 && GET_CODE (operand1) == CONST_INT
1760 && HOST_BITS_PER_WIDE_INT > 32
1761 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1765 /* Extract the low order 32 bits of the value and sign extend.
1766 If the new value is the same as the original value, we can
1767 can use the original value as-is. If the new value is
1768 different, we use it and insert the most-significant 32-bits
1769 of the original value into the final result. */
1770 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1771 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1774 #if HOST_BITS_PER_WIDE_INT > 32
1775 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1779 operand1 = GEN_INT (nval);
1783 if (reload_in_progress || reload_completed)
1784 temp = scratch_reg ? scratch_reg : operand0;
1786 temp = gen_reg_rtx (mode);
1788 /* We don't directly split DImode constants on 32-bit targets
1789 because PLUS uses an 11-bit immediate and the insn sequence
1790 generated is not as efficient as the one using HIGH/LO_SUM. */
1791 if (GET_CODE (operand1) == CONST_INT
1792 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1795 /* Directly break constant into high and low parts. This
1796 provides better optimization opportunities because various
1797 passes recognize constants split with PLUS but not LO_SUM.
1798 We use a 14-bit signed low part except when the addition
1799 of 0x4000 to the high part might change the sign of the
1801 HOST_WIDE_INT low = value & 0x3fff;
1802 HOST_WIDE_INT high = value & ~ 0x3fff;
1806 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1814 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1815 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1819 emit_insn (gen_rtx_SET (VOIDmode, temp,
1820 gen_rtx_HIGH (mode, operand1)));
1821 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1824 insn = emit_move_insn (operands[0], operands[1]);
1826 /* Now insert the most significant 32 bits of the value
1827 into the register. When we don't have a second register
1828 available, it could take up to nine instructions to load
1829 a 64-bit integer constant. Prior to reload, we force
1830 constants that would take more than three instructions
1831 to load to the constant pool. During and after reload,
1832 we have to handle all possible values. */
1835 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
1836 register and the value to be inserted is outside the
1837 range that can be loaded with three depdi instructions. */
1838 if (temp != operand0 && (insv >= 16384 || insv < -16384))
1840 operand1 = GEN_INT (insv);
1842 emit_insn (gen_rtx_SET (VOIDmode, temp,
1843 gen_rtx_HIGH (mode, operand1)));
1844 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
1845 emit_insn (gen_insv (operand0, GEN_INT (32),
1850 int len = 5, pos = 27;
1852 /* Insert the bits using the depdi instruction. */
1855 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
1856 HOST_WIDE_INT sign = v5 < 0;
1858 /* Left extend the insertion. */
1859 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
1860 while (pos > 0 && (insv & 1) == sign)
1862 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
1867 emit_insn (gen_insv (operand0, GEN_INT (len),
1868 GEN_INT (pos), GEN_INT (v5)));
1870 len = pos > 0 && pos < 5 ? pos : 5;
1877 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
1882 /* Now have insn-emit do whatever it normally does. */
1886 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1887 it will need a link/runtime reloc). */
1890 reloc_needed (tree exp)
1894 switch (TREE_CODE (exp))
1901 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1902 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1907 case NON_LVALUE_EXPR:
1908 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1914 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1915 if (TREE_VALUE (link) != 0)
1916 reloc |= reloc_needed (TREE_VALUE (link));
1929 /* Does operand (which is a symbolic_operand) live in text space?
1930 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1934 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
1936 if (GET_CODE (operand) == CONST)
1937 operand = XEXP (XEXP (operand, 0), 0);
1940 if (GET_CODE (operand) == SYMBOL_REF)
1941 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1945 if (GET_CODE (operand) == SYMBOL_REF)
1946 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1952 /* Return the best assembler insn template
1953 for moving operands[1] into operands[0] as a fullword. */
1955 singlemove_string (rtx *operands)
1957 HOST_WIDE_INT intval;
1959 if (GET_CODE (operands[0]) == MEM)
1960 return "stw %r1,%0";
1961 if (GET_CODE (operands[1]) == MEM)
1963 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1968 gcc_assert (GET_MODE (operands[1]) == SFmode);
1970 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1972 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1973 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1975 operands[1] = GEN_INT (i);
1976 /* Fall through to CONST_INT case. */
1978 if (GET_CODE (operands[1]) == CONST_INT)
1980 intval = INTVAL (operands[1]);
1982 if (VAL_14_BITS_P (intval))
1984 else if ((intval & 0x7ff) == 0)
1985 return "ldil L'%1,%0";
1986 else if (zdepi_cint_p (intval))
1987 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1989 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1991 return "copy %1,%0";
1995 /* Compute position (in OP[1]) and width (in OP[2])
1996 useful for copying IMM to a register using the zdepi
1997 instructions. Store the immediate value to insert in OP[0]. */
1999 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2003 /* Find the least significant set bit in IMM. */
2004 for (lsb = 0; lsb < 32; lsb++)
2011 /* Choose variants based on *sign* of the 5-bit field. */
2012 if ((imm & 0x10) == 0)
2013 len = (lsb <= 28) ? 4 : 32 - lsb;
2016 /* Find the width of the bitstring in IMM. */
2017 for (len = 5; len < 32; len++)
2019 if ((imm & (1 << len)) == 0)
2023 /* Sign extend IMM as a 5-bit value. */
2024 imm = (imm & 0xf) - 0x10;
2032 /* Compute position (in OP[1]) and width (in OP[2])
2033 useful for copying IMM to a register using the depdi,z
2034 instructions. Store the immediate value to insert in OP[0]. */
2036 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2038 HOST_WIDE_INT lsb, len;
2040 /* Find the least significant set bit in IMM. */
2041 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2048 /* Choose variants based on *sign* of the 5-bit field. */
2049 if ((imm & 0x10) == 0)
2050 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2051 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2054 /* Find the width of the bitstring in IMM. */
2055 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2057 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2061 /* Sign extend IMM as a 5-bit value. */
2062 imm = (imm & 0xf) - 0x10;
2070 /* Output assembler code to perform a doubleword move insn
2071 with operands OPERANDS. */
2074 output_move_double (rtx *operands)
2076 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2078 rtx addreg0 = 0, addreg1 = 0;
2080 /* First classify both operands. */
2082 if (REG_P (operands[0]))
2084 else if (offsettable_memref_p (operands[0]))
2086 else if (GET_CODE (operands[0]) == MEM)
2091 if (REG_P (operands[1]))
2093 else if (CONSTANT_P (operands[1]))
2095 else if (offsettable_memref_p (operands[1]))
2097 else if (GET_CODE (operands[1]) == MEM)
2102 /* Check for the cases that the operand constraints are not
2103 supposed to allow to happen. */
2104 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2106 /* Handle auto decrementing and incrementing loads and stores
2107 specifically, since the structure of the function doesn't work
2108 for them without major modification. Do it better when we learn
2109 this port about the general inc/dec addressing of PA.
2110 (This was written by tege. Chide him if it doesn't work.) */
2112 if (optype0 == MEMOP)
2114 /* We have to output the address syntax ourselves, since print_operand
2115 doesn't deal with the addresses we want to use. Fix this later. */
2117 rtx addr = XEXP (operands[0], 0);
2118 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2120 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2122 operands[0] = XEXP (addr, 0);
2123 gcc_assert (GET_CODE (operands[1]) == REG
2124 && GET_CODE (operands[0]) == REG);
2126 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2128 /* No overlap between high target register and address
2129 register. (We do this in a non-obvious way to
2130 save a register file writeback) */
2131 if (GET_CODE (addr) == POST_INC)
2132 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2133 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2135 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2137 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2139 operands[0] = XEXP (addr, 0);
2140 gcc_assert (GET_CODE (operands[1]) == REG
2141 && GET_CODE (operands[0]) == REG);
2143 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2144 /* No overlap between high target register and address
2145 register. (We do this in a non-obvious way to save a
2146 register file writeback) */
2147 if (GET_CODE (addr) == PRE_INC)
2148 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2149 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2152 if (optype1 == MEMOP)
2154 /* We have to output the address syntax ourselves, since print_operand
2155 doesn't deal with the addresses we want to use. Fix this later. */
2157 rtx addr = XEXP (operands[1], 0);
2158 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2160 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2162 operands[1] = XEXP (addr, 0);
2163 gcc_assert (GET_CODE (operands[0]) == REG
2164 && GET_CODE (operands[1]) == REG);
2166 if (!reg_overlap_mentioned_p (high_reg, addr))
2168 /* No overlap between high target register and address
2169 register. (We do this in a non-obvious way to
2170 save a register file writeback) */
2171 if (GET_CODE (addr) == POST_INC)
2172 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2173 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2177 /* This is an undefined situation. We should load into the
2178 address register *and* update that register. Probably
2179 we don't need to handle this at all. */
2180 if (GET_CODE (addr) == POST_INC)
2181 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2182 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2185 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2187 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2189 operands[1] = XEXP (addr, 0);
2190 gcc_assert (GET_CODE (operands[0]) == REG
2191 && GET_CODE (operands[1]) == REG);
2193 if (!reg_overlap_mentioned_p (high_reg, addr))
2195 /* No overlap between high target register and address
2196 register. (We do this in a non-obvious way to
2197 save a register file writeback) */
2198 if (GET_CODE (addr) == PRE_INC)
2199 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2200 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2204 /* This is an undefined situation. We should load into the
2205 address register *and* update that register. Probably
2206 we don't need to handle this at all. */
2207 if (GET_CODE (addr) == PRE_INC)
2208 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2209 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2212 else if (GET_CODE (addr) == PLUS
2213 && GET_CODE (XEXP (addr, 0)) == MULT)
2215 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2217 if (!reg_overlap_mentioned_p (high_reg, addr))
2221 xoperands[0] = high_reg;
2222 xoperands[1] = XEXP (addr, 1);
2223 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2224 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2225 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2227 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2233 xoperands[0] = high_reg;
2234 xoperands[1] = XEXP (addr, 1);
2235 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2236 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2237 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2239 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2244 /* If an operand is an unoffsettable memory ref, find a register
2245 we can increment temporarily to make it refer to the second word. */
2247 if (optype0 == MEMOP)
2248 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2250 if (optype1 == MEMOP)
2251 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2253 /* Ok, we can do one word at a time.
2254 Normally we do the low-numbered word first.
2256 In either case, set up in LATEHALF the operands to use
2257 for the high-numbered word and in some cases alter the
2258 operands in OPERANDS to be suitable for the low-numbered word. */
2260 if (optype0 == REGOP)
2261 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2262 else if (optype0 == OFFSOP)
2263 latehalf[0] = adjust_address (operands[0], SImode, 4);
2265 latehalf[0] = operands[0];
2267 if (optype1 == REGOP)
2268 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2269 else if (optype1 == OFFSOP)
2270 latehalf[1] = adjust_address (operands[1], SImode, 4);
2271 else if (optype1 == CNSTOP)
2272 split_double (operands[1], &operands[1], &latehalf[1]);
2274 latehalf[1] = operands[1];
2276 /* If the first move would clobber the source of the second one,
2277 do them in the other order.
2279 This can happen in two cases:
2281 mem -> register where the first half of the destination register
2282 is the same register used in the memory's address. Reload
2283 can create such insns.
2285 mem in this case will be either register indirect or register
2286 indirect plus a valid offset.
2288 register -> register move where REGNO(dst) == REGNO(src + 1)
2289 someone (Tim/Tege?) claimed this can happen for parameter loads.
2291 Handle mem -> register case first. */
2292 if (optype0 == REGOP
2293 && (optype1 == MEMOP || optype1 == OFFSOP)
2294 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2297 /* Do the late half first. */
2299 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2300 output_asm_insn (singlemove_string (latehalf), latehalf);
2304 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2305 return singlemove_string (operands);
2308 /* Now handle register -> register case. */
2309 if (optype0 == REGOP && optype1 == REGOP
2310 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2312 output_asm_insn (singlemove_string (latehalf), latehalf);
2313 return singlemove_string (operands);
2316 /* Normal case: do the two words, low-numbered first. */
2318 output_asm_insn (singlemove_string (operands), operands);
2320 /* Make any unoffsettable addresses point at high-numbered word. */
2322 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2324 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2327 output_asm_insn (singlemove_string (latehalf), latehalf);
2329 /* Undo the adds we just did. */
2331 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2333 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2339 output_fp_move_double (rtx *operands)
2341 if (FP_REG_P (operands[0]))
2343 if (FP_REG_P (operands[1])
2344 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2345 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2347 output_asm_insn ("fldd%F1 %1,%0", operands);
2349 else if (FP_REG_P (operands[1]))
2351 output_asm_insn ("fstd%F0 %1,%0", operands);
2357 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2359 /* This is a pain. You have to be prepared to deal with an
2360 arbitrary address here including pre/post increment/decrement.
2362 so avoid this in the MD. */
2363 gcc_assert (GET_CODE (operands[0]) == REG);
2365 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2366 xoperands[0] = operands[0];
2367 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2372 /* Return a REG that occurs in ADDR with coefficient 1.
2373 ADDR can be effectively incremented by incrementing REG. */
2376 find_addr_reg (rtx addr)
2378 while (GET_CODE (addr) == PLUS)
2380 if (GET_CODE (XEXP (addr, 0)) == REG)
2381 addr = XEXP (addr, 0);
2382 else if (GET_CODE (XEXP (addr, 1)) == REG)
2383 addr = XEXP (addr, 1);
2384 else if (CONSTANT_P (XEXP (addr, 0)))
2385 addr = XEXP (addr, 1);
2386 else if (CONSTANT_P (XEXP (addr, 1)))
2387 addr = XEXP (addr, 0);
2391 gcc_assert (GET_CODE (addr) == REG);
2395 /* Emit code to perform a block move.
2397 OPERANDS[0] is the destination pointer as a REG, clobbered.
2398 OPERANDS[1] is the source pointer as a REG, clobbered.
2399 OPERANDS[2] is a register for temporary storage.
2400 OPERANDS[3] is a register for temporary storage.
2401 OPERANDS[4] is the size as a CONST_INT
2402 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2403 OPERANDS[6] is another temporary register. */
2406 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2408 int align = INTVAL (operands[5]);
2409 unsigned long n_bytes = INTVAL (operands[4]);
2411 /* We can't move more than a word at a time because the PA
2412 has no longer integer move insns. (Could use fp mem ops?) */
2413 if (align > (TARGET_64BIT ? 8 : 4))
2414 align = (TARGET_64BIT ? 8 : 4);
2416 /* Note that we know each loop below will execute at least twice
2417 (else we would have open-coded the copy). */
2421 /* Pre-adjust the loop counter. */
2422 operands[4] = GEN_INT (n_bytes - 16);
2423 output_asm_insn ("ldi %4,%2", operands);
2426 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2427 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2428 output_asm_insn ("std,ma %3,8(%0)", operands);
2429 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2430 output_asm_insn ("std,ma %6,8(%0)", operands);
2432 /* Handle the residual. There could be up to 7 bytes of
2433 residual to copy! */
2434 if (n_bytes % 16 != 0)
2436 operands[4] = GEN_INT (n_bytes % 8);
2437 if (n_bytes % 16 >= 8)
2438 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2439 if (n_bytes % 8 != 0)
2440 output_asm_insn ("ldd 0(%1),%6", operands);
2441 if (n_bytes % 16 >= 8)
2442 output_asm_insn ("std,ma %3,8(%0)", operands);
2443 if (n_bytes % 8 != 0)
2444 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2449 /* Pre-adjust the loop counter. */
2450 operands[4] = GEN_INT (n_bytes - 8);
2451 output_asm_insn ("ldi %4,%2", operands);
2454 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2455 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2456 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2457 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2458 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2460 /* Handle the residual. There could be up to 7 bytes of
2461 residual to copy! */
2462 if (n_bytes % 8 != 0)
2464 operands[4] = GEN_INT (n_bytes % 4);
2465 if (n_bytes % 8 >= 4)
2466 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2467 if (n_bytes % 4 != 0)
2468 output_asm_insn ("ldw 0(%1),%6", operands);
2469 if (n_bytes % 8 >= 4)
2470 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2471 if (n_bytes % 4 != 0)
2472 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2477 /* Pre-adjust the loop counter. */
2478 operands[4] = GEN_INT (n_bytes - 4);
2479 output_asm_insn ("ldi %4,%2", operands);
2482 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2483 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2484 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2485 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2486 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2488 /* Handle the residual. */
2489 if (n_bytes % 4 != 0)
2491 if (n_bytes % 4 >= 2)
2492 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2493 if (n_bytes % 2 != 0)
2494 output_asm_insn ("ldb 0(%1),%6", operands);
2495 if (n_bytes % 4 >= 2)
2496 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2497 if (n_bytes % 2 != 0)
2498 output_asm_insn ("stb %6,0(%0)", operands);
2503 /* Pre-adjust the loop counter. */
2504 operands[4] = GEN_INT (n_bytes - 2);
2505 output_asm_insn ("ldi %4,%2", operands);
2508 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2509 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2510 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2511 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2512 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2514 /* Handle the residual. */
2515 if (n_bytes % 2 != 0)
2517 output_asm_insn ("ldb 0(%1),%3", operands);
2518 output_asm_insn ("stb %3,0(%0)", operands);
2527 /* Count the number of insns necessary to handle this block move.
2529 Basic structure is the same as emit_block_move, except that we
2530 count insns rather than emit them. */
2533 compute_movmem_length (rtx insn)
2535 rtx pat = PATTERN (insn);
2536 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2537 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2538 unsigned int n_insns = 0;
2540 /* We can't move more than four bytes at a time because the PA
2541 has no longer integer move insns. (Could use fp mem ops?) */
2542 if (align > (TARGET_64BIT ? 8 : 4))
2543 align = (TARGET_64BIT ? 8 : 4);
2545 /* The basic copying loop. */
2549 if (n_bytes % (2 * align) != 0)
2551 if ((n_bytes % (2 * align)) >= align)
2554 if ((n_bytes % align) != 0)
2558 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2562 /* Emit code to perform a block clear.
2564 OPERANDS[0] is the destination pointer as a REG, clobbered.
2565 OPERANDS[1] is a register for temporary storage.
2566 OPERANDS[2] is the size as a CONST_INT
2567 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2570 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2572 int align = INTVAL (operands[3]);
2573 unsigned long n_bytes = INTVAL (operands[2]);
2575 /* We can't clear more than a word at a time because the PA
2576 has no longer integer move insns. */
2577 if (align > (TARGET_64BIT ? 8 : 4))
2578 align = (TARGET_64BIT ? 8 : 4);
2580 /* Note that we know each loop below will execute at least twice
2581 (else we would have open-coded the copy). */
2585 /* Pre-adjust the loop counter. */
2586 operands[2] = GEN_INT (n_bytes - 16);
2587 output_asm_insn ("ldi %2,%1", operands);
2590 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2591 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2592 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2594 /* Handle the residual. There could be up to 7 bytes of
2595 residual to copy! */
2596 if (n_bytes % 16 != 0)
2598 operands[2] = GEN_INT (n_bytes % 8);
2599 if (n_bytes % 16 >= 8)
2600 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2601 if (n_bytes % 8 != 0)
2602 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2607 /* Pre-adjust the loop counter. */
2608 operands[2] = GEN_INT (n_bytes - 8);
2609 output_asm_insn ("ldi %2,%1", operands);
2612 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2613 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2614 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2616 /* Handle the residual. There could be up to 7 bytes of
2617 residual to copy! */
2618 if (n_bytes % 8 != 0)
2620 operands[2] = GEN_INT (n_bytes % 4);
2621 if (n_bytes % 8 >= 4)
2622 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2623 if (n_bytes % 4 != 0)
2624 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2629 /* Pre-adjust the loop counter. */
2630 operands[2] = GEN_INT (n_bytes - 4);
2631 output_asm_insn ("ldi %2,%1", operands);
2634 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2635 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2636 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2638 /* Handle the residual. */
2639 if (n_bytes % 4 != 0)
2641 if (n_bytes % 4 >= 2)
2642 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2643 if (n_bytes % 2 != 0)
2644 output_asm_insn ("stb %%r0,0(%0)", operands);
2649 /* Pre-adjust the loop counter. */
2650 operands[2] = GEN_INT (n_bytes - 2);
2651 output_asm_insn ("ldi %2,%1", operands);
2654 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2655 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2656 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2658 /* Handle the residual. */
2659 if (n_bytes % 2 != 0)
2660 output_asm_insn ("stb %%r0,0(%0)", operands);
2669 /* Count the number of insns necessary to handle this block move.
2671 Basic structure is the same as emit_block_move, except that we
2672 count insns rather than emit them. */
2675 compute_clrmem_length (rtx insn)
2677 rtx pat = PATTERN (insn);
2678 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2679 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2680 unsigned int n_insns = 0;
2682 /* We can't clear more than a word at a time because the PA
2683 has no longer integer move insns. */
2684 if (align > (TARGET_64BIT ? 8 : 4))
2685 align = (TARGET_64BIT ? 8 : 4);
2687 /* The basic loop. */
2691 if (n_bytes % (2 * align) != 0)
2693 if ((n_bytes % (2 * align)) >= align)
2696 if ((n_bytes % align) != 0)
2700 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2706 output_and (rtx *operands)
2708 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2710 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2711 int ls0, ls1, ms0, p, len;
2713 for (ls0 = 0; ls0 < 32; ls0++)
2714 if ((mask & (1 << ls0)) == 0)
2717 for (ls1 = ls0; ls1 < 32; ls1++)
2718 if ((mask & (1 << ls1)) != 0)
2721 for (ms0 = ls1; ms0 < 32; ms0++)
2722 if ((mask & (1 << ms0)) == 0)
2725 gcc_assert (ms0 == 32);
2733 operands[2] = GEN_INT (len);
2734 return "{extru|extrw,u} %1,31,%2,%0";
2738 /* We could use this `depi' for the case above as well, but `depi'
2739 requires one more register file access than an `extru'. */
2744 operands[2] = GEN_INT (p);
2745 operands[3] = GEN_INT (len);
2746 return "{depi|depwi} 0,%2,%3,%0";
2750 return "and %1,%2,%0";
2753 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2754 storing the result in operands[0]. */
2756 output_64bit_and (rtx *operands)
2758 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2760 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2761 int ls0, ls1, ms0, p, len;
2763 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2764 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2767 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2768 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2771 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2772 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2775 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2777 if (ls1 == HOST_BITS_PER_WIDE_INT)
2783 operands[2] = GEN_INT (len);
2784 return "extrd,u %1,63,%2,%0";
2788 /* We could use this `depi' for the case above as well, but `depi'
2789 requires one more register file access than an `extru'. */
2794 operands[2] = GEN_INT (p);
2795 operands[3] = GEN_INT (len);
2796 return "depdi 0,%2,%3,%0";
2800 return "and %1,%2,%0";
2804 output_ior (rtx *operands)
2806 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2807 int bs0, bs1, p, len;
2809 if (INTVAL (operands[2]) == 0)
2810 return "copy %1,%0";
2812 for (bs0 = 0; bs0 < 32; bs0++)
2813 if ((mask & (1 << bs0)) != 0)
2816 for (bs1 = bs0; bs1 < 32; bs1++)
2817 if ((mask & (1 << bs1)) == 0)
2820 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2825 operands[2] = GEN_INT (p);
2826 operands[3] = GEN_INT (len);
2827 return "{depi|depwi} -1,%2,%3,%0";
2830 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2831 storing the result in operands[0]. */
2833 output_64bit_ior (rtx *operands)
2835 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2836 int bs0, bs1, p, len;
2838 if (INTVAL (operands[2]) == 0)
2839 return "copy %1,%0";
2841 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2842 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2845 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2846 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2849 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
2850 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2855 operands[2] = GEN_INT (p);
2856 operands[3] = GEN_INT (len);
2857 return "depdi -1,%2,%3,%0";
2860 /* Target hook for assembling integer objects. This code handles
2861 aligned SI and DI integers specially since function references
2862 must be preceded by P%. */
2865 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
2867 if (size == UNITS_PER_WORD
2869 && function_label_operand (x, VOIDmode))
2871 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2872 output_addr_const (asm_out_file, x);
2873 fputc ('\n', asm_out_file);
2876 return default_assemble_integer (x, size, aligned_p);
2879 /* Output an ascii string. */
2881 output_ascii (FILE *file, const char *p, int size)
2885 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2887 /* The HP assembler can only take strings of 256 characters at one
2888 time. This is a limitation on input line length, *not* the
2889 length of the string. Sigh. Even worse, it seems that the
2890 restriction is in number of input characters (see \xnn &
2891 \whatever). So we have to do this very carefully. */
2893 fputs ("\t.STRING \"", file);
2896 for (i = 0; i < size; i += 4)
2900 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2902 register unsigned int c = (unsigned char) p[i + io];
2904 if (c == '\"' || c == '\\')
2905 partial_output[co++] = '\\';
2906 if (c >= ' ' && c < 0177)
2907 partial_output[co++] = c;
2911 partial_output[co++] = '\\';
2912 partial_output[co++] = 'x';
2913 hexd = c / 16 - 0 + '0';
2915 hexd -= '9' - 'a' + 1;
2916 partial_output[co++] = hexd;
2917 hexd = c % 16 - 0 + '0';
2919 hexd -= '9' - 'a' + 1;
2920 partial_output[co++] = hexd;
2923 if (chars_output + co > 243)
2925 fputs ("\"\n\t.STRING \"", file);
2928 fwrite (partial_output, 1, (size_t) co, file);
2932 fputs ("\"\n", file);
2935 /* Try to rewrite floating point comparisons & branches to avoid
2936 useless add,tr insns.
2938 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2939 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2940 first attempt to remove useless add,tr insns. It is zero
2941 for the second pass as reorg sometimes leaves bogus REG_DEAD
2944 When CHECK_NOTES is zero we can only eliminate add,tr insns
2945 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2948 remove_useless_addtr_insns (int check_notes)
2951 static int pass = 0;
2953 /* This is fairly cheap, so always run it when optimizing. */
2957 int fbranch_count = 0;
2959 /* Walk all the insns in this function looking for fcmp & fbranch
2960 instructions. Keep track of how many of each we find. */
2961 for (insn = get_insns (); insn; insn = next_insn (insn))
2965 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2966 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2969 tmp = PATTERN (insn);
2971 /* It must be a set. */
2972 if (GET_CODE (tmp) != SET)
2975 /* If the destination is CCFP, then we've found an fcmp insn. */
2976 tmp = SET_DEST (tmp);
2977 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2983 tmp = PATTERN (insn);
2984 /* If this is an fbranch instruction, bump the fbranch counter. */
2985 if (GET_CODE (tmp) == SET
2986 && SET_DEST (tmp) == pc_rtx
2987 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2988 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2989 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2990 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2998 /* Find all floating point compare + branch insns. If possible,
2999 reverse the comparison & the branch to avoid add,tr insns. */
3000 for (insn = get_insns (); insn; insn = next_insn (insn))
3004 /* Ignore anything that isn't an INSN. */
3005 if (GET_CODE (insn) != INSN)
3008 tmp = PATTERN (insn);
3010 /* It must be a set. */
3011 if (GET_CODE (tmp) != SET)
3014 /* The destination must be CCFP, which is register zero. */
3015 tmp = SET_DEST (tmp);
3016 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3019 /* INSN should be a set of CCFP.
3021 See if the result of this insn is used in a reversed FP
3022 conditional branch. If so, reverse our condition and
3023 the branch. Doing so avoids useless add,tr insns. */
3024 next = next_insn (insn);
3027 /* Jumps, calls and labels stop our search. */
3028 if (GET_CODE (next) == JUMP_INSN
3029 || GET_CODE (next) == CALL_INSN
3030 || GET_CODE (next) == CODE_LABEL)
3033 /* As does another fcmp insn. */
3034 if (GET_CODE (next) == INSN
3035 && GET_CODE (PATTERN (next)) == SET
3036 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3037 && REGNO (SET_DEST (PATTERN (next))) == 0)
3040 next = next_insn (next);
3043 /* Is NEXT_INSN a branch? */
3045 && GET_CODE (next) == JUMP_INSN)
3047 rtx pattern = PATTERN (next);
3049 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3050 and CCFP dies, then reverse our conditional and the branch
3051 to avoid the add,tr. */
3052 if (GET_CODE (pattern) == SET
3053 && SET_DEST (pattern) == pc_rtx
3054 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3055 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3056 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3057 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3058 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3059 && (fcmp_count == fbranch_count
3061 && find_regno_note (next, REG_DEAD, 0))))
3063 /* Reverse the branch. */
3064 tmp = XEXP (SET_SRC (pattern), 1);
3065 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3066 XEXP (SET_SRC (pattern), 2) = tmp;
3067 INSN_CODE (next) = -1;
3069 /* Reverse our condition. */
3070 tmp = PATTERN (insn);
3071 PUT_CODE (XEXP (tmp, 1),
3072 (reverse_condition_maybe_unordered
3073 (GET_CODE (XEXP (tmp, 1)))));
3083 /* You may have trouble believing this, but this is the 32 bit HP-PA
3088 Variable arguments (optional; any number may be allocated)
3090 SP-(4*(N+9)) arg word N
3095 Fixed arguments (must be allocated; may remain unused)
3104 SP-32 External Data Pointer (DP)
3106 SP-24 External/stub RP (RP')
3110 SP-8 Calling Stub RP (RP'')
3115 SP-0 Stack Pointer (points to next available address)
3119 /* This function saves registers as follows. Registers marked with ' are
3120 this function's registers (as opposed to the previous function's).
3121 If a frame_pointer isn't needed, r4 is saved as a general register;
3122 the space for the frame pointer is still allocated, though, to keep
3128 SP (FP') Previous FP
3129 SP + 4 Alignment filler (sigh)
3130 SP + 8 Space for locals reserved here.
3134 SP + n All call saved register used.
3138 SP + o All call saved fp registers used.
3142 SP + p (SP') points to next available address.
3146 /* Global variables set by output_function_prologue(). */
3147 /* Size of frame. Need to know this to emit return insns from
3149 static HOST_WIDE_INT actual_fsize, local_fsize;
3150 static int save_fregs;
3152 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3153 Handle case where DISP > 8k by using the add_high_const patterns.
3155 Note in DISP > 8k case, we will leave the high part of the address
3156 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3159 store_reg (int reg, HOST_WIDE_INT disp, int base)
3161 rtx insn, dest, src, basereg;
3163 src = gen_rtx_REG (word_mode, reg);
3164 basereg = gen_rtx_REG (Pmode, base);
3165 if (VAL_14_BITS_P (disp))
3167 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3168 insn = emit_move_insn (dest, src);
3170 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3172 rtx delta = GEN_INT (disp);
3173 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3175 emit_move_insn (tmpreg, delta);
3176 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3177 dest = gen_rtx_MEM (word_mode, tmpreg);
3178 insn = emit_move_insn (dest, src);
3182 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3183 gen_rtx_SET (VOIDmode,
3184 gen_rtx_MEM (word_mode,
3185 gen_rtx_PLUS (word_mode, basereg,
3193 rtx delta = GEN_INT (disp);
3194 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3195 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3197 emit_move_insn (tmpreg, high);
3198 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3199 insn = emit_move_insn (dest, src);
3203 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3204 gen_rtx_SET (VOIDmode,
3205 gen_rtx_MEM (word_mode,
3206 gen_rtx_PLUS (word_mode, basereg,
3214 RTX_FRAME_RELATED_P (insn) = 1;
3217 /* Emit RTL to store REG at the memory location specified by BASE and then
3218 add MOD to BASE. MOD must be <= 8k. */
3221 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3223 rtx insn, basereg, srcreg, delta;
3225 gcc_assert (VAL_14_BITS_P (mod));
3227 basereg = gen_rtx_REG (Pmode, base);
3228 srcreg = gen_rtx_REG (word_mode, reg);
3229 delta = GEN_INT (mod);
3231 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3234 RTX_FRAME_RELATED_P (insn) = 1;
3236 /* RTX_FRAME_RELATED_P must be set on each frame related set
3237 in a parallel with more than one element. Don't set
3238 RTX_FRAME_RELATED_P in the first set if reg is temporary
3239 register 1. The effect of this operation is recorded in
3240 the initial copy. */
3243 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3244 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3248 /* The first element of a PARALLEL is always processed if it is
3249 a SET. Thus, we need an expression list for this case. */
3251 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3252 gen_rtx_SET (VOIDmode, basereg,
3253 gen_rtx_PLUS (word_mode, basereg, delta)),
3259 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3260 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3261 whether to add a frame note or not.
3263 In the DISP > 8k case, we leave the high part of the address in %r1.
3264 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3267 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3271 if (VAL_14_BITS_P (disp))
3273 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3274 plus_constant (gen_rtx_REG (Pmode, base), disp));
3276 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3278 rtx basereg = gen_rtx_REG (Pmode, base);
3279 rtx delta = GEN_INT (disp);
3280 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3282 emit_move_insn (tmpreg, delta);
3283 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3284 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3288 rtx basereg = gen_rtx_REG (Pmode, base);
3289 rtx delta = GEN_INT (disp);
3290 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3292 emit_move_insn (tmpreg,
3293 gen_rtx_PLUS (Pmode, basereg,
3294 gen_rtx_HIGH (Pmode, delta)));
3295 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3296 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3299 if (DO_FRAME_NOTES && note)
3300 RTX_FRAME_RELATED_P (insn) = 1;
3304 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3309 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3310 be consistent with the rounding and size calculation done here.
3311 Change them at the same time. */
3313 /* We do our own stack alignment. First, round the size of the
3314 stack locals up to a word boundary. */
3315 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3317 /* Space for previous frame pointer + filler. If any frame is
3318 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3319 waste some space here for the sake of HP compatibility. The
3320 first slot is only used when the frame pointer is needed. */
3321 if (size || frame_pointer_needed)
3322 size += STARTING_FRAME_OFFSET;
3324 /* If the current function calls __builtin_eh_return, then we need
3325 to allocate stack space for registers that will hold data for
3326 the exception handler. */
3327 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3331 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3333 size += i * UNITS_PER_WORD;
3336 /* Account for space used by the callee general register saves. */
3337 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3338 if (regs_ever_live[i])
3339 size += UNITS_PER_WORD;
3341 /* Account for space used by the callee floating point register saves. */
3342 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3343 if (regs_ever_live[i]
3344 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3348 /* We always save both halves of the FP register, so always
3349 increment the frame size by 8 bytes. */
3353 /* If any of the floating registers are saved, account for the
3354 alignment needed for the floating point register save block. */
3357 size = (size + 7) & ~7;
3362 /* The various ABIs include space for the outgoing parameters in the
3363 size of the current function's stack frame. We don't need to align
3364 for the outgoing arguments as their alignment is set by the final
3365 rounding for the frame as a whole. */
3366 size += current_function_outgoing_args_size;
3368 /* Allocate space for the fixed frame marker. This space must be
3369 allocated for any function that makes calls or allocates
3371 if (!current_function_is_leaf || size)
3372 size += TARGET_64BIT ? 48 : 32;
3374 /* Finally, round to the preferred stack boundary. */
3375 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3376 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3379 /* Generate the assembly code for function entry. FILE is a stdio
3380 stream to output the code to. SIZE is an int: how many units of
3381 temporary storage to allocate.
3383 Refer to the array `regs_ever_live' to determine which registers to
3384 save; `regs_ever_live[I]' is nonzero if register number I is ever
3385 used in the function. This function is responsible for knowing
3386 which registers should not be saved even if used. */
3388 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3389 of memory. If any fpu reg is used in the function, we allocate
3390 such a block here, at the bottom of the frame, just in case it's needed.
3392 If this function is a leaf procedure, then we may choose not
3393 to do a "save" insn. The decision about whether or not
3394 to do this is made in regclass.c. */
3397 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3399 /* The function's label and associated .PROC must never be
3400 separated and must be output *after* any profiling declarations
3401 to avoid changing spaces/subspaces within a procedure. */
3402 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3403 fputs ("\t.PROC\n", file);
3405 /* hppa_expand_prologue does the dirty work now. We just need
3406 to output the assembler directives which denote the start
3408 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3409 if (regs_ever_live[2])
3410 fputs (",CALLS,SAVE_RP", file);
3412 fputs (",NO_CALLS", file);
3414 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3415 at the beginning of the frame and that it is used as the frame
3416 pointer for the frame. We do this because our current frame
3417 layout doesn't conform to that specified in the the HP runtime
3418 documentation and we need a way to indicate to programs such as
3419 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3420 isn't used by HP compilers but is supported by the assembler.
3421 However, SAVE_SP is supposed to indicate that the previous stack
3422 pointer has been saved in the frame marker. */
3423 if (frame_pointer_needed)
3424 fputs (",SAVE_SP", file);
3426 /* Pass on information about the number of callee register saves
3427 performed in the prologue.
3429 The compiler is supposed to pass the highest register number
3430 saved, the assembler then has to adjust that number before
3431 entering it into the unwind descriptor (to account for any
3432 caller saved registers with lower register numbers than the
3433 first callee saved register). */
3435 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3438 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3440 fputs ("\n\t.ENTRY\n", file);
3442 remove_useless_addtr_insns (0);
3446 hppa_expand_prologue (void)
3448 int merge_sp_adjust_with_store = 0;
3449 HOST_WIDE_INT size = get_frame_size ();
3450 HOST_WIDE_INT offset;
3458 /* Compute total size for frame pointer, filler, locals and rounding to
3459 the next word boundary. Similar code appears in compute_frame_size
3460 and must be changed in tandem with this code. */
3461 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3462 if (local_fsize || frame_pointer_needed)
3463 local_fsize += STARTING_FRAME_OFFSET;
3465 actual_fsize = compute_frame_size (size, &save_fregs);
3467 /* Compute a few things we will use often. */
3468 tmpreg = gen_rtx_REG (word_mode, 1);
3470 /* Save RP first. The calling conventions manual states RP will
3471 always be stored into the caller's frame at sp - 20 or sp - 16
3472 depending on which ABI is in use. */
3473 if (regs_ever_live[2] || current_function_calls_eh_return)
3474 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3476 /* Allocate the local frame and set up the frame pointer if needed. */
3477 if (actual_fsize != 0)
3479 if (frame_pointer_needed)
3481 /* Copy the old frame pointer temporarily into %r1. Set up the
3482 new stack pointer, then store away the saved old frame pointer
3483 into the stack at sp and at the same time update the stack
3484 pointer by actual_fsize bytes. Two versions, first
3485 handles small (<8k) frames. The second handles large (>=8k)
3487 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3490 /* We need to record the frame pointer save here since the
3491 new frame pointer is set in the following insn. */
3492 RTX_FRAME_RELATED_P (insn) = 1;
3494 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3495 gen_rtx_SET (VOIDmode,
3496 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3501 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3503 RTX_FRAME_RELATED_P (insn) = 1;
3505 if (VAL_14_BITS_P (actual_fsize))
3506 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3509 /* It is incorrect to store the saved frame pointer at *sp,
3510 then increment sp (writes beyond the current stack boundary).
3512 So instead use stwm to store at *sp and post-increment the
3513 stack pointer as an atomic operation. Then increment sp to
3514 finish allocating the new frame. */
3515 HOST_WIDE_INT adjust1 = 8192 - 64;
3516 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3518 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3519 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3523 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3524 we need to store the previous stack pointer (frame pointer)
3525 into the frame marker on targets that use the HP unwind
3526 library. This allows the HP unwind library to be used to
3527 unwind GCC frames. However, we are not fully compatible
3528 with the HP library because our frame layout differs from
3529 that specified in the HP runtime specification.
3531 We don't want a frame note on this instruction as the frame
3532 marker moves during dynamic stack allocation.
3534 This instruction also serves as a blockage to prevent
3535 register spills from being scheduled before the stack
3536 pointer is raised. This is necessary as we store
3537 registers using the frame pointer as a base register,
3538 and the frame pointer is set before sp is raised. */
3539 if (TARGET_HPUX_UNWIND_LIBRARY)
3541 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3542 GEN_INT (TARGET_64BIT ? -8 : -4));
3544 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3548 emit_insn (gen_blockage ());
3550 /* no frame pointer needed. */
3553 /* In some cases we can perform the first callee register save
3554 and allocating the stack frame at the same time. If so, just
3555 make a note of it and defer allocating the frame until saving
3556 the callee registers. */
3557 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3558 merge_sp_adjust_with_store = 1;
3559 /* Can not optimize. Adjust the stack frame by actual_fsize
3562 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3567 /* Normal register save.
3569 Do not save the frame pointer in the frame_pointer_needed case. It
3570 was done earlier. */
3571 if (frame_pointer_needed)
3573 offset = local_fsize;
3575 /* Saving the EH return data registers in the frame is the simplest
3576 way to get the frame unwind information emitted. We put them
3577 just before the general registers. */
3578 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3580 unsigned int i, regno;
3584 regno = EH_RETURN_DATA_REGNO (i);
3585 if (regno == INVALID_REGNUM)
3588 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3589 offset += UNITS_PER_WORD;
3593 for (i = 18; i >= 4; i--)
3594 if (regs_ever_live[i] && ! call_used_regs[i])
3596 store_reg (i, offset, FRAME_POINTER_REGNUM);
3597 offset += UNITS_PER_WORD;
3600 /* Account for %r3 which is saved in a special place. */
3603 /* No frame pointer needed. */
3606 offset = local_fsize - actual_fsize;
3608 /* Saving the EH return data registers in the frame is the simplest
3609 way to get the frame unwind information emitted. */
3610 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3612 unsigned int i, regno;
3616 regno = EH_RETURN_DATA_REGNO (i);
3617 if (regno == INVALID_REGNUM)
3620 /* If merge_sp_adjust_with_store is nonzero, then we can
3621 optimize the first save. */
3622 if (merge_sp_adjust_with_store)
3624 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3625 merge_sp_adjust_with_store = 0;
3628 store_reg (regno, offset, STACK_POINTER_REGNUM);
3629 offset += UNITS_PER_WORD;
3633 for (i = 18; i >= 3; i--)
3634 if (regs_ever_live[i] && ! call_used_regs[i])
3636 /* If merge_sp_adjust_with_store is nonzero, then we can
3637 optimize the first GR save. */
3638 if (merge_sp_adjust_with_store)
3640 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3641 merge_sp_adjust_with_store = 0;
3644 store_reg (i, offset, STACK_POINTER_REGNUM);
3645 offset += UNITS_PER_WORD;
3649 /* If we wanted to merge the SP adjustment with a GR save, but we never
3650 did any GR saves, then just emit the adjustment here. */
3651 if (merge_sp_adjust_with_store)
3652 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3656 /* The hppa calling conventions say that %r19, the pic offset
3657 register, is saved at sp - 32 (in this function's frame)
3658 when generating PIC code. FIXME: What is the correct thing
3659 to do for functions which make no calls and allocate no
3660 frame? Do we need to allocate a frame, or can we just omit
3661 the save? For now we'll just omit the save.
3663 We don't want a note on this insn as the frame marker can
3664 move if there is a dynamic stack allocation. */
3665 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3667 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3669 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3673 /* Align pointer properly (doubleword boundary). */
3674 offset = (offset + 7) & ~7;
3676 /* Floating point register store. */
3681 /* First get the frame or stack pointer to the start of the FP register
3683 if (frame_pointer_needed)
3685 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3686 base = frame_pointer_rtx;
3690 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3691 base = stack_pointer_rtx;
3694 /* Now actually save the FP registers. */
3695 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3697 if (regs_ever_live[i]
3698 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3700 rtx addr, insn, reg;
3701 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3702 reg = gen_rtx_REG (DFmode, i);
3703 insn = emit_move_insn (addr, reg);
3706 RTX_FRAME_RELATED_P (insn) = 1;
3709 rtx mem = gen_rtx_MEM (DFmode,
3710 plus_constant (base, offset));
3712 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3713 gen_rtx_SET (VOIDmode, mem, reg),
3718 rtx meml = gen_rtx_MEM (SFmode,
3719 plus_constant (base, offset));
3720 rtx memr = gen_rtx_MEM (SFmode,
3721 plus_constant (base, offset + 4));
3722 rtx regl = gen_rtx_REG (SFmode, i);
3723 rtx regr = gen_rtx_REG (SFmode, i + 1);
3724 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3725 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3728 RTX_FRAME_RELATED_P (setl) = 1;
3729 RTX_FRAME_RELATED_P (setr) = 1;
3730 vec = gen_rtvec (2, setl, setr);
3732 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3733 gen_rtx_SEQUENCE (VOIDmode, vec),
3737 offset += GET_MODE_SIZE (DFmode);
3744 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3745 Handle case where DISP > 8k by using the add_high_const patterns. */
3748 load_reg (int reg, HOST_WIDE_INT disp, int base)
3750 rtx dest = gen_rtx_REG (word_mode, reg);
3751 rtx basereg = gen_rtx_REG (Pmode, base);
3754 if (VAL_14_BITS_P (disp))
3755 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3756 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3758 rtx delta = GEN_INT (disp);
3759 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3761 emit_move_insn (tmpreg, delta);
3762 if (TARGET_DISABLE_INDEXING)
3764 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3765 src = gen_rtx_MEM (word_mode, tmpreg);
3768 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3772 rtx delta = GEN_INT (disp);
3773 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3774 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3776 emit_move_insn (tmpreg, high);
3777 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3780 emit_move_insn (dest, src);
3783 /* Update the total code bytes output to the text section. */
3786 update_total_code_bytes (int nbytes)
3788 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3789 && !IN_NAMED_SECTION_P (cfun->decl))
3791 if (INSN_ADDRESSES_SET_P ())
3793 unsigned long old_total = total_code_bytes;
3795 total_code_bytes += nbytes;
3797 /* Be prepared to handle overflows. */
3798 if (old_total > total_code_bytes)
3799 total_code_bytes = -1;
3802 total_code_bytes = -1;
3806 /* This function generates the assembly code for function exit.
3807 Args are as for output_function_prologue ().
3809 The function epilogue should not depend on the current stack
3810 pointer! It should use the frame pointer only. This is mandatory
3811 because of alloca; we also take advantage of it to omit stack
3812 adjustments before returning. */
3815 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3817 rtx insn = get_last_insn ();
3821 /* hppa_expand_epilogue does the dirty work now. We just need
3822 to output the assembler directives which denote the end
3825 To make debuggers happy, emit a nop if the epilogue was completely
3826 eliminated due to a volatile call as the last insn in the
3827 current function. That way the return address (in %r2) will
3828 always point to a valid instruction in the current function. */
3830 /* Get the last real insn. */
3831 if (GET_CODE (insn) == NOTE)
3832 insn = prev_real_insn (insn);
3834 /* If it is a sequence, then look inside. */
3835 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3836 insn = XVECEXP (PATTERN (insn), 0, 0);
3838 /* If insn is a CALL_INSN, then it must be a call to a volatile
3839 function (otherwise there would be epilogue insns). */
3840 if (insn && GET_CODE (insn) == CALL_INSN)
3842 fputs ("\tnop\n", file);
3846 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3848 if (TARGET_SOM && TARGET_GAS)
3850 /* We done with this subspace except possibly for some additional
3851 debug information. Forget that we are in this subspace to ensure
3852 that the next function is output in its own subspace. */
3856 if (INSN_ADDRESSES_SET_P ())
3858 insn = get_last_nonnote_insn ();
3859 last_address += INSN_ADDRESSES (INSN_UID (insn));
3861 last_address += insn_default_length (insn);
3862 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
3863 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
3866 /* Finally, update the total number of code bytes output so far. */
3867 update_total_code_bytes (last_address);
3871 hppa_expand_epilogue (void)
3874 HOST_WIDE_INT offset;
3875 HOST_WIDE_INT ret_off = 0;
3877 int merge_sp_adjust_with_load = 0;
3879 /* We will use this often. */
3880 tmpreg = gen_rtx_REG (word_mode, 1);
3882 /* Try to restore RP early to avoid load/use interlocks when
3883 RP gets used in the return (bv) instruction. This appears to still
3884 be necessary even when we schedule the prologue and epilogue. */
3885 if (regs_ever_live [2] || current_function_calls_eh_return)
3887 ret_off = TARGET_64BIT ? -16 : -20;
3888 if (frame_pointer_needed)
3890 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3895 /* No frame pointer, and stack is smaller than 8k. */
3896 if (VAL_14_BITS_P (ret_off - actual_fsize))
3898 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3904 /* General register restores. */
3905 if (frame_pointer_needed)
3907 offset = local_fsize;
3909 /* If the current function calls __builtin_eh_return, then we need
3910 to restore the saved EH data registers. */
3911 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3913 unsigned int i, regno;
3917 regno = EH_RETURN_DATA_REGNO (i);
3918 if (regno == INVALID_REGNUM)
3921 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3922 offset += UNITS_PER_WORD;
3926 for (i = 18; i >= 4; i--)
3927 if (regs_ever_live[i] && ! call_used_regs[i])
3929 load_reg (i, offset, FRAME_POINTER_REGNUM);
3930 offset += UNITS_PER_WORD;
3935 offset = local_fsize - actual_fsize;
3937 /* If the current function calls __builtin_eh_return, then we need
3938 to restore the saved EH data registers. */
3939 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3941 unsigned int i, regno;
3945 regno = EH_RETURN_DATA_REGNO (i);
3946 if (regno == INVALID_REGNUM)
3949 /* Only for the first load.
3950 merge_sp_adjust_with_load holds the register load
3951 with which we will merge the sp adjustment. */
3952 if (merge_sp_adjust_with_load == 0
3954 && VAL_14_BITS_P (-actual_fsize))
3955 merge_sp_adjust_with_load = regno;
3957 load_reg (regno, offset, STACK_POINTER_REGNUM);
3958 offset += UNITS_PER_WORD;
3962 for (i = 18; i >= 3; i--)
3964 if (regs_ever_live[i] && ! call_used_regs[i])
3966 /* Only for the first load.
3967 merge_sp_adjust_with_load holds the register load
3968 with which we will merge the sp adjustment. */
3969 if (merge_sp_adjust_with_load == 0
3971 && VAL_14_BITS_P (-actual_fsize))
3972 merge_sp_adjust_with_load = i;
3974 load_reg (i, offset, STACK_POINTER_REGNUM);
3975 offset += UNITS_PER_WORD;
3980 /* Align pointer properly (doubleword boundary). */
3981 offset = (offset + 7) & ~7;
3983 /* FP register restores. */
3986 /* Adjust the register to index off of. */
3987 if (frame_pointer_needed)
3988 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3990 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3992 /* Actually do the restores now. */
3993 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3994 if (regs_ever_live[i]
3995 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3997 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3998 rtx dest = gen_rtx_REG (DFmode, i);
3999 emit_move_insn (dest, src);
4003 /* Emit a blockage insn here to keep these insns from being moved to
4004 an earlier spot in the epilogue, or into the main instruction stream.
4006 This is necessary as we must not cut the stack back before all the
4007 restores are finished. */
4008 emit_insn (gen_blockage ());
4010 /* Reset stack pointer (and possibly frame pointer). The stack
4011 pointer is initially set to fp + 64 to avoid a race condition. */
4012 if (frame_pointer_needed)
4014 rtx delta = GEN_INT (-64);
4016 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4017 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4019 /* If we were deferring a callee register restore, do it now. */
4020 else if (merge_sp_adjust_with_load)
4022 rtx delta = GEN_INT (-actual_fsize);
4023 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4025 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4027 else if (actual_fsize != 0)
4028 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4031 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4032 frame greater than 8k), do so now. */
4034 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4036 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4038 rtx sa = EH_RETURN_STACKADJ_RTX;
4040 emit_insn (gen_blockage ());
4041 emit_insn (TARGET_64BIT
4042 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4043 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4048 hppa_pic_save_rtx (void)
4050 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4054 hppa_profile_hook (int label_no)
4056 /* We use SImode for the address of the function in both 32 and
4057 64-bit code to avoid having to provide DImode versions of the
4058 lcla2 and load_offset_label_address insn patterns. */
4059 rtx reg = gen_reg_rtx (SImode);
4060 rtx label_rtx = gen_label_rtx ();
4061 rtx begin_label_rtx, call_insn;
4062 char begin_label_name[16];
4064 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4066 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4069 emit_move_insn (arg_pointer_rtx,
4070 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4073 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4075 /* The address of the function is loaded into %r25 with a instruction-
4076 relative sequence that avoids the use of relocations. The sequence
4077 is split so that the load_offset_label_address instruction can
4078 occupy the delay slot of the call to _mcount. */
4080 emit_insn (gen_lcla2 (reg, label_rtx));
4082 emit_insn (gen_lcla1 (reg, label_rtx));
4084 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4085 reg, begin_label_rtx, label_rtx));
4087 #ifndef NO_PROFILE_COUNTERS
4089 rtx count_label_rtx, addr, r24;
4090 char count_label_name[16];
4092 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4093 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4095 addr = force_reg (Pmode, count_label_rtx);
4096 r24 = gen_rtx_REG (Pmode, 24);
4097 emit_move_insn (r24, addr);
4100 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4101 gen_rtx_SYMBOL_REF (Pmode,
4103 GEN_INT (TARGET_64BIT ? 24 : 12)));
4105 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4110 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4111 gen_rtx_SYMBOL_REF (Pmode,
4113 GEN_INT (TARGET_64BIT ? 16 : 8)));
4117 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4118 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4120 /* Indicate the _mcount call cannot throw, nor will it execute a
4122 REG_NOTES (call_insn)
4123 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4126 /* Fetch the return address for the frame COUNT steps up from
4127 the current frame, after the prologue. FRAMEADDR is the
4128 frame pointer of the COUNT frame.
4130 We want to ignore any export stub remnants here. To handle this,
4131 we examine the code at the return address, and if it is an export
4132 stub, we return a memory rtx for the stub return address stored
4135 The value returned is used in two different ways:
4137 1. To find a function's caller.
4139 2. To change the return address for a function.
4141 This function handles most instances of case 1; however, it will
4142 fail if there are two levels of stubs to execute on the return
4143 path. The only way I believe that can happen is if the return value
4144 needs a parameter relocation, which never happens for C code.
4146 This function handles most instances of case 2; however, it will
4147 fail if we did not originally have stub code on the return path
4148 but will need stub code on the new return path. This can happen if
4149 the caller & callee are both in the main program, but the new
4150 return location is in a shared library. */
4153 return_addr_rtx (int count, rtx frameaddr)
4163 rp = get_hard_reg_initial_val (Pmode, 2);
4165 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4168 saved_rp = gen_reg_rtx (Pmode);
4169 emit_move_insn (saved_rp, rp);
4171 /* Get pointer to the instruction stream. We have to mask out the
4172 privilege level from the two low order bits of the return address
4173 pointer here so that ins will point to the start of the first
4174 instruction that would have been executed if we returned. */
4175 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4176 label = gen_label_rtx ();
4178 /* Check the instruction stream at the normal return address for the
4181 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4182 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4183 0x00011820 | stub+16: mtsp r1,sr0
4184 0xe0400002 | stub+20: be,n 0(sr0,rp)
4186 If it is an export stub, than our return address is really in
4189 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4190 NULL_RTX, SImode, 1);
4191 emit_jump_insn (gen_bne (label));
4193 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4194 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4195 emit_jump_insn (gen_bne (label));
4197 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4198 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4199 emit_jump_insn (gen_bne (label));
4201 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4202 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4204 /* If there is no export stub then just use the value saved from
4205 the return pointer register. */
4207 emit_jump_insn (gen_bne (label));
4209 /* Here we know that our return address points to an export
4210 stub. We don't want to return the address of the export stub,
4211 but rather the return address of the export stub. That return
4212 address is stored at -24[frameaddr]. */
4214 emit_move_insn (saved_rp,
4216 memory_address (Pmode,
4217 plus_constant (frameaddr,
4224 /* This is only valid once reload has completed because it depends on
4225 knowing exactly how much (if any) frame there is and...
4227 It's only valid if there is no frame marker to de-allocate and...
4229 It's only valid if %r2 hasn't been saved into the caller's frame
4230 (we're not profiling and %r2 isn't live anywhere). */
4232 hppa_can_use_return_insn_p (void)
4234 return (reload_completed
4235 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4236 && ! regs_ever_live[2]
4237 && ! frame_pointer_needed);
4241 emit_bcond_fp (enum rtx_code code, rtx operand0)
4243 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4244 gen_rtx_IF_THEN_ELSE (VOIDmode,
4245 gen_rtx_fmt_ee (code,
4247 gen_rtx_REG (CCFPmode, 0),
4249 gen_rtx_LABEL_REF (VOIDmode, operand0),
4255 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4257 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4258 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4261 /* Adjust the cost of a scheduling dependency. Return the new cost of
4262 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4265 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4267 enum attr_type attr_type;
4269 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4270 true dependencies as they are described with bypasses now. */
4271 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4274 if (! recog_memoized (insn))
4277 attr_type = get_attr_type (insn);
4279 switch (REG_NOTE_KIND (link))
4282 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4285 if (attr_type == TYPE_FPLOAD)
4287 rtx pat = PATTERN (insn);
4288 rtx dep_pat = PATTERN (dep_insn);
4289 if (GET_CODE (pat) == PARALLEL)
4291 /* This happens for the fldXs,mb patterns. */
4292 pat = XVECEXP (pat, 0, 0);
4294 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4295 /* If this happens, we have to extend this to schedule
4296 optimally. Return 0 for now. */
4299 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4301 if (! recog_memoized (dep_insn))
4303 switch (get_attr_type (dep_insn))
4310 case TYPE_FPSQRTSGL:
4311 case TYPE_FPSQRTDBL:
4312 /* A fpload can't be issued until one cycle before a
4313 preceding arithmetic operation has finished if
4314 the target of the fpload is any of the sources
4315 (or destination) of the arithmetic operation. */
4316 return insn_default_latency (dep_insn) - 1;
4323 else if (attr_type == TYPE_FPALU)
4325 rtx pat = PATTERN (insn);
4326 rtx dep_pat = PATTERN (dep_insn);
4327 if (GET_CODE (pat) == PARALLEL)
4329 /* This happens for the fldXs,mb patterns. */
4330 pat = XVECEXP (pat, 0, 0);
4332 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4333 /* If this happens, we have to extend this to schedule
4334 optimally. Return 0 for now. */
4337 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4339 if (! recog_memoized (dep_insn))
4341 switch (get_attr_type (dep_insn))
4345 case TYPE_FPSQRTSGL:
4346 case TYPE_FPSQRTDBL:
4347 /* An ALU flop can't be issued until two cycles before a
4348 preceding divide or sqrt operation has finished if
4349 the target of the ALU flop is any of the sources
4350 (or destination) of the divide or sqrt operation. */
4351 return insn_default_latency (dep_insn) - 2;
4359 /* For other anti dependencies, the cost is 0. */
4362 case REG_DEP_OUTPUT:
4363 /* Output dependency; DEP_INSN writes a register that INSN writes some
4365 if (attr_type == TYPE_FPLOAD)
4367 rtx pat = PATTERN (insn);
4368 rtx dep_pat = PATTERN (dep_insn);
4369 if (GET_CODE (pat) == PARALLEL)
4371 /* This happens for the fldXs,mb patterns. */
4372 pat = XVECEXP (pat, 0, 0);
4374 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4375 /* If this happens, we have to extend this to schedule
4376 optimally. Return 0 for now. */
4379 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4381 if (! recog_memoized (dep_insn))
4383 switch (get_attr_type (dep_insn))
4390 case TYPE_FPSQRTSGL:
4391 case TYPE_FPSQRTDBL:
4392 /* A fpload can't be issued until one cycle before a
4393 preceding arithmetic operation has finished if
4394 the target of the fpload is the destination of the
4395 arithmetic operation.
4397 Exception: For PA7100LC, PA7200 and PA7300, the cost
4398 is 3 cycles, unless they bundle together. We also
4399 pay the penalty if the second insn is a fpload. */
4400 return insn_default_latency (dep_insn) - 1;
4407 else if (attr_type == TYPE_FPALU)
4409 rtx pat = PATTERN (insn);
4410 rtx dep_pat = PATTERN (dep_insn);
4411 if (GET_CODE (pat) == PARALLEL)
4413 /* This happens for the fldXs,mb patterns. */
4414 pat = XVECEXP (pat, 0, 0);
4416 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4417 /* If this happens, we have to extend this to schedule
4418 optimally. Return 0 for now. */
4421 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4423 if (! recog_memoized (dep_insn))
4425 switch (get_attr_type (dep_insn))
4429 case TYPE_FPSQRTSGL:
4430 case TYPE_FPSQRTDBL:
4431 /* An ALU flop can't be issued until two cycles before a
4432 preceding divide or sqrt operation has finished if
4433 the target of the ALU flop is also the target of
4434 the divide or sqrt operation. */
4435 return insn_default_latency (dep_insn) - 2;
4443 /* For other output dependencies, the cost is 0. */
4451 /* Adjust scheduling priorities. We use this to try and keep addil
4452 and the next use of %r1 close together. */
4454 pa_adjust_priority (rtx insn, int priority)
4456 rtx set = single_set (insn);
4460 src = SET_SRC (set);
4461 dest = SET_DEST (set);
4462 if (GET_CODE (src) == LO_SUM
4463 && symbolic_operand (XEXP (src, 1), VOIDmode)
4464 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4467 else if (GET_CODE (src) == MEM
4468 && GET_CODE (XEXP (src, 0)) == LO_SUM
4469 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4470 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4473 else if (GET_CODE (dest) == MEM
4474 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4475 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4476 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4482 /* The 700 can only issue a single insn at a time.
4483 The 7XXX processors can issue two insns at a time.
4484 The 8000 can issue 4 insns at a time. */
4486 pa_issue_rate (void)
4490 case PROCESSOR_700: return 1;
4491 case PROCESSOR_7100: return 2;
4492 case PROCESSOR_7100LC: return 2;
4493 case PROCESSOR_7200: return 2;
4494 case PROCESSOR_7300: return 2;
4495 case PROCESSOR_8000: return 4;
4504 /* Return any length adjustment needed by INSN which already has its length
4505 computed as LENGTH. Return zero if no adjustment is necessary.
4507 For the PA: function calls, millicode calls, and backwards short
4508 conditional branches with unfilled delay slots need an adjustment by +1
4509 (to account for the NOP which will be inserted into the instruction stream).
4511 Also compute the length of an inline block move here as it is too
4512 complicated to express as a length attribute in pa.md. */
4514 pa_adjust_insn_length (rtx insn, int length)
4516 rtx pat = PATTERN (insn);
4518 /* Jumps inside switch tables which have unfilled delay slots need
4520 if (GET_CODE (insn) == JUMP_INSN
4521 && GET_CODE (pat) == PARALLEL
4522 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4524 /* Millicode insn with an unfilled delay slot. */
4525 else if (GET_CODE (insn) == INSN
4526 && GET_CODE (pat) != SEQUENCE
4527 && GET_CODE (pat) != USE
4528 && GET_CODE (pat) != CLOBBER
4529 && get_attr_type (insn) == TYPE_MILLI)
4531 /* Block move pattern. */
4532 else if (GET_CODE (insn) == INSN
4533 && GET_CODE (pat) == PARALLEL
4534 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4535 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4536 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4537 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4538 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4539 return compute_movmem_length (insn) - 4;
4540 /* Block clear pattern. */
4541 else if (GET_CODE (insn) == INSN
4542 && GET_CODE (pat) == PARALLEL
4543 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4544 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4545 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4546 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4547 return compute_clrmem_length (insn) - 4;
4548 /* Conditional branch with an unfilled delay slot. */
4549 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4551 /* Adjust a short backwards conditional with an unfilled delay slot. */
4552 if (GET_CODE (pat) == SET
4554 && ! forward_branch_p (insn))
4556 else if (GET_CODE (pat) == PARALLEL
4557 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4560 /* Adjust dbra insn with short backwards conditional branch with
4561 unfilled delay slot -- only for case where counter is in a
4562 general register register. */
4563 else if (GET_CODE (pat) == PARALLEL
4564 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4565 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4566 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4568 && ! forward_branch_p (insn))
4576 /* Print operand X (an rtx) in assembler syntax to file FILE.
4577 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4578 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4581 print_operand (FILE *file, rtx x, int code)
4586 /* Output a 'nop' if there's nothing for the delay slot. */
4587 if (dbr_sequence_length () == 0)
4588 fputs ("\n\tnop", file);
4591 /* Output a nullification completer if there's nothing for the */
4592 /* delay slot or nullification is requested. */
4593 if (dbr_sequence_length () == 0 ||
4595 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4599 /* Print out the second register name of a register pair.
4600 I.e., R (6) => 7. */
4601 fputs (reg_names[REGNO (x) + 1], file);
4604 /* A register or zero. */
4606 || (x == CONST0_RTX (DFmode))
4607 || (x == CONST0_RTX (SFmode)))
4609 fputs ("%r0", file);
4615 /* A register or zero (floating point). */
4617 || (x == CONST0_RTX (DFmode))
4618 || (x == CONST0_RTX (SFmode)))
4620 fputs ("%fr0", file);
4629 xoperands[0] = XEXP (XEXP (x, 0), 0);
4630 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4631 output_global_address (file, xoperands[1], 0);
4632 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4636 case 'C': /* Plain (C)ondition */
4638 switch (GET_CODE (x))
4641 fputs ("=", file); break;
4643 fputs ("<>", file); break;
4645 fputs (">", file); break;
4647 fputs (">=", file); break;
4649 fputs (">>=", file); break;
4651 fputs (">>", file); break;
4653 fputs ("<", file); break;
4655 fputs ("<=", file); break;
4657 fputs ("<<=", file); break;
4659 fputs ("<<", file); break;
4664 case 'N': /* Condition, (N)egated */
4665 switch (GET_CODE (x))
4668 fputs ("<>", file); break;
4670 fputs ("=", file); break;
4672 fputs ("<=", file); break;
4674 fputs ("<", file); break;
4676 fputs ("<<", file); break;
4678 fputs ("<<=", file); break;
4680 fputs (">=", file); break;
4682 fputs (">", file); break;
4684 fputs (">>", file); break;
4686 fputs (">>=", file); break;
4691 /* For floating point comparisons. Note that the output
4692 predicates are the complement of the desired mode. The
4693 conditions for GT, GE, LT, LE and LTGT cause an invalid
4694 operation exception if the result is unordered and this
4695 exception is enabled in the floating-point status register. */
4697 switch (GET_CODE (x))
4700 fputs ("!=", file); break;
4702 fputs ("=", file); break;
4704 fputs ("!>", file); break;
4706 fputs ("!>=", file); break;
4708 fputs ("!<", file); break;
4710 fputs ("!<=", file); break;
4712 fputs ("!<>", file); break;
4714 fputs ("!?<=", file); break;
4716 fputs ("!?<", file); break;
4718 fputs ("!?>=", file); break;
4720 fputs ("!?>", file); break;
4722 fputs ("!?=", file); break;
4724 fputs ("!?", file); break;
4726 fputs ("?", file); break;
4731 case 'S': /* Condition, operands are (S)wapped. */
4732 switch (GET_CODE (x))
4735 fputs ("=", file); break;
4737 fputs ("<>", file); break;
4739 fputs ("<", file); break;
4741 fputs ("<=", file); break;
4743 fputs ("<<=", file); break;
4745 fputs ("<<", file); break;
4747 fputs (">", file); break;
4749 fputs (">=", file); break;
4751 fputs (">>=", file); break;
4753 fputs (">>", file); break;
4758 case 'B': /* Condition, (B)oth swapped and negate. */
4759 switch (GET_CODE (x))
4762 fputs ("<>", file); break;
4764 fputs ("=", file); break;
4766 fputs (">=", file); break;
4768 fputs (">", file); break;
4770 fputs (">>", file); break;
4772 fputs (">>=", file); break;
4774 fputs ("<=", file); break;
4776 fputs ("<", file); break;
4778 fputs ("<<", file); break;
4780 fputs ("<<=", file); break;
4786 gcc_assert (GET_CODE (x) == CONST_INT);
4787 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4790 gcc_assert (GET_CODE (x) == CONST_INT);
4791 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4794 gcc_assert (GET_CODE (x) == CONST_INT);
4795 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4798 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
4799 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4802 gcc_assert (GET_CODE (x) == CONST_INT);
4803 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4806 gcc_assert (GET_CODE (x) == CONST_INT);
4807 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4810 if (GET_CODE (x) == CONST_INT)
4815 switch (GET_CODE (XEXP (x, 0)))
4819 if (ASSEMBLER_DIALECT == 0)
4820 fputs ("s,mb", file);
4822 fputs (",mb", file);
4826 if (ASSEMBLER_DIALECT == 0)
4827 fputs ("s,ma", file);
4829 fputs (",ma", file);
4832 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4833 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4835 if (ASSEMBLER_DIALECT == 0)
4838 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4839 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4841 if (ASSEMBLER_DIALECT == 0)
4842 fputs ("x,s", file);
4846 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4850 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4856 output_global_address (file, x, 0);
4859 output_global_address (file, x, 1);
4861 case 0: /* Don't do anything special */
4866 compute_zdepwi_operands (INTVAL (x), op);
4867 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4873 compute_zdepdi_operands (INTVAL (x), op);
4874 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4878 /* We can get here from a .vtable_inherit due to our
4879 CONSTANT_ADDRESS_P rejecting perfectly good constant
4885 if (GET_CODE (x) == REG)
4887 fputs (reg_names [REGNO (x)], file);
4888 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4894 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4895 && (REGNO (x) & 1) == 0)
4898 else if (GET_CODE (x) == MEM)
4900 int size = GET_MODE_SIZE (GET_MODE (x));
4901 rtx base = NULL_RTX;
4902 switch (GET_CODE (XEXP (x, 0)))
4906 base = XEXP (XEXP (x, 0), 0);
4907 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4911 base = XEXP (XEXP (x, 0), 0);
4912 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4915 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4916 fprintf (file, "%s(%s)",
4917 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4918 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4919 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4920 fprintf (file, "%s(%s)",
4921 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4922 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4923 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4924 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4926 /* Because the REG_POINTER flag can get lost during reload,
4927 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
4928 index and base registers in the combined move patterns. */
4929 rtx base = XEXP (XEXP (x, 0), 1);
4930 rtx index = XEXP (XEXP (x, 0), 0);
4932 fprintf (file, "%s(%s)",
4933 reg_names [REGNO (index)], reg_names [REGNO (base)]);
4936 output_address (XEXP (x, 0));
4939 output_address (XEXP (x, 0));
4944 output_addr_const (file, x);
4947 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4950 output_global_address (FILE *file, rtx x, int round_constant)
4953 /* Imagine (high (const (plus ...))). */
4954 if (GET_CODE (x) == HIGH)
4957 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4958 output_addr_const (file, x);
4959 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4961 output_addr_const (file, x);
4962 fputs ("-$global$", file);
4964 else if (GET_CODE (x) == CONST)
4966 const char *sep = "";
4967 int offset = 0; /* assembler wants -$global$ at end */
4968 rtx base = NULL_RTX;
4970 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
4973 base = XEXP (XEXP (x, 0), 0);
4974 output_addr_const (file, base);
4977 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4983 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
4986 base = XEXP (XEXP (x, 0), 1);
4987 output_addr_const (file, base);
4990 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4996 /* How bogus. The compiler is apparently responsible for
4997 rounding the constant if it uses an LR field selector.
4999 The linker and/or assembler seem a better place since
5000 they have to do this kind of thing already.
5002 If we fail to do this, HP's optimizing linker may eliminate
5003 an addil, but not update the ldw/stw/ldo instruction that
5004 uses the result of the addil. */
5006 offset = ((offset + 0x1000) & ~0x1fff);
5008 switch (GET_CODE (XEXP (x, 0)))
5021 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5029 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5030 fputs ("-$global$", file);
5032 fprintf (file, "%s%d", sep, offset);
5035 output_addr_const (file, x);
5038 /* Output boilerplate text to appear at the beginning of the file.
5039 There are several possible versions. */
5040 #define aputs(x) fputs(x, asm_out_file)
5042 pa_file_start_level (void)
5045 aputs ("\t.LEVEL 2.0w\n");
5046 else if (TARGET_PA_20)
5047 aputs ("\t.LEVEL 2.0\n");
5048 else if (TARGET_PA_11)
5049 aputs ("\t.LEVEL 1.1\n");
5051 aputs ("\t.LEVEL 1.0\n");
5055 pa_file_start_space (int sortspace)
5057 aputs ("\t.SPACE $PRIVATE$");
5060 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5061 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5062 "\n\t.SPACE $TEXT$");
5065 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5066 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5070 pa_file_start_file (int want_version)
5072 if (write_symbols != NO_DEBUG)
5074 output_file_directive (asm_out_file, main_input_filename);
5076 aputs ("\t.version\t\"01.01\"\n");
5081 pa_file_start_mcount (const char *aswhat)
5084 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5088 pa_elf_file_start (void)
5090 pa_file_start_level ();
5091 pa_file_start_mcount ("ENTRY");
5092 pa_file_start_file (0);
5096 pa_som_file_start (void)
5098 pa_file_start_level ();
5099 pa_file_start_space (0);
5100 aputs ("\t.IMPORT $global$,DATA\n"
5101 "\t.IMPORT $$dyncall,MILLICODE\n");
5102 pa_file_start_mcount ("CODE");
5103 pa_file_start_file (0);
5107 pa_linux_file_start (void)
5109 pa_file_start_file (1);
5110 pa_file_start_level ();
5111 pa_file_start_mcount ("CODE");
5115 pa_hpux64_gas_file_start (void)
5117 pa_file_start_level ();
5118 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5120 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5122 pa_file_start_file (1);
5126 pa_hpux64_hpas_file_start (void)
5128 pa_file_start_level ();
5129 pa_file_start_space (1);
5130 pa_file_start_mcount ("CODE");
5131 pa_file_start_file (0);
5135 static struct deferred_plabel *
5136 get_plabel (rtx symbol)
5138 const char *fname = XSTR (symbol, 0);
5141 /* See if we have already put this function on the list of deferred
5142 plabels. This list is generally small, so a liner search is not
5143 too ugly. If it proves too slow replace it with something faster. */
5144 for (i = 0; i < n_deferred_plabels; i++)
5145 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5148 /* If the deferred plabel list is empty, or this entry was not found
5149 on the list, create a new entry on the list. */
5150 if (deferred_plabels == NULL || i == n_deferred_plabels)
5154 if (deferred_plabels == 0)
5155 deferred_plabels = (struct deferred_plabel *)
5156 ggc_alloc (sizeof (struct deferred_plabel));
5158 deferred_plabels = (struct deferred_plabel *)
5159 ggc_realloc (deferred_plabels,
5160 ((n_deferred_plabels + 1)
5161 * sizeof (struct deferred_plabel)));
5163 i = n_deferred_plabels++;
5164 deferred_plabels[i].internal_label = gen_label_rtx ();
5165 deferred_plabels[i].symbol = symbol;
5167 /* Gross. We have just implicitly taken the address of this
5168 function. Mark it in the same manner as assemble_name. */
5169 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5171 mark_referenced (id);
5174 return &deferred_plabels[i];
5178 output_deferred_plabels (void)
5181 /* If we have deferred plabels, then we need to switch into the data
5182 section and align it to a 4 byte boundary before we output the
5183 deferred plabels. */
5184 if (n_deferred_plabels)
5187 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5190 /* Now output the deferred plabels. */
5191 for (i = 0; i < n_deferred_plabels; i++)
5193 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5194 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5195 assemble_integer (deferred_plabels[i].symbol,
5196 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5200 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5201 /* Initialize optabs to point to HPUX long double emulation routines. */
5203 pa_hpux_init_libfuncs (void)
5205 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5206 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5207 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5208 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5209 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5210 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5211 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5212 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5213 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5215 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5216 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5217 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5218 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5219 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5220 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5221 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5223 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5224 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5225 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5226 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5228 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5229 ? "__U_Qfcnvfxt_quad_to_sgl"
5230 : "_U_Qfcnvfxt_quad_to_sgl");
5231 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5232 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5233 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5235 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5236 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5240 /* HP's millicode routines mean something special to the assembler.
5241 Keep track of which ones we have used. */
5243 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5244 static void import_milli (enum millicodes);
5245 static char imported[(int) end1000];
5246 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5247 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5248 #define MILLI_START 10
5251 import_milli (enum millicodes code)
5253 char str[sizeof (import_string)];
5255 if (!imported[(int) code])
5257 imported[(int) code] = 1;
5258 strcpy (str, import_string);
5259 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5260 output_asm_insn (str, 0);
5264 /* The register constraints have put the operands and return value in
5265 the proper registers. */
5268 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5270 import_milli (mulI);
5271 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5274 /* Emit the rtl for doing a division by a constant. */
5276 /* Do magic division millicodes exist for this value? */
5277 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5279 /* We'll use an array to keep track of the magic millicodes and
5280 whether or not we've used them already. [n][0] is signed, [n][1] is
5283 static int div_milli[16][2];
5286 emit_hpdiv_const (rtx *operands, int unsignedp)
5288 if (GET_CODE (operands[2]) == CONST_INT
5289 && INTVAL (operands[2]) > 0
5290 && INTVAL (operands[2]) < 16
5291 && magic_milli[INTVAL (operands[2])])
5293 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5295 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5299 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5300 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5302 gen_rtx_REG (SImode, 26),
5304 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5305 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5306 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5307 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5308 gen_rtx_CLOBBER (VOIDmode, ret))));
5309 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5316 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5320 /* If the divisor is a constant, try to use one of the special
5322 if (GET_CODE (operands[0]) == CONST_INT)
5324 static char buf[100];
5325 divisor = INTVAL (operands[0]);
5326 if (!div_milli[divisor][unsignedp])
5328 div_milli[divisor][unsignedp] = 1;
5330 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5332 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5336 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5337 INTVAL (operands[0]));
5338 return output_millicode_call (insn,
5339 gen_rtx_SYMBOL_REF (SImode, buf));
5343 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5344 INTVAL (operands[0]));
5345 return output_millicode_call (insn,
5346 gen_rtx_SYMBOL_REF (SImode, buf));
5349 /* Divisor isn't a special constant. */
5354 import_milli (divU);
5355 return output_millicode_call (insn,
5356 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5360 import_milli (divI);
5361 return output_millicode_call (insn,
5362 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5367 /* Output a $$rem millicode to do mod. */
5370 output_mod_insn (int unsignedp, rtx insn)
5374 import_milli (remU);
5375 return output_millicode_call (insn,
5376 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5380 import_milli (remI);
5381 return output_millicode_call (insn,
5382 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5387 output_arg_descriptor (rtx call_insn)
5389 const char *arg_regs[4];
5390 enum machine_mode arg_mode;
5392 int i, output_flag = 0;
5395 /* We neither need nor want argument location descriptors for the
5396 64bit runtime environment or the ELF32 environment. */
5397 if (TARGET_64BIT || TARGET_ELF32)
5400 for (i = 0; i < 4; i++)
5403 /* Specify explicitly that no argument relocations should take place
5404 if using the portable runtime calling conventions. */
5405 if (TARGET_PORTABLE_RUNTIME)
5407 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5412 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5413 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5414 link; link = XEXP (link, 1))
5416 rtx use = XEXP (link, 0);
5418 if (! (GET_CODE (use) == USE
5419 && GET_CODE (XEXP (use, 0)) == REG
5420 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5423 arg_mode = GET_MODE (XEXP (use, 0));
5424 regno = REGNO (XEXP (use, 0));
5425 if (regno >= 23 && regno <= 26)
5427 arg_regs[26 - regno] = "GR";
5428 if (arg_mode == DImode)
5429 arg_regs[25 - regno] = "GR";
5431 else if (regno >= 32 && regno <= 39)
5433 if (arg_mode == SFmode)
5434 arg_regs[(regno - 32) / 2] = "FR";
5437 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5438 arg_regs[(regno - 34) / 2] = "FR";
5439 arg_regs[(regno - 34) / 2 + 1] = "FU";
5441 arg_regs[(regno - 34) / 2] = "FU";
5442 arg_regs[(regno - 34) / 2 + 1] = "FR";
5447 fputs ("\t.CALL ", asm_out_file);
5448 for (i = 0; i < 4; i++)
5453 fputc (',', asm_out_file);
5454 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5457 fputc ('\n', asm_out_file);
5460 /* Return the class of any secondary reload register that is needed to
5461 move IN into a register in class CLASS using mode MODE.
5463 Profiling has showed this routine and its descendants account for
5464 a significant amount of compile time (~7%). So it has been
5465 optimized to reduce redundant computations and eliminate useless
5468 It might be worthwhile to try and make this a leaf function too. */
5471 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5473 int regno, is_symbolic;
5475 /* Trying to load a constant into a FP register during PIC code
5476 generation will require %r1 as a scratch register. */
5478 && GET_MODE_CLASS (mode) == MODE_INT
5479 && FP_REG_CLASS_P (class)
5480 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5483 /* Profiling showed the PA port spends about 1.3% of its compilation
5484 time in true_regnum from calls inside secondary_reload_class. */
5486 if (GET_CODE (in) == REG)
5489 if (regno >= FIRST_PSEUDO_REGISTER)
5490 regno = true_regnum (in);
5492 else if (GET_CODE (in) == SUBREG)
5493 regno = true_regnum (in);
5497 /* If we have something like (mem (mem (...)), we can safely assume the
5498 inner MEM will end up in a general register after reloading, so there's
5499 no need for a secondary reload. */
5500 if (GET_CODE (in) == MEM
5501 && GET_CODE (XEXP (in, 0)) == MEM)
5504 /* Handle out of range displacement for integer mode loads/stores of
5506 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5507 && GET_MODE_CLASS (mode) == MODE_INT
5508 && FP_REG_CLASS_P (class))
5509 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5510 return GENERAL_REGS;
5512 /* A SAR<->FP register copy requires a secondary register (GPR) as
5513 well as secondary memory. */
5514 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5515 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5516 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5517 return GENERAL_REGS;
5519 if (GET_CODE (in) == HIGH)
5522 /* Profiling has showed GCC spends about 2.6% of its compilation
5523 time in symbolic_operand from calls inside secondary_reload_class.
5525 We use an inline copy and only compute its return value once to avoid
5527 switch (GET_CODE (in))
5537 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5538 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5539 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5549 && read_only_operand (in, VOIDmode))
5552 if (class != R1_REGS && is_symbolic)
5558 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5559 by invisible reference. As a GCC extension, we also pass anything
5560 with a zero or variable size by reference.
5562 The 64-bit runtime does not describe passing any types by invisible
5563 reference. The internals of GCC can't currently handle passing
5564 empty structures, and zero or variable length arrays when they are
5565 not passed entirely on the stack or by reference. Thus, as a GCC
5566 extension, we pass these types by reference. The HP compiler doesn't
5567 support these types, so hopefully there shouldn't be any compatibility
5568 issues. This may have to be revisited when HP releases a C99 compiler
5569 or updates the ABI. */
5572 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5573 enum machine_mode mode, tree type,
5574 bool named ATTRIBUTE_UNUSED)
5579 size = int_size_in_bytes (type);
5581 size = GET_MODE_SIZE (mode);
5586 return size <= 0 || size > 8;
5590 function_arg_padding (enum machine_mode mode, tree type)
5593 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5595 /* Return none if justification is not required. */
5597 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5598 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5601 /* The directions set here are ignored when a BLKmode argument larger
5602 than a word is placed in a register. Different code is used for
5603 the stack and registers. This makes it difficult to have a
5604 consistent data representation for both the stack and registers.
5605 For both runtimes, the justification and padding for arguments on
5606 the stack and in registers should be identical. */
5608 /* The 64-bit runtime specifies left justification for aggregates. */
5611 /* The 32-bit runtime architecture specifies right justification.
5612 When the argument is passed on the stack, the argument is padded
5613 with garbage on the left. The HP compiler pads with zeros. */
5617 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5624 /* Do what is necessary for `va_start'. We look at the current function
5625 to determine if stdargs or varargs is used and fill in an initial
5626 va_list. A pointer to this constructor is returned. */
5629 hppa_builtin_saveregs (void)
5632 tree fntype = TREE_TYPE (current_function_decl);
5633 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5634 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5635 != void_type_node)))
5636 ? UNITS_PER_WORD : 0);
5639 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5641 offset = current_function_arg_offset_rtx;
5647 /* Adjust for varargs/stdarg differences. */
5649 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5651 offset = current_function_arg_offset_rtx;
5653 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5654 from the incoming arg pointer and growing to larger addresses. */
5655 for (i = 26, off = -64; i >= 19; i--, off += 8)
5656 emit_move_insn (gen_rtx_MEM (word_mode,
5657 plus_constant (arg_pointer_rtx, off)),
5658 gen_rtx_REG (word_mode, i));
5660 /* The incoming args pointer points just beyond the flushback area;
5661 normally this is not a serious concern. However, when we are doing
5662 varargs/stdargs we want to make the arg pointer point to the start
5663 of the incoming argument area. */
5664 emit_move_insn (virtual_incoming_args_rtx,
5665 plus_constant (arg_pointer_rtx, -64));
5667 /* Now return a pointer to the first anonymous argument. */
5668 return copy_to_reg (expand_binop (Pmode, add_optab,
5669 virtual_incoming_args_rtx,
5670 offset, 0, 0, OPTAB_LIB_WIDEN));
5673 /* Store general registers on the stack. */
5674 dest = gen_rtx_MEM (BLKmode,
5675 plus_constant (current_function_internal_arg_pointer,
5677 set_mem_alias_set (dest, get_varargs_alias_set ());
5678 set_mem_align (dest, BITS_PER_WORD);
5679 move_block_from_reg (23, dest, 4);
5681 /* move_block_from_reg will emit code to store the argument registers
5682 individually as scalar stores.
5684 However, other insns may later load from the same addresses for
5685 a structure load (passing a struct to a varargs routine).
5687 The alias code assumes that such aliasing can never happen, so we
5688 have to keep memory referencing insns from moving up beyond the
5689 last argument register store. So we emit a blockage insn here. */
5690 emit_insn (gen_blockage ());
5692 return copy_to_reg (expand_binop (Pmode, add_optab,
5693 current_function_internal_arg_pointer,
5694 offset, 0, 0, OPTAB_LIB_WIDEN));
5698 hppa_va_start (tree valist, rtx nextarg)
5700 nextarg = expand_builtin_saveregs ();
5701 std_expand_builtin_va_start (valist, nextarg);
5705 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5709 /* Args grow upward. We can use the generic routines. */
5710 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5712 else /* !TARGET_64BIT */
5714 tree ptr = build_pointer_type (type);
5717 unsigned int size, ofs;
5720 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5724 ptr = build_pointer_type (type);
5726 size = int_size_in_bytes (type);
5727 valist_type = TREE_TYPE (valist);
5729 /* Args grow down. Not handled by generic routines. */
5731 u = fold_convert (valist_type, size_in_bytes (type));
5732 t = build (MINUS_EXPR, valist_type, valist, u);
5734 /* Copied from va-pa.h, but we probably don't need to align to
5735 word size, since we generate and preserve that invariant. */
5736 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
5737 t = build (BIT_AND_EXPR, valist_type, t, u);
5739 t = build (MODIFY_EXPR, valist_type, valist, t);
5741 ofs = (8 - size) % 4;
5744 u = fold_convert (valist_type, size_int (ofs));
5745 t = build (PLUS_EXPR, valist_type, t, u);
5748 t = fold_convert (ptr, t);
5749 t = build_fold_indirect_ref (t);
5752 t = build_fold_indirect_ref (t);
5758 /* True if MODE is valid for the target. By "valid", we mean able to
5759 be manipulated in non-trivial ways. In particular, this means all
5760 the arithmetic is supported.
5762 Currently, TImode is not valid as the HP 64-bit runtime documentation
5763 doesn't document the alignment and calling conventions for this type.
5764 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
5765 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
5768 pa_scalar_mode_supported_p (enum machine_mode mode)
5770 int precision = GET_MODE_PRECISION (mode);
5772 switch (GET_MODE_CLASS (mode))
5774 case MODE_PARTIAL_INT:
5776 if (precision == CHAR_TYPE_SIZE)
5778 if (precision == SHORT_TYPE_SIZE)
5780 if (precision == INT_TYPE_SIZE)
5782 if (precision == LONG_TYPE_SIZE)
5784 if (precision == LONG_LONG_TYPE_SIZE)
5789 if (precision == FLOAT_TYPE_SIZE)
5791 if (precision == DOUBLE_TYPE_SIZE)
5793 if (precision == LONG_DOUBLE_TYPE_SIZE)
5802 /* This routine handles all the normal conditional branch sequences we
5803 might need to generate. It handles compare immediate vs compare
5804 register, nullification of delay slots, varying length branches,
5805 negated branches, and all combinations of the above. It returns the
5806 output appropriate to emit the branch corresponding to all given
5810 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
5812 static char buf[100];
5816 /* A conditional branch to the following instruction (e.g. the delay slot)
5817 is asking for a disaster. This can happen when not optimizing and
5818 when jump optimization fails.
5820 While it is usually safe to emit nothing, this can fail if the
5821 preceding instruction is a nullified branch with an empty delay
5822 slot and the same branch target as this branch. We could check
5823 for this but jump optimization should eliminate nop jumps. It
5824 is always safe to emit a nop. */
5825 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5828 /* The doubleword form of the cmpib instruction doesn't have the LEU
5829 and GTU conditions while the cmpb instruction does. Since we accept
5830 zero for cmpb, we must ensure that we use cmpb for the comparison. */
5831 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
5832 operands[2] = gen_rtx_REG (DImode, 0);
5834 /* If this is a long branch with its delay slot unfilled, set `nullify'
5835 as it can nullify the delay slot and save a nop. */
5836 if (length == 8 && dbr_sequence_length () == 0)
5839 /* If this is a short forward conditional branch which did not get
5840 its delay slot filled, the delay slot can still be nullified. */
5841 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5842 nullify = forward_branch_p (insn);
5844 /* A forward branch over a single nullified insn can be done with a
5845 comclr instruction. This avoids a single cycle penalty due to
5846 mis-predicted branch if we fall through (branch not taken). */
5848 && next_real_insn (insn) != 0
5849 && get_attr_length (next_real_insn (insn)) == 4
5850 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5856 /* All short conditional branches except backwards with an unfilled
5860 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5862 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5863 if (GET_MODE (operands[1]) == DImode)
5866 strcat (buf, "%B3");
5868 strcat (buf, "%S3");
5870 strcat (buf, " %2,%r1,%%r0");
5872 strcat (buf, ",n %2,%r1,%0");
5874 strcat (buf, " %2,%r1,%0");
5877 /* All long conditionals. Note a short backward branch with an
5878 unfilled delay slot is treated just like a long backward branch
5879 with an unfilled delay slot. */
5881 /* Handle weird backwards branch with a filled delay slot
5882 with is nullified. */
5883 if (dbr_sequence_length () != 0
5884 && ! forward_branch_p (insn)
5887 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5888 if (GET_MODE (operands[1]) == DImode)
5891 strcat (buf, "%S3");
5893 strcat (buf, "%B3");
5894 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5896 /* Handle short backwards branch with an unfilled delay slot.
5897 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5898 taken and untaken branches. */
5899 else if (dbr_sequence_length () == 0
5900 && ! forward_branch_p (insn)
5901 && INSN_ADDRESSES_SET_P ()
5902 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5903 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5905 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5906 if (GET_MODE (operands[1]) == DImode)
5909 strcat (buf, "%B3 %2,%r1,%0%#");
5911 strcat (buf, "%S3 %2,%r1,%0%#");
5915 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5916 if (GET_MODE (operands[1]) == DImode)
5919 strcat (buf, "%S3");
5921 strcat (buf, "%B3");
5923 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5925 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5931 xoperands[0] = operands[0];
5932 xoperands[1] = operands[1];
5933 xoperands[2] = operands[2];
5934 xoperands[3] = operands[3];
5936 /* The reversed conditional branch must branch over one additional
5937 instruction if the delay slot is filled. If the delay slot
5938 is empty, the instruction after the reversed condition branch
5939 must be nullified. */
5940 nullify = dbr_sequence_length () == 0;
5941 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
5943 /* Create a reversed conditional branch which branches around
5944 the following insns. */
5945 if (GET_MODE (operands[1]) != DImode)
5951 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
5954 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
5960 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
5963 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
5972 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
5975 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
5981 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
5984 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
5988 output_asm_insn (buf, xoperands);
5989 return output_lbranch (operands[0], insn);
5997 /* This routine handles long unconditional branches that exceed the
5998 maximum range of a simple branch instruction. */
6001 output_lbranch (rtx dest, rtx insn)
6005 xoperands[0] = dest;
6007 /* First, free up the delay slot. */
6008 if (dbr_sequence_length () != 0)
6010 /* We can't handle a jump in the delay slot. */
6011 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6013 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6016 /* Now delete the delay insn. */
6017 PUT_CODE (NEXT_INSN (insn), NOTE);
6018 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6019 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6022 /* Output an insn to save %r1. The runtime documentation doesn't
6023 specify whether the "Clean Up" slot in the callers frame can
6024 be clobbered by the callee. It isn't copied by HP's builtin
6025 alloca, so this suggests that it can be clobbered if necessary.
6026 The "Static Link" location is copied by HP builtin alloca, so
6027 we avoid using it. Using the cleanup slot might be a problem
6028 if we have to interoperate with languages that pass cleanup
6029 information. However, it should be possible to handle these
6030 situations with GCC's asm feature.
6032 The "Current RP" slot is reserved for the called procedure, so
6033 we try to use it when we don't have a frame of our own. It's
6034 rather unlikely that we won't have a frame when we need to emit
6037 Really the way to go long term is a register scavenger; goto
6038 the target of the jump and find a register which we can use
6039 as a scratch to hold the value in %r1. Then, we wouldn't have
6040 to free up the delay slot or clobber a slot that may be needed
6041 for other purposes. */
6044 if (actual_fsize == 0 && !regs_ever_live[2])
6045 /* Use the return pointer slot in the frame marker. */
6046 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6048 /* Use the slot at -40 in the frame marker since HP builtin
6049 alloca doesn't copy it. */
6050 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6054 if (actual_fsize == 0 && !regs_ever_live[2])
6055 /* Use the return pointer slot in the frame marker. */
6056 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6058 /* Use the "Clean Up" slot in the frame marker. In GCC,
6059 the only other use of this location is for copying a
6060 floating point double argument from a floating-point
6061 register to two general registers. The copy is done
6062 as an "atomic" operation when outputting a call, so it
6063 won't interfere with our using the location here. */
6064 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6067 if (TARGET_PORTABLE_RUNTIME)
6069 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6070 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6071 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6075 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6076 if (TARGET_SOM || !TARGET_GAS)
6078 xoperands[1] = gen_label_rtx ();
6079 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6080 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6081 CODE_LABEL_NUMBER (xoperands[1]));
6082 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6086 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6087 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6089 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6092 /* Now output a very long branch to the original target. */
6093 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6095 /* Now restore the value of %r1 in the delay slot. */
6098 if (actual_fsize == 0 && !regs_ever_live[2])
6099 return "ldd -16(%%r30),%%r1";
6101 return "ldd -40(%%r30),%%r1";
6105 if (actual_fsize == 0 && !regs_ever_live[2])
6106 return "ldw -20(%%r30),%%r1";
6108 return "ldw -12(%%r30),%%r1";
6112 /* This routine handles all the branch-on-bit conditional branch sequences we
6113 might need to generate. It handles nullification of delay slots,
6114 varying length branches, negated branches and all combinations of the
6115 above. it returns the appropriate output template to emit the branch. */
6118 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6119 int negated, rtx insn, int which)
6121 static char buf[100];
6124 /* A conditional branch to the following instruction (e.g. the delay slot) is
6125 asking for a disaster. I do not think this can happen as this pattern
6126 is only used when optimizing; jump optimization should eliminate the
6127 jump. But be prepared just in case. */
6129 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6132 /* If this is a long branch with its delay slot unfilled, set `nullify'
6133 as it can nullify the delay slot and save a nop. */
6134 if (length == 8 && dbr_sequence_length () == 0)
6137 /* If this is a short forward conditional branch which did not get
6138 its delay slot filled, the delay slot can still be nullified. */
6139 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6140 nullify = forward_branch_p (insn);
6142 /* A forward branch over a single nullified insn can be done with a
6143 extrs instruction. This avoids a single cycle penalty due to
6144 mis-predicted branch if we fall through (branch not taken). */
6147 && next_real_insn (insn) != 0
6148 && get_attr_length (next_real_insn (insn)) == 4
6149 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6156 /* All short conditional branches except backwards with an unfilled
6160 strcpy (buf, "{extrs,|extrw,s,}");
6162 strcpy (buf, "bb,");
6163 if (useskip && GET_MODE (operands[0]) == DImode)
6164 strcpy (buf, "extrd,s,*");
6165 else if (GET_MODE (operands[0]) == DImode)
6166 strcpy (buf, "bb,*");
6167 if ((which == 0 && negated)
6168 || (which == 1 && ! negated))
6173 strcat (buf, " %0,%1,1,%%r0");
6174 else if (nullify && negated)
6175 strcat (buf, ",n %0,%1,%3");
6176 else if (nullify && ! negated)
6177 strcat (buf, ",n %0,%1,%2");
6178 else if (! nullify && negated)
6179 strcat (buf, "%0,%1,%3");
6180 else if (! nullify && ! negated)
6181 strcat (buf, " %0,%1,%2");
6184 /* All long conditionals. Note a short backward branch with an
6185 unfilled delay slot is treated just like a long backward branch
6186 with an unfilled delay slot. */
6188 /* Handle weird backwards branch with a filled delay slot
6189 with is nullified. */
6190 if (dbr_sequence_length () != 0
6191 && ! forward_branch_p (insn)
6194 strcpy (buf, "bb,");
6195 if (GET_MODE (operands[0]) == DImode)
6197 if ((which == 0 && negated)
6198 || (which == 1 && ! negated))
6203 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6205 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6207 /* Handle short backwards branch with an unfilled delay slot.
6208 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6209 taken and untaken branches. */
6210 else if (dbr_sequence_length () == 0
6211 && ! forward_branch_p (insn)
6212 && INSN_ADDRESSES_SET_P ()
6213 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6214 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6216 strcpy (buf, "bb,");
6217 if (GET_MODE (operands[0]) == DImode)
6219 if ((which == 0 && negated)
6220 || (which == 1 && ! negated))
6225 strcat (buf, " %0,%1,%3%#");
6227 strcat (buf, " %0,%1,%2%#");
6231 strcpy (buf, "{extrs,|extrw,s,}");
6232 if (GET_MODE (operands[0]) == DImode)
6233 strcpy (buf, "extrd,s,*");
6234 if ((which == 0 && negated)
6235 || (which == 1 && ! negated))
6239 if (nullify && negated)
6240 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6241 else if (nullify && ! negated)
6242 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6244 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6246 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6256 /* This routine handles all the branch-on-variable-bit conditional branch
6257 sequences we might need to generate. It handles nullification of delay
6258 slots, varying length branches, negated branches and all combinations
6259 of the above. it returns the appropriate output template to emit the
6263 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6264 int negated, rtx insn, int which)
6266 static char buf[100];
6269 /* A conditional branch to the following instruction (e.g. the delay slot) is
6270 asking for a disaster. I do not think this can happen as this pattern
6271 is only used when optimizing; jump optimization should eliminate the
6272 jump. But be prepared just in case. */
6274 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6277 /* If this is a long branch with its delay slot unfilled, set `nullify'
6278 as it can nullify the delay slot and save a nop. */
6279 if (length == 8 && dbr_sequence_length () == 0)
6282 /* If this is a short forward conditional branch which did not get
6283 its delay slot filled, the delay slot can still be nullified. */
6284 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6285 nullify = forward_branch_p (insn);
6287 /* A forward branch over a single nullified insn can be done with a
6288 extrs instruction. This avoids a single cycle penalty due to
6289 mis-predicted branch if we fall through (branch not taken). */
6292 && next_real_insn (insn) != 0
6293 && get_attr_length (next_real_insn (insn)) == 4
6294 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6301 /* All short conditional branches except backwards with an unfilled
6305 strcpy (buf, "{vextrs,|extrw,s,}");
6307 strcpy (buf, "{bvb,|bb,}");
6308 if (useskip && GET_MODE (operands[0]) == DImode)
6309 strcpy (buf, "extrd,s,*");
6310 else if (GET_MODE (operands[0]) == DImode)
6311 strcpy (buf, "bb,*");
6312 if ((which == 0 && negated)
6313 || (which == 1 && ! negated))
6318 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6319 else if (nullify && negated)
6320 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6321 else if (nullify && ! negated)
6322 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6323 else if (! nullify && negated)
6324 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6325 else if (! nullify && ! negated)
6326 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6329 /* All long conditionals. Note a short backward branch with an
6330 unfilled delay slot is treated just like a long backward branch
6331 with an unfilled delay slot. */
6333 /* Handle weird backwards branch with a filled delay slot
6334 with is nullified. */
6335 if (dbr_sequence_length () != 0
6336 && ! forward_branch_p (insn)
6339 strcpy (buf, "{bvb,|bb,}");
6340 if (GET_MODE (operands[0]) == DImode)
6342 if ((which == 0 && negated)
6343 || (which == 1 && ! negated))
6348 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6350 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6352 /* Handle short backwards branch with an unfilled delay slot.
6353 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6354 taken and untaken branches. */
6355 else if (dbr_sequence_length () == 0
6356 && ! forward_branch_p (insn)
6357 && INSN_ADDRESSES_SET_P ()
6358 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6359 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6361 strcpy (buf, "{bvb,|bb,}");
6362 if (GET_MODE (operands[0]) == DImode)
6364 if ((which == 0 && negated)
6365 || (which == 1 && ! negated))
6370 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6372 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6376 strcpy (buf, "{vextrs,|extrw,s,}");
6377 if (GET_MODE (operands[0]) == DImode)
6378 strcpy (buf, "extrd,s,*");
6379 if ((which == 0 && negated)
6380 || (which == 1 && ! negated))
6384 if (nullify && negated)
6385 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6386 else if (nullify && ! negated)
6387 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6389 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6391 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6401 /* Return the output template for emitting a dbra type insn.
6403 Note it may perform some output operations on its own before
6404 returning the final output string. */
6406 output_dbra (rtx *operands, rtx insn, int which_alternative)
6409 /* A conditional branch to the following instruction (e.g. the delay slot) is
6410 asking for a disaster. Be prepared! */
6412 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6414 if (which_alternative == 0)
6415 return "ldo %1(%0),%0";
6416 else if (which_alternative == 1)
6418 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6419 output_asm_insn ("ldw -16(%%r30),%4", operands);
6420 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6421 return "{fldws|fldw} -16(%%r30),%0";
6425 output_asm_insn ("ldw %0,%4", operands);
6426 return "ldo %1(%4),%4\n\tstw %4,%0";
6430 if (which_alternative == 0)
6432 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6433 int length = get_attr_length (insn);
6435 /* If this is a long branch with its delay slot unfilled, set `nullify'
6436 as it can nullify the delay slot and save a nop. */
6437 if (length == 8 && dbr_sequence_length () == 0)
6440 /* If this is a short forward conditional branch which did not get
6441 its delay slot filled, the delay slot can still be nullified. */
6442 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6443 nullify = forward_branch_p (insn);
6449 return "addib,%C2,n %1,%0,%3";
6451 return "addib,%C2 %1,%0,%3";
6454 /* Handle weird backwards branch with a fulled delay slot
6455 which is nullified. */
6456 if (dbr_sequence_length () != 0
6457 && ! forward_branch_p (insn)
6459 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6460 /* Handle short backwards branch with an unfilled delay slot.
6461 Using a addb;nop rather than addi;bl saves 1 cycle for both
6462 taken and untaken branches. */
6463 else if (dbr_sequence_length () == 0
6464 && ! forward_branch_p (insn)
6465 && INSN_ADDRESSES_SET_P ()
6466 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6467 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6468 return "addib,%C2 %1,%0,%3%#";
6470 /* Handle normal cases. */
6472 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6474 return "addi,%N2 %1,%0,%0\n\tb %3";
6481 /* Deal with gross reload from FP register case. */
6482 else if (which_alternative == 1)
6484 /* Move loop counter from FP register to MEM then into a GR,
6485 increment the GR, store the GR into MEM, and finally reload
6486 the FP register from MEM from within the branch's delay slot. */
6487 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6489 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6490 if (get_attr_length (insn) == 24)
6491 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6493 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6495 /* Deal with gross reload from memory case. */
6498 /* Reload loop counter from memory, the store back to memory
6499 happens in the branch's delay slot. */
6500 output_asm_insn ("ldw %0,%4", operands);
6501 if (get_attr_length (insn) == 12)
6502 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6504 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6508 /* Return the output template for emitting a dbra type insn.
6510 Note it may perform some output operations on its own before
6511 returning the final output string. */
6513 output_movb (rtx *operands, rtx insn, int which_alternative,
6514 int reverse_comparison)
6517 /* A conditional branch to the following instruction (e.g. the delay slot) is
6518 asking for a disaster. Be prepared! */
6520 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6522 if (which_alternative == 0)
6523 return "copy %1,%0";
6524 else if (which_alternative == 1)
6526 output_asm_insn ("stw %1,-16(%%r30)", operands);
6527 return "{fldws|fldw} -16(%%r30),%0";
6529 else if (which_alternative == 2)
6535 /* Support the second variant. */
6536 if (reverse_comparison)
6537 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6539 if (which_alternative == 0)
6541 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6542 int length = get_attr_length (insn);
6544 /* If this is a long branch with its delay slot unfilled, set `nullify'
6545 as it can nullify the delay slot and save a nop. */
6546 if (length == 8 && dbr_sequence_length () == 0)
6549 /* If this is a short forward conditional branch which did not get
6550 its delay slot filled, the delay slot can still be nullified. */
6551 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6552 nullify = forward_branch_p (insn);
6558 return "movb,%C2,n %1,%0,%3";
6560 return "movb,%C2 %1,%0,%3";
6563 /* Handle weird backwards branch with a filled delay slot
6564 which is nullified. */
6565 if (dbr_sequence_length () != 0
6566 && ! forward_branch_p (insn)
6568 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6570 /* Handle short backwards branch with an unfilled delay slot.
6571 Using a movb;nop rather than or;bl saves 1 cycle for both
6572 taken and untaken branches. */
6573 else if (dbr_sequence_length () == 0
6574 && ! forward_branch_p (insn)
6575 && INSN_ADDRESSES_SET_P ()
6576 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6577 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6578 return "movb,%C2 %1,%0,%3%#";
6579 /* Handle normal cases. */
6581 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6583 return "or,%N2 %1,%%r0,%0\n\tb %3";
6589 /* Deal with gross reload from FP register case. */
6590 else if (which_alternative == 1)
6592 /* Move loop counter from FP register to MEM then into a GR,
6593 increment the GR, store the GR into MEM, and finally reload
6594 the FP register from MEM from within the branch's delay slot. */
6595 output_asm_insn ("stw %1,-16(%%r30)", operands);
6596 if (get_attr_length (insn) == 12)
6597 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6599 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6601 /* Deal with gross reload from memory case. */
6602 else if (which_alternative == 2)
6604 /* Reload loop counter from memory, the store back to memory
6605 happens in the branch's delay slot. */
6606 if (get_attr_length (insn) == 8)
6607 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6609 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6611 /* Handle SAR as a destination. */
6614 if (get_attr_length (insn) == 8)
6615 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6617 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6621 /* Copy any FP arguments in INSN into integer registers. */
6623 copy_fp_args (rtx insn)
6628 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6630 int arg_mode, regno;
6631 rtx use = XEXP (link, 0);
6633 if (! (GET_CODE (use) == USE
6634 && GET_CODE (XEXP (use, 0)) == REG
6635 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6638 arg_mode = GET_MODE (XEXP (use, 0));
6639 regno = REGNO (XEXP (use, 0));
6641 /* Is it a floating point register? */
6642 if (regno >= 32 && regno <= 39)
6644 /* Copy the FP register into an integer register via memory. */
6645 if (arg_mode == SFmode)
6647 xoperands[0] = XEXP (use, 0);
6648 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6649 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6650 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6654 xoperands[0] = XEXP (use, 0);
6655 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6656 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6657 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6658 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6664 /* Compute length of the FP argument copy sequence for INSN. */
6666 length_fp_args (rtx insn)
6671 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6673 int arg_mode, regno;
6674 rtx use = XEXP (link, 0);
6676 if (! (GET_CODE (use) == USE
6677 && GET_CODE (XEXP (use, 0)) == REG
6678 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6681 arg_mode = GET_MODE (XEXP (use, 0));
6682 regno = REGNO (XEXP (use, 0));
6684 /* Is it a floating point register? */
6685 if (regno >= 32 && regno <= 39)
6687 if (arg_mode == SFmode)
6697 /* Return the attribute length for the millicode call instruction INSN.
6698 The length must match the code generated by output_millicode_call.
6699 We include the delay slot in the returned length as it is better to
6700 over estimate the length than to under estimate it. */
6703 attr_length_millicode_call (rtx insn)
6705 unsigned long distance = -1;
6706 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6708 if (INSN_ADDRESSES_SET_P ())
6710 distance = (total + insn_current_reference_address (insn));
6711 if (distance < total)
6717 if (!TARGET_LONG_CALLS && distance < 7600000)
6722 else if (TARGET_PORTABLE_RUNTIME)
6726 if (!TARGET_LONG_CALLS && distance < 240000)
6729 if (TARGET_LONG_ABS_CALL && !flag_pic)
6736 /* INSN is a function call. It may have an unconditional jump
6739 CALL_DEST is the routine we are calling. */
6742 output_millicode_call (rtx insn, rtx call_dest)
6744 int attr_length = get_attr_length (insn);
6745 int seq_length = dbr_sequence_length ();
6750 xoperands[0] = call_dest;
6751 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6753 /* Handle the common case where we are sure that the branch will
6754 reach the beginning of the $CODE$ subspace. The within reach
6755 form of the $$sh_func_adrs call has a length of 28. Because
6756 it has an attribute type of multi, it never has a nonzero
6757 sequence length. The length of the $$sh_func_adrs is the same
6758 as certain out of reach PIC calls to other routines. */
6759 if (!TARGET_LONG_CALLS
6760 && ((seq_length == 0
6761 && (attr_length == 12
6762 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6763 || (seq_length != 0 && attr_length == 8)))
6765 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6771 /* It might seem that one insn could be saved by accessing
6772 the millicode function using the linkage table. However,
6773 this doesn't work in shared libraries and other dynamically
6774 loaded objects. Using a pc-relative sequence also avoids
6775 problems related to the implicit use of the gp register. */
6776 output_asm_insn ("b,l .+8,%%r1", xoperands);
6780 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6781 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6785 xoperands[1] = gen_label_rtx ();
6786 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6787 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6788 CODE_LABEL_NUMBER (xoperands[1]));
6789 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6792 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6794 else if (TARGET_PORTABLE_RUNTIME)
6796 /* Pure portable runtime doesn't allow be/ble; we also don't
6797 have PIC support in the assembler/linker, so this sequence
6800 /* Get the address of our target into %r1. */
6801 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6802 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6804 /* Get our return address into %r31. */
6805 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6806 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6808 /* Jump to our target address in %r1. */
6809 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6813 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6815 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6817 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6821 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6822 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6824 if (TARGET_SOM || !TARGET_GAS)
6826 /* The HP assembler can generate relocations for the
6827 difference of two symbols. GAS can do this for a
6828 millicode symbol but not an arbitrary external
6829 symbol when generating SOM output. */
6830 xoperands[1] = gen_label_rtx ();
6831 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6832 CODE_LABEL_NUMBER (xoperands[1]));
6833 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6834 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6838 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6839 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6843 /* Jump to our target address in %r1. */
6844 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6848 if (seq_length == 0)
6849 output_asm_insn ("nop", xoperands);
6851 /* We are done if there isn't a jump in the delay slot. */
6852 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6855 /* This call has an unconditional jump in its delay slot. */
6856 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6858 /* See if the return address can be adjusted. Use the containing
6859 sequence insn's address. */
6860 if (INSN_ADDRESSES_SET_P ())
6862 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6863 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6864 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6866 if (VAL_14_BITS_P (distance))
6868 xoperands[1] = gen_label_rtx ();
6869 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6870 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6871 CODE_LABEL_NUMBER (xoperands[1]));
6874 /* ??? This branch may not reach its target. */
6875 output_asm_insn ("nop\n\tb,n %0", xoperands);
6878 /* ??? This branch may not reach its target. */
6879 output_asm_insn ("nop\n\tb,n %0", xoperands);
6881 /* Delete the jump. */
6882 PUT_CODE (NEXT_INSN (insn), NOTE);
6883 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6884 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6889 /* Return the attribute length of the call instruction INSN. The SIBCALL
6890 flag indicates whether INSN is a regular call or a sibling call. The
6891 length returned must be longer than the code actually generated by
6892 output_call. Since branch shortening is done before delay branch
6893 sequencing, there is no way to determine whether or not the delay
6894 slot will be filled during branch shortening. Even when the delay
6895 slot is filled, we may have to add a nop if the delay slot contains
6896 a branch that can't reach its target. Thus, we always have to include
6897 the delay slot in the length estimate. This used to be done in
6898 pa_adjust_insn_length but we do it here now as some sequences always
6899 fill the delay slot and we can save four bytes in the estimate for
6903 attr_length_call (rtx insn, int sibcall)
6909 rtx pat = PATTERN (insn);
6910 unsigned long distance = -1;
6912 if (INSN_ADDRESSES_SET_P ())
6914 unsigned long total;
6916 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6917 distance = (total + insn_current_reference_address (insn));
6918 if (distance < total)
6922 /* Determine if this is a local call. */
6923 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
6924 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
6926 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
6928 call_decl = SYMBOL_REF_DECL (call_dest);
6929 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
6931 /* pc-relative branch. */
6932 if (!TARGET_LONG_CALLS
6933 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
6934 || distance < 240000))
6937 /* 64-bit plabel sequence. */
6938 else if (TARGET_64BIT && !local_call)
6939 length += sibcall ? 28 : 24;
6941 /* non-pic long absolute branch sequence. */
6942 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
6945 /* long pc-relative branch sequence. */
6946 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6947 || (TARGET_64BIT && !TARGET_GAS)
6948 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
6952 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
6956 /* 32-bit plabel sequence. */
6962 length += length_fp_args (insn);
6972 if (!TARGET_NO_SPACE_REGS)
6980 /* INSN is a function call. It may have an unconditional jump
6983 CALL_DEST is the routine we are calling. */
6986 output_call (rtx insn, rtx call_dest, int sibcall)
6988 int delay_insn_deleted = 0;
6989 int delay_slot_filled = 0;
6990 int seq_length = dbr_sequence_length ();
6991 tree call_decl = SYMBOL_REF_DECL (call_dest);
6992 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
6995 xoperands[0] = call_dest;
6997 /* Handle the common case where we're sure that the branch will reach
6998 the beginning of the "$CODE$" subspace. This is the beginning of
6999 the current function if we are in a named section. */
7000 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7002 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7003 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7007 if (TARGET_64BIT && !local_call)
7009 /* ??? As far as I can tell, the HP linker doesn't support the
7010 long pc-relative sequence described in the 64-bit runtime
7011 architecture. So, we use a slightly longer indirect call. */
7012 struct deferred_plabel *p = get_plabel (call_dest);
7014 xoperands[0] = p->internal_label;
7015 xoperands[1] = gen_label_rtx ();
7017 /* If this isn't a sibcall, we put the load of %r27 into the
7018 delay slot. We can't do this in a sibcall as we don't
7019 have a second call-clobbered scratch register available. */
7021 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7024 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7027 /* Now delete the delay insn. */
7028 PUT_CODE (NEXT_INSN (insn), NOTE);
7029 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7030 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7031 delay_insn_deleted = 1;
7034 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7035 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7036 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7040 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7041 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7042 output_asm_insn ("bve (%%r1)", xoperands);
7046 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7047 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7048 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7049 delay_slot_filled = 1;
7054 int indirect_call = 0;
7056 /* Emit a long call. There are several different sequences
7057 of increasing length and complexity. In most cases,
7058 they don't allow an instruction in the delay slot. */
7059 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7060 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7061 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7066 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7068 && (!TARGET_PA_20 || indirect_call))
7070 /* A non-jump insn in the delay slot. By definition we can
7071 emit this insn before the call (and in fact before argument
7073 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7076 /* Now delete the delay insn. */
7077 PUT_CODE (NEXT_INSN (insn), NOTE);
7078 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7079 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7080 delay_insn_deleted = 1;
7083 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7085 /* This is the best sequence for making long calls in
7086 non-pic code. Unfortunately, GNU ld doesn't provide
7087 the stub needed for external calls, and GAS's support
7088 for this with the SOM linker is buggy. It is safe
7089 to use this for local calls. */
7090 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7092 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7096 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7099 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7101 output_asm_insn ("copy %%r31,%%r2", xoperands);
7102 delay_slot_filled = 1;
7107 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7108 || (TARGET_64BIT && !TARGET_GAS))
7110 /* The HP assembler and linker can handle relocations
7111 for the difference of two symbols. GAS and the HP
7112 linker can't do this when one of the symbols is
7114 xoperands[1] = gen_label_rtx ();
7115 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7116 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7117 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7118 CODE_LABEL_NUMBER (xoperands[1]));
7119 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7121 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7123 /* GAS currently can't generate the relocations that
7124 are needed for the SOM linker under HP-UX using this
7125 sequence. The GNU linker doesn't generate the stubs
7126 that are needed for external calls on TARGET_ELF32
7127 with this sequence. For now, we have to use a
7128 longer plabel sequence when using GAS. */
7129 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7130 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7132 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7137 /* Emit a long plabel-based call sequence. This is
7138 essentially an inline implementation of $$dyncall.
7139 We don't actually try to call $$dyncall as this is
7140 as difficult as calling the function itself. */
7141 struct deferred_plabel *p = get_plabel (call_dest);
7143 xoperands[0] = p->internal_label;
7144 xoperands[1] = gen_label_rtx ();
7146 /* Since the call is indirect, FP arguments in registers
7147 need to be copied to the general registers. Then, the
7148 argument relocation stub will copy them back. */
7150 copy_fp_args (insn);
7154 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7155 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7156 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7160 output_asm_insn ("addil LR'%0-$global$,%%r27",
7162 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7166 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7167 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7168 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7169 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7171 if (!sibcall && !TARGET_PA_20)
7173 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7174 if (TARGET_NO_SPACE_REGS)
7175 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7177 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7184 output_asm_insn ("bve (%%r1)", xoperands);
7189 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7190 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7191 delay_slot_filled = 1;
7194 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7199 if (!TARGET_NO_SPACE_REGS)
7200 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7205 if (TARGET_NO_SPACE_REGS)
7206 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7208 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7212 if (TARGET_NO_SPACE_REGS)
7213 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7215 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7218 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7220 output_asm_insn ("copy %%r31,%%r2", xoperands);
7221 delay_slot_filled = 1;
7228 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7229 output_asm_insn ("nop", xoperands);
7231 /* We are done if there isn't a jump in the delay slot. */
7233 || delay_insn_deleted
7234 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7237 /* A sibcall should never have a branch in the delay slot. */
7238 gcc_assert (!sibcall);
7240 /* This call has an unconditional jump in its delay slot. */
7241 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7243 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7245 /* See if the return address can be adjusted. Use the containing
7246 sequence insn's address. */
7247 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7248 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7249 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7251 if (VAL_14_BITS_P (distance))
7253 xoperands[1] = gen_label_rtx ();
7254 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7255 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7256 CODE_LABEL_NUMBER (xoperands[1]));
7259 output_asm_insn ("nop\n\tb,n %0", xoperands);
7262 output_asm_insn ("b,n %0", xoperands);
7264 /* Delete the jump. */
7265 PUT_CODE (NEXT_INSN (insn), NOTE);
7266 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7267 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7272 /* Return the attribute length of the indirect call instruction INSN.
7273 The length must match the code generated by output_indirect call.
7274 The returned length includes the delay slot. Currently, the delay
7275 slot of an indirect call sequence is not exposed and it is used by
7276 the sequence itself. */
7279 attr_length_indirect_call (rtx insn)
7281 unsigned long distance = -1;
7282 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7284 if (INSN_ADDRESSES_SET_P ())
7286 distance = (total + insn_current_reference_address (insn));
7287 if (distance < total)
7294 if (TARGET_FAST_INDIRECT_CALLS
7295 || (!TARGET_PORTABLE_RUNTIME
7296 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7302 if (TARGET_PORTABLE_RUNTIME)
7305 /* Out of reach, can use ble. */
7310 output_indirect_call (rtx insn, rtx call_dest)
7316 xoperands[0] = call_dest;
7317 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7318 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7322 /* First the special case for kernels, level 0 systems, etc. */
7323 if (TARGET_FAST_INDIRECT_CALLS)
7324 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7326 /* Now the normal case -- we can reach $$dyncall directly or
7327 we're sure that we can get there via a long-branch stub.
7329 No need to check target flags as the length uniquely identifies
7330 the remaining cases. */
7331 if (attr_length_indirect_call (insn) == 8)
7333 /* The HP linker substitutes a BLE for millicode calls using
7334 the short PIC PCREL form. Thus, we must use %r31 as the
7335 link register when generating PA 1.x code. */
7337 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7339 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7342 /* Long millicode call, but we are not generating PIC or portable runtime
7344 if (attr_length_indirect_call (insn) == 12)
7345 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7347 /* Long millicode call for portable runtime. */
7348 if (attr_length_indirect_call (insn) == 20)
7349 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7351 /* We need a long PIC call to $$dyncall. */
7352 xoperands[0] = NULL_RTX;
7353 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7354 if (TARGET_SOM || !TARGET_GAS)
7356 xoperands[0] = gen_label_rtx ();
7357 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7358 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7359 CODE_LABEL_NUMBER (xoperands[0]));
7360 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7364 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7365 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7368 output_asm_insn ("blr %%r0,%%r2", xoperands);
7369 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7373 /* Return the total length of the save and restore instructions needed for
7374 the data linkage table pointer (i.e., the PIC register) across the call
7375 instruction INSN. No-return calls do not require a save and restore.
7376 In addition, we may be able to avoid the save and restore for calls
7377 within the same translation unit. */
7380 attr_length_save_restore_dltp (rtx insn)
7382 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7388 /* In HPUX 8.0's shared library scheme, special relocations are needed
7389 for function labels if they might be passed to a function
7390 in a shared library (because shared libraries don't live in code
7391 space), and special magic is needed to construct their address. */
7394 hppa_encode_label (rtx sym)
7396 const char *str = XSTR (sym, 0);
7397 int len = strlen (str) + 1;
7400 p = newstr = alloca (len + 1);
7404 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7408 pa_encode_section_info (tree decl, rtx rtl, int first)
7410 if (first && TEXT_SPACE_P (decl))
7412 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7413 if (TREE_CODE (decl) == FUNCTION_DECL)
7414 hppa_encode_label (XEXP (rtl, 0));
7418 /* This is sort of inverse to pa_encode_section_info. */
7421 pa_strip_name_encoding (const char *str)
7423 str += (*str == '@');
7424 str += (*str == '*');
7429 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7431 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7434 /* Returns 1 if OP is a function label involved in a simple addition
7435 with a constant. Used to keep certain patterns from matching
7436 during instruction combination. */
7438 is_function_label_plus_const (rtx op)
7440 /* Strip off any CONST. */
7441 if (GET_CODE (op) == CONST)
7444 return (GET_CODE (op) == PLUS
7445 && function_label_operand (XEXP (op, 0), Pmode)
7446 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7449 /* Output assembly code for a thunk to FUNCTION. */
7452 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7453 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7456 static unsigned int current_thunk_number;
7457 int val_14 = VAL_14_BITS_P (delta);
7462 xoperands[0] = XEXP (DECL_RTL (function), 0);
7463 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7464 xoperands[2] = GEN_INT (delta);
7466 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7467 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7469 /* Output the thunk. We know that the function is in the same
7470 translation unit (i.e., the same space) as the thunk, and that
7471 thunks are output after their method. Thus, we don't need an
7472 external branch to reach the function. With SOM and GAS,
7473 functions and thunks are effectively in different sections.
7474 Thus, we can always use a IA-relative branch and the linker
7475 will add a long branch stub if necessary.
7477 However, we have to be careful when generating PIC code on the
7478 SOM port to ensure that the sequence does not transfer to an
7479 import stub for the target function as this could clobber the
7480 return value saved at SP-24. This would also apply to the
7481 32-bit linux port if the multi-space model is implemented. */
7482 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7483 && !(flag_pic && TREE_PUBLIC (function))
7484 && (TARGET_GAS || last_address < 262132))
7485 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7486 && ((targetm.have_named_sections
7487 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7488 /* The GNU 64-bit linker has rather poor stub management.
7489 So, we use a long branch from thunks that aren't in
7490 the same section as the target function. */
7492 && (DECL_SECTION_NAME (thunk_fndecl)
7493 != DECL_SECTION_NAME (function)))
7494 || ((DECL_SECTION_NAME (thunk_fndecl)
7495 == DECL_SECTION_NAME (function))
7496 && last_address < 262132)))
7497 || (!targetm.have_named_sections && last_address < 262132))))
7500 output_asm_insn ("addil L'%2,%%r26", xoperands);
7502 output_asm_insn ("b %0", xoperands);
7506 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7511 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7515 else if (TARGET_64BIT)
7517 /* We only have one call-clobbered scratch register, so we can't
7518 make use of the delay slot if delta doesn't fit in 14 bits. */
7521 output_asm_insn ("addil L'%2,%%r26", xoperands);
7522 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7525 output_asm_insn ("b,l .+8,%%r1", xoperands);
7529 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7530 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7534 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7535 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7540 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7541 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7546 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7550 else if (TARGET_PORTABLE_RUNTIME)
7552 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7553 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7556 output_asm_insn ("addil L'%2,%%r26", xoperands);
7558 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7562 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7567 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7571 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7573 /* The function is accessible from outside this module. The only
7574 way to avoid an import stub between the thunk and function is to
7575 call the function directly with an indirect sequence similar to
7576 that used by $$dyncall. This is possible because $$dyncall acts
7577 as the import stub in an indirect call. */
7578 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7579 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7580 output_asm_insn ("addil LT'%3,%%r19", xoperands);
7581 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
7582 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7583 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
7584 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
7585 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
7586 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7590 output_asm_insn ("addil L'%2,%%r26", xoperands);
7596 output_asm_insn ("bve (%%r22)", xoperands);
7599 else if (TARGET_NO_SPACE_REGS)
7601 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
7606 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
7607 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
7608 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
7613 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7615 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7619 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7621 if (TARGET_SOM || !TARGET_GAS)
7623 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
7624 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
7628 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7629 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
7633 output_asm_insn ("addil L'%2,%%r26", xoperands);
7635 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7639 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7644 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7651 output_asm_insn ("addil L'%2,%%r26", xoperands);
7653 output_asm_insn ("ldil L'%0,%%r22", xoperands);
7654 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
7658 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7663 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7668 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7670 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7673 output_asm_insn (".align 4", xoperands);
7674 ASM_OUTPUT_LABEL (file, label);
7675 output_asm_insn (".word P'%0", xoperands);
7677 else if (TARGET_SOM && TARGET_GAS)
7680 current_thunk_number++;
7681 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7682 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7683 last_address += nbytes;
7684 update_total_code_bytes (nbytes);
7687 /* Only direct calls to static functions are allowed to be sibling (tail)
7690 This restriction is necessary because some linker generated stubs will
7691 store return pointers into rp' in some cases which might clobber a
7692 live value already in rp'.
7694 In a sibcall the current function and the target function share stack
7695 space. Thus if the path to the current function and the path to the
7696 target function save a value in rp', they save the value into the
7697 same stack slot, which has undesirable consequences.
7699 Because of the deferred binding nature of shared libraries any function
7700 with external scope could be in a different load module and thus require
7701 rp' to be saved when calling that function. So sibcall optimizations
7702 can only be safe for static function.
7704 Note that GCC never needs return value relocations, so we don't have to
7705 worry about static calls with return value relocations (which require
7708 It is safe to perform a sibcall optimization when the target function
7709 will never return. */
7711 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7713 if (TARGET_PORTABLE_RUNTIME)
7716 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7717 single subspace mode and the call is not indirect. As far as I know,
7718 there is no operating system support for the multiple subspace mode.
7719 It might be possible to support indirect calls if we didn't use
7720 $$dyncall (see the indirect sequence generated in output_call). */
7722 return (decl != NULL_TREE);
7724 /* Sibcalls are not ok because the arg pointer register is not a fixed
7725 register. This prevents the sibcall optimization from occurring. In
7726 addition, there are problems with stub placement using GNU ld. This
7727 is because a normal sibcall branch uses a 17-bit relocation while
7728 a regular call branch uses a 22-bit relocation. As a result, more
7729 care needs to be taken in the placement of long-branch stubs. */
7733 /* Sibcalls are only ok within a translation unit. */
7734 return (decl && !TREE_PUBLIC (decl));
7737 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7738 use in fmpyadd instructions. */
7740 fmpyaddoperands (rtx *operands)
7742 enum machine_mode mode = GET_MODE (operands[0]);
7744 /* Must be a floating point mode. */
7745 if (mode != SFmode && mode != DFmode)
7748 /* All modes must be the same. */
7749 if (! (mode == GET_MODE (operands[1])
7750 && mode == GET_MODE (operands[2])
7751 && mode == GET_MODE (operands[3])
7752 && mode == GET_MODE (operands[4])
7753 && mode == GET_MODE (operands[5])))
7756 /* All operands must be registers. */
7757 if (! (GET_CODE (operands[1]) == REG
7758 && GET_CODE (operands[2]) == REG
7759 && GET_CODE (operands[3]) == REG
7760 && GET_CODE (operands[4]) == REG
7761 && GET_CODE (operands[5]) == REG))
7764 /* Only 2 real operands to the addition. One of the input operands must
7765 be the same as the output operand. */
7766 if (! rtx_equal_p (operands[3], operands[4])
7767 && ! rtx_equal_p (operands[3], operands[5]))
7770 /* Inout operand of add cannot conflict with any operands from multiply. */
7771 if (rtx_equal_p (operands[3], operands[0])
7772 || rtx_equal_p (operands[3], operands[1])
7773 || rtx_equal_p (operands[3], operands[2]))
7776 /* multiply cannot feed into addition operands. */
7777 if (rtx_equal_p (operands[4], operands[0])
7778 || rtx_equal_p (operands[5], operands[0]))
7781 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7783 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7784 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7785 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7786 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7787 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7788 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7791 /* Passed. Operands are suitable for fmpyadd. */
7795 #if !defined(USE_COLLECT2)
7797 pa_asm_out_constructor (rtx symbol, int priority)
7799 if (!function_label_operand (symbol, VOIDmode))
7800 hppa_encode_label (symbol);
7802 #ifdef CTORS_SECTION_ASM_OP
7803 default_ctor_section_asm_out_constructor (symbol, priority);
7805 # ifdef TARGET_ASM_NAMED_SECTION
7806 default_named_section_asm_out_constructor (symbol, priority);
7808 default_stabs_asm_out_constructor (symbol, priority);
7814 pa_asm_out_destructor (rtx symbol, int priority)
7816 if (!function_label_operand (symbol, VOIDmode))
7817 hppa_encode_label (symbol);
7819 #ifdef DTORS_SECTION_ASM_OP
7820 default_dtor_section_asm_out_destructor (symbol, priority);
7822 # ifdef TARGET_ASM_NAMED_SECTION
7823 default_named_section_asm_out_destructor (symbol, priority);
7825 default_stabs_asm_out_destructor (symbol, priority);
7831 /* This function places uninitialized global data in the bss section.
7832 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
7833 function on the SOM port to prevent uninitialized global data from
7834 being placed in the data section. */
7837 pa_asm_output_aligned_bss (FILE *stream,
7839 unsigned HOST_WIDE_INT size,
7843 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7845 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7846 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7849 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7850 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7853 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7854 ASM_OUTPUT_LABEL (stream, name);
7855 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
7858 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
7859 that doesn't allow the alignment of global common storage to be directly
7860 specified. The SOM linker aligns common storage based on the rounded
7861 value of the NUM_BYTES parameter in the .comm directive. It's not
7862 possible to use the .align directive as it doesn't affect the alignment
7863 of the label associated with a .comm directive. */
7866 pa_asm_output_aligned_common (FILE *stream,
7868 unsigned HOST_WIDE_INT size,
7871 unsigned int max_common_align;
7873 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
7874 if (align > max_common_align)
7876 warning ("alignment (%u) for %s exceeds maximum alignment "
7877 "for global common data. Using %u",
7878 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
7879 align = max_common_align;
7884 assemble_name (stream, name);
7885 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
7886 MAX (size, align / BITS_PER_UNIT));
7889 /* We can't use .comm for local common storage as the SOM linker effectively
7890 treats the symbol as universal and uses the same storage for local symbols
7891 with the same name in different object files. The .block directive
7892 reserves an uninitialized block of storage. However, it's not common
7893 storage. Fortunately, GCC never requests common storage with the same
7894 name in any given translation unit. */
7897 pa_asm_output_aligned_local (FILE *stream,
7899 unsigned HOST_WIDE_INT size,
7903 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7906 fprintf (stream, "%s", LOCAL_ASM_OP);
7907 assemble_name (stream, name);
7908 fprintf (stream, "\n");
7911 ASM_OUTPUT_LABEL (stream, name);
7912 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
7915 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7916 use in fmpysub instructions. */
7918 fmpysuboperands (rtx *operands)
7920 enum machine_mode mode = GET_MODE (operands[0]);
7922 /* Must be a floating point mode. */
7923 if (mode != SFmode && mode != DFmode)
7926 /* All modes must be the same. */
7927 if (! (mode == GET_MODE (operands[1])
7928 && mode == GET_MODE (operands[2])
7929 && mode == GET_MODE (operands[3])
7930 && mode == GET_MODE (operands[4])
7931 && mode == GET_MODE (operands[5])))
7934 /* All operands must be registers. */
7935 if (! (GET_CODE (operands[1]) == REG
7936 && GET_CODE (operands[2]) == REG
7937 && GET_CODE (operands[3]) == REG
7938 && GET_CODE (operands[4]) == REG
7939 && GET_CODE (operands[5]) == REG))
7942 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
7943 operation, so operands[4] must be the same as operand[3]. */
7944 if (! rtx_equal_p (operands[3], operands[4]))
7947 /* multiply cannot feed into subtraction. */
7948 if (rtx_equal_p (operands[5], operands[0]))
7951 /* Inout operand of sub cannot conflict with any operands from multiply. */
7952 if (rtx_equal_p (operands[3], operands[0])
7953 || rtx_equal_p (operands[3], operands[1])
7954 || rtx_equal_p (operands[3], operands[2]))
7957 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7959 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7960 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7961 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7962 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7963 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7964 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7967 /* Passed. Operands are suitable for fmpysub. */
7971 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
7972 constants for shadd instructions. */
7974 shadd_constant_p (int val)
7976 if (val == 2 || val == 4 || val == 8)
7982 /* Return 1 if OP is valid as a base or index register in a
7986 borx_reg_operand (rtx op, enum machine_mode mode)
7988 if (GET_CODE (op) != REG)
7991 /* We must reject virtual registers as the only expressions that
7992 can be instantiated are REG and REG+CONST. */
7993 if (op == virtual_incoming_args_rtx
7994 || op == virtual_stack_vars_rtx
7995 || op == virtual_stack_dynamic_rtx
7996 || op == virtual_outgoing_args_rtx
7997 || op == virtual_cfa_rtx)
8000 /* While it's always safe to index off the frame pointer, it's not
8001 profitable to do so when the frame pointer is being eliminated. */
8002 if (!reload_completed
8003 && flag_omit_frame_pointer
8004 && !current_function_calls_alloca
8005 && op == frame_pointer_rtx)
8008 return register_operand (op, mode);
8011 /* Return 1 if this operand is anything other than a hard register. */
8014 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8016 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8019 /* Return 1 if INSN branches forward. Should be using insn_addresses
8020 to avoid walking through all the insns... */
8022 forward_branch_p (rtx insn)
8024 rtx label = JUMP_LABEL (insn);
8031 insn = NEXT_INSN (insn);
8034 return (insn == label);
8037 /* Return 1 if OP is an equality comparison, else return 0. */
8039 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8041 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8044 /* Return 1 if INSN is in the delay slot of a call instruction. */
8046 jump_in_call_delay (rtx insn)
8049 if (GET_CODE (insn) != JUMP_INSN)
8052 if (PREV_INSN (insn)
8053 && PREV_INSN (PREV_INSN (insn))
8054 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8056 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8058 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8059 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8066 /* Output an unconditional move and branch insn. */
8069 output_parallel_movb (rtx *operands, int length)
8071 /* These are the cases in which we win. */
8073 return "mov%I1b,tr %1,%0,%2";
8075 /* None of these cases wins, but they don't lose either. */
8076 if (dbr_sequence_length () == 0)
8078 /* Nothing in the delay slot, fake it by putting the combined
8079 insn (the copy or add) in the delay slot of a bl. */
8080 if (GET_CODE (operands[1]) == CONST_INT)
8081 return "b %2\n\tldi %1,%0";
8083 return "b %2\n\tcopy %1,%0";
8087 /* Something in the delay slot, but we've got a long branch. */
8088 if (GET_CODE (operands[1]) == CONST_INT)
8089 return "ldi %1,%0\n\tb %2";
8091 return "copy %1,%0\n\tb %2";
8095 /* Output an unconditional add and branch insn. */
8098 output_parallel_addb (rtx *operands, int length)
8100 /* To make life easy we want operand0 to be the shared input/output
8101 operand and operand1 to be the readonly operand. */
8102 if (operands[0] == operands[1])
8103 operands[1] = operands[2];
8105 /* These are the cases in which we win. */
8107 return "add%I1b,tr %1,%0,%3";
8109 /* None of these cases win, but they don't lose either. */
8110 if (dbr_sequence_length () == 0)
8112 /* Nothing in the delay slot, fake it by putting the combined
8113 insn (the copy or add) in the delay slot of a bl. */
8114 return "b %3\n\tadd%I1 %1,%0,%0";
8118 /* Something in the delay slot, but we've got a long branch. */
8119 return "add%I1 %1,%0,%0\n\tb %3";
8123 /* Return nonzero if INSN (a jump insn) immediately follows a call
8124 to a named function. This is used to avoid filling the delay slot
8125 of the jump since it can usually be eliminated by modifying RP in
8126 the delay slot of the call. */
8129 following_call (rtx insn)
8131 if (! TARGET_JUMP_IN_DELAY)
8134 /* Find the previous real insn, skipping NOTEs. */
8135 insn = PREV_INSN (insn);
8136 while (insn && GET_CODE (insn) == NOTE)
8137 insn = PREV_INSN (insn);
8139 /* Check for CALL_INSNs and millicode calls. */
8141 && ((GET_CODE (insn) == CALL_INSN
8142 && get_attr_type (insn) != TYPE_DYNCALL)
8143 || (GET_CODE (insn) == INSN
8144 && GET_CODE (PATTERN (insn)) != SEQUENCE
8145 && GET_CODE (PATTERN (insn)) != USE
8146 && GET_CODE (PATTERN (insn)) != CLOBBER
8147 && get_attr_type (insn) == TYPE_MILLI)))
8153 /* We use this hook to perform a PA specific optimization which is difficult
8154 to do in earlier passes.
8156 We want the delay slots of branches within jump tables to be filled.
8157 None of the compiler passes at the moment even has the notion that a
8158 PA jump table doesn't contain addresses, but instead contains actual
8161 Because we actually jump into the table, the addresses of each entry
8162 must stay constant in relation to the beginning of the table (which
8163 itself must stay constant relative to the instruction to jump into
8164 it). I don't believe we can guarantee earlier passes of the compiler
8165 will adhere to those rules.
8167 So, late in the compilation process we find all the jump tables, and
8168 expand them into real code -- e.g. each entry in the jump table vector
8169 will get an appropriate label followed by a jump to the final target.
8171 Reorg and the final jump pass can then optimize these branches and
8172 fill their delay slots. We end up with smaller, more efficient code.
8174 The jump instructions within the table are special; we must be able
8175 to identify them during assembly output (if the jumps don't get filled
8176 we need to emit a nop rather than nullifying the delay slot)). We
8177 identify jumps in switch tables by using insns with the attribute
8178 type TYPE_BTABLE_BRANCH.
8180 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8181 insns. This serves two purposes, first it prevents jump.c from
8182 noticing that the last N entries in the table jump to the instruction
8183 immediately after the table and deleting the jumps. Second, those
8184 insns mark where we should emit .begin_brtab and .end_brtab directives
8185 when using GAS (allows for better link time optimizations). */
8192 remove_useless_addtr_insns (1);
8194 if (pa_cpu < PROCESSOR_8000)
8195 pa_combine_instructions ();
8198 /* This is fairly cheap, so always run it if optimizing. */
8199 if (optimize > 0 && !TARGET_BIG_SWITCH)
8201 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8202 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8204 rtx pattern, tmp, location, label;
8205 unsigned int length, i;
8207 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8208 if (GET_CODE (insn) != JUMP_INSN
8209 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8210 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8213 /* Emit marker for the beginning of the branch table. */
8214 emit_insn_before (gen_begin_brtab (), insn);
8216 pattern = PATTERN (insn);
8217 location = PREV_INSN (insn);
8218 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8220 for (i = 0; i < length; i++)
8222 /* Emit a label before each jump to keep jump.c from
8223 removing this code. */
8224 tmp = gen_label_rtx ();
8225 LABEL_NUSES (tmp) = 1;
8226 emit_label_after (tmp, location);
8227 location = NEXT_INSN (location);
8229 if (GET_CODE (pattern) == ADDR_VEC)
8230 label = XEXP (XVECEXP (pattern, 0, i), 0);
8232 label = XEXP (XVECEXP (pattern, 1, i), 0);
8234 tmp = gen_short_jump (label);
8236 /* Emit the jump itself. */
8237 tmp = emit_jump_insn_after (tmp, location);
8238 JUMP_LABEL (tmp) = label;
8239 LABEL_NUSES (label)++;
8240 location = NEXT_INSN (location);
8242 /* Emit a BARRIER after the jump. */
8243 emit_barrier_after (location);
8244 location = NEXT_INSN (location);
8247 /* Emit marker for the end of the branch table. */
8248 emit_insn_before (gen_end_brtab (), location);
8249 location = NEXT_INSN (location);
8250 emit_barrier_after (location);
8252 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8258 /* Still need brtab marker insns. FIXME: the presence of these
8259 markers disables output of the branch table to readonly memory,
8260 and any alignment directives that might be needed. Possibly,
8261 the begin_brtab insn should be output before the label for the
8262 table. This doesn't matter at the moment since the tables are
8263 always output in the text section. */
8264 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8266 /* Find an ADDR_VEC insn. */
8267 if (GET_CODE (insn) != JUMP_INSN
8268 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8269 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8272 /* Now generate markers for the beginning and end of the
8274 emit_insn_before (gen_begin_brtab (), insn);
8275 emit_insn_after (gen_end_brtab (), insn);
8280 /* The PA has a number of odd instructions which can perform multiple
8281 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8282 it may be profitable to combine two instructions into one instruction
8283 with two outputs. It's not profitable PA2.0 machines because the
8284 two outputs would take two slots in the reorder buffers.
8286 This routine finds instructions which can be combined and combines
8287 them. We only support some of the potential combinations, and we
8288 only try common ways to find suitable instructions.
8290 * addb can add two registers or a register and a small integer
8291 and jump to a nearby (+-8k) location. Normally the jump to the
8292 nearby location is conditional on the result of the add, but by
8293 using the "true" condition we can make the jump unconditional.
8294 Thus addb can perform two independent operations in one insn.
8296 * movb is similar to addb in that it can perform a reg->reg
8297 or small immediate->reg copy and jump to a nearby (+-8k location).
8299 * fmpyadd and fmpysub can perform a FP multiply and either an
8300 FP add or FP sub if the operands of the multiply and add/sub are
8301 independent (there are other minor restrictions). Note both
8302 the fmpy and fadd/fsub can in theory move to better spots according
8303 to data dependencies, but for now we require the fmpy stay at a
8306 * Many of the memory operations can perform pre & post updates
8307 of index registers. GCC's pre/post increment/decrement addressing
8308 is far too simple to take advantage of all the possibilities. This
8309 pass may not be suitable since those insns may not be independent.
8311 * comclr can compare two ints or an int and a register, nullify
8312 the following instruction and zero some other register. This
8313 is more difficult to use as it's harder to find an insn which
8314 will generate a comclr than finding something like an unconditional
8315 branch. (conditional moves & long branches create comclr insns).
8317 * Most arithmetic operations can conditionally skip the next
8318 instruction. They can be viewed as "perform this operation
8319 and conditionally jump to this nearby location" (where nearby
8320 is an insns away). These are difficult to use due to the
8321 branch length restrictions. */
8324 pa_combine_instructions (void)
8328 /* This can get expensive since the basic algorithm is on the
8329 order of O(n^2) (or worse). Only do it for -O2 or higher
8330 levels of optimization. */
8334 /* Walk down the list of insns looking for "anchor" insns which
8335 may be combined with "floating" insns. As the name implies,
8336 "anchor" instructions don't move, while "floating" insns may
8338 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8339 new = make_insn_raw (new);
8341 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8343 enum attr_pa_combine_type anchor_attr;
8344 enum attr_pa_combine_type floater_attr;
8346 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8347 Also ignore any special USE insns. */
8348 if ((GET_CODE (anchor) != INSN
8349 && GET_CODE (anchor) != JUMP_INSN
8350 && GET_CODE (anchor) != CALL_INSN)
8351 || GET_CODE (PATTERN (anchor)) == USE
8352 || GET_CODE (PATTERN (anchor)) == CLOBBER
8353 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8354 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8357 anchor_attr = get_attr_pa_combine_type (anchor);
8358 /* See if anchor is an insn suitable for combination. */
8359 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8360 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8361 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8362 && ! forward_branch_p (anchor)))
8366 for (floater = PREV_INSN (anchor);
8368 floater = PREV_INSN (floater))
8370 if (GET_CODE (floater) == NOTE
8371 || (GET_CODE (floater) == INSN
8372 && (GET_CODE (PATTERN (floater)) == USE
8373 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8376 /* Anything except a regular INSN will stop our search. */
8377 if (GET_CODE (floater) != INSN
8378 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8379 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8385 /* See if FLOATER is suitable for combination with the
8387 floater_attr = get_attr_pa_combine_type (floater);
8388 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8389 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8390 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8391 && floater_attr == PA_COMBINE_TYPE_FMPY))
8393 /* If ANCHOR and FLOATER can be combined, then we're
8394 done with this pass. */
8395 if (pa_can_combine_p (new, anchor, floater, 0,
8396 SET_DEST (PATTERN (floater)),
8397 XEXP (SET_SRC (PATTERN (floater)), 0),
8398 XEXP (SET_SRC (PATTERN (floater)), 1)))
8402 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8403 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8405 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8407 if (pa_can_combine_p (new, anchor, floater, 0,
8408 SET_DEST (PATTERN (floater)),
8409 XEXP (SET_SRC (PATTERN (floater)), 0),
8410 XEXP (SET_SRC (PATTERN (floater)), 1)))
8415 if (pa_can_combine_p (new, anchor, floater, 0,
8416 SET_DEST (PATTERN (floater)),
8417 SET_SRC (PATTERN (floater)),
8418 SET_SRC (PATTERN (floater))))
8424 /* If we didn't find anything on the backwards scan try forwards. */
8426 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8427 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8429 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8431 if (GET_CODE (floater) == NOTE
8432 || (GET_CODE (floater) == INSN
8433 && (GET_CODE (PATTERN (floater)) == USE
8434 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8438 /* Anything except a regular INSN will stop our search. */
8439 if (GET_CODE (floater) != INSN
8440 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8441 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8447 /* See if FLOATER is suitable for combination with the
8449 floater_attr = get_attr_pa_combine_type (floater);
8450 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8451 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8452 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8453 && floater_attr == PA_COMBINE_TYPE_FMPY))
8455 /* If ANCHOR and FLOATER can be combined, then we're
8456 done with this pass. */
8457 if (pa_can_combine_p (new, anchor, floater, 1,
8458 SET_DEST (PATTERN (floater)),
8459 XEXP (SET_SRC (PATTERN (floater)),
8461 XEXP (SET_SRC (PATTERN (floater)),
8468 /* FLOATER will be nonzero if we found a suitable floating
8469 insn for combination with ANCHOR. */
8471 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8472 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8474 /* Emit the new instruction and delete the old anchor. */
8475 emit_insn_before (gen_rtx_PARALLEL
8477 gen_rtvec (2, PATTERN (anchor),
8478 PATTERN (floater))),
8481 PUT_CODE (anchor, NOTE);
8482 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8483 NOTE_SOURCE_FILE (anchor) = 0;
8485 /* Emit a special USE insn for FLOATER, then delete
8486 the floating insn. */
8487 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8488 delete_insn (floater);
8493 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8496 /* Emit the new_jump instruction and delete the old anchor. */
8498 = emit_jump_insn_before (gen_rtx_PARALLEL
8500 gen_rtvec (2, PATTERN (anchor),
8501 PATTERN (floater))),
8504 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8505 PUT_CODE (anchor, NOTE);
8506 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8507 NOTE_SOURCE_FILE (anchor) = 0;
8509 /* Emit a special USE insn for FLOATER, then delete
8510 the floating insn. */
8511 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8512 delete_insn (floater);
8520 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8523 int insn_code_number;
8526 /* Create a PARALLEL with the patterns of ANCHOR and
8527 FLOATER, try to recognize it, then test constraints
8528 for the resulting pattern.
8530 If the pattern doesn't match or the constraints
8531 aren't met keep searching for a suitable floater
8533 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8534 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8535 INSN_CODE (new) = -1;
8536 insn_code_number = recog_memoized (new);
8537 if (insn_code_number < 0
8538 || (extract_insn (new), ! constrain_operands (1)))
8552 /* There's up to three operands to consider. One
8553 output and two inputs.
8555 The output must not be used between FLOATER & ANCHOR
8556 exclusive. The inputs must not be set between
8557 FLOATER and ANCHOR exclusive. */
8559 if (reg_used_between_p (dest, start, end))
8562 if (reg_set_between_p (src1, start, end))
8565 if (reg_set_between_p (src2, start, end))
8568 /* If we get here, then everything is good. */
8572 /* Return nonzero if references for INSN are delayed.
8574 Millicode insns are actually function calls with some special
8575 constraints on arguments and register usage.
8577 Millicode calls always expect their arguments in the integer argument
8578 registers, and always return their result in %r29 (ret1). They
8579 are expected to clobber their arguments, %r1, %r29, and the return
8580 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8582 This function tells reorg that the references to arguments and
8583 millicode calls do not appear to happen until after the millicode call.
8584 This allows reorg to put insns which set the argument registers into the
8585 delay slot of the millicode call -- thus they act more like traditional
8588 Note we cannot consider side effects of the insn to be delayed because
8589 the branch and link insn will clobber the return pointer. If we happened
8590 to use the return pointer in the delay slot of the call, then we lose.
8592 get_attr_type will try to recognize the given insn, so make sure to
8593 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8596 insn_refs_are_delayed (rtx insn)
8598 return ((GET_CODE (insn) == INSN
8599 && GET_CODE (PATTERN (insn)) != SEQUENCE
8600 && GET_CODE (PATTERN (insn)) != USE
8601 && GET_CODE (PATTERN (insn)) != CLOBBER
8602 && get_attr_type (insn) == TYPE_MILLI));
8605 /* On the HP-PA the value is found in register(s) 28(-29), unless
8606 the mode is SF or DF. Then the value is returned in fr4 (32).
8608 This must perform the same promotions as PROMOTE_MODE, else
8609 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8611 Small structures must be returned in a PARALLEL on PA64 in order
8612 to match the HP Compiler ABI. */
8615 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8617 enum machine_mode valmode;
8619 /* Aggregates with a size less than or equal to 128 bits are returned
8620 in GR 28(-29). They are left justified. The pad bits are undefined.
8621 Larger aggregates are returned in memory. */
8622 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8626 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8628 for (i = 0; i < ub; i++)
8630 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8631 gen_rtx_REG (DImode, 28 + i),
8636 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8639 if ((INTEGRAL_TYPE_P (valtype)
8640 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8641 || POINTER_TYPE_P (valtype))
8642 valmode = word_mode;
8644 valmode = TYPE_MODE (valtype);
8646 if (TREE_CODE (valtype) == REAL_TYPE
8647 && TYPE_MODE (valtype) != TFmode
8648 && !TARGET_SOFT_FLOAT)
8649 return gen_rtx_REG (valmode, 32);
8651 return gen_rtx_REG (valmode, 28);
8654 /* Return the location of a parameter that is passed in a register or NULL
8655 if the parameter has any component that is passed in memory.
8657 This is new code and will be pushed to into the net sources after
8660 ??? We might want to restructure this so that it looks more like other
8663 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8664 int named ATTRIBUTE_UNUSED)
8666 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8673 if (mode == VOIDmode)
8676 arg_size = FUNCTION_ARG_SIZE (mode, type);
8678 /* If this arg would be passed partially or totally on the stack, then
8679 this routine should return zero. pa_arg_partial_bytes will
8680 handle arguments which are split between regs and stack slots if
8681 the ABI mandates split arguments. */
8684 /* The 32-bit ABI does not split arguments. */
8685 if (cum->words + arg_size > max_arg_words)
8691 alignment = cum->words & 1;
8692 if (cum->words + alignment >= max_arg_words)
8696 /* The 32bit ABIs and the 64bit ABIs are rather different,
8697 particularly in their handling of FP registers. We might
8698 be able to cleverly share code between them, but I'm not
8699 going to bother in the hope that splitting them up results
8700 in code that is more easily understood. */
8704 /* Advance the base registers to their current locations.
8706 Remember, gprs grow towards smaller register numbers while
8707 fprs grow to higher register numbers. Also remember that
8708 although FP regs are 32-bit addressable, we pretend that
8709 the registers are 64-bits wide. */
8710 gpr_reg_base = 26 - cum->words;
8711 fpr_reg_base = 32 + cum->words;
8713 /* Arguments wider than one word and small aggregates need special
8717 || (type && AGGREGATE_TYPE_P (type)))
8719 /* Double-extended precision (80-bit), quad-precision (128-bit)
8720 and aggregates including complex numbers are aligned on
8721 128-bit boundaries. The first eight 64-bit argument slots
8722 are associated one-to-one, with general registers r26
8723 through r19, and also with floating-point registers fr4
8724 through fr11. Arguments larger than one word are always
8725 passed in general registers.
8727 Using a PARALLEL with a word mode register results in left
8728 justified data on a big-endian target. */
8731 int i, offset = 0, ub = arg_size;
8733 /* Align the base register. */
8734 gpr_reg_base -= alignment;
8736 ub = MIN (ub, max_arg_words - cum->words - alignment);
8737 for (i = 0; i < ub; i++)
8739 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8740 gen_rtx_REG (DImode, gpr_reg_base),
8746 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8751 /* If the argument is larger than a word, then we know precisely
8752 which registers we must use. */
8766 /* Structures 5 to 8 bytes in size are passed in the general
8767 registers in the same manner as other non floating-point
8768 objects. The data is right-justified and zero-extended
8769 to 64 bits. This is opposite to the normal justification
8770 used on big endian targets and requires special treatment.
8771 We now define BLOCK_REG_PADDING to pad these objects. */
8772 if (mode == BLKmode)
8774 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8775 gen_rtx_REG (DImode, gpr_reg_base),
8777 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8782 /* We have a single word (32 bits). A simple computation
8783 will get us the register #s we need. */
8784 gpr_reg_base = 26 - cum->words;
8785 fpr_reg_base = 32 + 2 * cum->words;
8789 /* Determine if the argument needs to be passed in both general and
8790 floating point registers. */
8791 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8792 /* If we are doing soft-float with portable runtime, then there
8793 is no need to worry about FP regs. */
8794 && !TARGET_SOFT_FLOAT
8795 /* The parameter must be some kind of float, else we can just
8796 pass it in integer registers. */
8797 && FLOAT_MODE_P (mode)
8798 /* The target function must not have a prototype. */
8799 && cum->nargs_prototype <= 0
8800 /* libcalls do not need to pass items in both FP and general
8802 && type != NULL_TREE
8803 /* All this hair applies to "outgoing" args only. This includes
8804 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8806 /* Also pass outgoing floating arguments in both registers in indirect
8807 calls with the 32 bit ABI and the HP assembler since there is no
8808 way to the specify argument locations in static functions. */
8813 && FLOAT_MODE_P (mode)))
8819 gen_rtx_EXPR_LIST (VOIDmode,
8820 gen_rtx_REG (mode, fpr_reg_base),
8822 gen_rtx_EXPR_LIST (VOIDmode,
8823 gen_rtx_REG (mode, gpr_reg_base),
8828 /* See if we should pass this parameter in a general register. */
8829 if (TARGET_SOFT_FLOAT
8830 /* Indirect calls in the normal 32bit ABI require all arguments
8831 to be passed in general registers. */
8832 || (!TARGET_PORTABLE_RUNTIME
8836 /* If the parameter is not a floating point parameter, then
8837 it belongs in GPRs. */
8838 || !FLOAT_MODE_P (mode))
8839 retval = gen_rtx_REG (mode, gpr_reg_base);
8841 retval = gen_rtx_REG (mode, fpr_reg_base);
8847 /* If this arg would be passed totally in registers or totally on the stack,
8848 then this routine should return zero. */
8851 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8852 tree type, bool named ATTRIBUTE_UNUSED)
8854 unsigned int max_arg_words = 8;
8855 unsigned int offset = 0;
8860 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8863 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8864 /* Arg fits fully into registers. */
8866 else if (cum->words + offset >= max_arg_words)
8867 /* Arg fully on the stack. */
8871 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
8875 /* Return a string to output before text in the current function.
8877 This function is only used with SOM. Because we don't support
8878 named subspaces, we can only create a new subspace or switch back
8879 to the default text subspace. */
8881 som_text_section_asm_op (void)
8888 if (cfun && !cfun->machine->in_nsubspa)
8890 /* We only want to emit a .nsubspa directive once at the
8891 start of the function. */
8892 cfun->machine->in_nsubspa = 1;
8894 /* Create a new subspace for the text. This provides
8895 better stub placement and one-only functions. */
8897 && DECL_ONE_ONLY (cfun->decl)
8898 && !DECL_WEAK (cfun->decl))
8900 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
8902 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
8906 /* There isn't a current function or the body of the current
8907 function has been completed. So, we are changing to the
8908 text section to output debugging information. Do this in
8909 the default text section. We need to forget that we are
8910 in the text section so that the function text_section in
8911 varasm.c will call us the next time around. */
8916 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
8919 /* On hpux10, the linker will give an error if we have a reference
8920 in the read-only data section to a symbol defined in a shared
8921 library. Therefore, expressions that might require a reloc can
8922 not be placed in the read-only data section. */
8925 pa_select_section (tree exp, int reloc,
8926 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
8928 if (TREE_CODE (exp) == VAR_DECL
8929 && TREE_READONLY (exp)
8930 && !TREE_THIS_VOLATILE (exp)
8931 && DECL_INITIAL (exp)
8932 && (DECL_INITIAL (exp) == error_mark_node
8933 || TREE_CONSTANT (DECL_INITIAL (exp)))
8937 && DECL_ONE_ONLY (exp)
8938 && !DECL_WEAK (exp))
8939 som_one_only_readonly_data_section ();
8941 readonly_data_section ();
8943 else if (CONSTANT_CLASS_P (exp) && !reloc)
8944 readonly_data_section ();
8946 && TREE_CODE (exp) == VAR_DECL
8947 && DECL_ONE_ONLY (exp)
8948 && !DECL_WEAK (exp))
8949 som_one_only_data_section ();
8955 pa_globalize_label (FILE *stream, const char *name)
8957 /* We only handle DATA objects here, functions are globalized in
8958 ASM_DECLARE_FUNCTION_NAME. */
8959 if (! FUNCTION_NAME_P (name))
8961 fputs ("\t.EXPORT ", stream);
8962 assemble_name (stream, name);
8963 fputs (",DATA\n", stream);
8967 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
8970 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
8971 int incoming ATTRIBUTE_UNUSED)
8973 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
8976 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8979 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
8981 /* SOM ABI says that objects larger than 64 bits are returned in memory.
8982 PA64 ABI says that objects larger than 128 bits are returned in memory.
8983 Note, int_size_in_bytes can return -1 if the size of the object is
8984 variable or larger than the maximum value that can be expressed as
8985 a HOST_WIDE_INT. It can also return zero for an empty type. The
8986 simplest way to handle variable and empty types is to pass them in
8987 memory. This avoids problems in defining the boundaries of argument
8988 slots, allocating registers, etc. */
8989 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
8990 || int_size_in_bytes (type) <= 0);
8993 /* Structure to hold declaration and name of external symbols that are
8994 emitted by GCC. We generate a vector of these symbols and output them
8995 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
8996 This avoids putting out names that are never really used. */
8998 typedef struct extern_symbol GTY(())
9004 /* Define gc'd vector type for extern_symbol. */
9005 DEF_VEC_O(extern_symbol);
9006 DEF_VEC_ALLOC_O(extern_symbol,gc);
9008 /* Vector of extern_symbol pointers. */
9009 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9011 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9012 /* Mark DECL (name NAME) as an external reference (assembler output
9013 file FILE). This saves the names to output at the end of the file
9014 if actually referenced. */
9017 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9019 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9021 gcc_assert (file == asm_out_file);
9026 /* Output text required at the end of an assembler file.
9027 This includes deferred plabels and .import directives for
9028 all external symbols that were actually referenced. */
9031 pa_hpux_file_end (void)
9036 output_deferred_plabels ();
9038 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9040 tree decl = p->decl;
9042 if (!TREE_ASM_WRITTEN (decl)
9043 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9044 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9047 VEC_free (extern_symbol, gc, extern_symbols);