1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "integrate.h"
52 #include "target-def.h"
54 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
56 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
57 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
60 hppa_use_dfa_pipeline_interface ()
65 /* Return nonzero if there is a bypass for the output of
66 OUT_INSN and the fp store IN_INSN. */
68 hppa_fpstore_bypass_p (out_insn, in_insn)
69 rtx out_insn, in_insn;
71 enum machine_mode store_mode;
72 enum machine_mode other_mode;
75 if (recog_memoized (in_insn) < 0
76 || get_attr_type (in_insn) != TYPE_FPSTORE
77 || recog_memoized (out_insn) < 0)
80 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
82 set = single_set (out_insn);
86 other_mode = GET_MODE (SET_SRC (set));
88 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
92 #ifndef DO_FRAME_NOTES
93 #ifdef INCOMING_RETURN_ADDR_RTX
94 #define DO_FRAME_NOTES 1
96 #define DO_FRAME_NOTES 0
100 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
101 static void pa_combine_instructions PARAMS ((rtx));
102 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
103 static int forward_branch_p PARAMS ((rtx));
104 static int shadd_constant_p PARAMS ((int));
105 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
106 static int compute_movstrsi_length PARAMS ((rtx));
107 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
108 static void remove_useless_addtr_insns PARAMS ((rtx, int));
109 static void store_reg PARAMS ((int, int, int));
110 static void store_reg_modify PARAMS ((int, int, int));
111 static void load_reg PARAMS ((int, int, int));
112 static void set_reg_plus_d PARAMS ((int, int, int, int));
113 static void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
114 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
115 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
116 static int pa_adjust_priority PARAMS ((rtx, int));
117 static int pa_issue_rate PARAMS ((void));
118 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
120 static void pa_encode_section_info PARAMS ((tree, int));
121 static const char *pa_strip_name_encoding PARAMS ((const char *));
122 static bool pa_function_ok_for_sibcall PARAMS ((tree, tree));
123 static void pa_globalize_label PARAMS ((FILE *, const char *))
125 static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
126 HOST_WIDE_INT, tree));
127 #if !defined(USE_COLLECT2)
128 static void pa_asm_out_constructor PARAMS ((rtx, int));
129 static void pa_asm_out_destructor PARAMS ((rtx, int));
131 static void copy_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
132 static int length_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
133 static struct deferred_plabel *get_plabel PARAMS ((const char *))
136 /* Save the operands last given to a compare for use when we
137 generate a scc or bcc insn. */
138 rtx hppa_compare_op0, hppa_compare_op1;
139 enum cmp_type hppa_branch_type;
141 /* Which cpu we are scheduling for. */
142 enum processor_type pa_cpu;
144 /* String to hold which cpu we are scheduling for. */
145 const char *pa_cpu_string;
147 /* Which architecture we are generating code for. */
148 enum architecture_type pa_arch;
150 /* String to hold which architecture we are generating code for. */
151 const char *pa_arch_string;
153 /* Counts for the number of callee-saved general and floating point
154 registers which were saved by the current function's prologue. */
155 static int gr_saved, fr_saved;
157 static rtx find_addr_reg PARAMS ((rtx));
159 /* Keep track of the number of bytes we have output in the CODE subspaces
160 during this compilation so we'll know when to emit inline long-calls. */
161 unsigned long total_code_bytes;
163 /* Variables to handle plabels that we discover are necessary at assembly
164 output time. They are output after the current function. */
165 struct deferred_plabel GTY(())
170 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
172 static size_t n_deferred_plabels = 0;
174 /* Initialize the GCC target structure. */
176 #undef TARGET_ASM_ALIGNED_HI_OP
177 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
178 #undef TARGET_ASM_ALIGNED_SI_OP
179 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
180 #undef TARGET_ASM_ALIGNED_DI_OP
181 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
182 #undef TARGET_ASM_UNALIGNED_HI_OP
183 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
184 #undef TARGET_ASM_UNALIGNED_SI_OP
185 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
186 #undef TARGET_ASM_UNALIGNED_DI_OP
187 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
188 #undef TARGET_ASM_INTEGER
189 #define TARGET_ASM_INTEGER pa_assemble_integer
191 #undef TARGET_ASM_FUNCTION_PROLOGUE
192 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
193 #undef TARGET_ASM_FUNCTION_EPILOGUE
194 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
196 #undef TARGET_SCHED_ADJUST_COST
197 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
198 #undef TARGET_SCHED_ADJUST_PRIORITY
199 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
200 #undef TARGET_SCHED_ISSUE_RATE
201 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
203 #undef TARGET_ENCODE_SECTION_INFO
204 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
205 #undef TARGET_STRIP_NAME_ENCODING
206 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
208 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
209 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
211 #undef TARGET_ASM_OUTPUT_MI_THUNK
212 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
213 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
214 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
216 #if !defined(USE_COLLECT2)
217 #undef TARGET_ASM_CONSTRUCTOR
218 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
219 #undef TARGET_ASM_DESTRUCTOR
220 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
223 struct gcc_target targetm = TARGET_INITIALIZER;
228 if (pa_cpu_string == NULL)
229 pa_cpu_string = TARGET_SCHED_DEFAULT;
231 if (! strcmp (pa_cpu_string, "8000"))
233 pa_cpu_string = "8000";
234 pa_cpu = PROCESSOR_8000;
236 else if (! strcmp (pa_cpu_string, "7100"))
238 pa_cpu_string = "7100";
239 pa_cpu = PROCESSOR_7100;
241 else if (! strcmp (pa_cpu_string, "700"))
243 pa_cpu_string = "700";
244 pa_cpu = PROCESSOR_700;
246 else if (! strcmp (pa_cpu_string, "7100LC"))
248 pa_cpu_string = "7100LC";
249 pa_cpu = PROCESSOR_7100LC;
251 else if (! strcmp (pa_cpu_string, "7200"))
253 pa_cpu_string = "7200";
254 pa_cpu = PROCESSOR_7200;
256 else if (! strcmp (pa_cpu_string, "7300"))
258 pa_cpu_string = "7300";
259 pa_cpu = PROCESSOR_7300;
263 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
266 /* Set the instruction set architecture. */
267 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
269 pa_arch_string = "1.0";
270 pa_arch = ARCHITECTURE_10;
271 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
273 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
275 pa_arch_string = "1.1";
276 pa_arch = ARCHITECTURE_11;
277 target_flags &= ~MASK_PA_20;
278 target_flags |= MASK_PA_11;
280 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
282 pa_arch_string = "2.0";
283 pa_arch = ARCHITECTURE_20;
284 target_flags |= MASK_PA_11 | MASK_PA_20;
286 else if (pa_arch_string)
288 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
291 /* Unconditional branches in the delay slot are not compatible with dwarf2
292 call frame information. There is no benefit in using this optimization
293 on PA8000 and later processors. */
294 if (pa_cpu >= PROCESSOR_8000
295 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
296 || flag_unwind_tables)
297 target_flags &= ~MASK_JUMP_IN_DELAY;
299 if (flag_pic && TARGET_PORTABLE_RUNTIME)
301 warning ("PIC code generation is not supported in the portable runtime model\n");
304 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
306 warning ("PIC code generation is not compatible with fast indirect calls\n");
309 if (! TARGET_GAS && write_symbols != NO_DEBUG)
311 warning ("-g is only supported when using GAS on this processor,");
312 warning ("-g option disabled");
313 write_symbols = NO_DEBUG;
316 /* We only support the "big PIC" model now. And we always generate PIC
317 code when in 64bit mode. */
318 if (flag_pic == 1 || TARGET_64BIT)
321 /* We can't guarantee that .dword is available for 32-bit targets. */
322 if (UNITS_PER_WORD == 4)
323 targetm.asm_out.aligned_op.di = NULL;
325 /* The unaligned ops are only available when using GAS. */
328 targetm.asm_out.unaligned_op.hi = NULL;
329 targetm.asm_out.unaligned_op.si = NULL;
330 targetm.asm_out.unaligned_op.di = NULL;
334 /* Return nonzero only if OP is a register of mode MODE,
337 reg_or_0_operand (op, mode)
339 enum machine_mode mode;
341 return (op == CONST0_RTX (mode) || register_operand (op, mode));
344 /* Return nonzero if OP is suitable for use in a call to a named
347 For 2.5 try to eliminate either call_operand_address or
348 function_label_operand, they perform very similar functions. */
350 call_operand_address (op, mode)
352 enum machine_mode mode ATTRIBUTE_UNUSED;
354 return (GET_MODE (op) == word_mode
355 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
358 /* Return 1 if X contains a symbolic expression. We know these
359 expressions will have one of a few well defined forms, so
360 we need only check those forms. */
362 symbolic_expression_p (x)
366 /* Strip off any HIGH. */
367 if (GET_CODE (x) == HIGH)
370 return (symbolic_operand (x, VOIDmode));
374 symbolic_operand (op, mode)
376 enum machine_mode mode ATTRIBUTE_UNUSED;
378 switch (GET_CODE (op))
385 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
386 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
387 && GET_CODE (XEXP (op, 1)) == CONST_INT);
393 /* Return truth value of statement that OP is a symbolic memory
394 operand of mode MODE. */
397 symbolic_memory_operand (op, mode)
399 enum machine_mode mode ATTRIBUTE_UNUSED;
401 if (GET_CODE (op) == SUBREG)
402 op = SUBREG_REG (op);
403 if (GET_CODE (op) != MEM)
406 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
407 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
410 /* Return 1 if the operand is either a register or a memory operand that is
414 reg_or_nonsymb_mem_operand (op, mode)
416 enum machine_mode mode;
418 if (register_operand (op, mode))
421 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
427 /* Return 1 if the operand is either a register, zero, or a memory operand
428 that is not symbolic. */
431 reg_or_0_or_nonsymb_mem_operand (op, mode)
433 enum machine_mode mode;
435 if (register_operand (op, mode))
438 if (op == CONST0_RTX (mode))
441 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
447 /* Return 1 if the operand is a register operand or a non-symbolic memory
448 operand after reload. This predicate is used for branch patterns that
449 internally handle register reloading. We need to accept non-symbolic
450 memory operands after reload to ensure that the pattern is still valid
451 if reload didn't find a hard register for the operand. */
454 reg_before_reload_operand (op, mode)
456 enum machine_mode mode;
458 /* Don't accept a SUBREG since it will need a reload. */
459 if (GET_CODE (op) == SUBREG)
462 if (register_operand (op, mode))
466 && memory_operand (op, mode)
467 && ! symbolic_memory_operand (op, mode))
473 /* Accept any constant that can be moved in one instruction into a
476 cint_ok_for_move (intval)
477 HOST_WIDE_INT intval;
479 /* OK if ldo, ldil, or zdepi, can be used. */
480 return (CONST_OK_FOR_LETTER_P (intval, 'J')
481 || CONST_OK_FOR_LETTER_P (intval, 'N')
482 || CONST_OK_FOR_LETTER_P (intval, 'K'));
485 /* Accept anything that can be moved in one instruction into a general
488 move_operand (op, mode)
490 enum machine_mode mode;
492 if (register_operand (op, mode))
495 if (GET_CODE (op) == CONSTANT_P_RTX)
498 if (GET_CODE (op) == CONST_INT)
499 return cint_ok_for_move (INTVAL (op));
501 if (GET_CODE (op) == SUBREG)
502 op = SUBREG_REG (op);
503 if (GET_CODE (op) != MEM)
508 /* We consider a LO_SUM DLT reference a move_operand now since it has
509 been merged into the normal movsi/movdi patterns. */
510 if (GET_CODE (op) == LO_SUM
511 && GET_CODE (XEXP (op, 0)) == REG
512 && REG_OK_FOR_BASE_P (XEXP (op, 0))
513 && GET_CODE (XEXP (op, 1)) == UNSPEC
514 && GET_MODE (op) == Pmode)
517 /* Since move_operand is only used for source operands, we can always
518 allow scaled indexing! */
519 if (! TARGET_DISABLE_INDEXING
520 && GET_CODE (op) == PLUS
521 && ((GET_CODE (XEXP (op, 0)) == MULT
522 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
523 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
524 && INTVAL (XEXP (XEXP (op, 0), 1))
525 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
526 && GET_CODE (XEXP (op, 1)) == REG)
527 || (GET_CODE (XEXP (op, 1)) == MULT
528 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
529 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
530 && INTVAL (XEXP (XEXP (op, 1), 1))
531 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
532 && GET_CODE (XEXP (op, 0)) == REG)))
535 return memory_address_p (mode, op);
538 /* Accept REG and any CONST_INT that can be moved in one instruction into a
541 reg_or_cint_move_operand (op, mode)
543 enum machine_mode mode;
545 if (register_operand (op, mode))
548 if (GET_CODE (op) == CONST_INT)
549 return cint_ok_for_move (INTVAL (op));
555 pic_label_operand (op, mode)
557 enum machine_mode mode ATTRIBUTE_UNUSED;
562 switch (GET_CODE (op))
568 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
569 && GET_CODE (XEXP (op, 1)) == CONST_INT);
576 fp_reg_operand (op, mode)
578 enum machine_mode mode ATTRIBUTE_UNUSED;
580 return reg_renumber && FP_REG_P (op);
585 /* Return truth value of whether OP can be used as an operand in a
586 three operand arithmetic insn that accepts registers of mode MODE
587 or 14-bit signed integers. */
589 arith_operand (op, mode)
591 enum machine_mode mode;
593 return (register_operand (op, mode)
594 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
597 /* Return truth value of whether OP can be used as an operand in a
598 three operand arithmetic insn that accepts registers of mode MODE
599 or 11-bit signed integers. */
601 arith11_operand (op, mode)
603 enum machine_mode mode;
605 return (register_operand (op, mode)
606 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
609 /* Return truth value of whether OP can be used as an operand in a
612 adddi3_operand (op, mode)
614 enum machine_mode mode;
616 return (register_operand (op, mode)
617 || (GET_CODE (op) == CONST_INT
618 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
621 /* A constant integer suitable for use in a PRE_MODIFY memory
624 pre_cint_operand (op, mode)
626 enum machine_mode mode ATTRIBUTE_UNUSED;
628 return (GET_CODE (op) == CONST_INT
629 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
632 /* A constant integer suitable for use in a POST_MODIFY memory
635 post_cint_operand (op, mode)
637 enum machine_mode mode ATTRIBUTE_UNUSED;
639 return (GET_CODE (op) == CONST_INT
640 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
644 arith_double_operand (op, mode)
646 enum machine_mode mode;
648 return (register_operand (op, mode)
649 || (GET_CODE (op) == CONST_DOUBLE
650 && GET_MODE (op) == mode
651 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
652 && ((CONST_DOUBLE_HIGH (op) >= 0)
653 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
656 /* Return truth value of whether OP is an integer which fits the
657 range constraining immediate operands in three-address insns, or
658 is an integer register. */
661 ireg_or_int5_operand (op, mode)
663 enum machine_mode mode ATTRIBUTE_UNUSED;
665 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
666 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
669 /* Return nonzero if OP is an integer register, else return zero. */
671 ireg_operand (op, mode)
673 enum machine_mode mode ATTRIBUTE_UNUSED;
675 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
678 /* Return truth value of whether OP is an integer which fits the
679 range constraining immediate operands in three-address insns. */
682 int5_operand (op, mode)
684 enum machine_mode mode ATTRIBUTE_UNUSED;
686 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
690 uint5_operand (op, mode)
692 enum machine_mode mode ATTRIBUTE_UNUSED;
694 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
698 int11_operand (op, mode)
700 enum machine_mode mode ATTRIBUTE_UNUSED;
702 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
706 uint32_operand (op, mode)
708 enum machine_mode mode ATTRIBUTE_UNUSED;
710 #if HOST_BITS_PER_WIDE_INT > 32
711 /* All allowed constants will fit a CONST_INT. */
712 return (GET_CODE (op) == CONST_INT
713 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
715 return (GET_CODE (op) == CONST_INT
716 || (GET_CODE (op) == CONST_DOUBLE
717 && CONST_DOUBLE_HIGH (op) == 0));
722 arith5_operand (op, mode)
724 enum machine_mode mode;
726 return register_operand (op, mode) || int5_operand (op, mode);
729 /* True iff zdepi can be used to generate this CONST_INT.
730 zdepi first sign extends a 5 bit signed number to a given field
731 length, then places this field anywhere in a zero. */
734 unsigned HOST_WIDE_INT x;
736 unsigned HOST_WIDE_INT lsb_mask, t;
738 /* This might not be obvious, but it's at least fast.
739 This function is critical; we don't have the time loops would take. */
741 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
742 /* Return true iff t is a power of two. */
743 return ((t & (t - 1)) == 0);
746 /* True iff depi or extru can be used to compute (reg & mask).
747 Accept bit pattern like these:
753 unsigned HOST_WIDE_INT mask;
756 mask += mask & -mask;
757 return (mask & (mask - 1)) == 0;
760 /* True iff depi or extru can be used to compute (reg & OP). */
762 and_operand (op, mode)
764 enum machine_mode mode;
766 return (register_operand (op, mode)
767 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
770 /* True iff depi can be used to compute (reg | MASK). */
773 unsigned HOST_WIDE_INT mask;
775 mask += mask & -mask;
776 return (mask & (mask - 1)) == 0;
779 /* True iff depi can be used to compute (reg | OP). */
781 ior_operand (op, mode)
783 enum machine_mode mode ATTRIBUTE_UNUSED;
785 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
789 lhs_lshift_operand (op, mode)
791 enum machine_mode mode;
793 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
796 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
797 Such values can be the left hand side x in (x << r), using the zvdepi
800 lhs_lshift_cint_operand (op, mode)
802 enum machine_mode mode ATTRIBUTE_UNUSED;
804 unsigned HOST_WIDE_INT x;
805 if (GET_CODE (op) != CONST_INT)
807 x = INTVAL (op) >> 4;
808 return (x & (x + 1)) == 0;
812 arith32_operand (op, mode)
814 enum machine_mode mode;
816 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
820 pc_or_label_operand (op, mode)
822 enum machine_mode mode ATTRIBUTE_UNUSED;
824 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
827 /* Legitimize PIC addresses. If the address is already
828 position-independent, we return ORIG. Newly generated
829 position-independent addresses go to REG. If we need more
830 than one register, we lose. */
833 legitimize_pic_address (orig, mode, reg)
835 enum machine_mode mode;
839 /* Labels need special handling. */
840 if (pic_label_operand (orig, mode))
842 /* We do not want to go through the movXX expanders here since that
843 would create recursion.
845 Nor do we really want to call a generator for a named pattern
846 since that requires multiple patterns if we want to support
849 So instead we just emit the raw set, which avoids the movXX
850 expanders completely. */
851 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
852 current_function_uses_pic_offset_table = 1;
855 if (GET_CODE (orig) == SYMBOL_REF)
861 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
862 gen_rtx_HIGH (word_mode, orig)));
864 = gen_rtx_MEM (Pmode,
865 gen_rtx_LO_SUM (Pmode, reg,
866 gen_rtx_UNSPEC (Pmode,
870 current_function_uses_pic_offset_table = 1;
871 RTX_UNCHANGING_P (pic_ref) = 1;
872 emit_move_insn (reg, pic_ref);
875 else if (GET_CODE (orig) == CONST)
879 if (GET_CODE (XEXP (orig, 0)) == PLUS
880 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
886 if (GET_CODE (XEXP (orig, 0)) == PLUS)
888 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
889 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
890 base == reg ? 0 : reg);
893 if (GET_CODE (orig) == CONST_INT)
895 if (INT_14_BITS (orig))
896 return plus_constant (base, INTVAL (orig));
897 orig = force_reg (Pmode, orig);
899 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
900 /* Likewise, should we set special REG_NOTEs here? */
905 /* Try machine-dependent ways of modifying an illegitimate address
906 to be legitimate. If we find one, return the new, valid address.
907 This macro is used in only one place: `memory_address' in explow.c.
909 OLDX is the address as it was before break_out_memory_refs was called.
910 In some cases it is useful to look at this to decide what needs to be done.
912 MODE and WIN are passed so that this macro can use
913 GO_IF_LEGITIMATE_ADDRESS.
915 It is always safe for this macro to do nothing. It exists to recognize
916 opportunities to optimize the output.
918 For the PA, transform:
920 memory(X + <large int>)
924 if (<large int> & mask) >= 16
925 Y = (<large int> & ~mask) + mask + 1 Round up.
927 Y = (<large int> & ~mask) Round down.
929 memory (Z + (<large int> - Y));
931 This is for CSE to find several similar references, and only use one Z.
933 X can either be a SYMBOL_REF or REG, but because combine can not
934 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
935 D will not fit in 14 bits.
937 MODE_FLOAT references allow displacements which fit in 5 bits, so use
940 MODE_INT references allow displacements which fit in 14 bits, so use
943 This relies on the fact that most mode MODE_FLOAT references will use FP
944 registers and most mode MODE_INT references will use integer registers.
945 (In the rare case of an FP register used in an integer MODE, we depend
946 on secondary reloads to clean things up.)
949 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
950 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
951 addressing modes to be used).
953 Put X and Z into registers. Then put the entire expression into
957 hppa_legitimize_address (x, oldx, mode)
958 rtx x, oldx ATTRIBUTE_UNUSED;
959 enum machine_mode mode;
964 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
966 /* Strip off CONST. */
967 if (GET_CODE (x) == CONST)
970 /* Special case. Get the SYMBOL_REF into a register and use indexing.
971 That should always be safe. */
972 if (GET_CODE (x) == PLUS
973 && GET_CODE (XEXP (x, 0)) == REG
974 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
976 rtx reg = force_reg (Pmode, XEXP (x, 1));
977 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
980 /* Note we must reject symbols which represent function addresses
981 since the assembler/linker can't handle arithmetic on plabels. */
982 if (GET_CODE (x) == PLUS
983 && GET_CODE (XEXP (x, 1)) == CONST_INT
984 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
985 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
986 || GET_CODE (XEXP (x, 0)) == REG))
988 rtx int_part, ptr_reg;
990 int offset = INTVAL (XEXP (x, 1));
993 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
994 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
996 /* Choose which way to round the offset. Round up if we
997 are >= halfway to the next boundary. */
998 if ((offset & mask) >= ((mask + 1) / 2))
999 newoffset = (offset & ~ mask) + mask + 1;
1001 newoffset = (offset & ~ mask);
1003 /* If the newoffset will not fit in 14 bits (ldo), then
1004 handling this would take 4 or 5 instructions (2 to load
1005 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1006 add the new offset and the SYMBOL_REF.) Combine can
1007 not handle 4->2 or 5->2 combinations, so do not create
1009 if (! VAL_14_BITS_P (newoffset)
1010 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1012 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1015 gen_rtx_HIGH (Pmode, const_part));
1018 gen_rtx_LO_SUM (Pmode,
1019 tmp_reg, const_part));
1023 if (! VAL_14_BITS_P (newoffset))
1024 int_part = force_reg (Pmode, GEN_INT (newoffset));
1026 int_part = GEN_INT (newoffset);
1028 ptr_reg = force_reg (Pmode,
1029 gen_rtx_PLUS (Pmode,
1030 force_reg (Pmode, XEXP (x, 0)),
1033 return plus_constant (ptr_reg, offset - newoffset);
1036 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1038 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1039 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1040 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1041 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1042 || GET_CODE (XEXP (x, 1)) == SUBREG)
1043 && GET_CODE (XEXP (x, 1)) != CONST)
1045 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1049 if (GET_CODE (reg1) != REG)
1050 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1052 reg2 = XEXP (XEXP (x, 0), 0);
1053 if (GET_CODE (reg2) != REG)
1054 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1056 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1057 gen_rtx_MULT (Pmode,
1063 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1065 Only do so for floating point modes since this is more speculative
1066 and we lose if it's an integer store. */
1067 if (GET_CODE (x) == PLUS
1068 && GET_CODE (XEXP (x, 0)) == PLUS
1069 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1070 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1071 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1072 && (mode == SFmode || mode == DFmode))
1075 /* First, try and figure out what to use as a base register. */
1076 rtx reg1, reg2, base, idx, orig_base;
1078 reg1 = XEXP (XEXP (x, 0), 1);
1083 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1084 then emit_move_sequence will turn on REG_POINTER so we'll know
1085 it's a base register below. */
1086 if (GET_CODE (reg1) != REG)
1087 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1089 if (GET_CODE (reg2) != REG)
1090 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1092 /* Figure out what the base and index are. */
1094 if (GET_CODE (reg1) == REG
1095 && REG_POINTER (reg1))
1098 orig_base = XEXP (XEXP (x, 0), 1);
1099 idx = gen_rtx_PLUS (Pmode,
1100 gen_rtx_MULT (Pmode,
1101 XEXP (XEXP (XEXP (x, 0), 0), 0),
1102 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1105 else if (GET_CODE (reg2) == REG
1106 && REG_POINTER (reg2))
1109 orig_base = XEXP (x, 1);
1116 /* If the index adds a large constant, try to scale the
1117 constant so that it can be loaded with only one insn. */
1118 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1119 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1120 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1121 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1123 /* Divide the CONST_INT by the scale factor, then add it to A. */
1124 int val = INTVAL (XEXP (idx, 1));
1126 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1127 reg1 = XEXP (XEXP (idx, 0), 0);
1128 if (GET_CODE (reg1) != REG)
1129 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1131 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1133 /* We can now generate a simple scaled indexed address. */
1136 (Pmode, gen_rtx_PLUS (Pmode,
1137 gen_rtx_MULT (Pmode, reg1,
1138 XEXP (XEXP (idx, 0), 1)),
1142 /* If B + C is still a valid base register, then add them. */
1143 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1144 && INTVAL (XEXP (idx, 1)) <= 4096
1145 && INTVAL (XEXP (idx, 1)) >= -4096)
1147 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1150 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1152 reg2 = XEXP (XEXP (idx, 0), 0);
1153 if (GET_CODE (reg2) != CONST_INT)
1154 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1156 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1157 gen_rtx_MULT (Pmode,
1163 /* Get the index into a register, then add the base + index and
1164 return a register holding the result. */
1166 /* First get A into a register. */
1167 reg1 = XEXP (XEXP (idx, 0), 0);
1168 if (GET_CODE (reg1) != REG)
1169 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1171 /* And get B into a register. */
1172 reg2 = XEXP (idx, 1);
1173 if (GET_CODE (reg2) != REG)
1174 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1176 reg1 = force_reg (Pmode,
1177 gen_rtx_PLUS (Pmode,
1178 gen_rtx_MULT (Pmode, reg1,
1179 XEXP (XEXP (idx, 0), 1)),
1182 /* Add the result to our base register and return. */
1183 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1187 /* Uh-oh. We might have an address for x[n-100000]. This needs
1188 special handling to avoid creating an indexed memory address
1189 with x-100000 as the base.
1191 If the constant part is small enough, then it's still safe because
1192 there is a guard page at the beginning and end of the data segment.
1194 Scaled references are common enough that we want to try and rearrange the
1195 terms so that we can use indexing for these addresses too. Only
1196 do the optimization for floatint point modes. */
1198 if (GET_CODE (x) == PLUS
1199 && symbolic_expression_p (XEXP (x, 1)))
1201 /* Ugly. We modify things here so that the address offset specified
1202 by the index expression is computed first, then added to x to form
1203 the entire address. */
1205 rtx regx1, regx2, regy1, regy2, y;
1207 /* Strip off any CONST. */
1209 if (GET_CODE (y) == CONST)
1212 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1214 /* See if this looks like
1215 (plus (mult (reg) (shadd_const))
1216 (const (plus (symbol_ref) (const_int))))
1218 Where const_int is small. In that case the const
1219 expression is a valid pointer for indexing.
1221 If const_int is big, but can be divided evenly by shadd_const
1222 and added to (reg). This allows more scaled indexed addresses. */
1223 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1224 && GET_CODE (XEXP (x, 0)) == MULT
1225 && GET_CODE (XEXP (y, 1)) == CONST_INT
1226 && INTVAL (XEXP (y, 1)) >= -4096
1227 && INTVAL (XEXP (y, 1)) <= 4095
1228 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1229 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1231 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1235 if (GET_CODE (reg1) != REG)
1236 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1238 reg2 = XEXP (XEXP (x, 0), 0);
1239 if (GET_CODE (reg2) != REG)
1240 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1242 return force_reg (Pmode,
1243 gen_rtx_PLUS (Pmode,
1244 gen_rtx_MULT (Pmode,
1249 else if ((mode == DFmode || mode == SFmode)
1250 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1251 && GET_CODE (XEXP (x, 0)) == MULT
1252 && GET_CODE (XEXP (y, 1)) == CONST_INT
1253 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1254 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1255 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1258 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1259 / INTVAL (XEXP (XEXP (x, 0), 1))));
1260 regx2 = XEXP (XEXP (x, 0), 0);
1261 if (GET_CODE (regx2) != REG)
1262 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1263 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1267 gen_rtx_PLUS (Pmode,
1268 gen_rtx_MULT (Pmode, regx2,
1269 XEXP (XEXP (x, 0), 1)),
1270 force_reg (Pmode, XEXP (y, 0))));
1272 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1273 && INTVAL (XEXP (y, 1)) >= -4096
1274 && INTVAL (XEXP (y, 1)) <= 4095)
1276 /* This is safe because of the guard page at the
1277 beginning and end of the data space. Just
1278 return the original address. */
1283 /* Doesn't look like one we can optimize. */
1284 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1285 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1286 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1287 regx1 = force_reg (Pmode,
1288 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1290 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1298 /* For the HPPA, REG and REG+CONST is cost 0
1299 and addresses involving symbolic constants are cost 2.
1301 PIC addresses are very expensive.
1303 It is no coincidence that this has the same structure
1304 as GO_IF_LEGITIMATE_ADDRESS. */
1306 hppa_address_cost (X)
1309 if (GET_CODE (X) == PLUS)
1311 else if (GET_CODE (X) == LO_SUM)
1313 else if (GET_CODE (X) == HIGH)
1318 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1319 new rtx with the correct mode. */
1321 force_mode (mode, orig)
1322 enum machine_mode mode;
1325 if (mode == GET_MODE (orig))
1328 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1331 return gen_rtx_REG (mode, REGNO (orig));
1334 /* Emit insns to move operands[1] into operands[0].
1336 Return 1 if we have written out everything that needs to be done to
1337 do the move. Otherwise, return 0 and the caller will emit the move
1340 Note SCRATCH_REG may not be in the proper mode depending on how it
1341 will be used. This routine is resposible for creating a new copy
1342 of SCRATCH_REG in the proper mode. */
1345 emit_move_sequence (operands, mode, scratch_reg)
1347 enum machine_mode mode;
1350 register rtx operand0 = operands[0];
1351 register rtx operand1 = operands[1];
1355 && reload_in_progress && GET_CODE (operand0) == REG
1356 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1357 operand0 = reg_equiv_mem[REGNO (operand0)];
1358 else if (scratch_reg
1359 && reload_in_progress && GET_CODE (operand0) == SUBREG
1360 && GET_CODE (SUBREG_REG (operand0)) == REG
1361 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1363 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1364 the code which tracks sets/uses for delete_output_reload. */
1365 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1366 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1367 SUBREG_BYTE (operand0));
1368 operand0 = alter_subreg (&temp);
1372 && reload_in_progress && GET_CODE (operand1) == REG
1373 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1374 operand1 = reg_equiv_mem[REGNO (operand1)];
1375 else if (scratch_reg
1376 && reload_in_progress && GET_CODE (operand1) == SUBREG
1377 && GET_CODE (SUBREG_REG (operand1)) == REG
1378 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1380 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1381 the code which tracks sets/uses for delete_output_reload. */
1382 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1383 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1384 SUBREG_BYTE (operand1));
1385 operand1 = alter_subreg (&temp);
1388 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1389 && ((tem = find_replacement (&XEXP (operand0, 0)))
1390 != XEXP (operand0, 0)))
1391 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1392 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1393 && ((tem = find_replacement (&XEXP (operand1, 0)))
1394 != XEXP (operand1, 0)))
1395 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1397 /* Handle secondary reloads for loads/stores of FP registers from
1398 REG+D addresses where D does not fit in 5 bits, including
1399 (subreg (mem (addr))) cases. */
1400 if (fp_reg_operand (operand0, mode)
1401 && ((GET_CODE (operand1) == MEM
1402 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1403 || ((GET_CODE (operand1) == SUBREG
1404 && GET_CODE (XEXP (operand1, 0)) == MEM
1405 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1408 if (GET_CODE (operand1) == SUBREG)
1409 operand1 = XEXP (operand1, 0);
1411 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1412 it in WORD_MODE regardless of what mode it was originally given
1414 scratch_reg = force_mode (word_mode, scratch_reg);
1416 /* D might not fit in 14 bits either; for such cases load D into
1418 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1420 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1421 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1423 XEXP (XEXP (operand1, 0), 0),
1427 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1428 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1429 gen_rtx_MEM (mode, scratch_reg)));
1432 else if (fp_reg_operand (operand1, mode)
1433 && ((GET_CODE (operand0) == MEM
1434 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1435 || ((GET_CODE (operand0) == SUBREG)
1436 && GET_CODE (XEXP (operand0, 0)) == MEM
1437 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1440 if (GET_CODE (operand0) == SUBREG)
1441 operand0 = XEXP (operand0, 0);
1443 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1444 it in WORD_MODE regardless of what mode it was originally given
1446 scratch_reg = force_mode (word_mode, scratch_reg);
1448 /* D might not fit in 14 bits either; for such cases load D into
1450 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1452 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1453 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1456 XEXP (XEXP (operand0, 0),
1461 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1462 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1466 /* Handle secondary reloads for loads of FP registers from constant
1467 expressions by forcing the constant into memory.
1469 use scratch_reg to hold the address of the memory location.
1471 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1472 NO_REGS when presented with a const_int and a register class
1473 containing only FP registers. Doing so unfortunately creates
1474 more problems than it solves. Fix this for 2.5. */
1475 else if (fp_reg_operand (operand0, mode)
1476 && CONSTANT_P (operand1)
1481 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1482 it in WORD_MODE regardless of what mode it was originally given
1484 scratch_reg = force_mode (word_mode, scratch_reg);
1486 /* Force the constant into memory and put the address of the
1487 memory location into scratch_reg. */
1488 xoperands[0] = scratch_reg;
1489 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1490 emit_move_sequence (xoperands, Pmode, 0);
1492 /* Now load the destination register. */
1493 emit_insn (gen_rtx_SET (mode, operand0,
1494 gen_rtx_MEM (mode, scratch_reg)));
1497 /* Handle secondary reloads for SAR. These occur when trying to load
1498 the SAR from memory, FP register, or with a constant. */
1499 else if (GET_CODE (operand0) == REG
1500 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1501 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1502 && (GET_CODE (operand1) == MEM
1503 || GET_CODE (operand1) == CONST_INT
1504 || (GET_CODE (operand1) == REG
1505 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1508 /* D might not fit in 14 bits either; for such cases load D into
1510 if (GET_CODE (operand1) == MEM
1511 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1513 /* We are reloading the address into the scratch register, so we
1514 want to make sure the scratch register is a full register. */
1515 scratch_reg = force_mode (word_mode, scratch_reg);
1517 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1518 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1521 XEXP (XEXP (operand1, 0),
1525 /* Now we are going to load the scratch register from memory,
1526 we want to load it in the same width as the original MEM,
1527 which must be the same as the width of the ultimate destination,
1529 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1531 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1536 /* We want to load the scratch register using the same mode as
1537 the ultimate destination. */
1538 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1540 emit_move_insn (scratch_reg, operand1);
1543 /* And emit the insn to set the ultimate destination. We know that
1544 the scratch register has the same mode as the destination at this
1546 emit_move_insn (operand0, scratch_reg);
1549 /* Handle most common case: storing into a register. */
1550 else if (register_operand (operand0, mode))
1552 if (register_operand (operand1, mode)
1553 || (GET_CODE (operand1) == CONST_INT
1554 && cint_ok_for_move (INTVAL (operand1)))
1555 || (operand1 == CONST0_RTX (mode))
1556 || (GET_CODE (operand1) == HIGH
1557 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1558 /* Only `general_operands' can come here, so MEM is ok. */
1559 || GET_CODE (operand1) == MEM)
1561 /* Run this case quickly. */
1562 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1566 else if (GET_CODE (operand0) == MEM)
1568 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1569 && !(reload_in_progress || reload_completed))
1571 rtx temp = gen_reg_rtx (DFmode);
1573 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1574 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1577 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1579 /* Run this case quickly. */
1580 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1583 if (! (reload_in_progress || reload_completed))
1585 operands[0] = validize_mem (operand0);
1586 operands[1] = operand1 = force_reg (mode, operand1);
1590 /* Simplify the source if we need to.
1591 Note we do have to handle function labels here, even though we do
1592 not consider them legitimate constants. Loop optimizations can
1593 call the emit_move_xxx with one as a source. */
1594 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1595 || function_label_operand (operand1, mode)
1596 || (GET_CODE (operand1) == HIGH
1597 && symbolic_operand (XEXP (operand1, 0), mode)))
1601 if (GET_CODE (operand1) == HIGH)
1604 operand1 = XEXP (operand1, 0);
1606 if (symbolic_operand (operand1, mode))
1608 /* Argh. The assembler and linker can't handle arithmetic
1611 So we force the plabel into memory, load operand0 from
1612 the memory location, then add in the constant part. */
1613 if ((GET_CODE (operand1) == CONST
1614 && GET_CODE (XEXP (operand1, 0)) == PLUS
1615 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1616 || function_label_operand (operand1, mode))
1618 rtx temp, const_part;
1620 /* Figure out what (if any) scratch register to use. */
1621 if (reload_in_progress || reload_completed)
1623 scratch_reg = scratch_reg ? scratch_reg : operand0;
1624 /* SCRATCH_REG will hold an address and maybe the actual
1625 data. We want it in WORD_MODE regardless of what mode it
1626 was originally given to us. */
1627 scratch_reg = force_mode (word_mode, scratch_reg);
1630 scratch_reg = gen_reg_rtx (Pmode);
1632 if (GET_CODE (operand1) == CONST)
1634 /* Save away the constant part of the expression. */
1635 const_part = XEXP (XEXP (operand1, 0), 1);
1636 if (GET_CODE (const_part) != CONST_INT)
1639 /* Force the function label into memory. */
1640 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1644 /* No constant part. */
1645 const_part = NULL_RTX;
1647 /* Force the function label into memory. */
1648 temp = force_const_mem (mode, operand1);
1652 /* Get the address of the memory location. PIC-ify it if
1654 temp = XEXP (temp, 0);
1656 temp = legitimize_pic_address (temp, mode, scratch_reg);
1658 /* Put the address of the memory location into our destination
1661 emit_move_sequence (operands, mode, scratch_reg);
1663 /* Now load from the memory location into our destination
1665 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1666 emit_move_sequence (operands, mode, scratch_reg);
1668 /* And add back in the constant part. */
1669 if (const_part != NULL_RTX)
1670 expand_inc (operand0, const_part);
1679 if (reload_in_progress || reload_completed)
1681 temp = scratch_reg ? scratch_reg : operand0;
1682 /* TEMP will hold an address and maybe the actual
1683 data. We want it in WORD_MODE regardless of what mode it
1684 was originally given to us. */
1685 temp = force_mode (word_mode, temp);
1688 temp = gen_reg_rtx (Pmode);
1690 /* (const (plus (symbol) (const_int))) must be forced to
1691 memory during/after reload if the const_int will not fit
1693 if (GET_CODE (operand1) == CONST
1694 && GET_CODE (XEXP (operand1, 0)) == PLUS
1695 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1696 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1697 && (reload_completed || reload_in_progress)
1700 operands[1] = force_const_mem (mode, operand1);
1701 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1703 emit_move_sequence (operands, mode, temp);
1707 operands[1] = legitimize_pic_address (operand1, mode, temp);
1708 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1711 /* On the HPPA, references to data space are supposed to use dp,
1712 register 27, but showing it in the RTL inhibits various cse
1713 and loop optimizations. */
1718 if (reload_in_progress || reload_completed)
1720 temp = scratch_reg ? scratch_reg : operand0;
1721 /* TEMP will hold an address and maybe the actual
1722 data. We want it in WORD_MODE regardless of what mode it
1723 was originally given to us. */
1724 temp = force_mode (word_mode, temp);
1727 temp = gen_reg_rtx (mode);
1729 /* Loading a SYMBOL_REF into a register makes that register
1730 safe to be used as the base in an indexed address.
1732 Don't mark hard registers though. That loses. */
1733 if (GET_CODE (operand0) == REG
1734 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1735 REG_POINTER (operand0) = 1;
1736 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1737 REG_POINTER (temp) = 1;
1739 set = gen_rtx_SET (mode, operand0, temp);
1741 set = gen_rtx_SET (VOIDmode,
1743 gen_rtx_LO_SUM (mode, temp, operand1));
1745 emit_insn (gen_rtx_SET (VOIDmode,
1747 gen_rtx_HIGH (mode, operand1)));
1753 else if (GET_CODE (operand1) != CONST_INT
1754 || ! cint_ok_for_move (INTVAL (operand1)))
1756 rtx extend = NULL_RTX;
1759 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1760 && HOST_BITS_PER_WIDE_INT > 32
1761 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1763 HOST_WIDE_INT val = INTVAL (operand1);
1766 /* Extract the low order 32 bits of the value and sign extend.
1767 If the new value is the same as the original value, we can
1768 can use the original value as-is. If the new value is
1769 different, we use it and insert the most-significant 32-bits
1770 of the original value into the final result. */
1771 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1772 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1775 #if HOST_BITS_PER_WIDE_INT > 32
1776 extend = GEN_INT (val >> 32);
1778 operand1 = GEN_INT (nval);
1782 if (reload_in_progress || reload_completed)
1785 temp = gen_reg_rtx (mode);
1787 /* We don't directly split DImode constants on 32-bit targets
1788 because PLUS uses an 11-bit immediate and the insn sequence
1789 generated is not as efficient as the one using HIGH/LO_SUM. */
1790 if (GET_CODE (operand1) == CONST_INT
1791 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1793 /* Directly break constant into high and low parts. This
1794 provides better optimization opportunities because various
1795 passes recognize constants split with PLUS but not LO_SUM.
1796 We use a 14-bit signed low part except when the addition
1797 of 0x4000 to the high part might change the sign of the
1799 HOST_WIDE_INT value = INTVAL (operand1);
1800 HOST_WIDE_INT low = value & 0x3fff;
1801 HOST_WIDE_INT high = value & ~ 0x3fff;
1805 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1813 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1814 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1818 emit_insn (gen_rtx_SET (VOIDmode, temp,
1819 gen_rtx_HIGH (mode, operand1)));
1820 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1823 emit_move_insn (operands[0], operands[1]);
1825 if (extend != NULL_RTX)
1826 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1832 /* Now have insn-emit do whatever it normally does. */
1836 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1837 it will need a link/runtime reloc). */
1845 switch (TREE_CODE (exp))
1852 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1853 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1858 case NON_LVALUE_EXPR:
1859 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1865 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1866 if (TREE_VALUE (link) != 0)
1867 reloc |= reloc_needed (TREE_VALUE (link));
1880 /* Does operand (which is a symbolic_operand) live in text space?
1881 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1885 read_only_operand (operand, mode)
1887 enum machine_mode mode ATTRIBUTE_UNUSED;
1889 if (GET_CODE (operand) == CONST)
1890 operand = XEXP (XEXP (operand, 0), 0);
1893 if (GET_CODE (operand) == SYMBOL_REF)
1894 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1898 if (GET_CODE (operand) == SYMBOL_REF)
1899 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1905 /* Return the best assembler insn template
1906 for moving operands[1] into operands[0] as a fullword. */
1908 singlemove_string (operands)
1911 HOST_WIDE_INT intval;
1913 if (GET_CODE (operands[0]) == MEM)
1914 return "stw %r1,%0";
1915 if (GET_CODE (operands[1]) == MEM)
1917 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1922 if (GET_MODE (operands[1]) != SFmode)
1925 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1927 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1928 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1930 operands[1] = GEN_INT (i);
1931 /* Fall through to CONST_INT case. */
1933 if (GET_CODE (operands[1]) == CONST_INT)
1935 intval = INTVAL (operands[1]);
1937 if (VAL_14_BITS_P (intval))
1939 else if ((intval & 0x7ff) == 0)
1940 return "ldil L'%1,%0";
1941 else if (zdepi_cint_p (intval))
1942 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1944 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1946 return "copy %1,%0";
1950 /* Compute position (in OP[1]) and width (in OP[2])
1951 useful for copying IMM to a register using the zdepi
1952 instructions. Store the immediate value to insert in OP[0]. */
1954 compute_zdepwi_operands (imm, op)
1955 unsigned HOST_WIDE_INT imm;
1960 /* Find the least significant set bit in IMM. */
1961 for (lsb = 0; lsb < 32; lsb++)
1968 /* Choose variants based on *sign* of the 5-bit field. */
1969 if ((imm & 0x10) == 0)
1970 len = (lsb <= 28) ? 4 : 32 - lsb;
1973 /* Find the width of the bitstring in IMM. */
1974 for (len = 5; len < 32; len++)
1976 if ((imm & (1 << len)) == 0)
1980 /* Sign extend IMM as a 5-bit value. */
1981 imm = (imm & 0xf) - 0x10;
1989 /* Compute position (in OP[1]) and width (in OP[2])
1990 useful for copying IMM to a register using the depdi,z
1991 instructions. Store the immediate value to insert in OP[0]. */
1993 compute_zdepdi_operands (imm, op)
1994 unsigned HOST_WIDE_INT imm;
1997 HOST_WIDE_INT lsb, len;
1999 /* Find the least significant set bit in IMM. */
2000 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2007 /* Choose variants based on *sign* of the 5-bit field. */
2008 if ((imm & 0x10) == 0)
2009 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2010 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2013 /* Find the width of the bitstring in IMM. */
2014 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2016 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2020 /* Sign extend IMM as a 5-bit value. */
2021 imm = (imm & 0xf) - 0x10;
2029 /* Output assembler code to perform a doubleword move insn
2030 with operands OPERANDS. */
2033 output_move_double (operands)
2036 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2038 rtx addreg0 = 0, addreg1 = 0;
2040 /* First classify both operands. */
2042 if (REG_P (operands[0]))
2044 else if (offsettable_memref_p (operands[0]))
2046 else if (GET_CODE (operands[0]) == MEM)
2051 if (REG_P (operands[1]))
2053 else if (CONSTANT_P (operands[1]))
2055 else if (offsettable_memref_p (operands[1]))
2057 else if (GET_CODE (operands[1]) == MEM)
2062 /* Check for the cases that the operand constraints are not
2063 supposed to allow to happen. Abort if we get one,
2064 because generating code for these cases is painful. */
2066 if (optype0 != REGOP && optype1 != REGOP)
2069 /* Handle auto decrementing and incrementing loads and stores
2070 specifically, since the structure of the function doesn't work
2071 for them without major modification. Do it better when we learn
2072 this port about the general inc/dec addressing of PA.
2073 (This was written by tege. Chide him if it doesn't work.) */
2075 if (optype0 == MEMOP)
2077 /* We have to output the address syntax ourselves, since print_operand
2078 doesn't deal with the addresses we want to use. Fix this later. */
2080 rtx addr = XEXP (operands[0], 0);
2081 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2083 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2085 operands[0] = XEXP (addr, 0);
2086 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2089 if (!reg_overlap_mentioned_p (high_reg, addr))
2091 /* No overlap between high target register and address
2092 register. (We do this in a non-obvious way to
2093 save a register file writeback) */
2094 if (GET_CODE (addr) == POST_INC)
2095 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2096 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2101 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2103 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2105 operands[0] = XEXP (addr, 0);
2106 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2109 if (!reg_overlap_mentioned_p (high_reg, addr))
2111 /* No overlap between high target register and address
2112 register. (We do this in a non-obvious way to
2113 save a register file writeback) */
2114 if (GET_CODE (addr) == PRE_INC)
2115 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2116 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2122 if (optype1 == MEMOP)
2124 /* We have to output the address syntax ourselves, since print_operand
2125 doesn't deal with the addresses we want to use. Fix this later. */
2127 rtx addr = XEXP (operands[1], 0);
2128 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2130 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2132 operands[1] = XEXP (addr, 0);
2133 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2136 if (!reg_overlap_mentioned_p (high_reg, addr))
2138 /* No overlap between high target register and address
2139 register. (We do this in a non-obvious way to
2140 save a register file writeback) */
2141 if (GET_CODE (addr) == POST_INC)
2142 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2143 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2147 /* This is an undefined situation. We should load into the
2148 address register *and* update that register. Probably
2149 we don't need to handle this at all. */
2150 if (GET_CODE (addr) == POST_INC)
2151 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2152 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2155 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2157 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2159 operands[1] = XEXP (addr, 0);
2160 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2163 if (!reg_overlap_mentioned_p (high_reg, addr))
2165 /* No overlap between high target register and address
2166 register. (We do this in a non-obvious way to
2167 save a register file writeback) */
2168 if (GET_CODE (addr) == PRE_INC)
2169 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2170 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2174 /* This is an undefined situation. We should load into the
2175 address register *and* update that register. Probably
2176 we don't need to handle this at all. */
2177 if (GET_CODE (addr) == PRE_INC)
2178 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2179 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2182 else if (GET_CODE (addr) == PLUS
2183 && GET_CODE (XEXP (addr, 0)) == MULT)
2185 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2187 if (!reg_overlap_mentioned_p (high_reg, addr))
2191 xoperands[0] = high_reg;
2192 xoperands[1] = XEXP (addr, 1);
2193 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2194 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2195 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2197 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2203 xoperands[0] = high_reg;
2204 xoperands[1] = XEXP (addr, 1);
2205 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2206 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2207 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2209 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2214 /* If an operand is an unoffsettable memory ref, find a register
2215 we can increment temporarily to make it refer to the second word. */
2217 if (optype0 == MEMOP)
2218 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2220 if (optype1 == MEMOP)
2221 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2223 /* Ok, we can do one word at a time.
2224 Normally we do the low-numbered word first.
2226 In either case, set up in LATEHALF the operands to use
2227 for the high-numbered word and in some cases alter the
2228 operands in OPERANDS to be suitable for the low-numbered word. */
2230 if (optype0 == REGOP)
2231 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2232 else if (optype0 == OFFSOP)
2233 latehalf[0] = adjust_address (operands[0], SImode, 4);
2235 latehalf[0] = operands[0];
2237 if (optype1 == REGOP)
2238 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2239 else if (optype1 == OFFSOP)
2240 latehalf[1] = adjust_address (operands[1], SImode, 4);
2241 else if (optype1 == CNSTOP)
2242 split_double (operands[1], &operands[1], &latehalf[1]);
2244 latehalf[1] = operands[1];
2246 /* If the first move would clobber the source of the second one,
2247 do them in the other order.
2249 This can happen in two cases:
2251 mem -> register where the first half of the destination register
2252 is the same register used in the memory's address. Reload
2253 can create such insns.
2255 mem in this case will be either register indirect or register
2256 indirect plus a valid offset.
2258 register -> register move where REGNO(dst) == REGNO(src + 1)
2259 someone (Tim/Tege?) claimed this can happen for parameter loads.
2261 Handle mem -> register case first. */
2262 if (optype0 == REGOP
2263 && (optype1 == MEMOP || optype1 == OFFSOP)
2264 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2267 /* Do the late half first. */
2269 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2270 output_asm_insn (singlemove_string (latehalf), latehalf);
2274 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2275 return singlemove_string (operands);
2278 /* Now handle register -> register case. */
2279 if (optype0 == REGOP && optype1 == REGOP
2280 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2282 output_asm_insn (singlemove_string (latehalf), latehalf);
2283 return singlemove_string (operands);
2286 /* Normal case: do the two words, low-numbered first. */
2288 output_asm_insn (singlemove_string (operands), operands);
2290 /* Make any unoffsettable addresses point at high-numbered word. */
2292 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2294 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2297 output_asm_insn (singlemove_string (latehalf), latehalf);
2299 /* Undo the adds we just did. */
2301 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2303 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2309 output_fp_move_double (operands)
2312 if (FP_REG_P (operands[0]))
2314 if (FP_REG_P (operands[1])
2315 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2316 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2318 output_asm_insn ("fldd%F1 %1,%0", operands);
2320 else if (FP_REG_P (operands[1]))
2322 output_asm_insn ("fstd%F0 %1,%0", operands);
2324 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2326 if (GET_CODE (operands[0]) == REG)
2329 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2330 xoperands[0] = operands[0];
2331 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2333 /* This is a pain. You have to be prepared to deal with an
2334 arbitrary address here including pre/post increment/decrement.
2336 so avoid this in the MD. */
2344 /* Return a REG that occurs in ADDR with coefficient 1.
2345 ADDR can be effectively incremented by incrementing REG. */
2348 find_addr_reg (addr)
2351 while (GET_CODE (addr) == PLUS)
2353 if (GET_CODE (XEXP (addr, 0)) == REG)
2354 addr = XEXP (addr, 0);
2355 else if (GET_CODE (XEXP (addr, 1)) == REG)
2356 addr = XEXP (addr, 1);
2357 else if (CONSTANT_P (XEXP (addr, 0)))
2358 addr = XEXP (addr, 1);
2359 else if (CONSTANT_P (XEXP (addr, 1)))
2360 addr = XEXP (addr, 0);
2364 if (GET_CODE (addr) == REG)
2369 /* Emit code to perform a block move.
2371 OPERANDS[0] is the destination pointer as a REG, clobbered.
2372 OPERANDS[1] is the source pointer as a REG, clobbered.
2373 OPERANDS[2] is a register for temporary storage.
2374 OPERANDS[4] is the size as a CONST_INT
2375 OPERANDS[3] is a register for temporary storage.
2376 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2377 OPERANDS[6] is another temporary register. */
2380 output_block_move (operands, size_is_constant)
2382 int size_is_constant ATTRIBUTE_UNUSED;
2384 int align = INTVAL (operands[5]);
2385 unsigned long n_bytes = INTVAL (operands[4]);
2387 /* We can't move more than four bytes at a time because the PA
2388 has no longer integer move insns. (Could use fp mem ops?) */
2392 /* Note that we know each loop below will execute at least twice
2393 (else we would have open-coded the copy). */
2397 /* Pre-adjust the loop counter. */
2398 operands[4] = GEN_INT (n_bytes - 8);
2399 output_asm_insn ("ldi %4,%2", operands);
2402 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2403 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2404 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2405 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2406 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2408 /* Handle the residual. There could be up to 7 bytes of
2409 residual to copy! */
2410 if (n_bytes % 8 != 0)
2412 operands[4] = GEN_INT (n_bytes % 4);
2413 if (n_bytes % 8 >= 4)
2414 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2415 if (n_bytes % 4 != 0)
2416 output_asm_insn ("ldw 0(%1),%6", operands);
2417 if (n_bytes % 8 >= 4)
2418 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2419 if (n_bytes % 4 != 0)
2420 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2425 /* Pre-adjust the loop counter. */
2426 operands[4] = GEN_INT (n_bytes - 4);
2427 output_asm_insn ("ldi %4,%2", operands);
2430 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2431 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2432 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2433 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2434 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2436 /* Handle the residual. */
2437 if (n_bytes % 4 != 0)
2439 if (n_bytes % 4 >= 2)
2440 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2441 if (n_bytes % 2 != 0)
2442 output_asm_insn ("ldb 0(%1),%6", operands);
2443 if (n_bytes % 4 >= 2)
2444 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2445 if (n_bytes % 2 != 0)
2446 output_asm_insn ("stb %6,0(%0)", operands);
2451 /* Pre-adjust the loop counter. */
2452 operands[4] = GEN_INT (n_bytes - 2);
2453 output_asm_insn ("ldi %4,%2", operands);
2456 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2457 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2458 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2459 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2460 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2462 /* Handle the residual. */
2463 if (n_bytes % 2 != 0)
2465 output_asm_insn ("ldb 0(%1),%3", operands);
2466 output_asm_insn ("stb %3,0(%0)", operands);
2475 /* Count the number of insns necessary to handle this block move.
2477 Basic structure is the same as emit_block_move, except that we
2478 count insns rather than emit them. */
2481 compute_movstrsi_length (insn)
2484 rtx pat = PATTERN (insn);
2485 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2486 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2487 unsigned int n_insns = 0;
2489 /* We can't move more than four bytes at a time because the PA
2490 has no longer integer move insns. (Could use fp mem ops?) */
2494 /* The basic copying loop. */
2498 if (n_bytes % (2 * align) != 0)
2500 if ((n_bytes % (2 * align)) >= align)
2503 if ((n_bytes % align) != 0)
2507 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2513 output_and (operands)
2516 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2518 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2519 int ls0, ls1, ms0, p, len;
2521 for (ls0 = 0; ls0 < 32; ls0++)
2522 if ((mask & (1 << ls0)) == 0)
2525 for (ls1 = ls0; ls1 < 32; ls1++)
2526 if ((mask & (1 << ls1)) != 0)
2529 for (ms0 = ls1; ms0 < 32; ms0++)
2530 if ((mask & (1 << ms0)) == 0)
2543 operands[2] = GEN_INT (len);
2544 return "{extru|extrw,u} %1,31,%2,%0";
2548 /* We could use this `depi' for the case above as well, but `depi'
2549 requires one more register file access than an `extru'. */
2554 operands[2] = GEN_INT (p);
2555 operands[3] = GEN_INT (len);
2556 return "{depi|depwi} 0,%2,%3,%0";
2560 return "and %1,%2,%0";
2563 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2564 storing the result in operands[0]. */
2566 output_64bit_and (operands)
2569 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2571 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2572 int ls0, ls1, ms0, p, len;
2574 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2575 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2578 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2579 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2582 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2583 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2586 if (ms0 != HOST_BITS_PER_WIDE_INT)
2589 if (ls1 == HOST_BITS_PER_WIDE_INT)
2596 operands[2] = GEN_INT (len);
2597 return "extrd,u %1,63,%2,%0";
2601 /* We could use this `depi' for the case above as well, but `depi'
2602 requires one more register file access than an `extru'. */
2607 operands[2] = GEN_INT (p);
2608 operands[3] = GEN_INT (len);
2609 return "depdi 0,%2,%3,%0";
2613 return "and %1,%2,%0";
2617 output_ior (operands)
2620 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2621 int bs0, bs1, p, len;
2623 if (INTVAL (operands[2]) == 0)
2624 return "copy %1,%0";
2626 for (bs0 = 0; bs0 < 32; bs0++)
2627 if ((mask & (1 << bs0)) != 0)
2630 for (bs1 = bs0; bs1 < 32; bs1++)
2631 if ((mask & (1 << bs1)) == 0)
2634 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2640 operands[2] = GEN_INT (p);
2641 operands[3] = GEN_INT (len);
2642 return "{depi|depwi} -1,%2,%3,%0";
2645 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2646 storing the result in operands[0]. */
2648 output_64bit_ior (operands)
2651 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2652 int bs0, bs1, p, len;
2654 if (INTVAL (operands[2]) == 0)
2655 return "copy %1,%0";
2657 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2658 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2661 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2662 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2665 if (bs1 != HOST_BITS_PER_WIDE_INT
2666 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2672 operands[2] = GEN_INT (p);
2673 operands[3] = GEN_INT (len);
2674 return "depdi -1,%2,%3,%0";
2677 /* Target hook for assembling integer objects. This code handles
2678 aligned SI and DI integers specially, since function references must
2679 be preceded by P%. */
2682 pa_assemble_integer (x, size, aligned_p)
2687 if (size == UNITS_PER_WORD && aligned_p
2688 && function_label_operand (x, VOIDmode))
2690 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2691 output_addr_const (asm_out_file, x);
2692 fputc ('\n', asm_out_file);
2695 return default_assemble_integer (x, size, aligned_p);
2698 /* Output an ascii string. */
2700 output_ascii (file, p, size)
2707 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2709 /* The HP assembler can only take strings of 256 characters at one
2710 time. This is a limitation on input line length, *not* the
2711 length of the string. Sigh. Even worse, it seems that the
2712 restriction is in number of input characters (see \xnn &
2713 \whatever). So we have to do this very carefully. */
2715 fputs ("\t.STRING \"", file);
2718 for (i = 0; i < size; i += 4)
2722 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2724 register unsigned int c = (unsigned char) p[i + io];
2726 if (c == '\"' || c == '\\')
2727 partial_output[co++] = '\\';
2728 if (c >= ' ' && c < 0177)
2729 partial_output[co++] = c;
2733 partial_output[co++] = '\\';
2734 partial_output[co++] = 'x';
2735 hexd = c / 16 - 0 + '0';
2737 hexd -= '9' - 'a' + 1;
2738 partial_output[co++] = hexd;
2739 hexd = c % 16 - 0 + '0';
2741 hexd -= '9' - 'a' + 1;
2742 partial_output[co++] = hexd;
2745 if (chars_output + co > 243)
2747 fputs ("\"\n\t.STRING \"", file);
2750 fwrite (partial_output, 1, (size_t) co, file);
2754 fputs ("\"\n", file);
2757 /* Try to rewrite floating point comparisons & branches to avoid
2758 useless add,tr insns.
2760 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2761 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2762 first attempt to remove useless add,tr insns. It is zero
2763 for the second pass as reorg sometimes leaves bogus REG_DEAD
2766 When CHECK_NOTES is zero we can only eliminate add,tr insns
2767 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2770 remove_useless_addtr_insns (insns, check_notes)
2775 static int pass = 0;
2777 /* This is fairly cheap, so always run it when optimizing. */
2781 int fbranch_count = 0;
2783 /* Walk all the insns in this function looking for fcmp & fbranch
2784 instructions. Keep track of how many of each we find. */
2785 insns = get_insns ();
2786 for (insn = insns; insn; insn = next_insn (insn))
2790 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2791 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2794 tmp = PATTERN (insn);
2796 /* It must be a set. */
2797 if (GET_CODE (tmp) != SET)
2800 /* If the destination is CCFP, then we've found an fcmp insn. */
2801 tmp = SET_DEST (tmp);
2802 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2808 tmp = PATTERN (insn);
2809 /* If this is an fbranch instruction, bump the fbranch counter. */
2810 if (GET_CODE (tmp) == SET
2811 && SET_DEST (tmp) == pc_rtx
2812 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2813 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2814 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2815 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2823 /* Find all floating point compare + branch insns. If possible,
2824 reverse the comparison & the branch to avoid add,tr insns. */
2825 for (insn = insns; insn; insn = next_insn (insn))
2829 /* Ignore anything that isn't an INSN. */
2830 if (GET_CODE (insn) != INSN)
2833 tmp = PATTERN (insn);
2835 /* It must be a set. */
2836 if (GET_CODE (tmp) != SET)
2839 /* The destination must be CCFP, which is register zero. */
2840 tmp = SET_DEST (tmp);
2841 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2844 /* INSN should be a set of CCFP.
2846 See if the result of this insn is used in a reversed FP
2847 conditional branch. If so, reverse our condition and
2848 the branch. Doing so avoids useless add,tr insns. */
2849 next = next_insn (insn);
2852 /* Jumps, calls and labels stop our search. */
2853 if (GET_CODE (next) == JUMP_INSN
2854 || GET_CODE (next) == CALL_INSN
2855 || GET_CODE (next) == CODE_LABEL)
2858 /* As does another fcmp insn. */
2859 if (GET_CODE (next) == INSN
2860 && GET_CODE (PATTERN (next)) == SET
2861 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2862 && REGNO (SET_DEST (PATTERN (next))) == 0)
2865 next = next_insn (next);
2868 /* Is NEXT_INSN a branch? */
2870 && GET_CODE (next) == JUMP_INSN)
2872 rtx pattern = PATTERN (next);
2874 /* If it a reversed fp conditional branch (eg uses add,tr)
2875 and CCFP dies, then reverse our conditional and the branch
2876 to avoid the add,tr. */
2877 if (GET_CODE (pattern) == SET
2878 && SET_DEST (pattern) == pc_rtx
2879 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2880 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2881 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2882 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2883 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2884 && (fcmp_count == fbranch_count
2886 && find_regno_note (next, REG_DEAD, 0))))
2888 /* Reverse the branch. */
2889 tmp = XEXP (SET_SRC (pattern), 1);
2890 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2891 XEXP (SET_SRC (pattern), 2) = tmp;
2892 INSN_CODE (next) = -1;
2894 /* Reverse our condition. */
2895 tmp = PATTERN (insn);
2896 PUT_CODE (XEXP (tmp, 1),
2897 (reverse_condition_maybe_unordered
2898 (GET_CODE (XEXP (tmp, 1)))));
2908 /* You may have trouble believing this, but this is the 32 bit HP-PA
2913 Variable arguments (optional; any number may be allocated)
2915 SP-(4*(N+9)) arg word N
2920 Fixed arguments (must be allocated; may remain unused)
2929 SP-32 External Data Pointer (DP)
2931 SP-24 External/stub RP (RP')
2935 SP-8 Calling Stub RP (RP'')
2940 SP-0 Stack Pointer (points to next available address)
2944 /* This function saves registers as follows. Registers marked with ' are
2945 this function's registers (as opposed to the previous function's).
2946 If a frame_pointer isn't needed, r4 is saved as a general register;
2947 the space for the frame pointer is still allocated, though, to keep
2953 SP (FP') Previous FP
2954 SP + 4 Alignment filler (sigh)
2955 SP + 8 Space for locals reserved here.
2959 SP + n All call saved register used.
2963 SP + o All call saved fp registers used.
2967 SP + p (SP') points to next available address.
2971 /* Global variables set by output_function_prologue(). */
2972 /* Size of frame. Need to know this to emit return insns from
2974 static int actual_fsize;
2975 static int local_fsize, save_fregs;
2977 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2978 Handle case where DISP > 8k by using the add_high_const patterns.
2980 Note in DISP > 8k case, we will leave the high part of the address
2981 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2984 store_reg (reg, disp, base)
2985 int reg, disp, base;
2987 rtx insn, dest, src, basereg;
2989 src = gen_rtx_REG (word_mode, reg);
2990 basereg = gen_rtx_REG (Pmode, base);
2991 if (VAL_14_BITS_P (disp))
2993 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2994 insn = emit_move_insn (dest, src);
2998 rtx delta = GEN_INT (disp);
2999 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3000 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3001 emit_move_insn (tmpreg, high);
3002 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3003 insn = emit_move_insn (dest, src);
3007 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3008 gen_rtx_SET (VOIDmode,
3009 gen_rtx_MEM (word_mode,
3010 gen_rtx_PLUS (word_mode, basereg,
3018 RTX_FRAME_RELATED_P (insn) = 1;
3021 /* Emit RTL to store REG at the memory location specified by BASE and then
3022 add MOD to BASE. MOD must be <= 8k. */
3025 store_reg_modify (base, reg, mod)
3028 rtx insn, basereg, srcreg, delta;
3030 if (! VAL_14_BITS_P (mod))
3033 basereg = gen_rtx_REG (Pmode, base);
3034 srcreg = gen_rtx_REG (word_mode, reg);
3035 delta = GEN_INT (mod);
3037 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3040 RTX_FRAME_RELATED_P (insn) = 1;
3042 /* RTX_FRAME_RELATED_P must be set on each frame related set
3043 in a parallel with more than one element. Don't set
3044 RTX_FRAME_RELATED_P in the first set if reg is temporary
3045 register 1. The effect of this operation is recorded in
3046 the initial copy. */
3049 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3050 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3054 /* The first element of a PARALLEL is always processed if it is
3055 a SET. Thus, we need an expression list for this case. */
3057 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3058 gen_rtx_SET (VOIDmode, basereg,
3059 gen_rtx_PLUS (word_mode, basereg, delta)),
3065 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3066 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3067 whether to add a frame note or not.
3069 In the DISP > 8k case, we leave the high part of the address in %r1.
3070 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3073 set_reg_plus_d (reg, base, disp, note)
3074 int reg, base, disp, note;
3078 if (VAL_14_BITS_P (disp))
3080 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3081 plus_constant (gen_rtx_REG (Pmode, base), disp));
3085 rtx basereg = gen_rtx_REG (Pmode, base);
3086 rtx delta = GEN_INT (disp);
3088 emit_move_insn (gen_rtx_REG (Pmode, 1),
3089 gen_rtx_PLUS (Pmode, basereg,
3090 gen_rtx_HIGH (Pmode, delta)));
3091 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3092 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3096 if (DO_FRAME_NOTES && note)
3097 RTX_FRAME_RELATED_P (insn) = 1;
3101 compute_frame_size (size, fregs_live)
3107 /* Space for frame pointer + filler. If any frame is allocated
3108 we need to add this in because of STARTING_FRAME_OFFSET.
3110 Similar code also appears in hppa_expand_prologue. Change both
3111 of them at the same time. */
3112 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
3114 /* If the current function calls __builtin_eh_return, then we need
3115 to allocate stack space for registers that will hold data for
3116 the exception handler. */
3117 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3121 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3123 fsize += i * UNITS_PER_WORD;
3126 /* Account for space used by the callee general register saves. */
3127 for (i = 18; i >= 3; i--)
3128 if (regs_ever_live[i])
3129 fsize += UNITS_PER_WORD;
3131 /* Round the stack. */
3132 fsize = (fsize + 7) & ~7;
3134 /* Account for space used by the callee floating point register saves. */
3135 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3136 if (regs_ever_live[i]
3137 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3142 /* We always save both halves of the FP register, so always
3143 increment the frame size by 8 bytes. */
3147 /* The various ABIs include space for the outgoing parameters in the
3148 size of the current function's stack frame. */
3149 fsize += current_function_outgoing_args_size;
3151 /* Allocate space for the fixed frame marker. This space must be
3152 allocated for any function that makes calls or otherwise allocates
3154 if (!current_function_is_leaf || fsize)
3155 fsize += TARGET_64BIT ? 16 : 32;
3157 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
3160 /* Generate the assembly code for function entry. FILE is a stdio
3161 stream to output the code to. SIZE is an int: how many units of
3162 temporary storage to allocate.
3164 Refer to the array `regs_ever_live' to determine which registers to
3165 save; `regs_ever_live[I]' is nonzero if register number I is ever
3166 used in the function. This function is responsible for knowing
3167 which registers should not be saved even if used. */
3169 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3170 of memory. If any fpu reg is used in the function, we allocate
3171 such a block here, at the bottom of the frame, just in case it's needed.
3173 If this function is a leaf procedure, then we may choose not
3174 to do a "save" insn. The decision about whether or not
3175 to do this is made in regclass.c. */
3178 pa_output_function_prologue (file, size)
3180 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3182 /* The function's label and associated .PROC must never be
3183 separated and must be output *after* any profiling declarations
3184 to avoid changing spaces/subspaces within a procedure. */
3185 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3186 fputs ("\t.PROC\n", file);
3188 /* hppa_expand_prologue does the dirty work now. We just need
3189 to output the assembler directives which denote the start
3191 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3192 if (regs_ever_live[2])
3193 fputs (",CALLS,SAVE_RP", file);
3195 fputs (",NO_CALLS", file);
3197 if (frame_pointer_needed)
3198 fputs (",SAVE_SP", file);
3200 /* Pass on information about the number of callee register saves
3201 performed in the prologue.
3203 The compiler is supposed to pass the highest register number
3204 saved, the assembler then has to adjust that number before
3205 entering it into the unwind descriptor (to account for any
3206 caller saved registers with lower register numbers than the
3207 first callee saved register). */
3209 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3212 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3214 fputs ("\n\t.ENTRY\n", file);
3216 /* If we're using GAS and SOM, and not using the portable runtime model,
3217 or function sections, then we don't need to accumulate the total number
3219 if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME)
3220 || flag_function_sections)
3221 total_code_bytes = 0;
3222 else if (INSN_ADDRESSES_SET_P ())
3224 unsigned long old_total = total_code_bytes;
3226 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_nonnote_insn ()));
3227 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3229 /* Be prepared to handle overflows. */
3230 if (old_total > total_code_bytes)
3231 total_code_bytes = -1;
3234 total_code_bytes = -1;
3236 remove_useless_addtr_insns (get_insns (), 0);
3240 hppa_expand_prologue ()
3242 int size = get_frame_size ();
3243 int merge_sp_adjust_with_store = 0;
3251 /* Allocate space for frame pointer + filler. If any frame is allocated
3252 we need to add this in because of STARTING_FRAME_OFFSET.
3254 Similar code also appears in compute_frame_size. Change both
3255 of them at the same time. */
3256 local_fsize = size + (size || frame_pointer_needed
3257 ? STARTING_FRAME_OFFSET : 0);
3259 actual_fsize = compute_frame_size (size, &save_fregs);
3261 /* Compute a few things we will use often. */
3262 tmpreg = gen_rtx_REG (word_mode, 1);
3264 /* Save RP first. The calling conventions manual states RP will
3265 always be stored into the caller's frame at sp - 20 or sp - 16
3266 depending on which ABI is in use. */
3267 if (regs_ever_live[2] || current_function_calls_eh_return)
3268 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3270 /* Allocate the local frame and set up the frame pointer if needed. */
3271 if (actual_fsize != 0)
3273 if (frame_pointer_needed)
3275 /* Copy the old frame pointer temporarily into %r1. Set up the
3276 new stack pointer, then store away the saved old frame pointer
3277 into the stack at sp and at the same time update the stack
3278 pointer by actual_fsize bytes. Two versions, first
3279 handles small (<8k) frames. The second handles large (>=8k)
3281 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3284 /* We need to record the frame pointer save here since the
3285 new frame pointer is set in the following insn. */
3286 RTX_FRAME_RELATED_P (insn) = 1;
3288 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3289 gen_rtx_SET (VOIDmode,
3290 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3295 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3297 RTX_FRAME_RELATED_P (insn) = 1;
3299 if (VAL_14_BITS_P (actual_fsize))
3300 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3303 /* It is incorrect to store the saved frame pointer at *sp,
3304 then increment sp (writes beyond the current stack boundary).
3306 So instead use stwm to store at *sp and post-increment the
3307 stack pointer as an atomic operation. Then increment sp to
3308 finish allocating the new frame. */
3309 int adjust1 = 8192 - 64;
3310 int adjust2 = actual_fsize - adjust1;
3312 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3313 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3317 /* Prevent register spills from being scheduled before the
3318 stack pointer is raised. Necessary as we will be storing
3319 registers using the frame pointer as a base register, and
3320 we happen to set fp before raising sp. */
3321 emit_insn (gen_blockage ());
3323 /* no frame pointer needed. */
3326 /* In some cases we can perform the first callee register save
3327 and allocating the stack frame at the same time. If so, just
3328 make a note of it and defer allocating the frame until saving
3329 the callee registers. */
3330 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3331 merge_sp_adjust_with_store = 1;
3332 /* Can not optimize. Adjust the stack frame by actual_fsize
3335 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3340 /* Normal register save.
3342 Do not save the frame pointer in the frame_pointer_needed case. It
3343 was done earlier. */
3344 if (frame_pointer_needed)
3346 offset = local_fsize;
3348 /* Saving the EH return data registers in the frame is the simplest
3349 way to get the frame unwind information emitted. We put them
3350 just before the general registers. */
3351 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3353 unsigned int i, regno;
3357 regno = EH_RETURN_DATA_REGNO (i);
3358 if (regno == INVALID_REGNUM)
3361 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3362 offset += UNITS_PER_WORD;
3366 for (i = 18; i >= 4; i--)
3367 if (regs_ever_live[i] && ! call_used_regs[i])
3369 store_reg (i, offset, FRAME_POINTER_REGNUM);
3370 offset += UNITS_PER_WORD;
3373 /* Account for %r3 which is saved in a special place. */
3376 /* No frame pointer needed. */
3379 offset = local_fsize - actual_fsize;
3381 /* Saving the EH return data registers in the frame is the simplest
3382 way to get the frame unwind information emitted. */
3383 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3385 unsigned int i, regno;
3389 regno = EH_RETURN_DATA_REGNO (i);
3390 if (regno == INVALID_REGNUM)
3393 /* If merge_sp_adjust_with_store is nonzero, then we can
3394 optimize the first save. */
3395 if (merge_sp_adjust_with_store)
3397 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3398 merge_sp_adjust_with_store = 0;
3401 store_reg (regno, offset, STACK_POINTER_REGNUM);
3402 offset += UNITS_PER_WORD;
3406 for (i = 18; i >= 3; i--)
3407 if (regs_ever_live[i] && ! call_used_regs[i])
3409 /* If merge_sp_adjust_with_store is nonzero, then we can
3410 optimize the first GR save. */
3411 if (merge_sp_adjust_with_store)
3413 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3414 merge_sp_adjust_with_store = 0;
3417 store_reg (i, offset, STACK_POINTER_REGNUM);
3418 offset += UNITS_PER_WORD;
3422 /* If we wanted to merge the SP adjustment with a GR save, but we never
3423 did any GR saves, then just emit the adjustment here. */
3424 if (merge_sp_adjust_with_store)
3425 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3429 /* The hppa calling conventions say that %r19, the pic offset
3430 register, is saved at sp - 32 (in this function's frame)
3431 when generating PIC code. FIXME: What is the correct thing
3432 to do for functions which make no calls and allocate no
3433 frame? Do we need to allocate a frame, or can we just omit
3434 the save? For now we'll just omit the save. */
3435 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3436 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3438 /* Align pointer properly (doubleword boundary). */
3439 offset = (offset + 7) & ~7;
3441 /* Floating point register store. */
3446 /* First get the frame or stack pointer to the start of the FP register
3448 if (frame_pointer_needed)
3450 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3451 base = frame_pointer_rtx;
3455 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3456 base = stack_pointer_rtx;
3459 /* Now actually save the FP registers. */
3460 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3462 if (regs_ever_live[i]
3463 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3465 rtx addr, insn, reg;
3466 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3467 reg = gen_rtx_REG (DFmode, i);
3468 insn = emit_move_insn (addr, reg);
3471 RTX_FRAME_RELATED_P (insn) = 1;
3474 rtx mem = gen_rtx_MEM (DFmode,
3475 plus_constant (base, offset));
3477 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3478 gen_rtx_SET (VOIDmode, mem, reg),
3483 rtx meml = gen_rtx_MEM (SFmode,
3484 plus_constant (base, offset));
3485 rtx memr = gen_rtx_MEM (SFmode,
3486 plus_constant (base, offset + 4));
3487 rtx regl = gen_rtx_REG (SFmode, i);
3488 rtx regr = gen_rtx_REG (SFmode, i + 1);
3489 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3490 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3493 RTX_FRAME_RELATED_P (setl) = 1;
3494 RTX_FRAME_RELATED_P (setr) = 1;
3495 vec = gen_rtvec (2, setl, setr);
3497 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3498 gen_rtx_SEQUENCE (VOIDmode, vec),
3502 offset += GET_MODE_SIZE (DFmode);
3508 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3509 prevent insns with frame notes being scheduled in the delay slot
3510 of calls. This causes problems because the dwarf2 output code
3511 processes the insn list serially. For now, limit the migration
3512 of prologue insns with a blockage. */
3514 emit_insn (gen_blockage ());
3517 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3518 Handle case where DISP > 8k by using the add_high_const patterns. */
3521 load_reg (reg, disp, base)
3522 int reg, disp, base;
3524 rtx src, dest, basereg;
3526 dest = gen_rtx_REG (word_mode, reg);
3527 basereg = gen_rtx_REG (Pmode, base);
3528 if (VAL_14_BITS_P (disp))
3530 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3531 emit_move_insn (dest, src);
3535 rtx delta = GEN_INT (disp);
3536 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3537 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3538 emit_move_insn (tmpreg, high);
3539 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3540 emit_move_insn (dest, src);
3544 /* This function generates the assembly code for function exit.
3545 Args are as for output_function_prologue ().
3547 The function epilogue should not depend on the current stack
3548 pointer! It should use the frame pointer only. This is mandatory
3549 because of alloca; we also take advantage of it to omit stack
3550 adjustments before returning. */
3553 pa_output_function_epilogue (file, size)
3555 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3557 rtx insn = get_last_insn ();
3559 /* hppa_expand_epilogue does the dirty work now. We just need
3560 to output the assembler directives which denote the end
3563 To make debuggers happy, emit a nop if the epilogue was completely
3564 eliminated due to a volatile call as the last insn in the
3565 current function. That way the return address (in %r2) will
3566 always point to a valid instruction in the current function. */
3568 /* Get the last real insn. */
3569 if (GET_CODE (insn) == NOTE)
3570 insn = prev_real_insn (insn);
3572 /* If it is a sequence, then look inside. */
3573 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3574 insn = XVECEXP (PATTERN (insn), 0, 0);
3576 /* If insn is a CALL_INSN, then it must be a call to a volatile
3577 function (otherwise there would be epilogue insns). */
3578 if (insn && GET_CODE (insn) == CALL_INSN)
3579 fputs ("\tnop\n", file);
3581 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3585 hppa_expand_epilogue ()
3589 int merge_sp_adjust_with_load = 0;
3592 /* We will use this often. */
3593 tmpreg = gen_rtx_REG (word_mode, 1);
3595 /* Try to restore RP early to avoid load/use interlocks when
3596 RP gets used in the return (bv) instruction. This appears to still
3597 be necessary even when we schedule the prologue and epilogue. */
3598 if (regs_ever_live [2] || current_function_calls_eh_return)
3600 ret_off = TARGET_64BIT ? -16 : -20;
3601 if (frame_pointer_needed)
3603 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3608 /* No frame pointer, and stack is smaller than 8k. */
3609 if (VAL_14_BITS_P (ret_off - actual_fsize))
3611 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3617 /* General register restores. */
3618 if (frame_pointer_needed)
3620 offset = local_fsize;
3622 /* If the current function calls __builtin_eh_return, then we need
3623 to restore the saved EH data registers. */
3624 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3626 unsigned int i, regno;
3630 regno = EH_RETURN_DATA_REGNO (i);
3631 if (regno == INVALID_REGNUM)
3634 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3635 offset += UNITS_PER_WORD;
3639 for (i = 18; i >= 4; i--)
3640 if (regs_ever_live[i] && ! call_used_regs[i])
3642 load_reg (i, offset, FRAME_POINTER_REGNUM);
3643 offset += UNITS_PER_WORD;
3648 offset = local_fsize - actual_fsize;
3650 /* If the current function calls __builtin_eh_return, then we need
3651 to restore the saved EH data registers. */
3652 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3654 unsigned int i, regno;
3658 regno = EH_RETURN_DATA_REGNO (i);
3659 if (regno == INVALID_REGNUM)
3662 /* Only for the first load.
3663 merge_sp_adjust_with_load holds the register load
3664 with which we will merge the sp adjustment. */
3665 if (merge_sp_adjust_with_load == 0
3667 && VAL_14_BITS_P (-actual_fsize))
3668 merge_sp_adjust_with_load = regno;
3670 load_reg (regno, offset, STACK_POINTER_REGNUM);
3671 offset += UNITS_PER_WORD;
3675 for (i = 18; i >= 3; i--)
3677 if (regs_ever_live[i] && ! call_used_regs[i])
3679 /* Only for the first load.
3680 merge_sp_adjust_with_load holds the register load
3681 with which we will merge the sp adjustment. */
3682 if (merge_sp_adjust_with_load == 0
3684 && VAL_14_BITS_P (-actual_fsize))
3685 merge_sp_adjust_with_load = i;
3687 load_reg (i, offset, STACK_POINTER_REGNUM);
3688 offset += UNITS_PER_WORD;
3693 /* Align pointer properly (doubleword boundary). */
3694 offset = (offset + 7) & ~7;
3696 /* FP register restores. */
3699 /* Adjust the register to index off of. */
3700 if (frame_pointer_needed)
3701 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3703 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3705 /* Actually do the restores now. */
3706 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3707 if (regs_ever_live[i]
3708 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3710 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3711 rtx dest = gen_rtx_REG (DFmode, i);
3712 emit_move_insn (dest, src);
3716 /* Emit a blockage insn here to keep these insns from being moved to
3717 an earlier spot in the epilogue, or into the main instruction stream.
3719 This is necessary as we must not cut the stack back before all the
3720 restores are finished. */
3721 emit_insn (gen_blockage ());
3723 /* Reset stack pointer (and possibly frame pointer). The stack
3724 pointer is initially set to fp + 64 to avoid a race condition. */
3725 if (frame_pointer_needed)
3727 rtx delta = GEN_INT (-64);
3729 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3730 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3732 /* If we were deferring a callee register restore, do it now. */
3733 else if (merge_sp_adjust_with_load)
3735 rtx delta = GEN_INT (-actual_fsize);
3736 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3738 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3740 else if (actual_fsize != 0)
3741 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3744 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3745 frame greater than 8k), do so now. */
3747 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3749 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3751 rtx sa = EH_RETURN_STACKADJ_RTX;
3753 emit_insn (gen_blockage ());
3754 emit_insn (TARGET_64BIT
3755 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3756 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3761 hppa_pic_save_rtx ()
3763 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3767 hppa_profile_hook (label_no)
3770 rtx begin_label_rtx, call_insn;
3771 char begin_label_name[16];
3773 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3775 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3778 emit_move_insn (arg_pointer_rtx,
3779 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3782 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3784 #ifndef NO_PROFILE_COUNTERS
3786 rtx count_label_rtx, addr, r24;
3787 char count_label_name[16];
3789 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3790 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3792 addr = force_reg (Pmode, count_label_rtx);
3793 r24 = gen_rtx_REG (Pmode, 24);
3794 emit_move_insn (r24, addr);
3796 /* %r25 is set from within the output pattern. */
3798 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3799 GEN_INT (TARGET_64BIT ? 24 : 12),
3802 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3805 /* %r25 is set from within the output pattern. */
3807 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3808 GEN_INT (TARGET_64BIT ? 16 : 8),
3812 /* Indicate the _mcount call cannot throw, nor will it execute a
3814 REG_NOTES (call_insn)
3815 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3819 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3821 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3823 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3827 /* Fetch the return address for the frame COUNT steps up from
3828 the current frame, after the prologue. FRAMEADDR is the
3829 frame pointer of the COUNT frame.
3831 We want to ignore any export stub remnants here. To handle this,
3832 we examine the code at the return address, and if it is an export
3833 stub, we return a memory rtx for the stub return address stored
3836 The value returned is used in two different ways:
3838 1. To find a function's caller.
3840 2. To change the return address for a function.
3842 This function handles most instances of case 1; however, it will
3843 fail if there are two levels of stubs to execute on the return
3844 path. The only way I believe that can happen is if the return value
3845 needs a parameter relocation, which never happens for C code.
3847 This function handles most instances of case 2; however, it will
3848 fail if we did not originally have stub code on the return path
3849 but will need stub code on the new return path. This can happen if
3850 the caller & callee are both in the main program, but the new
3851 return location is in a shared library. */
3854 return_addr_rtx (count, frameaddr)
3866 rp = get_hard_reg_initial_val (Pmode, 2);
3868 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3871 saved_rp = gen_reg_rtx (Pmode);
3872 emit_move_insn (saved_rp, rp);
3874 /* Get pointer to the instruction stream. We have to mask out the
3875 privilege level from the two low order bits of the return address
3876 pointer here so that ins will point to the start of the first
3877 instruction that would have been executed if we returned. */
3878 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3879 label = gen_label_rtx ();
3881 /* Check the instruction stream at the normal return address for the
3884 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3885 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3886 0x00011820 | stub+16: mtsp r1,sr0
3887 0xe0400002 | stub+20: be,n 0(sr0,rp)
3889 If it is an export stub, than our return address is really in
3892 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3893 NULL_RTX, SImode, 1);
3894 emit_jump_insn (gen_bne (label));
3896 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3897 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3898 emit_jump_insn (gen_bne (label));
3900 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3901 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3902 emit_jump_insn (gen_bne (label));
3904 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3905 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3907 /* If there is no export stub then just use the value saved from
3908 the return pointer register. */
3910 emit_jump_insn (gen_bne (label));
3912 /* Here we know that our return address points to an export
3913 stub. We don't want to return the address of the export stub,
3914 but rather the return address of the export stub. That return
3915 address is stored at -24[frameaddr]. */
3917 emit_move_insn (saved_rp,
3919 memory_address (Pmode,
3920 plus_constant (frameaddr,
3927 /* This is only valid once reload has completed because it depends on
3928 knowing exactly how much (if any) frame there is and...
3930 It's only valid if there is no frame marker to de-allocate and...
3932 It's only valid if %r2 hasn't been saved into the caller's frame
3933 (we're not profiling and %r2 isn't live anywhere). */
3935 hppa_can_use_return_insn_p ()
3937 return (reload_completed
3938 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3939 && ! regs_ever_live[2]
3940 && ! frame_pointer_needed);
3944 emit_bcond_fp (code, operand0)
3948 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3949 gen_rtx_IF_THEN_ELSE (VOIDmode,
3950 gen_rtx_fmt_ee (code,
3952 gen_rtx_REG (CCFPmode, 0),
3954 gen_rtx_LABEL_REF (VOIDmode, operand0),
3960 gen_cmp_fp (code, operand0, operand1)
3962 rtx operand0, operand1;
3964 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3965 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3968 /* Adjust the cost of a scheduling dependency. Return the new cost of
3969 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3972 pa_adjust_cost (insn, link, dep_insn, cost)
3978 enum attr_type attr_type;
3980 /* Don't adjust costs for a pa8000 chip, also do not adjust any
3981 true dependencies as they are described with bypasses now. */
3982 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
3985 if (! recog_memoized (insn))
3988 attr_type = get_attr_type (insn);
3990 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3992 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3995 if (attr_type == TYPE_FPLOAD)
3997 rtx pat = PATTERN (insn);
3998 rtx dep_pat = PATTERN (dep_insn);
3999 if (GET_CODE (pat) == PARALLEL)
4001 /* This happens for the fldXs,mb patterns. */
4002 pat = XVECEXP (pat, 0, 0);
4004 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4005 /* If this happens, we have to extend this to schedule
4006 optimally. Return 0 for now. */
4009 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4011 if (! recog_memoized (dep_insn))
4013 switch (get_attr_type (dep_insn))
4020 case TYPE_FPSQRTSGL:
4021 case TYPE_FPSQRTDBL:
4022 /* A fpload can't be issued until one cycle before a
4023 preceding arithmetic operation has finished if
4024 the target of the fpload is any of the sources
4025 (or destination) of the arithmetic operation. */
4026 return insn_default_latency (dep_insn) - 1;
4033 else if (attr_type == TYPE_FPALU)
4035 rtx pat = PATTERN (insn);
4036 rtx dep_pat = PATTERN (dep_insn);
4037 if (GET_CODE (pat) == PARALLEL)
4039 /* This happens for the fldXs,mb patterns. */
4040 pat = XVECEXP (pat, 0, 0);
4042 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4043 /* If this happens, we have to extend this to schedule
4044 optimally. Return 0 for now. */
4047 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4049 if (! recog_memoized (dep_insn))
4051 switch (get_attr_type (dep_insn))
4055 case TYPE_FPSQRTSGL:
4056 case TYPE_FPSQRTDBL:
4057 /* An ALU flop can't be issued until two cycles before a
4058 preceding divide or sqrt operation has finished if
4059 the target of the ALU flop is any of the sources
4060 (or destination) of the divide or sqrt operation. */
4061 return insn_default_latency (dep_insn) - 2;
4069 /* For other anti dependencies, the cost is 0. */
4072 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4074 /* Output dependency; DEP_INSN writes a register that INSN writes some
4076 if (attr_type == TYPE_FPLOAD)
4078 rtx pat = PATTERN (insn);
4079 rtx dep_pat = PATTERN (dep_insn);
4080 if (GET_CODE (pat) == PARALLEL)
4082 /* This happens for the fldXs,mb patterns. */
4083 pat = XVECEXP (pat, 0, 0);
4085 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4086 /* If this happens, we have to extend this to schedule
4087 optimally. Return 0 for now. */
4090 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4092 if (! recog_memoized (dep_insn))
4094 switch (get_attr_type (dep_insn))
4101 case TYPE_FPSQRTSGL:
4102 case TYPE_FPSQRTDBL:
4103 /* A fpload can't be issued until one cycle before a
4104 preceding arithmetic operation has finished if
4105 the target of the fpload is the destination of the
4106 arithmetic operation.
4108 Exception: For PA7100LC, PA7200 and PA7300, the cost
4109 is 3 cycles, unless they bundle together. We also
4110 pay the penalty if the second insn is a fpload. */
4111 return insn_default_latency (dep_insn) - 1;
4118 else if (attr_type == TYPE_FPALU)
4120 rtx pat = PATTERN (insn);
4121 rtx dep_pat = PATTERN (dep_insn);
4122 if (GET_CODE (pat) == PARALLEL)
4124 /* This happens for the fldXs,mb patterns. */
4125 pat = XVECEXP (pat, 0, 0);
4127 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4128 /* If this happens, we have to extend this to schedule
4129 optimally. Return 0 for now. */
4132 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4134 if (! recog_memoized (dep_insn))
4136 switch (get_attr_type (dep_insn))
4140 case TYPE_FPSQRTSGL:
4141 case TYPE_FPSQRTDBL:
4142 /* An ALU flop can't be issued until two cycles before a
4143 preceding divide or sqrt operation has finished if
4144 the target of the ALU flop is also the target of
4145 the divide or sqrt operation. */
4146 return insn_default_latency (dep_insn) - 2;
4154 /* For other output dependencies, the cost is 0. */
4161 /* Adjust scheduling priorities. We use this to try and keep addil
4162 and the next use of %r1 close together. */
4164 pa_adjust_priority (insn, priority)
4168 rtx set = single_set (insn);
4172 src = SET_SRC (set);
4173 dest = SET_DEST (set);
4174 if (GET_CODE (src) == LO_SUM
4175 && symbolic_operand (XEXP (src, 1), VOIDmode)
4176 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4179 else if (GET_CODE (src) == MEM
4180 && GET_CODE (XEXP (src, 0)) == LO_SUM
4181 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4182 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4185 else if (GET_CODE (dest) == MEM
4186 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4187 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4188 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4194 /* The 700 can only issue a single insn at a time.
4195 The 7XXX processors can issue two insns at a time.
4196 The 8000 can issue 4 insns at a time. */
4202 case PROCESSOR_700: return 1;
4203 case PROCESSOR_7100: return 2;
4204 case PROCESSOR_7100LC: return 2;
4205 case PROCESSOR_7200: return 2;
4206 case PROCESSOR_7300: return 2;
4207 case PROCESSOR_8000: return 4;
4216 /* Return any length adjustment needed by INSN which already has its length
4217 computed as LENGTH. Return zero if no adjustment is necessary.
4219 For the PA: function calls, millicode calls, and backwards short
4220 conditional branches with unfilled delay slots need an adjustment by +1
4221 (to account for the NOP which will be inserted into the instruction stream).
4223 Also compute the length of an inline block move here as it is too
4224 complicated to express as a length attribute in pa.md. */
4226 pa_adjust_insn_length (insn, length)
4230 rtx pat = PATTERN (insn);
4232 /* Call insns which are *not* indirect and have unfilled delay slots. */
4233 if (GET_CODE (insn) == CALL_INSN)
4236 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4237 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4239 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4240 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4246 /* Jumps inside switch tables which have unfilled delay slots
4247 also need adjustment. */
4248 else if (GET_CODE (insn) == JUMP_INSN
4249 && simplejump_p (insn)
4250 && GET_MODE (insn) == SImode)
4252 /* Millicode insn with an unfilled delay slot. */
4253 else if (GET_CODE (insn) == INSN
4254 && GET_CODE (pat) != SEQUENCE
4255 && GET_CODE (pat) != USE
4256 && GET_CODE (pat) != CLOBBER
4257 && get_attr_type (insn) == TYPE_MILLI)
4259 /* Block move pattern. */
4260 else if (GET_CODE (insn) == INSN
4261 && GET_CODE (pat) == PARALLEL
4262 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4263 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4264 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4265 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4266 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4267 return compute_movstrsi_length (insn) - 4;
4268 /* Conditional branch with an unfilled delay slot. */
4269 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4271 /* Adjust a short backwards conditional with an unfilled delay slot. */
4272 if (GET_CODE (pat) == SET
4274 && ! forward_branch_p (insn))
4276 else if (GET_CODE (pat) == PARALLEL
4277 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4280 /* Adjust dbra insn with short backwards conditional branch with
4281 unfilled delay slot -- only for case where counter is in a
4282 general register register. */
4283 else if (GET_CODE (pat) == PARALLEL
4284 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4285 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4286 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4288 && ! forward_branch_p (insn))
4296 /* Print operand X (an rtx) in assembler syntax to file FILE.
4297 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4298 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4301 print_operand (file, x, code)
4309 /* Output a 'nop' if there's nothing for the delay slot. */
4310 if (dbr_sequence_length () == 0)
4311 fputs ("\n\tnop", file);
4314 /* Output a nullification completer if there's nothing for the */
4315 /* delay slot or nullification is requested. */
4316 if (dbr_sequence_length () == 0 ||
4318 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4322 /* Print out the second register name of a register pair.
4323 I.e., R (6) => 7. */
4324 fputs (reg_names[REGNO (x) + 1], file);
4327 /* A register or zero. */
4329 || (x == CONST0_RTX (DFmode))
4330 || (x == CONST0_RTX (SFmode)))
4332 fputs ("%r0", file);
4338 /* A register or zero (floating point). */
4340 || (x == CONST0_RTX (DFmode))
4341 || (x == CONST0_RTX (SFmode)))
4343 fputs ("%fr0", file);
4352 xoperands[0] = XEXP (XEXP (x, 0), 0);
4353 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4354 output_global_address (file, xoperands[1], 0);
4355 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4359 case 'C': /* Plain (C)ondition */
4361 switch (GET_CODE (x))
4364 fputs ("=", file); break;
4366 fputs ("<>", file); break;
4368 fputs (">", file); break;
4370 fputs (">=", file); break;
4372 fputs (">>=", file); break;
4374 fputs (">>", file); break;
4376 fputs ("<", file); break;
4378 fputs ("<=", file); break;
4380 fputs ("<<=", file); break;
4382 fputs ("<<", file); break;
4387 case 'N': /* Condition, (N)egated */
4388 switch (GET_CODE (x))
4391 fputs ("<>", file); break;
4393 fputs ("=", file); break;
4395 fputs ("<=", file); break;
4397 fputs ("<", file); break;
4399 fputs ("<<", file); break;
4401 fputs ("<<=", file); break;
4403 fputs (">=", file); break;
4405 fputs (">", file); break;
4407 fputs (">>", file); break;
4409 fputs (">>=", file); break;
4414 /* For floating point comparisons. Note that the output
4415 predicates are the complement of the desired mode. */
4417 switch (GET_CODE (x))
4420 fputs ("!=", file); break;
4422 fputs ("=", file); break;
4424 fputs ("!>", file); break;
4426 fputs ("!>=", file); break;
4428 fputs ("!<", file); break;
4430 fputs ("!<=", file); break;
4432 fputs ("!<>", file); break;
4434 fputs (">", file); break;
4436 fputs (">=", file); break;
4438 fputs ("<", file); break;
4440 fputs ("<=", file); break;
4442 fputs ("<>", file); break;
4444 fputs ("<=>", file); break;
4446 fputs ("!<=>", file); break;
4451 case 'S': /* Condition, operands are (S)wapped. */
4452 switch (GET_CODE (x))
4455 fputs ("=", file); break;
4457 fputs ("<>", file); break;
4459 fputs ("<", file); break;
4461 fputs ("<=", file); break;
4463 fputs ("<<=", file); break;
4465 fputs ("<<", file); break;
4467 fputs (">", file); break;
4469 fputs (">=", file); break;
4471 fputs (">>=", file); break;
4473 fputs (">>", file); break;
4478 case 'B': /* Condition, (B)oth swapped and negate. */
4479 switch (GET_CODE (x))
4482 fputs ("<>", file); break;
4484 fputs ("=", file); break;
4486 fputs (">=", file); break;
4488 fputs (">", file); break;
4490 fputs (">>", file); break;
4492 fputs (">>=", file); break;
4494 fputs ("<=", file); break;
4496 fputs ("<", file); break;
4498 fputs ("<<", file); break;
4500 fputs ("<<=", file); break;
4506 if (GET_CODE (x) == CONST_INT)
4508 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4513 if (GET_CODE (x) == CONST_INT)
4515 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4520 if (GET_CODE (x) == CONST_INT)
4522 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4527 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4529 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4534 if (GET_CODE (x) == CONST_INT)
4536 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4541 if (GET_CODE (x) == CONST_INT)
4543 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4548 if (GET_CODE (x) == CONST_INT)
4553 switch (GET_CODE (XEXP (x, 0)))
4557 if (ASSEMBLER_DIALECT == 0)
4558 fputs ("s,mb", file);
4560 fputs (",mb", file);
4564 if (ASSEMBLER_DIALECT == 0)
4565 fputs ("s,ma", file);
4567 fputs (",ma", file);
4570 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4571 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4573 if (ASSEMBLER_DIALECT == 0)
4574 fputs ("x,s", file);
4578 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4582 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4588 output_global_address (file, x, 0);
4591 output_global_address (file, x, 1);
4593 case 0: /* Don't do anything special */
4598 compute_zdepwi_operands (INTVAL (x), op);
4599 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4605 compute_zdepdi_operands (INTVAL (x), op);
4606 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4610 /* We can get here from a .vtable_inherit due to our
4611 CONSTANT_ADDRESS_P rejecting perfectly good constant
4617 if (GET_CODE (x) == REG)
4619 fputs (reg_names [REGNO (x)], file);
4620 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4626 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4627 && (REGNO (x) & 1) == 0)
4630 else if (GET_CODE (x) == MEM)
4632 int size = GET_MODE_SIZE (GET_MODE (x));
4633 rtx base = NULL_RTX;
4634 switch (GET_CODE (XEXP (x, 0)))
4638 base = XEXP (XEXP (x, 0), 0);
4639 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4643 base = XEXP (XEXP (x, 0), 0);
4644 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4647 if (GET_CODE (XEXP (x, 0)) == PLUS
4648 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4649 fprintf (file, "%s(%s)",
4650 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4651 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4652 else if (GET_CODE (XEXP (x, 0)) == PLUS
4653 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4654 fprintf (file, "%s(%s)",
4655 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4656 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4658 output_address (XEXP (x, 0));
4663 output_addr_const (file, x);
4666 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4669 output_global_address (file, x, round_constant)
4675 /* Imagine (high (const (plus ...))). */
4676 if (GET_CODE (x) == HIGH)
4679 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4680 assemble_name (file, XSTR (x, 0));
4681 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4683 assemble_name (file, XSTR (x, 0));
4684 fputs ("-$global$", file);
4686 else if (GET_CODE (x) == CONST)
4688 const char *sep = "";
4689 int offset = 0; /* assembler wants -$global$ at end */
4690 rtx base = NULL_RTX;
4692 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4694 base = XEXP (XEXP (x, 0), 0);
4695 output_addr_const (file, base);
4697 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4698 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4701 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4703 base = XEXP (XEXP (x, 0), 1);
4704 output_addr_const (file, base);
4706 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4707 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4710 /* How bogus. The compiler is apparently responsible for
4711 rounding the constant if it uses an LR field selector.
4713 The linker and/or assembler seem a better place since
4714 they have to do this kind of thing already.
4716 If we fail to do this, HP's optimizing linker may eliminate
4717 an addil, but not update the ldw/stw/ldo instruction that
4718 uses the result of the addil. */
4720 offset = ((offset + 0x1000) & ~0x1fff);
4722 if (GET_CODE (XEXP (x, 0)) == PLUS)
4732 else if (GET_CODE (XEXP (x, 0)) == MINUS
4733 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4737 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4738 fputs ("-$global$", file);
4740 fprintf (file, "%s%d", sep, offset);
4743 output_addr_const (file, x);
4746 static struct deferred_plabel *
4752 /* See if we have already put this function on the list of deferred
4753 plabels. This list is generally small, so a liner search is not
4754 too ugly. If it proves too slow replace it with something faster. */
4755 for (i = 0; i < n_deferred_plabels; i++)
4756 if (strcmp (fname, deferred_plabels[i].name) == 0)
4759 /* If the deferred plabel list is empty, or this entry was not found
4760 on the list, create a new entry on the list. */
4761 if (deferred_plabels == NULL || i == n_deferred_plabels)
4763 const char *real_name;
4765 if (deferred_plabels == 0)
4766 deferred_plabels = (struct deferred_plabel *)
4767 ggc_alloc (sizeof (struct deferred_plabel));
4769 deferred_plabels = (struct deferred_plabel *)
4770 ggc_realloc (deferred_plabels,
4771 ((n_deferred_plabels + 1)
4772 * sizeof (struct deferred_plabel)));
4774 i = n_deferred_plabels++;
4775 deferred_plabels[i].internal_label = gen_label_rtx ();
4776 deferred_plabels[i].name = ggc_strdup (fname);
4778 /* Gross. We have just implicitly taken the address of this function,
4780 real_name = (*targetm.strip_name_encoding) (fname);
4781 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
4784 return &deferred_plabels[i];
4788 output_deferred_plabels (file)
4792 /* If we have deferred plabels, then we need to switch into the data
4793 section and align it to a 4 byte boundary before we output the
4794 deferred plabels. */
4795 if (n_deferred_plabels)
4798 ASM_OUTPUT_ALIGN (file, TARGET_64BIT ? 3 : 2);
4801 /* Now output the deferred plabels. */
4802 for (i = 0; i < n_deferred_plabels; i++)
4804 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4805 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4806 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4810 /* HP's millicode routines mean something special to the assembler.
4811 Keep track of which ones we have used. */
4813 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
4814 static void import_milli PARAMS ((enum millicodes));
4815 static char imported[(int) end1000];
4816 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
4817 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4818 #define MILLI_START 10
4822 enum millicodes code;
4824 char str[sizeof (import_string)];
4826 if (!imported[(int) code])
4828 imported[(int) code] = 1;
4829 strcpy (str, import_string);
4830 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4831 output_asm_insn (str, 0);
4835 /* The register constraints have put the operands and return value in
4836 the proper registers. */
4839 output_mul_insn (unsignedp, insn)
4840 int unsignedp ATTRIBUTE_UNUSED;
4843 import_milli (mulI);
4844 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4847 /* Emit the rtl for doing a division by a constant. */
4849 /* Do magic division millicodes exist for this value? */
4850 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4853 /* We'll use an array to keep track of the magic millicodes and
4854 whether or not we've used them already. [n][0] is signed, [n][1] is
4857 static int div_milli[16][2];
4860 div_operand (op, mode)
4862 enum machine_mode mode;
4864 return (mode == SImode
4865 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4866 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4867 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4871 emit_hpdiv_const (operands, unsignedp)
4875 if (GET_CODE (operands[2]) == CONST_INT
4876 && INTVAL (operands[2]) > 0
4877 && INTVAL (operands[2]) < 16
4878 && magic_milli[INTVAL (operands[2])])
4880 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4882 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4885 (PARALLEL, VOIDmode,
4886 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4887 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4889 gen_rtx_REG (SImode, 26),
4891 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4892 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4893 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4894 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4895 gen_rtx_CLOBBER (VOIDmode, ret))));
4896 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4903 output_div_insn (operands, unsignedp, insn)
4910 /* If the divisor is a constant, try to use one of the special
4912 if (GET_CODE (operands[0]) == CONST_INT)
4914 static char buf[100];
4915 divisor = INTVAL (operands[0]);
4916 if (!div_milli[divisor][unsignedp])
4918 div_milli[divisor][unsignedp] = 1;
4920 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4922 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4926 sprintf (buf, "$$divU_");
4927 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4928 return output_millicode_call (insn,
4929 gen_rtx_SYMBOL_REF (SImode, buf));
4933 sprintf (buf, "$$divI_");
4934 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4935 return output_millicode_call (insn,
4936 gen_rtx_SYMBOL_REF (SImode, buf));
4939 /* Divisor isn't a special constant. */
4944 import_milli (divU);
4945 return output_millicode_call (insn,
4946 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4950 import_milli (divI);
4951 return output_millicode_call (insn,
4952 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4957 /* Output a $$rem millicode to do mod. */
4960 output_mod_insn (unsignedp, insn)
4966 import_milli (remU);
4967 return output_millicode_call (insn,
4968 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4972 import_milli (remI);
4973 return output_millicode_call (insn,
4974 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4979 output_arg_descriptor (call_insn)
4982 const char *arg_regs[4];
4983 enum machine_mode arg_mode;
4985 int i, output_flag = 0;
4988 /* We neither need nor want argument location descriptors for the
4989 64bit runtime environment or the ELF32 environment. */
4990 if (TARGET_64BIT || TARGET_ELF32)
4993 for (i = 0; i < 4; i++)
4996 /* Specify explicitly that no argument relocations should take place
4997 if using the portable runtime calling conventions. */
4998 if (TARGET_PORTABLE_RUNTIME)
5000 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5005 if (GET_CODE (call_insn) != CALL_INSN)
5007 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5009 rtx use = XEXP (link, 0);
5011 if (! (GET_CODE (use) == USE
5012 && GET_CODE (XEXP (use, 0)) == REG
5013 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5016 arg_mode = GET_MODE (XEXP (use, 0));
5017 regno = REGNO (XEXP (use, 0));
5018 if (regno >= 23 && regno <= 26)
5020 arg_regs[26 - regno] = "GR";
5021 if (arg_mode == DImode)
5022 arg_regs[25 - regno] = "GR";
5024 else if (regno >= 32 && regno <= 39)
5026 if (arg_mode == SFmode)
5027 arg_regs[(regno - 32) / 2] = "FR";
5030 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5031 arg_regs[(regno - 34) / 2] = "FR";
5032 arg_regs[(regno - 34) / 2 + 1] = "FU";
5034 arg_regs[(regno - 34) / 2] = "FU";
5035 arg_regs[(regno - 34) / 2 + 1] = "FR";
5040 fputs ("\t.CALL ", asm_out_file);
5041 for (i = 0; i < 4; i++)
5046 fputc (',', asm_out_file);
5047 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5050 fputc ('\n', asm_out_file);
5053 /* Return the class of any secondary reload register that is needed to
5054 move IN into a register in class CLASS using mode MODE.
5056 Profiling has showed this routine and its descendants account for
5057 a significant amount of compile time (~7%). So it has been
5058 optimized to reduce redundant computations and eliminate useless
5061 It might be worthwhile to try and make this a leaf function too. */
5064 secondary_reload_class (class, mode, in)
5065 enum reg_class class;
5066 enum machine_mode mode;
5069 int regno, is_symbolic;
5071 /* Trying to load a constant into a FP register during PIC code
5072 generation will require %r1 as a scratch register. */
5074 && GET_MODE_CLASS (mode) == MODE_INT
5075 && FP_REG_CLASS_P (class)
5076 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5079 /* Profiling showed the PA port spends about 1.3% of its compilation
5080 time in true_regnum from calls inside secondary_reload_class. */
5082 if (GET_CODE (in) == REG)
5085 if (regno >= FIRST_PSEUDO_REGISTER)
5086 regno = true_regnum (in);
5088 else if (GET_CODE (in) == SUBREG)
5089 regno = true_regnum (in);
5093 /* If we have something like (mem (mem (...)), we can safely assume the
5094 inner MEM will end up in a general register after reloading, so there's
5095 no need for a secondary reload. */
5096 if (GET_CODE (in) == MEM
5097 && GET_CODE (XEXP (in, 0)) == MEM)
5100 /* Handle out of range displacement for integer mode loads/stores of
5102 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5103 && GET_MODE_CLASS (mode) == MODE_INT
5104 && FP_REG_CLASS_P (class))
5105 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5106 return GENERAL_REGS;
5108 /* A SAR<->FP register copy requires a secondary register (GPR) as
5109 well as secondary memory. */
5110 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5111 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5112 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5113 return GENERAL_REGS;
5115 if (GET_CODE (in) == HIGH)
5118 /* Profiling has showed GCC spends about 2.6% of its compilation
5119 time in symbolic_operand from calls inside secondary_reload_class.
5121 We use an inline copy and only compute its return value once to avoid
5123 switch (GET_CODE (in))
5133 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5134 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5135 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5145 && read_only_operand (in, VOIDmode))
5148 if (class != R1_REGS && is_symbolic)
5155 function_arg_padding (mode, type)
5156 enum machine_mode mode;
5160 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5162 /* Return none if justification is not required. */
5164 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5165 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5168 /* The directions set here are ignored when a BLKmode argument larger
5169 than a word is placed in a register. Different code is used for
5170 the stack and registers. This makes it difficult to have a
5171 consistent data representation for both the stack and registers.
5172 For both runtimes, the justification and padding for arguments on
5173 the stack and in registers should be identical. */
5175 /* The 64-bit runtime specifies left justification for aggregates. */
5178 /* The 32-bit runtime architecture specifies right justification.
5179 When the argument is passed on the stack, the argument is padded
5180 with garbage on the left. The HP compiler pads with zeros. */
5184 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5191 /* Do what is necessary for `va_start'. We look at the current function
5192 to determine if stdargs or varargs is used and fill in an initial
5193 va_list. A pointer to this constructor is returned. */
5196 hppa_builtin_saveregs ()
5199 tree fntype = TREE_TYPE (current_function_decl);
5200 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5201 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5202 != void_type_node)))
5203 ? UNITS_PER_WORD : 0);
5206 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5208 offset = current_function_arg_offset_rtx;
5214 /* Adjust for varargs/stdarg differences. */
5216 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5218 offset = current_function_arg_offset_rtx;
5220 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5221 from the incoming arg pointer and growing to larger addresses. */
5222 for (i = 26, off = -64; i >= 19; i--, off += 8)
5223 emit_move_insn (gen_rtx_MEM (word_mode,
5224 plus_constant (arg_pointer_rtx, off)),
5225 gen_rtx_REG (word_mode, i));
5227 /* The incoming args pointer points just beyond the flushback area;
5228 normally this is not a serious concern. However, when we are doing
5229 varargs/stdargs we want to make the arg pointer point to the start
5230 of the incoming argument area. */
5231 emit_move_insn (virtual_incoming_args_rtx,
5232 plus_constant (arg_pointer_rtx, -64));
5234 /* Now return a pointer to the first anonymous argument. */
5235 return copy_to_reg (expand_binop (Pmode, add_optab,
5236 virtual_incoming_args_rtx,
5237 offset, 0, 0, OPTAB_LIB_WIDEN));
5240 /* Store general registers on the stack. */
5241 dest = gen_rtx_MEM (BLKmode,
5242 plus_constant (current_function_internal_arg_pointer,
5244 set_mem_alias_set (dest, get_varargs_alias_set ());
5245 set_mem_align (dest, BITS_PER_WORD);
5246 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5248 /* move_block_from_reg will emit code to store the argument registers
5249 individually as scalar stores.
5251 However, other insns may later load from the same addresses for
5252 a structure load (passing a struct to a varargs routine).
5254 The alias code assumes that such aliasing can never happen, so we
5255 have to keep memory referencing insns from moving up beyond the
5256 last argument register store. So we emit a blockage insn here. */
5257 emit_insn (gen_blockage ());
5259 return copy_to_reg (expand_binop (Pmode, add_optab,
5260 current_function_internal_arg_pointer,
5261 offset, 0, 0, OPTAB_LIB_WIDEN));
5265 hppa_va_start (valist, nextarg)
5269 nextarg = expand_builtin_saveregs ();
5270 std_expand_builtin_va_start (valist, nextarg);
5274 hppa_va_arg (valist, type)
5277 HOST_WIDE_INT size = int_size_in_bytes (type);
5283 /* Every argument in PA64 is supposed to be passed by value
5284 (including large structs). However, as a GCC extension, we
5285 pass zero and variable sized arguments by reference. Empty
5286 structures are a GCC extension not supported by the HP
5287 compilers. Thus, passing them by reference isn't likely
5288 to conflict with the ABI. For variable sized arguments,
5289 GCC doesn't have the infrastructure to allocate these to
5292 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5294 if (size > UNITS_PER_WORD)
5296 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5297 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5298 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5299 build_int_2 (-2 * UNITS_PER_WORD, -1));
5300 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5301 TREE_SIDE_EFFECTS (t) = 1;
5302 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5306 return std_expand_builtin_va_arg (valist, type);
5309 ptr = build_pointer_type (type);
5311 /* Args grow upward. */
5312 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5313 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5314 TREE_SIDE_EFFECTS (t) = 1;
5316 pptr = build_pointer_type (ptr);
5317 t = build1 (NOP_EXPR, pptr, t);
5318 TREE_SIDE_EFFECTS (t) = 1;
5320 t = build1 (INDIRECT_REF, ptr, t);
5321 TREE_SIDE_EFFECTS (t) = 1;
5324 else /* !TARGET_64BIT */
5326 ptr = build_pointer_type (type);
5328 /* "Large" and variable sized types are passed by reference. */
5329 if (size > 8 || size <= 0)
5331 /* Args grow downward. */
5332 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5333 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5334 TREE_SIDE_EFFECTS (t) = 1;
5336 pptr = build_pointer_type (ptr);
5337 t = build1 (NOP_EXPR, pptr, t);
5338 TREE_SIDE_EFFECTS (t) = 1;
5340 t = build1 (INDIRECT_REF, ptr, t);
5341 TREE_SIDE_EFFECTS (t) = 1;
5345 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5346 build_int_2 (-size, -1));
5348 /* Copied from va-pa.h, but we probably don't need to align to
5349 word size, since we generate and preserve that invariant. */
5350 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5351 build_int_2 ((size > 4 ? -8 : -4), -1));
5353 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5354 TREE_SIDE_EFFECTS (t) = 1;
5356 ofs = (8 - size) % 4;
5359 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
5360 build_int_2 (ofs, 0));
5361 TREE_SIDE_EFFECTS (t) = 1;
5364 t = build1 (NOP_EXPR, ptr, t);
5365 TREE_SIDE_EFFECTS (t) = 1;
5370 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
5375 /* This routine handles all the normal conditional branch sequences we
5376 might need to generate. It handles compare immediate vs compare
5377 register, nullification of delay slots, varying length branches,
5378 negated branches, and all combinations of the above. It returns the
5379 output appropriate to emit the branch corresponding to all given
5383 output_cbranch (operands, nullify, length, negated, insn)
5385 int nullify, length, negated;
5388 static char buf[100];
5391 /* A conditional branch to the following instruction (eg the delay slot) is
5392 asking for a disaster. This can happen when not optimizing.
5394 In such cases it is safe to emit nothing. */
5396 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5399 /* If this is a long branch with its delay slot unfilled, set `nullify'
5400 as it can nullify the delay slot and save a nop. */
5401 if (length == 8 && dbr_sequence_length () == 0)
5404 /* If this is a short forward conditional branch which did not get
5405 its delay slot filled, the delay slot can still be nullified. */
5406 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5407 nullify = forward_branch_p (insn);
5409 /* A forward branch over a single nullified insn can be done with a
5410 comclr instruction. This avoids a single cycle penalty due to
5411 mis-predicted branch if we fall through (branch not taken). */
5413 && next_real_insn (insn) != 0
5414 && get_attr_length (next_real_insn (insn)) == 4
5415 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5421 /* All short conditional branches except backwards with an unfilled
5425 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5427 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5428 if (GET_MODE (operands[1]) == DImode)
5431 strcat (buf, "%B3");
5433 strcat (buf, "%S3");
5435 strcat (buf, " %2,%r1,%%r0");
5437 strcat (buf, ",n %2,%r1,%0");
5439 strcat (buf, " %2,%r1,%0");
5442 /* All long conditionals. Note a short backward branch with an
5443 unfilled delay slot is treated just like a long backward branch
5444 with an unfilled delay slot. */
5446 /* Handle weird backwards branch with a filled delay slot
5447 with is nullified. */
5448 if (dbr_sequence_length () != 0
5449 && ! forward_branch_p (insn)
5452 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5453 if (GET_MODE (operands[1]) == DImode)
5456 strcat (buf, "%S3");
5458 strcat (buf, "%B3");
5459 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5461 /* Handle short backwards branch with an unfilled delay slot.
5462 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5463 taken and untaken branches. */
5464 else if (dbr_sequence_length () == 0
5465 && ! forward_branch_p (insn)
5466 && INSN_ADDRESSES_SET_P ()
5467 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5468 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5470 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5471 if (GET_MODE (operands[1]) == DImode)
5474 strcat (buf, "%B3 %2,%r1,%0%#");
5476 strcat (buf, "%S3 %2,%r1,%0%#");
5480 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5481 if (GET_MODE (operands[1]) == DImode)
5484 strcat (buf, "%S3");
5486 strcat (buf, "%B3");
5488 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5490 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5495 /* Very long branch. Right now we only handle these when not
5496 optimizing. See "jump" pattern in pa.md for details. */
5500 /* Create a reversed conditional branch which branches around
5501 the following insns. */
5503 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5505 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5506 if (GET_MODE (operands[1]) == DImode)
5510 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5513 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5515 output_asm_insn (buf, operands);
5517 /* Output an insn to save %r1. */
5518 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5520 /* Now output a very long branch to the original target. */
5521 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5523 /* Now restore the value of %r1 in the delay slot. We're not
5524 optimizing so we know nothing else can be in the delay slot. */
5525 return "ldw -16(%%r30),%%r1";
5528 /* Very long branch when generating PIC code. Right now we only
5529 handle these when not optimizing. See "jump" pattern in pa.md
5534 /* Create a reversed conditional branch which branches around
5535 the following insns. */
5537 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5539 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5540 if (GET_MODE (operands[1]) == DImode)
5543 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5545 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5547 output_asm_insn (buf, operands);
5549 /* Output an insn to save %r1. */
5550 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5552 /* Now output a very long PIC branch to the original target. */
5556 xoperands[0] = operands[0];
5557 xoperands[1] = operands[1];
5558 xoperands[2] = operands[2];
5559 xoperands[3] = operands[3];
5561 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5562 if (TARGET_SOM || !TARGET_GAS)
5564 xoperands[4] = gen_label_rtx ();
5565 output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands);
5566 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5567 CODE_LABEL_NUMBER (xoperands[4]));
5568 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands);
5572 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5573 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1",
5576 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5579 /* Now restore the value of %r1 in the delay slot. We're not
5580 optimizing so we know nothing else can be in the delay slot. */
5581 return "ldw -16(%%r30),%%r1";
5589 /* This routine handles all the branch-on-bit conditional branch sequences we
5590 might need to generate. It handles nullification of delay slots,
5591 varying length branches, negated branches and all combinations of the
5592 above. it returns the appropriate output template to emit the branch. */
5595 output_bb (operands, nullify, length, negated, insn, which)
5596 rtx *operands ATTRIBUTE_UNUSED;
5597 int nullify, length, negated;
5601 static char buf[100];
5604 /* A conditional branch to the following instruction (eg the delay slot) is
5605 asking for a disaster. I do not think this can happen as this pattern
5606 is only used when optimizing; jump optimization should eliminate the
5607 jump. But be prepared just in case. */
5609 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5612 /* If this is a long branch with its delay slot unfilled, set `nullify'
5613 as it can nullify the delay slot and save a nop. */
5614 if (length == 8 && dbr_sequence_length () == 0)
5617 /* If this is a short forward conditional branch which did not get
5618 its delay slot filled, the delay slot can still be nullified. */
5619 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5620 nullify = forward_branch_p (insn);
5622 /* A forward branch over a single nullified insn can be done with a
5623 extrs instruction. This avoids a single cycle penalty due to
5624 mis-predicted branch if we fall through (branch not taken). */
5627 && next_real_insn (insn) != 0
5628 && get_attr_length (next_real_insn (insn)) == 4
5629 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5636 /* All short conditional branches except backwards with an unfilled
5640 strcpy (buf, "{extrs,|extrw,s,}");
5642 strcpy (buf, "bb,");
5643 if (useskip && GET_MODE (operands[0]) == DImode)
5644 strcpy (buf, "extrd,s,*");
5645 else if (GET_MODE (operands[0]) == DImode)
5646 strcpy (buf, "bb,*");
5647 if ((which == 0 && negated)
5648 || (which == 1 && ! negated))
5653 strcat (buf, " %0,%1,1,%%r0");
5654 else if (nullify && negated)
5655 strcat (buf, ",n %0,%1,%3");
5656 else if (nullify && ! negated)
5657 strcat (buf, ",n %0,%1,%2");
5658 else if (! nullify && negated)
5659 strcat (buf, "%0,%1,%3");
5660 else if (! nullify && ! negated)
5661 strcat (buf, " %0,%1,%2");
5664 /* All long conditionals. Note a short backward branch with an
5665 unfilled delay slot is treated just like a long backward branch
5666 with an unfilled delay slot. */
5668 /* Handle weird backwards branch with a filled delay slot
5669 with is nullified. */
5670 if (dbr_sequence_length () != 0
5671 && ! forward_branch_p (insn)
5674 strcpy (buf, "bb,");
5675 if (GET_MODE (operands[0]) == DImode)
5677 if ((which == 0 && negated)
5678 || (which == 1 && ! negated))
5683 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5685 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5687 /* Handle short backwards branch with an unfilled delay slot.
5688 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5689 taken and untaken branches. */
5690 else if (dbr_sequence_length () == 0
5691 && ! forward_branch_p (insn)
5692 && INSN_ADDRESSES_SET_P ()
5693 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5694 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5696 strcpy (buf, "bb,");
5697 if (GET_MODE (operands[0]) == DImode)
5699 if ((which == 0 && negated)
5700 || (which == 1 && ! negated))
5705 strcat (buf, " %0,%1,%3%#");
5707 strcat (buf, " %0,%1,%2%#");
5711 strcpy (buf, "{extrs,|extrw,s,}");
5712 if (GET_MODE (operands[0]) == DImode)
5713 strcpy (buf, "extrd,s,*");
5714 if ((which == 0 && negated)
5715 || (which == 1 && ! negated))
5719 if (nullify && negated)
5720 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5721 else if (nullify && ! negated)
5722 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5724 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5726 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5736 /* This routine handles all the branch-on-variable-bit conditional branch
5737 sequences we might need to generate. It handles nullification of delay
5738 slots, varying length branches, negated branches and all combinations
5739 of the above. it returns the appropriate output template to emit the
5743 output_bvb (operands, nullify, length, negated, insn, which)
5744 rtx *operands ATTRIBUTE_UNUSED;
5745 int nullify, length, negated;
5749 static char buf[100];
5752 /* A conditional branch to the following instruction (eg the delay slot) is
5753 asking for a disaster. I do not think this can happen as this pattern
5754 is only used when optimizing; jump optimization should eliminate the
5755 jump. But be prepared just in case. */
5757 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5760 /* If this is a long branch with its delay slot unfilled, set `nullify'
5761 as it can nullify the delay slot and save a nop. */
5762 if (length == 8 && dbr_sequence_length () == 0)
5765 /* If this is a short forward conditional branch which did not get
5766 its delay slot filled, the delay slot can still be nullified. */
5767 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5768 nullify = forward_branch_p (insn);
5770 /* A forward branch over a single nullified insn can be done with a
5771 extrs instruction. This avoids a single cycle penalty due to
5772 mis-predicted branch if we fall through (branch not taken). */
5775 && next_real_insn (insn) != 0
5776 && get_attr_length (next_real_insn (insn)) == 4
5777 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5784 /* All short conditional branches except backwards with an unfilled
5788 strcpy (buf, "{vextrs,|extrw,s,}");
5790 strcpy (buf, "{bvb,|bb,}");
5791 if (useskip && GET_MODE (operands[0]) == DImode)
5792 strcpy (buf, "extrd,s,*}");
5793 else if (GET_MODE (operands[0]) == DImode)
5794 strcpy (buf, "bb,*");
5795 if ((which == 0 && negated)
5796 || (which == 1 && ! negated))
5801 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5802 else if (nullify && negated)
5803 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5804 else if (nullify && ! negated)
5805 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5806 else if (! nullify && negated)
5807 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5808 else if (! nullify && ! negated)
5809 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5812 /* All long conditionals. Note a short backward branch with an
5813 unfilled delay slot is treated just like a long backward branch
5814 with an unfilled delay slot. */
5816 /* Handle weird backwards branch with a filled delay slot
5817 with is nullified. */
5818 if (dbr_sequence_length () != 0
5819 && ! forward_branch_p (insn)
5822 strcpy (buf, "{bvb,|bb,}");
5823 if (GET_MODE (operands[0]) == DImode)
5825 if ((which == 0 && negated)
5826 || (which == 1 && ! negated))
5831 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5833 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5835 /* Handle short backwards branch with an unfilled delay slot.
5836 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5837 taken and untaken branches. */
5838 else if (dbr_sequence_length () == 0
5839 && ! forward_branch_p (insn)
5840 && INSN_ADDRESSES_SET_P ()
5841 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5842 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5844 strcpy (buf, "{bvb,|bb,}");
5845 if (GET_MODE (operands[0]) == DImode)
5847 if ((which == 0 && negated)
5848 || (which == 1 && ! negated))
5853 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5855 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5859 strcpy (buf, "{vextrs,|extrw,s,}");
5860 if (GET_MODE (operands[0]) == DImode)
5861 strcpy (buf, "extrd,s,*");
5862 if ((which == 0 && negated)
5863 || (which == 1 && ! negated))
5867 if (nullify && negated)
5868 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5869 else if (nullify && ! negated)
5870 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5872 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5874 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5884 /* Return the output template for emitting a dbra type insn.
5886 Note it may perform some output operations on its own before
5887 returning the final output string. */
5889 output_dbra (operands, insn, which_alternative)
5892 int which_alternative;
5895 /* A conditional branch to the following instruction (eg the delay slot) is
5896 asking for a disaster. Be prepared! */
5898 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5900 if (which_alternative == 0)
5901 return "ldo %1(%0),%0";
5902 else if (which_alternative == 1)
5904 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5905 output_asm_insn ("ldw -16(%%r30),%4", operands);
5906 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5907 return "{fldws|fldw} -16(%%r30),%0";
5911 output_asm_insn ("ldw %0,%4", operands);
5912 return "ldo %1(%4),%4\n\tstw %4,%0";
5916 if (which_alternative == 0)
5918 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5919 int length = get_attr_length (insn);
5921 /* If this is a long branch with its delay slot unfilled, set `nullify'
5922 as it can nullify the delay slot and save a nop. */
5923 if (length == 8 && dbr_sequence_length () == 0)
5926 /* If this is a short forward conditional branch which did not get
5927 its delay slot filled, the delay slot can still be nullified. */
5928 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5929 nullify = forward_branch_p (insn);
5931 /* Handle short versions first. */
5932 if (length == 4 && nullify)
5933 return "addib,%C2,n %1,%0,%3";
5934 else if (length == 4 && ! nullify)
5935 return "addib,%C2 %1,%0,%3";
5936 else if (length == 8)
5938 /* Handle weird backwards branch with a fulled delay slot
5939 which is nullified. */
5940 if (dbr_sequence_length () != 0
5941 && ! forward_branch_p (insn)
5943 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5944 /* Handle short backwards branch with an unfilled delay slot.
5945 Using a addb;nop rather than addi;bl saves 1 cycle for both
5946 taken and untaken branches. */
5947 else if (dbr_sequence_length () == 0
5948 && ! forward_branch_p (insn)
5949 && INSN_ADDRESSES_SET_P ()
5950 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5951 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5952 return "addib,%C2 %1,%0,%3%#";
5954 /* Handle normal cases. */
5956 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5958 return "addi,%N2 %1,%0,%0\n\tb %3";
5963 /* Deal with gross reload from FP register case. */
5964 else if (which_alternative == 1)
5966 /* Move loop counter from FP register to MEM then into a GR,
5967 increment the GR, store the GR into MEM, and finally reload
5968 the FP register from MEM from within the branch's delay slot. */
5969 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5971 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5972 if (get_attr_length (insn) == 24)
5973 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5975 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5977 /* Deal with gross reload from memory case. */
5980 /* Reload loop counter from memory, the store back to memory
5981 happens in the branch's delay slot. */
5982 output_asm_insn ("ldw %0,%4", operands);
5983 if (get_attr_length (insn) == 12)
5984 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5986 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5990 /* Return the output template for emitting a dbra type insn.
5992 Note it may perform some output operations on its own before
5993 returning the final output string. */
5995 output_movb (operands, insn, which_alternative, reverse_comparison)
5998 int which_alternative;
5999 int reverse_comparison;
6002 /* A conditional branch to the following instruction (eg the delay slot) is
6003 asking for a disaster. Be prepared! */
6005 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
6007 if (which_alternative == 0)
6008 return "copy %1,%0";
6009 else if (which_alternative == 1)
6011 output_asm_insn ("stw %1,-16(%%r30)", operands);
6012 return "{fldws|fldw} -16(%%r30),%0";
6014 else if (which_alternative == 2)
6020 /* Support the second variant. */
6021 if (reverse_comparison)
6022 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6024 if (which_alternative == 0)
6026 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6027 int length = get_attr_length (insn);
6029 /* If this is a long branch with its delay slot unfilled, set `nullify'
6030 as it can nullify the delay slot and save a nop. */
6031 if (length == 8 && dbr_sequence_length () == 0)
6034 /* If this is a short forward conditional branch which did not get
6035 its delay slot filled, the delay slot can still be nullified. */
6036 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6037 nullify = forward_branch_p (insn);
6039 /* Handle short versions first. */
6040 if (length == 4 && nullify)
6041 return "movb,%C2,n %1,%0,%3";
6042 else if (length == 4 && ! nullify)
6043 return "movb,%C2 %1,%0,%3";
6044 else if (length == 8)
6046 /* Handle weird backwards branch with a filled delay slot
6047 which is nullified. */
6048 if (dbr_sequence_length () != 0
6049 && ! forward_branch_p (insn)
6051 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6053 /* Handle short backwards branch with an unfilled delay slot.
6054 Using a movb;nop rather than or;bl saves 1 cycle for both
6055 taken and untaken branches. */
6056 else if (dbr_sequence_length () == 0
6057 && ! forward_branch_p (insn)
6058 && INSN_ADDRESSES_SET_P ()
6059 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6060 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6061 return "movb,%C2 %1,%0,%3%#";
6062 /* Handle normal cases. */
6064 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6066 return "or,%N2 %1,%%r0,%0\n\tb %3";
6071 /* Deal with gross reload from FP register case. */
6072 else if (which_alternative == 1)
6074 /* Move loop counter from FP register to MEM then into a GR,
6075 increment the GR, store the GR into MEM, and finally reload
6076 the FP register from MEM from within the branch's delay slot. */
6077 output_asm_insn ("stw %1,-16(%%r30)", operands);
6078 if (get_attr_length (insn) == 12)
6079 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6081 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6083 /* Deal with gross reload from memory case. */
6084 else if (which_alternative == 2)
6086 /* Reload loop counter from memory, the store back to memory
6087 happens in the branch's delay slot. */
6088 if (get_attr_length (insn) == 8)
6089 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6091 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6093 /* Handle SAR as a destination. */
6096 if (get_attr_length (insn) == 8)
6097 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6099 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6103 /* Copy any FP arguments in INSN into integer registers. */
6111 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6113 int arg_mode, regno;
6114 rtx use = XEXP (link, 0);
6116 if (! (GET_CODE (use) == USE
6117 && GET_CODE (XEXP (use, 0)) == REG
6118 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6121 arg_mode = GET_MODE (XEXP (use, 0));
6122 regno = REGNO (XEXP (use, 0));
6124 /* Is it a floating point register? */
6125 if (regno >= 32 && regno <= 39)
6127 /* Copy the FP register into an integer register via memory. */
6128 if (arg_mode == SFmode)
6130 xoperands[0] = XEXP (use, 0);
6131 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6132 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6133 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6137 xoperands[0] = XEXP (use, 0);
6138 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6139 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6140 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6141 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6147 /* Compute length of the FP argument copy sequence for INSN. */
6149 length_fp_args (insn)
6155 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6157 int arg_mode, regno;
6158 rtx use = XEXP (link, 0);
6160 if (! (GET_CODE (use) == USE
6161 && GET_CODE (XEXP (use, 0)) == REG
6162 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6165 arg_mode = GET_MODE (XEXP (use, 0));
6166 regno = REGNO (XEXP (use, 0));
6168 /* Is it a floating point register? */
6169 if (regno >= 32 && regno <= 39)
6171 if (arg_mode == SFmode)
6181 /* We include the delay slot in the returned length as it is better to
6182 over estimate the length than to under estimate it. */
6185 attr_length_millicode_call (insn, length)
6189 unsigned long distance = total_code_bytes + INSN_ADDRESSES (INSN_UID (insn));
6191 if (distance < total_code_bytes)
6196 if (!TARGET_LONG_CALLS && distance < 7600000)
6201 else if (TARGET_PORTABLE_RUNTIME)
6205 if (!TARGET_LONG_CALLS && distance < 240000)
6208 if (TARGET_LONG_ABS_CALL && !flag_pic)
6215 /* INSN is a function call. It may have an unconditional jump
6218 CALL_DEST is the routine we are calling. */
6221 output_millicode_call (insn, call_dest)
6225 int attr_length = get_attr_length (insn);
6226 int seq_length = dbr_sequence_length ();
6231 xoperands[0] = call_dest;
6232 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6234 /* Handle the common case where we are sure that the branch will
6235 reach the beginning of the $CODE$ subspace. The within reach
6236 form of the $$sh_func_adrs call has a length of 28. Because
6237 it has an attribute type of multi, it never has a nonzero
6238 sequence length. The length of the $$sh_func_adrs is the same
6239 as certain out of reach PIC calls to other routines. */
6240 if (!TARGET_LONG_CALLS
6241 && ((seq_length == 0
6242 && (attr_length == 12
6243 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6244 || (seq_length != 0 && attr_length == 8)))
6246 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6252 /* It might seem that one insn could be saved by accessing
6253 the millicode function using the linkage table. However,
6254 this doesn't work in shared libraries and other dynamically
6255 loaded objects. Using a pc-relative sequence also avoids
6256 problems related to the implicit use of the gp register. */
6257 output_asm_insn ("b,l .+8,%%r1", xoperands);
6261 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6262 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6266 xoperands[1] = gen_label_rtx ();
6267 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6268 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6269 CODE_LABEL_NUMBER (xoperands[1]));
6270 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6273 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6275 else if (TARGET_PORTABLE_RUNTIME)
6277 /* Pure portable runtime doesn't allow be/ble; we also don't
6278 have PIC support in the assembler/linker, so this sequence
6281 /* Get the address of our target into %r1. */
6282 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6283 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6285 /* Get our return address into %r31. */
6286 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6287 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6289 /* Jump to our target address in %r1. */
6290 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6294 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6296 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6298 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6302 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6303 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6305 if (TARGET_SOM || !TARGET_GAS)
6307 /* The HP assembler can generate relocations for the
6308 difference of two symbols. GAS can do this for a
6309 millicode symbol but not an arbitrary external
6310 symbol when generating SOM output. */
6311 xoperands[1] = gen_label_rtx ();
6312 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6313 CODE_LABEL_NUMBER (xoperands[1]));
6314 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6315 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6319 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6320 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6324 /* Jump to our target address in %r1. */
6325 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6329 if (seq_length == 0)
6330 output_asm_insn ("nop", xoperands);
6332 /* We are done if there isn't a jump in the delay slot. */
6333 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6336 /* This call has an unconditional jump in its delay slot. */
6337 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6339 /* See if the return address can be adjusted. Use the containing
6340 sequence insn's address. */
6341 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6342 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6343 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6345 if (VAL_14_BITS_P (distance))
6347 xoperands[1] = gen_label_rtx ();
6348 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6349 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6350 CODE_LABEL_NUMBER (xoperands[1]));
6353 /* ??? This branch may not reach its target. */
6354 output_asm_insn ("nop\n\tb,n %0", xoperands);
6356 /* Delete the jump. */
6357 PUT_CODE (NEXT_INSN (insn), NOTE);
6358 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6359 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6364 /* We include the delay slot in the returned length as it is better to
6365 over estimate the length than to under estimate it. */
6368 attr_length_call (insn, sibcall)
6372 unsigned long distance = total_code_bytes + INSN_ADDRESSES (INSN_UID (insn));
6374 if (distance < total_code_bytes)
6379 if (!TARGET_LONG_CALLS
6380 && ((!sibcall && distance < 7600000) || distance < 240000))
6383 return (sibcall ? 28 : 24);
6387 if (!TARGET_LONG_CALLS
6388 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
6389 || distance < 240000))
6392 if (TARGET_LONG_ABS_CALL && !flag_pic)
6395 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6396 || (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6408 length += length_fp_args (insn);
6414 return (length + 32);
6419 return (length + 40);
6424 /* INSN is a function call. It may have an unconditional jump
6427 CALL_DEST is the routine we are calling. */
6430 output_call (insn, call_dest, sibcall)
6435 int delay_insn_deleted = 0;
6436 int delay_slot_filled = 0;
6437 int attr_length = get_attr_length (insn);
6438 int seq_length = dbr_sequence_length ();
6441 xoperands[0] = call_dest;
6443 /* Handle the common case where we're sure that the branch will reach
6444 the beginning of the $CODE$ subspace. */
6445 if (!TARGET_LONG_CALLS
6446 && ((seq_length == 0 && attr_length == 12)
6447 || (seq_length != 0 && attr_length == 8)))
6449 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6450 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
6456 /* ??? As far as I can tell, the HP linker doesn't support the
6457 long pc-relative sequence described in the 64-bit runtime
6458 architecture. So, we use a slightly longer indirect call. */
6459 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6461 xoperands[0] = p->internal_label;
6462 xoperands[1] = gen_label_rtx ();
6464 /* If this isn't a sibcall, we put the load of %r27 into the
6465 delay slot. We can't do this in a sibcall as we don't
6466 have a second call-clobbered scratch register available. */
6468 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6471 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6474 /* Now delete the delay insn. */
6475 PUT_CODE (NEXT_INSN (insn), NOTE);
6476 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6477 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6478 delay_insn_deleted = 1;
6481 output_asm_insn ("addil LT'%0,%%r27", xoperands);
6482 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
6483 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
6487 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6488 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
6489 output_asm_insn ("bve (%%r1)", xoperands);
6493 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
6494 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
6495 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6496 delay_slot_filled = 1;
6501 int indirect_call = 0;
6503 /* Emit a long call. There are several different sequences
6504 of increasing length and complexity. In most cases,
6505 they don't allow an instruction in the delay slot. */
6506 if (!(TARGET_LONG_ABS_CALL && !flag_pic)
6507 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6508 && !(TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6512 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6514 && (!TARGET_PA_20 || indirect_call))
6516 /* A non-jump insn in the delay slot. By definition we can
6517 emit this insn before the call (and in fact before argument
6519 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6521 /* Now delete the delay insn. */
6522 PUT_CODE (NEXT_INSN (insn), NOTE);
6523 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6524 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6525 delay_insn_deleted = 1;
6528 if (TARGET_LONG_ABS_CALL && !flag_pic)
6530 /* This is the best sequence for making long calls in
6531 non-pic code. Unfortunately, GNU ld doesn't provide
6532 the stub needed for external calls, and GAS's support
6533 for this with the SOM linker is buggy. */
6534 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6536 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
6540 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
6543 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6545 output_asm_insn ("copy %%r31,%%r2", xoperands);
6546 delay_slot_filled = 1;
6551 if (TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6553 /* The HP assembler and linker can handle relocations
6554 for the difference of two symbols. GAS and the HP
6555 linker can't do this when one of the symbols is
6557 xoperands[1] = gen_label_rtx ();
6558 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6559 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6560 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6561 CODE_LABEL_NUMBER (xoperands[1]));
6562 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6564 else if (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL)
6566 /* GAS currently can't generate the relocations that
6567 are needed for the SOM linker under HP-UX using this
6568 sequence. The GNU linker doesn't generate the stubs
6569 that are needed for external calls on TARGET_ELF32
6570 with this sequence. For now, we have to use a
6571 longer plabel sequence when using GAS. */
6572 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6573 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
6575 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
6580 /* Emit a long plabel-based call sequence. This is
6581 essentially an inline implementation of $$dyncall.
6582 We don't actually try to call $$dyncall as this is
6583 as difficult as calling the function itself. */
6584 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6586 xoperands[0] = p->internal_label;
6587 xoperands[1] = gen_label_rtx ();
6589 /* Since the call is indirect, FP arguments in registers
6590 need to be copied to the general registers. Then, the
6591 argument relocation stub will copy them back. */
6593 copy_fp_args (insn);
6597 output_asm_insn ("addil LT'%0,%%r19", xoperands);
6598 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
6599 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
6603 output_asm_insn ("addil LR'%0-$global$,%%r27",
6605 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
6609 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
6610 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
6611 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
6612 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
6614 if (!sibcall && !TARGET_PA_20)
6616 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
6617 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
6624 output_asm_insn ("bve (%%r1)", xoperands);
6629 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6630 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
6631 delay_slot_filled = 1;
6634 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6639 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
6643 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
6646 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
6649 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
6651 output_asm_insn ("copy %%r31,%%r2", xoperands);
6652 delay_slot_filled = 1;
6659 if (seq_length == 0 || (delay_insn_deleted && !delay_slot_filled))
6660 output_asm_insn ("nop", xoperands);
6662 /* We are done if there isn't a jump in the delay slot. */
6664 || delay_insn_deleted
6665 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6668 /* A sibcall should never have a branch in the delay slot. */
6672 /* This call has an unconditional jump in its delay slot. */
6673 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6675 if (!delay_slot_filled)
6677 /* See if the return address can be adjusted. Use the containing
6678 sequence insn's address. */
6679 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6680 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6681 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6683 if (VAL_14_BITS_P (distance))
6685 xoperands[1] = gen_label_rtx ();
6686 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
6687 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6688 CODE_LABEL_NUMBER (xoperands[1]));
6691 /* ??? This branch may not reach its target. */
6692 output_asm_insn ("nop\n\tb,n %0", xoperands);
6695 /* ??? This branch may not reach its target. */
6696 output_asm_insn ("b,n %0", xoperands);
6698 /* Delete the jump. */
6699 PUT_CODE (NEXT_INSN (insn), NOTE);
6700 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6701 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6706 /* In HPUX 8.0's shared library scheme, special relocations are needed
6707 for function labels if they might be passed to a function
6708 in a shared library (because shared libraries don't live in code
6709 space), and special magic is needed to construct their address. */
6712 hppa_encode_label (sym)
6715 const char *str = XSTR (sym, 0);
6716 int len = strlen (str) + 1;
6719 p = newstr = alloca (len + 1);
6723 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6727 pa_encode_section_info (decl, first)
6731 if (first && TEXT_SPACE_P (decl))
6734 if (TREE_CODE (decl) == FUNCTION_DECL
6735 || TREE_CODE (decl) == VAR_DECL)
6736 rtl = DECL_RTL (decl);
6738 rtl = TREE_CST_RTL (decl);
6739 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
6740 if (TREE_CODE (decl) == FUNCTION_DECL)
6741 hppa_encode_label (XEXP (DECL_RTL (decl), 0));
6745 /* This is sort of inverse to pa_encode_section_info. */
6748 pa_strip_name_encoding (str)
6751 str += (*str == '@');
6752 str += (*str == '*');
6757 function_label_operand (op, mode)
6759 enum machine_mode mode ATTRIBUTE_UNUSED;
6761 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6764 /* Returns 1 if OP is a function label involved in a simple addition
6765 with a constant. Used to keep certain patterns from matching
6766 during instruction combination. */
6768 is_function_label_plus_const (op)
6771 /* Strip off any CONST. */
6772 if (GET_CODE (op) == CONST)
6775 return (GET_CODE (op) == PLUS
6776 && function_label_operand (XEXP (op, 0), Pmode)
6777 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6780 /* Output assembly code for a thunk to FUNCTION. */
6783 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
6786 HOST_WIDE_INT delta;
6787 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
6790 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
6791 static unsigned int current_thunk_number;
6794 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
6795 lab = (*targetm.strip_name_encoding) (label);
6796 target_name = (*targetm.strip_name_encoding) (target_name);
6797 /* FIXME: total_code_bytes is not handled correctly in files with
6799 pa_output_function_prologue (file, 0);
6800 if (VAL_14_BITS_P (delta))
6802 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6804 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
6805 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
6806 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6807 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6808 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6809 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6810 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6811 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6812 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
6813 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6814 fprintf (file, "(%%r26),%%r26\n");
6818 fprintf (file, "\tb %s\n\tldo ", target_name);
6819 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6820 fprintf (file, "(%%r26),%%r26\n");
6825 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6827 fprintf (file, "\taddil L'");
6828 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6829 fprintf (file, ",%%r26\n\tldo R'");
6830 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6831 fprintf (file, "(%%r1),%%r26\n");
6832 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
6833 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
6834 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6835 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6836 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6837 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6838 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6839 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6840 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
6844 fprintf (file, "\taddil L'");
6845 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6846 fprintf (file, ",%%r26\n\tb %s\n\tldo R'", target_name);
6847 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6848 fprintf (file, "(%%r1),%%r26\n");
6852 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
6853 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6856 fprintf (file, "\t.align 4\n");
6857 (*targetm.asm_out.internal_label) (file, "LTHN", current_thunk_number);
6858 fprintf (file, "\t.word P'%s\n", target_name);
6859 function_section (thunk_fndecl);
6861 current_thunk_number++;
6864 /* Only direct calls to static functions are allowed to be sibling (tail)
6867 This restriction is necessary because some linker generated stubs will
6868 store return pointers into rp' in some cases which might clobber a
6869 live value already in rp'.
6871 In a sibcall the current function and the target function share stack
6872 space. Thus if the path to the current function and the path to the
6873 target function save a value in rp', they save the value into the
6874 same stack slot, which has undesirable consequences.
6876 Because of the deferred binding nature of shared libraries any function
6877 with external scope could be in a different load module and thus require
6878 rp' to be saved when calling that function. So sibcall optimizations
6879 can only be safe for static function.
6881 Note that GCC never needs return value relocations, so we don't have to
6882 worry about static calls with return value relocations (which require
6885 It is safe to perform a sibcall optimization when the target function
6886 will never return. */
6888 pa_function_ok_for_sibcall (decl, exp)
6890 tree exp ATTRIBUTE_UNUSED;
6892 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
6893 single subspace mode and the call is not indirect. As far as I know,
6894 there is no operating system support for the multiple subspace mode.
6895 It might be possible to support indirect calls if we didn't use
6896 $$dyncall (see the indirect sequence generated in output_call). */
6898 return (decl != NULL_TREE);
6900 /* Sibcalls are not ok because the arg pointer register is not a fixed
6901 register. This prevents the sibcall optimization from occuring. In
6902 addition, there are problems with stub placement using GNU ld. This
6903 is because a normal sibcall branch uses a 17-bit relocation while
6904 a regular call branch uses a 22-bit relocation. As a result, more
6905 care needs to be taken in the placement of long-branch stubs. */
6910 && !TARGET_PORTABLE_RUNTIME
6911 && !TREE_PUBLIC (decl));
6914 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6915 use in fmpyadd instructions. */
6917 fmpyaddoperands (operands)
6920 enum machine_mode mode = GET_MODE (operands[0]);
6922 /* Must be a floating point mode. */
6923 if (mode != SFmode && mode != DFmode)
6926 /* All modes must be the same. */
6927 if (! (mode == GET_MODE (operands[1])
6928 && mode == GET_MODE (operands[2])
6929 && mode == GET_MODE (operands[3])
6930 && mode == GET_MODE (operands[4])
6931 && mode == GET_MODE (operands[5])))
6934 /* All operands must be registers. */
6935 if (! (GET_CODE (operands[1]) == REG
6936 && GET_CODE (operands[2]) == REG
6937 && GET_CODE (operands[3]) == REG
6938 && GET_CODE (operands[4]) == REG
6939 && GET_CODE (operands[5]) == REG))
6942 /* Only 2 real operands to the addition. One of the input operands must
6943 be the same as the output operand. */
6944 if (! rtx_equal_p (operands[3], operands[4])
6945 && ! rtx_equal_p (operands[3], operands[5]))
6948 /* Inout operand of add can not conflict with any operands from multiply. */
6949 if (rtx_equal_p (operands[3], operands[0])
6950 || rtx_equal_p (operands[3], operands[1])
6951 || rtx_equal_p (operands[3], operands[2]))
6954 /* multiply can not feed into addition operands. */
6955 if (rtx_equal_p (operands[4], operands[0])
6956 || rtx_equal_p (operands[5], operands[0]))
6959 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6961 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6962 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6963 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6964 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6965 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6966 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6969 /* Passed. Operands are suitable for fmpyadd. */
6973 #if !defined(USE_COLLECT2)
6975 pa_asm_out_constructor (symbol, priority)
6979 if (!function_label_operand (symbol, VOIDmode))
6980 hppa_encode_label (symbol);
6982 #ifdef CTORS_SECTION_ASM_OP
6983 default_ctor_section_asm_out_constructor (symbol, priority);
6985 # ifdef TARGET_ASM_NAMED_SECTION
6986 default_named_section_asm_out_constructor (symbol, priority);
6988 default_stabs_asm_out_constructor (symbol, priority);
6994 pa_asm_out_destructor (symbol, priority)
6998 if (!function_label_operand (symbol, VOIDmode))
6999 hppa_encode_label (symbol);
7001 #ifdef DTORS_SECTION_ASM_OP
7002 default_dtor_section_asm_out_destructor (symbol, priority);
7004 # ifdef TARGET_ASM_NAMED_SECTION
7005 default_named_section_asm_out_destructor (symbol, priority);
7007 default_stabs_asm_out_destructor (symbol, priority);
7013 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7014 use in fmpysub instructions. */
7016 fmpysuboperands (operands)
7019 enum machine_mode mode = GET_MODE (operands[0]);
7021 /* Must be a floating point mode. */
7022 if (mode != SFmode && mode != DFmode)
7025 /* All modes must be the same. */
7026 if (! (mode == GET_MODE (operands[1])
7027 && mode == GET_MODE (operands[2])
7028 && mode == GET_MODE (operands[3])
7029 && mode == GET_MODE (operands[4])
7030 && mode == GET_MODE (operands[5])))
7033 /* All operands must be registers. */
7034 if (! (GET_CODE (operands[1]) == REG
7035 && GET_CODE (operands[2]) == REG
7036 && GET_CODE (operands[3]) == REG
7037 && GET_CODE (operands[4]) == REG
7038 && GET_CODE (operands[5]) == REG))
7041 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
7042 operation, so operands[4] must be the same as operand[3]. */
7043 if (! rtx_equal_p (operands[3], operands[4]))
7046 /* multiply can not feed into subtraction. */
7047 if (rtx_equal_p (operands[5], operands[0]))
7050 /* Inout operand of sub can not conflict with any operands from multiply. */
7051 if (rtx_equal_p (operands[3], operands[0])
7052 || rtx_equal_p (operands[3], operands[1])
7053 || rtx_equal_p (operands[3], operands[2]))
7056 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7058 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7059 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7060 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7061 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7062 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7063 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7066 /* Passed. Operands are suitable for fmpysub. */
7071 plus_xor_ior_operator (op, mode)
7073 enum machine_mode mode ATTRIBUTE_UNUSED;
7075 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
7076 || GET_CODE (op) == IOR);
7079 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
7080 constants for shadd instructions. */
7082 shadd_constant_p (val)
7085 if (val == 2 || val == 4 || val == 8)
7091 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
7092 the valid constant for shadd instructions. */
7094 shadd_operand (op, mode)
7096 enum machine_mode mode ATTRIBUTE_UNUSED;
7098 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
7101 /* Return 1 if OP is valid as a base register in a reg + reg address. */
7104 basereg_operand (op, mode)
7106 enum machine_mode mode;
7108 /* cse will create some unscaled indexed addresses, however; it
7109 generally isn't a win on the PA, so avoid creating unscaled
7110 indexed addresses until after cse is finished. */
7111 if (!cse_not_expected)
7114 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
7115 we don't have to worry about the braindamaged implicit space
7116 register selection from the basereg. */
7117 if (TARGET_NO_SPACE_REGS)
7118 return (GET_CODE (op) == REG);
7120 /* While it's always safe to index off the frame pointer, it's not
7121 always profitable, particularly when the frame pointer is being
7123 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
7126 return (GET_CODE (op) == REG
7128 && register_operand (op, mode));
7131 /* Return 1 if this operand is anything other than a hard register. */
7134 non_hard_reg_operand (op, mode)
7136 enum machine_mode mode ATTRIBUTE_UNUSED;
7138 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
7141 /* Return 1 if INSN branches forward. Should be using insn_addresses
7142 to avoid walking through all the insns... */
7144 forward_branch_p (insn)
7147 rtx label = JUMP_LABEL (insn);
7154 insn = NEXT_INSN (insn);
7157 return (insn == label);
7160 /* Return 1 if OP is an equality comparison, else return 0. */
7162 eq_neq_comparison_operator (op, mode)
7164 enum machine_mode mode ATTRIBUTE_UNUSED;
7166 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
7169 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
7171 movb_comparison_operator (op, mode)
7173 enum machine_mode mode ATTRIBUTE_UNUSED;
7175 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
7176 || GET_CODE (op) == LT || GET_CODE (op) == GE);
7179 /* Return 1 if INSN is in the delay slot of a call instruction. */
7181 jump_in_call_delay (insn)
7185 if (GET_CODE (insn) != JUMP_INSN)
7188 if (PREV_INSN (insn)
7189 && PREV_INSN (PREV_INSN (insn))
7190 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
7192 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
7194 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
7195 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
7202 /* Output an unconditional move and branch insn. */
7205 output_parallel_movb (operands, length)
7209 /* These are the cases in which we win. */
7211 return "mov%I1b,tr %1,%0,%2";
7213 /* None of these cases wins, but they don't lose either. */
7214 if (dbr_sequence_length () == 0)
7216 /* Nothing in the delay slot, fake it by putting the combined
7217 insn (the copy or add) in the delay slot of a bl. */
7218 if (GET_CODE (operands[1]) == CONST_INT)
7219 return "b %2\n\tldi %1,%0";
7221 return "b %2\n\tcopy %1,%0";
7225 /* Something in the delay slot, but we've got a long branch. */
7226 if (GET_CODE (operands[1]) == CONST_INT)
7227 return "ldi %1,%0\n\tb %2";
7229 return "copy %1,%0\n\tb %2";
7233 /* Output an unconditional add and branch insn. */
7236 output_parallel_addb (operands, length)
7240 /* To make life easy we want operand0 to be the shared input/output
7241 operand and operand1 to be the readonly operand. */
7242 if (operands[0] == operands[1])
7243 operands[1] = operands[2];
7245 /* These are the cases in which we win. */
7247 return "add%I1b,tr %1,%0,%3";
7249 /* None of these cases win, but they don't lose either. */
7250 if (dbr_sequence_length () == 0)
7252 /* Nothing in the delay slot, fake it by putting the combined
7253 insn (the copy or add) in the delay slot of a bl. */
7254 return "b %3\n\tadd%I1 %1,%0,%0";
7258 /* Something in the delay slot, but we've got a long branch. */
7259 return "add%I1 %1,%0,%0\n\tb %3";
7263 /* Return nonzero if INSN (a jump insn) immediately follows a call
7264 to a named function. This is used to avoid filling the delay slot
7265 of the jump since it can usually be eliminated by modifying RP in
7266 the delay slot of the call. */
7269 following_call (insn)
7272 if (! TARGET_JUMP_IN_DELAY)
7275 /* Find the previous real insn, skipping NOTEs. */
7276 insn = PREV_INSN (insn);
7277 while (insn && GET_CODE (insn) == NOTE)
7278 insn = PREV_INSN (insn);
7280 /* Check for CALL_INSNs and millicode calls. */
7282 && ((GET_CODE (insn) == CALL_INSN
7283 && get_attr_type (insn) != TYPE_DYNCALL)
7284 || (GET_CODE (insn) == INSN
7285 && GET_CODE (PATTERN (insn)) != SEQUENCE
7286 && GET_CODE (PATTERN (insn)) != USE
7287 && GET_CODE (PATTERN (insn)) != CLOBBER
7288 && get_attr_type (insn) == TYPE_MILLI)))
7294 /* We use this hook to perform a PA specific optimization which is difficult
7295 to do in earlier passes.
7297 We want the delay slots of branches within jump tables to be filled.
7298 None of the compiler passes at the moment even has the notion that a
7299 PA jump table doesn't contain addresses, but instead contains actual
7302 Because we actually jump into the table, the addresses of each entry
7303 must stay constant in relation to the beginning of the table (which
7304 itself must stay constant relative to the instruction to jump into
7305 it). I don't believe we can guarantee earlier passes of the compiler
7306 will adhere to those rules.
7308 So, late in the compilation process we find all the jump tables, and
7309 expand them into real code -- eg each entry in the jump table vector
7310 will get an appropriate label followed by a jump to the final target.
7312 Reorg and the final jump pass can then optimize these branches and
7313 fill their delay slots. We end up with smaller, more efficient code.
7315 The jump instructions within the table are special; we must be able
7316 to identify them during assembly output (if the jumps don't get filled
7317 we need to emit a nop rather than nullifying the delay slot)). We
7318 identify jumps in switch tables by marking the SET with DImode.
7320 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
7321 insns. This serves two purposes, first it prevents jump.c from
7322 noticing that the last N entries in the table jump to the instruction
7323 immediately after the table and deleting the jumps. Second, those
7324 insns mark where we should emit .begin_brtab and .end_brtab directives
7325 when using GAS (allows for better link time optimizations). */
7333 remove_useless_addtr_insns (insns, 1);
7335 if (pa_cpu < PROCESSOR_8000)
7336 pa_combine_instructions (get_insns ());
7339 /* This is fairly cheap, so always run it if optimizing. */
7340 if (optimize > 0 && !TARGET_BIG_SWITCH)
7342 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
7343 insns = get_insns ();
7344 for (insn = insns; insn; insn = NEXT_INSN (insn))
7346 rtx pattern, tmp, location;
7347 unsigned int length, i;
7349 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
7350 if (GET_CODE (insn) != JUMP_INSN
7351 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7352 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7355 /* Emit marker for the beginning of the branch table. */
7356 emit_insn_before (gen_begin_brtab (), insn);
7358 pattern = PATTERN (insn);
7359 location = PREV_INSN (insn);
7360 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
7362 for (i = 0; i < length; i++)
7364 /* Emit a label before each jump to keep jump.c from
7365 removing this code. */
7366 tmp = gen_label_rtx ();
7367 LABEL_NUSES (tmp) = 1;
7368 emit_label_after (tmp, location);
7369 location = NEXT_INSN (location);
7371 if (GET_CODE (pattern) == ADDR_VEC)
7373 /* Emit the jump itself. */
7374 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7375 tmp = emit_jump_insn_after (tmp, location);
7376 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7377 /* It is easy to rely on the branch table markers
7378 during assembly output to trigger the correct code
7379 for a switch table jump with an unfilled delay slot,
7381 However, that requires state and assumes that we look
7384 We can't make such assumptions when computing the length
7385 of instructions. Ugh. We could walk the insn chain to
7386 determine if this instruction is in a branch table, but
7387 that can get rather expensive, particularly during the
7388 branch shortening phase of the compiler.
7390 So instead we mark this jump as being special. This is
7391 far from ideal and knows that no code after this will
7392 muck around with the mode of the JUMP_INSN itself. */
7393 PUT_MODE (tmp, SImode);
7394 LABEL_NUSES (JUMP_LABEL (tmp))++;
7395 location = NEXT_INSN (location);
7399 /* Emit the jump itself. */
7400 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7401 tmp = emit_jump_insn_after (tmp, location);
7402 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7403 /* It is easy to rely on the branch table markers
7404 during assembly output to trigger the correct code
7405 for a switch table jump with an unfilled delay slot,
7407 However, that requires state and assumes that we look
7410 We can't make such assumptions when computing the length
7411 of instructions. Ugh. We could walk the insn chain to
7412 determine if this instruction is in a branch table, but
7413 that can get rather expensive, particularly during the
7414 branch shortening phase of the compiler.
7416 So instead we mark this jump as being special. This is
7417 far from ideal and knows that no code after this will
7418 muck around with the mode of the JUMP_INSN itself. */
7419 PUT_MODE (tmp, SImode);
7420 LABEL_NUSES (JUMP_LABEL (tmp))++;
7421 location = NEXT_INSN (location);
7424 /* Emit a BARRIER after the jump. */
7425 emit_barrier_after (location);
7426 location = NEXT_INSN (location);
7429 /* Emit marker for the end of the branch table. */
7430 emit_insn_before (gen_end_brtab (), location);
7431 location = NEXT_INSN (location);
7432 emit_barrier_after (location);
7434 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7440 /* Sill need an end_brtab insn. */
7441 insns = get_insns ();
7442 for (insn = insns; insn; insn = NEXT_INSN (insn))
7444 /* Find an ADDR_VEC insn. */
7445 if (GET_CODE (insn) != JUMP_INSN
7446 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7447 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7450 /* Now generate markers for the beginning and end of the
7452 emit_insn_before (gen_begin_brtab (), insn);
7453 emit_insn_after (gen_end_brtab (), insn);
7458 /* The PA has a number of odd instructions which can perform multiple
7459 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7460 it may be profitable to combine two instructions into one instruction
7461 with two outputs. It's not profitable PA2.0 machines because the
7462 two outputs would take two slots in the reorder buffers.
7464 This routine finds instructions which can be combined and combines
7465 them. We only support some of the potential combinations, and we
7466 only try common ways to find suitable instructions.
7468 * addb can add two registers or a register and a small integer
7469 and jump to a nearby (+-8k) location. Normally the jump to the
7470 nearby location is conditional on the result of the add, but by
7471 using the "true" condition we can make the jump unconditional.
7472 Thus addb can perform two independent operations in one insn.
7474 * movb is similar to addb in that it can perform a reg->reg
7475 or small immediate->reg copy and jump to a nearby (+-8k location).
7477 * fmpyadd and fmpysub can perform a FP multiply and either an
7478 FP add or FP sub if the operands of the multiply and add/sub are
7479 independent (there are other minor restrictions). Note both
7480 the fmpy and fadd/fsub can in theory move to better spots according
7481 to data dependencies, but for now we require the fmpy stay at a
7484 * Many of the memory operations can perform pre & post updates
7485 of index registers. GCC's pre/post increment/decrement addressing
7486 is far too simple to take advantage of all the possibilities. This
7487 pass may not be suitable since those insns may not be independent.
7489 * comclr can compare two ints or an int and a register, nullify
7490 the following instruction and zero some other register. This
7491 is more difficult to use as it's harder to find an insn which
7492 will generate a comclr than finding something like an unconditional
7493 branch. (conditional moves & long branches create comclr insns).
7495 * Most arithmetic operations can conditionally skip the next
7496 instruction. They can be viewed as "perform this operation
7497 and conditionally jump to this nearby location" (where nearby
7498 is an insns away). These are difficult to use due to the
7499 branch length restrictions. */
7502 pa_combine_instructions (insns)
7503 rtx insns ATTRIBUTE_UNUSED;
7507 /* This can get expensive since the basic algorithm is on the
7508 order of O(n^2) (or worse). Only do it for -O2 or higher
7509 levels of optimization. */
7513 /* Walk down the list of insns looking for "anchor" insns which
7514 may be combined with "floating" insns. As the name implies,
7515 "anchor" instructions don't move, while "floating" insns may
7517 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7518 new = make_insn_raw (new);
7520 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7522 enum attr_pa_combine_type anchor_attr;
7523 enum attr_pa_combine_type floater_attr;
7525 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7526 Also ignore any special USE insns. */
7527 if ((GET_CODE (anchor) != INSN
7528 && GET_CODE (anchor) != JUMP_INSN
7529 && GET_CODE (anchor) != CALL_INSN)
7530 || GET_CODE (PATTERN (anchor)) == USE
7531 || GET_CODE (PATTERN (anchor)) == CLOBBER
7532 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7533 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7536 anchor_attr = get_attr_pa_combine_type (anchor);
7537 /* See if anchor is an insn suitable for combination. */
7538 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7539 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7540 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7541 && ! forward_branch_p (anchor)))
7545 for (floater = PREV_INSN (anchor);
7547 floater = PREV_INSN (floater))
7549 if (GET_CODE (floater) == NOTE
7550 || (GET_CODE (floater) == INSN
7551 && (GET_CODE (PATTERN (floater)) == USE
7552 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7555 /* Anything except a regular INSN will stop our search. */
7556 if (GET_CODE (floater) != INSN
7557 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7558 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7564 /* See if FLOATER is suitable for combination with the
7566 floater_attr = get_attr_pa_combine_type (floater);
7567 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7568 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7569 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7570 && floater_attr == PA_COMBINE_TYPE_FMPY))
7572 /* If ANCHOR and FLOATER can be combined, then we're
7573 done with this pass. */
7574 if (pa_can_combine_p (new, anchor, floater, 0,
7575 SET_DEST (PATTERN (floater)),
7576 XEXP (SET_SRC (PATTERN (floater)), 0),
7577 XEXP (SET_SRC (PATTERN (floater)), 1)))
7581 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7582 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7584 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7586 if (pa_can_combine_p (new, anchor, floater, 0,
7587 SET_DEST (PATTERN (floater)),
7588 XEXP (SET_SRC (PATTERN (floater)), 0),
7589 XEXP (SET_SRC (PATTERN (floater)), 1)))
7594 if (pa_can_combine_p (new, anchor, floater, 0,
7595 SET_DEST (PATTERN (floater)),
7596 SET_SRC (PATTERN (floater)),
7597 SET_SRC (PATTERN (floater))))
7603 /* If we didn't find anything on the backwards scan try forwards. */
7605 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7606 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7608 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7610 if (GET_CODE (floater) == NOTE
7611 || (GET_CODE (floater) == INSN
7612 && (GET_CODE (PATTERN (floater)) == USE
7613 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7617 /* Anything except a regular INSN will stop our search. */
7618 if (GET_CODE (floater) != INSN
7619 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7620 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7626 /* See if FLOATER is suitable for combination with the
7628 floater_attr = get_attr_pa_combine_type (floater);
7629 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7630 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7631 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7632 && floater_attr == PA_COMBINE_TYPE_FMPY))
7634 /* If ANCHOR and FLOATER can be combined, then we're
7635 done with this pass. */
7636 if (pa_can_combine_p (new, anchor, floater, 1,
7637 SET_DEST (PATTERN (floater)),
7638 XEXP (SET_SRC (PATTERN (floater)),
7640 XEXP (SET_SRC (PATTERN (floater)),
7647 /* FLOATER will be nonzero if we found a suitable floating
7648 insn for combination with ANCHOR. */
7650 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7651 || anchor_attr == PA_COMBINE_TYPE_FMPY))
7653 /* Emit the new instruction and delete the old anchor. */
7654 emit_insn_before (gen_rtx_PARALLEL
7656 gen_rtvec (2, PATTERN (anchor),
7657 PATTERN (floater))),
7660 PUT_CODE (anchor, NOTE);
7661 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7662 NOTE_SOURCE_FILE (anchor) = 0;
7664 /* Emit a special USE insn for FLOATER, then delete
7665 the floating insn. */
7666 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7667 delete_insn (floater);
7672 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
7675 /* Emit the new_jump instruction and delete the old anchor. */
7677 = emit_jump_insn_before (gen_rtx_PARALLEL
7679 gen_rtvec (2, PATTERN (anchor),
7680 PATTERN (floater))),
7683 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
7684 PUT_CODE (anchor, NOTE);
7685 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7686 NOTE_SOURCE_FILE (anchor) = 0;
7688 /* Emit a special USE insn for FLOATER, then delete
7689 the floating insn. */
7690 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7691 delete_insn (floater);
7699 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7700 rtx new, anchor, floater;
7702 rtx dest, src1, src2;
7704 int insn_code_number;
7707 /* Create a PARALLEL with the patterns of ANCHOR and
7708 FLOATER, try to recognize it, then test constraints
7709 for the resulting pattern.
7711 If the pattern doesn't match or the constraints
7712 aren't met keep searching for a suitable floater
7714 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7715 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7716 INSN_CODE (new) = -1;
7717 insn_code_number = recog_memoized (new);
7718 if (insn_code_number < 0
7719 || (extract_insn (new), ! constrain_operands (1)))
7733 /* There's up to three operands to consider. One
7734 output and two inputs.
7736 The output must not be used between FLOATER & ANCHOR
7737 exclusive. The inputs must not be set between
7738 FLOATER and ANCHOR exclusive. */
7740 if (reg_used_between_p (dest, start, end))
7743 if (reg_set_between_p (src1, start, end))
7746 if (reg_set_between_p (src2, start, end))
7749 /* If we get here, then everything is good. */
7753 /* Return nonzero if references for INSN are delayed.
7755 Millicode insns are actually function calls with some special
7756 constraints on arguments and register usage.
7758 Millicode calls always expect their arguments in the integer argument
7759 registers, and always return their result in %r29 (ret1). They
7760 are expected to clobber their arguments, %r1, %r29, and the return
7761 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7763 This function tells reorg that the references to arguments and
7764 millicode calls do not appear to happen until after the millicode call.
7765 This allows reorg to put insns which set the argument registers into the
7766 delay slot of the millicode call -- thus they act more like traditional
7769 Note we can not consider side effects of the insn to be delayed because
7770 the branch and link insn will clobber the return pointer. If we happened
7771 to use the return pointer in the delay slot of the call, then we lose.
7773 get_attr_type will try to recognize the given insn, so make sure to
7774 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7777 insn_refs_are_delayed (insn)
7780 return ((GET_CODE (insn) == INSN
7781 && GET_CODE (PATTERN (insn)) != SEQUENCE
7782 && GET_CODE (PATTERN (insn)) != USE
7783 && GET_CODE (PATTERN (insn)) != CLOBBER
7784 && get_attr_type (insn) == TYPE_MILLI));
7787 /* On the HP-PA the value is found in register(s) 28(-29), unless
7788 the mode is SF or DF. Then the value is returned in fr4 (32).
7790 This must perform the same promotions as PROMOTE_MODE, else
7791 PROMOTE_FUNCTION_RETURN will not work correctly.
7793 Small structures must be returned in a PARALLEL on PA64 in order
7794 to match the HP Compiler ABI. */
7797 function_value (valtype, func)
7799 tree func ATTRIBUTE_UNUSED;
7801 enum machine_mode valmode;
7803 /* Aggregates with a size less than or equal to 128 bits are returned
7804 in GR 28(-29). They are left justified. The pad bits are undefined.
7805 Larger aggregates are returned in memory. */
7806 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
7810 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
7812 for (i = 0; i < ub; i++)
7814 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7815 gen_rtx_REG (DImode, 28 + i),
7820 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
7823 if ((INTEGRAL_TYPE_P (valtype)
7824 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
7825 || POINTER_TYPE_P (valtype))
7826 valmode = word_mode;
7828 valmode = TYPE_MODE (valtype);
7830 if (TREE_CODE (valtype) == REAL_TYPE
7831 && TYPE_MODE (valtype) != TFmode
7832 && !TARGET_SOFT_FLOAT)
7833 return gen_rtx_REG (valmode, 32);
7835 return gen_rtx_REG (valmode, 28);
7838 /* Return the location of a parameter that is passed in a register or NULL
7839 if the parameter has any component that is passed in memory.
7841 This is new code and will be pushed to into the net sources after
7844 ??? We might want to restructure this so that it looks more like other
7847 function_arg (cum, mode, type, named, incoming)
7848 CUMULATIVE_ARGS *cum;
7849 enum machine_mode mode;
7851 int named ATTRIBUTE_UNUSED;
7854 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7861 if (mode == VOIDmode)
7864 arg_size = FUNCTION_ARG_SIZE (mode, type);
7866 /* If this arg would be passed partially or totally on the stack, then
7867 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7868 handle arguments which are split between regs and stack slots if
7869 the ABI mandates split arguments. */
7872 /* The 32-bit ABI does not split arguments. */
7873 if (cum->words + arg_size > max_arg_words)
7879 alignment = cum->words & 1;
7880 if (cum->words + alignment >= max_arg_words)
7884 /* The 32bit ABIs and the 64bit ABIs are rather different,
7885 particularly in their handling of FP registers. We might
7886 be able to cleverly share code between them, but I'm not
7887 going to bother in the hope that splitting them up results
7888 in code that is more easily understood. */
7892 /* Advance the base registers to their current locations.
7894 Remember, gprs grow towards smaller register numbers while
7895 fprs grow to higher register numbers. Also remember that
7896 although FP regs are 32-bit addressable, we pretend that
7897 the registers are 64-bits wide. */
7898 gpr_reg_base = 26 - cum->words;
7899 fpr_reg_base = 32 + cum->words;
7901 /* Arguments wider than one word and small aggregates need special
7905 || (type && AGGREGATE_TYPE_P (type)))
7907 /* Double-extended precision (80-bit), quad-precision (128-bit)
7908 and aggregates including complex numbers are aligned on
7909 128-bit boundaries. The first eight 64-bit argument slots
7910 are associated one-to-one, with general registers r26
7911 through r19, and also with floating-point registers fr4
7912 through fr11. Arguments larger than one word are always
7913 passed in general registers.
7915 Using a PARALLEL with a word mode register results in left
7916 justified data on a big-endian target. */
7919 int i, offset = 0, ub = arg_size;
7921 /* Align the base register. */
7922 gpr_reg_base -= alignment;
7924 ub = MIN (ub, max_arg_words - cum->words - alignment);
7925 for (i = 0; i < ub; i++)
7927 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7928 gen_rtx_REG (DImode, gpr_reg_base),
7934 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7939 /* If the argument is larger than a word, then we know precisely
7940 which registers we must use. */
7954 /* Structures 5 to 8 bytes in size are passed in the general
7955 registers in the same manner as other non floating-point
7956 objects. The data is right-justified and zero-extended
7959 This is magic. Normally, using a PARALLEL results in left
7960 justified data on a big-endian target. However, using a
7961 single double-word register provides the required right
7962 justication for 5 to 8 byte structures. This has nothing
7963 to do with the direction of padding specified for the argument.
7964 It has to do with how the data is widened and shifted into
7965 and from the register.
7967 Aside from adding load_multiple and store_multiple patterns,
7968 this is the only way that I have found to obtain right
7969 justification of BLKmode data when it has a size greater
7970 than one word. Splitting the operation into two SImode loads
7971 or returning a DImode REG results in left justified data. */
7972 if (mode == BLKmode)
7974 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
7975 gen_rtx_REG (DImode, gpr_reg_base),
7977 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
7982 /* We have a single word (32 bits). A simple computation
7983 will get us the register #s we need. */
7984 gpr_reg_base = 26 - cum->words;
7985 fpr_reg_base = 32 + 2 * cum->words;
7989 /* Determine if the argument needs to be passed in both general and
7990 floating point registers. */
7991 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7992 /* If we are doing soft-float with portable runtime, then there
7993 is no need to worry about FP regs. */
7994 && ! TARGET_SOFT_FLOAT
7995 /* The parameter must be some kind of float, else we can just
7996 pass it in integer registers. */
7997 && FLOAT_MODE_P (mode)
7998 /* The target function must not have a prototype. */
7999 && cum->nargs_prototype <= 0
8000 /* libcalls do not need to pass items in both FP and general
8002 && type != NULL_TREE
8003 /* All this hair applies to outgoing args only. */
8005 /* Also pass outgoing floating arguments in both registers in indirect
8006 calls with the 32 bit ABI and the HP assembler since there is no
8007 way to the specify argument locations in static functions. */
8012 && FLOAT_MODE_P (mode)))
8018 gen_rtx_EXPR_LIST (VOIDmode,
8019 gen_rtx_REG (mode, fpr_reg_base),
8021 gen_rtx_EXPR_LIST (VOIDmode,
8022 gen_rtx_REG (mode, gpr_reg_base),
8027 /* See if we should pass this parameter in a general register. */
8028 if (TARGET_SOFT_FLOAT
8029 /* Indirect calls in the normal 32bit ABI require all arguments
8030 to be passed in general registers. */
8031 || (!TARGET_PORTABLE_RUNTIME
8035 /* If the parameter is not a floating point parameter, then
8036 it belongs in GPRs. */
8037 || !FLOAT_MODE_P (mode))
8038 retval = gen_rtx_REG (mode, gpr_reg_base);
8040 retval = gen_rtx_REG (mode, fpr_reg_base);
8046 /* If this arg would be passed totally in registers or totally on the stack,
8047 then this routine should return zero. It is currently called only for
8048 the 64-bit target. */
8050 function_arg_partial_nregs (cum, mode, type, named)
8051 CUMULATIVE_ARGS *cum;
8052 enum machine_mode mode;
8054 int named ATTRIBUTE_UNUSED;
8056 unsigned int max_arg_words = 8;
8057 unsigned int offset = 0;
8059 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8062 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8063 /* Arg fits fully into registers. */
8065 else if (cum->words + offset >= max_arg_words)
8066 /* Arg fully on the stack. */
8070 return max_arg_words - cum->words - offset;
8074 /* Return 1 if this is a comparison operator. This allows the use of
8075 MATCH_OPERATOR to recognize all the branch insns. */
8078 cmpib_comparison_operator (op, mode)
8080 enum machine_mode mode;
8082 return ((mode == VOIDmode || GET_MODE (op) == mode)
8083 && (GET_CODE (op) == EQ
8084 || GET_CODE (op) == NE
8085 || GET_CODE (op) == GT
8086 || GET_CODE (op) == GTU
8087 || GET_CODE (op) == GE
8088 || GET_CODE (op) == LT
8089 || GET_CODE (op) == LE
8090 || GET_CODE (op) == LEU));
8093 /* On hpux10, the linker will give an error if we have a reference
8094 in the read-only data section to a symbol defined in a shared
8095 library. Therefore, expressions that might require a reloc can
8096 not be placed in the read-only data section. */
8099 pa_select_section (exp, reloc, align)
8102 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
8104 if (TREE_CODE (exp) == VAR_DECL
8105 && TREE_READONLY (exp)
8106 && !TREE_THIS_VOLATILE (exp)
8107 && DECL_INITIAL (exp)
8108 && (DECL_INITIAL (exp) == error_mark_node
8109 || TREE_CONSTANT (DECL_INITIAL (exp)))
8111 readonly_data_section ();
8112 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
8113 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
8115 readonly_data_section ();
8121 pa_globalize_label (stream, name)
8125 /* We only handle DATA objects here, functions are globalized in
8126 ASM_DECLARE_FUNCTION_NAME. */
8127 if (! FUNCTION_NAME_P (name))
8129 fputs ("\t.EXPORT ", stream);
8130 assemble_name (stream, name);
8131 fputs (",DATA\n", stream);