1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static bool pa_handle_option (size_t, const char *, int);
88 static int hppa_address_cost (rtx);
89 static bool hppa_rtx_costs (rtx, int, int, int *);
90 static inline rtx force_mode (enum machine_mode, rtx);
91 static void pa_reorg (void);
92 static void pa_combine_instructions (void);
93 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
94 static int forward_branch_p (rtx);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static bool pa_scalar_mode_supported_p (enum machine_mode);
127 static bool pa_commutative_p (rtx x, int outer_code);
128 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
129 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
141 #ifdef ASM_OUTPUT_EXTERNAL_REAL
142 static void pa_hpux_file_end (void);
144 #ifdef HPUX_LONG_DOUBLE_LIBRARY
145 static void pa_hpux_init_libfuncs (void);
147 static rtx pa_struct_value_rtx (tree, int);
148 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
150 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
152 static struct machine_function * pa_init_machine_status (void);
155 /* Save the operands last given to a compare for use when we
156 generate a scc or bcc insn. */
157 rtx hppa_compare_op0, hppa_compare_op1;
158 enum cmp_type hppa_branch_type;
160 /* Which cpu we are scheduling for. */
161 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
163 /* The UNIX standard to use for predefines and linking. */
164 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
166 /* Counts for the number of callee-saved general and floating point
167 registers which were saved by the current function's prologue. */
168 static int gr_saved, fr_saved;
170 static rtx find_addr_reg (rtx);
172 /* Keep track of the number of bytes we have output in the CODE subspace
173 during this compilation so we'll know when to emit inline long-calls. */
174 unsigned long total_code_bytes;
176 /* The last address of the previous function plus the number of bytes in
177 associated thunks that have been output. This is used to determine if
178 a thunk can use an IA-relative branch to reach its target function. */
179 static int last_address;
181 /* Variables to handle plabels that we discover are necessary at assembly
182 output time. They are output after the current function. */
183 struct deferred_plabel GTY(())
188 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
190 static size_t n_deferred_plabels = 0;
193 /* Initialize the GCC target structure. */
195 #undef TARGET_ASM_ALIGNED_HI_OP
196 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
197 #undef TARGET_ASM_ALIGNED_SI_OP
198 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
199 #undef TARGET_ASM_ALIGNED_DI_OP
200 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
201 #undef TARGET_ASM_UNALIGNED_HI_OP
202 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
203 #undef TARGET_ASM_UNALIGNED_SI_OP
204 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
205 #undef TARGET_ASM_UNALIGNED_DI_OP
206 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
207 #undef TARGET_ASM_INTEGER
208 #define TARGET_ASM_INTEGER pa_assemble_integer
210 #undef TARGET_ASM_FUNCTION_PROLOGUE
211 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
212 #undef TARGET_ASM_FUNCTION_EPILOGUE
213 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
215 #undef TARGET_SCHED_ADJUST_COST
216 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
217 #undef TARGET_SCHED_ADJUST_PRIORITY
218 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
219 #undef TARGET_SCHED_ISSUE_RATE
220 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
222 #undef TARGET_ENCODE_SECTION_INFO
223 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
224 #undef TARGET_STRIP_NAME_ENCODING
225 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
227 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
228 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
230 #undef TARGET_COMMUTATIVE_P
231 #define TARGET_COMMUTATIVE_P pa_commutative_p
233 #undef TARGET_ASM_OUTPUT_MI_THUNK
234 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
235 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
236 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
238 #undef TARGET_ASM_FILE_END
239 #ifdef ASM_OUTPUT_EXTERNAL_REAL
240 #define TARGET_ASM_FILE_END pa_hpux_file_end
242 #define TARGET_ASM_FILE_END output_deferred_plabels
245 #if !defined(USE_COLLECT2)
246 #undef TARGET_ASM_CONSTRUCTOR
247 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
248 #undef TARGET_ASM_DESTRUCTOR
249 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
252 #undef TARGET_DEFAULT_TARGET_FLAGS
253 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
254 #undef TARGET_HANDLE_OPTION
255 #define TARGET_HANDLE_OPTION pa_handle_option
257 #undef TARGET_INIT_BUILTINS
258 #define TARGET_INIT_BUILTINS pa_init_builtins
260 #undef TARGET_RTX_COSTS
261 #define TARGET_RTX_COSTS hppa_rtx_costs
262 #undef TARGET_ADDRESS_COST
263 #define TARGET_ADDRESS_COST hppa_address_cost
265 #undef TARGET_MACHINE_DEPENDENT_REORG
266 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
268 #ifdef HPUX_LONG_DOUBLE_LIBRARY
269 #undef TARGET_INIT_LIBFUNCS
270 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
273 #undef TARGET_PROMOTE_FUNCTION_RETURN
274 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
275 #undef TARGET_PROMOTE_PROTOTYPES
276 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
278 #undef TARGET_STRUCT_VALUE_RTX
279 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
280 #undef TARGET_RETURN_IN_MEMORY
281 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
282 #undef TARGET_MUST_PASS_IN_STACK
283 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
284 #undef TARGET_PASS_BY_REFERENCE
285 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
286 #undef TARGET_CALLEE_COPIES
287 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
288 #undef TARGET_ARG_PARTIAL_BYTES
289 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
291 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
292 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
293 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
294 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
296 #undef TARGET_SCALAR_MODE_SUPPORTED_P
297 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
299 #undef TARGET_CANNOT_FORCE_CONST_MEM
300 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
302 struct gcc_target targetm = TARGET_INITIALIZER;
304 /* Parse the -mfixed-range= option string. */
307 fix_range (const char *const_str)
310 char *str, *dash, *comma;
312 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
313 REG2 are either register names or register numbers. The effect
314 of this option is to mark the registers in the range from REG1 to
315 REG2 as ``fixed'' so they won't be used by the compiler. This is
316 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
318 i = strlen (const_str);
319 str = (char *) alloca (i + 1);
320 memcpy (str, const_str, i + 1);
324 dash = strchr (str, '-');
327 warning (0, "value of -mfixed-range must have form REG1-REG2");
332 comma = strchr (dash + 1, ',');
336 first = decode_reg_name (str);
339 warning (0, "unknown register name: %s", str);
343 last = decode_reg_name (dash + 1);
346 warning (0, "unknown register name: %s", dash + 1);
354 warning (0, "%s-%s is an empty range", str, dash + 1);
358 for (i = first; i <= last; ++i)
359 fixed_regs[i] = call_used_regs[i] = 1;
368 /* Check if all floating point registers have been fixed. */
369 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
374 target_flags |= MASK_DISABLE_FPREGS;
377 /* Implement TARGET_HANDLE_OPTION. */
380 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
385 case OPT_mpa_risc_1_0:
387 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
391 case OPT_mpa_risc_1_1:
393 target_flags &= ~MASK_PA_20;
394 target_flags |= MASK_PA_11;
397 case OPT_mpa_risc_2_0:
399 target_flags |= MASK_PA_11 | MASK_PA_20;
403 if (strcmp (arg, "8000") == 0)
404 pa_cpu = PROCESSOR_8000;
405 else if (strcmp (arg, "7100") == 0)
406 pa_cpu = PROCESSOR_7100;
407 else if (strcmp (arg, "700") == 0)
408 pa_cpu = PROCESSOR_700;
409 else if (strcmp (arg, "7100LC") == 0)
410 pa_cpu = PROCESSOR_7100LC;
411 else if (strcmp (arg, "7200") == 0)
412 pa_cpu = PROCESSOR_7200;
413 else if (strcmp (arg, "7300") == 0)
414 pa_cpu = PROCESSOR_7300;
419 case OPT_mfixed_range_:
429 #if TARGET_HPUX_10_10
435 #if TARGET_HPUX_11_11
447 override_options (void)
449 /* Unconditional branches in the delay slot are not compatible with dwarf2
450 call frame information. There is no benefit in using this optimization
451 on PA8000 and later processors. */
452 if (pa_cpu >= PROCESSOR_8000
453 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
454 || flag_unwind_tables)
455 target_flags &= ~MASK_JUMP_IN_DELAY;
457 if (flag_pic && TARGET_PORTABLE_RUNTIME)
459 warning (0, "PIC code generation is not supported in the portable runtime model");
462 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
464 warning (0, "PIC code generation is not compatible with fast indirect calls");
467 if (! TARGET_GAS && write_symbols != NO_DEBUG)
469 warning (0, "-g is only supported when using GAS on this processor,");
470 warning (0, "-g option disabled");
471 write_symbols = NO_DEBUG;
474 /* We only support the "big PIC" model now. And we always generate PIC
475 code when in 64bit mode. */
476 if (flag_pic == 1 || TARGET_64BIT)
479 /* We can't guarantee that .dword is available for 32-bit targets. */
480 if (UNITS_PER_WORD == 4)
481 targetm.asm_out.aligned_op.di = NULL;
483 /* The unaligned ops are only available when using GAS. */
486 targetm.asm_out.unaligned_op.hi = NULL;
487 targetm.asm_out.unaligned_op.si = NULL;
488 targetm.asm_out.unaligned_op.di = NULL;
491 init_machine_status = pa_init_machine_status;
495 pa_init_builtins (void)
497 #ifdef DONT_HAVE_FPUTC_UNLOCKED
498 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
499 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
503 /* Function to init struct machine_function.
504 This will be called, via a pointer variable,
505 from push_function_context. */
507 static struct machine_function *
508 pa_init_machine_status (void)
510 return ggc_alloc_cleared (sizeof (machine_function));
513 /* If FROM is a probable pointer register, mark TO as a probable
514 pointer register with the same pointer alignment as FROM. */
517 copy_reg_pointer (rtx to, rtx from)
519 if (REG_POINTER (from))
520 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
523 /* Return 1 if X contains a symbolic expression. We know these
524 expressions will have one of a few well defined forms, so
525 we need only check those forms. */
527 symbolic_expression_p (rtx x)
530 /* Strip off any HIGH. */
531 if (GET_CODE (x) == HIGH)
534 return (symbolic_operand (x, VOIDmode));
537 /* Accept any constant that can be moved in one instruction into a
540 cint_ok_for_move (HOST_WIDE_INT intval)
542 /* OK if ldo, ldil, or zdepi, can be used. */
543 return (CONST_OK_FOR_LETTER_P (intval, 'J')
544 || CONST_OK_FOR_LETTER_P (intval, 'N')
545 || CONST_OK_FOR_LETTER_P (intval, 'K'));
548 /* Return truth value of whether OP can be used as an operand in a
551 adddi3_operand (rtx op, enum machine_mode mode)
553 return (register_operand (op, mode)
554 || (GET_CODE (op) == CONST_INT
555 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
558 /* True iff zdepi can be used to generate this CONST_INT.
559 zdepi first sign extends a 5 bit signed number to a given field
560 length, then places this field anywhere in a zero. */
562 zdepi_cint_p (unsigned HOST_WIDE_INT x)
564 unsigned HOST_WIDE_INT lsb_mask, t;
566 /* This might not be obvious, but it's at least fast.
567 This function is critical; we don't have the time loops would take. */
569 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
570 /* Return true iff t is a power of two. */
571 return ((t & (t - 1)) == 0);
574 /* True iff depi or extru can be used to compute (reg & mask).
575 Accept bit pattern like these:
580 and_mask_p (unsigned HOST_WIDE_INT mask)
583 mask += mask & -mask;
584 return (mask & (mask - 1)) == 0;
587 /* True iff depi can be used to compute (reg | MASK). */
589 ior_mask_p (unsigned HOST_WIDE_INT mask)
591 mask += mask & -mask;
592 return (mask & (mask - 1)) == 0;
595 /* Legitimize PIC addresses. If the address is already
596 position-independent, we return ORIG. Newly generated
597 position-independent addresses go to REG. If we need more
598 than one register, we lose. */
601 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
605 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
607 /* Labels need special handling. */
608 if (pic_label_operand (orig, mode))
610 /* We do not want to go through the movXX expanders here since that
611 would create recursion.
613 Nor do we really want to call a generator for a named pattern
614 since that requires multiple patterns if we want to support
617 So instead we just emit the raw set, which avoids the movXX
618 expanders completely. */
619 mark_reg_pointer (reg, BITS_PER_UNIT);
620 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
621 current_function_uses_pic_offset_table = 1;
624 if (GET_CODE (orig) == SYMBOL_REF)
630 /* Before reload, allocate a temporary register for the intermediate
631 result. This allows the sequence to be deleted when the final
632 result is unused and the insns are trivially dead. */
633 tmp_reg = ((reload_in_progress || reload_completed)
634 ? reg : gen_reg_rtx (Pmode));
636 emit_move_insn (tmp_reg,
637 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
638 gen_rtx_HIGH (word_mode, orig)));
640 = gen_const_mem (Pmode,
641 gen_rtx_LO_SUM (Pmode, tmp_reg,
642 gen_rtx_UNSPEC (Pmode,
646 current_function_uses_pic_offset_table = 1;
647 mark_reg_pointer (reg, BITS_PER_UNIT);
648 insn = emit_move_insn (reg, pic_ref);
650 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
651 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
655 else if (GET_CODE (orig) == CONST)
659 if (GET_CODE (XEXP (orig, 0)) == PLUS
660 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
664 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
666 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
667 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
668 base == reg ? 0 : reg);
670 if (GET_CODE (orig) == CONST_INT)
672 if (INT_14_BITS (orig))
673 return plus_constant (base, INTVAL (orig));
674 orig = force_reg (Pmode, orig);
676 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
677 /* Likewise, should we set special REG_NOTEs here? */
683 static GTY(()) rtx gen_tls_tga;
686 gen_tls_get_addr (void)
689 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
694 hppa_tls_call (rtx arg)
698 ret = gen_reg_rtx (Pmode);
699 emit_library_call_value (gen_tls_get_addr (), ret,
700 LCT_CONST, Pmode, 1, arg, Pmode);
706 legitimize_tls_address (rtx addr)
708 rtx ret, insn, tmp, t1, t2, tp;
709 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
713 case TLS_MODEL_GLOBAL_DYNAMIC:
714 tmp = gen_reg_rtx (Pmode);
715 emit_insn (gen_tgd_load (tmp, addr));
716 ret = hppa_tls_call (tmp);
719 case TLS_MODEL_LOCAL_DYNAMIC:
720 ret = gen_reg_rtx (Pmode);
721 tmp = gen_reg_rtx (Pmode);
723 emit_insn (gen_tld_load (tmp, addr));
724 t1 = hppa_tls_call (tmp);
727 t2 = gen_reg_rtx (Pmode);
728 emit_libcall_block (insn, t2, t1,
729 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
731 emit_insn (gen_tld_offset_load (ret, addr, t2));
734 case TLS_MODEL_INITIAL_EXEC:
735 tp = gen_reg_rtx (Pmode);
736 tmp = gen_reg_rtx (Pmode);
737 ret = gen_reg_rtx (Pmode);
738 emit_insn (gen_tp_load (tp));
739 emit_insn (gen_tie_load (tmp, addr));
740 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
743 case TLS_MODEL_LOCAL_EXEC:
744 tp = gen_reg_rtx (Pmode);
745 ret = gen_reg_rtx (Pmode);
746 emit_insn (gen_tp_load (tp));
747 emit_insn (gen_tle_load (ret, addr, tp));
757 /* Try machine-dependent ways of modifying an illegitimate address
758 to be legitimate. If we find one, return the new, valid address.
759 This macro is used in only one place: `memory_address' in explow.c.
761 OLDX is the address as it was before break_out_memory_refs was called.
762 In some cases it is useful to look at this to decide what needs to be done.
764 MODE and WIN are passed so that this macro can use
765 GO_IF_LEGITIMATE_ADDRESS.
767 It is always safe for this macro to do nothing. It exists to recognize
768 opportunities to optimize the output.
770 For the PA, transform:
772 memory(X + <large int>)
776 if (<large int> & mask) >= 16
777 Y = (<large int> & ~mask) + mask + 1 Round up.
779 Y = (<large int> & ~mask) Round down.
781 memory (Z + (<large int> - Y));
783 This is for CSE to find several similar references, and only use one Z.
785 X can either be a SYMBOL_REF or REG, but because combine cannot
786 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
787 D will not fit in 14 bits.
789 MODE_FLOAT references allow displacements which fit in 5 bits, so use
792 MODE_INT references allow displacements which fit in 14 bits, so use
795 This relies on the fact that most mode MODE_FLOAT references will use FP
796 registers and most mode MODE_INT references will use integer registers.
797 (In the rare case of an FP register used in an integer MODE, we depend
798 on secondary reloads to clean things up.)
801 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
802 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
803 addressing modes to be used).
805 Put X and Z into registers. Then put the entire expression into
809 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
810 enum machine_mode mode)
814 /* We need to canonicalize the order of operands in unscaled indexed
815 addresses since the code that checks if an address is valid doesn't
816 always try both orders. */
817 if (!TARGET_NO_SPACE_REGS
818 && GET_CODE (x) == PLUS
819 && GET_MODE (x) == Pmode
820 && REG_P (XEXP (x, 0))
821 && REG_P (XEXP (x, 1))
822 && REG_POINTER (XEXP (x, 0))
823 && !REG_POINTER (XEXP (x, 1)))
824 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
826 if (PA_SYMBOL_REF_TLS_P (x))
827 return legitimize_tls_address (x);
829 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
831 /* Strip off CONST. */
832 if (GET_CODE (x) == CONST)
835 /* Special case. Get the SYMBOL_REF into a register and use indexing.
836 That should always be safe. */
837 if (GET_CODE (x) == PLUS
838 && GET_CODE (XEXP (x, 0)) == REG
839 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
841 rtx reg = force_reg (Pmode, XEXP (x, 1));
842 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
845 /* Note we must reject symbols which represent function addresses
846 since the assembler/linker can't handle arithmetic on plabels. */
847 if (GET_CODE (x) == PLUS
848 && GET_CODE (XEXP (x, 1)) == CONST_INT
849 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
850 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
851 || GET_CODE (XEXP (x, 0)) == REG))
853 rtx int_part, ptr_reg;
855 int offset = INTVAL (XEXP (x, 1));
858 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
859 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
861 /* Choose which way to round the offset. Round up if we
862 are >= halfway to the next boundary. */
863 if ((offset & mask) >= ((mask + 1) / 2))
864 newoffset = (offset & ~ mask) + mask + 1;
866 newoffset = (offset & ~ mask);
868 /* If the newoffset will not fit in 14 bits (ldo), then
869 handling this would take 4 or 5 instructions (2 to load
870 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
871 add the new offset and the SYMBOL_REF.) Combine can
872 not handle 4->2 or 5->2 combinations, so do not create
874 if (! VAL_14_BITS_P (newoffset)
875 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
877 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
880 gen_rtx_HIGH (Pmode, const_part));
883 gen_rtx_LO_SUM (Pmode,
884 tmp_reg, const_part));
888 if (! VAL_14_BITS_P (newoffset))
889 int_part = force_reg (Pmode, GEN_INT (newoffset));
891 int_part = GEN_INT (newoffset);
893 ptr_reg = force_reg (Pmode,
895 force_reg (Pmode, XEXP (x, 0)),
898 return plus_constant (ptr_reg, offset - newoffset);
901 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
903 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
904 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
905 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
906 && (OBJECT_P (XEXP (x, 1))
907 || GET_CODE (XEXP (x, 1)) == SUBREG)
908 && GET_CODE (XEXP (x, 1)) != CONST)
910 int val = INTVAL (XEXP (XEXP (x, 0), 1));
914 if (GET_CODE (reg1) != REG)
915 reg1 = force_reg (Pmode, force_operand (reg1, 0));
917 reg2 = XEXP (XEXP (x, 0), 0);
918 if (GET_CODE (reg2) != REG)
919 reg2 = force_reg (Pmode, force_operand (reg2, 0));
921 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
928 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
930 Only do so for floating point modes since this is more speculative
931 and we lose if it's an integer store. */
932 if (GET_CODE (x) == PLUS
933 && GET_CODE (XEXP (x, 0)) == PLUS
934 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
935 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
936 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
937 && (mode == SFmode || mode == DFmode))
940 /* First, try and figure out what to use as a base register. */
941 rtx reg1, reg2, base, idx, orig_base;
943 reg1 = XEXP (XEXP (x, 0), 1);
948 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
949 then emit_move_sequence will turn on REG_POINTER so we'll know
950 it's a base register below. */
951 if (GET_CODE (reg1) != REG)
952 reg1 = force_reg (Pmode, force_operand (reg1, 0));
954 if (GET_CODE (reg2) != REG)
955 reg2 = force_reg (Pmode, force_operand (reg2, 0));
957 /* Figure out what the base and index are. */
959 if (GET_CODE (reg1) == REG
960 && REG_POINTER (reg1))
963 orig_base = XEXP (XEXP (x, 0), 1);
964 idx = gen_rtx_PLUS (Pmode,
966 XEXP (XEXP (XEXP (x, 0), 0), 0),
967 XEXP (XEXP (XEXP (x, 0), 0), 1)),
970 else if (GET_CODE (reg2) == REG
971 && REG_POINTER (reg2))
974 orig_base = XEXP (x, 1);
981 /* If the index adds a large constant, try to scale the
982 constant so that it can be loaded with only one insn. */
983 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
984 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
985 / INTVAL (XEXP (XEXP (idx, 0), 1)))
986 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
988 /* Divide the CONST_INT by the scale factor, then add it to A. */
989 int val = INTVAL (XEXP (idx, 1));
991 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
992 reg1 = XEXP (XEXP (idx, 0), 0);
993 if (GET_CODE (reg1) != REG)
994 reg1 = force_reg (Pmode, force_operand (reg1, 0));
996 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
998 /* We can now generate a simple scaled indexed address. */
1001 (Pmode, gen_rtx_PLUS (Pmode,
1002 gen_rtx_MULT (Pmode, reg1,
1003 XEXP (XEXP (idx, 0), 1)),
1007 /* If B + C is still a valid base register, then add them. */
1008 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1009 && INTVAL (XEXP (idx, 1)) <= 4096
1010 && INTVAL (XEXP (idx, 1)) >= -4096)
1012 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1015 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1017 reg2 = XEXP (XEXP (idx, 0), 0);
1018 if (GET_CODE (reg2) != CONST_INT)
1019 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1021 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1022 gen_rtx_MULT (Pmode,
1028 /* Get the index into a register, then add the base + index and
1029 return a register holding the result. */
1031 /* First get A into a register. */
1032 reg1 = XEXP (XEXP (idx, 0), 0);
1033 if (GET_CODE (reg1) != REG)
1034 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1036 /* And get B into a register. */
1037 reg2 = XEXP (idx, 1);
1038 if (GET_CODE (reg2) != REG)
1039 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1041 reg1 = force_reg (Pmode,
1042 gen_rtx_PLUS (Pmode,
1043 gen_rtx_MULT (Pmode, reg1,
1044 XEXP (XEXP (idx, 0), 1)),
1047 /* Add the result to our base register and return. */
1048 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1052 /* Uh-oh. We might have an address for x[n-100000]. This needs
1053 special handling to avoid creating an indexed memory address
1054 with x-100000 as the base.
1056 If the constant part is small enough, then it's still safe because
1057 there is a guard page at the beginning and end of the data segment.
1059 Scaled references are common enough that we want to try and rearrange the
1060 terms so that we can use indexing for these addresses too. Only
1061 do the optimization for floatint point modes. */
1063 if (GET_CODE (x) == PLUS
1064 && symbolic_expression_p (XEXP (x, 1)))
1066 /* Ugly. We modify things here so that the address offset specified
1067 by the index expression is computed first, then added to x to form
1068 the entire address. */
1070 rtx regx1, regx2, regy1, regy2, y;
1072 /* Strip off any CONST. */
1074 if (GET_CODE (y) == CONST)
1077 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1079 /* See if this looks like
1080 (plus (mult (reg) (shadd_const))
1081 (const (plus (symbol_ref) (const_int))))
1083 Where const_int is small. In that case the const
1084 expression is a valid pointer for indexing.
1086 If const_int is big, but can be divided evenly by shadd_const
1087 and added to (reg). This allows more scaled indexed addresses. */
1088 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1089 && GET_CODE (XEXP (x, 0)) == MULT
1090 && GET_CODE (XEXP (y, 1)) == CONST_INT
1091 && INTVAL (XEXP (y, 1)) >= -4096
1092 && INTVAL (XEXP (y, 1)) <= 4095
1093 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1094 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1096 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1100 if (GET_CODE (reg1) != REG)
1101 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1103 reg2 = XEXP (XEXP (x, 0), 0);
1104 if (GET_CODE (reg2) != REG)
1105 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1107 return force_reg (Pmode,
1108 gen_rtx_PLUS (Pmode,
1109 gen_rtx_MULT (Pmode,
1114 else if ((mode == DFmode || mode == SFmode)
1115 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1116 && GET_CODE (XEXP (x, 0)) == MULT
1117 && GET_CODE (XEXP (y, 1)) == CONST_INT
1118 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1119 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1120 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1123 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1124 / INTVAL (XEXP (XEXP (x, 0), 1))));
1125 regx2 = XEXP (XEXP (x, 0), 0);
1126 if (GET_CODE (regx2) != REG)
1127 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1128 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1132 gen_rtx_PLUS (Pmode,
1133 gen_rtx_MULT (Pmode, regx2,
1134 XEXP (XEXP (x, 0), 1)),
1135 force_reg (Pmode, XEXP (y, 0))));
1137 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1138 && INTVAL (XEXP (y, 1)) >= -4096
1139 && INTVAL (XEXP (y, 1)) <= 4095)
1141 /* This is safe because of the guard page at the
1142 beginning and end of the data space. Just
1143 return the original address. */
1148 /* Doesn't look like one we can optimize. */
1149 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1150 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1151 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1152 regx1 = force_reg (Pmode,
1153 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1155 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1163 /* For the HPPA, REG and REG+CONST is cost 0
1164 and addresses involving symbolic constants are cost 2.
1166 PIC addresses are very expensive.
1168 It is no coincidence that this has the same structure
1169 as GO_IF_LEGITIMATE_ADDRESS. */
1172 hppa_address_cost (rtx X)
1174 switch (GET_CODE (X))
1187 /* Compute a (partial) cost for rtx X. Return true if the complete
1188 cost has been computed, and false if subexpressions should be
1189 scanned. In either case, *TOTAL contains the cost result. */
1192 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1197 if (INTVAL (x) == 0)
1199 else if (INT_14_BITS (x))
1216 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1217 && outer_code != SET)
1224 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1225 *total = COSTS_N_INSNS (3);
1226 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1227 *total = COSTS_N_INSNS (8);
1229 *total = COSTS_N_INSNS (20);
1233 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1235 *total = COSTS_N_INSNS (14);
1243 *total = COSTS_N_INSNS (60);
1246 case PLUS: /* this includes shNadd insns */
1248 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1249 *total = COSTS_N_INSNS (3);
1251 *total = COSTS_N_INSNS (1);
1257 *total = COSTS_N_INSNS (1);
1265 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1266 new rtx with the correct mode. */
1268 force_mode (enum machine_mode mode, rtx orig)
1270 if (mode == GET_MODE (orig))
1273 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1275 return gen_rtx_REG (mode, REGNO (orig));
1278 /* Return 1 if *X is a thread-local symbol. */
1281 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1283 return PA_SYMBOL_REF_TLS_P (*x);
1286 /* Return 1 if X contains a thread-local symbol. */
1289 pa_tls_referenced_p (rtx x)
1291 if (!TARGET_HAVE_TLS)
1294 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1297 /* Emit insns to move operands[1] into operands[0].
1299 Return 1 if we have written out everything that needs to be done to
1300 do the move. Otherwise, return 0 and the caller will emit the move
1303 Note SCRATCH_REG may not be in the proper mode depending on how it
1304 will be used. This routine is responsible for creating a new copy
1305 of SCRATCH_REG in the proper mode. */
1308 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1310 register rtx operand0 = operands[0];
1311 register rtx operand1 = operands[1];
1314 /* We can only handle indexed addresses in the destination operand
1315 of floating point stores. Thus, we need to break out indexed
1316 addresses from the destination operand. */
1317 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1319 /* This is only safe up to the beginning of life analysis. */
1320 gcc_assert (!no_new_pseudos);
1322 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1323 operand0 = replace_equiv_address (operand0, tem);
1326 /* On targets with non-equivalent space registers, break out unscaled
1327 indexed addresses from the source operand before the final CSE.
1328 We have to do this because the REG_POINTER flag is not correctly
1329 carried through various optimization passes and CSE may substitute
1330 a pseudo without the pointer set for one with the pointer set. As
1331 a result, we loose various opportunities to create insns with
1332 unscaled indexed addresses. */
1333 if (!TARGET_NO_SPACE_REGS
1334 && !cse_not_expected
1335 && GET_CODE (operand1) == MEM
1336 && GET_CODE (XEXP (operand1, 0)) == PLUS
1337 && REG_P (XEXP (XEXP (operand1, 0), 0))
1338 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1340 = replace_equiv_address (operand1,
1341 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1344 && reload_in_progress && GET_CODE (operand0) == REG
1345 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1346 operand0 = reg_equiv_mem[REGNO (operand0)];
1347 else if (scratch_reg
1348 && reload_in_progress && GET_CODE (operand0) == SUBREG
1349 && GET_CODE (SUBREG_REG (operand0)) == REG
1350 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1352 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1353 the code which tracks sets/uses for delete_output_reload. */
1354 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1355 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1356 SUBREG_BYTE (operand0));
1357 operand0 = alter_subreg (&temp);
1361 && reload_in_progress && GET_CODE (operand1) == REG
1362 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1363 operand1 = reg_equiv_mem[REGNO (operand1)];
1364 else if (scratch_reg
1365 && reload_in_progress && GET_CODE (operand1) == SUBREG
1366 && GET_CODE (SUBREG_REG (operand1)) == REG
1367 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1369 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1370 the code which tracks sets/uses for delete_output_reload. */
1371 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1372 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1373 SUBREG_BYTE (operand1));
1374 operand1 = alter_subreg (&temp);
1377 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1378 && ((tem = find_replacement (&XEXP (operand0, 0)))
1379 != XEXP (operand0, 0)))
1380 operand0 = replace_equiv_address (operand0, tem);
1382 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1383 && ((tem = find_replacement (&XEXP (operand1, 0)))
1384 != XEXP (operand1, 0)))
1385 operand1 = replace_equiv_address (operand1, tem);
1387 /* Handle secondary reloads for loads/stores of FP registers from
1388 REG+D addresses where D does not fit in 5 or 14 bits, including
1389 (subreg (mem (addr))) cases. */
1391 && fp_reg_operand (operand0, mode)
1392 && ((GET_CODE (operand1) == MEM
1393 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1394 XEXP (operand1, 0)))
1395 || ((GET_CODE (operand1) == SUBREG
1396 && GET_CODE (XEXP (operand1, 0)) == MEM
1397 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1399 XEXP (XEXP (operand1, 0), 0))))))
1401 if (GET_CODE (operand1) == SUBREG)
1402 operand1 = XEXP (operand1, 0);
1404 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1405 it in WORD_MODE regardless of what mode it was originally given
1407 scratch_reg = force_mode (word_mode, scratch_reg);
1409 /* D might not fit in 14 bits either; for such cases load D into
1411 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1413 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1414 emit_move_insn (scratch_reg,
1415 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1417 XEXP (XEXP (operand1, 0), 0),
1421 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1422 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1423 replace_equiv_address (operand1, scratch_reg)));
1426 else if (scratch_reg
1427 && fp_reg_operand (operand1, mode)
1428 && ((GET_CODE (operand0) == MEM
1429 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1431 XEXP (operand0, 0)))
1432 || ((GET_CODE (operand0) == SUBREG)
1433 && GET_CODE (XEXP (operand0, 0)) == MEM
1434 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1436 XEXP (XEXP (operand0, 0), 0)))))
1438 if (GET_CODE (operand0) == SUBREG)
1439 operand0 = XEXP (operand0, 0);
1441 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1442 it in WORD_MODE regardless of what mode it was originally given
1444 scratch_reg = force_mode (word_mode, scratch_reg);
1446 /* D might not fit in 14 bits either; for such cases load D into
1448 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1450 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1451 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1454 XEXP (XEXP (operand0, 0),
1459 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1460 emit_insn (gen_rtx_SET (VOIDmode,
1461 replace_equiv_address (operand0, scratch_reg),
1465 /* Handle secondary reloads for loads of FP registers from constant
1466 expressions by forcing the constant into memory.
1468 Use scratch_reg to hold the address of the memory location.
1470 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1471 NO_REGS when presented with a const_int and a register class
1472 containing only FP registers. Doing so unfortunately creates
1473 more problems than it solves. Fix this for 2.5. */
1474 else if (scratch_reg
1475 && CONSTANT_P (operand1)
1476 && fp_reg_operand (operand0, mode))
1478 rtx const_mem, xoperands[2];
1480 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1481 it in WORD_MODE regardless of what mode it was originally given
1483 scratch_reg = force_mode (word_mode, scratch_reg);
1485 /* Force the constant into memory and put the address of the
1486 memory location into scratch_reg. */
1487 const_mem = force_const_mem (mode, operand1);
1488 xoperands[0] = scratch_reg;
1489 xoperands[1] = XEXP (const_mem, 0);
1490 emit_move_sequence (xoperands, Pmode, 0);
1492 /* Now load the destination register. */
1493 emit_insn (gen_rtx_SET (mode, operand0,
1494 replace_equiv_address (const_mem, scratch_reg)));
1497 /* Handle secondary reloads for SAR. These occur when trying to load
1498 the SAR from memory, FP register, or with a constant. */
1499 else if (scratch_reg
1500 && GET_CODE (operand0) == REG
1501 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1502 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1503 && (GET_CODE (operand1) == MEM
1504 || GET_CODE (operand1) == CONST_INT
1505 || (GET_CODE (operand1) == REG
1506 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1508 /* D might not fit in 14 bits either; for such cases load D into
1510 if (GET_CODE (operand1) == MEM
1511 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1513 /* We are reloading the address into the scratch register, so we
1514 want to make sure the scratch register is a full register. */
1515 scratch_reg = force_mode (word_mode, scratch_reg);
1517 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1518 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1521 XEXP (XEXP (operand1, 0),
1525 /* Now we are going to load the scratch register from memory,
1526 we want to load it in the same width as the original MEM,
1527 which must be the same as the width of the ultimate destination,
1529 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1531 emit_move_insn (scratch_reg,
1532 replace_equiv_address (operand1, scratch_reg));
1536 /* We want to load the scratch register using the same mode as
1537 the ultimate destination. */
1538 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1540 emit_move_insn (scratch_reg, operand1);
1543 /* And emit the insn to set the ultimate destination. We know that
1544 the scratch register has the same mode as the destination at this
1546 emit_move_insn (operand0, scratch_reg);
1549 /* Handle the most common case: storing into a register. */
1550 else if (register_operand (operand0, mode))
1552 if (register_operand (operand1, mode)
1553 || (GET_CODE (operand1) == CONST_INT
1554 && cint_ok_for_move (INTVAL (operand1)))
1555 || (operand1 == CONST0_RTX (mode))
1556 || (GET_CODE (operand1) == HIGH
1557 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1558 /* Only `general_operands' can come here, so MEM is ok. */
1559 || GET_CODE (operand1) == MEM)
1561 /* Various sets are created during RTL generation which don't
1562 have the REG_POINTER flag correctly set. After the CSE pass,
1563 instruction recognition can fail if we don't consistently
1564 set this flag when performing register copies. This should
1565 also improve the opportunities for creating insns that use
1566 unscaled indexing. */
1567 if (REG_P (operand0) && REG_P (operand1))
1569 if (REG_POINTER (operand1)
1570 && !REG_POINTER (operand0)
1571 && !HARD_REGISTER_P (operand0))
1572 copy_reg_pointer (operand0, operand1);
1573 else if (REG_POINTER (operand0)
1574 && !REG_POINTER (operand1)
1575 && !HARD_REGISTER_P (operand1))
1576 copy_reg_pointer (operand1, operand0);
1579 /* When MEMs are broken out, the REG_POINTER flag doesn't
1580 get set. In some cases, we can set the REG_POINTER flag
1581 from the declaration for the MEM. */
1582 if (REG_P (operand0)
1583 && GET_CODE (operand1) == MEM
1584 && !REG_POINTER (operand0))
1586 tree decl = MEM_EXPR (operand1);
1588 /* Set the register pointer flag and register alignment
1589 if the declaration for this memory reference is a
1590 pointer type. Fortran indirect argument references
1593 && !(flag_argument_noalias > 1
1594 && TREE_CODE (decl) == INDIRECT_REF
1595 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1599 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1601 if (TREE_CODE (decl) == COMPONENT_REF)
1602 decl = TREE_OPERAND (decl, 1);
1604 type = TREE_TYPE (decl);
1605 if (TREE_CODE (type) == ARRAY_TYPE)
1606 type = get_inner_array_type (type);
1608 if (POINTER_TYPE_P (type))
1612 type = TREE_TYPE (type);
1613 /* Using TYPE_ALIGN_OK is rather conservative as
1614 only the ada frontend actually sets it. */
1615 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1617 mark_reg_pointer (operand0, align);
1622 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1626 else if (GET_CODE (operand0) == MEM)
1628 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1629 && !(reload_in_progress || reload_completed))
1631 rtx temp = gen_reg_rtx (DFmode);
1633 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1634 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1637 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1639 /* Run this case quickly. */
1640 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1643 if (! (reload_in_progress || reload_completed))
1645 operands[0] = validize_mem (operand0);
1646 operands[1] = operand1 = force_reg (mode, operand1);
1650 /* Simplify the source if we need to.
1651 Note we do have to handle function labels here, even though we do
1652 not consider them legitimate constants. Loop optimizations can
1653 call the emit_move_xxx with one as a source. */
1654 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1655 || function_label_operand (operand1, mode)
1656 || (GET_CODE (operand1) == HIGH
1657 && symbolic_operand (XEXP (operand1, 0), mode)))
1661 if (GET_CODE (operand1) == HIGH)
1664 operand1 = XEXP (operand1, 0);
1666 if (symbolic_operand (operand1, mode))
1668 /* Argh. The assembler and linker can't handle arithmetic
1671 So we force the plabel into memory, load operand0 from
1672 the memory location, then add in the constant part. */
1673 if ((GET_CODE (operand1) == CONST
1674 && GET_CODE (XEXP (operand1, 0)) == PLUS
1675 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1676 || function_label_operand (operand1, mode))
1678 rtx temp, const_part;
1680 /* Figure out what (if any) scratch register to use. */
1681 if (reload_in_progress || reload_completed)
1683 scratch_reg = scratch_reg ? scratch_reg : operand0;
1684 /* SCRATCH_REG will hold an address and maybe the actual
1685 data. We want it in WORD_MODE regardless of what mode it
1686 was originally given to us. */
1687 scratch_reg = force_mode (word_mode, scratch_reg);
1690 scratch_reg = gen_reg_rtx (Pmode);
1692 if (GET_CODE (operand1) == CONST)
1694 /* Save away the constant part of the expression. */
1695 const_part = XEXP (XEXP (operand1, 0), 1);
1696 gcc_assert (GET_CODE (const_part) == CONST_INT);
1698 /* Force the function label into memory. */
1699 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1703 /* No constant part. */
1704 const_part = NULL_RTX;
1706 /* Force the function label into memory. */
1707 temp = force_const_mem (mode, operand1);
1711 /* Get the address of the memory location. PIC-ify it if
1713 temp = XEXP (temp, 0);
1715 temp = legitimize_pic_address (temp, mode, scratch_reg);
1717 /* Put the address of the memory location into our destination
1720 emit_move_sequence (operands, mode, scratch_reg);
1722 /* Now load from the memory location into our destination
1724 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1725 emit_move_sequence (operands, mode, scratch_reg);
1727 /* And add back in the constant part. */
1728 if (const_part != NULL_RTX)
1729 expand_inc (operand0, const_part);
1738 if (reload_in_progress || reload_completed)
1740 temp = scratch_reg ? scratch_reg : operand0;
1741 /* TEMP will hold an address and maybe the actual
1742 data. We want it in WORD_MODE regardless of what mode it
1743 was originally given to us. */
1744 temp = force_mode (word_mode, temp);
1747 temp = gen_reg_rtx (Pmode);
1749 /* (const (plus (symbol) (const_int))) must be forced to
1750 memory during/after reload if the const_int will not fit
1752 if (GET_CODE (operand1) == CONST
1753 && GET_CODE (XEXP (operand1, 0)) == PLUS
1754 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1755 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1756 && (reload_completed || reload_in_progress)
1759 rtx const_mem = force_const_mem (mode, operand1);
1760 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1762 operands[1] = replace_equiv_address (const_mem, operands[1]);
1763 emit_move_sequence (operands, mode, temp);
1767 operands[1] = legitimize_pic_address (operand1, mode, temp);
1768 if (REG_P (operand0) && REG_P (operands[1]))
1769 copy_reg_pointer (operand0, operands[1]);
1770 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1773 /* On the HPPA, references to data space are supposed to use dp,
1774 register 27, but showing it in the RTL inhibits various cse
1775 and loop optimizations. */
1780 if (reload_in_progress || reload_completed)
1782 temp = scratch_reg ? scratch_reg : operand0;
1783 /* TEMP will hold an address and maybe the actual
1784 data. We want it in WORD_MODE regardless of what mode it
1785 was originally given to us. */
1786 temp = force_mode (word_mode, temp);
1789 temp = gen_reg_rtx (mode);
1791 /* Loading a SYMBOL_REF into a register makes that register
1792 safe to be used as the base in an indexed address.
1794 Don't mark hard registers though. That loses. */
1795 if (GET_CODE (operand0) == REG
1796 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1797 mark_reg_pointer (operand0, BITS_PER_UNIT);
1798 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1799 mark_reg_pointer (temp, BITS_PER_UNIT);
1802 set = gen_rtx_SET (mode, operand0, temp);
1804 set = gen_rtx_SET (VOIDmode,
1806 gen_rtx_LO_SUM (mode, temp, operand1));
1808 emit_insn (gen_rtx_SET (VOIDmode,
1810 gen_rtx_HIGH (mode, operand1)));
1816 else if (pa_tls_referenced_p (operand1))
1821 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
1823 addend = XEXP (XEXP (tmp, 0), 1);
1824 tmp = XEXP (XEXP (tmp, 0), 0);
1827 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
1828 tmp = legitimize_tls_address (tmp);
1831 tmp = gen_rtx_PLUS (mode, tmp, addend);
1832 tmp = force_operand (tmp, operands[0]);
1836 else if (GET_CODE (operand1) != CONST_INT
1837 || !cint_ok_for_move (INTVAL (operand1)))
1841 HOST_WIDE_INT value = 0;
1842 HOST_WIDE_INT insv = 0;
1845 if (GET_CODE (operand1) == CONST_INT)
1846 value = INTVAL (operand1);
1849 && GET_CODE (operand1) == CONST_INT
1850 && HOST_BITS_PER_WIDE_INT > 32
1851 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1855 /* Extract the low order 32 bits of the value and sign extend.
1856 If the new value is the same as the original value, we can
1857 can use the original value as-is. If the new value is
1858 different, we use it and insert the most-significant 32-bits
1859 of the original value into the final result. */
1860 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1861 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1864 #if HOST_BITS_PER_WIDE_INT > 32
1865 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1869 operand1 = GEN_INT (nval);
1873 if (reload_in_progress || reload_completed)
1874 temp = scratch_reg ? scratch_reg : operand0;
1876 temp = gen_reg_rtx (mode);
1878 /* We don't directly split DImode constants on 32-bit targets
1879 because PLUS uses an 11-bit immediate and the insn sequence
1880 generated is not as efficient as the one using HIGH/LO_SUM. */
1881 if (GET_CODE (operand1) == CONST_INT
1882 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1885 /* Directly break constant into high and low parts. This
1886 provides better optimization opportunities because various
1887 passes recognize constants split with PLUS but not LO_SUM.
1888 We use a 14-bit signed low part except when the addition
1889 of 0x4000 to the high part might change the sign of the
1891 HOST_WIDE_INT low = value & 0x3fff;
1892 HOST_WIDE_INT high = value & ~ 0x3fff;
1896 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1904 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1905 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1909 emit_insn (gen_rtx_SET (VOIDmode, temp,
1910 gen_rtx_HIGH (mode, operand1)));
1911 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1914 insn = emit_move_insn (operands[0], operands[1]);
1916 /* Now insert the most significant 32 bits of the value
1917 into the register. When we don't have a second register
1918 available, it could take up to nine instructions to load
1919 a 64-bit integer constant. Prior to reload, we force
1920 constants that would take more than three instructions
1921 to load to the constant pool. During and after reload,
1922 we have to handle all possible values. */
1925 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
1926 register and the value to be inserted is outside the
1927 range that can be loaded with three depdi instructions. */
1928 if (temp != operand0 && (insv >= 16384 || insv < -16384))
1930 operand1 = GEN_INT (insv);
1932 emit_insn (gen_rtx_SET (VOIDmode, temp,
1933 gen_rtx_HIGH (mode, operand1)));
1934 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
1935 emit_insn (gen_insv (operand0, GEN_INT (32),
1940 int len = 5, pos = 27;
1942 /* Insert the bits using the depdi instruction. */
1945 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
1946 HOST_WIDE_INT sign = v5 < 0;
1948 /* Left extend the insertion. */
1949 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
1950 while (pos > 0 && (insv & 1) == sign)
1952 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
1957 emit_insn (gen_insv (operand0, GEN_INT (len),
1958 GEN_INT (pos), GEN_INT (v5)));
1960 len = pos > 0 && pos < 5 ? pos : 5;
1967 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
1972 /* Now have insn-emit do whatever it normally does. */
1976 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1977 it will need a link/runtime reloc). */
1980 reloc_needed (tree exp)
1984 switch (TREE_CODE (exp))
1991 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1992 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1997 case NON_LVALUE_EXPR:
1998 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2004 unsigned HOST_WIDE_INT ix;
2006 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2008 reloc |= reloc_needed (value);
2021 /* Does operand (which is a symbolic_operand) live in text space?
2022 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2026 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2028 if (GET_CODE (operand) == CONST)
2029 operand = XEXP (XEXP (operand, 0), 0);
2032 if (GET_CODE (operand) == SYMBOL_REF)
2033 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2037 if (GET_CODE (operand) == SYMBOL_REF)
2038 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2044 /* Return the best assembler insn template
2045 for moving operands[1] into operands[0] as a fullword. */
2047 singlemove_string (rtx *operands)
2049 HOST_WIDE_INT intval;
2051 if (GET_CODE (operands[0]) == MEM)
2052 return "stw %r1,%0";
2053 if (GET_CODE (operands[1]) == MEM)
2055 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2060 gcc_assert (GET_MODE (operands[1]) == SFmode);
2062 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2064 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2065 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2067 operands[1] = GEN_INT (i);
2068 /* Fall through to CONST_INT case. */
2070 if (GET_CODE (operands[1]) == CONST_INT)
2072 intval = INTVAL (operands[1]);
2074 if (VAL_14_BITS_P (intval))
2076 else if ((intval & 0x7ff) == 0)
2077 return "ldil L'%1,%0";
2078 else if (zdepi_cint_p (intval))
2079 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2081 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2083 return "copy %1,%0";
2087 /* Compute position (in OP[1]) and width (in OP[2])
2088 useful for copying IMM to a register using the zdepi
2089 instructions. Store the immediate value to insert in OP[0]. */
2091 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2095 /* Find the least significant set bit in IMM. */
2096 for (lsb = 0; lsb < 32; lsb++)
2103 /* Choose variants based on *sign* of the 5-bit field. */
2104 if ((imm & 0x10) == 0)
2105 len = (lsb <= 28) ? 4 : 32 - lsb;
2108 /* Find the width of the bitstring in IMM. */
2109 for (len = 5; len < 32; len++)
2111 if ((imm & (1 << len)) == 0)
2115 /* Sign extend IMM as a 5-bit value. */
2116 imm = (imm & 0xf) - 0x10;
2124 /* Compute position (in OP[1]) and width (in OP[2])
2125 useful for copying IMM to a register using the depdi,z
2126 instructions. Store the immediate value to insert in OP[0]. */
2128 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2130 HOST_WIDE_INT lsb, len;
2132 /* Find the least significant set bit in IMM. */
2133 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2140 /* Choose variants based on *sign* of the 5-bit field. */
2141 if ((imm & 0x10) == 0)
2142 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2143 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2146 /* Find the width of the bitstring in IMM. */
2147 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2149 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2153 /* Sign extend IMM as a 5-bit value. */
2154 imm = (imm & 0xf) - 0x10;
2162 /* Output assembler code to perform a doubleword move insn
2163 with operands OPERANDS. */
2166 output_move_double (rtx *operands)
2168 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2170 rtx addreg0 = 0, addreg1 = 0;
2172 /* First classify both operands. */
2174 if (REG_P (operands[0]))
2176 else if (offsettable_memref_p (operands[0]))
2178 else if (GET_CODE (operands[0]) == MEM)
2183 if (REG_P (operands[1]))
2185 else if (CONSTANT_P (operands[1]))
2187 else if (offsettable_memref_p (operands[1]))
2189 else if (GET_CODE (operands[1]) == MEM)
2194 /* Check for the cases that the operand constraints are not
2195 supposed to allow to happen. */
2196 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2198 /* Handle auto decrementing and incrementing loads and stores
2199 specifically, since the structure of the function doesn't work
2200 for them without major modification. Do it better when we learn
2201 this port about the general inc/dec addressing of PA.
2202 (This was written by tege. Chide him if it doesn't work.) */
2204 if (optype0 == MEMOP)
2206 /* We have to output the address syntax ourselves, since print_operand
2207 doesn't deal with the addresses we want to use. Fix this later. */
2209 rtx addr = XEXP (operands[0], 0);
2210 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2212 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2214 operands[0] = XEXP (addr, 0);
2215 gcc_assert (GET_CODE (operands[1]) == REG
2216 && GET_CODE (operands[0]) == REG);
2218 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2220 /* No overlap between high target register and address
2221 register. (We do this in a non-obvious way to
2222 save a register file writeback) */
2223 if (GET_CODE (addr) == POST_INC)
2224 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2225 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2227 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2229 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2231 operands[0] = XEXP (addr, 0);
2232 gcc_assert (GET_CODE (operands[1]) == REG
2233 && GET_CODE (operands[0]) == REG);
2235 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2236 /* No overlap between high target register and address
2237 register. (We do this in a non-obvious way to save a
2238 register file writeback) */
2239 if (GET_CODE (addr) == PRE_INC)
2240 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2241 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2244 if (optype1 == MEMOP)
2246 /* We have to output the address syntax ourselves, since print_operand
2247 doesn't deal with the addresses we want to use. Fix this later. */
2249 rtx addr = XEXP (operands[1], 0);
2250 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2252 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2254 operands[1] = XEXP (addr, 0);
2255 gcc_assert (GET_CODE (operands[0]) == REG
2256 && GET_CODE (operands[1]) == REG);
2258 if (!reg_overlap_mentioned_p (high_reg, addr))
2260 /* No overlap between high target register and address
2261 register. (We do this in a non-obvious way to
2262 save a register file writeback) */
2263 if (GET_CODE (addr) == POST_INC)
2264 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2265 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2269 /* This is an undefined situation. We should load into the
2270 address register *and* update that register. Probably
2271 we don't need to handle this at all. */
2272 if (GET_CODE (addr) == POST_INC)
2273 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2274 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2277 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2279 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2281 operands[1] = XEXP (addr, 0);
2282 gcc_assert (GET_CODE (operands[0]) == REG
2283 && GET_CODE (operands[1]) == REG);
2285 if (!reg_overlap_mentioned_p (high_reg, addr))
2287 /* No overlap between high target register and address
2288 register. (We do this in a non-obvious way to
2289 save a register file writeback) */
2290 if (GET_CODE (addr) == PRE_INC)
2291 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2292 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2296 /* This is an undefined situation. We should load into the
2297 address register *and* update that register. Probably
2298 we don't need to handle this at all. */
2299 if (GET_CODE (addr) == PRE_INC)
2300 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2301 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2304 else if (GET_CODE (addr) == PLUS
2305 && GET_CODE (XEXP (addr, 0)) == MULT)
2307 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2309 if (!reg_overlap_mentioned_p (high_reg, addr))
2313 xoperands[0] = high_reg;
2314 xoperands[1] = XEXP (addr, 1);
2315 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2316 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2317 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2319 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2325 xoperands[0] = high_reg;
2326 xoperands[1] = XEXP (addr, 1);
2327 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2328 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2329 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2331 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2336 /* If an operand is an unoffsettable memory ref, find a register
2337 we can increment temporarily to make it refer to the second word. */
2339 if (optype0 == MEMOP)
2340 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2342 if (optype1 == MEMOP)
2343 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2345 /* Ok, we can do one word at a time.
2346 Normally we do the low-numbered word first.
2348 In either case, set up in LATEHALF the operands to use
2349 for the high-numbered word and in some cases alter the
2350 operands in OPERANDS to be suitable for the low-numbered word. */
2352 if (optype0 == REGOP)
2353 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2354 else if (optype0 == OFFSOP)
2355 latehalf[0] = adjust_address (operands[0], SImode, 4);
2357 latehalf[0] = operands[0];
2359 if (optype1 == REGOP)
2360 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2361 else if (optype1 == OFFSOP)
2362 latehalf[1] = adjust_address (operands[1], SImode, 4);
2363 else if (optype1 == CNSTOP)
2364 split_double (operands[1], &operands[1], &latehalf[1]);
2366 latehalf[1] = operands[1];
2368 /* If the first move would clobber the source of the second one,
2369 do them in the other order.
2371 This can happen in two cases:
2373 mem -> register where the first half of the destination register
2374 is the same register used in the memory's address. Reload
2375 can create such insns.
2377 mem in this case will be either register indirect or register
2378 indirect plus a valid offset.
2380 register -> register move where REGNO(dst) == REGNO(src + 1)
2381 someone (Tim/Tege?) claimed this can happen for parameter loads.
2383 Handle mem -> register case first. */
2384 if (optype0 == REGOP
2385 && (optype1 == MEMOP || optype1 == OFFSOP)
2386 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2389 /* Do the late half first. */
2391 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2392 output_asm_insn (singlemove_string (latehalf), latehalf);
2396 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2397 return singlemove_string (operands);
2400 /* Now handle register -> register case. */
2401 if (optype0 == REGOP && optype1 == REGOP
2402 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2404 output_asm_insn (singlemove_string (latehalf), latehalf);
2405 return singlemove_string (operands);
2408 /* Normal case: do the two words, low-numbered first. */
2410 output_asm_insn (singlemove_string (operands), operands);
2412 /* Make any unoffsettable addresses point at high-numbered word. */
2414 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2416 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2419 output_asm_insn (singlemove_string (latehalf), latehalf);
2421 /* Undo the adds we just did. */
2423 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2425 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2431 output_fp_move_double (rtx *operands)
2433 if (FP_REG_P (operands[0]))
2435 if (FP_REG_P (operands[1])
2436 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2437 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2439 output_asm_insn ("fldd%F1 %1,%0", operands);
2441 else if (FP_REG_P (operands[1]))
2443 output_asm_insn ("fstd%F0 %1,%0", operands);
2449 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2451 /* This is a pain. You have to be prepared to deal with an
2452 arbitrary address here including pre/post increment/decrement.
2454 so avoid this in the MD. */
2455 gcc_assert (GET_CODE (operands[0]) == REG);
2457 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2458 xoperands[0] = operands[0];
2459 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2464 /* Return a REG that occurs in ADDR with coefficient 1.
2465 ADDR can be effectively incremented by incrementing REG. */
2468 find_addr_reg (rtx addr)
2470 while (GET_CODE (addr) == PLUS)
2472 if (GET_CODE (XEXP (addr, 0)) == REG)
2473 addr = XEXP (addr, 0);
2474 else if (GET_CODE (XEXP (addr, 1)) == REG)
2475 addr = XEXP (addr, 1);
2476 else if (CONSTANT_P (XEXP (addr, 0)))
2477 addr = XEXP (addr, 1);
2478 else if (CONSTANT_P (XEXP (addr, 1)))
2479 addr = XEXP (addr, 0);
2483 gcc_assert (GET_CODE (addr) == REG);
2487 /* Emit code to perform a block move.
2489 OPERANDS[0] is the destination pointer as a REG, clobbered.
2490 OPERANDS[1] is the source pointer as a REG, clobbered.
2491 OPERANDS[2] is a register for temporary storage.
2492 OPERANDS[3] is a register for temporary storage.
2493 OPERANDS[4] is the size as a CONST_INT
2494 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2495 OPERANDS[6] is another temporary register. */
2498 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2500 int align = INTVAL (operands[5]);
2501 unsigned long n_bytes = INTVAL (operands[4]);
2503 /* We can't move more than a word at a time because the PA
2504 has no longer integer move insns. (Could use fp mem ops?) */
2505 if (align > (TARGET_64BIT ? 8 : 4))
2506 align = (TARGET_64BIT ? 8 : 4);
2508 /* Note that we know each loop below will execute at least twice
2509 (else we would have open-coded the copy). */
2513 /* Pre-adjust the loop counter. */
2514 operands[4] = GEN_INT (n_bytes - 16);
2515 output_asm_insn ("ldi %4,%2", operands);
2518 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2519 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2520 output_asm_insn ("std,ma %3,8(%0)", operands);
2521 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2522 output_asm_insn ("std,ma %6,8(%0)", operands);
2524 /* Handle the residual. There could be up to 7 bytes of
2525 residual to copy! */
2526 if (n_bytes % 16 != 0)
2528 operands[4] = GEN_INT (n_bytes % 8);
2529 if (n_bytes % 16 >= 8)
2530 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2531 if (n_bytes % 8 != 0)
2532 output_asm_insn ("ldd 0(%1),%6", operands);
2533 if (n_bytes % 16 >= 8)
2534 output_asm_insn ("std,ma %3,8(%0)", operands);
2535 if (n_bytes % 8 != 0)
2536 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2541 /* Pre-adjust the loop counter. */
2542 operands[4] = GEN_INT (n_bytes - 8);
2543 output_asm_insn ("ldi %4,%2", operands);
2546 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2547 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2548 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2549 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2550 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2552 /* Handle the residual. There could be up to 7 bytes of
2553 residual to copy! */
2554 if (n_bytes % 8 != 0)
2556 operands[4] = GEN_INT (n_bytes % 4);
2557 if (n_bytes % 8 >= 4)
2558 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2559 if (n_bytes % 4 != 0)
2560 output_asm_insn ("ldw 0(%1),%6", operands);
2561 if (n_bytes % 8 >= 4)
2562 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2563 if (n_bytes % 4 != 0)
2564 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2569 /* Pre-adjust the loop counter. */
2570 operands[4] = GEN_INT (n_bytes - 4);
2571 output_asm_insn ("ldi %4,%2", operands);
2574 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2575 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2576 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2577 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2578 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2580 /* Handle the residual. */
2581 if (n_bytes % 4 != 0)
2583 if (n_bytes % 4 >= 2)
2584 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2585 if (n_bytes % 2 != 0)
2586 output_asm_insn ("ldb 0(%1),%6", operands);
2587 if (n_bytes % 4 >= 2)
2588 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2589 if (n_bytes % 2 != 0)
2590 output_asm_insn ("stb %6,0(%0)", operands);
2595 /* Pre-adjust the loop counter. */
2596 operands[4] = GEN_INT (n_bytes - 2);
2597 output_asm_insn ("ldi %4,%2", operands);
2600 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2601 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2602 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2603 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2604 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2606 /* Handle the residual. */
2607 if (n_bytes % 2 != 0)
2609 output_asm_insn ("ldb 0(%1),%3", operands);
2610 output_asm_insn ("stb %3,0(%0)", operands);
2619 /* Count the number of insns necessary to handle this block move.
2621 Basic structure is the same as emit_block_move, except that we
2622 count insns rather than emit them. */
2625 compute_movmem_length (rtx insn)
2627 rtx pat = PATTERN (insn);
2628 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2629 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2630 unsigned int n_insns = 0;
2632 /* We can't move more than four bytes at a time because the PA
2633 has no longer integer move insns. (Could use fp mem ops?) */
2634 if (align > (TARGET_64BIT ? 8 : 4))
2635 align = (TARGET_64BIT ? 8 : 4);
2637 /* The basic copying loop. */
2641 if (n_bytes % (2 * align) != 0)
2643 if ((n_bytes % (2 * align)) >= align)
2646 if ((n_bytes % align) != 0)
2650 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2654 /* Emit code to perform a block clear.
2656 OPERANDS[0] is the destination pointer as a REG, clobbered.
2657 OPERANDS[1] is a register for temporary storage.
2658 OPERANDS[2] is the size as a CONST_INT
2659 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2662 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2664 int align = INTVAL (operands[3]);
2665 unsigned long n_bytes = INTVAL (operands[2]);
2667 /* We can't clear more than a word at a time because the PA
2668 has no longer integer move insns. */
2669 if (align > (TARGET_64BIT ? 8 : 4))
2670 align = (TARGET_64BIT ? 8 : 4);
2672 /* Note that we know each loop below will execute at least twice
2673 (else we would have open-coded the copy). */
2677 /* Pre-adjust the loop counter. */
2678 operands[2] = GEN_INT (n_bytes - 16);
2679 output_asm_insn ("ldi %2,%1", operands);
2682 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2683 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2684 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2686 /* Handle the residual. There could be up to 7 bytes of
2687 residual to copy! */
2688 if (n_bytes % 16 != 0)
2690 operands[2] = GEN_INT (n_bytes % 8);
2691 if (n_bytes % 16 >= 8)
2692 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2693 if (n_bytes % 8 != 0)
2694 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2699 /* Pre-adjust the loop counter. */
2700 operands[2] = GEN_INT (n_bytes - 8);
2701 output_asm_insn ("ldi %2,%1", operands);
2704 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2705 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2706 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2708 /* Handle the residual. There could be up to 7 bytes of
2709 residual to copy! */
2710 if (n_bytes % 8 != 0)
2712 operands[2] = GEN_INT (n_bytes % 4);
2713 if (n_bytes % 8 >= 4)
2714 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2715 if (n_bytes % 4 != 0)
2716 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2721 /* Pre-adjust the loop counter. */
2722 operands[2] = GEN_INT (n_bytes - 4);
2723 output_asm_insn ("ldi %2,%1", operands);
2726 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2727 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2728 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2730 /* Handle the residual. */
2731 if (n_bytes % 4 != 0)
2733 if (n_bytes % 4 >= 2)
2734 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2735 if (n_bytes % 2 != 0)
2736 output_asm_insn ("stb %%r0,0(%0)", operands);
2741 /* Pre-adjust the loop counter. */
2742 operands[2] = GEN_INT (n_bytes - 2);
2743 output_asm_insn ("ldi %2,%1", operands);
2746 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2747 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2748 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2750 /* Handle the residual. */
2751 if (n_bytes % 2 != 0)
2752 output_asm_insn ("stb %%r0,0(%0)", operands);
2761 /* Count the number of insns necessary to handle this block move.
2763 Basic structure is the same as emit_block_move, except that we
2764 count insns rather than emit them. */
2767 compute_clrmem_length (rtx insn)
2769 rtx pat = PATTERN (insn);
2770 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2771 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2772 unsigned int n_insns = 0;
2774 /* We can't clear more than a word at a time because the PA
2775 has no longer integer move insns. */
2776 if (align > (TARGET_64BIT ? 8 : 4))
2777 align = (TARGET_64BIT ? 8 : 4);
2779 /* The basic loop. */
2783 if (n_bytes % (2 * align) != 0)
2785 if ((n_bytes % (2 * align)) >= align)
2788 if ((n_bytes % align) != 0)
2792 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2798 output_and (rtx *operands)
2800 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2802 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2803 int ls0, ls1, ms0, p, len;
2805 for (ls0 = 0; ls0 < 32; ls0++)
2806 if ((mask & (1 << ls0)) == 0)
2809 for (ls1 = ls0; ls1 < 32; ls1++)
2810 if ((mask & (1 << ls1)) != 0)
2813 for (ms0 = ls1; ms0 < 32; ms0++)
2814 if ((mask & (1 << ms0)) == 0)
2817 gcc_assert (ms0 == 32);
2825 operands[2] = GEN_INT (len);
2826 return "{extru|extrw,u} %1,31,%2,%0";
2830 /* We could use this `depi' for the case above as well, but `depi'
2831 requires one more register file access than an `extru'. */
2836 operands[2] = GEN_INT (p);
2837 operands[3] = GEN_INT (len);
2838 return "{depi|depwi} 0,%2,%3,%0";
2842 return "and %1,%2,%0";
2845 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2846 storing the result in operands[0]. */
2848 output_64bit_and (rtx *operands)
2850 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2852 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2853 int ls0, ls1, ms0, p, len;
2855 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2856 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2859 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2860 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2863 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2864 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2867 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2869 if (ls1 == HOST_BITS_PER_WIDE_INT)
2875 operands[2] = GEN_INT (len);
2876 return "extrd,u %1,63,%2,%0";
2880 /* We could use this `depi' for the case above as well, but `depi'
2881 requires one more register file access than an `extru'. */
2886 operands[2] = GEN_INT (p);
2887 operands[3] = GEN_INT (len);
2888 return "depdi 0,%2,%3,%0";
2892 return "and %1,%2,%0";
2896 output_ior (rtx *operands)
2898 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2899 int bs0, bs1, p, len;
2901 if (INTVAL (operands[2]) == 0)
2902 return "copy %1,%0";
2904 for (bs0 = 0; bs0 < 32; bs0++)
2905 if ((mask & (1 << bs0)) != 0)
2908 for (bs1 = bs0; bs1 < 32; bs1++)
2909 if ((mask & (1 << bs1)) == 0)
2912 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2917 operands[2] = GEN_INT (p);
2918 operands[3] = GEN_INT (len);
2919 return "{depi|depwi} -1,%2,%3,%0";
2922 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2923 storing the result in operands[0]. */
2925 output_64bit_ior (rtx *operands)
2927 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2928 int bs0, bs1, p, len;
2930 if (INTVAL (operands[2]) == 0)
2931 return "copy %1,%0";
2933 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2934 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2937 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2938 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2941 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
2942 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2947 operands[2] = GEN_INT (p);
2948 operands[3] = GEN_INT (len);
2949 return "depdi -1,%2,%3,%0";
2952 /* Target hook for assembling integer objects. This code handles
2953 aligned SI and DI integers specially since function references
2954 must be preceded by P%. */
2957 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
2959 if (size == UNITS_PER_WORD
2961 && function_label_operand (x, VOIDmode))
2963 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2964 output_addr_const (asm_out_file, x);
2965 fputc ('\n', asm_out_file);
2968 return default_assemble_integer (x, size, aligned_p);
2971 /* Output an ascii string. */
2973 output_ascii (FILE *file, const char *p, int size)
2977 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2979 /* The HP assembler can only take strings of 256 characters at one
2980 time. This is a limitation on input line length, *not* the
2981 length of the string. Sigh. Even worse, it seems that the
2982 restriction is in number of input characters (see \xnn &
2983 \whatever). So we have to do this very carefully. */
2985 fputs ("\t.STRING \"", file);
2988 for (i = 0; i < size; i += 4)
2992 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2994 register unsigned int c = (unsigned char) p[i + io];
2996 if (c == '\"' || c == '\\')
2997 partial_output[co++] = '\\';
2998 if (c >= ' ' && c < 0177)
2999 partial_output[co++] = c;
3003 partial_output[co++] = '\\';
3004 partial_output[co++] = 'x';
3005 hexd = c / 16 - 0 + '0';
3007 hexd -= '9' - 'a' + 1;
3008 partial_output[co++] = hexd;
3009 hexd = c % 16 - 0 + '0';
3011 hexd -= '9' - 'a' + 1;
3012 partial_output[co++] = hexd;
3015 if (chars_output + co > 243)
3017 fputs ("\"\n\t.STRING \"", file);
3020 fwrite (partial_output, 1, (size_t) co, file);
3024 fputs ("\"\n", file);
3027 /* Try to rewrite floating point comparisons & branches to avoid
3028 useless add,tr insns.
3030 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3031 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3032 first attempt to remove useless add,tr insns. It is zero
3033 for the second pass as reorg sometimes leaves bogus REG_DEAD
3036 When CHECK_NOTES is zero we can only eliminate add,tr insns
3037 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3040 remove_useless_addtr_insns (int check_notes)
3043 static int pass = 0;
3045 /* This is fairly cheap, so always run it when optimizing. */
3049 int fbranch_count = 0;
3051 /* Walk all the insns in this function looking for fcmp & fbranch
3052 instructions. Keep track of how many of each we find. */
3053 for (insn = get_insns (); insn; insn = next_insn (insn))
3057 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3058 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3061 tmp = PATTERN (insn);
3063 /* It must be a set. */
3064 if (GET_CODE (tmp) != SET)
3067 /* If the destination is CCFP, then we've found an fcmp insn. */
3068 tmp = SET_DEST (tmp);
3069 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3075 tmp = PATTERN (insn);
3076 /* If this is an fbranch instruction, bump the fbranch counter. */
3077 if (GET_CODE (tmp) == SET
3078 && SET_DEST (tmp) == pc_rtx
3079 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3080 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3081 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3082 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3090 /* Find all floating point compare + branch insns. If possible,
3091 reverse the comparison & the branch to avoid add,tr insns. */
3092 for (insn = get_insns (); insn; insn = next_insn (insn))
3096 /* Ignore anything that isn't an INSN. */
3097 if (GET_CODE (insn) != INSN)
3100 tmp = PATTERN (insn);
3102 /* It must be a set. */
3103 if (GET_CODE (tmp) != SET)
3106 /* The destination must be CCFP, which is register zero. */
3107 tmp = SET_DEST (tmp);
3108 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3111 /* INSN should be a set of CCFP.
3113 See if the result of this insn is used in a reversed FP
3114 conditional branch. If so, reverse our condition and
3115 the branch. Doing so avoids useless add,tr insns. */
3116 next = next_insn (insn);
3119 /* Jumps, calls and labels stop our search. */
3120 if (GET_CODE (next) == JUMP_INSN
3121 || GET_CODE (next) == CALL_INSN
3122 || GET_CODE (next) == CODE_LABEL)
3125 /* As does another fcmp insn. */
3126 if (GET_CODE (next) == INSN
3127 && GET_CODE (PATTERN (next)) == SET
3128 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3129 && REGNO (SET_DEST (PATTERN (next))) == 0)
3132 next = next_insn (next);
3135 /* Is NEXT_INSN a branch? */
3137 && GET_CODE (next) == JUMP_INSN)
3139 rtx pattern = PATTERN (next);
3141 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3142 and CCFP dies, then reverse our conditional and the branch
3143 to avoid the add,tr. */
3144 if (GET_CODE (pattern) == SET
3145 && SET_DEST (pattern) == pc_rtx
3146 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3147 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3148 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3149 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3150 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3151 && (fcmp_count == fbranch_count
3153 && find_regno_note (next, REG_DEAD, 0))))
3155 /* Reverse the branch. */
3156 tmp = XEXP (SET_SRC (pattern), 1);
3157 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3158 XEXP (SET_SRC (pattern), 2) = tmp;
3159 INSN_CODE (next) = -1;
3161 /* Reverse our condition. */
3162 tmp = PATTERN (insn);
3163 PUT_CODE (XEXP (tmp, 1),
3164 (reverse_condition_maybe_unordered
3165 (GET_CODE (XEXP (tmp, 1)))));
3175 /* You may have trouble believing this, but this is the 32 bit HP-PA
3180 Variable arguments (optional; any number may be allocated)
3182 SP-(4*(N+9)) arg word N
3187 Fixed arguments (must be allocated; may remain unused)
3196 SP-32 External Data Pointer (DP)
3198 SP-24 External/stub RP (RP')
3202 SP-8 Calling Stub RP (RP'')
3207 SP-0 Stack Pointer (points to next available address)
3211 /* This function saves registers as follows. Registers marked with ' are
3212 this function's registers (as opposed to the previous function's).
3213 If a frame_pointer isn't needed, r4 is saved as a general register;
3214 the space for the frame pointer is still allocated, though, to keep
3220 SP (FP') Previous FP
3221 SP + 4 Alignment filler (sigh)
3222 SP + 8 Space for locals reserved here.
3226 SP + n All call saved register used.
3230 SP + o All call saved fp registers used.
3234 SP + p (SP') points to next available address.
3238 /* Global variables set by output_function_prologue(). */
3239 /* Size of frame. Need to know this to emit return insns from
3241 static HOST_WIDE_INT actual_fsize, local_fsize;
3242 static int save_fregs;
3244 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3245 Handle case where DISP > 8k by using the add_high_const patterns.
3247 Note in DISP > 8k case, we will leave the high part of the address
3248 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3251 store_reg (int reg, HOST_WIDE_INT disp, int base)
3253 rtx insn, dest, src, basereg;
3255 src = gen_rtx_REG (word_mode, reg);
3256 basereg = gen_rtx_REG (Pmode, base);
3257 if (VAL_14_BITS_P (disp))
3259 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3260 insn = emit_move_insn (dest, src);
3262 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3264 rtx delta = GEN_INT (disp);
3265 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3267 emit_move_insn (tmpreg, delta);
3268 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3269 dest = gen_rtx_MEM (word_mode, tmpreg);
3270 insn = emit_move_insn (dest, src);
3274 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3275 gen_rtx_SET (VOIDmode,
3276 gen_rtx_MEM (word_mode,
3277 gen_rtx_PLUS (word_mode, basereg,
3285 rtx delta = GEN_INT (disp);
3286 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3287 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3289 emit_move_insn (tmpreg, high);
3290 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3291 insn = emit_move_insn (dest, src);
3295 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3296 gen_rtx_SET (VOIDmode,
3297 gen_rtx_MEM (word_mode,
3298 gen_rtx_PLUS (word_mode, basereg,
3306 RTX_FRAME_RELATED_P (insn) = 1;
3309 /* Emit RTL to store REG at the memory location specified by BASE and then
3310 add MOD to BASE. MOD must be <= 8k. */
3313 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3315 rtx insn, basereg, srcreg, delta;
3317 gcc_assert (VAL_14_BITS_P (mod));
3319 basereg = gen_rtx_REG (Pmode, base);
3320 srcreg = gen_rtx_REG (word_mode, reg);
3321 delta = GEN_INT (mod);
3323 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3326 RTX_FRAME_RELATED_P (insn) = 1;
3328 /* RTX_FRAME_RELATED_P must be set on each frame related set
3329 in a parallel with more than one element. */
3330 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3331 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3335 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3336 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3337 whether to add a frame note or not.
3339 In the DISP > 8k case, we leave the high part of the address in %r1.
3340 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3343 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3347 if (VAL_14_BITS_P (disp))
3349 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3350 plus_constant (gen_rtx_REG (Pmode, base), disp));
3352 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3354 rtx basereg = gen_rtx_REG (Pmode, base);
3355 rtx delta = GEN_INT (disp);
3356 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3358 emit_move_insn (tmpreg, delta);
3359 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3360 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3364 rtx basereg = gen_rtx_REG (Pmode, base);
3365 rtx delta = GEN_INT (disp);
3366 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3368 emit_move_insn (tmpreg,
3369 gen_rtx_PLUS (Pmode, basereg,
3370 gen_rtx_HIGH (Pmode, delta)));
3371 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3372 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3375 if (DO_FRAME_NOTES && note)
3376 RTX_FRAME_RELATED_P (insn) = 1;
3380 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3385 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3386 be consistent with the rounding and size calculation done here.
3387 Change them at the same time. */
3389 /* We do our own stack alignment. First, round the size of the
3390 stack locals up to a word boundary. */
3391 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3393 /* Space for previous frame pointer + filler. If any frame is
3394 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3395 waste some space here for the sake of HP compatibility. The
3396 first slot is only used when the frame pointer is needed. */
3397 if (size || frame_pointer_needed)
3398 size += STARTING_FRAME_OFFSET;
3400 /* If the current function calls __builtin_eh_return, then we need
3401 to allocate stack space for registers that will hold data for
3402 the exception handler. */
3403 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3407 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3409 size += i * UNITS_PER_WORD;
3412 /* Account for space used by the callee general register saves. */
3413 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3414 if (regs_ever_live[i])
3415 size += UNITS_PER_WORD;
3417 /* Account for space used by the callee floating point register saves. */
3418 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3419 if (regs_ever_live[i]
3420 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3424 /* We always save both halves of the FP register, so always
3425 increment the frame size by 8 bytes. */
3429 /* If any of the floating registers are saved, account for the
3430 alignment needed for the floating point register save block. */
3433 size = (size + 7) & ~7;
3438 /* The various ABIs include space for the outgoing parameters in the
3439 size of the current function's stack frame. We don't need to align
3440 for the outgoing arguments as their alignment is set by the final
3441 rounding for the frame as a whole. */
3442 size += current_function_outgoing_args_size;
3444 /* Allocate space for the fixed frame marker. This space must be
3445 allocated for any function that makes calls or allocates
3447 if (!current_function_is_leaf || size)
3448 size += TARGET_64BIT ? 48 : 32;
3450 /* Finally, round to the preferred stack boundary. */
3451 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3452 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3455 /* Generate the assembly code for function entry. FILE is a stdio
3456 stream to output the code to. SIZE is an int: how many units of
3457 temporary storage to allocate.
3459 Refer to the array `regs_ever_live' to determine which registers to
3460 save; `regs_ever_live[I]' is nonzero if register number I is ever
3461 used in the function. This function is responsible for knowing
3462 which registers should not be saved even if used. */
3464 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3465 of memory. If any fpu reg is used in the function, we allocate
3466 such a block here, at the bottom of the frame, just in case it's needed.
3468 If this function is a leaf procedure, then we may choose not
3469 to do a "save" insn. The decision about whether or not
3470 to do this is made in regclass.c. */
3473 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3475 /* The function's label and associated .PROC must never be
3476 separated and must be output *after* any profiling declarations
3477 to avoid changing spaces/subspaces within a procedure. */
3478 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3479 fputs ("\t.PROC\n", file);
3481 /* hppa_expand_prologue does the dirty work now. We just need
3482 to output the assembler directives which denote the start
3484 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3485 if (regs_ever_live[2])
3486 fputs (",CALLS,SAVE_RP", file);
3488 fputs (",NO_CALLS", file);
3490 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3491 at the beginning of the frame and that it is used as the frame
3492 pointer for the frame. We do this because our current frame
3493 layout doesn't conform to that specified in the HP runtime
3494 documentation and we need a way to indicate to programs such as
3495 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3496 isn't used by HP compilers but is supported by the assembler.
3497 However, SAVE_SP is supposed to indicate that the previous stack
3498 pointer has been saved in the frame marker. */
3499 if (frame_pointer_needed)
3500 fputs (",SAVE_SP", file);
3502 /* Pass on information about the number of callee register saves
3503 performed in the prologue.
3505 The compiler is supposed to pass the highest register number
3506 saved, the assembler then has to adjust that number before
3507 entering it into the unwind descriptor (to account for any
3508 caller saved registers with lower register numbers than the
3509 first callee saved register). */
3511 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3514 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3516 fputs ("\n\t.ENTRY\n", file);
3518 remove_useless_addtr_insns (0);
3522 hppa_expand_prologue (void)
3524 int merge_sp_adjust_with_store = 0;
3525 HOST_WIDE_INT size = get_frame_size ();
3526 HOST_WIDE_INT offset;
3534 /* Compute total size for frame pointer, filler, locals and rounding to
3535 the next word boundary. Similar code appears in compute_frame_size
3536 and must be changed in tandem with this code. */
3537 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3538 if (local_fsize || frame_pointer_needed)
3539 local_fsize += STARTING_FRAME_OFFSET;
3541 actual_fsize = compute_frame_size (size, &save_fregs);
3543 /* Compute a few things we will use often. */
3544 tmpreg = gen_rtx_REG (word_mode, 1);
3546 /* Save RP first. The calling conventions manual states RP will
3547 always be stored into the caller's frame at sp - 20 or sp - 16
3548 depending on which ABI is in use. */
3549 if (regs_ever_live[2] || current_function_calls_eh_return)
3550 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3552 /* Allocate the local frame and set up the frame pointer if needed. */
3553 if (actual_fsize != 0)
3555 if (frame_pointer_needed)
3557 /* Copy the old frame pointer temporarily into %r1. Set up the
3558 new stack pointer, then store away the saved old frame pointer
3559 into the stack at sp and at the same time update the stack
3560 pointer by actual_fsize bytes. Two versions, first
3561 handles small (<8k) frames. The second handles large (>=8k)
3563 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3565 RTX_FRAME_RELATED_P (insn) = 1;
3567 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3569 RTX_FRAME_RELATED_P (insn) = 1;
3571 if (VAL_14_BITS_P (actual_fsize))
3572 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3575 /* It is incorrect to store the saved frame pointer at *sp,
3576 then increment sp (writes beyond the current stack boundary).
3578 So instead use stwm to store at *sp and post-increment the
3579 stack pointer as an atomic operation. Then increment sp to
3580 finish allocating the new frame. */
3581 HOST_WIDE_INT adjust1 = 8192 - 64;
3582 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3584 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3585 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3589 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3590 we need to store the previous stack pointer (frame pointer)
3591 into the frame marker on targets that use the HP unwind
3592 library. This allows the HP unwind library to be used to
3593 unwind GCC frames. However, we are not fully compatible
3594 with the HP library because our frame layout differs from
3595 that specified in the HP runtime specification.
3597 We don't want a frame note on this instruction as the frame
3598 marker moves during dynamic stack allocation.
3600 This instruction also serves as a blockage to prevent
3601 register spills from being scheduled before the stack
3602 pointer is raised. This is necessary as we store
3603 registers using the frame pointer as a base register,
3604 and the frame pointer is set before sp is raised. */
3605 if (TARGET_HPUX_UNWIND_LIBRARY)
3607 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3608 GEN_INT (TARGET_64BIT ? -8 : -4));
3610 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3614 emit_insn (gen_blockage ());
3616 /* no frame pointer needed. */
3619 /* In some cases we can perform the first callee register save
3620 and allocating the stack frame at the same time. If so, just
3621 make a note of it and defer allocating the frame until saving
3622 the callee registers. */
3623 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3624 merge_sp_adjust_with_store = 1;
3625 /* Can not optimize. Adjust the stack frame by actual_fsize
3628 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3633 /* Normal register save.
3635 Do not save the frame pointer in the frame_pointer_needed case. It
3636 was done earlier. */
3637 if (frame_pointer_needed)
3639 offset = local_fsize;
3641 /* Saving the EH return data registers in the frame is the simplest
3642 way to get the frame unwind information emitted. We put them
3643 just before the general registers. */
3644 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3646 unsigned int i, regno;
3650 regno = EH_RETURN_DATA_REGNO (i);
3651 if (regno == INVALID_REGNUM)
3654 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3655 offset += UNITS_PER_WORD;
3659 for (i = 18; i >= 4; i--)
3660 if (regs_ever_live[i] && ! call_used_regs[i])
3662 store_reg (i, offset, FRAME_POINTER_REGNUM);
3663 offset += UNITS_PER_WORD;
3666 /* Account for %r3 which is saved in a special place. */
3669 /* No frame pointer needed. */
3672 offset = local_fsize - actual_fsize;
3674 /* Saving the EH return data registers in the frame is the simplest
3675 way to get the frame unwind information emitted. */
3676 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3678 unsigned int i, regno;
3682 regno = EH_RETURN_DATA_REGNO (i);
3683 if (regno == INVALID_REGNUM)
3686 /* If merge_sp_adjust_with_store is nonzero, then we can
3687 optimize the first save. */
3688 if (merge_sp_adjust_with_store)
3690 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3691 merge_sp_adjust_with_store = 0;
3694 store_reg (regno, offset, STACK_POINTER_REGNUM);
3695 offset += UNITS_PER_WORD;
3699 for (i = 18; i >= 3; i--)
3700 if (regs_ever_live[i] && ! call_used_regs[i])
3702 /* If merge_sp_adjust_with_store is nonzero, then we can
3703 optimize the first GR save. */
3704 if (merge_sp_adjust_with_store)
3706 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3707 merge_sp_adjust_with_store = 0;
3710 store_reg (i, offset, STACK_POINTER_REGNUM);
3711 offset += UNITS_PER_WORD;
3715 /* If we wanted to merge the SP adjustment with a GR save, but we never
3716 did any GR saves, then just emit the adjustment here. */
3717 if (merge_sp_adjust_with_store)
3718 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3722 /* The hppa calling conventions say that %r19, the pic offset
3723 register, is saved at sp - 32 (in this function's frame)
3724 when generating PIC code. FIXME: What is the correct thing
3725 to do for functions which make no calls and allocate no
3726 frame? Do we need to allocate a frame, or can we just omit
3727 the save? For now we'll just omit the save.
3729 We don't want a note on this insn as the frame marker can
3730 move if there is a dynamic stack allocation. */
3731 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3733 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3735 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3739 /* Align pointer properly (doubleword boundary). */
3740 offset = (offset + 7) & ~7;
3742 /* Floating point register store. */
3747 /* First get the frame or stack pointer to the start of the FP register
3749 if (frame_pointer_needed)
3751 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3752 base = frame_pointer_rtx;
3756 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3757 base = stack_pointer_rtx;
3760 /* Now actually save the FP registers. */
3761 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3763 if (regs_ever_live[i]
3764 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3766 rtx addr, insn, reg;
3767 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3768 reg = gen_rtx_REG (DFmode, i);
3769 insn = emit_move_insn (addr, reg);
3772 RTX_FRAME_RELATED_P (insn) = 1;
3775 rtx mem = gen_rtx_MEM (DFmode,
3776 plus_constant (base, offset));
3778 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3779 gen_rtx_SET (VOIDmode, mem, reg),
3784 rtx meml = gen_rtx_MEM (SFmode,
3785 plus_constant (base, offset));
3786 rtx memr = gen_rtx_MEM (SFmode,
3787 plus_constant (base, offset + 4));
3788 rtx regl = gen_rtx_REG (SFmode, i);
3789 rtx regr = gen_rtx_REG (SFmode, i + 1);
3790 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3791 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3794 RTX_FRAME_RELATED_P (setl) = 1;
3795 RTX_FRAME_RELATED_P (setr) = 1;
3796 vec = gen_rtvec (2, setl, setr);
3798 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3799 gen_rtx_SEQUENCE (VOIDmode, vec),
3803 offset += GET_MODE_SIZE (DFmode);
3810 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3811 Handle case where DISP > 8k by using the add_high_const patterns. */
3814 load_reg (int reg, HOST_WIDE_INT disp, int base)
3816 rtx dest = gen_rtx_REG (word_mode, reg);
3817 rtx basereg = gen_rtx_REG (Pmode, base);
3820 if (VAL_14_BITS_P (disp))
3821 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3822 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3824 rtx delta = GEN_INT (disp);
3825 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3827 emit_move_insn (tmpreg, delta);
3828 if (TARGET_DISABLE_INDEXING)
3830 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3831 src = gen_rtx_MEM (word_mode, tmpreg);
3834 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3838 rtx delta = GEN_INT (disp);
3839 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3840 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3842 emit_move_insn (tmpreg, high);
3843 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3846 emit_move_insn (dest, src);
3849 /* Update the total code bytes output to the text section. */
3852 update_total_code_bytes (int nbytes)
3854 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3855 && !IN_NAMED_SECTION_P (cfun->decl))
3857 if (INSN_ADDRESSES_SET_P ())
3859 unsigned long old_total = total_code_bytes;
3861 total_code_bytes += nbytes;
3863 /* Be prepared to handle overflows. */
3864 if (old_total > total_code_bytes)
3865 total_code_bytes = -1;
3868 total_code_bytes = -1;
3872 /* This function generates the assembly code for function exit.
3873 Args are as for output_function_prologue ().
3875 The function epilogue should not depend on the current stack
3876 pointer! It should use the frame pointer only. This is mandatory
3877 because of alloca; we also take advantage of it to omit stack
3878 adjustments before returning. */
3881 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3883 rtx insn = get_last_insn ();
3887 /* hppa_expand_epilogue does the dirty work now. We just need
3888 to output the assembler directives which denote the end
3891 To make debuggers happy, emit a nop if the epilogue was completely
3892 eliminated due to a volatile call as the last insn in the
3893 current function. That way the return address (in %r2) will
3894 always point to a valid instruction in the current function. */
3896 /* Get the last real insn. */
3897 if (GET_CODE (insn) == NOTE)
3898 insn = prev_real_insn (insn);
3900 /* If it is a sequence, then look inside. */
3901 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3902 insn = XVECEXP (PATTERN (insn), 0, 0);
3904 /* If insn is a CALL_INSN, then it must be a call to a volatile
3905 function (otherwise there would be epilogue insns). */
3906 if (insn && GET_CODE (insn) == CALL_INSN)
3908 fputs ("\tnop\n", file);
3912 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3914 if (TARGET_SOM && TARGET_GAS)
3916 /* We done with this subspace except possibly for some additional
3917 debug information. Forget that we are in this subspace to ensure
3918 that the next function is output in its own subspace. */
3922 if (INSN_ADDRESSES_SET_P ())
3924 insn = get_last_nonnote_insn ();
3925 last_address += INSN_ADDRESSES (INSN_UID (insn));
3927 last_address += insn_default_length (insn);
3928 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
3929 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
3932 /* Finally, update the total number of code bytes output so far. */
3933 update_total_code_bytes (last_address);
3937 hppa_expand_epilogue (void)
3940 HOST_WIDE_INT offset;
3941 HOST_WIDE_INT ret_off = 0;
3943 int merge_sp_adjust_with_load = 0;
3945 /* We will use this often. */
3946 tmpreg = gen_rtx_REG (word_mode, 1);
3948 /* Try to restore RP early to avoid load/use interlocks when
3949 RP gets used in the return (bv) instruction. This appears to still
3950 be necessary even when we schedule the prologue and epilogue. */
3951 if (regs_ever_live [2] || current_function_calls_eh_return)
3953 ret_off = TARGET_64BIT ? -16 : -20;
3954 if (frame_pointer_needed)
3956 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3961 /* No frame pointer, and stack is smaller than 8k. */
3962 if (VAL_14_BITS_P (ret_off - actual_fsize))
3964 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3970 /* General register restores. */
3971 if (frame_pointer_needed)
3973 offset = local_fsize;
3975 /* If the current function calls __builtin_eh_return, then we need
3976 to restore the saved EH data registers. */
3977 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3979 unsigned int i, regno;
3983 regno = EH_RETURN_DATA_REGNO (i);
3984 if (regno == INVALID_REGNUM)
3987 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3988 offset += UNITS_PER_WORD;
3992 for (i = 18; i >= 4; i--)
3993 if (regs_ever_live[i] && ! call_used_regs[i])
3995 load_reg (i, offset, FRAME_POINTER_REGNUM);
3996 offset += UNITS_PER_WORD;
4001 offset = local_fsize - actual_fsize;
4003 /* If the current function calls __builtin_eh_return, then we need
4004 to restore the saved EH data registers. */
4005 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4007 unsigned int i, regno;
4011 regno = EH_RETURN_DATA_REGNO (i);
4012 if (regno == INVALID_REGNUM)
4015 /* Only for the first load.
4016 merge_sp_adjust_with_load holds the register load
4017 with which we will merge the sp adjustment. */
4018 if (merge_sp_adjust_with_load == 0
4020 && VAL_14_BITS_P (-actual_fsize))
4021 merge_sp_adjust_with_load = regno;
4023 load_reg (regno, offset, STACK_POINTER_REGNUM);
4024 offset += UNITS_PER_WORD;
4028 for (i = 18; i >= 3; i--)
4030 if (regs_ever_live[i] && ! call_used_regs[i])
4032 /* Only for the first load.
4033 merge_sp_adjust_with_load holds the register load
4034 with which we will merge the sp adjustment. */
4035 if (merge_sp_adjust_with_load == 0
4037 && VAL_14_BITS_P (-actual_fsize))
4038 merge_sp_adjust_with_load = i;
4040 load_reg (i, offset, STACK_POINTER_REGNUM);
4041 offset += UNITS_PER_WORD;
4046 /* Align pointer properly (doubleword boundary). */
4047 offset = (offset + 7) & ~7;
4049 /* FP register restores. */
4052 /* Adjust the register to index off of. */
4053 if (frame_pointer_needed)
4054 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4056 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4058 /* Actually do the restores now. */
4059 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4060 if (regs_ever_live[i]
4061 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4063 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4064 rtx dest = gen_rtx_REG (DFmode, i);
4065 emit_move_insn (dest, src);
4069 /* Emit a blockage insn here to keep these insns from being moved to
4070 an earlier spot in the epilogue, or into the main instruction stream.
4072 This is necessary as we must not cut the stack back before all the
4073 restores are finished. */
4074 emit_insn (gen_blockage ());
4076 /* Reset stack pointer (and possibly frame pointer). The stack
4077 pointer is initially set to fp + 64 to avoid a race condition. */
4078 if (frame_pointer_needed)
4080 rtx delta = GEN_INT (-64);
4082 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4083 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4085 /* If we were deferring a callee register restore, do it now. */
4086 else if (merge_sp_adjust_with_load)
4088 rtx delta = GEN_INT (-actual_fsize);
4089 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4091 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4093 else if (actual_fsize != 0)
4094 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4097 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4098 frame greater than 8k), do so now. */
4100 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4102 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4104 rtx sa = EH_RETURN_STACKADJ_RTX;
4106 emit_insn (gen_blockage ());
4107 emit_insn (TARGET_64BIT
4108 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4109 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4114 hppa_pic_save_rtx (void)
4116 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4119 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4120 #define NO_DEFERRED_PROFILE_COUNTERS 0
4123 /* Define heap vector type for funcdef numbers. */
4125 DEF_VEC_ALLOC_I(int,heap);
4127 /* Vector of funcdef numbers. */
4128 static VEC(int,heap) *funcdef_nos;
4130 /* Output deferred profile counters. */
4132 output_deferred_profile_counters (void)
4137 if (VEC_empty (int, funcdef_nos))
4141 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4142 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4144 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4146 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4147 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4150 VEC_free (int, heap, funcdef_nos);
4154 hppa_profile_hook (int label_no)
4156 /* We use SImode for the address of the function in both 32 and
4157 64-bit code to avoid having to provide DImode versions of the
4158 lcla2 and load_offset_label_address insn patterns. */
4159 rtx reg = gen_reg_rtx (SImode);
4160 rtx label_rtx = gen_label_rtx ();
4161 rtx begin_label_rtx, call_insn;
4162 char begin_label_name[16];
4164 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4166 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4169 emit_move_insn (arg_pointer_rtx,
4170 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4173 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4175 /* The address of the function is loaded into %r25 with a instruction-
4176 relative sequence that avoids the use of relocations. The sequence
4177 is split so that the load_offset_label_address instruction can
4178 occupy the delay slot of the call to _mcount. */
4180 emit_insn (gen_lcla2 (reg, label_rtx));
4182 emit_insn (gen_lcla1 (reg, label_rtx));
4184 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4185 reg, begin_label_rtx, label_rtx));
4187 #if !NO_DEFERRED_PROFILE_COUNTERS
4189 rtx count_label_rtx, addr, r24;
4190 char count_label_name[16];
4192 VEC_safe_push (int, heap, funcdef_nos, label_no);
4193 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4194 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4196 addr = force_reg (Pmode, count_label_rtx);
4197 r24 = gen_rtx_REG (Pmode, 24);
4198 emit_move_insn (r24, addr);
4201 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4202 gen_rtx_SYMBOL_REF (Pmode,
4204 GEN_INT (TARGET_64BIT ? 24 : 12)));
4206 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4211 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4212 gen_rtx_SYMBOL_REF (Pmode,
4214 GEN_INT (TARGET_64BIT ? 16 : 8)));
4218 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4219 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4221 /* Indicate the _mcount call cannot throw, nor will it execute a
4223 REG_NOTES (call_insn)
4224 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4227 /* Fetch the return address for the frame COUNT steps up from
4228 the current frame, after the prologue. FRAMEADDR is the
4229 frame pointer of the COUNT frame.
4231 We want to ignore any export stub remnants here. To handle this,
4232 we examine the code at the return address, and if it is an export
4233 stub, we return a memory rtx for the stub return address stored
4236 The value returned is used in two different ways:
4238 1. To find a function's caller.
4240 2. To change the return address for a function.
4242 This function handles most instances of case 1; however, it will
4243 fail if there are two levels of stubs to execute on the return
4244 path. The only way I believe that can happen is if the return value
4245 needs a parameter relocation, which never happens for C code.
4247 This function handles most instances of case 2; however, it will
4248 fail if we did not originally have stub code on the return path
4249 but will need stub code on the new return path. This can happen if
4250 the caller & callee are both in the main program, but the new
4251 return location is in a shared library. */
4254 return_addr_rtx (int count, rtx frameaddr)
4264 rp = get_hard_reg_initial_val (Pmode, 2);
4266 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4269 saved_rp = gen_reg_rtx (Pmode);
4270 emit_move_insn (saved_rp, rp);
4272 /* Get pointer to the instruction stream. We have to mask out the
4273 privilege level from the two low order bits of the return address
4274 pointer here so that ins will point to the start of the first
4275 instruction that would have been executed if we returned. */
4276 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4277 label = gen_label_rtx ();
4279 /* Check the instruction stream at the normal return address for the
4282 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4283 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4284 0x00011820 | stub+16: mtsp r1,sr0
4285 0xe0400002 | stub+20: be,n 0(sr0,rp)
4287 If it is an export stub, than our return address is really in
4290 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4291 NULL_RTX, SImode, 1);
4292 emit_jump_insn (gen_bne (label));
4294 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4295 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4296 emit_jump_insn (gen_bne (label));
4298 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4299 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4300 emit_jump_insn (gen_bne (label));
4302 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4303 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4305 /* If there is no export stub then just use the value saved from
4306 the return pointer register. */
4308 emit_jump_insn (gen_bne (label));
4310 /* Here we know that our return address points to an export
4311 stub. We don't want to return the address of the export stub,
4312 but rather the return address of the export stub. That return
4313 address is stored at -24[frameaddr]. */
4315 emit_move_insn (saved_rp,
4317 memory_address (Pmode,
4318 plus_constant (frameaddr,
4325 /* This is only valid once reload has completed because it depends on
4326 knowing exactly how much (if any) frame there is and...
4328 It's only valid if there is no frame marker to de-allocate and...
4330 It's only valid if %r2 hasn't been saved into the caller's frame
4331 (we're not profiling and %r2 isn't live anywhere). */
4333 hppa_can_use_return_insn_p (void)
4335 return (reload_completed
4336 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4337 && ! regs_ever_live[2]
4338 && ! frame_pointer_needed);
4342 emit_bcond_fp (enum rtx_code code, rtx operand0)
4344 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4345 gen_rtx_IF_THEN_ELSE (VOIDmode,
4346 gen_rtx_fmt_ee (code,
4348 gen_rtx_REG (CCFPmode, 0),
4350 gen_rtx_LABEL_REF (VOIDmode, operand0),
4356 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4358 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4359 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4362 /* Adjust the cost of a scheduling dependency. Return the new cost of
4363 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4366 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4368 enum attr_type attr_type;
4370 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4371 true dependencies as they are described with bypasses now. */
4372 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4375 if (! recog_memoized (insn))
4378 attr_type = get_attr_type (insn);
4380 switch (REG_NOTE_KIND (link))
4383 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4386 if (attr_type == TYPE_FPLOAD)
4388 rtx pat = PATTERN (insn);
4389 rtx dep_pat = PATTERN (dep_insn);
4390 if (GET_CODE (pat) == PARALLEL)
4392 /* This happens for the fldXs,mb patterns. */
4393 pat = XVECEXP (pat, 0, 0);
4395 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4396 /* If this happens, we have to extend this to schedule
4397 optimally. Return 0 for now. */
4400 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4402 if (! recog_memoized (dep_insn))
4404 switch (get_attr_type (dep_insn))
4411 case TYPE_FPSQRTSGL:
4412 case TYPE_FPSQRTDBL:
4413 /* A fpload can't be issued until one cycle before a
4414 preceding arithmetic operation has finished if
4415 the target of the fpload is any of the sources
4416 (or destination) of the arithmetic operation. */
4417 return insn_default_latency (dep_insn) - 1;
4424 else if (attr_type == TYPE_FPALU)
4426 rtx pat = PATTERN (insn);
4427 rtx dep_pat = PATTERN (dep_insn);
4428 if (GET_CODE (pat) == PARALLEL)
4430 /* This happens for the fldXs,mb patterns. */
4431 pat = XVECEXP (pat, 0, 0);
4433 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4434 /* If this happens, we have to extend this to schedule
4435 optimally. Return 0 for now. */
4438 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4440 if (! recog_memoized (dep_insn))
4442 switch (get_attr_type (dep_insn))
4446 case TYPE_FPSQRTSGL:
4447 case TYPE_FPSQRTDBL:
4448 /* An ALU flop can't be issued until two cycles before a
4449 preceding divide or sqrt operation has finished if
4450 the target of the ALU flop is any of the sources
4451 (or destination) of the divide or sqrt operation. */
4452 return insn_default_latency (dep_insn) - 2;
4460 /* For other anti dependencies, the cost is 0. */
4463 case REG_DEP_OUTPUT:
4464 /* Output dependency; DEP_INSN writes a register that INSN writes some
4466 if (attr_type == TYPE_FPLOAD)
4468 rtx pat = PATTERN (insn);
4469 rtx dep_pat = PATTERN (dep_insn);
4470 if (GET_CODE (pat) == PARALLEL)
4472 /* This happens for the fldXs,mb patterns. */
4473 pat = XVECEXP (pat, 0, 0);
4475 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4476 /* If this happens, we have to extend this to schedule
4477 optimally. Return 0 for now. */
4480 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4482 if (! recog_memoized (dep_insn))
4484 switch (get_attr_type (dep_insn))
4491 case TYPE_FPSQRTSGL:
4492 case TYPE_FPSQRTDBL:
4493 /* A fpload can't be issued until one cycle before a
4494 preceding arithmetic operation has finished if
4495 the target of the fpload is the destination of the
4496 arithmetic operation.
4498 Exception: For PA7100LC, PA7200 and PA7300, the cost
4499 is 3 cycles, unless they bundle together. We also
4500 pay the penalty if the second insn is a fpload. */
4501 return insn_default_latency (dep_insn) - 1;
4508 else if (attr_type == TYPE_FPALU)
4510 rtx pat = PATTERN (insn);
4511 rtx dep_pat = PATTERN (dep_insn);
4512 if (GET_CODE (pat) == PARALLEL)
4514 /* This happens for the fldXs,mb patterns. */
4515 pat = XVECEXP (pat, 0, 0);
4517 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4518 /* If this happens, we have to extend this to schedule
4519 optimally. Return 0 for now. */
4522 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4524 if (! recog_memoized (dep_insn))
4526 switch (get_attr_type (dep_insn))
4530 case TYPE_FPSQRTSGL:
4531 case TYPE_FPSQRTDBL:
4532 /* An ALU flop can't be issued until two cycles before a
4533 preceding divide or sqrt operation has finished if
4534 the target of the ALU flop is also the target of
4535 the divide or sqrt operation. */
4536 return insn_default_latency (dep_insn) - 2;
4544 /* For other output dependencies, the cost is 0. */
4552 /* Adjust scheduling priorities. We use this to try and keep addil
4553 and the next use of %r1 close together. */
4555 pa_adjust_priority (rtx insn, int priority)
4557 rtx set = single_set (insn);
4561 src = SET_SRC (set);
4562 dest = SET_DEST (set);
4563 if (GET_CODE (src) == LO_SUM
4564 && symbolic_operand (XEXP (src, 1), VOIDmode)
4565 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4568 else if (GET_CODE (src) == MEM
4569 && GET_CODE (XEXP (src, 0)) == LO_SUM
4570 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4571 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4574 else if (GET_CODE (dest) == MEM
4575 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4576 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4577 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4583 /* The 700 can only issue a single insn at a time.
4584 The 7XXX processors can issue two insns at a time.
4585 The 8000 can issue 4 insns at a time. */
4587 pa_issue_rate (void)
4591 case PROCESSOR_700: return 1;
4592 case PROCESSOR_7100: return 2;
4593 case PROCESSOR_7100LC: return 2;
4594 case PROCESSOR_7200: return 2;
4595 case PROCESSOR_7300: return 2;
4596 case PROCESSOR_8000: return 4;
4605 /* Return any length adjustment needed by INSN which already has its length
4606 computed as LENGTH. Return zero if no adjustment is necessary.
4608 For the PA: function calls, millicode calls, and backwards short
4609 conditional branches with unfilled delay slots need an adjustment by +1
4610 (to account for the NOP which will be inserted into the instruction stream).
4612 Also compute the length of an inline block move here as it is too
4613 complicated to express as a length attribute in pa.md. */
4615 pa_adjust_insn_length (rtx insn, int length)
4617 rtx pat = PATTERN (insn);
4619 /* Jumps inside switch tables which have unfilled delay slots need
4621 if (GET_CODE (insn) == JUMP_INSN
4622 && GET_CODE (pat) == PARALLEL
4623 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4625 /* Millicode insn with an unfilled delay slot. */
4626 else if (GET_CODE (insn) == INSN
4627 && GET_CODE (pat) != SEQUENCE
4628 && GET_CODE (pat) != USE
4629 && GET_CODE (pat) != CLOBBER
4630 && get_attr_type (insn) == TYPE_MILLI)
4632 /* Block move pattern. */
4633 else if (GET_CODE (insn) == INSN
4634 && GET_CODE (pat) == PARALLEL
4635 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4636 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4637 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4638 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4639 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4640 return compute_movmem_length (insn) - 4;
4641 /* Block clear pattern. */
4642 else if (GET_CODE (insn) == INSN
4643 && GET_CODE (pat) == PARALLEL
4644 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4645 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4646 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4647 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4648 return compute_clrmem_length (insn) - 4;
4649 /* Conditional branch with an unfilled delay slot. */
4650 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4652 /* Adjust a short backwards conditional with an unfilled delay slot. */
4653 if (GET_CODE (pat) == SET
4655 && ! forward_branch_p (insn))
4657 else if (GET_CODE (pat) == PARALLEL
4658 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4661 /* Adjust dbra insn with short backwards conditional branch with
4662 unfilled delay slot -- only for case where counter is in a
4663 general register register. */
4664 else if (GET_CODE (pat) == PARALLEL
4665 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4666 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4667 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4669 && ! forward_branch_p (insn))
4677 /* Print operand X (an rtx) in assembler syntax to file FILE.
4678 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4679 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4682 print_operand (FILE *file, rtx x, int code)
4687 /* Output a 'nop' if there's nothing for the delay slot. */
4688 if (dbr_sequence_length () == 0)
4689 fputs ("\n\tnop", file);
4692 /* Output a nullification completer if there's nothing for the */
4693 /* delay slot or nullification is requested. */
4694 if (dbr_sequence_length () == 0 ||
4696 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4700 /* Print out the second register name of a register pair.
4701 I.e., R (6) => 7. */
4702 fputs (reg_names[REGNO (x) + 1], file);
4705 /* A register or zero. */
4707 || (x == CONST0_RTX (DFmode))
4708 || (x == CONST0_RTX (SFmode)))
4710 fputs ("%r0", file);
4716 /* A register or zero (floating point). */
4718 || (x == CONST0_RTX (DFmode))
4719 || (x == CONST0_RTX (SFmode)))
4721 fputs ("%fr0", file);
4730 xoperands[0] = XEXP (XEXP (x, 0), 0);
4731 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4732 output_global_address (file, xoperands[1], 0);
4733 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4737 case 'C': /* Plain (C)ondition */
4739 switch (GET_CODE (x))
4742 fputs ("=", file); break;
4744 fputs ("<>", file); break;
4746 fputs (">", file); break;
4748 fputs (">=", file); break;
4750 fputs (">>=", file); break;
4752 fputs (">>", file); break;
4754 fputs ("<", file); break;
4756 fputs ("<=", file); break;
4758 fputs ("<<=", file); break;
4760 fputs ("<<", file); break;
4765 case 'N': /* Condition, (N)egated */
4766 switch (GET_CODE (x))
4769 fputs ("<>", file); break;
4771 fputs ("=", file); break;
4773 fputs ("<=", file); break;
4775 fputs ("<", file); break;
4777 fputs ("<<", file); break;
4779 fputs ("<<=", file); break;
4781 fputs (">=", file); break;
4783 fputs (">", file); break;
4785 fputs (">>", file); break;
4787 fputs (">>=", file); break;
4792 /* For floating point comparisons. Note that the output
4793 predicates are the complement of the desired mode. The
4794 conditions for GT, GE, LT, LE and LTGT cause an invalid
4795 operation exception if the result is unordered and this
4796 exception is enabled in the floating-point status register. */
4798 switch (GET_CODE (x))
4801 fputs ("!=", file); break;
4803 fputs ("=", file); break;
4805 fputs ("!>", file); break;
4807 fputs ("!>=", file); break;
4809 fputs ("!<", file); break;
4811 fputs ("!<=", file); break;
4813 fputs ("!<>", file); break;
4815 fputs ("!?<=", file); break;
4817 fputs ("!?<", file); break;
4819 fputs ("!?>=", file); break;
4821 fputs ("!?>", file); break;
4823 fputs ("!?=", file); break;
4825 fputs ("!?", file); break;
4827 fputs ("?", file); break;
4832 case 'S': /* Condition, operands are (S)wapped. */
4833 switch (GET_CODE (x))
4836 fputs ("=", file); break;
4838 fputs ("<>", file); break;
4840 fputs ("<", file); break;
4842 fputs ("<=", file); break;
4844 fputs ("<<=", file); break;
4846 fputs ("<<", file); break;
4848 fputs (">", file); break;
4850 fputs (">=", file); break;
4852 fputs (">>=", file); break;
4854 fputs (">>", file); break;
4859 case 'B': /* Condition, (B)oth swapped and negate. */
4860 switch (GET_CODE (x))
4863 fputs ("<>", file); break;
4865 fputs ("=", file); break;
4867 fputs (">=", file); break;
4869 fputs (">", file); break;
4871 fputs (">>", file); break;
4873 fputs (">>=", file); break;
4875 fputs ("<=", file); break;
4877 fputs ("<", file); break;
4879 fputs ("<<", file); break;
4881 fputs ("<<=", file); break;
4887 gcc_assert (GET_CODE (x) == CONST_INT);
4888 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4891 gcc_assert (GET_CODE (x) == CONST_INT);
4892 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4895 gcc_assert (GET_CODE (x) == CONST_INT);
4896 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4899 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
4900 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4903 gcc_assert (GET_CODE (x) == CONST_INT);
4904 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4907 gcc_assert (GET_CODE (x) == CONST_INT);
4908 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4911 if (GET_CODE (x) == CONST_INT)
4916 switch (GET_CODE (XEXP (x, 0)))
4920 if (ASSEMBLER_DIALECT == 0)
4921 fputs ("s,mb", file);
4923 fputs (",mb", file);
4927 if (ASSEMBLER_DIALECT == 0)
4928 fputs ("s,ma", file);
4930 fputs (",ma", file);
4933 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4934 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4936 if (ASSEMBLER_DIALECT == 0)
4939 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4940 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4942 if (ASSEMBLER_DIALECT == 0)
4943 fputs ("x,s", file);
4947 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4951 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4957 output_global_address (file, x, 0);
4960 output_global_address (file, x, 1);
4962 case 0: /* Don't do anything special */
4967 compute_zdepwi_operands (INTVAL (x), op);
4968 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4974 compute_zdepdi_operands (INTVAL (x), op);
4975 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4979 /* We can get here from a .vtable_inherit due to our
4980 CONSTANT_ADDRESS_P rejecting perfectly good constant
4986 if (GET_CODE (x) == REG)
4988 fputs (reg_names [REGNO (x)], file);
4989 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4995 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4996 && (REGNO (x) & 1) == 0)
4999 else if (GET_CODE (x) == MEM)
5001 int size = GET_MODE_SIZE (GET_MODE (x));
5002 rtx base = NULL_RTX;
5003 switch (GET_CODE (XEXP (x, 0)))
5007 base = XEXP (XEXP (x, 0), 0);
5008 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5012 base = XEXP (XEXP (x, 0), 0);
5013 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5016 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5017 fprintf (file, "%s(%s)",
5018 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5019 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5020 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5021 fprintf (file, "%s(%s)",
5022 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5023 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5024 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5025 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5027 /* Because the REG_POINTER flag can get lost during reload,
5028 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5029 index and base registers in the combined move patterns. */
5030 rtx base = XEXP (XEXP (x, 0), 1);
5031 rtx index = XEXP (XEXP (x, 0), 0);
5033 fprintf (file, "%s(%s)",
5034 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5037 output_address (XEXP (x, 0));
5040 output_address (XEXP (x, 0));
5045 output_addr_const (file, x);
5048 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5051 output_global_address (FILE *file, rtx x, int round_constant)
5054 /* Imagine (high (const (plus ...))). */
5055 if (GET_CODE (x) == HIGH)
5058 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5059 output_addr_const (file, x);
5060 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5062 output_addr_const (file, x);
5063 fputs ("-$global$", file);
5065 else if (GET_CODE (x) == CONST)
5067 const char *sep = "";
5068 int offset = 0; /* assembler wants -$global$ at end */
5069 rtx base = NULL_RTX;
5071 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5074 base = XEXP (XEXP (x, 0), 0);
5075 output_addr_const (file, base);
5078 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5084 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5087 base = XEXP (XEXP (x, 0), 1);
5088 output_addr_const (file, base);
5091 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5097 /* How bogus. The compiler is apparently responsible for
5098 rounding the constant if it uses an LR field selector.
5100 The linker and/or assembler seem a better place since
5101 they have to do this kind of thing already.
5103 If we fail to do this, HP's optimizing linker may eliminate
5104 an addil, but not update the ldw/stw/ldo instruction that
5105 uses the result of the addil. */
5107 offset = ((offset + 0x1000) & ~0x1fff);
5109 switch (GET_CODE (XEXP (x, 0)))
5122 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5130 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5131 fputs ("-$global$", file);
5133 fprintf (file, "%s%d", sep, offset);
5136 output_addr_const (file, x);
5139 /* Output boilerplate text to appear at the beginning of the file.
5140 There are several possible versions. */
5141 #define aputs(x) fputs(x, asm_out_file)
5143 pa_file_start_level (void)
5146 aputs ("\t.LEVEL 2.0w\n");
5147 else if (TARGET_PA_20)
5148 aputs ("\t.LEVEL 2.0\n");
5149 else if (TARGET_PA_11)
5150 aputs ("\t.LEVEL 1.1\n");
5152 aputs ("\t.LEVEL 1.0\n");
5156 pa_file_start_space (int sortspace)
5158 aputs ("\t.SPACE $PRIVATE$");
5161 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5162 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5163 "\n\t.SPACE $TEXT$");
5166 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5167 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5171 pa_file_start_file (int want_version)
5173 if (write_symbols != NO_DEBUG)
5175 output_file_directive (asm_out_file, main_input_filename);
5177 aputs ("\t.version\t\"01.01\"\n");
5182 pa_file_start_mcount (const char *aswhat)
5185 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5189 pa_elf_file_start (void)
5191 pa_file_start_level ();
5192 pa_file_start_mcount ("ENTRY");
5193 pa_file_start_file (0);
5197 pa_som_file_start (void)
5199 pa_file_start_level ();
5200 pa_file_start_space (0);
5201 aputs ("\t.IMPORT $global$,DATA\n"
5202 "\t.IMPORT $$dyncall,MILLICODE\n");
5203 pa_file_start_mcount ("CODE");
5204 pa_file_start_file (0);
5208 pa_linux_file_start (void)
5210 pa_file_start_file (1);
5211 pa_file_start_level ();
5212 pa_file_start_mcount ("CODE");
5216 pa_hpux64_gas_file_start (void)
5218 pa_file_start_level ();
5219 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5221 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5223 pa_file_start_file (1);
5227 pa_hpux64_hpas_file_start (void)
5229 pa_file_start_level ();
5230 pa_file_start_space (1);
5231 pa_file_start_mcount ("CODE");
5232 pa_file_start_file (0);
5236 /* Search the deferred plabel list for SYMBOL and return its internal
5237 label. If an entry for SYMBOL is not found, a new entry is created. */
5240 get_deferred_plabel (rtx symbol)
5242 const char *fname = XSTR (symbol, 0);
5245 /* See if we have already put this function on the list of deferred
5246 plabels. This list is generally small, so a liner search is not
5247 too ugly. If it proves too slow replace it with something faster. */
5248 for (i = 0; i < n_deferred_plabels; i++)
5249 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5252 /* If the deferred plabel list is empty, or this entry was not found
5253 on the list, create a new entry on the list. */
5254 if (deferred_plabels == NULL || i == n_deferred_plabels)
5258 if (deferred_plabels == 0)
5259 deferred_plabels = (struct deferred_plabel *)
5260 ggc_alloc (sizeof (struct deferred_plabel));
5262 deferred_plabels = (struct deferred_plabel *)
5263 ggc_realloc (deferred_plabels,
5264 ((n_deferred_plabels + 1)
5265 * sizeof (struct deferred_plabel)));
5267 i = n_deferred_plabels++;
5268 deferred_plabels[i].internal_label = gen_label_rtx ();
5269 deferred_plabels[i].symbol = symbol;
5271 /* Gross. We have just implicitly taken the address of this
5272 function. Mark it in the same manner as assemble_name. */
5273 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5275 mark_referenced (id);
5278 return deferred_plabels[i].internal_label;
5282 output_deferred_plabels (void)
5285 /* If we have deferred plabels, then we need to switch into the data
5286 section and align it to a 4 byte boundary before we output the
5287 deferred plabels. */
5288 if (n_deferred_plabels)
5291 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5294 /* Now output the deferred plabels. */
5295 for (i = 0; i < n_deferred_plabels; i++)
5297 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5298 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5299 assemble_integer (deferred_plabels[i].symbol,
5300 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5304 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5305 /* Initialize optabs to point to HPUX long double emulation routines. */
5307 pa_hpux_init_libfuncs (void)
5309 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5310 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5311 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5312 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5313 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5314 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5315 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5316 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5317 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5319 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5320 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5321 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5322 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5323 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5324 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5325 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5327 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5328 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5329 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5330 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5332 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5333 ? "__U_Qfcnvfxt_quad_to_sgl"
5334 : "_U_Qfcnvfxt_quad_to_sgl");
5335 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5336 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5337 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5339 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5340 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5344 /* HP's millicode routines mean something special to the assembler.
5345 Keep track of which ones we have used. */
5347 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5348 static void import_milli (enum millicodes);
5349 static char imported[(int) end1000];
5350 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5351 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5352 #define MILLI_START 10
5355 import_milli (enum millicodes code)
5357 char str[sizeof (import_string)];
5359 if (!imported[(int) code])
5361 imported[(int) code] = 1;
5362 strcpy (str, import_string);
5363 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5364 output_asm_insn (str, 0);
5368 /* The register constraints have put the operands and return value in
5369 the proper registers. */
5372 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5374 import_milli (mulI);
5375 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5378 /* Emit the rtl for doing a division by a constant. */
5380 /* Do magic division millicodes exist for this value? */
5381 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5383 /* We'll use an array to keep track of the magic millicodes and
5384 whether or not we've used them already. [n][0] is signed, [n][1] is
5387 static int div_milli[16][2];
5390 emit_hpdiv_const (rtx *operands, int unsignedp)
5392 if (GET_CODE (operands[2]) == CONST_INT
5393 && INTVAL (operands[2]) > 0
5394 && INTVAL (operands[2]) < 16
5395 && magic_milli[INTVAL (operands[2])])
5397 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5399 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5403 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5404 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5406 gen_rtx_REG (SImode, 26),
5408 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5409 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5410 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5411 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5412 gen_rtx_CLOBBER (VOIDmode, ret))));
5413 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5420 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5424 /* If the divisor is a constant, try to use one of the special
5426 if (GET_CODE (operands[0]) == CONST_INT)
5428 static char buf[100];
5429 divisor = INTVAL (operands[0]);
5430 if (!div_milli[divisor][unsignedp])
5432 div_milli[divisor][unsignedp] = 1;
5434 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5436 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5440 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5441 INTVAL (operands[0]));
5442 return output_millicode_call (insn,
5443 gen_rtx_SYMBOL_REF (SImode, buf));
5447 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5448 INTVAL (operands[0]));
5449 return output_millicode_call (insn,
5450 gen_rtx_SYMBOL_REF (SImode, buf));
5453 /* Divisor isn't a special constant. */
5458 import_milli (divU);
5459 return output_millicode_call (insn,
5460 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5464 import_milli (divI);
5465 return output_millicode_call (insn,
5466 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5471 /* Output a $$rem millicode to do mod. */
5474 output_mod_insn (int unsignedp, rtx insn)
5478 import_milli (remU);
5479 return output_millicode_call (insn,
5480 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5484 import_milli (remI);
5485 return output_millicode_call (insn,
5486 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5491 output_arg_descriptor (rtx call_insn)
5493 const char *arg_regs[4];
5494 enum machine_mode arg_mode;
5496 int i, output_flag = 0;
5499 /* We neither need nor want argument location descriptors for the
5500 64bit runtime environment or the ELF32 environment. */
5501 if (TARGET_64BIT || TARGET_ELF32)
5504 for (i = 0; i < 4; i++)
5507 /* Specify explicitly that no argument relocations should take place
5508 if using the portable runtime calling conventions. */
5509 if (TARGET_PORTABLE_RUNTIME)
5511 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5516 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5517 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5518 link; link = XEXP (link, 1))
5520 rtx use = XEXP (link, 0);
5522 if (! (GET_CODE (use) == USE
5523 && GET_CODE (XEXP (use, 0)) == REG
5524 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5527 arg_mode = GET_MODE (XEXP (use, 0));
5528 regno = REGNO (XEXP (use, 0));
5529 if (regno >= 23 && regno <= 26)
5531 arg_regs[26 - regno] = "GR";
5532 if (arg_mode == DImode)
5533 arg_regs[25 - regno] = "GR";
5535 else if (regno >= 32 && regno <= 39)
5537 if (arg_mode == SFmode)
5538 arg_regs[(regno - 32) / 2] = "FR";
5541 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5542 arg_regs[(regno - 34) / 2] = "FR";
5543 arg_regs[(regno - 34) / 2 + 1] = "FU";
5545 arg_regs[(regno - 34) / 2] = "FU";
5546 arg_regs[(regno - 34) / 2 + 1] = "FR";
5551 fputs ("\t.CALL ", asm_out_file);
5552 for (i = 0; i < 4; i++)
5557 fputc (',', asm_out_file);
5558 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5561 fputc ('\n', asm_out_file);
5564 /* Return the class of any secondary reload register that is needed to
5565 move IN into a register in class CLASS using mode MODE.
5567 Profiling has showed this routine and its descendants account for
5568 a significant amount of compile time (~7%). So it has been
5569 optimized to reduce redundant computations and eliminate useless
5572 It might be worthwhile to try and make this a leaf function too. */
5575 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5577 int regno, is_symbolic;
5579 /* Trying to load a constant into a FP register during PIC code
5580 generation will require %r1 as a scratch register. */
5582 && GET_MODE_CLASS (mode) == MODE_INT
5583 && FP_REG_CLASS_P (class)
5584 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5587 /* Profiling showed the PA port spends about 1.3% of its compilation
5588 time in true_regnum from calls inside secondary_reload_class. */
5590 if (GET_CODE (in) == REG)
5593 if (regno >= FIRST_PSEUDO_REGISTER)
5594 regno = true_regnum (in);
5596 else if (GET_CODE (in) == SUBREG)
5597 regno = true_regnum (in);
5601 /* If we have something like (mem (mem (...)), we can safely assume the
5602 inner MEM will end up in a general register after reloading, so there's
5603 no need for a secondary reload. */
5604 if (GET_CODE (in) == MEM
5605 && GET_CODE (XEXP (in, 0)) == MEM)
5608 /* Handle out of range displacement for integer mode loads/stores of
5610 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5611 && GET_MODE_CLASS (mode) == MODE_INT
5612 && FP_REG_CLASS_P (class))
5613 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5614 return GENERAL_REGS;
5616 /* A SAR<->FP register copy requires a secondary register (GPR) as
5617 well as secondary memory. */
5618 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5619 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5620 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5621 return GENERAL_REGS;
5623 if (GET_CODE (in) == HIGH)
5626 /* Profiling has showed GCC spends about 2.6% of its compilation
5627 time in symbolic_operand from calls inside secondary_reload_class.
5629 We use an inline copy and only compute its return value once to avoid
5631 switch (GET_CODE (in))
5641 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5642 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5643 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5653 && read_only_operand (in, VOIDmode))
5656 if (class != R1_REGS && is_symbolic)
5662 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5663 by invisible reference. As a GCC extension, we also pass anything
5664 with a zero or variable size by reference.
5666 The 64-bit runtime does not describe passing any types by invisible
5667 reference. The internals of GCC can't currently handle passing
5668 empty structures, and zero or variable length arrays when they are
5669 not passed entirely on the stack or by reference. Thus, as a GCC
5670 extension, we pass these types by reference. The HP compiler doesn't
5671 support these types, so hopefully there shouldn't be any compatibility
5672 issues. This may have to be revisited when HP releases a C99 compiler
5673 or updates the ABI. */
5676 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5677 enum machine_mode mode, tree type,
5678 bool named ATTRIBUTE_UNUSED)
5683 size = int_size_in_bytes (type);
5685 size = GET_MODE_SIZE (mode);
5690 return size <= 0 || size > 8;
5694 function_arg_padding (enum machine_mode mode, tree type)
5697 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5699 /* Return none if justification is not required. */
5701 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5702 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5705 /* The directions set here are ignored when a BLKmode argument larger
5706 than a word is placed in a register. Different code is used for
5707 the stack and registers. This makes it difficult to have a
5708 consistent data representation for both the stack and registers.
5709 For both runtimes, the justification and padding for arguments on
5710 the stack and in registers should be identical. */
5712 /* The 64-bit runtime specifies left justification for aggregates. */
5715 /* The 32-bit runtime architecture specifies right justification.
5716 When the argument is passed on the stack, the argument is padded
5717 with garbage on the left. The HP compiler pads with zeros. */
5721 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5728 /* Do what is necessary for `va_start'. We look at the current function
5729 to determine if stdargs or varargs is used and fill in an initial
5730 va_list. A pointer to this constructor is returned. */
5733 hppa_builtin_saveregs (void)
5736 tree fntype = TREE_TYPE (current_function_decl);
5737 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5738 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5739 != void_type_node)))
5740 ? UNITS_PER_WORD : 0);
5743 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5745 offset = current_function_arg_offset_rtx;
5751 /* Adjust for varargs/stdarg differences. */
5753 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5755 offset = current_function_arg_offset_rtx;
5757 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5758 from the incoming arg pointer and growing to larger addresses. */
5759 for (i = 26, off = -64; i >= 19; i--, off += 8)
5760 emit_move_insn (gen_rtx_MEM (word_mode,
5761 plus_constant (arg_pointer_rtx, off)),
5762 gen_rtx_REG (word_mode, i));
5764 /* The incoming args pointer points just beyond the flushback area;
5765 normally this is not a serious concern. However, when we are doing
5766 varargs/stdargs we want to make the arg pointer point to the start
5767 of the incoming argument area. */
5768 emit_move_insn (virtual_incoming_args_rtx,
5769 plus_constant (arg_pointer_rtx, -64));
5771 /* Now return a pointer to the first anonymous argument. */
5772 return copy_to_reg (expand_binop (Pmode, add_optab,
5773 virtual_incoming_args_rtx,
5774 offset, 0, 0, OPTAB_LIB_WIDEN));
5777 /* Store general registers on the stack. */
5778 dest = gen_rtx_MEM (BLKmode,
5779 plus_constant (current_function_internal_arg_pointer,
5781 set_mem_alias_set (dest, get_varargs_alias_set ());
5782 set_mem_align (dest, BITS_PER_WORD);
5783 move_block_from_reg (23, dest, 4);
5785 /* move_block_from_reg will emit code to store the argument registers
5786 individually as scalar stores.
5788 However, other insns may later load from the same addresses for
5789 a structure load (passing a struct to a varargs routine).
5791 The alias code assumes that such aliasing can never happen, so we
5792 have to keep memory referencing insns from moving up beyond the
5793 last argument register store. So we emit a blockage insn here. */
5794 emit_insn (gen_blockage ());
5796 return copy_to_reg (expand_binop (Pmode, add_optab,
5797 current_function_internal_arg_pointer,
5798 offset, 0, 0, OPTAB_LIB_WIDEN));
5802 hppa_va_start (tree valist, rtx nextarg)
5804 nextarg = expand_builtin_saveregs ();
5805 std_expand_builtin_va_start (valist, nextarg);
5809 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5813 /* Args grow upward. We can use the generic routines. */
5814 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5816 else /* !TARGET_64BIT */
5818 tree ptr = build_pointer_type (type);
5821 unsigned int size, ofs;
5824 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5828 ptr = build_pointer_type (type);
5830 size = int_size_in_bytes (type);
5831 valist_type = TREE_TYPE (valist);
5833 /* Args grow down. Not handled by generic routines. */
5835 u = fold_convert (valist_type, size_in_bytes (type));
5836 t = build (MINUS_EXPR, valist_type, valist, u);
5838 /* Copied from va-pa.h, but we probably don't need to align to
5839 word size, since we generate and preserve that invariant. */
5840 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
5841 t = build (BIT_AND_EXPR, valist_type, t, u);
5843 t = build (MODIFY_EXPR, valist_type, valist, t);
5845 ofs = (8 - size) % 4;
5848 u = fold_convert (valist_type, size_int (ofs));
5849 t = build (PLUS_EXPR, valist_type, t, u);
5852 t = fold_convert (ptr, t);
5853 t = build_va_arg_indirect_ref (t);
5856 t = build_va_arg_indirect_ref (t);
5862 /* True if MODE is valid for the target. By "valid", we mean able to
5863 be manipulated in non-trivial ways. In particular, this means all
5864 the arithmetic is supported.
5866 Currently, TImode is not valid as the HP 64-bit runtime documentation
5867 doesn't document the alignment and calling conventions for this type.
5868 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
5869 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
5872 pa_scalar_mode_supported_p (enum machine_mode mode)
5874 int precision = GET_MODE_PRECISION (mode);
5876 switch (GET_MODE_CLASS (mode))
5878 case MODE_PARTIAL_INT:
5880 if (precision == CHAR_TYPE_SIZE)
5882 if (precision == SHORT_TYPE_SIZE)
5884 if (precision == INT_TYPE_SIZE)
5886 if (precision == LONG_TYPE_SIZE)
5888 if (precision == LONG_LONG_TYPE_SIZE)
5893 if (precision == FLOAT_TYPE_SIZE)
5895 if (precision == DOUBLE_TYPE_SIZE)
5897 if (precision == LONG_DOUBLE_TYPE_SIZE)
5906 /* This routine handles all the normal conditional branch sequences we
5907 might need to generate. It handles compare immediate vs compare
5908 register, nullification of delay slots, varying length branches,
5909 negated branches, and all combinations of the above. It returns the
5910 output appropriate to emit the branch corresponding to all given
5914 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
5916 static char buf[100];
5920 /* A conditional branch to the following instruction (e.g. the delay slot)
5921 is asking for a disaster. This can happen when not optimizing and
5922 when jump optimization fails.
5924 While it is usually safe to emit nothing, this can fail if the
5925 preceding instruction is a nullified branch with an empty delay
5926 slot and the same branch target as this branch. We could check
5927 for this but jump optimization should eliminate nop jumps. It
5928 is always safe to emit a nop. */
5929 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5932 /* The doubleword form of the cmpib instruction doesn't have the LEU
5933 and GTU conditions while the cmpb instruction does. Since we accept
5934 zero for cmpb, we must ensure that we use cmpb for the comparison. */
5935 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
5936 operands[2] = gen_rtx_REG (DImode, 0);
5937 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
5938 operands[1] = gen_rtx_REG (DImode, 0);
5940 /* If this is a long branch with its delay slot unfilled, set `nullify'
5941 as it can nullify the delay slot and save a nop. */
5942 if (length == 8 && dbr_sequence_length () == 0)
5945 /* If this is a short forward conditional branch which did not get
5946 its delay slot filled, the delay slot can still be nullified. */
5947 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5948 nullify = forward_branch_p (insn);
5950 /* A forward branch over a single nullified insn can be done with a
5951 comclr instruction. This avoids a single cycle penalty due to
5952 mis-predicted branch if we fall through (branch not taken). */
5954 && next_real_insn (insn) != 0
5955 && get_attr_length (next_real_insn (insn)) == 4
5956 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5962 /* All short conditional branches except backwards with an unfilled
5966 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5968 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5969 if (GET_MODE (operands[1]) == DImode)
5972 strcat (buf, "%B3");
5974 strcat (buf, "%S3");
5976 strcat (buf, " %2,%r1,%%r0");
5978 strcat (buf, ",n %2,%r1,%0");
5980 strcat (buf, " %2,%r1,%0");
5983 /* All long conditionals. Note a short backward branch with an
5984 unfilled delay slot is treated just like a long backward branch
5985 with an unfilled delay slot. */
5987 /* Handle weird backwards branch with a filled delay slot
5988 with is nullified. */
5989 if (dbr_sequence_length () != 0
5990 && ! forward_branch_p (insn)
5993 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5994 if (GET_MODE (operands[1]) == DImode)
5997 strcat (buf, "%S3");
5999 strcat (buf, "%B3");
6000 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6002 /* Handle short backwards branch with an unfilled delay slot.
6003 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6004 taken and untaken branches. */
6005 else if (dbr_sequence_length () == 0
6006 && ! forward_branch_p (insn)
6007 && INSN_ADDRESSES_SET_P ()
6008 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6009 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6011 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6012 if (GET_MODE (operands[1]) == DImode)
6015 strcat (buf, "%B3 %2,%r1,%0%#");
6017 strcat (buf, "%S3 %2,%r1,%0%#");
6021 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6022 if (GET_MODE (operands[1]) == DImode)
6025 strcat (buf, "%S3");
6027 strcat (buf, "%B3");
6029 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6031 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6037 xoperands[0] = operands[0];
6038 xoperands[1] = operands[1];
6039 xoperands[2] = operands[2];
6040 xoperands[3] = operands[3];
6042 /* The reversed conditional branch must branch over one additional
6043 instruction if the delay slot is filled. If the delay slot
6044 is empty, the instruction after the reversed condition branch
6045 must be nullified. */
6046 nullify = dbr_sequence_length () == 0;
6047 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6049 /* Create a reversed conditional branch which branches around
6050 the following insns. */
6051 if (GET_MODE (operands[1]) != DImode)
6057 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6060 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6066 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6069 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6078 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6081 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6087 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6090 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6094 output_asm_insn (buf, xoperands);
6095 return output_lbranch (operands[0], insn);
6103 /* This routine handles long unconditional branches that exceed the
6104 maximum range of a simple branch instruction. */
6107 output_lbranch (rtx dest, rtx insn)
6111 xoperands[0] = dest;
6113 /* First, free up the delay slot. */
6114 if (dbr_sequence_length () != 0)
6116 /* We can't handle a jump in the delay slot. */
6117 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6119 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6122 /* Now delete the delay insn. */
6123 PUT_CODE (NEXT_INSN (insn), NOTE);
6124 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6125 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6128 /* Output an insn to save %r1. The runtime documentation doesn't
6129 specify whether the "Clean Up" slot in the callers frame can
6130 be clobbered by the callee. It isn't copied by HP's builtin
6131 alloca, so this suggests that it can be clobbered if necessary.
6132 The "Static Link" location is copied by HP builtin alloca, so
6133 we avoid using it. Using the cleanup slot might be a problem
6134 if we have to interoperate with languages that pass cleanup
6135 information. However, it should be possible to handle these
6136 situations with GCC's asm feature.
6138 The "Current RP" slot is reserved for the called procedure, so
6139 we try to use it when we don't have a frame of our own. It's
6140 rather unlikely that we won't have a frame when we need to emit
6143 Really the way to go long term is a register scavenger; goto
6144 the target of the jump and find a register which we can use
6145 as a scratch to hold the value in %r1. Then, we wouldn't have
6146 to free up the delay slot or clobber a slot that may be needed
6147 for other purposes. */
6150 if (actual_fsize == 0 && !regs_ever_live[2])
6151 /* Use the return pointer slot in the frame marker. */
6152 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6154 /* Use the slot at -40 in the frame marker since HP builtin
6155 alloca doesn't copy it. */
6156 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6160 if (actual_fsize == 0 && !regs_ever_live[2])
6161 /* Use the return pointer slot in the frame marker. */
6162 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6164 /* Use the "Clean Up" slot in the frame marker. In GCC,
6165 the only other use of this location is for copying a
6166 floating point double argument from a floating-point
6167 register to two general registers. The copy is done
6168 as an "atomic" operation when outputting a call, so it
6169 won't interfere with our using the location here. */
6170 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6173 if (TARGET_PORTABLE_RUNTIME)
6175 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6176 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6177 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6181 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6182 if (TARGET_SOM || !TARGET_GAS)
6184 xoperands[1] = gen_label_rtx ();
6185 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6186 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6187 CODE_LABEL_NUMBER (xoperands[1]));
6188 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6192 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6193 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6195 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6198 /* Now output a very long branch to the original target. */
6199 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6201 /* Now restore the value of %r1 in the delay slot. */
6204 if (actual_fsize == 0 && !regs_ever_live[2])
6205 return "ldd -16(%%r30),%%r1";
6207 return "ldd -40(%%r30),%%r1";
6211 if (actual_fsize == 0 && !regs_ever_live[2])
6212 return "ldw -20(%%r30),%%r1";
6214 return "ldw -12(%%r30),%%r1";
6218 /* This routine handles all the branch-on-bit conditional branch sequences we
6219 might need to generate. It handles nullification of delay slots,
6220 varying length branches, negated branches and all combinations of the
6221 above. it returns the appropriate output template to emit the branch. */
6224 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6225 int negated, rtx insn, int which)
6227 static char buf[100];
6230 /* A conditional branch to the following instruction (e.g. the delay slot) is
6231 asking for a disaster. I do not think this can happen as this pattern
6232 is only used when optimizing; jump optimization should eliminate the
6233 jump. But be prepared just in case. */
6235 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6238 /* If this is a long branch with its delay slot unfilled, set `nullify'
6239 as it can nullify the delay slot and save a nop. */
6240 if (length == 8 && dbr_sequence_length () == 0)
6243 /* If this is a short forward conditional branch which did not get
6244 its delay slot filled, the delay slot can still be nullified. */
6245 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6246 nullify = forward_branch_p (insn);
6248 /* A forward branch over a single nullified insn can be done with a
6249 extrs instruction. This avoids a single cycle penalty due to
6250 mis-predicted branch if we fall through (branch not taken). */
6253 && next_real_insn (insn) != 0
6254 && get_attr_length (next_real_insn (insn)) == 4
6255 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6262 /* All short conditional branches except backwards with an unfilled
6266 strcpy (buf, "{extrs,|extrw,s,}");
6268 strcpy (buf, "bb,");
6269 if (useskip && GET_MODE (operands[0]) == DImode)
6270 strcpy (buf, "extrd,s,*");
6271 else if (GET_MODE (operands[0]) == DImode)
6272 strcpy (buf, "bb,*");
6273 if ((which == 0 && negated)
6274 || (which == 1 && ! negated))
6279 strcat (buf, " %0,%1,1,%%r0");
6280 else if (nullify && negated)
6281 strcat (buf, ",n %0,%1,%3");
6282 else if (nullify && ! negated)
6283 strcat (buf, ",n %0,%1,%2");
6284 else if (! nullify && negated)
6285 strcat (buf, "%0,%1,%3");
6286 else if (! nullify && ! negated)
6287 strcat (buf, " %0,%1,%2");
6290 /* All long conditionals. Note a short backward branch with an
6291 unfilled delay slot is treated just like a long backward branch
6292 with an unfilled delay slot. */
6294 /* Handle weird backwards branch with a filled delay slot
6295 with is nullified. */
6296 if (dbr_sequence_length () != 0
6297 && ! forward_branch_p (insn)
6300 strcpy (buf, "bb,");
6301 if (GET_MODE (operands[0]) == DImode)
6303 if ((which == 0 && negated)
6304 || (which == 1 && ! negated))
6309 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6311 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6313 /* Handle short backwards branch with an unfilled delay slot.
6314 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6315 taken and untaken branches. */
6316 else if (dbr_sequence_length () == 0
6317 && ! forward_branch_p (insn)
6318 && INSN_ADDRESSES_SET_P ()
6319 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6320 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6322 strcpy (buf, "bb,");
6323 if (GET_MODE (operands[0]) == DImode)
6325 if ((which == 0 && negated)
6326 || (which == 1 && ! negated))
6331 strcat (buf, " %0,%1,%3%#");
6333 strcat (buf, " %0,%1,%2%#");
6337 strcpy (buf, "{extrs,|extrw,s,}");
6338 if (GET_MODE (operands[0]) == DImode)
6339 strcpy (buf, "extrd,s,*");
6340 if ((which == 0 && negated)
6341 || (which == 1 && ! negated))
6345 if (nullify && negated)
6346 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6347 else if (nullify && ! negated)
6348 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6350 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6352 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6362 /* This routine handles all the branch-on-variable-bit conditional branch
6363 sequences we might need to generate. It handles nullification of delay
6364 slots, varying length branches, negated branches and all combinations
6365 of the above. it returns the appropriate output template to emit the
6369 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6370 int negated, rtx insn, int which)
6372 static char buf[100];
6375 /* A conditional branch to the following instruction (e.g. the delay slot) is
6376 asking for a disaster. I do not think this can happen as this pattern
6377 is only used when optimizing; jump optimization should eliminate the
6378 jump. But be prepared just in case. */
6380 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6383 /* If this is a long branch with its delay slot unfilled, set `nullify'
6384 as it can nullify the delay slot and save a nop. */
6385 if (length == 8 && dbr_sequence_length () == 0)
6388 /* If this is a short forward conditional branch which did not get
6389 its delay slot filled, the delay slot can still be nullified. */
6390 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6391 nullify = forward_branch_p (insn);
6393 /* A forward branch over a single nullified insn can be done with a
6394 extrs instruction. This avoids a single cycle penalty due to
6395 mis-predicted branch if we fall through (branch not taken). */
6398 && next_real_insn (insn) != 0
6399 && get_attr_length (next_real_insn (insn)) == 4
6400 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6407 /* All short conditional branches except backwards with an unfilled
6411 strcpy (buf, "{vextrs,|extrw,s,}");
6413 strcpy (buf, "{bvb,|bb,}");
6414 if (useskip && GET_MODE (operands[0]) == DImode)
6415 strcpy (buf, "extrd,s,*");
6416 else if (GET_MODE (operands[0]) == DImode)
6417 strcpy (buf, "bb,*");
6418 if ((which == 0 && negated)
6419 || (which == 1 && ! negated))
6424 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6425 else if (nullify && negated)
6426 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6427 else if (nullify && ! negated)
6428 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6429 else if (! nullify && negated)
6430 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6431 else if (! nullify && ! negated)
6432 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6435 /* All long conditionals. Note a short backward branch with an
6436 unfilled delay slot is treated just like a long backward branch
6437 with an unfilled delay slot. */
6439 /* Handle weird backwards branch with a filled delay slot
6440 with is nullified. */
6441 if (dbr_sequence_length () != 0
6442 && ! forward_branch_p (insn)
6445 strcpy (buf, "{bvb,|bb,}");
6446 if (GET_MODE (operands[0]) == DImode)
6448 if ((which == 0 && negated)
6449 || (which == 1 && ! negated))
6454 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6456 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6458 /* Handle short backwards branch with an unfilled delay slot.
6459 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6460 taken and untaken branches. */
6461 else if (dbr_sequence_length () == 0
6462 && ! forward_branch_p (insn)
6463 && INSN_ADDRESSES_SET_P ()
6464 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6465 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6467 strcpy (buf, "{bvb,|bb,}");
6468 if (GET_MODE (operands[0]) == DImode)
6470 if ((which == 0 && negated)
6471 || (which == 1 && ! negated))
6476 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6478 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6482 strcpy (buf, "{vextrs,|extrw,s,}");
6483 if (GET_MODE (operands[0]) == DImode)
6484 strcpy (buf, "extrd,s,*");
6485 if ((which == 0 && negated)
6486 || (which == 1 && ! negated))
6490 if (nullify && negated)
6491 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6492 else if (nullify && ! negated)
6493 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6495 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6497 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6507 /* Return the output template for emitting a dbra type insn.
6509 Note it may perform some output operations on its own before
6510 returning the final output string. */
6512 output_dbra (rtx *operands, rtx insn, int which_alternative)
6515 /* A conditional branch to the following instruction (e.g. the delay slot) is
6516 asking for a disaster. Be prepared! */
6518 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6520 if (which_alternative == 0)
6521 return "ldo %1(%0),%0";
6522 else if (which_alternative == 1)
6524 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6525 output_asm_insn ("ldw -16(%%r30),%4", operands);
6526 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6527 return "{fldws|fldw} -16(%%r30),%0";
6531 output_asm_insn ("ldw %0,%4", operands);
6532 return "ldo %1(%4),%4\n\tstw %4,%0";
6536 if (which_alternative == 0)
6538 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6539 int length = get_attr_length (insn);
6541 /* If this is a long branch with its delay slot unfilled, set `nullify'
6542 as it can nullify the delay slot and save a nop. */
6543 if (length == 8 && dbr_sequence_length () == 0)
6546 /* If this is a short forward conditional branch which did not get
6547 its delay slot filled, the delay slot can still be nullified. */
6548 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6549 nullify = forward_branch_p (insn);
6555 return "addib,%C2,n %1,%0,%3";
6557 return "addib,%C2 %1,%0,%3";
6560 /* Handle weird backwards branch with a fulled delay slot
6561 which is nullified. */
6562 if (dbr_sequence_length () != 0
6563 && ! forward_branch_p (insn)
6565 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6566 /* Handle short backwards branch with an unfilled delay slot.
6567 Using a addb;nop rather than addi;bl saves 1 cycle for both
6568 taken and untaken branches. */
6569 else if (dbr_sequence_length () == 0
6570 && ! forward_branch_p (insn)
6571 && INSN_ADDRESSES_SET_P ()
6572 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6573 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6574 return "addib,%C2 %1,%0,%3%#";
6576 /* Handle normal cases. */
6578 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6580 return "addi,%N2 %1,%0,%0\n\tb %3";
6587 /* Deal with gross reload from FP register case. */
6588 else if (which_alternative == 1)
6590 /* Move loop counter from FP register to MEM then into a GR,
6591 increment the GR, store the GR into MEM, and finally reload
6592 the FP register from MEM from within the branch's delay slot. */
6593 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6595 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6596 if (get_attr_length (insn) == 24)
6597 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6599 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6601 /* Deal with gross reload from memory case. */
6604 /* Reload loop counter from memory, the store back to memory
6605 happens in the branch's delay slot. */
6606 output_asm_insn ("ldw %0,%4", operands);
6607 if (get_attr_length (insn) == 12)
6608 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6610 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6614 /* Return the output template for emitting a dbra type insn.
6616 Note it may perform some output operations on its own before
6617 returning the final output string. */
6619 output_movb (rtx *operands, rtx insn, int which_alternative,
6620 int reverse_comparison)
6623 /* A conditional branch to the following instruction (e.g. the delay slot) is
6624 asking for a disaster. Be prepared! */
6626 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6628 if (which_alternative == 0)
6629 return "copy %1,%0";
6630 else if (which_alternative == 1)
6632 output_asm_insn ("stw %1,-16(%%r30)", operands);
6633 return "{fldws|fldw} -16(%%r30),%0";
6635 else if (which_alternative == 2)
6641 /* Support the second variant. */
6642 if (reverse_comparison)
6643 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6645 if (which_alternative == 0)
6647 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6648 int length = get_attr_length (insn);
6650 /* If this is a long branch with its delay slot unfilled, set `nullify'
6651 as it can nullify the delay slot and save a nop. */
6652 if (length == 8 && dbr_sequence_length () == 0)
6655 /* If this is a short forward conditional branch which did not get
6656 its delay slot filled, the delay slot can still be nullified. */
6657 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6658 nullify = forward_branch_p (insn);
6664 return "movb,%C2,n %1,%0,%3";
6666 return "movb,%C2 %1,%0,%3";
6669 /* Handle weird backwards branch with a filled delay slot
6670 which is nullified. */
6671 if (dbr_sequence_length () != 0
6672 && ! forward_branch_p (insn)
6674 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6676 /* Handle short backwards branch with an unfilled delay slot.
6677 Using a movb;nop rather than or;bl saves 1 cycle for both
6678 taken and untaken branches. */
6679 else if (dbr_sequence_length () == 0
6680 && ! forward_branch_p (insn)
6681 && INSN_ADDRESSES_SET_P ()
6682 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6683 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6684 return "movb,%C2 %1,%0,%3%#";
6685 /* Handle normal cases. */
6687 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6689 return "or,%N2 %1,%%r0,%0\n\tb %3";
6695 /* Deal with gross reload from FP register case. */
6696 else if (which_alternative == 1)
6698 /* Move loop counter from FP register to MEM then into a GR,
6699 increment the GR, store the GR into MEM, and finally reload
6700 the FP register from MEM from within the branch's delay slot. */
6701 output_asm_insn ("stw %1,-16(%%r30)", operands);
6702 if (get_attr_length (insn) == 12)
6703 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6705 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6707 /* Deal with gross reload from memory case. */
6708 else if (which_alternative == 2)
6710 /* Reload loop counter from memory, the store back to memory
6711 happens in the branch's delay slot. */
6712 if (get_attr_length (insn) == 8)
6713 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6715 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6717 /* Handle SAR as a destination. */
6720 if (get_attr_length (insn) == 8)
6721 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6723 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6727 /* Copy any FP arguments in INSN into integer registers. */
6729 copy_fp_args (rtx insn)
6734 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6736 int arg_mode, regno;
6737 rtx use = XEXP (link, 0);
6739 if (! (GET_CODE (use) == USE
6740 && GET_CODE (XEXP (use, 0)) == REG
6741 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6744 arg_mode = GET_MODE (XEXP (use, 0));
6745 regno = REGNO (XEXP (use, 0));
6747 /* Is it a floating point register? */
6748 if (regno >= 32 && regno <= 39)
6750 /* Copy the FP register into an integer register via memory. */
6751 if (arg_mode == SFmode)
6753 xoperands[0] = XEXP (use, 0);
6754 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6755 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6756 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6760 xoperands[0] = XEXP (use, 0);
6761 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6762 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6763 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6764 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6770 /* Compute length of the FP argument copy sequence for INSN. */
6772 length_fp_args (rtx insn)
6777 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6779 int arg_mode, regno;
6780 rtx use = XEXP (link, 0);
6782 if (! (GET_CODE (use) == USE
6783 && GET_CODE (XEXP (use, 0)) == REG
6784 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6787 arg_mode = GET_MODE (XEXP (use, 0));
6788 regno = REGNO (XEXP (use, 0));
6790 /* Is it a floating point register? */
6791 if (regno >= 32 && regno <= 39)
6793 if (arg_mode == SFmode)
6803 /* Return the attribute length for the millicode call instruction INSN.
6804 The length must match the code generated by output_millicode_call.
6805 We include the delay slot in the returned length as it is better to
6806 over estimate the length than to under estimate it. */
6809 attr_length_millicode_call (rtx insn)
6811 unsigned long distance = -1;
6812 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6814 if (INSN_ADDRESSES_SET_P ())
6816 distance = (total + insn_current_reference_address (insn));
6817 if (distance < total)
6823 if (!TARGET_LONG_CALLS && distance < 7600000)
6828 else if (TARGET_PORTABLE_RUNTIME)
6832 if (!TARGET_LONG_CALLS && distance < 240000)
6835 if (TARGET_LONG_ABS_CALL && !flag_pic)
6842 /* INSN is a function call. It may have an unconditional jump
6845 CALL_DEST is the routine we are calling. */
6848 output_millicode_call (rtx insn, rtx call_dest)
6850 int attr_length = get_attr_length (insn);
6851 int seq_length = dbr_sequence_length ();
6856 xoperands[0] = call_dest;
6857 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6859 /* Handle the common case where we are sure that the branch will
6860 reach the beginning of the $CODE$ subspace. The within reach
6861 form of the $$sh_func_adrs call has a length of 28. Because
6862 it has an attribute type of multi, it never has a nonzero
6863 sequence length. The length of the $$sh_func_adrs is the same
6864 as certain out of reach PIC calls to other routines. */
6865 if (!TARGET_LONG_CALLS
6866 && ((seq_length == 0
6867 && (attr_length == 12
6868 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6869 || (seq_length != 0 && attr_length == 8)))
6871 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6877 /* It might seem that one insn could be saved by accessing
6878 the millicode function using the linkage table. However,
6879 this doesn't work in shared libraries and other dynamically
6880 loaded objects. Using a pc-relative sequence also avoids
6881 problems related to the implicit use of the gp register. */
6882 output_asm_insn ("b,l .+8,%%r1", xoperands);
6886 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6887 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6891 xoperands[1] = gen_label_rtx ();
6892 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6893 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6894 CODE_LABEL_NUMBER (xoperands[1]));
6895 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6898 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6900 else if (TARGET_PORTABLE_RUNTIME)
6902 /* Pure portable runtime doesn't allow be/ble; we also don't
6903 have PIC support in the assembler/linker, so this sequence
6906 /* Get the address of our target into %r1. */
6907 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6908 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6910 /* Get our return address into %r31. */
6911 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6912 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6914 /* Jump to our target address in %r1. */
6915 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6919 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6921 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6923 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6927 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6928 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6930 if (TARGET_SOM || !TARGET_GAS)
6932 /* The HP assembler can generate relocations for the
6933 difference of two symbols. GAS can do this for a
6934 millicode symbol but not an arbitrary external
6935 symbol when generating SOM output. */
6936 xoperands[1] = gen_label_rtx ();
6937 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6938 CODE_LABEL_NUMBER (xoperands[1]));
6939 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6940 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6944 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6945 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6949 /* Jump to our target address in %r1. */
6950 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6954 if (seq_length == 0)
6955 output_asm_insn ("nop", xoperands);
6957 /* We are done if there isn't a jump in the delay slot. */
6958 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6961 /* This call has an unconditional jump in its delay slot. */
6962 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6964 /* See if the return address can be adjusted. Use the containing
6965 sequence insn's address. */
6966 if (INSN_ADDRESSES_SET_P ())
6968 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6969 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6970 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6972 if (VAL_14_BITS_P (distance))
6974 xoperands[1] = gen_label_rtx ();
6975 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6976 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6977 CODE_LABEL_NUMBER (xoperands[1]));
6980 /* ??? This branch may not reach its target. */
6981 output_asm_insn ("nop\n\tb,n %0", xoperands);
6984 /* ??? This branch may not reach its target. */
6985 output_asm_insn ("nop\n\tb,n %0", xoperands);
6987 /* Delete the jump. */
6988 PUT_CODE (NEXT_INSN (insn), NOTE);
6989 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6990 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6995 /* Return the attribute length of the call instruction INSN. The SIBCALL
6996 flag indicates whether INSN is a regular call or a sibling call. The
6997 length returned must be longer than the code actually generated by
6998 output_call. Since branch shortening is done before delay branch
6999 sequencing, there is no way to determine whether or not the delay
7000 slot will be filled during branch shortening. Even when the delay
7001 slot is filled, we may have to add a nop if the delay slot contains
7002 a branch that can't reach its target. Thus, we always have to include
7003 the delay slot in the length estimate. This used to be done in
7004 pa_adjust_insn_length but we do it here now as some sequences always
7005 fill the delay slot and we can save four bytes in the estimate for
7009 attr_length_call (rtx insn, int sibcall)
7015 rtx pat = PATTERN (insn);
7016 unsigned long distance = -1;
7018 if (INSN_ADDRESSES_SET_P ())
7020 unsigned long total;
7022 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7023 distance = (total + insn_current_reference_address (insn));
7024 if (distance < total)
7028 /* Determine if this is a local call. */
7029 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7030 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7032 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7034 call_decl = SYMBOL_REF_DECL (call_dest);
7035 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7037 /* pc-relative branch. */
7038 if (!TARGET_LONG_CALLS
7039 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7040 || distance < 240000))
7043 /* 64-bit plabel sequence. */
7044 else if (TARGET_64BIT && !local_call)
7045 length += sibcall ? 28 : 24;
7047 /* non-pic long absolute branch sequence. */
7048 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7051 /* long pc-relative branch sequence. */
7052 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7053 || (TARGET_64BIT && !TARGET_GAS)
7054 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7058 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7062 /* 32-bit plabel sequence. */
7068 length += length_fp_args (insn);
7078 if (!TARGET_NO_SPACE_REGS)
7086 /* INSN is a function call. It may have an unconditional jump
7089 CALL_DEST is the routine we are calling. */
7092 output_call (rtx insn, rtx call_dest, int sibcall)
7094 int delay_insn_deleted = 0;
7095 int delay_slot_filled = 0;
7096 int seq_length = dbr_sequence_length ();
7097 tree call_decl = SYMBOL_REF_DECL (call_dest);
7098 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7101 xoperands[0] = call_dest;
7103 /* Handle the common case where we're sure that the branch will reach
7104 the beginning of the "$CODE$" subspace. This is the beginning of
7105 the current function if we are in a named section. */
7106 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7108 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7109 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7113 if (TARGET_64BIT && !local_call)
7115 /* ??? As far as I can tell, the HP linker doesn't support the
7116 long pc-relative sequence described in the 64-bit runtime
7117 architecture. So, we use a slightly longer indirect call. */
7118 xoperands[0] = get_deferred_plabel (call_dest);
7119 xoperands[1] = gen_label_rtx ();
7121 /* If this isn't a sibcall, we put the load of %r27 into the
7122 delay slot. We can't do this in a sibcall as we don't
7123 have a second call-clobbered scratch register available. */
7125 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7128 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7131 /* Now delete the delay insn. */
7132 PUT_CODE (NEXT_INSN (insn), NOTE);
7133 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7134 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7135 delay_insn_deleted = 1;
7138 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7139 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7140 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7144 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7145 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7146 output_asm_insn ("bve (%%r1)", xoperands);
7150 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7151 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7152 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7153 delay_slot_filled = 1;
7158 int indirect_call = 0;
7160 /* Emit a long call. There are several different sequences
7161 of increasing length and complexity. In most cases,
7162 they don't allow an instruction in the delay slot. */
7163 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7164 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7165 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7170 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7172 && (!TARGET_PA_20 || indirect_call))
7174 /* A non-jump insn in the delay slot. By definition we can
7175 emit this insn before the call (and in fact before argument
7177 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7180 /* Now delete the delay insn. */
7181 PUT_CODE (NEXT_INSN (insn), NOTE);
7182 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7183 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7184 delay_insn_deleted = 1;
7187 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7189 /* This is the best sequence for making long calls in
7190 non-pic code. Unfortunately, GNU ld doesn't provide
7191 the stub needed for external calls, and GAS's support
7192 for this with the SOM linker is buggy. It is safe
7193 to use this for local calls. */
7194 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7196 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7200 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7203 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7205 output_asm_insn ("copy %%r31,%%r2", xoperands);
7206 delay_slot_filled = 1;
7211 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7212 || (TARGET_64BIT && !TARGET_GAS))
7214 /* The HP assembler and linker can handle relocations
7215 for the difference of two symbols. GAS and the HP
7216 linker can't do this when one of the symbols is
7218 xoperands[1] = gen_label_rtx ();
7219 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7220 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7221 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7222 CODE_LABEL_NUMBER (xoperands[1]));
7223 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7225 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7227 /* GAS currently can't generate the relocations that
7228 are needed for the SOM linker under HP-UX using this
7229 sequence. The GNU linker doesn't generate the stubs
7230 that are needed for external calls on TARGET_ELF32
7231 with this sequence. For now, we have to use a
7232 longer plabel sequence when using GAS. */
7233 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7234 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7236 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7241 /* Emit a long plabel-based call sequence. This is
7242 essentially an inline implementation of $$dyncall.
7243 We don't actually try to call $$dyncall as this is
7244 as difficult as calling the function itself. */
7245 xoperands[0] = get_deferred_plabel (call_dest);
7246 xoperands[1] = gen_label_rtx ();
7248 /* Since the call is indirect, FP arguments in registers
7249 need to be copied to the general registers. Then, the
7250 argument relocation stub will copy them back. */
7252 copy_fp_args (insn);
7256 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7257 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7258 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7262 output_asm_insn ("addil LR'%0-$global$,%%r27",
7264 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7268 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7269 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7270 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7271 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7273 if (!sibcall && !TARGET_PA_20)
7275 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7276 if (TARGET_NO_SPACE_REGS)
7277 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7279 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7286 output_asm_insn ("bve (%%r1)", xoperands);
7291 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7292 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7293 delay_slot_filled = 1;
7296 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7301 if (!TARGET_NO_SPACE_REGS)
7302 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7307 if (TARGET_NO_SPACE_REGS)
7308 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7310 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7314 if (TARGET_NO_SPACE_REGS)
7315 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7317 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7320 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7322 output_asm_insn ("copy %%r31,%%r2", xoperands);
7323 delay_slot_filled = 1;
7330 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7331 output_asm_insn ("nop", xoperands);
7333 /* We are done if there isn't a jump in the delay slot. */
7335 || delay_insn_deleted
7336 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7339 /* A sibcall should never have a branch in the delay slot. */
7340 gcc_assert (!sibcall);
7342 /* This call has an unconditional jump in its delay slot. */
7343 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7345 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7347 /* See if the return address can be adjusted. Use the containing
7348 sequence insn's address. */
7349 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7350 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7351 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7353 if (VAL_14_BITS_P (distance))
7355 xoperands[1] = gen_label_rtx ();
7356 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7357 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7358 CODE_LABEL_NUMBER (xoperands[1]));
7361 output_asm_insn ("nop\n\tb,n %0", xoperands);
7364 output_asm_insn ("b,n %0", xoperands);
7366 /* Delete the jump. */
7367 PUT_CODE (NEXT_INSN (insn), NOTE);
7368 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7369 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7374 /* Return the attribute length of the indirect call instruction INSN.
7375 The length must match the code generated by output_indirect call.
7376 The returned length includes the delay slot. Currently, the delay
7377 slot of an indirect call sequence is not exposed and it is used by
7378 the sequence itself. */
7381 attr_length_indirect_call (rtx insn)
7383 unsigned long distance = -1;
7384 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7386 if (INSN_ADDRESSES_SET_P ())
7388 distance = (total + insn_current_reference_address (insn));
7389 if (distance < total)
7396 if (TARGET_FAST_INDIRECT_CALLS
7397 || (!TARGET_PORTABLE_RUNTIME
7398 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7404 if (TARGET_PORTABLE_RUNTIME)
7407 /* Out of reach, can use ble. */
7412 output_indirect_call (rtx insn, rtx call_dest)
7418 xoperands[0] = call_dest;
7419 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7420 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7424 /* First the special case for kernels, level 0 systems, etc. */
7425 if (TARGET_FAST_INDIRECT_CALLS)
7426 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7428 /* Now the normal case -- we can reach $$dyncall directly or
7429 we're sure that we can get there via a long-branch stub.
7431 No need to check target flags as the length uniquely identifies
7432 the remaining cases. */
7433 if (attr_length_indirect_call (insn) == 8)
7435 /* The HP linker substitutes a BLE for millicode calls using
7436 the short PIC PCREL form. Thus, we must use %r31 as the
7437 link register when generating PA 1.x code. */
7439 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7441 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7444 /* Long millicode call, but we are not generating PIC or portable runtime
7446 if (attr_length_indirect_call (insn) == 12)
7447 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7449 /* Long millicode call for portable runtime. */
7450 if (attr_length_indirect_call (insn) == 20)
7451 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7453 /* We need a long PIC call to $$dyncall. */
7454 xoperands[0] = NULL_RTX;
7455 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7456 if (TARGET_SOM || !TARGET_GAS)
7458 xoperands[0] = gen_label_rtx ();
7459 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7460 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7461 CODE_LABEL_NUMBER (xoperands[0]));
7462 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7466 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7467 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7470 output_asm_insn ("blr %%r0,%%r2", xoperands);
7471 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7475 /* Return the total length of the save and restore instructions needed for
7476 the data linkage table pointer (i.e., the PIC register) across the call
7477 instruction INSN. No-return calls do not require a save and restore.
7478 In addition, we may be able to avoid the save and restore for calls
7479 within the same translation unit. */
7482 attr_length_save_restore_dltp (rtx insn)
7484 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7490 /* In HPUX 8.0's shared library scheme, special relocations are needed
7491 for function labels if they might be passed to a function
7492 in a shared library (because shared libraries don't live in code
7493 space), and special magic is needed to construct their address. */
7496 hppa_encode_label (rtx sym)
7498 const char *str = XSTR (sym, 0);
7499 int len = strlen (str) + 1;
7502 p = newstr = alloca (len + 1);
7506 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7510 pa_encode_section_info (tree decl, rtx rtl, int first)
7512 default_encode_section_info (decl, rtl, first);
7514 if (first && TEXT_SPACE_P (decl))
7516 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7517 if (TREE_CODE (decl) == FUNCTION_DECL)
7518 hppa_encode_label (XEXP (rtl, 0));
7522 /* This is sort of inverse to pa_encode_section_info. */
7525 pa_strip_name_encoding (const char *str)
7527 str += (*str == '@');
7528 str += (*str == '*');
7533 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7535 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7538 /* Returns 1 if OP is a function label involved in a simple addition
7539 with a constant. Used to keep certain patterns from matching
7540 during instruction combination. */
7542 is_function_label_plus_const (rtx op)
7544 /* Strip off any CONST. */
7545 if (GET_CODE (op) == CONST)
7548 return (GET_CODE (op) == PLUS
7549 && function_label_operand (XEXP (op, 0), Pmode)
7550 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7553 /* Output assembly code for a thunk to FUNCTION. */
7556 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7557 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7560 static unsigned int current_thunk_number;
7561 int val_14 = VAL_14_BITS_P (delta);
7566 xoperands[0] = XEXP (DECL_RTL (function), 0);
7567 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7568 xoperands[2] = GEN_INT (delta);
7570 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7571 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7573 /* Output the thunk. We know that the function is in the same
7574 translation unit (i.e., the same space) as the thunk, and that
7575 thunks are output after their method. Thus, we don't need an
7576 external branch to reach the function. With SOM and GAS,
7577 functions and thunks are effectively in different sections.
7578 Thus, we can always use a IA-relative branch and the linker
7579 will add a long branch stub if necessary.
7581 However, we have to be careful when generating PIC code on the
7582 SOM port to ensure that the sequence does not transfer to an
7583 import stub for the target function as this could clobber the
7584 return value saved at SP-24. This would also apply to the
7585 32-bit linux port if the multi-space model is implemented. */
7586 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7587 && !(flag_pic && TREE_PUBLIC (function))
7588 && (TARGET_GAS || last_address < 262132))
7589 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7590 && ((targetm.have_named_sections
7591 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7592 /* The GNU 64-bit linker has rather poor stub management.
7593 So, we use a long branch from thunks that aren't in
7594 the same section as the target function. */
7596 && (DECL_SECTION_NAME (thunk_fndecl)
7597 != DECL_SECTION_NAME (function)))
7598 || ((DECL_SECTION_NAME (thunk_fndecl)
7599 == DECL_SECTION_NAME (function))
7600 && last_address < 262132)))
7601 || (!targetm.have_named_sections && last_address < 262132))))
7604 output_asm_insn ("addil L'%2,%%r26", xoperands);
7606 output_asm_insn ("b %0", xoperands);
7610 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7615 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7619 else if (TARGET_64BIT)
7621 /* We only have one call-clobbered scratch register, so we can't
7622 make use of the delay slot if delta doesn't fit in 14 bits. */
7625 output_asm_insn ("addil L'%2,%%r26", xoperands);
7626 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7629 output_asm_insn ("b,l .+8,%%r1", xoperands);
7633 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7634 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7638 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7639 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7644 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7645 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7650 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7654 else if (TARGET_PORTABLE_RUNTIME)
7656 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7657 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7660 output_asm_insn ("addil L'%2,%%r26", xoperands);
7662 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7666 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7671 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7675 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7677 /* The function is accessible from outside this module. The only
7678 way to avoid an import stub between the thunk and function is to
7679 call the function directly with an indirect sequence similar to
7680 that used by $$dyncall. This is possible because $$dyncall acts
7681 as the import stub in an indirect call. */
7682 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7683 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7684 output_asm_insn ("addil LT'%3,%%r19", xoperands);
7685 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
7686 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7687 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
7688 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
7689 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
7690 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7694 output_asm_insn ("addil L'%2,%%r26", xoperands);
7700 output_asm_insn ("bve (%%r22)", xoperands);
7703 else if (TARGET_NO_SPACE_REGS)
7705 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
7710 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
7711 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
7712 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
7717 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7719 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7723 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7725 if (TARGET_SOM || !TARGET_GAS)
7727 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
7728 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
7732 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7733 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
7737 output_asm_insn ("addil L'%2,%%r26", xoperands);
7739 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7743 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7748 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7755 output_asm_insn ("addil L'%2,%%r26", xoperands);
7757 output_asm_insn ("ldil L'%0,%%r22", xoperands);
7758 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
7762 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7767 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7772 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7774 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7777 output_asm_insn (".align 4", xoperands);
7778 ASM_OUTPUT_LABEL (file, label);
7779 output_asm_insn (".word P'%0", xoperands);
7781 else if (TARGET_SOM && TARGET_GAS)
7784 current_thunk_number++;
7785 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7786 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7787 last_address += nbytes;
7788 update_total_code_bytes (nbytes);
7791 /* Only direct calls to static functions are allowed to be sibling (tail)
7794 This restriction is necessary because some linker generated stubs will
7795 store return pointers into rp' in some cases which might clobber a
7796 live value already in rp'.
7798 In a sibcall the current function and the target function share stack
7799 space. Thus if the path to the current function and the path to the
7800 target function save a value in rp', they save the value into the
7801 same stack slot, which has undesirable consequences.
7803 Because of the deferred binding nature of shared libraries any function
7804 with external scope could be in a different load module and thus require
7805 rp' to be saved when calling that function. So sibcall optimizations
7806 can only be safe for static function.
7808 Note that GCC never needs return value relocations, so we don't have to
7809 worry about static calls with return value relocations (which require
7812 It is safe to perform a sibcall optimization when the target function
7813 will never return. */
7815 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7817 if (TARGET_PORTABLE_RUNTIME)
7820 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7821 single subspace mode and the call is not indirect. As far as I know,
7822 there is no operating system support for the multiple subspace mode.
7823 It might be possible to support indirect calls if we didn't use
7824 $$dyncall (see the indirect sequence generated in output_call). */
7826 return (decl != NULL_TREE);
7828 /* Sibcalls are not ok because the arg pointer register is not a fixed
7829 register. This prevents the sibcall optimization from occurring. In
7830 addition, there are problems with stub placement using GNU ld. This
7831 is because a normal sibcall branch uses a 17-bit relocation while
7832 a regular call branch uses a 22-bit relocation. As a result, more
7833 care needs to be taken in the placement of long-branch stubs. */
7837 /* Sibcalls are only ok within a translation unit. */
7838 return (decl && !TREE_PUBLIC (decl));
7841 /* ??? Addition is not commutative on the PA due to the weird implicit
7842 space register selection rules for memory addresses. Therefore, we
7843 don't consider a + b == b + a, as this might be inside a MEM. */
7845 pa_commutative_p (rtx x, int outer_code)
7847 return (COMMUTATIVE_P (x)
7848 && (TARGET_NO_SPACE_REGS
7849 || (outer_code != UNKNOWN && outer_code != MEM)
7850 || GET_CODE (x) != PLUS));
7853 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7854 use in fmpyadd instructions. */
7856 fmpyaddoperands (rtx *operands)
7858 enum machine_mode mode = GET_MODE (operands[0]);
7860 /* Must be a floating point mode. */
7861 if (mode != SFmode && mode != DFmode)
7864 /* All modes must be the same. */
7865 if (! (mode == GET_MODE (operands[1])
7866 && mode == GET_MODE (operands[2])
7867 && mode == GET_MODE (operands[3])
7868 && mode == GET_MODE (operands[4])
7869 && mode == GET_MODE (operands[5])))
7872 /* All operands must be registers. */
7873 if (! (GET_CODE (operands[1]) == REG
7874 && GET_CODE (operands[2]) == REG
7875 && GET_CODE (operands[3]) == REG
7876 && GET_CODE (operands[4]) == REG
7877 && GET_CODE (operands[5]) == REG))
7880 /* Only 2 real operands to the addition. One of the input operands must
7881 be the same as the output operand. */
7882 if (! rtx_equal_p (operands[3], operands[4])
7883 && ! rtx_equal_p (operands[3], operands[5]))
7886 /* Inout operand of add cannot conflict with any operands from multiply. */
7887 if (rtx_equal_p (operands[3], operands[0])
7888 || rtx_equal_p (operands[3], operands[1])
7889 || rtx_equal_p (operands[3], operands[2]))
7892 /* multiply cannot feed into addition operands. */
7893 if (rtx_equal_p (operands[4], operands[0])
7894 || rtx_equal_p (operands[5], operands[0]))
7897 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7899 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7900 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7901 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7902 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7903 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7904 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7907 /* Passed. Operands are suitable for fmpyadd. */
7911 #if !defined(USE_COLLECT2)
7913 pa_asm_out_constructor (rtx symbol, int priority)
7915 if (!function_label_operand (symbol, VOIDmode))
7916 hppa_encode_label (symbol);
7918 #ifdef CTORS_SECTION_ASM_OP
7919 default_ctor_section_asm_out_constructor (symbol, priority);
7921 # ifdef TARGET_ASM_NAMED_SECTION
7922 default_named_section_asm_out_constructor (symbol, priority);
7924 default_stabs_asm_out_constructor (symbol, priority);
7930 pa_asm_out_destructor (rtx symbol, int priority)
7932 if (!function_label_operand (symbol, VOIDmode))
7933 hppa_encode_label (symbol);
7935 #ifdef DTORS_SECTION_ASM_OP
7936 default_dtor_section_asm_out_destructor (symbol, priority);
7938 # ifdef TARGET_ASM_NAMED_SECTION
7939 default_named_section_asm_out_destructor (symbol, priority);
7941 default_stabs_asm_out_destructor (symbol, priority);
7947 /* This function places uninitialized global data in the bss section.
7948 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
7949 function on the SOM port to prevent uninitialized global data from
7950 being placed in the data section. */
7953 pa_asm_output_aligned_bss (FILE *stream,
7955 unsigned HOST_WIDE_INT size,
7959 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7961 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7962 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7965 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7966 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7969 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7970 ASM_OUTPUT_LABEL (stream, name);
7971 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
7974 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
7975 that doesn't allow the alignment of global common storage to be directly
7976 specified. The SOM linker aligns common storage based on the rounded
7977 value of the NUM_BYTES parameter in the .comm directive. It's not
7978 possible to use the .align directive as it doesn't affect the alignment
7979 of the label associated with a .comm directive. */
7982 pa_asm_output_aligned_common (FILE *stream,
7984 unsigned HOST_WIDE_INT size,
7987 unsigned int max_common_align;
7989 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
7990 if (align > max_common_align)
7992 warning (0, "alignment (%u) for %s exceeds maximum alignment "
7993 "for global common data. Using %u",
7994 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
7995 align = max_common_align;
8000 assemble_name (stream, name);
8001 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8002 MAX (size, align / BITS_PER_UNIT));
8005 /* We can't use .comm for local common storage as the SOM linker effectively
8006 treats the symbol as universal and uses the same storage for local symbols
8007 with the same name in different object files. The .block directive
8008 reserves an uninitialized block of storage. However, it's not common
8009 storage. Fortunately, GCC never requests common storage with the same
8010 name in any given translation unit. */
8013 pa_asm_output_aligned_local (FILE *stream,
8015 unsigned HOST_WIDE_INT size,
8019 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8022 fprintf (stream, "%s", LOCAL_ASM_OP);
8023 assemble_name (stream, name);
8024 fprintf (stream, "\n");
8027 ASM_OUTPUT_LABEL (stream, name);
8028 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8031 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8032 use in fmpysub instructions. */
8034 fmpysuboperands (rtx *operands)
8036 enum machine_mode mode = GET_MODE (operands[0]);
8038 /* Must be a floating point mode. */
8039 if (mode != SFmode && mode != DFmode)
8042 /* All modes must be the same. */
8043 if (! (mode == GET_MODE (operands[1])
8044 && mode == GET_MODE (operands[2])
8045 && mode == GET_MODE (operands[3])
8046 && mode == GET_MODE (operands[4])
8047 && mode == GET_MODE (operands[5])))
8050 /* All operands must be registers. */
8051 if (! (GET_CODE (operands[1]) == REG
8052 && GET_CODE (operands[2]) == REG
8053 && GET_CODE (operands[3]) == REG
8054 && GET_CODE (operands[4]) == REG
8055 && GET_CODE (operands[5]) == REG))
8058 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8059 operation, so operands[4] must be the same as operand[3]. */
8060 if (! rtx_equal_p (operands[3], operands[4]))
8063 /* multiply cannot feed into subtraction. */
8064 if (rtx_equal_p (operands[5], operands[0]))
8067 /* Inout operand of sub cannot conflict with any operands from multiply. */
8068 if (rtx_equal_p (operands[3], operands[0])
8069 || rtx_equal_p (operands[3], operands[1])
8070 || rtx_equal_p (operands[3], operands[2]))
8073 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8075 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8076 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8077 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8078 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8079 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8080 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8083 /* Passed. Operands are suitable for fmpysub. */
8087 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8088 constants for shadd instructions. */
8090 shadd_constant_p (int val)
8092 if (val == 2 || val == 4 || val == 8)
8098 /* Return 1 if OP is valid as a base or index register in a
8102 borx_reg_operand (rtx op, enum machine_mode mode)
8104 if (GET_CODE (op) != REG)
8107 /* We must reject virtual registers as the only expressions that
8108 can be instantiated are REG and REG+CONST. */
8109 if (op == virtual_incoming_args_rtx
8110 || op == virtual_stack_vars_rtx
8111 || op == virtual_stack_dynamic_rtx
8112 || op == virtual_outgoing_args_rtx
8113 || op == virtual_cfa_rtx)
8116 /* While it's always safe to index off the frame pointer, it's not
8117 profitable to do so when the frame pointer is being eliminated. */
8118 if (!reload_completed
8119 && flag_omit_frame_pointer
8120 && !current_function_calls_alloca
8121 && op == frame_pointer_rtx)
8124 return register_operand (op, mode);
8127 /* Return 1 if this operand is anything other than a hard register. */
8130 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8132 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8135 /* Return 1 if INSN branches forward. Should be using insn_addresses
8136 to avoid walking through all the insns... */
8138 forward_branch_p (rtx insn)
8140 rtx label = JUMP_LABEL (insn);
8147 insn = NEXT_INSN (insn);
8150 return (insn == label);
8153 /* Return 1 if OP is an equality comparison, else return 0. */
8155 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8157 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8160 /* Return 1 if INSN is in the delay slot of a call instruction. */
8162 jump_in_call_delay (rtx insn)
8165 if (GET_CODE (insn) != JUMP_INSN)
8168 if (PREV_INSN (insn)
8169 && PREV_INSN (PREV_INSN (insn))
8170 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8172 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8174 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8175 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8182 /* Output an unconditional move and branch insn. */
8185 output_parallel_movb (rtx *operands, int length)
8187 /* These are the cases in which we win. */
8189 return "mov%I1b,tr %1,%0,%2";
8191 /* None of these cases wins, but they don't lose either. */
8192 if (dbr_sequence_length () == 0)
8194 /* Nothing in the delay slot, fake it by putting the combined
8195 insn (the copy or add) in the delay slot of a bl. */
8196 if (GET_CODE (operands[1]) == CONST_INT)
8197 return "b %2\n\tldi %1,%0";
8199 return "b %2\n\tcopy %1,%0";
8203 /* Something in the delay slot, but we've got a long branch. */
8204 if (GET_CODE (operands[1]) == CONST_INT)
8205 return "ldi %1,%0\n\tb %2";
8207 return "copy %1,%0\n\tb %2";
8211 /* Output an unconditional add and branch insn. */
8214 output_parallel_addb (rtx *operands, int length)
8216 /* To make life easy we want operand0 to be the shared input/output
8217 operand and operand1 to be the readonly operand. */
8218 if (operands[0] == operands[1])
8219 operands[1] = operands[2];
8221 /* These are the cases in which we win. */
8223 return "add%I1b,tr %1,%0,%3";
8225 /* None of these cases win, but they don't lose either. */
8226 if (dbr_sequence_length () == 0)
8228 /* Nothing in the delay slot, fake it by putting the combined
8229 insn (the copy or add) in the delay slot of a bl. */
8230 return "b %3\n\tadd%I1 %1,%0,%0";
8234 /* Something in the delay slot, but we've got a long branch. */
8235 return "add%I1 %1,%0,%0\n\tb %3";
8239 /* Return nonzero if INSN (a jump insn) immediately follows a call
8240 to a named function. This is used to avoid filling the delay slot
8241 of the jump since it can usually be eliminated by modifying RP in
8242 the delay slot of the call. */
8245 following_call (rtx insn)
8247 if (! TARGET_JUMP_IN_DELAY)
8250 /* Find the previous real insn, skipping NOTEs. */
8251 insn = PREV_INSN (insn);
8252 while (insn && GET_CODE (insn) == NOTE)
8253 insn = PREV_INSN (insn);
8255 /* Check for CALL_INSNs and millicode calls. */
8257 && ((GET_CODE (insn) == CALL_INSN
8258 && get_attr_type (insn) != TYPE_DYNCALL)
8259 || (GET_CODE (insn) == INSN
8260 && GET_CODE (PATTERN (insn)) != SEQUENCE
8261 && GET_CODE (PATTERN (insn)) != USE
8262 && GET_CODE (PATTERN (insn)) != CLOBBER
8263 && get_attr_type (insn) == TYPE_MILLI)))
8269 /* We use this hook to perform a PA specific optimization which is difficult
8270 to do in earlier passes.
8272 We want the delay slots of branches within jump tables to be filled.
8273 None of the compiler passes at the moment even has the notion that a
8274 PA jump table doesn't contain addresses, but instead contains actual
8277 Because we actually jump into the table, the addresses of each entry
8278 must stay constant in relation to the beginning of the table (which
8279 itself must stay constant relative to the instruction to jump into
8280 it). I don't believe we can guarantee earlier passes of the compiler
8281 will adhere to those rules.
8283 So, late in the compilation process we find all the jump tables, and
8284 expand them into real code -- e.g. each entry in the jump table vector
8285 will get an appropriate label followed by a jump to the final target.
8287 Reorg and the final jump pass can then optimize these branches and
8288 fill their delay slots. We end up with smaller, more efficient code.
8290 The jump instructions within the table are special; we must be able
8291 to identify them during assembly output (if the jumps don't get filled
8292 we need to emit a nop rather than nullifying the delay slot)). We
8293 identify jumps in switch tables by using insns with the attribute
8294 type TYPE_BTABLE_BRANCH.
8296 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8297 insns. This serves two purposes, first it prevents jump.c from
8298 noticing that the last N entries in the table jump to the instruction
8299 immediately after the table and deleting the jumps. Second, those
8300 insns mark where we should emit .begin_brtab and .end_brtab directives
8301 when using GAS (allows for better link time optimizations). */
8308 remove_useless_addtr_insns (1);
8310 if (pa_cpu < PROCESSOR_8000)
8311 pa_combine_instructions ();
8314 /* This is fairly cheap, so always run it if optimizing. */
8315 if (optimize > 0 && !TARGET_BIG_SWITCH)
8317 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8318 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8320 rtx pattern, tmp, location, label;
8321 unsigned int length, i;
8323 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8324 if (GET_CODE (insn) != JUMP_INSN
8325 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8326 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8329 /* Emit marker for the beginning of the branch table. */
8330 emit_insn_before (gen_begin_brtab (), insn);
8332 pattern = PATTERN (insn);
8333 location = PREV_INSN (insn);
8334 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8336 for (i = 0; i < length; i++)
8338 /* Emit a label before each jump to keep jump.c from
8339 removing this code. */
8340 tmp = gen_label_rtx ();
8341 LABEL_NUSES (tmp) = 1;
8342 emit_label_after (tmp, location);
8343 location = NEXT_INSN (location);
8345 if (GET_CODE (pattern) == ADDR_VEC)
8346 label = XEXP (XVECEXP (pattern, 0, i), 0);
8348 label = XEXP (XVECEXP (pattern, 1, i), 0);
8350 tmp = gen_short_jump (label);
8352 /* Emit the jump itself. */
8353 tmp = emit_jump_insn_after (tmp, location);
8354 JUMP_LABEL (tmp) = label;
8355 LABEL_NUSES (label)++;
8356 location = NEXT_INSN (location);
8358 /* Emit a BARRIER after the jump. */
8359 emit_barrier_after (location);
8360 location = NEXT_INSN (location);
8363 /* Emit marker for the end of the branch table. */
8364 emit_insn_before (gen_end_brtab (), location);
8365 location = NEXT_INSN (location);
8366 emit_barrier_after (location);
8368 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8374 /* Still need brtab marker insns. FIXME: the presence of these
8375 markers disables output of the branch table to readonly memory,
8376 and any alignment directives that might be needed. Possibly,
8377 the begin_brtab insn should be output before the label for the
8378 table. This doesn't matter at the moment since the tables are
8379 always output in the text section. */
8380 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8382 /* Find an ADDR_VEC insn. */
8383 if (GET_CODE (insn) != JUMP_INSN
8384 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8385 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8388 /* Now generate markers for the beginning and end of the
8390 emit_insn_before (gen_begin_brtab (), insn);
8391 emit_insn_after (gen_end_brtab (), insn);
8396 /* The PA has a number of odd instructions which can perform multiple
8397 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8398 it may be profitable to combine two instructions into one instruction
8399 with two outputs. It's not profitable PA2.0 machines because the
8400 two outputs would take two slots in the reorder buffers.
8402 This routine finds instructions which can be combined and combines
8403 them. We only support some of the potential combinations, and we
8404 only try common ways to find suitable instructions.
8406 * addb can add two registers or a register and a small integer
8407 and jump to a nearby (+-8k) location. Normally the jump to the
8408 nearby location is conditional on the result of the add, but by
8409 using the "true" condition we can make the jump unconditional.
8410 Thus addb can perform two independent operations in one insn.
8412 * movb is similar to addb in that it can perform a reg->reg
8413 or small immediate->reg copy and jump to a nearby (+-8k location).
8415 * fmpyadd and fmpysub can perform a FP multiply and either an
8416 FP add or FP sub if the operands of the multiply and add/sub are
8417 independent (there are other minor restrictions). Note both
8418 the fmpy and fadd/fsub can in theory move to better spots according
8419 to data dependencies, but for now we require the fmpy stay at a
8422 * Many of the memory operations can perform pre & post updates
8423 of index registers. GCC's pre/post increment/decrement addressing
8424 is far too simple to take advantage of all the possibilities. This
8425 pass may not be suitable since those insns may not be independent.
8427 * comclr can compare two ints or an int and a register, nullify
8428 the following instruction and zero some other register. This
8429 is more difficult to use as it's harder to find an insn which
8430 will generate a comclr than finding something like an unconditional
8431 branch. (conditional moves & long branches create comclr insns).
8433 * Most arithmetic operations can conditionally skip the next
8434 instruction. They can be viewed as "perform this operation
8435 and conditionally jump to this nearby location" (where nearby
8436 is an insns away). These are difficult to use due to the
8437 branch length restrictions. */
8440 pa_combine_instructions (void)
8444 /* This can get expensive since the basic algorithm is on the
8445 order of O(n^2) (or worse). Only do it for -O2 or higher
8446 levels of optimization. */
8450 /* Walk down the list of insns looking for "anchor" insns which
8451 may be combined with "floating" insns. As the name implies,
8452 "anchor" instructions don't move, while "floating" insns may
8454 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8455 new = make_insn_raw (new);
8457 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8459 enum attr_pa_combine_type anchor_attr;
8460 enum attr_pa_combine_type floater_attr;
8462 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8463 Also ignore any special USE insns. */
8464 if ((GET_CODE (anchor) != INSN
8465 && GET_CODE (anchor) != JUMP_INSN
8466 && GET_CODE (anchor) != CALL_INSN)
8467 || GET_CODE (PATTERN (anchor)) == USE
8468 || GET_CODE (PATTERN (anchor)) == CLOBBER
8469 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8470 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8473 anchor_attr = get_attr_pa_combine_type (anchor);
8474 /* See if anchor is an insn suitable for combination. */
8475 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8476 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8477 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8478 && ! forward_branch_p (anchor)))
8482 for (floater = PREV_INSN (anchor);
8484 floater = PREV_INSN (floater))
8486 if (GET_CODE (floater) == NOTE
8487 || (GET_CODE (floater) == INSN
8488 && (GET_CODE (PATTERN (floater)) == USE
8489 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8492 /* Anything except a regular INSN will stop our search. */
8493 if (GET_CODE (floater) != INSN
8494 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8495 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8501 /* See if FLOATER is suitable for combination with the
8503 floater_attr = get_attr_pa_combine_type (floater);
8504 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8505 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8506 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8507 && floater_attr == PA_COMBINE_TYPE_FMPY))
8509 /* If ANCHOR and FLOATER can be combined, then we're
8510 done with this pass. */
8511 if (pa_can_combine_p (new, anchor, floater, 0,
8512 SET_DEST (PATTERN (floater)),
8513 XEXP (SET_SRC (PATTERN (floater)), 0),
8514 XEXP (SET_SRC (PATTERN (floater)), 1)))
8518 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8519 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8521 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8523 if (pa_can_combine_p (new, anchor, floater, 0,
8524 SET_DEST (PATTERN (floater)),
8525 XEXP (SET_SRC (PATTERN (floater)), 0),
8526 XEXP (SET_SRC (PATTERN (floater)), 1)))
8531 if (pa_can_combine_p (new, anchor, floater, 0,
8532 SET_DEST (PATTERN (floater)),
8533 SET_SRC (PATTERN (floater)),
8534 SET_SRC (PATTERN (floater))))
8540 /* If we didn't find anything on the backwards scan try forwards. */
8542 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8543 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8545 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8547 if (GET_CODE (floater) == NOTE
8548 || (GET_CODE (floater) == INSN
8549 && (GET_CODE (PATTERN (floater)) == USE
8550 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8554 /* Anything except a regular INSN will stop our search. */
8555 if (GET_CODE (floater) != INSN
8556 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8557 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8563 /* See if FLOATER is suitable for combination with the
8565 floater_attr = get_attr_pa_combine_type (floater);
8566 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8567 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8568 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8569 && floater_attr == PA_COMBINE_TYPE_FMPY))
8571 /* If ANCHOR and FLOATER can be combined, then we're
8572 done with this pass. */
8573 if (pa_can_combine_p (new, anchor, floater, 1,
8574 SET_DEST (PATTERN (floater)),
8575 XEXP (SET_SRC (PATTERN (floater)),
8577 XEXP (SET_SRC (PATTERN (floater)),
8584 /* FLOATER will be nonzero if we found a suitable floating
8585 insn for combination with ANCHOR. */
8587 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8588 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8590 /* Emit the new instruction and delete the old anchor. */
8591 emit_insn_before (gen_rtx_PARALLEL
8593 gen_rtvec (2, PATTERN (anchor),
8594 PATTERN (floater))),
8597 PUT_CODE (anchor, NOTE);
8598 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8599 NOTE_SOURCE_FILE (anchor) = 0;
8601 /* Emit a special USE insn for FLOATER, then delete
8602 the floating insn. */
8603 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8604 delete_insn (floater);
8609 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8612 /* Emit the new_jump instruction and delete the old anchor. */
8614 = emit_jump_insn_before (gen_rtx_PARALLEL
8616 gen_rtvec (2, PATTERN (anchor),
8617 PATTERN (floater))),
8620 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8621 PUT_CODE (anchor, NOTE);
8622 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8623 NOTE_SOURCE_FILE (anchor) = 0;
8625 /* Emit a special USE insn for FLOATER, then delete
8626 the floating insn. */
8627 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8628 delete_insn (floater);
8636 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8639 int insn_code_number;
8642 /* Create a PARALLEL with the patterns of ANCHOR and
8643 FLOATER, try to recognize it, then test constraints
8644 for the resulting pattern.
8646 If the pattern doesn't match or the constraints
8647 aren't met keep searching for a suitable floater
8649 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8650 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8651 INSN_CODE (new) = -1;
8652 insn_code_number = recog_memoized (new);
8653 if (insn_code_number < 0
8654 || (extract_insn (new), ! constrain_operands (1)))
8668 /* There's up to three operands to consider. One
8669 output and two inputs.
8671 The output must not be used between FLOATER & ANCHOR
8672 exclusive. The inputs must not be set between
8673 FLOATER and ANCHOR exclusive. */
8675 if (reg_used_between_p (dest, start, end))
8678 if (reg_set_between_p (src1, start, end))
8681 if (reg_set_between_p (src2, start, end))
8684 /* If we get here, then everything is good. */
8688 /* Return nonzero if references for INSN are delayed.
8690 Millicode insns are actually function calls with some special
8691 constraints on arguments and register usage.
8693 Millicode calls always expect their arguments in the integer argument
8694 registers, and always return their result in %r29 (ret1). They
8695 are expected to clobber their arguments, %r1, %r29, and the return
8696 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8698 This function tells reorg that the references to arguments and
8699 millicode calls do not appear to happen until after the millicode call.
8700 This allows reorg to put insns which set the argument registers into the
8701 delay slot of the millicode call -- thus they act more like traditional
8704 Note we cannot consider side effects of the insn to be delayed because
8705 the branch and link insn will clobber the return pointer. If we happened
8706 to use the return pointer in the delay slot of the call, then we lose.
8708 get_attr_type will try to recognize the given insn, so make sure to
8709 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8712 insn_refs_are_delayed (rtx insn)
8714 return ((GET_CODE (insn) == INSN
8715 && GET_CODE (PATTERN (insn)) != SEQUENCE
8716 && GET_CODE (PATTERN (insn)) != USE
8717 && GET_CODE (PATTERN (insn)) != CLOBBER
8718 && get_attr_type (insn) == TYPE_MILLI));
8721 /* On the HP-PA the value is found in register(s) 28(-29), unless
8722 the mode is SF or DF. Then the value is returned in fr4 (32).
8724 This must perform the same promotions as PROMOTE_MODE, else
8725 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8727 Small structures must be returned in a PARALLEL on PA64 in order
8728 to match the HP Compiler ABI. */
8731 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8733 enum machine_mode valmode;
8735 if (AGGREGATE_TYPE_P (valtype))
8739 /* Aggregates with a size less than or equal to 128 bits are
8740 returned in GR 28(-29). They are left justified. The pad
8741 bits are undefined. Larger aggregates are returned in
8745 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8747 for (i = 0; i < ub; i++)
8749 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8750 gen_rtx_REG (DImode, 28 + i),
8755 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8757 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
8759 /* Aggregates 5 to 8 bytes in size are returned in general
8760 registers r28-r29 in the same manner as other non
8761 floating-point objects. The data is right-justified and
8762 zero-extended to 64 bits. This is opposite to the normal
8763 justification used on big endian targets and requires
8764 special treatment. */
8765 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8766 gen_rtx_REG (DImode, 28), const0_rtx);
8767 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
8771 if ((INTEGRAL_TYPE_P (valtype)
8772 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8773 || POINTER_TYPE_P (valtype))
8774 valmode = word_mode;
8776 valmode = TYPE_MODE (valtype);
8778 if (TREE_CODE (valtype) == REAL_TYPE
8779 && !AGGREGATE_TYPE_P (valtype)
8780 && TYPE_MODE (valtype) != TFmode
8781 && !TARGET_SOFT_FLOAT)
8782 return gen_rtx_REG (valmode, 32);
8784 return gen_rtx_REG (valmode, 28);
8787 /* Return the location of a parameter that is passed in a register or NULL
8788 if the parameter has any component that is passed in memory.
8790 This is new code and will be pushed to into the net sources after
8793 ??? We might want to restructure this so that it looks more like other
8796 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8797 int named ATTRIBUTE_UNUSED)
8799 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8806 if (mode == VOIDmode)
8809 arg_size = FUNCTION_ARG_SIZE (mode, type);
8811 /* If this arg would be passed partially or totally on the stack, then
8812 this routine should return zero. pa_arg_partial_bytes will
8813 handle arguments which are split between regs and stack slots if
8814 the ABI mandates split arguments. */
8817 /* The 32-bit ABI does not split arguments. */
8818 if (cum->words + arg_size > max_arg_words)
8824 alignment = cum->words & 1;
8825 if (cum->words + alignment >= max_arg_words)
8829 /* The 32bit ABIs and the 64bit ABIs are rather different,
8830 particularly in their handling of FP registers. We might
8831 be able to cleverly share code between them, but I'm not
8832 going to bother in the hope that splitting them up results
8833 in code that is more easily understood. */
8837 /* Advance the base registers to their current locations.
8839 Remember, gprs grow towards smaller register numbers while
8840 fprs grow to higher register numbers. Also remember that
8841 although FP regs are 32-bit addressable, we pretend that
8842 the registers are 64-bits wide. */
8843 gpr_reg_base = 26 - cum->words;
8844 fpr_reg_base = 32 + cum->words;
8846 /* Arguments wider than one word and small aggregates need special
8850 || (type && AGGREGATE_TYPE_P (type)))
8852 /* Double-extended precision (80-bit), quad-precision (128-bit)
8853 and aggregates including complex numbers are aligned on
8854 128-bit boundaries. The first eight 64-bit argument slots
8855 are associated one-to-one, with general registers r26
8856 through r19, and also with floating-point registers fr4
8857 through fr11. Arguments larger than one word are always
8858 passed in general registers.
8860 Using a PARALLEL with a word mode register results in left
8861 justified data on a big-endian target. */
8864 int i, offset = 0, ub = arg_size;
8866 /* Align the base register. */
8867 gpr_reg_base -= alignment;
8869 ub = MIN (ub, max_arg_words - cum->words - alignment);
8870 for (i = 0; i < ub; i++)
8872 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8873 gen_rtx_REG (DImode, gpr_reg_base),
8879 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8884 /* If the argument is larger than a word, then we know precisely
8885 which registers we must use. */
8899 /* Structures 5 to 8 bytes in size are passed in the general
8900 registers in the same manner as other non floating-point
8901 objects. The data is right-justified and zero-extended
8902 to 64 bits. This is opposite to the normal justification
8903 used on big endian targets and requires special treatment.
8904 We now define BLOCK_REG_PADDING to pad these objects. */
8905 if (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
8907 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8908 gen_rtx_REG (DImode, gpr_reg_base),
8910 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
8915 /* We have a single word (32 bits). A simple computation
8916 will get us the register #s we need. */
8917 gpr_reg_base = 26 - cum->words;
8918 fpr_reg_base = 32 + 2 * cum->words;
8922 /* Determine if the argument needs to be passed in both general and
8923 floating point registers. */
8924 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8925 /* If we are doing soft-float with portable runtime, then there
8926 is no need to worry about FP regs. */
8927 && !TARGET_SOFT_FLOAT
8928 /* The parameter must be some kind of float, else we can just
8929 pass it in integer registers. */
8930 && FLOAT_MODE_P (mode)
8931 /* The target function must not have a prototype. */
8932 && cum->nargs_prototype <= 0
8933 /* libcalls do not need to pass items in both FP and general
8935 && type != NULL_TREE
8936 /* All this hair applies to "outgoing" args only. This includes
8937 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8939 /* Also pass outgoing floating arguments in both registers in indirect
8940 calls with the 32 bit ABI and the HP assembler since there is no
8941 way to the specify argument locations in static functions. */
8946 && FLOAT_MODE_P (mode)))
8952 gen_rtx_EXPR_LIST (VOIDmode,
8953 gen_rtx_REG (mode, fpr_reg_base),
8955 gen_rtx_EXPR_LIST (VOIDmode,
8956 gen_rtx_REG (mode, gpr_reg_base),
8961 /* See if we should pass this parameter in a general register. */
8962 if (TARGET_SOFT_FLOAT
8963 /* Indirect calls in the normal 32bit ABI require all arguments
8964 to be passed in general registers. */
8965 || (!TARGET_PORTABLE_RUNTIME
8969 /* If the parameter is not a floating point parameter, then
8970 it belongs in GPRs. */
8971 || !FLOAT_MODE_P (mode)
8972 /* Structure with single SFmode field belongs in GPR. */
8973 || (type && AGGREGATE_TYPE_P (type)))
8974 retval = gen_rtx_REG (mode, gpr_reg_base);
8976 retval = gen_rtx_REG (mode, fpr_reg_base);
8982 /* If this arg would be passed totally in registers or totally on the stack,
8983 then this routine should return zero. */
8986 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8987 tree type, bool named ATTRIBUTE_UNUSED)
8989 unsigned int max_arg_words = 8;
8990 unsigned int offset = 0;
8995 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8998 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8999 /* Arg fits fully into registers. */
9001 else if (cum->words + offset >= max_arg_words)
9002 /* Arg fully on the stack. */
9006 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9010 /* Return a string to output before text in the current function.
9012 This function is only used with SOM. Because we don't support
9013 named subspaces, we can only create a new subspace or switch back
9014 to the default text subspace. */
9016 som_text_section_asm_op (void)
9023 if (cfun && !cfun->machine->in_nsubspa)
9025 /* We only want to emit a .nsubspa directive once at the
9026 start of the function. */
9027 cfun->machine->in_nsubspa = 1;
9029 /* Create a new subspace for the text. This provides
9030 better stub placement and one-only functions. */
9032 && DECL_ONE_ONLY (cfun->decl)
9033 && !DECL_WEAK (cfun->decl))
9035 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
9037 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
9041 /* There isn't a current function or the body of the current
9042 function has been completed. So, we are changing to the
9043 text section to output debugging information. Do this in
9044 the default text section. We need to forget that we are
9045 in the text section so that the function text_section in
9046 varasm.c will call us the next time around. */
9051 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
9054 /* On hpux10, the linker will give an error if we have a reference
9055 in the read-only data section to a symbol defined in a shared
9056 library. Therefore, expressions that might require a reloc can
9057 not be placed in the read-only data section. */
9060 pa_select_section (tree exp, int reloc,
9061 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9063 if (TREE_CODE (exp) == VAR_DECL
9064 && TREE_READONLY (exp)
9065 && !TREE_THIS_VOLATILE (exp)
9066 && DECL_INITIAL (exp)
9067 && (DECL_INITIAL (exp) == error_mark_node
9068 || TREE_CONSTANT (DECL_INITIAL (exp)))
9072 && DECL_ONE_ONLY (exp)
9073 && !DECL_WEAK (exp))
9074 som_one_only_readonly_data_section ();
9076 readonly_data_section ();
9078 else if (CONSTANT_CLASS_P (exp) && !reloc)
9079 readonly_data_section ();
9081 && TREE_CODE (exp) == VAR_DECL
9082 && DECL_ONE_ONLY (exp)
9083 && !DECL_WEAK (exp))
9084 som_one_only_data_section ();
9090 pa_globalize_label (FILE *stream, const char *name)
9092 /* We only handle DATA objects here, functions are globalized in
9093 ASM_DECLARE_FUNCTION_NAME. */
9094 if (! FUNCTION_NAME_P (name))
9096 fputs ("\t.EXPORT ", stream);
9097 assemble_name (stream, name);
9098 fputs (",DATA\n", stream);
9102 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9105 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9106 int incoming ATTRIBUTE_UNUSED)
9108 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9111 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9114 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9116 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9117 PA64 ABI says that objects larger than 128 bits are returned in memory.
9118 Note, int_size_in_bytes can return -1 if the size of the object is
9119 variable or larger than the maximum value that can be expressed as
9120 a HOST_WIDE_INT. It can also return zero for an empty type. The
9121 simplest way to handle variable and empty types is to pass them in
9122 memory. This avoids problems in defining the boundaries of argument
9123 slots, allocating registers, etc. */
9124 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9125 || int_size_in_bytes (type) <= 0);
9128 /* Structure to hold declaration and name of external symbols that are
9129 emitted by GCC. We generate a vector of these symbols and output them
9130 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9131 This avoids putting out names that are never really used. */
9133 typedef struct extern_symbol GTY(())
9139 /* Define gc'd vector type for extern_symbol. */
9140 DEF_VEC_O(extern_symbol);
9141 DEF_VEC_ALLOC_O(extern_symbol,gc);
9143 /* Vector of extern_symbol pointers. */
9144 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9146 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9147 /* Mark DECL (name NAME) as an external reference (assembler output
9148 file FILE). This saves the names to output at the end of the file
9149 if actually referenced. */
9152 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9154 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9156 gcc_assert (file == asm_out_file);
9161 /* Output text required at the end of an assembler file.
9162 This includes deferred plabels and .import directives for
9163 all external symbols that were actually referenced. */
9166 pa_hpux_file_end (void)
9171 if (!NO_DEFERRED_PROFILE_COUNTERS)
9172 output_deferred_profile_counters ();
9174 output_deferred_plabels ();
9176 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9178 tree decl = p->decl;
9180 if (!TREE_ASM_WRITTEN (decl)
9181 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9182 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9185 VEC_free (extern_symbol, gc, extern_symbols);