1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
48 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || (get_attr_type (in_insn) != TYPE_FPSTORE
62 && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD)
63 || recog_memoized (out_insn) < 0)
66 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
68 set = single_set (out_insn);
72 other_mode = GET_MODE (SET_SRC (set));
74 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
78 #ifndef DO_FRAME_NOTES
79 #ifdef INCOMING_RETURN_ADDR_RTX
80 #define DO_FRAME_NOTES 1
82 #define DO_FRAME_NOTES 0
86 static void copy_reg_pointer (rtx, rtx);
87 static void fix_range (const char *);
88 static bool pa_handle_option (size_t, const char *, int);
89 static int hppa_address_cost (rtx);
90 static bool hppa_rtx_costs (rtx, int, int, int *);
91 static inline rtx force_mode (enum machine_mode, rtx);
92 static void pa_reorg (void);
93 static void pa_combine_instructions (void);
94 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
95 static int forward_branch_p (rtx);
96 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
97 static int compute_movmem_length (rtx);
98 static int compute_clrmem_length (rtx);
99 static bool pa_assemble_integer (rtx, unsigned int, int);
100 static void remove_useless_addtr_insns (int);
101 static void store_reg (int, HOST_WIDE_INT, int);
102 static void store_reg_modify (int, int, HOST_WIDE_INT);
103 static void load_reg (int, HOST_WIDE_INT, int);
104 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
105 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
106 static void update_total_code_bytes (int);
107 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
108 static int pa_adjust_cost (rtx, rtx, rtx, int);
109 static int pa_adjust_priority (rtx, int);
110 static int pa_issue_rate (void);
111 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
112 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
114 static void pa_encode_section_info (tree, rtx, int);
115 static const char *pa_strip_name_encoding (const char *);
116 static bool pa_function_ok_for_sibcall (tree, tree);
117 static void pa_globalize_label (FILE *, const char *)
119 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
120 HOST_WIDE_INT, tree);
121 #if !defined(USE_COLLECT2)
122 static void pa_asm_out_constructor (rtx, int);
123 static void pa_asm_out_destructor (rtx, int);
125 static void pa_init_builtins (void);
126 static rtx hppa_builtin_saveregs (void);
127 static void hppa_va_start (tree, rtx);
128 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
129 static bool pa_scalar_mode_supported_p (enum machine_mode);
130 static bool pa_commutative_p (const_rtx x, int outer_code);
131 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
132 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
134 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
135 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
136 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
137 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
139 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
140 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
141 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
142 static void output_deferred_plabels (void);
143 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
144 #ifdef ASM_OUTPUT_EXTERNAL_REAL
145 static void pa_hpux_file_end (void);
147 #ifdef HPUX_LONG_DOUBLE_LIBRARY
148 static void pa_hpux_init_libfuncs (void);
150 static rtx pa_struct_value_rtx (tree, int);
151 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
153 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
155 static struct machine_function * pa_init_machine_status (void);
156 static enum reg_class pa_secondary_reload (bool, rtx, enum reg_class,
158 secondary_reload_info *);
159 static void pa_extra_live_on_entry (bitmap);
161 /* The following extra sections are only used for SOM. */
162 static GTY(()) section *som_readonly_data_section;
163 static GTY(()) section *som_one_only_readonly_data_section;
164 static GTY(()) section *som_one_only_data_section;
166 /* Save the operands last given to a compare for use when we
167 generate a scc or bcc insn. */
168 rtx hppa_compare_op0, hppa_compare_op1;
169 enum cmp_type hppa_branch_type;
171 /* Which cpu we are scheduling for. */
172 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
174 /* The UNIX standard to use for predefines and linking. */
175 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
177 /* Counts for the number of callee-saved general and floating point
178 registers which were saved by the current function's prologue. */
179 static int gr_saved, fr_saved;
181 /* Boolean indicating whether the return pointer was saved by the
182 current function's prologue. */
183 static bool rp_saved;
185 static rtx find_addr_reg (rtx);
187 /* Keep track of the number of bytes we have output in the CODE subspace
188 during this compilation so we'll know when to emit inline long-calls. */
189 unsigned long total_code_bytes;
191 /* The last address of the previous function plus the number of bytes in
192 associated thunks that have been output. This is used to determine if
193 a thunk can use an IA-relative branch to reach its target function. */
194 static int last_address;
196 /* Variables to handle plabels that we discover are necessary at assembly
197 output time. They are output after the current function. */
198 struct deferred_plabel GTY(())
203 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
205 static size_t n_deferred_plabels = 0;
208 /* Initialize the GCC target structure. */
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
212 #undef TARGET_ASM_ALIGNED_SI_OP
213 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
214 #undef TARGET_ASM_ALIGNED_DI_OP
215 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
216 #undef TARGET_ASM_UNALIGNED_HI_OP
217 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
218 #undef TARGET_ASM_UNALIGNED_SI_OP
219 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
220 #undef TARGET_ASM_UNALIGNED_DI_OP
221 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
222 #undef TARGET_ASM_INTEGER
223 #define TARGET_ASM_INTEGER pa_assemble_integer
225 #undef TARGET_ASM_FUNCTION_PROLOGUE
226 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
227 #undef TARGET_ASM_FUNCTION_EPILOGUE
228 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
230 #undef TARGET_SCHED_ADJUST_COST
231 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
232 #undef TARGET_SCHED_ADJUST_PRIORITY
233 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
234 #undef TARGET_SCHED_ISSUE_RATE
235 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
237 #undef TARGET_ENCODE_SECTION_INFO
238 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
239 #undef TARGET_STRIP_NAME_ENCODING
240 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
242 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
243 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
245 #undef TARGET_COMMUTATIVE_P
246 #define TARGET_COMMUTATIVE_P pa_commutative_p
248 #undef TARGET_ASM_OUTPUT_MI_THUNK
249 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
250 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
251 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
253 #undef TARGET_ASM_FILE_END
254 #ifdef ASM_OUTPUT_EXTERNAL_REAL
255 #define TARGET_ASM_FILE_END pa_hpux_file_end
257 #define TARGET_ASM_FILE_END output_deferred_plabels
260 #if !defined(USE_COLLECT2)
261 #undef TARGET_ASM_CONSTRUCTOR
262 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
263 #undef TARGET_ASM_DESTRUCTOR
264 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
267 #undef TARGET_DEFAULT_TARGET_FLAGS
268 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
269 #undef TARGET_HANDLE_OPTION
270 #define TARGET_HANDLE_OPTION pa_handle_option
272 #undef TARGET_INIT_BUILTINS
273 #define TARGET_INIT_BUILTINS pa_init_builtins
275 #undef TARGET_RTX_COSTS
276 #define TARGET_RTX_COSTS hppa_rtx_costs
277 #undef TARGET_ADDRESS_COST
278 #define TARGET_ADDRESS_COST hppa_address_cost
280 #undef TARGET_MACHINE_DEPENDENT_REORG
281 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
283 #ifdef HPUX_LONG_DOUBLE_LIBRARY
284 #undef TARGET_INIT_LIBFUNCS
285 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
288 #undef TARGET_PROMOTE_FUNCTION_RETURN
289 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
290 #undef TARGET_PROMOTE_PROTOTYPES
291 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
293 #undef TARGET_STRUCT_VALUE_RTX
294 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
295 #undef TARGET_RETURN_IN_MEMORY
296 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
297 #undef TARGET_MUST_PASS_IN_STACK
298 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
299 #undef TARGET_PASS_BY_REFERENCE
300 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
301 #undef TARGET_CALLEE_COPIES
302 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
303 #undef TARGET_ARG_PARTIAL_BYTES
304 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
306 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
307 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
308 #undef TARGET_EXPAND_BUILTIN_VA_START
309 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
310 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
311 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
313 #undef TARGET_SCALAR_MODE_SUPPORTED_P
314 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
316 #undef TARGET_CANNOT_FORCE_CONST_MEM
317 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
319 #undef TARGET_SECONDARY_RELOAD
320 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
322 #undef TARGET_EXTRA_LIVE_ON_ENTRY
323 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
325 struct gcc_target targetm = TARGET_INITIALIZER;
327 /* Parse the -mfixed-range= option string. */
330 fix_range (const char *const_str)
333 char *str, *dash, *comma;
335 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
336 REG2 are either register names or register numbers. The effect
337 of this option is to mark the registers in the range from REG1 to
338 REG2 as ``fixed'' so they won't be used by the compiler. This is
339 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
341 i = strlen (const_str);
342 str = (char *) alloca (i + 1);
343 memcpy (str, const_str, i + 1);
347 dash = strchr (str, '-');
350 warning (0, "value of -mfixed-range must have form REG1-REG2");
355 comma = strchr (dash + 1, ',');
359 first = decode_reg_name (str);
362 warning (0, "unknown register name: %s", str);
366 last = decode_reg_name (dash + 1);
369 warning (0, "unknown register name: %s", dash + 1);
377 warning (0, "%s-%s is an empty range", str, dash + 1);
381 for (i = first; i <= last; ++i)
382 fixed_regs[i] = call_used_regs[i] = 1;
391 /* Check if all floating point registers have been fixed. */
392 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
397 target_flags |= MASK_DISABLE_FPREGS;
400 /* Implement TARGET_HANDLE_OPTION. */
403 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
408 case OPT_mpa_risc_1_0:
410 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
414 case OPT_mpa_risc_1_1:
416 target_flags &= ~MASK_PA_20;
417 target_flags |= MASK_PA_11;
420 case OPT_mpa_risc_2_0:
422 target_flags |= MASK_PA_11 | MASK_PA_20;
426 if (strcmp (arg, "8000") == 0)
427 pa_cpu = PROCESSOR_8000;
428 else if (strcmp (arg, "7100") == 0)
429 pa_cpu = PROCESSOR_7100;
430 else if (strcmp (arg, "700") == 0)
431 pa_cpu = PROCESSOR_700;
432 else if (strcmp (arg, "7100LC") == 0)
433 pa_cpu = PROCESSOR_7100LC;
434 else if (strcmp (arg, "7200") == 0)
435 pa_cpu = PROCESSOR_7200;
436 else if (strcmp (arg, "7300") == 0)
437 pa_cpu = PROCESSOR_7300;
442 case OPT_mfixed_range_:
452 #if TARGET_HPUX_10_10
458 #if TARGET_HPUX_11_11
470 override_options (void)
472 /* Unconditional branches in the delay slot are not compatible with dwarf2
473 call frame information. There is no benefit in using this optimization
474 on PA8000 and later processors. */
475 if (pa_cpu >= PROCESSOR_8000
476 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
477 || flag_unwind_tables)
478 target_flags &= ~MASK_JUMP_IN_DELAY;
480 if (flag_pic && TARGET_PORTABLE_RUNTIME)
482 warning (0, "PIC code generation is not supported in the portable runtime model");
485 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
487 warning (0, "PIC code generation is not compatible with fast indirect calls");
490 if (! TARGET_GAS && write_symbols != NO_DEBUG)
492 warning (0, "-g is only supported when using GAS on this processor,");
493 warning (0, "-g option disabled");
494 write_symbols = NO_DEBUG;
497 /* We only support the "big PIC" model now. And we always generate PIC
498 code when in 64bit mode. */
499 if (flag_pic == 1 || TARGET_64BIT)
502 /* We can't guarantee that .dword is available for 32-bit targets. */
503 if (UNITS_PER_WORD == 4)
504 targetm.asm_out.aligned_op.di = NULL;
506 /* The unaligned ops are only available when using GAS. */
509 targetm.asm_out.unaligned_op.hi = NULL;
510 targetm.asm_out.unaligned_op.si = NULL;
511 targetm.asm_out.unaligned_op.di = NULL;
514 init_machine_status = pa_init_machine_status;
518 pa_init_builtins (void)
520 #ifdef DONT_HAVE_FPUTC_UNLOCKED
521 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] =
522 built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
523 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED]
524 = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
527 if (built_in_decls [BUILT_IN_FINITE])
528 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE], "_Isfinite");
529 if (built_in_decls [BUILT_IN_FINITEF])
530 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF], "_Isfinitef");
534 /* Function to init struct machine_function.
535 This will be called, via a pointer variable,
536 from push_function_context. */
538 static struct machine_function *
539 pa_init_machine_status (void)
541 return ggc_alloc_cleared (sizeof (machine_function));
544 /* If FROM is a probable pointer register, mark TO as a probable
545 pointer register with the same pointer alignment as FROM. */
548 copy_reg_pointer (rtx to, rtx from)
550 if (REG_POINTER (from))
551 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
554 /* Return 1 if X contains a symbolic expression. We know these
555 expressions will have one of a few well defined forms, so
556 we need only check those forms. */
558 symbolic_expression_p (rtx x)
561 /* Strip off any HIGH. */
562 if (GET_CODE (x) == HIGH)
565 return (symbolic_operand (x, VOIDmode));
568 /* Accept any constant that can be moved in one instruction into a
571 cint_ok_for_move (HOST_WIDE_INT ival)
573 /* OK if ldo, ldil, or zdepi, can be used. */
574 return (VAL_14_BITS_P (ival)
575 || ldil_cint_p (ival)
576 || zdepi_cint_p (ival));
579 /* Return truth value of whether OP can be used as an operand in a
582 adddi3_operand (rtx op, enum machine_mode mode)
584 return (register_operand (op, mode)
585 || (GET_CODE (op) == CONST_INT
586 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
589 /* True iff the operand OP can be used as the destination operand of
590 an integer store. This also implies the operand could be used as
591 the source operand of an integer load. Symbolic, lo_sum and indexed
592 memory operands are not allowed. We accept reloading pseudos and
593 other memory operands. */
595 integer_store_memory_operand (rtx op, enum machine_mode mode)
597 return ((reload_in_progress
599 && REGNO (op) >= FIRST_PSEUDO_REGISTER
600 && reg_renumber [REGNO (op)] < 0)
601 || (GET_CODE (op) == MEM
602 && (reload_in_progress || memory_address_p (mode, XEXP (op, 0)))
603 && !symbolic_memory_operand (op, VOIDmode)
604 && !IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))
605 && !IS_INDEX_ADDR_P (XEXP (op, 0))));
608 /* True iff ldil can be used to load this CONST_INT. The least
609 significant 11 bits of the value must be zero and the value must
610 not change sign when extended from 32 to 64 bits. */
612 ldil_cint_p (HOST_WIDE_INT ival)
614 HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff);
616 return x == 0 || x == ((HOST_WIDE_INT) -1 << 31);
619 /* True iff zdepi can be used to generate this CONST_INT.
620 zdepi first sign extends a 5-bit signed number to a given field
621 length, then places this field anywhere in a zero. */
623 zdepi_cint_p (unsigned HOST_WIDE_INT x)
625 unsigned HOST_WIDE_INT lsb_mask, t;
627 /* This might not be obvious, but it's at least fast.
628 This function is critical; we don't have the time loops would take. */
630 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
631 /* Return true iff t is a power of two. */
632 return ((t & (t - 1)) == 0);
635 /* True iff depi or extru can be used to compute (reg & mask).
636 Accept bit pattern like these:
641 and_mask_p (unsigned HOST_WIDE_INT mask)
644 mask += mask & -mask;
645 return (mask & (mask - 1)) == 0;
648 /* True iff depi can be used to compute (reg | MASK). */
650 ior_mask_p (unsigned HOST_WIDE_INT mask)
652 mask += mask & -mask;
653 return (mask & (mask - 1)) == 0;
656 /* Legitimize PIC addresses. If the address is already
657 position-independent, we return ORIG. Newly generated
658 position-independent addresses go to REG. If we need more
659 than one register, we lose. */
662 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
666 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
668 /* Labels need special handling. */
669 if (pic_label_operand (orig, mode))
671 /* We do not want to go through the movXX expanders here since that
672 would create recursion.
674 Nor do we really want to call a generator for a named pattern
675 since that requires multiple patterns if we want to support
678 So instead we just emit the raw set, which avoids the movXX
679 expanders completely. */
680 mark_reg_pointer (reg, BITS_PER_UNIT);
681 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
682 current_function_uses_pic_offset_table = 1;
685 if (GET_CODE (orig) == SYMBOL_REF)
691 /* Before reload, allocate a temporary register for the intermediate
692 result. This allows the sequence to be deleted when the final
693 result is unused and the insns are trivially dead. */
694 tmp_reg = ((reload_in_progress || reload_completed)
695 ? reg : gen_reg_rtx (Pmode));
697 /* Force function labels into memory. */
698 if (function_label_operand (orig, mode))
699 orig = force_const_mem (mode, orig);
701 emit_move_insn (tmp_reg,
702 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
703 gen_rtx_HIGH (word_mode, orig)));
705 = gen_const_mem (Pmode,
706 gen_rtx_LO_SUM (Pmode, tmp_reg,
707 gen_rtx_UNSPEC (Pmode,
711 current_function_uses_pic_offset_table = 1;
712 mark_reg_pointer (reg, BITS_PER_UNIT);
713 insn = emit_move_insn (reg, pic_ref);
715 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
716 set_unique_reg_note (insn, REG_EQUAL, orig);
720 else if (GET_CODE (orig) == CONST)
724 if (GET_CODE (XEXP (orig, 0)) == PLUS
725 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
729 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
731 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
732 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
733 base == reg ? 0 : reg);
735 if (GET_CODE (orig) == CONST_INT)
737 if (INT_14_BITS (orig))
738 return plus_constant (base, INTVAL (orig));
739 orig = force_reg (Pmode, orig);
741 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
742 /* Likewise, should we set special REG_NOTEs here? */
748 static GTY(()) rtx gen_tls_tga;
751 gen_tls_get_addr (void)
754 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
759 hppa_tls_call (rtx arg)
763 ret = gen_reg_rtx (Pmode);
764 emit_library_call_value (gen_tls_get_addr (), ret,
765 LCT_CONST, Pmode, 1, arg, Pmode);
771 legitimize_tls_address (rtx addr)
773 rtx ret, insn, tmp, t1, t2, tp;
774 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
778 case TLS_MODEL_GLOBAL_DYNAMIC:
779 tmp = gen_reg_rtx (Pmode);
781 emit_insn (gen_tgd_load_pic (tmp, addr));
783 emit_insn (gen_tgd_load (tmp, addr));
784 ret = hppa_tls_call (tmp);
787 case TLS_MODEL_LOCAL_DYNAMIC:
788 ret = gen_reg_rtx (Pmode);
789 tmp = gen_reg_rtx (Pmode);
792 emit_insn (gen_tld_load_pic (tmp, addr));
794 emit_insn (gen_tld_load (tmp, addr));
795 t1 = hppa_tls_call (tmp);
798 t2 = gen_reg_rtx (Pmode);
799 emit_libcall_block (insn, t2, t1,
800 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
802 emit_insn (gen_tld_offset_load (ret, addr, t2));
805 case TLS_MODEL_INITIAL_EXEC:
806 tp = gen_reg_rtx (Pmode);
807 tmp = gen_reg_rtx (Pmode);
808 ret = gen_reg_rtx (Pmode);
809 emit_insn (gen_tp_load (tp));
811 emit_insn (gen_tie_load_pic (tmp, addr));
813 emit_insn (gen_tie_load (tmp, addr));
814 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
817 case TLS_MODEL_LOCAL_EXEC:
818 tp = gen_reg_rtx (Pmode);
819 ret = gen_reg_rtx (Pmode);
820 emit_insn (gen_tp_load (tp));
821 emit_insn (gen_tle_load (ret, addr, tp));
831 /* Try machine-dependent ways of modifying an illegitimate address
832 to be legitimate. If we find one, return the new, valid address.
833 This macro is used in only one place: `memory_address' in explow.c.
835 OLDX is the address as it was before break_out_memory_refs was called.
836 In some cases it is useful to look at this to decide what needs to be done.
838 MODE and WIN are passed so that this macro can use
839 GO_IF_LEGITIMATE_ADDRESS.
841 It is always safe for this macro to do nothing. It exists to recognize
842 opportunities to optimize the output.
844 For the PA, transform:
846 memory(X + <large int>)
850 if (<large int> & mask) >= 16
851 Y = (<large int> & ~mask) + mask + 1 Round up.
853 Y = (<large int> & ~mask) Round down.
855 memory (Z + (<large int> - Y));
857 This is for CSE to find several similar references, and only use one Z.
859 X can either be a SYMBOL_REF or REG, but because combine cannot
860 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
861 D will not fit in 14 bits.
863 MODE_FLOAT references allow displacements which fit in 5 bits, so use
866 MODE_INT references allow displacements which fit in 14 bits, so use
869 This relies on the fact that most mode MODE_FLOAT references will use FP
870 registers and most mode MODE_INT references will use integer registers.
871 (In the rare case of an FP register used in an integer MODE, we depend
872 on secondary reloads to clean things up.)
875 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
876 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
877 addressing modes to be used).
879 Put X and Z into registers. Then put the entire expression into
883 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
884 enum machine_mode mode)
888 /* We need to canonicalize the order of operands in unscaled indexed
889 addresses since the code that checks if an address is valid doesn't
890 always try both orders. */
891 if (!TARGET_NO_SPACE_REGS
892 && GET_CODE (x) == PLUS
893 && GET_MODE (x) == Pmode
894 && REG_P (XEXP (x, 0))
895 && REG_P (XEXP (x, 1))
896 && REG_POINTER (XEXP (x, 0))
897 && !REG_POINTER (XEXP (x, 1)))
898 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
900 if (PA_SYMBOL_REF_TLS_P (x))
901 return legitimize_tls_address (x);
903 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
905 /* Strip off CONST. */
906 if (GET_CODE (x) == CONST)
909 /* Special case. Get the SYMBOL_REF into a register and use indexing.
910 That should always be safe. */
911 if (GET_CODE (x) == PLUS
912 && GET_CODE (XEXP (x, 0)) == REG
913 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
915 rtx reg = force_reg (Pmode, XEXP (x, 1));
916 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
919 /* Note we must reject symbols which represent function addresses
920 since the assembler/linker can't handle arithmetic on plabels. */
921 if (GET_CODE (x) == PLUS
922 && GET_CODE (XEXP (x, 1)) == CONST_INT
923 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
924 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
925 || GET_CODE (XEXP (x, 0)) == REG))
927 rtx int_part, ptr_reg;
929 int offset = INTVAL (XEXP (x, 1));
932 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
933 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
935 /* Choose which way to round the offset. Round up if we
936 are >= halfway to the next boundary. */
937 if ((offset & mask) >= ((mask + 1) / 2))
938 newoffset = (offset & ~ mask) + mask + 1;
940 newoffset = (offset & ~ mask);
942 /* If the newoffset will not fit in 14 bits (ldo), then
943 handling this would take 4 or 5 instructions (2 to load
944 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
945 add the new offset and the SYMBOL_REF.) Combine can
946 not handle 4->2 or 5->2 combinations, so do not create
948 if (! VAL_14_BITS_P (newoffset)
949 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
951 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
954 gen_rtx_HIGH (Pmode, const_part));
957 gen_rtx_LO_SUM (Pmode,
958 tmp_reg, const_part));
962 if (! VAL_14_BITS_P (newoffset))
963 int_part = force_reg (Pmode, GEN_INT (newoffset));
965 int_part = GEN_INT (newoffset);
967 ptr_reg = force_reg (Pmode,
969 force_reg (Pmode, XEXP (x, 0)),
972 return plus_constant (ptr_reg, offset - newoffset);
975 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
977 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
978 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
979 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
980 && (OBJECT_P (XEXP (x, 1))
981 || GET_CODE (XEXP (x, 1)) == SUBREG)
982 && GET_CODE (XEXP (x, 1)) != CONST)
984 int val = INTVAL (XEXP (XEXP (x, 0), 1));
988 if (GET_CODE (reg1) != REG)
989 reg1 = force_reg (Pmode, force_operand (reg1, 0));
991 reg2 = XEXP (XEXP (x, 0), 0);
992 if (GET_CODE (reg2) != REG)
993 reg2 = force_reg (Pmode, force_operand (reg2, 0));
995 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1002 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1004 Only do so for floating point modes since this is more speculative
1005 and we lose if it's an integer store. */
1006 if (GET_CODE (x) == PLUS
1007 && GET_CODE (XEXP (x, 0)) == PLUS
1008 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1009 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1010 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1011 && (mode == SFmode || mode == DFmode))
1014 /* First, try and figure out what to use as a base register. */
1015 rtx reg1, reg2, base, idx, orig_base;
1017 reg1 = XEXP (XEXP (x, 0), 1);
1022 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1023 then emit_move_sequence will turn on REG_POINTER so we'll know
1024 it's a base register below. */
1025 if (GET_CODE (reg1) != REG)
1026 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1028 if (GET_CODE (reg2) != REG)
1029 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1031 /* Figure out what the base and index are. */
1033 if (GET_CODE (reg1) == REG
1034 && REG_POINTER (reg1))
1037 orig_base = XEXP (XEXP (x, 0), 1);
1038 idx = gen_rtx_PLUS (Pmode,
1039 gen_rtx_MULT (Pmode,
1040 XEXP (XEXP (XEXP (x, 0), 0), 0),
1041 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1044 else if (GET_CODE (reg2) == REG
1045 && REG_POINTER (reg2))
1048 orig_base = XEXP (x, 1);
1055 /* If the index adds a large constant, try to scale the
1056 constant so that it can be loaded with only one insn. */
1057 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1058 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1059 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1060 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1062 /* Divide the CONST_INT by the scale factor, then add it to A. */
1063 int val = INTVAL (XEXP (idx, 1));
1065 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1066 reg1 = XEXP (XEXP (idx, 0), 0);
1067 if (GET_CODE (reg1) != REG)
1068 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1070 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1072 /* We can now generate a simple scaled indexed address. */
1075 (Pmode, gen_rtx_PLUS (Pmode,
1076 gen_rtx_MULT (Pmode, reg1,
1077 XEXP (XEXP (idx, 0), 1)),
1081 /* If B + C is still a valid base register, then add them. */
1082 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1083 && INTVAL (XEXP (idx, 1)) <= 4096
1084 && INTVAL (XEXP (idx, 1)) >= -4096)
1086 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1089 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1091 reg2 = XEXP (XEXP (idx, 0), 0);
1092 if (GET_CODE (reg2) != CONST_INT)
1093 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1095 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1096 gen_rtx_MULT (Pmode,
1102 /* Get the index into a register, then add the base + index and
1103 return a register holding the result. */
1105 /* First get A into a register. */
1106 reg1 = XEXP (XEXP (idx, 0), 0);
1107 if (GET_CODE (reg1) != REG)
1108 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1110 /* And get B into a register. */
1111 reg2 = XEXP (idx, 1);
1112 if (GET_CODE (reg2) != REG)
1113 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1115 reg1 = force_reg (Pmode,
1116 gen_rtx_PLUS (Pmode,
1117 gen_rtx_MULT (Pmode, reg1,
1118 XEXP (XEXP (idx, 0), 1)),
1121 /* Add the result to our base register and return. */
1122 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1126 /* Uh-oh. We might have an address for x[n-100000]. This needs
1127 special handling to avoid creating an indexed memory address
1128 with x-100000 as the base.
1130 If the constant part is small enough, then it's still safe because
1131 there is a guard page at the beginning and end of the data segment.
1133 Scaled references are common enough that we want to try and rearrange the
1134 terms so that we can use indexing for these addresses too. Only
1135 do the optimization for floatint point modes. */
1137 if (GET_CODE (x) == PLUS
1138 && symbolic_expression_p (XEXP (x, 1)))
1140 /* Ugly. We modify things here so that the address offset specified
1141 by the index expression is computed first, then added to x to form
1142 the entire address. */
1144 rtx regx1, regx2, regy1, regy2, y;
1146 /* Strip off any CONST. */
1148 if (GET_CODE (y) == CONST)
1151 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1153 /* See if this looks like
1154 (plus (mult (reg) (shadd_const))
1155 (const (plus (symbol_ref) (const_int))))
1157 Where const_int is small. In that case the const
1158 expression is a valid pointer for indexing.
1160 If const_int is big, but can be divided evenly by shadd_const
1161 and added to (reg). This allows more scaled indexed addresses. */
1162 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1163 && GET_CODE (XEXP (x, 0)) == MULT
1164 && GET_CODE (XEXP (y, 1)) == CONST_INT
1165 && INTVAL (XEXP (y, 1)) >= -4096
1166 && INTVAL (XEXP (y, 1)) <= 4095
1167 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1168 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1170 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1174 if (GET_CODE (reg1) != REG)
1175 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1177 reg2 = XEXP (XEXP (x, 0), 0);
1178 if (GET_CODE (reg2) != REG)
1179 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1181 return force_reg (Pmode,
1182 gen_rtx_PLUS (Pmode,
1183 gen_rtx_MULT (Pmode,
1188 else if ((mode == DFmode || mode == SFmode)
1189 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1190 && GET_CODE (XEXP (x, 0)) == MULT
1191 && GET_CODE (XEXP (y, 1)) == CONST_INT
1192 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1193 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1194 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1197 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1198 / INTVAL (XEXP (XEXP (x, 0), 1))));
1199 regx2 = XEXP (XEXP (x, 0), 0);
1200 if (GET_CODE (regx2) != REG)
1201 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1202 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1206 gen_rtx_PLUS (Pmode,
1207 gen_rtx_MULT (Pmode, regx2,
1208 XEXP (XEXP (x, 0), 1)),
1209 force_reg (Pmode, XEXP (y, 0))));
1211 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1212 && INTVAL (XEXP (y, 1)) >= -4096
1213 && INTVAL (XEXP (y, 1)) <= 4095)
1215 /* This is safe because of the guard page at the
1216 beginning and end of the data space. Just
1217 return the original address. */
1222 /* Doesn't look like one we can optimize. */
1223 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1224 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1225 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1226 regx1 = force_reg (Pmode,
1227 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1229 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1237 /* For the HPPA, REG and REG+CONST is cost 0
1238 and addresses involving symbolic constants are cost 2.
1240 PIC addresses are very expensive.
1242 It is no coincidence that this has the same structure
1243 as GO_IF_LEGITIMATE_ADDRESS. */
1246 hppa_address_cost (rtx X)
1248 switch (GET_CODE (X))
1261 /* Compute a (partial) cost for rtx X. Return true if the complete
1262 cost has been computed, and false if subexpressions should be
1263 scanned. In either case, *TOTAL contains the cost result. */
1266 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1271 if (INTVAL (x) == 0)
1273 else if (INT_14_BITS (x))
1290 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1291 && outer_code != SET)
1298 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1299 *total = COSTS_N_INSNS (3);
1300 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1301 *total = COSTS_N_INSNS (8);
1303 *total = COSTS_N_INSNS (20);
1307 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1309 *total = COSTS_N_INSNS (14);
1317 *total = COSTS_N_INSNS (60);
1320 case PLUS: /* this includes shNadd insns */
1322 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1323 *total = COSTS_N_INSNS (3);
1325 *total = COSTS_N_INSNS (1);
1331 *total = COSTS_N_INSNS (1);
1339 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1340 new rtx with the correct mode. */
1342 force_mode (enum machine_mode mode, rtx orig)
1344 if (mode == GET_MODE (orig))
1347 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1349 return gen_rtx_REG (mode, REGNO (orig));
1352 /* Return 1 if *X is a thread-local symbol. */
1355 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1357 return PA_SYMBOL_REF_TLS_P (*x);
1360 /* Return 1 if X contains a thread-local symbol. */
1363 pa_tls_referenced_p (rtx x)
1365 if (!TARGET_HAVE_TLS)
1368 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1371 /* Emit insns to move operands[1] into operands[0].
1373 Return 1 if we have written out everything that needs to be done to
1374 do the move. Otherwise, return 0 and the caller will emit the move
1377 Note SCRATCH_REG may not be in the proper mode depending on how it
1378 will be used. This routine is responsible for creating a new copy
1379 of SCRATCH_REG in the proper mode. */
1382 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1384 register rtx operand0 = operands[0];
1385 register rtx operand1 = operands[1];
1388 /* We can only handle indexed addresses in the destination operand
1389 of floating point stores. Thus, we need to break out indexed
1390 addresses from the destination operand. */
1391 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1393 gcc_assert (can_create_pseudo_p ());
1395 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1396 operand0 = replace_equiv_address (operand0, tem);
1399 /* On targets with non-equivalent space registers, break out unscaled
1400 indexed addresses from the source operand before the final CSE.
1401 We have to do this because the REG_POINTER flag is not correctly
1402 carried through various optimization passes and CSE may substitute
1403 a pseudo without the pointer set for one with the pointer set. As
1404 a result, we loose various opportunities to create insns with
1405 unscaled indexed addresses. */
1406 if (!TARGET_NO_SPACE_REGS
1407 && !cse_not_expected
1408 && GET_CODE (operand1) == MEM
1409 && GET_CODE (XEXP (operand1, 0)) == PLUS
1410 && REG_P (XEXP (XEXP (operand1, 0), 0))
1411 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1413 = replace_equiv_address (operand1,
1414 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1417 && reload_in_progress && GET_CODE (operand0) == REG
1418 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1419 operand0 = reg_equiv_mem[REGNO (operand0)];
1420 else if (scratch_reg
1421 && reload_in_progress && GET_CODE (operand0) == SUBREG
1422 && GET_CODE (SUBREG_REG (operand0)) == REG
1423 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1425 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1426 the code which tracks sets/uses for delete_output_reload. */
1427 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1428 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1429 SUBREG_BYTE (operand0));
1430 operand0 = alter_subreg (&temp);
1434 && reload_in_progress && GET_CODE (operand1) == REG
1435 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1436 operand1 = reg_equiv_mem[REGNO (operand1)];
1437 else if (scratch_reg
1438 && reload_in_progress && GET_CODE (operand1) == SUBREG
1439 && GET_CODE (SUBREG_REG (operand1)) == REG
1440 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1442 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1443 the code which tracks sets/uses for delete_output_reload. */
1444 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1445 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1446 SUBREG_BYTE (operand1));
1447 operand1 = alter_subreg (&temp);
1450 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1451 && ((tem = find_replacement (&XEXP (operand0, 0)))
1452 != XEXP (operand0, 0)))
1453 operand0 = replace_equiv_address (operand0, tem);
1455 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1456 && ((tem = find_replacement (&XEXP (operand1, 0)))
1457 != XEXP (operand1, 0)))
1458 operand1 = replace_equiv_address (operand1, tem);
1460 /* Handle secondary reloads for loads/stores of FP registers from
1461 REG+D addresses where D does not fit in 5 or 14 bits, including
1462 (subreg (mem (addr))) cases. */
1464 && fp_reg_operand (operand0, mode)
1465 && ((GET_CODE (operand1) == MEM
1466 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1467 XEXP (operand1, 0)))
1468 || ((GET_CODE (operand1) == SUBREG
1469 && GET_CODE (XEXP (operand1, 0)) == MEM
1470 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1472 XEXP (XEXP (operand1, 0), 0))))))
1474 if (GET_CODE (operand1) == SUBREG)
1475 operand1 = XEXP (operand1, 0);
1477 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1478 it in WORD_MODE regardless of what mode it was originally given
1480 scratch_reg = force_mode (word_mode, scratch_reg);
1482 /* D might not fit in 14 bits either; for such cases load D into
1484 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1486 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1487 emit_move_insn (scratch_reg,
1488 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1490 XEXP (XEXP (operand1, 0), 0),
1494 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1495 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1496 replace_equiv_address (operand1, scratch_reg)));
1499 else if (scratch_reg
1500 && fp_reg_operand (operand1, mode)
1501 && ((GET_CODE (operand0) == MEM
1502 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1504 XEXP (operand0, 0)))
1505 || ((GET_CODE (operand0) == SUBREG)
1506 && GET_CODE (XEXP (operand0, 0)) == MEM
1507 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1509 XEXP (XEXP (operand0, 0), 0)))))
1511 if (GET_CODE (operand0) == SUBREG)
1512 operand0 = XEXP (operand0, 0);
1514 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1515 it in WORD_MODE regardless of what mode it was originally given
1517 scratch_reg = force_mode (word_mode, scratch_reg);
1519 /* D might not fit in 14 bits either; for such cases load D into
1521 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1523 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1524 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1527 XEXP (XEXP (operand0, 0),
1532 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1533 emit_insn (gen_rtx_SET (VOIDmode,
1534 replace_equiv_address (operand0, scratch_reg),
1538 /* Handle secondary reloads for loads of FP registers from constant
1539 expressions by forcing the constant into memory.
1541 Use scratch_reg to hold the address of the memory location.
1543 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1544 NO_REGS when presented with a const_int and a register class
1545 containing only FP registers. Doing so unfortunately creates
1546 more problems than it solves. Fix this for 2.5. */
1547 else if (scratch_reg
1548 && CONSTANT_P (operand1)
1549 && fp_reg_operand (operand0, mode))
1551 rtx const_mem, xoperands[2];
1553 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1554 it in WORD_MODE regardless of what mode it was originally given
1556 scratch_reg = force_mode (word_mode, scratch_reg);
1558 /* Force the constant into memory and put the address of the
1559 memory location into scratch_reg. */
1560 const_mem = force_const_mem (mode, operand1);
1561 xoperands[0] = scratch_reg;
1562 xoperands[1] = XEXP (const_mem, 0);
1563 emit_move_sequence (xoperands, Pmode, 0);
1565 /* Now load the destination register. */
1566 emit_insn (gen_rtx_SET (mode, operand0,
1567 replace_equiv_address (const_mem, scratch_reg)));
1570 /* Handle secondary reloads for SAR. These occur when trying to load
1571 the SAR from memory, FP register, or with a constant. */
1572 else if (scratch_reg
1573 && GET_CODE (operand0) == REG
1574 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1575 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1576 && (GET_CODE (operand1) == MEM
1577 || GET_CODE (operand1) == CONST_INT
1578 || (GET_CODE (operand1) == REG
1579 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1581 /* D might not fit in 14 bits either; for such cases load D into
1583 if (GET_CODE (operand1) == MEM
1584 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1586 /* We are reloading the address into the scratch register, so we
1587 want to make sure the scratch register is a full register. */
1588 scratch_reg = force_mode (word_mode, scratch_reg);
1590 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1591 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1594 XEXP (XEXP (operand1, 0),
1598 /* Now we are going to load the scratch register from memory,
1599 we want to load it in the same width as the original MEM,
1600 which must be the same as the width of the ultimate destination,
1602 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1604 emit_move_insn (scratch_reg,
1605 replace_equiv_address (operand1, scratch_reg));
1609 /* We want to load the scratch register using the same mode as
1610 the ultimate destination. */
1611 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1613 emit_move_insn (scratch_reg, operand1);
1616 /* And emit the insn to set the ultimate destination. We know that
1617 the scratch register has the same mode as the destination at this
1619 emit_move_insn (operand0, scratch_reg);
1622 /* Handle the most common case: storing into a register. */
1623 else if (register_operand (operand0, mode))
1625 if (register_operand (operand1, mode)
1626 || (GET_CODE (operand1) == CONST_INT
1627 && cint_ok_for_move (INTVAL (operand1)))
1628 || (operand1 == CONST0_RTX (mode))
1629 || (GET_CODE (operand1) == HIGH
1630 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1631 /* Only `general_operands' can come here, so MEM is ok. */
1632 || GET_CODE (operand1) == MEM)
1634 /* Various sets are created during RTL generation which don't
1635 have the REG_POINTER flag correctly set. After the CSE pass,
1636 instruction recognition can fail if we don't consistently
1637 set this flag when performing register copies. This should
1638 also improve the opportunities for creating insns that use
1639 unscaled indexing. */
1640 if (REG_P (operand0) && REG_P (operand1))
1642 if (REG_POINTER (operand1)
1643 && !REG_POINTER (operand0)
1644 && !HARD_REGISTER_P (operand0))
1645 copy_reg_pointer (operand0, operand1);
1646 else if (REG_POINTER (operand0)
1647 && !REG_POINTER (operand1)
1648 && !HARD_REGISTER_P (operand1))
1649 copy_reg_pointer (operand1, operand0);
1652 /* When MEMs are broken out, the REG_POINTER flag doesn't
1653 get set. In some cases, we can set the REG_POINTER flag
1654 from the declaration for the MEM. */
1655 if (REG_P (operand0)
1656 && GET_CODE (operand1) == MEM
1657 && !REG_POINTER (operand0))
1659 tree decl = MEM_EXPR (operand1);
1661 /* Set the register pointer flag and register alignment
1662 if the declaration for this memory reference is a
1663 pointer type. Fortran indirect argument references
1666 && !(flag_argument_noalias > 1
1667 && TREE_CODE (decl) == INDIRECT_REF
1668 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1672 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1674 if (TREE_CODE (decl) == COMPONENT_REF)
1675 decl = TREE_OPERAND (decl, 1);
1677 type = TREE_TYPE (decl);
1678 if (TREE_CODE (type) == ARRAY_TYPE)
1679 type = get_inner_array_type (type);
1681 if (POINTER_TYPE_P (type))
1685 type = TREE_TYPE (type);
1686 /* Using TYPE_ALIGN_OK is rather conservative as
1687 only the ada frontend actually sets it. */
1688 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1690 mark_reg_pointer (operand0, align);
1695 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1699 else if (GET_CODE (operand0) == MEM)
1701 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1702 && !(reload_in_progress || reload_completed))
1704 rtx temp = gen_reg_rtx (DFmode);
1706 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1707 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1710 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1712 /* Run this case quickly. */
1713 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1716 if (! (reload_in_progress || reload_completed))
1718 operands[0] = validize_mem (operand0);
1719 operands[1] = operand1 = force_reg (mode, operand1);
1723 /* Simplify the source if we need to.
1724 Note we do have to handle function labels here, even though we do
1725 not consider them legitimate constants. Loop optimizations can
1726 call the emit_move_xxx with one as a source. */
1727 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1728 || function_label_operand (operand1, mode)
1729 || (GET_CODE (operand1) == HIGH
1730 && symbolic_operand (XEXP (operand1, 0), mode)))
1734 if (GET_CODE (operand1) == HIGH)
1737 operand1 = XEXP (operand1, 0);
1739 if (symbolic_operand (operand1, mode))
1741 /* Argh. The assembler and linker can't handle arithmetic
1744 So we force the plabel into memory, load operand0 from
1745 the memory location, then add in the constant part. */
1746 if ((GET_CODE (operand1) == CONST
1747 && GET_CODE (XEXP (operand1, 0)) == PLUS
1748 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1749 || function_label_operand (operand1, mode))
1751 rtx temp, const_part;
1753 /* Figure out what (if any) scratch register to use. */
1754 if (reload_in_progress || reload_completed)
1756 scratch_reg = scratch_reg ? scratch_reg : operand0;
1757 /* SCRATCH_REG will hold an address and maybe the actual
1758 data. We want it in WORD_MODE regardless of what mode it
1759 was originally given to us. */
1760 scratch_reg = force_mode (word_mode, scratch_reg);
1763 scratch_reg = gen_reg_rtx (Pmode);
1765 if (GET_CODE (operand1) == CONST)
1767 /* Save away the constant part of the expression. */
1768 const_part = XEXP (XEXP (operand1, 0), 1);
1769 gcc_assert (GET_CODE (const_part) == CONST_INT);
1771 /* Force the function label into memory. */
1772 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1776 /* No constant part. */
1777 const_part = NULL_RTX;
1779 /* Force the function label into memory. */
1780 temp = force_const_mem (mode, operand1);
1784 /* Get the address of the memory location. PIC-ify it if
1786 temp = XEXP (temp, 0);
1788 temp = legitimize_pic_address (temp, mode, scratch_reg);
1790 /* Put the address of the memory location into our destination
1793 emit_move_sequence (operands, mode, scratch_reg);
1795 /* Now load from the memory location into our destination
1797 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1798 emit_move_sequence (operands, mode, scratch_reg);
1800 /* And add back in the constant part. */
1801 if (const_part != NULL_RTX)
1802 expand_inc (operand0, const_part);
1811 if (reload_in_progress || reload_completed)
1813 temp = scratch_reg ? scratch_reg : operand0;
1814 /* TEMP will hold an address and maybe the actual
1815 data. We want it in WORD_MODE regardless of what mode it
1816 was originally given to us. */
1817 temp = force_mode (word_mode, temp);
1820 temp = gen_reg_rtx (Pmode);
1822 /* (const (plus (symbol) (const_int))) must be forced to
1823 memory during/after reload if the const_int will not fit
1825 if (GET_CODE (operand1) == CONST
1826 && GET_CODE (XEXP (operand1, 0)) == PLUS
1827 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1828 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1829 && (reload_completed || reload_in_progress)
1832 rtx const_mem = force_const_mem (mode, operand1);
1833 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1835 operands[1] = replace_equiv_address (const_mem, operands[1]);
1836 emit_move_sequence (operands, mode, temp);
1840 operands[1] = legitimize_pic_address (operand1, mode, temp);
1841 if (REG_P (operand0) && REG_P (operands[1]))
1842 copy_reg_pointer (operand0, operands[1]);
1843 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1846 /* On the HPPA, references to data space are supposed to use dp,
1847 register 27, but showing it in the RTL inhibits various cse
1848 and loop optimizations. */
1853 if (reload_in_progress || reload_completed)
1855 temp = scratch_reg ? scratch_reg : operand0;
1856 /* TEMP will hold an address and maybe the actual
1857 data. We want it in WORD_MODE regardless of what mode it
1858 was originally given to us. */
1859 temp = force_mode (word_mode, temp);
1862 temp = gen_reg_rtx (mode);
1864 /* Loading a SYMBOL_REF into a register makes that register
1865 safe to be used as the base in an indexed address.
1867 Don't mark hard registers though. That loses. */
1868 if (GET_CODE (operand0) == REG
1869 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1870 mark_reg_pointer (operand0, BITS_PER_UNIT);
1871 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1872 mark_reg_pointer (temp, BITS_PER_UNIT);
1875 set = gen_rtx_SET (mode, operand0, temp);
1877 set = gen_rtx_SET (VOIDmode,
1879 gen_rtx_LO_SUM (mode, temp, operand1));
1881 emit_insn (gen_rtx_SET (VOIDmode,
1883 gen_rtx_HIGH (mode, operand1)));
1889 else if (pa_tls_referenced_p (operand1))
1894 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
1896 addend = XEXP (XEXP (tmp, 0), 1);
1897 tmp = XEXP (XEXP (tmp, 0), 0);
1900 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
1901 tmp = legitimize_tls_address (tmp);
1904 tmp = gen_rtx_PLUS (mode, tmp, addend);
1905 tmp = force_operand (tmp, operands[0]);
1909 else if (GET_CODE (operand1) != CONST_INT
1910 || !cint_ok_for_move (INTVAL (operand1)))
1914 HOST_WIDE_INT value = 0;
1915 HOST_WIDE_INT insv = 0;
1918 if (GET_CODE (operand1) == CONST_INT)
1919 value = INTVAL (operand1);
1922 && GET_CODE (operand1) == CONST_INT
1923 && HOST_BITS_PER_WIDE_INT > 32
1924 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1928 /* Extract the low order 32 bits of the value and sign extend.
1929 If the new value is the same as the original value, we can
1930 can use the original value as-is. If the new value is
1931 different, we use it and insert the most-significant 32-bits
1932 of the original value into the final result. */
1933 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1934 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1937 #if HOST_BITS_PER_WIDE_INT > 32
1938 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1942 operand1 = GEN_INT (nval);
1946 if (reload_in_progress || reload_completed)
1947 temp = scratch_reg ? scratch_reg : operand0;
1949 temp = gen_reg_rtx (mode);
1951 /* We don't directly split DImode constants on 32-bit targets
1952 because PLUS uses an 11-bit immediate and the insn sequence
1953 generated is not as efficient as the one using HIGH/LO_SUM. */
1954 if (GET_CODE (operand1) == CONST_INT
1955 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
1956 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1959 /* Directly break constant into high and low parts. This
1960 provides better optimization opportunities because various
1961 passes recognize constants split with PLUS but not LO_SUM.
1962 We use a 14-bit signed low part except when the addition
1963 of 0x4000 to the high part might change the sign of the
1965 HOST_WIDE_INT low = value & 0x3fff;
1966 HOST_WIDE_INT high = value & ~ 0x3fff;
1970 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1978 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1979 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1983 emit_insn (gen_rtx_SET (VOIDmode, temp,
1984 gen_rtx_HIGH (mode, operand1)));
1985 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1988 insn = emit_move_insn (operands[0], operands[1]);
1990 /* Now insert the most significant 32 bits of the value
1991 into the register. When we don't have a second register
1992 available, it could take up to nine instructions to load
1993 a 64-bit integer constant. Prior to reload, we force
1994 constants that would take more than three instructions
1995 to load to the constant pool. During and after reload,
1996 we have to handle all possible values. */
1999 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2000 register and the value to be inserted is outside the
2001 range that can be loaded with three depdi instructions. */
2002 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2004 operand1 = GEN_INT (insv);
2006 emit_insn (gen_rtx_SET (VOIDmode, temp,
2007 gen_rtx_HIGH (mode, operand1)));
2008 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2009 emit_insn (gen_insv (operand0, GEN_INT (32),
2014 int len = 5, pos = 27;
2016 /* Insert the bits using the depdi instruction. */
2019 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2020 HOST_WIDE_INT sign = v5 < 0;
2022 /* Left extend the insertion. */
2023 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2024 while (pos > 0 && (insv & 1) == sign)
2026 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2031 emit_insn (gen_insv (operand0, GEN_INT (len),
2032 GEN_INT (pos), GEN_INT (v5)));
2034 len = pos > 0 && pos < 5 ? pos : 5;
2040 set_unique_reg_note (insn, REG_EQUAL, op1);
2045 /* Now have insn-emit do whatever it normally does. */
2049 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2050 it will need a link/runtime reloc). */
2053 reloc_needed (tree exp)
2057 switch (TREE_CODE (exp))
2062 case POINTER_PLUS_EXPR:
2065 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2066 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2071 case NON_LVALUE_EXPR:
2072 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2078 unsigned HOST_WIDE_INT ix;
2080 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2082 reloc |= reloc_needed (value);
2095 /* Does operand (which is a symbolic_operand) live in text space?
2096 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2100 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2102 if (GET_CODE (operand) == CONST)
2103 operand = XEXP (XEXP (operand, 0), 0);
2106 if (GET_CODE (operand) == SYMBOL_REF)
2107 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2111 if (GET_CODE (operand) == SYMBOL_REF)
2112 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2118 /* Return the best assembler insn template
2119 for moving operands[1] into operands[0] as a fullword. */
2121 singlemove_string (rtx *operands)
2123 HOST_WIDE_INT intval;
2125 if (GET_CODE (operands[0]) == MEM)
2126 return "stw %r1,%0";
2127 if (GET_CODE (operands[1]) == MEM)
2129 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2134 gcc_assert (GET_MODE (operands[1]) == SFmode);
2136 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2138 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2139 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2141 operands[1] = GEN_INT (i);
2142 /* Fall through to CONST_INT case. */
2144 if (GET_CODE (operands[1]) == CONST_INT)
2146 intval = INTVAL (operands[1]);
2148 if (VAL_14_BITS_P (intval))
2150 else if ((intval & 0x7ff) == 0)
2151 return "ldil L'%1,%0";
2152 else if (zdepi_cint_p (intval))
2153 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2155 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2157 return "copy %1,%0";
2161 /* Compute position (in OP[1]) and width (in OP[2])
2162 useful for copying IMM to a register using the zdepi
2163 instructions. Store the immediate value to insert in OP[0]. */
2165 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2169 /* Find the least significant set bit in IMM. */
2170 for (lsb = 0; lsb < 32; lsb++)
2177 /* Choose variants based on *sign* of the 5-bit field. */
2178 if ((imm & 0x10) == 0)
2179 len = (lsb <= 28) ? 4 : 32 - lsb;
2182 /* Find the width of the bitstring in IMM. */
2183 for (len = 5; len < 32; len++)
2185 if ((imm & (1 << len)) == 0)
2189 /* Sign extend IMM as a 5-bit value. */
2190 imm = (imm & 0xf) - 0x10;
2198 /* Compute position (in OP[1]) and width (in OP[2])
2199 useful for copying IMM to a register using the depdi,z
2200 instructions. Store the immediate value to insert in OP[0]. */
2202 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2204 HOST_WIDE_INT lsb, len;
2206 /* Find the least significant set bit in IMM. */
2207 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2214 /* Choose variants based on *sign* of the 5-bit field. */
2215 if ((imm & 0x10) == 0)
2216 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2217 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2220 /* Find the width of the bitstring in IMM. */
2221 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2223 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2227 /* Sign extend IMM as a 5-bit value. */
2228 imm = (imm & 0xf) - 0x10;
2236 /* Output assembler code to perform a doubleword move insn
2237 with operands OPERANDS. */
2240 output_move_double (rtx *operands)
2242 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2244 rtx addreg0 = 0, addreg1 = 0;
2246 /* First classify both operands. */
2248 if (REG_P (operands[0]))
2250 else if (offsettable_memref_p (operands[0]))
2252 else if (GET_CODE (operands[0]) == MEM)
2257 if (REG_P (operands[1]))
2259 else if (CONSTANT_P (operands[1]))
2261 else if (offsettable_memref_p (operands[1]))
2263 else if (GET_CODE (operands[1]) == MEM)
2268 /* Check for the cases that the operand constraints are not
2269 supposed to allow to happen. */
2270 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2272 /* Handle copies between general and floating registers. */
2274 if (optype0 == REGOP && optype1 == REGOP
2275 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2277 if (FP_REG_P (operands[0]))
2279 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2280 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2281 return "{fldds|fldd} -16(%%sp),%0";
2285 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2286 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2287 return "{ldws|ldw} -12(%%sp),%R0";
2291 /* Handle auto decrementing and incrementing loads and stores
2292 specifically, since the structure of the function doesn't work
2293 for them without major modification. Do it better when we learn
2294 this port about the general inc/dec addressing of PA.
2295 (This was written by tege. Chide him if it doesn't work.) */
2297 if (optype0 == MEMOP)
2299 /* We have to output the address syntax ourselves, since print_operand
2300 doesn't deal with the addresses we want to use. Fix this later. */
2302 rtx addr = XEXP (operands[0], 0);
2303 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2305 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2307 operands[0] = XEXP (addr, 0);
2308 gcc_assert (GET_CODE (operands[1]) == REG
2309 && GET_CODE (operands[0]) == REG);
2311 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2313 /* No overlap between high target register and address
2314 register. (We do this in a non-obvious way to
2315 save a register file writeback) */
2316 if (GET_CODE (addr) == POST_INC)
2317 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2318 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2320 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2322 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2324 operands[0] = XEXP (addr, 0);
2325 gcc_assert (GET_CODE (operands[1]) == REG
2326 && GET_CODE (operands[0]) == REG);
2328 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2329 /* No overlap between high target register and address
2330 register. (We do this in a non-obvious way to save a
2331 register file writeback) */
2332 if (GET_CODE (addr) == PRE_INC)
2333 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2334 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2337 if (optype1 == MEMOP)
2339 /* We have to output the address syntax ourselves, since print_operand
2340 doesn't deal with the addresses we want to use. Fix this later. */
2342 rtx addr = XEXP (operands[1], 0);
2343 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2345 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2347 operands[1] = XEXP (addr, 0);
2348 gcc_assert (GET_CODE (operands[0]) == REG
2349 && GET_CODE (operands[1]) == REG);
2351 if (!reg_overlap_mentioned_p (high_reg, addr))
2353 /* No overlap between high target register and address
2354 register. (We do this in a non-obvious way to
2355 save a register file writeback) */
2356 if (GET_CODE (addr) == POST_INC)
2357 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2358 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2362 /* This is an undefined situation. We should load into the
2363 address register *and* update that register. Probably
2364 we don't need to handle this at all. */
2365 if (GET_CODE (addr) == POST_INC)
2366 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2367 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2370 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2372 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2374 operands[1] = XEXP (addr, 0);
2375 gcc_assert (GET_CODE (operands[0]) == REG
2376 && GET_CODE (operands[1]) == REG);
2378 if (!reg_overlap_mentioned_p (high_reg, addr))
2380 /* No overlap between high target register and address
2381 register. (We do this in a non-obvious way to
2382 save a register file writeback) */
2383 if (GET_CODE (addr) == PRE_INC)
2384 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2385 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2389 /* This is an undefined situation. We should load into the
2390 address register *and* update that register. Probably
2391 we don't need to handle this at all. */
2392 if (GET_CODE (addr) == PRE_INC)
2393 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2394 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2397 else if (GET_CODE (addr) == PLUS
2398 && GET_CODE (XEXP (addr, 0)) == MULT)
2401 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2403 if (!reg_overlap_mentioned_p (high_reg, addr))
2405 xoperands[0] = high_reg;
2406 xoperands[1] = XEXP (addr, 1);
2407 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2408 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2409 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2411 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2415 xoperands[0] = high_reg;
2416 xoperands[1] = XEXP (addr, 1);
2417 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2418 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2419 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2421 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2426 /* If an operand is an unoffsettable memory ref, find a register
2427 we can increment temporarily to make it refer to the second word. */
2429 if (optype0 == MEMOP)
2430 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2432 if (optype1 == MEMOP)
2433 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2435 /* Ok, we can do one word at a time.
2436 Normally we do the low-numbered word first.
2438 In either case, set up in LATEHALF the operands to use
2439 for the high-numbered word and in some cases alter the
2440 operands in OPERANDS to be suitable for the low-numbered word. */
2442 if (optype0 == REGOP)
2443 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2444 else if (optype0 == OFFSOP)
2445 latehalf[0] = adjust_address (operands[0], SImode, 4);
2447 latehalf[0] = operands[0];
2449 if (optype1 == REGOP)
2450 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2451 else if (optype1 == OFFSOP)
2452 latehalf[1] = adjust_address (operands[1], SImode, 4);
2453 else if (optype1 == CNSTOP)
2454 split_double (operands[1], &operands[1], &latehalf[1]);
2456 latehalf[1] = operands[1];
2458 /* If the first move would clobber the source of the second one,
2459 do them in the other order.
2461 This can happen in two cases:
2463 mem -> register where the first half of the destination register
2464 is the same register used in the memory's address. Reload
2465 can create such insns.
2467 mem in this case will be either register indirect or register
2468 indirect plus a valid offset.
2470 register -> register move where REGNO(dst) == REGNO(src + 1)
2471 someone (Tim/Tege?) claimed this can happen for parameter loads.
2473 Handle mem -> register case first. */
2474 if (optype0 == REGOP
2475 && (optype1 == MEMOP || optype1 == OFFSOP)
2476 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2479 /* Do the late half first. */
2481 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2482 output_asm_insn (singlemove_string (latehalf), latehalf);
2486 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2487 return singlemove_string (operands);
2490 /* Now handle register -> register case. */
2491 if (optype0 == REGOP && optype1 == REGOP
2492 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2494 output_asm_insn (singlemove_string (latehalf), latehalf);
2495 return singlemove_string (operands);
2498 /* Normal case: do the two words, low-numbered first. */
2500 output_asm_insn (singlemove_string (operands), operands);
2502 /* Make any unoffsettable addresses point at high-numbered word. */
2504 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2506 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2509 output_asm_insn (singlemove_string (latehalf), latehalf);
2511 /* Undo the adds we just did. */
2513 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2515 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2521 output_fp_move_double (rtx *operands)
2523 if (FP_REG_P (operands[0]))
2525 if (FP_REG_P (operands[1])
2526 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2527 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2529 output_asm_insn ("fldd%F1 %1,%0", operands);
2531 else if (FP_REG_P (operands[1]))
2533 output_asm_insn ("fstd%F0 %1,%0", operands);
2539 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2541 /* This is a pain. You have to be prepared to deal with an
2542 arbitrary address here including pre/post increment/decrement.
2544 so avoid this in the MD. */
2545 gcc_assert (GET_CODE (operands[0]) == REG);
2547 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2548 xoperands[0] = operands[0];
2549 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2554 /* Return a REG that occurs in ADDR with coefficient 1.
2555 ADDR can be effectively incremented by incrementing REG. */
2558 find_addr_reg (rtx addr)
2560 while (GET_CODE (addr) == PLUS)
2562 if (GET_CODE (XEXP (addr, 0)) == REG)
2563 addr = XEXP (addr, 0);
2564 else if (GET_CODE (XEXP (addr, 1)) == REG)
2565 addr = XEXP (addr, 1);
2566 else if (CONSTANT_P (XEXP (addr, 0)))
2567 addr = XEXP (addr, 1);
2568 else if (CONSTANT_P (XEXP (addr, 1)))
2569 addr = XEXP (addr, 0);
2573 gcc_assert (GET_CODE (addr) == REG);
2577 /* Emit code to perform a block move.
2579 OPERANDS[0] is the destination pointer as a REG, clobbered.
2580 OPERANDS[1] is the source pointer as a REG, clobbered.
2581 OPERANDS[2] is a register for temporary storage.
2582 OPERANDS[3] is a register for temporary storage.
2583 OPERANDS[4] is the size as a CONST_INT
2584 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2585 OPERANDS[6] is another temporary register. */
2588 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2590 int align = INTVAL (operands[5]);
2591 unsigned long n_bytes = INTVAL (operands[4]);
2593 /* We can't move more than a word at a time because the PA
2594 has no longer integer move insns. (Could use fp mem ops?) */
2595 if (align > (TARGET_64BIT ? 8 : 4))
2596 align = (TARGET_64BIT ? 8 : 4);
2598 /* Note that we know each loop below will execute at least twice
2599 (else we would have open-coded the copy). */
2603 /* Pre-adjust the loop counter. */
2604 operands[4] = GEN_INT (n_bytes - 16);
2605 output_asm_insn ("ldi %4,%2", operands);
2608 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2609 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2610 output_asm_insn ("std,ma %3,8(%0)", operands);
2611 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2612 output_asm_insn ("std,ma %6,8(%0)", operands);
2614 /* Handle the residual. There could be up to 7 bytes of
2615 residual to copy! */
2616 if (n_bytes % 16 != 0)
2618 operands[4] = GEN_INT (n_bytes % 8);
2619 if (n_bytes % 16 >= 8)
2620 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2621 if (n_bytes % 8 != 0)
2622 output_asm_insn ("ldd 0(%1),%6", operands);
2623 if (n_bytes % 16 >= 8)
2624 output_asm_insn ("std,ma %3,8(%0)", operands);
2625 if (n_bytes % 8 != 0)
2626 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2631 /* Pre-adjust the loop counter. */
2632 operands[4] = GEN_INT (n_bytes - 8);
2633 output_asm_insn ("ldi %4,%2", operands);
2636 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2637 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2638 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2639 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2640 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2642 /* Handle the residual. There could be up to 7 bytes of
2643 residual to copy! */
2644 if (n_bytes % 8 != 0)
2646 operands[4] = GEN_INT (n_bytes % 4);
2647 if (n_bytes % 8 >= 4)
2648 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2649 if (n_bytes % 4 != 0)
2650 output_asm_insn ("ldw 0(%1),%6", operands);
2651 if (n_bytes % 8 >= 4)
2652 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2653 if (n_bytes % 4 != 0)
2654 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2659 /* Pre-adjust the loop counter. */
2660 operands[4] = GEN_INT (n_bytes - 4);
2661 output_asm_insn ("ldi %4,%2", operands);
2664 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2665 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2666 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2667 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2668 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2670 /* Handle the residual. */
2671 if (n_bytes % 4 != 0)
2673 if (n_bytes % 4 >= 2)
2674 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2675 if (n_bytes % 2 != 0)
2676 output_asm_insn ("ldb 0(%1),%6", operands);
2677 if (n_bytes % 4 >= 2)
2678 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2679 if (n_bytes % 2 != 0)
2680 output_asm_insn ("stb %6,0(%0)", operands);
2685 /* Pre-adjust the loop counter. */
2686 operands[4] = GEN_INT (n_bytes - 2);
2687 output_asm_insn ("ldi %4,%2", operands);
2690 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2691 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2692 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2693 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2694 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2696 /* Handle the residual. */
2697 if (n_bytes % 2 != 0)
2699 output_asm_insn ("ldb 0(%1),%3", operands);
2700 output_asm_insn ("stb %3,0(%0)", operands);
2709 /* Count the number of insns necessary to handle this block move.
2711 Basic structure is the same as emit_block_move, except that we
2712 count insns rather than emit them. */
2715 compute_movmem_length (rtx insn)
2717 rtx pat = PATTERN (insn);
2718 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2719 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2720 unsigned int n_insns = 0;
2722 /* We can't move more than four bytes at a time because the PA
2723 has no longer integer move insns. (Could use fp mem ops?) */
2724 if (align > (TARGET_64BIT ? 8 : 4))
2725 align = (TARGET_64BIT ? 8 : 4);
2727 /* The basic copying loop. */
2731 if (n_bytes % (2 * align) != 0)
2733 if ((n_bytes % (2 * align)) >= align)
2736 if ((n_bytes % align) != 0)
2740 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2744 /* Emit code to perform a block clear.
2746 OPERANDS[0] is the destination pointer as a REG, clobbered.
2747 OPERANDS[1] is a register for temporary storage.
2748 OPERANDS[2] is the size as a CONST_INT
2749 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2752 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2754 int align = INTVAL (operands[3]);
2755 unsigned long n_bytes = INTVAL (operands[2]);
2757 /* We can't clear more than a word at a time because the PA
2758 has no longer integer move insns. */
2759 if (align > (TARGET_64BIT ? 8 : 4))
2760 align = (TARGET_64BIT ? 8 : 4);
2762 /* Note that we know each loop below will execute at least twice
2763 (else we would have open-coded the copy). */
2767 /* Pre-adjust the loop counter. */
2768 operands[2] = GEN_INT (n_bytes - 16);
2769 output_asm_insn ("ldi %2,%1", operands);
2772 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2773 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2774 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2776 /* Handle the residual. There could be up to 7 bytes of
2777 residual to copy! */
2778 if (n_bytes % 16 != 0)
2780 operands[2] = GEN_INT (n_bytes % 8);
2781 if (n_bytes % 16 >= 8)
2782 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2783 if (n_bytes % 8 != 0)
2784 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2789 /* Pre-adjust the loop counter. */
2790 operands[2] = GEN_INT (n_bytes - 8);
2791 output_asm_insn ("ldi %2,%1", operands);
2794 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2795 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2796 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2798 /* Handle the residual. There could be up to 7 bytes of
2799 residual to copy! */
2800 if (n_bytes % 8 != 0)
2802 operands[2] = GEN_INT (n_bytes % 4);
2803 if (n_bytes % 8 >= 4)
2804 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2805 if (n_bytes % 4 != 0)
2806 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2811 /* Pre-adjust the loop counter. */
2812 operands[2] = GEN_INT (n_bytes - 4);
2813 output_asm_insn ("ldi %2,%1", operands);
2816 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2817 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2818 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2820 /* Handle the residual. */
2821 if (n_bytes % 4 != 0)
2823 if (n_bytes % 4 >= 2)
2824 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2825 if (n_bytes % 2 != 0)
2826 output_asm_insn ("stb %%r0,0(%0)", operands);
2831 /* Pre-adjust the loop counter. */
2832 operands[2] = GEN_INT (n_bytes - 2);
2833 output_asm_insn ("ldi %2,%1", operands);
2836 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2837 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2838 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2840 /* Handle the residual. */
2841 if (n_bytes % 2 != 0)
2842 output_asm_insn ("stb %%r0,0(%0)", operands);
2851 /* Count the number of insns necessary to handle this block move.
2853 Basic structure is the same as emit_block_move, except that we
2854 count insns rather than emit them. */
2857 compute_clrmem_length (rtx insn)
2859 rtx pat = PATTERN (insn);
2860 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2861 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2862 unsigned int n_insns = 0;
2864 /* We can't clear more than a word at a time because the PA
2865 has no longer integer move insns. */
2866 if (align > (TARGET_64BIT ? 8 : 4))
2867 align = (TARGET_64BIT ? 8 : 4);
2869 /* The basic loop. */
2873 if (n_bytes % (2 * align) != 0)
2875 if ((n_bytes % (2 * align)) >= align)
2878 if ((n_bytes % align) != 0)
2882 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2888 output_and (rtx *operands)
2890 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2892 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2893 int ls0, ls1, ms0, p, len;
2895 for (ls0 = 0; ls0 < 32; ls0++)
2896 if ((mask & (1 << ls0)) == 0)
2899 for (ls1 = ls0; ls1 < 32; ls1++)
2900 if ((mask & (1 << ls1)) != 0)
2903 for (ms0 = ls1; ms0 < 32; ms0++)
2904 if ((mask & (1 << ms0)) == 0)
2907 gcc_assert (ms0 == 32);
2915 operands[2] = GEN_INT (len);
2916 return "{extru|extrw,u} %1,31,%2,%0";
2920 /* We could use this `depi' for the case above as well, but `depi'
2921 requires one more register file access than an `extru'. */
2926 operands[2] = GEN_INT (p);
2927 operands[3] = GEN_INT (len);
2928 return "{depi|depwi} 0,%2,%3,%0";
2932 return "and %1,%2,%0";
2935 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2936 storing the result in operands[0]. */
2938 output_64bit_and (rtx *operands)
2940 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2942 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2943 int ls0, ls1, ms0, p, len;
2945 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2946 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2949 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2950 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2953 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2954 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2957 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2959 if (ls1 == HOST_BITS_PER_WIDE_INT)
2965 operands[2] = GEN_INT (len);
2966 return "extrd,u %1,63,%2,%0";
2970 /* We could use this `depi' for the case above as well, but `depi'
2971 requires one more register file access than an `extru'. */
2976 operands[2] = GEN_INT (p);
2977 operands[3] = GEN_INT (len);
2978 return "depdi 0,%2,%3,%0";
2982 return "and %1,%2,%0";
2986 output_ior (rtx *operands)
2988 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2989 int bs0, bs1, p, len;
2991 if (INTVAL (operands[2]) == 0)
2992 return "copy %1,%0";
2994 for (bs0 = 0; bs0 < 32; bs0++)
2995 if ((mask & (1 << bs0)) != 0)
2998 for (bs1 = bs0; bs1 < 32; bs1++)
2999 if ((mask & (1 << bs1)) == 0)
3002 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3007 operands[2] = GEN_INT (p);
3008 operands[3] = GEN_INT (len);
3009 return "{depi|depwi} -1,%2,%3,%0";
3012 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3013 storing the result in operands[0]. */
3015 output_64bit_ior (rtx *operands)
3017 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3018 int bs0, bs1, p, len;
3020 if (INTVAL (operands[2]) == 0)
3021 return "copy %1,%0";
3023 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3024 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3027 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3028 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3031 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
3032 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3037 operands[2] = GEN_INT (p);
3038 operands[3] = GEN_INT (len);
3039 return "depdi -1,%2,%3,%0";
3042 /* Target hook for assembling integer objects. This code handles
3043 aligned SI and DI integers specially since function references
3044 must be preceded by P%. */
3047 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3049 if (size == UNITS_PER_WORD
3051 && function_label_operand (x, VOIDmode))
3053 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3054 output_addr_const (asm_out_file, x);
3055 fputc ('\n', asm_out_file);
3058 return default_assemble_integer (x, size, aligned_p);
3061 /* Output an ascii string. */
3063 output_ascii (FILE *file, const char *p, int size)
3067 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3069 /* The HP assembler can only take strings of 256 characters at one
3070 time. This is a limitation on input line length, *not* the
3071 length of the string. Sigh. Even worse, it seems that the
3072 restriction is in number of input characters (see \xnn &
3073 \whatever). So we have to do this very carefully. */
3075 fputs ("\t.STRING \"", file);
3078 for (i = 0; i < size; i += 4)
3082 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3084 register unsigned int c = (unsigned char) p[i + io];
3086 if (c == '\"' || c == '\\')
3087 partial_output[co++] = '\\';
3088 if (c >= ' ' && c < 0177)
3089 partial_output[co++] = c;
3093 partial_output[co++] = '\\';
3094 partial_output[co++] = 'x';
3095 hexd = c / 16 - 0 + '0';
3097 hexd -= '9' - 'a' + 1;
3098 partial_output[co++] = hexd;
3099 hexd = c % 16 - 0 + '0';
3101 hexd -= '9' - 'a' + 1;
3102 partial_output[co++] = hexd;
3105 if (chars_output + co > 243)
3107 fputs ("\"\n\t.STRING \"", file);
3110 fwrite (partial_output, 1, (size_t) co, file);
3114 fputs ("\"\n", file);
3117 /* Try to rewrite floating point comparisons & branches to avoid
3118 useless add,tr insns.
3120 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3121 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3122 first attempt to remove useless add,tr insns. It is zero
3123 for the second pass as reorg sometimes leaves bogus REG_DEAD
3126 When CHECK_NOTES is zero we can only eliminate add,tr insns
3127 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3130 remove_useless_addtr_insns (int check_notes)
3133 static int pass = 0;
3135 /* This is fairly cheap, so always run it when optimizing. */
3139 int fbranch_count = 0;
3141 /* Walk all the insns in this function looking for fcmp & fbranch
3142 instructions. Keep track of how many of each we find. */
3143 for (insn = get_insns (); insn; insn = next_insn (insn))
3147 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3148 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3151 tmp = PATTERN (insn);
3153 /* It must be a set. */
3154 if (GET_CODE (tmp) != SET)
3157 /* If the destination is CCFP, then we've found an fcmp insn. */
3158 tmp = SET_DEST (tmp);
3159 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3165 tmp = PATTERN (insn);
3166 /* If this is an fbranch instruction, bump the fbranch counter. */
3167 if (GET_CODE (tmp) == SET
3168 && SET_DEST (tmp) == pc_rtx
3169 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3170 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3171 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3172 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3180 /* Find all floating point compare + branch insns. If possible,
3181 reverse the comparison & the branch to avoid add,tr insns. */
3182 for (insn = get_insns (); insn; insn = next_insn (insn))
3186 /* Ignore anything that isn't an INSN. */
3187 if (GET_CODE (insn) != INSN)
3190 tmp = PATTERN (insn);
3192 /* It must be a set. */
3193 if (GET_CODE (tmp) != SET)
3196 /* The destination must be CCFP, which is register zero. */
3197 tmp = SET_DEST (tmp);
3198 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3201 /* INSN should be a set of CCFP.
3203 See if the result of this insn is used in a reversed FP
3204 conditional branch. If so, reverse our condition and
3205 the branch. Doing so avoids useless add,tr insns. */
3206 next = next_insn (insn);
3209 /* Jumps, calls and labels stop our search. */
3210 if (GET_CODE (next) == JUMP_INSN
3211 || GET_CODE (next) == CALL_INSN
3212 || GET_CODE (next) == CODE_LABEL)
3215 /* As does another fcmp insn. */
3216 if (GET_CODE (next) == INSN
3217 && GET_CODE (PATTERN (next)) == SET
3218 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3219 && REGNO (SET_DEST (PATTERN (next))) == 0)
3222 next = next_insn (next);
3225 /* Is NEXT_INSN a branch? */
3227 && GET_CODE (next) == JUMP_INSN)
3229 rtx pattern = PATTERN (next);
3231 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3232 and CCFP dies, then reverse our conditional and the branch
3233 to avoid the add,tr. */
3234 if (GET_CODE (pattern) == SET
3235 && SET_DEST (pattern) == pc_rtx
3236 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3237 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3238 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3239 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3240 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3241 && (fcmp_count == fbranch_count
3243 && find_regno_note (next, REG_DEAD, 0))))
3245 /* Reverse the branch. */
3246 tmp = XEXP (SET_SRC (pattern), 1);
3247 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3248 XEXP (SET_SRC (pattern), 2) = tmp;
3249 INSN_CODE (next) = -1;
3251 /* Reverse our condition. */
3252 tmp = PATTERN (insn);
3253 PUT_CODE (XEXP (tmp, 1),
3254 (reverse_condition_maybe_unordered
3255 (GET_CODE (XEXP (tmp, 1)))));
3265 /* You may have trouble believing this, but this is the 32 bit HP-PA
3270 Variable arguments (optional; any number may be allocated)
3272 SP-(4*(N+9)) arg word N
3277 Fixed arguments (must be allocated; may remain unused)
3286 SP-32 External Data Pointer (DP)
3288 SP-24 External/stub RP (RP')
3292 SP-8 Calling Stub RP (RP'')
3297 SP-0 Stack Pointer (points to next available address)
3301 /* This function saves registers as follows. Registers marked with ' are
3302 this function's registers (as opposed to the previous function's).
3303 If a frame_pointer isn't needed, r4 is saved as a general register;
3304 the space for the frame pointer is still allocated, though, to keep
3310 SP (FP') Previous FP
3311 SP + 4 Alignment filler (sigh)
3312 SP + 8 Space for locals reserved here.
3316 SP + n All call saved register used.
3320 SP + o All call saved fp registers used.
3324 SP + p (SP') points to next available address.
3328 /* Global variables set by output_function_prologue(). */
3329 /* Size of frame. Need to know this to emit return insns from
3331 static HOST_WIDE_INT actual_fsize, local_fsize;
3332 static int save_fregs;
3334 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3335 Handle case where DISP > 8k by using the add_high_const patterns.
3337 Note in DISP > 8k case, we will leave the high part of the address
3338 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3341 store_reg (int reg, HOST_WIDE_INT disp, int base)
3343 rtx insn, dest, src, basereg;
3345 src = gen_rtx_REG (word_mode, reg);
3346 basereg = gen_rtx_REG (Pmode, base);
3347 if (VAL_14_BITS_P (disp))
3349 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3350 insn = emit_move_insn (dest, src);
3352 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3354 rtx delta = GEN_INT (disp);
3355 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3357 emit_move_insn (tmpreg, delta);
3358 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3362 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3363 gen_rtx_SET (VOIDmode, tmpreg,
3364 gen_rtx_PLUS (Pmode, basereg, delta)),
3366 RTX_FRAME_RELATED_P (insn) = 1;
3368 dest = gen_rtx_MEM (word_mode, tmpreg);
3369 insn = emit_move_insn (dest, src);
3373 rtx delta = GEN_INT (disp);
3374 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3375 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3377 emit_move_insn (tmpreg, high);
3378 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3379 insn = emit_move_insn (dest, src);
3383 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3384 gen_rtx_SET (VOIDmode,
3385 gen_rtx_MEM (word_mode,
3386 gen_rtx_PLUS (word_mode, basereg,
3394 RTX_FRAME_RELATED_P (insn) = 1;
3397 /* Emit RTL to store REG at the memory location specified by BASE and then
3398 add MOD to BASE. MOD must be <= 8k. */
3401 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3403 rtx insn, basereg, srcreg, delta;
3405 gcc_assert (VAL_14_BITS_P (mod));
3407 basereg = gen_rtx_REG (Pmode, base);
3408 srcreg = gen_rtx_REG (word_mode, reg);
3409 delta = GEN_INT (mod);
3411 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3414 RTX_FRAME_RELATED_P (insn) = 1;
3416 /* RTX_FRAME_RELATED_P must be set on each frame related set
3417 in a parallel with more than one element. */
3418 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3419 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3423 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3424 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3425 whether to add a frame note or not.
3427 In the DISP > 8k case, we leave the high part of the address in %r1.
3428 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3431 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3435 if (VAL_14_BITS_P (disp))
3437 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3438 plus_constant (gen_rtx_REG (Pmode, base), disp));
3440 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3442 rtx basereg = gen_rtx_REG (Pmode, base);
3443 rtx delta = GEN_INT (disp);
3444 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3446 emit_move_insn (tmpreg, delta);
3447 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3448 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3451 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3452 gen_rtx_SET (VOIDmode, tmpreg,
3453 gen_rtx_PLUS (Pmode, basereg, delta)),
3458 rtx basereg = gen_rtx_REG (Pmode, base);
3459 rtx delta = GEN_INT (disp);
3460 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3462 emit_move_insn (tmpreg,
3463 gen_rtx_PLUS (Pmode, basereg,
3464 gen_rtx_HIGH (Pmode, delta)));
3465 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3466 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3469 if (DO_FRAME_NOTES && note)
3470 RTX_FRAME_RELATED_P (insn) = 1;
3474 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3479 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3480 be consistent with the rounding and size calculation done here.
3481 Change them at the same time. */
3483 /* We do our own stack alignment. First, round the size of the
3484 stack locals up to a word boundary. */
3485 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3487 /* Space for previous frame pointer + filler. If any frame is
3488 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3489 waste some space here for the sake of HP compatibility. The
3490 first slot is only used when the frame pointer is needed. */
3491 if (size || frame_pointer_needed)
3492 size += STARTING_FRAME_OFFSET;
3494 /* If the current function calls __builtin_eh_return, then we need
3495 to allocate stack space for registers that will hold data for
3496 the exception handler. */
3497 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3501 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3503 size += i * UNITS_PER_WORD;
3506 /* Account for space used by the callee general register saves. */
3507 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3508 if (df_regs_ever_live_p (i))
3509 size += UNITS_PER_WORD;
3511 /* Account for space used by the callee floating point register saves. */
3512 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3513 if (df_regs_ever_live_p (i)
3514 || (!TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3518 /* We always save both halves of the FP register, so always
3519 increment the frame size by 8 bytes. */
3523 /* If any of the floating registers are saved, account for the
3524 alignment needed for the floating point register save block. */
3527 size = (size + 7) & ~7;
3532 /* The various ABIs include space for the outgoing parameters in the
3533 size of the current function's stack frame. We don't need to align
3534 for the outgoing arguments as their alignment is set by the final
3535 rounding for the frame as a whole. */
3536 size += current_function_outgoing_args_size;
3538 /* Allocate space for the fixed frame marker. This space must be
3539 allocated for any function that makes calls or allocates
3541 if (!current_function_is_leaf || size)
3542 size += TARGET_64BIT ? 48 : 32;
3544 /* Finally, round to the preferred stack boundary. */
3545 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3546 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3549 /* Generate the assembly code for function entry. FILE is a stdio
3550 stream to output the code to. SIZE is an int: how many units of
3551 temporary storage to allocate.
3553 Refer to the array `regs_ever_live' to determine which registers to
3554 save; `regs_ever_live[I]' is nonzero if register number I is ever
3555 used in the function. This function is responsible for knowing
3556 which registers should not be saved even if used. */
3558 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3559 of memory. If any fpu reg is used in the function, we allocate
3560 such a block here, at the bottom of the frame, just in case it's needed.
3562 If this function is a leaf procedure, then we may choose not
3563 to do a "save" insn. The decision about whether or not
3564 to do this is made in regclass.c. */
3567 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3569 /* The function's label and associated .PROC must never be
3570 separated and must be output *after* any profiling declarations
3571 to avoid changing spaces/subspaces within a procedure. */
3572 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3573 fputs ("\t.PROC\n", file);
3575 /* hppa_expand_prologue does the dirty work now. We just need
3576 to output the assembler directives which denote the start
3578 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3579 if (current_function_is_leaf)
3580 fputs (",NO_CALLS", file);
3582 fputs (",CALLS", file);
3584 fputs (",SAVE_RP", file);
3586 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3587 at the beginning of the frame and that it is used as the frame
3588 pointer for the frame. We do this because our current frame
3589 layout doesn't conform to that specified in the HP runtime
3590 documentation and we need a way to indicate to programs such as
3591 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3592 isn't used by HP compilers but is supported by the assembler.
3593 However, SAVE_SP is supposed to indicate that the previous stack
3594 pointer has been saved in the frame marker. */
3595 if (frame_pointer_needed)
3596 fputs (",SAVE_SP", file);
3598 /* Pass on information about the number of callee register saves
3599 performed in the prologue.
3601 The compiler is supposed to pass the highest register number
3602 saved, the assembler then has to adjust that number before
3603 entering it into the unwind descriptor (to account for any
3604 caller saved registers with lower register numbers than the
3605 first callee saved register). */
3607 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3610 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3612 fputs ("\n\t.ENTRY\n", file);
3614 remove_useless_addtr_insns (0);
3618 hppa_expand_prologue (void)
3620 int merge_sp_adjust_with_store = 0;
3621 HOST_WIDE_INT size = get_frame_size ();
3622 HOST_WIDE_INT offset;
3630 /* Compute total size for frame pointer, filler, locals and rounding to
3631 the next word boundary. Similar code appears in compute_frame_size
3632 and must be changed in tandem with this code. */
3633 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3634 if (local_fsize || frame_pointer_needed)
3635 local_fsize += STARTING_FRAME_OFFSET;
3637 actual_fsize = compute_frame_size (size, &save_fregs);
3639 /* Compute a few things we will use often. */
3640 tmpreg = gen_rtx_REG (word_mode, 1);
3642 /* Save RP first. The calling conventions manual states RP will
3643 always be stored into the caller's frame at sp - 20 or sp - 16
3644 depending on which ABI is in use. */
3645 if (df_regs_ever_live_p (2) || current_function_calls_eh_return)
3647 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3653 /* Allocate the local frame and set up the frame pointer if needed. */
3654 if (actual_fsize != 0)
3656 if (frame_pointer_needed)
3658 /* Copy the old frame pointer temporarily into %r1. Set up the
3659 new stack pointer, then store away the saved old frame pointer
3660 into the stack at sp and at the same time update the stack
3661 pointer by actual_fsize bytes. Two versions, first
3662 handles small (<8k) frames. The second handles large (>=8k)
3664 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3666 RTX_FRAME_RELATED_P (insn) = 1;
3668 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3670 RTX_FRAME_RELATED_P (insn) = 1;
3672 if (VAL_14_BITS_P (actual_fsize))
3673 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3676 /* It is incorrect to store the saved frame pointer at *sp,
3677 then increment sp (writes beyond the current stack boundary).
3679 So instead use stwm to store at *sp and post-increment the
3680 stack pointer as an atomic operation. Then increment sp to
3681 finish allocating the new frame. */
3682 HOST_WIDE_INT adjust1 = 8192 - 64;
3683 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3685 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3686 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3690 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3691 we need to store the previous stack pointer (frame pointer)
3692 into the frame marker on targets that use the HP unwind
3693 library. This allows the HP unwind library to be used to
3694 unwind GCC frames. However, we are not fully compatible
3695 with the HP library because our frame layout differs from
3696 that specified in the HP runtime specification.
3698 We don't want a frame note on this instruction as the frame
3699 marker moves during dynamic stack allocation.
3701 This instruction also serves as a blockage to prevent
3702 register spills from being scheduled before the stack
3703 pointer is raised. This is necessary as we store
3704 registers using the frame pointer as a base register,
3705 and the frame pointer is set before sp is raised. */
3706 if (TARGET_HPUX_UNWIND_LIBRARY)
3708 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3709 GEN_INT (TARGET_64BIT ? -8 : -4));
3711 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3715 emit_insn (gen_blockage ());
3717 /* no frame pointer needed. */
3720 /* In some cases we can perform the first callee register save
3721 and allocating the stack frame at the same time. If so, just
3722 make a note of it and defer allocating the frame until saving
3723 the callee registers. */
3724 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3725 merge_sp_adjust_with_store = 1;
3726 /* Can not optimize. Adjust the stack frame by actual_fsize
3729 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3734 /* Normal register save.
3736 Do not save the frame pointer in the frame_pointer_needed case. It
3737 was done earlier. */
3738 if (frame_pointer_needed)
3740 offset = local_fsize;
3742 /* Saving the EH return data registers in the frame is the simplest
3743 way to get the frame unwind information emitted. We put them
3744 just before the general registers. */
3745 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3747 unsigned int i, regno;
3751 regno = EH_RETURN_DATA_REGNO (i);
3752 if (regno == INVALID_REGNUM)
3755 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3756 offset += UNITS_PER_WORD;
3760 for (i = 18; i >= 4; i--)
3761 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3763 store_reg (i, offset, FRAME_POINTER_REGNUM);
3764 offset += UNITS_PER_WORD;
3767 /* Account for %r3 which is saved in a special place. */
3770 /* No frame pointer needed. */
3773 offset = local_fsize - actual_fsize;
3775 /* Saving the EH return data registers in the frame is the simplest
3776 way to get the frame unwind information emitted. */
3777 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3779 unsigned int i, regno;
3783 regno = EH_RETURN_DATA_REGNO (i);
3784 if (regno == INVALID_REGNUM)
3787 /* If merge_sp_adjust_with_store is nonzero, then we can
3788 optimize the first save. */
3789 if (merge_sp_adjust_with_store)
3791 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3792 merge_sp_adjust_with_store = 0;
3795 store_reg (regno, offset, STACK_POINTER_REGNUM);
3796 offset += UNITS_PER_WORD;
3800 for (i = 18; i >= 3; i--)
3801 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3803 /* If merge_sp_adjust_with_store is nonzero, then we can
3804 optimize the first GR save. */
3805 if (merge_sp_adjust_with_store)
3807 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3808 merge_sp_adjust_with_store = 0;
3811 store_reg (i, offset, STACK_POINTER_REGNUM);
3812 offset += UNITS_PER_WORD;
3816 /* If we wanted to merge the SP adjustment with a GR save, but we never
3817 did any GR saves, then just emit the adjustment here. */
3818 if (merge_sp_adjust_with_store)
3819 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3823 /* The hppa calling conventions say that %r19, the pic offset
3824 register, is saved at sp - 32 (in this function's frame)
3825 when generating PIC code. FIXME: What is the correct thing
3826 to do for functions which make no calls and allocate no
3827 frame? Do we need to allocate a frame, or can we just omit
3828 the save? For now we'll just omit the save.
3830 We don't want a note on this insn as the frame marker can
3831 move if there is a dynamic stack allocation. */
3832 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3834 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3836 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3840 /* Align pointer properly (doubleword boundary). */
3841 offset = (offset + 7) & ~7;
3843 /* Floating point register store. */
3848 /* First get the frame or stack pointer to the start of the FP register
3850 if (frame_pointer_needed)
3852 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3853 base = frame_pointer_rtx;
3857 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3858 base = stack_pointer_rtx;
3861 /* Now actually save the FP registers. */
3862 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3864 if (df_regs_ever_live_p (i)
3865 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3867 rtx addr, insn, reg;
3868 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3869 reg = gen_rtx_REG (DFmode, i);
3870 insn = emit_move_insn (addr, reg);
3873 RTX_FRAME_RELATED_P (insn) = 1;
3876 rtx mem = gen_rtx_MEM (DFmode,
3877 plus_constant (base, offset));
3879 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3880 gen_rtx_SET (VOIDmode, mem, reg),
3885 rtx meml = gen_rtx_MEM (SFmode,
3886 plus_constant (base, offset));
3887 rtx memr = gen_rtx_MEM (SFmode,
3888 plus_constant (base, offset + 4));
3889 rtx regl = gen_rtx_REG (SFmode, i);
3890 rtx regr = gen_rtx_REG (SFmode, i + 1);
3891 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3892 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3895 RTX_FRAME_RELATED_P (setl) = 1;
3896 RTX_FRAME_RELATED_P (setr) = 1;
3897 vec = gen_rtvec (2, setl, setr);
3899 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3900 gen_rtx_SEQUENCE (VOIDmode, vec),
3904 offset += GET_MODE_SIZE (DFmode);
3911 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3912 Handle case where DISP > 8k by using the add_high_const patterns. */
3915 load_reg (int reg, HOST_WIDE_INT disp, int base)
3917 rtx dest = gen_rtx_REG (word_mode, reg);
3918 rtx basereg = gen_rtx_REG (Pmode, base);
3921 if (VAL_14_BITS_P (disp))
3922 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3923 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3925 rtx delta = GEN_INT (disp);
3926 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3928 emit_move_insn (tmpreg, delta);
3929 if (TARGET_DISABLE_INDEXING)
3931 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3932 src = gen_rtx_MEM (word_mode, tmpreg);
3935 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3939 rtx delta = GEN_INT (disp);
3940 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3941 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3943 emit_move_insn (tmpreg, high);
3944 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3947 emit_move_insn (dest, src);
3950 /* Update the total code bytes output to the text section. */
3953 update_total_code_bytes (int nbytes)
3955 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3956 && !IN_NAMED_SECTION_P (cfun->decl))
3958 if (INSN_ADDRESSES_SET_P ())
3960 unsigned long old_total = total_code_bytes;
3962 total_code_bytes += nbytes;
3964 /* Be prepared to handle overflows. */
3965 if (old_total > total_code_bytes)
3966 total_code_bytes = -1;
3969 total_code_bytes = -1;
3973 /* This function generates the assembly code for function exit.
3974 Args are as for output_function_prologue ().
3976 The function epilogue should not depend on the current stack
3977 pointer! It should use the frame pointer only. This is mandatory
3978 because of alloca; we also take advantage of it to omit stack
3979 adjustments before returning. */
3982 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3984 rtx insn = get_last_insn ();
3988 /* hppa_expand_epilogue does the dirty work now. We just need
3989 to output the assembler directives which denote the end
3992 To make debuggers happy, emit a nop if the epilogue was completely
3993 eliminated due to a volatile call as the last insn in the
3994 current function. That way the return address (in %r2) will
3995 always point to a valid instruction in the current function. */
3997 /* Get the last real insn. */
3998 if (GET_CODE (insn) == NOTE)
3999 insn = prev_real_insn (insn);
4001 /* If it is a sequence, then look inside. */
4002 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4003 insn = XVECEXP (PATTERN (insn), 0, 0);
4005 /* If insn is a CALL_INSN, then it must be a call to a volatile
4006 function (otherwise there would be epilogue insns). */
4007 if (insn && GET_CODE (insn) == CALL_INSN)
4009 fputs ("\tnop\n", file);
4013 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4015 if (TARGET_SOM && TARGET_GAS)
4017 /* We done with this subspace except possibly for some additional
4018 debug information. Forget that we are in this subspace to ensure
4019 that the next function is output in its own subspace. */
4021 cfun->machine->in_nsubspa = 2;
4024 if (INSN_ADDRESSES_SET_P ())
4026 insn = get_last_nonnote_insn ();
4027 last_address += INSN_ADDRESSES (INSN_UID (insn));
4029 last_address += insn_default_length (insn);
4030 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4031 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4034 /* Finally, update the total number of code bytes output so far. */
4035 update_total_code_bytes (last_address);
4039 hppa_expand_epilogue (void)
4042 HOST_WIDE_INT offset;
4043 HOST_WIDE_INT ret_off = 0;
4045 int merge_sp_adjust_with_load = 0;
4047 /* We will use this often. */
4048 tmpreg = gen_rtx_REG (word_mode, 1);
4050 /* Try to restore RP early to avoid load/use interlocks when
4051 RP gets used in the return (bv) instruction. This appears to still
4052 be necessary even when we schedule the prologue and epilogue. */
4055 ret_off = TARGET_64BIT ? -16 : -20;
4056 if (frame_pointer_needed)
4058 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4063 /* No frame pointer, and stack is smaller than 8k. */
4064 if (VAL_14_BITS_P (ret_off - actual_fsize))
4066 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4072 /* General register restores. */
4073 if (frame_pointer_needed)
4075 offset = local_fsize;
4077 /* If the current function calls __builtin_eh_return, then we need
4078 to restore the saved EH data registers. */
4079 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4081 unsigned int i, regno;
4085 regno = EH_RETURN_DATA_REGNO (i);
4086 if (regno == INVALID_REGNUM)
4089 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4090 offset += UNITS_PER_WORD;
4094 for (i = 18; i >= 4; i--)
4095 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4097 load_reg (i, offset, FRAME_POINTER_REGNUM);
4098 offset += UNITS_PER_WORD;
4103 offset = local_fsize - actual_fsize;
4105 /* If the current function calls __builtin_eh_return, then we need
4106 to restore the saved EH data registers. */
4107 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4109 unsigned int i, regno;
4113 regno = EH_RETURN_DATA_REGNO (i);
4114 if (regno == INVALID_REGNUM)
4117 /* Only for the first load.
4118 merge_sp_adjust_with_load holds the register load
4119 with which we will merge the sp adjustment. */
4120 if (merge_sp_adjust_with_load == 0
4122 && VAL_14_BITS_P (-actual_fsize))
4123 merge_sp_adjust_with_load = regno;
4125 load_reg (regno, offset, STACK_POINTER_REGNUM);
4126 offset += UNITS_PER_WORD;
4130 for (i = 18; i >= 3; i--)
4132 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4134 /* Only for the first load.
4135 merge_sp_adjust_with_load holds the register load
4136 with which we will merge the sp adjustment. */
4137 if (merge_sp_adjust_with_load == 0
4139 && VAL_14_BITS_P (-actual_fsize))
4140 merge_sp_adjust_with_load = i;
4142 load_reg (i, offset, STACK_POINTER_REGNUM);
4143 offset += UNITS_PER_WORD;
4148 /* Align pointer properly (doubleword boundary). */
4149 offset = (offset + 7) & ~7;
4151 /* FP register restores. */
4154 /* Adjust the register to index off of. */
4155 if (frame_pointer_needed)
4156 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4158 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4160 /* Actually do the restores now. */
4161 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4162 if (df_regs_ever_live_p (i)
4163 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4165 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4166 rtx dest = gen_rtx_REG (DFmode, i);
4167 emit_move_insn (dest, src);
4171 /* Emit a blockage insn here to keep these insns from being moved to
4172 an earlier spot in the epilogue, or into the main instruction stream.
4174 This is necessary as we must not cut the stack back before all the
4175 restores are finished. */
4176 emit_insn (gen_blockage ());
4178 /* Reset stack pointer (and possibly frame pointer). The stack
4179 pointer is initially set to fp + 64 to avoid a race condition. */
4180 if (frame_pointer_needed)
4182 rtx delta = GEN_INT (-64);
4184 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4185 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4187 /* If we were deferring a callee register restore, do it now. */
4188 else if (merge_sp_adjust_with_load)
4190 rtx delta = GEN_INT (-actual_fsize);
4191 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4193 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4195 else if (actual_fsize != 0)
4196 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4199 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4200 frame greater than 8k), do so now. */
4202 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4204 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4206 rtx sa = EH_RETURN_STACKADJ_RTX;
4208 emit_insn (gen_blockage ());
4209 emit_insn (TARGET_64BIT
4210 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4211 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4216 hppa_pic_save_rtx (void)
4218 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4221 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4222 #define NO_DEFERRED_PROFILE_COUNTERS 0
4226 /* Vector of funcdef numbers. */
4227 static VEC(int,heap) *funcdef_nos;
4229 /* Output deferred profile counters. */
4231 output_deferred_profile_counters (void)
4236 if (VEC_empty (int, funcdef_nos))
4239 switch_to_section (data_section);
4240 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4241 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4243 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4245 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4246 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4249 VEC_free (int, heap, funcdef_nos);
4253 hppa_profile_hook (int label_no)
4255 /* We use SImode for the address of the function in both 32 and
4256 64-bit code to avoid having to provide DImode versions of the
4257 lcla2 and load_offset_label_address insn patterns. */
4258 rtx reg = gen_reg_rtx (SImode);
4259 rtx label_rtx = gen_label_rtx ();
4260 rtx begin_label_rtx, call_insn;
4261 char begin_label_name[16];
4263 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4265 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4268 emit_move_insn (arg_pointer_rtx,
4269 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4272 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4274 /* The address of the function is loaded into %r25 with an instruction-
4275 relative sequence that avoids the use of relocations. The sequence
4276 is split so that the load_offset_label_address instruction can
4277 occupy the delay slot of the call to _mcount. */
4279 emit_insn (gen_lcla2 (reg, label_rtx));
4281 emit_insn (gen_lcla1 (reg, label_rtx));
4283 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4284 reg, begin_label_rtx, label_rtx));
4286 #if !NO_DEFERRED_PROFILE_COUNTERS
4288 rtx count_label_rtx, addr, r24;
4289 char count_label_name[16];
4291 VEC_safe_push (int, heap, funcdef_nos, label_no);
4292 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4293 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4295 addr = force_reg (Pmode, count_label_rtx);
4296 r24 = gen_rtx_REG (Pmode, 24);
4297 emit_move_insn (r24, addr);
4300 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4301 gen_rtx_SYMBOL_REF (Pmode,
4303 GEN_INT (TARGET_64BIT ? 24 : 12)));
4305 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4310 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4311 gen_rtx_SYMBOL_REF (Pmode,
4313 GEN_INT (TARGET_64BIT ? 16 : 8)));
4317 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4318 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4320 /* Indicate the _mcount call cannot throw, nor will it execute a
4322 REG_NOTES (call_insn)
4323 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4326 /* Fetch the return address for the frame COUNT steps up from
4327 the current frame, after the prologue. FRAMEADDR is the
4328 frame pointer of the COUNT frame.
4330 We want to ignore any export stub remnants here. To handle this,
4331 we examine the code at the return address, and if it is an export
4332 stub, we return a memory rtx for the stub return address stored
4335 The value returned is used in two different ways:
4337 1. To find a function's caller.
4339 2. To change the return address for a function.
4341 This function handles most instances of case 1; however, it will
4342 fail if there are two levels of stubs to execute on the return
4343 path. The only way I believe that can happen is if the return value
4344 needs a parameter relocation, which never happens for C code.
4346 This function handles most instances of case 2; however, it will
4347 fail if we did not originally have stub code on the return path
4348 but will need stub code on the new return path. This can happen if
4349 the caller & callee are both in the main program, but the new
4350 return location is in a shared library. */
4353 return_addr_rtx (int count, rtx frameaddr)
4363 rp = get_hard_reg_initial_val (Pmode, 2);
4365 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4368 saved_rp = gen_reg_rtx (Pmode);
4369 emit_move_insn (saved_rp, rp);
4371 /* Get pointer to the instruction stream. We have to mask out the
4372 privilege level from the two low order bits of the return address
4373 pointer here so that ins will point to the start of the first
4374 instruction that would have been executed if we returned. */
4375 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4376 label = gen_label_rtx ();
4378 /* Check the instruction stream at the normal return address for the
4381 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4382 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4383 0x00011820 | stub+16: mtsp r1,sr0
4384 0xe0400002 | stub+20: be,n 0(sr0,rp)
4386 If it is an export stub, than our return address is really in
4389 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4390 NULL_RTX, SImode, 1);
4391 emit_jump_insn (gen_bne (label));
4393 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4394 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4395 emit_jump_insn (gen_bne (label));
4397 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4398 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4399 emit_jump_insn (gen_bne (label));
4401 /* 0xe0400002 must be specified as -532676606 so that it won't be
4402 rejected as an invalid immediate operand on 64-bit hosts. */
4403 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4404 GEN_INT (-532676606), NE, NULL_RTX, SImode, 1);
4406 /* If there is no export stub then just use the value saved from
4407 the return pointer register. */
4409 emit_jump_insn (gen_bne (label));
4411 /* Here we know that our return address points to an export
4412 stub. We don't want to return the address of the export stub,
4413 but rather the return address of the export stub. That return
4414 address is stored at -24[frameaddr]. */
4416 emit_move_insn (saved_rp,
4418 memory_address (Pmode,
4419 plus_constant (frameaddr,
4427 emit_bcond_fp (enum rtx_code code, rtx operand0)
4429 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4430 gen_rtx_IF_THEN_ELSE (VOIDmode,
4431 gen_rtx_fmt_ee (code,
4433 gen_rtx_REG (CCFPmode, 0),
4435 gen_rtx_LABEL_REF (VOIDmode, operand0),
4441 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4443 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4444 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4447 /* Adjust the cost of a scheduling dependency. Return the new cost of
4448 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4451 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4453 enum attr_type attr_type;
4455 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4456 true dependencies as they are described with bypasses now. */
4457 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4460 if (! recog_memoized (insn))
4463 attr_type = get_attr_type (insn);
4465 switch (REG_NOTE_KIND (link))
4468 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4471 if (attr_type == TYPE_FPLOAD)
4473 rtx pat = PATTERN (insn);
4474 rtx dep_pat = PATTERN (dep_insn);
4475 if (GET_CODE (pat) == PARALLEL)
4477 /* This happens for the fldXs,mb patterns. */
4478 pat = XVECEXP (pat, 0, 0);
4480 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4481 /* If this happens, we have to extend this to schedule
4482 optimally. Return 0 for now. */
4485 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4487 if (! recog_memoized (dep_insn))
4489 switch (get_attr_type (dep_insn))
4496 case TYPE_FPSQRTSGL:
4497 case TYPE_FPSQRTDBL:
4498 /* A fpload can't be issued until one cycle before a
4499 preceding arithmetic operation has finished if
4500 the target of the fpload is any of the sources
4501 (or destination) of the arithmetic operation. */
4502 return insn_default_latency (dep_insn) - 1;
4509 else if (attr_type == TYPE_FPALU)
4511 rtx pat = PATTERN (insn);
4512 rtx dep_pat = PATTERN (dep_insn);
4513 if (GET_CODE (pat) == PARALLEL)
4515 /* This happens for the fldXs,mb patterns. */
4516 pat = XVECEXP (pat, 0, 0);
4518 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4519 /* If this happens, we have to extend this to schedule
4520 optimally. Return 0 for now. */
4523 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4525 if (! recog_memoized (dep_insn))
4527 switch (get_attr_type (dep_insn))
4531 case TYPE_FPSQRTSGL:
4532 case TYPE_FPSQRTDBL:
4533 /* An ALU flop can't be issued until two cycles before a
4534 preceding divide or sqrt operation has finished if
4535 the target of the ALU flop is any of the sources
4536 (or destination) of the divide or sqrt operation. */
4537 return insn_default_latency (dep_insn) - 2;
4545 /* For other anti dependencies, the cost is 0. */
4548 case REG_DEP_OUTPUT:
4549 /* Output dependency; DEP_INSN writes a register that INSN writes some
4551 if (attr_type == TYPE_FPLOAD)
4553 rtx pat = PATTERN (insn);
4554 rtx dep_pat = PATTERN (dep_insn);
4555 if (GET_CODE (pat) == PARALLEL)
4557 /* This happens for the fldXs,mb patterns. */
4558 pat = XVECEXP (pat, 0, 0);
4560 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4561 /* If this happens, we have to extend this to schedule
4562 optimally. Return 0 for now. */
4565 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4567 if (! recog_memoized (dep_insn))
4569 switch (get_attr_type (dep_insn))
4576 case TYPE_FPSQRTSGL:
4577 case TYPE_FPSQRTDBL:
4578 /* A fpload can't be issued until one cycle before a
4579 preceding arithmetic operation has finished if
4580 the target of the fpload is the destination of the
4581 arithmetic operation.
4583 Exception: For PA7100LC, PA7200 and PA7300, the cost
4584 is 3 cycles, unless they bundle together. We also
4585 pay the penalty if the second insn is a fpload. */
4586 return insn_default_latency (dep_insn) - 1;
4593 else if (attr_type == TYPE_FPALU)
4595 rtx pat = PATTERN (insn);
4596 rtx dep_pat = PATTERN (dep_insn);
4597 if (GET_CODE (pat) == PARALLEL)
4599 /* This happens for the fldXs,mb patterns. */
4600 pat = XVECEXP (pat, 0, 0);
4602 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4603 /* If this happens, we have to extend this to schedule
4604 optimally. Return 0 for now. */
4607 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4609 if (! recog_memoized (dep_insn))
4611 switch (get_attr_type (dep_insn))
4615 case TYPE_FPSQRTSGL:
4616 case TYPE_FPSQRTDBL:
4617 /* An ALU flop can't be issued until two cycles before a
4618 preceding divide or sqrt operation has finished if
4619 the target of the ALU flop is also the target of
4620 the divide or sqrt operation. */
4621 return insn_default_latency (dep_insn) - 2;
4629 /* For other output dependencies, the cost is 0. */
4637 /* Adjust scheduling priorities. We use this to try and keep addil
4638 and the next use of %r1 close together. */
4640 pa_adjust_priority (rtx insn, int priority)
4642 rtx set = single_set (insn);
4646 src = SET_SRC (set);
4647 dest = SET_DEST (set);
4648 if (GET_CODE (src) == LO_SUM
4649 && symbolic_operand (XEXP (src, 1), VOIDmode)
4650 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4653 else if (GET_CODE (src) == MEM
4654 && GET_CODE (XEXP (src, 0)) == LO_SUM
4655 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4656 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4659 else if (GET_CODE (dest) == MEM
4660 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4661 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4662 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4668 /* The 700 can only issue a single insn at a time.
4669 The 7XXX processors can issue two insns at a time.
4670 The 8000 can issue 4 insns at a time. */
4672 pa_issue_rate (void)
4676 case PROCESSOR_700: return 1;
4677 case PROCESSOR_7100: return 2;
4678 case PROCESSOR_7100LC: return 2;
4679 case PROCESSOR_7200: return 2;
4680 case PROCESSOR_7300: return 2;
4681 case PROCESSOR_8000: return 4;
4690 /* Return any length adjustment needed by INSN which already has its length
4691 computed as LENGTH. Return zero if no adjustment is necessary.
4693 For the PA: function calls, millicode calls, and backwards short
4694 conditional branches with unfilled delay slots need an adjustment by +1
4695 (to account for the NOP which will be inserted into the instruction stream).
4697 Also compute the length of an inline block move here as it is too
4698 complicated to express as a length attribute in pa.md. */
4700 pa_adjust_insn_length (rtx insn, int length)
4702 rtx pat = PATTERN (insn);
4704 /* Jumps inside switch tables which have unfilled delay slots need
4706 if (GET_CODE (insn) == JUMP_INSN
4707 && GET_CODE (pat) == PARALLEL
4708 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4710 /* Millicode insn with an unfilled delay slot. */
4711 else if (GET_CODE (insn) == INSN
4712 && GET_CODE (pat) != SEQUENCE
4713 && GET_CODE (pat) != USE
4714 && GET_CODE (pat) != CLOBBER
4715 && get_attr_type (insn) == TYPE_MILLI)
4717 /* Block move pattern. */
4718 else if (GET_CODE (insn) == INSN
4719 && GET_CODE (pat) == PARALLEL
4720 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4721 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4722 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4723 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4724 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4725 return compute_movmem_length (insn) - 4;
4726 /* Block clear pattern. */
4727 else if (GET_CODE (insn) == INSN
4728 && GET_CODE (pat) == PARALLEL
4729 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4730 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4731 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4732 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4733 return compute_clrmem_length (insn) - 4;
4734 /* Conditional branch with an unfilled delay slot. */
4735 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4737 /* Adjust a short backwards conditional with an unfilled delay slot. */
4738 if (GET_CODE (pat) == SET
4740 && ! forward_branch_p (insn))
4742 else if (GET_CODE (pat) == PARALLEL
4743 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4746 /* Adjust dbra insn with short backwards conditional branch with
4747 unfilled delay slot -- only for case where counter is in a
4748 general register register. */
4749 else if (GET_CODE (pat) == PARALLEL
4750 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4751 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4752 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4754 && ! forward_branch_p (insn))
4762 /* Print operand X (an rtx) in assembler syntax to file FILE.
4763 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4764 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4767 print_operand (FILE *file, rtx x, int code)
4772 /* Output a 'nop' if there's nothing for the delay slot. */
4773 if (dbr_sequence_length () == 0)
4774 fputs ("\n\tnop", file);
4777 /* Output a nullification completer if there's nothing for the */
4778 /* delay slot or nullification is requested. */
4779 if (dbr_sequence_length () == 0 ||
4781 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4785 /* Print out the second register name of a register pair.
4786 I.e., R (6) => 7. */
4787 fputs (reg_names[REGNO (x) + 1], file);
4790 /* A register or zero. */
4792 || (x == CONST0_RTX (DFmode))
4793 || (x == CONST0_RTX (SFmode)))
4795 fputs ("%r0", file);
4801 /* A register or zero (floating point). */
4803 || (x == CONST0_RTX (DFmode))
4804 || (x == CONST0_RTX (SFmode)))
4806 fputs ("%fr0", file);
4815 xoperands[0] = XEXP (XEXP (x, 0), 0);
4816 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4817 output_global_address (file, xoperands[1], 0);
4818 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4822 case 'C': /* Plain (C)ondition */
4824 switch (GET_CODE (x))
4827 fputs ("=", file); break;
4829 fputs ("<>", file); break;
4831 fputs (">", file); break;
4833 fputs (">=", file); break;
4835 fputs (">>=", file); break;
4837 fputs (">>", file); break;
4839 fputs ("<", file); break;
4841 fputs ("<=", file); break;
4843 fputs ("<<=", file); break;
4845 fputs ("<<", file); break;
4850 case 'N': /* Condition, (N)egated */
4851 switch (GET_CODE (x))
4854 fputs ("<>", file); break;
4856 fputs ("=", file); break;
4858 fputs ("<=", file); break;
4860 fputs ("<", file); break;
4862 fputs ("<<", file); break;
4864 fputs ("<<=", file); break;
4866 fputs (">=", file); break;
4868 fputs (">", file); break;
4870 fputs (">>", file); break;
4872 fputs (">>=", file); break;
4877 /* For floating point comparisons. Note that the output
4878 predicates are the complement of the desired mode. The
4879 conditions for GT, GE, LT, LE and LTGT cause an invalid
4880 operation exception if the result is unordered and this
4881 exception is enabled in the floating-point status register. */
4883 switch (GET_CODE (x))
4886 fputs ("!=", file); break;
4888 fputs ("=", file); break;
4890 fputs ("!>", file); break;
4892 fputs ("!>=", file); break;
4894 fputs ("!<", file); break;
4896 fputs ("!<=", file); break;
4898 fputs ("!<>", file); break;
4900 fputs ("!?<=", file); break;
4902 fputs ("!?<", file); break;
4904 fputs ("!?>=", file); break;
4906 fputs ("!?>", file); break;
4908 fputs ("!?=", file); break;
4910 fputs ("!?", file); break;
4912 fputs ("?", file); break;
4917 case 'S': /* Condition, operands are (S)wapped. */
4918 switch (GET_CODE (x))
4921 fputs ("=", file); break;
4923 fputs ("<>", file); break;
4925 fputs ("<", file); break;
4927 fputs ("<=", file); break;
4929 fputs ("<<=", file); break;
4931 fputs ("<<", file); break;
4933 fputs (">", file); break;
4935 fputs (">=", file); break;
4937 fputs (">>=", file); break;
4939 fputs (">>", file); break;
4944 case 'B': /* Condition, (B)oth swapped and negate. */
4945 switch (GET_CODE (x))
4948 fputs ("<>", file); break;
4950 fputs ("=", file); break;
4952 fputs (">=", file); break;
4954 fputs (">", file); break;
4956 fputs (">>", file); break;
4958 fputs (">>=", file); break;
4960 fputs ("<=", file); break;
4962 fputs ("<", file); break;
4964 fputs ("<<", file); break;
4966 fputs ("<<=", file); break;
4972 gcc_assert (GET_CODE (x) == CONST_INT);
4973 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4976 gcc_assert (GET_CODE (x) == CONST_INT);
4977 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4980 gcc_assert (GET_CODE (x) == CONST_INT);
4981 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4984 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
4985 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4988 gcc_assert (GET_CODE (x) == CONST_INT);
4989 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4992 gcc_assert (GET_CODE (x) == CONST_INT);
4993 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4996 if (GET_CODE (x) == CONST_INT)
5001 switch (GET_CODE (XEXP (x, 0)))
5005 if (ASSEMBLER_DIALECT == 0)
5006 fputs ("s,mb", file);
5008 fputs (",mb", file);
5012 if (ASSEMBLER_DIALECT == 0)
5013 fputs ("s,ma", file);
5015 fputs (",ma", file);
5018 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5019 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5021 if (ASSEMBLER_DIALECT == 0)
5024 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5025 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5027 if (ASSEMBLER_DIALECT == 0)
5028 fputs ("x,s", file);
5032 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5036 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5042 output_global_address (file, x, 0);
5045 output_global_address (file, x, 1);
5047 case 0: /* Don't do anything special */
5052 compute_zdepwi_operands (INTVAL (x), op);
5053 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5059 compute_zdepdi_operands (INTVAL (x), op);
5060 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5064 /* We can get here from a .vtable_inherit due to our
5065 CONSTANT_ADDRESS_P rejecting perfectly good constant
5071 if (GET_CODE (x) == REG)
5073 fputs (reg_names [REGNO (x)], file);
5074 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5080 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5081 && (REGNO (x) & 1) == 0)
5084 else if (GET_CODE (x) == MEM)
5086 int size = GET_MODE_SIZE (GET_MODE (x));
5087 rtx base = NULL_RTX;
5088 switch (GET_CODE (XEXP (x, 0)))
5092 base = XEXP (XEXP (x, 0), 0);
5093 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5097 base = XEXP (XEXP (x, 0), 0);
5098 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5101 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5102 fprintf (file, "%s(%s)",
5103 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5104 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5105 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5106 fprintf (file, "%s(%s)",
5107 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5108 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5109 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5110 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5112 /* Because the REG_POINTER flag can get lost during reload,
5113 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5114 index and base registers in the combined move patterns. */
5115 rtx base = XEXP (XEXP (x, 0), 1);
5116 rtx index = XEXP (XEXP (x, 0), 0);
5118 fprintf (file, "%s(%s)",
5119 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5122 output_address (XEXP (x, 0));
5125 output_address (XEXP (x, 0));
5130 output_addr_const (file, x);
5133 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5136 output_global_address (FILE *file, rtx x, int round_constant)
5139 /* Imagine (high (const (plus ...))). */
5140 if (GET_CODE (x) == HIGH)
5143 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5144 output_addr_const (file, x);
5145 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5147 output_addr_const (file, x);
5148 fputs ("-$global$", file);
5150 else if (GET_CODE (x) == CONST)
5152 const char *sep = "";
5153 int offset = 0; /* assembler wants -$global$ at end */
5154 rtx base = NULL_RTX;
5156 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5159 base = XEXP (XEXP (x, 0), 0);
5160 output_addr_const (file, base);
5163 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5169 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5172 base = XEXP (XEXP (x, 0), 1);
5173 output_addr_const (file, base);
5176 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5182 /* How bogus. The compiler is apparently responsible for
5183 rounding the constant if it uses an LR field selector.
5185 The linker and/or assembler seem a better place since
5186 they have to do this kind of thing already.
5188 If we fail to do this, HP's optimizing linker may eliminate
5189 an addil, but not update the ldw/stw/ldo instruction that
5190 uses the result of the addil. */
5192 offset = ((offset + 0x1000) & ~0x1fff);
5194 switch (GET_CODE (XEXP (x, 0)))
5207 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5215 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5216 fputs ("-$global$", file);
5218 fprintf (file, "%s%d", sep, offset);
5221 output_addr_const (file, x);
5224 /* Output boilerplate text to appear at the beginning of the file.
5225 There are several possible versions. */
5226 #define aputs(x) fputs(x, asm_out_file)
5228 pa_file_start_level (void)
5231 aputs ("\t.LEVEL 2.0w\n");
5232 else if (TARGET_PA_20)
5233 aputs ("\t.LEVEL 2.0\n");
5234 else if (TARGET_PA_11)
5235 aputs ("\t.LEVEL 1.1\n");
5237 aputs ("\t.LEVEL 1.0\n");
5241 pa_file_start_space (int sortspace)
5243 aputs ("\t.SPACE $PRIVATE$");
5246 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5247 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5248 "\n\t.SPACE $TEXT$");
5251 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5252 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5256 pa_file_start_file (int want_version)
5258 if (write_symbols != NO_DEBUG)
5260 output_file_directive (asm_out_file, main_input_filename);
5262 aputs ("\t.version\t\"01.01\"\n");
5267 pa_file_start_mcount (const char *aswhat)
5270 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5274 pa_elf_file_start (void)
5276 pa_file_start_level ();
5277 pa_file_start_mcount ("ENTRY");
5278 pa_file_start_file (0);
5282 pa_som_file_start (void)
5284 pa_file_start_level ();
5285 pa_file_start_space (0);
5286 aputs ("\t.IMPORT $global$,DATA\n"
5287 "\t.IMPORT $$dyncall,MILLICODE\n");
5288 pa_file_start_mcount ("CODE");
5289 pa_file_start_file (0);
5293 pa_linux_file_start (void)
5295 pa_file_start_file (1);
5296 pa_file_start_level ();
5297 pa_file_start_mcount ("CODE");
5301 pa_hpux64_gas_file_start (void)
5303 pa_file_start_level ();
5304 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5306 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5308 pa_file_start_file (1);
5312 pa_hpux64_hpas_file_start (void)
5314 pa_file_start_level ();
5315 pa_file_start_space (1);
5316 pa_file_start_mcount ("CODE");
5317 pa_file_start_file (0);
5321 /* Search the deferred plabel list for SYMBOL and return its internal
5322 label. If an entry for SYMBOL is not found, a new entry is created. */
5325 get_deferred_plabel (rtx symbol)
5327 const char *fname = XSTR (symbol, 0);
5330 /* See if we have already put this function on the list of deferred
5331 plabels. This list is generally small, so a liner search is not
5332 too ugly. If it proves too slow replace it with something faster. */
5333 for (i = 0; i < n_deferred_plabels; i++)
5334 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5337 /* If the deferred plabel list is empty, or this entry was not found
5338 on the list, create a new entry on the list. */
5339 if (deferred_plabels == NULL || i == n_deferred_plabels)
5343 if (deferred_plabels == 0)
5344 deferred_plabels = (struct deferred_plabel *)
5345 ggc_alloc (sizeof (struct deferred_plabel));
5347 deferred_plabels = (struct deferred_plabel *)
5348 ggc_realloc (deferred_plabels,
5349 ((n_deferred_plabels + 1)
5350 * sizeof (struct deferred_plabel)));
5352 i = n_deferred_plabels++;
5353 deferred_plabels[i].internal_label = gen_label_rtx ();
5354 deferred_plabels[i].symbol = symbol;
5356 /* Gross. We have just implicitly taken the address of this
5357 function. Mark it in the same manner as assemble_name. */
5358 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5360 mark_referenced (id);
5363 return deferred_plabels[i].internal_label;
5367 output_deferred_plabels (void)
5371 /* If we have some deferred plabels, then we need to switch into the
5372 data or readonly data section, and align it to a 4 byte boundary
5373 before outputting the deferred plabels. */
5374 if (n_deferred_plabels)
5376 switch_to_section (flag_pic ? data_section : readonly_data_section);
5377 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5380 /* Now output the deferred plabels. */
5381 for (i = 0; i < n_deferred_plabels; i++)
5383 targetm.asm_out.internal_label (asm_out_file, "L",
5384 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5385 assemble_integer (deferred_plabels[i].symbol,
5386 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5390 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5391 /* Initialize optabs to point to HPUX long double emulation routines. */
5393 pa_hpux_init_libfuncs (void)
5395 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5396 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5397 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5398 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5399 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5400 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5401 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5402 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5403 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5405 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5406 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5407 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5408 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5409 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5410 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5411 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5413 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5414 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5415 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5416 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5418 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5419 ? "__U_Qfcnvfxt_quad_to_sgl"
5420 : "_U_Qfcnvfxt_quad_to_sgl");
5421 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5422 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5423 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5425 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5426 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5427 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad");
5428 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad");
5432 /* HP's millicode routines mean something special to the assembler.
5433 Keep track of which ones we have used. */
5435 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5436 static void import_milli (enum millicodes);
5437 static char imported[(int) end1000];
5438 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5439 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5440 #define MILLI_START 10
5443 import_milli (enum millicodes code)
5445 char str[sizeof (import_string)];
5447 if (!imported[(int) code])
5449 imported[(int) code] = 1;
5450 strcpy (str, import_string);
5451 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5452 output_asm_insn (str, 0);
5456 /* The register constraints have put the operands and return value in
5457 the proper registers. */
5460 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5462 import_milli (mulI);
5463 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5466 /* Emit the rtl for doing a division by a constant. */
5468 /* Do magic division millicodes exist for this value? */
5469 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5471 /* We'll use an array to keep track of the magic millicodes and
5472 whether or not we've used them already. [n][0] is signed, [n][1] is
5475 static int div_milli[16][2];
5478 emit_hpdiv_const (rtx *operands, int unsignedp)
5480 if (GET_CODE (operands[2]) == CONST_INT
5481 && INTVAL (operands[2]) > 0
5482 && INTVAL (operands[2]) < 16
5483 && magic_milli[INTVAL (operands[2])])
5485 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5487 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5491 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5492 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5494 gen_rtx_REG (SImode, 26),
5496 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5497 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5498 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5499 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5500 gen_rtx_CLOBBER (VOIDmode, ret))));
5501 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5508 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5512 /* If the divisor is a constant, try to use one of the special
5514 if (GET_CODE (operands[0]) == CONST_INT)
5516 static char buf[100];
5517 divisor = INTVAL (operands[0]);
5518 if (!div_milli[divisor][unsignedp])
5520 div_milli[divisor][unsignedp] = 1;
5522 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5524 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5528 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5529 INTVAL (operands[0]));
5530 return output_millicode_call (insn,
5531 gen_rtx_SYMBOL_REF (SImode, buf));
5535 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5536 INTVAL (operands[0]));
5537 return output_millicode_call (insn,
5538 gen_rtx_SYMBOL_REF (SImode, buf));
5541 /* Divisor isn't a special constant. */
5546 import_milli (divU);
5547 return output_millicode_call (insn,
5548 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5552 import_milli (divI);
5553 return output_millicode_call (insn,
5554 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5559 /* Output a $$rem millicode to do mod. */
5562 output_mod_insn (int unsignedp, rtx insn)
5566 import_milli (remU);
5567 return output_millicode_call (insn,
5568 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5572 import_milli (remI);
5573 return output_millicode_call (insn,
5574 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5579 output_arg_descriptor (rtx call_insn)
5581 const char *arg_regs[4];
5582 enum machine_mode arg_mode;
5584 int i, output_flag = 0;
5587 /* We neither need nor want argument location descriptors for the
5588 64bit runtime environment or the ELF32 environment. */
5589 if (TARGET_64BIT || TARGET_ELF32)
5592 for (i = 0; i < 4; i++)
5595 /* Specify explicitly that no argument relocations should take place
5596 if using the portable runtime calling conventions. */
5597 if (TARGET_PORTABLE_RUNTIME)
5599 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5604 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5605 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5606 link; link = XEXP (link, 1))
5608 rtx use = XEXP (link, 0);
5610 if (! (GET_CODE (use) == USE
5611 && GET_CODE (XEXP (use, 0)) == REG
5612 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5615 arg_mode = GET_MODE (XEXP (use, 0));
5616 regno = REGNO (XEXP (use, 0));
5617 if (regno >= 23 && regno <= 26)
5619 arg_regs[26 - regno] = "GR";
5620 if (arg_mode == DImode)
5621 arg_regs[25 - regno] = "GR";
5623 else if (regno >= 32 && regno <= 39)
5625 if (arg_mode == SFmode)
5626 arg_regs[(regno - 32) / 2] = "FR";
5629 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5630 arg_regs[(regno - 34) / 2] = "FR";
5631 arg_regs[(regno - 34) / 2 + 1] = "FU";
5633 arg_regs[(regno - 34) / 2] = "FU";
5634 arg_regs[(regno - 34) / 2 + 1] = "FR";
5639 fputs ("\t.CALL ", asm_out_file);
5640 for (i = 0; i < 4; i++)
5645 fputc (',', asm_out_file);
5646 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5649 fputc ('\n', asm_out_file);
5652 static enum reg_class
5653 pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
5654 enum machine_mode mode, secondary_reload_info *sri)
5656 int is_symbolic, regno;
5658 /* Handle the easy stuff first. */
5659 if (class == R1_REGS)
5665 if (class == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5671 /* If we have something like (mem (mem (...)), we can safely assume the
5672 inner MEM will end up in a general register after reloading, so there's
5673 no need for a secondary reload. */
5674 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5677 /* Trying to load a constant into a FP register during PIC code
5678 generation requires %r1 as a scratch register. */
5680 && (mode == SImode || mode == DImode)
5681 && FP_REG_CLASS_P (class)
5682 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5684 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5685 : CODE_FOR_reload_indi_r1);
5689 /* Profiling showed the PA port spends about 1.3% of its compilation
5690 time in true_regnum from calls inside pa_secondary_reload_class. */
5691 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5692 regno = true_regnum (x);
5694 /* In order to allow 14-bit displacements in integer loads and stores,
5695 we need to prevent reload from generating out of range integer mode
5696 loads and stores to the floating point registers. Previously, we
5697 used to call for a secondary reload and have emit_move_sequence()
5698 fix the instruction sequence. However, reload occasionally wouldn't
5699 generate the reload and we would end up with an invalid REG+D memory
5700 address. So, now we use an intermediate general register for most
5701 memory loads and stores. */
5702 if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5703 && GET_MODE_CLASS (mode) == MODE_INT
5704 && FP_REG_CLASS_P (class))
5706 /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check
5707 the secondary reload needed for a pseudo. It never passes a
5709 if (GET_CODE (x) == MEM)
5713 /* We don't need an intermediate for indexed and LO_SUM DLT
5714 memory addresses. When INT14_OK_STRICT is true, it might
5715 appear that we could directly allow register indirect
5716 memory addresses. However, this doesn't work because we
5717 don't support SUBREGs in floating-point register copies
5718 and reload doesn't tell us when it's going to use a SUBREG. */
5719 if (IS_INDEX_ADDR_P (x)
5720 || IS_LO_SUM_DLT_ADDR_P (x))
5723 /* Otherwise, we need an intermediate general register. */
5724 return GENERAL_REGS;
5727 /* Request a secondary reload with a general scratch register
5728 for everthing else. ??? Could symbolic operands be handled
5729 directly when generating non-pic PA 2.0 code? */
5730 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5734 /* We need a secondary register (GPR) for copies between the SAR
5735 and anything other than a general register. */
5736 if (class == SHIFT_REGS && (regno <= 0 || regno >= 32))
5738 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5742 /* A SAR<->FP register copy requires a secondary register (GPR) as
5743 well as secondary memory. */
5744 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5745 && (REGNO_REG_CLASS (regno) == SHIFT_REGS
5746 && FP_REG_CLASS_P (class)))
5748 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5752 /* Secondary reloads of symbolic operands require %r1 as a scratch
5753 register when we're generating PIC code and when the operand isn't
5755 if (GET_CODE (x) == HIGH)
5758 /* Profiling has showed GCC spends about 2.6% of its compilation
5759 time in symbolic_operand from calls inside pa_secondary_reload_class.
5760 So, we use an inline copy to avoid useless work. */
5761 switch (GET_CODE (x))
5766 is_symbolic = !SYMBOL_REF_TLS_MODEL (x);
5773 is_symbolic = (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5774 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
5775 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
5776 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5783 if (is_symbolic && (flag_pic || !read_only_operand (x, VOIDmode)))
5785 gcc_assert (mode == SImode || mode == DImode);
5786 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5787 : CODE_FOR_reload_indi_r1);
5793 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
5794 is only marked as live on entry by df-scan when it is a fixed
5795 register. It isn't a fixed register in the 64-bit runtime,
5796 so we need to mark it here. */
5799 pa_extra_live_on_entry (bitmap regs)
5802 bitmap_set_bit (regs, ARG_POINTER_REGNUM);
5805 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
5806 to prevent it from being deleted. */
5809 pa_eh_return_handler_rtx (void)
5813 tmp = gen_rtx_PLUS (word_mode, frame_pointer_rtx,
5814 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20));
5815 tmp = gen_rtx_MEM (word_mode, tmp);
5820 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5821 by invisible reference. As a GCC extension, we also pass anything
5822 with a zero or variable size by reference.
5824 The 64-bit runtime does not describe passing any types by invisible
5825 reference. The internals of GCC can't currently handle passing
5826 empty structures, and zero or variable length arrays when they are
5827 not passed entirely on the stack or by reference. Thus, as a GCC
5828 extension, we pass these types by reference. The HP compiler doesn't
5829 support these types, so hopefully there shouldn't be any compatibility
5830 issues. This may have to be revisited when HP releases a C99 compiler
5831 or updates the ABI. */
5834 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5835 enum machine_mode mode, const_tree type,
5836 bool named ATTRIBUTE_UNUSED)
5841 size = int_size_in_bytes (type);
5843 size = GET_MODE_SIZE (mode);
5848 return size <= 0 || size > 8;
5852 function_arg_padding (enum machine_mode mode, const_tree type)
5855 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5857 /* Return none if justification is not required. */
5859 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5860 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5863 /* The directions set here are ignored when a BLKmode argument larger
5864 than a word is placed in a register. Different code is used for
5865 the stack and registers. This makes it difficult to have a
5866 consistent data representation for both the stack and registers.
5867 For both runtimes, the justification and padding for arguments on
5868 the stack and in registers should be identical. */
5870 /* The 64-bit runtime specifies left justification for aggregates. */
5873 /* The 32-bit runtime architecture specifies right justification.
5874 When the argument is passed on the stack, the argument is padded
5875 with garbage on the left. The HP compiler pads with zeros. */
5879 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5886 /* Do what is necessary for `va_start'. We look at the current function
5887 to determine if stdargs or varargs is used and fill in an initial
5888 va_list. A pointer to this constructor is returned. */
5891 hppa_builtin_saveregs (void)
5894 tree fntype = TREE_TYPE (current_function_decl);
5895 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5896 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5897 != void_type_node)))
5898 ? UNITS_PER_WORD : 0);
5901 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5903 offset = current_function_arg_offset_rtx;
5909 /* Adjust for varargs/stdarg differences. */
5911 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5913 offset = current_function_arg_offset_rtx;
5915 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5916 from the incoming arg pointer and growing to larger addresses. */
5917 for (i = 26, off = -64; i >= 19; i--, off += 8)
5918 emit_move_insn (gen_rtx_MEM (word_mode,
5919 plus_constant (arg_pointer_rtx, off)),
5920 gen_rtx_REG (word_mode, i));
5922 /* The incoming args pointer points just beyond the flushback area;
5923 normally this is not a serious concern. However, when we are doing
5924 varargs/stdargs we want to make the arg pointer point to the start
5925 of the incoming argument area. */
5926 emit_move_insn (virtual_incoming_args_rtx,
5927 plus_constant (arg_pointer_rtx, -64));
5929 /* Now return a pointer to the first anonymous argument. */
5930 return copy_to_reg (expand_binop (Pmode, add_optab,
5931 virtual_incoming_args_rtx,
5932 offset, 0, 0, OPTAB_LIB_WIDEN));
5935 /* Store general registers on the stack. */
5936 dest = gen_rtx_MEM (BLKmode,
5937 plus_constant (current_function_internal_arg_pointer,
5939 set_mem_alias_set (dest, get_varargs_alias_set ());
5940 set_mem_align (dest, BITS_PER_WORD);
5941 move_block_from_reg (23, dest, 4);
5943 /* move_block_from_reg will emit code to store the argument registers
5944 individually as scalar stores.
5946 However, other insns may later load from the same addresses for
5947 a structure load (passing a struct to a varargs routine).
5949 The alias code assumes that such aliasing can never happen, so we
5950 have to keep memory referencing insns from moving up beyond the
5951 last argument register store. So we emit a blockage insn here. */
5952 emit_insn (gen_blockage ());
5954 return copy_to_reg (expand_binop (Pmode, add_optab,
5955 current_function_internal_arg_pointer,
5956 offset, 0, 0, OPTAB_LIB_WIDEN));
5960 hppa_va_start (tree valist, rtx nextarg)
5962 nextarg = expand_builtin_saveregs ();
5963 std_expand_builtin_va_start (valist, nextarg);
5967 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5971 /* Args grow upward. We can use the generic routines. */
5972 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5974 else /* !TARGET_64BIT */
5976 tree ptr = build_pointer_type (type);
5979 unsigned int size, ofs;
5982 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5986 ptr = build_pointer_type (type);
5988 size = int_size_in_bytes (type);
5989 valist_type = TREE_TYPE (valist);
5991 /* Args grow down. Not handled by generic routines. */
5993 u = fold_convert (sizetype, size_in_bytes (type));
5994 u = fold_build1 (NEGATE_EXPR, sizetype, u);
5995 t = build2 (POINTER_PLUS_EXPR, valist_type, valist, u);
5997 /* Copied from va-pa.h, but we probably don't need to align to
5998 word size, since we generate and preserve that invariant. */
5999 u = size_int (size > 4 ? -8 : -4);
6000 t = fold_convert (sizetype, t);
6001 t = build2 (BIT_AND_EXPR, sizetype, t, u);
6002 t = fold_convert (valist_type, t);
6004 t = build2 (MODIFY_EXPR, valist_type, valist, t);
6006 ofs = (8 - size) % 4;
6010 t = build2 (POINTER_PLUS_EXPR, valist_type, t, u);
6013 t = fold_convert (ptr, t);
6014 t = build_va_arg_indirect_ref (t);
6017 t = build_va_arg_indirect_ref (t);
6023 /* True if MODE is valid for the target. By "valid", we mean able to
6024 be manipulated in non-trivial ways. In particular, this means all
6025 the arithmetic is supported.
6027 Currently, TImode is not valid as the HP 64-bit runtime documentation
6028 doesn't document the alignment and calling conventions for this type.
6029 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6030 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6033 pa_scalar_mode_supported_p (enum machine_mode mode)
6035 int precision = GET_MODE_PRECISION (mode);
6037 switch (GET_MODE_CLASS (mode))
6039 case MODE_PARTIAL_INT:
6041 if (precision == CHAR_TYPE_SIZE)
6043 if (precision == SHORT_TYPE_SIZE)
6045 if (precision == INT_TYPE_SIZE)
6047 if (precision == LONG_TYPE_SIZE)
6049 if (precision == LONG_LONG_TYPE_SIZE)
6054 if (precision == FLOAT_TYPE_SIZE)
6056 if (precision == DOUBLE_TYPE_SIZE)
6058 if (precision == LONG_DOUBLE_TYPE_SIZE)
6062 case MODE_DECIMAL_FLOAT:
6070 /* This routine handles all the normal conditional branch sequences we
6071 might need to generate. It handles compare immediate vs compare
6072 register, nullification of delay slots, varying length branches,
6073 negated branches, and all combinations of the above. It returns the
6074 output appropriate to emit the branch corresponding to all given
6078 output_cbranch (rtx *operands, int negated, rtx insn)
6080 static char buf[100];
6082 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6083 int length = get_attr_length (insn);
6086 /* A conditional branch to the following instruction (e.g. the delay slot)
6087 is asking for a disaster. This can happen when not optimizing and
6088 when jump optimization fails.
6090 While it is usually safe to emit nothing, this can fail if the
6091 preceding instruction is a nullified branch with an empty delay
6092 slot and the same branch target as this branch. We could check
6093 for this but jump optimization should eliminate nop jumps. It
6094 is always safe to emit a nop. */
6095 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6098 /* The doubleword form of the cmpib instruction doesn't have the LEU
6099 and GTU conditions while the cmpb instruction does. Since we accept
6100 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6101 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6102 operands[2] = gen_rtx_REG (DImode, 0);
6103 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
6104 operands[1] = gen_rtx_REG (DImode, 0);
6106 /* If this is a long branch with its delay slot unfilled, set `nullify'
6107 as it can nullify the delay slot and save a nop. */
6108 if (length == 8 && dbr_sequence_length () == 0)
6111 /* If this is a short forward conditional branch which did not get
6112 its delay slot filled, the delay slot can still be nullified. */
6113 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6114 nullify = forward_branch_p (insn);
6116 /* A forward branch over a single nullified insn can be done with a
6117 comclr instruction. This avoids a single cycle penalty due to
6118 mis-predicted branch if we fall through (branch not taken). */
6120 && next_real_insn (insn) != 0
6121 && get_attr_length (next_real_insn (insn)) == 4
6122 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6128 /* All short conditional branches except backwards with an unfilled
6132 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6134 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6135 if (GET_MODE (operands[1]) == DImode)
6138 strcat (buf, "%B3");
6140 strcat (buf, "%S3");
6142 strcat (buf, " %2,%r1,%%r0");
6144 strcat (buf, ",n %2,%r1,%0");
6146 strcat (buf, " %2,%r1,%0");
6149 /* All long conditionals. Note a short backward branch with an
6150 unfilled delay slot is treated just like a long backward branch
6151 with an unfilled delay slot. */
6153 /* Handle weird backwards branch with a filled delay slot
6154 which is nullified. */
6155 if (dbr_sequence_length () != 0
6156 && ! forward_branch_p (insn)
6159 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6160 if (GET_MODE (operands[1]) == DImode)
6163 strcat (buf, "%S3");
6165 strcat (buf, "%B3");
6166 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6168 /* Handle short backwards branch with an unfilled delay slot.
6169 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6170 taken and untaken branches. */
6171 else if (dbr_sequence_length () == 0
6172 && ! forward_branch_p (insn)
6173 && INSN_ADDRESSES_SET_P ()
6174 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6175 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6177 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6178 if (GET_MODE (operands[1]) == DImode)
6181 strcat (buf, "%B3 %2,%r1,%0%#");
6183 strcat (buf, "%S3 %2,%r1,%0%#");
6187 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6188 if (GET_MODE (operands[1]) == DImode)
6191 strcat (buf, "%S3");
6193 strcat (buf, "%B3");
6195 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6197 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6202 /* The reversed conditional branch must branch over one additional
6203 instruction if the delay slot is filled and needs to be extracted
6204 by output_lbranch. If the delay slot is empty or this is a
6205 nullified forward branch, the instruction after the reversed
6206 condition branch must be nullified. */
6207 if (dbr_sequence_length () == 0
6208 || (nullify && forward_branch_p (insn)))
6212 operands[4] = GEN_INT (length);
6217 operands[4] = GEN_INT (length + 4);
6220 /* Create a reversed conditional branch which branches around
6221 the following insns. */
6222 if (GET_MODE (operands[1]) != DImode)
6228 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6231 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6237 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6240 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6249 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6252 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6258 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6261 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6265 output_asm_insn (buf, operands);
6266 return output_lbranch (operands[0], insn, xdelay);
6271 /* This routine handles output of long unconditional branches that
6272 exceed the maximum range of a simple branch instruction. Since
6273 we don't have a register available for the branch, we save register
6274 %r1 in the frame marker, load the branch destination DEST into %r1,
6275 execute the branch, and restore %r1 in the delay slot of the branch.
6277 Since long branches may have an insn in the delay slot and the
6278 delay slot is used to restore %r1, we in general need to extract
6279 this insn and execute it before the branch. However, to facilitate
6280 use of this function by conditional branches, we also provide an
6281 option to not extract the delay insn so that it will be emitted
6282 after the long branch. So, if there is an insn in the delay slot,
6283 it is extracted if XDELAY is nonzero.
6285 The lengths of the various long-branch sequences are 20, 16 and 24
6286 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6289 output_lbranch (rtx dest, rtx insn, int xdelay)
6293 xoperands[0] = dest;
6295 /* First, free up the delay slot. */
6296 if (xdelay && dbr_sequence_length () != 0)
6298 /* We can't handle a jump in the delay slot. */
6299 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6301 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6304 /* Now delete the delay insn. */
6305 SET_INSN_DELETED (NEXT_INSN (insn));
6308 /* Output an insn to save %r1. The runtime documentation doesn't
6309 specify whether the "Clean Up" slot in the callers frame can
6310 be clobbered by the callee. It isn't copied by HP's builtin
6311 alloca, so this suggests that it can be clobbered if necessary.
6312 The "Static Link" location is copied by HP builtin alloca, so
6313 we avoid using it. Using the cleanup slot might be a problem
6314 if we have to interoperate with languages that pass cleanup
6315 information. However, it should be possible to handle these
6316 situations with GCC's asm feature.
6318 The "Current RP" slot is reserved for the called procedure, so
6319 we try to use it when we don't have a frame of our own. It's
6320 rather unlikely that we won't have a frame when we need to emit
6323 Really the way to go long term is a register scavenger; goto
6324 the target of the jump and find a register which we can use
6325 as a scratch to hold the value in %r1. Then, we wouldn't have
6326 to free up the delay slot or clobber a slot that may be needed
6327 for other purposes. */
6330 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6331 /* Use the return pointer slot in the frame marker. */
6332 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6334 /* Use the slot at -40 in the frame marker since HP builtin
6335 alloca doesn't copy it. */
6336 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6340 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6341 /* Use the return pointer slot in the frame marker. */
6342 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6344 /* Use the "Clean Up" slot in the frame marker. In GCC,
6345 the only other use of this location is for copying a
6346 floating point double argument from a floating-point
6347 register to two general registers. The copy is done
6348 as an "atomic" operation when outputting a call, so it
6349 won't interfere with our using the location here. */
6350 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6353 if (TARGET_PORTABLE_RUNTIME)
6355 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6356 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6357 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6361 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6362 if (TARGET_SOM || !TARGET_GAS)
6364 xoperands[1] = gen_label_rtx ();
6365 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6366 targetm.asm_out.internal_label (asm_out_file, "L",
6367 CODE_LABEL_NUMBER (xoperands[1]));
6368 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6372 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6373 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6375 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6378 /* Now output a very long branch to the original target. */
6379 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6381 /* Now restore the value of %r1 in the delay slot. */
6384 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6385 return "ldd -16(%%r30),%%r1";
6387 return "ldd -40(%%r30),%%r1";
6391 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6392 return "ldw -20(%%r30),%%r1";
6394 return "ldw -12(%%r30),%%r1";
6398 /* This routine handles all the branch-on-bit conditional branch sequences we
6399 might need to generate. It handles nullification of delay slots,
6400 varying length branches, negated branches and all combinations of the
6401 above. it returns the appropriate output template to emit the branch. */
6404 output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6406 static char buf[100];
6408 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6409 int length = get_attr_length (insn);
6412 /* A conditional branch to the following instruction (e.g. the delay slot) is
6413 asking for a disaster. I do not think this can happen as this pattern
6414 is only used when optimizing; jump optimization should eliminate the
6415 jump. But be prepared just in case. */
6417 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6420 /* If this is a long branch with its delay slot unfilled, set `nullify'
6421 as it can nullify the delay slot and save a nop. */
6422 if (length == 8 && dbr_sequence_length () == 0)
6425 /* If this is a short forward conditional branch which did not get
6426 its delay slot filled, the delay slot can still be nullified. */
6427 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6428 nullify = forward_branch_p (insn);
6430 /* A forward branch over a single nullified insn can be done with a
6431 extrs instruction. This avoids a single cycle penalty due to
6432 mis-predicted branch if we fall through (branch not taken). */
6435 && next_real_insn (insn) != 0
6436 && get_attr_length (next_real_insn (insn)) == 4
6437 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6444 /* All short conditional branches except backwards with an unfilled
6448 strcpy (buf, "{extrs,|extrw,s,}");
6450 strcpy (buf, "bb,");
6451 if (useskip && GET_MODE (operands[0]) == DImode)
6452 strcpy (buf, "extrd,s,*");
6453 else if (GET_MODE (operands[0]) == DImode)
6454 strcpy (buf, "bb,*");
6455 if ((which == 0 && negated)
6456 || (which == 1 && ! negated))
6461 strcat (buf, " %0,%1,1,%%r0");
6462 else if (nullify && negated)
6463 strcat (buf, ",n %0,%1,%3");
6464 else if (nullify && ! negated)
6465 strcat (buf, ",n %0,%1,%2");
6466 else if (! nullify && negated)
6467 strcat (buf, "%0,%1,%3");
6468 else if (! nullify && ! negated)
6469 strcat (buf, " %0,%1,%2");
6472 /* All long conditionals. Note a short backward branch with an
6473 unfilled delay slot is treated just like a long backward branch
6474 with an unfilled delay slot. */
6476 /* Handle weird backwards branch with a filled delay slot
6477 which is nullified. */
6478 if (dbr_sequence_length () != 0
6479 && ! forward_branch_p (insn)
6482 strcpy (buf, "bb,");
6483 if (GET_MODE (operands[0]) == DImode)
6485 if ((which == 0 && negated)
6486 || (which == 1 && ! negated))
6491 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6493 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6495 /* Handle short backwards branch with an unfilled delay slot.
6496 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6497 taken and untaken branches. */
6498 else if (dbr_sequence_length () == 0
6499 && ! forward_branch_p (insn)
6500 && INSN_ADDRESSES_SET_P ()
6501 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6502 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6504 strcpy (buf, "bb,");
6505 if (GET_MODE (operands[0]) == DImode)
6507 if ((which == 0 && negated)
6508 || (which == 1 && ! negated))
6513 strcat (buf, " %0,%1,%3%#");
6515 strcat (buf, " %0,%1,%2%#");
6519 if (GET_MODE (operands[0]) == DImode)
6520 strcpy (buf, "extrd,s,*");
6522 strcpy (buf, "{extrs,|extrw,s,}");
6523 if ((which == 0 && negated)
6524 || (which == 1 && ! negated))
6528 if (nullify && negated)
6529 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6530 else if (nullify && ! negated)
6531 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6533 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6535 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6540 /* The reversed conditional branch must branch over one additional
6541 instruction if the delay slot is filled and needs to be extracted
6542 by output_lbranch. If the delay slot is empty or this is a
6543 nullified forward branch, the instruction after the reversed
6544 condition branch must be nullified. */
6545 if (dbr_sequence_length () == 0
6546 || (nullify && forward_branch_p (insn)))
6550 operands[4] = GEN_INT (length);
6555 operands[4] = GEN_INT (length + 4);
6558 if (GET_MODE (operands[0]) == DImode)
6559 strcpy (buf, "bb,*");
6561 strcpy (buf, "bb,");
6562 if ((which == 0 && negated)
6563 || (which == 1 && !negated))
6568 strcat (buf, ",n %0,%1,.+%4");
6570 strcat (buf, " %0,%1,.+%4");
6571 output_asm_insn (buf, operands);
6572 return output_lbranch (negated ? operands[3] : operands[2],
6578 /* This routine handles all the branch-on-variable-bit conditional branch
6579 sequences we might need to generate. It handles nullification of delay
6580 slots, varying length branches, negated branches and all combinations
6581 of the above. it returns the appropriate output template to emit the
6585 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6587 static char buf[100];
6589 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6590 int length = get_attr_length (insn);
6593 /* A conditional branch to the following instruction (e.g. the delay slot) is
6594 asking for a disaster. I do not think this can happen as this pattern
6595 is only used when optimizing; jump optimization should eliminate the
6596 jump. But be prepared just in case. */
6598 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6601 /* If this is a long branch with its delay slot unfilled, set `nullify'
6602 as it can nullify the delay slot and save a nop. */
6603 if (length == 8 && dbr_sequence_length () == 0)
6606 /* If this is a short forward conditional branch which did not get
6607 its delay slot filled, the delay slot can still be nullified. */
6608 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6609 nullify = forward_branch_p (insn);
6611 /* A forward branch over a single nullified insn can be done with a
6612 extrs instruction. This avoids a single cycle penalty due to
6613 mis-predicted branch if we fall through (branch not taken). */
6616 && next_real_insn (insn) != 0
6617 && get_attr_length (next_real_insn (insn)) == 4
6618 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6625 /* All short conditional branches except backwards with an unfilled
6629 strcpy (buf, "{vextrs,|extrw,s,}");
6631 strcpy (buf, "{bvb,|bb,}");
6632 if (useskip && GET_MODE (operands[0]) == DImode)
6633 strcpy (buf, "extrd,s,*");
6634 else if (GET_MODE (operands[0]) == DImode)
6635 strcpy (buf, "bb,*");
6636 if ((which == 0 && negated)
6637 || (which == 1 && ! negated))
6642 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6643 else if (nullify && negated)
6644 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6645 else if (nullify && ! negated)
6646 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6647 else if (! nullify && negated)
6648 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6649 else if (! nullify && ! negated)
6650 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6653 /* All long conditionals. Note a short backward branch with an
6654 unfilled delay slot is treated just like a long backward branch
6655 with an unfilled delay slot. */
6657 /* Handle weird backwards branch with a filled delay slot
6658 which is nullified. */
6659 if (dbr_sequence_length () != 0
6660 && ! forward_branch_p (insn)
6663 strcpy (buf, "{bvb,|bb,}");
6664 if (GET_MODE (operands[0]) == DImode)
6666 if ((which == 0 && negated)
6667 || (which == 1 && ! negated))
6672 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6674 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6676 /* Handle short backwards branch with an unfilled delay slot.
6677 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6678 taken and untaken branches. */
6679 else if (dbr_sequence_length () == 0
6680 && ! forward_branch_p (insn)
6681 && INSN_ADDRESSES_SET_P ()
6682 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6683 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6685 strcpy (buf, "{bvb,|bb,}");
6686 if (GET_MODE (operands[0]) == DImode)
6688 if ((which == 0 && negated)
6689 || (which == 1 && ! negated))
6694 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6696 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6700 strcpy (buf, "{vextrs,|extrw,s,}");
6701 if (GET_MODE (operands[0]) == DImode)
6702 strcpy (buf, "extrd,s,*");
6703 if ((which == 0 && negated)
6704 || (which == 1 && ! negated))
6708 if (nullify && negated)
6709 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6710 else if (nullify && ! negated)
6711 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6713 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6715 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6720 /* The reversed conditional branch must branch over one additional
6721 instruction if the delay slot is filled and needs to be extracted
6722 by output_lbranch. If the delay slot is empty or this is a
6723 nullified forward branch, the instruction after the reversed
6724 condition branch must be nullified. */
6725 if (dbr_sequence_length () == 0
6726 || (nullify && forward_branch_p (insn)))
6730 operands[4] = GEN_INT (length);
6735 operands[4] = GEN_INT (length + 4);
6738 if (GET_MODE (operands[0]) == DImode)
6739 strcpy (buf, "bb,*");
6741 strcpy (buf, "{bvb,|bb,}");
6742 if ((which == 0 && negated)
6743 || (which == 1 && !negated))
6748 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
6750 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
6751 output_asm_insn (buf, operands);
6752 return output_lbranch (negated ? operands[3] : operands[2],
6758 /* Return the output template for emitting a dbra type insn.
6760 Note it may perform some output operations on its own before
6761 returning the final output string. */
6763 output_dbra (rtx *operands, rtx insn, int which_alternative)
6765 int length = get_attr_length (insn);
6767 /* A conditional branch to the following instruction (e.g. the delay slot) is
6768 asking for a disaster. Be prepared! */
6770 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6772 if (which_alternative == 0)
6773 return "ldo %1(%0),%0";
6774 else if (which_alternative == 1)
6776 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6777 output_asm_insn ("ldw -16(%%r30),%4", operands);
6778 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6779 return "{fldws|fldw} -16(%%r30),%0";
6783 output_asm_insn ("ldw %0,%4", operands);
6784 return "ldo %1(%4),%4\n\tstw %4,%0";
6788 if (which_alternative == 0)
6790 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6793 /* If this is a long branch with its delay slot unfilled, set `nullify'
6794 as it can nullify the delay slot and save a nop. */
6795 if (length == 8 && dbr_sequence_length () == 0)
6798 /* If this is a short forward conditional branch which did not get
6799 its delay slot filled, the delay slot can still be nullified. */
6800 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6801 nullify = forward_branch_p (insn);
6807 return "addib,%C2,n %1,%0,%3";
6809 return "addib,%C2 %1,%0,%3";
6812 /* Handle weird backwards branch with a fulled delay slot
6813 which is nullified. */
6814 if (dbr_sequence_length () != 0
6815 && ! forward_branch_p (insn)
6817 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6818 /* Handle short backwards branch with an unfilled delay slot.
6819 Using a addb;nop rather than addi;bl saves 1 cycle for both
6820 taken and untaken branches. */
6821 else if (dbr_sequence_length () == 0
6822 && ! forward_branch_p (insn)
6823 && INSN_ADDRESSES_SET_P ()
6824 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6825 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6826 return "addib,%C2 %1,%0,%3%#";
6828 /* Handle normal cases. */
6830 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6832 return "addi,%N2 %1,%0,%0\n\tb %3";
6835 /* The reversed conditional branch must branch over one additional
6836 instruction if the delay slot is filled and needs to be extracted
6837 by output_lbranch. If the delay slot is empty or this is a
6838 nullified forward branch, the instruction after the reversed
6839 condition branch must be nullified. */
6840 if (dbr_sequence_length () == 0
6841 || (nullify && forward_branch_p (insn)))
6845 operands[4] = GEN_INT (length);
6850 operands[4] = GEN_INT (length + 4);
6854 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
6856 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
6858 return output_lbranch (operands[3], insn, xdelay);
6862 /* Deal with gross reload from FP register case. */
6863 else if (which_alternative == 1)
6865 /* Move loop counter from FP register to MEM then into a GR,
6866 increment the GR, store the GR into MEM, and finally reload
6867 the FP register from MEM from within the branch's delay slot. */
6868 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6870 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6872 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6873 else if (length == 28)
6874 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6877 operands[5] = GEN_INT (length - 16);
6878 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
6879 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
6880 return output_lbranch (operands[3], insn, 0);
6883 /* Deal with gross reload from memory case. */
6886 /* Reload loop counter from memory, the store back to memory
6887 happens in the branch's delay slot. */
6888 output_asm_insn ("ldw %0,%4", operands);
6890 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6891 else if (length == 16)
6892 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6895 operands[5] = GEN_INT (length - 4);
6896 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
6897 return output_lbranch (operands[3], insn, 0);
6902 /* Return the output template for emitting a movb type insn.
6904 Note it may perform some output operations on its own before
6905 returning the final output string. */
6907 output_movb (rtx *operands, rtx insn, int which_alternative,
6908 int reverse_comparison)
6910 int length = get_attr_length (insn);
6912 /* A conditional branch to the following instruction (e.g. the delay slot) is
6913 asking for a disaster. Be prepared! */
6915 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6917 if (which_alternative == 0)
6918 return "copy %1,%0";
6919 else if (which_alternative == 1)
6921 output_asm_insn ("stw %1,-16(%%r30)", operands);
6922 return "{fldws|fldw} -16(%%r30),%0";
6924 else if (which_alternative == 2)
6930 /* Support the second variant. */
6931 if (reverse_comparison)
6932 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6934 if (which_alternative == 0)
6936 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6939 /* If this is a long branch with its delay slot unfilled, set `nullify'
6940 as it can nullify the delay slot and save a nop. */
6941 if (length == 8 && dbr_sequence_length () == 0)
6944 /* If this is a short forward conditional branch which did not get
6945 its delay slot filled, the delay slot can still be nullified. */
6946 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6947 nullify = forward_branch_p (insn);
6953 return "movb,%C2,n %1,%0,%3";
6955 return "movb,%C2 %1,%0,%3";
6958 /* Handle weird backwards branch with a filled delay slot
6959 which is nullified. */
6960 if (dbr_sequence_length () != 0
6961 && ! forward_branch_p (insn)
6963 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6965 /* Handle short backwards branch with an unfilled delay slot.
6966 Using a movb;nop rather than or;bl saves 1 cycle for both
6967 taken and untaken branches. */
6968 else if (dbr_sequence_length () == 0
6969 && ! forward_branch_p (insn)
6970 && INSN_ADDRESSES_SET_P ()
6971 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6972 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6973 return "movb,%C2 %1,%0,%3%#";
6974 /* Handle normal cases. */
6976 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6978 return "or,%N2 %1,%%r0,%0\n\tb %3";
6981 /* The reversed conditional branch must branch over one additional
6982 instruction if the delay slot is filled and needs to be extracted
6983 by output_lbranch. If the delay slot is empty or this is a
6984 nullified forward branch, the instruction after the reversed
6985 condition branch must be nullified. */
6986 if (dbr_sequence_length () == 0
6987 || (nullify && forward_branch_p (insn)))
6991 operands[4] = GEN_INT (length);
6996 operands[4] = GEN_INT (length + 4);
7000 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
7002 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
7004 return output_lbranch (operands[3], insn, xdelay);
7007 /* Deal with gross reload for FP destination register case. */
7008 else if (which_alternative == 1)
7010 /* Move source register to MEM, perform the branch test, then
7011 finally load the FP register from MEM from within the branch's
7013 output_asm_insn ("stw %1,-16(%%r30)", operands);
7015 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7016 else if (length == 16)
7017 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7020 operands[4] = GEN_INT (length - 4);
7021 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
7022 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7023 return output_lbranch (operands[3], insn, 0);
7026 /* Deal with gross reload from memory case. */
7027 else if (which_alternative == 2)
7029 /* Reload loop counter from memory, the store back to memory
7030 happens in the branch's delay slot. */
7032 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7033 else if (length == 12)
7034 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7037 operands[4] = GEN_INT (length);
7038 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7040 return output_lbranch (operands[3], insn, 0);
7043 /* Handle SAR as a destination. */
7047 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7048 else if (length == 12)
7049 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7052 operands[4] = GEN_INT (length);
7053 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7055 return output_lbranch (operands[3], insn, 0);
7060 /* Copy any FP arguments in INSN into integer registers. */
7062 copy_fp_args (rtx insn)
7067 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7069 int arg_mode, regno;
7070 rtx use = XEXP (link, 0);
7072 if (! (GET_CODE (use) == USE
7073 && GET_CODE (XEXP (use, 0)) == REG
7074 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7077 arg_mode = GET_MODE (XEXP (use, 0));
7078 regno = REGNO (XEXP (use, 0));
7080 /* Is it a floating point register? */
7081 if (regno >= 32 && regno <= 39)
7083 /* Copy the FP register into an integer register via memory. */
7084 if (arg_mode == SFmode)
7086 xoperands[0] = XEXP (use, 0);
7087 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7088 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7089 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7093 xoperands[0] = XEXP (use, 0);
7094 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7095 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7096 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7097 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7103 /* Compute length of the FP argument copy sequence for INSN. */
7105 length_fp_args (rtx insn)
7110 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7112 int arg_mode, regno;
7113 rtx use = XEXP (link, 0);
7115 if (! (GET_CODE (use) == USE
7116 && GET_CODE (XEXP (use, 0)) == REG
7117 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7120 arg_mode = GET_MODE (XEXP (use, 0));
7121 regno = REGNO (XEXP (use, 0));
7123 /* Is it a floating point register? */
7124 if (regno >= 32 && regno <= 39)
7126 if (arg_mode == SFmode)
7136 /* Return the attribute length for the millicode call instruction INSN.
7137 The length must match the code generated by output_millicode_call.
7138 We include the delay slot in the returned length as it is better to
7139 over estimate the length than to under estimate it. */
7142 attr_length_millicode_call (rtx insn)
7144 unsigned long distance = -1;
7145 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7147 if (INSN_ADDRESSES_SET_P ())
7149 distance = (total + insn_current_reference_address (insn));
7150 if (distance < total)
7156 if (!TARGET_LONG_CALLS && distance < 7600000)
7161 else if (TARGET_PORTABLE_RUNTIME)
7165 if (!TARGET_LONG_CALLS && distance < 240000)
7168 if (TARGET_LONG_ABS_CALL && !flag_pic)
7175 /* INSN is a function call. It may have an unconditional jump
7178 CALL_DEST is the routine we are calling. */
7181 output_millicode_call (rtx insn, rtx call_dest)
7183 int attr_length = get_attr_length (insn);
7184 int seq_length = dbr_sequence_length ();
7189 xoperands[0] = call_dest;
7190 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7192 /* Handle the common case where we are sure that the branch will
7193 reach the beginning of the $CODE$ subspace. The within reach
7194 form of the $$sh_func_adrs call has a length of 28. Because
7195 it has an attribute type of multi, it never has a nonzero
7196 sequence length. The length of the $$sh_func_adrs is the same
7197 as certain out of reach PIC calls to other routines. */
7198 if (!TARGET_LONG_CALLS
7199 && ((seq_length == 0
7200 && (attr_length == 12
7201 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7202 || (seq_length != 0 && attr_length == 8)))
7204 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7210 /* It might seem that one insn could be saved by accessing
7211 the millicode function using the linkage table. However,
7212 this doesn't work in shared libraries and other dynamically
7213 loaded objects. Using a pc-relative sequence also avoids
7214 problems related to the implicit use of the gp register. */
7215 output_asm_insn ("b,l .+8,%%r1", xoperands);
7219 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7220 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7224 xoperands[1] = gen_label_rtx ();
7225 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7226 targetm.asm_out.internal_label (asm_out_file, "L",
7227 CODE_LABEL_NUMBER (xoperands[1]));
7228 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7231 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7233 else if (TARGET_PORTABLE_RUNTIME)
7235 /* Pure portable runtime doesn't allow be/ble; we also don't
7236 have PIC support in the assembler/linker, so this sequence
7239 /* Get the address of our target into %r1. */
7240 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7241 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7243 /* Get our return address into %r31. */
7244 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7245 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7247 /* Jump to our target address in %r1. */
7248 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7252 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7254 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7256 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7260 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7261 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7263 if (TARGET_SOM || !TARGET_GAS)
7265 /* The HP assembler can generate relocations for the
7266 difference of two symbols. GAS can do this for a
7267 millicode symbol but not an arbitrary external
7268 symbol when generating SOM output. */
7269 xoperands[1] = gen_label_rtx ();
7270 targetm.asm_out.internal_label (asm_out_file, "L",
7271 CODE_LABEL_NUMBER (xoperands[1]));
7272 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7273 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7277 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7278 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7282 /* Jump to our target address in %r1. */
7283 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7287 if (seq_length == 0)
7288 output_asm_insn ("nop", xoperands);
7290 /* We are done if there isn't a jump in the delay slot. */
7291 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7294 /* This call has an unconditional jump in its delay slot. */
7295 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7297 /* See if the return address can be adjusted. Use the containing
7298 sequence insn's address. */
7299 if (INSN_ADDRESSES_SET_P ())
7301 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7302 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7303 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7305 if (VAL_14_BITS_P (distance))
7307 xoperands[1] = gen_label_rtx ();
7308 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7309 targetm.asm_out.internal_label (asm_out_file, "L",
7310 CODE_LABEL_NUMBER (xoperands[1]));
7313 /* ??? This branch may not reach its target. */
7314 output_asm_insn ("nop\n\tb,n %0", xoperands);
7317 /* ??? This branch may not reach its target. */
7318 output_asm_insn ("nop\n\tb,n %0", xoperands);
7320 /* Delete the jump. */
7321 SET_INSN_DELETED (NEXT_INSN (insn));
7326 /* Return the attribute length of the call instruction INSN. The SIBCALL
7327 flag indicates whether INSN is a regular call or a sibling call. The
7328 length returned must be longer than the code actually generated by
7329 output_call. Since branch shortening is done before delay branch
7330 sequencing, there is no way to determine whether or not the delay
7331 slot will be filled during branch shortening. Even when the delay
7332 slot is filled, we may have to add a nop if the delay slot contains
7333 a branch that can't reach its target. Thus, we always have to include
7334 the delay slot in the length estimate. This used to be done in
7335 pa_adjust_insn_length but we do it here now as some sequences always
7336 fill the delay slot and we can save four bytes in the estimate for
7340 attr_length_call (rtx insn, int sibcall)
7346 rtx pat = PATTERN (insn);
7347 unsigned long distance = -1;
7349 if (INSN_ADDRESSES_SET_P ())
7351 unsigned long total;
7353 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7354 distance = (total + insn_current_reference_address (insn));
7355 if (distance < total)
7359 /* Determine if this is a local call. */
7360 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7361 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7363 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7365 call_decl = SYMBOL_REF_DECL (call_dest);
7366 local_call = call_decl && targetm.binds_local_p (call_decl);
7368 /* pc-relative branch. */
7369 if (!TARGET_LONG_CALLS
7370 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7371 || distance < 240000))
7374 /* 64-bit plabel sequence. */
7375 else if (TARGET_64BIT && !local_call)
7376 length += sibcall ? 28 : 24;
7378 /* non-pic long absolute branch sequence. */
7379 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7382 /* long pc-relative branch sequence. */
7383 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7384 || (TARGET_64BIT && !TARGET_GAS)
7385 || (TARGET_GAS && !TARGET_SOM
7386 && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7390 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7394 /* 32-bit plabel sequence. */
7400 length += length_fp_args (insn);
7410 if (!TARGET_NO_SPACE_REGS)
7418 /* INSN is a function call. It may have an unconditional jump
7421 CALL_DEST is the routine we are calling. */
7424 output_call (rtx insn, rtx call_dest, int sibcall)
7426 int delay_insn_deleted = 0;
7427 int delay_slot_filled = 0;
7428 int seq_length = dbr_sequence_length ();
7429 tree call_decl = SYMBOL_REF_DECL (call_dest);
7430 int local_call = call_decl && targetm.binds_local_p (call_decl);
7433 xoperands[0] = call_dest;
7435 /* Handle the common case where we're sure that the branch will reach
7436 the beginning of the "$CODE$" subspace. This is the beginning of
7437 the current function if we are in a named section. */
7438 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7440 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7441 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7445 if (TARGET_64BIT && !local_call)
7447 /* ??? As far as I can tell, the HP linker doesn't support the
7448 long pc-relative sequence described in the 64-bit runtime
7449 architecture. So, we use a slightly longer indirect call. */
7450 xoperands[0] = get_deferred_plabel (call_dest);
7451 xoperands[1] = gen_label_rtx ();
7453 /* If this isn't a sibcall, we put the load of %r27 into the
7454 delay slot. We can't do this in a sibcall as we don't
7455 have a second call-clobbered scratch register available. */
7457 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7460 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7463 /* Now delete the delay insn. */
7464 SET_INSN_DELETED (NEXT_INSN (insn));
7465 delay_insn_deleted = 1;
7468 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7469 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7470 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7474 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7475 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7476 output_asm_insn ("bve (%%r1)", xoperands);
7480 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7481 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7482 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7483 delay_slot_filled = 1;
7488 int indirect_call = 0;
7490 /* Emit a long call. There are several different sequences
7491 of increasing length and complexity. In most cases,
7492 they don't allow an instruction in the delay slot. */
7493 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7494 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7495 && !(TARGET_GAS && !TARGET_SOM
7496 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7501 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7503 && (!TARGET_PA_20 || indirect_call))
7505 /* A non-jump insn in the delay slot. By definition we can
7506 emit this insn before the call (and in fact before argument
7508 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7511 /* Now delete the delay insn. */
7512 SET_INSN_DELETED (NEXT_INSN (insn));
7513 delay_insn_deleted = 1;
7516 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7518 /* This is the best sequence for making long calls in
7519 non-pic code. Unfortunately, GNU ld doesn't provide
7520 the stub needed for external calls, and GAS's support
7521 for this with the SOM linker is buggy. It is safe
7522 to use this for local calls. */
7523 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7525 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7529 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7532 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7534 output_asm_insn ("copy %%r31,%%r2", xoperands);
7535 delay_slot_filled = 1;
7540 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7541 || (TARGET_64BIT && !TARGET_GAS))
7543 /* The HP assembler and linker can handle relocations
7544 for the difference of two symbols. GAS and the HP
7545 linker can't do this when one of the symbols is
7547 xoperands[1] = gen_label_rtx ();
7548 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7549 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7550 targetm.asm_out.internal_label (asm_out_file, "L",
7551 CODE_LABEL_NUMBER (xoperands[1]));
7552 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7554 else if (TARGET_GAS && !TARGET_SOM
7555 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7557 /* GAS currently can't generate the relocations that
7558 are needed for the SOM linker under HP-UX using this
7559 sequence. The GNU linker doesn't generate the stubs
7560 that are needed for external calls on TARGET_ELF32
7561 with this sequence. For now, we have to use a
7562 longer plabel sequence when using GAS. */
7563 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7564 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7566 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7571 /* Emit a long plabel-based call sequence. This is
7572 essentially an inline implementation of $$dyncall.
7573 We don't actually try to call $$dyncall as this is
7574 as difficult as calling the function itself. */
7575 xoperands[0] = get_deferred_plabel (call_dest);
7576 xoperands[1] = gen_label_rtx ();
7578 /* Since the call is indirect, FP arguments in registers
7579 need to be copied to the general registers. Then, the
7580 argument relocation stub will copy them back. */
7582 copy_fp_args (insn);
7586 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7587 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7588 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7592 output_asm_insn ("addil LR'%0-$global$,%%r27",
7594 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7598 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7599 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7600 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7601 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7603 if (!sibcall && !TARGET_PA_20)
7605 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7606 if (TARGET_NO_SPACE_REGS)
7607 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7609 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7616 output_asm_insn ("bve (%%r1)", xoperands);
7621 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7622 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7623 delay_slot_filled = 1;
7626 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7631 if (!TARGET_NO_SPACE_REGS)
7632 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7637 if (TARGET_NO_SPACE_REGS)
7638 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7640 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7644 if (TARGET_NO_SPACE_REGS)
7645 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7647 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7650 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7652 output_asm_insn ("copy %%r31,%%r2", xoperands);
7653 delay_slot_filled = 1;
7660 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7661 output_asm_insn ("nop", xoperands);
7663 /* We are done if there isn't a jump in the delay slot. */
7665 || delay_insn_deleted
7666 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7669 /* A sibcall should never have a branch in the delay slot. */
7670 gcc_assert (!sibcall);
7672 /* This call has an unconditional jump in its delay slot. */
7673 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7675 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7677 /* See if the return address can be adjusted. Use the containing
7678 sequence insn's address. */
7679 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7680 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7681 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7683 if (VAL_14_BITS_P (distance))
7685 xoperands[1] = gen_label_rtx ();
7686 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7687 targetm.asm_out.internal_label (asm_out_file, "L",
7688 CODE_LABEL_NUMBER (xoperands[1]));
7691 output_asm_insn ("nop\n\tb,n %0", xoperands);
7694 output_asm_insn ("b,n %0", xoperands);
7696 /* Delete the jump. */
7697 SET_INSN_DELETED (NEXT_INSN (insn));
7702 /* Return the attribute length of the indirect call instruction INSN.
7703 The length must match the code generated by output_indirect call.
7704 The returned length includes the delay slot. Currently, the delay
7705 slot of an indirect call sequence is not exposed and it is used by
7706 the sequence itself. */
7709 attr_length_indirect_call (rtx insn)
7711 unsigned long distance = -1;
7712 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7714 if (INSN_ADDRESSES_SET_P ())
7716 distance = (total + insn_current_reference_address (insn));
7717 if (distance < total)
7724 if (TARGET_FAST_INDIRECT_CALLS
7725 || (!TARGET_PORTABLE_RUNTIME
7726 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
7727 || distance < 240000)))
7733 if (TARGET_PORTABLE_RUNTIME)
7736 /* Out of reach, can use ble. */
7741 output_indirect_call (rtx insn, rtx call_dest)
7747 xoperands[0] = call_dest;
7748 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7749 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7753 /* First the special case for kernels, level 0 systems, etc. */
7754 if (TARGET_FAST_INDIRECT_CALLS)
7755 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7757 /* Now the normal case -- we can reach $$dyncall directly or
7758 we're sure that we can get there via a long-branch stub.
7760 No need to check target flags as the length uniquely identifies
7761 the remaining cases. */
7762 if (attr_length_indirect_call (insn) == 8)
7764 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
7765 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
7766 variant of the B,L instruction can't be used on the SOM target. */
7767 if (TARGET_PA_20 && !TARGET_SOM)
7768 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7770 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7773 /* Long millicode call, but we are not generating PIC or portable runtime
7775 if (attr_length_indirect_call (insn) == 12)
7776 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7778 /* Long millicode call for portable runtime. */
7779 if (attr_length_indirect_call (insn) == 20)
7780 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7782 /* We need a long PIC call to $$dyncall. */
7783 xoperands[0] = NULL_RTX;
7784 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7785 if (TARGET_SOM || !TARGET_GAS)
7787 xoperands[0] = gen_label_rtx ();
7788 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7789 targetm.asm_out.internal_label (asm_out_file, "L",
7790 CODE_LABEL_NUMBER (xoperands[0]));
7791 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7795 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7796 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7799 output_asm_insn ("blr %%r0,%%r2", xoperands);
7800 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7804 /* Return the total length of the save and restore instructions needed for
7805 the data linkage table pointer (i.e., the PIC register) across the call
7806 instruction INSN. No-return calls do not require a save and restore.
7807 In addition, we may be able to avoid the save and restore for calls
7808 within the same translation unit. */
7811 attr_length_save_restore_dltp (rtx insn)
7813 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7819 /* In HPUX 8.0's shared library scheme, special relocations are needed
7820 for function labels if they might be passed to a function
7821 in a shared library (because shared libraries don't live in code
7822 space), and special magic is needed to construct their address. */
7825 hppa_encode_label (rtx sym)
7827 const char *str = XSTR (sym, 0);
7828 int len = strlen (str) + 1;
7831 p = newstr = alloca (len + 1);
7835 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7839 pa_encode_section_info (tree decl, rtx rtl, int first)
7841 int old_referenced = 0;
7843 if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
7845 = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED;
7847 default_encode_section_info (decl, rtl, first);
7849 if (first && TEXT_SPACE_P (decl))
7851 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7852 if (TREE_CODE (decl) == FUNCTION_DECL)
7853 hppa_encode_label (XEXP (rtl, 0));
7855 else if (old_referenced)
7856 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced;
7859 /* This is sort of inverse to pa_encode_section_info. */
7862 pa_strip_name_encoding (const char *str)
7864 str += (*str == '@');
7865 str += (*str == '*');
7870 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7872 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7875 /* Returns 1 if OP is a function label involved in a simple addition
7876 with a constant. Used to keep certain patterns from matching
7877 during instruction combination. */
7879 is_function_label_plus_const (rtx op)
7881 /* Strip off any CONST. */
7882 if (GET_CODE (op) == CONST)
7885 return (GET_CODE (op) == PLUS
7886 && function_label_operand (XEXP (op, 0), Pmode)
7887 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7890 /* Output assembly code for a thunk to FUNCTION. */
7893 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7894 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7897 static unsigned int current_thunk_number;
7898 int val_14 = VAL_14_BITS_P (delta);
7903 xoperands[0] = XEXP (DECL_RTL (function), 0);
7904 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7905 xoperands[2] = GEN_INT (delta);
7907 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7908 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7910 /* Output the thunk. We know that the function is in the same
7911 translation unit (i.e., the same space) as the thunk, and that
7912 thunks are output after their method. Thus, we don't need an
7913 external branch to reach the function. With SOM and GAS,
7914 functions and thunks are effectively in different sections.
7915 Thus, we can always use a IA-relative branch and the linker
7916 will add a long branch stub if necessary.
7918 However, we have to be careful when generating PIC code on the
7919 SOM port to ensure that the sequence does not transfer to an
7920 import stub for the target function as this could clobber the
7921 return value saved at SP-24. This would also apply to the
7922 32-bit linux port if the multi-space model is implemented. */
7923 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7924 && !(flag_pic && TREE_PUBLIC (function))
7925 && (TARGET_GAS || last_address < 262132))
7926 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7927 && ((targetm.have_named_sections
7928 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7929 /* The GNU 64-bit linker has rather poor stub management.
7930 So, we use a long branch from thunks that aren't in
7931 the same section as the target function. */
7933 && (DECL_SECTION_NAME (thunk_fndecl)
7934 != DECL_SECTION_NAME (function)))
7935 || ((DECL_SECTION_NAME (thunk_fndecl)
7936 == DECL_SECTION_NAME (function))
7937 && last_address < 262132)))
7938 || (!targetm.have_named_sections && last_address < 262132))))
7941 output_asm_insn ("addil L'%2,%%r26", xoperands);
7943 output_asm_insn ("b %0", xoperands);
7947 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7952 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7956 else if (TARGET_64BIT)
7958 /* We only have one call-clobbered scratch register, so we can't
7959 make use of the delay slot if delta doesn't fit in 14 bits. */
7962 output_asm_insn ("addil L'%2,%%r26", xoperands);
7963 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7966 output_asm_insn ("b,l .+8,%%r1", xoperands);
7970 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7971 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7975 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7976 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7981 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7982 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7987 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7991 else if (TARGET_PORTABLE_RUNTIME)
7993 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7994 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7997 output_asm_insn ("addil L'%2,%%r26", xoperands);
7999 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8003 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8008 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8012 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8014 /* The function is accessible from outside this module. The only
8015 way to avoid an import stub between the thunk and function is to
8016 call the function directly with an indirect sequence similar to
8017 that used by $$dyncall. This is possible because $$dyncall acts
8018 as the import stub in an indirect call. */
8019 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
8020 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8021 output_asm_insn ("addil LT'%3,%%r19", xoperands);
8022 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
8023 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8024 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
8025 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
8026 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
8027 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8031 output_asm_insn ("addil L'%2,%%r26", xoperands);
8037 output_asm_insn ("bve (%%r22)", xoperands);
8040 else if (TARGET_NO_SPACE_REGS)
8042 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
8047 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
8048 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
8049 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
8054 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8056 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8060 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8062 if (TARGET_SOM || !TARGET_GAS)
8064 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
8065 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
8069 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8070 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
8074 output_asm_insn ("addil L'%2,%%r26", xoperands);
8076 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8080 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8085 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8092 output_asm_insn ("addil L'%2,%%r26", xoperands);
8094 output_asm_insn ("ldil L'%0,%%r22", xoperands);
8095 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
8099 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8104 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8109 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8111 if (TARGET_SOM && TARGET_GAS)
8113 /* We done with this subspace except possibly for some additional
8114 debug information. Forget that we are in this subspace to ensure
8115 that the next function is output in its own subspace. */
8117 cfun->machine->in_nsubspa = 2;
8120 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8122 switch_to_section (data_section);
8123 output_asm_insn (".align 4", xoperands);
8124 ASM_OUTPUT_LABEL (file, label);
8125 output_asm_insn (".word P'%0", xoperands);
8128 current_thunk_number++;
8129 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8130 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8131 last_address += nbytes;
8132 update_total_code_bytes (nbytes);
8135 /* Only direct calls to static functions are allowed to be sibling (tail)
8138 This restriction is necessary because some linker generated stubs will
8139 store return pointers into rp' in some cases which might clobber a
8140 live value already in rp'.
8142 In a sibcall the current function and the target function share stack
8143 space. Thus if the path to the current function and the path to the
8144 target function save a value in rp', they save the value into the
8145 same stack slot, which has undesirable consequences.
8147 Because of the deferred binding nature of shared libraries any function
8148 with external scope could be in a different load module and thus require
8149 rp' to be saved when calling that function. So sibcall optimizations
8150 can only be safe for static function.
8152 Note that GCC never needs return value relocations, so we don't have to
8153 worry about static calls with return value relocations (which require
8156 It is safe to perform a sibcall optimization when the target function
8157 will never return. */
8159 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8161 if (TARGET_PORTABLE_RUNTIME)
8164 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8165 single subspace mode and the call is not indirect. As far as I know,
8166 there is no operating system support for the multiple subspace mode.
8167 It might be possible to support indirect calls if we didn't use
8168 $$dyncall (see the indirect sequence generated in output_call). */
8170 return (decl != NULL_TREE);
8172 /* Sibcalls are not ok because the arg pointer register is not a fixed
8173 register. This prevents the sibcall optimization from occurring. In
8174 addition, there are problems with stub placement using GNU ld. This
8175 is because a normal sibcall branch uses a 17-bit relocation while
8176 a regular call branch uses a 22-bit relocation. As a result, more
8177 care needs to be taken in the placement of long-branch stubs. */
8181 /* Sibcalls are only ok within a translation unit. */
8182 return (decl && !TREE_PUBLIC (decl));
8185 /* ??? Addition is not commutative on the PA due to the weird implicit
8186 space register selection rules for memory addresses. Therefore, we
8187 don't consider a + b == b + a, as this might be inside a MEM. */
8189 pa_commutative_p (const_rtx x, int outer_code)
8191 return (COMMUTATIVE_P (x)
8192 && (TARGET_NO_SPACE_REGS
8193 || (outer_code != UNKNOWN && outer_code != MEM)
8194 || GET_CODE (x) != PLUS));
8197 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8198 use in fmpyadd instructions. */
8200 fmpyaddoperands (rtx *operands)
8202 enum machine_mode mode = GET_MODE (operands[0]);
8204 /* Must be a floating point mode. */
8205 if (mode != SFmode && mode != DFmode)
8208 /* All modes must be the same. */
8209 if (! (mode == GET_MODE (operands[1])
8210 && mode == GET_MODE (operands[2])
8211 && mode == GET_MODE (operands[3])
8212 && mode == GET_MODE (operands[4])
8213 && mode == GET_MODE (operands[5])))
8216 /* All operands must be registers. */
8217 if (! (GET_CODE (operands[1]) == REG
8218 && GET_CODE (operands[2]) == REG
8219 && GET_CODE (operands[3]) == REG
8220 && GET_CODE (operands[4]) == REG
8221 && GET_CODE (operands[5]) == REG))
8224 /* Only 2 real operands to the addition. One of the input operands must
8225 be the same as the output operand. */
8226 if (! rtx_equal_p (operands[3], operands[4])
8227 && ! rtx_equal_p (operands[3], operands[5]))
8230 /* Inout operand of add cannot conflict with any operands from multiply. */
8231 if (rtx_equal_p (operands[3], operands[0])
8232 || rtx_equal_p (operands[3], operands[1])
8233 || rtx_equal_p (operands[3], operands[2]))
8236 /* multiply cannot feed into addition operands. */
8237 if (rtx_equal_p (operands[4], operands[0])
8238 || rtx_equal_p (operands[5], operands[0]))
8241 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8243 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8244 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8245 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8246 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8247 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8248 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8251 /* Passed. Operands are suitable for fmpyadd. */
8255 #if !defined(USE_COLLECT2)
8257 pa_asm_out_constructor (rtx symbol, int priority)
8259 if (!function_label_operand (symbol, VOIDmode))
8260 hppa_encode_label (symbol);
8262 #ifdef CTORS_SECTION_ASM_OP
8263 default_ctor_section_asm_out_constructor (symbol, priority);
8265 # ifdef TARGET_ASM_NAMED_SECTION
8266 default_named_section_asm_out_constructor (symbol, priority);
8268 default_stabs_asm_out_constructor (symbol, priority);
8274 pa_asm_out_destructor (rtx symbol, int priority)
8276 if (!function_label_operand (symbol, VOIDmode))
8277 hppa_encode_label (symbol);
8279 #ifdef DTORS_SECTION_ASM_OP
8280 default_dtor_section_asm_out_destructor (symbol, priority);
8282 # ifdef TARGET_ASM_NAMED_SECTION
8283 default_named_section_asm_out_destructor (symbol, priority);
8285 default_stabs_asm_out_destructor (symbol, priority);
8291 /* This function places uninitialized global data in the bss section.
8292 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8293 function on the SOM port to prevent uninitialized global data from
8294 being placed in the data section. */
8297 pa_asm_output_aligned_bss (FILE *stream,
8299 unsigned HOST_WIDE_INT size,
8302 switch_to_section (bss_section);
8303 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8305 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8306 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8309 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8310 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8313 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8314 ASM_OUTPUT_LABEL (stream, name);
8315 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8318 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8319 that doesn't allow the alignment of global common storage to be directly
8320 specified. The SOM linker aligns common storage based on the rounded
8321 value of the NUM_BYTES parameter in the .comm directive. It's not
8322 possible to use the .align directive as it doesn't affect the alignment
8323 of the label associated with a .comm directive. */
8326 pa_asm_output_aligned_common (FILE *stream,
8328 unsigned HOST_WIDE_INT size,
8331 unsigned int max_common_align;
8333 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8334 if (align > max_common_align)
8336 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8337 "for global common data. Using %u",
8338 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8339 align = max_common_align;
8342 switch_to_section (bss_section);
8344 assemble_name (stream, name);
8345 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8346 MAX (size, align / BITS_PER_UNIT));
8349 /* We can't use .comm for local common storage as the SOM linker effectively
8350 treats the symbol as universal and uses the same storage for local symbols
8351 with the same name in different object files. The .block directive
8352 reserves an uninitialized block of storage. However, it's not common
8353 storage. Fortunately, GCC never requests common storage with the same
8354 name in any given translation unit. */
8357 pa_asm_output_aligned_local (FILE *stream,
8359 unsigned HOST_WIDE_INT size,
8362 switch_to_section (bss_section);
8363 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8366 fprintf (stream, "%s", LOCAL_ASM_OP);
8367 assemble_name (stream, name);
8368 fprintf (stream, "\n");
8371 ASM_OUTPUT_LABEL (stream, name);
8372 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8375 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8376 use in fmpysub instructions. */
8378 fmpysuboperands (rtx *operands)
8380 enum machine_mode mode = GET_MODE (operands[0]);
8382 /* Must be a floating point mode. */
8383 if (mode != SFmode && mode != DFmode)
8386 /* All modes must be the same. */
8387 if (! (mode == GET_MODE (operands[1])
8388 && mode == GET_MODE (operands[2])
8389 && mode == GET_MODE (operands[3])
8390 && mode == GET_MODE (operands[4])
8391 && mode == GET_MODE (operands[5])))
8394 /* All operands must be registers. */
8395 if (! (GET_CODE (operands[1]) == REG
8396 && GET_CODE (operands[2]) == REG
8397 && GET_CODE (operands[3]) == REG
8398 && GET_CODE (operands[4]) == REG
8399 && GET_CODE (operands[5]) == REG))
8402 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8403 operation, so operands[4] must be the same as operand[3]. */
8404 if (! rtx_equal_p (operands[3], operands[4]))
8407 /* multiply cannot feed into subtraction. */
8408 if (rtx_equal_p (operands[5], operands[0]))
8411 /* Inout operand of sub cannot conflict with any operands from multiply. */
8412 if (rtx_equal_p (operands[3], operands[0])
8413 || rtx_equal_p (operands[3], operands[1])
8414 || rtx_equal_p (operands[3], operands[2]))
8417 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8419 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8420 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8421 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8422 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8423 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8424 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8427 /* Passed. Operands are suitable for fmpysub. */
8431 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8432 constants for shadd instructions. */
8434 shadd_constant_p (int val)
8436 if (val == 2 || val == 4 || val == 8)
8442 /* Return 1 if OP is valid as a base or index register in a
8446 borx_reg_operand (rtx op, enum machine_mode mode)
8448 if (GET_CODE (op) != REG)
8451 /* We must reject virtual registers as the only expressions that
8452 can be instantiated are REG and REG+CONST. */
8453 if (op == virtual_incoming_args_rtx
8454 || op == virtual_stack_vars_rtx
8455 || op == virtual_stack_dynamic_rtx
8456 || op == virtual_outgoing_args_rtx
8457 || op == virtual_cfa_rtx)
8460 /* While it's always safe to index off the frame pointer, it's not
8461 profitable to do so when the frame pointer is being eliminated. */
8462 if (!reload_completed
8463 && flag_omit_frame_pointer
8464 && !current_function_calls_alloca
8465 && op == frame_pointer_rtx)
8468 return register_operand (op, mode);
8471 /* Return 1 if this operand is anything other than a hard register. */
8474 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8476 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8479 /* Return 1 if INSN branches forward. Should be using insn_addresses
8480 to avoid walking through all the insns... */
8482 forward_branch_p (rtx insn)
8484 rtx label = JUMP_LABEL (insn);
8491 insn = NEXT_INSN (insn);
8494 return (insn == label);
8497 /* Return 1 if OP is an equality comparison, else return 0. */
8499 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8501 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8504 /* Return 1 if INSN is in the delay slot of a call instruction. */
8506 jump_in_call_delay (rtx insn)
8509 if (GET_CODE (insn) != JUMP_INSN)
8512 if (PREV_INSN (insn)
8513 && PREV_INSN (PREV_INSN (insn))
8514 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8516 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8518 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8519 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8526 /* Output an unconditional move and branch insn. */
8529 output_parallel_movb (rtx *operands, rtx insn)
8531 int length = get_attr_length (insn);
8533 /* These are the cases in which we win. */
8535 return "mov%I1b,tr %1,%0,%2";
8537 /* None of the following cases win, but they don't lose either. */
8540 if (dbr_sequence_length () == 0)
8542 /* Nothing in the delay slot, fake it by putting the combined
8543 insn (the copy or add) in the delay slot of a bl. */
8544 if (GET_CODE (operands[1]) == CONST_INT)
8545 return "b %2\n\tldi %1,%0";
8547 return "b %2\n\tcopy %1,%0";
8551 /* Something in the delay slot, but we've got a long branch. */
8552 if (GET_CODE (operands[1]) == CONST_INT)
8553 return "ldi %1,%0\n\tb %2";
8555 return "copy %1,%0\n\tb %2";
8559 if (GET_CODE (operands[1]) == CONST_INT)
8560 output_asm_insn ("ldi %1,%0", operands);
8562 output_asm_insn ("copy %1,%0", operands);
8563 return output_lbranch (operands[2], insn, 1);
8566 /* Output an unconditional add and branch insn. */
8569 output_parallel_addb (rtx *operands, rtx insn)
8571 int length = get_attr_length (insn);
8573 /* To make life easy we want operand0 to be the shared input/output
8574 operand and operand1 to be the readonly operand. */
8575 if (operands[0] == operands[1])
8576 operands[1] = operands[2];
8578 /* These are the cases in which we win. */
8580 return "add%I1b,tr %1,%0,%3";
8582 /* None of the following cases win, but they don't lose either. */
8585 if (dbr_sequence_length () == 0)
8586 /* Nothing in the delay slot, fake it by putting the combined
8587 insn (the copy or add) in the delay slot of a bl. */
8588 return "b %3\n\tadd%I1 %1,%0,%0";
8590 /* Something in the delay slot, but we've got a long branch. */
8591 return "add%I1 %1,%0,%0\n\tb %3";
8594 output_asm_insn ("add%I1 %1,%0,%0", operands);
8595 return output_lbranch (operands[3], insn, 1);
8598 /* Return nonzero if INSN (a jump insn) immediately follows a call
8599 to a named function. This is used to avoid filling the delay slot
8600 of the jump since it can usually be eliminated by modifying RP in
8601 the delay slot of the call. */
8604 following_call (rtx insn)
8606 if (! TARGET_JUMP_IN_DELAY)
8609 /* Find the previous real insn, skipping NOTEs. */
8610 insn = PREV_INSN (insn);
8611 while (insn && GET_CODE (insn) == NOTE)
8612 insn = PREV_INSN (insn);
8614 /* Check for CALL_INSNs and millicode calls. */
8616 && ((GET_CODE (insn) == CALL_INSN
8617 && get_attr_type (insn) != TYPE_DYNCALL)
8618 || (GET_CODE (insn) == INSN
8619 && GET_CODE (PATTERN (insn)) != SEQUENCE
8620 && GET_CODE (PATTERN (insn)) != USE
8621 && GET_CODE (PATTERN (insn)) != CLOBBER
8622 && get_attr_type (insn) == TYPE_MILLI)))
8628 /* We use this hook to perform a PA specific optimization which is difficult
8629 to do in earlier passes.
8631 We want the delay slots of branches within jump tables to be filled.
8632 None of the compiler passes at the moment even has the notion that a
8633 PA jump table doesn't contain addresses, but instead contains actual
8636 Because we actually jump into the table, the addresses of each entry
8637 must stay constant in relation to the beginning of the table (which
8638 itself must stay constant relative to the instruction to jump into
8639 it). I don't believe we can guarantee earlier passes of the compiler
8640 will adhere to those rules.
8642 So, late in the compilation process we find all the jump tables, and
8643 expand them into real code -- e.g. each entry in the jump table vector
8644 will get an appropriate label followed by a jump to the final target.
8646 Reorg and the final jump pass can then optimize these branches and
8647 fill their delay slots. We end up with smaller, more efficient code.
8649 The jump instructions within the table are special; we must be able
8650 to identify them during assembly output (if the jumps don't get filled
8651 we need to emit a nop rather than nullifying the delay slot)). We
8652 identify jumps in switch tables by using insns with the attribute
8653 type TYPE_BTABLE_BRANCH.
8655 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8656 insns. This serves two purposes, first it prevents jump.c from
8657 noticing that the last N entries in the table jump to the instruction
8658 immediately after the table and deleting the jumps. Second, those
8659 insns mark where we should emit .begin_brtab and .end_brtab directives
8660 when using GAS (allows for better link time optimizations). */
8667 remove_useless_addtr_insns (1);
8669 if (pa_cpu < PROCESSOR_8000)
8670 pa_combine_instructions ();
8673 /* This is fairly cheap, so always run it if optimizing. */
8674 if (optimize > 0 && !TARGET_BIG_SWITCH)
8676 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8677 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8679 rtx pattern, tmp, location, label;
8680 unsigned int length, i;
8682 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8683 if (GET_CODE (insn) != JUMP_INSN
8684 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8685 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8688 /* Emit marker for the beginning of the branch table. */
8689 emit_insn_before (gen_begin_brtab (), insn);
8691 pattern = PATTERN (insn);
8692 location = PREV_INSN (insn);
8693 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8695 for (i = 0; i < length; i++)
8697 /* Emit a label before each jump to keep jump.c from
8698 removing this code. */
8699 tmp = gen_label_rtx ();
8700 LABEL_NUSES (tmp) = 1;
8701 emit_label_after (tmp, location);
8702 location = NEXT_INSN (location);
8704 if (GET_CODE (pattern) == ADDR_VEC)
8705 label = XEXP (XVECEXP (pattern, 0, i), 0);
8707 label = XEXP (XVECEXP (pattern, 1, i), 0);
8709 tmp = gen_short_jump (label);
8711 /* Emit the jump itself. */
8712 tmp = emit_jump_insn_after (tmp, location);
8713 JUMP_LABEL (tmp) = label;
8714 LABEL_NUSES (label)++;
8715 location = NEXT_INSN (location);
8717 /* Emit a BARRIER after the jump. */
8718 emit_barrier_after (location);
8719 location = NEXT_INSN (location);
8722 /* Emit marker for the end of the branch table. */
8723 emit_insn_before (gen_end_brtab (), location);
8724 location = NEXT_INSN (location);
8725 emit_barrier_after (location);
8727 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8733 /* Still need brtab marker insns. FIXME: the presence of these
8734 markers disables output of the branch table to readonly memory,
8735 and any alignment directives that might be needed. Possibly,
8736 the begin_brtab insn should be output before the label for the
8737 table. This doesn't matter at the moment since the tables are
8738 always output in the text section. */
8739 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8741 /* Find an ADDR_VEC insn. */
8742 if (GET_CODE (insn) != JUMP_INSN
8743 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8744 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8747 /* Now generate markers for the beginning and end of the
8749 emit_insn_before (gen_begin_brtab (), insn);
8750 emit_insn_after (gen_end_brtab (), insn);
8755 /* The PA has a number of odd instructions which can perform multiple
8756 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8757 it may be profitable to combine two instructions into one instruction
8758 with two outputs. It's not profitable PA2.0 machines because the
8759 two outputs would take two slots in the reorder buffers.
8761 This routine finds instructions which can be combined and combines
8762 them. We only support some of the potential combinations, and we
8763 only try common ways to find suitable instructions.
8765 * addb can add two registers or a register and a small integer
8766 and jump to a nearby (+-8k) location. Normally the jump to the
8767 nearby location is conditional on the result of the add, but by
8768 using the "true" condition we can make the jump unconditional.
8769 Thus addb can perform two independent operations in one insn.
8771 * movb is similar to addb in that it can perform a reg->reg
8772 or small immediate->reg copy and jump to a nearby (+-8k location).
8774 * fmpyadd and fmpysub can perform a FP multiply and either an
8775 FP add or FP sub if the operands of the multiply and add/sub are
8776 independent (there are other minor restrictions). Note both
8777 the fmpy and fadd/fsub can in theory move to better spots according
8778 to data dependencies, but for now we require the fmpy stay at a
8781 * Many of the memory operations can perform pre & post updates
8782 of index registers. GCC's pre/post increment/decrement addressing
8783 is far too simple to take advantage of all the possibilities. This
8784 pass may not be suitable since those insns may not be independent.
8786 * comclr can compare two ints or an int and a register, nullify
8787 the following instruction and zero some other register. This
8788 is more difficult to use as it's harder to find an insn which
8789 will generate a comclr than finding something like an unconditional
8790 branch. (conditional moves & long branches create comclr insns).
8792 * Most arithmetic operations can conditionally skip the next
8793 instruction. They can be viewed as "perform this operation
8794 and conditionally jump to this nearby location" (where nearby
8795 is an insns away). These are difficult to use due to the
8796 branch length restrictions. */
8799 pa_combine_instructions (void)
8803 /* This can get expensive since the basic algorithm is on the
8804 order of O(n^2) (or worse). Only do it for -O2 or higher
8805 levels of optimization. */
8809 /* Walk down the list of insns looking for "anchor" insns which
8810 may be combined with "floating" insns. As the name implies,
8811 "anchor" instructions don't move, while "floating" insns may
8813 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8814 new = make_insn_raw (new);
8816 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8818 enum attr_pa_combine_type anchor_attr;
8819 enum attr_pa_combine_type floater_attr;
8821 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8822 Also ignore any special USE insns. */
8823 if ((GET_CODE (anchor) != INSN
8824 && GET_CODE (anchor) != JUMP_INSN
8825 && GET_CODE (anchor) != CALL_INSN)
8826 || GET_CODE (PATTERN (anchor)) == USE
8827 || GET_CODE (PATTERN (anchor)) == CLOBBER
8828 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8829 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8832 anchor_attr = get_attr_pa_combine_type (anchor);
8833 /* See if anchor is an insn suitable for combination. */
8834 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8835 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8836 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8837 && ! forward_branch_p (anchor)))
8841 for (floater = PREV_INSN (anchor);
8843 floater = PREV_INSN (floater))
8845 if (GET_CODE (floater) == NOTE
8846 || (GET_CODE (floater) == INSN
8847 && (GET_CODE (PATTERN (floater)) == USE
8848 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8851 /* Anything except a regular INSN will stop our search. */
8852 if (GET_CODE (floater) != INSN
8853 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8854 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8860 /* See if FLOATER is suitable for combination with the
8862 floater_attr = get_attr_pa_combine_type (floater);
8863 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8864 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8865 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8866 && floater_attr == PA_COMBINE_TYPE_FMPY))
8868 /* If ANCHOR and FLOATER can be combined, then we're
8869 done with this pass. */
8870 if (pa_can_combine_p (new, anchor, floater, 0,
8871 SET_DEST (PATTERN (floater)),
8872 XEXP (SET_SRC (PATTERN (floater)), 0),
8873 XEXP (SET_SRC (PATTERN (floater)), 1)))
8877 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8878 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8880 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8882 if (pa_can_combine_p (new, anchor, floater, 0,
8883 SET_DEST (PATTERN (floater)),
8884 XEXP (SET_SRC (PATTERN (floater)), 0),
8885 XEXP (SET_SRC (PATTERN (floater)), 1)))
8890 if (pa_can_combine_p (new, anchor, floater, 0,
8891 SET_DEST (PATTERN (floater)),
8892 SET_SRC (PATTERN (floater)),
8893 SET_SRC (PATTERN (floater))))
8899 /* If we didn't find anything on the backwards scan try forwards. */
8901 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8902 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8904 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8906 if (GET_CODE (floater) == NOTE
8907 || (GET_CODE (floater) == INSN
8908 && (GET_CODE (PATTERN (floater)) == USE
8909 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8913 /* Anything except a regular INSN will stop our search. */
8914 if (GET_CODE (floater) != INSN
8915 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8916 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8922 /* See if FLOATER is suitable for combination with the
8924 floater_attr = get_attr_pa_combine_type (floater);
8925 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8926 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8927 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8928 && floater_attr == PA_COMBINE_TYPE_FMPY))
8930 /* If ANCHOR and FLOATER can be combined, then we're
8931 done with this pass. */
8932 if (pa_can_combine_p (new, anchor, floater, 1,
8933 SET_DEST (PATTERN (floater)),
8934 XEXP (SET_SRC (PATTERN (floater)),
8936 XEXP (SET_SRC (PATTERN (floater)),
8943 /* FLOATER will be nonzero if we found a suitable floating
8944 insn for combination with ANCHOR. */
8946 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8947 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8949 /* Emit the new instruction and delete the old anchor. */
8950 emit_insn_before (gen_rtx_PARALLEL
8952 gen_rtvec (2, PATTERN (anchor),
8953 PATTERN (floater))),
8956 SET_INSN_DELETED (anchor);
8958 /* Emit a special USE insn for FLOATER, then delete
8959 the floating insn. */
8960 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8961 delete_insn (floater);
8966 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8969 /* Emit the new_jump instruction and delete the old anchor. */
8971 = emit_jump_insn_before (gen_rtx_PARALLEL
8973 gen_rtvec (2, PATTERN (anchor),
8974 PATTERN (floater))),
8977 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8978 SET_INSN_DELETED (anchor);
8980 /* Emit a special USE insn for FLOATER, then delete
8981 the floating insn. */
8982 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8983 delete_insn (floater);
8991 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8994 int insn_code_number;
8997 /* Create a PARALLEL with the patterns of ANCHOR and
8998 FLOATER, try to recognize it, then test constraints
8999 for the resulting pattern.
9001 If the pattern doesn't match or the constraints
9002 aren't met keep searching for a suitable floater
9004 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
9005 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
9006 INSN_CODE (new) = -1;
9007 insn_code_number = recog_memoized (new);
9008 if (insn_code_number < 0
9009 || (extract_insn (new), ! constrain_operands (1)))
9023 /* There's up to three operands to consider. One
9024 output and two inputs.
9026 The output must not be used between FLOATER & ANCHOR
9027 exclusive. The inputs must not be set between
9028 FLOATER and ANCHOR exclusive. */
9030 if (reg_used_between_p (dest, start, end))
9033 if (reg_set_between_p (src1, start, end))
9036 if (reg_set_between_p (src2, start, end))
9039 /* If we get here, then everything is good. */
9043 /* Return nonzero if references for INSN are delayed.
9045 Millicode insns are actually function calls with some special
9046 constraints on arguments and register usage.
9048 Millicode calls always expect their arguments in the integer argument
9049 registers, and always return their result in %r29 (ret1). They
9050 are expected to clobber their arguments, %r1, %r29, and the return
9051 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9053 This function tells reorg that the references to arguments and
9054 millicode calls do not appear to happen until after the millicode call.
9055 This allows reorg to put insns which set the argument registers into the
9056 delay slot of the millicode call -- thus they act more like traditional
9059 Note we cannot consider side effects of the insn to be delayed because
9060 the branch and link insn will clobber the return pointer. If we happened
9061 to use the return pointer in the delay slot of the call, then we lose.
9063 get_attr_type will try to recognize the given insn, so make sure to
9064 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9067 insn_refs_are_delayed (rtx insn)
9069 return ((GET_CODE (insn) == INSN
9070 && GET_CODE (PATTERN (insn)) != SEQUENCE
9071 && GET_CODE (PATTERN (insn)) != USE
9072 && GET_CODE (PATTERN (insn)) != CLOBBER
9073 && get_attr_type (insn) == TYPE_MILLI));
9076 /* On the HP-PA the value is found in register(s) 28(-29), unless
9077 the mode is SF or DF. Then the value is returned in fr4 (32).
9079 This must perform the same promotions as PROMOTE_MODE, else
9080 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
9082 Small structures must be returned in a PARALLEL on PA64 in order
9083 to match the HP Compiler ABI. */
9086 function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
9088 enum machine_mode valmode;
9090 if (AGGREGATE_TYPE_P (valtype)
9091 || TREE_CODE (valtype) == COMPLEX_TYPE
9092 || TREE_CODE (valtype) == VECTOR_TYPE)
9096 /* Aggregates with a size less than or equal to 128 bits are
9097 returned in GR 28(-29). They are left justified. The pad
9098 bits are undefined. Larger aggregates are returned in
9102 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9104 for (i = 0; i < ub; i++)
9106 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9107 gen_rtx_REG (DImode, 28 + i),
9112 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9114 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9116 /* Aggregates 5 to 8 bytes in size are returned in general
9117 registers r28-r29 in the same manner as other non
9118 floating-point objects. The data is right-justified and
9119 zero-extended to 64 bits. This is opposite to the normal
9120 justification used on big endian targets and requires
9121 special treatment. */
9122 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9123 gen_rtx_REG (DImode, 28), const0_rtx);
9124 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9128 if ((INTEGRAL_TYPE_P (valtype)
9129 && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD)
9130 || POINTER_TYPE_P (valtype))
9131 valmode = word_mode;
9133 valmode = TYPE_MODE (valtype);
9135 if (TREE_CODE (valtype) == REAL_TYPE
9136 && !AGGREGATE_TYPE_P (valtype)
9137 && TYPE_MODE (valtype) != TFmode
9138 && !TARGET_SOFT_FLOAT)
9139 return gen_rtx_REG (valmode, 32);
9141 return gen_rtx_REG (valmode, 28);
9144 /* Return the location of a parameter that is passed in a register or NULL
9145 if the parameter has any component that is passed in memory.
9147 This is new code and will be pushed to into the net sources after
9150 ??? We might want to restructure this so that it looks more like other
9153 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
9154 int named ATTRIBUTE_UNUSED)
9156 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9163 if (mode == VOIDmode)
9166 arg_size = FUNCTION_ARG_SIZE (mode, type);
9168 /* If this arg would be passed partially or totally on the stack, then
9169 this routine should return zero. pa_arg_partial_bytes will
9170 handle arguments which are split between regs and stack slots if
9171 the ABI mandates split arguments. */
9174 /* The 32-bit ABI does not split arguments. */
9175 if (cum->words + arg_size > max_arg_words)
9181 alignment = cum->words & 1;
9182 if (cum->words + alignment >= max_arg_words)
9186 /* The 32bit ABIs and the 64bit ABIs are rather different,
9187 particularly in their handling of FP registers. We might
9188 be able to cleverly share code between them, but I'm not
9189 going to bother in the hope that splitting them up results
9190 in code that is more easily understood. */
9194 /* Advance the base registers to their current locations.
9196 Remember, gprs grow towards smaller register numbers while
9197 fprs grow to higher register numbers. Also remember that
9198 although FP regs are 32-bit addressable, we pretend that
9199 the registers are 64-bits wide. */
9200 gpr_reg_base = 26 - cum->words;
9201 fpr_reg_base = 32 + cum->words;
9203 /* Arguments wider than one word and small aggregates need special
9207 || (type && (AGGREGATE_TYPE_P (type)
9208 || TREE_CODE (type) == COMPLEX_TYPE
9209 || TREE_CODE (type) == VECTOR_TYPE)))
9211 /* Double-extended precision (80-bit), quad-precision (128-bit)
9212 and aggregates including complex numbers are aligned on
9213 128-bit boundaries. The first eight 64-bit argument slots
9214 are associated one-to-one, with general registers r26
9215 through r19, and also with floating-point registers fr4
9216 through fr11. Arguments larger than one word are always
9217 passed in general registers.
9219 Using a PARALLEL with a word mode register results in left
9220 justified data on a big-endian target. */
9223 int i, offset = 0, ub = arg_size;
9225 /* Align the base register. */
9226 gpr_reg_base -= alignment;
9228 ub = MIN (ub, max_arg_words - cum->words - alignment);
9229 for (i = 0; i < ub; i++)
9231 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9232 gen_rtx_REG (DImode, gpr_reg_base),
9238 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9243 /* If the argument is larger than a word, then we know precisely
9244 which registers we must use. */
9258 /* Structures 5 to 8 bytes in size are passed in the general
9259 registers in the same manner as other non floating-point
9260 objects. The data is right-justified and zero-extended
9261 to 64 bits. This is opposite to the normal justification
9262 used on big endian targets and requires special treatment.
9263 We now define BLOCK_REG_PADDING to pad these objects.
9264 Aggregates, complex and vector types are passed in the same
9265 manner as structures. */
9267 || (type && (AGGREGATE_TYPE_P (type)
9268 || TREE_CODE (type) == COMPLEX_TYPE
9269 || TREE_CODE (type) == VECTOR_TYPE)))
9271 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9272 gen_rtx_REG (DImode, gpr_reg_base),
9274 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9279 /* We have a single word (32 bits). A simple computation
9280 will get us the register #s we need. */
9281 gpr_reg_base = 26 - cum->words;
9282 fpr_reg_base = 32 + 2 * cum->words;
9286 /* Determine if the argument needs to be passed in both general and
9287 floating point registers. */
9288 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9289 /* If we are doing soft-float with portable runtime, then there
9290 is no need to worry about FP regs. */
9291 && !TARGET_SOFT_FLOAT
9292 /* The parameter must be some kind of scalar float, else we just
9293 pass it in integer registers. */
9294 && GET_MODE_CLASS (mode) == MODE_FLOAT
9295 /* The target function must not have a prototype. */
9296 && cum->nargs_prototype <= 0
9297 /* libcalls do not need to pass items in both FP and general
9299 && type != NULL_TREE
9300 /* All this hair applies to "outgoing" args only. This includes
9301 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9303 /* Also pass outgoing floating arguments in both registers in indirect
9304 calls with the 32 bit ABI and the HP assembler since there is no
9305 way to the specify argument locations in static functions. */
9310 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9316 gen_rtx_EXPR_LIST (VOIDmode,
9317 gen_rtx_REG (mode, fpr_reg_base),
9319 gen_rtx_EXPR_LIST (VOIDmode,
9320 gen_rtx_REG (mode, gpr_reg_base),
9325 /* See if we should pass this parameter in a general register. */
9326 if (TARGET_SOFT_FLOAT
9327 /* Indirect calls in the normal 32bit ABI require all arguments
9328 to be passed in general registers. */
9329 || (!TARGET_PORTABLE_RUNTIME
9333 /* If the parameter is not a scalar floating-point parameter,
9334 then it belongs in GPRs. */
9335 || GET_MODE_CLASS (mode) != MODE_FLOAT
9336 /* Structure with single SFmode field belongs in GPR. */
9337 || (type && AGGREGATE_TYPE_P (type)))
9338 retval = gen_rtx_REG (mode, gpr_reg_base);
9340 retval = gen_rtx_REG (mode, fpr_reg_base);
9346 /* If this arg would be passed totally in registers or totally on the stack,
9347 then this routine should return zero. */
9350 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9351 tree type, bool named ATTRIBUTE_UNUSED)
9353 unsigned int max_arg_words = 8;
9354 unsigned int offset = 0;
9359 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9362 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9363 /* Arg fits fully into registers. */
9365 else if (cum->words + offset >= max_arg_words)
9366 /* Arg fully on the stack. */
9370 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9374 /* A get_unnamed_section callback for switching to the text section.
9376 This function is only used with SOM. Because we don't support
9377 named subspaces, we can only create a new subspace or switch back
9378 to the default text subspace. */
9381 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9383 gcc_assert (TARGET_SOM);
9386 if (cfun && cfun->machine && !cfun->machine->in_nsubspa)
9388 /* We only want to emit a .nsubspa directive once at the
9389 start of the function. */
9390 cfun->machine->in_nsubspa = 1;
9392 /* Create a new subspace for the text. This provides
9393 better stub placement and one-only functions. */
9395 && DECL_ONE_ONLY (cfun->decl)
9396 && !DECL_WEAK (cfun->decl))
9398 output_section_asm_op ("\t.SPACE $TEXT$\n"
9399 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9400 "ACCESS=44,SORT=24,COMDAT");
9406 /* There isn't a current function or the body of the current
9407 function has been completed. So, we are changing to the
9408 text section to output debugging information. Thus, we
9409 need to forget that we are in the text section so that
9410 varasm.c will call us when text_section is selected again. */
9411 gcc_assert (!cfun || !cfun->machine
9412 || cfun->machine->in_nsubspa == 2);
9415 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9418 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9421 /* A get_unnamed_section callback for switching to comdat data
9422 sections. This function is only used with SOM. */
9425 som_output_comdat_data_section_asm_op (const void *data)
9428 output_section_asm_op (data);
9431 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9434 pa_som_asm_init_sections (void)
9437 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9439 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9440 is not being generated. */
9441 som_readonly_data_section
9442 = get_unnamed_section (0, output_section_asm_op,
9443 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9445 /* When secondary definitions are not supported, SOM makes readonly
9446 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9448 som_one_only_readonly_data_section
9449 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9451 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9452 "ACCESS=0x2c,SORT=16,COMDAT");
9455 /* When secondary definitions are not supported, SOM makes data one-only
9456 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9457 som_one_only_data_section
9458 = get_unnamed_section (SECTION_WRITE,
9459 som_output_comdat_data_section_asm_op,
9460 "\t.SPACE $PRIVATE$\n"
9461 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9462 "ACCESS=31,SORT=24,COMDAT");
9464 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9465 which reference data within the $TEXT$ space (for example constant
9466 strings in the $LIT$ subspace).
9468 The assemblers (GAS and HP as) both have problems with handling
9469 the difference of two symbols which is the other correct way to
9470 reference constant data during PIC code generation.
9472 So, there's no way to reference constant data which is in the
9473 $TEXT$ space during PIC generation. Instead place all constant
9474 data into the $PRIVATE$ subspace (this reduces sharing, but it
9475 works correctly). */
9476 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9478 /* We must not have a reference to an external symbol defined in a
9479 shared library in a readonly section, else the SOM linker will
9482 So, we force exception information into the data section. */
9483 exception_section = data_section;
9486 /* On hpux10, the linker will give an error if we have a reference
9487 in the read-only data section to a symbol defined in a shared
9488 library. Therefore, expressions that might require a reloc can
9489 not be placed in the read-only data section. */
9492 pa_select_section (tree exp, int reloc,
9493 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9495 if (TREE_CODE (exp) == VAR_DECL
9496 && TREE_READONLY (exp)
9497 && !TREE_THIS_VOLATILE (exp)
9498 && DECL_INITIAL (exp)
9499 && (DECL_INITIAL (exp) == error_mark_node
9500 || TREE_CONSTANT (DECL_INITIAL (exp)))
9504 && DECL_ONE_ONLY (exp)
9505 && !DECL_WEAK (exp))
9506 return som_one_only_readonly_data_section;
9508 return readonly_data_section;
9510 else if (CONSTANT_CLASS_P (exp) && !reloc)
9511 return readonly_data_section;
9513 && TREE_CODE (exp) == VAR_DECL
9514 && DECL_ONE_ONLY (exp)
9515 && !DECL_WEAK (exp))
9516 return som_one_only_data_section;
9518 return data_section;
9522 pa_globalize_label (FILE *stream, const char *name)
9524 /* We only handle DATA objects here, functions are globalized in
9525 ASM_DECLARE_FUNCTION_NAME. */
9526 if (! FUNCTION_NAME_P (name))
9528 fputs ("\t.EXPORT ", stream);
9529 assemble_name (stream, name);
9530 fputs (",DATA\n", stream);
9534 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9537 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9538 int incoming ATTRIBUTE_UNUSED)
9540 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9543 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9546 pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
9548 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9549 PA64 ABI says that objects larger than 128 bits are returned in memory.
9550 Note, int_size_in_bytes can return -1 if the size of the object is
9551 variable or larger than the maximum value that can be expressed as
9552 a HOST_WIDE_INT. It can also return zero for an empty type. The
9553 simplest way to handle variable and empty types is to pass them in
9554 memory. This avoids problems in defining the boundaries of argument
9555 slots, allocating registers, etc. */
9556 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9557 || int_size_in_bytes (type) <= 0);
9560 /* Structure to hold declaration and name of external symbols that are
9561 emitted by GCC. We generate a vector of these symbols and output them
9562 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9563 This avoids putting out names that are never really used. */
9565 typedef struct extern_symbol GTY(())
9571 /* Define gc'd vector type for extern_symbol. */
9572 DEF_VEC_O(extern_symbol);
9573 DEF_VEC_ALLOC_O(extern_symbol,gc);
9575 /* Vector of extern_symbol pointers. */
9576 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9578 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9579 /* Mark DECL (name NAME) as an external reference (assembler output
9580 file FILE). This saves the names to output at the end of the file
9581 if actually referenced. */
9584 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9586 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9588 gcc_assert (file == asm_out_file);
9593 /* Output text required at the end of an assembler file.
9594 This includes deferred plabels and .import directives for
9595 all external symbols that were actually referenced. */
9598 pa_hpux_file_end (void)
9603 if (!NO_DEFERRED_PROFILE_COUNTERS)
9604 output_deferred_profile_counters ();
9606 output_deferred_plabels ();
9608 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9610 tree decl = p->decl;
9612 if (!TREE_ASM_WRITTEN (decl)
9613 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9614 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9617 VEC_free (extern_symbol, gc, extern_symbols);
9621 /* Return true if a change from mode FROM to mode TO for a register
9622 in register class CLASS is invalid. */
9625 pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9626 enum reg_class class)
9631 /* Reject changes to/from complex and vector modes. */
9632 if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from)
9633 || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to))
9636 if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to))
9639 /* There is no way to load QImode or HImode values directly from
9640 memory. SImode loads to the FP registers are not zero extended.
9641 On the 64-bit target, this conflicts with the definition of
9642 LOAD_EXTEND_OP. Thus, we can't allow changing between modes
9643 with different sizes in the floating-point registers. */
9644 if (MAYBE_FP_REG_CLASS_P (class))
9647 /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
9648 in specific sets of registers. Thus, we cannot allow changing
9649 to a larger mode when it's larger than a word. */
9650 if (GET_MODE_SIZE (to) > UNITS_PER_WORD
9651 && GET_MODE_SIZE (to) > GET_MODE_SIZE (from))
9657 /* Returns TRUE if it is a good idea to tie two pseudo registers
9658 when one has mode MODE1 and one has mode MODE2.
9659 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
9660 for any hard reg, then this must be FALSE for correct output.
9662 We should return FALSE for QImode and HImode because these modes
9663 are not ok in the floating-point registers. However, this prevents
9664 tieing these modes to SImode and DImode in the general registers.
9665 So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
9666 CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
9667 in the floating-point registers. */
9670 pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9672 /* Don't tie modes in different classes. */
9673 if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2))