1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 static int hppa_use_dfa_pipeline_interface (void);
53 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
54 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
57 hppa_use_dfa_pipeline_interface (void)
62 /* Return nonzero if there is a bypass for the output of
63 OUT_INSN and the fp store IN_INSN. */
65 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
67 enum machine_mode store_mode;
68 enum machine_mode other_mode;
71 if (recog_memoized (in_insn) < 0
72 || get_attr_type (in_insn) != TYPE_FPSTORE
73 || recog_memoized (out_insn) < 0)
76 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
78 set = single_set (out_insn);
82 other_mode = GET_MODE (SET_SRC (set));
84 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
88 #ifndef DO_FRAME_NOTES
89 #ifdef INCOMING_RETURN_ADDR_RTX
90 #define DO_FRAME_NOTES 1
92 #define DO_FRAME_NOTES 0
96 static void copy_reg_pointer (rtx, rtx);
97 static int hppa_address_cost (rtx);
98 static bool hppa_rtx_costs (rtx, int, int, int *);
99 static inline rtx force_mode (enum machine_mode, rtx);
100 static void pa_reorg (void);
101 static void pa_combine_instructions (void);
102 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
103 static int forward_branch_p (rtx);
104 static int shadd_constant_p (int);
105 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
106 static int compute_movstr_length (rtx);
107 static int compute_clrstr_length (rtx);
108 static bool pa_assemble_integer (rtx, unsigned int, int);
109 static void remove_useless_addtr_insns (int);
110 static void store_reg (int, HOST_WIDE_INT, int);
111 static void store_reg_modify (int, int, HOST_WIDE_INT);
112 static void load_reg (int, HOST_WIDE_INT, int);
113 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
114 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static void update_total_code_bytes (int);
116 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
117 static int pa_adjust_cost (rtx, rtx, rtx, int);
118 static int pa_adjust_priority (rtx, int);
119 static int pa_issue_rate (void);
120 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
122 static void pa_encode_section_info (tree, rtx, int);
123 static const char *pa_strip_name_encoding (const char *);
124 static bool pa_function_ok_for_sibcall (tree, tree);
125 static void pa_globalize_label (FILE *, const char *)
127 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
128 HOST_WIDE_INT, tree);
129 #if !defined(USE_COLLECT2)
130 static void pa_asm_out_constructor (rtx, int);
131 static void pa_asm_out_destructor (rtx, int);
133 static void pa_init_builtins (void);
134 static rtx hppa_builtin_saveregs (void);
135 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
136 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
137 static struct deferred_plabel *get_plabel (const char *)
139 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
140 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
141 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
142 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
143 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
144 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
145 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
146 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
147 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
148 static void output_deferred_plabels (void);
149 #ifdef HPUX_LONG_DOUBLE_LIBRARY
150 static void pa_hpux_init_libfuncs (void);
152 static rtx pa_struct_value_rtx (tree, int);
154 /* Save the operands last given to a compare for use when we
155 generate a scc or bcc insn. */
156 rtx hppa_compare_op0, hppa_compare_op1;
157 enum cmp_type hppa_branch_type;
159 /* Which cpu we are scheduling for. */
160 enum processor_type pa_cpu;
162 /* String to hold which cpu we are scheduling for. */
163 const char *pa_cpu_string;
165 /* Which architecture we are generating code for. */
166 enum architecture_type pa_arch;
168 /* String to hold which architecture we are generating code for. */
169 const char *pa_arch_string;
171 /* Counts for the number of callee-saved general and floating point
172 registers which were saved by the current function's prologue. */
173 static int gr_saved, fr_saved;
175 static rtx find_addr_reg (rtx);
177 /* Keep track of the number of bytes we have output in the CODE subspace
178 during this compilation so we'll know when to emit inline long-calls. */
179 unsigned long total_code_bytes;
181 /* The last address of the previous function plus the number of bytes in
182 associated thunks that have been output. This is used to determine if
183 a thunk can use an IA-relative branch to reach its target function. */
184 static int last_address;
186 /* Variables to handle plabels that we discover are necessary at assembly
187 output time. They are output after the current function. */
188 struct deferred_plabel GTY(())
193 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
195 static size_t n_deferred_plabels = 0;
198 /* Initialize the GCC target structure. */
200 #undef TARGET_ASM_ALIGNED_HI_OP
201 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
202 #undef TARGET_ASM_ALIGNED_SI_OP
203 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
204 #undef TARGET_ASM_ALIGNED_DI_OP
205 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
206 #undef TARGET_ASM_UNALIGNED_HI_OP
207 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
208 #undef TARGET_ASM_UNALIGNED_SI_OP
209 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
210 #undef TARGET_ASM_UNALIGNED_DI_OP
211 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
212 #undef TARGET_ASM_INTEGER
213 #define TARGET_ASM_INTEGER pa_assemble_integer
215 #undef TARGET_ASM_FUNCTION_PROLOGUE
216 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
217 #undef TARGET_ASM_FUNCTION_EPILOGUE
218 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
220 #undef TARGET_SCHED_ADJUST_COST
221 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
222 #undef TARGET_SCHED_ADJUST_PRIORITY
223 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
224 #undef TARGET_SCHED_ISSUE_RATE
225 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
227 #undef TARGET_ENCODE_SECTION_INFO
228 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
229 #undef TARGET_STRIP_NAME_ENCODING
230 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
232 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
233 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
235 #undef TARGET_ASM_OUTPUT_MI_THUNK
236 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
237 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
238 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
240 #undef TARGET_ASM_FILE_END
241 #define TARGET_ASM_FILE_END output_deferred_plabels
243 #if !defined(USE_COLLECT2)
244 #undef TARGET_ASM_CONSTRUCTOR
245 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
246 #undef TARGET_ASM_DESTRUCTOR
247 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
250 #undef TARGET_INIT_BUILTINS
251 #define TARGET_INIT_BUILTINS pa_init_builtins
253 #undef TARGET_RTX_COSTS
254 #define TARGET_RTX_COSTS hppa_rtx_costs
255 #undef TARGET_ADDRESS_COST
256 #define TARGET_ADDRESS_COST hppa_address_cost
258 #undef TARGET_MACHINE_DEPENDENT_REORG
259 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
261 #ifdef HPUX_LONG_DOUBLE_LIBRARY
262 #undef TARGET_INIT_LIBFUNCS
263 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
266 #undef TARGET_PROMOTE_FUNCTION_RETURN
267 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
268 #undef TARGET_PROMOTE_PROTOTYPES
269 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
271 #undef TARGET_STRUCT_VALUE_RTX
272 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
273 #undef TARGET_RETURN_IN_MEMORY
274 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
276 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
277 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
279 struct gcc_target targetm = TARGET_INITIALIZER;
282 override_options (void)
284 if (pa_cpu_string == NULL)
285 pa_cpu_string = TARGET_SCHED_DEFAULT;
287 if (! strcmp (pa_cpu_string, "8000"))
289 pa_cpu_string = "8000";
290 pa_cpu = PROCESSOR_8000;
292 else if (! strcmp (pa_cpu_string, "7100"))
294 pa_cpu_string = "7100";
295 pa_cpu = PROCESSOR_7100;
297 else if (! strcmp (pa_cpu_string, "700"))
299 pa_cpu_string = "700";
300 pa_cpu = PROCESSOR_700;
302 else if (! strcmp (pa_cpu_string, "7100LC"))
304 pa_cpu_string = "7100LC";
305 pa_cpu = PROCESSOR_7100LC;
307 else if (! strcmp (pa_cpu_string, "7200"))
309 pa_cpu_string = "7200";
310 pa_cpu = PROCESSOR_7200;
312 else if (! strcmp (pa_cpu_string, "7300"))
314 pa_cpu_string = "7300";
315 pa_cpu = PROCESSOR_7300;
319 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
322 /* Set the instruction set architecture. */
323 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
325 pa_arch_string = "1.0";
326 pa_arch = ARCHITECTURE_10;
327 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
329 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
331 pa_arch_string = "1.1";
332 pa_arch = ARCHITECTURE_11;
333 target_flags &= ~MASK_PA_20;
334 target_flags |= MASK_PA_11;
336 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
338 pa_arch_string = "2.0";
339 pa_arch = ARCHITECTURE_20;
340 target_flags |= MASK_PA_11 | MASK_PA_20;
342 else if (pa_arch_string)
344 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
347 /* Unconditional branches in the delay slot are not compatible with dwarf2
348 call frame information. There is no benefit in using this optimization
349 on PA8000 and later processors. */
350 if (pa_cpu >= PROCESSOR_8000
351 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
352 || flag_unwind_tables)
353 target_flags &= ~MASK_JUMP_IN_DELAY;
355 if (flag_pic && TARGET_PORTABLE_RUNTIME)
357 warning ("PIC code generation is not supported in the portable runtime model\n");
360 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
362 warning ("PIC code generation is not compatible with fast indirect calls\n");
365 if (! TARGET_GAS && write_symbols != NO_DEBUG)
367 warning ("-g is only supported when using GAS on this processor,");
368 warning ("-g option disabled");
369 write_symbols = NO_DEBUG;
372 /* We only support the "big PIC" model now. And we always generate PIC
373 code when in 64bit mode. */
374 if (flag_pic == 1 || TARGET_64BIT)
377 /* We can't guarantee that .dword is available for 32-bit targets. */
378 if (UNITS_PER_WORD == 4)
379 targetm.asm_out.aligned_op.di = NULL;
381 /* The unaligned ops are only available when using GAS. */
384 targetm.asm_out.unaligned_op.hi = NULL;
385 targetm.asm_out.unaligned_op.si = NULL;
386 targetm.asm_out.unaligned_op.di = NULL;
391 pa_init_builtins (void)
393 #ifdef DONT_HAVE_FPUTC_UNLOCKED
394 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
395 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
399 /* If FROM is a probable pointer register, mark TO as a probable
400 pointer register with the same pointer alignment as FROM. */
403 copy_reg_pointer (rtx to, rtx from)
405 if (REG_POINTER (from))
406 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
409 /* Return nonzero only if OP is a register of mode MODE,
412 reg_or_0_operand (rtx op, enum machine_mode mode)
414 return (op == CONST0_RTX (mode) || register_operand (op, mode));
417 /* Return nonzero if OP is suitable for use in a call to a named
420 For 2.5 try to eliminate either call_operand_address or
421 function_label_operand, they perform very similar functions. */
423 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
425 return (GET_MODE (op) == word_mode
426 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
429 /* Return 1 if X contains a symbolic expression. We know these
430 expressions will have one of a few well defined forms, so
431 we need only check those forms. */
433 symbolic_expression_p (rtx x)
436 /* Strip off any HIGH. */
437 if (GET_CODE (x) == HIGH)
440 return (symbolic_operand (x, VOIDmode));
444 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
446 switch (GET_CODE (op))
453 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
454 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
455 && GET_CODE (XEXP (op, 1)) == CONST_INT);
461 /* Return truth value of statement that OP is a symbolic memory
462 operand of mode MODE. */
465 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
467 if (GET_CODE (op) == SUBREG)
468 op = SUBREG_REG (op);
469 if (GET_CODE (op) != MEM)
472 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
473 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
476 /* Return 1 if the operand is either a register, zero, or a memory operand
477 that is not symbolic. */
480 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
482 if (register_operand (op, mode))
485 if (op == CONST0_RTX (mode))
488 if (GET_CODE (op) == SUBREG)
489 op = SUBREG_REG (op);
491 if (GET_CODE (op) != MEM)
494 /* Until problems with management of the REG_POINTER flag are resolved,
495 we need to delay creating move insns with unscaled indexed addresses
496 until CSE is not expected. */
497 if (!TARGET_NO_SPACE_REGS
499 && GET_CODE (XEXP (op, 0)) == PLUS
500 && REG_P (XEXP (XEXP (op, 0), 0))
501 && REG_P (XEXP (XEXP (op, 0), 1)))
504 return (!symbolic_memory_operand (op, mode)
505 && memory_address_p (mode, XEXP (op, 0)));
508 /* Return 1 if the operand is a register operand or a non-symbolic memory
509 operand after reload. This predicate is used for branch patterns that
510 internally handle register reloading. We need to accept non-symbolic
511 memory operands after reload to ensure that the pattern is still valid
512 if reload didn't find a hard register for the operand. */
515 reg_before_reload_operand (rtx op, enum machine_mode mode)
517 /* Don't accept a SUBREG since it will need a reload. */
518 if (GET_CODE (op) == SUBREG)
521 if (register_operand (op, mode))
525 && memory_operand (op, mode)
526 && !symbolic_memory_operand (op, mode))
532 /* Accept any constant that can be moved in one instruction into a
535 cint_ok_for_move (HOST_WIDE_INT intval)
537 /* OK if ldo, ldil, or zdepi, can be used. */
538 return (CONST_OK_FOR_LETTER_P (intval, 'J')
539 || CONST_OK_FOR_LETTER_P (intval, 'N')
540 || CONST_OK_FOR_LETTER_P (intval, 'K'));
543 /* Return 1 iff OP is an indexed memory operand. */
545 indexed_memory_operand (rtx op, enum machine_mode mode)
547 if (GET_MODE (op) != mode)
550 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
551 if (reload_completed && GET_CODE (op) == SUBREG)
552 op = SUBREG_REG (op);
554 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
559 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
562 /* Accept anything that can be used as a destination operand for a
563 move instruction. We don't accept indexed memory operands since
564 they are supported only for floating point stores. */
566 move_dest_operand (rtx op, enum machine_mode mode)
568 if (register_operand (op, mode))
571 if (GET_MODE (op) != mode)
574 if (GET_CODE (op) == SUBREG)
575 op = SUBREG_REG (op);
577 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
582 return (memory_address_p (mode, op)
583 && !IS_INDEX_ADDR_P (op)
584 && !IS_LO_SUM_DLT_ADDR_P (op));
587 /* Accept anything that can be used as a source operand for a move
590 move_src_operand (rtx op, enum machine_mode mode)
592 if (register_operand (op, mode))
595 if (GET_CODE (op) == CONSTANT_P_RTX)
598 if (GET_CODE (op) == CONST_INT)
599 return cint_ok_for_move (INTVAL (op));
601 if (GET_MODE (op) != mode)
604 if (GET_CODE (op) == SUBREG)
605 op = SUBREG_REG (op);
607 if (GET_CODE (op) != MEM)
610 /* Until problems with management of the REG_POINTER flag are resolved,
611 we need to delay creating move insns with unscaled indexed addresses
612 until CSE is not expected. */
613 if (!TARGET_NO_SPACE_REGS
615 && GET_CODE (XEXP (op, 0)) == PLUS
616 && REG_P (XEXP (XEXP (op, 0), 0))
617 && REG_P (XEXP (XEXP (op, 0), 1)))
620 return memory_address_p (mode, XEXP (op, 0));
623 /* Accept REG and any CONST_INT that can be moved in one instruction into a
626 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
628 if (register_operand (op, mode))
631 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
635 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
640 switch (GET_CODE (op))
646 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
647 && GET_CODE (XEXP (op, 1)) == CONST_INT);
654 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
656 return reg_renumber && FP_REG_P (op);
661 /* Return truth value of whether OP can be used as an operand in a
662 three operand arithmetic insn that accepts registers of mode MODE
663 or 14-bit signed integers. */
665 arith_operand (rtx op, enum machine_mode mode)
667 return (register_operand (op, mode)
668 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
671 /* Return truth value of whether OP can be used as an operand in a
672 three operand arithmetic insn that accepts registers of mode MODE
673 or 11-bit signed integers. */
675 arith11_operand (rtx op, enum machine_mode mode)
677 return (register_operand (op, mode)
678 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
681 /* Return truth value of whether OP can be used as an operand in a
684 adddi3_operand (rtx op, enum machine_mode mode)
686 return (register_operand (op, mode)
687 || (GET_CODE (op) == CONST_INT
688 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
691 /* A constant integer suitable for use in a PRE_MODIFY memory
694 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
696 return (GET_CODE (op) == CONST_INT
697 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
700 /* A constant integer suitable for use in a POST_MODIFY memory
703 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
705 return (GET_CODE (op) == CONST_INT
706 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
710 arith_double_operand (rtx op, enum machine_mode mode)
712 return (register_operand (op, mode)
713 || (GET_CODE (op) == CONST_DOUBLE
714 && GET_MODE (op) == mode
715 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
716 && ((CONST_DOUBLE_HIGH (op) >= 0)
717 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
720 /* Return truth value of whether OP is an integer which fits the
721 range constraining immediate operands in three-address insns, or
722 is an integer register. */
725 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
727 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
728 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
731 /* Return nonzero if OP is an integer register, else return zero. */
733 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
735 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
738 /* Return truth value of whether OP is an integer which fits the
739 range constraining immediate operands in three-address insns. */
742 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
744 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
748 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
750 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
754 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
756 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
760 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
762 #if HOST_BITS_PER_WIDE_INT > 32
763 /* All allowed constants will fit a CONST_INT. */
764 return (GET_CODE (op) == CONST_INT
765 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
767 return (GET_CODE (op) == CONST_INT
768 || (GET_CODE (op) == CONST_DOUBLE
769 && CONST_DOUBLE_HIGH (op) == 0));
774 arith5_operand (rtx op, enum machine_mode mode)
776 return register_operand (op, mode) || int5_operand (op, mode);
779 /* True iff zdepi can be used to generate this CONST_INT.
780 zdepi first sign extends a 5 bit signed number to a given field
781 length, then places this field anywhere in a zero. */
783 zdepi_cint_p (unsigned HOST_WIDE_INT x)
785 unsigned HOST_WIDE_INT lsb_mask, t;
787 /* This might not be obvious, but it's at least fast.
788 This function is critical; we don't have the time loops would take. */
790 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
791 /* Return true iff t is a power of two. */
792 return ((t & (t - 1)) == 0);
795 /* True iff depi or extru can be used to compute (reg & mask).
796 Accept bit pattern like these:
801 and_mask_p (unsigned HOST_WIDE_INT mask)
804 mask += mask & -mask;
805 return (mask & (mask - 1)) == 0;
808 /* True iff depi or extru can be used to compute (reg & OP). */
810 and_operand (rtx op, enum machine_mode mode)
812 return (register_operand (op, mode)
813 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
816 /* True iff depi can be used to compute (reg | MASK). */
818 ior_mask_p (unsigned HOST_WIDE_INT mask)
820 mask += mask & -mask;
821 return (mask & (mask - 1)) == 0;
824 /* True iff depi can be used to compute (reg | OP). */
826 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
828 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
832 lhs_lshift_operand (rtx op, enum machine_mode mode)
834 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
837 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
838 Such values can be the left hand side x in (x << r), using the zvdepi
841 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
843 unsigned HOST_WIDE_INT x;
844 if (GET_CODE (op) != CONST_INT)
846 x = INTVAL (op) >> 4;
847 return (x & (x + 1)) == 0;
851 arith32_operand (rtx op, enum machine_mode mode)
853 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
857 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
859 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
862 /* Legitimize PIC addresses. If the address is already
863 position-independent, we return ORIG. Newly generated
864 position-independent addresses go to REG. If we need more
865 than one register, we lose. */
868 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
872 /* Labels need special handling. */
873 if (pic_label_operand (orig, mode))
875 /* We do not want to go through the movXX expanders here since that
876 would create recursion.
878 Nor do we really want to call a generator for a named pattern
879 since that requires multiple patterns if we want to support
882 So instead we just emit the raw set, which avoids the movXX
883 expanders completely. */
884 mark_reg_pointer (reg, BITS_PER_UNIT);
885 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
886 current_function_uses_pic_offset_table = 1;
889 if (GET_CODE (orig) == SYMBOL_REF)
896 /* Before reload, allocate a temporary register for the intermediate
897 result. This allows the sequence to be deleted when the final
898 result is unused and the insns are trivially dead. */
899 tmp_reg = ((reload_in_progress || reload_completed)
900 ? reg : gen_reg_rtx (Pmode));
902 emit_move_insn (tmp_reg,
903 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
904 gen_rtx_HIGH (word_mode, orig)));
906 = gen_rtx_MEM (Pmode,
907 gen_rtx_LO_SUM (Pmode, tmp_reg,
908 gen_rtx_UNSPEC (Pmode,
912 current_function_uses_pic_offset_table = 1;
913 MEM_NOTRAP_P (pic_ref) = 1;
914 RTX_UNCHANGING_P (pic_ref) = 1;
915 mark_reg_pointer (reg, BITS_PER_UNIT);
916 insn = emit_move_insn (reg, pic_ref);
918 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
919 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
923 else if (GET_CODE (orig) == CONST)
927 if (GET_CODE (XEXP (orig, 0)) == PLUS
928 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
934 if (GET_CODE (XEXP (orig, 0)) == PLUS)
936 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
937 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
938 base == reg ? 0 : reg);
943 if (GET_CODE (orig) == CONST_INT)
945 if (INT_14_BITS (orig))
946 return plus_constant (base, INTVAL (orig));
947 orig = force_reg (Pmode, orig);
949 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
950 /* Likewise, should we set special REG_NOTEs here? */
956 /* Try machine-dependent ways of modifying an illegitimate address
957 to be legitimate. If we find one, return the new, valid address.
958 This macro is used in only one place: `memory_address' in explow.c.
960 OLDX is the address as it was before break_out_memory_refs was called.
961 In some cases it is useful to look at this to decide what needs to be done.
963 MODE and WIN are passed so that this macro can use
964 GO_IF_LEGITIMATE_ADDRESS.
966 It is always safe for this macro to do nothing. It exists to recognize
967 opportunities to optimize the output.
969 For the PA, transform:
971 memory(X + <large int>)
975 if (<large int> & mask) >= 16
976 Y = (<large int> & ~mask) + mask + 1 Round up.
978 Y = (<large int> & ~mask) Round down.
980 memory (Z + (<large int> - Y));
982 This is for CSE to find several similar references, and only use one Z.
984 X can either be a SYMBOL_REF or REG, but because combine can not
985 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
986 D will not fit in 14 bits.
988 MODE_FLOAT references allow displacements which fit in 5 bits, so use
991 MODE_INT references allow displacements which fit in 14 bits, so use
994 This relies on the fact that most mode MODE_FLOAT references will use FP
995 registers and most mode MODE_INT references will use integer registers.
996 (In the rare case of an FP register used in an integer MODE, we depend
997 on secondary reloads to clean things up.)
1000 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1001 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1002 addressing modes to be used).
1004 Put X and Z into registers. Then put the entire expression into
1008 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1009 enum machine_mode mode)
1013 /* We need to canonicalize the order of operands in unscaled indexed
1014 addresses since the code that checks if an address is valid doesn't
1015 always try both orders. */
1016 if (!TARGET_NO_SPACE_REGS
1017 && GET_CODE (x) == PLUS
1018 && GET_MODE (x) == Pmode
1019 && REG_P (XEXP (x, 0))
1020 && REG_P (XEXP (x, 1))
1021 && REG_POINTER (XEXP (x, 0))
1022 && !REG_POINTER (XEXP (x, 1)))
1023 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1026 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1028 /* Strip off CONST. */
1029 if (GET_CODE (x) == CONST)
1032 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1033 That should always be safe. */
1034 if (GET_CODE (x) == PLUS
1035 && GET_CODE (XEXP (x, 0)) == REG
1036 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1038 rtx reg = force_reg (Pmode, XEXP (x, 1));
1039 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1042 /* Note we must reject symbols which represent function addresses
1043 since the assembler/linker can't handle arithmetic on plabels. */
1044 if (GET_CODE (x) == PLUS
1045 && GET_CODE (XEXP (x, 1)) == CONST_INT
1046 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1047 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1048 || GET_CODE (XEXP (x, 0)) == REG))
1050 rtx int_part, ptr_reg;
1052 int offset = INTVAL (XEXP (x, 1));
1055 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1056 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1058 /* Choose which way to round the offset. Round up if we
1059 are >= halfway to the next boundary. */
1060 if ((offset & mask) >= ((mask + 1) / 2))
1061 newoffset = (offset & ~ mask) + mask + 1;
1063 newoffset = (offset & ~ mask);
1065 /* If the newoffset will not fit in 14 bits (ldo), then
1066 handling this would take 4 or 5 instructions (2 to load
1067 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1068 add the new offset and the SYMBOL_REF.) Combine can
1069 not handle 4->2 or 5->2 combinations, so do not create
1071 if (! VAL_14_BITS_P (newoffset)
1072 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1074 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1077 gen_rtx_HIGH (Pmode, const_part));
1080 gen_rtx_LO_SUM (Pmode,
1081 tmp_reg, const_part));
1085 if (! VAL_14_BITS_P (newoffset))
1086 int_part = force_reg (Pmode, GEN_INT (newoffset));
1088 int_part = GEN_INT (newoffset);
1090 ptr_reg = force_reg (Pmode,
1091 gen_rtx_PLUS (Pmode,
1092 force_reg (Pmode, XEXP (x, 0)),
1095 return plus_constant (ptr_reg, offset - newoffset);
1098 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1100 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1101 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1102 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1103 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1104 || GET_CODE (XEXP (x, 1)) == SUBREG)
1105 && GET_CODE (XEXP (x, 1)) != CONST)
1107 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1111 if (GET_CODE (reg1) != REG)
1112 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1114 reg2 = XEXP (XEXP (x, 0), 0);
1115 if (GET_CODE (reg2) != REG)
1116 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1118 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1119 gen_rtx_MULT (Pmode,
1125 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1127 Only do so for floating point modes since this is more speculative
1128 and we lose if it's an integer store. */
1129 if (GET_CODE (x) == PLUS
1130 && GET_CODE (XEXP (x, 0)) == PLUS
1131 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1132 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1133 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1134 && (mode == SFmode || mode == DFmode))
1137 /* First, try and figure out what to use as a base register. */
1138 rtx reg1, reg2, base, idx, orig_base;
1140 reg1 = XEXP (XEXP (x, 0), 1);
1145 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1146 then emit_move_sequence will turn on REG_POINTER so we'll know
1147 it's a base register below. */
1148 if (GET_CODE (reg1) != REG)
1149 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1151 if (GET_CODE (reg2) != REG)
1152 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1154 /* Figure out what the base and index are. */
1156 if (GET_CODE (reg1) == REG
1157 && REG_POINTER (reg1))
1160 orig_base = XEXP (XEXP (x, 0), 1);
1161 idx = gen_rtx_PLUS (Pmode,
1162 gen_rtx_MULT (Pmode,
1163 XEXP (XEXP (XEXP (x, 0), 0), 0),
1164 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1167 else if (GET_CODE (reg2) == REG
1168 && REG_POINTER (reg2))
1171 orig_base = XEXP (x, 1);
1178 /* If the index adds a large constant, try to scale the
1179 constant so that it can be loaded with only one insn. */
1180 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1181 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1182 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1183 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1185 /* Divide the CONST_INT by the scale factor, then add it to A. */
1186 int val = INTVAL (XEXP (idx, 1));
1188 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1189 reg1 = XEXP (XEXP (idx, 0), 0);
1190 if (GET_CODE (reg1) != REG)
1191 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1193 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1195 /* We can now generate a simple scaled indexed address. */
1198 (Pmode, gen_rtx_PLUS (Pmode,
1199 gen_rtx_MULT (Pmode, reg1,
1200 XEXP (XEXP (idx, 0), 1)),
1204 /* If B + C is still a valid base register, then add them. */
1205 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1206 && INTVAL (XEXP (idx, 1)) <= 4096
1207 && INTVAL (XEXP (idx, 1)) >= -4096)
1209 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1212 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1214 reg2 = XEXP (XEXP (idx, 0), 0);
1215 if (GET_CODE (reg2) != CONST_INT)
1216 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1218 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1219 gen_rtx_MULT (Pmode,
1225 /* Get the index into a register, then add the base + index and
1226 return a register holding the result. */
1228 /* First get A into a register. */
1229 reg1 = XEXP (XEXP (idx, 0), 0);
1230 if (GET_CODE (reg1) != REG)
1231 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1233 /* And get B into a register. */
1234 reg2 = XEXP (idx, 1);
1235 if (GET_CODE (reg2) != REG)
1236 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1238 reg1 = force_reg (Pmode,
1239 gen_rtx_PLUS (Pmode,
1240 gen_rtx_MULT (Pmode, reg1,
1241 XEXP (XEXP (idx, 0), 1)),
1244 /* Add the result to our base register and return. */
1245 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1249 /* Uh-oh. We might have an address for x[n-100000]. This needs
1250 special handling to avoid creating an indexed memory address
1251 with x-100000 as the base.
1253 If the constant part is small enough, then it's still safe because
1254 there is a guard page at the beginning and end of the data segment.
1256 Scaled references are common enough that we want to try and rearrange the
1257 terms so that we can use indexing for these addresses too. Only
1258 do the optimization for floatint point modes. */
1260 if (GET_CODE (x) == PLUS
1261 && symbolic_expression_p (XEXP (x, 1)))
1263 /* Ugly. We modify things here so that the address offset specified
1264 by the index expression is computed first, then added to x to form
1265 the entire address. */
1267 rtx regx1, regx2, regy1, regy2, y;
1269 /* Strip off any CONST. */
1271 if (GET_CODE (y) == CONST)
1274 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1276 /* See if this looks like
1277 (plus (mult (reg) (shadd_const))
1278 (const (plus (symbol_ref) (const_int))))
1280 Where const_int is small. In that case the const
1281 expression is a valid pointer for indexing.
1283 If const_int is big, but can be divided evenly by shadd_const
1284 and added to (reg). This allows more scaled indexed addresses. */
1285 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1286 && GET_CODE (XEXP (x, 0)) == MULT
1287 && GET_CODE (XEXP (y, 1)) == CONST_INT
1288 && INTVAL (XEXP (y, 1)) >= -4096
1289 && INTVAL (XEXP (y, 1)) <= 4095
1290 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1291 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1293 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1297 if (GET_CODE (reg1) != REG)
1298 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1300 reg2 = XEXP (XEXP (x, 0), 0);
1301 if (GET_CODE (reg2) != REG)
1302 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1304 return force_reg (Pmode,
1305 gen_rtx_PLUS (Pmode,
1306 gen_rtx_MULT (Pmode,
1311 else if ((mode == DFmode || mode == SFmode)
1312 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1313 && GET_CODE (XEXP (x, 0)) == MULT
1314 && GET_CODE (XEXP (y, 1)) == CONST_INT
1315 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1316 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1317 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1320 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1321 / INTVAL (XEXP (XEXP (x, 0), 1))));
1322 regx2 = XEXP (XEXP (x, 0), 0);
1323 if (GET_CODE (regx2) != REG)
1324 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1325 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1329 gen_rtx_PLUS (Pmode,
1330 gen_rtx_MULT (Pmode, regx2,
1331 XEXP (XEXP (x, 0), 1)),
1332 force_reg (Pmode, XEXP (y, 0))));
1334 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1335 && INTVAL (XEXP (y, 1)) >= -4096
1336 && INTVAL (XEXP (y, 1)) <= 4095)
1338 /* This is safe because of the guard page at the
1339 beginning and end of the data space. Just
1340 return the original address. */
1345 /* Doesn't look like one we can optimize. */
1346 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1347 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1348 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1349 regx1 = force_reg (Pmode,
1350 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1352 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1360 /* For the HPPA, REG and REG+CONST is cost 0
1361 and addresses involving symbolic constants are cost 2.
1363 PIC addresses are very expensive.
1365 It is no coincidence that this has the same structure
1366 as GO_IF_LEGITIMATE_ADDRESS. */
1369 hppa_address_cost (rtx X)
1371 switch (GET_CODE (X))
1384 /* Compute a (partial) cost for rtx X. Return true if the complete
1385 cost has been computed, and false if subexpressions should be
1386 scanned. In either case, *TOTAL contains the cost result. */
1389 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1394 if (INTVAL (x) == 0)
1396 else if (INT_14_BITS (x))
1413 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1414 && outer_code != SET)
1421 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1422 *total = COSTS_N_INSNS (3);
1423 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1424 *total = COSTS_N_INSNS (8);
1426 *total = COSTS_N_INSNS (20);
1430 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1432 *total = COSTS_N_INSNS (14);
1440 *total = COSTS_N_INSNS (60);
1443 case PLUS: /* this includes shNadd insns */
1445 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1446 *total = COSTS_N_INSNS (3);
1448 *total = COSTS_N_INSNS (1);
1454 *total = COSTS_N_INSNS (1);
1462 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1463 new rtx with the correct mode. */
1465 force_mode (enum machine_mode mode, rtx orig)
1467 if (mode == GET_MODE (orig))
1470 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1473 return gen_rtx_REG (mode, REGNO (orig));
1476 /* Emit insns to move operands[1] into operands[0].
1478 Return 1 if we have written out everything that needs to be done to
1479 do the move. Otherwise, return 0 and the caller will emit the move
1482 Note SCRATCH_REG may not be in the proper mode depending on how it
1483 will be used. This routine is responsible for creating a new copy
1484 of SCRATCH_REG in the proper mode. */
1487 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1489 register rtx operand0 = operands[0];
1490 register rtx operand1 = operands[1];
1493 /* We can only handle indexed addresses in the destination operand
1494 of floating point stores. Thus, we need to break out indexed
1495 addresses from the destination operand. */
1496 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1498 /* This is only safe up to the beginning of life analysis. */
1502 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1503 operand0 = replace_equiv_address (operand0, tem);
1506 /* On targets with non-equivalent space registers, break out unscaled
1507 indexed addresses from the source operand before the final CSE.
1508 We have to do this because the REG_POINTER flag is not correctly
1509 carried through various optimization passes and CSE may substitute
1510 a pseudo without the pointer set for one with the pointer set. As
1511 a result, we loose various opportunites to create insns with
1512 unscaled indexed addresses. */
1513 if (!TARGET_NO_SPACE_REGS
1514 && !cse_not_expected
1515 && GET_CODE (operand1) == MEM
1516 && GET_CODE (XEXP (operand1, 0)) == PLUS
1517 && REG_P (XEXP (XEXP (operand1, 0), 0))
1518 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1520 = replace_equiv_address (operand1,
1521 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1524 && reload_in_progress && GET_CODE (operand0) == REG
1525 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1526 operand0 = reg_equiv_mem[REGNO (operand0)];
1527 else if (scratch_reg
1528 && reload_in_progress && GET_CODE (operand0) == SUBREG
1529 && GET_CODE (SUBREG_REG (operand0)) == REG
1530 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1532 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1533 the code which tracks sets/uses for delete_output_reload. */
1534 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1535 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1536 SUBREG_BYTE (operand0));
1537 operand0 = alter_subreg (&temp);
1541 && reload_in_progress && GET_CODE (operand1) == REG
1542 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1543 operand1 = reg_equiv_mem[REGNO (operand1)];
1544 else if (scratch_reg
1545 && reload_in_progress && GET_CODE (operand1) == SUBREG
1546 && GET_CODE (SUBREG_REG (operand1)) == REG
1547 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1549 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1550 the code which tracks sets/uses for delete_output_reload. */
1551 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1552 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1553 SUBREG_BYTE (operand1));
1554 operand1 = alter_subreg (&temp);
1557 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1558 && ((tem = find_replacement (&XEXP (operand0, 0)))
1559 != XEXP (operand0, 0)))
1560 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1562 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1563 && ((tem = find_replacement (&XEXP (operand1, 0)))
1564 != XEXP (operand1, 0)))
1565 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1567 /* Handle secondary reloads for loads/stores of FP registers from
1568 REG+D addresses where D does not fit in 5 bits, including
1569 (subreg (mem (addr))) cases. */
1571 && fp_reg_operand (operand0, mode)
1572 && ((GET_CODE (operand1) == MEM
1573 && !memory_address_p (DFmode, XEXP (operand1, 0)))
1574 || ((GET_CODE (operand1) == SUBREG
1575 && GET_CODE (XEXP (operand1, 0)) == MEM
1576 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))))
1578 if (GET_CODE (operand1) == SUBREG)
1579 operand1 = XEXP (operand1, 0);
1581 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1582 it in WORD_MODE regardless of what mode it was originally given
1584 scratch_reg = force_mode (word_mode, scratch_reg);
1586 /* D might not fit in 14 bits either; for such cases load D into
1588 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1590 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1591 emit_move_insn (scratch_reg,
1592 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1594 XEXP (XEXP (operand1, 0), 0),
1598 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1599 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1600 gen_rtx_MEM (mode, scratch_reg)));
1603 else if (scratch_reg
1604 && fp_reg_operand (operand1, mode)
1605 && ((GET_CODE (operand0) == MEM
1606 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1607 || ((GET_CODE (operand0) == SUBREG)
1608 && GET_CODE (XEXP (operand0, 0)) == MEM
1609 && !memory_address_p (DFmode,
1610 XEXP (XEXP (operand0, 0), 0)))))
1612 if (GET_CODE (operand0) == SUBREG)
1613 operand0 = XEXP (operand0, 0);
1615 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1616 it in WORD_MODE regardless of what mode it was originally given
1618 scratch_reg = force_mode (word_mode, scratch_reg);
1620 /* D might not fit in 14 bits either; for such cases load D into
1622 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1624 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1625 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1628 XEXP (XEXP (operand0, 0),
1633 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1634 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1638 /* Handle secondary reloads for loads of FP registers from constant
1639 expressions by forcing the constant into memory.
1641 Use scratch_reg to hold the address of the memory location.
1643 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1644 NO_REGS when presented with a const_int and a register class
1645 containing only FP registers. Doing so unfortunately creates
1646 more problems than it solves. Fix this for 2.5. */
1647 else if (scratch_reg
1648 && CONSTANT_P (operand1)
1649 && fp_reg_operand (operand0, mode))
1653 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1654 it in WORD_MODE regardless of what mode it was originally given
1656 scratch_reg = force_mode (word_mode, scratch_reg);
1658 /* Force the constant into memory and put the address of the
1659 memory location into scratch_reg. */
1660 xoperands[0] = scratch_reg;
1661 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1662 emit_move_sequence (xoperands, Pmode, 0);
1664 /* Now load the destination register. */
1665 emit_insn (gen_rtx_SET (mode, operand0,
1666 gen_rtx_MEM (mode, scratch_reg)));
1669 /* Handle secondary reloads for SAR. These occur when trying to load
1670 the SAR from memory, FP register, or with a constant. */
1671 else if (scratch_reg
1672 && GET_CODE (operand0) == REG
1673 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1674 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1675 && (GET_CODE (operand1) == MEM
1676 || GET_CODE (operand1) == CONST_INT
1677 || (GET_CODE (operand1) == REG
1678 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1680 /* D might not fit in 14 bits either; for such cases load D into
1682 if (GET_CODE (operand1) == MEM
1683 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1685 /* We are reloading the address into the scratch register, so we
1686 want to make sure the scratch register is a full register. */
1687 scratch_reg = force_mode (word_mode, scratch_reg);
1689 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1690 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1693 XEXP (XEXP (operand1, 0),
1697 /* Now we are going to load the scratch register from memory,
1698 we want to load it in the same width as the original MEM,
1699 which must be the same as the width of the ultimate destination,
1701 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1703 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1708 /* We want to load the scratch register using the same mode as
1709 the ultimate destination. */
1710 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1712 emit_move_insn (scratch_reg, operand1);
1715 /* And emit the insn to set the ultimate destination. We know that
1716 the scratch register has the same mode as the destination at this
1718 emit_move_insn (operand0, scratch_reg);
1721 /* Handle the most common case: storing into a register. */
1722 else if (register_operand (operand0, mode))
1724 if (register_operand (operand1, mode)
1725 || (GET_CODE (operand1) == CONST_INT
1726 && cint_ok_for_move (INTVAL (operand1)))
1727 || (operand1 == CONST0_RTX (mode))
1728 || (GET_CODE (operand1) == HIGH
1729 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1730 /* Only `general_operands' can come here, so MEM is ok. */
1731 || GET_CODE (operand1) == MEM)
1733 /* Various sets are created during RTL generation which don't
1734 have the REG_POINTER flag correctly set. After the CSE pass,
1735 instruction recognition can fail if we don't consistently
1736 set this flag when performing register copies. This should
1737 also improve the opportunities for creating insns that use
1738 unscaled indexing. */
1739 if (REG_P (operand0) && REG_P (operand1))
1741 if (REG_POINTER (operand1)
1742 && !REG_POINTER (operand0)
1743 && !HARD_REGISTER_P (operand0))
1744 copy_reg_pointer (operand0, operand1);
1745 else if (REG_POINTER (operand0)
1746 && !REG_POINTER (operand1)
1747 && !HARD_REGISTER_P (operand1))
1748 copy_reg_pointer (operand1, operand0);
1751 /* When MEMs are broken out, the REG_POINTER flag doesn't
1752 get set. In some cases, we can set the REG_POINTER flag
1753 from the declaration for the MEM. */
1754 if (REG_P (operand0)
1755 && GET_CODE (operand1) == MEM
1756 && !REG_POINTER (operand0))
1758 tree decl = MEM_EXPR (operand1);
1760 /* Set the register pointer flag and register alignment
1761 if the declaration for this memory reference is a
1762 pointer type. Fortran indirect argument references
1765 && !(flag_argument_noalias > 1
1766 && TREE_CODE (decl) == INDIRECT_REF
1767 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1771 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1773 if (TREE_CODE (decl) == COMPONENT_REF)
1774 decl = TREE_OPERAND (decl, 1);
1776 type = TREE_TYPE (decl);
1777 if (TREE_CODE (type) == ARRAY_TYPE)
1778 type = get_inner_array_type (type);
1780 if (POINTER_TYPE_P (type))
1784 type = TREE_TYPE (type);
1785 /* Using TYPE_ALIGN_OK is rather conservative as
1786 only the ada frontend actually sets it. */
1787 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1789 mark_reg_pointer (operand0, align);
1794 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1798 else if (GET_CODE (operand0) == MEM)
1800 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1801 && !(reload_in_progress || reload_completed))
1803 rtx temp = gen_reg_rtx (DFmode);
1805 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1806 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1809 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1811 /* Run this case quickly. */
1812 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1815 if (! (reload_in_progress || reload_completed))
1817 operands[0] = validize_mem (operand0);
1818 operands[1] = operand1 = force_reg (mode, operand1);
1822 /* Simplify the source if we need to.
1823 Note we do have to handle function labels here, even though we do
1824 not consider them legitimate constants. Loop optimizations can
1825 call the emit_move_xxx with one as a source. */
1826 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1827 || function_label_operand (operand1, mode)
1828 || (GET_CODE (operand1) == HIGH
1829 && symbolic_operand (XEXP (operand1, 0), mode)))
1833 if (GET_CODE (operand1) == HIGH)
1836 operand1 = XEXP (operand1, 0);
1838 if (symbolic_operand (operand1, mode))
1840 /* Argh. The assembler and linker can't handle arithmetic
1843 So we force the plabel into memory, load operand0 from
1844 the memory location, then add in the constant part. */
1845 if ((GET_CODE (operand1) == CONST
1846 && GET_CODE (XEXP (operand1, 0)) == PLUS
1847 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1848 || function_label_operand (operand1, mode))
1850 rtx temp, const_part;
1852 /* Figure out what (if any) scratch register to use. */
1853 if (reload_in_progress || reload_completed)
1855 scratch_reg = scratch_reg ? scratch_reg : operand0;
1856 /* SCRATCH_REG will hold an address and maybe the actual
1857 data. We want it in WORD_MODE regardless of what mode it
1858 was originally given to us. */
1859 scratch_reg = force_mode (word_mode, scratch_reg);
1862 scratch_reg = gen_reg_rtx (Pmode);
1864 if (GET_CODE (operand1) == CONST)
1866 /* Save away the constant part of the expression. */
1867 const_part = XEXP (XEXP (operand1, 0), 1);
1868 if (GET_CODE (const_part) != CONST_INT)
1871 /* Force the function label into memory. */
1872 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1876 /* No constant part. */
1877 const_part = NULL_RTX;
1879 /* Force the function label into memory. */
1880 temp = force_const_mem (mode, operand1);
1884 /* Get the address of the memory location. PIC-ify it if
1886 temp = XEXP (temp, 0);
1888 temp = legitimize_pic_address (temp, mode, scratch_reg);
1890 /* Put the address of the memory location into our destination
1893 emit_move_sequence (operands, mode, scratch_reg);
1895 /* Now load from the memory location into our destination
1897 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1898 emit_move_sequence (operands, mode, scratch_reg);
1900 /* And add back in the constant part. */
1901 if (const_part != NULL_RTX)
1902 expand_inc (operand0, const_part);
1911 if (reload_in_progress || reload_completed)
1913 temp = scratch_reg ? scratch_reg : operand0;
1914 /* TEMP will hold an address and maybe the actual
1915 data. We want it in WORD_MODE regardless of what mode it
1916 was originally given to us. */
1917 temp = force_mode (word_mode, temp);
1920 temp = gen_reg_rtx (Pmode);
1922 /* (const (plus (symbol) (const_int))) must be forced to
1923 memory during/after reload if the const_int will not fit
1925 if (GET_CODE (operand1) == CONST
1926 && GET_CODE (XEXP (operand1, 0)) == PLUS
1927 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1928 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1929 && (reload_completed || reload_in_progress)
1932 operands[1] = force_const_mem (mode, operand1);
1933 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1935 emit_move_sequence (operands, mode, temp);
1939 operands[1] = legitimize_pic_address (operand1, mode, temp);
1940 if (REG_P (operand0) && REG_P (operands[1]))
1941 copy_reg_pointer (operand0, operands[1]);
1942 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1945 /* On the HPPA, references to data space are supposed to use dp,
1946 register 27, but showing it in the RTL inhibits various cse
1947 and loop optimizations. */
1952 if (reload_in_progress || reload_completed)
1954 temp = scratch_reg ? scratch_reg : operand0;
1955 /* TEMP will hold an address and maybe the actual
1956 data. We want it in WORD_MODE regardless of what mode it
1957 was originally given to us. */
1958 temp = force_mode (word_mode, temp);
1961 temp = gen_reg_rtx (mode);
1963 /* Loading a SYMBOL_REF into a register makes that register
1964 safe to be used as the base in an indexed address.
1966 Don't mark hard registers though. That loses. */
1967 if (GET_CODE (operand0) == REG
1968 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1969 mark_reg_pointer (operand0, BITS_PER_UNIT);
1970 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1971 mark_reg_pointer (temp, BITS_PER_UNIT);
1974 set = gen_rtx_SET (mode, operand0, temp);
1976 set = gen_rtx_SET (VOIDmode,
1978 gen_rtx_LO_SUM (mode, temp, operand1));
1980 emit_insn (gen_rtx_SET (VOIDmode,
1982 gen_rtx_HIGH (mode, operand1)));
1988 else if (GET_CODE (operand1) != CONST_INT
1989 || !cint_ok_for_move (INTVAL (operand1)))
1993 HOST_WIDE_INT value = INTVAL (operand1);
1994 HOST_WIDE_INT insv = 0;
1998 && GET_CODE (operand1) == CONST_INT
1999 && HOST_BITS_PER_WIDE_INT > 32
2000 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2004 /* Extract the low order 32 bits of the value and sign extend.
2005 If the new value is the same as the original value, we can
2006 can use the original value as-is. If the new value is
2007 different, we use it and insert the most-significant 32-bits
2008 of the original value into the final result. */
2009 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2010 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2013 #if HOST_BITS_PER_WIDE_INT > 32
2014 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2018 operand1 = GEN_INT (nval);
2022 if (reload_in_progress || reload_completed)
2023 temp = scratch_reg ? scratch_reg : operand0;
2025 temp = gen_reg_rtx (mode);
2027 /* We don't directly split DImode constants on 32-bit targets
2028 because PLUS uses an 11-bit immediate and the insn sequence
2029 generated is not as efficient as the one using HIGH/LO_SUM. */
2030 if (GET_CODE (operand1) == CONST_INT
2031 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2034 /* Directly break constant into high and low parts. This
2035 provides better optimization opportunities because various
2036 passes recognize constants split with PLUS but not LO_SUM.
2037 We use a 14-bit signed low part except when the addition
2038 of 0x4000 to the high part might change the sign of the
2040 HOST_WIDE_INT low = value & 0x3fff;
2041 HOST_WIDE_INT high = value & ~ 0x3fff;
2045 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2053 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2054 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2058 emit_insn (gen_rtx_SET (VOIDmode, temp,
2059 gen_rtx_HIGH (mode, operand1)));
2060 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2063 insn = emit_move_insn (operands[0], operands[1]);
2065 /* Now insert the most significant 32 bits of the value
2066 into the register. When we don't have a second register
2067 available, it could take up to nine instructions to load
2068 a 64-bit integer constant. Prior to reload, we force
2069 constants that would take more than three instructions
2070 to load to the constant pool. During and after reload,
2071 we have to handle all possible values. */
2074 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2075 register and the value to be inserted is outside the
2076 range that can be loaded with three depdi instructions. */
2077 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2079 operand1 = GEN_INT (insv);
2081 emit_insn (gen_rtx_SET (VOIDmode, temp,
2082 gen_rtx_HIGH (mode, operand1)));
2083 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2084 emit_insn (gen_insv (operand0, GEN_INT (32),
2089 int len = 5, pos = 27;
2091 /* Insert the bits using the depdi instruction. */
2094 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2095 HOST_WIDE_INT sign = v5 < 0;
2097 /* Left extend the insertion. */
2098 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2099 while (pos > 0 && (insv & 1) == sign)
2101 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2106 emit_insn (gen_insv (operand0, GEN_INT (len),
2107 GEN_INT (pos), GEN_INT (v5)));
2109 len = pos > 0 && pos < 5 ? pos : 5;
2116 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2121 /* Now have insn-emit do whatever it normally does. */
2125 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2126 it will need a link/runtime reloc). */
2129 reloc_needed (tree exp)
2133 switch (TREE_CODE (exp))
2140 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2141 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2146 case NON_LVALUE_EXPR:
2147 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2153 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2154 if (TREE_VALUE (link) != 0)
2155 reloc |= reloc_needed (TREE_VALUE (link));
2168 /* Does operand (which is a symbolic_operand) live in text space?
2169 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2173 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2175 if (GET_CODE (operand) == CONST)
2176 operand = XEXP (XEXP (operand, 0), 0);
2179 if (GET_CODE (operand) == SYMBOL_REF)
2180 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2184 if (GET_CODE (operand) == SYMBOL_REF)
2185 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2191 /* Return the best assembler insn template
2192 for moving operands[1] into operands[0] as a fullword. */
2194 singlemove_string (rtx *operands)
2196 HOST_WIDE_INT intval;
2198 if (GET_CODE (operands[0]) == MEM)
2199 return "stw %r1,%0";
2200 if (GET_CODE (operands[1]) == MEM)
2202 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2207 if (GET_MODE (operands[1]) != SFmode)
2210 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2212 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2213 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2215 operands[1] = GEN_INT (i);
2216 /* Fall through to CONST_INT case. */
2218 if (GET_CODE (operands[1]) == CONST_INT)
2220 intval = INTVAL (operands[1]);
2222 if (VAL_14_BITS_P (intval))
2224 else if ((intval & 0x7ff) == 0)
2225 return "ldil L'%1,%0";
2226 else if (zdepi_cint_p (intval))
2227 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2229 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2231 return "copy %1,%0";
2235 /* Compute position (in OP[1]) and width (in OP[2])
2236 useful for copying IMM to a register using the zdepi
2237 instructions. Store the immediate value to insert in OP[0]. */
2239 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2243 /* Find the least significant set bit in IMM. */
2244 for (lsb = 0; lsb < 32; lsb++)
2251 /* Choose variants based on *sign* of the 5-bit field. */
2252 if ((imm & 0x10) == 0)
2253 len = (lsb <= 28) ? 4 : 32 - lsb;
2256 /* Find the width of the bitstring in IMM. */
2257 for (len = 5; len < 32; len++)
2259 if ((imm & (1 << len)) == 0)
2263 /* Sign extend IMM as a 5-bit value. */
2264 imm = (imm & 0xf) - 0x10;
2272 /* Compute position (in OP[1]) and width (in OP[2])
2273 useful for copying IMM to a register using the depdi,z
2274 instructions. Store the immediate value to insert in OP[0]. */
2276 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2278 HOST_WIDE_INT lsb, len;
2280 /* Find the least significant set bit in IMM. */
2281 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2288 /* Choose variants based on *sign* of the 5-bit field. */
2289 if ((imm & 0x10) == 0)
2290 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2291 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2294 /* Find the width of the bitstring in IMM. */
2295 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2297 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2301 /* Sign extend IMM as a 5-bit value. */
2302 imm = (imm & 0xf) - 0x10;
2310 /* Output assembler code to perform a doubleword move insn
2311 with operands OPERANDS. */
2314 output_move_double (rtx *operands)
2316 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2318 rtx addreg0 = 0, addreg1 = 0;
2320 /* First classify both operands. */
2322 if (REG_P (operands[0]))
2324 else if (offsettable_memref_p (operands[0]))
2326 else if (GET_CODE (operands[0]) == MEM)
2331 if (REG_P (operands[1]))
2333 else if (CONSTANT_P (operands[1]))
2335 else if (offsettable_memref_p (operands[1]))
2337 else if (GET_CODE (operands[1]) == MEM)
2342 /* Check for the cases that the operand constraints are not
2343 supposed to allow to happen. Abort if we get one,
2344 because generating code for these cases is painful. */
2346 if (optype0 != REGOP && optype1 != REGOP)
2349 /* Handle auto decrementing and incrementing loads and stores
2350 specifically, since the structure of the function doesn't work
2351 for them without major modification. Do it better when we learn
2352 this port about the general inc/dec addressing of PA.
2353 (This was written by tege. Chide him if it doesn't work.) */
2355 if (optype0 == MEMOP)
2357 /* We have to output the address syntax ourselves, since print_operand
2358 doesn't deal with the addresses we want to use. Fix this later. */
2360 rtx addr = XEXP (operands[0], 0);
2361 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2363 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2365 operands[0] = XEXP (addr, 0);
2366 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2369 if (!reg_overlap_mentioned_p (high_reg, addr))
2371 /* No overlap between high target register and address
2372 register. (We do this in a non-obvious way to
2373 save a register file writeback) */
2374 if (GET_CODE (addr) == POST_INC)
2375 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2376 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2381 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2383 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2385 operands[0] = XEXP (addr, 0);
2386 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2389 if (!reg_overlap_mentioned_p (high_reg, addr))
2391 /* No overlap between high target register and address
2392 register. (We do this in a non-obvious way to
2393 save a register file writeback) */
2394 if (GET_CODE (addr) == PRE_INC)
2395 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2396 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2402 if (optype1 == MEMOP)
2404 /* We have to output the address syntax ourselves, since print_operand
2405 doesn't deal with the addresses we want to use. Fix this later. */
2407 rtx addr = XEXP (operands[1], 0);
2408 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2410 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2412 operands[1] = XEXP (addr, 0);
2413 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2416 if (!reg_overlap_mentioned_p (high_reg, addr))
2418 /* No overlap between high target register and address
2419 register. (We do this in a non-obvious way to
2420 save a register file writeback) */
2421 if (GET_CODE (addr) == POST_INC)
2422 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2423 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2427 /* This is an undefined situation. We should load into the
2428 address register *and* update that register. Probably
2429 we don't need to handle this at all. */
2430 if (GET_CODE (addr) == POST_INC)
2431 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2432 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2435 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2437 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2439 operands[1] = XEXP (addr, 0);
2440 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2443 if (!reg_overlap_mentioned_p (high_reg, addr))
2445 /* No overlap between high target register and address
2446 register. (We do this in a non-obvious way to
2447 save a register file writeback) */
2448 if (GET_CODE (addr) == PRE_INC)
2449 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2450 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2454 /* This is an undefined situation. We should load into the
2455 address register *and* update that register. Probably
2456 we don't need to handle this at all. */
2457 if (GET_CODE (addr) == PRE_INC)
2458 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2459 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2462 else if (GET_CODE (addr) == PLUS
2463 && GET_CODE (XEXP (addr, 0)) == MULT)
2465 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2467 if (!reg_overlap_mentioned_p (high_reg, addr))
2471 xoperands[0] = high_reg;
2472 xoperands[1] = XEXP (addr, 1);
2473 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2474 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2475 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2477 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2483 xoperands[0] = high_reg;
2484 xoperands[1] = XEXP (addr, 1);
2485 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2486 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2487 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2489 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2494 /* If an operand is an unoffsettable memory ref, find a register
2495 we can increment temporarily to make it refer to the second word. */
2497 if (optype0 == MEMOP)
2498 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2500 if (optype1 == MEMOP)
2501 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2503 /* Ok, we can do one word at a time.
2504 Normally we do the low-numbered word first.
2506 In either case, set up in LATEHALF the operands to use
2507 for the high-numbered word and in some cases alter the
2508 operands in OPERANDS to be suitable for the low-numbered word. */
2510 if (optype0 == REGOP)
2511 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2512 else if (optype0 == OFFSOP)
2513 latehalf[0] = adjust_address (operands[0], SImode, 4);
2515 latehalf[0] = operands[0];
2517 if (optype1 == REGOP)
2518 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2519 else if (optype1 == OFFSOP)
2520 latehalf[1] = adjust_address (operands[1], SImode, 4);
2521 else if (optype1 == CNSTOP)
2522 split_double (operands[1], &operands[1], &latehalf[1]);
2524 latehalf[1] = operands[1];
2526 /* If the first move would clobber the source of the second one,
2527 do them in the other order.
2529 This can happen in two cases:
2531 mem -> register where the first half of the destination register
2532 is the same register used in the memory's address. Reload
2533 can create such insns.
2535 mem in this case will be either register indirect or register
2536 indirect plus a valid offset.
2538 register -> register move where REGNO(dst) == REGNO(src + 1)
2539 someone (Tim/Tege?) claimed this can happen for parameter loads.
2541 Handle mem -> register case first. */
2542 if (optype0 == REGOP
2543 && (optype1 == MEMOP || optype1 == OFFSOP)
2544 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2547 /* Do the late half first. */
2549 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2550 output_asm_insn (singlemove_string (latehalf), latehalf);
2554 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2555 return singlemove_string (operands);
2558 /* Now handle register -> register case. */
2559 if (optype0 == REGOP && optype1 == REGOP
2560 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2562 output_asm_insn (singlemove_string (latehalf), latehalf);
2563 return singlemove_string (operands);
2566 /* Normal case: do the two words, low-numbered first. */
2568 output_asm_insn (singlemove_string (operands), operands);
2570 /* Make any unoffsettable addresses point at high-numbered word. */
2572 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2574 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2577 output_asm_insn (singlemove_string (latehalf), latehalf);
2579 /* Undo the adds we just did. */
2581 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2583 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2589 output_fp_move_double (rtx *operands)
2591 if (FP_REG_P (operands[0]))
2593 if (FP_REG_P (operands[1])
2594 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2595 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2597 output_asm_insn ("fldd%F1 %1,%0", operands);
2599 else if (FP_REG_P (operands[1]))
2601 output_asm_insn ("fstd%F0 %1,%0", operands);
2603 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2605 if (GET_CODE (operands[0]) == REG)
2608 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2609 xoperands[0] = operands[0];
2610 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2612 /* This is a pain. You have to be prepared to deal with an
2613 arbitrary address here including pre/post increment/decrement.
2615 so avoid this in the MD. */
2623 /* Return a REG that occurs in ADDR with coefficient 1.
2624 ADDR can be effectively incremented by incrementing REG. */
2627 find_addr_reg (rtx addr)
2629 while (GET_CODE (addr) == PLUS)
2631 if (GET_CODE (XEXP (addr, 0)) == REG)
2632 addr = XEXP (addr, 0);
2633 else if (GET_CODE (XEXP (addr, 1)) == REG)
2634 addr = XEXP (addr, 1);
2635 else if (CONSTANT_P (XEXP (addr, 0)))
2636 addr = XEXP (addr, 1);
2637 else if (CONSTANT_P (XEXP (addr, 1)))
2638 addr = XEXP (addr, 0);
2642 if (GET_CODE (addr) == REG)
2647 /* Emit code to perform a block move.
2649 OPERANDS[0] is the destination pointer as a REG, clobbered.
2650 OPERANDS[1] is the source pointer as a REG, clobbered.
2651 OPERANDS[2] is a register for temporary storage.
2652 OPERANDS[3] is a register for temporary storage.
2653 OPERANDS[4] is the size as a CONST_INT
2654 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2655 OPERANDS[6] is another temporary register. */
2658 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2660 int align = INTVAL (operands[5]);
2661 unsigned long n_bytes = INTVAL (operands[4]);
2663 /* We can't move more than a word at a time because the PA
2664 has no longer integer move insns. (Could use fp mem ops?) */
2665 if (align > (TARGET_64BIT ? 8 : 4))
2666 align = (TARGET_64BIT ? 8 : 4);
2668 /* Note that we know each loop below will execute at least twice
2669 (else we would have open-coded the copy). */
2673 /* Pre-adjust the loop counter. */
2674 operands[4] = GEN_INT (n_bytes - 16);
2675 output_asm_insn ("ldi %4,%2", operands);
2678 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2679 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2680 output_asm_insn ("std,ma %3,8(%0)", operands);
2681 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2682 output_asm_insn ("std,ma %6,8(%0)", operands);
2684 /* Handle the residual. There could be up to 7 bytes of
2685 residual to copy! */
2686 if (n_bytes % 16 != 0)
2688 operands[4] = GEN_INT (n_bytes % 8);
2689 if (n_bytes % 16 >= 8)
2690 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2691 if (n_bytes % 8 != 0)
2692 output_asm_insn ("ldd 0(%1),%6", operands);
2693 if (n_bytes % 16 >= 8)
2694 output_asm_insn ("std,ma %3,8(%0)", operands);
2695 if (n_bytes % 8 != 0)
2696 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2701 /* Pre-adjust the loop counter. */
2702 operands[4] = GEN_INT (n_bytes - 8);
2703 output_asm_insn ("ldi %4,%2", operands);
2706 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2707 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2708 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2709 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2710 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2712 /* Handle the residual. There could be up to 7 bytes of
2713 residual to copy! */
2714 if (n_bytes % 8 != 0)
2716 operands[4] = GEN_INT (n_bytes % 4);
2717 if (n_bytes % 8 >= 4)
2718 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2719 if (n_bytes % 4 != 0)
2720 output_asm_insn ("ldw 0(%1),%6", operands);
2721 if (n_bytes % 8 >= 4)
2722 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2723 if (n_bytes % 4 != 0)
2724 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2729 /* Pre-adjust the loop counter. */
2730 operands[4] = GEN_INT (n_bytes - 4);
2731 output_asm_insn ("ldi %4,%2", operands);
2734 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2735 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2736 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2737 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2738 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2740 /* Handle the residual. */
2741 if (n_bytes % 4 != 0)
2743 if (n_bytes % 4 >= 2)
2744 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2745 if (n_bytes % 2 != 0)
2746 output_asm_insn ("ldb 0(%1),%6", operands);
2747 if (n_bytes % 4 >= 2)
2748 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2749 if (n_bytes % 2 != 0)
2750 output_asm_insn ("stb %6,0(%0)", operands);
2755 /* Pre-adjust the loop counter. */
2756 operands[4] = GEN_INT (n_bytes - 2);
2757 output_asm_insn ("ldi %4,%2", operands);
2760 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2761 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2762 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2763 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2764 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2766 /* Handle the residual. */
2767 if (n_bytes % 2 != 0)
2769 output_asm_insn ("ldb 0(%1),%3", operands);
2770 output_asm_insn ("stb %3,0(%0)", operands);
2779 /* Count the number of insns necessary to handle this block move.
2781 Basic structure is the same as emit_block_move, except that we
2782 count insns rather than emit them. */
2785 compute_movstr_length (rtx insn)
2787 rtx pat = PATTERN (insn);
2788 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2789 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2790 unsigned int n_insns = 0;
2792 /* We can't move more than four bytes at a time because the PA
2793 has no longer integer move insns. (Could use fp mem ops?) */
2794 if (align > (TARGET_64BIT ? 8 : 4))
2795 align = (TARGET_64BIT ? 8 : 4);
2797 /* The basic copying loop. */
2801 if (n_bytes % (2 * align) != 0)
2803 if ((n_bytes % (2 * align)) >= align)
2806 if ((n_bytes % align) != 0)
2810 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2814 /* Emit code to perform a block clear.
2816 OPERANDS[0] is the destination pointer as a REG, clobbered.
2817 OPERANDS[1] is a register for temporary storage.
2818 OPERANDS[2] is the size as a CONST_INT
2819 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2822 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2824 int align = INTVAL (operands[3]);
2825 unsigned long n_bytes = INTVAL (operands[2]);
2827 /* We can't clear more than a word at a time because the PA
2828 has no longer integer move insns. */
2829 if (align > (TARGET_64BIT ? 8 : 4))
2830 align = (TARGET_64BIT ? 8 : 4);
2832 /* Note that we know each loop below will execute at least twice
2833 (else we would have open-coded the copy). */
2837 /* Pre-adjust the loop counter. */
2838 operands[2] = GEN_INT (n_bytes - 16);
2839 output_asm_insn ("ldi %2,%1", operands);
2842 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2843 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2844 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2846 /* Handle the residual. There could be up to 7 bytes of
2847 residual to copy! */
2848 if (n_bytes % 16 != 0)
2850 operands[2] = GEN_INT (n_bytes % 8);
2851 if (n_bytes % 16 >= 8)
2852 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2853 if (n_bytes % 8 != 0)
2854 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2859 /* Pre-adjust the loop counter. */
2860 operands[2] = GEN_INT (n_bytes - 8);
2861 output_asm_insn ("ldi %2,%1", operands);
2864 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2865 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2866 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2868 /* Handle the residual. There could be up to 7 bytes of
2869 residual to copy! */
2870 if (n_bytes % 8 != 0)
2872 operands[2] = GEN_INT (n_bytes % 4);
2873 if (n_bytes % 8 >= 4)
2874 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2875 if (n_bytes % 4 != 0)
2876 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2881 /* Pre-adjust the loop counter. */
2882 operands[2] = GEN_INT (n_bytes - 4);
2883 output_asm_insn ("ldi %2,%1", operands);
2886 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2887 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2888 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2890 /* Handle the residual. */
2891 if (n_bytes % 4 != 0)
2893 if (n_bytes % 4 >= 2)
2894 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2895 if (n_bytes % 2 != 0)
2896 output_asm_insn ("stb %%r0,0(%0)", operands);
2901 /* Pre-adjust the loop counter. */
2902 operands[2] = GEN_INT (n_bytes - 2);
2903 output_asm_insn ("ldi %2,%1", operands);
2906 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2907 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2908 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2910 /* Handle the residual. */
2911 if (n_bytes % 2 != 0)
2912 output_asm_insn ("stb %%r0,0(%0)", operands);
2921 /* Count the number of insns necessary to handle this block move.
2923 Basic structure is the same as emit_block_move, except that we
2924 count insns rather than emit them. */
2927 compute_clrstr_length (rtx insn)
2929 rtx pat = PATTERN (insn);
2930 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2931 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2932 unsigned int n_insns = 0;
2934 /* We can't clear more than a word at a time because the PA
2935 has no longer integer move insns. */
2936 if (align > (TARGET_64BIT ? 8 : 4))
2937 align = (TARGET_64BIT ? 8 : 4);
2939 /* The basic loop. */
2943 if (n_bytes % (2 * align) != 0)
2945 if ((n_bytes % (2 * align)) >= align)
2948 if ((n_bytes % align) != 0)
2952 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2958 output_and (rtx *operands)
2960 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2962 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2963 int ls0, ls1, ms0, p, len;
2965 for (ls0 = 0; ls0 < 32; ls0++)
2966 if ((mask & (1 << ls0)) == 0)
2969 for (ls1 = ls0; ls1 < 32; ls1++)
2970 if ((mask & (1 << ls1)) != 0)
2973 for (ms0 = ls1; ms0 < 32; ms0++)
2974 if ((mask & (1 << ms0)) == 0)
2987 operands[2] = GEN_INT (len);
2988 return "{extru|extrw,u} %1,31,%2,%0";
2992 /* We could use this `depi' for the case above as well, but `depi'
2993 requires one more register file access than an `extru'. */
2998 operands[2] = GEN_INT (p);
2999 operands[3] = GEN_INT (len);
3000 return "{depi|depwi} 0,%2,%3,%0";
3004 return "and %1,%2,%0";
3007 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3008 storing the result in operands[0]. */
3010 output_64bit_and (rtx *operands)
3012 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3014 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3015 int ls0, ls1, ms0, p, len;
3017 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3018 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3021 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3022 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3025 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3026 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3029 if (ms0 != HOST_BITS_PER_WIDE_INT)
3032 if (ls1 == HOST_BITS_PER_WIDE_INT)
3039 operands[2] = GEN_INT (len);
3040 return "extrd,u %1,63,%2,%0";
3044 /* We could use this `depi' for the case above as well, but `depi'
3045 requires one more register file access than an `extru'. */
3050 operands[2] = GEN_INT (p);
3051 operands[3] = GEN_INT (len);
3052 return "depdi 0,%2,%3,%0";
3056 return "and %1,%2,%0";
3060 output_ior (rtx *operands)
3062 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3063 int bs0, bs1, p, len;
3065 if (INTVAL (operands[2]) == 0)
3066 return "copy %1,%0";
3068 for (bs0 = 0; bs0 < 32; bs0++)
3069 if ((mask & (1 << bs0)) != 0)
3072 for (bs1 = bs0; bs1 < 32; bs1++)
3073 if ((mask & (1 << bs1)) == 0)
3076 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3082 operands[2] = GEN_INT (p);
3083 operands[3] = GEN_INT (len);
3084 return "{depi|depwi} -1,%2,%3,%0";
3087 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3088 storing the result in operands[0]. */
3090 output_64bit_ior (rtx *operands)
3092 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3093 int bs0, bs1, p, len;
3095 if (INTVAL (operands[2]) == 0)
3096 return "copy %1,%0";
3098 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3099 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3102 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3103 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3106 if (bs1 != HOST_BITS_PER_WIDE_INT
3107 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3113 operands[2] = GEN_INT (p);
3114 operands[3] = GEN_INT (len);
3115 return "depdi -1,%2,%3,%0";
3118 /* Target hook for assembling integer objects. This code handles
3119 aligned SI and DI integers specially, since function references must
3120 be preceded by P%. */
3123 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3125 if (size == UNITS_PER_WORD && aligned_p
3126 && function_label_operand (x, VOIDmode))
3128 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3129 output_addr_const (asm_out_file, x);
3130 fputc ('\n', asm_out_file);
3133 return default_assemble_integer (x, size, aligned_p);
3136 /* Output an ascii string. */
3138 output_ascii (FILE *file, const char *p, int size)
3142 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3144 /* The HP assembler can only take strings of 256 characters at one
3145 time. This is a limitation on input line length, *not* the
3146 length of the string. Sigh. Even worse, it seems that the
3147 restriction is in number of input characters (see \xnn &
3148 \whatever). So we have to do this very carefully. */
3150 fputs ("\t.STRING \"", file);
3153 for (i = 0; i < size; i += 4)
3157 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3159 register unsigned int c = (unsigned char) p[i + io];
3161 if (c == '\"' || c == '\\')
3162 partial_output[co++] = '\\';
3163 if (c >= ' ' && c < 0177)
3164 partial_output[co++] = c;
3168 partial_output[co++] = '\\';
3169 partial_output[co++] = 'x';
3170 hexd = c / 16 - 0 + '0';
3172 hexd -= '9' - 'a' + 1;
3173 partial_output[co++] = hexd;
3174 hexd = c % 16 - 0 + '0';
3176 hexd -= '9' - 'a' + 1;
3177 partial_output[co++] = hexd;
3180 if (chars_output + co > 243)
3182 fputs ("\"\n\t.STRING \"", file);
3185 fwrite (partial_output, 1, (size_t) co, file);
3189 fputs ("\"\n", file);
3192 /* Try to rewrite floating point comparisons & branches to avoid
3193 useless add,tr insns.
3195 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3196 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3197 first attempt to remove useless add,tr insns. It is zero
3198 for the second pass as reorg sometimes leaves bogus REG_DEAD
3201 When CHECK_NOTES is zero we can only eliminate add,tr insns
3202 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3205 remove_useless_addtr_insns (int check_notes)
3208 static int pass = 0;
3210 /* This is fairly cheap, so always run it when optimizing. */
3214 int fbranch_count = 0;
3216 /* Walk all the insns in this function looking for fcmp & fbranch
3217 instructions. Keep track of how many of each we find. */
3218 for (insn = get_insns (); insn; insn = next_insn (insn))
3222 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3223 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3226 tmp = PATTERN (insn);
3228 /* It must be a set. */
3229 if (GET_CODE (tmp) != SET)
3232 /* If the destination is CCFP, then we've found an fcmp insn. */
3233 tmp = SET_DEST (tmp);
3234 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3240 tmp = PATTERN (insn);
3241 /* If this is an fbranch instruction, bump the fbranch counter. */
3242 if (GET_CODE (tmp) == SET
3243 && SET_DEST (tmp) == pc_rtx
3244 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3245 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3246 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3247 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3255 /* Find all floating point compare + branch insns. If possible,
3256 reverse the comparison & the branch to avoid add,tr insns. */
3257 for (insn = get_insns (); insn; insn = next_insn (insn))
3261 /* Ignore anything that isn't an INSN. */
3262 if (GET_CODE (insn) != INSN)
3265 tmp = PATTERN (insn);
3267 /* It must be a set. */
3268 if (GET_CODE (tmp) != SET)
3271 /* The destination must be CCFP, which is register zero. */
3272 tmp = SET_DEST (tmp);
3273 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3276 /* INSN should be a set of CCFP.
3278 See if the result of this insn is used in a reversed FP
3279 conditional branch. If so, reverse our condition and
3280 the branch. Doing so avoids useless add,tr insns. */
3281 next = next_insn (insn);
3284 /* Jumps, calls and labels stop our search. */
3285 if (GET_CODE (next) == JUMP_INSN
3286 || GET_CODE (next) == CALL_INSN
3287 || GET_CODE (next) == CODE_LABEL)
3290 /* As does another fcmp insn. */
3291 if (GET_CODE (next) == INSN
3292 && GET_CODE (PATTERN (next)) == SET
3293 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3294 && REGNO (SET_DEST (PATTERN (next))) == 0)
3297 next = next_insn (next);
3300 /* Is NEXT_INSN a branch? */
3302 && GET_CODE (next) == JUMP_INSN)
3304 rtx pattern = PATTERN (next);
3306 /* If it a reversed fp conditional branch (eg uses add,tr)
3307 and CCFP dies, then reverse our conditional and the branch
3308 to avoid the add,tr. */
3309 if (GET_CODE (pattern) == SET
3310 && SET_DEST (pattern) == pc_rtx
3311 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3312 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3313 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3314 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3315 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3316 && (fcmp_count == fbranch_count
3318 && find_regno_note (next, REG_DEAD, 0))))
3320 /* Reverse the branch. */
3321 tmp = XEXP (SET_SRC (pattern), 1);
3322 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3323 XEXP (SET_SRC (pattern), 2) = tmp;
3324 INSN_CODE (next) = -1;
3326 /* Reverse our condition. */
3327 tmp = PATTERN (insn);
3328 PUT_CODE (XEXP (tmp, 1),
3329 (reverse_condition_maybe_unordered
3330 (GET_CODE (XEXP (tmp, 1)))));
3340 /* You may have trouble believing this, but this is the 32 bit HP-PA
3345 Variable arguments (optional; any number may be allocated)
3347 SP-(4*(N+9)) arg word N
3352 Fixed arguments (must be allocated; may remain unused)
3361 SP-32 External Data Pointer (DP)
3363 SP-24 External/stub RP (RP')
3367 SP-8 Calling Stub RP (RP'')
3372 SP-0 Stack Pointer (points to next available address)
3376 /* This function saves registers as follows. Registers marked with ' are
3377 this function's registers (as opposed to the previous function's).
3378 If a frame_pointer isn't needed, r4 is saved as a general register;
3379 the space for the frame pointer is still allocated, though, to keep
3385 SP (FP') Previous FP
3386 SP + 4 Alignment filler (sigh)
3387 SP + 8 Space for locals reserved here.
3391 SP + n All call saved register used.
3395 SP + o All call saved fp registers used.
3399 SP + p (SP') points to next available address.
3403 /* Global variables set by output_function_prologue(). */
3404 /* Size of frame. Need to know this to emit return insns from
3406 static HOST_WIDE_INT actual_fsize, local_fsize;
3407 static int save_fregs;
3409 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3410 Handle case where DISP > 8k by using the add_high_const patterns.
3412 Note in DISP > 8k case, we will leave the high part of the address
3413 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3416 store_reg (int reg, HOST_WIDE_INT disp, int base)
3418 rtx insn, dest, src, basereg;
3420 src = gen_rtx_REG (word_mode, reg);
3421 basereg = gen_rtx_REG (Pmode, base);
3422 if (VAL_14_BITS_P (disp))
3424 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3425 insn = emit_move_insn (dest, src);
3427 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3429 rtx delta = GEN_INT (disp);
3430 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3432 emit_move_insn (tmpreg, delta);
3433 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3434 dest = gen_rtx_MEM (word_mode, tmpreg);
3435 insn = emit_move_insn (dest, src);
3439 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3440 gen_rtx_SET (VOIDmode,
3441 gen_rtx_MEM (word_mode,
3442 gen_rtx_PLUS (word_mode, basereg,
3450 rtx delta = GEN_INT (disp);
3451 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3452 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3454 emit_move_insn (tmpreg, high);
3455 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3456 insn = emit_move_insn (dest, src);
3460 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3461 gen_rtx_SET (VOIDmode,
3462 gen_rtx_MEM (word_mode,
3463 gen_rtx_PLUS (word_mode, basereg,
3471 RTX_FRAME_RELATED_P (insn) = 1;
3474 /* Emit RTL to store REG at the memory location specified by BASE and then
3475 add MOD to BASE. MOD must be <= 8k. */
3478 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3480 rtx insn, basereg, srcreg, delta;
3482 if (!VAL_14_BITS_P (mod))
3485 basereg = gen_rtx_REG (Pmode, base);
3486 srcreg = gen_rtx_REG (word_mode, reg);
3487 delta = GEN_INT (mod);
3489 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3492 RTX_FRAME_RELATED_P (insn) = 1;
3494 /* RTX_FRAME_RELATED_P must be set on each frame related set
3495 in a parallel with more than one element. Don't set
3496 RTX_FRAME_RELATED_P in the first set if reg is temporary
3497 register 1. The effect of this operation is recorded in
3498 the initial copy. */
3501 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3502 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3506 /* The first element of a PARALLEL is always processed if it is
3507 a SET. Thus, we need an expression list for this case. */
3509 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3510 gen_rtx_SET (VOIDmode, basereg,
3511 gen_rtx_PLUS (word_mode, basereg, delta)),
3517 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3518 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3519 whether to add a frame note or not.
3521 In the DISP > 8k case, we leave the high part of the address in %r1.
3522 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3525 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3529 if (VAL_14_BITS_P (disp))
3531 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3532 plus_constant (gen_rtx_REG (Pmode, base), disp));
3534 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3536 rtx basereg = gen_rtx_REG (Pmode, base);
3537 rtx delta = GEN_INT (disp);
3538 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3540 emit_move_insn (tmpreg, delta);
3541 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3542 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3546 rtx basereg = gen_rtx_REG (Pmode, base);
3547 rtx delta = GEN_INT (disp);
3548 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3550 emit_move_insn (tmpreg,
3551 gen_rtx_PLUS (Pmode, basereg,
3552 gen_rtx_HIGH (Pmode, delta)));
3553 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3554 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3557 if (DO_FRAME_NOTES && note)
3558 RTX_FRAME_RELATED_P (insn) = 1;
3562 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3567 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3568 be consistent with the rounding and size calculation done here.
3569 Change them at the same time. */
3571 /* We do our own stack alignment. First, round the size of the
3572 stack locals up to a word boundary. */
3573 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3575 /* Space for previous frame pointer + filler. If any frame is
3576 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3577 waste some space here for the sake of HP compatibility. The
3578 first slot is only used when the frame pointer is needed. */
3579 if (size || frame_pointer_needed)
3580 size += STARTING_FRAME_OFFSET;
3582 /* If the current function calls __builtin_eh_return, then we need
3583 to allocate stack space for registers that will hold data for
3584 the exception handler. */
3585 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3589 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3591 size += i * UNITS_PER_WORD;
3594 /* Account for space used by the callee general register saves. */
3595 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3596 if (regs_ever_live[i])
3597 size += UNITS_PER_WORD;
3599 /* Account for space used by the callee floating point register saves. */
3600 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3601 if (regs_ever_live[i]
3602 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3606 /* We always save both halves of the FP register, so always
3607 increment the frame size by 8 bytes. */
3611 /* If any of the floating registers are saved, account for the
3612 alignment needed for the floating point register save block. */
3615 size = (size + 7) & ~7;
3620 /* The various ABIs include space for the outgoing parameters in the
3621 size of the current function's stack frame. We don't need to align
3622 for the outgoing arguments as their alignment is set by the final
3623 rounding for the frame as a whole. */
3624 size += current_function_outgoing_args_size;
3626 /* Allocate space for the fixed frame marker. This space must be
3627 allocated for any function that makes calls or allocates
3629 if (!current_function_is_leaf || size)
3630 size += TARGET_64BIT ? 48 : 32;
3632 /* Finally, round to the preferred stack boundary. */
3633 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3634 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3637 /* Generate the assembly code for function entry. FILE is a stdio
3638 stream to output the code to. SIZE is an int: how many units of
3639 temporary storage to allocate.
3641 Refer to the array `regs_ever_live' to determine which registers to
3642 save; `regs_ever_live[I]' is nonzero if register number I is ever
3643 used in the function. This function is responsible for knowing
3644 which registers should not be saved even if used. */
3646 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3647 of memory. If any fpu reg is used in the function, we allocate
3648 such a block here, at the bottom of the frame, just in case it's needed.
3650 If this function is a leaf procedure, then we may choose not
3651 to do a "save" insn. The decision about whether or not
3652 to do this is made in regclass.c. */
3655 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3657 /* The function's label and associated .PROC must never be
3658 separated and must be output *after* any profiling declarations
3659 to avoid changing spaces/subspaces within a procedure. */
3660 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3661 fputs ("\t.PROC\n", file);
3663 /* hppa_expand_prologue does the dirty work now. We just need
3664 to output the assembler directives which denote the start
3666 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3667 if (regs_ever_live[2])
3668 fputs (",CALLS,SAVE_RP", file);
3670 fputs (",NO_CALLS", file);
3672 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3673 at the beginning of the frame and that it is used as the frame
3674 pointer for the frame. We do this because our current frame
3675 layout doesn't conform to that specified in the the HP runtime
3676 documentation and we need a way to indicate to programs such as
3677 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3678 isn't used by HP compilers but is supported by the assembler.
3679 However, SAVE_SP is supposed to indicate that the previous stack
3680 pointer has been saved in the frame marker. */
3681 if (frame_pointer_needed)
3682 fputs (",SAVE_SP", file);
3684 /* Pass on information about the number of callee register saves
3685 performed in the prologue.
3687 The compiler is supposed to pass the highest register number
3688 saved, the assembler then has to adjust that number before
3689 entering it into the unwind descriptor (to account for any
3690 caller saved registers with lower register numbers than the
3691 first callee saved register). */
3693 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3696 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3698 fputs ("\n\t.ENTRY\n", file);
3700 remove_useless_addtr_insns (0);
3704 hppa_expand_prologue (void)
3706 int merge_sp_adjust_with_store = 0;
3707 HOST_WIDE_INT size = get_frame_size ();
3708 HOST_WIDE_INT offset;
3716 /* Compute total size for frame pointer, filler, locals and rounding to
3717 the next word boundary. Similar code appears in compute_frame_size
3718 and must be changed in tandem with this code. */
3719 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3720 if (local_fsize || frame_pointer_needed)
3721 local_fsize += STARTING_FRAME_OFFSET;
3723 actual_fsize = compute_frame_size (size, &save_fregs);
3725 /* Compute a few things we will use often. */
3726 tmpreg = gen_rtx_REG (word_mode, 1);
3728 /* Save RP first. The calling conventions manual states RP will
3729 always be stored into the caller's frame at sp - 20 or sp - 16
3730 depending on which ABI is in use. */
3731 if (regs_ever_live[2] || current_function_calls_eh_return)
3732 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3734 /* Allocate the local frame and set up the frame pointer if needed. */
3735 if (actual_fsize != 0)
3737 if (frame_pointer_needed)
3739 /* Copy the old frame pointer temporarily into %r1. Set up the
3740 new stack pointer, then store away the saved old frame pointer
3741 into the stack at sp and at the same time update the stack
3742 pointer by actual_fsize bytes. Two versions, first
3743 handles small (<8k) frames. The second handles large (>=8k)
3745 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3748 /* We need to record the frame pointer save here since the
3749 new frame pointer is set in the following insn. */
3750 RTX_FRAME_RELATED_P (insn) = 1;
3752 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3753 gen_rtx_SET (VOIDmode,
3754 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3759 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3761 RTX_FRAME_RELATED_P (insn) = 1;
3763 if (VAL_14_BITS_P (actual_fsize))
3764 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3767 /* It is incorrect to store the saved frame pointer at *sp,
3768 then increment sp (writes beyond the current stack boundary).
3770 So instead use stwm to store at *sp and post-increment the
3771 stack pointer as an atomic operation. Then increment sp to
3772 finish allocating the new frame. */
3773 HOST_WIDE_INT adjust1 = 8192 - 64;
3774 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3776 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3777 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3781 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3782 we need to store the previous stack pointer (frame pointer)
3783 into the frame marker on targets that use the HP unwind
3784 library. This allows the HP unwind library to be used to
3785 unwind GCC frames. However, we are not fully compatible
3786 with the HP library because our frame layout differs from
3787 that specified in the HP runtime specification.
3789 We don't want a frame note on this instruction as the frame
3790 marker moves during dynamic stack allocation.
3792 This instruction also serves as a blockage to prevent
3793 register spills from being scheduled before the stack
3794 pointer is raised. This is necessary as we store
3795 registers using the frame pointer as a base register,
3796 and the frame pointer is set before sp is raised. */
3797 if (TARGET_HPUX_UNWIND_LIBRARY)
3799 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3800 GEN_INT (TARGET_64BIT ? -8 : -4));
3802 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3806 emit_insn (gen_blockage ());
3808 /* no frame pointer needed. */
3811 /* In some cases we can perform the first callee register save
3812 and allocating the stack frame at the same time. If so, just
3813 make a note of it and defer allocating the frame until saving
3814 the callee registers. */
3815 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3816 merge_sp_adjust_with_store = 1;
3817 /* Can not optimize. Adjust the stack frame by actual_fsize
3820 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3825 /* Normal register save.
3827 Do not save the frame pointer in the frame_pointer_needed case. It
3828 was done earlier. */
3829 if (frame_pointer_needed)
3831 offset = local_fsize;
3833 /* Saving the EH return data registers in the frame is the simplest
3834 way to get the frame unwind information emitted. We put them
3835 just before the general registers. */
3836 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3838 unsigned int i, regno;
3842 regno = EH_RETURN_DATA_REGNO (i);
3843 if (regno == INVALID_REGNUM)
3846 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3847 offset += UNITS_PER_WORD;
3851 for (i = 18; i >= 4; i--)
3852 if (regs_ever_live[i] && ! call_used_regs[i])
3854 store_reg (i, offset, FRAME_POINTER_REGNUM);
3855 offset += UNITS_PER_WORD;
3858 /* Account for %r3 which is saved in a special place. */
3861 /* No frame pointer needed. */
3864 offset = local_fsize - actual_fsize;
3866 /* Saving the EH return data registers in the frame is the simplest
3867 way to get the frame unwind information emitted. */
3868 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3870 unsigned int i, regno;
3874 regno = EH_RETURN_DATA_REGNO (i);
3875 if (regno == INVALID_REGNUM)
3878 /* If merge_sp_adjust_with_store is nonzero, then we can
3879 optimize the first save. */
3880 if (merge_sp_adjust_with_store)
3882 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3883 merge_sp_adjust_with_store = 0;
3886 store_reg (regno, offset, STACK_POINTER_REGNUM);
3887 offset += UNITS_PER_WORD;
3891 for (i = 18; i >= 3; i--)
3892 if (regs_ever_live[i] && ! call_used_regs[i])
3894 /* If merge_sp_adjust_with_store is nonzero, then we can
3895 optimize the first GR save. */
3896 if (merge_sp_adjust_with_store)
3898 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3899 merge_sp_adjust_with_store = 0;
3902 store_reg (i, offset, STACK_POINTER_REGNUM);
3903 offset += UNITS_PER_WORD;
3907 /* If we wanted to merge the SP adjustment with a GR save, but we never
3908 did any GR saves, then just emit the adjustment here. */
3909 if (merge_sp_adjust_with_store)
3910 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3914 /* The hppa calling conventions say that %r19, the pic offset
3915 register, is saved at sp - 32 (in this function's frame)
3916 when generating PIC code. FIXME: What is the correct thing
3917 to do for functions which make no calls and allocate no
3918 frame? Do we need to allocate a frame, or can we just omit
3919 the save? For now we'll just omit the save.
3921 We don't want a note on this insn as the frame marker can
3922 move if there is a dynamic stack allocation. */
3923 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3925 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3927 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3931 /* Align pointer properly (doubleword boundary). */
3932 offset = (offset + 7) & ~7;
3934 /* Floating point register store. */
3939 /* First get the frame or stack pointer to the start of the FP register
3941 if (frame_pointer_needed)
3943 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3944 base = frame_pointer_rtx;
3948 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3949 base = stack_pointer_rtx;
3952 /* Now actually save the FP registers. */
3953 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3955 if (regs_ever_live[i]
3956 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3958 rtx addr, insn, reg;
3959 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3960 reg = gen_rtx_REG (DFmode, i);
3961 insn = emit_move_insn (addr, reg);
3964 RTX_FRAME_RELATED_P (insn) = 1;
3967 rtx mem = gen_rtx_MEM (DFmode,
3968 plus_constant (base, offset));
3970 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3971 gen_rtx_SET (VOIDmode, mem, reg),
3976 rtx meml = gen_rtx_MEM (SFmode,
3977 plus_constant (base, offset));
3978 rtx memr = gen_rtx_MEM (SFmode,
3979 plus_constant (base, offset + 4));
3980 rtx regl = gen_rtx_REG (SFmode, i);
3981 rtx regr = gen_rtx_REG (SFmode, i + 1);
3982 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3983 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3986 RTX_FRAME_RELATED_P (setl) = 1;
3987 RTX_FRAME_RELATED_P (setr) = 1;
3988 vec = gen_rtvec (2, setl, setr);
3990 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3991 gen_rtx_SEQUENCE (VOIDmode, vec),
3995 offset += GET_MODE_SIZE (DFmode);
4002 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4003 Handle case where DISP > 8k by using the add_high_const patterns. */
4006 load_reg (int reg, HOST_WIDE_INT disp, int base)
4008 rtx dest = gen_rtx_REG (word_mode, reg);
4009 rtx basereg = gen_rtx_REG (Pmode, base);
4012 if (VAL_14_BITS_P (disp))
4013 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4014 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4016 rtx delta = GEN_INT (disp);
4017 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4019 emit_move_insn (tmpreg, delta);
4020 if (TARGET_DISABLE_INDEXING)
4022 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4023 src = gen_rtx_MEM (word_mode, tmpreg);
4026 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4030 rtx delta = GEN_INT (disp);
4031 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4032 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4034 emit_move_insn (tmpreg, high);
4035 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4038 emit_move_insn (dest, src);
4041 /* Update the total code bytes output to the text section. */
4044 update_total_code_bytes (int nbytes)
4046 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4047 && !IN_NAMED_SECTION_P (cfun->decl))
4049 if (INSN_ADDRESSES_SET_P ())
4051 unsigned long old_total = total_code_bytes;
4053 total_code_bytes += nbytes;
4055 /* Be prepared to handle overflows. */
4056 if (old_total > total_code_bytes)
4057 total_code_bytes = -1;
4060 total_code_bytes = -1;
4064 /* This function generates the assembly code for function exit.
4065 Args are as for output_function_prologue ().
4067 The function epilogue should not depend on the current stack
4068 pointer! It should use the frame pointer only. This is mandatory
4069 because of alloca; we also take advantage of it to omit stack
4070 adjustments before returning. */
4073 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4075 rtx insn = get_last_insn ();
4079 /* hppa_expand_epilogue does the dirty work now. We just need
4080 to output the assembler directives which denote the end
4083 To make debuggers happy, emit a nop if the epilogue was completely
4084 eliminated due to a volatile call as the last insn in the
4085 current function. That way the return address (in %r2) will
4086 always point to a valid instruction in the current function. */
4088 /* Get the last real insn. */
4089 if (GET_CODE (insn) == NOTE)
4090 insn = prev_real_insn (insn);
4092 /* If it is a sequence, then look inside. */
4093 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4094 insn = XVECEXP (PATTERN (insn), 0, 0);
4096 /* If insn is a CALL_INSN, then it must be a call to a volatile
4097 function (otherwise there would be epilogue insns). */
4098 if (insn && GET_CODE (insn) == CALL_INSN)
4100 fputs ("\tnop\n", file);
4104 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4106 if (INSN_ADDRESSES_SET_P ())
4108 insn = get_last_nonnote_insn ();
4109 last_address += INSN_ADDRESSES (INSN_UID (insn));
4111 last_address += insn_default_length (insn);
4112 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4113 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4116 /* Finally, update the total number of code bytes output so far. */
4117 update_total_code_bytes (last_address);
4121 hppa_expand_epilogue (void)
4124 HOST_WIDE_INT offset;
4125 HOST_WIDE_INT ret_off = 0;
4127 int merge_sp_adjust_with_load = 0;
4129 /* We will use this often. */
4130 tmpreg = gen_rtx_REG (word_mode, 1);
4132 /* Try to restore RP early to avoid load/use interlocks when
4133 RP gets used in the return (bv) instruction. This appears to still
4134 be necessary even when we schedule the prologue and epilogue. */
4135 if (regs_ever_live [2] || current_function_calls_eh_return)
4137 ret_off = TARGET_64BIT ? -16 : -20;
4138 if (frame_pointer_needed)
4140 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4145 /* No frame pointer, and stack is smaller than 8k. */
4146 if (VAL_14_BITS_P (ret_off - actual_fsize))
4148 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4154 /* General register restores. */
4155 if (frame_pointer_needed)
4157 offset = local_fsize;
4159 /* If the current function calls __builtin_eh_return, then we need
4160 to restore the saved EH data registers. */
4161 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4163 unsigned int i, regno;
4167 regno = EH_RETURN_DATA_REGNO (i);
4168 if (regno == INVALID_REGNUM)
4171 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4172 offset += UNITS_PER_WORD;
4176 for (i = 18; i >= 4; i--)
4177 if (regs_ever_live[i] && ! call_used_regs[i])
4179 load_reg (i, offset, FRAME_POINTER_REGNUM);
4180 offset += UNITS_PER_WORD;
4185 offset = local_fsize - actual_fsize;
4187 /* If the current function calls __builtin_eh_return, then we need
4188 to restore the saved EH data registers. */
4189 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4191 unsigned int i, regno;
4195 regno = EH_RETURN_DATA_REGNO (i);
4196 if (regno == INVALID_REGNUM)
4199 /* Only for the first load.
4200 merge_sp_adjust_with_load holds the register load
4201 with which we will merge the sp adjustment. */
4202 if (merge_sp_adjust_with_load == 0
4204 && VAL_14_BITS_P (-actual_fsize))
4205 merge_sp_adjust_with_load = regno;
4207 load_reg (regno, offset, STACK_POINTER_REGNUM);
4208 offset += UNITS_PER_WORD;
4212 for (i = 18; i >= 3; i--)
4214 if (regs_ever_live[i] && ! call_used_regs[i])
4216 /* Only for the first load.
4217 merge_sp_adjust_with_load holds the register load
4218 with which we will merge the sp adjustment. */
4219 if (merge_sp_adjust_with_load == 0
4221 && VAL_14_BITS_P (-actual_fsize))
4222 merge_sp_adjust_with_load = i;
4224 load_reg (i, offset, STACK_POINTER_REGNUM);
4225 offset += UNITS_PER_WORD;
4230 /* Align pointer properly (doubleword boundary). */
4231 offset = (offset + 7) & ~7;
4233 /* FP register restores. */
4236 /* Adjust the register to index off of. */
4237 if (frame_pointer_needed)
4238 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4240 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4242 /* Actually do the restores now. */
4243 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4244 if (regs_ever_live[i]
4245 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4247 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4248 rtx dest = gen_rtx_REG (DFmode, i);
4249 emit_move_insn (dest, src);
4253 /* Emit a blockage insn here to keep these insns from being moved to
4254 an earlier spot in the epilogue, or into the main instruction stream.
4256 This is necessary as we must not cut the stack back before all the
4257 restores are finished. */
4258 emit_insn (gen_blockage ());
4260 /* Reset stack pointer (and possibly frame pointer). The stack
4261 pointer is initially set to fp + 64 to avoid a race condition. */
4262 if (frame_pointer_needed)
4264 rtx delta = GEN_INT (-64);
4266 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4267 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4269 /* If we were deferring a callee register restore, do it now. */
4270 else if (merge_sp_adjust_with_load)
4272 rtx delta = GEN_INT (-actual_fsize);
4273 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4275 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4277 else if (actual_fsize != 0)
4278 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4281 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4282 frame greater than 8k), do so now. */
4284 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4286 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4288 rtx sa = EH_RETURN_STACKADJ_RTX;
4290 emit_insn (gen_blockage ());
4291 emit_insn (TARGET_64BIT
4292 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4293 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4298 hppa_pic_save_rtx (void)
4300 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4304 hppa_profile_hook (int label_no)
4306 /* We use SImode for the address of the function in both 32 and
4307 64-bit code to avoid having to provide DImode versions of the
4308 lcla2 and load_offset_label_address insn patterns. */
4309 rtx reg = gen_reg_rtx (SImode);
4310 rtx label_rtx = gen_label_rtx ();
4311 rtx begin_label_rtx, call_insn;
4312 char begin_label_name[16];
4314 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4316 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4319 emit_move_insn (arg_pointer_rtx,
4320 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4323 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4325 /* The address of the function is loaded into %r25 with a instruction-
4326 relative sequence that avoids the use of relocations. The sequence
4327 is split so that the load_offset_label_address instruction can
4328 occupy the delay slot of the call to _mcount. */
4330 emit_insn (gen_lcla2 (reg, label_rtx));
4332 emit_insn (gen_lcla1 (reg, label_rtx));
4334 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4335 reg, begin_label_rtx, label_rtx));
4337 #ifndef NO_PROFILE_COUNTERS
4339 rtx count_label_rtx, addr, r24;
4340 char count_label_name[16];
4342 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4343 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4345 addr = force_reg (Pmode, count_label_rtx);
4346 r24 = gen_rtx_REG (Pmode, 24);
4347 emit_move_insn (r24, addr);
4350 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4351 gen_rtx_SYMBOL_REF (Pmode,
4353 GEN_INT (TARGET_64BIT ? 24 : 12)));
4355 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4360 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4361 gen_rtx_SYMBOL_REF (Pmode,
4363 GEN_INT (TARGET_64BIT ? 16 : 8)));
4367 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4368 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4370 /* Indicate the _mcount call cannot throw, nor will it execute a
4372 REG_NOTES (call_insn)
4373 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4376 /* Fetch the return address for the frame COUNT steps up from
4377 the current frame, after the prologue. FRAMEADDR is the
4378 frame pointer of the COUNT frame.
4380 We want to ignore any export stub remnants here. To handle this,
4381 we examine the code at the return address, and if it is an export
4382 stub, we return a memory rtx for the stub return address stored
4385 The value returned is used in two different ways:
4387 1. To find a function's caller.
4389 2. To change the return address for a function.
4391 This function handles most instances of case 1; however, it will
4392 fail if there are two levels of stubs to execute on the return
4393 path. The only way I believe that can happen is if the return value
4394 needs a parameter relocation, which never happens for C code.
4396 This function handles most instances of case 2; however, it will
4397 fail if we did not originally have stub code on the return path
4398 but will need stub code on the new return path. This can happen if
4399 the caller & callee are both in the main program, but the new
4400 return location is in a shared library. */
4403 return_addr_rtx (int count, rtx frameaddr)
4413 rp = get_hard_reg_initial_val (Pmode, 2);
4415 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4418 saved_rp = gen_reg_rtx (Pmode);
4419 emit_move_insn (saved_rp, rp);
4421 /* Get pointer to the instruction stream. We have to mask out the
4422 privilege level from the two low order bits of the return address
4423 pointer here so that ins will point to the start of the first
4424 instruction that would have been executed if we returned. */
4425 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4426 label = gen_label_rtx ();
4428 /* Check the instruction stream at the normal return address for the
4431 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4432 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4433 0x00011820 | stub+16: mtsp r1,sr0
4434 0xe0400002 | stub+20: be,n 0(sr0,rp)
4436 If it is an export stub, than our return address is really in
4439 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4440 NULL_RTX, SImode, 1);
4441 emit_jump_insn (gen_bne (label));
4443 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4444 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4445 emit_jump_insn (gen_bne (label));
4447 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4448 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4449 emit_jump_insn (gen_bne (label));
4451 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4452 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4454 /* If there is no export stub then just use the value saved from
4455 the return pointer register. */
4457 emit_jump_insn (gen_bne (label));
4459 /* Here we know that our return address points to an export
4460 stub. We don't want to return the address of the export stub,
4461 but rather the return address of the export stub. That return
4462 address is stored at -24[frameaddr]. */
4464 emit_move_insn (saved_rp,
4466 memory_address (Pmode,
4467 plus_constant (frameaddr,
4474 /* This is only valid once reload has completed because it depends on
4475 knowing exactly how much (if any) frame there is and...
4477 It's only valid if there is no frame marker to de-allocate and...
4479 It's only valid if %r2 hasn't been saved into the caller's frame
4480 (we're not profiling and %r2 isn't live anywhere). */
4482 hppa_can_use_return_insn_p (void)
4484 return (reload_completed
4485 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4486 && ! regs_ever_live[2]
4487 && ! frame_pointer_needed);
4491 emit_bcond_fp (enum rtx_code code, rtx operand0)
4493 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4494 gen_rtx_IF_THEN_ELSE (VOIDmode,
4495 gen_rtx_fmt_ee (code,
4497 gen_rtx_REG (CCFPmode, 0),
4499 gen_rtx_LABEL_REF (VOIDmode, operand0),
4505 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4507 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4508 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4511 /* Adjust the cost of a scheduling dependency. Return the new cost of
4512 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4515 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4517 enum attr_type attr_type;
4519 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4520 true dependencies as they are described with bypasses now. */
4521 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4524 if (! recog_memoized (insn))
4527 attr_type = get_attr_type (insn);
4529 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4531 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4534 if (attr_type == TYPE_FPLOAD)
4536 rtx pat = PATTERN (insn);
4537 rtx dep_pat = PATTERN (dep_insn);
4538 if (GET_CODE (pat) == PARALLEL)
4540 /* This happens for the fldXs,mb patterns. */
4541 pat = XVECEXP (pat, 0, 0);
4543 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4544 /* If this happens, we have to extend this to schedule
4545 optimally. Return 0 for now. */
4548 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4550 if (! recog_memoized (dep_insn))
4552 switch (get_attr_type (dep_insn))
4559 case TYPE_FPSQRTSGL:
4560 case TYPE_FPSQRTDBL:
4561 /* A fpload can't be issued until one cycle before a
4562 preceding arithmetic operation has finished if
4563 the target of the fpload is any of the sources
4564 (or destination) of the arithmetic operation. */
4565 return insn_default_latency (dep_insn) - 1;
4572 else if (attr_type == TYPE_FPALU)
4574 rtx pat = PATTERN (insn);
4575 rtx dep_pat = PATTERN (dep_insn);
4576 if (GET_CODE (pat) == PARALLEL)
4578 /* This happens for the fldXs,mb patterns. */
4579 pat = XVECEXP (pat, 0, 0);
4581 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4582 /* If this happens, we have to extend this to schedule
4583 optimally. Return 0 for now. */
4586 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4588 if (! recog_memoized (dep_insn))
4590 switch (get_attr_type (dep_insn))
4594 case TYPE_FPSQRTSGL:
4595 case TYPE_FPSQRTDBL:
4596 /* An ALU flop can't be issued until two cycles before a
4597 preceding divide or sqrt operation has finished if
4598 the target of the ALU flop is any of the sources
4599 (or destination) of the divide or sqrt operation. */
4600 return insn_default_latency (dep_insn) - 2;
4608 /* For other anti dependencies, the cost is 0. */
4611 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4613 /* Output dependency; DEP_INSN writes a register that INSN writes some
4615 if (attr_type == TYPE_FPLOAD)
4617 rtx pat = PATTERN (insn);
4618 rtx dep_pat = PATTERN (dep_insn);
4619 if (GET_CODE (pat) == PARALLEL)
4621 /* This happens for the fldXs,mb patterns. */
4622 pat = XVECEXP (pat, 0, 0);
4624 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4625 /* If this happens, we have to extend this to schedule
4626 optimally. Return 0 for now. */
4629 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4631 if (! recog_memoized (dep_insn))
4633 switch (get_attr_type (dep_insn))
4640 case TYPE_FPSQRTSGL:
4641 case TYPE_FPSQRTDBL:
4642 /* A fpload can't be issued until one cycle before a
4643 preceding arithmetic operation has finished if
4644 the target of the fpload is the destination of the
4645 arithmetic operation.
4647 Exception: For PA7100LC, PA7200 and PA7300, the cost
4648 is 3 cycles, unless they bundle together. We also
4649 pay the penalty if the second insn is a fpload. */
4650 return insn_default_latency (dep_insn) - 1;
4657 else if (attr_type == TYPE_FPALU)
4659 rtx pat = PATTERN (insn);
4660 rtx dep_pat = PATTERN (dep_insn);
4661 if (GET_CODE (pat) == PARALLEL)
4663 /* This happens for the fldXs,mb patterns. */
4664 pat = XVECEXP (pat, 0, 0);
4666 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4667 /* If this happens, we have to extend this to schedule
4668 optimally. Return 0 for now. */
4671 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4673 if (! recog_memoized (dep_insn))
4675 switch (get_attr_type (dep_insn))
4679 case TYPE_FPSQRTSGL:
4680 case TYPE_FPSQRTDBL:
4681 /* An ALU flop can't be issued until two cycles before a
4682 preceding divide or sqrt operation has finished if
4683 the target of the ALU flop is also the target of
4684 the divide or sqrt operation. */
4685 return insn_default_latency (dep_insn) - 2;
4693 /* For other output dependencies, the cost is 0. */
4700 /* Adjust scheduling priorities. We use this to try and keep addil
4701 and the next use of %r1 close together. */
4703 pa_adjust_priority (rtx insn, int priority)
4705 rtx set = single_set (insn);
4709 src = SET_SRC (set);
4710 dest = SET_DEST (set);
4711 if (GET_CODE (src) == LO_SUM
4712 && symbolic_operand (XEXP (src, 1), VOIDmode)
4713 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4716 else if (GET_CODE (src) == MEM
4717 && GET_CODE (XEXP (src, 0)) == LO_SUM
4718 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4719 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4722 else if (GET_CODE (dest) == MEM
4723 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4724 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4725 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4731 /* The 700 can only issue a single insn at a time.
4732 The 7XXX processors can issue two insns at a time.
4733 The 8000 can issue 4 insns at a time. */
4735 pa_issue_rate (void)
4739 case PROCESSOR_700: return 1;
4740 case PROCESSOR_7100: return 2;
4741 case PROCESSOR_7100LC: return 2;
4742 case PROCESSOR_7200: return 2;
4743 case PROCESSOR_7300: return 2;
4744 case PROCESSOR_8000: return 4;
4753 /* Return any length adjustment needed by INSN which already has its length
4754 computed as LENGTH. Return zero if no adjustment is necessary.
4756 For the PA: function calls, millicode calls, and backwards short
4757 conditional branches with unfilled delay slots need an adjustment by +1
4758 (to account for the NOP which will be inserted into the instruction stream).
4760 Also compute the length of an inline block move here as it is too
4761 complicated to express as a length attribute in pa.md. */
4763 pa_adjust_insn_length (rtx insn, int length)
4765 rtx pat = PATTERN (insn);
4767 /* Jumps inside switch tables which have unfilled delay slots need
4769 if (GET_CODE (insn) == JUMP_INSN
4770 && GET_CODE (pat) == PARALLEL
4771 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4773 /* Millicode insn with an unfilled delay slot. */
4774 else if (GET_CODE (insn) == INSN
4775 && GET_CODE (pat) != SEQUENCE
4776 && GET_CODE (pat) != USE
4777 && GET_CODE (pat) != CLOBBER
4778 && get_attr_type (insn) == TYPE_MILLI)
4780 /* Block move pattern. */
4781 else if (GET_CODE (insn) == INSN
4782 && GET_CODE (pat) == PARALLEL
4783 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4784 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4785 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4786 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4787 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4788 return compute_movstr_length (insn) - 4;
4789 /* Block clear pattern. */
4790 else if (GET_CODE (insn) == INSN
4791 && GET_CODE (pat) == PARALLEL
4792 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4793 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4794 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4795 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4796 return compute_clrstr_length (insn) - 4;
4797 /* Conditional branch with an unfilled delay slot. */
4798 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4800 /* Adjust a short backwards conditional with an unfilled delay slot. */
4801 if (GET_CODE (pat) == SET
4803 && ! forward_branch_p (insn))
4805 else if (GET_CODE (pat) == PARALLEL
4806 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4809 /* Adjust dbra insn with short backwards conditional branch with
4810 unfilled delay slot -- only for case where counter is in a
4811 general register register. */
4812 else if (GET_CODE (pat) == PARALLEL
4813 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4814 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4815 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4817 && ! forward_branch_p (insn))
4825 /* Print operand X (an rtx) in assembler syntax to file FILE.
4826 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4827 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4830 print_operand (FILE *file, rtx x, int code)
4835 /* Output a 'nop' if there's nothing for the delay slot. */
4836 if (dbr_sequence_length () == 0)
4837 fputs ("\n\tnop", file);
4840 /* Output a nullification completer if there's nothing for the */
4841 /* delay slot or nullification is requested. */
4842 if (dbr_sequence_length () == 0 ||
4844 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4848 /* Print out the second register name of a register pair.
4849 I.e., R (6) => 7. */
4850 fputs (reg_names[REGNO (x) + 1], file);
4853 /* A register or zero. */
4855 || (x == CONST0_RTX (DFmode))
4856 || (x == CONST0_RTX (SFmode)))
4858 fputs ("%r0", file);
4864 /* A register or zero (floating point). */
4866 || (x == CONST0_RTX (DFmode))
4867 || (x == CONST0_RTX (SFmode)))
4869 fputs ("%fr0", file);
4878 xoperands[0] = XEXP (XEXP (x, 0), 0);
4879 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4880 output_global_address (file, xoperands[1], 0);
4881 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4885 case 'C': /* Plain (C)ondition */
4887 switch (GET_CODE (x))
4890 fputs ("=", file); break;
4892 fputs ("<>", file); break;
4894 fputs (">", file); break;
4896 fputs (">=", file); break;
4898 fputs (">>=", file); break;
4900 fputs (">>", file); break;
4902 fputs ("<", file); break;
4904 fputs ("<=", file); break;
4906 fputs ("<<=", file); break;
4908 fputs ("<<", file); break;
4913 case 'N': /* Condition, (N)egated */
4914 switch (GET_CODE (x))
4917 fputs ("<>", file); break;
4919 fputs ("=", file); break;
4921 fputs ("<=", file); break;
4923 fputs ("<", file); break;
4925 fputs ("<<", file); break;
4927 fputs ("<<=", file); break;
4929 fputs (">=", file); break;
4931 fputs (">", file); break;
4933 fputs (">>", file); break;
4935 fputs (">>=", file); break;
4940 /* For floating point comparisons. Note that the output
4941 predicates are the complement of the desired mode. */
4943 switch (GET_CODE (x))
4946 fputs ("!=", file); break;
4948 fputs ("=", file); break;
4950 fputs ("!>", file); break;
4952 fputs ("!>=", file); break;
4954 fputs ("!<", file); break;
4956 fputs ("!<=", file); break;
4958 fputs ("!<>", file); break;
4960 fputs (">", file); break;
4962 fputs (">=", file); break;
4964 fputs ("<", file); break;
4966 fputs ("<=", file); break;
4968 fputs ("<>", file); break;
4970 fputs ("<=>", file); break;
4972 fputs ("!<=>", file); break;
4977 case 'S': /* Condition, operands are (S)wapped. */
4978 switch (GET_CODE (x))
4981 fputs ("=", file); break;
4983 fputs ("<>", file); break;
4985 fputs ("<", file); break;
4987 fputs ("<=", file); break;
4989 fputs ("<<=", file); break;
4991 fputs ("<<", file); break;
4993 fputs (">", file); break;
4995 fputs (">=", file); break;
4997 fputs (">>=", file); break;
4999 fputs (">>", file); break;
5004 case 'B': /* Condition, (B)oth swapped and negate. */
5005 switch (GET_CODE (x))
5008 fputs ("<>", file); break;
5010 fputs ("=", file); break;
5012 fputs (">=", file); break;
5014 fputs (">", file); break;
5016 fputs (">>", file); break;
5018 fputs (">>=", file); break;
5020 fputs ("<=", file); break;
5022 fputs ("<", file); break;
5024 fputs ("<<", file); break;
5026 fputs ("<<=", file); break;
5032 if (GET_CODE (x) == CONST_INT)
5034 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5039 if (GET_CODE (x) == CONST_INT)
5041 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5046 if (GET_CODE (x) == CONST_INT)
5048 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5053 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5055 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5060 if (GET_CODE (x) == CONST_INT)
5062 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5067 if (GET_CODE (x) == CONST_INT)
5069 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5074 if (GET_CODE (x) == CONST_INT)
5079 switch (GET_CODE (XEXP (x, 0)))
5083 if (ASSEMBLER_DIALECT == 0)
5084 fputs ("s,mb", file);
5086 fputs (",mb", file);
5090 if (ASSEMBLER_DIALECT == 0)
5091 fputs ("s,ma", file);
5093 fputs (",ma", file);
5096 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5097 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5099 if (ASSEMBLER_DIALECT == 0)
5102 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5103 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5105 if (ASSEMBLER_DIALECT == 0)
5106 fputs ("x,s", file);
5110 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5114 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5120 output_global_address (file, x, 0);
5123 output_global_address (file, x, 1);
5125 case 0: /* Don't do anything special */
5130 compute_zdepwi_operands (INTVAL (x), op);
5131 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5137 compute_zdepdi_operands (INTVAL (x), op);
5138 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5142 /* We can get here from a .vtable_inherit due to our
5143 CONSTANT_ADDRESS_P rejecting perfectly good constant
5149 if (GET_CODE (x) == REG)
5151 fputs (reg_names [REGNO (x)], file);
5152 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5158 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5159 && (REGNO (x) & 1) == 0)
5162 else if (GET_CODE (x) == MEM)
5164 int size = GET_MODE_SIZE (GET_MODE (x));
5165 rtx base = NULL_RTX;
5166 switch (GET_CODE (XEXP (x, 0)))
5170 base = XEXP (XEXP (x, 0), 0);
5171 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5175 base = XEXP (XEXP (x, 0), 0);
5176 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5179 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5180 fprintf (file, "%s(%s)",
5181 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5182 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5183 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5184 fprintf (file, "%s(%s)",
5185 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5186 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5187 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5188 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5190 /* Because the REG_POINTER flag can get lost during reload,
5191 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5192 index and base registers in the combined move patterns. */
5193 rtx base = XEXP (XEXP (x, 0), 1);
5194 rtx index = XEXP (XEXP (x, 0), 0);
5196 fprintf (file, "%s(%s)",
5197 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5200 output_address (XEXP (x, 0));
5203 output_address (XEXP (x, 0));
5208 output_addr_const (file, x);
5211 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5214 output_global_address (FILE *file, rtx x, int round_constant)
5217 /* Imagine (high (const (plus ...))). */
5218 if (GET_CODE (x) == HIGH)
5221 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5222 assemble_name (file, XSTR (x, 0));
5223 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5225 assemble_name (file, XSTR (x, 0));
5226 fputs ("-$global$", file);
5228 else if (GET_CODE (x) == CONST)
5230 const char *sep = "";
5231 int offset = 0; /* assembler wants -$global$ at end */
5232 rtx base = NULL_RTX;
5234 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5236 base = XEXP (XEXP (x, 0), 0);
5237 output_addr_const (file, base);
5239 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5240 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5243 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5245 base = XEXP (XEXP (x, 0), 1);
5246 output_addr_const (file, base);
5248 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5249 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5252 /* How bogus. The compiler is apparently responsible for
5253 rounding the constant if it uses an LR field selector.
5255 The linker and/or assembler seem a better place since
5256 they have to do this kind of thing already.
5258 If we fail to do this, HP's optimizing linker may eliminate
5259 an addil, but not update the ldw/stw/ldo instruction that
5260 uses the result of the addil. */
5262 offset = ((offset + 0x1000) & ~0x1fff);
5264 if (GET_CODE (XEXP (x, 0)) == PLUS)
5274 else if (GET_CODE (XEXP (x, 0)) == MINUS
5275 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5279 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5280 fputs ("-$global$", file);
5282 fprintf (file, "%s%d", sep, offset);
5285 output_addr_const (file, x);
5288 /* Output boilerplate text to appear at the beginning of the file.
5289 There are several possible versions. */
5290 #define aputs(x) fputs(x, asm_out_file)
5292 pa_file_start_level (void)
5295 aputs ("\t.LEVEL 2.0w\n");
5296 else if (TARGET_PA_20)
5297 aputs ("\t.LEVEL 2.0\n");
5298 else if (TARGET_PA_11)
5299 aputs ("\t.LEVEL 1.1\n");
5301 aputs ("\t.LEVEL 1.0\n");
5305 pa_file_start_space (int sortspace)
5307 aputs ("\t.SPACE $PRIVATE$");
5310 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5311 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5312 "\n\t.SPACE $TEXT$");
5315 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5316 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5320 pa_file_start_file (int want_version)
5322 if (write_symbols != NO_DEBUG)
5324 output_file_directive (asm_out_file, main_input_filename);
5326 aputs ("\t.version\t\"01.01\"\n");
5331 pa_file_start_mcount (const char *aswhat)
5334 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5338 pa_elf_file_start (void)
5340 pa_file_start_level ();
5341 pa_file_start_mcount ("ENTRY");
5342 pa_file_start_file (0);
5346 pa_som_file_start (void)
5348 pa_file_start_level ();
5349 pa_file_start_space (0);
5350 aputs ("\t.IMPORT $global$,DATA\n"
5351 "\t.IMPORT $$dyncall,MILLICODE\n");
5352 pa_file_start_mcount ("CODE");
5353 pa_file_start_file (0);
5357 pa_linux_file_start (void)
5359 pa_file_start_file (1);
5360 pa_file_start_level ();
5361 pa_file_start_mcount ("CODE");
5365 pa_hpux64_gas_file_start (void)
5367 pa_file_start_level ();
5368 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5370 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5372 pa_file_start_file (1);
5376 pa_hpux64_hpas_file_start (void)
5378 pa_file_start_level ();
5379 pa_file_start_space (1);
5380 pa_file_start_mcount ("CODE");
5381 pa_file_start_file (0);
5385 static struct deferred_plabel *
5386 get_plabel (const char *fname)
5390 /* See if we have already put this function on the list of deferred
5391 plabels. This list is generally small, so a liner search is not
5392 too ugly. If it proves too slow replace it with something faster. */
5393 for (i = 0; i < n_deferred_plabels; i++)
5394 if (strcmp (fname, deferred_plabels[i].name) == 0)
5397 /* If the deferred plabel list is empty, or this entry was not found
5398 on the list, create a new entry on the list. */
5399 if (deferred_plabels == NULL || i == n_deferred_plabels)
5401 const char *real_name;
5403 if (deferred_plabels == 0)
5404 deferred_plabels = (struct deferred_plabel *)
5405 ggc_alloc (sizeof (struct deferred_plabel));
5407 deferred_plabels = (struct deferred_plabel *)
5408 ggc_realloc (deferred_plabels,
5409 ((n_deferred_plabels + 1)
5410 * sizeof (struct deferred_plabel)));
5412 i = n_deferred_plabels++;
5413 deferred_plabels[i].internal_label = gen_label_rtx ();
5414 deferred_plabels[i].name = ggc_strdup (fname);
5416 /* Gross. We have just implicitly taken the address of this function,
5418 real_name = (*targetm.strip_name_encoding) (fname);
5419 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5422 return &deferred_plabels[i];
5426 output_deferred_plabels (void)
5429 /* If we have deferred plabels, then we need to switch into the data
5430 section and align it to a 4 byte boundary before we output the
5431 deferred plabels. */
5432 if (n_deferred_plabels)
5435 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5438 /* Now output the deferred plabels. */
5439 for (i = 0; i < n_deferred_plabels; i++)
5441 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5442 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5443 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5444 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5448 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5449 /* Initialize optabs to point to HPUX long double emulation routines. */
5451 pa_hpux_init_libfuncs (void)
5453 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5454 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5455 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5456 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5457 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5458 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5459 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5460 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5461 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5463 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5464 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5465 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5466 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5467 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5468 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5470 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5471 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5472 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5473 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5475 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5476 ? "__U_Qfcnvfxt_quad_to_sgl"
5477 : "_U_Qfcnvfxt_quad_to_sgl");
5478 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5479 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5480 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5482 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5483 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5487 /* HP's millicode routines mean something special to the assembler.
5488 Keep track of which ones we have used. */
5490 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5491 static void import_milli (enum millicodes);
5492 static char imported[(int) end1000];
5493 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5494 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5495 #define MILLI_START 10
5498 import_milli (enum millicodes code)
5500 char str[sizeof (import_string)];
5502 if (!imported[(int) code])
5504 imported[(int) code] = 1;
5505 strcpy (str, import_string);
5506 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5507 output_asm_insn (str, 0);
5511 /* The register constraints have put the operands and return value in
5512 the proper registers. */
5515 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5517 import_milli (mulI);
5518 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5521 /* Emit the rtl for doing a division by a constant. */
5523 /* Do magic division millicodes exist for this value? */
5524 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5527 /* We'll use an array to keep track of the magic millicodes and
5528 whether or not we've used them already. [n][0] is signed, [n][1] is
5531 static int div_milli[16][2];
5534 div_operand (rtx op, enum machine_mode mode)
5536 return (mode == SImode
5537 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5538 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5539 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5543 emit_hpdiv_const (rtx *operands, int unsignedp)
5545 if (GET_CODE (operands[2]) == CONST_INT
5546 && INTVAL (operands[2]) > 0
5547 && INTVAL (operands[2]) < 16
5548 && magic_milli[INTVAL (operands[2])])
5550 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5552 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5555 (PARALLEL, VOIDmode,
5556 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5557 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5559 gen_rtx_REG (SImode, 26),
5561 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5562 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5563 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5564 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5565 gen_rtx_CLOBBER (VOIDmode, ret))));
5566 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5573 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5577 /* If the divisor is a constant, try to use one of the special
5579 if (GET_CODE (operands[0]) == CONST_INT)
5581 static char buf[100];
5582 divisor = INTVAL (operands[0]);
5583 if (!div_milli[divisor][unsignedp])
5585 div_milli[divisor][unsignedp] = 1;
5587 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5589 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5593 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5594 INTVAL (operands[0]));
5595 return output_millicode_call (insn,
5596 gen_rtx_SYMBOL_REF (SImode, buf));
5600 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5601 INTVAL (operands[0]));
5602 return output_millicode_call (insn,
5603 gen_rtx_SYMBOL_REF (SImode, buf));
5606 /* Divisor isn't a special constant. */
5611 import_milli (divU);
5612 return output_millicode_call (insn,
5613 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5617 import_milli (divI);
5618 return output_millicode_call (insn,
5619 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5624 /* Output a $$rem millicode to do mod. */
5627 output_mod_insn (int unsignedp, rtx insn)
5631 import_milli (remU);
5632 return output_millicode_call (insn,
5633 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5637 import_milli (remI);
5638 return output_millicode_call (insn,
5639 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5644 output_arg_descriptor (rtx call_insn)
5646 const char *arg_regs[4];
5647 enum machine_mode arg_mode;
5649 int i, output_flag = 0;
5652 /* We neither need nor want argument location descriptors for the
5653 64bit runtime environment or the ELF32 environment. */
5654 if (TARGET_64BIT || TARGET_ELF32)
5657 for (i = 0; i < 4; i++)
5660 /* Specify explicitly that no argument relocations should take place
5661 if using the portable runtime calling conventions. */
5662 if (TARGET_PORTABLE_RUNTIME)
5664 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5669 if (GET_CODE (call_insn) != CALL_INSN)
5671 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5673 rtx use = XEXP (link, 0);
5675 if (! (GET_CODE (use) == USE
5676 && GET_CODE (XEXP (use, 0)) == REG
5677 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5680 arg_mode = GET_MODE (XEXP (use, 0));
5681 regno = REGNO (XEXP (use, 0));
5682 if (regno >= 23 && regno <= 26)
5684 arg_regs[26 - regno] = "GR";
5685 if (arg_mode == DImode)
5686 arg_regs[25 - regno] = "GR";
5688 else if (regno >= 32 && regno <= 39)
5690 if (arg_mode == SFmode)
5691 arg_regs[(regno - 32) / 2] = "FR";
5694 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5695 arg_regs[(regno - 34) / 2] = "FR";
5696 arg_regs[(regno - 34) / 2 + 1] = "FU";
5698 arg_regs[(regno - 34) / 2] = "FU";
5699 arg_regs[(regno - 34) / 2 + 1] = "FR";
5704 fputs ("\t.CALL ", asm_out_file);
5705 for (i = 0; i < 4; i++)
5710 fputc (',', asm_out_file);
5711 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5714 fputc ('\n', asm_out_file);
5717 /* Return the class of any secondary reload register that is needed to
5718 move IN into a register in class CLASS using mode MODE.
5720 Profiling has showed this routine and its descendants account for
5721 a significant amount of compile time (~7%). So it has been
5722 optimized to reduce redundant computations and eliminate useless
5725 It might be worthwhile to try and make this a leaf function too. */
5728 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5730 int regno, is_symbolic;
5732 /* Trying to load a constant into a FP register during PIC code
5733 generation will require %r1 as a scratch register. */
5735 && GET_MODE_CLASS (mode) == MODE_INT
5736 && FP_REG_CLASS_P (class)
5737 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5740 /* Profiling showed the PA port spends about 1.3% of its compilation
5741 time in true_regnum from calls inside secondary_reload_class. */
5743 if (GET_CODE (in) == REG)
5746 if (regno >= FIRST_PSEUDO_REGISTER)
5747 regno = true_regnum (in);
5749 else if (GET_CODE (in) == SUBREG)
5750 regno = true_regnum (in);
5754 /* If we have something like (mem (mem (...)), we can safely assume the
5755 inner MEM will end up in a general register after reloading, so there's
5756 no need for a secondary reload. */
5757 if (GET_CODE (in) == MEM
5758 && GET_CODE (XEXP (in, 0)) == MEM)
5761 /* Handle out of range displacement for integer mode loads/stores of
5763 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5764 && GET_MODE_CLASS (mode) == MODE_INT
5765 && FP_REG_CLASS_P (class))
5766 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5767 return GENERAL_REGS;
5769 /* A SAR<->FP register copy requires a secondary register (GPR) as
5770 well as secondary memory. */
5771 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5772 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5773 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5774 return GENERAL_REGS;
5776 if (GET_CODE (in) == HIGH)
5779 /* Profiling has showed GCC spends about 2.6% of its compilation
5780 time in symbolic_operand from calls inside secondary_reload_class.
5782 We use an inline copy and only compute its return value once to avoid
5784 switch (GET_CODE (in))
5794 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5795 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5796 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5806 && read_only_operand (in, VOIDmode))
5809 if (class != R1_REGS && is_symbolic)
5816 function_arg_padding (enum machine_mode mode, tree type)
5819 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5821 /* Return none if justification is not required. */
5823 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5824 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5827 /* The directions set here are ignored when a BLKmode argument larger
5828 than a word is placed in a register. Different code is used for
5829 the stack and registers. This makes it difficult to have a
5830 consistent data representation for both the stack and registers.
5831 For both runtimes, the justification and padding for arguments on
5832 the stack and in registers should be identical. */
5834 /* The 64-bit runtime specifies left justification for aggregates. */
5837 /* The 32-bit runtime architecture specifies right justification.
5838 When the argument is passed on the stack, the argument is padded
5839 with garbage on the left. The HP compiler pads with zeros. */
5843 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5850 /* Do what is necessary for `va_start'. We look at the current function
5851 to determine if stdargs or varargs is used and fill in an initial
5852 va_list. A pointer to this constructor is returned. */
5855 hppa_builtin_saveregs (void)
5858 tree fntype = TREE_TYPE (current_function_decl);
5859 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5860 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5861 != void_type_node)))
5862 ? UNITS_PER_WORD : 0);
5865 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5867 offset = current_function_arg_offset_rtx;
5873 /* Adjust for varargs/stdarg differences. */
5875 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5877 offset = current_function_arg_offset_rtx;
5879 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5880 from the incoming arg pointer and growing to larger addresses. */
5881 for (i = 26, off = -64; i >= 19; i--, off += 8)
5882 emit_move_insn (gen_rtx_MEM (word_mode,
5883 plus_constant (arg_pointer_rtx, off)),
5884 gen_rtx_REG (word_mode, i));
5886 /* The incoming args pointer points just beyond the flushback area;
5887 normally this is not a serious concern. However, when we are doing
5888 varargs/stdargs we want to make the arg pointer point to the start
5889 of the incoming argument area. */
5890 emit_move_insn (virtual_incoming_args_rtx,
5891 plus_constant (arg_pointer_rtx, -64));
5893 /* Now return a pointer to the first anonymous argument. */
5894 return copy_to_reg (expand_binop (Pmode, add_optab,
5895 virtual_incoming_args_rtx,
5896 offset, 0, 0, OPTAB_LIB_WIDEN));
5899 /* Store general registers on the stack. */
5900 dest = gen_rtx_MEM (BLKmode,
5901 plus_constant (current_function_internal_arg_pointer,
5903 set_mem_alias_set (dest, get_varargs_alias_set ());
5904 set_mem_align (dest, BITS_PER_WORD);
5905 move_block_from_reg (23, dest, 4);
5907 /* move_block_from_reg will emit code to store the argument registers
5908 individually as scalar stores.
5910 However, other insns may later load from the same addresses for
5911 a structure load (passing a struct to a varargs routine).
5913 The alias code assumes that such aliasing can never happen, so we
5914 have to keep memory referencing insns from moving up beyond the
5915 last argument register store. So we emit a blockage insn here. */
5916 emit_insn (gen_blockage ());
5918 return copy_to_reg (expand_binop (Pmode, add_optab,
5919 current_function_internal_arg_pointer,
5920 offset, 0, 0, OPTAB_LIB_WIDEN));
5924 hppa_va_start (tree valist, rtx nextarg)
5926 nextarg = expand_builtin_saveregs ();
5927 std_expand_builtin_va_start (valist, nextarg);
5931 hppa_va_arg (tree valist, tree type)
5933 HOST_WIDE_INT size = int_size_in_bytes (type);
5939 /* Every argument in PA64 is supposed to be passed by value
5940 (including large structs). However, as a GCC extension, we
5941 pass zero and variable sized arguments by reference. Empty
5942 structures are a GCC extension not supported by the HP
5943 compilers. Thus, passing them by reference isn't likely
5944 to conflict with the ABI. For variable sized arguments,
5945 GCC doesn't have the infrastructure to allocate these to
5948 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5950 if (size > UNITS_PER_WORD)
5952 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5953 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5954 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5955 build_int_2 (-2 * UNITS_PER_WORD, -1));
5956 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5957 TREE_SIDE_EFFECTS (t) = 1;
5958 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5962 return std_expand_builtin_va_arg (valist, type);
5965 ptr = build_pointer_type (type);
5967 /* Args grow upward. */
5968 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5969 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5970 TREE_SIDE_EFFECTS (t) = 1;
5972 pptr = build_pointer_type (ptr);
5973 t = build1 (NOP_EXPR, pptr, t);
5974 TREE_SIDE_EFFECTS (t) = 1;
5976 t = build1 (INDIRECT_REF, ptr, t);
5977 TREE_SIDE_EFFECTS (t) = 1;
5980 else /* !TARGET_64BIT */
5982 ptr = build_pointer_type (type);
5984 /* "Large" and variable sized types are passed by reference. */
5985 if (size > 8 || size <= 0)
5987 /* Args grow downward. */
5988 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5989 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5990 TREE_SIDE_EFFECTS (t) = 1;
5992 pptr = build_pointer_type (ptr);
5993 t = build1 (NOP_EXPR, pptr, t);
5994 TREE_SIDE_EFFECTS (t) = 1;
5996 t = build1 (INDIRECT_REF, ptr, t);
5997 TREE_SIDE_EFFECTS (t) = 1;
6001 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
6002 build_int_2 (-size, -1));
6004 /* Copied from va-pa.h, but we probably don't need to align to
6005 word size, since we generate and preserve that invariant. */
6006 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
6007 build_int_2 ((size > 4 ? -8 : -4), -1));
6009 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6010 TREE_SIDE_EFFECTS (t) = 1;
6012 ofs = (8 - size) % 4;
6015 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
6016 build_int_2 (ofs, 0));
6017 TREE_SIDE_EFFECTS (t) = 1;
6020 t = build1 (NOP_EXPR, ptr, t);
6021 TREE_SIDE_EFFECTS (t) = 1;
6026 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
6031 /* This routine handles all the normal conditional branch sequences we
6032 might need to generate. It handles compare immediate vs compare
6033 register, nullification of delay slots, varying length branches,
6034 negated branches, and all combinations of the above. It returns the
6035 output appropriate to emit the branch corresponding to all given
6039 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6041 static char buf[100];
6045 /* A conditional branch to the following instruction (eg the delay slot)
6046 is asking for a disaster. This can happen when not optimizing and
6047 when jump optimization fails.
6049 While it is usually safe to emit nothing, this can fail if the
6050 preceding instruction is a nullified branch with an empty delay
6051 slot and the same branch target as this branch. We could check
6052 for this but jump optimization should eliminate nop jumps. It
6053 is always safe to emit a nop. */
6054 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6057 /* The doubleword form of the cmpib instruction doesn't have the LEU
6058 and GTU conditions while the cmpb instruction does. Since we accept
6059 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6060 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6061 operands[2] = gen_rtx_REG (DImode, 0);
6063 /* If this is a long branch with its delay slot unfilled, set `nullify'
6064 as it can nullify the delay slot and save a nop. */
6065 if (length == 8 && dbr_sequence_length () == 0)
6068 /* If this is a short forward conditional branch which did not get
6069 its delay slot filled, the delay slot can still be nullified. */
6070 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6071 nullify = forward_branch_p (insn);
6073 /* A forward branch over a single nullified insn can be done with a
6074 comclr instruction. This avoids a single cycle penalty due to
6075 mis-predicted branch if we fall through (branch not taken). */
6077 && next_real_insn (insn) != 0
6078 && get_attr_length (next_real_insn (insn)) == 4
6079 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6085 /* All short conditional branches except backwards with an unfilled
6089 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6091 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6092 if (GET_MODE (operands[1]) == DImode)
6095 strcat (buf, "%B3");
6097 strcat (buf, "%S3");
6099 strcat (buf, " %2,%r1,%%r0");
6101 strcat (buf, ",n %2,%r1,%0");
6103 strcat (buf, " %2,%r1,%0");
6106 /* All long conditionals. Note a short backward branch with an
6107 unfilled delay slot is treated just like a long backward branch
6108 with an unfilled delay slot. */
6110 /* Handle weird backwards branch with a filled delay slot
6111 with is nullified. */
6112 if (dbr_sequence_length () != 0
6113 && ! forward_branch_p (insn)
6116 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6117 if (GET_MODE (operands[1]) == DImode)
6120 strcat (buf, "%S3");
6122 strcat (buf, "%B3");
6123 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6125 /* Handle short backwards branch with an unfilled delay slot.
6126 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6127 taken and untaken branches. */
6128 else if (dbr_sequence_length () == 0
6129 && ! forward_branch_p (insn)
6130 && INSN_ADDRESSES_SET_P ()
6131 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6132 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6134 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6135 if (GET_MODE (operands[1]) == DImode)
6138 strcat (buf, "%B3 %2,%r1,%0%#");
6140 strcat (buf, "%S3 %2,%r1,%0%#");
6144 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6145 if (GET_MODE (operands[1]) == DImode)
6148 strcat (buf, "%S3");
6150 strcat (buf, "%B3");
6152 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6154 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6160 xoperands[0] = operands[0];
6161 xoperands[1] = operands[1];
6162 xoperands[2] = operands[2];
6163 xoperands[3] = operands[3];
6165 /* The reversed conditional branch must branch over one additional
6166 instruction if the delay slot is filled. If the delay slot
6167 is empty, the instruction after the reversed condition branch
6168 must be nullified. */
6169 nullify = dbr_sequence_length () == 0;
6170 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6172 /* Create a reversed conditional branch which branches around
6173 the following insns. */
6174 if (GET_MODE (operands[1]) != DImode)
6180 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6183 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6189 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6192 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6201 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6204 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6210 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6213 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6217 output_asm_insn (buf, xoperands);
6218 return output_lbranch (operands[0], insn);
6226 /* This routine handles long unconditional branches that exceed the
6227 maximum range of a simple branch instruction. */
6230 output_lbranch (rtx dest, rtx insn)
6234 xoperands[0] = dest;
6236 /* First, free up the delay slot. */
6237 if (dbr_sequence_length () != 0)
6239 /* We can't handle a jump in the delay slot. */
6240 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6243 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6244 optimize, 0, 0, NULL);
6246 /* Now delete the delay insn. */
6247 PUT_CODE (NEXT_INSN (insn), NOTE);
6248 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6249 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6252 /* Output an insn to save %r1. The runtime documentation doesn't
6253 specify whether the "Clean Up" slot in the callers frame can
6254 be clobbered by the callee. It isn't copied by HP's builtin
6255 alloca, so this suggests that it can be clobbered if necessary.
6256 The "Static Link" location is copied by HP builtin alloca, so
6257 we avoid using it. Using the cleanup slot might be a problem
6258 if we have to interoperate with languages that pass cleanup
6259 information. However, it should be possible to handle these
6260 situations with GCC's asm feature.
6262 The "Current RP" slot is reserved for the called procedure, so
6263 we try to use it when we don't have a frame of our own. It's
6264 rather unlikely that we won't have a frame when we need to emit
6267 Really the way to go long term is a register scavenger; goto
6268 the target of the jump and find a register which we can use
6269 as a scratch to hold the value in %r1. Then, we wouldn't have
6270 to free up the delay slot or clobber a slot that may be needed
6271 for other purposes. */
6274 if (actual_fsize == 0 && !regs_ever_live[2])
6275 /* Use the return pointer slot in the frame marker. */
6276 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6278 /* Use the slot at -40 in the frame marker since HP builtin
6279 alloca doesn't copy it. */
6280 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6284 if (actual_fsize == 0 && !regs_ever_live[2])
6285 /* Use the return pointer slot in the frame marker. */
6286 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6288 /* Use the "Clean Up" slot in the frame marker. In GCC,
6289 the only other use of this location is for copying a
6290 floating point double argument from a floating-point
6291 register to two general registers. The copy is done
6292 as an "atomic" operation when outputting a call, so it
6293 won't interfere with our using the location here. */
6294 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6297 if (TARGET_PORTABLE_RUNTIME)
6299 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6300 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6301 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6305 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6306 if (TARGET_SOM || !TARGET_GAS)
6308 xoperands[1] = gen_label_rtx ();
6309 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6310 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6311 CODE_LABEL_NUMBER (xoperands[1]));
6312 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6316 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6317 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6319 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6322 /* Now output a very long branch to the original target. */
6323 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6325 /* Now restore the value of %r1 in the delay slot. */
6328 if (actual_fsize == 0 && !regs_ever_live[2])
6329 return "ldd -16(%%r30),%%r1";
6331 return "ldd -40(%%r30),%%r1";
6335 if (actual_fsize == 0 && !regs_ever_live[2])
6336 return "ldw -20(%%r30),%%r1";
6338 return "ldw -12(%%r30),%%r1";
6342 /* This routine handles all the branch-on-bit conditional branch sequences we
6343 might need to generate. It handles nullification of delay slots,
6344 varying length branches, negated branches and all combinations of the
6345 above. it returns the appropriate output template to emit the branch. */
6348 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6349 int negated, rtx insn, int which)
6351 static char buf[100];
6354 /* A conditional branch to the following instruction (eg the delay slot) is
6355 asking for a disaster. I do not think this can happen as this pattern
6356 is only used when optimizing; jump optimization should eliminate the
6357 jump. But be prepared just in case. */
6359 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6362 /* If this is a long branch with its delay slot unfilled, set `nullify'
6363 as it can nullify the delay slot and save a nop. */
6364 if (length == 8 && dbr_sequence_length () == 0)
6367 /* If this is a short forward conditional branch which did not get
6368 its delay slot filled, the delay slot can still be nullified. */
6369 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6370 nullify = forward_branch_p (insn);
6372 /* A forward branch over a single nullified insn can be done with a
6373 extrs instruction. This avoids a single cycle penalty due to
6374 mis-predicted branch if we fall through (branch not taken). */
6377 && next_real_insn (insn) != 0
6378 && get_attr_length (next_real_insn (insn)) == 4
6379 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6386 /* All short conditional branches except backwards with an unfilled
6390 strcpy (buf, "{extrs,|extrw,s,}");
6392 strcpy (buf, "bb,");
6393 if (useskip && GET_MODE (operands[0]) == DImode)
6394 strcpy (buf, "extrd,s,*");
6395 else if (GET_MODE (operands[0]) == DImode)
6396 strcpy (buf, "bb,*");
6397 if ((which == 0 && negated)
6398 || (which == 1 && ! negated))
6403 strcat (buf, " %0,%1,1,%%r0");
6404 else if (nullify && negated)
6405 strcat (buf, ",n %0,%1,%3");
6406 else if (nullify && ! negated)
6407 strcat (buf, ",n %0,%1,%2");
6408 else if (! nullify && negated)
6409 strcat (buf, "%0,%1,%3");
6410 else if (! nullify && ! negated)
6411 strcat (buf, " %0,%1,%2");
6414 /* All long conditionals. Note a short backward branch with an
6415 unfilled delay slot is treated just like a long backward branch
6416 with an unfilled delay slot. */
6418 /* Handle weird backwards branch with a filled delay slot
6419 with is nullified. */
6420 if (dbr_sequence_length () != 0
6421 && ! forward_branch_p (insn)
6424 strcpy (buf, "bb,");
6425 if (GET_MODE (operands[0]) == DImode)
6427 if ((which == 0 && negated)
6428 || (which == 1 && ! negated))
6433 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6435 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6437 /* Handle short backwards branch with an unfilled delay slot.
6438 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6439 taken and untaken branches. */
6440 else if (dbr_sequence_length () == 0
6441 && ! forward_branch_p (insn)
6442 && INSN_ADDRESSES_SET_P ()
6443 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6444 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6446 strcpy (buf, "bb,");
6447 if (GET_MODE (operands[0]) == DImode)
6449 if ((which == 0 && negated)
6450 || (which == 1 && ! negated))
6455 strcat (buf, " %0,%1,%3%#");
6457 strcat (buf, " %0,%1,%2%#");
6461 strcpy (buf, "{extrs,|extrw,s,}");
6462 if (GET_MODE (operands[0]) == DImode)
6463 strcpy (buf, "extrd,s,*");
6464 if ((which == 0 && negated)
6465 || (which == 1 && ! negated))
6469 if (nullify && negated)
6470 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6471 else if (nullify && ! negated)
6472 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6474 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6476 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6486 /* This routine handles all the branch-on-variable-bit conditional branch
6487 sequences we might need to generate. It handles nullification of delay
6488 slots, varying length branches, negated branches and all combinations
6489 of the above. it returns the appropriate output template to emit the
6493 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6494 int negated, rtx insn, int which)
6496 static char buf[100];
6499 /* A conditional branch to the following instruction (eg the delay slot) is
6500 asking for a disaster. I do not think this can happen as this pattern
6501 is only used when optimizing; jump optimization should eliminate the
6502 jump. But be prepared just in case. */
6504 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6507 /* If this is a long branch with its delay slot unfilled, set `nullify'
6508 as it can nullify the delay slot and save a nop. */
6509 if (length == 8 && dbr_sequence_length () == 0)
6512 /* If this is a short forward conditional branch which did not get
6513 its delay slot filled, the delay slot can still be nullified. */
6514 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6515 nullify = forward_branch_p (insn);
6517 /* A forward branch over a single nullified insn can be done with a
6518 extrs instruction. This avoids a single cycle penalty due to
6519 mis-predicted branch if we fall through (branch not taken). */
6522 && next_real_insn (insn) != 0
6523 && get_attr_length (next_real_insn (insn)) == 4
6524 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6531 /* All short conditional branches except backwards with an unfilled
6535 strcpy (buf, "{vextrs,|extrw,s,}");
6537 strcpy (buf, "{bvb,|bb,}");
6538 if (useskip && GET_MODE (operands[0]) == DImode)
6539 strcpy (buf, "extrd,s,*");
6540 else if (GET_MODE (operands[0]) == DImode)
6541 strcpy (buf, "bb,*");
6542 if ((which == 0 && negated)
6543 || (which == 1 && ! negated))
6548 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6549 else if (nullify && negated)
6550 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6551 else if (nullify && ! negated)
6552 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6553 else if (! nullify && negated)
6554 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6555 else if (! nullify && ! negated)
6556 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6559 /* All long conditionals. Note a short backward branch with an
6560 unfilled delay slot is treated just like a long backward branch
6561 with an unfilled delay slot. */
6563 /* Handle weird backwards branch with a filled delay slot
6564 with is nullified. */
6565 if (dbr_sequence_length () != 0
6566 && ! forward_branch_p (insn)
6569 strcpy (buf, "{bvb,|bb,}");
6570 if (GET_MODE (operands[0]) == DImode)
6572 if ((which == 0 && negated)
6573 || (which == 1 && ! negated))
6578 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6580 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6582 /* Handle short backwards branch with an unfilled delay slot.
6583 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6584 taken and untaken branches. */
6585 else if (dbr_sequence_length () == 0
6586 && ! forward_branch_p (insn)
6587 && INSN_ADDRESSES_SET_P ()
6588 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6589 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6591 strcpy (buf, "{bvb,|bb,}");
6592 if (GET_MODE (operands[0]) == DImode)
6594 if ((which == 0 && negated)
6595 || (which == 1 && ! negated))
6600 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6602 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6606 strcpy (buf, "{vextrs,|extrw,s,}");
6607 if (GET_MODE (operands[0]) == DImode)
6608 strcpy (buf, "extrd,s,*");
6609 if ((which == 0 && negated)
6610 || (which == 1 && ! negated))
6614 if (nullify && negated)
6615 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6616 else if (nullify && ! negated)
6617 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6619 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6621 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6631 /* Return the output template for emitting a dbra type insn.
6633 Note it may perform some output operations on its own before
6634 returning the final output string. */
6636 output_dbra (rtx *operands, rtx insn, int which_alternative)
6639 /* A conditional branch to the following instruction (eg the delay slot) is
6640 asking for a disaster. Be prepared! */
6642 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6644 if (which_alternative == 0)
6645 return "ldo %1(%0),%0";
6646 else if (which_alternative == 1)
6648 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6649 output_asm_insn ("ldw -16(%%r30),%4", operands);
6650 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6651 return "{fldws|fldw} -16(%%r30),%0";
6655 output_asm_insn ("ldw %0,%4", operands);
6656 return "ldo %1(%4),%4\n\tstw %4,%0";
6660 if (which_alternative == 0)
6662 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6663 int length = get_attr_length (insn);
6665 /* If this is a long branch with its delay slot unfilled, set `nullify'
6666 as it can nullify the delay slot and save a nop. */
6667 if (length == 8 && dbr_sequence_length () == 0)
6670 /* If this is a short forward conditional branch which did not get
6671 its delay slot filled, the delay slot can still be nullified. */
6672 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6673 nullify = forward_branch_p (insn);
6675 /* Handle short versions first. */
6676 if (length == 4 && nullify)
6677 return "addib,%C2,n %1,%0,%3";
6678 else if (length == 4 && ! nullify)
6679 return "addib,%C2 %1,%0,%3";
6680 else if (length == 8)
6682 /* Handle weird backwards branch with a fulled delay slot
6683 which is nullified. */
6684 if (dbr_sequence_length () != 0
6685 && ! forward_branch_p (insn)
6687 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6688 /* Handle short backwards branch with an unfilled delay slot.
6689 Using a addb;nop rather than addi;bl saves 1 cycle for both
6690 taken and untaken branches. */
6691 else if (dbr_sequence_length () == 0
6692 && ! forward_branch_p (insn)
6693 && INSN_ADDRESSES_SET_P ()
6694 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6695 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6696 return "addib,%C2 %1,%0,%3%#";
6698 /* Handle normal cases. */
6700 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6702 return "addi,%N2 %1,%0,%0\n\tb %3";
6707 /* Deal with gross reload from FP register case. */
6708 else if (which_alternative == 1)
6710 /* Move loop counter from FP register to MEM then into a GR,
6711 increment the GR, store the GR into MEM, and finally reload
6712 the FP register from MEM from within the branch's delay slot. */
6713 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6715 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6716 if (get_attr_length (insn) == 24)
6717 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6719 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6721 /* Deal with gross reload from memory case. */
6724 /* Reload loop counter from memory, the store back to memory
6725 happens in the branch's delay slot. */
6726 output_asm_insn ("ldw %0,%4", operands);
6727 if (get_attr_length (insn) == 12)
6728 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6730 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6734 /* Return the output template for emitting a dbra type insn.
6736 Note it may perform some output operations on its own before
6737 returning the final output string. */
6739 output_movb (rtx *operands, rtx insn, int which_alternative,
6740 int reverse_comparison)
6743 /* A conditional branch to the following instruction (eg the delay slot) is
6744 asking for a disaster. Be prepared! */
6746 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6748 if (which_alternative == 0)
6749 return "copy %1,%0";
6750 else if (which_alternative == 1)
6752 output_asm_insn ("stw %1,-16(%%r30)", operands);
6753 return "{fldws|fldw} -16(%%r30),%0";
6755 else if (which_alternative == 2)
6761 /* Support the second variant. */
6762 if (reverse_comparison)
6763 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6765 if (which_alternative == 0)
6767 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6768 int length = get_attr_length (insn);
6770 /* If this is a long branch with its delay slot unfilled, set `nullify'
6771 as it can nullify the delay slot and save a nop. */
6772 if (length == 8 && dbr_sequence_length () == 0)
6775 /* If this is a short forward conditional branch which did not get
6776 its delay slot filled, the delay slot can still be nullified. */
6777 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6778 nullify = forward_branch_p (insn);
6780 /* Handle short versions first. */
6781 if (length == 4 && nullify)
6782 return "movb,%C2,n %1,%0,%3";
6783 else if (length == 4 && ! nullify)
6784 return "movb,%C2 %1,%0,%3";
6785 else if (length == 8)
6787 /* Handle weird backwards branch with a filled delay slot
6788 which is nullified. */
6789 if (dbr_sequence_length () != 0
6790 && ! forward_branch_p (insn)
6792 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6794 /* Handle short backwards branch with an unfilled delay slot.
6795 Using a movb;nop rather than or;bl saves 1 cycle for both
6796 taken and untaken branches. */
6797 else if (dbr_sequence_length () == 0
6798 && ! forward_branch_p (insn)
6799 && INSN_ADDRESSES_SET_P ()
6800 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6801 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6802 return "movb,%C2 %1,%0,%3%#";
6803 /* Handle normal cases. */
6805 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6807 return "or,%N2 %1,%%r0,%0\n\tb %3";
6812 /* Deal with gross reload from FP register case. */
6813 else if (which_alternative == 1)
6815 /* Move loop counter from FP register to MEM then into a GR,
6816 increment the GR, store the GR into MEM, and finally reload
6817 the FP register from MEM from within the branch's delay slot. */
6818 output_asm_insn ("stw %1,-16(%%r30)", operands);
6819 if (get_attr_length (insn) == 12)
6820 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6822 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6824 /* Deal with gross reload from memory case. */
6825 else if (which_alternative == 2)
6827 /* Reload loop counter from memory, the store back to memory
6828 happens in the branch's delay slot. */
6829 if (get_attr_length (insn) == 8)
6830 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6832 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6834 /* Handle SAR as a destination. */
6837 if (get_attr_length (insn) == 8)
6838 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6840 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6844 /* Copy any FP arguments in INSN into integer registers. */
6846 copy_fp_args (rtx insn)
6851 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6853 int arg_mode, regno;
6854 rtx use = XEXP (link, 0);
6856 if (! (GET_CODE (use) == USE
6857 && GET_CODE (XEXP (use, 0)) == REG
6858 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6861 arg_mode = GET_MODE (XEXP (use, 0));
6862 regno = REGNO (XEXP (use, 0));
6864 /* Is it a floating point register? */
6865 if (regno >= 32 && regno <= 39)
6867 /* Copy the FP register into an integer register via memory. */
6868 if (arg_mode == SFmode)
6870 xoperands[0] = XEXP (use, 0);
6871 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6872 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6873 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6877 xoperands[0] = XEXP (use, 0);
6878 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6879 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6880 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6881 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6887 /* Compute length of the FP argument copy sequence for INSN. */
6889 length_fp_args (rtx insn)
6894 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6896 int arg_mode, regno;
6897 rtx use = XEXP (link, 0);
6899 if (! (GET_CODE (use) == USE
6900 && GET_CODE (XEXP (use, 0)) == REG
6901 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6904 arg_mode = GET_MODE (XEXP (use, 0));
6905 regno = REGNO (XEXP (use, 0));
6907 /* Is it a floating point register? */
6908 if (regno >= 32 && regno <= 39)
6910 if (arg_mode == SFmode)
6920 /* Return the attribute length for the millicode call instruction INSN.
6921 The length must match the code generated by output_millicode_call.
6922 We include the delay slot in the returned length as it is better to
6923 over estimate the length than to under estimate it. */
6926 attr_length_millicode_call (rtx insn)
6928 unsigned long distance = -1;
6929 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6931 if (INSN_ADDRESSES_SET_P ())
6933 distance = (total + insn_current_reference_address (insn));
6934 if (distance < total)
6940 if (!TARGET_LONG_CALLS && distance < 7600000)
6945 else if (TARGET_PORTABLE_RUNTIME)
6949 if (!TARGET_LONG_CALLS && distance < 240000)
6952 if (TARGET_LONG_ABS_CALL && !flag_pic)
6959 /* INSN is a function call. It may have an unconditional jump
6962 CALL_DEST is the routine we are calling. */
6965 output_millicode_call (rtx insn, rtx call_dest)
6967 int attr_length = get_attr_length (insn);
6968 int seq_length = dbr_sequence_length ();
6973 xoperands[0] = call_dest;
6974 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6976 /* Handle the common case where we are sure that the branch will
6977 reach the beginning of the $CODE$ subspace. The within reach
6978 form of the $$sh_func_adrs call has a length of 28. Because
6979 it has an attribute type of multi, it never has a nonzero
6980 sequence length. The length of the $$sh_func_adrs is the same
6981 as certain out of reach PIC calls to other routines. */
6982 if (!TARGET_LONG_CALLS
6983 && ((seq_length == 0
6984 && (attr_length == 12
6985 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6986 || (seq_length != 0 && attr_length == 8)))
6988 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6994 /* It might seem that one insn could be saved by accessing
6995 the millicode function using the linkage table. However,
6996 this doesn't work in shared libraries and other dynamically
6997 loaded objects. Using a pc-relative sequence also avoids
6998 problems related to the implicit use of the gp register. */
6999 output_asm_insn ("b,l .+8,%%r1", xoperands);
7003 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7004 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7008 xoperands[1] = gen_label_rtx ();
7009 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7010 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7011 CODE_LABEL_NUMBER (xoperands[1]));
7012 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7015 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7017 else if (TARGET_PORTABLE_RUNTIME)
7019 /* Pure portable runtime doesn't allow be/ble; we also don't
7020 have PIC support in the assembler/linker, so this sequence
7023 /* Get the address of our target into %r1. */
7024 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7025 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7027 /* Get our return address into %r31. */
7028 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7029 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7031 /* Jump to our target address in %r1. */
7032 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7036 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7038 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7040 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7044 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7045 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7047 if (TARGET_SOM || !TARGET_GAS)
7049 /* The HP assembler can generate relocations for the
7050 difference of two symbols. GAS can do this for a
7051 millicode symbol but not an arbitrary external
7052 symbol when generating SOM output. */
7053 xoperands[1] = gen_label_rtx ();
7054 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7055 CODE_LABEL_NUMBER (xoperands[1]));
7056 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7057 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7061 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7062 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7066 /* Jump to our target address in %r1. */
7067 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7071 if (seq_length == 0)
7072 output_asm_insn ("nop", xoperands);
7074 /* We are done if there isn't a jump in the delay slot. */
7075 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7078 /* This call has an unconditional jump in its delay slot. */
7079 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7081 /* See if the return address can be adjusted. Use the containing
7082 sequence insn's address. */
7083 if (INSN_ADDRESSES_SET_P ())
7085 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7086 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7087 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7089 if (VAL_14_BITS_P (distance))
7091 xoperands[1] = gen_label_rtx ();
7092 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7093 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7094 CODE_LABEL_NUMBER (xoperands[1]));
7097 /* ??? This branch may not reach its target. */
7098 output_asm_insn ("nop\n\tb,n %0", xoperands);
7101 /* ??? This branch may not reach its target. */
7102 output_asm_insn ("nop\n\tb,n %0", xoperands);
7104 /* Delete the jump. */
7105 PUT_CODE (NEXT_INSN (insn), NOTE);
7106 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7107 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7112 /* Return the attribute length of the call instruction INSN. The SIBCALL
7113 flag indicates whether INSN is a regular call or a sibling call. The
7114 length returned must be longer than the code actually generated by
7115 output_call. Since branch shortening is done before delay branch
7116 sequencing, there is no way to determine whether or not the delay
7117 slot will be filled during branch shortening. Even when the delay
7118 slot is filled, we may have to add a nop if the delay slot contains
7119 a branch that can't reach its target. Thus, we always have to include
7120 the delay slot in the length estimate. This used to be done in
7121 pa_adjust_insn_length but we do it here now as some sequences always
7122 fill the delay slot and we can save four bytes in the estimate for
7126 attr_length_call (rtx insn, int sibcall)
7132 rtx pat = PATTERN (insn);
7133 unsigned long distance = -1;
7135 if (INSN_ADDRESSES_SET_P ())
7137 unsigned long total;
7139 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7140 distance = (total + insn_current_reference_address (insn));
7141 if (distance < total)
7145 /* Determine if this is a local call. */
7146 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7147 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7149 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7151 call_decl = SYMBOL_REF_DECL (call_dest);
7152 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7154 /* pc-relative branch. */
7155 if (!TARGET_LONG_CALLS
7156 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7157 || distance < 240000))
7160 /* 64-bit plabel sequence. */
7161 else if (TARGET_64BIT && !local_call)
7162 length += sibcall ? 28 : 24;
7164 /* non-pic long absolute branch sequence. */
7165 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7168 /* long pc-relative branch sequence. */
7169 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7170 || (TARGET_64BIT && !TARGET_GAS)
7171 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7175 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7179 /* 32-bit plabel sequence. */
7185 length += length_fp_args (insn);
7195 if (!TARGET_NO_SPACE_REGS)
7203 /* INSN is a function call. It may have an unconditional jump
7206 CALL_DEST is the routine we are calling. */
7209 output_call (rtx insn, rtx call_dest, int sibcall)
7211 int delay_insn_deleted = 0;
7212 int delay_slot_filled = 0;
7213 int seq_length = dbr_sequence_length ();
7214 tree call_decl = SYMBOL_REF_DECL (call_dest);
7215 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7218 xoperands[0] = call_dest;
7220 /* Handle the common case where we're sure that the branch will reach
7221 the beginning of the "$CODE$" subspace. This is the beginning of
7222 the current function if we are in a named section. */
7223 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7225 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7226 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7230 if (TARGET_64BIT && !local_call)
7232 /* ??? As far as I can tell, the HP linker doesn't support the
7233 long pc-relative sequence described in the 64-bit runtime
7234 architecture. So, we use a slightly longer indirect call. */
7235 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7237 xoperands[0] = p->internal_label;
7238 xoperands[1] = gen_label_rtx ();
7240 /* If this isn't a sibcall, we put the load of %r27 into the
7241 delay slot. We can't do this in a sibcall as we don't
7242 have a second call-clobbered scratch register available. */
7244 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7247 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7248 optimize, 0, 0, NULL);
7250 /* Now delete the delay insn. */
7251 PUT_CODE (NEXT_INSN (insn), NOTE);
7252 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7253 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7254 delay_insn_deleted = 1;
7257 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7258 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7259 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7263 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7264 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7265 output_asm_insn ("bve (%%r1)", xoperands);
7269 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7270 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7271 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7272 delay_slot_filled = 1;
7277 int indirect_call = 0;
7279 /* Emit a long call. There are several different sequences
7280 of increasing length and complexity. In most cases,
7281 they don't allow an instruction in the delay slot. */
7282 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7283 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7284 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7289 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7291 && (!TARGET_PA_20 || indirect_call))
7293 /* A non-jump insn in the delay slot. By definition we can
7294 emit this insn before the call (and in fact before argument
7296 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7299 /* Now delete the delay insn. */
7300 PUT_CODE (NEXT_INSN (insn), NOTE);
7301 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7302 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7303 delay_insn_deleted = 1;
7306 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7308 /* This is the best sequence for making long calls in
7309 non-pic code. Unfortunately, GNU ld doesn't provide
7310 the stub needed for external calls, and GAS's support
7311 for this with the SOM linker is buggy. It is safe
7312 to use this for local calls. */
7313 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7315 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7319 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7322 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7324 output_asm_insn ("copy %%r31,%%r2", xoperands);
7325 delay_slot_filled = 1;
7330 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7331 || (TARGET_64BIT && !TARGET_GAS))
7333 /* The HP assembler and linker can handle relocations
7334 for the difference of two symbols. GAS and the HP
7335 linker can't do this when one of the symbols is
7337 xoperands[1] = gen_label_rtx ();
7338 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7339 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7340 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7341 CODE_LABEL_NUMBER (xoperands[1]));
7342 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7344 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7346 /* GAS currently can't generate the relocations that
7347 are needed for the SOM linker under HP-UX using this
7348 sequence. The GNU linker doesn't generate the stubs
7349 that are needed for external calls on TARGET_ELF32
7350 with this sequence. For now, we have to use a
7351 longer plabel sequence when using GAS. */
7352 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7353 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7355 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7360 /* Emit a long plabel-based call sequence. This is
7361 essentially an inline implementation of $$dyncall.
7362 We don't actually try to call $$dyncall as this is
7363 as difficult as calling the function itself. */
7364 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7366 xoperands[0] = p->internal_label;
7367 xoperands[1] = gen_label_rtx ();
7369 /* Since the call is indirect, FP arguments in registers
7370 need to be copied to the general registers. Then, the
7371 argument relocation stub will copy them back. */
7373 copy_fp_args (insn);
7377 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7378 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7379 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7383 output_asm_insn ("addil LR'%0-$global$,%%r27",
7385 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7389 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7390 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7391 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7392 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7394 if (!sibcall && !TARGET_PA_20)
7396 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7397 if (TARGET_NO_SPACE_REGS)
7398 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7400 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7407 output_asm_insn ("bve (%%r1)", xoperands);
7412 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7413 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7414 delay_slot_filled = 1;
7417 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7422 if (!TARGET_NO_SPACE_REGS)
7423 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7428 if (TARGET_NO_SPACE_REGS)
7429 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7431 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7435 if (TARGET_NO_SPACE_REGS)
7436 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7438 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7441 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7443 output_asm_insn ("copy %%r31,%%r2", xoperands);
7444 delay_slot_filled = 1;
7451 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7452 output_asm_insn ("nop", xoperands);
7454 /* We are done if there isn't a jump in the delay slot. */
7456 || delay_insn_deleted
7457 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7460 /* A sibcall should never have a branch in the delay slot. */
7464 /* This call has an unconditional jump in its delay slot. */
7465 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7467 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7469 /* See if the return address can be adjusted. Use the containing
7470 sequence insn's address. */
7471 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7472 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7473 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7475 if (VAL_14_BITS_P (distance))
7477 xoperands[1] = gen_label_rtx ();
7478 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7479 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7480 CODE_LABEL_NUMBER (xoperands[1]));
7483 output_asm_insn ("nop\n\tb,n %0", xoperands);
7486 output_asm_insn ("b,n %0", xoperands);
7488 /* Delete the jump. */
7489 PUT_CODE (NEXT_INSN (insn), NOTE);
7490 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7491 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7496 /* Return the attribute length of the indirect call instruction INSN.
7497 The length must match the code generated by output_indirect call.
7498 The returned length includes the delay slot. Currently, the delay
7499 slot of an indirect call sequence is not exposed and it is used by
7500 the sequence itself. */
7503 attr_length_indirect_call (rtx insn)
7505 unsigned long distance = -1;
7506 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7508 if (INSN_ADDRESSES_SET_P ())
7510 distance = (total + insn_current_reference_address (insn));
7511 if (distance < total)
7518 if (TARGET_FAST_INDIRECT_CALLS
7519 || (!TARGET_PORTABLE_RUNTIME
7520 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7526 if (TARGET_PORTABLE_RUNTIME)
7529 /* Out of reach, can use ble. */
7534 output_indirect_call (rtx insn, rtx call_dest)
7540 xoperands[0] = call_dest;
7541 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7542 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7546 /* First the special case for kernels, level 0 systems, etc. */
7547 if (TARGET_FAST_INDIRECT_CALLS)
7548 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7550 /* Now the normal case -- we can reach $$dyncall directly or
7551 we're sure that we can get there via a long-branch stub.
7553 No need to check target flags as the length uniquely identifies
7554 the remaining cases. */
7555 if (attr_length_indirect_call (insn) == 8)
7556 return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7558 /* Long millicode call, but we are not generating PIC or portable runtime
7560 if (attr_length_indirect_call (insn) == 12)
7561 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7563 /* Long millicode call for portable runtime. */
7564 if (attr_length_indirect_call (insn) == 20)
7565 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7567 /* We need a long PIC call to $$dyncall. */
7568 xoperands[0] = NULL_RTX;
7569 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7570 if (TARGET_SOM || !TARGET_GAS)
7572 xoperands[0] = gen_label_rtx ();
7573 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7574 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7575 CODE_LABEL_NUMBER (xoperands[0]));
7576 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7580 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7581 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7584 output_asm_insn ("blr %%r0,%%r2", xoperands);
7585 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7589 /* Return the total length of the save and restore instructions needed for
7590 the data linkage table pointer (i.e., the PIC register) across the call
7591 instruction INSN. No-return calls do not require a save and restore.
7592 In addition, we may be able to avoid the save and restore for calls
7593 within the same translation unit. */
7596 attr_length_save_restore_dltp (rtx insn)
7598 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7604 /* In HPUX 8.0's shared library scheme, special relocations are needed
7605 for function labels if they might be passed to a function
7606 in a shared library (because shared libraries don't live in code
7607 space), and special magic is needed to construct their address. */
7610 hppa_encode_label (rtx sym)
7612 const char *str = XSTR (sym, 0);
7613 int len = strlen (str) + 1;
7616 p = newstr = alloca (len + 1);
7620 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7624 pa_encode_section_info (tree decl, rtx rtl, int first)
7626 if (first && TEXT_SPACE_P (decl))
7628 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7629 if (TREE_CODE (decl) == FUNCTION_DECL)
7630 hppa_encode_label (XEXP (rtl, 0));
7634 /* This is sort of inverse to pa_encode_section_info. */
7637 pa_strip_name_encoding (const char *str)
7639 str += (*str == '@');
7640 str += (*str == '*');
7645 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7647 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7650 /* Returns 1 if OP is a function label involved in a simple addition
7651 with a constant. Used to keep certain patterns from matching
7652 during instruction combination. */
7654 is_function_label_plus_const (rtx op)
7656 /* Strip off any CONST. */
7657 if (GET_CODE (op) == CONST)
7660 return (GET_CODE (op) == PLUS
7661 && function_label_operand (XEXP (op, 0), Pmode)
7662 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7665 /* Output assembly code for a thunk to FUNCTION. */
7668 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7669 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7672 const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7673 const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
7674 int val_14 = VAL_14_BITS_P (delta);
7676 static unsigned int current_thunk_number;
7679 ASM_OUTPUT_LABEL (file, tname);
7680 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7682 fname = (*targetm.strip_name_encoding) (fname);
7683 tname = (*targetm.strip_name_encoding) (tname);
7685 /* Output the thunk. We know that the function is in the same
7686 translation unit (i.e., the same space) as the thunk, and that
7687 thunks are output after their method. Thus, we don't need an
7688 external branch to reach the function. With SOM and GAS,
7689 functions and thunks are effectively in different sections.
7690 Thus, we can always use a IA-relative branch and the linker
7691 will add a long branch stub if necessary.
7693 However, we have to be careful when generating PIC code on the
7694 SOM port to ensure that the sequence does not transfer to an
7695 import stub for the target function as this could clobber the
7696 return value saved at SP-24. This would also apply to the
7697 32-bit linux port if the multi-space model is implemented. */
7698 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7699 && !(flag_pic && TREE_PUBLIC (function))
7700 && (TARGET_GAS || last_address < 262132))
7701 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7702 && ((targetm.have_named_sections
7703 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7704 /* The GNU 64-bit linker has rather poor stub management.
7705 So, we use a long branch from thunks that aren't in
7706 the same section as the target function. */
7708 && (DECL_SECTION_NAME (thunk_fndecl)
7709 != DECL_SECTION_NAME (function)))
7710 || ((DECL_SECTION_NAME (thunk_fndecl)
7711 == DECL_SECTION_NAME (function))
7712 && last_address < 262132)))
7713 || (!targetm.have_named_sections && last_address < 262132))))
7717 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7718 "(%%r26),%%r26\n", fname, delta);
7723 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7725 fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7726 "(%%r1),%%r26\n", fname, delta);
7730 else if (TARGET_64BIT)
7732 /* We only have one call-clobbered scratch register, so we can't
7733 make use of the delay slot if delta doesn't fit in 14 bits. */
7735 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7736 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7737 "(%%r1),%%r26\n", delta, delta);
7739 fprintf (file, "\tb,l .+8,%%r1\n");
7743 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7744 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname);
7748 int off = val_14 ? 8 : 16;
7749 fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off);
7750 fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off);
7755 fprintf (file, "\tbv %%r0(%%r1)\n\tldo ");
7756 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7761 fprintf (file, "\tbv,n %%r0(%%r1)\n");
7765 else if (TARGET_PORTABLE_RUNTIME)
7767 fprintf (file, "\tldil L'%s,%%r1\n", fname);
7768 fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname);
7772 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7773 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7778 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7780 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7781 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7785 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7787 /* The function is accessible from outside this module. The only
7788 way to avoid an import stub between the thunk and function is to
7789 call the function directly with an indirect sequence similar to
7790 that used by $$dyncall. This is possible because $$dyncall acts
7791 as the import stub in an indirect call. */
7794 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7795 lab = (*targetm.strip_name_encoding) (label);
7797 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7798 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7799 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7800 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7801 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7802 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7803 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7806 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7812 fprintf (file, "\tbve (%%r22)\n\tldo ");
7817 if (TARGET_NO_SPACE_REGS)
7819 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7824 fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
7825 fprintf (file, "\tmtsp %%r21,%%sr0\n");
7826 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7832 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7834 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7839 fprintf (file, "\tb,l .+8,%%r1\n");
7841 fprintf (file, "\tbl .+8,%%r1\n");
7843 if (TARGET_SOM || !TARGET_GAS)
7845 fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname);
7846 fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname);
7850 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7851 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname);
7856 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7857 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7862 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7864 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7865 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7872 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta);
7874 fprintf (file, "\tldil L'%s,%%r22\n", fname);
7875 fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname);
7879 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7884 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7889 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7891 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7894 fprintf (file, "\t.align 4\n");
7895 ASM_OUTPUT_LABEL (file, label);
7896 fprintf (file, "\t.word P'%s\n", fname);
7897 function_section (thunk_fndecl);
7900 current_thunk_number++;
7901 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7902 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7903 last_address += nbytes;
7904 update_total_code_bytes (nbytes);
7907 /* Only direct calls to static functions are allowed to be sibling (tail)
7910 This restriction is necessary because some linker generated stubs will
7911 store return pointers into rp' in some cases which might clobber a
7912 live value already in rp'.
7914 In a sibcall the current function and the target function share stack
7915 space. Thus if the path to the current function and the path to the
7916 target function save a value in rp', they save the value into the
7917 same stack slot, which has undesirable consequences.
7919 Because of the deferred binding nature of shared libraries any function
7920 with external scope could be in a different load module and thus require
7921 rp' to be saved when calling that function. So sibcall optimizations
7922 can only be safe for static function.
7924 Note that GCC never needs return value relocations, so we don't have to
7925 worry about static calls with return value relocations (which require
7928 It is safe to perform a sibcall optimization when the target function
7929 will never return. */
7931 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7933 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7934 single subspace mode and the call is not indirect. As far as I know,
7935 there is no operating system support for the multiple subspace mode.
7936 It might be possible to support indirect calls if we didn't use
7937 $$dyncall (see the indirect sequence generated in output_call). */
7939 return (decl != NULL_TREE);
7941 /* Sibcalls are not ok because the arg pointer register is not a fixed
7942 register. This prevents the sibcall optimization from occurring. In
7943 addition, there are problems with stub placement using GNU ld. This
7944 is because a normal sibcall branch uses a 17-bit relocation while
7945 a regular call branch uses a 22-bit relocation. As a result, more
7946 care needs to be taken in the placement of long-branch stubs. */
7951 && !TARGET_PORTABLE_RUNTIME
7952 && !TREE_PUBLIC (decl));
7955 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7956 use in fmpyadd instructions. */
7958 fmpyaddoperands (rtx *operands)
7960 enum machine_mode mode = GET_MODE (operands[0]);
7962 /* Must be a floating point mode. */
7963 if (mode != SFmode && mode != DFmode)
7966 /* All modes must be the same. */
7967 if (! (mode == GET_MODE (operands[1])
7968 && mode == GET_MODE (operands[2])
7969 && mode == GET_MODE (operands[3])
7970 && mode == GET_MODE (operands[4])
7971 && mode == GET_MODE (operands[5])))
7974 /* All operands must be registers. */
7975 if (! (GET_CODE (operands[1]) == REG
7976 && GET_CODE (operands[2]) == REG
7977 && GET_CODE (operands[3]) == REG
7978 && GET_CODE (operands[4]) == REG
7979 && GET_CODE (operands[5]) == REG))
7982 /* Only 2 real operands to the addition. One of the input operands must
7983 be the same as the output operand. */
7984 if (! rtx_equal_p (operands[3], operands[4])
7985 && ! rtx_equal_p (operands[3], operands[5]))
7988 /* Inout operand of add can not conflict with any operands from multiply. */
7989 if (rtx_equal_p (operands[3], operands[0])
7990 || rtx_equal_p (operands[3], operands[1])
7991 || rtx_equal_p (operands[3], operands[2]))
7994 /* multiply can not feed into addition operands. */
7995 if (rtx_equal_p (operands[4], operands[0])
7996 || rtx_equal_p (operands[5], operands[0]))
7999 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8001 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8002 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8003 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8004 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8005 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8006 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8009 /* Passed. Operands are suitable for fmpyadd. */
8013 #if !defined(USE_COLLECT2)
8015 pa_asm_out_constructor (rtx symbol, int priority)
8017 if (!function_label_operand (symbol, VOIDmode))
8018 hppa_encode_label (symbol);
8020 #ifdef CTORS_SECTION_ASM_OP
8021 default_ctor_section_asm_out_constructor (symbol, priority);
8023 # ifdef TARGET_ASM_NAMED_SECTION
8024 default_named_section_asm_out_constructor (symbol, priority);
8026 default_stabs_asm_out_constructor (symbol, priority);
8032 pa_asm_out_destructor (rtx symbol, int priority)
8034 if (!function_label_operand (symbol, VOIDmode))
8035 hppa_encode_label (symbol);
8037 #ifdef DTORS_SECTION_ASM_OP
8038 default_dtor_section_asm_out_destructor (symbol, priority);
8040 # ifdef TARGET_ASM_NAMED_SECTION
8041 default_named_section_asm_out_destructor (symbol, priority);
8043 default_stabs_asm_out_destructor (symbol, priority);
8049 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8050 use in fmpysub instructions. */
8052 fmpysuboperands (rtx *operands)
8054 enum machine_mode mode = GET_MODE (operands[0]);
8056 /* Must be a floating point mode. */
8057 if (mode != SFmode && mode != DFmode)
8060 /* All modes must be the same. */
8061 if (! (mode == GET_MODE (operands[1])
8062 && mode == GET_MODE (operands[2])
8063 && mode == GET_MODE (operands[3])
8064 && mode == GET_MODE (operands[4])
8065 && mode == GET_MODE (operands[5])))
8068 /* All operands must be registers. */
8069 if (! (GET_CODE (operands[1]) == REG
8070 && GET_CODE (operands[2]) == REG
8071 && GET_CODE (operands[3]) == REG
8072 && GET_CODE (operands[4]) == REG
8073 && GET_CODE (operands[5]) == REG))
8076 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8077 operation, so operands[4] must be the same as operand[3]. */
8078 if (! rtx_equal_p (operands[3], operands[4]))
8081 /* multiply can not feed into subtraction. */
8082 if (rtx_equal_p (operands[5], operands[0]))
8085 /* Inout operand of sub can not conflict with any operands from multiply. */
8086 if (rtx_equal_p (operands[3], operands[0])
8087 || rtx_equal_p (operands[3], operands[1])
8088 || rtx_equal_p (operands[3], operands[2]))
8091 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8093 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8094 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8095 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8096 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8097 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8098 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8101 /* Passed. Operands are suitable for fmpysub. */
8106 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8108 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8109 || GET_CODE (op) == IOR);
8112 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8113 constants for shadd instructions. */
8115 shadd_constant_p (int val)
8117 if (val == 2 || val == 4 || val == 8)
8123 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8124 the valid constant for shadd instructions. */
8126 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8128 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8131 /* Return 1 if OP is valid as a base or index register in a
8135 borx_reg_operand (rtx op, enum machine_mode mode)
8137 if (GET_CODE (op) != REG)
8140 /* We must reject virtual registers as the only expressions that
8141 can be instantiated are REG and REG+CONST. */
8142 if (op == virtual_incoming_args_rtx
8143 || op == virtual_stack_vars_rtx
8144 || op == virtual_stack_dynamic_rtx
8145 || op == virtual_outgoing_args_rtx
8146 || op == virtual_cfa_rtx)
8149 /* While it's always safe to index off the frame pointer, it's not
8150 profitable to do so when the frame pointer is being eliminated. */
8151 if (!reload_completed
8152 && flag_omit_frame_pointer
8153 && !current_function_calls_alloca
8154 && op == frame_pointer_rtx)
8157 return register_operand (op, mode);
8160 /* Return 1 if this operand is anything other than a hard register. */
8163 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8165 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8168 /* Return 1 if INSN branches forward. Should be using insn_addresses
8169 to avoid walking through all the insns... */
8171 forward_branch_p (rtx insn)
8173 rtx label = JUMP_LABEL (insn);
8180 insn = NEXT_INSN (insn);
8183 return (insn == label);
8186 /* Return 1 if OP is an equality comparison, else return 0. */
8188 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8190 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8193 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8195 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8197 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8198 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8201 /* Return 1 if INSN is in the delay slot of a call instruction. */
8203 jump_in_call_delay (rtx insn)
8206 if (GET_CODE (insn) != JUMP_INSN)
8209 if (PREV_INSN (insn)
8210 && PREV_INSN (PREV_INSN (insn))
8211 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8213 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8215 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8216 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8223 /* Output an unconditional move and branch insn. */
8226 output_parallel_movb (rtx *operands, int length)
8228 /* These are the cases in which we win. */
8230 return "mov%I1b,tr %1,%0,%2";
8232 /* None of these cases wins, but they don't lose either. */
8233 if (dbr_sequence_length () == 0)
8235 /* Nothing in the delay slot, fake it by putting the combined
8236 insn (the copy or add) in the delay slot of a bl. */
8237 if (GET_CODE (operands[1]) == CONST_INT)
8238 return "b %2\n\tldi %1,%0";
8240 return "b %2\n\tcopy %1,%0";
8244 /* Something in the delay slot, but we've got a long branch. */
8245 if (GET_CODE (operands[1]) == CONST_INT)
8246 return "ldi %1,%0\n\tb %2";
8248 return "copy %1,%0\n\tb %2";
8252 /* Output an unconditional add and branch insn. */
8255 output_parallel_addb (rtx *operands, int length)
8257 /* To make life easy we want operand0 to be the shared input/output
8258 operand and operand1 to be the readonly operand. */
8259 if (operands[0] == operands[1])
8260 operands[1] = operands[2];
8262 /* These are the cases in which we win. */
8264 return "add%I1b,tr %1,%0,%3";
8266 /* None of these cases win, but they don't lose either. */
8267 if (dbr_sequence_length () == 0)
8269 /* Nothing in the delay slot, fake it by putting the combined
8270 insn (the copy or add) in the delay slot of a bl. */
8271 return "b %3\n\tadd%I1 %1,%0,%0";
8275 /* Something in the delay slot, but we've got a long branch. */
8276 return "add%I1 %1,%0,%0\n\tb %3";
8280 /* Return nonzero if INSN (a jump insn) immediately follows a call
8281 to a named function. This is used to avoid filling the delay slot
8282 of the jump since it can usually be eliminated by modifying RP in
8283 the delay slot of the call. */
8286 following_call (rtx insn)
8288 if (! TARGET_JUMP_IN_DELAY)
8291 /* Find the previous real insn, skipping NOTEs. */
8292 insn = PREV_INSN (insn);
8293 while (insn && GET_CODE (insn) == NOTE)
8294 insn = PREV_INSN (insn);
8296 /* Check for CALL_INSNs and millicode calls. */
8298 && ((GET_CODE (insn) == CALL_INSN
8299 && get_attr_type (insn) != TYPE_DYNCALL)
8300 || (GET_CODE (insn) == INSN
8301 && GET_CODE (PATTERN (insn)) != SEQUENCE
8302 && GET_CODE (PATTERN (insn)) != USE
8303 && GET_CODE (PATTERN (insn)) != CLOBBER
8304 && get_attr_type (insn) == TYPE_MILLI)))
8310 /* We use this hook to perform a PA specific optimization which is difficult
8311 to do in earlier passes.
8313 We want the delay slots of branches within jump tables to be filled.
8314 None of the compiler passes at the moment even has the notion that a
8315 PA jump table doesn't contain addresses, but instead contains actual
8318 Because we actually jump into the table, the addresses of each entry
8319 must stay constant in relation to the beginning of the table (which
8320 itself must stay constant relative to the instruction to jump into
8321 it). I don't believe we can guarantee earlier passes of the compiler
8322 will adhere to those rules.
8324 So, late in the compilation process we find all the jump tables, and
8325 expand them into real code -- eg each entry in the jump table vector
8326 will get an appropriate label followed by a jump to the final target.
8328 Reorg and the final jump pass can then optimize these branches and
8329 fill their delay slots. We end up with smaller, more efficient code.
8331 The jump instructions within the table are special; we must be able
8332 to identify them during assembly output (if the jumps don't get filled
8333 we need to emit a nop rather than nullifying the delay slot)). We
8334 identify jumps in switch tables by using insns with the attribute
8335 type TYPE_BTABLE_BRANCH.
8337 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8338 insns. This serves two purposes, first it prevents jump.c from
8339 noticing that the last N entries in the table jump to the instruction
8340 immediately after the table and deleting the jumps. Second, those
8341 insns mark where we should emit .begin_brtab and .end_brtab directives
8342 when using GAS (allows for better link time optimizations). */
8349 remove_useless_addtr_insns (1);
8351 if (pa_cpu < PROCESSOR_8000)
8352 pa_combine_instructions ();
8355 /* This is fairly cheap, so always run it if optimizing. */
8356 if (optimize > 0 && !TARGET_BIG_SWITCH)
8358 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8359 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8361 rtx pattern, tmp, location, label;
8362 unsigned int length, i;
8364 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8365 if (GET_CODE (insn) != JUMP_INSN
8366 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8367 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8370 /* Emit marker for the beginning of the branch table. */
8371 emit_insn_before (gen_begin_brtab (), insn);
8373 pattern = PATTERN (insn);
8374 location = PREV_INSN (insn);
8375 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8377 for (i = 0; i < length; i++)
8379 /* Emit a label before each jump to keep jump.c from
8380 removing this code. */
8381 tmp = gen_label_rtx ();
8382 LABEL_NUSES (tmp) = 1;
8383 emit_label_after (tmp, location);
8384 location = NEXT_INSN (location);
8386 if (GET_CODE (pattern) == ADDR_VEC)
8387 label = XEXP (XVECEXP (pattern, 0, i), 0);
8389 label = XEXP (XVECEXP (pattern, 1, i), 0);
8391 tmp = gen_short_jump (label);
8393 /* Emit the jump itself. */
8394 tmp = emit_jump_insn_after (tmp, location);
8395 JUMP_LABEL (tmp) = label;
8396 LABEL_NUSES (label)++;
8397 location = NEXT_INSN (location);
8399 /* Emit a BARRIER after the jump. */
8400 emit_barrier_after (location);
8401 location = NEXT_INSN (location);
8404 /* Emit marker for the end of the branch table. */
8405 emit_insn_before (gen_end_brtab (), location);
8406 location = NEXT_INSN (location);
8407 emit_barrier_after (location);
8409 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8415 /* Still need brtab marker insns. FIXME: the presence of these
8416 markers disables output of the branch table to readonly memory,
8417 and any alignment directives that might be needed. Possibly,
8418 the begin_brtab insn should be output before the label for the
8419 table. This doesn matter at the moment since the tables are
8420 always output in the text section. */
8421 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8423 /* Find an ADDR_VEC insn. */
8424 if (GET_CODE (insn) != JUMP_INSN
8425 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8426 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8429 /* Now generate markers for the beginning and end of the
8431 emit_insn_before (gen_begin_brtab (), insn);
8432 emit_insn_after (gen_end_brtab (), insn);
8437 /* The PA has a number of odd instructions which can perform multiple
8438 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8439 it may be profitable to combine two instructions into one instruction
8440 with two outputs. It's not profitable PA2.0 machines because the
8441 two outputs would take two slots in the reorder buffers.
8443 This routine finds instructions which can be combined and combines
8444 them. We only support some of the potential combinations, and we
8445 only try common ways to find suitable instructions.
8447 * addb can add two registers or a register and a small integer
8448 and jump to a nearby (+-8k) location. Normally the jump to the
8449 nearby location is conditional on the result of the add, but by
8450 using the "true" condition we can make the jump unconditional.
8451 Thus addb can perform two independent operations in one insn.
8453 * movb is similar to addb in that it can perform a reg->reg
8454 or small immediate->reg copy and jump to a nearby (+-8k location).
8456 * fmpyadd and fmpysub can perform a FP multiply and either an
8457 FP add or FP sub if the operands of the multiply and add/sub are
8458 independent (there are other minor restrictions). Note both
8459 the fmpy and fadd/fsub can in theory move to better spots according
8460 to data dependencies, but for now we require the fmpy stay at a
8463 * Many of the memory operations can perform pre & post updates
8464 of index registers. GCC's pre/post increment/decrement addressing
8465 is far too simple to take advantage of all the possibilities. This
8466 pass may not be suitable since those insns may not be independent.
8468 * comclr can compare two ints or an int and a register, nullify
8469 the following instruction and zero some other register. This
8470 is more difficult to use as it's harder to find an insn which
8471 will generate a comclr than finding something like an unconditional
8472 branch. (conditional moves & long branches create comclr insns).
8474 * Most arithmetic operations can conditionally skip the next
8475 instruction. They can be viewed as "perform this operation
8476 and conditionally jump to this nearby location" (where nearby
8477 is an insns away). These are difficult to use due to the
8478 branch length restrictions. */
8481 pa_combine_instructions (void)
8485 /* This can get expensive since the basic algorithm is on the
8486 order of O(n^2) (or worse). Only do it for -O2 or higher
8487 levels of optimization. */
8491 /* Walk down the list of insns looking for "anchor" insns which
8492 may be combined with "floating" insns. As the name implies,
8493 "anchor" instructions don't move, while "floating" insns may
8495 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8496 new = make_insn_raw (new);
8498 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8500 enum attr_pa_combine_type anchor_attr;
8501 enum attr_pa_combine_type floater_attr;
8503 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8504 Also ignore any special USE insns. */
8505 if ((GET_CODE (anchor) != INSN
8506 && GET_CODE (anchor) != JUMP_INSN
8507 && GET_CODE (anchor) != CALL_INSN)
8508 || GET_CODE (PATTERN (anchor)) == USE
8509 || GET_CODE (PATTERN (anchor)) == CLOBBER
8510 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8511 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8514 anchor_attr = get_attr_pa_combine_type (anchor);
8515 /* See if anchor is an insn suitable for combination. */
8516 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8517 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8518 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8519 && ! forward_branch_p (anchor)))
8523 for (floater = PREV_INSN (anchor);
8525 floater = PREV_INSN (floater))
8527 if (GET_CODE (floater) == NOTE
8528 || (GET_CODE (floater) == INSN
8529 && (GET_CODE (PATTERN (floater)) == USE
8530 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8533 /* Anything except a regular INSN will stop our search. */
8534 if (GET_CODE (floater) != INSN
8535 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8536 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8542 /* See if FLOATER is suitable for combination with the
8544 floater_attr = get_attr_pa_combine_type (floater);
8545 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8546 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8547 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8548 && floater_attr == PA_COMBINE_TYPE_FMPY))
8550 /* If ANCHOR and FLOATER can be combined, then we're
8551 done with this pass. */
8552 if (pa_can_combine_p (new, anchor, floater, 0,
8553 SET_DEST (PATTERN (floater)),
8554 XEXP (SET_SRC (PATTERN (floater)), 0),
8555 XEXP (SET_SRC (PATTERN (floater)), 1)))
8559 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8560 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8562 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8564 if (pa_can_combine_p (new, anchor, floater, 0,
8565 SET_DEST (PATTERN (floater)),
8566 XEXP (SET_SRC (PATTERN (floater)), 0),
8567 XEXP (SET_SRC (PATTERN (floater)), 1)))
8572 if (pa_can_combine_p (new, anchor, floater, 0,
8573 SET_DEST (PATTERN (floater)),
8574 SET_SRC (PATTERN (floater)),
8575 SET_SRC (PATTERN (floater))))
8581 /* If we didn't find anything on the backwards scan try forwards. */
8583 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8584 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8586 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8588 if (GET_CODE (floater) == NOTE
8589 || (GET_CODE (floater) == INSN
8590 && (GET_CODE (PATTERN (floater)) == USE
8591 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8595 /* Anything except a regular INSN will stop our search. */
8596 if (GET_CODE (floater) != INSN
8597 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8598 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8604 /* See if FLOATER is suitable for combination with the
8606 floater_attr = get_attr_pa_combine_type (floater);
8607 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8608 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8609 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8610 && floater_attr == PA_COMBINE_TYPE_FMPY))
8612 /* If ANCHOR and FLOATER can be combined, then we're
8613 done with this pass. */
8614 if (pa_can_combine_p (new, anchor, floater, 1,
8615 SET_DEST (PATTERN (floater)),
8616 XEXP (SET_SRC (PATTERN (floater)),
8618 XEXP (SET_SRC (PATTERN (floater)),
8625 /* FLOATER will be nonzero if we found a suitable floating
8626 insn for combination with ANCHOR. */
8628 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8629 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8631 /* Emit the new instruction and delete the old anchor. */
8632 emit_insn_before (gen_rtx_PARALLEL
8634 gen_rtvec (2, PATTERN (anchor),
8635 PATTERN (floater))),
8638 PUT_CODE (anchor, NOTE);
8639 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8640 NOTE_SOURCE_FILE (anchor) = 0;
8642 /* Emit a special USE insn for FLOATER, then delete
8643 the floating insn. */
8644 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8645 delete_insn (floater);
8650 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8653 /* Emit the new_jump instruction and delete the old anchor. */
8655 = emit_jump_insn_before (gen_rtx_PARALLEL
8657 gen_rtvec (2, PATTERN (anchor),
8658 PATTERN (floater))),
8661 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8662 PUT_CODE (anchor, NOTE);
8663 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8664 NOTE_SOURCE_FILE (anchor) = 0;
8666 /* Emit a special USE insn for FLOATER, then delete
8667 the floating insn. */
8668 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8669 delete_insn (floater);
8677 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8680 int insn_code_number;
8683 /* Create a PARALLEL with the patterns of ANCHOR and
8684 FLOATER, try to recognize it, then test constraints
8685 for the resulting pattern.
8687 If the pattern doesn't match or the constraints
8688 aren't met keep searching for a suitable floater
8690 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8691 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8692 INSN_CODE (new) = -1;
8693 insn_code_number = recog_memoized (new);
8694 if (insn_code_number < 0
8695 || (extract_insn (new), ! constrain_operands (1)))
8709 /* There's up to three operands to consider. One
8710 output and two inputs.
8712 The output must not be used between FLOATER & ANCHOR
8713 exclusive. The inputs must not be set between
8714 FLOATER and ANCHOR exclusive. */
8716 if (reg_used_between_p (dest, start, end))
8719 if (reg_set_between_p (src1, start, end))
8722 if (reg_set_between_p (src2, start, end))
8725 /* If we get here, then everything is good. */
8729 /* Return nonzero if references for INSN are delayed.
8731 Millicode insns are actually function calls with some special
8732 constraints on arguments and register usage.
8734 Millicode calls always expect their arguments in the integer argument
8735 registers, and always return their result in %r29 (ret1). They
8736 are expected to clobber their arguments, %r1, %r29, and the return
8737 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8739 This function tells reorg that the references to arguments and
8740 millicode calls do not appear to happen until after the millicode call.
8741 This allows reorg to put insns which set the argument registers into the
8742 delay slot of the millicode call -- thus they act more like traditional
8745 Note we can not consider side effects of the insn to be delayed because
8746 the branch and link insn will clobber the return pointer. If we happened
8747 to use the return pointer in the delay slot of the call, then we lose.
8749 get_attr_type will try to recognize the given insn, so make sure to
8750 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8753 insn_refs_are_delayed (rtx insn)
8755 return ((GET_CODE (insn) == INSN
8756 && GET_CODE (PATTERN (insn)) != SEQUENCE
8757 && GET_CODE (PATTERN (insn)) != USE
8758 && GET_CODE (PATTERN (insn)) != CLOBBER
8759 && get_attr_type (insn) == TYPE_MILLI));
8762 /* On the HP-PA the value is found in register(s) 28(-29), unless
8763 the mode is SF or DF. Then the value is returned in fr4 (32).
8765 This must perform the same promotions as PROMOTE_MODE, else
8766 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8768 Small structures must be returned in a PARALLEL on PA64 in order
8769 to match the HP Compiler ABI. */
8772 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8774 enum machine_mode valmode;
8776 /* Aggregates with a size less than or equal to 128 bits are returned
8777 in GR 28(-29). They are left justified. The pad bits are undefined.
8778 Larger aggregates are returned in memory. */
8779 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8783 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8785 for (i = 0; i < ub; i++)
8787 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8788 gen_rtx_REG (DImode, 28 + i),
8793 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8796 if ((INTEGRAL_TYPE_P (valtype)
8797 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8798 || POINTER_TYPE_P (valtype))
8799 valmode = word_mode;
8801 valmode = TYPE_MODE (valtype);
8803 if (TREE_CODE (valtype) == REAL_TYPE
8804 && TYPE_MODE (valtype) != TFmode
8805 && !TARGET_SOFT_FLOAT)
8806 return gen_rtx_REG (valmode, 32);
8808 return gen_rtx_REG (valmode, 28);
8811 /* Return the location of a parameter that is passed in a register or NULL
8812 if the parameter has any component that is passed in memory.
8814 This is new code and will be pushed to into the net sources after
8817 ??? We might want to restructure this so that it looks more like other
8820 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8821 int named ATTRIBUTE_UNUSED)
8823 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8830 if (mode == VOIDmode)
8833 arg_size = FUNCTION_ARG_SIZE (mode, type);
8835 /* If this arg would be passed partially or totally on the stack, then
8836 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8837 handle arguments which are split between regs and stack slots if
8838 the ABI mandates split arguments. */
8841 /* The 32-bit ABI does not split arguments. */
8842 if (cum->words + arg_size > max_arg_words)
8848 alignment = cum->words & 1;
8849 if (cum->words + alignment >= max_arg_words)
8853 /* The 32bit ABIs and the 64bit ABIs are rather different,
8854 particularly in their handling of FP registers. We might
8855 be able to cleverly share code between them, but I'm not
8856 going to bother in the hope that splitting them up results
8857 in code that is more easily understood. */
8861 /* Advance the base registers to their current locations.
8863 Remember, gprs grow towards smaller register numbers while
8864 fprs grow to higher register numbers. Also remember that
8865 although FP regs are 32-bit addressable, we pretend that
8866 the registers are 64-bits wide. */
8867 gpr_reg_base = 26 - cum->words;
8868 fpr_reg_base = 32 + cum->words;
8870 /* Arguments wider than one word and small aggregates need special
8874 || (type && AGGREGATE_TYPE_P (type)))
8876 /* Double-extended precision (80-bit), quad-precision (128-bit)
8877 and aggregates including complex numbers are aligned on
8878 128-bit boundaries. The first eight 64-bit argument slots
8879 are associated one-to-one, with general registers r26
8880 through r19, and also with floating-point registers fr4
8881 through fr11. Arguments larger than one word are always
8882 passed in general registers.
8884 Using a PARALLEL with a word mode register results in left
8885 justified data on a big-endian target. */
8888 int i, offset = 0, ub = arg_size;
8890 /* Align the base register. */
8891 gpr_reg_base -= alignment;
8893 ub = MIN (ub, max_arg_words - cum->words - alignment);
8894 for (i = 0; i < ub; i++)
8896 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8897 gen_rtx_REG (DImode, gpr_reg_base),
8903 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8908 /* If the argument is larger than a word, then we know precisely
8909 which registers we must use. */
8923 /* Structures 5 to 8 bytes in size are passed in the general
8924 registers in the same manner as other non floating-point
8925 objects. The data is right-justified and zero-extended
8928 This is magic. Normally, using a PARALLEL results in left
8929 justified data on a big-endian target. However, using a
8930 single double-word register provides the required right
8931 justification for 5 to 8 byte structures. This has nothing
8932 to do with the direction of padding specified for the argument.
8933 It has to do with how the data is widened and shifted into
8934 and from the register.
8936 Aside from adding load_multiple and store_multiple patterns,
8937 this is the only way that I have found to obtain right
8938 justification of BLKmode data when it has a size greater
8939 than one word. Splitting the operation into two SImode loads
8940 or returning a DImode REG results in left justified data. */
8941 if (mode == BLKmode)
8943 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8944 gen_rtx_REG (DImode, gpr_reg_base),
8946 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8951 /* We have a single word (32 bits). A simple computation
8952 will get us the register #s we need. */
8953 gpr_reg_base = 26 - cum->words;
8954 fpr_reg_base = 32 + 2 * cum->words;
8958 /* Determine if the argument needs to be passed in both general and
8959 floating point registers. */
8960 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8961 /* If we are doing soft-float with portable runtime, then there
8962 is no need to worry about FP regs. */
8963 && !TARGET_SOFT_FLOAT
8964 /* The parameter must be some kind of float, else we can just
8965 pass it in integer registers. */
8966 && FLOAT_MODE_P (mode)
8967 /* The target function must not have a prototype. */
8968 && cum->nargs_prototype <= 0
8969 /* libcalls do not need to pass items in both FP and general
8971 && type != NULL_TREE
8972 /* All this hair applies to "outgoing" args only. This includes
8973 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8975 /* Also pass outgoing floating arguments in both registers in indirect
8976 calls with the 32 bit ABI and the HP assembler since there is no
8977 way to the specify argument locations in static functions. */
8982 && FLOAT_MODE_P (mode)))
8988 gen_rtx_EXPR_LIST (VOIDmode,
8989 gen_rtx_REG (mode, fpr_reg_base),
8991 gen_rtx_EXPR_LIST (VOIDmode,
8992 gen_rtx_REG (mode, gpr_reg_base),
8997 /* See if we should pass this parameter in a general register. */
8998 if (TARGET_SOFT_FLOAT
8999 /* Indirect calls in the normal 32bit ABI require all arguments
9000 to be passed in general registers. */
9001 || (!TARGET_PORTABLE_RUNTIME
9005 /* If the parameter is not a floating point parameter, then
9006 it belongs in GPRs. */
9007 || !FLOAT_MODE_P (mode))
9008 retval = gen_rtx_REG (mode, gpr_reg_base);
9010 retval = gen_rtx_REG (mode, fpr_reg_base);
9016 /* If this arg would be passed totally in registers or totally on the stack,
9017 then this routine should return zero. It is currently called only for
9018 the 64-bit target. */
9020 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9021 tree type, int named ATTRIBUTE_UNUSED)
9023 unsigned int max_arg_words = 8;
9024 unsigned int offset = 0;
9026 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9029 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9030 /* Arg fits fully into registers. */
9032 else if (cum->words + offset >= max_arg_words)
9033 /* Arg fully on the stack. */
9037 return max_arg_words - cum->words - offset;
9041 /* Return 1 if this is a comparison operator. This allows the use of
9042 MATCH_OPERATOR to recognize all the branch insns. */
9045 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9047 return ((mode == VOIDmode || GET_MODE (op) == mode)
9048 && (GET_CODE (op) == EQ
9049 || GET_CODE (op) == NE
9050 || GET_CODE (op) == GT
9051 || GET_CODE (op) == GTU
9052 || GET_CODE (op) == GE
9053 || GET_CODE (op) == LT
9054 || GET_CODE (op) == LE
9055 || GET_CODE (op) == LEU));
9058 /* On hpux10, the linker will give an error if we have a reference
9059 in the read-only data section to a symbol defined in a shared
9060 library. Therefore, expressions that might require a reloc can
9061 not be placed in the read-only data section. */
9064 pa_select_section (tree exp, int reloc,
9065 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9067 if (TREE_CODE (exp) == VAR_DECL
9068 && TREE_READONLY (exp)
9069 && !TREE_THIS_VOLATILE (exp)
9070 && DECL_INITIAL (exp)
9071 && (DECL_INITIAL (exp) == error_mark_node
9072 || TREE_CONSTANT (DECL_INITIAL (exp)))
9074 readonly_data_section ();
9075 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
9076 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
9078 readonly_data_section ();
9084 pa_globalize_label (FILE *stream, const char *name)
9086 /* We only handle DATA objects here, functions are globalized in
9087 ASM_DECLARE_FUNCTION_NAME. */
9088 if (! FUNCTION_NAME_P (name))
9090 fputs ("\t.EXPORT ", stream);
9091 assemble_name (stream, name);
9092 fputs (",DATA\n", stream);
9097 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9098 int incoming ATTRIBUTE_UNUSED)
9100 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9104 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9106 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9107 PA64 ABI says that objects larger than 128 bits are returned in memory.
9108 Note, int_size_in_bytes can return -1 if the size of the object is
9109 variable or larger than the maximum value that can be expressed as
9110 a HOST_WIDE_INT. It can also return zero for an empty type. The
9111 simplest way to handle variable and empty types is to pass them in
9112 memory. This avoids problems in defining the boundaries of argument
9113 slots, allocating registers, etc. */
9114 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9115 || int_size_in_bytes (type) <= 0);