1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
41 #include "integrate.h"
50 #include "target-def.h"
52 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
54 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
55 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
58 hppa_use_dfa_pipeline_interface ()
63 /* Return nonzero if there is a bypass for the output of
64 OUT_INSN and the fp store IN_INSN. */
66 hppa_fpstore_bypass_p (out_insn, in_insn)
67 rtx out_insn, in_insn;
69 enum machine_mode store_mode;
70 enum machine_mode other_mode;
73 if (recog_memoized (in_insn) < 0
74 || get_attr_type (in_insn) != TYPE_FPSTORE
75 || recog_memoized (out_insn) < 0)
78 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
80 set = single_set (out_insn);
84 other_mode = GET_MODE (SET_SRC (set));
86 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
90 #ifndef DO_FRAME_NOTES
91 #ifdef INCOMING_RETURN_ADDR_RTX
92 #define DO_FRAME_NOTES 1
94 #define DO_FRAME_NOTES 0
98 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
99 static void pa_combine_instructions PARAMS ((rtx));
100 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
101 static int forward_branch_p PARAMS ((rtx));
102 static int shadd_constant_p PARAMS ((int));
103 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
104 static int compute_movstrsi_length PARAMS ((rtx));
105 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
106 static void remove_useless_addtr_insns PARAMS ((rtx, int));
107 static void store_reg PARAMS ((int, int, int));
108 static void store_reg_modify PARAMS ((int, int, int));
109 static void load_reg PARAMS ((int, int, int));
110 static void set_reg_plus_d PARAMS ((int, int, int, int));
111 static void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
112 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
113 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
114 static int pa_adjust_priority PARAMS ((rtx, int));
115 static int pa_issue_rate PARAMS ((void));
116 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
118 static void pa_encode_section_info PARAMS ((tree, int));
119 static const char *pa_strip_name_encoding PARAMS ((const char *));
120 static void pa_globalize_label PARAMS ((FILE *, const char *))
122 static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, tree));
125 /* Save the operands last given to a compare for use when we
126 generate a scc or bcc insn. */
128 rtx hppa_compare_op0, hppa_compare_op1;
129 enum cmp_type hppa_branch_type;
131 /* Which cpu we are scheduling for. */
132 enum processor_type pa_cpu;
134 /* String to hold which cpu we are scheduling for. */
135 const char *pa_cpu_string;
137 /* Which architecture we are generating code for. */
138 enum architecture_type pa_arch;
140 /* String to hold which architecture we are generating code for. */
141 const char *pa_arch_string;
143 /* Counts for the number of callee-saved general and floating point
144 registers which were saved by the current function's prologue. */
145 static int gr_saved, fr_saved;
147 static rtx find_addr_reg PARAMS ((rtx));
149 /* Keep track of the number of bytes we have output in the CODE subspaces
150 during this compilation so we'll know when to emit inline long-calls. */
152 unsigned int total_code_bytes;
154 /* Variables to handle plabels that we discover are necessary at assembly
155 output time. They are output after the current function. */
157 struct deferred_plabel GTY(())
162 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
164 static size_t n_deferred_plabels = 0;
166 /* Initialize the GCC target structure. */
168 #undef TARGET_ASM_ALIGNED_HI_OP
169 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
170 #undef TARGET_ASM_ALIGNED_SI_OP
171 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
172 #undef TARGET_ASM_ALIGNED_DI_OP
173 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
174 #undef TARGET_ASM_UNALIGNED_HI_OP
175 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
176 #undef TARGET_ASM_UNALIGNED_SI_OP
177 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
178 #undef TARGET_ASM_UNALIGNED_DI_OP
179 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
180 #undef TARGET_ASM_INTEGER
181 #define TARGET_ASM_INTEGER pa_assemble_integer
183 #undef TARGET_ASM_FUNCTION_PROLOGUE
184 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
185 #undef TARGET_ASM_FUNCTION_EPILOGUE
186 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
188 #undef TARGET_SCHED_ADJUST_COST
189 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
190 #undef TARGET_SCHED_ADJUST_PRIORITY
191 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
192 #undef TARGET_SCHED_ISSUE_RATE
193 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
195 #undef TARGET_ENCODE_SECTION_INFO
196 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
197 #undef TARGET_STRIP_NAME_ENCODING
198 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
200 #undef TARGET_ASM_OUTPUT_MI_THUNK
201 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
203 struct gcc_target targetm = TARGET_INITIALIZER;
208 if (pa_cpu_string == NULL)
209 pa_cpu_string = TARGET_SCHED_DEFAULT;
211 if (! strcmp (pa_cpu_string, "8000"))
213 pa_cpu_string = "8000";
214 pa_cpu = PROCESSOR_8000;
216 else if (! strcmp (pa_cpu_string, "7100"))
218 pa_cpu_string = "7100";
219 pa_cpu = PROCESSOR_7100;
221 else if (! strcmp (pa_cpu_string, "700"))
223 pa_cpu_string = "700";
224 pa_cpu = PROCESSOR_700;
226 else if (! strcmp (pa_cpu_string, "7100LC"))
228 pa_cpu_string = "7100LC";
229 pa_cpu = PROCESSOR_7100LC;
231 else if (! strcmp (pa_cpu_string, "7200"))
233 pa_cpu_string = "7200";
234 pa_cpu = PROCESSOR_7200;
236 else if (! strcmp (pa_cpu_string, "7300"))
238 pa_cpu_string = "7300";
239 pa_cpu = PROCESSOR_7300;
243 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
246 /* Set the instruction set architecture. */
247 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
249 pa_arch_string = "1.0";
250 pa_arch = ARCHITECTURE_10;
251 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
253 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
255 pa_arch_string = "1.1";
256 pa_arch = ARCHITECTURE_11;
257 target_flags &= ~MASK_PA_20;
258 target_flags |= MASK_PA_11;
260 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
262 pa_arch_string = "2.0";
263 pa_arch = ARCHITECTURE_20;
264 target_flags |= MASK_PA_11 | MASK_PA_20;
266 else if (pa_arch_string)
268 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
271 /* Unconditional branches in the delay slot are not compatible with dwarf2
272 call frame information. There is no benefit in using this optimization
273 on PA8000 and later processors. */
274 if (pa_cpu >= PROCESSOR_8000
275 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
276 || flag_unwind_tables)
277 target_flags &= ~MASK_JUMP_IN_DELAY;
279 if (flag_pic && TARGET_PORTABLE_RUNTIME)
281 warning ("PIC code generation is not supported in the portable runtime model\n");
284 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
286 warning ("PIC code generation is not compatible with fast indirect calls\n");
289 if (! TARGET_GAS && write_symbols != NO_DEBUG)
291 warning ("-g is only supported when using GAS on this processor,");
292 warning ("-g option disabled");
293 write_symbols = NO_DEBUG;
296 /* We only support the "big PIC" model now. And we always generate PIC
297 code when in 64bit mode. */
298 if (flag_pic == 1 || TARGET_64BIT)
301 /* We can't guarantee that .dword is available for 32-bit targets. */
302 if (UNITS_PER_WORD == 4)
303 targetm.asm_out.aligned_op.di = NULL;
305 /* The unaligned ops are only available when using GAS. */
308 targetm.asm_out.unaligned_op.hi = NULL;
309 targetm.asm_out.unaligned_op.si = NULL;
310 targetm.asm_out.unaligned_op.di = NULL;
314 /* Return nonzero only if OP is a register of mode MODE,
317 reg_or_0_operand (op, mode)
319 enum machine_mode mode;
321 return (op == CONST0_RTX (mode) || register_operand (op, mode));
324 /* Return nonzero if OP is suitable for use in a call to a named
327 For 2.5 try to eliminate either call_operand_address or
328 function_label_operand, they perform very similar functions. */
330 call_operand_address (op, mode)
332 enum machine_mode mode ATTRIBUTE_UNUSED;
334 return (GET_MODE (op) == word_mode
335 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
338 /* Return 1 if X contains a symbolic expression. We know these
339 expressions will have one of a few well defined forms, so
340 we need only check those forms. */
342 symbolic_expression_p (x)
346 /* Strip off any HIGH. */
347 if (GET_CODE (x) == HIGH)
350 return (symbolic_operand (x, VOIDmode));
354 symbolic_operand (op, mode)
356 enum machine_mode mode ATTRIBUTE_UNUSED;
358 switch (GET_CODE (op))
365 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
366 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
367 && GET_CODE (XEXP (op, 1)) == CONST_INT);
373 /* Return truth value of statement that OP is a symbolic memory
374 operand of mode MODE. */
377 symbolic_memory_operand (op, mode)
379 enum machine_mode mode ATTRIBUTE_UNUSED;
381 if (GET_CODE (op) == SUBREG)
382 op = SUBREG_REG (op);
383 if (GET_CODE (op) != MEM)
386 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
387 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
390 /* Return 1 if the operand is either a register or a memory operand that is
394 reg_or_nonsymb_mem_operand (op, mode)
396 enum machine_mode mode;
398 if (register_operand (op, mode))
401 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
407 /* Return 1 if the operand is either a register, zero, or a memory operand
408 that is not symbolic. */
411 reg_or_0_or_nonsymb_mem_operand (op, mode)
413 enum machine_mode mode;
415 if (register_operand (op, mode))
418 if (op == CONST0_RTX (mode))
421 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
427 /* Return 1 if the operand is a register operand or a non-symbolic memory
428 operand after reload. This predicate is used for branch patterns that
429 internally handle register reloading. We need to accept non-symbolic
430 memory operands after reload to ensure that the pattern is still valid
431 if reload didn't find a hard register for the operand. */
434 reg_before_reload_operand (op, mode)
436 enum machine_mode mode;
438 /* Don't accept a SUBREG since it will need a reload. */
439 if (GET_CODE (op) == SUBREG)
442 if (register_operand (op, mode))
446 && memory_operand (op, mode)
447 && ! symbolic_memory_operand (op, mode))
453 /* Accept any constant that can be moved in one instruction into a
456 cint_ok_for_move (intval)
457 HOST_WIDE_INT intval;
459 /* OK if ldo, ldil, or zdepi, can be used. */
460 return (CONST_OK_FOR_LETTER_P (intval, 'J')
461 || CONST_OK_FOR_LETTER_P (intval, 'N')
462 || CONST_OK_FOR_LETTER_P (intval, 'K'));
465 /* Accept anything that can be moved in one instruction into a general
468 move_operand (op, mode)
470 enum machine_mode mode;
472 if (register_operand (op, mode))
475 if (GET_CODE (op) == CONSTANT_P_RTX)
478 if (GET_CODE (op) == CONST_INT)
479 return cint_ok_for_move (INTVAL (op));
481 if (GET_CODE (op) == SUBREG)
482 op = SUBREG_REG (op);
483 if (GET_CODE (op) != MEM)
488 /* We consider a LO_SUM DLT reference a move_operand now since it has
489 been merged into the normal movsi/movdi patterns. */
490 if (GET_CODE (op) == LO_SUM
491 && GET_CODE (XEXP (op, 0)) == REG
492 && REG_OK_FOR_BASE_P (XEXP (op, 0))
493 && GET_CODE (XEXP (op, 1)) == UNSPEC
494 && GET_MODE (op) == Pmode)
497 /* Since move_operand is only used for source operands, we can always
498 allow scaled indexing! */
499 if (! TARGET_DISABLE_INDEXING
500 && GET_CODE (op) == PLUS
501 && ((GET_CODE (XEXP (op, 0)) == MULT
502 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
503 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
504 && INTVAL (XEXP (XEXP (op, 0), 1))
505 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
506 && GET_CODE (XEXP (op, 1)) == REG)
507 || (GET_CODE (XEXP (op, 1)) == MULT
508 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
509 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
510 && INTVAL (XEXP (XEXP (op, 1), 1))
511 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
512 && GET_CODE (XEXP (op, 0)) == REG)))
515 return memory_address_p (mode, op);
518 /* Accept REG and any CONST_INT that can be moved in one instruction into a
521 reg_or_cint_move_operand (op, mode)
523 enum machine_mode mode;
525 if (register_operand (op, mode))
528 if (GET_CODE (op) == CONST_INT)
529 return cint_ok_for_move (INTVAL (op));
535 pic_label_operand (op, mode)
537 enum machine_mode mode ATTRIBUTE_UNUSED;
542 switch (GET_CODE (op))
548 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
549 && GET_CODE (XEXP (op, 1)) == CONST_INT);
556 fp_reg_operand (op, mode)
558 enum machine_mode mode ATTRIBUTE_UNUSED;
560 return reg_renumber && FP_REG_P (op);
565 /* Return truth value of whether OP can be used as an operand in a
566 three operand arithmetic insn that accepts registers of mode MODE
567 or 14-bit signed integers. */
569 arith_operand (op, mode)
571 enum machine_mode mode;
573 return (register_operand (op, mode)
574 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
577 /* Return truth value of whether OP can be used as an operand in a
578 three operand arithmetic insn that accepts registers of mode MODE
579 or 11-bit signed integers. */
581 arith11_operand (op, mode)
583 enum machine_mode mode;
585 return (register_operand (op, mode)
586 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
589 /* Return truth value of whether OP can be used as an operand in a
592 adddi3_operand (op, mode)
594 enum machine_mode mode;
596 return (register_operand (op, mode)
597 || (GET_CODE (op) == CONST_INT
598 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
601 /* A constant integer suitable for use in a PRE_MODIFY memory
604 pre_cint_operand (op, mode)
606 enum machine_mode mode ATTRIBUTE_UNUSED;
608 return (GET_CODE (op) == CONST_INT
609 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
612 /* A constant integer suitable for use in a POST_MODIFY memory
615 post_cint_operand (op, mode)
617 enum machine_mode mode ATTRIBUTE_UNUSED;
619 return (GET_CODE (op) == CONST_INT
620 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
624 arith_double_operand (op, mode)
626 enum machine_mode mode;
628 return (register_operand (op, mode)
629 || (GET_CODE (op) == CONST_DOUBLE
630 && GET_MODE (op) == mode
631 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
632 && ((CONST_DOUBLE_HIGH (op) >= 0)
633 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
636 /* Return truth value of whether OP is an integer which fits the
637 range constraining immediate operands in three-address insns, or
638 is an integer register. */
641 ireg_or_int5_operand (op, mode)
643 enum machine_mode mode ATTRIBUTE_UNUSED;
645 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
646 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
649 /* Return nonzero if OP is an integer register, else return zero. */
651 ireg_operand (op, mode)
653 enum machine_mode mode ATTRIBUTE_UNUSED;
655 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
658 /* Return truth value of whether OP is an integer which fits the
659 range constraining immediate operands in three-address insns. */
662 int5_operand (op, mode)
664 enum machine_mode mode ATTRIBUTE_UNUSED;
666 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
670 uint5_operand (op, mode)
672 enum machine_mode mode ATTRIBUTE_UNUSED;
674 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
678 int11_operand (op, mode)
680 enum machine_mode mode ATTRIBUTE_UNUSED;
682 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
686 uint32_operand (op, mode)
688 enum machine_mode mode ATTRIBUTE_UNUSED;
690 #if HOST_BITS_PER_WIDE_INT > 32
691 /* All allowed constants will fit a CONST_INT. */
692 return (GET_CODE (op) == CONST_INT
693 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
695 return (GET_CODE (op) == CONST_INT
696 || (GET_CODE (op) == CONST_DOUBLE
697 && CONST_DOUBLE_HIGH (op) == 0));
702 arith5_operand (op, mode)
704 enum machine_mode mode;
706 return register_operand (op, mode) || int5_operand (op, mode);
709 /* True iff zdepi can be used to generate this CONST_INT.
710 zdepi first sign extends a 5 bit signed number to a given field
711 length, then places this field anywhere in a zero. */
714 unsigned HOST_WIDE_INT x;
716 unsigned HOST_WIDE_INT lsb_mask, t;
718 /* This might not be obvious, but it's at least fast.
719 This function is critical; we don't have the time loops would take. */
721 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
722 /* Return true iff t is a power of two. */
723 return ((t & (t - 1)) == 0);
726 /* True iff depi or extru can be used to compute (reg & mask).
727 Accept bit pattern like these:
733 unsigned HOST_WIDE_INT mask;
736 mask += mask & -mask;
737 return (mask & (mask - 1)) == 0;
740 /* True iff depi or extru can be used to compute (reg & OP). */
742 and_operand (op, mode)
744 enum machine_mode mode;
746 return (register_operand (op, mode)
747 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
750 /* True iff depi can be used to compute (reg | MASK). */
753 unsigned HOST_WIDE_INT mask;
755 mask += mask & -mask;
756 return (mask & (mask - 1)) == 0;
759 /* True iff depi can be used to compute (reg | OP). */
761 ior_operand (op, mode)
763 enum machine_mode mode ATTRIBUTE_UNUSED;
765 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
769 lhs_lshift_operand (op, mode)
771 enum machine_mode mode;
773 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
776 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
777 Such values can be the left hand side x in (x << r), using the zvdepi
780 lhs_lshift_cint_operand (op, mode)
782 enum machine_mode mode ATTRIBUTE_UNUSED;
784 unsigned HOST_WIDE_INT x;
785 if (GET_CODE (op) != CONST_INT)
787 x = INTVAL (op) >> 4;
788 return (x & (x + 1)) == 0;
792 arith32_operand (op, mode)
794 enum machine_mode mode;
796 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
800 pc_or_label_operand (op, mode)
802 enum machine_mode mode ATTRIBUTE_UNUSED;
804 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
807 /* Legitimize PIC addresses. If the address is already
808 position-independent, we return ORIG. Newly generated
809 position-independent addresses go to REG. If we need more
810 than one register, we lose. */
813 legitimize_pic_address (orig, mode, reg)
815 enum machine_mode mode;
819 /* Labels need special handling. */
820 if (pic_label_operand (orig, mode))
822 /* We do not want to go through the movXX expanders here since that
823 would create recursion.
825 Nor do we really want to call a generator for a named pattern
826 since that requires multiple patterns if we want to support
829 So instead we just emit the raw set, which avoids the movXX
830 expanders completely. */
831 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
832 current_function_uses_pic_offset_table = 1;
835 if (GET_CODE (orig) == SYMBOL_REF)
841 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
842 gen_rtx_HIGH (word_mode, orig)));
844 = gen_rtx_MEM (Pmode,
845 gen_rtx_LO_SUM (Pmode, reg,
846 gen_rtx_UNSPEC (Pmode,
850 current_function_uses_pic_offset_table = 1;
851 RTX_UNCHANGING_P (pic_ref) = 1;
852 emit_move_insn (reg, pic_ref);
855 else if (GET_CODE (orig) == CONST)
859 if (GET_CODE (XEXP (orig, 0)) == PLUS
860 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
866 if (GET_CODE (XEXP (orig, 0)) == PLUS)
868 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
869 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
870 base == reg ? 0 : reg);
873 if (GET_CODE (orig) == CONST_INT)
875 if (INT_14_BITS (orig))
876 return plus_constant (base, INTVAL (orig));
877 orig = force_reg (Pmode, orig);
879 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
880 /* Likewise, should we set special REG_NOTEs here? */
885 /* Try machine-dependent ways of modifying an illegitimate address
886 to be legitimate. If we find one, return the new, valid address.
887 This macro is used in only one place: `memory_address' in explow.c.
889 OLDX is the address as it was before break_out_memory_refs was called.
890 In some cases it is useful to look at this to decide what needs to be done.
892 MODE and WIN are passed so that this macro can use
893 GO_IF_LEGITIMATE_ADDRESS.
895 It is always safe for this macro to do nothing. It exists to recognize
896 opportunities to optimize the output.
898 For the PA, transform:
900 memory(X + <large int>)
904 if (<large int> & mask) >= 16
905 Y = (<large int> & ~mask) + mask + 1 Round up.
907 Y = (<large int> & ~mask) Round down.
909 memory (Z + (<large int> - Y));
911 This is for CSE to find several similar references, and only use one Z.
913 X can either be a SYMBOL_REF or REG, but because combine can not
914 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
915 D will not fit in 14 bits.
917 MODE_FLOAT references allow displacements which fit in 5 bits, so use
920 MODE_INT references allow displacements which fit in 14 bits, so use
923 This relies on the fact that most mode MODE_FLOAT references will use FP
924 registers and most mode MODE_INT references will use integer registers.
925 (In the rare case of an FP register used in an integer MODE, we depend
926 on secondary reloads to clean things up.)
929 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
930 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
931 addressing modes to be used).
933 Put X and Z into registers. Then put the entire expression into
937 hppa_legitimize_address (x, oldx, mode)
938 rtx x, oldx ATTRIBUTE_UNUSED;
939 enum machine_mode mode;
944 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
946 /* Strip off CONST. */
947 if (GET_CODE (x) == CONST)
950 /* Special case. Get the SYMBOL_REF into a register and use indexing.
951 That should always be safe. */
952 if (GET_CODE (x) == PLUS
953 && GET_CODE (XEXP (x, 0)) == REG
954 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
956 rtx reg = force_reg (Pmode, XEXP (x, 1));
957 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
960 /* Note we must reject symbols which represent function addresses
961 since the assembler/linker can't handle arithmetic on plabels. */
962 if (GET_CODE (x) == PLUS
963 && GET_CODE (XEXP (x, 1)) == CONST_INT
964 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
965 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
966 || GET_CODE (XEXP (x, 0)) == REG))
968 rtx int_part, ptr_reg;
970 int offset = INTVAL (XEXP (x, 1));
973 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
974 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
976 /* Choose which way to round the offset. Round up if we
977 are >= halfway to the next boundary. */
978 if ((offset & mask) >= ((mask + 1) / 2))
979 newoffset = (offset & ~ mask) + mask + 1;
981 newoffset = (offset & ~ mask);
983 /* If the newoffset will not fit in 14 bits (ldo), then
984 handling this would take 4 or 5 instructions (2 to load
985 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
986 add the new offset and the SYMBOL_REF.) Combine can
987 not handle 4->2 or 5->2 combinations, so do not create
989 if (! VAL_14_BITS_P (newoffset)
990 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
992 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
995 gen_rtx_HIGH (Pmode, const_part));
998 gen_rtx_LO_SUM (Pmode,
999 tmp_reg, const_part));
1003 if (! VAL_14_BITS_P (newoffset))
1004 int_part = force_reg (Pmode, GEN_INT (newoffset));
1006 int_part = GEN_INT (newoffset);
1008 ptr_reg = force_reg (Pmode,
1009 gen_rtx_PLUS (Pmode,
1010 force_reg (Pmode, XEXP (x, 0)),
1013 return plus_constant (ptr_reg, offset - newoffset);
1016 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1018 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1019 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1020 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1021 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1022 || GET_CODE (XEXP (x, 1)) == SUBREG)
1023 && GET_CODE (XEXP (x, 1)) != CONST)
1025 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1029 if (GET_CODE (reg1) != REG)
1030 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1032 reg2 = XEXP (XEXP (x, 0), 0);
1033 if (GET_CODE (reg2) != REG)
1034 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1036 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1037 gen_rtx_MULT (Pmode,
1043 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1045 Only do so for floating point modes since this is more speculative
1046 and we lose if it's an integer store. */
1047 if (GET_CODE (x) == PLUS
1048 && GET_CODE (XEXP (x, 0)) == PLUS
1049 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1050 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1051 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1052 && (mode == SFmode || mode == DFmode))
1055 /* First, try and figure out what to use as a base register. */
1056 rtx reg1, reg2, base, idx, orig_base;
1058 reg1 = XEXP (XEXP (x, 0), 1);
1063 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1064 then emit_move_sequence will turn on REG_POINTER so we'll know
1065 it's a base register below. */
1066 if (GET_CODE (reg1) != REG)
1067 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1069 if (GET_CODE (reg2) != REG)
1070 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1072 /* Figure out what the base and index are. */
1074 if (GET_CODE (reg1) == REG
1075 && REG_POINTER (reg1))
1078 orig_base = XEXP (XEXP (x, 0), 1);
1079 idx = gen_rtx_PLUS (Pmode,
1080 gen_rtx_MULT (Pmode,
1081 XEXP (XEXP (XEXP (x, 0), 0), 0),
1082 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1085 else if (GET_CODE (reg2) == REG
1086 && REG_POINTER (reg2))
1089 orig_base = XEXP (x, 1);
1096 /* If the index adds a large constant, try to scale the
1097 constant so that it can be loaded with only one insn. */
1098 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1099 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1100 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1101 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1103 /* Divide the CONST_INT by the scale factor, then add it to A. */
1104 int val = INTVAL (XEXP (idx, 1));
1106 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1107 reg1 = XEXP (XEXP (idx, 0), 0);
1108 if (GET_CODE (reg1) != REG)
1109 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1111 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1113 /* We can now generate a simple scaled indexed address. */
1116 (Pmode, gen_rtx_PLUS (Pmode,
1117 gen_rtx_MULT (Pmode, reg1,
1118 XEXP (XEXP (idx, 0), 1)),
1122 /* If B + C is still a valid base register, then add them. */
1123 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1124 && INTVAL (XEXP (idx, 1)) <= 4096
1125 && INTVAL (XEXP (idx, 1)) >= -4096)
1127 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1130 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1132 reg2 = XEXP (XEXP (idx, 0), 0);
1133 if (GET_CODE (reg2) != CONST_INT)
1134 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1136 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1137 gen_rtx_MULT (Pmode,
1143 /* Get the index into a register, then add the base + index and
1144 return a register holding the result. */
1146 /* First get A into a register. */
1147 reg1 = XEXP (XEXP (idx, 0), 0);
1148 if (GET_CODE (reg1) != REG)
1149 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1151 /* And get B into a register. */
1152 reg2 = XEXP (idx, 1);
1153 if (GET_CODE (reg2) != REG)
1154 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1156 reg1 = force_reg (Pmode,
1157 gen_rtx_PLUS (Pmode,
1158 gen_rtx_MULT (Pmode, reg1,
1159 XEXP (XEXP (idx, 0), 1)),
1162 /* Add the result to our base register and return. */
1163 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1167 /* Uh-oh. We might have an address for x[n-100000]. This needs
1168 special handling to avoid creating an indexed memory address
1169 with x-100000 as the base.
1171 If the constant part is small enough, then it's still safe because
1172 there is a guard page at the beginning and end of the data segment.
1174 Scaled references are common enough that we want to try and rearrange the
1175 terms so that we can use indexing for these addresses too. Only
1176 do the optimization for floatint point modes. */
1178 if (GET_CODE (x) == PLUS
1179 && symbolic_expression_p (XEXP (x, 1)))
1181 /* Ugly. We modify things here so that the address offset specified
1182 by the index expression is computed first, then added to x to form
1183 the entire address. */
1185 rtx regx1, regx2, regy1, regy2, y;
1187 /* Strip off any CONST. */
1189 if (GET_CODE (y) == CONST)
1192 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1194 /* See if this looks like
1195 (plus (mult (reg) (shadd_const))
1196 (const (plus (symbol_ref) (const_int))))
1198 Where const_int is small. In that case the const
1199 expression is a valid pointer for indexing.
1201 If const_int is big, but can be divided evenly by shadd_const
1202 and added to (reg). This allows more scaled indexed addresses. */
1203 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1204 && GET_CODE (XEXP (x, 0)) == MULT
1205 && GET_CODE (XEXP (y, 1)) == CONST_INT
1206 && INTVAL (XEXP (y, 1)) >= -4096
1207 && INTVAL (XEXP (y, 1)) <= 4095
1208 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1209 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1211 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1215 if (GET_CODE (reg1) != REG)
1216 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1218 reg2 = XEXP (XEXP (x, 0), 0);
1219 if (GET_CODE (reg2) != REG)
1220 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1222 return force_reg (Pmode,
1223 gen_rtx_PLUS (Pmode,
1224 gen_rtx_MULT (Pmode,
1229 else if ((mode == DFmode || mode == SFmode)
1230 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1231 && GET_CODE (XEXP (x, 0)) == MULT
1232 && GET_CODE (XEXP (y, 1)) == CONST_INT
1233 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1234 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1235 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1238 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1239 / INTVAL (XEXP (XEXP (x, 0), 1))));
1240 regx2 = XEXP (XEXP (x, 0), 0);
1241 if (GET_CODE (regx2) != REG)
1242 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1243 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1247 gen_rtx_PLUS (Pmode,
1248 gen_rtx_MULT (Pmode, regx2,
1249 XEXP (XEXP (x, 0), 1)),
1250 force_reg (Pmode, XEXP (y, 0))));
1252 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1253 && INTVAL (XEXP (y, 1)) >= -4096
1254 && INTVAL (XEXP (y, 1)) <= 4095)
1256 /* This is safe because of the guard page at the
1257 beginning and end of the data space. Just
1258 return the original address. */
1263 /* Doesn't look like one we can optimize. */
1264 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1265 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1266 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1267 regx1 = force_reg (Pmode,
1268 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1270 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1278 /* For the HPPA, REG and REG+CONST is cost 0
1279 and addresses involving symbolic constants are cost 2.
1281 PIC addresses are very expensive.
1283 It is no coincidence that this has the same structure
1284 as GO_IF_LEGITIMATE_ADDRESS. */
1286 hppa_address_cost (X)
1289 if (GET_CODE (X) == PLUS)
1291 else if (GET_CODE (X) == LO_SUM)
1293 else if (GET_CODE (X) == HIGH)
1298 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1299 new rtx with the correct mode. */
1301 force_mode (mode, orig)
1302 enum machine_mode mode;
1305 if (mode == GET_MODE (orig))
1308 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1311 return gen_rtx_REG (mode, REGNO (orig));
1314 /* Emit insns to move operands[1] into operands[0].
1316 Return 1 if we have written out everything that needs to be done to
1317 do the move. Otherwise, return 0 and the caller will emit the move
1320 Note SCRATCH_REG may not be in the proper mode depending on how it
1321 will be used. This routine is resposible for creating a new copy
1322 of SCRATCH_REG in the proper mode. */
1325 emit_move_sequence (operands, mode, scratch_reg)
1327 enum machine_mode mode;
1330 register rtx operand0 = operands[0];
1331 register rtx operand1 = operands[1];
1335 && reload_in_progress && GET_CODE (operand0) == REG
1336 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1337 operand0 = reg_equiv_mem[REGNO (operand0)];
1338 else if (scratch_reg
1339 && reload_in_progress && GET_CODE (operand0) == SUBREG
1340 && GET_CODE (SUBREG_REG (operand0)) == REG
1341 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1343 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1344 the code which tracks sets/uses for delete_output_reload. */
1345 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1346 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1347 SUBREG_BYTE (operand0));
1348 operand0 = alter_subreg (&temp);
1352 && reload_in_progress && GET_CODE (operand1) == REG
1353 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1354 operand1 = reg_equiv_mem[REGNO (operand1)];
1355 else if (scratch_reg
1356 && reload_in_progress && GET_CODE (operand1) == SUBREG
1357 && GET_CODE (SUBREG_REG (operand1)) == REG
1358 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1360 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1361 the code which tracks sets/uses for delete_output_reload. */
1362 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1363 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1364 SUBREG_BYTE (operand1));
1365 operand1 = alter_subreg (&temp);
1368 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1369 && ((tem = find_replacement (&XEXP (operand0, 0)))
1370 != XEXP (operand0, 0)))
1371 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1372 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1373 && ((tem = find_replacement (&XEXP (operand1, 0)))
1374 != XEXP (operand1, 0)))
1375 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1377 /* Handle secondary reloads for loads/stores of FP registers from
1378 REG+D addresses where D does not fit in 5 bits, including
1379 (subreg (mem (addr))) cases. */
1380 if (fp_reg_operand (operand0, mode)
1381 && ((GET_CODE (operand1) == MEM
1382 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1383 || ((GET_CODE (operand1) == SUBREG
1384 && GET_CODE (XEXP (operand1, 0)) == MEM
1385 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1388 if (GET_CODE (operand1) == SUBREG)
1389 operand1 = XEXP (operand1, 0);
1391 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1392 it in WORD_MODE regardless of what mode it was originally given
1394 scratch_reg = force_mode (word_mode, scratch_reg);
1396 /* D might not fit in 14 bits either; for such cases load D into
1398 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1400 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1401 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1403 XEXP (XEXP (operand1, 0), 0),
1407 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1408 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1409 gen_rtx_MEM (mode, scratch_reg)));
1412 else if (fp_reg_operand (operand1, mode)
1413 && ((GET_CODE (operand0) == MEM
1414 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1415 || ((GET_CODE (operand0) == SUBREG)
1416 && GET_CODE (XEXP (operand0, 0)) == MEM
1417 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1420 if (GET_CODE (operand0) == SUBREG)
1421 operand0 = XEXP (operand0, 0);
1423 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1424 it in WORD_MODE regardless of what mode it was originally given
1426 scratch_reg = force_mode (word_mode, scratch_reg);
1428 /* D might not fit in 14 bits either; for such cases load D into
1430 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1432 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1433 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1436 XEXP (XEXP (operand0, 0),
1441 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1442 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1446 /* Handle secondary reloads for loads of FP registers from constant
1447 expressions by forcing the constant into memory.
1449 use scratch_reg to hold the address of the memory location.
1451 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1452 NO_REGS when presented with a const_int and an register class
1453 containing only FP registers. Doing so unfortunately creates
1454 more problems than it solves. Fix this for 2.5. */
1455 else if (fp_reg_operand (operand0, mode)
1456 && CONSTANT_P (operand1)
1461 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1462 it in WORD_MODE regardless of what mode it was originally given
1464 scratch_reg = force_mode (word_mode, scratch_reg);
1466 /* Force the constant into memory and put the address of the
1467 memory location into scratch_reg. */
1468 xoperands[0] = scratch_reg;
1469 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1470 emit_move_sequence (xoperands, Pmode, 0);
1472 /* Now load the destination register. */
1473 emit_insn (gen_rtx_SET (mode, operand0,
1474 gen_rtx_MEM (mode, scratch_reg)));
1477 /* Handle secondary reloads for SAR. These occur when trying to load
1478 the SAR from memory, FP register, or with a constant. */
1479 else if (GET_CODE (operand0) == REG
1480 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1481 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1482 && (GET_CODE (operand1) == MEM
1483 || GET_CODE (operand1) == CONST_INT
1484 || (GET_CODE (operand1) == REG
1485 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1488 /* D might not fit in 14 bits either; for such cases load D into
1490 if (GET_CODE (operand1) == MEM
1491 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1493 /* We are reloading the address into the scratch register, so we
1494 want to make sure the scratch register is a full register. */
1495 scratch_reg = force_mode (word_mode, scratch_reg);
1497 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1498 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1501 XEXP (XEXP (operand1, 0),
1505 /* Now we are going to load the scratch register from memory,
1506 we want to load it in the same width as the original MEM,
1507 which must be the same as the width of the ultimate destination,
1509 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1511 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1516 /* We want to load the scratch register using the same mode as
1517 the ultimate destination. */
1518 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1520 emit_move_insn (scratch_reg, operand1);
1523 /* And emit the insn to set the ultimate destination. We know that
1524 the scratch register has the same mode as the destination at this
1526 emit_move_insn (operand0, scratch_reg);
1529 /* Handle most common case: storing into a register. */
1530 else if (register_operand (operand0, mode))
1532 if (register_operand (operand1, mode)
1533 || (GET_CODE (operand1) == CONST_INT
1534 && cint_ok_for_move (INTVAL (operand1)))
1535 || (operand1 == CONST0_RTX (mode))
1536 || (GET_CODE (operand1) == HIGH
1537 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1538 /* Only `general_operands' can come here, so MEM is ok. */
1539 || GET_CODE (operand1) == MEM)
1541 /* Run this case quickly. */
1542 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1546 else if (GET_CODE (operand0) == MEM)
1548 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1549 && !(reload_in_progress || reload_completed))
1551 rtx temp = gen_reg_rtx (DFmode);
1553 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1554 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1557 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1559 /* Run this case quickly. */
1560 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1563 if (! (reload_in_progress || reload_completed))
1565 operands[0] = validize_mem (operand0);
1566 operands[1] = operand1 = force_reg (mode, operand1);
1570 /* Simplify the source if we need to.
1571 Note we do have to handle function labels here, even though we do
1572 not consider them legitimate constants. Loop optimizations can
1573 call the emit_move_xxx with one as a source. */
1574 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1575 || function_label_operand (operand1, mode)
1576 || (GET_CODE (operand1) == HIGH
1577 && symbolic_operand (XEXP (operand1, 0), mode)))
1581 if (GET_CODE (operand1) == HIGH)
1584 operand1 = XEXP (operand1, 0);
1586 if (symbolic_operand (operand1, mode))
1588 /* Argh. The assembler and linker can't handle arithmetic
1591 So we force the plabel into memory, load operand0 from
1592 the memory location, then add in the constant part. */
1593 if ((GET_CODE (operand1) == CONST
1594 && GET_CODE (XEXP (operand1, 0)) == PLUS
1595 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1596 || function_label_operand (operand1, mode))
1598 rtx temp, const_part;
1600 /* Figure out what (if any) scratch register to use. */
1601 if (reload_in_progress || reload_completed)
1603 scratch_reg = scratch_reg ? scratch_reg : operand0;
1604 /* SCRATCH_REG will hold an address and maybe the actual
1605 data. We want it in WORD_MODE regardless of what mode it
1606 was originally given to us. */
1607 scratch_reg = force_mode (word_mode, scratch_reg);
1610 scratch_reg = gen_reg_rtx (Pmode);
1612 if (GET_CODE (operand1) == CONST)
1614 /* Save away the constant part of the expression. */
1615 const_part = XEXP (XEXP (operand1, 0), 1);
1616 if (GET_CODE (const_part) != CONST_INT)
1619 /* Force the function label into memory. */
1620 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1624 /* No constant part. */
1625 const_part = NULL_RTX;
1627 /* Force the function label into memory. */
1628 temp = force_const_mem (mode, operand1);
1632 /* Get the address of the memory location. PIC-ify it if
1634 temp = XEXP (temp, 0);
1636 temp = legitimize_pic_address (temp, mode, scratch_reg);
1638 /* Put the address of the memory location into our destination
1641 emit_move_sequence (operands, mode, scratch_reg);
1643 /* Now load from the memory location into our destination
1645 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1646 emit_move_sequence (operands, mode, scratch_reg);
1648 /* And add back in the constant part. */
1649 if (const_part != NULL_RTX)
1650 expand_inc (operand0, const_part);
1659 if (reload_in_progress || reload_completed)
1661 temp = scratch_reg ? scratch_reg : operand0;
1662 /* TEMP will hold an address and maybe the actual
1663 data. We want it in WORD_MODE regardless of what mode it
1664 was originally given to us. */
1665 temp = force_mode (word_mode, temp);
1668 temp = gen_reg_rtx (Pmode);
1670 /* (const (plus (symbol) (const_int))) must be forced to
1671 memory during/after reload if the const_int will not fit
1673 if (GET_CODE (operand1) == CONST
1674 && GET_CODE (XEXP (operand1, 0)) == PLUS
1675 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1676 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1677 && (reload_completed || reload_in_progress)
1680 operands[1] = force_const_mem (mode, operand1);
1681 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1683 emit_move_sequence (operands, mode, temp);
1687 operands[1] = legitimize_pic_address (operand1, mode, temp);
1688 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1691 /* On the HPPA, references to data space are supposed to use dp,
1692 register 27, but showing it in the RTL inhibits various cse
1693 and loop optimizations. */
1698 if (reload_in_progress || reload_completed)
1700 temp = scratch_reg ? scratch_reg : operand0;
1701 /* TEMP will hold an address and maybe the actual
1702 data. We want it in WORD_MODE regardless of what mode it
1703 was originally given to us. */
1704 temp = force_mode (word_mode, temp);
1707 temp = gen_reg_rtx (mode);
1709 /* Loading a SYMBOL_REF into a register makes that register
1710 safe to be used as the base in an indexed address.
1712 Don't mark hard registers though. That loses. */
1713 if (GET_CODE (operand0) == REG
1714 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1715 REG_POINTER (operand0) = 1;
1716 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1717 REG_POINTER (temp) = 1;
1719 set = gen_rtx_SET (mode, operand0, temp);
1721 set = gen_rtx_SET (VOIDmode,
1723 gen_rtx_LO_SUM (mode, temp, operand1));
1725 emit_insn (gen_rtx_SET (VOIDmode,
1727 gen_rtx_HIGH (mode, operand1)));
1733 else if (GET_CODE (operand1) != CONST_INT
1734 || ! cint_ok_for_move (INTVAL (operand1)))
1736 rtx extend = NULL_RTX;
1739 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1740 && HOST_BITS_PER_WIDE_INT > 32
1741 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1743 HOST_WIDE_INT val = INTVAL (operand1);
1746 /* Extract the low order 32 bits of the value and sign extend.
1747 If the new value is the same as the original value, we can
1748 can use the original value as-is. If the new value is
1749 different, we use it and insert the most-significant 32-bits
1750 of the original value into the final result. */
1751 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1752 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1755 #if HOST_BITS_PER_WIDE_INT > 32
1756 extend = GEN_INT (val >> 32);
1758 operand1 = GEN_INT (nval);
1762 if (reload_in_progress || reload_completed)
1765 temp = gen_reg_rtx (mode);
1767 /* We don't directly split DImode constants on 32-bit targets
1768 because PLUS uses an 11-bit immediate and the insn sequence
1769 generated is not as efficient as the one using HIGH/LO_SUM. */
1770 if (GET_CODE (operand1) == CONST_INT
1771 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1773 /* Directly break constant into high and low parts. This
1774 provides better optimization opportunities because various
1775 passes recognize constants split with PLUS but not LO_SUM.
1776 We use a 14-bit signed low part except when the addition
1777 of 0x4000 to the high part might change the sign of the
1779 HOST_WIDE_INT value = INTVAL (operand1);
1780 HOST_WIDE_INT low = value & 0x3fff;
1781 HOST_WIDE_INT high = value & ~ 0x3fff;
1785 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1793 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1794 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1798 emit_insn (gen_rtx_SET (VOIDmode, temp,
1799 gen_rtx_HIGH (mode, operand1)));
1800 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1803 emit_move_insn (operands[0], operands[1]);
1805 if (extend != NULL_RTX)
1806 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1812 /* Now have insn-emit do whatever it normally does. */
1816 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1817 it will need a link/runtime reloc). */
1825 switch (TREE_CODE (exp))
1832 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1833 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1838 case NON_LVALUE_EXPR:
1839 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1845 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1846 if (TREE_VALUE (link) != 0)
1847 reloc |= reloc_needed (TREE_VALUE (link));
1860 /* Does operand (which is a symbolic_operand) live in text space?
1861 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1865 read_only_operand (operand, mode)
1867 enum machine_mode mode ATTRIBUTE_UNUSED;
1869 if (GET_CODE (operand) == CONST)
1870 operand = XEXP (XEXP (operand, 0), 0);
1873 if (GET_CODE (operand) == SYMBOL_REF)
1874 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1878 if (GET_CODE (operand) == SYMBOL_REF)
1879 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1885 /* Return the best assembler insn template
1886 for moving operands[1] into operands[0] as a fullword. */
1888 singlemove_string (operands)
1891 HOST_WIDE_INT intval;
1893 if (GET_CODE (operands[0]) == MEM)
1894 return "stw %r1,%0";
1895 if (GET_CODE (operands[1]) == MEM)
1897 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1902 if (GET_MODE (operands[1]) != SFmode)
1905 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1907 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1908 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1910 operands[1] = GEN_INT (i);
1911 /* Fall through to CONST_INT case. */
1913 if (GET_CODE (operands[1]) == CONST_INT)
1915 intval = INTVAL (operands[1]);
1917 if (VAL_14_BITS_P (intval))
1919 else if ((intval & 0x7ff) == 0)
1920 return "ldil L'%1,%0";
1921 else if (zdepi_cint_p (intval))
1922 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1924 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1926 return "copy %1,%0";
1930 /* Compute position (in OP[1]) and width (in OP[2])
1931 useful for copying IMM to a register using the zdepi
1932 instructions. Store the immediate value to insert in OP[0]. */
1934 compute_zdepwi_operands (imm, op)
1935 unsigned HOST_WIDE_INT imm;
1940 /* Find the least significant set bit in IMM. */
1941 for (lsb = 0; lsb < 32; lsb++)
1948 /* Choose variants based on *sign* of the 5-bit field. */
1949 if ((imm & 0x10) == 0)
1950 len = (lsb <= 28) ? 4 : 32 - lsb;
1953 /* Find the width of the bitstring in IMM. */
1954 for (len = 5; len < 32; len++)
1956 if ((imm & (1 << len)) == 0)
1960 /* Sign extend IMM as a 5-bit value. */
1961 imm = (imm & 0xf) - 0x10;
1969 /* Compute position (in OP[1]) and width (in OP[2])
1970 useful for copying IMM to a register using the depdi,z
1971 instructions. Store the immediate value to insert in OP[0]. */
1973 compute_zdepdi_operands (imm, op)
1974 unsigned HOST_WIDE_INT imm;
1977 HOST_WIDE_INT lsb, len;
1979 /* Find the least significant set bit in IMM. */
1980 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1987 /* Choose variants based on *sign* of the 5-bit field. */
1988 if ((imm & 0x10) == 0)
1989 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1990 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1993 /* Find the width of the bitstring in IMM. */
1994 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1996 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2000 /* Sign extend IMM as a 5-bit value. */
2001 imm = (imm & 0xf) - 0x10;
2009 /* Output assembler code to perform a doubleword move insn
2010 with operands OPERANDS. */
2013 output_move_double (operands)
2016 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2018 rtx addreg0 = 0, addreg1 = 0;
2020 /* First classify both operands. */
2022 if (REG_P (operands[0]))
2024 else if (offsettable_memref_p (operands[0]))
2026 else if (GET_CODE (operands[0]) == MEM)
2031 if (REG_P (operands[1]))
2033 else if (CONSTANT_P (operands[1]))
2035 else if (offsettable_memref_p (operands[1]))
2037 else if (GET_CODE (operands[1]) == MEM)
2042 /* Check for the cases that the operand constraints are not
2043 supposed to allow to happen. Abort if we get one,
2044 because generating code for these cases is painful. */
2046 if (optype0 != REGOP && optype1 != REGOP)
2049 /* Handle auto decrementing and incrementing loads and stores
2050 specifically, since the structure of the function doesn't work
2051 for them without major modification. Do it better when we learn
2052 this port about the general inc/dec addressing of PA.
2053 (This was written by tege. Chide him if it doesn't work.) */
2055 if (optype0 == MEMOP)
2057 /* We have to output the address syntax ourselves, since print_operand
2058 doesn't deal with the addresses we want to use. Fix this later. */
2060 rtx addr = XEXP (operands[0], 0);
2061 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2063 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2065 operands[0] = XEXP (addr, 0);
2066 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2069 if (!reg_overlap_mentioned_p (high_reg, addr))
2071 /* No overlap between high target register and address
2072 register. (We do this in a non-obvious way to
2073 save a register file writeback) */
2074 if (GET_CODE (addr) == POST_INC)
2075 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2076 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2081 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2083 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2085 operands[0] = XEXP (addr, 0);
2086 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2089 if (!reg_overlap_mentioned_p (high_reg, addr))
2091 /* No overlap between high target register and address
2092 register. (We do this in a non-obvious way to
2093 save a register file writeback) */
2094 if (GET_CODE (addr) == PRE_INC)
2095 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2096 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2102 if (optype1 == MEMOP)
2104 /* We have to output the address syntax ourselves, since print_operand
2105 doesn't deal with the addresses we want to use. Fix this later. */
2107 rtx addr = XEXP (operands[1], 0);
2108 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2110 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2112 operands[1] = XEXP (addr, 0);
2113 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2116 if (!reg_overlap_mentioned_p (high_reg, addr))
2118 /* No overlap between high target register and address
2119 register. (We do this in a non-obvious way to
2120 save a register file writeback) */
2121 if (GET_CODE (addr) == POST_INC)
2122 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2123 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2127 /* This is an undefined situation. We should load into the
2128 address register *and* update that register. Probably
2129 we don't need to handle this at all. */
2130 if (GET_CODE (addr) == POST_INC)
2131 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2132 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2135 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2137 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2139 operands[1] = XEXP (addr, 0);
2140 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2143 if (!reg_overlap_mentioned_p (high_reg, addr))
2145 /* No overlap between high target register and address
2146 register. (We do this in a non-obvious way to
2147 save a register file writeback) */
2148 if (GET_CODE (addr) == PRE_INC)
2149 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2150 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2154 /* This is an undefined situation. We should load into the
2155 address register *and* update that register. Probably
2156 we don't need to handle this at all. */
2157 if (GET_CODE (addr) == PRE_INC)
2158 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2159 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2162 else if (GET_CODE (addr) == PLUS
2163 && GET_CODE (XEXP (addr, 0)) == MULT)
2165 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2167 if (!reg_overlap_mentioned_p (high_reg, addr))
2171 xoperands[0] = high_reg;
2172 xoperands[1] = XEXP (addr, 1);
2173 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2174 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2175 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2177 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2183 xoperands[0] = high_reg;
2184 xoperands[1] = XEXP (addr, 1);
2185 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2186 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2187 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2189 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2194 /* If an operand is an unoffsettable memory ref, find a register
2195 we can increment temporarily to make it refer to the second word. */
2197 if (optype0 == MEMOP)
2198 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2200 if (optype1 == MEMOP)
2201 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2203 /* Ok, we can do one word at a time.
2204 Normally we do the low-numbered word first.
2206 In either case, set up in LATEHALF the operands to use
2207 for the high-numbered word and in some cases alter the
2208 operands in OPERANDS to be suitable for the low-numbered word. */
2210 if (optype0 == REGOP)
2211 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2212 else if (optype0 == OFFSOP)
2213 latehalf[0] = adjust_address (operands[0], SImode, 4);
2215 latehalf[0] = operands[0];
2217 if (optype1 == REGOP)
2218 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2219 else if (optype1 == OFFSOP)
2220 latehalf[1] = adjust_address (operands[1], SImode, 4);
2221 else if (optype1 == CNSTOP)
2222 split_double (operands[1], &operands[1], &latehalf[1]);
2224 latehalf[1] = operands[1];
2226 /* If the first move would clobber the source of the second one,
2227 do them in the other order.
2229 This can happen in two cases:
2231 mem -> register where the first half of the destination register
2232 is the same register used in the memory's address. Reload
2233 can create such insns.
2235 mem in this case will be either register indirect or register
2236 indirect plus a valid offset.
2238 register -> register move where REGNO(dst) == REGNO(src + 1)
2239 someone (Tim/Tege?) claimed this can happen for parameter loads.
2241 Handle mem -> register case first. */
2242 if (optype0 == REGOP
2243 && (optype1 == MEMOP || optype1 == OFFSOP)
2244 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2247 /* Do the late half first. */
2249 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2250 output_asm_insn (singlemove_string (latehalf), latehalf);
2254 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2255 return singlemove_string (operands);
2258 /* Now handle register -> register case. */
2259 if (optype0 == REGOP && optype1 == REGOP
2260 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2262 output_asm_insn (singlemove_string (latehalf), latehalf);
2263 return singlemove_string (operands);
2266 /* Normal case: do the two words, low-numbered first. */
2268 output_asm_insn (singlemove_string (operands), operands);
2270 /* Make any unoffsettable addresses point at high-numbered word. */
2272 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2274 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2277 output_asm_insn (singlemove_string (latehalf), latehalf);
2279 /* Undo the adds we just did. */
2281 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2283 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2289 output_fp_move_double (operands)
2292 if (FP_REG_P (operands[0]))
2294 if (FP_REG_P (operands[1])
2295 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2296 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2298 output_asm_insn ("fldd%F1 %1,%0", operands);
2300 else if (FP_REG_P (operands[1]))
2302 output_asm_insn ("fstd%F0 %1,%0", operands);
2304 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2306 if (GET_CODE (operands[0]) == REG)
2309 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2310 xoperands[0] = operands[0];
2311 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2313 /* This is a pain. You have to be prepared to deal with an
2314 arbitrary address here including pre/post increment/decrement.
2316 so avoid this in the MD. */
2324 /* Return a REG that occurs in ADDR with coefficient 1.
2325 ADDR can be effectively incremented by incrementing REG. */
2328 find_addr_reg (addr)
2331 while (GET_CODE (addr) == PLUS)
2333 if (GET_CODE (XEXP (addr, 0)) == REG)
2334 addr = XEXP (addr, 0);
2335 else if (GET_CODE (XEXP (addr, 1)) == REG)
2336 addr = XEXP (addr, 1);
2337 else if (CONSTANT_P (XEXP (addr, 0)))
2338 addr = XEXP (addr, 1);
2339 else if (CONSTANT_P (XEXP (addr, 1)))
2340 addr = XEXP (addr, 0);
2344 if (GET_CODE (addr) == REG)
2349 /* Emit code to perform a block move.
2351 OPERANDS[0] is the destination pointer as a REG, clobbered.
2352 OPERANDS[1] is the source pointer as a REG, clobbered.
2353 OPERANDS[2] is a register for temporary storage.
2354 OPERANDS[4] is the size as a CONST_INT
2355 OPERANDS[3] is a register for temporary storage.
2356 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2357 OPERANDS[6] is another temporary register. */
2360 output_block_move (operands, size_is_constant)
2362 int size_is_constant ATTRIBUTE_UNUSED;
2364 int align = INTVAL (operands[5]);
2365 unsigned long n_bytes = INTVAL (operands[4]);
2367 /* We can't move more than four bytes at a time because the PA
2368 has no longer integer move insns. (Could use fp mem ops?) */
2372 /* Note that we know each loop below will execute at least twice
2373 (else we would have open-coded the copy). */
2377 /* Pre-adjust the loop counter. */
2378 operands[4] = GEN_INT (n_bytes - 8);
2379 output_asm_insn ("ldi %4,%2", operands);
2382 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2383 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2384 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2385 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2386 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2388 /* Handle the residual. There could be up to 7 bytes of
2389 residual to copy! */
2390 if (n_bytes % 8 != 0)
2392 operands[4] = GEN_INT (n_bytes % 4);
2393 if (n_bytes % 8 >= 4)
2394 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2395 if (n_bytes % 4 != 0)
2396 output_asm_insn ("ldw 0(%1),%6", operands);
2397 if (n_bytes % 8 >= 4)
2398 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2399 if (n_bytes % 4 != 0)
2400 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2405 /* Pre-adjust the loop counter. */
2406 operands[4] = GEN_INT (n_bytes - 4);
2407 output_asm_insn ("ldi %4,%2", operands);
2410 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2411 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2412 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2413 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2414 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2416 /* Handle the residual. */
2417 if (n_bytes % 4 != 0)
2419 if (n_bytes % 4 >= 2)
2420 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2421 if (n_bytes % 2 != 0)
2422 output_asm_insn ("ldb 0(%1),%6", operands);
2423 if (n_bytes % 4 >= 2)
2424 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2425 if (n_bytes % 2 != 0)
2426 output_asm_insn ("stb %6,0(%0)", operands);
2431 /* Pre-adjust the loop counter. */
2432 operands[4] = GEN_INT (n_bytes - 2);
2433 output_asm_insn ("ldi %4,%2", operands);
2436 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2437 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2438 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2439 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2440 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2442 /* Handle the residual. */
2443 if (n_bytes % 2 != 0)
2445 output_asm_insn ("ldb 0(%1),%3", operands);
2446 output_asm_insn ("stb %3,0(%0)", operands);
2455 /* Count the number of insns necessary to handle this block move.
2457 Basic structure is the same as emit_block_move, except that we
2458 count insns rather than emit them. */
2461 compute_movstrsi_length (insn)
2464 rtx pat = PATTERN (insn);
2465 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2466 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2467 unsigned int n_insns = 0;
2469 /* We can't move more than four bytes at a time because the PA
2470 has no longer integer move insns. (Could use fp mem ops?) */
2474 /* The basic copying loop. */
2478 if (n_bytes % (2 * align) != 0)
2480 if ((n_bytes % (2 * align)) >= align)
2483 if ((n_bytes % align) != 0)
2487 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2493 output_and (operands)
2496 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2498 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2499 int ls0, ls1, ms0, p, len;
2501 for (ls0 = 0; ls0 < 32; ls0++)
2502 if ((mask & (1 << ls0)) == 0)
2505 for (ls1 = ls0; ls1 < 32; ls1++)
2506 if ((mask & (1 << ls1)) != 0)
2509 for (ms0 = ls1; ms0 < 32; ms0++)
2510 if ((mask & (1 << ms0)) == 0)
2523 operands[2] = GEN_INT (len);
2524 return "{extru|extrw,u} %1,31,%2,%0";
2528 /* We could use this `depi' for the case above as well, but `depi'
2529 requires one more register file access than an `extru'. */
2534 operands[2] = GEN_INT (p);
2535 operands[3] = GEN_INT (len);
2536 return "{depi|depwi} 0,%2,%3,%0";
2540 return "and %1,%2,%0";
2543 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2544 storing the result in operands[0]. */
2546 output_64bit_and (operands)
2549 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2551 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2552 int ls0, ls1, ms0, p, len;
2554 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2555 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2558 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2559 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2562 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2563 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2566 if (ms0 != HOST_BITS_PER_WIDE_INT)
2569 if (ls1 == HOST_BITS_PER_WIDE_INT)
2576 operands[2] = GEN_INT (len);
2577 return "extrd,u %1,63,%2,%0";
2581 /* We could use this `depi' for the case above as well, but `depi'
2582 requires one more register file access than an `extru'. */
2587 operands[2] = GEN_INT (p);
2588 operands[3] = GEN_INT (len);
2589 return "depdi 0,%2,%3,%0";
2593 return "and %1,%2,%0";
2597 output_ior (operands)
2600 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2601 int bs0, bs1, p, len;
2603 if (INTVAL (operands[2]) == 0)
2604 return "copy %1,%0";
2606 for (bs0 = 0; bs0 < 32; bs0++)
2607 if ((mask & (1 << bs0)) != 0)
2610 for (bs1 = bs0; bs1 < 32; bs1++)
2611 if ((mask & (1 << bs1)) == 0)
2614 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2620 operands[2] = GEN_INT (p);
2621 operands[3] = GEN_INT (len);
2622 return "{depi|depwi} -1,%2,%3,%0";
2625 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2626 storing the result in operands[0]. */
2628 output_64bit_ior (operands)
2631 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2632 int bs0, bs1, p, len;
2634 if (INTVAL (operands[2]) == 0)
2635 return "copy %1,%0";
2637 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2638 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2641 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2642 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2645 if (bs1 != HOST_BITS_PER_WIDE_INT
2646 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2652 operands[2] = GEN_INT (p);
2653 operands[3] = GEN_INT (len);
2654 return "depdi -1,%2,%3,%0";
2657 /* Target hook for assembling integer objects. This code handles
2658 aligned SI and DI integers specially, since function references must
2659 be preceded by P%. */
2662 pa_assemble_integer (x, size, aligned_p)
2667 if (size == UNITS_PER_WORD && aligned_p
2668 && function_label_operand (x, VOIDmode))
2670 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2671 output_addr_const (asm_out_file, x);
2672 fputc ('\n', asm_out_file);
2675 return default_assemble_integer (x, size, aligned_p);
2678 /* Output an ascii string. */
2680 output_ascii (file, p, size)
2687 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2689 /* The HP assembler can only take strings of 256 characters at one
2690 time. This is a limitation on input line length, *not* the
2691 length of the string. Sigh. Even worse, it seems that the
2692 restriction is in number of input characters (see \xnn &
2693 \whatever). So we have to do this very carefully. */
2695 fputs ("\t.STRING \"", file);
2698 for (i = 0; i < size; i += 4)
2702 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2704 register unsigned int c = (unsigned char) p[i + io];
2706 if (c == '\"' || c == '\\')
2707 partial_output[co++] = '\\';
2708 if (c >= ' ' && c < 0177)
2709 partial_output[co++] = c;
2713 partial_output[co++] = '\\';
2714 partial_output[co++] = 'x';
2715 hexd = c / 16 - 0 + '0';
2717 hexd -= '9' - 'a' + 1;
2718 partial_output[co++] = hexd;
2719 hexd = c % 16 - 0 + '0';
2721 hexd -= '9' - 'a' + 1;
2722 partial_output[co++] = hexd;
2725 if (chars_output + co > 243)
2727 fputs ("\"\n\t.STRING \"", file);
2730 fwrite (partial_output, 1, (size_t) co, file);
2734 fputs ("\"\n", file);
2737 /* Try to rewrite floating point comparisons & branches to avoid
2738 useless add,tr insns.
2740 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2741 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2742 first attempt to remove useless add,tr insns. It is zero
2743 for the second pass as reorg sometimes leaves bogus REG_DEAD
2746 When CHECK_NOTES is zero we can only eliminate add,tr insns
2747 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2750 remove_useless_addtr_insns (insns, check_notes)
2755 static int pass = 0;
2757 /* This is fairly cheap, so always run it when optimizing. */
2761 int fbranch_count = 0;
2763 /* Walk all the insns in this function looking for fcmp & fbranch
2764 instructions. Keep track of how many of each we find. */
2765 insns = get_insns ();
2766 for (insn = insns; insn; insn = next_insn (insn))
2770 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2771 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2774 tmp = PATTERN (insn);
2776 /* It must be a set. */
2777 if (GET_CODE (tmp) != SET)
2780 /* If the destination is CCFP, then we've found an fcmp insn. */
2781 tmp = SET_DEST (tmp);
2782 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2788 tmp = PATTERN (insn);
2789 /* If this is an fbranch instruction, bump the fbranch counter. */
2790 if (GET_CODE (tmp) == SET
2791 && SET_DEST (tmp) == pc_rtx
2792 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2793 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2794 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2795 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2803 /* Find all floating point compare + branch insns. If possible,
2804 reverse the comparison & the branch to avoid add,tr insns. */
2805 for (insn = insns; insn; insn = next_insn (insn))
2809 /* Ignore anything that isn't an INSN. */
2810 if (GET_CODE (insn) != INSN)
2813 tmp = PATTERN (insn);
2815 /* It must be a set. */
2816 if (GET_CODE (tmp) != SET)
2819 /* The destination must be CCFP, which is register zero. */
2820 tmp = SET_DEST (tmp);
2821 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2824 /* INSN should be a set of CCFP.
2826 See if the result of this insn is used in a reversed FP
2827 conditional branch. If so, reverse our condition and
2828 the branch. Doing so avoids useless add,tr insns. */
2829 next = next_insn (insn);
2832 /* Jumps, calls and labels stop our search. */
2833 if (GET_CODE (next) == JUMP_INSN
2834 || GET_CODE (next) == CALL_INSN
2835 || GET_CODE (next) == CODE_LABEL)
2838 /* As does another fcmp insn. */
2839 if (GET_CODE (next) == INSN
2840 && GET_CODE (PATTERN (next)) == SET
2841 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2842 && REGNO (SET_DEST (PATTERN (next))) == 0)
2845 next = next_insn (next);
2848 /* Is NEXT_INSN a branch? */
2850 && GET_CODE (next) == JUMP_INSN)
2852 rtx pattern = PATTERN (next);
2854 /* If it a reversed fp conditional branch (eg uses add,tr)
2855 and CCFP dies, then reverse our conditional and the branch
2856 to avoid the add,tr. */
2857 if (GET_CODE (pattern) == SET
2858 && SET_DEST (pattern) == pc_rtx
2859 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2860 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2861 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2862 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2863 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2864 && (fcmp_count == fbranch_count
2866 && find_regno_note (next, REG_DEAD, 0))))
2868 /* Reverse the branch. */
2869 tmp = XEXP (SET_SRC (pattern), 1);
2870 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2871 XEXP (SET_SRC (pattern), 2) = tmp;
2872 INSN_CODE (next) = -1;
2874 /* Reverse our condition. */
2875 tmp = PATTERN (insn);
2876 PUT_CODE (XEXP (tmp, 1),
2877 (reverse_condition_maybe_unordered
2878 (GET_CODE (XEXP (tmp, 1)))));
2888 /* You may have trouble believing this, but this is the 32 bit HP-PA
2893 Variable arguments (optional; any number may be allocated)
2895 SP-(4*(N+9)) arg word N
2900 Fixed arguments (must be allocated; may remain unused)
2909 SP-32 External Data Pointer (DP)
2911 SP-24 External/stub RP (RP')
2915 SP-8 Calling Stub RP (RP'')
2920 SP-0 Stack Pointer (points to next available address)
2924 /* This function saves registers as follows. Registers marked with ' are
2925 this function's registers (as opposed to the previous function's).
2926 If a frame_pointer isn't needed, r4 is saved as a general register;
2927 the space for the frame pointer is still allocated, though, to keep
2933 SP (FP') Previous FP
2934 SP + 4 Alignment filler (sigh)
2935 SP + 8 Space for locals reserved here.
2939 SP + n All call saved register used.
2943 SP + o All call saved fp registers used.
2947 SP + p (SP') points to next available address.
2951 /* Global variables set by output_function_prologue(). */
2952 /* Size of frame. Need to know this to emit return insns from
2954 static int actual_fsize;
2955 static int local_fsize, save_fregs;
2957 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2958 Handle case where DISP > 8k by using the add_high_const patterns.
2960 Note in DISP > 8k case, we will leave the high part of the address
2961 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2964 store_reg (reg, disp, base)
2965 int reg, disp, base;
2967 rtx insn, dest, src, basereg;
2969 src = gen_rtx_REG (word_mode, reg);
2970 basereg = gen_rtx_REG (Pmode, base);
2971 if (VAL_14_BITS_P (disp))
2973 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2974 insn = emit_move_insn (dest, src);
2978 rtx delta = GEN_INT (disp);
2979 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2980 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2981 emit_move_insn (tmpreg, high);
2982 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2983 insn = emit_move_insn (dest, src);
2987 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2988 gen_rtx_SET (VOIDmode,
2989 gen_rtx_MEM (word_mode,
2990 gen_rtx_PLUS (word_mode, basereg,
2998 RTX_FRAME_RELATED_P (insn) = 1;
3001 /* Emit RTL to store REG at the memory location specified by BASE and then
3002 add MOD to BASE. MOD must be <= 8k. */
3005 store_reg_modify (base, reg, mod)
3008 rtx insn, basereg, srcreg, delta;
3010 if (! VAL_14_BITS_P (mod))
3013 basereg = gen_rtx_REG (Pmode, base);
3014 srcreg = gen_rtx_REG (word_mode, reg);
3015 delta = GEN_INT (mod);
3017 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3020 RTX_FRAME_RELATED_P (insn) = 1;
3022 /* RTX_FRAME_RELATED_P must be set on each frame related set
3023 in a parallel with more than one element. Don't set
3024 RTX_FRAME_RELATED_P in the first set if reg is temporary
3025 register 1. The effect of this operation is recorded in
3026 the initial copy. */
3029 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3030 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3034 /* The first element of a PARALLEL is always processed if it is
3035 a SET. Thus, we need an expression list for this case. */
3037 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3038 gen_rtx_SET (VOIDmode, basereg,
3039 gen_rtx_PLUS (word_mode, basereg, delta)),
3045 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3046 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3047 whether to add a frame note or not.
3049 In the DISP > 8k case, we leave the high part of the address in %r1.
3050 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3053 set_reg_plus_d (reg, base, disp, note)
3054 int reg, base, disp, note;
3058 if (VAL_14_BITS_P (disp))
3060 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3061 plus_constant (gen_rtx_REG (Pmode, base), disp));
3065 rtx basereg = gen_rtx_REG (Pmode, base);
3066 rtx delta = GEN_INT (disp);
3068 emit_move_insn (gen_rtx_REG (Pmode, 1),
3069 gen_rtx_PLUS (Pmode, basereg,
3070 gen_rtx_HIGH (Pmode, delta)));
3071 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3072 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3076 if (DO_FRAME_NOTES && note)
3077 RTX_FRAME_RELATED_P (insn) = 1;
3081 compute_frame_size (size, fregs_live)
3087 /* Space for frame pointer + filler. If any frame is allocated
3088 we need to add this in because of STARTING_FRAME_OFFSET.
3090 Similar code also appears in hppa_expand_prologue. Change both
3091 of them at the same time. */
3092 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
3094 /* If the current function calls __builtin_eh_return, then we need
3095 to allocate stack space for registers that will hold data for
3096 the exception handler. */
3097 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3101 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3103 fsize += i * UNITS_PER_WORD;
3106 /* Account for space used by the callee general register saves. */
3107 for (i = 18; i >= 3; i--)
3108 if (regs_ever_live[i])
3109 fsize += UNITS_PER_WORD;
3111 /* Round the stack. */
3112 fsize = (fsize + 7) & ~7;
3114 /* Account for space used by the callee floating point register saves. */
3115 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3116 if (regs_ever_live[i]
3117 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3122 /* We always save both halves of the FP register, so always
3123 increment the frame size by 8 bytes. */
3127 /* The various ABIs include space for the outgoing parameters in the
3128 size of the current function's stack frame. */
3129 fsize += current_function_outgoing_args_size;
3131 /* Allocate space for the fixed frame marker. This space must be
3132 allocated for any function that makes calls or otherwise allocates
3134 if (!current_function_is_leaf || fsize)
3135 fsize += TARGET_64BIT ? 16 : 32;
3137 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
3140 /* Generate the assembly code for function entry. FILE is a stdio
3141 stream to output the code to. SIZE is an int: how many units of
3142 temporary storage to allocate.
3144 Refer to the array `regs_ever_live' to determine which registers to
3145 save; `regs_ever_live[I]' is nonzero if register number I is ever
3146 used in the function. This function is responsible for knowing
3147 which registers should not be saved even if used. */
3149 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3150 of memory. If any fpu reg is used in the function, we allocate
3151 such a block here, at the bottom of the frame, just in case it's needed.
3153 If this function is a leaf procedure, then we may choose not
3154 to do a "save" insn. The decision about whether or not
3155 to do this is made in regclass.c. */
3158 pa_output_function_prologue (file, size)
3160 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3162 /* The function's label and associated .PROC must never be
3163 separated and must be output *after* any profiling declarations
3164 to avoid changing spaces/subspaces within a procedure. */
3165 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3166 fputs ("\t.PROC\n", file);
3168 /* hppa_expand_prologue does the dirty work now. We just need
3169 to output the assembler directives which denote the start
3171 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3172 if (regs_ever_live[2])
3173 fputs (",CALLS,SAVE_RP", file);
3175 fputs (",NO_CALLS", file);
3177 if (frame_pointer_needed)
3178 fputs (",SAVE_SP", file);
3180 /* Pass on information about the number of callee register saves
3181 performed in the prologue.
3183 The compiler is supposed to pass the highest register number
3184 saved, the assembler then has to adjust that number before
3185 entering it into the unwind descriptor (to account for any
3186 caller saved registers with lower register numbers than the
3187 first callee saved register). */
3189 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3192 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3194 fputs ("\n\t.ENTRY\n", file);
3196 /* If we're using GAS and SOM, and not using the portable runtime model,
3197 then we don't need to accumulate the total number of code bytes. */
3198 if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME)
3199 /* FIXME: we can't handle long calls for TARGET_64BIT. */
3201 total_code_bytes = 0;
3202 else if (INSN_ADDRESSES_SET_P ())
3204 unsigned int old_total = total_code_bytes;
3206 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_nonnote_insn ()));
3207 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3209 /* Be prepared to handle overflows. */
3210 if (old_total > total_code_bytes)
3211 total_code_bytes = -1;
3214 total_code_bytes = -1;
3216 remove_useless_addtr_insns (get_insns (), 0);
3220 hppa_expand_prologue ()
3222 int size = get_frame_size ();
3223 int merge_sp_adjust_with_store = 0;
3231 /* Allocate space for frame pointer + filler. If any frame is allocated
3232 we need to add this in because of STARTING_FRAME_OFFSET.
3234 Similar code also appears in compute_frame_size. Change both
3235 of them at the same time. */
3236 local_fsize = size + (size || frame_pointer_needed
3237 ? STARTING_FRAME_OFFSET : 0);
3239 actual_fsize = compute_frame_size (size, &save_fregs);
3241 /* Compute a few things we will use often. */
3242 tmpreg = gen_rtx_REG (word_mode, 1);
3244 /* Save RP first. The calling conventions manual states RP will
3245 always be stored into the caller's frame at sp - 20 or sp - 16
3246 depending on which ABI is in use. */
3247 if (regs_ever_live[2] || current_function_calls_eh_return)
3248 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3250 /* Allocate the local frame and set up the frame pointer if needed. */
3251 if (actual_fsize != 0)
3253 if (frame_pointer_needed)
3255 /* Copy the old frame pointer temporarily into %r1. Set up the
3256 new stack pointer, then store away the saved old frame pointer
3257 into the stack at sp and at the same time update the stack
3258 pointer by actual_fsize bytes. Two versions, first
3259 handles small (<8k) frames. The second handles large (>=8k)
3261 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3264 /* We need to record the frame pointer save here since the
3265 new frame pointer is set in the following insn. */
3266 RTX_FRAME_RELATED_P (insn) = 1;
3268 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3269 gen_rtx_SET (VOIDmode,
3270 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3275 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3277 RTX_FRAME_RELATED_P (insn) = 1;
3279 if (VAL_14_BITS_P (actual_fsize))
3280 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3283 /* It is incorrect to store the saved frame pointer at *sp,
3284 then increment sp (writes beyond the current stack boundary).
3286 So instead use stwm to store at *sp and post-increment the
3287 stack pointer as an atomic operation. Then increment sp to
3288 finish allocating the new frame. */
3289 int adjust1 = 8192 - 64;
3290 int adjust2 = actual_fsize - adjust1;
3292 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3293 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3297 /* Prevent register spills from being scheduled before the
3298 stack pointer is raised. Necessary as we will be storing
3299 registers using the frame pointer as a base register, and
3300 we happen to set fp before raising sp. */
3301 emit_insn (gen_blockage ());
3303 /* no frame pointer needed. */
3306 /* In some cases we can perform the first callee register save
3307 and allocating the stack frame at the same time. If so, just
3308 make a note of it and defer allocating the frame until saving
3309 the callee registers. */
3310 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3311 merge_sp_adjust_with_store = 1;
3312 /* Can not optimize. Adjust the stack frame by actual_fsize
3315 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3320 /* Normal register save.
3322 Do not save the frame pointer in the frame_pointer_needed case. It
3323 was done earlier. */
3324 if (frame_pointer_needed)
3326 offset = local_fsize;
3328 /* Saving the EH return data registers in the frame is the simplest
3329 way to get the frame unwind information emitted. We put them
3330 just before the general registers. */
3331 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3333 unsigned int i, regno;
3337 regno = EH_RETURN_DATA_REGNO (i);
3338 if (regno == INVALID_REGNUM)
3341 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3342 offset += UNITS_PER_WORD;
3346 for (i = 18; i >= 4; i--)
3347 if (regs_ever_live[i] && ! call_used_regs[i])
3349 store_reg (i, offset, FRAME_POINTER_REGNUM);
3350 offset += UNITS_PER_WORD;
3353 /* Account for %r3 which is saved in a special place. */
3356 /* No frame pointer needed. */
3359 offset = local_fsize - actual_fsize;
3361 /* Saving the EH return data registers in the frame is the simplest
3362 way to get the frame unwind information emitted. */
3363 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3365 unsigned int i, regno;
3369 regno = EH_RETURN_DATA_REGNO (i);
3370 if (regno == INVALID_REGNUM)
3373 /* If merge_sp_adjust_with_store is nonzero, then we can
3374 optimize the first save. */
3375 if (merge_sp_adjust_with_store)
3377 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3378 merge_sp_adjust_with_store = 0;
3381 store_reg (regno, offset, STACK_POINTER_REGNUM);
3382 offset += UNITS_PER_WORD;
3386 for (i = 18; i >= 3; i--)
3387 if (regs_ever_live[i] && ! call_used_regs[i])
3389 /* If merge_sp_adjust_with_store is nonzero, then we can
3390 optimize the first GR save. */
3391 if (merge_sp_adjust_with_store)
3393 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3394 merge_sp_adjust_with_store = 0;
3397 store_reg (i, offset, STACK_POINTER_REGNUM);
3398 offset += UNITS_PER_WORD;
3402 /* If we wanted to merge the SP adjustment with a GR save, but we never
3403 did any GR saves, then just emit the adjustment here. */
3404 if (merge_sp_adjust_with_store)
3405 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3409 /* The hppa calling conventions say that %r19, the pic offset
3410 register, is saved at sp - 32 (in this function's frame)
3411 when generating PIC code. FIXME: What is the correct thing
3412 to do for functions which make no calls and allocate no
3413 frame? Do we need to allocate a frame, or can we just omit
3414 the save? For now we'll just omit the save. */
3415 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3416 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3418 /* Align pointer properly (doubleword boundary). */
3419 offset = (offset + 7) & ~7;
3421 /* Floating point register store. */
3426 /* First get the frame or stack pointer to the start of the FP register
3428 if (frame_pointer_needed)
3430 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3431 base = frame_pointer_rtx;
3435 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3436 base = stack_pointer_rtx;
3439 /* Now actually save the FP registers. */
3440 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3442 if (regs_ever_live[i]
3443 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3445 rtx addr, insn, reg;
3446 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3447 reg = gen_rtx_REG (DFmode, i);
3448 insn = emit_move_insn (addr, reg);
3451 RTX_FRAME_RELATED_P (insn) = 1;
3454 rtx mem = gen_rtx_MEM (DFmode,
3455 plus_constant (base, offset));
3457 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3458 gen_rtx_SET (VOIDmode, mem, reg),
3463 rtx meml = gen_rtx_MEM (SFmode,
3464 plus_constant (base, offset));
3465 rtx memr = gen_rtx_MEM (SFmode,
3466 plus_constant (base, offset + 4));
3467 rtx regl = gen_rtx_REG (SFmode, i);
3468 rtx regr = gen_rtx_REG (SFmode, i + 1);
3469 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3470 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3473 RTX_FRAME_RELATED_P (setl) = 1;
3474 RTX_FRAME_RELATED_P (setr) = 1;
3475 vec = gen_rtvec (2, setl, setr);
3477 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3478 gen_rtx_SEQUENCE (VOIDmode, vec),
3482 offset += GET_MODE_SIZE (DFmode);
3488 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3489 prevent insns with frame notes being scheduled in the delay slot
3490 of calls. This causes problems because the dwarf2 output code
3491 processes the insn list serially. For now, limit the migration
3492 of prologue insns with a blockage. */
3494 emit_insn (gen_blockage ());
3497 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3498 Handle case where DISP > 8k by using the add_high_const patterns. */
3501 load_reg (reg, disp, base)
3502 int reg, disp, base;
3504 rtx src, dest, basereg;
3506 dest = gen_rtx_REG (word_mode, reg);
3507 basereg = gen_rtx_REG (Pmode, base);
3508 if (VAL_14_BITS_P (disp))
3510 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3511 emit_move_insn (dest, src);
3515 rtx delta = GEN_INT (disp);
3516 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3517 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3518 emit_move_insn (tmpreg, high);
3519 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3520 emit_move_insn (dest, src);
3524 /* This function generates the assembly code for function exit.
3525 Args are as for output_function_prologue ().
3527 The function epilogue should not depend on the current stack
3528 pointer! It should use the frame pointer only. This is mandatory
3529 because of alloca; we also take advantage of it to omit stack
3530 adjustments before returning. */
3533 pa_output_function_epilogue (file, size)
3535 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3537 rtx insn = get_last_insn ();
3539 /* hppa_expand_epilogue does the dirty work now. We just need
3540 to output the assembler directives which denote the end
3543 To make debuggers happy, emit a nop if the epilogue was completely
3544 eliminated due to a volatile call as the last insn in the
3545 current function. That way the return address (in %r2) will
3546 always point to a valid instruction in the current function. */
3548 /* Get the last real insn. */
3549 if (GET_CODE (insn) == NOTE)
3550 insn = prev_real_insn (insn);
3552 /* If it is a sequence, then look inside. */
3553 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3554 insn = XVECEXP (PATTERN (insn), 0, 0);
3556 /* If insn is a CALL_INSN, then it must be a call to a volatile
3557 function (otherwise there would be epilogue insns). */
3558 if (insn && GET_CODE (insn) == CALL_INSN)
3559 fputs ("\tnop\n", file);
3561 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3565 hppa_expand_epilogue ()
3569 int merge_sp_adjust_with_load = 0;
3572 /* We will use this often. */
3573 tmpreg = gen_rtx_REG (word_mode, 1);
3575 /* Try to restore RP early to avoid load/use interlocks when
3576 RP gets used in the return (bv) instruction. This appears to still
3577 be necessary even when we schedule the prologue and epilogue. */
3578 if (regs_ever_live [2] || current_function_calls_eh_return)
3580 ret_off = TARGET_64BIT ? -16 : -20;
3581 if (frame_pointer_needed)
3583 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3588 /* No frame pointer, and stack is smaller than 8k. */
3589 if (VAL_14_BITS_P (ret_off - actual_fsize))
3591 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3597 /* General register restores. */
3598 if (frame_pointer_needed)
3600 offset = local_fsize;
3602 /* If the current function calls __builtin_eh_return, then we need
3603 to restore the saved EH data registers. */
3604 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3606 unsigned int i, regno;
3610 regno = EH_RETURN_DATA_REGNO (i);
3611 if (regno == INVALID_REGNUM)
3614 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3615 offset += UNITS_PER_WORD;
3619 for (i = 18; i >= 4; i--)
3620 if (regs_ever_live[i] && ! call_used_regs[i])
3622 load_reg (i, offset, FRAME_POINTER_REGNUM);
3623 offset += UNITS_PER_WORD;
3628 offset = local_fsize - actual_fsize;
3630 /* If the current function calls __builtin_eh_return, then we need
3631 to restore the saved EH data registers. */
3632 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3634 unsigned int i, regno;
3638 regno = EH_RETURN_DATA_REGNO (i);
3639 if (regno == INVALID_REGNUM)
3642 /* Only for the first load.
3643 merge_sp_adjust_with_load holds the register load
3644 with which we will merge the sp adjustment. */
3645 if (merge_sp_adjust_with_load == 0
3647 && VAL_14_BITS_P (-actual_fsize))
3648 merge_sp_adjust_with_load = regno;
3650 load_reg (regno, offset, STACK_POINTER_REGNUM);
3651 offset += UNITS_PER_WORD;
3655 for (i = 18; i >= 3; i--)
3657 if (regs_ever_live[i] && ! call_used_regs[i])
3659 /* Only for the first load.
3660 merge_sp_adjust_with_load holds the register load
3661 with which we will merge the sp adjustment. */
3662 if (merge_sp_adjust_with_load == 0
3664 && VAL_14_BITS_P (-actual_fsize))
3665 merge_sp_adjust_with_load = i;
3667 load_reg (i, offset, STACK_POINTER_REGNUM);
3668 offset += UNITS_PER_WORD;
3673 /* Align pointer properly (doubleword boundary). */
3674 offset = (offset + 7) & ~7;
3676 /* FP register restores. */
3679 /* Adjust the register to index off of. */
3680 if (frame_pointer_needed)
3681 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3683 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3685 /* Actually do the restores now. */
3686 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3687 if (regs_ever_live[i]
3688 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3690 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3691 rtx dest = gen_rtx_REG (DFmode, i);
3692 emit_move_insn (dest, src);
3696 /* Emit a blockage insn here to keep these insns from being moved to
3697 an earlier spot in the epilogue, or into the main instruction stream.
3699 This is necessary as we must not cut the stack back before all the
3700 restores are finished. */
3701 emit_insn (gen_blockage ());
3703 /* Reset stack pointer (and possibly frame pointer). The stack
3704 pointer is initially set to fp + 64 to avoid a race condition. */
3705 if (frame_pointer_needed)
3707 rtx delta = GEN_INT (-64);
3709 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3710 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3712 /* If we were deferring a callee register restore, do it now. */
3713 else if (merge_sp_adjust_with_load)
3715 rtx delta = GEN_INT (-actual_fsize);
3716 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3718 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3720 else if (actual_fsize != 0)
3721 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3724 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3725 frame greater than 8k), do so now. */
3727 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3729 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3731 rtx sa = EH_RETURN_STACKADJ_RTX;
3733 emit_insn (gen_blockage ());
3734 emit_insn (TARGET_64BIT
3735 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3736 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3741 hppa_pic_save_rtx ()
3743 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3747 hppa_profile_hook (label_no)
3750 rtx begin_label_rtx, call_insn;
3751 char begin_label_name[16];
3753 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3755 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3758 emit_move_insn (arg_pointer_rtx,
3759 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3762 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3764 #ifndef NO_PROFILE_COUNTERS
3766 rtx count_label_rtx, addr, r24;
3767 char count_label_name[16];
3769 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3770 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3772 addr = force_reg (Pmode, count_label_rtx);
3773 r24 = gen_rtx_REG (Pmode, 24);
3774 emit_move_insn (r24, addr);
3776 /* %r25 is set from within the output pattern. */
3778 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3779 GEN_INT (TARGET_64BIT ? 24 : 12),
3782 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3785 /* %r25 is set from within the output pattern. */
3787 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3788 GEN_INT (TARGET_64BIT ? 16 : 8),
3792 /* Indicate the _mcount call cannot throw, nor will it execute a
3794 REG_NOTES (call_insn)
3795 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3799 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3801 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3803 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3807 /* Fetch the return address for the frame COUNT steps up from
3808 the current frame, after the prologue. FRAMEADDR is the
3809 frame pointer of the COUNT frame.
3811 We want to ignore any export stub remnants here. To handle this,
3812 we examine the code at the return address, and if it is an export
3813 stub, we return a memory rtx for the stub return address stored
3816 The value returned is used in two different ways:
3818 1. To find a function's caller.
3820 2. To change the return address for a function.
3822 This function handles most instances of case 1; however, it will
3823 fail if there are two levels of stubs to execute on the return
3824 path. The only way I believe that can happen is if the return value
3825 needs a parameter relocation, which never happens for C code.
3827 This function handles most instances of case 2; however, it will
3828 fail if we did not originally have stub code on the return path
3829 but will need stub code on the new return path. This can happen if
3830 the caller & callee are both in the main program, but the new
3831 return location is in a shared library. */
3834 return_addr_rtx (count, frameaddr)
3846 rp = get_hard_reg_initial_val (Pmode, 2);
3848 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3851 saved_rp = gen_reg_rtx (Pmode);
3852 emit_move_insn (saved_rp, rp);
3854 /* Get pointer to the instruction stream. We have to mask out the
3855 privilege level from the two low order bits of the return address
3856 pointer here so that ins will point to the start of the first
3857 instruction that would have been executed if we returned. */
3858 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3859 label = gen_label_rtx ();
3861 /* Check the instruction stream at the normal return address for the
3864 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3865 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3866 0x00011820 | stub+16: mtsp r1,sr0
3867 0xe0400002 | stub+20: be,n 0(sr0,rp)
3869 If it is an export stub, than our return address is really in
3872 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3873 NULL_RTX, SImode, 1);
3874 emit_jump_insn (gen_bne (label));
3876 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3877 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3878 emit_jump_insn (gen_bne (label));
3880 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3881 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3882 emit_jump_insn (gen_bne (label));
3884 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3885 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3887 /* If there is no export stub then just use the value saved from
3888 the return pointer register. */
3890 emit_jump_insn (gen_bne (label));
3892 /* Here we know that our return address points to an export
3893 stub. We don't want to return the address of the export stub,
3894 but rather the return address of the export stub. That return
3895 address is stored at -24[frameaddr]. */
3897 emit_move_insn (saved_rp,
3899 memory_address (Pmode,
3900 plus_constant (frameaddr,
3907 /* This is only valid once reload has completed because it depends on
3908 knowing exactly how much (if any) frame there is and...
3910 It's only valid if there is no frame marker to de-allocate and...
3912 It's only valid if %r2 hasn't been saved into the caller's frame
3913 (we're not profiling and %r2 isn't live anywhere). */
3915 hppa_can_use_return_insn_p ()
3917 return (reload_completed
3918 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3919 && ! regs_ever_live[2]
3920 && ! frame_pointer_needed);
3924 emit_bcond_fp (code, operand0)
3928 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3929 gen_rtx_IF_THEN_ELSE (VOIDmode,
3930 gen_rtx_fmt_ee (code,
3932 gen_rtx_REG (CCFPmode, 0),
3934 gen_rtx_LABEL_REF (VOIDmode, operand0),
3940 gen_cmp_fp (code, operand0, operand1)
3942 rtx operand0, operand1;
3944 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3945 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3948 /* Adjust the cost of a scheduling dependency. Return the new cost of
3949 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3952 pa_adjust_cost (insn, link, dep_insn, cost)
3958 enum attr_type attr_type;
3960 /* Don't adjust costs for a pa8000 chip, also do not adjust any
3961 true dependencies as they are described with bypasses now. */
3962 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
3965 if (! recog_memoized (insn))
3968 attr_type = get_attr_type (insn);
3970 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3972 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3975 if (attr_type == TYPE_FPLOAD)
3977 rtx pat = PATTERN (insn);
3978 rtx dep_pat = PATTERN (dep_insn);
3979 if (GET_CODE (pat) == PARALLEL)
3981 /* This happens for the fldXs,mb patterns. */
3982 pat = XVECEXP (pat, 0, 0);
3984 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3985 /* If this happens, we have to extend this to schedule
3986 optimally. Return 0 for now. */
3989 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3991 if (! recog_memoized (dep_insn))
3993 switch (get_attr_type (dep_insn))
4000 case TYPE_FPSQRTSGL:
4001 case TYPE_FPSQRTDBL:
4002 /* A fpload can't be issued until one cycle before a
4003 preceding arithmetic operation has finished if
4004 the target of the fpload is any of the sources
4005 (or destination) of the arithmetic operation. */
4006 return insn_default_latency (dep_insn) - 1;
4013 else if (attr_type == TYPE_FPALU)
4015 rtx pat = PATTERN (insn);
4016 rtx dep_pat = PATTERN (dep_insn);
4017 if (GET_CODE (pat) == PARALLEL)
4019 /* This happens for the fldXs,mb patterns. */
4020 pat = XVECEXP (pat, 0, 0);
4022 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4023 /* If this happens, we have to extend this to schedule
4024 optimally. Return 0 for now. */
4027 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4029 if (! recog_memoized (dep_insn))
4031 switch (get_attr_type (dep_insn))
4035 case TYPE_FPSQRTSGL:
4036 case TYPE_FPSQRTDBL:
4037 /* An ALU flop can't be issued until two cycles before a
4038 preceding divide or sqrt operation has finished if
4039 the target of the ALU flop is any of the sources
4040 (or destination) of the divide or sqrt operation. */
4041 return insn_default_latency (dep_insn) - 2;
4049 /* For other anti dependencies, the cost is 0. */
4052 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4054 /* Output dependency; DEP_INSN writes a register that INSN writes some
4056 if (attr_type == TYPE_FPLOAD)
4058 rtx pat = PATTERN (insn);
4059 rtx dep_pat = PATTERN (dep_insn);
4060 if (GET_CODE (pat) == PARALLEL)
4062 /* This happens for the fldXs,mb patterns. */
4063 pat = XVECEXP (pat, 0, 0);
4065 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4066 /* If this happens, we have to extend this to schedule
4067 optimally. Return 0 for now. */
4070 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4072 if (! recog_memoized (dep_insn))
4074 switch (get_attr_type (dep_insn))
4081 case TYPE_FPSQRTSGL:
4082 case TYPE_FPSQRTDBL:
4083 /* A fpload can't be issued until one cycle before a
4084 preceding arithmetic operation has finished if
4085 the target of the fpload is the destination of the
4086 arithmetic operation.
4088 Exception: For PA7100LC, PA7200 and PA7300, the cost
4089 is 3 cycles, unless they bundle together. We also
4090 pay the penalty if the second insn is a fpload. */
4091 return insn_default_latency (dep_insn) - 1;
4098 else if (attr_type == TYPE_FPALU)
4100 rtx pat = PATTERN (insn);
4101 rtx dep_pat = PATTERN (dep_insn);
4102 if (GET_CODE (pat) == PARALLEL)
4104 /* This happens for the fldXs,mb patterns. */
4105 pat = XVECEXP (pat, 0, 0);
4107 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4108 /* If this happens, we have to extend this to schedule
4109 optimally. Return 0 for now. */
4112 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4114 if (! recog_memoized (dep_insn))
4116 switch (get_attr_type (dep_insn))
4120 case TYPE_FPSQRTSGL:
4121 case TYPE_FPSQRTDBL:
4122 /* An ALU flop can't be issued until two cycles before a
4123 preceding divide or sqrt operation has finished if
4124 the target of the ALU flop is also the target of
4125 the divide or sqrt operation. */
4126 return insn_default_latency (dep_insn) - 2;
4134 /* For other output dependencies, the cost is 0. */
4141 /* Adjust scheduling priorities. We use this to try and keep addil
4142 and the next use of %r1 close together. */
4144 pa_adjust_priority (insn, priority)
4148 rtx set = single_set (insn);
4152 src = SET_SRC (set);
4153 dest = SET_DEST (set);
4154 if (GET_CODE (src) == LO_SUM
4155 && symbolic_operand (XEXP (src, 1), VOIDmode)
4156 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4159 else if (GET_CODE (src) == MEM
4160 && GET_CODE (XEXP (src, 0)) == LO_SUM
4161 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4162 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4165 else if (GET_CODE (dest) == MEM
4166 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4167 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4168 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4174 /* The 700 can only issue a single insn at a time.
4175 The 7XXX processors can issue two insns at a time.
4176 The 8000 can issue 4 insns at a time. */
4182 case PROCESSOR_700: return 1;
4183 case PROCESSOR_7100: return 2;
4184 case PROCESSOR_7100LC: return 2;
4185 case PROCESSOR_7200: return 2;
4186 case PROCESSOR_7300: return 2;
4187 case PROCESSOR_8000: return 4;
4196 /* Return any length adjustment needed by INSN which already has its length
4197 computed as LENGTH. Return zero if no adjustment is necessary.
4199 For the PA: function calls, millicode calls, and backwards short
4200 conditional branches with unfilled delay slots need an adjustment by +1
4201 (to account for the NOP which will be inserted into the instruction stream).
4203 Also compute the length of an inline block move here as it is too
4204 complicated to express as a length attribute in pa.md. */
4206 pa_adjust_insn_length (insn, length)
4210 rtx pat = PATTERN (insn);
4212 /* Call insns which are *not* indirect and have unfilled delay slots. */
4213 if (GET_CODE (insn) == CALL_INSN)
4216 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4217 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4219 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4220 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4226 /* Jumps inside switch tables which have unfilled delay slots
4227 also need adjustment. */
4228 else if (GET_CODE (insn) == JUMP_INSN
4229 && simplejump_p (insn)
4230 && GET_MODE (insn) == SImode)
4232 /* Millicode insn with an unfilled delay slot. */
4233 else if (GET_CODE (insn) == INSN
4234 && GET_CODE (pat) != SEQUENCE
4235 && GET_CODE (pat) != USE
4236 && GET_CODE (pat) != CLOBBER
4237 && get_attr_type (insn) == TYPE_MILLI)
4239 /* Block move pattern. */
4240 else if (GET_CODE (insn) == INSN
4241 && GET_CODE (pat) == PARALLEL
4242 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4243 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4244 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4245 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4246 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4247 return compute_movstrsi_length (insn) - 4;
4248 /* Conditional branch with an unfilled delay slot. */
4249 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4251 /* Adjust a short backwards conditional with an unfilled delay slot. */
4252 if (GET_CODE (pat) == SET
4254 && ! forward_branch_p (insn))
4256 else if (GET_CODE (pat) == PARALLEL
4257 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4260 /* Adjust dbra insn with short backwards conditional branch with
4261 unfilled delay slot -- only for case where counter is in a
4262 general register register. */
4263 else if (GET_CODE (pat) == PARALLEL
4264 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4265 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4266 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4268 && ! forward_branch_p (insn))
4276 /* Print operand X (an rtx) in assembler syntax to file FILE.
4277 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4278 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4281 print_operand (file, x, code)
4289 /* Output a 'nop' if there's nothing for the delay slot. */
4290 if (dbr_sequence_length () == 0)
4291 fputs ("\n\tnop", file);
4294 /* Output an nullification completer if there's nothing for the */
4295 /* delay slot or nullification is requested. */
4296 if (dbr_sequence_length () == 0 ||
4298 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4302 /* Print out the second register name of a register pair.
4303 I.e., R (6) => 7. */
4304 fputs (reg_names[REGNO (x) + 1], file);
4307 /* A register or zero. */
4309 || (x == CONST0_RTX (DFmode))
4310 || (x == CONST0_RTX (SFmode)))
4312 fputs ("%r0", file);
4318 /* A register or zero (floating point). */
4320 || (x == CONST0_RTX (DFmode))
4321 || (x == CONST0_RTX (SFmode)))
4323 fputs ("%fr0", file);
4332 xoperands[0] = XEXP (XEXP (x, 0), 0);
4333 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4334 output_global_address (file, xoperands[1], 0);
4335 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4339 case 'C': /* Plain (C)ondition */
4341 switch (GET_CODE (x))
4344 fputs ("=", file); break;
4346 fputs ("<>", file); break;
4348 fputs (">", file); break;
4350 fputs (">=", file); break;
4352 fputs (">>=", file); break;
4354 fputs (">>", file); break;
4356 fputs ("<", file); break;
4358 fputs ("<=", file); break;
4360 fputs ("<<=", file); break;
4362 fputs ("<<", file); break;
4367 case 'N': /* Condition, (N)egated */
4368 switch (GET_CODE (x))
4371 fputs ("<>", file); break;
4373 fputs ("=", file); break;
4375 fputs ("<=", file); break;
4377 fputs ("<", file); break;
4379 fputs ("<<", file); break;
4381 fputs ("<<=", file); break;
4383 fputs (">=", file); break;
4385 fputs (">", file); break;
4387 fputs (">>", file); break;
4389 fputs (">>=", file); break;
4394 /* For floating point comparisons. Note that the output
4395 predicates are the complement of the desired mode. */
4397 switch (GET_CODE (x))
4400 fputs ("!=", file); break;
4402 fputs ("=", file); break;
4404 fputs ("!>", file); break;
4406 fputs ("!>=", file); break;
4408 fputs ("!<", file); break;
4410 fputs ("!<=", file); break;
4412 fputs ("!<>", file); break;
4414 fputs (">", file); break;
4416 fputs (">=", file); break;
4418 fputs ("<", file); break;
4420 fputs ("<=", file); break;
4422 fputs ("<>", file); break;
4424 fputs ("<=>", file); break;
4426 fputs ("!<=>", file); break;
4431 case 'S': /* Condition, operands are (S)wapped. */
4432 switch (GET_CODE (x))
4435 fputs ("=", file); break;
4437 fputs ("<>", file); break;
4439 fputs ("<", file); break;
4441 fputs ("<=", file); break;
4443 fputs ("<<=", file); break;
4445 fputs ("<<", file); break;
4447 fputs (">", file); break;
4449 fputs (">=", file); break;
4451 fputs (">>=", file); break;
4453 fputs (">>", file); break;
4458 case 'B': /* Condition, (B)oth swapped and negate. */
4459 switch (GET_CODE (x))
4462 fputs ("<>", file); break;
4464 fputs ("=", file); break;
4466 fputs (">=", file); break;
4468 fputs (">", file); break;
4470 fputs (">>", file); break;
4472 fputs (">>=", file); break;
4474 fputs ("<=", file); break;
4476 fputs ("<", file); break;
4478 fputs ("<<", file); break;
4480 fputs ("<<=", file); break;
4486 if (GET_CODE (x) == CONST_INT)
4488 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4493 if (GET_CODE (x) == CONST_INT)
4495 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4500 if (GET_CODE (x) == CONST_INT)
4502 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4507 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4509 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4514 if (GET_CODE (x) == CONST_INT)
4516 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4521 if (GET_CODE (x) == CONST_INT)
4523 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4528 if (GET_CODE (x) == CONST_INT)
4533 switch (GET_CODE (XEXP (x, 0)))
4537 if (ASSEMBLER_DIALECT == 0)
4538 fputs ("s,mb", file);
4540 fputs (",mb", file);
4544 if (ASSEMBLER_DIALECT == 0)
4545 fputs ("s,ma", file);
4547 fputs (",ma", file);
4550 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4551 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4553 if (ASSEMBLER_DIALECT == 0)
4554 fputs ("x,s", file);
4558 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4562 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4568 output_global_address (file, x, 0);
4571 output_global_address (file, x, 1);
4573 case 0: /* Don't do anything special */
4578 compute_zdepwi_operands (INTVAL (x), op);
4579 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4585 compute_zdepdi_operands (INTVAL (x), op);
4586 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4590 /* We can get here from a .vtable_inherit due to our
4591 CONSTANT_ADDRESS_P rejecting perfectly good constant
4597 if (GET_CODE (x) == REG)
4599 fputs (reg_names [REGNO (x)], file);
4600 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4606 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4607 && (REGNO (x) & 1) == 0)
4610 else if (GET_CODE (x) == MEM)
4612 int size = GET_MODE_SIZE (GET_MODE (x));
4613 rtx base = NULL_RTX;
4614 switch (GET_CODE (XEXP (x, 0)))
4618 base = XEXP (XEXP (x, 0), 0);
4619 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4623 base = XEXP (XEXP (x, 0), 0);
4624 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4627 if (GET_CODE (XEXP (x, 0)) == PLUS
4628 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4629 fprintf (file, "%s(%s)",
4630 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4631 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4632 else if (GET_CODE (XEXP (x, 0)) == PLUS
4633 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4634 fprintf (file, "%s(%s)",
4635 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4636 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4638 output_address (XEXP (x, 0));
4643 output_addr_const (file, x);
4646 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4649 output_global_address (file, x, round_constant)
4655 /* Imagine (high (const (plus ...))). */
4656 if (GET_CODE (x) == HIGH)
4659 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4660 assemble_name (file, XSTR (x, 0));
4661 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4663 assemble_name (file, XSTR (x, 0));
4664 fputs ("-$global$", file);
4666 else if (GET_CODE (x) == CONST)
4668 const char *sep = "";
4669 int offset = 0; /* assembler wants -$global$ at end */
4670 rtx base = NULL_RTX;
4672 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4674 base = XEXP (XEXP (x, 0), 0);
4675 output_addr_const (file, base);
4677 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4678 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4681 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4683 base = XEXP (XEXP (x, 0), 1);
4684 output_addr_const (file, base);
4686 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4687 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4690 /* How bogus. The compiler is apparently responsible for
4691 rounding the constant if it uses an LR field selector.
4693 The linker and/or assembler seem a better place since
4694 they have to do this kind of thing already.
4696 If we fail to do this, HP's optimizing linker may eliminate
4697 an addil, but not update the ldw/stw/ldo instruction that
4698 uses the result of the addil. */
4700 offset = ((offset + 0x1000) & ~0x1fff);
4702 if (GET_CODE (XEXP (x, 0)) == PLUS)
4712 else if (GET_CODE (XEXP (x, 0)) == MINUS
4713 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4717 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4718 fputs ("-$global$", file);
4720 fprintf (file, "%s%d", sep, offset);
4723 output_addr_const (file, x);
4727 output_deferred_plabels (file)
4731 /* If we have deferred plabels, then we need to switch into the data
4732 section and align it to a 4 byte boundary before we output the
4733 deferred plabels. */
4734 if (n_deferred_plabels)
4737 ASM_OUTPUT_ALIGN (file, 2);
4740 /* Now output the deferred plabels. */
4741 for (i = 0; i < n_deferred_plabels; i++)
4743 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4744 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4745 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4749 /* HP's millicode routines mean something special to the assembler.
4750 Keep track of which ones we have used. */
4752 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
4753 static void import_milli PARAMS ((enum millicodes));
4754 static char imported[(int) end1000];
4755 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
4756 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4757 #define MILLI_START 10
4761 enum millicodes code;
4763 char str[sizeof (import_string)];
4765 if (!imported[(int) code])
4767 imported[(int) code] = 1;
4768 strcpy (str, import_string);
4769 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4770 output_asm_insn (str, 0);
4774 /* The register constraints have put the operands and return value in
4775 the proper registers. */
4778 output_mul_insn (unsignedp, insn)
4779 int unsignedp ATTRIBUTE_UNUSED;
4782 import_milli (mulI);
4783 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4786 /* Emit the rtl for doing a division by a constant. */
4788 /* Do magic division millicodes exist for this value? */
4789 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4792 /* We'll use an array to keep track of the magic millicodes and
4793 whether or not we've used them already. [n][0] is signed, [n][1] is
4796 static int div_milli[16][2];
4799 div_operand (op, mode)
4801 enum machine_mode mode;
4803 return (mode == SImode
4804 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4805 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4806 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4810 emit_hpdiv_const (operands, unsignedp)
4814 if (GET_CODE (operands[2]) == CONST_INT
4815 && INTVAL (operands[2]) > 0
4816 && INTVAL (operands[2]) < 16
4817 && magic_milli[INTVAL (operands[2])])
4819 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4821 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4824 (PARALLEL, VOIDmode,
4825 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4826 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4828 gen_rtx_REG (SImode, 26),
4830 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4831 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4832 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4833 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4834 gen_rtx_CLOBBER (VOIDmode, ret))));
4835 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4842 output_div_insn (operands, unsignedp, insn)
4849 /* If the divisor is a constant, try to use one of the special
4851 if (GET_CODE (operands[0]) == CONST_INT)
4853 static char buf[100];
4854 divisor = INTVAL (operands[0]);
4855 if (!div_milli[divisor][unsignedp])
4857 div_milli[divisor][unsignedp] = 1;
4859 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4861 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4865 sprintf (buf, "$$divU_");
4866 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4867 return output_millicode_call (insn,
4868 gen_rtx_SYMBOL_REF (SImode, buf));
4872 sprintf (buf, "$$divI_");
4873 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4874 return output_millicode_call (insn,
4875 gen_rtx_SYMBOL_REF (SImode, buf));
4878 /* Divisor isn't a special constant. */
4883 import_milli (divU);
4884 return output_millicode_call (insn,
4885 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4889 import_milli (divI);
4890 return output_millicode_call (insn,
4891 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4896 /* Output a $$rem millicode to do mod. */
4899 output_mod_insn (unsignedp, insn)
4905 import_milli (remU);
4906 return output_millicode_call (insn,
4907 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4911 import_milli (remI);
4912 return output_millicode_call (insn,
4913 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4918 output_arg_descriptor (call_insn)
4921 const char *arg_regs[4];
4922 enum machine_mode arg_mode;
4924 int i, output_flag = 0;
4927 /* We neither need nor want argument location descriptors for the
4928 64bit runtime environment or the ELF32 environment. */
4929 if (TARGET_64BIT || TARGET_ELF32)
4932 for (i = 0; i < 4; i++)
4935 /* Specify explicitly that no argument relocations should take place
4936 if using the portable runtime calling conventions. */
4937 if (TARGET_PORTABLE_RUNTIME)
4939 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4944 if (GET_CODE (call_insn) != CALL_INSN)
4946 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4948 rtx use = XEXP (link, 0);
4950 if (! (GET_CODE (use) == USE
4951 && GET_CODE (XEXP (use, 0)) == REG
4952 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4955 arg_mode = GET_MODE (XEXP (use, 0));
4956 regno = REGNO (XEXP (use, 0));
4957 if (regno >= 23 && regno <= 26)
4959 arg_regs[26 - regno] = "GR";
4960 if (arg_mode == DImode)
4961 arg_regs[25 - regno] = "GR";
4963 else if (regno >= 32 && regno <= 39)
4965 if (arg_mode == SFmode)
4966 arg_regs[(regno - 32) / 2] = "FR";
4969 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4970 arg_regs[(regno - 34) / 2] = "FR";
4971 arg_regs[(regno - 34) / 2 + 1] = "FU";
4973 arg_regs[(regno - 34) / 2] = "FU";
4974 arg_regs[(regno - 34) / 2 + 1] = "FR";
4979 fputs ("\t.CALL ", asm_out_file);
4980 for (i = 0; i < 4; i++)
4985 fputc (',', asm_out_file);
4986 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4989 fputc ('\n', asm_out_file);
4992 /* Return the class of any secondary reload register that is needed to
4993 move IN into a register in class CLASS using mode MODE.
4995 Profiling has showed this routine and its descendants account for
4996 a significant amount of compile time (~7%). So it has been
4997 optimized to reduce redundant computations and eliminate useless
5000 It might be worthwhile to try and make this a leaf function too. */
5003 secondary_reload_class (class, mode, in)
5004 enum reg_class class;
5005 enum machine_mode mode;
5008 int regno, is_symbolic;
5010 /* Trying to load a constant into a FP register during PIC code
5011 generation will require %r1 as a scratch register. */
5013 && GET_MODE_CLASS (mode) == MODE_INT
5014 && FP_REG_CLASS_P (class)
5015 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5018 /* Profiling showed the PA port spends about 1.3% of its compilation
5019 time in true_regnum from calls inside secondary_reload_class. */
5021 if (GET_CODE (in) == REG)
5024 if (regno >= FIRST_PSEUDO_REGISTER)
5025 regno = true_regnum (in);
5027 else if (GET_CODE (in) == SUBREG)
5028 regno = true_regnum (in);
5032 /* If we have something like (mem (mem (...)), we can safely assume the
5033 inner MEM will end up in a general register after reloading, so there's
5034 no need for a secondary reload. */
5035 if (GET_CODE (in) == MEM
5036 && GET_CODE (XEXP (in, 0)) == MEM)
5039 /* Handle out of range displacement for integer mode loads/stores of
5041 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5042 && GET_MODE_CLASS (mode) == MODE_INT
5043 && FP_REG_CLASS_P (class))
5044 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5045 return GENERAL_REGS;
5047 /* A SAR<->FP register copy requires a secondary register (GPR) as
5048 well as secondary memory. */
5049 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5050 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5051 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5052 return GENERAL_REGS;
5054 if (GET_CODE (in) == HIGH)
5057 /* Profiling has showed GCC spends about 2.6% of its compilation
5058 time in symbolic_operand from calls inside secondary_reload_class.
5060 We use an inline copy and only compute its return value once to avoid
5062 switch (GET_CODE (in))
5072 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5073 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5074 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5084 && read_only_operand (in, VOIDmode))
5087 if (class != R1_REGS && is_symbolic)
5094 function_arg_padding (mode, type)
5095 enum machine_mode mode;
5099 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5101 /* Return none if justification is not required. */
5103 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5104 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5107 /* The directions set here are ignored when a BLKmode argument larger
5108 than a word is placed in a register. Different code is used for
5109 the stack and registers. This makes it difficult to have a
5110 consistent data representation for both the stack and registers.
5111 For both runtimes, the justification and padding for arguments on
5112 the stack and in registers should be identical. */
5114 /* The 64-bit runtime specifies left justification for aggregates. */
5117 /* The 32-bit runtime architecture specifies right justification.
5118 When the argument is passed on the stack, the argument is padded
5119 with garbage on the left. The HP compiler pads with zeros. */
5123 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5130 /* Do what is necessary for `va_start'. We look at the current function
5131 to determine if stdargs or varargs is used and fill in an initial
5132 va_list. A pointer to this constructor is returned. */
5135 hppa_builtin_saveregs ()
5138 tree fntype = TREE_TYPE (current_function_decl);
5139 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5140 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5141 != void_type_node)))
5142 ? UNITS_PER_WORD : 0);
5145 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5147 offset = current_function_arg_offset_rtx;
5153 /* Adjust for varargs/stdarg differences. */
5155 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5157 offset = current_function_arg_offset_rtx;
5159 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5160 from the incoming arg pointer and growing to larger addresses. */
5161 for (i = 26, off = -64; i >= 19; i--, off += 8)
5162 emit_move_insn (gen_rtx_MEM (word_mode,
5163 plus_constant (arg_pointer_rtx, off)),
5164 gen_rtx_REG (word_mode, i));
5166 /* The incoming args pointer points just beyond the flushback area;
5167 normally this is not a serious concern. However, when we are doing
5168 varargs/stdargs we want to make the arg pointer point to the start
5169 of the incoming argument area. */
5170 emit_move_insn (virtual_incoming_args_rtx,
5171 plus_constant (arg_pointer_rtx, -64));
5173 /* Now return a pointer to the first anonymous argument. */
5174 return copy_to_reg (expand_binop (Pmode, add_optab,
5175 virtual_incoming_args_rtx,
5176 offset, 0, 0, OPTAB_LIB_WIDEN));
5179 /* Store general registers on the stack. */
5180 dest = gen_rtx_MEM (BLKmode,
5181 plus_constant (current_function_internal_arg_pointer,
5183 set_mem_alias_set (dest, get_varargs_alias_set ());
5184 set_mem_align (dest, BITS_PER_WORD);
5185 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5187 /* move_block_from_reg will emit code to store the argument registers
5188 individually as scalar stores.
5190 However, other insns may later load from the same addresses for
5191 a structure load (passing a struct to a varargs routine).
5193 The alias code assumes that such aliasing can never happen, so we
5194 have to keep memory referencing insns from moving up beyond the
5195 last argument register store. So we emit a blockage insn here. */
5196 emit_insn (gen_blockage ());
5198 return copy_to_reg (expand_binop (Pmode, add_optab,
5199 current_function_internal_arg_pointer,
5200 offset, 0, 0, OPTAB_LIB_WIDEN));
5204 hppa_va_start (valist, nextarg)
5208 nextarg = expand_builtin_saveregs ();
5209 std_expand_builtin_va_start (valist, nextarg);
5213 hppa_va_arg (valist, type)
5216 HOST_WIDE_INT size = int_size_in_bytes (type);
5222 /* Every argument in PA64 is supposed to be passed by value
5223 (including large structs). However, as a GCC extension, we
5224 pass zero and variable sized arguments by reference. Empty
5225 structures are a GCC extension not supported by the HP
5226 compilers. Thus, passing them by reference isn't likely
5227 to conflict with the ABI. For variable sized arguments,
5228 GCC doesn't have the infrastructure to allocate these to
5231 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5233 if (size > UNITS_PER_WORD)
5235 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5236 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5237 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5238 build_int_2 (-2 * UNITS_PER_WORD, -1));
5239 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5240 TREE_SIDE_EFFECTS (t) = 1;
5241 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5245 return std_expand_builtin_va_arg (valist, type);
5248 ptr = build_pointer_type (type);
5250 /* Args grow upward. */
5251 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5252 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5253 TREE_SIDE_EFFECTS (t) = 1;
5255 pptr = build_pointer_type (ptr);
5256 t = build1 (NOP_EXPR, pptr, t);
5257 TREE_SIDE_EFFECTS (t) = 1;
5259 t = build1 (INDIRECT_REF, ptr, t);
5260 TREE_SIDE_EFFECTS (t) = 1;
5263 else /* !TARGET_64BIT */
5265 ptr = build_pointer_type (type);
5267 /* "Large" and variable sized types are passed by reference. */
5268 if (size > 8 || size <= 0)
5270 /* Args grow downward. */
5271 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5272 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5273 TREE_SIDE_EFFECTS (t) = 1;
5275 pptr = build_pointer_type (ptr);
5276 t = build1 (NOP_EXPR, pptr, t);
5277 TREE_SIDE_EFFECTS (t) = 1;
5279 t = build1 (INDIRECT_REF, ptr, t);
5280 TREE_SIDE_EFFECTS (t) = 1;
5284 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5285 build_int_2 (-size, -1));
5287 /* Copied from va-pa.h, but we probably don't need to align to
5288 word size, since we generate and preserve that invariant. */
5289 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5290 build_int_2 ((size > 4 ? -8 : -4), -1));
5292 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5293 TREE_SIDE_EFFECTS (t) = 1;
5295 ofs = (8 - size) % 4;
5298 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
5299 build_int_2 (ofs, 0));
5300 TREE_SIDE_EFFECTS (t) = 1;
5303 t = build1 (NOP_EXPR, ptr, t);
5304 TREE_SIDE_EFFECTS (t) = 1;
5309 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
5314 /* This routine handles all the normal conditional branch sequences we
5315 might need to generate. It handles compare immediate vs compare
5316 register, nullification of delay slots, varying length branches,
5317 negated branches, and all combinations of the above. It returns the
5318 output appropriate to emit the branch corresponding to all given
5322 output_cbranch (operands, nullify, length, negated, insn)
5324 int nullify, length, negated;
5327 static char buf[100];
5330 /* A conditional branch to the following instruction (eg the delay slot) is
5331 asking for a disaster. This can happen when not optimizing.
5333 In such cases it is safe to emit nothing. */
5335 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5338 /* If this is a long branch with its delay slot unfilled, set `nullify'
5339 as it can nullify the delay slot and save a nop. */
5340 if (length == 8 && dbr_sequence_length () == 0)
5343 /* If this is a short forward conditional branch which did not get
5344 its delay slot filled, the delay slot can still be nullified. */
5345 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5346 nullify = forward_branch_p (insn);
5348 /* A forward branch over a single nullified insn can be done with a
5349 comclr instruction. This avoids a single cycle penalty due to
5350 mis-predicted branch if we fall through (branch not taken). */
5352 && next_real_insn (insn) != 0
5353 && get_attr_length (next_real_insn (insn)) == 4
5354 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5360 /* All short conditional branches except backwards with an unfilled
5364 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5366 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5367 if (GET_MODE (operands[1]) == DImode)
5370 strcat (buf, "%B3");
5372 strcat (buf, "%S3");
5374 strcat (buf, " %2,%r1,%%r0");
5376 strcat (buf, ",n %2,%r1,%0");
5378 strcat (buf, " %2,%r1,%0");
5381 /* All long conditionals. Note an short backward branch with an
5382 unfilled delay slot is treated just like a long backward branch
5383 with an unfilled delay slot. */
5385 /* Handle weird backwards branch with a filled delay slot
5386 with is nullified. */
5387 if (dbr_sequence_length () != 0
5388 && ! forward_branch_p (insn)
5391 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5392 if (GET_MODE (operands[1]) == DImode)
5395 strcat (buf, "%S3");
5397 strcat (buf, "%B3");
5398 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5400 /* Handle short backwards branch with an unfilled delay slot.
5401 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5402 taken and untaken branches. */
5403 else if (dbr_sequence_length () == 0
5404 && ! forward_branch_p (insn)
5405 && INSN_ADDRESSES_SET_P ()
5406 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5407 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5409 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5410 if (GET_MODE (operands[1]) == DImode)
5413 strcat (buf, "%B3 %2,%r1,%0%#");
5415 strcat (buf, "%S3 %2,%r1,%0%#");
5419 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5420 if (GET_MODE (operands[1]) == DImode)
5423 strcat (buf, "%S3");
5425 strcat (buf, "%B3");
5427 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5429 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5434 /* Very long branch. Right now we only handle these when not
5435 optimizing. See "jump" pattern in pa.md for details. */
5439 /* Create a reversed conditional branch which branches around
5440 the following insns. */
5442 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5444 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5445 if (GET_MODE (operands[1]) == DImode)
5449 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5452 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5454 output_asm_insn (buf, operands);
5456 /* Output an insn to save %r1. */
5457 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5459 /* Now output a very long branch to the original target. */
5460 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5462 /* Now restore the value of %r1 in the delay slot. We're not
5463 optimizing so we know nothing else can be in the delay slot. */
5464 return "ldw -16(%%r30),%%r1";
5467 /* Very long branch when generating PIC code. Right now we only
5468 handle these when not optimizing. See "jump" pattern in pa.md
5473 /* Create a reversed conditional branch which branches around
5474 the following insns. */
5476 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5478 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5479 if (GET_MODE (operands[1]) == DImode)
5482 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5484 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5486 output_asm_insn (buf, operands);
5488 /* Output an insn to save %r1. */
5489 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5491 /* Now output a very long PIC branch to the original target. */
5495 xoperands[0] = operands[0];
5496 xoperands[1] = operands[1];
5497 xoperands[2] = operands[2];
5498 xoperands[3] = operands[3];
5499 if (TARGET_SOM || ! TARGET_GAS)
5500 xoperands[4] = gen_label_rtx ();
5502 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5503 if (TARGET_SOM || ! TARGET_GAS)
5505 output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands);
5506 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5507 CODE_LABEL_NUMBER (xoperands[4]));
5508 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands);
5512 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5513 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1",
5516 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5519 /* Now restore the value of %r1 in the delay slot. We're not
5520 optimizing so we know nothing else can be in the delay slot. */
5521 return "ldw -16(%%r30),%%r1";
5529 /* This routine handles all the branch-on-bit conditional branch sequences we
5530 might need to generate. It handles nullification of delay slots,
5531 varying length branches, negated branches and all combinations of the
5532 above. it returns the appropriate output template to emit the branch. */
5535 output_bb (operands, nullify, length, negated, insn, which)
5536 rtx *operands ATTRIBUTE_UNUSED;
5537 int nullify, length, negated;
5541 static char buf[100];
5544 /* A conditional branch to the following instruction (eg the delay slot) is
5545 asking for a disaster. I do not think this can happen as this pattern
5546 is only used when optimizing; jump optimization should eliminate the
5547 jump. But be prepared just in case. */
5549 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5552 /* If this is a long branch with its delay slot unfilled, set `nullify'
5553 as it can nullify the delay slot and save a nop. */
5554 if (length == 8 && dbr_sequence_length () == 0)
5557 /* If this is a short forward conditional branch which did not get
5558 its delay slot filled, the delay slot can still be nullified. */
5559 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5560 nullify = forward_branch_p (insn);
5562 /* A forward branch over a single nullified insn can be done with a
5563 extrs instruction. This avoids a single cycle penalty due to
5564 mis-predicted branch if we fall through (branch not taken). */
5567 && next_real_insn (insn) != 0
5568 && get_attr_length (next_real_insn (insn)) == 4
5569 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5576 /* All short conditional branches except backwards with an unfilled
5580 strcpy (buf, "{extrs,|extrw,s,}");
5582 strcpy (buf, "bb,");
5583 if (useskip && GET_MODE (operands[0]) == DImode)
5584 strcpy (buf, "extrd,s,*");
5585 else if (GET_MODE (operands[0]) == DImode)
5586 strcpy (buf, "bb,*");
5587 if ((which == 0 && negated)
5588 || (which == 1 && ! negated))
5593 strcat (buf, " %0,%1,1,%%r0");
5594 else if (nullify && negated)
5595 strcat (buf, ",n %0,%1,%3");
5596 else if (nullify && ! negated)
5597 strcat (buf, ",n %0,%1,%2");
5598 else if (! nullify && negated)
5599 strcat (buf, "%0,%1,%3");
5600 else if (! nullify && ! negated)
5601 strcat (buf, " %0,%1,%2");
5604 /* All long conditionals. Note an short backward branch with an
5605 unfilled delay slot is treated just like a long backward branch
5606 with an unfilled delay slot. */
5608 /* Handle weird backwards branch with a filled delay slot
5609 with is nullified. */
5610 if (dbr_sequence_length () != 0
5611 && ! forward_branch_p (insn)
5614 strcpy (buf, "bb,");
5615 if (GET_MODE (operands[0]) == DImode)
5617 if ((which == 0 && negated)
5618 || (which == 1 && ! negated))
5623 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5625 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5627 /* Handle short backwards branch with an unfilled delay slot.
5628 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5629 taken and untaken branches. */
5630 else if (dbr_sequence_length () == 0
5631 && ! forward_branch_p (insn)
5632 && INSN_ADDRESSES_SET_P ()
5633 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5634 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5636 strcpy (buf, "bb,");
5637 if (GET_MODE (operands[0]) == DImode)
5639 if ((which == 0 && negated)
5640 || (which == 1 && ! negated))
5645 strcat (buf, " %0,%1,%3%#");
5647 strcat (buf, " %0,%1,%2%#");
5651 strcpy (buf, "{extrs,|extrw,s,}");
5652 if (GET_MODE (operands[0]) == DImode)
5653 strcpy (buf, "extrd,s,*");
5654 if ((which == 0 && negated)
5655 || (which == 1 && ! negated))
5659 if (nullify && negated)
5660 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5661 else if (nullify && ! negated)
5662 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5664 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5666 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5676 /* This routine handles all the branch-on-variable-bit conditional branch
5677 sequences we might need to generate. It handles nullification of delay
5678 slots, varying length branches, negated branches and all combinations
5679 of the above. it returns the appropriate output template to emit the
5683 output_bvb (operands, nullify, length, negated, insn, which)
5684 rtx *operands ATTRIBUTE_UNUSED;
5685 int nullify, length, negated;
5689 static char buf[100];
5692 /* A conditional branch to the following instruction (eg the delay slot) is
5693 asking for a disaster. I do not think this can happen as this pattern
5694 is only used when optimizing; jump optimization should eliminate the
5695 jump. But be prepared just in case. */
5697 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5700 /* If this is a long branch with its delay slot unfilled, set `nullify'
5701 as it can nullify the delay slot and save a nop. */
5702 if (length == 8 && dbr_sequence_length () == 0)
5705 /* If this is a short forward conditional branch which did not get
5706 its delay slot filled, the delay slot can still be nullified. */
5707 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5708 nullify = forward_branch_p (insn);
5710 /* A forward branch over a single nullified insn can be done with a
5711 extrs instruction. This avoids a single cycle penalty due to
5712 mis-predicted branch if we fall through (branch not taken). */
5715 && next_real_insn (insn) != 0
5716 && get_attr_length (next_real_insn (insn)) == 4
5717 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5724 /* All short conditional branches except backwards with an unfilled
5728 strcpy (buf, "{vextrs,|extrw,s,}");
5730 strcpy (buf, "{bvb,|bb,}");
5731 if (useskip && GET_MODE (operands[0]) == DImode)
5732 strcpy (buf, "extrd,s,*}");
5733 else if (GET_MODE (operands[0]) == DImode)
5734 strcpy (buf, "bb,*");
5735 if ((which == 0 && negated)
5736 || (which == 1 && ! negated))
5741 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5742 else if (nullify && negated)
5743 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5744 else if (nullify && ! negated)
5745 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5746 else if (! nullify && negated)
5747 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5748 else if (! nullify && ! negated)
5749 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5752 /* All long conditionals. Note an short backward branch with an
5753 unfilled delay slot is treated just like a long backward branch
5754 with an unfilled delay slot. */
5756 /* Handle weird backwards branch with a filled delay slot
5757 with is nullified. */
5758 if (dbr_sequence_length () != 0
5759 && ! forward_branch_p (insn)
5762 strcpy (buf, "{bvb,|bb,}");
5763 if (GET_MODE (operands[0]) == DImode)
5765 if ((which == 0 && negated)
5766 || (which == 1 && ! negated))
5771 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5773 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5775 /* Handle short backwards branch with an unfilled delay slot.
5776 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5777 taken and untaken branches. */
5778 else if (dbr_sequence_length () == 0
5779 && ! forward_branch_p (insn)
5780 && INSN_ADDRESSES_SET_P ()
5781 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5782 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5784 strcpy (buf, "{bvb,|bb,}");
5785 if (GET_MODE (operands[0]) == DImode)
5787 if ((which == 0 && negated)
5788 || (which == 1 && ! negated))
5793 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5795 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5799 strcpy (buf, "{vextrs,|extrw,s,}");
5800 if (GET_MODE (operands[0]) == DImode)
5801 strcpy (buf, "extrd,s,*");
5802 if ((which == 0 && negated)
5803 || (which == 1 && ! negated))
5807 if (nullify && negated)
5808 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5809 else if (nullify && ! negated)
5810 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5812 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5814 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5824 /* Return the output template for emitting a dbra type insn.
5826 Note it may perform some output operations on its own before
5827 returning the final output string. */
5829 output_dbra (operands, insn, which_alternative)
5832 int which_alternative;
5835 /* A conditional branch to the following instruction (eg the delay slot) is
5836 asking for a disaster. Be prepared! */
5838 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5840 if (which_alternative == 0)
5841 return "ldo %1(%0),%0";
5842 else if (which_alternative == 1)
5844 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5845 output_asm_insn ("ldw -16(%%r30),%4", operands);
5846 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5847 return "{fldws|fldw} -16(%%r30),%0";
5851 output_asm_insn ("ldw %0,%4", operands);
5852 return "ldo %1(%4),%4\n\tstw %4,%0";
5856 if (which_alternative == 0)
5858 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5859 int length = get_attr_length (insn);
5861 /* If this is a long branch with its delay slot unfilled, set `nullify'
5862 as it can nullify the delay slot and save a nop. */
5863 if (length == 8 && dbr_sequence_length () == 0)
5866 /* If this is a short forward conditional branch which did not get
5867 its delay slot filled, the delay slot can still be nullified. */
5868 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5869 nullify = forward_branch_p (insn);
5871 /* Handle short versions first. */
5872 if (length == 4 && nullify)
5873 return "addib,%C2,n %1,%0,%3";
5874 else if (length == 4 && ! nullify)
5875 return "addib,%C2 %1,%0,%3";
5876 else if (length == 8)
5878 /* Handle weird backwards branch with a fulled delay slot
5879 which is nullified. */
5880 if (dbr_sequence_length () != 0
5881 && ! forward_branch_p (insn)
5883 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5884 /* Handle short backwards branch with an unfilled delay slot.
5885 Using a addb;nop rather than addi;bl saves 1 cycle for both
5886 taken and untaken branches. */
5887 else if (dbr_sequence_length () == 0
5888 && ! forward_branch_p (insn)
5889 && INSN_ADDRESSES_SET_P ()
5890 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5891 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5892 return "addib,%C2 %1,%0,%3%#";
5894 /* Handle normal cases. */
5896 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5898 return "addi,%N2 %1,%0,%0\n\tb %3";
5903 /* Deal with gross reload from FP register case. */
5904 else if (which_alternative == 1)
5906 /* Move loop counter from FP register to MEM then into a GR,
5907 increment the GR, store the GR into MEM, and finally reload
5908 the FP register from MEM from within the branch's delay slot. */
5909 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5911 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5912 if (get_attr_length (insn) == 24)
5913 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5915 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5917 /* Deal with gross reload from memory case. */
5920 /* Reload loop counter from memory, the store back to memory
5921 happens in the branch's delay slot. */
5922 output_asm_insn ("ldw %0,%4", operands);
5923 if (get_attr_length (insn) == 12)
5924 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5926 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5930 /* Return the output template for emitting a dbra type insn.
5932 Note it may perform some output operations on its own before
5933 returning the final output string. */
5935 output_movb (operands, insn, which_alternative, reverse_comparison)
5938 int which_alternative;
5939 int reverse_comparison;
5942 /* A conditional branch to the following instruction (eg the delay slot) is
5943 asking for a disaster. Be prepared! */
5945 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5947 if (which_alternative == 0)
5948 return "copy %1,%0";
5949 else if (which_alternative == 1)
5951 output_asm_insn ("stw %1,-16(%%r30)", operands);
5952 return "{fldws|fldw} -16(%%r30),%0";
5954 else if (which_alternative == 2)
5960 /* Support the second variant. */
5961 if (reverse_comparison)
5962 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5964 if (which_alternative == 0)
5966 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5967 int length = get_attr_length (insn);
5969 /* If this is a long branch with its delay slot unfilled, set `nullify'
5970 as it can nullify the delay slot and save a nop. */
5971 if (length == 8 && dbr_sequence_length () == 0)
5974 /* If this is a short forward conditional branch which did not get
5975 its delay slot filled, the delay slot can still be nullified. */
5976 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5977 nullify = forward_branch_p (insn);
5979 /* Handle short versions first. */
5980 if (length == 4 && nullify)
5981 return "movb,%C2,n %1,%0,%3";
5982 else if (length == 4 && ! nullify)
5983 return "movb,%C2 %1,%0,%3";
5984 else if (length == 8)
5986 /* Handle weird backwards branch with a filled delay slot
5987 which is nullified. */
5988 if (dbr_sequence_length () != 0
5989 && ! forward_branch_p (insn)
5991 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5993 /* Handle short backwards branch with an unfilled delay slot.
5994 Using a movb;nop rather than or;bl saves 1 cycle for both
5995 taken and untaken branches. */
5996 else if (dbr_sequence_length () == 0
5997 && ! forward_branch_p (insn)
5998 && INSN_ADDRESSES_SET_P ()
5999 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6000 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6001 return "movb,%C2 %1,%0,%3%#";
6002 /* Handle normal cases. */
6004 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6006 return "or,%N2 %1,%%r0,%0\n\tb %3";
6011 /* Deal with gross reload from FP register case. */
6012 else if (which_alternative == 1)
6014 /* Move loop counter from FP register to MEM then into a GR,
6015 increment the GR, store the GR into MEM, and finally reload
6016 the FP register from MEM from within the branch's delay slot. */
6017 output_asm_insn ("stw %1,-16(%%r30)", operands);
6018 if (get_attr_length (insn) == 12)
6019 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6021 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6023 /* Deal with gross reload from memory case. */
6024 else if (which_alternative == 2)
6026 /* Reload loop counter from memory, the store back to memory
6027 happens in the branch's delay slot. */
6028 if (get_attr_length (insn) == 8)
6029 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6031 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6033 /* Handle SAR as a destination. */
6036 if (get_attr_length (insn) == 8)
6037 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6039 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6044 /* INSN is a millicode call. It may have an unconditional jump in its delay
6047 CALL_DEST is the routine we are calling. */
6050 output_millicode_call (insn, call_dest)
6054 int attr_length = get_attr_length (insn);
6055 int seq_length = dbr_sequence_length ();
6060 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6062 /* Handle common case -- empty delay slot or no jump in the delay slot,
6063 and we're sure that the branch will reach the beginning of the $CODE$
6064 subspace. The within reach form of the $$sh_func_adrs call has
6065 a length of 28 and attribute type of multi. This length is the
6066 same as the maximum length of an out of reach PIC call to $$div. */
6067 if ((seq_length == 0
6068 && (attr_length == 8
6069 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6071 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6072 && attr_length == 4))
6074 xoperands[0] = call_dest;
6075 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
6079 /* This call may not reach the beginning of the $CODE$ subspace. */
6080 if (attr_length > 8)
6082 int delay_insn_deleted = 0;
6084 /* We need to emit an inline long-call branch. */
6086 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6088 /* A non-jump insn in the delay slot. By definition we can
6089 emit this insn before the call. */
6090 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6092 /* Now delete the delay insn. */
6093 PUT_CODE (NEXT_INSN (insn), NOTE);
6094 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6095 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6096 delay_insn_deleted = 1;
6099 /* PIC long millicode call sequence. */
6102 xoperands[0] = call_dest;
6103 if (TARGET_SOM || ! TARGET_GAS)
6104 xoperands[1] = gen_label_rtx ();
6106 /* Get our address + 8 into %r1. */
6107 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6109 if (TARGET_SOM || ! TARGET_GAS)
6111 /* Add %r1 to the offset of our target from the next insn. */
6112 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
6113 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6114 CODE_LABEL_NUMBER (xoperands[1]));
6115 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
6119 output_asm_insn ("addil L%%%0-$PIC_pcrel$0+4,%%r1", xoperands);
6120 output_asm_insn ("ldo R%%%0-$PIC_pcrel$0+8(%%r1),%%r1",
6124 /* Get the return address into %r31. */
6125 output_asm_insn ("blr 0,%3", xoperands);
6127 /* Branch to our target which is in %r1. */
6128 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
6130 /* Empty delay slot. Note this insn gets fetched twice and
6131 executed once. To be safe we use a nop. */
6132 output_asm_insn ("nop", xoperands);
6134 /* Pure portable runtime doesn't allow be/ble; we also don't have
6135 PIC support in the assembler/linker, so this sequence is needed. */
6136 else if (TARGET_PORTABLE_RUNTIME)
6138 xoperands[0] = call_dest;
6139 /* Get the address of our target into %r29. */
6140 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
6141 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
6143 /* Get our return address into %r31. */
6144 output_asm_insn ("blr %%r0,%3", xoperands);
6146 /* Jump to our target address in %r29. */
6147 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
6149 /* Empty delay slot. Note this insn gets fetched twice and
6150 executed once. To be safe we use a nop. */
6151 output_asm_insn ("nop", xoperands);
6153 /* If we're allowed to use be/ble instructions, then this is the
6154 best sequence to use for a long millicode call. */
6157 xoperands[0] = call_dest;
6158 output_asm_insn ("ldil L%%%0,%3", xoperands);
6160 output_asm_insn ("be,l R%%%0(%%sr4,%3),%%sr0,%%r31", xoperands);
6162 output_asm_insn ("ble R%%%0(%%sr4,%3)", xoperands);
6163 output_asm_insn ("nop", xoperands);
6166 /* If we had a jump in the call's delay slot, output it now. */
6167 if (seq_length != 0 && !delay_insn_deleted)
6169 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6170 output_asm_insn ("b,n %0", xoperands);
6172 /* Now delete the delay insn. */
6173 PUT_CODE (NEXT_INSN (insn), NOTE);
6174 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6175 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6180 /* This call has an unconditional jump in its delay slot and the
6181 call is known to reach its target or the beginning of the current
6184 /* Use the containing sequence insn's address. */
6185 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6187 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6188 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6190 /* If the branch was too far away, emit a normal call followed
6191 by a nop, followed by the unconditional branch.
6193 If the branch is close, then adjust %r2 from within the
6194 call's delay slot. */
6196 xoperands[0] = call_dest;
6197 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6198 if (! VAL_14_BITS_P (distance))
6199 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
6202 xoperands[2] = gen_label_rtx ();
6203 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
6205 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6206 CODE_LABEL_NUMBER (xoperands[2]));
6209 /* Delete the jump. */
6210 PUT_CODE (NEXT_INSN (insn), NOTE);
6211 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6212 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6216 /* INSN is either a function call. It may have an unconditional jump
6219 CALL_DEST is the routine we are calling. */
6222 output_call (insn, call_dest, sibcall)
6227 int attr_length = get_attr_length (insn);
6228 int seq_length = dbr_sequence_length ();
6233 /* Handle common case -- empty delay slot or no jump in the delay slot,
6234 and we're sure that the branch will reach the beginning of the $CODE$
6236 if ((seq_length == 0 && attr_length == 12)
6238 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6239 && attr_length == 8))
6241 xoperands[0] = call_dest;
6242 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6243 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
6247 /* This call may not reach the beginning of the $CODE$ subspace. */
6248 if (attr_length > 12)
6250 int delay_insn_deleted = 0;
6254 /* We need to emit an inline long-call branch. Furthermore,
6255 because we're changing a named function call into an indirect
6256 function call well after the parameters have been set up, we
6257 need to make sure any FP args appear in both the integer
6258 and FP registers. Also, we need move any delay slot insn
6259 out of the delay slot. And finally, we can't rely on the linker
6260 being able to fix the call to $$dyncall! -- Yuk!. */
6262 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6264 /* A non-jump insn in the delay slot. By definition we can
6265 emit this insn before the call (and in fact before argument
6267 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6269 /* Now delete the delay insn. */
6270 PUT_CODE (NEXT_INSN (insn), NOTE);
6271 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6272 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6273 delay_insn_deleted = 1;
6276 /* Now copy any FP arguments into integer registers. */
6277 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6279 int arg_mode, regno;
6280 rtx use = XEXP (link, 0);
6281 if (! (GET_CODE (use) == USE
6282 && GET_CODE (XEXP (use, 0)) == REG
6283 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6286 arg_mode = GET_MODE (XEXP (use, 0));
6287 regno = REGNO (XEXP (use, 0));
6288 /* Is it a floating point register? */
6289 if (regno >= 32 && regno <= 39)
6291 /* Copy from the FP register into an integer register
6293 if (arg_mode == SFmode)
6295 xoperands[0] = XEXP (use, 0);
6296 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6297 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
6299 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6303 xoperands[0] = XEXP (use, 0);
6304 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6305 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
6307 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6308 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6313 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
6314 we don't have any direct calls in that case. */
6317 const char *name = XSTR (call_dest, 0);
6319 /* See if we have already put this function on the list
6320 of deferred plabels. This list is generally small,
6321 so a liner search is not too ugly. If it proves too
6322 slow replace it with something faster. */
6323 for (i = 0; i < n_deferred_plabels; i++)
6324 if (strcmp (name, deferred_plabels[i].name) == 0)
6327 /* If the deferred plabel list is empty, or this entry was
6328 not found on the list, create a new entry on the list. */
6329 if (deferred_plabels == NULL || i == n_deferred_plabels)
6331 const char *real_name;
6333 if (deferred_plabels == 0)
6334 deferred_plabels = (struct deferred_plabel *)
6335 ggc_alloc (sizeof (struct deferred_plabel));
6337 deferred_plabels = (struct deferred_plabel *)
6338 ggc_realloc (deferred_plabels,
6339 ((n_deferred_plabels + 1)
6340 * sizeof (struct deferred_plabel)));
6342 i = n_deferred_plabels++;
6343 deferred_plabels[i].internal_label = gen_label_rtx ();
6344 deferred_plabels[i].name = ggc_strdup (name);
6346 /* Gross. We have just implicitly taken the address of this
6347 function, mark it as such. */
6348 real_name = (*targetm.strip_name_encoding) (name);
6349 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
6352 /* We have to load the address of the function using a procedure
6353 label (plabel). Inline plabels can lose for PIC and other
6354 cases, so avoid them by creating a 32bit plabel in the data
6358 xoperands[0] = deferred_plabels[i].internal_label;
6359 if (TARGET_SOM || ! TARGET_GAS)
6360 xoperands[1] = gen_label_rtx ();
6362 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6363 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6364 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6366 /* Get our address + 8 into %r1. */
6367 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6369 if (TARGET_SOM || ! TARGET_GAS)
6371 /* Add %r1 to the offset of dyncall from the next insn. */
6372 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6373 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6374 CODE_LABEL_NUMBER (xoperands[1]));
6375 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6379 output_asm_insn ("addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1",
6381 output_asm_insn ("ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
6385 /* Get the return address into %r31. */
6386 output_asm_insn ("blr %%r0,%%r31", xoperands);
6388 /* Branch to our target which is in %r1. */
6389 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6393 /* This call never returns, so we do not need to fix the
6395 output_asm_insn ("nop", xoperands);
6399 /* Copy the return address into %r2 also. */
6400 output_asm_insn ("copy %%r31,%%r2", xoperands);
6405 xoperands[0] = deferred_plabels[i].internal_label;
6407 /* Get the address of our target into %r22. */
6408 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6409 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6411 /* Get the high part of the address of $dyncall into %r2, then
6412 add in the low part in the branch instruction. */
6413 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6415 output_asm_insn ("be,l R%%$$dyncall(%%sr4,%%r2),%%sr0,%%r31",
6418 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
6422 /* This call never returns, so we do not need to fix the
6424 output_asm_insn ("nop", xoperands);
6428 /* Copy the return address into %r2 also. */
6429 output_asm_insn ("copy %%r31,%%r2", xoperands);
6434 /* If we had a jump in the call's delay slot, output it now. */
6435 if (seq_length != 0 && !delay_insn_deleted)
6437 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6438 output_asm_insn ("b,n %0", xoperands);
6440 /* Now delete the delay insn. */
6441 PUT_CODE (NEXT_INSN (insn), NOTE);
6442 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6443 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6448 /* This call has an unconditional jump in its delay slot and the
6449 call is known to reach its target or the beginning of the current
6452 /* Use the containing sequence insn's address. */
6453 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6455 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6456 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6458 /* If the branch is too far away, emit a normal call followed
6459 by a nop, followed by the unconditional branch. If the branch
6460 is close, then adjust %r2 in the call's delay slot. */
6462 xoperands[0] = call_dest;
6463 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6464 if (! VAL_14_BITS_P (distance))
6465 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6468 xoperands[3] = gen_label_rtx ();
6469 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6471 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6472 CODE_LABEL_NUMBER (xoperands[3]));
6475 /* Delete the jump. */
6476 PUT_CODE (NEXT_INSN (insn), NOTE);
6477 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6478 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6482 /* In HPUX 8.0's shared library scheme, special relocations are needed
6483 for function labels if they might be passed to a function
6484 in a shared library (because shared libraries don't live in code
6485 space), and special magic is needed to construct their address. */
6488 hppa_encode_label (sym)
6491 const char *str = XSTR (sym, 0);
6492 int len = strlen (str) + 1;
6495 p = newstr = alloca (len + 1);
6499 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6503 pa_encode_section_info (decl, first)
6507 if (first && TEXT_SPACE_P (decl))
6510 if (TREE_CODE (decl) == FUNCTION_DECL
6511 || TREE_CODE (decl) == VAR_DECL)
6512 rtl = DECL_RTL (decl);
6514 rtl = TREE_CST_RTL (decl);
6515 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
6516 if (TREE_CODE (decl) == FUNCTION_DECL)
6517 hppa_encode_label (XEXP (DECL_RTL (decl), 0));
6521 /* This is sort of inverse to pa_encode_section_info. */
6524 pa_strip_name_encoding (str)
6527 str += (*str == '@');
6528 str += (*str == '*');
6533 function_label_operand (op, mode)
6535 enum machine_mode mode ATTRIBUTE_UNUSED;
6537 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6540 /* Returns 1 if OP is a function label involved in a simple addition
6541 with a constant. Used to keep certain patterns from matching
6542 during instruction combination. */
6544 is_function_label_plus_const (op)
6547 /* Strip off any CONST. */
6548 if (GET_CODE (op) == CONST)
6551 return (GET_CODE (op) == PLUS
6552 && function_label_operand (XEXP (op, 0), Pmode)
6553 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6556 /* Output assembly code for a thunk to FUNCTION. */
6559 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, function)
6562 HOST_WIDE_INT delta;
6565 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
6566 static unsigned int current_thunk_number;
6569 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
6570 lab = (*targetm.strip_name_encoding) (label);
6571 target_name = (*targetm.strip_name_encoding) (target_name);
6572 /* FIXME: total_code_bytes is not handled correctly in files with
6574 pa_output_function_prologue (file, 0);
6575 if (VAL_14_BITS_P (delta))
6577 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6579 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6580 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6581 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6582 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6583 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6584 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6585 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6586 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6587 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
6588 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6589 fprintf (file, "(%%r26),%%r26\n");
6593 fprintf (file, "\tb %s\n\tldo ", target_name);
6594 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6595 fprintf (file, "(%%r26),%%r26\n");
6600 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6602 fprintf (file, "\taddil L%%");
6603 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6604 fprintf (file, ",%%r26\n\tldo R%%");
6605 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6606 fprintf (file, "(%%r1),%%r26\n");
6607 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6608 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6609 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6610 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6611 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6612 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6613 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6614 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6615 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
6619 fprintf (file, "\taddil L%%");
6620 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6621 fprintf (file, ",%%r26\n\tb %s\n\tldo R%%", target_name);
6622 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6623 fprintf (file, "(%%r1),%%r26\n");
6627 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
6628 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6631 fprintf (file, "\t.align 4\n");
6632 ASM_OUTPUT_INTERNAL_LABEL (file, "LTHN", current_thunk_number);
6633 fprintf (file, "\t.word P%%%s\n", target_name);
6634 function_section (thunk_fndecl);
6636 current_thunk_number++;
6639 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6640 use in fmpyadd instructions. */
6642 fmpyaddoperands (operands)
6645 enum machine_mode mode = GET_MODE (operands[0]);
6647 /* Must be a floating point mode. */
6648 if (mode != SFmode && mode != DFmode)
6651 /* All modes must be the same. */
6652 if (! (mode == GET_MODE (operands[1])
6653 && mode == GET_MODE (operands[2])
6654 && mode == GET_MODE (operands[3])
6655 && mode == GET_MODE (operands[4])
6656 && mode == GET_MODE (operands[5])))
6659 /* All operands must be registers. */
6660 if (! (GET_CODE (operands[1]) == REG
6661 && GET_CODE (operands[2]) == REG
6662 && GET_CODE (operands[3]) == REG
6663 && GET_CODE (operands[4]) == REG
6664 && GET_CODE (operands[5]) == REG))
6667 /* Only 2 real operands to the addition. One of the input operands must
6668 be the same as the output operand. */
6669 if (! rtx_equal_p (operands[3], operands[4])
6670 && ! rtx_equal_p (operands[3], operands[5]))
6673 /* Inout operand of add can not conflict with any operands from multiply. */
6674 if (rtx_equal_p (operands[3], operands[0])
6675 || rtx_equal_p (operands[3], operands[1])
6676 || rtx_equal_p (operands[3], operands[2]))
6679 /* multiply can not feed into addition operands. */
6680 if (rtx_equal_p (operands[4], operands[0])
6681 || rtx_equal_p (operands[5], operands[0]))
6684 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6686 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6687 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6688 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6689 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6690 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6691 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6694 /* Passed. Operands are suitable for fmpyadd. */
6698 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6699 use in fmpysub instructions. */
6701 fmpysuboperands (operands)
6704 enum machine_mode mode = GET_MODE (operands[0]);
6706 /* Must be a floating point mode. */
6707 if (mode != SFmode && mode != DFmode)
6710 /* All modes must be the same. */
6711 if (! (mode == GET_MODE (operands[1])
6712 && mode == GET_MODE (operands[2])
6713 && mode == GET_MODE (operands[3])
6714 && mode == GET_MODE (operands[4])
6715 && mode == GET_MODE (operands[5])))
6718 /* All operands must be registers. */
6719 if (! (GET_CODE (operands[1]) == REG
6720 && GET_CODE (operands[2]) == REG
6721 && GET_CODE (operands[3]) == REG
6722 && GET_CODE (operands[4]) == REG
6723 && GET_CODE (operands[5]) == REG))
6726 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6727 operation, so operands[4] must be the same as operand[3]. */
6728 if (! rtx_equal_p (operands[3], operands[4]))
6731 /* multiply can not feed into subtraction. */
6732 if (rtx_equal_p (operands[5], operands[0]))
6735 /* Inout operand of sub can not conflict with any operands from multiply. */
6736 if (rtx_equal_p (operands[3], operands[0])
6737 || rtx_equal_p (operands[3], operands[1])
6738 || rtx_equal_p (operands[3], operands[2]))
6741 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6743 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6744 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6745 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6746 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6747 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6748 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6751 /* Passed. Operands are suitable for fmpysub. */
6756 plus_xor_ior_operator (op, mode)
6758 enum machine_mode mode ATTRIBUTE_UNUSED;
6760 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6761 || GET_CODE (op) == IOR);
6764 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6765 constants for shadd instructions. */
6767 shadd_constant_p (val)
6770 if (val == 2 || val == 4 || val == 8)
6776 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6777 the valid constant for shadd instructions. */
6779 shadd_operand (op, mode)
6781 enum machine_mode mode ATTRIBUTE_UNUSED;
6783 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6786 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6789 basereg_operand (op, mode)
6791 enum machine_mode mode;
6793 /* cse will create some unscaled indexed addresses, however; it
6794 generally isn't a win on the PA, so avoid creating unscaled
6795 indexed addresses until after cse is finished. */
6796 if (!cse_not_expected)
6799 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6800 we don't have to worry about the braindamaged implicit space
6801 register selection from the basereg. */
6802 if (TARGET_NO_SPACE_REGS)
6803 return (GET_CODE (op) == REG);
6805 /* While it's always safe to index off the frame pointer, it's not
6806 always profitable, particularly when the frame pointer is being
6808 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6811 return (GET_CODE (op) == REG
6813 && register_operand (op, mode));
6816 /* Return 1 if this operand is anything other than a hard register. */
6819 non_hard_reg_operand (op, mode)
6821 enum machine_mode mode ATTRIBUTE_UNUSED;
6823 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6826 /* Return 1 if INSN branches forward. Should be using insn_addresses
6827 to avoid walking through all the insns... */
6829 forward_branch_p (insn)
6832 rtx label = JUMP_LABEL (insn);
6839 insn = NEXT_INSN (insn);
6842 return (insn == label);
6845 /* Return 1 if OP is an equality comparison, else return 0. */
6847 eq_neq_comparison_operator (op, mode)
6849 enum machine_mode mode ATTRIBUTE_UNUSED;
6851 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6854 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6856 movb_comparison_operator (op, mode)
6858 enum machine_mode mode ATTRIBUTE_UNUSED;
6860 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6861 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6864 /* Return 1 if INSN is in the delay slot of a call instruction. */
6866 jump_in_call_delay (insn)
6870 if (GET_CODE (insn) != JUMP_INSN)
6873 if (PREV_INSN (insn)
6874 && PREV_INSN (PREV_INSN (insn))
6875 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6877 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6879 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6880 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6887 /* Output an unconditional move and branch insn. */
6890 output_parallel_movb (operands, length)
6894 /* These are the cases in which we win. */
6896 return "mov%I1b,tr %1,%0,%2";
6898 /* None of these cases wins, but they don't lose either. */
6899 if (dbr_sequence_length () == 0)
6901 /* Nothing in the delay slot, fake it by putting the combined
6902 insn (the copy or add) in the delay slot of a bl. */
6903 if (GET_CODE (operands[1]) == CONST_INT)
6904 return "b %2\n\tldi %1,%0";
6906 return "b %2\n\tcopy %1,%0";
6910 /* Something in the delay slot, but we've got a long branch. */
6911 if (GET_CODE (operands[1]) == CONST_INT)
6912 return "ldi %1,%0\n\tb %2";
6914 return "copy %1,%0\n\tb %2";
6918 /* Output an unconditional add and branch insn. */
6921 output_parallel_addb (operands, length)
6925 /* To make life easy we want operand0 to be the shared input/output
6926 operand and operand1 to be the readonly operand. */
6927 if (operands[0] == operands[1])
6928 operands[1] = operands[2];
6930 /* These are the cases in which we win. */
6932 return "add%I1b,tr %1,%0,%3";
6934 /* None of these cases win, but they don't lose either. */
6935 if (dbr_sequence_length () == 0)
6937 /* Nothing in the delay slot, fake it by putting the combined
6938 insn (the copy or add) in the delay slot of a bl. */
6939 return "b %3\n\tadd%I1 %1,%0,%0";
6943 /* Something in the delay slot, but we've got a long branch. */
6944 return "add%I1 %1,%0,%0\n\tb %3";
6948 /* Return nonzero if INSN (a jump insn) immediately follows a call
6949 to a named function. This is used to avoid filling the delay slot
6950 of the jump since it can usually be eliminated by modifying RP in
6951 the delay slot of the call. */
6954 following_call (insn)
6957 if (! TARGET_JUMP_IN_DELAY)
6960 /* Find the previous real insn, skipping NOTEs. */
6961 insn = PREV_INSN (insn);
6962 while (insn && GET_CODE (insn) == NOTE)
6963 insn = PREV_INSN (insn);
6965 /* Check for CALL_INSNs and millicode calls. */
6967 && ((GET_CODE (insn) == CALL_INSN
6968 && get_attr_type (insn) != TYPE_DYNCALL)
6969 || (GET_CODE (insn) == INSN
6970 && GET_CODE (PATTERN (insn)) != SEQUENCE
6971 && GET_CODE (PATTERN (insn)) != USE
6972 && GET_CODE (PATTERN (insn)) != CLOBBER
6973 && get_attr_type (insn) == TYPE_MILLI)))
6979 /* We use this hook to perform a PA specific optimization which is difficult
6980 to do in earlier passes.
6982 We want the delay slots of branches within jump tables to be filled.
6983 None of the compiler passes at the moment even has the notion that a
6984 PA jump table doesn't contain addresses, but instead contains actual
6987 Because we actually jump into the table, the addresses of each entry
6988 must stay constant in relation to the beginning of the table (which
6989 itself must stay constant relative to the instruction to jump into
6990 it). I don't believe we can guarantee earlier passes of the compiler
6991 will adhere to those rules.
6993 So, late in the compilation process we find all the jump tables, and
6994 expand them into real code -- eg each entry in the jump table vector
6995 will get an appropriate label followed by a jump to the final target.
6997 Reorg and the final jump pass can then optimize these branches and
6998 fill their delay slots. We end up with smaller, more efficient code.
7000 The jump instructions within the table are special; we must be able
7001 to identify them during assembly output (if the jumps don't get filled
7002 we need to emit a nop rather than nullifying the delay slot)). We
7003 identify jumps in switch tables by marking the SET with DImode.
7005 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
7006 insns. This serves two purposes, first it prevents jump.c from
7007 noticing that the last N entries in the table jump to the instruction
7008 immediately after the table and deleting the jumps. Second, those
7009 insns mark where we should emit .begin_brtab and .end_brtab directives
7010 when using GAS (allows for better link time optimizations). */
7018 remove_useless_addtr_insns (insns, 1);
7020 if (pa_cpu < PROCESSOR_8000)
7021 pa_combine_instructions (get_insns ());
7024 /* This is fairly cheap, so always run it if optimizing. */
7025 if (optimize > 0 && !TARGET_BIG_SWITCH)
7027 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
7028 insns = get_insns ();
7029 for (insn = insns; insn; insn = NEXT_INSN (insn))
7031 rtx pattern, tmp, location;
7032 unsigned int length, i;
7034 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
7035 if (GET_CODE (insn) != JUMP_INSN
7036 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7037 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7040 /* Emit marker for the beginning of the branch table. */
7041 emit_insn_before (gen_begin_brtab (), insn);
7043 pattern = PATTERN (insn);
7044 location = PREV_INSN (insn);
7045 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
7047 for (i = 0; i < length; i++)
7049 /* Emit a label before each jump to keep jump.c from
7050 removing this code. */
7051 tmp = gen_label_rtx ();
7052 LABEL_NUSES (tmp) = 1;
7053 emit_label_after (tmp, location);
7054 location = NEXT_INSN (location);
7056 if (GET_CODE (pattern) == ADDR_VEC)
7058 /* Emit the jump itself. */
7059 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7060 tmp = emit_jump_insn_after (tmp, location);
7061 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7062 /* It is easy to rely on the branch table markers
7063 during assembly output to trigger the correct code
7064 for a switch table jump with an unfilled delay slot,
7066 However, that requires state and assumes that we look
7069 We can't make such assumptions when computing the length
7070 of instructions. Ugh. We could walk the insn chain to
7071 determine if this instruction is in a branch table, but
7072 that can get rather expensive, particularly during the
7073 branch shortening phase of the compiler.
7075 So instead we mark this jump as being special. This is
7076 far from ideal and knows that no code after this will
7077 muck around with the mode of the JUMP_INSN itself. */
7078 PUT_MODE (tmp, SImode);
7079 LABEL_NUSES (JUMP_LABEL (tmp))++;
7080 location = NEXT_INSN (location);
7084 /* Emit the jump itself. */
7085 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7086 tmp = emit_jump_insn_after (tmp, location);
7087 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7088 /* It is easy to rely on the branch table markers
7089 during assembly output to trigger the correct code
7090 for a switch table jump with an unfilled delay slot,
7092 However, that requires state and assumes that we look
7095 We can't make such assumptions when computing the length
7096 of instructions. Ugh. We could walk the insn chain to
7097 determine if this instruction is in a branch table, but
7098 that can get rather expensive, particularly during the
7099 branch shortening phase of the compiler.
7101 So instead we mark this jump as being special. This is
7102 far from ideal and knows that no code after this will
7103 muck around with the mode of the JUMP_INSN itself. */
7104 PUT_MODE (tmp, SImode);
7105 LABEL_NUSES (JUMP_LABEL (tmp))++;
7106 location = NEXT_INSN (location);
7109 /* Emit a BARRIER after the jump. */
7110 emit_barrier_after (location);
7111 location = NEXT_INSN (location);
7114 /* Emit marker for the end of the branch table. */
7115 emit_insn_before (gen_end_brtab (), location);
7116 location = NEXT_INSN (location);
7117 emit_barrier_after (location);
7119 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7125 /* Sill need an end_brtab insn. */
7126 insns = get_insns ();
7127 for (insn = insns; insn; insn = NEXT_INSN (insn))
7129 /* Find an ADDR_VEC insn. */
7130 if (GET_CODE (insn) != JUMP_INSN
7131 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7132 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7135 /* Now generate markers for the beginning and end of the
7137 emit_insn_before (gen_begin_brtab (), insn);
7138 emit_insn_after (gen_end_brtab (), insn);
7143 /* The PA has a number of odd instructions which can perform multiple
7144 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7145 it may be profitable to combine two instructions into one instruction
7146 with two outputs. It's not profitable PA2.0 machines because the
7147 two outputs would take two slots in the reorder buffers.
7149 This routine finds instructions which can be combined and combines
7150 them. We only support some of the potential combinations, and we
7151 only try common ways to find suitable instructions.
7153 * addb can add two registers or a register and a small integer
7154 and jump to a nearby (+-8k) location. Normally the jump to the
7155 nearby location is conditional on the result of the add, but by
7156 using the "true" condition we can make the jump unconditional.
7157 Thus addb can perform two independent operations in one insn.
7159 * movb is similar to addb in that it can perform a reg->reg
7160 or small immediate->reg copy and jump to a nearby (+-8k location).
7162 * fmpyadd and fmpysub can perform a FP multiply and either an
7163 FP add or FP sub if the operands of the multiply and add/sub are
7164 independent (there are other minor restrictions). Note both
7165 the fmpy and fadd/fsub can in theory move to better spots according
7166 to data dependencies, but for now we require the fmpy stay at a
7169 * Many of the memory operations can perform pre & post updates
7170 of index registers. GCC's pre/post increment/decrement addressing
7171 is far too simple to take advantage of all the possibilities. This
7172 pass may not be suitable since those insns may not be independent.
7174 * comclr can compare two ints or an int and a register, nullify
7175 the following instruction and zero some other register. This
7176 is more difficult to use as it's harder to find an insn which
7177 will generate a comclr than finding something like an unconditional
7178 branch. (conditional moves & long branches create comclr insns).
7180 * Most arithmetic operations can conditionally skip the next
7181 instruction. They can be viewed as "perform this operation
7182 and conditionally jump to this nearby location" (where nearby
7183 is an insns away). These are difficult to use due to the
7184 branch length restrictions. */
7187 pa_combine_instructions (insns)
7188 rtx insns ATTRIBUTE_UNUSED;
7192 /* This can get expensive since the basic algorithm is on the
7193 order of O(n^2) (or worse). Only do it for -O2 or higher
7194 levels of optimization. */
7198 /* Walk down the list of insns looking for "anchor" insns which
7199 may be combined with "floating" insns. As the name implies,
7200 "anchor" instructions don't move, while "floating" insns may
7202 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7203 new = make_insn_raw (new);
7205 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7207 enum attr_pa_combine_type anchor_attr;
7208 enum attr_pa_combine_type floater_attr;
7210 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7211 Also ignore any special USE insns. */
7212 if ((GET_CODE (anchor) != INSN
7213 && GET_CODE (anchor) != JUMP_INSN
7214 && GET_CODE (anchor) != CALL_INSN)
7215 || GET_CODE (PATTERN (anchor)) == USE
7216 || GET_CODE (PATTERN (anchor)) == CLOBBER
7217 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7218 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7221 anchor_attr = get_attr_pa_combine_type (anchor);
7222 /* See if anchor is an insn suitable for combination. */
7223 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7224 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7225 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7226 && ! forward_branch_p (anchor)))
7230 for (floater = PREV_INSN (anchor);
7232 floater = PREV_INSN (floater))
7234 if (GET_CODE (floater) == NOTE
7235 || (GET_CODE (floater) == INSN
7236 && (GET_CODE (PATTERN (floater)) == USE
7237 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7240 /* Anything except a regular INSN will stop our search. */
7241 if (GET_CODE (floater) != INSN
7242 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7243 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7249 /* See if FLOATER is suitable for combination with the
7251 floater_attr = get_attr_pa_combine_type (floater);
7252 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7253 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7254 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7255 && floater_attr == PA_COMBINE_TYPE_FMPY))
7257 /* If ANCHOR and FLOATER can be combined, then we're
7258 done with this pass. */
7259 if (pa_can_combine_p (new, anchor, floater, 0,
7260 SET_DEST (PATTERN (floater)),
7261 XEXP (SET_SRC (PATTERN (floater)), 0),
7262 XEXP (SET_SRC (PATTERN (floater)), 1)))
7266 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7267 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7269 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7271 if (pa_can_combine_p (new, anchor, floater, 0,
7272 SET_DEST (PATTERN (floater)),
7273 XEXP (SET_SRC (PATTERN (floater)), 0),
7274 XEXP (SET_SRC (PATTERN (floater)), 1)))
7279 if (pa_can_combine_p (new, anchor, floater, 0,
7280 SET_DEST (PATTERN (floater)),
7281 SET_SRC (PATTERN (floater)),
7282 SET_SRC (PATTERN (floater))))
7288 /* If we didn't find anything on the backwards scan try forwards. */
7290 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7291 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7293 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7295 if (GET_CODE (floater) == NOTE
7296 || (GET_CODE (floater) == INSN
7297 && (GET_CODE (PATTERN (floater)) == USE
7298 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7302 /* Anything except a regular INSN will stop our search. */
7303 if (GET_CODE (floater) != INSN
7304 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7305 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7311 /* See if FLOATER is suitable for combination with the
7313 floater_attr = get_attr_pa_combine_type (floater);
7314 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7315 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7316 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7317 && floater_attr == PA_COMBINE_TYPE_FMPY))
7319 /* If ANCHOR and FLOATER can be combined, then we're
7320 done with this pass. */
7321 if (pa_can_combine_p (new, anchor, floater, 1,
7322 SET_DEST (PATTERN (floater)),
7323 XEXP (SET_SRC (PATTERN (floater)),
7325 XEXP (SET_SRC (PATTERN (floater)),
7332 /* FLOATER will be nonzero if we found a suitable floating
7333 insn for combination with ANCHOR. */
7335 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7336 || anchor_attr == PA_COMBINE_TYPE_FMPY))
7338 /* Emit the new instruction and delete the old anchor. */
7339 emit_insn_before (gen_rtx_PARALLEL
7341 gen_rtvec (2, PATTERN (anchor),
7342 PATTERN (floater))),
7345 PUT_CODE (anchor, NOTE);
7346 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7347 NOTE_SOURCE_FILE (anchor) = 0;
7349 /* Emit a special USE insn for FLOATER, then delete
7350 the floating insn. */
7351 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7352 delete_insn (floater);
7357 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
7360 /* Emit the new_jump instruction and delete the old anchor. */
7362 = emit_jump_insn_before (gen_rtx_PARALLEL
7364 gen_rtvec (2, PATTERN (anchor),
7365 PATTERN (floater))),
7368 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
7369 PUT_CODE (anchor, NOTE);
7370 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7371 NOTE_SOURCE_FILE (anchor) = 0;
7373 /* Emit a special USE insn for FLOATER, then delete
7374 the floating insn. */
7375 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7376 delete_insn (floater);
7384 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7385 rtx new, anchor, floater;
7387 rtx dest, src1, src2;
7389 int insn_code_number;
7392 /* Create a PARALLEL with the patterns of ANCHOR and
7393 FLOATER, try to recognize it, then test constraints
7394 for the resulting pattern.
7396 If the pattern doesn't match or the constraints
7397 aren't met keep searching for a suitable floater
7399 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7400 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7401 INSN_CODE (new) = -1;
7402 insn_code_number = recog_memoized (new);
7403 if (insn_code_number < 0
7404 || (extract_insn (new), ! constrain_operands (1)))
7418 /* There's up to three operands to consider. One
7419 output and two inputs.
7421 The output must not be used between FLOATER & ANCHOR
7422 exclusive. The inputs must not be set between
7423 FLOATER and ANCHOR exclusive. */
7425 if (reg_used_between_p (dest, start, end))
7428 if (reg_set_between_p (src1, start, end))
7431 if (reg_set_between_p (src2, start, end))
7434 /* If we get here, then everything is good. */
7438 /* Return nonzero if references for INSN are delayed.
7440 Millicode insns are actually function calls with some special
7441 constraints on arguments and register usage.
7443 Millicode calls always expect their arguments in the integer argument
7444 registers, and always return their result in %r29 (ret1). They
7445 are expected to clobber their arguments, %r1, %r29, and the return
7446 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7448 This function tells reorg that the references to arguments and
7449 millicode calls do not appear to happen until after the millicode call.
7450 This allows reorg to put insns which set the argument registers into the
7451 delay slot of the millicode call -- thus they act more like traditional
7454 Note we can not consider side effects of the insn to be delayed because
7455 the branch and link insn will clobber the return pointer. If we happened
7456 to use the return pointer in the delay slot of the call, then we lose.
7458 get_attr_type will try to recognize the given insn, so make sure to
7459 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7462 insn_refs_are_delayed (insn)
7465 return ((GET_CODE (insn) == INSN
7466 && GET_CODE (PATTERN (insn)) != SEQUENCE
7467 && GET_CODE (PATTERN (insn)) != USE
7468 && GET_CODE (PATTERN (insn)) != CLOBBER
7469 && get_attr_type (insn) == TYPE_MILLI));
7472 /* Return the location of a parameter that is passed in a register or NULL
7473 if the parameter has any component that is passed in memory.
7475 This is new code and will be pushed to into the net sources after
7478 ??? We might want to restructure this so that it looks more like other
7481 function_arg (cum, mode, type, named, incoming)
7482 CUMULATIVE_ARGS *cum;
7483 enum machine_mode mode;
7485 int named ATTRIBUTE_UNUSED;
7488 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7495 if (mode == VOIDmode)
7498 arg_size = FUNCTION_ARG_SIZE (mode, type);
7500 /* If this arg would be passed partially or totally on the stack, then
7501 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7502 handle arguments which are split between regs and stack slots if
7503 the ABI mandates split arguments. */
7506 /* The 32-bit ABI does not split arguments. */
7507 if (cum->words + arg_size > max_arg_words)
7513 alignment = cum->words & 1;
7514 if (cum->words + alignment >= max_arg_words)
7518 /* The 32bit ABIs and the 64bit ABIs are rather different,
7519 particularly in their handling of FP registers. We might
7520 be able to cleverly share code between them, but I'm not
7521 going to bother in the hope that splitting them up results
7522 in code that is more easily understood. */
7526 /* Advance the base registers to their current locations.
7528 Remember, gprs grow towards smaller register numbers while
7529 fprs grow to higher register numbers. Also remember that
7530 although FP regs are 32-bit addressable, we pretend that
7531 the registers are 64-bits wide. */
7532 gpr_reg_base = 26 - cum->words;
7533 fpr_reg_base = 32 + cum->words;
7535 /* Arguments wider than one word and small aggregates need special
7539 || (type && AGGREGATE_TYPE_P (type)))
7541 /* Double-extended precision (80-bit), quad-precision (128-bit)
7542 and aggregates including complex numbers are aligned on
7543 128-bit boundaries. The first eight 64-bit argument slots
7544 are associated one-to-one, with general registers r26
7545 through r19, and also with floating-point registers fr4
7546 through fr11. Arguments larger than one word are always
7547 passed in general registers.
7549 Using a PARALLEL with a word mode register results in left
7550 justified data on a big-endian target. */
7553 int i, offset = 0, ub = arg_size;
7555 /* Align the base register. */
7556 gpr_reg_base -= alignment;
7558 ub = MIN (ub, max_arg_words - cum->words - alignment);
7559 for (i = 0; i < ub; i++)
7561 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7562 gen_rtx_REG (DImode, gpr_reg_base),
7568 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7573 /* If the argument is larger than a word, then we know precisely
7574 which registers we must use. */
7588 /* Structures 5 to 8 bytes in size are passed in the general
7589 registers in the same manner as other non floating-point
7590 objects. The data is right-justified and zero-extended
7593 This is magic. Normally, using a PARALLEL results in left
7594 justified data on a big-endian target. However, using a
7595 single double-word register provides the required right
7596 justication for 5 to 8 byte structures. This has nothing
7597 to do with the direction of padding specified for the argument.
7598 It has to do with how the data is widened and shifted into
7599 and from the register.
7601 Aside from adding load_multiple and store_multiple patterns,
7602 this is the only way that I have found to obtain right
7603 justification of BLKmode data when it has a size greater
7604 than one word. Splitting the operation into two SImode loads
7605 or returning a DImode REG results in left justified data. */
7606 if (mode == BLKmode)
7610 loc[0] = gen_rtx_EXPR_LIST (VOIDmode,
7611 gen_rtx_REG (DImode, gpr_reg_base),
7613 return gen_rtx_PARALLEL (mode, gen_rtvec_v (1, loc));
7618 /* We have a single word (32 bits). A simple computation
7619 will get us the register #s we need. */
7620 gpr_reg_base = 26 - cum->words;
7621 fpr_reg_base = 32 + 2 * cum->words;
7625 /* Determine if the argument needs to be passed in both general and
7626 floating point registers. */
7627 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7628 /* If we are doing soft-float with portable runtime, then there
7629 is no need to worry about FP regs. */
7630 && ! TARGET_SOFT_FLOAT
7631 /* The parameter must be some kind of float, else we can just
7632 pass it in integer registers. */
7633 && FLOAT_MODE_P (mode)
7634 /* The target function must not have a prototype. */
7635 && cum->nargs_prototype <= 0
7636 /* libcalls do not need to pass items in both FP and general
7638 && type != NULL_TREE
7639 /* All this hair applies to outgoing args only. */
7641 /* Also pass outgoing floating arguments in both registers in indirect
7642 calls with the 32 bit ABI and the HP assembler since there is no
7643 way to the specify argument locations in static functions. */
7648 && FLOAT_MODE_P (mode)))
7654 gen_rtx_EXPR_LIST (VOIDmode,
7655 gen_rtx_REG (mode, fpr_reg_base),
7657 gen_rtx_EXPR_LIST (VOIDmode,
7658 gen_rtx_REG (mode, gpr_reg_base),
7663 /* See if we should pass this parameter in a general register. */
7664 if (TARGET_SOFT_FLOAT
7665 /* Indirect calls in the normal 32bit ABI require all arguments
7666 to be passed in general registers. */
7667 || (!TARGET_PORTABLE_RUNTIME
7671 /* If the parameter is not a floating point parameter, then
7672 it belongs in GPRs. */
7673 || !FLOAT_MODE_P (mode))
7674 retval = gen_rtx_REG (mode, gpr_reg_base);
7676 retval = gen_rtx_REG (mode, fpr_reg_base);
7682 /* If this arg would be passed totally in registers or totally on the stack,
7683 then this routine should return zero. It is currently called only for
7684 the 64-bit target. */
7686 function_arg_partial_nregs (cum, mode, type, named)
7687 CUMULATIVE_ARGS *cum;
7688 enum machine_mode mode;
7690 int named ATTRIBUTE_UNUSED;
7692 unsigned int max_arg_words = 8;
7693 unsigned int offset = 0;
7695 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7698 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7699 /* Arg fits fully into registers. */
7701 else if (cum->words + offset >= max_arg_words)
7702 /* Arg fully on the stack. */
7706 return max_arg_words - cum->words - offset;
7710 /* Return 1 if this is a comparison operator. This allows the use of
7711 MATCH_OPERATOR to recognize all the branch insns. */
7714 cmpib_comparison_operator (op, mode)
7716 enum machine_mode mode;
7718 return ((mode == VOIDmode || GET_MODE (op) == mode)
7719 && (GET_CODE (op) == EQ
7720 || GET_CODE (op) == NE
7721 || GET_CODE (op) == GT
7722 || GET_CODE (op) == GTU
7723 || GET_CODE (op) == GE
7724 || GET_CODE (op) == LT
7725 || GET_CODE (op) == LE
7726 || GET_CODE (op) == LEU));
7729 /* On hpux10, the linker will give an error if we have a reference
7730 in the read-only data section to a symbol defined in a shared
7731 library. Therefore, expressions that might require a reloc can
7732 not be placed in the read-only data section. */
7735 pa_select_section (exp, reloc, align)
7738 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
7740 if (TREE_CODE (exp) == VAR_DECL
7741 && TREE_READONLY (exp)
7742 && !TREE_THIS_VOLATILE (exp)
7743 && DECL_INITIAL (exp)
7744 && (DECL_INITIAL (exp) == error_mark_node
7745 || TREE_CONSTANT (DECL_INITIAL (exp)))
7747 readonly_data_section ();
7748 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
7749 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
7751 readonly_data_section ();
7757 pa_globalize_label (stream, name)
7761 /* We only handle DATA objects here, functions are globalized in
7762 ASM_DECLARE_FUNCTION_NAME. */
7763 if (! FUNCTION_NAME_P (name))
7765 fputs ("\t.EXPORT ", stream);
7766 assemble_name (stream, name);
7767 fputs (",DATA\n", stream);