1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static int hppa_address_cost (rtx);
88 static bool hppa_rtx_costs (rtx, int, int, int *);
89 static inline rtx force_mode (enum machine_mode, rtx);
90 static void pa_reorg (void);
91 static void pa_combine_instructions (void);
92 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
93 static int forward_branch_p (rtx);
94 static int shadd_constant_p (int);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
127 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static struct deferred_plabel *get_plabel (const char *)
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 #ifdef HPUX_LONG_DOUBLE_LIBRARY
141 static void pa_hpux_init_libfuncs (void);
143 static rtx pa_struct_value_rtx (tree, int);
144 static bool pa_pass_by_reference (CUMULATIVE_ARGS *ca, enum machine_mode,
148 /* Save the operands last given to a compare for use when we
149 generate a scc or bcc insn. */
150 rtx hppa_compare_op0, hppa_compare_op1;
151 enum cmp_type hppa_branch_type;
153 /* Which architecture we are generating code for. */
154 enum architecture_type pa_arch;
156 /* String to hold which architecture we are generating code for. */
157 const char *pa_arch_string;
159 /* String used with the -mfixed-range= option. */
160 const char *pa_fixed_range_string;
162 /* Which cpu we are scheduling for. */
163 enum processor_type pa_cpu;
165 /* String to hold which cpu we are scheduling for. */
166 const char *pa_cpu_string;
168 /* Counts for the number of callee-saved general and floating point
169 registers which were saved by the current function's prologue. */
170 static int gr_saved, fr_saved;
172 static rtx find_addr_reg (rtx);
174 /* Keep track of the number of bytes we have output in the CODE subspace
175 during this compilation so we'll know when to emit inline long-calls. */
176 unsigned long total_code_bytes;
178 /* The last address of the previous function plus the number of bytes in
179 associated thunks that have been output. This is used to determine if
180 a thunk can use an IA-relative branch to reach its target function. */
181 static int last_address;
183 /* Variables to handle plabels that we discover are necessary at assembly
184 output time. They are output after the current function. */
185 struct deferred_plabel GTY(())
190 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
192 static size_t n_deferred_plabels = 0;
195 /* Initialize the GCC target structure. */
197 #undef TARGET_ASM_ALIGNED_HI_OP
198 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
199 #undef TARGET_ASM_ALIGNED_SI_OP
200 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
201 #undef TARGET_ASM_ALIGNED_DI_OP
202 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
203 #undef TARGET_ASM_UNALIGNED_HI_OP
204 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
205 #undef TARGET_ASM_UNALIGNED_SI_OP
206 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
207 #undef TARGET_ASM_UNALIGNED_DI_OP
208 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
209 #undef TARGET_ASM_INTEGER
210 #define TARGET_ASM_INTEGER pa_assemble_integer
212 #undef TARGET_ASM_FUNCTION_PROLOGUE
213 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
214 #undef TARGET_ASM_FUNCTION_EPILOGUE
215 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
217 #undef TARGET_SCHED_ADJUST_COST
218 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
219 #undef TARGET_SCHED_ADJUST_PRIORITY
220 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
221 #undef TARGET_SCHED_ISSUE_RATE
222 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
224 #undef TARGET_ENCODE_SECTION_INFO
225 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
226 #undef TARGET_STRIP_NAME_ENCODING
227 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
229 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
230 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
232 #undef TARGET_ASM_OUTPUT_MI_THUNK
233 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
234 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
235 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
237 #undef TARGET_ASM_FILE_END
238 #define TARGET_ASM_FILE_END output_deferred_plabels
240 #if !defined(USE_COLLECT2)
241 #undef TARGET_ASM_CONSTRUCTOR
242 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
243 #undef TARGET_ASM_DESTRUCTOR
244 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
247 #undef TARGET_INIT_BUILTINS
248 #define TARGET_INIT_BUILTINS pa_init_builtins
250 #undef TARGET_RTX_COSTS
251 #define TARGET_RTX_COSTS hppa_rtx_costs
252 #undef TARGET_ADDRESS_COST
253 #define TARGET_ADDRESS_COST hppa_address_cost
255 #undef TARGET_MACHINE_DEPENDENT_REORG
256 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
258 #ifdef HPUX_LONG_DOUBLE_LIBRARY
259 #undef TARGET_INIT_LIBFUNCS
260 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
263 #undef TARGET_PROMOTE_FUNCTION_RETURN
264 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
265 #undef TARGET_PROMOTE_PROTOTYPES
266 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
268 #undef TARGET_STRUCT_VALUE_RTX
269 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
270 #undef TARGET_RETURN_IN_MEMORY
271 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
272 #undef TARGET_MUST_PASS_IN_STACK
273 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
274 #undef TARGET_PASS_BY_REFERENCE
275 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
277 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
278 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
279 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
280 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
282 struct gcc_target targetm = TARGET_INITIALIZER;
284 /* Parse the -mfixed-range= option string. */
287 fix_range (const char *const_str)
290 char *str, *dash, *comma;
292 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
293 REG2 are either register names or register numbers. The effect
294 of this option is to mark the registers in the range from REG1 to
295 REG2 as ``fixed'' so they won't be used by the compiler. This is
296 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
298 i = strlen (const_str);
299 str = (char *) alloca (i + 1);
300 memcpy (str, const_str, i + 1);
304 dash = strchr (str, '-');
307 warning ("value of -mfixed-range must have form REG1-REG2");
312 comma = strchr (dash + 1, ',');
316 first = decode_reg_name (str);
319 warning ("unknown register name: %s", str);
323 last = decode_reg_name (dash + 1);
326 warning ("unknown register name: %s", dash + 1);
334 warning ("%s-%s is an empty range", str, dash + 1);
338 for (i = first; i <= last; ++i)
339 fixed_regs[i] = call_used_regs[i] = 1;
348 /* Check if all floating point registers have been fixed. */
349 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
354 target_flags |= MASK_DISABLE_FPREGS;
358 override_options (void)
360 if (pa_cpu_string == NULL)
361 pa_cpu_string = TARGET_SCHED_DEFAULT;
363 if (! strcmp (pa_cpu_string, "8000"))
365 pa_cpu_string = "8000";
366 pa_cpu = PROCESSOR_8000;
368 else if (! strcmp (pa_cpu_string, "7100"))
370 pa_cpu_string = "7100";
371 pa_cpu = PROCESSOR_7100;
373 else if (! strcmp (pa_cpu_string, "700"))
375 pa_cpu_string = "700";
376 pa_cpu = PROCESSOR_700;
378 else if (! strcmp (pa_cpu_string, "7100LC"))
380 pa_cpu_string = "7100LC";
381 pa_cpu = PROCESSOR_7100LC;
383 else if (! strcmp (pa_cpu_string, "7200"))
385 pa_cpu_string = "7200";
386 pa_cpu = PROCESSOR_7200;
388 else if (! strcmp (pa_cpu_string, "7300"))
390 pa_cpu_string = "7300";
391 pa_cpu = PROCESSOR_7300;
395 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
398 /* Set the instruction architecture. */
399 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
401 pa_arch_string = "1.0";
402 pa_arch = ARCHITECTURE_10;
403 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
405 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
407 pa_arch_string = "1.1";
408 pa_arch = ARCHITECTURE_11;
409 target_flags &= ~MASK_PA_20;
410 target_flags |= MASK_PA_11;
412 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
414 pa_arch_string = "2.0";
415 pa_arch = ARCHITECTURE_20;
416 target_flags |= MASK_PA_11 | MASK_PA_20;
418 else if (pa_arch_string)
420 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
423 if (pa_fixed_range_string)
424 fix_range (pa_fixed_range_string);
426 /* Unconditional branches in the delay slot are not compatible with dwarf2
427 call frame information. There is no benefit in using this optimization
428 on PA8000 and later processors. */
429 if (pa_cpu >= PROCESSOR_8000
430 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
431 || flag_unwind_tables)
432 target_flags &= ~MASK_JUMP_IN_DELAY;
434 if (flag_pic && TARGET_PORTABLE_RUNTIME)
436 warning ("PIC code generation is not supported in the portable runtime model\n");
439 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
441 warning ("PIC code generation is not compatible with fast indirect calls\n");
444 if (! TARGET_GAS && write_symbols != NO_DEBUG)
446 warning ("-g is only supported when using GAS on this processor,");
447 warning ("-g option disabled");
448 write_symbols = NO_DEBUG;
451 /* We only support the "big PIC" model now. And we always generate PIC
452 code when in 64bit mode. */
453 if (flag_pic == 1 || TARGET_64BIT)
456 /* We can't guarantee that .dword is available for 32-bit targets. */
457 if (UNITS_PER_WORD == 4)
458 targetm.asm_out.aligned_op.di = NULL;
460 /* The unaligned ops are only available when using GAS. */
463 targetm.asm_out.unaligned_op.hi = NULL;
464 targetm.asm_out.unaligned_op.si = NULL;
465 targetm.asm_out.unaligned_op.di = NULL;
470 pa_init_builtins (void)
472 #ifdef DONT_HAVE_FPUTC_UNLOCKED
473 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
474 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
478 /* If FROM is a probable pointer register, mark TO as a probable
479 pointer register with the same pointer alignment as FROM. */
482 copy_reg_pointer (rtx to, rtx from)
484 if (REG_POINTER (from))
485 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
488 /* Return nonzero only if OP is a register of mode MODE,
491 reg_or_0_operand (rtx op, enum machine_mode mode)
493 return (op == CONST0_RTX (mode) || register_operand (op, mode));
496 /* Return nonzero if OP is suitable for use in a call to a named
499 For 2.5 try to eliminate either call_operand_address or
500 function_label_operand, they perform very similar functions. */
502 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
504 return (GET_MODE (op) == word_mode
505 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
508 /* Return 1 if X contains a symbolic expression. We know these
509 expressions will have one of a few well defined forms, so
510 we need only check those forms. */
512 symbolic_expression_p (rtx x)
515 /* Strip off any HIGH. */
516 if (GET_CODE (x) == HIGH)
519 return (symbolic_operand (x, VOIDmode));
523 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
525 switch (GET_CODE (op))
532 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
533 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
534 && GET_CODE (XEXP (op, 1)) == CONST_INT);
540 /* Return truth value of statement that OP is a symbolic memory
541 operand of mode MODE. */
544 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
546 if (GET_CODE (op) == SUBREG)
547 op = SUBREG_REG (op);
548 if (GET_CODE (op) != MEM)
551 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
552 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
555 /* Return 1 if the operand is either a register, zero, or a memory operand
556 that is not symbolic. */
559 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
561 if (register_operand (op, mode))
564 if (op == CONST0_RTX (mode))
567 if (GET_CODE (op) == SUBREG)
568 op = SUBREG_REG (op);
570 if (GET_CODE (op) != MEM)
573 /* Until problems with management of the REG_POINTER flag are resolved,
574 we need to delay creating move insns with unscaled indexed addresses
575 until CSE is not expected. */
576 if (!TARGET_NO_SPACE_REGS
578 && GET_CODE (XEXP (op, 0)) == PLUS
579 && REG_P (XEXP (XEXP (op, 0), 0))
580 && REG_P (XEXP (XEXP (op, 0), 1)))
583 return (!symbolic_memory_operand (op, mode)
584 && memory_address_p (mode, XEXP (op, 0)));
587 /* Return 1 if the operand is a register operand or a non-symbolic memory
588 operand after reload. This predicate is used for branch patterns that
589 internally handle register reloading. We need to accept non-symbolic
590 memory operands after reload to ensure that the pattern is still valid
591 if reload didn't find a hard register for the operand. */
594 reg_before_reload_operand (rtx op, enum machine_mode mode)
596 /* Don't accept a SUBREG since it will need a reload. */
597 if (GET_CODE (op) == SUBREG)
600 if (register_operand (op, mode))
604 && memory_operand (op, mode)
605 && !symbolic_memory_operand (op, mode))
611 /* Accept any constant that can be moved in one instruction into a
614 cint_ok_for_move (HOST_WIDE_INT intval)
616 /* OK if ldo, ldil, or zdepi, can be used. */
617 return (CONST_OK_FOR_LETTER_P (intval, 'J')
618 || CONST_OK_FOR_LETTER_P (intval, 'N')
619 || CONST_OK_FOR_LETTER_P (intval, 'K'));
622 /* Return 1 iff OP is an indexed memory operand. */
624 indexed_memory_operand (rtx op, enum machine_mode mode)
626 if (GET_MODE (op) != mode)
629 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
630 if (reload_completed && GET_CODE (op) == SUBREG)
631 op = SUBREG_REG (op);
633 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
638 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
641 /* Accept anything that can be used as a destination operand for a
642 move instruction. We don't accept indexed memory operands since
643 they are supported only for floating point stores. */
645 move_dest_operand (rtx op, enum machine_mode mode)
647 if (register_operand (op, mode))
650 if (GET_MODE (op) != mode)
653 if (GET_CODE (op) == SUBREG)
654 op = SUBREG_REG (op);
656 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
661 return (memory_address_p (mode, op)
662 && !IS_INDEX_ADDR_P (op)
663 && !IS_LO_SUM_DLT_ADDR_P (op));
666 /* Accept anything that can be used as a source operand for a move
669 move_src_operand (rtx op, enum machine_mode mode)
671 if (register_operand (op, mode))
674 if (GET_CODE (op) == CONST_INT)
675 return cint_ok_for_move (INTVAL (op));
677 if (GET_MODE (op) != mode)
680 if (GET_CODE (op) == SUBREG)
681 op = SUBREG_REG (op);
683 if (GET_CODE (op) != MEM)
686 /* Until problems with management of the REG_POINTER flag are resolved,
687 we need to delay creating move insns with unscaled indexed addresses
688 until CSE is not expected. */
689 if (!TARGET_NO_SPACE_REGS
691 && GET_CODE (XEXP (op, 0)) == PLUS
692 && REG_P (XEXP (XEXP (op, 0), 0))
693 && REG_P (XEXP (XEXP (op, 0), 1)))
696 return memory_address_p (mode, XEXP (op, 0));
699 /* Accept anything that can be used as the source operand for a prefetch
702 prefetch_operand (rtx op, enum machine_mode mode)
704 if (GET_CODE (op) != MEM)
707 /* Until problems with management of the REG_POINTER flag are resolved,
708 we need to delay creating prefetch insns with unscaled indexed addresses
709 until CSE is not expected. */
710 if (!TARGET_NO_SPACE_REGS
712 && GET_CODE (XEXP (op, 0)) == PLUS
713 && REG_P (XEXP (XEXP (op, 0), 0))
714 && REG_P (XEXP (XEXP (op, 0), 1)))
717 return memory_address_p (mode, XEXP (op, 0));
720 /* Accept REG and any CONST_INT that can be moved in one instruction into a
723 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
725 if (register_operand (op, mode))
728 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
732 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
737 switch (GET_CODE (op))
743 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
744 && GET_CODE (XEXP (op, 1)) == CONST_INT);
751 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
753 return reg_renumber && FP_REG_P (op);
758 /* Return truth value of whether OP can be used as an operand in a
759 three operand arithmetic insn that accepts registers of mode MODE
760 or 14-bit signed integers. */
762 arith_operand (rtx op, enum machine_mode mode)
764 return (register_operand (op, mode)
765 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
768 /* Return truth value of whether OP can be used as an operand in a
769 three operand arithmetic insn that accepts registers of mode MODE
770 or 11-bit signed integers. */
772 arith11_operand (rtx op, enum machine_mode mode)
774 return (register_operand (op, mode)
775 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
778 /* Return truth value of whether OP can be used as an operand in a
781 adddi3_operand (rtx op, enum machine_mode mode)
783 return (register_operand (op, mode)
784 || (GET_CODE (op) == CONST_INT
785 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
788 /* A constant integer suitable for use in a PRE_MODIFY memory
791 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
793 return (GET_CODE (op) == CONST_INT
794 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
797 /* A constant integer suitable for use in a POST_MODIFY memory
800 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
802 return (GET_CODE (op) == CONST_INT
803 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
807 arith_double_operand (rtx op, enum machine_mode mode)
809 return (register_operand (op, mode)
810 || (GET_CODE (op) == CONST_DOUBLE
811 && GET_MODE (op) == mode
812 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
813 && ((CONST_DOUBLE_HIGH (op) >= 0)
814 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
817 /* Return truth value of whether OP is an integer which fits the
818 range constraining immediate operands in three-address insns, or
819 is an integer register. */
822 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
824 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
825 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
828 /* Return nonzero if OP is an integer register, else return zero. */
830 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
832 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
835 /* Return truth value of whether OP is an integer which fits the
836 range constraining immediate operands in three-address insns. */
839 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
841 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
845 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
847 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
851 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
853 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
857 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
859 #if HOST_BITS_PER_WIDE_INT > 32
860 /* All allowed constants will fit a CONST_INT. */
861 return (GET_CODE (op) == CONST_INT
862 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
864 return (GET_CODE (op) == CONST_INT
865 || (GET_CODE (op) == CONST_DOUBLE
866 && CONST_DOUBLE_HIGH (op) == 0));
871 arith5_operand (rtx op, enum machine_mode mode)
873 return register_operand (op, mode) || int5_operand (op, mode);
876 /* True iff zdepi can be used to generate this CONST_INT.
877 zdepi first sign extends a 5 bit signed number to a given field
878 length, then places this field anywhere in a zero. */
880 zdepi_cint_p (unsigned HOST_WIDE_INT x)
882 unsigned HOST_WIDE_INT lsb_mask, t;
884 /* This might not be obvious, but it's at least fast.
885 This function is critical; we don't have the time loops would take. */
887 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
888 /* Return true iff t is a power of two. */
889 return ((t & (t - 1)) == 0);
892 /* True iff depi or extru can be used to compute (reg & mask).
893 Accept bit pattern like these:
898 and_mask_p (unsigned HOST_WIDE_INT mask)
901 mask += mask & -mask;
902 return (mask & (mask - 1)) == 0;
905 /* True iff depi or extru can be used to compute (reg & OP). */
907 and_operand (rtx op, enum machine_mode mode)
909 return (register_operand (op, mode)
910 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
913 /* True iff depi can be used to compute (reg | MASK). */
915 ior_mask_p (unsigned HOST_WIDE_INT mask)
917 mask += mask & -mask;
918 return (mask & (mask - 1)) == 0;
921 /* True iff depi can be used to compute (reg | OP). */
923 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
925 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
929 lhs_lshift_operand (rtx op, enum machine_mode mode)
931 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
934 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
935 Such values can be the left hand side x in (x << r), using the zvdepi
938 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
940 unsigned HOST_WIDE_INT x;
941 if (GET_CODE (op) != CONST_INT)
943 x = INTVAL (op) >> 4;
944 return (x & (x + 1)) == 0;
948 arith32_operand (rtx op, enum machine_mode mode)
950 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
954 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
956 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
959 /* Legitimize PIC addresses. If the address is already
960 position-independent, we return ORIG. Newly generated
961 position-independent addresses go to REG. If we need more
962 than one register, we lose. */
965 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
969 /* Labels need special handling. */
970 if (pic_label_operand (orig, mode))
972 /* We do not want to go through the movXX expanders here since that
973 would create recursion.
975 Nor do we really want to call a generator for a named pattern
976 since that requires multiple patterns if we want to support
979 So instead we just emit the raw set, which avoids the movXX
980 expanders completely. */
981 mark_reg_pointer (reg, BITS_PER_UNIT);
982 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
983 current_function_uses_pic_offset_table = 1;
986 if (GET_CODE (orig) == SYMBOL_REF)
993 /* Before reload, allocate a temporary register for the intermediate
994 result. This allows the sequence to be deleted when the final
995 result is unused and the insns are trivially dead. */
996 tmp_reg = ((reload_in_progress || reload_completed)
997 ? reg : gen_reg_rtx (Pmode));
999 emit_move_insn (tmp_reg,
1000 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
1001 gen_rtx_HIGH (word_mode, orig)));
1003 = gen_rtx_MEM (Pmode,
1004 gen_rtx_LO_SUM (Pmode, tmp_reg,
1005 gen_rtx_UNSPEC (Pmode,
1006 gen_rtvec (1, orig),
1007 UNSPEC_DLTIND14R)));
1009 current_function_uses_pic_offset_table = 1;
1010 MEM_NOTRAP_P (pic_ref) = 1;
1011 RTX_UNCHANGING_P (pic_ref) = 1;
1012 mark_reg_pointer (reg, BITS_PER_UNIT);
1013 insn = emit_move_insn (reg, pic_ref);
1015 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
1016 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
1020 else if (GET_CODE (orig) == CONST)
1024 if (GET_CODE (XEXP (orig, 0)) == PLUS
1025 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1031 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1033 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1034 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1035 base == reg ? 0 : reg);
1040 if (GET_CODE (orig) == CONST_INT)
1042 if (INT_14_BITS (orig))
1043 return plus_constant (base, INTVAL (orig));
1044 orig = force_reg (Pmode, orig);
1046 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1047 /* Likewise, should we set special REG_NOTEs here? */
1053 /* Try machine-dependent ways of modifying an illegitimate address
1054 to be legitimate. If we find one, return the new, valid address.
1055 This macro is used in only one place: `memory_address' in explow.c.
1057 OLDX is the address as it was before break_out_memory_refs was called.
1058 In some cases it is useful to look at this to decide what needs to be done.
1060 MODE and WIN are passed so that this macro can use
1061 GO_IF_LEGITIMATE_ADDRESS.
1063 It is always safe for this macro to do nothing. It exists to recognize
1064 opportunities to optimize the output.
1066 For the PA, transform:
1068 memory(X + <large int>)
1072 if (<large int> & mask) >= 16
1073 Y = (<large int> & ~mask) + mask + 1 Round up.
1075 Y = (<large int> & ~mask) Round down.
1077 memory (Z + (<large int> - Y));
1079 This is for CSE to find several similar references, and only use one Z.
1081 X can either be a SYMBOL_REF or REG, but because combine can not
1082 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1083 D will not fit in 14 bits.
1085 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1088 MODE_INT references allow displacements which fit in 14 bits, so use
1091 This relies on the fact that most mode MODE_FLOAT references will use FP
1092 registers and most mode MODE_INT references will use integer registers.
1093 (In the rare case of an FP register used in an integer MODE, we depend
1094 on secondary reloads to clean things up.)
1097 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1098 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1099 addressing modes to be used).
1101 Put X and Z into registers. Then put the entire expression into
1105 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1106 enum machine_mode mode)
1110 /* We need to canonicalize the order of operands in unscaled indexed
1111 addresses since the code that checks if an address is valid doesn't
1112 always try both orders. */
1113 if (!TARGET_NO_SPACE_REGS
1114 && GET_CODE (x) == PLUS
1115 && GET_MODE (x) == Pmode
1116 && REG_P (XEXP (x, 0))
1117 && REG_P (XEXP (x, 1))
1118 && REG_POINTER (XEXP (x, 0))
1119 && !REG_POINTER (XEXP (x, 1)))
1120 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1123 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1125 /* Strip off CONST. */
1126 if (GET_CODE (x) == CONST)
1129 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1130 That should always be safe. */
1131 if (GET_CODE (x) == PLUS
1132 && GET_CODE (XEXP (x, 0)) == REG
1133 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1135 rtx reg = force_reg (Pmode, XEXP (x, 1));
1136 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1139 /* Note we must reject symbols which represent function addresses
1140 since the assembler/linker can't handle arithmetic on plabels. */
1141 if (GET_CODE (x) == PLUS
1142 && GET_CODE (XEXP (x, 1)) == CONST_INT
1143 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1144 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1145 || GET_CODE (XEXP (x, 0)) == REG))
1147 rtx int_part, ptr_reg;
1149 int offset = INTVAL (XEXP (x, 1));
1152 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1153 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1155 /* Choose which way to round the offset. Round up if we
1156 are >= halfway to the next boundary. */
1157 if ((offset & mask) >= ((mask + 1) / 2))
1158 newoffset = (offset & ~ mask) + mask + 1;
1160 newoffset = (offset & ~ mask);
1162 /* If the newoffset will not fit in 14 bits (ldo), then
1163 handling this would take 4 or 5 instructions (2 to load
1164 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1165 add the new offset and the SYMBOL_REF.) Combine can
1166 not handle 4->2 or 5->2 combinations, so do not create
1168 if (! VAL_14_BITS_P (newoffset)
1169 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1171 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1174 gen_rtx_HIGH (Pmode, const_part));
1177 gen_rtx_LO_SUM (Pmode,
1178 tmp_reg, const_part));
1182 if (! VAL_14_BITS_P (newoffset))
1183 int_part = force_reg (Pmode, GEN_INT (newoffset));
1185 int_part = GEN_INT (newoffset);
1187 ptr_reg = force_reg (Pmode,
1188 gen_rtx_PLUS (Pmode,
1189 force_reg (Pmode, XEXP (x, 0)),
1192 return plus_constant (ptr_reg, offset - newoffset);
1195 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1197 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1198 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1199 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1200 && (OBJECT_P (XEXP (x, 1))
1201 || GET_CODE (XEXP (x, 1)) == SUBREG)
1202 && GET_CODE (XEXP (x, 1)) != CONST)
1204 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1208 if (GET_CODE (reg1) != REG)
1209 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1211 reg2 = XEXP (XEXP (x, 0), 0);
1212 if (GET_CODE (reg2) != REG)
1213 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1215 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1216 gen_rtx_MULT (Pmode,
1222 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1224 Only do so for floating point modes since this is more speculative
1225 and we lose if it's an integer store. */
1226 if (GET_CODE (x) == PLUS
1227 && GET_CODE (XEXP (x, 0)) == PLUS
1228 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1229 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1230 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1231 && (mode == SFmode || mode == DFmode))
1234 /* First, try and figure out what to use as a base register. */
1235 rtx reg1, reg2, base, idx, orig_base;
1237 reg1 = XEXP (XEXP (x, 0), 1);
1242 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1243 then emit_move_sequence will turn on REG_POINTER so we'll know
1244 it's a base register below. */
1245 if (GET_CODE (reg1) != REG)
1246 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1248 if (GET_CODE (reg2) != REG)
1249 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1251 /* Figure out what the base and index are. */
1253 if (GET_CODE (reg1) == REG
1254 && REG_POINTER (reg1))
1257 orig_base = XEXP (XEXP (x, 0), 1);
1258 idx = gen_rtx_PLUS (Pmode,
1259 gen_rtx_MULT (Pmode,
1260 XEXP (XEXP (XEXP (x, 0), 0), 0),
1261 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1264 else if (GET_CODE (reg2) == REG
1265 && REG_POINTER (reg2))
1268 orig_base = XEXP (x, 1);
1275 /* If the index adds a large constant, try to scale the
1276 constant so that it can be loaded with only one insn. */
1277 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1278 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1279 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1280 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1282 /* Divide the CONST_INT by the scale factor, then add it to A. */
1283 int val = INTVAL (XEXP (idx, 1));
1285 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1286 reg1 = XEXP (XEXP (idx, 0), 0);
1287 if (GET_CODE (reg1) != REG)
1288 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1290 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1292 /* We can now generate a simple scaled indexed address. */
1295 (Pmode, gen_rtx_PLUS (Pmode,
1296 gen_rtx_MULT (Pmode, reg1,
1297 XEXP (XEXP (idx, 0), 1)),
1301 /* If B + C is still a valid base register, then add them. */
1302 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1303 && INTVAL (XEXP (idx, 1)) <= 4096
1304 && INTVAL (XEXP (idx, 1)) >= -4096)
1306 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1309 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1311 reg2 = XEXP (XEXP (idx, 0), 0);
1312 if (GET_CODE (reg2) != CONST_INT)
1313 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1315 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1316 gen_rtx_MULT (Pmode,
1322 /* Get the index into a register, then add the base + index and
1323 return a register holding the result. */
1325 /* First get A into a register. */
1326 reg1 = XEXP (XEXP (idx, 0), 0);
1327 if (GET_CODE (reg1) != REG)
1328 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1330 /* And get B into a register. */
1331 reg2 = XEXP (idx, 1);
1332 if (GET_CODE (reg2) != REG)
1333 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1335 reg1 = force_reg (Pmode,
1336 gen_rtx_PLUS (Pmode,
1337 gen_rtx_MULT (Pmode, reg1,
1338 XEXP (XEXP (idx, 0), 1)),
1341 /* Add the result to our base register and return. */
1342 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1346 /* Uh-oh. We might have an address for x[n-100000]. This needs
1347 special handling to avoid creating an indexed memory address
1348 with x-100000 as the base.
1350 If the constant part is small enough, then it's still safe because
1351 there is a guard page at the beginning and end of the data segment.
1353 Scaled references are common enough that we want to try and rearrange the
1354 terms so that we can use indexing for these addresses too. Only
1355 do the optimization for floatint point modes. */
1357 if (GET_CODE (x) == PLUS
1358 && symbolic_expression_p (XEXP (x, 1)))
1360 /* Ugly. We modify things here so that the address offset specified
1361 by the index expression is computed first, then added to x to form
1362 the entire address. */
1364 rtx regx1, regx2, regy1, regy2, y;
1366 /* Strip off any CONST. */
1368 if (GET_CODE (y) == CONST)
1371 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1373 /* See if this looks like
1374 (plus (mult (reg) (shadd_const))
1375 (const (plus (symbol_ref) (const_int))))
1377 Where const_int is small. In that case the const
1378 expression is a valid pointer for indexing.
1380 If const_int is big, but can be divided evenly by shadd_const
1381 and added to (reg). This allows more scaled indexed addresses. */
1382 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1383 && GET_CODE (XEXP (x, 0)) == MULT
1384 && GET_CODE (XEXP (y, 1)) == CONST_INT
1385 && INTVAL (XEXP (y, 1)) >= -4096
1386 && INTVAL (XEXP (y, 1)) <= 4095
1387 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1388 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1390 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1394 if (GET_CODE (reg1) != REG)
1395 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1397 reg2 = XEXP (XEXP (x, 0), 0);
1398 if (GET_CODE (reg2) != REG)
1399 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1401 return force_reg (Pmode,
1402 gen_rtx_PLUS (Pmode,
1403 gen_rtx_MULT (Pmode,
1408 else if ((mode == DFmode || mode == SFmode)
1409 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1410 && GET_CODE (XEXP (x, 0)) == MULT
1411 && GET_CODE (XEXP (y, 1)) == CONST_INT
1412 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1413 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1414 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1417 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1418 / INTVAL (XEXP (XEXP (x, 0), 1))));
1419 regx2 = XEXP (XEXP (x, 0), 0);
1420 if (GET_CODE (regx2) != REG)
1421 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1422 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1426 gen_rtx_PLUS (Pmode,
1427 gen_rtx_MULT (Pmode, regx2,
1428 XEXP (XEXP (x, 0), 1)),
1429 force_reg (Pmode, XEXP (y, 0))));
1431 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1432 && INTVAL (XEXP (y, 1)) >= -4096
1433 && INTVAL (XEXP (y, 1)) <= 4095)
1435 /* This is safe because of the guard page at the
1436 beginning and end of the data space. Just
1437 return the original address. */
1442 /* Doesn't look like one we can optimize. */
1443 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1444 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1445 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1446 regx1 = force_reg (Pmode,
1447 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1449 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1457 /* For the HPPA, REG and REG+CONST is cost 0
1458 and addresses involving symbolic constants are cost 2.
1460 PIC addresses are very expensive.
1462 It is no coincidence that this has the same structure
1463 as GO_IF_LEGITIMATE_ADDRESS. */
1466 hppa_address_cost (rtx X)
1468 switch (GET_CODE (X))
1481 /* Compute a (partial) cost for rtx X. Return true if the complete
1482 cost has been computed, and false if subexpressions should be
1483 scanned. In either case, *TOTAL contains the cost result. */
1486 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1491 if (INTVAL (x) == 0)
1493 else if (INT_14_BITS (x))
1510 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1511 && outer_code != SET)
1518 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1519 *total = COSTS_N_INSNS (3);
1520 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1521 *total = COSTS_N_INSNS (8);
1523 *total = COSTS_N_INSNS (20);
1527 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1529 *total = COSTS_N_INSNS (14);
1537 *total = COSTS_N_INSNS (60);
1540 case PLUS: /* this includes shNadd insns */
1542 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1543 *total = COSTS_N_INSNS (3);
1545 *total = COSTS_N_INSNS (1);
1551 *total = COSTS_N_INSNS (1);
1559 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1560 new rtx with the correct mode. */
1562 force_mode (enum machine_mode mode, rtx orig)
1564 if (mode == GET_MODE (orig))
1567 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1570 return gen_rtx_REG (mode, REGNO (orig));
1573 /* Emit insns to move operands[1] into operands[0].
1575 Return 1 if we have written out everything that needs to be done to
1576 do the move. Otherwise, return 0 and the caller will emit the move
1579 Note SCRATCH_REG may not be in the proper mode depending on how it
1580 will be used. This routine is responsible for creating a new copy
1581 of SCRATCH_REG in the proper mode. */
1584 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1586 register rtx operand0 = operands[0];
1587 register rtx operand1 = operands[1];
1590 /* We can only handle indexed addresses in the destination operand
1591 of floating point stores. Thus, we need to break out indexed
1592 addresses from the destination operand. */
1593 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1595 /* This is only safe up to the beginning of life analysis. */
1599 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1600 operand0 = replace_equiv_address (operand0, tem);
1603 /* On targets with non-equivalent space registers, break out unscaled
1604 indexed addresses from the source operand before the final CSE.
1605 We have to do this because the REG_POINTER flag is not correctly
1606 carried through various optimization passes and CSE may substitute
1607 a pseudo without the pointer set for one with the pointer set. As
1608 a result, we loose various opportunities to create insns with
1609 unscaled indexed addresses. */
1610 if (!TARGET_NO_SPACE_REGS
1611 && !cse_not_expected
1612 && GET_CODE (operand1) == MEM
1613 && GET_CODE (XEXP (operand1, 0)) == PLUS
1614 && REG_P (XEXP (XEXP (operand1, 0), 0))
1615 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1617 = replace_equiv_address (operand1,
1618 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1621 && reload_in_progress && GET_CODE (operand0) == REG
1622 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1623 operand0 = reg_equiv_mem[REGNO (operand0)];
1624 else if (scratch_reg
1625 && reload_in_progress && GET_CODE (operand0) == SUBREG
1626 && GET_CODE (SUBREG_REG (operand0)) == REG
1627 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1629 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1630 the code which tracks sets/uses for delete_output_reload. */
1631 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1632 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1633 SUBREG_BYTE (operand0));
1634 operand0 = alter_subreg (&temp);
1638 && reload_in_progress && GET_CODE (operand1) == REG
1639 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1640 operand1 = reg_equiv_mem[REGNO (operand1)];
1641 else if (scratch_reg
1642 && reload_in_progress && GET_CODE (operand1) == SUBREG
1643 && GET_CODE (SUBREG_REG (operand1)) == REG
1644 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1646 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1647 the code which tracks sets/uses for delete_output_reload. */
1648 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1649 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1650 SUBREG_BYTE (operand1));
1651 operand1 = alter_subreg (&temp);
1654 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1655 && ((tem = find_replacement (&XEXP (operand0, 0)))
1656 != XEXP (operand0, 0)))
1657 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1659 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1660 && ((tem = find_replacement (&XEXP (operand1, 0)))
1661 != XEXP (operand1, 0)))
1662 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1664 /* Handle secondary reloads for loads/stores of FP registers from
1665 REG+D addresses where D does not fit in 5 or 14 bits, including
1666 (subreg (mem (addr))) cases. */
1668 && fp_reg_operand (operand0, mode)
1669 && ((GET_CODE (operand1) == MEM
1670 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1671 XEXP (operand1, 0)))
1672 || ((GET_CODE (operand1) == SUBREG
1673 && GET_CODE (XEXP (operand1, 0)) == MEM
1674 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1676 XEXP (XEXP (operand1, 0), 0))))))
1678 if (GET_CODE (operand1) == SUBREG)
1679 operand1 = XEXP (operand1, 0);
1681 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1682 it in WORD_MODE regardless of what mode it was originally given
1684 scratch_reg = force_mode (word_mode, scratch_reg);
1686 /* D might not fit in 14 bits either; for such cases load D into
1688 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1690 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1691 emit_move_insn (scratch_reg,
1692 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1694 XEXP (XEXP (operand1, 0), 0),
1698 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1699 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1700 gen_rtx_MEM (mode, scratch_reg)));
1703 else if (scratch_reg
1704 && fp_reg_operand (operand1, mode)
1705 && ((GET_CODE (operand0) == MEM
1706 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1708 XEXP (operand0, 0)))
1709 || ((GET_CODE (operand0) == SUBREG)
1710 && GET_CODE (XEXP (operand0, 0)) == MEM
1711 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1713 XEXP (XEXP (operand0, 0), 0)))))
1715 if (GET_CODE (operand0) == SUBREG)
1716 operand0 = XEXP (operand0, 0);
1718 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1719 it in WORD_MODE regardless of what mode it was originally given
1721 scratch_reg = force_mode (word_mode, scratch_reg);
1723 /* D might not fit in 14 bits either; for such cases load D into
1725 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1727 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1728 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1731 XEXP (XEXP (operand0, 0),
1736 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1737 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1741 /* Handle secondary reloads for loads of FP registers from constant
1742 expressions by forcing the constant into memory.
1744 Use scratch_reg to hold the address of the memory location.
1746 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1747 NO_REGS when presented with a const_int and a register class
1748 containing only FP registers. Doing so unfortunately creates
1749 more problems than it solves. Fix this for 2.5. */
1750 else if (scratch_reg
1751 && CONSTANT_P (operand1)
1752 && fp_reg_operand (operand0, mode))
1756 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1757 it in WORD_MODE regardless of what mode it was originally given
1759 scratch_reg = force_mode (word_mode, scratch_reg);
1761 /* Force the constant into memory and put the address of the
1762 memory location into scratch_reg. */
1763 xoperands[0] = scratch_reg;
1764 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1765 emit_move_sequence (xoperands, Pmode, 0);
1767 /* Now load the destination register. */
1768 emit_insn (gen_rtx_SET (mode, operand0,
1769 gen_rtx_MEM (mode, scratch_reg)));
1772 /* Handle secondary reloads for SAR. These occur when trying to load
1773 the SAR from memory, FP register, or with a constant. */
1774 else if (scratch_reg
1775 && GET_CODE (operand0) == REG
1776 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1777 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1778 && (GET_CODE (operand1) == MEM
1779 || GET_CODE (operand1) == CONST_INT
1780 || (GET_CODE (operand1) == REG
1781 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1783 /* D might not fit in 14 bits either; for such cases load D into
1785 if (GET_CODE (operand1) == MEM
1786 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1788 /* We are reloading the address into the scratch register, so we
1789 want to make sure the scratch register is a full register. */
1790 scratch_reg = force_mode (word_mode, scratch_reg);
1792 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1793 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1796 XEXP (XEXP (operand1, 0),
1800 /* Now we are going to load the scratch register from memory,
1801 we want to load it in the same width as the original MEM,
1802 which must be the same as the width of the ultimate destination,
1804 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1806 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1811 /* We want to load the scratch register using the same mode as
1812 the ultimate destination. */
1813 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1815 emit_move_insn (scratch_reg, operand1);
1818 /* And emit the insn to set the ultimate destination. We know that
1819 the scratch register has the same mode as the destination at this
1821 emit_move_insn (operand0, scratch_reg);
1824 /* Handle the most common case: storing into a register. */
1825 else if (register_operand (operand0, mode))
1827 if (register_operand (operand1, mode)
1828 || (GET_CODE (operand1) == CONST_INT
1829 && cint_ok_for_move (INTVAL (operand1)))
1830 || (operand1 == CONST0_RTX (mode))
1831 || (GET_CODE (operand1) == HIGH
1832 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1833 /* Only `general_operands' can come here, so MEM is ok. */
1834 || GET_CODE (operand1) == MEM)
1836 /* Various sets are created during RTL generation which don't
1837 have the REG_POINTER flag correctly set. After the CSE pass,
1838 instruction recognition can fail if we don't consistently
1839 set this flag when performing register copies. This should
1840 also improve the opportunities for creating insns that use
1841 unscaled indexing. */
1842 if (REG_P (operand0) && REG_P (operand1))
1844 if (REG_POINTER (operand1)
1845 && !REG_POINTER (operand0)
1846 && !HARD_REGISTER_P (operand0))
1847 copy_reg_pointer (operand0, operand1);
1848 else if (REG_POINTER (operand0)
1849 && !REG_POINTER (operand1)
1850 && !HARD_REGISTER_P (operand1))
1851 copy_reg_pointer (operand1, operand0);
1854 /* When MEMs are broken out, the REG_POINTER flag doesn't
1855 get set. In some cases, we can set the REG_POINTER flag
1856 from the declaration for the MEM. */
1857 if (REG_P (operand0)
1858 && GET_CODE (operand1) == MEM
1859 && !REG_POINTER (operand0))
1861 tree decl = MEM_EXPR (operand1);
1863 /* Set the register pointer flag and register alignment
1864 if the declaration for this memory reference is a
1865 pointer type. Fortran indirect argument references
1868 && !(flag_argument_noalias > 1
1869 && TREE_CODE (decl) == INDIRECT_REF
1870 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1874 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1876 if (TREE_CODE (decl) == COMPONENT_REF)
1877 decl = TREE_OPERAND (decl, 1);
1879 type = TREE_TYPE (decl);
1880 if (TREE_CODE (type) == ARRAY_TYPE)
1881 type = get_inner_array_type (type);
1883 if (POINTER_TYPE_P (type))
1887 type = TREE_TYPE (type);
1888 /* Using TYPE_ALIGN_OK is rather conservative as
1889 only the ada frontend actually sets it. */
1890 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1892 mark_reg_pointer (operand0, align);
1897 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1901 else if (GET_CODE (operand0) == MEM)
1903 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1904 && !(reload_in_progress || reload_completed))
1906 rtx temp = gen_reg_rtx (DFmode);
1908 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1909 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1912 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1914 /* Run this case quickly. */
1915 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1918 if (! (reload_in_progress || reload_completed))
1920 operands[0] = validize_mem (operand0);
1921 operands[1] = operand1 = force_reg (mode, operand1);
1925 /* Simplify the source if we need to.
1926 Note we do have to handle function labels here, even though we do
1927 not consider them legitimate constants. Loop optimizations can
1928 call the emit_move_xxx with one as a source. */
1929 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1930 || function_label_operand (operand1, mode)
1931 || (GET_CODE (operand1) == HIGH
1932 && symbolic_operand (XEXP (operand1, 0), mode)))
1936 if (GET_CODE (operand1) == HIGH)
1939 operand1 = XEXP (operand1, 0);
1941 if (symbolic_operand (operand1, mode))
1943 /* Argh. The assembler and linker can't handle arithmetic
1946 So we force the plabel into memory, load operand0 from
1947 the memory location, then add in the constant part. */
1948 if ((GET_CODE (operand1) == CONST
1949 && GET_CODE (XEXP (operand1, 0)) == PLUS
1950 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1951 || function_label_operand (operand1, mode))
1953 rtx temp, const_part;
1955 /* Figure out what (if any) scratch register to use. */
1956 if (reload_in_progress || reload_completed)
1958 scratch_reg = scratch_reg ? scratch_reg : operand0;
1959 /* SCRATCH_REG will hold an address and maybe the actual
1960 data. We want it in WORD_MODE regardless of what mode it
1961 was originally given to us. */
1962 scratch_reg = force_mode (word_mode, scratch_reg);
1965 scratch_reg = gen_reg_rtx (Pmode);
1967 if (GET_CODE (operand1) == CONST)
1969 /* Save away the constant part of the expression. */
1970 const_part = XEXP (XEXP (operand1, 0), 1);
1971 if (GET_CODE (const_part) != CONST_INT)
1974 /* Force the function label into memory. */
1975 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1979 /* No constant part. */
1980 const_part = NULL_RTX;
1982 /* Force the function label into memory. */
1983 temp = force_const_mem (mode, operand1);
1987 /* Get the address of the memory location. PIC-ify it if
1989 temp = XEXP (temp, 0);
1991 temp = legitimize_pic_address (temp, mode, scratch_reg);
1993 /* Put the address of the memory location into our destination
1996 emit_move_sequence (operands, mode, scratch_reg);
1998 /* Now load from the memory location into our destination
2000 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
2001 emit_move_sequence (operands, mode, scratch_reg);
2003 /* And add back in the constant part. */
2004 if (const_part != NULL_RTX)
2005 expand_inc (operand0, const_part);
2014 if (reload_in_progress || reload_completed)
2016 temp = scratch_reg ? scratch_reg : operand0;
2017 /* TEMP will hold an address and maybe the actual
2018 data. We want it in WORD_MODE regardless of what mode it
2019 was originally given to us. */
2020 temp = force_mode (word_mode, temp);
2023 temp = gen_reg_rtx (Pmode);
2025 /* (const (plus (symbol) (const_int))) must be forced to
2026 memory during/after reload if the const_int will not fit
2028 if (GET_CODE (operand1) == CONST
2029 && GET_CODE (XEXP (operand1, 0)) == PLUS
2030 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
2031 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
2032 && (reload_completed || reload_in_progress)
2035 operands[1] = force_const_mem (mode, operand1);
2036 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
2038 operands[1] = gen_rtx_MEM (mode, operands[1]);
2039 emit_move_sequence (operands, mode, temp);
2043 operands[1] = legitimize_pic_address (operand1, mode, temp);
2044 if (REG_P (operand0) && REG_P (operands[1]))
2045 copy_reg_pointer (operand0, operands[1]);
2046 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2049 /* On the HPPA, references to data space are supposed to use dp,
2050 register 27, but showing it in the RTL inhibits various cse
2051 and loop optimizations. */
2056 if (reload_in_progress || reload_completed)
2058 temp = scratch_reg ? scratch_reg : operand0;
2059 /* TEMP will hold an address and maybe the actual
2060 data. We want it in WORD_MODE regardless of what mode it
2061 was originally given to us. */
2062 temp = force_mode (word_mode, temp);
2065 temp = gen_reg_rtx (mode);
2067 /* Loading a SYMBOL_REF into a register makes that register
2068 safe to be used as the base in an indexed address.
2070 Don't mark hard registers though. That loses. */
2071 if (GET_CODE (operand0) == REG
2072 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2073 mark_reg_pointer (operand0, BITS_PER_UNIT);
2074 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2075 mark_reg_pointer (temp, BITS_PER_UNIT);
2078 set = gen_rtx_SET (mode, operand0, temp);
2080 set = gen_rtx_SET (VOIDmode,
2082 gen_rtx_LO_SUM (mode, temp, operand1));
2084 emit_insn (gen_rtx_SET (VOIDmode,
2086 gen_rtx_HIGH (mode, operand1)));
2092 else if (GET_CODE (operand1) != CONST_INT
2093 || !cint_ok_for_move (INTVAL (operand1)))
2097 HOST_WIDE_INT value = 0;
2098 HOST_WIDE_INT insv = 0;
2101 if (GET_CODE (operand1) == CONST_INT)
2102 value = INTVAL (operand1);
2105 && GET_CODE (operand1) == CONST_INT
2106 && HOST_BITS_PER_WIDE_INT > 32
2107 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2111 /* Extract the low order 32 bits of the value and sign extend.
2112 If the new value is the same as the original value, we can
2113 can use the original value as-is. If the new value is
2114 different, we use it and insert the most-significant 32-bits
2115 of the original value into the final result. */
2116 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2117 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2120 #if HOST_BITS_PER_WIDE_INT > 32
2121 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2125 operand1 = GEN_INT (nval);
2129 if (reload_in_progress || reload_completed)
2130 temp = scratch_reg ? scratch_reg : operand0;
2132 temp = gen_reg_rtx (mode);
2134 /* We don't directly split DImode constants on 32-bit targets
2135 because PLUS uses an 11-bit immediate and the insn sequence
2136 generated is not as efficient as the one using HIGH/LO_SUM. */
2137 if (GET_CODE (operand1) == CONST_INT
2138 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2141 /* Directly break constant into high and low parts. This
2142 provides better optimization opportunities because various
2143 passes recognize constants split with PLUS but not LO_SUM.
2144 We use a 14-bit signed low part except when the addition
2145 of 0x4000 to the high part might change the sign of the
2147 HOST_WIDE_INT low = value & 0x3fff;
2148 HOST_WIDE_INT high = value & ~ 0x3fff;
2152 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2160 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2161 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2165 emit_insn (gen_rtx_SET (VOIDmode, temp,
2166 gen_rtx_HIGH (mode, operand1)));
2167 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2170 insn = emit_move_insn (operands[0], operands[1]);
2172 /* Now insert the most significant 32 bits of the value
2173 into the register. When we don't have a second register
2174 available, it could take up to nine instructions to load
2175 a 64-bit integer constant. Prior to reload, we force
2176 constants that would take more than three instructions
2177 to load to the constant pool. During and after reload,
2178 we have to handle all possible values. */
2181 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2182 register and the value to be inserted is outside the
2183 range that can be loaded with three depdi instructions. */
2184 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2186 operand1 = GEN_INT (insv);
2188 emit_insn (gen_rtx_SET (VOIDmode, temp,
2189 gen_rtx_HIGH (mode, operand1)));
2190 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2191 emit_insn (gen_insv (operand0, GEN_INT (32),
2196 int len = 5, pos = 27;
2198 /* Insert the bits using the depdi instruction. */
2201 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2202 HOST_WIDE_INT sign = v5 < 0;
2204 /* Left extend the insertion. */
2205 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2206 while (pos > 0 && (insv & 1) == sign)
2208 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2213 emit_insn (gen_insv (operand0, GEN_INT (len),
2214 GEN_INT (pos), GEN_INT (v5)));
2216 len = pos > 0 && pos < 5 ? pos : 5;
2223 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2228 /* Now have insn-emit do whatever it normally does. */
2232 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2233 it will need a link/runtime reloc). */
2236 reloc_needed (tree exp)
2240 switch (TREE_CODE (exp))
2247 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2248 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2253 case NON_LVALUE_EXPR:
2254 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2260 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2261 if (TREE_VALUE (link) != 0)
2262 reloc |= reloc_needed (TREE_VALUE (link));
2275 /* Does operand (which is a symbolic_operand) live in text space?
2276 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2280 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2282 if (GET_CODE (operand) == CONST)
2283 operand = XEXP (XEXP (operand, 0), 0);
2286 if (GET_CODE (operand) == SYMBOL_REF)
2287 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2291 if (GET_CODE (operand) == SYMBOL_REF)
2292 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2298 /* Return the best assembler insn template
2299 for moving operands[1] into operands[0] as a fullword. */
2301 singlemove_string (rtx *operands)
2303 HOST_WIDE_INT intval;
2305 if (GET_CODE (operands[0]) == MEM)
2306 return "stw %r1,%0";
2307 if (GET_CODE (operands[1]) == MEM)
2309 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2314 if (GET_MODE (operands[1]) != SFmode)
2317 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2319 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2320 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2322 operands[1] = GEN_INT (i);
2323 /* Fall through to CONST_INT case. */
2325 if (GET_CODE (operands[1]) == CONST_INT)
2327 intval = INTVAL (operands[1]);
2329 if (VAL_14_BITS_P (intval))
2331 else if ((intval & 0x7ff) == 0)
2332 return "ldil L'%1,%0";
2333 else if (zdepi_cint_p (intval))
2334 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2336 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2338 return "copy %1,%0";
2342 /* Compute position (in OP[1]) and width (in OP[2])
2343 useful for copying IMM to a register using the zdepi
2344 instructions. Store the immediate value to insert in OP[0]. */
2346 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2350 /* Find the least significant set bit in IMM. */
2351 for (lsb = 0; lsb < 32; lsb++)
2358 /* Choose variants based on *sign* of the 5-bit field. */
2359 if ((imm & 0x10) == 0)
2360 len = (lsb <= 28) ? 4 : 32 - lsb;
2363 /* Find the width of the bitstring in IMM. */
2364 for (len = 5; len < 32; len++)
2366 if ((imm & (1 << len)) == 0)
2370 /* Sign extend IMM as a 5-bit value. */
2371 imm = (imm & 0xf) - 0x10;
2379 /* Compute position (in OP[1]) and width (in OP[2])
2380 useful for copying IMM to a register using the depdi,z
2381 instructions. Store the immediate value to insert in OP[0]. */
2383 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2385 HOST_WIDE_INT lsb, len;
2387 /* Find the least significant set bit in IMM. */
2388 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2395 /* Choose variants based on *sign* of the 5-bit field. */
2396 if ((imm & 0x10) == 0)
2397 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2398 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2401 /* Find the width of the bitstring in IMM. */
2402 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2404 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2408 /* Sign extend IMM as a 5-bit value. */
2409 imm = (imm & 0xf) - 0x10;
2417 /* Output assembler code to perform a doubleword move insn
2418 with operands OPERANDS. */
2421 output_move_double (rtx *operands)
2423 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2425 rtx addreg0 = 0, addreg1 = 0;
2427 /* First classify both operands. */
2429 if (REG_P (operands[0]))
2431 else if (offsettable_memref_p (operands[0]))
2433 else if (GET_CODE (operands[0]) == MEM)
2438 if (REG_P (operands[1]))
2440 else if (CONSTANT_P (operands[1]))
2442 else if (offsettable_memref_p (operands[1]))
2444 else if (GET_CODE (operands[1]) == MEM)
2449 /* Check for the cases that the operand constraints are not
2450 supposed to allow to happen. Abort if we get one,
2451 because generating code for these cases is painful. */
2453 if (optype0 != REGOP && optype1 != REGOP)
2456 /* Handle auto decrementing and incrementing loads and stores
2457 specifically, since the structure of the function doesn't work
2458 for them without major modification. Do it better when we learn
2459 this port about the general inc/dec addressing of PA.
2460 (This was written by tege. Chide him if it doesn't work.) */
2462 if (optype0 == MEMOP)
2464 /* We have to output the address syntax ourselves, since print_operand
2465 doesn't deal with the addresses we want to use. Fix this later. */
2467 rtx addr = XEXP (operands[0], 0);
2468 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2470 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2472 operands[0] = XEXP (addr, 0);
2473 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2476 if (!reg_overlap_mentioned_p (high_reg, addr))
2478 /* No overlap between high target register and address
2479 register. (We do this in a non-obvious way to
2480 save a register file writeback) */
2481 if (GET_CODE (addr) == POST_INC)
2482 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2483 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2488 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2490 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2492 operands[0] = XEXP (addr, 0);
2493 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2496 if (!reg_overlap_mentioned_p (high_reg, addr))
2498 /* No overlap between high target register and address
2499 register. (We do this in a non-obvious way to
2500 save a register file writeback) */
2501 if (GET_CODE (addr) == PRE_INC)
2502 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2503 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2509 if (optype1 == MEMOP)
2511 /* We have to output the address syntax ourselves, since print_operand
2512 doesn't deal with the addresses we want to use. Fix this later. */
2514 rtx addr = XEXP (operands[1], 0);
2515 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2517 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2519 operands[1] = XEXP (addr, 0);
2520 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2523 if (!reg_overlap_mentioned_p (high_reg, addr))
2525 /* No overlap between high target register and address
2526 register. (We do this in a non-obvious way to
2527 save a register file writeback) */
2528 if (GET_CODE (addr) == POST_INC)
2529 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2530 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2534 /* This is an undefined situation. We should load into the
2535 address register *and* update that register. Probably
2536 we don't need to handle this at all. */
2537 if (GET_CODE (addr) == POST_INC)
2538 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2539 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2542 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2544 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2546 operands[1] = XEXP (addr, 0);
2547 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2550 if (!reg_overlap_mentioned_p (high_reg, addr))
2552 /* No overlap between high target register and address
2553 register. (We do this in a non-obvious way to
2554 save a register file writeback) */
2555 if (GET_CODE (addr) == PRE_INC)
2556 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2557 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2561 /* This is an undefined situation. We should load into the
2562 address register *and* update that register. Probably
2563 we don't need to handle this at all. */
2564 if (GET_CODE (addr) == PRE_INC)
2565 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2566 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2569 else if (GET_CODE (addr) == PLUS
2570 && GET_CODE (XEXP (addr, 0)) == MULT)
2572 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2574 if (!reg_overlap_mentioned_p (high_reg, addr))
2578 xoperands[0] = high_reg;
2579 xoperands[1] = XEXP (addr, 1);
2580 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2581 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2582 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2584 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2590 xoperands[0] = high_reg;
2591 xoperands[1] = XEXP (addr, 1);
2592 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2593 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2594 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2596 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2601 /* If an operand is an unoffsettable memory ref, find a register
2602 we can increment temporarily to make it refer to the second word. */
2604 if (optype0 == MEMOP)
2605 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2607 if (optype1 == MEMOP)
2608 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2610 /* Ok, we can do one word at a time.
2611 Normally we do the low-numbered word first.
2613 In either case, set up in LATEHALF the operands to use
2614 for the high-numbered word and in some cases alter the
2615 operands in OPERANDS to be suitable for the low-numbered word. */
2617 if (optype0 == REGOP)
2618 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2619 else if (optype0 == OFFSOP)
2620 latehalf[0] = adjust_address (operands[0], SImode, 4);
2622 latehalf[0] = operands[0];
2624 if (optype1 == REGOP)
2625 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2626 else if (optype1 == OFFSOP)
2627 latehalf[1] = adjust_address (operands[1], SImode, 4);
2628 else if (optype1 == CNSTOP)
2629 split_double (operands[1], &operands[1], &latehalf[1]);
2631 latehalf[1] = operands[1];
2633 /* If the first move would clobber the source of the second one,
2634 do them in the other order.
2636 This can happen in two cases:
2638 mem -> register where the first half of the destination register
2639 is the same register used in the memory's address. Reload
2640 can create such insns.
2642 mem in this case will be either register indirect or register
2643 indirect plus a valid offset.
2645 register -> register move where REGNO(dst) == REGNO(src + 1)
2646 someone (Tim/Tege?) claimed this can happen for parameter loads.
2648 Handle mem -> register case first. */
2649 if (optype0 == REGOP
2650 && (optype1 == MEMOP || optype1 == OFFSOP)
2651 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2654 /* Do the late half first. */
2656 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2657 output_asm_insn (singlemove_string (latehalf), latehalf);
2661 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2662 return singlemove_string (operands);
2665 /* Now handle register -> register case. */
2666 if (optype0 == REGOP && optype1 == REGOP
2667 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2669 output_asm_insn (singlemove_string (latehalf), latehalf);
2670 return singlemove_string (operands);
2673 /* Normal case: do the two words, low-numbered first. */
2675 output_asm_insn (singlemove_string (operands), operands);
2677 /* Make any unoffsettable addresses point at high-numbered word. */
2679 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2681 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2684 output_asm_insn (singlemove_string (latehalf), latehalf);
2686 /* Undo the adds we just did. */
2688 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2690 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2696 output_fp_move_double (rtx *operands)
2698 if (FP_REG_P (operands[0]))
2700 if (FP_REG_P (operands[1])
2701 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2702 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2704 output_asm_insn ("fldd%F1 %1,%0", operands);
2706 else if (FP_REG_P (operands[1]))
2708 output_asm_insn ("fstd%F0 %1,%0", operands);
2710 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2712 if (GET_CODE (operands[0]) == REG)
2715 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2716 xoperands[0] = operands[0];
2717 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2719 /* This is a pain. You have to be prepared to deal with an
2720 arbitrary address here including pre/post increment/decrement.
2722 so avoid this in the MD. */
2730 /* Return a REG that occurs in ADDR with coefficient 1.
2731 ADDR can be effectively incremented by incrementing REG. */
2734 find_addr_reg (rtx addr)
2736 while (GET_CODE (addr) == PLUS)
2738 if (GET_CODE (XEXP (addr, 0)) == REG)
2739 addr = XEXP (addr, 0);
2740 else if (GET_CODE (XEXP (addr, 1)) == REG)
2741 addr = XEXP (addr, 1);
2742 else if (CONSTANT_P (XEXP (addr, 0)))
2743 addr = XEXP (addr, 1);
2744 else if (CONSTANT_P (XEXP (addr, 1)))
2745 addr = XEXP (addr, 0);
2749 if (GET_CODE (addr) == REG)
2754 /* Emit code to perform a block move.
2756 OPERANDS[0] is the destination pointer as a REG, clobbered.
2757 OPERANDS[1] is the source pointer as a REG, clobbered.
2758 OPERANDS[2] is a register for temporary storage.
2759 OPERANDS[3] is a register for temporary storage.
2760 OPERANDS[4] is the size as a CONST_INT
2761 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2762 OPERANDS[6] is another temporary register. */
2765 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2767 int align = INTVAL (operands[5]);
2768 unsigned long n_bytes = INTVAL (operands[4]);
2770 /* We can't move more than a word at a time because the PA
2771 has no longer integer move insns. (Could use fp mem ops?) */
2772 if (align > (TARGET_64BIT ? 8 : 4))
2773 align = (TARGET_64BIT ? 8 : 4);
2775 /* Note that we know each loop below will execute at least twice
2776 (else we would have open-coded the copy). */
2780 /* Pre-adjust the loop counter. */
2781 operands[4] = GEN_INT (n_bytes - 16);
2782 output_asm_insn ("ldi %4,%2", operands);
2785 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2786 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2787 output_asm_insn ("std,ma %3,8(%0)", operands);
2788 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2789 output_asm_insn ("std,ma %6,8(%0)", operands);
2791 /* Handle the residual. There could be up to 7 bytes of
2792 residual to copy! */
2793 if (n_bytes % 16 != 0)
2795 operands[4] = GEN_INT (n_bytes % 8);
2796 if (n_bytes % 16 >= 8)
2797 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2798 if (n_bytes % 8 != 0)
2799 output_asm_insn ("ldd 0(%1),%6", operands);
2800 if (n_bytes % 16 >= 8)
2801 output_asm_insn ("std,ma %3,8(%0)", operands);
2802 if (n_bytes % 8 != 0)
2803 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2808 /* Pre-adjust the loop counter. */
2809 operands[4] = GEN_INT (n_bytes - 8);
2810 output_asm_insn ("ldi %4,%2", operands);
2813 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2814 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2815 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2816 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2817 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2819 /* Handle the residual. There could be up to 7 bytes of
2820 residual to copy! */
2821 if (n_bytes % 8 != 0)
2823 operands[4] = GEN_INT (n_bytes % 4);
2824 if (n_bytes % 8 >= 4)
2825 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2826 if (n_bytes % 4 != 0)
2827 output_asm_insn ("ldw 0(%1),%6", operands);
2828 if (n_bytes % 8 >= 4)
2829 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2830 if (n_bytes % 4 != 0)
2831 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2836 /* Pre-adjust the loop counter. */
2837 operands[4] = GEN_INT (n_bytes - 4);
2838 output_asm_insn ("ldi %4,%2", operands);
2841 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2842 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2843 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2844 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2845 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2847 /* Handle the residual. */
2848 if (n_bytes % 4 != 0)
2850 if (n_bytes % 4 >= 2)
2851 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2852 if (n_bytes % 2 != 0)
2853 output_asm_insn ("ldb 0(%1),%6", operands);
2854 if (n_bytes % 4 >= 2)
2855 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2856 if (n_bytes % 2 != 0)
2857 output_asm_insn ("stb %6,0(%0)", operands);
2862 /* Pre-adjust the loop counter. */
2863 operands[4] = GEN_INT (n_bytes - 2);
2864 output_asm_insn ("ldi %4,%2", operands);
2867 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2868 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2869 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2870 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2871 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2873 /* Handle the residual. */
2874 if (n_bytes % 2 != 0)
2876 output_asm_insn ("ldb 0(%1),%3", operands);
2877 output_asm_insn ("stb %3,0(%0)", operands);
2886 /* Count the number of insns necessary to handle this block move.
2888 Basic structure is the same as emit_block_move, except that we
2889 count insns rather than emit them. */
2892 compute_movmem_length (rtx insn)
2894 rtx pat = PATTERN (insn);
2895 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2896 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2897 unsigned int n_insns = 0;
2899 /* We can't move more than four bytes at a time because the PA
2900 has no longer integer move insns. (Could use fp mem ops?) */
2901 if (align > (TARGET_64BIT ? 8 : 4))
2902 align = (TARGET_64BIT ? 8 : 4);
2904 /* The basic copying loop. */
2908 if (n_bytes % (2 * align) != 0)
2910 if ((n_bytes % (2 * align)) >= align)
2913 if ((n_bytes % align) != 0)
2917 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2921 /* Emit code to perform a block clear.
2923 OPERANDS[0] is the destination pointer as a REG, clobbered.
2924 OPERANDS[1] is a register for temporary storage.
2925 OPERANDS[2] is the size as a CONST_INT
2926 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2929 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2931 int align = INTVAL (operands[3]);
2932 unsigned long n_bytes = INTVAL (operands[2]);
2934 /* We can't clear more than a word at a time because the PA
2935 has no longer integer move insns. */
2936 if (align > (TARGET_64BIT ? 8 : 4))
2937 align = (TARGET_64BIT ? 8 : 4);
2939 /* Note that we know each loop below will execute at least twice
2940 (else we would have open-coded the copy). */
2944 /* Pre-adjust the loop counter. */
2945 operands[2] = GEN_INT (n_bytes - 16);
2946 output_asm_insn ("ldi %2,%1", operands);
2949 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2950 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2951 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2953 /* Handle the residual. There could be up to 7 bytes of
2954 residual to copy! */
2955 if (n_bytes % 16 != 0)
2957 operands[2] = GEN_INT (n_bytes % 8);
2958 if (n_bytes % 16 >= 8)
2959 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2960 if (n_bytes % 8 != 0)
2961 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2966 /* Pre-adjust the loop counter. */
2967 operands[2] = GEN_INT (n_bytes - 8);
2968 output_asm_insn ("ldi %2,%1", operands);
2971 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2972 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2973 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2975 /* Handle the residual. There could be up to 7 bytes of
2976 residual to copy! */
2977 if (n_bytes % 8 != 0)
2979 operands[2] = GEN_INT (n_bytes % 4);
2980 if (n_bytes % 8 >= 4)
2981 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2982 if (n_bytes % 4 != 0)
2983 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2988 /* Pre-adjust the loop counter. */
2989 operands[2] = GEN_INT (n_bytes - 4);
2990 output_asm_insn ("ldi %2,%1", operands);
2993 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2994 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2995 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2997 /* Handle the residual. */
2998 if (n_bytes % 4 != 0)
3000 if (n_bytes % 4 >= 2)
3001 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3002 if (n_bytes % 2 != 0)
3003 output_asm_insn ("stb %%r0,0(%0)", operands);
3008 /* Pre-adjust the loop counter. */
3009 operands[2] = GEN_INT (n_bytes - 2);
3010 output_asm_insn ("ldi %2,%1", operands);
3013 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3014 output_asm_insn ("addib,>= -2,%1,.-4", operands);
3015 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3017 /* Handle the residual. */
3018 if (n_bytes % 2 != 0)
3019 output_asm_insn ("stb %%r0,0(%0)", operands);
3028 /* Count the number of insns necessary to handle this block move.
3030 Basic structure is the same as emit_block_move, except that we
3031 count insns rather than emit them. */
3034 compute_clrmem_length (rtx insn)
3036 rtx pat = PATTERN (insn);
3037 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
3038 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
3039 unsigned int n_insns = 0;
3041 /* We can't clear more than a word at a time because the PA
3042 has no longer integer move insns. */
3043 if (align > (TARGET_64BIT ? 8 : 4))
3044 align = (TARGET_64BIT ? 8 : 4);
3046 /* The basic loop. */
3050 if (n_bytes % (2 * align) != 0)
3052 if ((n_bytes % (2 * align)) >= align)
3055 if ((n_bytes % align) != 0)
3059 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3065 output_and (rtx *operands)
3067 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3069 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3070 int ls0, ls1, ms0, p, len;
3072 for (ls0 = 0; ls0 < 32; ls0++)
3073 if ((mask & (1 << ls0)) == 0)
3076 for (ls1 = ls0; ls1 < 32; ls1++)
3077 if ((mask & (1 << ls1)) != 0)
3080 for (ms0 = ls1; ms0 < 32; ms0++)
3081 if ((mask & (1 << ms0)) == 0)
3094 operands[2] = GEN_INT (len);
3095 return "{extru|extrw,u} %1,31,%2,%0";
3099 /* We could use this `depi' for the case above as well, but `depi'
3100 requires one more register file access than an `extru'. */
3105 operands[2] = GEN_INT (p);
3106 operands[3] = GEN_INT (len);
3107 return "{depi|depwi} 0,%2,%3,%0";
3111 return "and %1,%2,%0";
3114 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3115 storing the result in operands[0]. */
3117 output_64bit_and (rtx *operands)
3119 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3121 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3122 int ls0, ls1, ms0, p, len;
3124 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3125 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3128 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3129 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3132 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3133 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3136 if (ms0 != HOST_BITS_PER_WIDE_INT)
3139 if (ls1 == HOST_BITS_PER_WIDE_INT)
3146 operands[2] = GEN_INT (len);
3147 return "extrd,u %1,63,%2,%0";
3151 /* We could use this `depi' for the case above as well, but `depi'
3152 requires one more register file access than an `extru'. */
3157 operands[2] = GEN_INT (p);
3158 operands[3] = GEN_INT (len);
3159 return "depdi 0,%2,%3,%0";
3163 return "and %1,%2,%0";
3167 output_ior (rtx *operands)
3169 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3170 int bs0, bs1, p, len;
3172 if (INTVAL (operands[2]) == 0)
3173 return "copy %1,%0";
3175 for (bs0 = 0; bs0 < 32; bs0++)
3176 if ((mask & (1 << bs0)) != 0)
3179 for (bs1 = bs0; bs1 < 32; bs1++)
3180 if ((mask & (1 << bs1)) == 0)
3183 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3189 operands[2] = GEN_INT (p);
3190 operands[3] = GEN_INT (len);
3191 return "{depi|depwi} -1,%2,%3,%0";
3194 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3195 storing the result in operands[0]. */
3197 output_64bit_ior (rtx *operands)
3199 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3200 int bs0, bs1, p, len;
3202 if (INTVAL (operands[2]) == 0)
3203 return "copy %1,%0";
3205 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3206 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3209 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3210 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3213 if (bs1 != HOST_BITS_PER_WIDE_INT
3214 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3220 operands[2] = GEN_INT (p);
3221 operands[3] = GEN_INT (len);
3222 return "depdi -1,%2,%3,%0";
3225 /* Target hook for assembling integer objects. This code handles
3226 aligned SI and DI integers specially, since function references must
3227 be preceded by P%. */
3230 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3232 if (size == UNITS_PER_WORD && aligned_p
3233 && function_label_operand (x, VOIDmode))
3235 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3236 output_addr_const (asm_out_file, x);
3237 fputc ('\n', asm_out_file);
3240 return default_assemble_integer (x, size, aligned_p);
3243 /* Output an ascii string. */
3245 output_ascii (FILE *file, const char *p, int size)
3249 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3251 /* The HP assembler can only take strings of 256 characters at one
3252 time. This is a limitation on input line length, *not* the
3253 length of the string. Sigh. Even worse, it seems that the
3254 restriction is in number of input characters (see \xnn &
3255 \whatever). So we have to do this very carefully. */
3257 fputs ("\t.STRING \"", file);
3260 for (i = 0; i < size; i += 4)
3264 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3266 register unsigned int c = (unsigned char) p[i + io];
3268 if (c == '\"' || c == '\\')
3269 partial_output[co++] = '\\';
3270 if (c >= ' ' && c < 0177)
3271 partial_output[co++] = c;
3275 partial_output[co++] = '\\';
3276 partial_output[co++] = 'x';
3277 hexd = c / 16 - 0 + '0';
3279 hexd -= '9' - 'a' + 1;
3280 partial_output[co++] = hexd;
3281 hexd = c % 16 - 0 + '0';
3283 hexd -= '9' - 'a' + 1;
3284 partial_output[co++] = hexd;
3287 if (chars_output + co > 243)
3289 fputs ("\"\n\t.STRING \"", file);
3292 fwrite (partial_output, 1, (size_t) co, file);
3296 fputs ("\"\n", file);
3299 /* Try to rewrite floating point comparisons & branches to avoid
3300 useless add,tr insns.
3302 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3303 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3304 first attempt to remove useless add,tr insns. It is zero
3305 for the second pass as reorg sometimes leaves bogus REG_DEAD
3308 When CHECK_NOTES is zero we can only eliminate add,tr insns
3309 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3312 remove_useless_addtr_insns (int check_notes)
3315 static int pass = 0;
3317 /* This is fairly cheap, so always run it when optimizing. */
3321 int fbranch_count = 0;
3323 /* Walk all the insns in this function looking for fcmp & fbranch
3324 instructions. Keep track of how many of each we find. */
3325 for (insn = get_insns (); insn; insn = next_insn (insn))
3329 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3330 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3333 tmp = PATTERN (insn);
3335 /* It must be a set. */
3336 if (GET_CODE (tmp) != SET)
3339 /* If the destination is CCFP, then we've found an fcmp insn. */
3340 tmp = SET_DEST (tmp);
3341 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3347 tmp = PATTERN (insn);
3348 /* If this is an fbranch instruction, bump the fbranch counter. */
3349 if (GET_CODE (tmp) == SET
3350 && SET_DEST (tmp) == pc_rtx
3351 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3352 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3353 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3354 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3362 /* Find all floating point compare + branch insns. If possible,
3363 reverse the comparison & the branch to avoid add,tr insns. */
3364 for (insn = get_insns (); insn; insn = next_insn (insn))
3368 /* Ignore anything that isn't an INSN. */
3369 if (GET_CODE (insn) != INSN)
3372 tmp = PATTERN (insn);
3374 /* It must be a set. */
3375 if (GET_CODE (tmp) != SET)
3378 /* The destination must be CCFP, which is register zero. */
3379 tmp = SET_DEST (tmp);
3380 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3383 /* INSN should be a set of CCFP.
3385 See if the result of this insn is used in a reversed FP
3386 conditional branch. If so, reverse our condition and
3387 the branch. Doing so avoids useless add,tr insns. */
3388 next = next_insn (insn);
3391 /* Jumps, calls and labels stop our search. */
3392 if (GET_CODE (next) == JUMP_INSN
3393 || GET_CODE (next) == CALL_INSN
3394 || GET_CODE (next) == CODE_LABEL)
3397 /* As does another fcmp insn. */
3398 if (GET_CODE (next) == INSN
3399 && GET_CODE (PATTERN (next)) == SET
3400 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3401 && REGNO (SET_DEST (PATTERN (next))) == 0)
3404 next = next_insn (next);
3407 /* Is NEXT_INSN a branch? */
3409 && GET_CODE (next) == JUMP_INSN)
3411 rtx pattern = PATTERN (next);
3413 /* If it a reversed fp conditional branch (eg uses add,tr)
3414 and CCFP dies, then reverse our conditional and the branch
3415 to avoid the add,tr. */
3416 if (GET_CODE (pattern) == SET
3417 && SET_DEST (pattern) == pc_rtx
3418 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3419 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3420 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3421 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3422 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3423 && (fcmp_count == fbranch_count
3425 && find_regno_note (next, REG_DEAD, 0))))
3427 /* Reverse the branch. */
3428 tmp = XEXP (SET_SRC (pattern), 1);
3429 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3430 XEXP (SET_SRC (pattern), 2) = tmp;
3431 INSN_CODE (next) = -1;
3433 /* Reverse our condition. */
3434 tmp = PATTERN (insn);
3435 PUT_CODE (XEXP (tmp, 1),
3436 (reverse_condition_maybe_unordered
3437 (GET_CODE (XEXP (tmp, 1)))));
3447 /* You may have trouble believing this, but this is the 32 bit HP-PA
3452 Variable arguments (optional; any number may be allocated)
3454 SP-(4*(N+9)) arg word N
3459 Fixed arguments (must be allocated; may remain unused)
3468 SP-32 External Data Pointer (DP)
3470 SP-24 External/stub RP (RP')
3474 SP-8 Calling Stub RP (RP'')
3479 SP-0 Stack Pointer (points to next available address)
3483 /* This function saves registers as follows. Registers marked with ' are
3484 this function's registers (as opposed to the previous function's).
3485 If a frame_pointer isn't needed, r4 is saved as a general register;
3486 the space for the frame pointer is still allocated, though, to keep
3492 SP (FP') Previous FP
3493 SP + 4 Alignment filler (sigh)
3494 SP + 8 Space for locals reserved here.
3498 SP + n All call saved register used.
3502 SP + o All call saved fp registers used.
3506 SP + p (SP') points to next available address.
3510 /* Global variables set by output_function_prologue(). */
3511 /* Size of frame. Need to know this to emit return insns from
3513 static HOST_WIDE_INT actual_fsize, local_fsize;
3514 static int save_fregs;
3516 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3517 Handle case where DISP > 8k by using the add_high_const patterns.
3519 Note in DISP > 8k case, we will leave the high part of the address
3520 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3523 store_reg (int reg, HOST_WIDE_INT disp, int base)
3525 rtx insn, dest, src, basereg;
3527 src = gen_rtx_REG (word_mode, reg);
3528 basereg = gen_rtx_REG (Pmode, base);
3529 if (VAL_14_BITS_P (disp))
3531 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3532 insn = emit_move_insn (dest, src);
3534 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3536 rtx delta = GEN_INT (disp);
3537 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3539 emit_move_insn (tmpreg, delta);
3540 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3541 dest = gen_rtx_MEM (word_mode, tmpreg);
3542 insn = emit_move_insn (dest, src);
3546 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3547 gen_rtx_SET (VOIDmode,
3548 gen_rtx_MEM (word_mode,
3549 gen_rtx_PLUS (word_mode, basereg,
3557 rtx delta = GEN_INT (disp);
3558 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3559 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3561 emit_move_insn (tmpreg, high);
3562 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3563 insn = emit_move_insn (dest, src);
3567 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3568 gen_rtx_SET (VOIDmode,
3569 gen_rtx_MEM (word_mode,
3570 gen_rtx_PLUS (word_mode, basereg,
3578 RTX_FRAME_RELATED_P (insn) = 1;
3581 /* Emit RTL to store REG at the memory location specified by BASE and then
3582 add MOD to BASE. MOD must be <= 8k. */
3585 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3587 rtx insn, basereg, srcreg, delta;
3589 if (!VAL_14_BITS_P (mod))
3592 basereg = gen_rtx_REG (Pmode, base);
3593 srcreg = gen_rtx_REG (word_mode, reg);
3594 delta = GEN_INT (mod);
3596 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3599 RTX_FRAME_RELATED_P (insn) = 1;
3601 /* RTX_FRAME_RELATED_P must be set on each frame related set
3602 in a parallel with more than one element. Don't set
3603 RTX_FRAME_RELATED_P in the first set if reg is temporary
3604 register 1. The effect of this operation is recorded in
3605 the initial copy. */
3608 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3609 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3613 /* The first element of a PARALLEL is always processed if it is
3614 a SET. Thus, we need an expression list for this case. */
3616 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3617 gen_rtx_SET (VOIDmode, basereg,
3618 gen_rtx_PLUS (word_mode, basereg, delta)),
3624 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3625 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3626 whether to add a frame note or not.
3628 In the DISP > 8k case, we leave the high part of the address in %r1.
3629 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3632 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3636 if (VAL_14_BITS_P (disp))
3638 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3639 plus_constant (gen_rtx_REG (Pmode, base), disp));
3641 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3643 rtx basereg = gen_rtx_REG (Pmode, base);
3644 rtx delta = GEN_INT (disp);
3645 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3647 emit_move_insn (tmpreg, delta);
3648 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3649 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3653 rtx basereg = gen_rtx_REG (Pmode, base);
3654 rtx delta = GEN_INT (disp);
3655 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3657 emit_move_insn (tmpreg,
3658 gen_rtx_PLUS (Pmode, basereg,
3659 gen_rtx_HIGH (Pmode, delta)));
3660 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3661 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3664 if (DO_FRAME_NOTES && note)
3665 RTX_FRAME_RELATED_P (insn) = 1;
3669 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3674 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3675 be consistent with the rounding and size calculation done here.
3676 Change them at the same time. */
3678 /* We do our own stack alignment. First, round the size of the
3679 stack locals up to a word boundary. */
3680 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3682 /* Space for previous frame pointer + filler. If any frame is
3683 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3684 waste some space here for the sake of HP compatibility. The
3685 first slot is only used when the frame pointer is needed. */
3686 if (size || frame_pointer_needed)
3687 size += STARTING_FRAME_OFFSET;
3689 /* If the current function calls __builtin_eh_return, then we need
3690 to allocate stack space for registers that will hold data for
3691 the exception handler. */
3692 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3696 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3698 size += i * UNITS_PER_WORD;
3701 /* Account for space used by the callee general register saves. */
3702 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3703 if (regs_ever_live[i])
3704 size += UNITS_PER_WORD;
3706 /* Account for space used by the callee floating point register saves. */
3707 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3708 if (regs_ever_live[i]
3709 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3713 /* We always save both halves of the FP register, so always
3714 increment the frame size by 8 bytes. */
3718 /* If any of the floating registers are saved, account for the
3719 alignment needed for the floating point register save block. */
3722 size = (size + 7) & ~7;
3727 /* The various ABIs include space for the outgoing parameters in the
3728 size of the current function's stack frame. We don't need to align
3729 for the outgoing arguments as their alignment is set by the final
3730 rounding for the frame as a whole. */
3731 size += current_function_outgoing_args_size;
3733 /* Allocate space for the fixed frame marker. This space must be
3734 allocated for any function that makes calls or allocates
3736 if (!current_function_is_leaf || size)
3737 size += TARGET_64BIT ? 48 : 32;
3739 /* Finally, round to the preferred stack boundary. */
3740 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3741 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3744 /* Generate the assembly code for function entry. FILE is a stdio
3745 stream to output the code to. SIZE is an int: how many units of
3746 temporary storage to allocate.
3748 Refer to the array `regs_ever_live' to determine which registers to
3749 save; `regs_ever_live[I]' is nonzero if register number I is ever
3750 used in the function. This function is responsible for knowing
3751 which registers should not be saved even if used. */
3753 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3754 of memory. If any fpu reg is used in the function, we allocate
3755 such a block here, at the bottom of the frame, just in case it's needed.
3757 If this function is a leaf procedure, then we may choose not
3758 to do a "save" insn. The decision about whether or not
3759 to do this is made in regclass.c. */
3762 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3764 /* The function's label and associated .PROC must never be
3765 separated and must be output *after* any profiling declarations
3766 to avoid changing spaces/subspaces within a procedure. */
3767 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3768 fputs ("\t.PROC\n", file);
3770 /* hppa_expand_prologue does the dirty work now. We just need
3771 to output the assembler directives which denote the start
3773 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3774 if (regs_ever_live[2])
3775 fputs (",CALLS,SAVE_RP", file);
3777 fputs (",NO_CALLS", file);
3779 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3780 at the beginning of the frame and that it is used as the frame
3781 pointer for the frame. We do this because our current frame
3782 layout doesn't conform to that specified in the the HP runtime
3783 documentation and we need a way to indicate to programs such as
3784 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3785 isn't used by HP compilers but is supported by the assembler.
3786 However, SAVE_SP is supposed to indicate that the previous stack
3787 pointer has been saved in the frame marker. */
3788 if (frame_pointer_needed)
3789 fputs (",SAVE_SP", file);
3791 /* Pass on information about the number of callee register saves
3792 performed in the prologue.
3794 The compiler is supposed to pass the highest register number
3795 saved, the assembler then has to adjust that number before
3796 entering it into the unwind descriptor (to account for any
3797 caller saved registers with lower register numbers than the
3798 first callee saved register). */
3800 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3803 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3805 fputs ("\n\t.ENTRY\n", file);
3807 remove_useless_addtr_insns (0);
3811 hppa_expand_prologue (void)
3813 int merge_sp_adjust_with_store = 0;
3814 HOST_WIDE_INT size = get_frame_size ();
3815 HOST_WIDE_INT offset;
3823 /* Compute total size for frame pointer, filler, locals and rounding to
3824 the next word boundary. Similar code appears in compute_frame_size
3825 and must be changed in tandem with this code. */
3826 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3827 if (local_fsize || frame_pointer_needed)
3828 local_fsize += STARTING_FRAME_OFFSET;
3830 actual_fsize = compute_frame_size (size, &save_fregs);
3832 /* Compute a few things we will use often. */
3833 tmpreg = gen_rtx_REG (word_mode, 1);
3835 /* Save RP first. The calling conventions manual states RP will
3836 always be stored into the caller's frame at sp - 20 or sp - 16
3837 depending on which ABI is in use. */
3838 if (regs_ever_live[2] || current_function_calls_eh_return)
3839 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3841 /* Allocate the local frame and set up the frame pointer if needed. */
3842 if (actual_fsize != 0)
3844 if (frame_pointer_needed)
3846 /* Copy the old frame pointer temporarily into %r1. Set up the
3847 new stack pointer, then store away the saved old frame pointer
3848 into the stack at sp and at the same time update the stack
3849 pointer by actual_fsize bytes. Two versions, first
3850 handles small (<8k) frames. The second handles large (>=8k)
3852 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3855 /* We need to record the frame pointer save here since the
3856 new frame pointer is set in the following insn. */
3857 RTX_FRAME_RELATED_P (insn) = 1;
3859 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3860 gen_rtx_SET (VOIDmode,
3861 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3866 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3868 RTX_FRAME_RELATED_P (insn) = 1;
3870 if (VAL_14_BITS_P (actual_fsize))
3871 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3874 /* It is incorrect to store the saved frame pointer at *sp,
3875 then increment sp (writes beyond the current stack boundary).
3877 So instead use stwm to store at *sp and post-increment the
3878 stack pointer as an atomic operation. Then increment sp to
3879 finish allocating the new frame. */
3880 HOST_WIDE_INT adjust1 = 8192 - 64;
3881 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3883 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3884 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3888 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3889 we need to store the previous stack pointer (frame pointer)
3890 into the frame marker on targets that use the HP unwind
3891 library. This allows the HP unwind library to be used to
3892 unwind GCC frames. However, we are not fully compatible
3893 with the HP library because our frame layout differs from
3894 that specified in the HP runtime specification.
3896 We don't want a frame note on this instruction as the frame
3897 marker moves during dynamic stack allocation.
3899 This instruction also serves as a blockage to prevent
3900 register spills from being scheduled before the stack
3901 pointer is raised. This is necessary as we store
3902 registers using the frame pointer as a base register,
3903 and the frame pointer is set before sp is raised. */
3904 if (TARGET_HPUX_UNWIND_LIBRARY)
3906 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3907 GEN_INT (TARGET_64BIT ? -8 : -4));
3909 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3913 emit_insn (gen_blockage ());
3915 /* no frame pointer needed. */
3918 /* In some cases we can perform the first callee register save
3919 and allocating the stack frame at the same time. If so, just
3920 make a note of it and defer allocating the frame until saving
3921 the callee registers. */
3922 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3923 merge_sp_adjust_with_store = 1;
3924 /* Can not optimize. Adjust the stack frame by actual_fsize
3927 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3932 /* Normal register save.
3934 Do not save the frame pointer in the frame_pointer_needed case. It
3935 was done earlier. */
3936 if (frame_pointer_needed)
3938 offset = local_fsize;
3940 /* Saving the EH return data registers in the frame is the simplest
3941 way to get the frame unwind information emitted. We put them
3942 just before the general registers. */
3943 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3945 unsigned int i, regno;
3949 regno = EH_RETURN_DATA_REGNO (i);
3950 if (regno == INVALID_REGNUM)
3953 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3954 offset += UNITS_PER_WORD;
3958 for (i = 18; i >= 4; i--)
3959 if (regs_ever_live[i] && ! call_used_regs[i])
3961 store_reg (i, offset, FRAME_POINTER_REGNUM);
3962 offset += UNITS_PER_WORD;
3965 /* Account for %r3 which is saved in a special place. */
3968 /* No frame pointer needed. */
3971 offset = local_fsize - actual_fsize;
3973 /* Saving the EH return data registers in the frame is the simplest
3974 way to get the frame unwind information emitted. */
3975 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3977 unsigned int i, regno;
3981 regno = EH_RETURN_DATA_REGNO (i);
3982 if (regno == INVALID_REGNUM)
3985 /* If merge_sp_adjust_with_store is nonzero, then we can
3986 optimize the first save. */
3987 if (merge_sp_adjust_with_store)
3989 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3990 merge_sp_adjust_with_store = 0;
3993 store_reg (regno, offset, STACK_POINTER_REGNUM);
3994 offset += UNITS_PER_WORD;
3998 for (i = 18; i >= 3; i--)
3999 if (regs_ever_live[i] && ! call_used_regs[i])
4001 /* If merge_sp_adjust_with_store is nonzero, then we can
4002 optimize the first GR save. */
4003 if (merge_sp_adjust_with_store)
4005 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
4006 merge_sp_adjust_with_store = 0;
4009 store_reg (i, offset, STACK_POINTER_REGNUM);
4010 offset += UNITS_PER_WORD;
4014 /* If we wanted to merge the SP adjustment with a GR save, but we never
4015 did any GR saves, then just emit the adjustment here. */
4016 if (merge_sp_adjust_with_store)
4017 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4021 /* The hppa calling conventions say that %r19, the pic offset
4022 register, is saved at sp - 32 (in this function's frame)
4023 when generating PIC code. FIXME: What is the correct thing
4024 to do for functions which make no calls and allocate no
4025 frame? Do we need to allocate a frame, or can we just omit
4026 the save? For now we'll just omit the save.
4028 We don't want a note on this insn as the frame marker can
4029 move if there is a dynamic stack allocation. */
4030 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
4032 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
4034 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
4038 /* Align pointer properly (doubleword boundary). */
4039 offset = (offset + 7) & ~7;
4041 /* Floating point register store. */
4046 /* First get the frame or stack pointer to the start of the FP register
4048 if (frame_pointer_needed)
4050 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4051 base = frame_pointer_rtx;
4055 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4056 base = stack_pointer_rtx;
4059 /* Now actually save the FP registers. */
4060 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4062 if (regs_ever_live[i]
4063 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4065 rtx addr, insn, reg;
4066 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4067 reg = gen_rtx_REG (DFmode, i);
4068 insn = emit_move_insn (addr, reg);
4071 RTX_FRAME_RELATED_P (insn) = 1;
4074 rtx mem = gen_rtx_MEM (DFmode,
4075 plus_constant (base, offset));
4077 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4078 gen_rtx_SET (VOIDmode, mem, reg),
4083 rtx meml = gen_rtx_MEM (SFmode,
4084 plus_constant (base, offset));
4085 rtx memr = gen_rtx_MEM (SFmode,
4086 plus_constant (base, offset + 4));
4087 rtx regl = gen_rtx_REG (SFmode, i);
4088 rtx regr = gen_rtx_REG (SFmode, i + 1);
4089 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4090 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4093 RTX_FRAME_RELATED_P (setl) = 1;
4094 RTX_FRAME_RELATED_P (setr) = 1;
4095 vec = gen_rtvec (2, setl, setr);
4097 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4098 gen_rtx_SEQUENCE (VOIDmode, vec),
4102 offset += GET_MODE_SIZE (DFmode);
4109 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4110 Handle case where DISP > 8k by using the add_high_const patterns. */
4113 load_reg (int reg, HOST_WIDE_INT disp, int base)
4115 rtx dest = gen_rtx_REG (word_mode, reg);
4116 rtx basereg = gen_rtx_REG (Pmode, base);
4119 if (VAL_14_BITS_P (disp))
4120 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4121 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4123 rtx delta = GEN_INT (disp);
4124 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4126 emit_move_insn (tmpreg, delta);
4127 if (TARGET_DISABLE_INDEXING)
4129 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4130 src = gen_rtx_MEM (word_mode, tmpreg);
4133 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4137 rtx delta = GEN_INT (disp);
4138 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4139 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4141 emit_move_insn (tmpreg, high);
4142 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4145 emit_move_insn (dest, src);
4148 /* Update the total code bytes output to the text section. */
4151 update_total_code_bytes (int nbytes)
4153 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4154 && !IN_NAMED_SECTION_P (cfun->decl))
4156 if (INSN_ADDRESSES_SET_P ())
4158 unsigned long old_total = total_code_bytes;
4160 total_code_bytes += nbytes;
4162 /* Be prepared to handle overflows. */
4163 if (old_total > total_code_bytes)
4164 total_code_bytes = -1;
4167 total_code_bytes = -1;
4171 /* This function generates the assembly code for function exit.
4172 Args are as for output_function_prologue ().
4174 The function epilogue should not depend on the current stack
4175 pointer! It should use the frame pointer only. This is mandatory
4176 because of alloca; we also take advantage of it to omit stack
4177 adjustments before returning. */
4180 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4182 rtx insn = get_last_insn ();
4186 /* hppa_expand_epilogue does the dirty work now. We just need
4187 to output the assembler directives which denote the end
4190 To make debuggers happy, emit a nop if the epilogue was completely
4191 eliminated due to a volatile call as the last insn in the
4192 current function. That way the return address (in %r2) will
4193 always point to a valid instruction in the current function. */
4195 /* Get the last real insn. */
4196 if (GET_CODE (insn) == NOTE)
4197 insn = prev_real_insn (insn);
4199 /* If it is a sequence, then look inside. */
4200 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4201 insn = XVECEXP (PATTERN (insn), 0, 0);
4203 /* If insn is a CALL_INSN, then it must be a call to a volatile
4204 function (otherwise there would be epilogue insns). */
4205 if (insn && GET_CODE (insn) == CALL_INSN)
4207 fputs ("\tnop\n", file);
4211 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4213 if (INSN_ADDRESSES_SET_P ())
4215 insn = get_last_nonnote_insn ();
4216 last_address += INSN_ADDRESSES (INSN_UID (insn));
4218 last_address += insn_default_length (insn);
4219 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4220 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4223 /* Finally, update the total number of code bytes output so far. */
4224 update_total_code_bytes (last_address);
4228 hppa_expand_epilogue (void)
4231 HOST_WIDE_INT offset;
4232 HOST_WIDE_INT ret_off = 0;
4234 int merge_sp_adjust_with_load = 0;
4236 /* We will use this often. */
4237 tmpreg = gen_rtx_REG (word_mode, 1);
4239 /* Try to restore RP early to avoid load/use interlocks when
4240 RP gets used in the return (bv) instruction. This appears to still
4241 be necessary even when we schedule the prologue and epilogue. */
4242 if (regs_ever_live [2] || current_function_calls_eh_return)
4244 ret_off = TARGET_64BIT ? -16 : -20;
4245 if (frame_pointer_needed)
4247 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4252 /* No frame pointer, and stack is smaller than 8k. */
4253 if (VAL_14_BITS_P (ret_off - actual_fsize))
4255 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4261 /* General register restores. */
4262 if (frame_pointer_needed)
4264 offset = local_fsize;
4266 /* If the current function calls __builtin_eh_return, then we need
4267 to restore the saved EH data registers. */
4268 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4270 unsigned int i, regno;
4274 regno = EH_RETURN_DATA_REGNO (i);
4275 if (regno == INVALID_REGNUM)
4278 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4279 offset += UNITS_PER_WORD;
4283 for (i = 18; i >= 4; i--)
4284 if (regs_ever_live[i] && ! call_used_regs[i])
4286 load_reg (i, offset, FRAME_POINTER_REGNUM);
4287 offset += UNITS_PER_WORD;
4292 offset = local_fsize - actual_fsize;
4294 /* If the current function calls __builtin_eh_return, then we need
4295 to restore the saved EH data registers. */
4296 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4298 unsigned int i, regno;
4302 regno = EH_RETURN_DATA_REGNO (i);
4303 if (regno == INVALID_REGNUM)
4306 /* Only for the first load.
4307 merge_sp_adjust_with_load holds the register load
4308 with which we will merge the sp adjustment. */
4309 if (merge_sp_adjust_with_load == 0
4311 && VAL_14_BITS_P (-actual_fsize))
4312 merge_sp_adjust_with_load = regno;
4314 load_reg (regno, offset, STACK_POINTER_REGNUM);
4315 offset += UNITS_PER_WORD;
4319 for (i = 18; i >= 3; i--)
4321 if (regs_ever_live[i] && ! call_used_regs[i])
4323 /* Only for the first load.
4324 merge_sp_adjust_with_load holds the register load
4325 with which we will merge the sp adjustment. */
4326 if (merge_sp_adjust_with_load == 0
4328 && VAL_14_BITS_P (-actual_fsize))
4329 merge_sp_adjust_with_load = i;
4331 load_reg (i, offset, STACK_POINTER_REGNUM);
4332 offset += UNITS_PER_WORD;
4337 /* Align pointer properly (doubleword boundary). */
4338 offset = (offset + 7) & ~7;
4340 /* FP register restores. */
4343 /* Adjust the register to index off of. */
4344 if (frame_pointer_needed)
4345 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4347 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4349 /* Actually do the restores now. */
4350 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4351 if (regs_ever_live[i]
4352 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4354 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4355 rtx dest = gen_rtx_REG (DFmode, i);
4356 emit_move_insn (dest, src);
4360 /* Emit a blockage insn here to keep these insns from being moved to
4361 an earlier spot in the epilogue, or into the main instruction stream.
4363 This is necessary as we must not cut the stack back before all the
4364 restores are finished. */
4365 emit_insn (gen_blockage ());
4367 /* Reset stack pointer (and possibly frame pointer). The stack
4368 pointer is initially set to fp + 64 to avoid a race condition. */
4369 if (frame_pointer_needed)
4371 rtx delta = GEN_INT (-64);
4373 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4374 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4376 /* If we were deferring a callee register restore, do it now. */
4377 else if (merge_sp_adjust_with_load)
4379 rtx delta = GEN_INT (-actual_fsize);
4380 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4382 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4384 else if (actual_fsize != 0)
4385 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4388 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4389 frame greater than 8k), do so now. */
4391 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4393 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4395 rtx sa = EH_RETURN_STACKADJ_RTX;
4397 emit_insn (gen_blockage ());
4398 emit_insn (TARGET_64BIT
4399 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4400 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4405 hppa_pic_save_rtx (void)
4407 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4411 hppa_profile_hook (int label_no)
4413 /* We use SImode for the address of the function in both 32 and
4414 64-bit code to avoid having to provide DImode versions of the
4415 lcla2 and load_offset_label_address insn patterns. */
4416 rtx reg = gen_reg_rtx (SImode);
4417 rtx label_rtx = gen_label_rtx ();
4418 rtx begin_label_rtx, call_insn;
4419 char begin_label_name[16];
4421 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4423 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4426 emit_move_insn (arg_pointer_rtx,
4427 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4430 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4432 /* The address of the function is loaded into %r25 with a instruction-
4433 relative sequence that avoids the use of relocations. The sequence
4434 is split so that the load_offset_label_address instruction can
4435 occupy the delay slot of the call to _mcount. */
4437 emit_insn (gen_lcla2 (reg, label_rtx));
4439 emit_insn (gen_lcla1 (reg, label_rtx));
4441 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4442 reg, begin_label_rtx, label_rtx));
4444 #ifndef NO_PROFILE_COUNTERS
4446 rtx count_label_rtx, addr, r24;
4447 char count_label_name[16];
4449 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4450 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4452 addr = force_reg (Pmode, count_label_rtx);
4453 r24 = gen_rtx_REG (Pmode, 24);
4454 emit_move_insn (r24, addr);
4457 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4458 gen_rtx_SYMBOL_REF (Pmode,
4460 GEN_INT (TARGET_64BIT ? 24 : 12)));
4462 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4467 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4468 gen_rtx_SYMBOL_REF (Pmode,
4470 GEN_INT (TARGET_64BIT ? 16 : 8)));
4474 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4475 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4477 /* Indicate the _mcount call cannot throw, nor will it execute a
4479 REG_NOTES (call_insn)
4480 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4483 /* Fetch the return address for the frame COUNT steps up from
4484 the current frame, after the prologue. FRAMEADDR is the
4485 frame pointer of the COUNT frame.
4487 We want to ignore any export stub remnants here. To handle this,
4488 we examine the code at the return address, and if it is an export
4489 stub, we return a memory rtx for the stub return address stored
4492 The value returned is used in two different ways:
4494 1. To find a function's caller.
4496 2. To change the return address for a function.
4498 This function handles most instances of case 1; however, it will
4499 fail if there are two levels of stubs to execute on the return
4500 path. The only way I believe that can happen is if the return value
4501 needs a parameter relocation, which never happens for C code.
4503 This function handles most instances of case 2; however, it will
4504 fail if we did not originally have stub code on the return path
4505 but will need stub code on the new return path. This can happen if
4506 the caller & callee are both in the main program, but the new
4507 return location is in a shared library. */
4510 return_addr_rtx (int count, rtx frameaddr)
4520 rp = get_hard_reg_initial_val (Pmode, 2);
4522 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4525 saved_rp = gen_reg_rtx (Pmode);
4526 emit_move_insn (saved_rp, rp);
4528 /* Get pointer to the instruction stream. We have to mask out the
4529 privilege level from the two low order bits of the return address
4530 pointer here so that ins will point to the start of the first
4531 instruction that would have been executed if we returned. */
4532 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4533 label = gen_label_rtx ();
4535 /* Check the instruction stream at the normal return address for the
4538 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4539 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4540 0x00011820 | stub+16: mtsp r1,sr0
4541 0xe0400002 | stub+20: be,n 0(sr0,rp)
4543 If it is an export stub, than our return address is really in
4546 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4547 NULL_RTX, SImode, 1);
4548 emit_jump_insn (gen_bne (label));
4550 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4551 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4552 emit_jump_insn (gen_bne (label));
4554 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4555 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4556 emit_jump_insn (gen_bne (label));
4558 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4559 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4561 /* If there is no export stub then just use the value saved from
4562 the return pointer register. */
4564 emit_jump_insn (gen_bne (label));
4566 /* Here we know that our return address points to an export
4567 stub. We don't want to return the address of the export stub,
4568 but rather the return address of the export stub. That return
4569 address is stored at -24[frameaddr]. */
4571 emit_move_insn (saved_rp,
4573 memory_address (Pmode,
4574 plus_constant (frameaddr,
4581 /* This is only valid once reload has completed because it depends on
4582 knowing exactly how much (if any) frame there is and...
4584 It's only valid if there is no frame marker to de-allocate and...
4586 It's only valid if %r2 hasn't been saved into the caller's frame
4587 (we're not profiling and %r2 isn't live anywhere). */
4589 hppa_can_use_return_insn_p (void)
4591 return (reload_completed
4592 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4593 && ! regs_ever_live[2]
4594 && ! frame_pointer_needed);
4598 emit_bcond_fp (enum rtx_code code, rtx operand0)
4600 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4601 gen_rtx_IF_THEN_ELSE (VOIDmode,
4602 gen_rtx_fmt_ee (code,
4604 gen_rtx_REG (CCFPmode, 0),
4606 gen_rtx_LABEL_REF (VOIDmode, operand0),
4612 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4614 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4615 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4618 /* Adjust the cost of a scheduling dependency. Return the new cost of
4619 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4622 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4624 enum attr_type attr_type;
4626 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4627 true dependencies as they are described with bypasses now. */
4628 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4631 if (! recog_memoized (insn))
4634 attr_type = get_attr_type (insn);
4636 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4638 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4641 if (attr_type == TYPE_FPLOAD)
4643 rtx pat = PATTERN (insn);
4644 rtx dep_pat = PATTERN (dep_insn);
4645 if (GET_CODE (pat) == PARALLEL)
4647 /* This happens for the fldXs,mb patterns. */
4648 pat = XVECEXP (pat, 0, 0);
4650 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4651 /* If this happens, we have to extend this to schedule
4652 optimally. Return 0 for now. */
4655 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4657 if (! recog_memoized (dep_insn))
4659 switch (get_attr_type (dep_insn))
4666 case TYPE_FPSQRTSGL:
4667 case TYPE_FPSQRTDBL:
4668 /* A fpload can't be issued until one cycle before a
4669 preceding arithmetic operation has finished if
4670 the target of the fpload is any of the sources
4671 (or destination) of the arithmetic operation. */
4672 return insn_default_latency (dep_insn) - 1;
4679 else if (attr_type == TYPE_FPALU)
4681 rtx pat = PATTERN (insn);
4682 rtx dep_pat = PATTERN (dep_insn);
4683 if (GET_CODE (pat) == PARALLEL)
4685 /* This happens for the fldXs,mb patterns. */
4686 pat = XVECEXP (pat, 0, 0);
4688 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4689 /* If this happens, we have to extend this to schedule
4690 optimally. Return 0 for now. */
4693 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4695 if (! recog_memoized (dep_insn))
4697 switch (get_attr_type (dep_insn))
4701 case TYPE_FPSQRTSGL:
4702 case TYPE_FPSQRTDBL:
4703 /* An ALU flop can't be issued until two cycles before a
4704 preceding divide or sqrt operation has finished if
4705 the target of the ALU flop is any of the sources
4706 (or destination) of the divide or sqrt operation. */
4707 return insn_default_latency (dep_insn) - 2;
4715 /* For other anti dependencies, the cost is 0. */
4718 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4720 /* Output dependency; DEP_INSN writes a register that INSN writes some
4722 if (attr_type == TYPE_FPLOAD)
4724 rtx pat = PATTERN (insn);
4725 rtx dep_pat = PATTERN (dep_insn);
4726 if (GET_CODE (pat) == PARALLEL)
4728 /* This happens for the fldXs,mb patterns. */
4729 pat = XVECEXP (pat, 0, 0);
4731 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4732 /* If this happens, we have to extend this to schedule
4733 optimally. Return 0 for now. */
4736 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4738 if (! recog_memoized (dep_insn))
4740 switch (get_attr_type (dep_insn))
4747 case TYPE_FPSQRTSGL:
4748 case TYPE_FPSQRTDBL:
4749 /* A fpload can't be issued until one cycle before a
4750 preceding arithmetic operation has finished if
4751 the target of the fpload is the destination of the
4752 arithmetic operation.
4754 Exception: For PA7100LC, PA7200 and PA7300, the cost
4755 is 3 cycles, unless they bundle together. We also
4756 pay the penalty if the second insn is a fpload. */
4757 return insn_default_latency (dep_insn) - 1;
4764 else if (attr_type == TYPE_FPALU)
4766 rtx pat = PATTERN (insn);
4767 rtx dep_pat = PATTERN (dep_insn);
4768 if (GET_CODE (pat) == PARALLEL)
4770 /* This happens for the fldXs,mb patterns. */
4771 pat = XVECEXP (pat, 0, 0);
4773 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4774 /* If this happens, we have to extend this to schedule
4775 optimally. Return 0 for now. */
4778 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4780 if (! recog_memoized (dep_insn))
4782 switch (get_attr_type (dep_insn))
4786 case TYPE_FPSQRTSGL:
4787 case TYPE_FPSQRTDBL:
4788 /* An ALU flop can't be issued until two cycles before a
4789 preceding divide or sqrt operation has finished if
4790 the target of the ALU flop is also the target of
4791 the divide or sqrt operation. */
4792 return insn_default_latency (dep_insn) - 2;
4800 /* For other output dependencies, the cost is 0. */
4807 /* Adjust scheduling priorities. We use this to try and keep addil
4808 and the next use of %r1 close together. */
4810 pa_adjust_priority (rtx insn, int priority)
4812 rtx set = single_set (insn);
4816 src = SET_SRC (set);
4817 dest = SET_DEST (set);
4818 if (GET_CODE (src) == LO_SUM
4819 && symbolic_operand (XEXP (src, 1), VOIDmode)
4820 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4823 else if (GET_CODE (src) == MEM
4824 && GET_CODE (XEXP (src, 0)) == LO_SUM
4825 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4826 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4829 else if (GET_CODE (dest) == MEM
4830 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4831 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4832 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4838 /* The 700 can only issue a single insn at a time.
4839 The 7XXX processors can issue two insns at a time.
4840 The 8000 can issue 4 insns at a time. */
4842 pa_issue_rate (void)
4846 case PROCESSOR_700: return 1;
4847 case PROCESSOR_7100: return 2;
4848 case PROCESSOR_7100LC: return 2;
4849 case PROCESSOR_7200: return 2;
4850 case PROCESSOR_7300: return 2;
4851 case PROCESSOR_8000: return 4;
4860 /* Return any length adjustment needed by INSN which already has its length
4861 computed as LENGTH. Return zero if no adjustment is necessary.
4863 For the PA: function calls, millicode calls, and backwards short
4864 conditional branches with unfilled delay slots need an adjustment by +1
4865 (to account for the NOP which will be inserted into the instruction stream).
4867 Also compute the length of an inline block move here as it is too
4868 complicated to express as a length attribute in pa.md. */
4870 pa_adjust_insn_length (rtx insn, int length)
4872 rtx pat = PATTERN (insn);
4874 /* Jumps inside switch tables which have unfilled delay slots need
4876 if (GET_CODE (insn) == JUMP_INSN
4877 && GET_CODE (pat) == PARALLEL
4878 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4880 /* Millicode insn with an unfilled delay slot. */
4881 else if (GET_CODE (insn) == INSN
4882 && GET_CODE (pat) != SEQUENCE
4883 && GET_CODE (pat) != USE
4884 && GET_CODE (pat) != CLOBBER
4885 && get_attr_type (insn) == TYPE_MILLI)
4887 /* Block move pattern. */
4888 else if (GET_CODE (insn) == INSN
4889 && GET_CODE (pat) == PARALLEL
4890 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4891 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4892 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4893 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4894 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4895 return compute_movmem_length (insn) - 4;
4896 /* Block clear pattern. */
4897 else if (GET_CODE (insn) == INSN
4898 && GET_CODE (pat) == PARALLEL
4899 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4900 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4901 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4902 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4903 return compute_clrmem_length (insn) - 4;
4904 /* Conditional branch with an unfilled delay slot. */
4905 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4907 /* Adjust a short backwards conditional with an unfilled delay slot. */
4908 if (GET_CODE (pat) == SET
4910 && ! forward_branch_p (insn))
4912 else if (GET_CODE (pat) == PARALLEL
4913 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4916 /* Adjust dbra insn with short backwards conditional branch with
4917 unfilled delay slot -- only for case where counter is in a
4918 general register register. */
4919 else if (GET_CODE (pat) == PARALLEL
4920 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4921 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4922 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4924 && ! forward_branch_p (insn))
4932 /* Print operand X (an rtx) in assembler syntax to file FILE.
4933 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4934 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4937 print_operand (FILE *file, rtx x, int code)
4942 /* Output a 'nop' if there's nothing for the delay slot. */
4943 if (dbr_sequence_length () == 0)
4944 fputs ("\n\tnop", file);
4947 /* Output a nullification completer if there's nothing for the */
4948 /* delay slot or nullification is requested. */
4949 if (dbr_sequence_length () == 0 ||
4951 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4955 /* Print out the second register name of a register pair.
4956 I.e., R (6) => 7. */
4957 fputs (reg_names[REGNO (x) + 1], file);
4960 /* A register or zero. */
4962 || (x == CONST0_RTX (DFmode))
4963 || (x == CONST0_RTX (SFmode)))
4965 fputs ("%r0", file);
4971 /* A register or zero (floating point). */
4973 || (x == CONST0_RTX (DFmode))
4974 || (x == CONST0_RTX (SFmode)))
4976 fputs ("%fr0", file);
4985 xoperands[0] = XEXP (XEXP (x, 0), 0);
4986 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4987 output_global_address (file, xoperands[1], 0);
4988 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4992 case 'C': /* Plain (C)ondition */
4994 switch (GET_CODE (x))
4997 fputs ("=", file); break;
4999 fputs ("<>", file); break;
5001 fputs (">", file); break;
5003 fputs (">=", file); break;
5005 fputs (">>=", file); break;
5007 fputs (">>", file); break;
5009 fputs ("<", file); break;
5011 fputs ("<=", file); break;
5013 fputs ("<<=", file); break;
5015 fputs ("<<", file); break;
5020 case 'N': /* Condition, (N)egated */
5021 switch (GET_CODE (x))
5024 fputs ("<>", file); break;
5026 fputs ("=", file); break;
5028 fputs ("<=", file); break;
5030 fputs ("<", file); break;
5032 fputs ("<<", file); break;
5034 fputs ("<<=", file); break;
5036 fputs (">=", file); break;
5038 fputs (">", file); break;
5040 fputs (">>", file); break;
5042 fputs (">>=", file); break;
5047 /* For floating point comparisons. Note that the output
5048 predicates are the complement of the desired mode. */
5050 switch (GET_CODE (x))
5053 fputs ("!=", file); break;
5055 fputs ("=", file); break;
5057 fputs ("!>", file); break;
5059 fputs ("!>=", file); break;
5061 fputs ("!<", file); break;
5063 fputs ("!<=", file); break;
5065 fputs ("!<>", file); break;
5067 fputs (">", file); break;
5069 fputs (">=", file); break;
5071 fputs ("<", file); break;
5073 fputs ("<=", file); break;
5075 fputs ("<>", file); break;
5077 fputs ("<=>", file); break;
5079 fputs ("!<=>", file); break;
5084 case 'S': /* Condition, operands are (S)wapped. */
5085 switch (GET_CODE (x))
5088 fputs ("=", file); break;
5090 fputs ("<>", file); break;
5092 fputs ("<", file); break;
5094 fputs ("<=", file); break;
5096 fputs ("<<=", file); break;
5098 fputs ("<<", file); break;
5100 fputs (">", file); break;
5102 fputs (">=", file); break;
5104 fputs (">>=", file); break;
5106 fputs (">>", file); break;
5111 case 'B': /* Condition, (B)oth swapped and negate. */
5112 switch (GET_CODE (x))
5115 fputs ("<>", file); break;
5117 fputs ("=", file); break;
5119 fputs (">=", file); break;
5121 fputs (">", file); break;
5123 fputs (">>", file); break;
5125 fputs (">>=", file); break;
5127 fputs ("<=", file); break;
5129 fputs ("<", file); break;
5131 fputs ("<<", file); break;
5133 fputs ("<<=", file); break;
5139 if (GET_CODE (x) == CONST_INT)
5141 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5146 if (GET_CODE (x) == CONST_INT)
5148 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5153 if (GET_CODE (x) == CONST_INT)
5155 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5160 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5162 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5167 if (GET_CODE (x) == CONST_INT)
5169 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5174 if (GET_CODE (x) == CONST_INT)
5176 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5181 if (GET_CODE (x) == CONST_INT)
5186 switch (GET_CODE (XEXP (x, 0)))
5190 if (ASSEMBLER_DIALECT == 0)
5191 fputs ("s,mb", file);
5193 fputs (",mb", file);
5197 if (ASSEMBLER_DIALECT == 0)
5198 fputs ("s,ma", file);
5200 fputs (",ma", file);
5203 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5204 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5206 if (ASSEMBLER_DIALECT == 0)
5209 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5210 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5212 if (ASSEMBLER_DIALECT == 0)
5213 fputs ("x,s", file);
5217 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5221 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5227 output_global_address (file, x, 0);
5230 output_global_address (file, x, 1);
5232 case 0: /* Don't do anything special */
5237 compute_zdepwi_operands (INTVAL (x), op);
5238 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5244 compute_zdepdi_operands (INTVAL (x), op);
5245 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5249 /* We can get here from a .vtable_inherit due to our
5250 CONSTANT_ADDRESS_P rejecting perfectly good constant
5256 if (GET_CODE (x) == REG)
5258 fputs (reg_names [REGNO (x)], file);
5259 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5265 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5266 && (REGNO (x) & 1) == 0)
5269 else if (GET_CODE (x) == MEM)
5271 int size = GET_MODE_SIZE (GET_MODE (x));
5272 rtx base = NULL_RTX;
5273 switch (GET_CODE (XEXP (x, 0)))
5277 base = XEXP (XEXP (x, 0), 0);
5278 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5282 base = XEXP (XEXP (x, 0), 0);
5283 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5286 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5287 fprintf (file, "%s(%s)",
5288 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5289 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5290 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5291 fprintf (file, "%s(%s)",
5292 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5293 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5294 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5295 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5297 /* Because the REG_POINTER flag can get lost during reload,
5298 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5299 index and base registers in the combined move patterns. */
5300 rtx base = XEXP (XEXP (x, 0), 1);
5301 rtx index = XEXP (XEXP (x, 0), 0);
5303 fprintf (file, "%s(%s)",
5304 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5307 output_address (XEXP (x, 0));
5310 output_address (XEXP (x, 0));
5315 output_addr_const (file, x);
5318 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5321 output_global_address (FILE *file, rtx x, int round_constant)
5324 /* Imagine (high (const (plus ...))). */
5325 if (GET_CODE (x) == HIGH)
5328 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5329 assemble_name (file, XSTR (x, 0));
5330 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5332 assemble_name (file, XSTR (x, 0));
5333 fputs ("-$global$", file);
5335 else if (GET_CODE (x) == CONST)
5337 const char *sep = "";
5338 int offset = 0; /* assembler wants -$global$ at end */
5339 rtx base = NULL_RTX;
5341 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5343 base = XEXP (XEXP (x, 0), 0);
5344 output_addr_const (file, base);
5346 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5347 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5350 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5352 base = XEXP (XEXP (x, 0), 1);
5353 output_addr_const (file, base);
5355 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5356 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5359 /* How bogus. The compiler is apparently responsible for
5360 rounding the constant if it uses an LR field selector.
5362 The linker and/or assembler seem a better place since
5363 they have to do this kind of thing already.
5365 If we fail to do this, HP's optimizing linker may eliminate
5366 an addil, but not update the ldw/stw/ldo instruction that
5367 uses the result of the addil. */
5369 offset = ((offset + 0x1000) & ~0x1fff);
5371 if (GET_CODE (XEXP (x, 0)) == PLUS)
5381 else if (GET_CODE (XEXP (x, 0)) == MINUS
5382 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5386 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5387 fputs ("-$global$", file);
5389 fprintf (file, "%s%d", sep, offset);
5392 output_addr_const (file, x);
5395 /* Output boilerplate text to appear at the beginning of the file.
5396 There are several possible versions. */
5397 #define aputs(x) fputs(x, asm_out_file)
5399 pa_file_start_level (void)
5402 aputs ("\t.LEVEL 2.0w\n");
5403 else if (TARGET_PA_20)
5404 aputs ("\t.LEVEL 2.0\n");
5405 else if (TARGET_PA_11)
5406 aputs ("\t.LEVEL 1.1\n");
5408 aputs ("\t.LEVEL 1.0\n");
5412 pa_file_start_space (int sortspace)
5414 aputs ("\t.SPACE $PRIVATE$");
5417 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5418 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5419 "\n\t.SPACE $TEXT$");
5422 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5423 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5427 pa_file_start_file (int want_version)
5429 if (write_symbols != NO_DEBUG)
5431 output_file_directive (asm_out_file, main_input_filename);
5433 aputs ("\t.version\t\"01.01\"\n");
5438 pa_file_start_mcount (const char *aswhat)
5441 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5445 pa_elf_file_start (void)
5447 pa_file_start_level ();
5448 pa_file_start_mcount ("ENTRY");
5449 pa_file_start_file (0);
5453 pa_som_file_start (void)
5455 pa_file_start_level ();
5456 pa_file_start_space (0);
5457 aputs ("\t.IMPORT $global$,DATA\n"
5458 "\t.IMPORT $$dyncall,MILLICODE\n");
5459 pa_file_start_mcount ("CODE");
5460 pa_file_start_file (0);
5464 pa_linux_file_start (void)
5466 pa_file_start_file (1);
5467 pa_file_start_level ();
5468 pa_file_start_mcount ("CODE");
5472 pa_hpux64_gas_file_start (void)
5474 pa_file_start_level ();
5475 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5477 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5479 pa_file_start_file (1);
5483 pa_hpux64_hpas_file_start (void)
5485 pa_file_start_level ();
5486 pa_file_start_space (1);
5487 pa_file_start_mcount ("CODE");
5488 pa_file_start_file (0);
5492 static struct deferred_plabel *
5493 get_plabel (const char *fname)
5497 /* See if we have already put this function on the list of deferred
5498 plabels. This list is generally small, so a liner search is not
5499 too ugly. If it proves too slow replace it with something faster. */
5500 for (i = 0; i < n_deferred_plabels; i++)
5501 if (strcmp (fname, deferred_plabels[i].name) == 0)
5504 /* If the deferred plabel list is empty, or this entry was not found
5505 on the list, create a new entry on the list. */
5506 if (deferred_plabels == NULL || i == n_deferred_plabels)
5508 const char *real_name;
5510 if (deferred_plabels == 0)
5511 deferred_plabels = (struct deferred_plabel *)
5512 ggc_alloc (sizeof (struct deferred_plabel));
5514 deferred_plabels = (struct deferred_plabel *)
5515 ggc_realloc (deferred_plabels,
5516 ((n_deferred_plabels + 1)
5517 * sizeof (struct deferred_plabel)));
5519 i = n_deferred_plabels++;
5520 deferred_plabels[i].internal_label = gen_label_rtx ();
5521 deferred_plabels[i].name = ggc_strdup (fname);
5523 /* Gross. We have just implicitly taken the address of this function,
5525 real_name = (*targetm.strip_name_encoding) (fname);
5526 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5529 return &deferred_plabels[i];
5533 output_deferred_plabels (void)
5536 /* If we have deferred plabels, then we need to switch into the data
5537 section and align it to a 4 byte boundary before we output the
5538 deferred plabels. */
5539 if (n_deferred_plabels)
5542 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5545 /* Now output the deferred plabels. */
5546 for (i = 0; i < n_deferred_plabels; i++)
5548 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5549 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5550 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5551 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5555 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5556 /* Initialize optabs to point to HPUX long double emulation routines. */
5558 pa_hpux_init_libfuncs (void)
5560 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5561 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5562 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5563 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5564 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5565 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5566 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5567 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5568 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5570 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5571 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5572 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5573 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5574 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5575 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5576 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5578 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5579 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5580 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5581 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5583 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5584 ? "__U_Qfcnvfxt_quad_to_sgl"
5585 : "_U_Qfcnvfxt_quad_to_sgl");
5586 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5587 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5588 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5590 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5591 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5595 /* HP's millicode routines mean something special to the assembler.
5596 Keep track of which ones we have used. */
5598 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5599 static void import_milli (enum millicodes);
5600 static char imported[(int) end1000];
5601 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5602 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5603 #define MILLI_START 10
5606 import_milli (enum millicodes code)
5608 char str[sizeof (import_string)];
5610 if (!imported[(int) code])
5612 imported[(int) code] = 1;
5613 strcpy (str, import_string);
5614 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5615 output_asm_insn (str, 0);
5619 /* The register constraints have put the operands and return value in
5620 the proper registers. */
5623 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5625 import_milli (mulI);
5626 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5629 /* Emit the rtl for doing a division by a constant. */
5631 /* Do magic division millicodes exist for this value? */
5632 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5635 /* We'll use an array to keep track of the magic millicodes and
5636 whether or not we've used them already. [n][0] is signed, [n][1] is
5639 static int div_milli[16][2];
5642 div_operand (rtx op, enum machine_mode mode)
5644 return (mode == SImode
5645 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5646 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5647 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5651 emit_hpdiv_const (rtx *operands, int unsignedp)
5653 if (GET_CODE (operands[2]) == CONST_INT
5654 && INTVAL (operands[2]) > 0
5655 && INTVAL (operands[2]) < 16
5656 && magic_milli[INTVAL (operands[2])])
5658 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5660 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5664 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5665 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5667 gen_rtx_REG (SImode, 26),
5669 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5670 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5671 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5672 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5673 gen_rtx_CLOBBER (VOIDmode, ret))));
5674 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5681 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5685 /* If the divisor is a constant, try to use one of the special
5687 if (GET_CODE (operands[0]) == CONST_INT)
5689 static char buf[100];
5690 divisor = INTVAL (operands[0]);
5691 if (!div_milli[divisor][unsignedp])
5693 div_milli[divisor][unsignedp] = 1;
5695 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5697 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5701 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5702 INTVAL (operands[0]));
5703 return output_millicode_call (insn,
5704 gen_rtx_SYMBOL_REF (SImode, buf));
5708 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5709 INTVAL (operands[0]));
5710 return output_millicode_call (insn,
5711 gen_rtx_SYMBOL_REF (SImode, buf));
5714 /* Divisor isn't a special constant. */
5719 import_milli (divU);
5720 return output_millicode_call (insn,
5721 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5725 import_milli (divI);
5726 return output_millicode_call (insn,
5727 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5732 /* Output a $$rem millicode to do mod. */
5735 output_mod_insn (int unsignedp, rtx insn)
5739 import_milli (remU);
5740 return output_millicode_call (insn,
5741 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5745 import_milli (remI);
5746 return output_millicode_call (insn,
5747 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5752 output_arg_descriptor (rtx call_insn)
5754 const char *arg_regs[4];
5755 enum machine_mode arg_mode;
5757 int i, output_flag = 0;
5760 /* We neither need nor want argument location descriptors for the
5761 64bit runtime environment or the ELF32 environment. */
5762 if (TARGET_64BIT || TARGET_ELF32)
5765 for (i = 0; i < 4; i++)
5768 /* Specify explicitly that no argument relocations should take place
5769 if using the portable runtime calling conventions. */
5770 if (TARGET_PORTABLE_RUNTIME)
5772 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5777 if (GET_CODE (call_insn) != CALL_INSN)
5779 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5781 rtx use = XEXP (link, 0);
5783 if (! (GET_CODE (use) == USE
5784 && GET_CODE (XEXP (use, 0)) == REG
5785 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5788 arg_mode = GET_MODE (XEXP (use, 0));
5789 regno = REGNO (XEXP (use, 0));
5790 if (regno >= 23 && regno <= 26)
5792 arg_regs[26 - regno] = "GR";
5793 if (arg_mode == DImode)
5794 arg_regs[25 - regno] = "GR";
5796 else if (regno >= 32 && regno <= 39)
5798 if (arg_mode == SFmode)
5799 arg_regs[(regno - 32) / 2] = "FR";
5802 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5803 arg_regs[(regno - 34) / 2] = "FR";
5804 arg_regs[(regno - 34) / 2 + 1] = "FU";
5806 arg_regs[(regno - 34) / 2] = "FU";
5807 arg_regs[(regno - 34) / 2 + 1] = "FR";
5812 fputs ("\t.CALL ", asm_out_file);
5813 for (i = 0; i < 4; i++)
5818 fputc (',', asm_out_file);
5819 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5822 fputc ('\n', asm_out_file);
5825 /* Return the class of any secondary reload register that is needed to
5826 move IN into a register in class CLASS using mode MODE.
5828 Profiling has showed this routine and its descendants account for
5829 a significant amount of compile time (~7%). So it has been
5830 optimized to reduce redundant computations and eliminate useless
5833 It might be worthwhile to try and make this a leaf function too. */
5836 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5838 int regno, is_symbolic;
5840 /* Trying to load a constant into a FP register during PIC code
5841 generation will require %r1 as a scratch register. */
5843 && GET_MODE_CLASS (mode) == MODE_INT
5844 && FP_REG_CLASS_P (class)
5845 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5848 /* Profiling showed the PA port spends about 1.3% of its compilation
5849 time in true_regnum from calls inside secondary_reload_class. */
5851 if (GET_CODE (in) == REG)
5854 if (regno >= FIRST_PSEUDO_REGISTER)
5855 regno = true_regnum (in);
5857 else if (GET_CODE (in) == SUBREG)
5858 regno = true_regnum (in);
5862 /* If we have something like (mem (mem (...)), we can safely assume the
5863 inner MEM will end up in a general register after reloading, so there's
5864 no need for a secondary reload. */
5865 if (GET_CODE (in) == MEM
5866 && GET_CODE (XEXP (in, 0)) == MEM)
5869 /* Handle out of range displacement for integer mode loads/stores of
5871 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5872 && GET_MODE_CLASS (mode) == MODE_INT
5873 && FP_REG_CLASS_P (class))
5874 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5875 return GENERAL_REGS;
5877 /* A SAR<->FP register copy requires a secondary register (GPR) as
5878 well as secondary memory. */
5879 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5880 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5881 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5882 return GENERAL_REGS;
5884 if (GET_CODE (in) == HIGH)
5887 /* Profiling has showed GCC spends about 2.6% of its compilation
5888 time in symbolic_operand from calls inside secondary_reload_class.
5890 We use an inline copy and only compute its return value once to avoid
5892 switch (GET_CODE (in))
5902 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5903 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5904 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5914 && read_only_operand (in, VOIDmode))
5917 if (class != R1_REGS && is_symbolic)
5923 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5924 by invisible reference. As a GCC extension, we also pass anything
5925 with a zero or variable size by reference.
5927 The 64-bit runtime does not describe passing any types by invisible
5928 reference. The internals of GCC can't currently handle passing
5929 empty structures, and zero or variable length arrays when they are
5930 not passed entirely on the stack or by reference. Thus, as a GCC
5931 extension, we pass these types by reference. The HP compiler doesn't
5932 support these types, so hopefully there shouldn't be any compatibility
5933 issues. This may have to be revisited when HP releases a C99 compiler
5934 or updates the ABI. */
5937 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5938 enum machine_mode mode, tree type,
5939 bool named ATTRIBUTE_UNUSED)
5944 size = int_size_in_bytes (type);
5946 size = GET_MODE_SIZE (mode);
5951 return size <= 0 || size > 8;
5955 function_arg_padding (enum machine_mode mode, tree type)
5958 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5960 /* Return none if justification is not required. */
5962 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5963 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5966 /* The directions set here are ignored when a BLKmode argument larger
5967 than a word is placed in a register. Different code is used for
5968 the stack and registers. This makes it difficult to have a
5969 consistent data representation for both the stack and registers.
5970 For both runtimes, the justification and padding for arguments on
5971 the stack and in registers should be identical. */
5973 /* The 64-bit runtime specifies left justification for aggregates. */
5976 /* The 32-bit runtime architecture specifies right justification.
5977 When the argument is passed on the stack, the argument is padded
5978 with garbage on the left. The HP compiler pads with zeros. */
5982 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5989 /* Do what is necessary for `va_start'. We look at the current function
5990 to determine if stdargs or varargs is used and fill in an initial
5991 va_list. A pointer to this constructor is returned. */
5994 hppa_builtin_saveregs (void)
5997 tree fntype = TREE_TYPE (current_function_decl);
5998 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5999 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6000 != void_type_node)))
6001 ? UNITS_PER_WORD : 0);
6004 offset = plus_constant (current_function_arg_offset_rtx, argadj);
6006 offset = current_function_arg_offset_rtx;
6012 /* Adjust for varargs/stdarg differences. */
6014 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
6016 offset = current_function_arg_offset_rtx;
6018 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6019 from the incoming arg pointer and growing to larger addresses. */
6020 for (i = 26, off = -64; i >= 19; i--, off += 8)
6021 emit_move_insn (gen_rtx_MEM (word_mode,
6022 plus_constant (arg_pointer_rtx, off)),
6023 gen_rtx_REG (word_mode, i));
6025 /* The incoming args pointer points just beyond the flushback area;
6026 normally this is not a serious concern. However, when we are doing
6027 varargs/stdargs we want to make the arg pointer point to the start
6028 of the incoming argument area. */
6029 emit_move_insn (virtual_incoming_args_rtx,
6030 plus_constant (arg_pointer_rtx, -64));
6032 /* Now return a pointer to the first anonymous argument. */
6033 return copy_to_reg (expand_binop (Pmode, add_optab,
6034 virtual_incoming_args_rtx,
6035 offset, 0, 0, OPTAB_LIB_WIDEN));
6038 /* Store general registers on the stack. */
6039 dest = gen_rtx_MEM (BLKmode,
6040 plus_constant (current_function_internal_arg_pointer,
6042 set_mem_alias_set (dest, get_varargs_alias_set ());
6043 set_mem_align (dest, BITS_PER_WORD);
6044 move_block_from_reg (23, dest, 4);
6046 /* move_block_from_reg will emit code to store the argument registers
6047 individually as scalar stores.
6049 However, other insns may later load from the same addresses for
6050 a structure load (passing a struct to a varargs routine).
6052 The alias code assumes that such aliasing can never happen, so we
6053 have to keep memory referencing insns from moving up beyond the
6054 last argument register store. So we emit a blockage insn here. */
6055 emit_insn (gen_blockage ());
6057 return copy_to_reg (expand_binop (Pmode, add_optab,
6058 current_function_internal_arg_pointer,
6059 offset, 0, 0, OPTAB_LIB_WIDEN));
6063 hppa_va_start (tree valist, rtx nextarg)
6065 nextarg = expand_builtin_saveregs ();
6066 std_expand_builtin_va_start (valist, nextarg);
6070 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
6074 /* Args grow upward. We can use the generic routines. */
6075 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6077 else /* !TARGET_64BIT */
6079 tree ptr = build_pointer_type (type);
6082 unsigned int size, ofs;
6085 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6089 ptr = build_pointer_type (type);
6091 size = int_size_in_bytes (type);
6092 valist_type = TREE_TYPE (valist);
6094 /* Args grow down. Not handled by generic routines. */
6096 u = fold_convert (valist_type, size_in_bytes (type));
6097 t = build (MINUS_EXPR, valist_type, valist, u);
6099 /* Copied from va-pa.h, but we probably don't need to align to
6100 word size, since we generate and preserve that invariant. */
6101 u = build_int_2 ((size > 4 ? -8 : -4), -1);
6102 u = fold_convert (valist_type, u);
6103 t = build (BIT_AND_EXPR, valist_type, t, u);
6105 t = build (MODIFY_EXPR, valist_type, valist, t);
6107 ofs = (8 - size) % 4;
6110 u = fold_convert (valist_type, size_int (ofs));
6111 t = build (PLUS_EXPR, valist_type, t, u);
6114 t = fold_convert (ptr, t);
6115 t = build_fold_indirect_ref (t);
6118 t = build_fold_indirect_ref (t);
6124 /* This routine handles all the normal conditional branch sequences we
6125 might need to generate. It handles compare immediate vs compare
6126 register, nullification of delay slots, varying length branches,
6127 negated branches, and all combinations of the above. It returns the
6128 output appropriate to emit the branch corresponding to all given
6132 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6134 static char buf[100];
6138 /* A conditional branch to the following instruction (eg the delay slot)
6139 is asking for a disaster. This can happen when not optimizing and
6140 when jump optimization fails.
6142 While it is usually safe to emit nothing, this can fail if the
6143 preceding instruction is a nullified branch with an empty delay
6144 slot and the same branch target as this branch. We could check
6145 for this but jump optimization should eliminate nop jumps. It
6146 is always safe to emit a nop. */
6147 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6150 /* The doubleword form of the cmpib instruction doesn't have the LEU
6151 and GTU conditions while the cmpb instruction does. Since we accept
6152 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6153 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6154 operands[2] = gen_rtx_REG (DImode, 0);
6156 /* If this is a long branch with its delay slot unfilled, set `nullify'
6157 as it can nullify the delay slot and save a nop. */
6158 if (length == 8 && dbr_sequence_length () == 0)
6161 /* If this is a short forward conditional branch which did not get
6162 its delay slot filled, the delay slot can still be nullified. */
6163 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6164 nullify = forward_branch_p (insn);
6166 /* A forward branch over a single nullified insn can be done with a
6167 comclr instruction. This avoids a single cycle penalty due to
6168 mis-predicted branch if we fall through (branch not taken). */
6170 && next_real_insn (insn) != 0
6171 && get_attr_length (next_real_insn (insn)) == 4
6172 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6178 /* All short conditional branches except backwards with an unfilled
6182 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6184 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6185 if (GET_MODE (operands[1]) == DImode)
6188 strcat (buf, "%B3");
6190 strcat (buf, "%S3");
6192 strcat (buf, " %2,%r1,%%r0");
6194 strcat (buf, ",n %2,%r1,%0");
6196 strcat (buf, " %2,%r1,%0");
6199 /* All long conditionals. Note a short backward branch with an
6200 unfilled delay slot is treated just like a long backward branch
6201 with an unfilled delay slot. */
6203 /* Handle weird backwards branch with a filled delay slot
6204 with is nullified. */
6205 if (dbr_sequence_length () != 0
6206 && ! forward_branch_p (insn)
6209 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6210 if (GET_MODE (operands[1]) == DImode)
6213 strcat (buf, "%S3");
6215 strcat (buf, "%B3");
6216 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6218 /* Handle short backwards branch with an unfilled delay slot.
6219 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6220 taken and untaken branches. */
6221 else if (dbr_sequence_length () == 0
6222 && ! forward_branch_p (insn)
6223 && INSN_ADDRESSES_SET_P ()
6224 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6225 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6227 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6228 if (GET_MODE (operands[1]) == DImode)
6231 strcat (buf, "%B3 %2,%r1,%0%#");
6233 strcat (buf, "%S3 %2,%r1,%0%#");
6237 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6238 if (GET_MODE (operands[1]) == DImode)
6241 strcat (buf, "%S3");
6243 strcat (buf, "%B3");
6245 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6247 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6253 xoperands[0] = operands[0];
6254 xoperands[1] = operands[1];
6255 xoperands[2] = operands[2];
6256 xoperands[3] = operands[3];
6258 /* The reversed conditional branch must branch over one additional
6259 instruction if the delay slot is filled. If the delay slot
6260 is empty, the instruction after the reversed condition branch
6261 must be nullified. */
6262 nullify = dbr_sequence_length () == 0;
6263 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6265 /* Create a reversed conditional branch which branches around
6266 the following insns. */
6267 if (GET_MODE (operands[1]) != DImode)
6273 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6276 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6282 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6285 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6294 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6297 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6303 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6306 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6310 output_asm_insn (buf, xoperands);
6311 return output_lbranch (operands[0], insn);
6319 /* This routine handles long unconditional branches that exceed the
6320 maximum range of a simple branch instruction. */
6323 output_lbranch (rtx dest, rtx insn)
6327 xoperands[0] = dest;
6329 /* First, free up the delay slot. */
6330 if (dbr_sequence_length () != 0)
6332 /* We can't handle a jump in the delay slot. */
6333 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6336 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6337 optimize, 0, 0, NULL);
6339 /* Now delete the delay insn. */
6340 PUT_CODE (NEXT_INSN (insn), NOTE);
6341 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6342 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6345 /* Output an insn to save %r1. The runtime documentation doesn't
6346 specify whether the "Clean Up" slot in the callers frame can
6347 be clobbered by the callee. It isn't copied by HP's builtin
6348 alloca, so this suggests that it can be clobbered if necessary.
6349 The "Static Link" location is copied by HP builtin alloca, so
6350 we avoid using it. Using the cleanup slot might be a problem
6351 if we have to interoperate with languages that pass cleanup
6352 information. However, it should be possible to handle these
6353 situations with GCC's asm feature.
6355 The "Current RP" slot is reserved for the called procedure, so
6356 we try to use it when we don't have a frame of our own. It's
6357 rather unlikely that we won't have a frame when we need to emit
6360 Really the way to go long term is a register scavenger; goto
6361 the target of the jump and find a register which we can use
6362 as a scratch to hold the value in %r1. Then, we wouldn't have
6363 to free up the delay slot or clobber a slot that may be needed
6364 for other purposes. */
6367 if (actual_fsize == 0 && !regs_ever_live[2])
6368 /* Use the return pointer slot in the frame marker. */
6369 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6371 /* Use the slot at -40 in the frame marker since HP builtin
6372 alloca doesn't copy it. */
6373 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6377 if (actual_fsize == 0 && !regs_ever_live[2])
6378 /* Use the return pointer slot in the frame marker. */
6379 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6381 /* Use the "Clean Up" slot in the frame marker. In GCC,
6382 the only other use of this location is for copying a
6383 floating point double argument from a floating-point
6384 register to two general registers. The copy is done
6385 as an "atomic" operation when outputting a call, so it
6386 won't interfere with our using the location here. */
6387 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6390 if (TARGET_PORTABLE_RUNTIME)
6392 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6393 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6394 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6398 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6399 if (TARGET_SOM || !TARGET_GAS)
6401 xoperands[1] = gen_label_rtx ();
6402 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6403 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6404 CODE_LABEL_NUMBER (xoperands[1]));
6405 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6409 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6410 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6412 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6415 /* Now output a very long branch to the original target. */
6416 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6418 /* Now restore the value of %r1 in the delay slot. */
6421 if (actual_fsize == 0 && !regs_ever_live[2])
6422 return "ldd -16(%%r30),%%r1";
6424 return "ldd -40(%%r30),%%r1";
6428 if (actual_fsize == 0 && !regs_ever_live[2])
6429 return "ldw -20(%%r30),%%r1";
6431 return "ldw -12(%%r30),%%r1";
6435 /* This routine handles all the branch-on-bit conditional branch sequences we
6436 might need to generate. It handles nullification of delay slots,
6437 varying length branches, negated branches and all combinations of the
6438 above. it returns the appropriate output template to emit the branch. */
6441 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6442 int negated, rtx insn, int which)
6444 static char buf[100];
6447 /* A conditional branch to the following instruction (eg the delay slot) is
6448 asking for a disaster. I do not think this can happen as this pattern
6449 is only used when optimizing; jump optimization should eliminate the
6450 jump. But be prepared just in case. */
6452 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6455 /* If this is a long branch with its delay slot unfilled, set `nullify'
6456 as it can nullify the delay slot and save a nop. */
6457 if (length == 8 && dbr_sequence_length () == 0)
6460 /* If this is a short forward conditional branch which did not get
6461 its delay slot filled, the delay slot can still be nullified. */
6462 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6463 nullify = forward_branch_p (insn);
6465 /* A forward branch over a single nullified insn can be done with a
6466 extrs instruction. This avoids a single cycle penalty due to
6467 mis-predicted branch if we fall through (branch not taken). */
6470 && next_real_insn (insn) != 0
6471 && get_attr_length (next_real_insn (insn)) == 4
6472 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6479 /* All short conditional branches except backwards with an unfilled
6483 strcpy (buf, "{extrs,|extrw,s,}");
6485 strcpy (buf, "bb,");
6486 if (useskip && GET_MODE (operands[0]) == DImode)
6487 strcpy (buf, "extrd,s,*");
6488 else if (GET_MODE (operands[0]) == DImode)
6489 strcpy (buf, "bb,*");
6490 if ((which == 0 && negated)
6491 || (which == 1 && ! negated))
6496 strcat (buf, " %0,%1,1,%%r0");
6497 else if (nullify && negated)
6498 strcat (buf, ",n %0,%1,%3");
6499 else if (nullify && ! negated)
6500 strcat (buf, ",n %0,%1,%2");
6501 else if (! nullify && negated)
6502 strcat (buf, "%0,%1,%3");
6503 else if (! nullify && ! negated)
6504 strcat (buf, " %0,%1,%2");
6507 /* All long conditionals. Note a short backward branch with an
6508 unfilled delay slot is treated just like a long backward branch
6509 with an unfilled delay slot. */
6511 /* Handle weird backwards branch with a filled delay slot
6512 with is nullified. */
6513 if (dbr_sequence_length () != 0
6514 && ! forward_branch_p (insn)
6517 strcpy (buf, "bb,");
6518 if (GET_MODE (operands[0]) == DImode)
6520 if ((which == 0 && negated)
6521 || (which == 1 && ! negated))
6526 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6528 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6530 /* Handle short backwards branch with an unfilled delay slot.
6531 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6532 taken and untaken branches. */
6533 else if (dbr_sequence_length () == 0
6534 && ! forward_branch_p (insn)
6535 && INSN_ADDRESSES_SET_P ()
6536 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6537 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6539 strcpy (buf, "bb,");
6540 if (GET_MODE (operands[0]) == DImode)
6542 if ((which == 0 && negated)
6543 || (which == 1 && ! negated))
6548 strcat (buf, " %0,%1,%3%#");
6550 strcat (buf, " %0,%1,%2%#");
6554 strcpy (buf, "{extrs,|extrw,s,}");
6555 if (GET_MODE (operands[0]) == DImode)
6556 strcpy (buf, "extrd,s,*");
6557 if ((which == 0 && negated)
6558 || (which == 1 && ! negated))
6562 if (nullify && negated)
6563 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6564 else if (nullify && ! negated)
6565 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6567 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6569 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6579 /* This routine handles all the branch-on-variable-bit conditional branch
6580 sequences we might need to generate. It handles nullification of delay
6581 slots, varying length branches, negated branches and all combinations
6582 of the above. it returns the appropriate output template to emit the
6586 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6587 int negated, rtx insn, int which)
6589 static char buf[100];
6592 /* A conditional branch to the following instruction (eg the delay slot) is
6593 asking for a disaster. I do not think this can happen as this pattern
6594 is only used when optimizing; jump optimization should eliminate the
6595 jump. But be prepared just in case. */
6597 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6600 /* If this is a long branch with its delay slot unfilled, set `nullify'
6601 as it can nullify the delay slot and save a nop. */
6602 if (length == 8 && dbr_sequence_length () == 0)
6605 /* If this is a short forward conditional branch which did not get
6606 its delay slot filled, the delay slot can still be nullified. */
6607 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6608 nullify = forward_branch_p (insn);
6610 /* A forward branch over a single nullified insn can be done with a
6611 extrs instruction. This avoids a single cycle penalty due to
6612 mis-predicted branch if we fall through (branch not taken). */
6615 && next_real_insn (insn) != 0
6616 && get_attr_length (next_real_insn (insn)) == 4
6617 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6624 /* All short conditional branches except backwards with an unfilled
6628 strcpy (buf, "{vextrs,|extrw,s,}");
6630 strcpy (buf, "{bvb,|bb,}");
6631 if (useskip && GET_MODE (operands[0]) == DImode)
6632 strcpy (buf, "extrd,s,*");
6633 else if (GET_MODE (operands[0]) == DImode)
6634 strcpy (buf, "bb,*");
6635 if ((which == 0 && negated)
6636 || (which == 1 && ! negated))
6641 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6642 else if (nullify && negated)
6643 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6644 else if (nullify && ! negated)
6645 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6646 else if (! nullify && negated)
6647 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6648 else if (! nullify && ! negated)
6649 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6652 /* All long conditionals. Note a short backward branch with an
6653 unfilled delay slot is treated just like a long backward branch
6654 with an unfilled delay slot. */
6656 /* Handle weird backwards branch with a filled delay slot
6657 with is nullified. */
6658 if (dbr_sequence_length () != 0
6659 && ! forward_branch_p (insn)
6662 strcpy (buf, "{bvb,|bb,}");
6663 if (GET_MODE (operands[0]) == DImode)
6665 if ((which == 0 && negated)
6666 || (which == 1 && ! negated))
6671 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6673 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6675 /* Handle short backwards branch with an unfilled delay slot.
6676 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6677 taken and untaken branches. */
6678 else if (dbr_sequence_length () == 0
6679 && ! forward_branch_p (insn)
6680 && INSN_ADDRESSES_SET_P ()
6681 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6682 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6684 strcpy (buf, "{bvb,|bb,}");
6685 if (GET_MODE (operands[0]) == DImode)
6687 if ((which == 0 && negated)
6688 || (which == 1 && ! negated))
6693 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6695 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6699 strcpy (buf, "{vextrs,|extrw,s,}");
6700 if (GET_MODE (operands[0]) == DImode)
6701 strcpy (buf, "extrd,s,*");
6702 if ((which == 0 && negated)
6703 || (which == 1 && ! negated))
6707 if (nullify && negated)
6708 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6709 else if (nullify && ! negated)
6710 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6712 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6714 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6724 /* Return the output template for emitting a dbra type insn.
6726 Note it may perform some output operations on its own before
6727 returning the final output string. */
6729 output_dbra (rtx *operands, rtx insn, int which_alternative)
6732 /* A conditional branch to the following instruction (eg the delay slot) is
6733 asking for a disaster. Be prepared! */
6735 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6737 if (which_alternative == 0)
6738 return "ldo %1(%0),%0";
6739 else if (which_alternative == 1)
6741 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6742 output_asm_insn ("ldw -16(%%r30),%4", operands);
6743 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6744 return "{fldws|fldw} -16(%%r30),%0";
6748 output_asm_insn ("ldw %0,%4", operands);
6749 return "ldo %1(%4),%4\n\tstw %4,%0";
6753 if (which_alternative == 0)
6755 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6756 int length = get_attr_length (insn);
6758 /* If this is a long branch with its delay slot unfilled, set `nullify'
6759 as it can nullify the delay slot and save a nop. */
6760 if (length == 8 && dbr_sequence_length () == 0)
6763 /* If this is a short forward conditional branch which did not get
6764 its delay slot filled, the delay slot can still be nullified. */
6765 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6766 nullify = forward_branch_p (insn);
6768 /* Handle short versions first. */
6769 if (length == 4 && nullify)
6770 return "addib,%C2,n %1,%0,%3";
6771 else if (length == 4 && ! nullify)
6772 return "addib,%C2 %1,%0,%3";
6773 else if (length == 8)
6775 /* Handle weird backwards branch with a fulled delay slot
6776 which is nullified. */
6777 if (dbr_sequence_length () != 0
6778 && ! forward_branch_p (insn)
6780 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6781 /* Handle short backwards branch with an unfilled delay slot.
6782 Using a addb;nop rather than addi;bl saves 1 cycle for both
6783 taken and untaken branches. */
6784 else if (dbr_sequence_length () == 0
6785 && ! forward_branch_p (insn)
6786 && INSN_ADDRESSES_SET_P ()
6787 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6788 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6789 return "addib,%C2 %1,%0,%3%#";
6791 /* Handle normal cases. */
6793 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6795 return "addi,%N2 %1,%0,%0\n\tb %3";
6800 /* Deal with gross reload from FP register case. */
6801 else if (which_alternative == 1)
6803 /* Move loop counter from FP register to MEM then into a GR,
6804 increment the GR, store the GR into MEM, and finally reload
6805 the FP register from MEM from within the branch's delay slot. */
6806 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6808 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6809 if (get_attr_length (insn) == 24)
6810 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6812 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6814 /* Deal with gross reload from memory case. */
6817 /* Reload loop counter from memory, the store back to memory
6818 happens in the branch's delay slot. */
6819 output_asm_insn ("ldw %0,%4", operands);
6820 if (get_attr_length (insn) == 12)
6821 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6823 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6827 /* Return the output template for emitting a dbra type insn.
6829 Note it may perform some output operations on its own before
6830 returning the final output string. */
6832 output_movb (rtx *operands, rtx insn, int which_alternative,
6833 int reverse_comparison)
6836 /* A conditional branch to the following instruction (eg the delay slot) is
6837 asking for a disaster. Be prepared! */
6839 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6841 if (which_alternative == 0)
6842 return "copy %1,%0";
6843 else if (which_alternative == 1)
6845 output_asm_insn ("stw %1,-16(%%r30)", operands);
6846 return "{fldws|fldw} -16(%%r30),%0";
6848 else if (which_alternative == 2)
6854 /* Support the second variant. */
6855 if (reverse_comparison)
6856 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6858 if (which_alternative == 0)
6860 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6861 int length = get_attr_length (insn);
6863 /* If this is a long branch with its delay slot unfilled, set `nullify'
6864 as it can nullify the delay slot and save a nop. */
6865 if (length == 8 && dbr_sequence_length () == 0)
6868 /* If this is a short forward conditional branch which did not get
6869 its delay slot filled, the delay slot can still be nullified. */
6870 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6871 nullify = forward_branch_p (insn);
6873 /* Handle short versions first. */
6874 if (length == 4 && nullify)
6875 return "movb,%C2,n %1,%0,%3";
6876 else if (length == 4 && ! nullify)
6877 return "movb,%C2 %1,%0,%3";
6878 else if (length == 8)
6880 /* Handle weird backwards branch with a filled delay slot
6881 which is nullified. */
6882 if (dbr_sequence_length () != 0
6883 && ! forward_branch_p (insn)
6885 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6887 /* Handle short backwards branch with an unfilled delay slot.
6888 Using a movb;nop rather than or;bl saves 1 cycle for both
6889 taken and untaken branches. */
6890 else if (dbr_sequence_length () == 0
6891 && ! forward_branch_p (insn)
6892 && INSN_ADDRESSES_SET_P ()
6893 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6894 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6895 return "movb,%C2 %1,%0,%3%#";
6896 /* Handle normal cases. */
6898 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6900 return "or,%N2 %1,%%r0,%0\n\tb %3";
6905 /* Deal with gross reload from FP register case. */
6906 else if (which_alternative == 1)
6908 /* Move loop counter from FP register to MEM then into a GR,
6909 increment the GR, store the GR into MEM, and finally reload
6910 the FP register from MEM from within the branch's delay slot. */
6911 output_asm_insn ("stw %1,-16(%%r30)", operands);
6912 if (get_attr_length (insn) == 12)
6913 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6915 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6917 /* Deal with gross reload from memory case. */
6918 else if (which_alternative == 2)
6920 /* Reload loop counter from memory, the store back to memory
6921 happens in the branch's delay slot. */
6922 if (get_attr_length (insn) == 8)
6923 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6925 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6927 /* Handle SAR as a destination. */
6930 if (get_attr_length (insn) == 8)
6931 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6933 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6937 /* Copy any FP arguments in INSN into integer registers. */
6939 copy_fp_args (rtx insn)
6944 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6946 int arg_mode, regno;
6947 rtx use = XEXP (link, 0);
6949 if (! (GET_CODE (use) == USE
6950 && GET_CODE (XEXP (use, 0)) == REG
6951 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6954 arg_mode = GET_MODE (XEXP (use, 0));
6955 regno = REGNO (XEXP (use, 0));
6957 /* Is it a floating point register? */
6958 if (regno >= 32 && regno <= 39)
6960 /* Copy the FP register into an integer register via memory. */
6961 if (arg_mode == SFmode)
6963 xoperands[0] = XEXP (use, 0);
6964 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6965 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6966 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6970 xoperands[0] = XEXP (use, 0);
6971 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6972 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6973 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6974 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6980 /* Compute length of the FP argument copy sequence for INSN. */
6982 length_fp_args (rtx insn)
6987 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6989 int arg_mode, regno;
6990 rtx use = XEXP (link, 0);
6992 if (! (GET_CODE (use) == USE
6993 && GET_CODE (XEXP (use, 0)) == REG
6994 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6997 arg_mode = GET_MODE (XEXP (use, 0));
6998 regno = REGNO (XEXP (use, 0));
7000 /* Is it a floating point register? */
7001 if (regno >= 32 && regno <= 39)
7003 if (arg_mode == SFmode)
7013 /* Return the attribute length for the millicode call instruction INSN.
7014 The length must match the code generated by output_millicode_call.
7015 We include the delay slot in the returned length as it is better to
7016 over estimate the length than to under estimate it. */
7019 attr_length_millicode_call (rtx insn)
7021 unsigned long distance = -1;
7022 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7024 if (INSN_ADDRESSES_SET_P ())
7026 distance = (total + insn_current_reference_address (insn));
7027 if (distance < total)
7033 if (!TARGET_LONG_CALLS && distance < 7600000)
7038 else if (TARGET_PORTABLE_RUNTIME)
7042 if (!TARGET_LONG_CALLS && distance < 240000)
7045 if (TARGET_LONG_ABS_CALL && !flag_pic)
7052 /* INSN is a function call. It may have an unconditional jump
7055 CALL_DEST is the routine we are calling. */
7058 output_millicode_call (rtx insn, rtx call_dest)
7060 int attr_length = get_attr_length (insn);
7061 int seq_length = dbr_sequence_length ();
7066 xoperands[0] = call_dest;
7067 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7069 /* Handle the common case where we are sure that the branch will
7070 reach the beginning of the $CODE$ subspace. The within reach
7071 form of the $$sh_func_adrs call has a length of 28. Because
7072 it has an attribute type of multi, it never has a nonzero
7073 sequence length. The length of the $$sh_func_adrs is the same
7074 as certain out of reach PIC calls to other routines. */
7075 if (!TARGET_LONG_CALLS
7076 && ((seq_length == 0
7077 && (attr_length == 12
7078 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7079 || (seq_length != 0 && attr_length == 8)))
7081 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7087 /* It might seem that one insn could be saved by accessing
7088 the millicode function using the linkage table. However,
7089 this doesn't work in shared libraries and other dynamically
7090 loaded objects. Using a pc-relative sequence also avoids
7091 problems related to the implicit use of the gp register. */
7092 output_asm_insn ("b,l .+8,%%r1", xoperands);
7096 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7097 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7101 xoperands[1] = gen_label_rtx ();
7102 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7103 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7104 CODE_LABEL_NUMBER (xoperands[1]));
7105 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7108 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7110 else if (TARGET_PORTABLE_RUNTIME)
7112 /* Pure portable runtime doesn't allow be/ble; we also don't
7113 have PIC support in the assembler/linker, so this sequence
7116 /* Get the address of our target into %r1. */
7117 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7118 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7120 /* Get our return address into %r31. */
7121 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7122 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7124 /* Jump to our target address in %r1. */
7125 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7129 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7131 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7133 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7137 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7138 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7140 if (TARGET_SOM || !TARGET_GAS)
7142 /* The HP assembler can generate relocations for the
7143 difference of two symbols. GAS can do this for a
7144 millicode symbol but not an arbitrary external
7145 symbol when generating SOM output. */
7146 xoperands[1] = gen_label_rtx ();
7147 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7148 CODE_LABEL_NUMBER (xoperands[1]));
7149 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7150 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7154 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7155 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7159 /* Jump to our target address in %r1. */
7160 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7164 if (seq_length == 0)
7165 output_asm_insn ("nop", xoperands);
7167 /* We are done if there isn't a jump in the delay slot. */
7168 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7171 /* This call has an unconditional jump in its delay slot. */
7172 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7174 /* See if the return address can be adjusted. Use the containing
7175 sequence insn's address. */
7176 if (INSN_ADDRESSES_SET_P ())
7178 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7179 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7180 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7182 if (VAL_14_BITS_P (distance))
7184 xoperands[1] = gen_label_rtx ();
7185 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7186 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7187 CODE_LABEL_NUMBER (xoperands[1]));
7190 /* ??? This branch may not reach its target. */
7191 output_asm_insn ("nop\n\tb,n %0", xoperands);
7194 /* ??? This branch may not reach its target. */
7195 output_asm_insn ("nop\n\tb,n %0", xoperands);
7197 /* Delete the jump. */
7198 PUT_CODE (NEXT_INSN (insn), NOTE);
7199 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7200 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7205 /* Return the attribute length of the call instruction INSN. The SIBCALL
7206 flag indicates whether INSN is a regular call or a sibling call. The
7207 length returned must be longer than the code actually generated by
7208 output_call. Since branch shortening is done before delay branch
7209 sequencing, there is no way to determine whether or not the delay
7210 slot will be filled during branch shortening. Even when the delay
7211 slot is filled, we may have to add a nop if the delay slot contains
7212 a branch that can't reach its target. Thus, we always have to include
7213 the delay slot in the length estimate. This used to be done in
7214 pa_adjust_insn_length but we do it here now as some sequences always
7215 fill the delay slot and we can save four bytes in the estimate for
7219 attr_length_call (rtx insn, int sibcall)
7225 rtx pat = PATTERN (insn);
7226 unsigned long distance = -1;
7228 if (INSN_ADDRESSES_SET_P ())
7230 unsigned long total;
7232 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7233 distance = (total + insn_current_reference_address (insn));
7234 if (distance < total)
7238 /* Determine if this is a local call. */
7239 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7240 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7242 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7244 call_decl = SYMBOL_REF_DECL (call_dest);
7245 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7247 /* pc-relative branch. */
7248 if (!TARGET_LONG_CALLS
7249 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7250 || distance < 240000))
7253 /* 64-bit plabel sequence. */
7254 else if (TARGET_64BIT && !local_call)
7255 length += sibcall ? 28 : 24;
7257 /* non-pic long absolute branch sequence. */
7258 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7261 /* long pc-relative branch sequence. */
7262 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7263 || (TARGET_64BIT && !TARGET_GAS)
7264 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7268 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7272 /* 32-bit plabel sequence. */
7278 length += length_fp_args (insn);
7288 if (!TARGET_NO_SPACE_REGS)
7296 /* INSN is a function call. It may have an unconditional jump
7299 CALL_DEST is the routine we are calling. */
7302 output_call (rtx insn, rtx call_dest, int sibcall)
7304 int delay_insn_deleted = 0;
7305 int delay_slot_filled = 0;
7306 int seq_length = dbr_sequence_length ();
7307 tree call_decl = SYMBOL_REF_DECL (call_dest);
7308 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7311 xoperands[0] = call_dest;
7313 /* Handle the common case where we're sure that the branch will reach
7314 the beginning of the "$CODE$" subspace. This is the beginning of
7315 the current function if we are in a named section. */
7316 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7318 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7319 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7323 if (TARGET_64BIT && !local_call)
7325 /* ??? As far as I can tell, the HP linker doesn't support the
7326 long pc-relative sequence described in the 64-bit runtime
7327 architecture. So, we use a slightly longer indirect call. */
7328 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7330 xoperands[0] = p->internal_label;
7331 xoperands[1] = gen_label_rtx ();
7333 /* If this isn't a sibcall, we put the load of %r27 into the
7334 delay slot. We can't do this in a sibcall as we don't
7335 have a second call-clobbered scratch register available. */
7337 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7340 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7341 optimize, 0, 0, NULL);
7343 /* Now delete the delay insn. */
7344 PUT_CODE (NEXT_INSN (insn), NOTE);
7345 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7346 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7347 delay_insn_deleted = 1;
7350 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7351 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7352 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7356 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7357 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7358 output_asm_insn ("bve (%%r1)", xoperands);
7362 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7363 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7364 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7365 delay_slot_filled = 1;
7370 int indirect_call = 0;
7372 /* Emit a long call. There are several different sequences
7373 of increasing length and complexity. In most cases,
7374 they don't allow an instruction in the delay slot. */
7375 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7376 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7377 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7382 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7384 && (!TARGET_PA_20 || indirect_call))
7386 /* A non-jump insn in the delay slot. By definition we can
7387 emit this insn before the call (and in fact before argument
7389 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7392 /* Now delete the delay insn. */
7393 PUT_CODE (NEXT_INSN (insn), NOTE);
7394 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7395 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7396 delay_insn_deleted = 1;
7399 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7401 /* This is the best sequence for making long calls in
7402 non-pic code. Unfortunately, GNU ld doesn't provide
7403 the stub needed for external calls, and GAS's support
7404 for this with the SOM linker is buggy. It is safe
7405 to use this for local calls. */
7406 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7408 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7412 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7415 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7417 output_asm_insn ("copy %%r31,%%r2", xoperands);
7418 delay_slot_filled = 1;
7423 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7424 || (TARGET_64BIT && !TARGET_GAS))
7426 /* The HP assembler and linker can handle relocations
7427 for the difference of two symbols. GAS and the HP
7428 linker can't do this when one of the symbols is
7430 xoperands[1] = gen_label_rtx ();
7431 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7432 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7433 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7434 CODE_LABEL_NUMBER (xoperands[1]));
7435 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7437 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7439 /* GAS currently can't generate the relocations that
7440 are needed for the SOM linker under HP-UX using this
7441 sequence. The GNU linker doesn't generate the stubs
7442 that are needed for external calls on TARGET_ELF32
7443 with this sequence. For now, we have to use a
7444 longer plabel sequence when using GAS. */
7445 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7446 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7448 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7453 /* Emit a long plabel-based call sequence. This is
7454 essentially an inline implementation of $$dyncall.
7455 We don't actually try to call $$dyncall as this is
7456 as difficult as calling the function itself. */
7457 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7459 xoperands[0] = p->internal_label;
7460 xoperands[1] = gen_label_rtx ();
7462 /* Since the call is indirect, FP arguments in registers
7463 need to be copied to the general registers. Then, the
7464 argument relocation stub will copy them back. */
7466 copy_fp_args (insn);
7470 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7471 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7472 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7476 output_asm_insn ("addil LR'%0-$global$,%%r27",
7478 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7482 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7483 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7484 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7485 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7487 if (!sibcall && !TARGET_PA_20)
7489 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7490 if (TARGET_NO_SPACE_REGS)
7491 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7493 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7500 output_asm_insn ("bve (%%r1)", xoperands);
7505 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7506 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7507 delay_slot_filled = 1;
7510 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7515 if (!TARGET_NO_SPACE_REGS)
7516 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7521 if (TARGET_NO_SPACE_REGS)
7522 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7524 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7528 if (TARGET_NO_SPACE_REGS)
7529 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7531 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7534 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7536 output_asm_insn ("copy %%r31,%%r2", xoperands);
7537 delay_slot_filled = 1;
7544 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7545 output_asm_insn ("nop", xoperands);
7547 /* We are done if there isn't a jump in the delay slot. */
7549 || delay_insn_deleted
7550 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7553 /* A sibcall should never have a branch in the delay slot. */
7557 /* This call has an unconditional jump in its delay slot. */
7558 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7560 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7562 /* See if the return address can be adjusted. Use the containing
7563 sequence insn's address. */
7564 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7565 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7566 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7568 if (VAL_14_BITS_P (distance))
7570 xoperands[1] = gen_label_rtx ();
7571 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7572 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7573 CODE_LABEL_NUMBER (xoperands[1]));
7576 output_asm_insn ("nop\n\tb,n %0", xoperands);
7579 output_asm_insn ("b,n %0", xoperands);
7581 /* Delete the jump. */
7582 PUT_CODE (NEXT_INSN (insn), NOTE);
7583 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7584 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7589 /* Return the attribute length of the indirect call instruction INSN.
7590 The length must match the code generated by output_indirect call.
7591 The returned length includes the delay slot. Currently, the delay
7592 slot of an indirect call sequence is not exposed and it is used by
7593 the sequence itself. */
7596 attr_length_indirect_call (rtx insn)
7598 unsigned long distance = -1;
7599 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7601 if (INSN_ADDRESSES_SET_P ())
7603 distance = (total + insn_current_reference_address (insn));
7604 if (distance < total)
7611 if (TARGET_FAST_INDIRECT_CALLS
7612 || (!TARGET_PORTABLE_RUNTIME
7613 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7619 if (TARGET_PORTABLE_RUNTIME)
7622 /* Out of reach, can use ble. */
7627 output_indirect_call (rtx insn, rtx call_dest)
7633 xoperands[0] = call_dest;
7634 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7635 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7639 /* First the special case for kernels, level 0 systems, etc. */
7640 if (TARGET_FAST_INDIRECT_CALLS)
7641 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7643 /* Now the normal case -- we can reach $$dyncall directly or
7644 we're sure that we can get there via a long-branch stub.
7646 No need to check target flags as the length uniquely identifies
7647 the remaining cases. */
7648 if (attr_length_indirect_call (insn) == 8)
7650 /* The HP linker substitutes a BLE for millicode calls using
7651 the short PIC PCREL form. Thus, we must use %r31 as the
7652 link register when generating PA 1.x code. */
7654 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7656 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7659 /* Long millicode call, but we are not generating PIC or portable runtime
7661 if (attr_length_indirect_call (insn) == 12)
7662 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7664 /* Long millicode call for portable runtime. */
7665 if (attr_length_indirect_call (insn) == 20)
7666 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7668 /* We need a long PIC call to $$dyncall. */
7669 xoperands[0] = NULL_RTX;
7670 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7671 if (TARGET_SOM || !TARGET_GAS)
7673 xoperands[0] = gen_label_rtx ();
7674 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7675 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7676 CODE_LABEL_NUMBER (xoperands[0]));
7677 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7681 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7682 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7685 output_asm_insn ("blr %%r0,%%r2", xoperands);
7686 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7690 /* Return the total length of the save and restore instructions needed for
7691 the data linkage table pointer (i.e., the PIC register) across the call
7692 instruction INSN. No-return calls do not require a save and restore.
7693 In addition, we may be able to avoid the save and restore for calls
7694 within the same translation unit. */
7697 attr_length_save_restore_dltp (rtx insn)
7699 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7705 /* In HPUX 8.0's shared library scheme, special relocations are needed
7706 for function labels if they might be passed to a function
7707 in a shared library (because shared libraries don't live in code
7708 space), and special magic is needed to construct their address. */
7711 hppa_encode_label (rtx sym)
7713 const char *str = XSTR (sym, 0);
7714 int len = strlen (str) + 1;
7717 p = newstr = alloca (len + 1);
7721 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7725 pa_encode_section_info (tree decl, rtx rtl, int first)
7727 if (first && TEXT_SPACE_P (decl))
7729 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7730 if (TREE_CODE (decl) == FUNCTION_DECL)
7731 hppa_encode_label (XEXP (rtl, 0));
7735 /* This is sort of inverse to pa_encode_section_info. */
7738 pa_strip_name_encoding (const char *str)
7740 str += (*str == '@');
7741 str += (*str == '*');
7746 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7748 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7751 /* Returns 1 if OP is a function label involved in a simple addition
7752 with a constant. Used to keep certain patterns from matching
7753 during instruction combination. */
7755 is_function_label_plus_const (rtx op)
7757 /* Strip off any CONST. */
7758 if (GET_CODE (op) == CONST)
7761 return (GET_CODE (op) == PLUS
7762 && function_label_operand (XEXP (op, 0), Pmode)
7763 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7766 /* Output assembly code for a thunk to FUNCTION. */
7769 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7770 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7773 const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7774 const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
7775 int val_14 = VAL_14_BITS_P (delta);
7777 static unsigned int current_thunk_number;
7780 ASM_OUTPUT_LABEL (file, tname);
7781 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7783 fname = (*targetm.strip_name_encoding) (fname);
7784 tname = (*targetm.strip_name_encoding) (tname);
7786 /* Output the thunk. We know that the function is in the same
7787 translation unit (i.e., the same space) as the thunk, and that
7788 thunks are output after their method. Thus, we don't need an
7789 external branch to reach the function. With SOM and GAS,
7790 functions and thunks are effectively in different sections.
7791 Thus, we can always use a IA-relative branch and the linker
7792 will add a long branch stub if necessary.
7794 However, we have to be careful when generating PIC code on the
7795 SOM port to ensure that the sequence does not transfer to an
7796 import stub for the target function as this could clobber the
7797 return value saved at SP-24. This would also apply to the
7798 32-bit linux port if the multi-space model is implemented. */
7799 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7800 && !(flag_pic && TREE_PUBLIC (function))
7801 && (TARGET_GAS || last_address < 262132))
7802 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7803 && ((targetm.have_named_sections
7804 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7805 /* The GNU 64-bit linker has rather poor stub management.
7806 So, we use a long branch from thunks that aren't in
7807 the same section as the target function. */
7809 && (DECL_SECTION_NAME (thunk_fndecl)
7810 != DECL_SECTION_NAME (function)))
7811 || ((DECL_SECTION_NAME (thunk_fndecl)
7812 == DECL_SECTION_NAME (function))
7813 && last_address < 262132)))
7814 || (!targetm.have_named_sections && last_address < 262132))))
7818 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7819 "(%%r26),%%r26\n", fname, delta);
7824 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7826 fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7827 "(%%r1),%%r26\n", fname, delta);
7831 else if (TARGET_64BIT)
7833 /* We only have one call-clobbered scratch register, so we can't
7834 make use of the delay slot if delta doesn't fit in 14 bits. */
7836 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7837 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7838 "(%%r1),%%r26\n", delta, delta);
7840 fprintf (file, "\tb,l .+8,%%r1\n");
7844 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7845 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname);
7849 int off = val_14 ? 8 : 16;
7850 fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off);
7851 fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off);
7856 fprintf (file, "\tbv %%r0(%%r1)\n\tldo ");
7857 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7862 fprintf (file, "\tbv,n %%r0(%%r1)\n");
7866 else if (TARGET_PORTABLE_RUNTIME)
7868 fprintf (file, "\tldil L'%s,%%r1\n", fname);
7869 fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname);
7873 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7874 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7879 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7881 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7882 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7886 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7888 /* The function is accessible from outside this module. The only
7889 way to avoid an import stub between the thunk and function is to
7890 call the function directly with an indirect sequence similar to
7891 that used by $$dyncall. This is possible because $$dyncall acts
7892 as the import stub in an indirect call. */
7895 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7896 lab = (*targetm.strip_name_encoding) (label);
7898 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7899 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7900 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7901 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7902 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7903 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7904 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7907 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7913 fprintf (file, "\tbve (%%r22)\n\tldo ");
7918 if (TARGET_NO_SPACE_REGS)
7920 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7925 fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
7926 fprintf (file, "\tmtsp %%r21,%%sr0\n");
7927 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7933 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7935 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7940 fprintf (file, "\tb,l .+8,%%r1\n");
7942 fprintf (file, "\tbl .+8,%%r1\n");
7944 if (TARGET_SOM || !TARGET_GAS)
7946 fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname);
7947 fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname);
7951 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7952 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname);
7957 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7958 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7963 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7965 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7966 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7973 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta);
7975 fprintf (file, "\tldil L'%s,%%r22\n", fname);
7976 fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname);
7980 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7985 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7990 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7992 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7995 fprintf (file, "\t.align 4\n");
7996 ASM_OUTPUT_LABEL (file, label);
7997 fprintf (file, "\t.word P'%s\n", fname);
7998 function_section (thunk_fndecl);
8001 current_thunk_number++;
8002 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8003 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8004 last_address += nbytes;
8005 update_total_code_bytes (nbytes);
8008 /* Only direct calls to static functions are allowed to be sibling (tail)
8011 This restriction is necessary because some linker generated stubs will
8012 store return pointers into rp' in some cases which might clobber a
8013 live value already in rp'.
8015 In a sibcall the current function and the target function share stack
8016 space. Thus if the path to the current function and the path to the
8017 target function save a value in rp', they save the value into the
8018 same stack slot, which has undesirable consequences.
8020 Because of the deferred binding nature of shared libraries any function
8021 with external scope could be in a different load module and thus require
8022 rp' to be saved when calling that function. So sibcall optimizations
8023 can only be safe for static function.
8025 Note that GCC never needs return value relocations, so we don't have to
8026 worry about static calls with return value relocations (which require
8029 It is safe to perform a sibcall optimization when the target function
8030 will never return. */
8032 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8034 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8035 single subspace mode and the call is not indirect. As far as I know,
8036 there is no operating system support for the multiple subspace mode.
8037 It might be possible to support indirect calls if we didn't use
8038 $$dyncall (see the indirect sequence generated in output_call). */
8040 return (decl != NULL_TREE);
8042 /* Sibcalls are not ok because the arg pointer register is not a fixed
8043 register. This prevents the sibcall optimization from occurring. In
8044 addition, there are problems with stub placement using GNU ld. This
8045 is because a normal sibcall branch uses a 17-bit relocation while
8046 a regular call branch uses a 22-bit relocation. As a result, more
8047 care needs to be taken in the placement of long-branch stubs. */
8052 && !TARGET_PORTABLE_RUNTIME
8053 && !TREE_PUBLIC (decl));
8056 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8057 use in fmpyadd instructions. */
8059 fmpyaddoperands (rtx *operands)
8061 enum machine_mode mode = GET_MODE (operands[0]);
8063 /* Must be a floating point mode. */
8064 if (mode != SFmode && mode != DFmode)
8067 /* All modes must be the same. */
8068 if (! (mode == GET_MODE (operands[1])
8069 && mode == GET_MODE (operands[2])
8070 && mode == GET_MODE (operands[3])
8071 && mode == GET_MODE (operands[4])
8072 && mode == GET_MODE (operands[5])))
8075 /* All operands must be registers. */
8076 if (! (GET_CODE (operands[1]) == REG
8077 && GET_CODE (operands[2]) == REG
8078 && GET_CODE (operands[3]) == REG
8079 && GET_CODE (operands[4]) == REG
8080 && GET_CODE (operands[5]) == REG))
8083 /* Only 2 real operands to the addition. One of the input operands must
8084 be the same as the output operand. */
8085 if (! rtx_equal_p (operands[3], operands[4])
8086 && ! rtx_equal_p (operands[3], operands[5]))
8089 /* Inout operand of add can not conflict with any operands from multiply. */
8090 if (rtx_equal_p (operands[3], operands[0])
8091 || rtx_equal_p (operands[3], operands[1])
8092 || rtx_equal_p (operands[3], operands[2]))
8095 /* multiply can not feed into addition operands. */
8096 if (rtx_equal_p (operands[4], operands[0])
8097 || rtx_equal_p (operands[5], operands[0]))
8100 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8102 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8103 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8104 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8105 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8106 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8107 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8110 /* Passed. Operands are suitable for fmpyadd. */
8114 #if !defined(USE_COLLECT2)
8116 pa_asm_out_constructor (rtx symbol, int priority)
8118 if (!function_label_operand (symbol, VOIDmode))
8119 hppa_encode_label (symbol);
8121 #ifdef CTORS_SECTION_ASM_OP
8122 default_ctor_section_asm_out_constructor (symbol, priority);
8124 # ifdef TARGET_ASM_NAMED_SECTION
8125 default_named_section_asm_out_constructor (symbol, priority);
8127 default_stabs_asm_out_constructor (symbol, priority);
8133 pa_asm_out_destructor (rtx symbol, int priority)
8135 if (!function_label_operand (symbol, VOIDmode))
8136 hppa_encode_label (symbol);
8138 #ifdef DTORS_SECTION_ASM_OP
8139 default_dtor_section_asm_out_destructor (symbol, priority);
8141 # ifdef TARGET_ASM_NAMED_SECTION
8142 default_named_section_asm_out_destructor (symbol, priority);
8144 default_stabs_asm_out_destructor (symbol, priority);
8150 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8151 use in fmpysub instructions. */
8153 fmpysuboperands (rtx *operands)
8155 enum machine_mode mode = GET_MODE (operands[0]);
8157 /* Must be a floating point mode. */
8158 if (mode != SFmode && mode != DFmode)
8161 /* All modes must be the same. */
8162 if (! (mode == GET_MODE (operands[1])
8163 && mode == GET_MODE (operands[2])
8164 && mode == GET_MODE (operands[3])
8165 && mode == GET_MODE (operands[4])
8166 && mode == GET_MODE (operands[5])))
8169 /* All operands must be registers. */
8170 if (! (GET_CODE (operands[1]) == REG
8171 && GET_CODE (operands[2]) == REG
8172 && GET_CODE (operands[3]) == REG
8173 && GET_CODE (operands[4]) == REG
8174 && GET_CODE (operands[5]) == REG))
8177 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8178 operation, so operands[4] must be the same as operand[3]. */
8179 if (! rtx_equal_p (operands[3], operands[4]))
8182 /* multiply can not feed into subtraction. */
8183 if (rtx_equal_p (operands[5], operands[0]))
8186 /* Inout operand of sub can not conflict with any operands from multiply. */
8187 if (rtx_equal_p (operands[3], operands[0])
8188 || rtx_equal_p (operands[3], operands[1])
8189 || rtx_equal_p (operands[3], operands[2]))
8192 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8194 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8195 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8196 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8197 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8198 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8199 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8202 /* Passed. Operands are suitable for fmpysub. */
8207 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8209 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8210 || GET_CODE (op) == IOR);
8213 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8214 constants for shadd instructions. */
8216 shadd_constant_p (int val)
8218 if (val == 2 || val == 4 || val == 8)
8224 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8225 the valid constant for shadd instructions. */
8227 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8229 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8232 /* Return 1 if OP is valid as a base or index register in a
8236 borx_reg_operand (rtx op, enum machine_mode mode)
8238 if (GET_CODE (op) != REG)
8241 /* We must reject virtual registers as the only expressions that
8242 can be instantiated are REG and REG+CONST. */
8243 if (op == virtual_incoming_args_rtx
8244 || op == virtual_stack_vars_rtx
8245 || op == virtual_stack_dynamic_rtx
8246 || op == virtual_outgoing_args_rtx
8247 || op == virtual_cfa_rtx)
8250 /* While it's always safe to index off the frame pointer, it's not
8251 profitable to do so when the frame pointer is being eliminated. */
8252 if (!reload_completed
8253 && flag_omit_frame_pointer
8254 && !current_function_calls_alloca
8255 && op == frame_pointer_rtx)
8258 return register_operand (op, mode);
8261 /* Return 1 if this operand is anything other than a hard register. */
8264 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8266 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8269 /* Return 1 if INSN branches forward. Should be using insn_addresses
8270 to avoid walking through all the insns... */
8272 forward_branch_p (rtx insn)
8274 rtx label = JUMP_LABEL (insn);
8281 insn = NEXT_INSN (insn);
8284 return (insn == label);
8287 /* Return 1 if OP is an equality comparison, else return 0. */
8289 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8291 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8294 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8296 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8298 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8299 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8302 /* Return 1 if INSN is in the delay slot of a call instruction. */
8304 jump_in_call_delay (rtx insn)
8307 if (GET_CODE (insn) != JUMP_INSN)
8310 if (PREV_INSN (insn)
8311 && PREV_INSN (PREV_INSN (insn))
8312 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8314 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8316 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8317 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8324 /* Output an unconditional move and branch insn. */
8327 output_parallel_movb (rtx *operands, int length)
8329 /* These are the cases in which we win. */
8331 return "mov%I1b,tr %1,%0,%2";
8333 /* None of these cases wins, but they don't lose either. */
8334 if (dbr_sequence_length () == 0)
8336 /* Nothing in the delay slot, fake it by putting the combined
8337 insn (the copy or add) in the delay slot of a bl. */
8338 if (GET_CODE (operands[1]) == CONST_INT)
8339 return "b %2\n\tldi %1,%0";
8341 return "b %2\n\tcopy %1,%0";
8345 /* Something in the delay slot, but we've got a long branch. */
8346 if (GET_CODE (operands[1]) == CONST_INT)
8347 return "ldi %1,%0\n\tb %2";
8349 return "copy %1,%0\n\tb %2";
8353 /* Output an unconditional add and branch insn. */
8356 output_parallel_addb (rtx *operands, int length)
8358 /* To make life easy we want operand0 to be the shared input/output
8359 operand and operand1 to be the readonly operand. */
8360 if (operands[0] == operands[1])
8361 operands[1] = operands[2];
8363 /* These are the cases in which we win. */
8365 return "add%I1b,tr %1,%0,%3";
8367 /* None of these cases win, but they don't lose either. */
8368 if (dbr_sequence_length () == 0)
8370 /* Nothing in the delay slot, fake it by putting the combined
8371 insn (the copy or add) in the delay slot of a bl. */
8372 return "b %3\n\tadd%I1 %1,%0,%0";
8376 /* Something in the delay slot, but we've got a long branch. */
8377 return "add%I1 %1,%0,%0\n\tb %3";
8381 /* Return nonzero if INSN (a jump insn) immediately follows a call
8382 to a named function. This is used to avoid filling the delay slot
8383 of the jump since it can usually be eliminated by modifying RP in
8384 the delay slot of the call. */
8387 following_call (rtx insn)
8389 if (! TARGET_JUMP_IN_DELAY)
8392 /* Find the previous real insn, skipping NOTEs. */
8393 insn = PREV_INSN (insn);
8394 while (insn && GET_CODE (insn) == NOTE)
8395 insn = PREV_INSN (insn);
8397 /* Check for CALL_INSNs and millicode calls. */
8399 && ((GET_CODE (insn) == CALL_INSN
8400 && get_attr_type (insn) != TYPE_DYNCALL)
8401 || (GET_CODE (insn) == INSN
8402 && GET_CODE (PATTERN (insn)) != SEQUENCE
8403 && GET_CODE (PATTERN (insn)) != USE
8404 && GET_CODE (PATTERN (insn)) != CLOBBER
8405 && get_attr_type (insn) == TYPE_MILLI)))
8411 /* We use this hook to perform a PA specific optimization which is difficult
8412 to do in earlier passes.
8414 We want the delay slots of branches within jump tables to be filled.
8415 None of the compiler passes at the moment even has the notion that a
8416 PA jump table doesn't contain addresses, but instead contains actual
8419 Because we actually jump into the table, the addresses of each entry
8420 must stay constant in relation to the beginning of the table (which
8421 itself must stay constant relative to the instruction to jump into
8422 it). I don't believe we can guarantee earlier passes of the compiler
8423 will adhere to those rules.
8425 So, late in the compilation process we find all the jump tables, and
8426 expand them into real code -- eg each entry in the jump table vector
8427 will get an appropriate label followed by a jump to the final target.
8429 Reorg and the final jump pass can then optimize these branches and
8430 fill their delay slots. We end up with smaller, more efficient code.
8432 The jump instructions within the table are special; we must be able
8433 to identify them during assembly output (if the jumps don't get filled
8434 we need to emit a nop rather than nullifying the delay slot)). We
8435 identify jumps in switch tables by using insns with the attribute
8436 type TYPE_BTABLE_BRANCH.
8438 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8439 insns. This serves two purposes, first it prevents jump.c from
8440 noticing that the last N entries in the table jump to the instruction
8441 immediately after the table and deleting the jumps. Second, those
8442 insns mark where we should emit .begin_brtab and .end_brtab directives
8443 when using GAS (allows for better link time optimizations). */
8450 remove_useless_addtr_insns (1);
8452 if (pa_cpu < PROCESSOR_8000)
8453 pa_combine_instructions ();
8456 /* This is fairly cheap, so always run it if optimizing. */
8457 if (optimize > 0 && !TARGET_BIG_SWITCH)
8459 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8460 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8462 rtx pattern, tmp, location, label;
8463 unsigned int length, i;
8465 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8466 if (GET_CODE (insn) != JUMP_INSN
8467 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8468 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8471 /* Emit marker for the beginning of the branch table. */
8472 emit_insn_before (gen_begin_brtab (), insn);
8474 pattern = PATTERN (insn);
8475 location = PREV_INSN (insn);
8476 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8478 for (i = 0; i < length; i++)
8480 /* Emit a label before each jump to keep jump.c from
8481 removing this code. */
8482 tmp = gen_label_rtx ();
8483 LABEL_NUSES (tmp) = 1;
8484 emit_label_after (tmp, location);
8485 location = NEXT_INSN (location);
8487 if (GET_CODE (pattern) == ADDR_VEC)
8488 label = XEXP (XVECEXP (pattern, 0, i), 0);
8490 label = XEXP (XVECEXP (pattern, 1, i), 0);
8492 tmp = gen_short_jump (label);
8494 /* Emit the jump itself. */
8495 tmp = emit_jump_insn_after (tmp, location);
8496 JUMP_LABEL (tmp) = label;
8497 LABEL_NUSES (label)++;
8498 location = NEXT_INSN (location);
8500 /* Emit a BARRIER after the jump. */
8501 emit_barrier_after (location);
8502 location = NEXT_INSN (location);
8505 /* Emit marker for the end of the branch table. */
8506 emit_insn_before (gen_end_brtab (), location);
8507 location = NEXT_INSN (location);
8508 emit_barrier_after (location);
8510 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8516 /* Still need brtab marker insns. FIXME: the presence of these
8517 markers disables output of the branch table to readonly memory,
8518 and any alignment directives that might be needed. Possibly,
8519 the begin_brtab insn should be output before the label for the
8520 table. This doesn't matter at the moment since the tables are
8521 always output in the text section. */
8522 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8524 /* Find an ADDR_VEC insn. */
8525 if (GET_CODE (insn) != JUMP_INSN
8526 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8527 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8530 /* Now generate markers for the beginning and end of the
8532 emit_insn_before (gen_begin_brtab (), insn);
8533 emit_insn_after (gen_end_brtab (), insn);
8538 /* The PA has a number of odd instructions which can perform multiple
8539 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8540 it may be profitable to combine two instructions into one instruction
8541 with two outputs. It's not profitable PA2.0 machines because the
8542 two outputs would take two slots in the reorder buffers.
8544 This routine finds instructions which can be combined and combines
8545 them. We only support some of the potential combinations, and we
8546 only try common ways to find suitable instructions.
8548 * addb can add two registers or a register and a small integer
8549 and jump to a nearby (+-8k) location. Normally the jump to the
8550 nearby location is conditional on the result of the add, but by
8551 using the "true" condition we can make the jump unconditional.
8552 Thus addb can perform two independent operations in one insn.
8554 * movb is similar to addb in that it can perform a reg->reg
8555 or small immediate->reg copy and jump to a nearby (+-8k location).
8557 * fmpyadd and fmpysub can perform a FP multiply and either an
8558 FP add or FP sub if the operands of the multiply and add/sub are
8559 independent (there are other minor restrictions). Note both
8560 the fmpy and fadd/fsub can in theory move to better spots according
8561 to data dependencies, but for now we require the fmpy stay at a
8564 * Many of the memory operations can perform pre & post updates
8565 of index registers. GCC's pre/post increment/decrement addressing
8566 is far too simple to take advantage of all the possibilities. This
8567 pass may not be suitable since those insns may not be independent.
8569 * comclr can compare two ints or an int and a register, nullify
8570 the following instruction and zero some other register. This
8571 is more difficult to use as it's harder to find an insn which
8572 will generate a comclr than finding something like an unconditional
8573 branch. (conditional moves & long branches create comclr insns).
8575 * Most arithmetic operations can conditionally skip the next
8576 instruction. They can be viewed as "perform this operation
8577 and conditionally jump to this nearby location" (where nearby
8578 is an insns away). These are difficult to use due to the
8579 branch length restrictions. */
8582 pa_combine_instructions (void)
8586 /* This can get expensive since the basic algorithm is on the
8587 order of O(n^2) (or worse). Only do it for -O2 or higher
8588 levels of optimization. */
8592 /* Walk down the list of insns looking for "anchor" insns which
8593 may be combined with "floating" insns. As the name implies,
8594 "anchor" instructions don't move, while "floating" insns may
8596 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8597 new = make_insn_raw (new);
8599 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8601 enum attr_pa_combine_type anchor_attr;
8602 enum attr_pa_combine_type floater_attr;
8604 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8605 Also ignore any special USE insns. */
8606 if ((GET_CODE (anchor) != INSN
8607 && GET_CODE (anchor) != JUMP_INSN
8608 && GET_CODE (anchor) != CALL_INSN)
8609 || GET_CODE (PATTERN (anchor)) == USE
8610 || GET_CODE (PATTERN (anchor)) == CLOBBER
8611 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8612 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8615 anchor_attr = get_attr_pa_combine_type (anchor);
8616 /* See if anchor is an insn suitable for combination. */
8617 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8618 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8619 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8620 && ! forward_branch_p (anchor)))
8624 for (floater = PREV_INSN (anchor);
8626 floater = PREV_INSN (floater))
8628 if (GET_CODE (floater) == NOTE
8629 || (GET_CODE (floater) == INSN
8630 && (GET_CODE (PATTERN (floater)) == USE
8631 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8634 /* Anything except a regular INSN will stop our search. */
8635 if (GET_CODE (floater) != INSN
8636 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8637 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8643 /* See if FLOATER is suitable for combination with the
8645 floater_attr = get_attr_pa_combine_type (floater);
8646 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8647 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8648 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8649 && floater_attr == PA_COMBINE_TYPE_FMPY))
8651 /* If ANCHOR and FLOATER can be combined, then we're
8652 done with this pass. */
8653 if (pa_can_combine_p (new, anchor, floater, 0,
8654 SET_DEST (PATTERN (floater)),
8655 XEXP (SET_SRC (PATTERN (floater)), 0),
8656 XEXP (SET_SRC (PATTERN (floater)), 1)))
8660 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8661 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8663 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8665 if (pa_can_combine_p (new, anchor, floater, 0,
8666 SET_DEST (PATTERN (floater)),
8667 XEXP (SET_SRC (PATTERN (floater)), 0),
8668 XEXP (SET_SRC (PATTERN (floater)), 1)))
8673 if (pa_can_combine_p (new, anchor, floater, 0,
8674 SET_DEST (PATTERN (floater)),
8675 SET_SRC (PATTERN (floater)),
8676 SET_SRC (PATTERN (floater))))
8682 /* If we didn't find anything on the backwards scan try forwards. */
8684 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8685 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8687 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8689 if (GET_CODE (floater) == NOTE
8690 || (GET_CODE (floater) == INSN
8691 && (GET_CODE (PATTERN (floater)) == USE
8692 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8696 /* Anything except a regular INSN will stop our search. */
8697 if (GET_CODE (floater) != INSN
8698 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8699 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8705 /* See if FLOATER is suitable for combination with the
8707 floater_attr = get_attr_pa_combine_type (floater);
8708 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8709 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8710 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8711 && floater_attr == PA_COMBINE_TYPE_FMPY))
8713 /* If ANCHOR and FLOATER can be combined, then we're
8714 done with this pass. */
8715 if (pa_can_combine_p (new, anchor, floater, 1,
8716 SET_DEST (PATTERN (floater)),
8717 XEXP (SET_SRC (PATTERN (floater)),
8719 XEXP (SET_SRC (PATTERN (floater)),
8726 /* FLOATER will be nonzero if we found a suitable floating
8727 insn for combination with ANCHOR. */
8729 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8730 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8732 /* Emit the new instruction and delete the old anchor. */
8733 emit_insn_before (gen_rtx_PARALLEL
8735 gen_rtvec (2, PATTERN (anchor),
8736 PATTERN (floater))),
8739 PUT_CODE (anchor, NOTE);
8740 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8741 NOTE_SOURCE_FILE (anchor) = 0;
8743 /* Emit a special USE insn for FLOATER, then delete
8744 the floating insn. */
8745 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8746 delete_insn (floater);
8751 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8754 /* Emit the new_jump instruction and delete the old anchor. */
8756 = emit_jump_insn_before (gen_rtx_PARALLEL
8758 gen_rtvec (2, PATTERN (anchor),
8759 PATTERN (floater))),
8762 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8763 PUT_CODE (anchor, NOTE);
8764 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8765 NOTE_SOURCE_FILE (anchor) = 0;
8767 /* Emit a special USE insn for FLOATER, then delete
8768 the floating insn. */
8769 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8770 delete_insn (floater);
8778 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8781 int insn_code_number;
8784 /* Create a PARALLEL with the patterns of ANCHOR and
8785 FLOATER, try to recognize it, then test constraints
8786 for the resulting pattern.
8788 If the pattern doesn't match or the constraints
8789 aren't met keep searching for a suitable floater
8791 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8792 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8793 INSN_CODE (new) = -1;
8794 insn_code_number = recog_memoized (new);
8795 if (insn_code_number < 0
8796 || (extract_insn (new), ! constrain_operands (1)))
8810 /* There's up to three operands to consider. One
8811 output and two inputs.
8813 The output must not be used between FLOATER & ANCHOR
8814 exclusive. The inputs must not be set between
8815 FLOATER and ANCHOR exclusive. */
8817 if (reg_used_between_p (dest, start, end))
8820 if (reg_set_between_p (src1, start, end))
8823 if (reg_set_between_p (src2, start, end))
8826 /* If we get here, then everything is good. */
8830 /* Return nonzero if references for INSN are delayed.
8832 Millicode insns are actually function calls with some special
8833 constraints on arguments and register usage.
8835 Millicode calls always expect their arguments in the integer argument
8836 registers, and always return their result in %r29 (ret1). They
8837 are expected to clobber their arguments, %r1, %r29, and the return
8838 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8840 This function tells reorg that the references to arguments and
8841 millicode calls do not appear to happen until after the millicode call.
8842 This allows reorg to put insns which set the argument registers into the
8843 delay slot of the millicode call -- thus they act more like traditional
8846 Note we can not consider side effects of the insn to be delayed because
8847 the branch and link insn will clobber the return pointer. If we happened
8848 to use the return pointer in the delay slot of the call, then we lose.
8850 get_attr_type will try to recognize the given insn, so make sure to
8851 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8854 insn_refs_are_delayed (rtx insn)
8856 return ((GET_CODE (insn) == INSN
8857 && GET_CODE (PATTERN (insn)) != SEQUENCE
8858 && GET_CODE (PATTERN (insn)) != USE
8859 && GET_CODE (PATTERN (insn)) != CLOBBER
8860 && get_attr_type (insn) == TYPE_MILLI));
8863 /* On the HP-PA the value is found in register(s) 28(-29), unless
8864 the mode is SF or DF. Then the value is returned in fr4 (32).
8866 This must perform the same promotions as PROMOTE_MODE, else
8867 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8869 Small structures must be returned in a PARALLEL on PA64 in order
8870 to match the HP Compiler ABI. */
8873 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8875 enum machine_mode valmode;
8877 /* Aggregates with a size less than or equal to 128 bits are returned
8878 in GR 28(-29). They are left justified. The pad bits are undefined.
8879 Larger aggregates are returned in memory. */
8880 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8884 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8886 for (i = 0; i < ub; i++)
8888 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8889 gen_rtx_REG (DImode, 28 + i),
8894 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8897 if ((INTEGRAL_TYPE_P (valtype)
8898 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8899 || POINTER_TYPE_P (valtype))
8900 valmode = word_mode;
8902 valmode = TYPE_MODE (valtype);
8904 if (TREE_CODE (valtype) == REAL_TYPE
8905 && TYPE_MODE (valtype) != TFmode
8906 && !TARGET_SOFT_FLOAT)
8907 return gen_rtx_REG (valmode, 32);
8909 return gen_rtx_REG (valmode, 28);
8912 /* Return the location of a parameter that is passed in a register or NULL
8913 if the parameter has any component that is passed in memory.
8915 This is new code and will be pushed to into the net sources after
8918 ??? We might want to restructure this so that it looks more like other
8921 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8922 int named ATTRIBUTE_UNUSED)
8924 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8931 if (mode == VOIDmode)
8934 arg_size = FUNCTION_ARG_SIZE (mode, type);
8936 /* If this arg would be passed partially or totally on the stack, then
8937 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8938 handle arguments which are split between regs and stack slots if
8939 the ABI mandates split arguments. */
8942 /* The 32-bit ABI does not split arguments. */
8943 if (cum->words + arg_size > max_arg_words)
8949 alignment = cum->words & 1;
8950 if (cum->words + alignment >= max_arg_words)
8954 /* The 32bit ABIs and the 64bit ABIs are rather different,
8955 particularly in their handling of FP registers. We might
8956 be able to cleverly share code between them, but I'm not
8957 going to bother in the hope that splitting them up results
8958 in code that is more easily understood. */
8962 /* Advance the base registers to their current locations.
8964 Remember, gprs grow towards smaller register numbers while
8965 fprs grow to higher register numbers. Also remember that
8966 although FP regs are 32-bit addressable, we pretend that
8967 the registers are 64-bits wide. */
8968 gpr_reg_base = 26 - cum->words;
8969 fpr_reg_base = 32 + cum->words;
8971 /* Arguments wider than one word and small aggregates need special
8975 || (type && AGGREGATE_TYPE_P (type)))
8977 /* Double-extended precision (80-bit), quad-precision (128-bit)
8978 and aggregates including complex numbers are aligned on
8979 128-bit boundaries. The first eight 64-bit argument slots
8980 are associated one-to-one, with general registers r26
8981 through r19, and also with floating-point registers fr4
8982 through fr11. Arguments larger than one word are always
8983 passed in general registers.
8985 Using a PARALLEL with a word mode register results in left
8986 justified data on a big-endian target. */
8989 int i, offset = 0, ub = arg_size;
8991 /* Align the base register. */
8992 gpr_reg_base -= alignment;
8994 ub = MIN (ub, max_arg_words - cum->words - alignment);
8995 for (i = 0; i < ub; i++)
8997 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8998 gen_rtx_REG (DImode, gpr_reg_base),
9004 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9009 /* If the argument is larger than a word, then we know precisely
9010 which registers we must use. */
9024 /* Structures 5 to 8 bytes in size are passed in the general
9025 registers in the same manner as other non floating-point
9026 objects. The data is right-justified and zero-extended
9027 to 64 bits. This is opposite to the normal justification
9028 used on big endian targets and requires special treatment.
9029 We now define BLOCK_REG_PADDING to pad these objects. */
9030 if (mode == BLKmode)
9032 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9033 gen_rtx_REG (DImode, gpr_reg_base),
9035 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
9040 /* We have a single word (32 bits). A simple computation
9041 will get us the register #s we need. */
9042 gpr_reg_base = 26 - cum->words;
9043 fpr_reg_base = 32 + 2 * cum->words;
9047 /* Determine if the argument needs to be passed in both general and
9048 floating point registers. */
9049 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9050 /* If we are doing soft-float with portable runtime, then there
9051 is no need to worry about FP regs. */
9052 && !TARGET_SOFT_FLOAT
9053 /* The parameter must be some kind of float, else we can just
9054 pass it in integer registers. */
9055 && FLOAT_MODE_P (mode)
9056 /* The target function must not have a prototype. */
9057 && cum->nargs_prototype <= 0
9058 /* libcalls do not need to pass items in both FP and general
9060 && type != NULL_TREE
9061 /* All this hair applies to "outgoing" args only. This includes
9062 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9064 /* Also pass outgoing floating arguments in both registers in indirect
9065 calls with the 32 bit ABI and the HP assembler since there is no
9066 way to the specify argument locations in static functions. */
9071 && FLOAT_MODE_P (mode)))
9077 gen_rtx_EXPR_LIST (VOIDmode,
9078 gen_rtx_REG (mode, fpr_reg_base),
9080 gen_rtx_EXPR_LIST (VOIDmode,
9081 gen_rtx_REG (mode, gpr_reg_base),
9086 /* See if we should pass this parameter in a general register. */
9087 if (TARGET_SOFT_FLOAT
9088 /* Indirect calls in the normal 32bit ABI require all arguments
9089 to be passed in general registers. */
9090 || (!TARGET_PORTABLE_RUNTIME
9094 /* If the parameter is not a floating point parameter, then
9095 it belongs in GPRs. */
9096 || !FLOAT_MODE_P (mode))
9097 retval = gen_rtx_REG (mode, gpr_reg_base);
9099 retval = gen_rtx_REG (mode, fpr_reg_base);
9105 /* If this arg would be passed totally in registers or totally on the stack,
9106 then this routine should return zero. It is currently called only for
9107 the 64-bit target. */
9109 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9110 tree type, int named ATTRIBUTE_UNUSED)
9112 unsigned int max_arg_words = 8;
9113 unsigned int offset = 0;
9115 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9118 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9119 /* Arg fits fully into registers. */
9121 else if (cum->words + offset >= max_arg_words)
9122 /* Arg fully on the stack. */
9126 return max_arg_words - cum->words - offset;
9130 /* Return 1 if this is a comparison operator. This allows the use of
9131 MATCH_OPERATOR to recognize all the branch insns. */
9134 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9136 return ((mode == VOIDmode || GET_MODE (op) == mode)
9137 && (GET_CODE (op) == EQ
9138 || GET_CODE (op) == NE
9139 || GET_CODE (op) == GT
9140 || GET_CODE (op) == GTU
9141 || GET_CODE (op) == GE
9142 || GET_CODE (op) == LT
9143 || GET_CODE (op) == LE
9144 || GET_CODE (op) == LEU));
9147 /* On hpux10, the linker will give an error if we have a reference
9148 in the read-only data section to a symbol defined in a shared
9149 library. Therefore, expressions that might require a reloc can
9150 not be placed in the read-only data section. */
9153 pa_select_section (tree exp, int reloc,
9154 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9156 if (TREE_CODE (exp) == VAR_DECL
9157 && TREE_READONLY (exp)
9158 && !TREE_THIS_VOLATILE (exp)
9159 && DECL_INITIAL (exp)
9160 && (DECL_INITIAL (exp) == error_mark_node
9161 || TREE_CONSTANT (DECL_INITIAL (exp)))
9163 readonly_data_section ();
9164 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
9166 readonly_data_section ();
9172 pa_globalize_label (FILE *stream, const char *name)
9174 /* We only handle DATA objects here, functions are globalized in
9175 ASM_DECLARE_FUNCTION_NAME. */
9176 if (! FUNCTION_NAME_P (name))
9178 fputs ("\t.EXPORT ", stream);
9179 assemble_name (stream, name);
9180 fputs (",DATA\n", stream);
9184 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9187 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9188 int incoming ATTRIBUTE_UNUSED)
9190 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9193 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9196 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9198 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9199 PA64 ABI says that objects larger than 128 bits are returned in memory.
9200 Note, int_size_in_bytes can return -1 if the size of the object is
9201 variable or larger than the maximum value that can be expressed as
9202 a HOST_WIDE_INT. It can also return zero for an empty type. The
9203 simplest way to handle variable and empty types is to pass them in
9204 memory. This avoids problems in defining the boundaries of argument
9205 slots, allocating registers, etc. */
9206 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9207 || int_size_in_bytes (type) <= 0);