1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
52 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
54 /* Return nonzero if there is a bypass for the output of
55 OUT_INSN and the fp store IN_INSN. */
57 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
59 enum machine_mode store_mode;
60 enum machine_mode other_mode;
63 if (recog_memoized (in_insn) < 0
64 || get_attr_type (in_insn) != TYPE_FPSTORE
65 || recog_memoized (out_insn) < 0)
68 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
70 set = single_set (out_insn);
74 other_mode = GET_MODE (SET_SRC (set));
76 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
80 #ifndef DO_FRAME_NOTES
81 #ifdef INCOMING_RETURN_ADDR_RTX
82 #define DO_FRAME_NOTES 1
84 #define DO_FRAME_NOTES 0
88 static void copy_reg_pointer (rtx, rtx);
89 static int hppa_address_cost (rtx);
90 static bool hppa_rtx_costs (rtx, int, int, int *);
91 static inline rtx force_mode (enum machine_mode, rtx);
92 static void pa_reorg (void);
93 static void pa_combine_instructions (void);
94 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
95 static int forward_branch_p (rtx);
96 static int shadd_constant_p (int);
97 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
98 static int compute_movmem_length (rtx);
99 static int compute_clrmem_length (rtx);
100 static bool pa_assemble_integer (rtx, unsigned int, int);
101 static void remove_useless_addtr_insns (int);
102 static void store_reg (int, HOST_WIDE_INT, int);
103 static void store_reg_modify (int, int, HOST_WIDE_INT);
104 static void load_reg (int, HOST_WIDE_INT, int);
105 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
106 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
107 static void update_total_code_bytes (int);
108 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
109 static int pa_adjust_cost (rtx, rtx, rtx, int);
110 static int pa_adjust_priority (rtx, int);
111 static int pa_issue_rate (void);
112 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
114 static void pa_encode_section_info (tree, rtx, int);
115 static const char *pa_strip_name_encoding (const char *);
116 static bool pa_function_ok_for_sibcall (tree, tree);
117 static void pa_globalize_label (FILE *, const char *)
119 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
120 HOST_WIDE_INT, tree);
121 #if !defined(USE_COLLECT2)
122 static void pa_asm_out_constructor (rtx, int);
123 static void pa_asm_out_destructor (rtx, int);
125 static void pa_init_builtins (void);
126 static rtx hppa_builtin_saveregs (void);
127 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
128 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
129 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
130 static struct deferred_plabel *get_plabel (const char *)
132 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
134 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
135 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
136 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
139 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
140 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
141 static void output_deferred_plabels (void);
142 #ifdef HPUX_LONG_DOUBLE_LIBRARY
143 static void pa_hpux_init_libfuncs (void);
145 static rtx pa_struct_value_rtx (tree, int);
147 /* Save the operands last given to a compare for use when we
148 generate a scc or bcc insn. */
149 rtx hppa_compare_op0, hppa_compare_op1;
150 enum cmp_type hppa_branch_type;
152 /* Which cpu we are scheduling for. */
153 enum processor_type pa_cpu;
155 /* String to hold which cpu we are scheduling for. */
156 const char *pa_cpu_string;
158 /* Which architecture we are generating code for. */
159 enum architecture_type pa_arch;
161 /* String to hold which architecture we are generating code for. */
162 const char *pa_arch_string;
164 /* Counts for the number of callee-saved general and floating point
165 registers which were saved by the current function's prologue. */
166 static int gr_saved, fr_saved;
168 static rtx find_addr_reg (rtx);
170 /* Keep track of the number of bytes we have output in the CODE subspace
171 during this compilation so we'll know when to emit inline long-calls. */
172 unsigned long total_code_bytes;
174 /* The last address of the previous function plus the number of bytes in
175 associated thunks that have been output. This is used to determine if
176 a thunk can use an IA-relative branch to reach its target function. */
177 static int last_address;
179 /* Variables to handle plabels that we discover are necessary at assembly
180 output time. They are output after the current function. */
181 struct deferred_plabel GTY(())
186 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
188 static size_t n_deferred_plabels = 0;
191 /* Initialize the GCC target structure. */
193 #undef TARGET_ASM_ALIGNED_HI_OP
194 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
195 #undef TARGET_ASM_ALIGNED_SI_OP
196 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
197 #undef TARGET_ASM_ALIGNED_DI_OP
198 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
199 #undef TARGET_ASM_UNALIGNED_HI_OP
200 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
201 #undef TARGET_ASM_UNALIGNED_SI_OP
202 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
203 #undef TARGET_ASM_UNALIGNED_DI_OP
204 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
205 #undef TARGET_ASM_INTEGER
206 #define TARGET_ASM_INTEGER pa_assemble_integer
208 #undef TARGET_ASM_FUNCTION_PROLOGUE
209 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
210 #undef TARGET_ASM_FUNCTION_EPILOGUE
211 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
213 #undef TARGET_SCHED_ADJUST_COST
214 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
215 #undef TARGET_SCHED_ADJUST_PRIORITY
216 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
217 #undef TARGET_SCHED_ISSUE_RATE
218 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
220 #undef TARGET_ENCODE_SECTION_INFO
221 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
222 #undef TARGET_STRIP_NAME_ENCODING
223 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
225 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
226 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
228 #undef TARGET_ASM_OUTPUT_MI_THUNK
229 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
230 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
231 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
233 #undef TARGET_ASM_FILE_END
234 #define TARGET_ASM_FILE_END output_deferred_plabels
236 #if !defined(USE_COLLECT2)
237 #undef TARGET_ASM_CONSTRUCTOR
238 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
239 #undef TARGET_ASM_DESTRUCTOR
240 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
243 #undef TARGET_INIT_BUILTINS
244 #define TARGET_INIT_BUILTINS pa_init_builtins
246 #undef TARGET_RTX_COSTS
247 #define TARGET_RTX_COSTS hppa_rtx_costs
248 #undef TARGET_ADDRESS_COST
249 #define TARGET_ADDRESS_COST hppa_address_cost
251 #undef TARGET_MACHINE_DEPENDENT_REORG
252 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
254 #ifdef HPUX_LONG_DOUBLE_LIBRARY
255 #undef TARGET_INIT_LIBFUNCS
256 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
259 #undef TARGET_PROMOTE_FUNCTION_RETURN
260 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
261 #undef TARGET_PROMOTE_PROTOTYPES
262 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
264 #undef TARGET_STRUCT_VALUE_RTX
265 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
266 #undef TARGET_RETURN_IN_MEMORY
267 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
269 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
270 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
271 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
272 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
274 struct gcc_target targetm = TARGET_INITIALIZER;
277 override_options (void)
279 if (pa_cpu_string == NULL)
280 pa_cpu_string = TARGET_SCHED_DEFAULT;
282 if (! strcmp (pa_cpu_string, "8000"))
284 pa_cpu_string = "8000";
285 pa_cpu = PROCESSOR_8000;
287 else if (! strcmp (pa_cpu_string, "7100"))
289 pa_cpu_string = "7100";
290 pa_cpu = PROCESSOR_7100;
292 else if (! strcmp (pa_cpu_string, "700"))
294 pa_cpu_string = "700";
295 pa_cpu = PROCESSOR_700;
297 else if (! strcmp (pa_cpu_string, "7100LC"))
299 pa_cpu_string = "7100LC";
300 pa_cpu = PROCESSOR_7100LC;
302 else if (! strcmp (pa_cpu_string, "7200"))
304 pa_cpu_string = "7200";
305 pa_cpu = PROCESSOR_7200;
307 else if (! strcmp (pa_cpu_string, "7300"))
309 pa_cpu_string = "7300";
310 pa_cpu = PROCESSOR_7300;
314 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
317 /* Set the instruction set architecture. */
318 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
320 pa_arch_string = "1.0";
321 pa_arch = ARCHITECTURE_10;
322 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
324 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
326 pa_arch_string = "1.1";
327 pa_arch = ARCHITECTURE_11;
328 target_flags &= ~MASK_PA_20;
329 target_flags |= MASK_PA_11;
331 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
333 pa_arch_string = "2.0";
334 pa_arch = ARCHITECTURE_20;
335 target_flags |= MASK_PA_11 | MASK_PA_20;
337 else if (pa_arch_string)
339 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
342 /* Unconditional branches in the delay slot are not compatible with dwarf2
343 call frame information. There is no benefit in using this optimization
344 on PA8000 and later processors. */
345 if (pa_cpu >= PROCESSOR_8000
346 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
347 || flag_unwind_tables)
348 target_flags &= ~MASK_JUMP_IN_DELAY;
350 if (flag_pic && TARGET_PORTABLE_RUNTIME)
352 warning ("PIC code generation is not supported in the portable runtime model\n");
355 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
357 warning ("PIC code generation is not compatible with fast indirect calls\n");
360 if (! TARGET_GAS && write_symbols != NO_DEBUG)
362 warning ("-g is only supported when using GAS on this processor,");
363 warning ("-g option disabled");
364 write_symbols = NO_DEBUG;
367 /* We only support the "big PIC" model now. And we always generate PIC
368 code when in 64bit mode. */
369 if (flag_pic == 1 || TARGET_64BIT)
372 /* We can't guarantee that .dword is available for 32-bit targets. */
373 if (UNITS_PER_WORD == 4)
374 targetm.asm_out.aligned_op.di = NULL;
376 /* The unaligned ops are only available when using GAS. */
379 targetm.asm_out.unaligned_op.hi = NULL;
380 targetm.asm_out.unaligned_op.si = NULL;
381 targetm.asm_out.unaligned_op.di = NULL;
386 pa_init_builtins (void)
388 #ifdef DONT_HAVE_FPUTC_UNLOCKED
389 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
390 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
394 /* If FROM is a probable pointer register, mark TO as a probable
395 pointer register with the same pointer alignment as FROM. */
398 copy_reg_pointer (rtx to, rtx from)
400 if (REG_POINTER (from))
401 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
404 /* Return nonzero only if OP is a register of mode MODE,
407 reg_or_0_operand (rtx op, enum machine_mode mode)
409 return (op == CONST0_RTX (mode) || register_operand (op, mode));
412 /* Return nonzero if OP is suitable for use in a call to a named
415 For 2.5 try to eliminate either call_operand_address or
416 function_label_operand, they perform very similar functions. */
418 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
420 return (GET_MODE (op) == word_mode
421 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
424 /* Return 1 if X contains a symbolic expression. We know these
425 expressions will have one of a few well defined forms, so
426 we need only check those forms. */
428 symbolic_expression_p (rtx x)
431 /* Strip off any HIGH. */
432 if (GET_CODE (x) == HIGH)
435 return (symbolic_operand (x, VOIDmode));
439 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
441 switch (GET_CODE (op))
448 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
449 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
450 && GET_CODE (XEXP (op, 1)) == CONST_INT);
456 /* Return truth value of statement that OP is a symbolic memory
457 operand of mode MODE. */
460 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
462 if (GET_CODE (op) == SUBREG)
463 op = SUBREG_REG (op);
464 if (GET_CODE (op) != MEM)
467 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
468 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
471 /* Return 1 if the operand is either a register, zero, or a memory operand
472 that is not symbolic. */
475 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
477 if (register_operand (op, mode))
480 if (op == CONST0_RTX (mode))
483 if (GET_CODE (op) == SUBREG)
484 op = SUBREG_REG (op);
486 if (GET_CODE (op) != MEM)
489 /* Until problems with management of the REG_POINTER flag are resolved,
490 we need to delay creating move insns with unscaled indexed addresses
491 until CSE is not expected. */
492 if (!TARGET_NO_SPACE_REGS
494 && GET_CODE (XEXP (op, 0)) == PLUS
495 && REG_P (XEXP (XEXP (op, 0), 0))
496 && REG_P (XEXP (XEXP (op, 0), 1)))
499 return (!symbolic_memory_operand (op, mode)
500 && memory_address_p (mode, XEXP (op, 0)));
503 /* Return 1 if the operand is a register operand or a non-symbolic memory
504 operand after reload. This predicate is used for branch patterns that
505 internally handle register reloading. We need to accept non-symbolic
506 memory operands after reload to ensure that the pattern is still valid
507 if reload didn't find a hard register for the operand. */
510 reg_before_reload_operand (rtx op, enum machine_mode mode)
512 /* Don't accept a SUBREG since it will need a reload. */
513 if (GET_CODE (op) == SUBREG)
516 if (register_operand (op, mode))
520 && memory_operand (op, mode)
521 && !symbolic_memory_operand (op, mode))
527 /* Accept any constant that can be moved in one instruction into a
530 cint_ok_for_move (HOST_WIDE_INT intval)
532 /* OK if ldo, ldil, or zdepi, can be used. */
533 return (CONST_OK_FOR_LETTER_P (intval, 'J')
534 || CONST_OK_FOR_LETTER_P (intval, 'N')
535 || CONST_OK_FOR_LETTER_P (intval, 'K'));
538 /* Return 1 iff OP is an indexed memory operand. */
540 indexed_memory_operand (rtx op, enum machine_mode mode)
542 if (GET_MODE (op) != mode)
545 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
546 if (reload_completed && GET_CODE (op) == SUBREG)
547 op = SUBREG_REG (op);
549 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
554 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
557 /* Accept anything that can be used as a destination operand for a
558 move instruction. We don't accept indexed memory operands since
559 they are supported only for floating point stores. */
561 move_dest_operand (rtx op, enum machine_mode mode)
563 if (register_operand (op, mode))
566 if (GET_MODE (op) != mode)
569 if (GET_CODE (op) == SUBREG)
570 op = SUBREG_REG (op);
572 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
577 return (memory_address_p (mode, op)
578 && !IS_INDEX_ADDR_P (op)
579 && !IS_LO_SUM_DLT_ADDR_P (op));
582 /* Accept anything that can be used as a source operand for a move
585 move_src_operand (rtx op, enum machine_mode mode)
587 if (register_operand (op, mode))
590 if (GET_CODE (op) == CONST_INT)
591 return cint_ok_for_move (INTVAL (op));
593 if (GET_MODE (op) != mode)
596 if (GET_CODE (op) == SUBREG)
597 op = SUBREG_REG (op);
599 if (GET_CODE (op) != MEM)
602 /* Until problems with management of the REG_POINTER flag are resolved,
603 we need to delay creating move insns with unscaled indexed addresses
604 until CSE is not expected. */
605 if (!TARGET_NO_SPACE_REGS
607 && GET_CODE (XEXP (op, 0)) == PLUS
608 && REG_P (XEXP (XEXP (op, 0), 0))
609 && REG_P (XEXP (XEXP (op, 0), 1)))
612 return memory_address_p (mode, XEXP (op, 0));
615 /* Accept anything that can be used as the source operand for a prefetch
618 prefetch_operand (rtx op, enum machine_mode mode)
620 if (GET_CODE (op) != MEM)
623 /* Until problems with management of the REG_POINTER flag are resolved,
624 we need to delay creating prefetch insns with unscaled indexed addresses
625 until CSE is not expected. */
626 if (!TARGET_NO_SPACE_REGS
628 && GET_CODE (XEXP (op, 0)) == PLUS
629 && REG_P (XEXP (XEXP (op, 0), 0))
630 && REG_P (XEXP (XEXP (op, 0), 1)))
633 return memory_address_p (mode, XEXP (op, 0));
636 /* Accept REG and any CONST_INT that can be moved in one instruction into a
639 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
641 if (register_operand (op, mode))
644 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
648 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
653 switch (GET_CODE (op))
659 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
660 && GET_CODE (XEXP (op, 1)) == CONST_INT);
667 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
669 return reg_renumber && FP_REG_P (op);
674 /* Return truth value of whether OP can be used as an operand in a
675 three operand arithmetic insn that accepts registers of mode MODE
676 or 14-bit signed integers. */
678 arith_operand (rtx op, enum machine_mode mode)
680 return (register_operand (op, mode)
681 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
684 /* Return truth value of whether OP can be used as an operand in a
685 three operand arithmetic insn that accepts registers of mode MODE
686 or 11-bit signed integers. */
688 arith11_operand (rtx op, enum machine_mode mode)
690 return (register_operand (op, mode)
691 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
694 /* Return truth value of whether OP can be used as an operand in a
697 adddi3_operand (rtx op, enum machine_mode mode)
699 return (register_operand (op, mode)
700 || (GET_CODE (op) == CONST_INT
701 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
704 /* A constant integer suitable for use in a PRE_MODIFY memory
707 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
709 return (GET_CODE (op) == CONST_INT
710 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
713 /* A constant integer suitable for use in a POST_MODIFY memory
716 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
718 return (GET_CODE (op) == CONST_INT
719 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
723 arith_double_operand (rtx op, enum machine_mode mode)
725 return (register_operand (op, mode)
726 || (GET_CODE (op) == CONST_DOUBLE
727 && GET_MODE (op) == mode
728 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
729 && ((CONST_DOUBLE_HIGH (op) >= 0)
730 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
733 /* Return truth value of whether OP is an integer which fits the
734 range constraining immediate operands in three-address insns, or
735 is an integer register. */
738 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
740 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
741 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
744 /* Return nonzero if OP is an integer register, else return zero. */
746 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
748 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
751 /* Return truth value of whether OP is an integer which fits the
752 range constraining immediate operands in three-address insns. */
755 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
757 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
761 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
763 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
767 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
769 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
773 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
775 #if HOST_BITS_PER_WIDE_INT > 32
776 /* All allowed constants will fit a CONST_INT. */
777 return (GET_CODE (op) == CONST_INT
778 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
780 return (GET_CODE (op) == CONST_INT
781 || (GET_CODE (op) == CONST_DOUBLE
782 && CONST_DOUBLE_HIGH (op) == 0));
787 arith5_operand (rtx op, enum machine_mode mode)
789 return register_operand (op, mode) || int5_operand (op, mode);
792 /* True iff zdepi can be used to generate this CONST_INT.
793 zdepi first sign extends a 5 bit signed number to a given field
794 length, then places this field anywhere in a zero. */
796 zdepi_cint_p (unsigned HOST_WIDE_INT x)
798 unsigned HOST_WIDE_INT lsb_mask, t;
800 /* This might not be obvious, but it's at least fast.
801 This function is critical; we don't have the time loops would take. */
803 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
804 /* Return true iff t is a power of two. */
805 return ((t & (t - 1)) == 0);
808 /* True iff depi or extru can be used to compute (reg & mask).
809 Accept bit pattern like these:
814 and_mask_p (unsigned HOST_WIDE_INT mask)
817 mask += mask & -mask;
818 return (mask & (mask - 1)) == 0;
821 /* True iff depi or extru can be used to compute (reg & OP). */
823 and_operand (rtx op, enum machine_mode mode)
825 return (register_operand (op, mode)
826 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
829 /* True iff depi can be used to compute (reg | MASK). */
831 ior_mask_p (unsigned HOST_WIDE_INT mask)
833 mask += mask & -mask;
834 return (mask & (mask - 1)) == 0;
837 /* True iff depi can be used to compute (reg | OP). */
839 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
841 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
845 lhs_lshift_operand (rtx op, enum machine_mode mode)
847 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
850 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
851 Such values can be the left hand side x in (x << r), using the zvdepi
854 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
856 unsigned HOST_WIDE_INT x;
857 if (GET_CODE (op) != CONST_INT)
859 x = INTVAL (op) >> 4;
860 return (x & (x + 1)) == 0;
864 arith32_operand (rtx op, enum machine_mode mode)
866 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
870 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
872 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
875 /* Legitimize PIC addresses. If the address is already
876 position-independent, we return ORIG. Newly generated
877 position-independent addresses go to REG. If we need more
878 than one register, we lose. */
881 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
885 /* Labels need special handling. */
886 if (pic_label_operand (orig, mode))
888 /* We do not want to go through the movXX expanders here since that
889 would create recursion.
891 Nor do we really want to call a generator for a named pattern
892 since that requires multiple patterns if we want to support
895 So instead we just emit the raw set, which avoids the movXX
896 expanders completely. */
897 mark_reg_pointer (reg, BITS_PER_UNIT);
898 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
899 current_function_uses_pic_offset_table = 1;
902 if (GET_CODE (orig) == SYMBOL_REF)
909 /* Before reload, allocate a temporary register for the intermediate
910 result. This allows the sequence to be deleted when the final
911 result is unused and the insns are trivially dead. */
912 tmp_reg = ((reload_in_progress || reload_completed)
913 ? reg : gen_reg_rtx (Pmode));
915 emit_move_insn (tmp_reg,
916 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
917 gen_rtx_HIGH (word_mode, orig)));
919 = gen_rtx_MEM (Pmode,
920 gen_rtx_LO_SUM (Pmode, tmp_reg,
921 gen_rtx_UNSPEC (Pmode,
925 current_function_uses_pic_offset_table = 1;
926 MEM_NOTRAP_P (pic_ref) = 1;
927 RTX_UNCHANGING_P (pic_ref) = 1;
928 mark_reg_pointer (reg, BITS_PER_UNIT);
929 insn = emit_move_insn (reg, pic_ref);
931 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
932 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
936 else if (GET_CODE (orig) == CONST)
940 if (GET_CODE (XEXP (orig, 0)) == PLUS
941 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
947 if (GET_CODE (XEXP (orig, 0)) == PLUS)
949 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
950 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
951 base == reg ? 0 : reg);
956 if (GET_CODE (orig) == CONST_INT)
958 if (INT_14_BITS (orig))
959 return plus_constant (base, INTVAL (orig));
960 orig = force_reg (Pmode, orig);
962 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
963 /* Likewise, should we set special REG_NOTEs here? */
969 /* Try machine-dependent ways of modifying an illegitimate address
970 to be legitimate. If we find one, return the new, valid address.
971 This macro is used in only one place: `memory_address' in explow.c.
973 OLDX is the address as it was before break_out_memory_refs was called.
974 In some cases it is useful to look at this to decide what needs to be done.
976 MODE and WIN are passed so that this macro can use
977 GO_IF_LEGITIMATE_ADDRESS.
979 It is always safe for this macro to do nothing. It exists to recognize
980 opportunities to optimize the output.
982 For the PA, transform:
984 memory(X + <large int>)
988 if (<large int> & mask) >= 16
989 Y = (<large int> & ~mask) + mask + 1 Round up.
991 Y = (<large int> & ~mask) Round down.
993 memory (Z + (<large int> - Y));
995 This is for CSE to find several similar references, and only use one Z.
997 X can either be a SYMBOL_REF or REG, but because combine can not
998 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
999 D will not fit in 14 bits.
1001 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1004 MODE_INT references allow displacements which fit in 14 bits, so use
1007 This relies on the fact that most mode MODE_FLOAT references will use FP
1008 registers and most mode MODE_INT references will use integer registers.
1009 (In the rare case of an FP register used in an integer MODE, we depend
1010 on secondary reloads to clean things up.)
1013 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1014 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1015 addressing modes to be used).
1017 Put X and Z into registers. Then put the entire expression into
1021 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1022 enum machine_mode mode)
1026 /* We need to canonicalize the order of operands in unscaled indexed
1027 addresses since the code that checks if an address is valid doesn't
1028 always try both orders. */
1029 if (!TARGET_NO_SPACE_REGS
1030 && GET_CODE (x) == PLUS
1031 && GET_MODE (x) == Pmode
1032 && REG_P (XEXP (x, 0))
1033 && REG_P (XEXP (x, 1))
1034 && REG_POINTER (XEXP (x, 0))
1035 && !REG_POINTER (XEXP (x, 1)))
1036 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1039 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1041 /* Strip off CONST. */
1042 if (GET_CODE (x) == CONST)
1045 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1046 That should always be safe. */
1047 if (GET_CODE (x) == PLUS
1048 && GET_CODE (XEXP (x, 0)) == REG
1049 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1051 rtx reg = force_reg (Pmode, XEXP (x, 1));
1052 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1055 /* Note we must reject symbols which represent function addresses
1056 since the assembler/linker can't handle arithmetic on plabels. */
1057 if (GET_CODE (x) == PLUS
1058 && GET_CODE (XEXP (x, 1)) == CONST_INT
1059 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1060 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1061 || GET_CODE (XEXP (x, 0)) == REG))
1063 rtx int_part, ptr_reg;
1065 int offset = INTVAL (XEXP (x, 1));
1068 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1069 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1071 /* Choose which way to round the offset. Round up if we
1072 are >= halfway to the next boundary. */
1073 if ((offset & mask) >= ((mask + 1) / 2))
1074 newoffset = (offset & ~ mask) + mask + 1;
1076 newoffset = (offset & ~ mask);
1078 /* If the newoffset will not fit in 14 bits (ldo), then
1079 handling this would take 4 or 5 instructions (2 to load
1080 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1081 add the new offset and the SYMBOL_REF.) Combine can
1082 not handle 4->2 or 5->2 combinations, so do not create
1084 if (! VAL_14_BITS_P (newoffset)
1085 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1087 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1090 gen_rtx_HIGH (Pmode, const_part));
1093 gen_rtx_LO_SUM (Pmode,
1094 tmp_reg, const_part));
1098 if (! VAL_14_BITS_P (newoffset))
1099 int_part = force_reg (Pmode, GEN_INT (newoffset));
1101 int_part = GEN_INT (newoffset);
1103 ptr_reg = force_reg (Pmode,
1104 gen_rtx_PLUS (Pmode,
1105 force_reg (Pmode, XEXP (x, 0)),
1108 return plus_constant (ptr_reg, offset - newoffset);
1111 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1113 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1114 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1115 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1116 && (OBJECT_P (XEXP (x, 1))
1117 || GET_CODE (XEXP (x, 1)) == SUBREG)
1118 && GET_CODE (XEXP (x, 1)) != CONST)
1120 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1124 if (GET_CODE (reg1) != REG)
1125 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1127 reg2 = XEXP (XEXP (x, 0), 0);
1128 if (GET_CODE (reg2) != REG)
1129 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1131 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1132 gen_rtx_MULT (Pmode,
1138 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1140 Only do so for floating point modes since this is more speculative
1141 and we lose if it's an integer store. */
1142 if (GET_CODE (x) == PLUS
1143 && GET_CODE (XEXP (x, 0)) == PLUS
1144 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1145 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1146 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1147 && (mode == SFmode || mode == DFmode))
1150 /* First, try and figure out what to use as a base register. */
1151 rtx reg1, reg2, base, idx, orig_base;
1153 reg1 = XEXP (XEXP (x, 0), 1);
1158 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1159 then emit_move_sequence will turn on REG_POINTER so we'll know
1160 it's a base register below. */
1161 if (GET_CODE (reg1) != REG)
1162 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1164 if (GET_CODE (reg2) != REG)
1165 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1167 /* Figure out what the base and index are. */
1169 if (GET_CODE (reg1) == REG
1170 && REG_POINTER (reg1))
1173 orig_base = XEXP (XEXP (x, 0), 1);
1174 idx = gen_rtx_PLUS (Pmode,
1175 gen_rtx_MULT (Pmode,
1176 XEXP (XEXP (XEXP (x, 0), 0), 0),
1177 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1180 else if (GET_CODE (reg2) == REG
1181 && REG_POINTER (reg2))
1184 orig_base = XEXP (x, 1);
1191 /* If the index adds a large constant, try to scale the
1192 constant so that it can be loaded with only one insn. */
1193 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1194 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1195 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1196 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1198 /* Divide the CONST_INT by the scale factor, then add it to A. */
1199 int val = INTVAL (XEXP (idx, 1));
1201 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1202 reg1 = XEXP (XEXP (idx, 0), 0);
1203 if (GET_CODE (reg1) != REG)
1204 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1206 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1208 /* We can now generate a simple scaled indexed address. */
1211 (Pmode, gen_rtx_PLUS (Pmode,
1212 gen_rtx_MULT (Pmode, reg1,
1213 XEXP (XEXP (idx, 0), 1)),
1217 /* If B + C is still a valid base register, then add them. */
1218 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1219 && INTVAL (XEXP (idx, 1)) <= 4096
1220 && INTVAL (XEXP (idx, 1)) >= -4096)
1222 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1225 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1227 reg2 = XEXP (XEXP (idx, 0), 0);
1228 if (GET_CODE (reg2) != CONST_INT)
1229 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1231 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1232 gen_rtx_MULT (Pmode,
1238 /* Get the index into a register, then add the base + index and
1239 return a register holding the result. */
1241 /* First get A into a register. */
1242 reg1 = XEXP (XEXP (idx, 0), 0);
1243 if (GET_CODE (reg1) != REG)
1244 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1246 /* And get B into a register. */
1247 reg2 = XEXP (idx, 1);
1248 if (GET_CODE (reg2) != REG)
1249 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1251 reg1 = force_reg (Pmode,
1252 gen_rtx_PLUS (Pmode,
1253 gen_rtx_MULT (Pmode, reg1,
1254 XEXP (XEXP (idx, 0), 1)),
1257 /* Add the result to our base register and return. */
1258 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1262 /* Uh-oh. We might have an address for x[n-100000]. This needs
1263 special handling to avoid creating an indexed memory address
1264 with x-100000 as the base.
1266 If the constant part is small enough, then it's still safe because
1267 there is a guard page at the beginning and end of the data segment.
1269 Scaled references are common enough that we want to try and rearrange the
1270 terms so that we can use indexing for these addresses too. Only
1271 do the optimization for floatint point modes. */
1273 if (GET_CODE (x) == PLUS
1274 && symbolic_expression_p (XEXP (x, 1)))
1276 /* Ugly. We modify things here so that the address offset specified
1277 by the index expression is computed first, then added to x to form
1278 the entire address. */
1280 rtx regx1, regx2, regy1, regy2, y;
1282 /* Strip off any CONST. */
1284 if (GET_CODE (y) == CONST)
1287 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1289 /* See if this looks like
1290 (plus (mult (reg) (shadd_const))
1291 (const (plus (symbol_ref) (const_int))))
1293 Where const_int is small. In that case the const
1294 expression is a valid pointer for indexing.
1296 If const_int is big, but can be divided evenly by shadd_const
1297 and added to (reg). This allows more scaled indexed addresses. */
1298 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1299 && GET_CODE (XEXP (x, 0)) == MULT
1300 && GET_CODE (XEXP (y, 1)) == CONST_INT
1301 && INTVAL (XEXP (y, 1)) >= -4096
1302 && INTVAL (XEXP (y, 1)) <= 4095
1303 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1304 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1306 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1310 if (GET_CODE (reg1) != REG)
1311 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1313 reg2 = XEXP (XEXP (x, 0), 0);
1314 if (GET_CODE (reg2) != REG)
1315 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1317 return force_reg (Pmode,
1318 gen_rtx_PLUS (Pmode,
1319 gen_rtx_MULT (Pmode,
1324 else if ((mode == DFmode || mode == SFmode)
1325 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1326 && GET_CODE (XEXP (x, 0)) == MULT
1327 && GET_CODE (XEXP (y, 1)) == CONST_INT
1328 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1329 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1330 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1333 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1334 / INTVAL (XEXP (XEXP (x, 0), 1))));
1335 regx2 = XEXP (XEXP (x, 0), 0);
1336 if (GET_CODE (regx2) != REG)
1337 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1338 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1342 gen_rtx_PLUS (Pmode,
1343 gen_rtx_MULT (Pmode, regx2,
1344 XEXP (XEXP (x, 0), 1)),
1345 force_reg (Pmode, XEXP (y, 0))));
1347 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1348 && INTVAL (XEXP (y, 1)) >= -4096
1349 && INTVAL (XEXP (y, 1)) <= 4095)
1351 /* This is safe because of the guard page at the
1352 beginning and end of the data space. Just
1353 return the original address. */
1358 /* Doesn't look like one we can optimize. */
1359 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1360 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1361 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1362 regx1 = force_reg (Pmode,
1363 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1365 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1373 /* For the HPPA, REG and REG+CONST is cost 0
1374 and addresses involving symbolic constants are cost 2.
1376 PIC addresses are very expensive.
1378 It is no coincidence that this has the same structure
1379 as GO_IF_LEGITIMATE_ADDRESS. */
1382 hppa_address_cost (rtx X)
1384 switch (GET_CODE (X))
1397 /* Compute a (partial) cost for rtx X. Return true if the complete
1398 cost has been computed, and false if subexpressions should be
1399 scanned. In either case, *TOTAL contains the cost result. */
1402 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1407 if (INTVAL (x) == 0)
1409 else if (INT_14_BITS (x))
1426 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1427 && outer_code != SET)
1434 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1435 *total = COSTS_N_INSNS (3);
1436 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1437 *total = COSTS_N_INSNS (8);
1439 *total = COSTS_N_INSNS (20);
1443 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1445 *total = COSTS_N_INSNS (14);
1453 *total = COSTS_N_INSNS (60);
1456 case PLUS: /* this includes shNadd insns */
1458 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1459 *total = COSTS_N_INSNS (3);
1461 *total = COSTS_N_INSNS (1);
1467 *total = COSTS_N_INSNS (1);
1475 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1476 new rtx with the correct mode. */
1478 force_mode (enum machine_mode mode, rtx orig)
1480 if (mode == GET_MODE (orig))
1483 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1486 return gen_rtx_REG (mode, REGNO (orig));
1489 /* Emit insns to move operands[1] into operands[0].
1491 Return 1 if we have written out everything that needs to be done to
1492 do the move. Otherwise, return 0 and the caller will emit the move
1495 Note SCRATCH_REG may not be in the proper mode depending on how it
1496 will be used. This routine is responsible for creating a new copy
1497 of SCRATCH_REG in the proper mode. */
1500 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1502 register rtx operand0 = operands[0];
1503 register rtx operand1 = operands[1];
1506 /* We can only handle indexed addresses in the destination operand
1507 of floating point stores. Thus, we need to break out indexed
1508 addresses from the destination operand. */
1509 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1511 /* This is only safe up to the beginning of life analysis. */
1515 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1516 operand0 = replace_equiv_address (operand0, tem);
1519 /* On targets with non-equivalent space registers, break out unscaled
1520 indexed addresses from the source operand before the final CSE.
1521 We have to do this because the REG_POINTER flag is not correctly
1522 carried through various optimization passes and CSE may substitute
1523 a pseudo without the pointer set for one with the pointer set. As
1524 a result, we loose various opportunities to create insns with
1525 unscaled indexed addresses. */
1526 if (!TARGET_NO_SPACE_REGS
1527 && !cse_not_expected
1528 && GET_CODE (operand1) == MEM
1529 && GET_CODE (XEXP (operand1, 0)) == PLUS
1530 && REG_P (XEXP (XEXP (operand1, 0), 0))
1531 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1533 = replace_equiv_address (operand1,
1534 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1537 && reload_in_progress && GET_CODE (operand0) == REG
1538 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1539 operand0 = reg_equiv_mem[REGNO (operand0)];
1540 else if (scratch_reg
1541 && reload_in_progress && GET_CODE (operand0) == SUBREG
1542 && GET_CODE (SUBREG_REG (operand0)) == REG
1543 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1545 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1546 the code which tracks sets/uses for delete_output_reload. */
1547 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1548 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1549 SUBREG_BYTE (operand0));
1550 operand0 = alter_subreg (&temp);
1554 && reload_in_progress && GET_CODE (operand1) == REG
1555 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1556 operand1 = reg_equiv_mem[REGNO (operand1)];
1557 else if (scratch_reg
1558 && reload_in_progress && GET_CODE (operand1) == SUBREG
1559 && GET_CODE (SUBREG_REG (operand1)) == REG
1560 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1562 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1563 the code which tracks sets/uses for delete_output_reload. */
1564 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1565 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1566 SUBREG_BYTE (operand1));
1567 operand1 = alter_subreg (&temp);
1570 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1571 && ((tem = find_replacement (&XEXP (operand0, 0)))
1572 != XEXP (operand0, 0)))
1573 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1575 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1576 && ((tem = find_replacement (&XEXP (operand1, 0)))
1577 != XEXP (operand1, 0)))
1578 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1580 /* Handle secondary reloads for loads/stores of FP registers from
1581 REG+D addresses where D does not fit in 5 or 14 bits, including
1582 (subreg (mem (addr))) cases. */
1584 && fp_reg_operand (operand0, mode)
1585 && ((GET_CODE (operand1) == MEM
1586 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1587 XEXP (operand1, 0)))
1588 || ((GET_CODE (operand1) == SUBREG
1589 && GET_CODE (XEXP (operand1, 0)) == MEM
1590 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1592 XEXP (XEXP (operand1, 0), 0))))))
1594 if (GET_CODE (operand1) == SUBREG)
1595 operand1 = XEXP (operand1, 0);
1597 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1598 it in WORD_MODE regardless of what mode it was originally given
1600 scratch_reg = force_mode (word_mode, scratch_reg);
1602 /* D might not fit in 14 bits either; for such cases load D into
1604 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1606 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1607 emit_move_insn (scratch_reg,
1608 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1610 XEXP (XEXP (operand1, 0), 0),
1614 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1615 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1616 gen_rtx_MEM (mode, scratch_reg)));
1619 else if (scratch_reg
1620 && fp_reg_operand (operand1, mode)
1621 && ((GET_CODE (operand0) == MEM
1622 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1624 XEXP (operand0, 0)))
1625 || ((GET_CODE (operand0) == SUBREG)
1626 && GET_CODE (XEXP (operand0, 0)) == MEM
1627 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1629 XEXP (XEXP (operand0, 0), 0)))))
1631 if (GET_CODE (operand0) == SUBREG)
1632 operand0 = XEXP (operand0, 0);
1634 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1635 it in WORD_MODE regardless of what mode it was originally given
1637 scratch_reg = force_mode (word_mode, scratch_reg);
1639 /* D might not fit in 14 bits either; for such cases load D into
1641 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1643 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1644 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1647 XEXP (XEXP (operand0, 0),
1652 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1653 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1657 /* Handle secondary reloads for loads of FP registers from constant
1658 expressions by forcing the constant into memory.
1660 Use scratch_reg to hold the address of the memory location.
1662 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1663 NO_REGS when presented with a const_int and a register class
1664 containing only FP registers. Doing so unfortunately creates
1665 more problems than it solves. Fix this for 2.5. */
1666 else if (scratch_reg
1667 && CONSTANT_P (operand1)
1668 && fp_reg_operand (operand0, mode))
1672 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1673 it in WORD_MODE regardless of what mode it was originally given
1675 scratch_reg = force_mode (word_mode, scratch_reg);
1677 /* Force the constant into memory and put the address of the
1678 memory location into scratch_reg. */
1679 xoperands[0] = scratch_reg;
1680 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1681 emit_move_sequence (xoperands, Pmode, 0);
1683 /* Now load the destination register. */
1684 emit_insn (gen_rtx_SET (mode, operand0,
1685 gen_rtx_MEM (mode, scratch_reg)));
1688 /* Handle secondary reloads for SAR. These occur when trying to load
1689 the SAR from memory, FP register, or with a constant. */
1690 else if (scratch_reg
1691 && GET_CODE (operand0) == REG
1692 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1693 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1694 && (GET_CODE (operand1) == MEM
1695 || GET_CODE (operand1) == CONST_INT
1696 || (GET_CODE (operand1) == REG
1697 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1699 /* D might not fit in 14 bits either; for such cases load D into
1701 if (GET_CODE (operand1) == MEM
1702 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1704 /* We are reloading the address into the scratch register, so we
1705 want to make sure the scratch register is a full register. */
1706 scratch_reg = force_mode (word_mode, scratch_reg);
1708 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1709 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1712 XEXP (XEXP (operand1, 0),
1716 /* Now we are going to load the scratch register from memory,
1717 we want to load it in the same width as the original MEM,
1718 which must be the same as the width of the ultimate destination,
1720 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1722 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1727 /* We want to load the scratch register using the same mode as
1728 the ultimate destination. */
1729 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1731 emit_move_insn (scratch_reg, operand1);
1734 /* And emit the insn to set the ultimate destination. We know that
1735 the scratch register has the same mode as the destination at this
1737 emit_move_insn (operand0, scratch_reg);
1740 /* Handle the most common case: storing into a register. */
1741 else if (register_operand (operand0, mode))
1743 if (register_operand (operand1, mode)
1744 || (GET_CODE (operand1) == CONST_INT
1745 && cint_ok_for_move (INTVAL (operand1)))
1746 || (operand1 == CONST0_RTX (mode))
1747 || (GET_CODE (operand1) == HIGH
1748 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1749 /* Only `general_operands' can come here, so MEM is ok. */
1750 || GET_CODE (operand1) == MEM)
1752 /* Various sets are created during RTL generation which don't
1753 have the REG_POINTER flag correctly set. After the CSE pass,
1754 instruction recognition can fail if we don't consistently
1755 set this flag when performing register copies. This should
1756 also improve the opportunities for creating insns that use
1757 unscaled indexing. */
1758 if (REG_P (operand0) && REG_P (operand1))
1760 if (REG_POINTER (operand1)
1761 && !REG_POINTER (operand0)
1762 && !HARD_REGISTER_P (operand0))
1763 copy_reg_pointer (operand0, operand1);
1764 else if (REG_POINTER (operand0)
1765 && !REG_POINTER (operand1)
1766 && !HARD_REGISTER_P (operand1))
1767 copy_reg_pointer (operand1, operand0);
1770 /* When MEMs are broken out, the REG_POINTER flag doesn't
1771 get set. In some cases, we can set the REG_POINTER flag
1772 from the declaration for the MEM. */
1773 if (REG_P (operand0)
1774 && GET_CODE (operand1) == MEM
1775 && !REG_POINTER (operand0))
1777 tree decl = MEM_EXPR (operand1);
1779 /* Set the register pointer flag and register alignment
1780 if the declaration for this memory reference is a
1781 pointer type. Fortran indirect argument references
1784 && !(flag_argument_noalias > 1
1785 && TREE_CODE (decl) == INDIRECT_REF
1786 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1790 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1792 if (TREE_CODE (decl) == COMPONENT_REF)
1793 decl = TREE_OPERAND (decl, 1);
1795 type = TREE_TYPE (decl);
1796 if (TREE_CODE (type) == ARRAY_TYPE)
1797 type = get_inner_array_type (type);
1799 if (POINTER_TYPE_P (type))
1803 type = TREE_TYPE (type);
1804 /* Using TYPE_ALIGN_OK is rather conservative as
1805 only the ada frontend actually sets it. */
1806 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1808 mark_reg_pointer (operand0, align);
1813 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1817 else if (GET_CODE (operand0) == MEM)
1819 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1820 && !(reload_in_progress || reload_completed))
1822 rtx temp = gen_reg_rtx (DFmode);
1824 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1825 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1828 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1830 /* Run this case quickly. */
1831 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1834 if (! (reload_in_progress || reload_completed))
1836 operands[0] = validize_mem (operand0);
1837 operands[1] = operand1 = force_reg (mode, operand1);
1841 /* Simplify the source if we need to.
1842 Note we do have to handle function labels here, even though we do
1843 not consider them legitimate constants. Loop optimizations can
1844 call the emit_move_xxx with one as a source. */
1845 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1846 || function_label_operand (operand1, mode)
1847 || (GET_CODE (operand1) == HIGH
1848 && symbolic_operand (XEXP (operand1, 0), mode)))
1852 if (GET_CODE (operand1) == HIGH)
1855 operand1 = XEXP (operand1, 0);
1857 if (symbolic_operand (operand1, mode))
1859 /* Argh. The assembler and linker can't handle arithmetic
1862 So we force the plabel into memory, load operand0 from
1863 the memory location, then add in the constant part. */
1864 if ((GET_CODE (operand1) == CONST
1865 && GET_CODE (XEXP (operand1, 0)) == PLUS
1866 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1867 || function_label_operand (operand1, mode))
1869 rtx temp, const_part;
1871 /* Figure out what (if any) scratch register to use. */
1872 if (reload_in_progress || reload_completed)
1874 scratch_reg = scratch_reg ? scratch_reg : operand0;
1875 /* SCRATCH_REG will hold an address and maybe the actual
1876 data. We want it in WORD_MODE regardless of what mode it
1877 was originally given to us. */
1878 scratch_reg = force_mode (word_mode, scratch_reg);
1881 scratch_reg = gen_reg_rtx (Pmode);
1883 if (GET_CODE (operand1) == CONST)
1885 /* Save away the constant part of the expression. */
1886 const_part = XEXP (XEXP (operand1, 0), 1);
1887 if (GET_CODE (const_part) != CONST_INT)
1890 /* Force the function label into memory. */
1891 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1895 /* No constant part. */
1896 const_part = NULL_RTX;
1898 /* Force the function label into memory. */
1899 temp = force_const_mem (mode, operand1);
1903 /* Get the address of the memory location. PIC-ify it if
1905 temp = XEXP (temp, 0);
1907 temp = legitimize_pic_address (temp, mode, scratch_reg);
1909 /* Put the address of the memory location into our destination
1912 emit_move_sequence (operands, mode, scratch_reg);
1914 /* Now load from the memory location into our destination
1916 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1917 emit_move_sequence (operands, mode, scratch_reg);
1919 /* And add back in the constant part. */
1920 if (const_part != NULL_RTX)
1921 expand_inc (operand0, const_part);
1930 if (reload_in_progress || reload_completed)
1932 temp = scratch_reg ? scratch_reg : operand0;
1933 /* TEMP will hold an address and maybe the actual
1934 data. We want it in WORD_MODE regardless of what mode it
1935 was originally given to us. */
1936 temp = force_mode (word_mode, temp);
1939 temp = gen_reg_rtx (Pmode);
1941 /* (const (plus (symbol) (const_int))) must be forced to
1942 memory during/after reload if the const_int will not fit
1944 if (GET_CODE (operand1) == CONST
1945 && GET_CODE (XEXP (operand1, 0)) == PLUS
1946 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1947 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1948 && (reload_completed || reload_in_progress)
1951 operands[1] = force_const_mem (mode, operand1);
1952 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1954 operands[1] = gen_rtx_MEM (mode, operands[1]);
1955 emit_move_sequence (operands, mode, temp);
1959 operands[1] = legitimize_pic_address (operand1, mode, temp);
1960 if (REG_P (operand0) && REG_P (operands[1]))
1961 copy_reg_pointer (operand0, operands[1]);
1962 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1965 /* On the HPPA, references to data space are supposed to use dp,
1966 register 27, but showing it in the RTL inhibits various cse
1967 and loop optimizations. */
1972 if (reload_in_progress || reload_completed)
1974 temp = scratch_reg ? scratch_reg : operand0;
1975 /* TEMP will hold an address and maybe the actual
1976 data. We want it in WORD_MODE regardless of what mode it
1977 was originally given to us. */
1978 temp = force_mode (word_mode, temp);
1981 temp = gen_reg_rtx (mode);
1983 /* Loading a SYMBOL_REF into a register makes that register
1984 safe to be used as the base in an indexed address.
1986 Don't mark hard registers though. That loses. */
1987 if (GET_CODE (operand0) == REG
1988 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1989 mark_reg_pointer (operand0, BITS_PER_UNIT);
1990 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1991 mark_reg_pointer (temp, BITS_PER_UNIT);
1994 set = gen_rtx_SET (mode, operand0, temp);
1996 set = gen_rtx_SET (VOIDmode,
1998 gen_rtx_LO_SUM (mode, temp, operand1));
2000 emit_insn (gen_rtx_SET (VOIDmode,
2002 gen_rtx_HIGH (mode, operand1)));
2008 else if (GET_CODE (operand1) != CONST_INT
2009 || !cint_ok_for_move (INTVAL (operand1)))
2013 HOST_WIDE_INT value = 0;
2014 HOST_WIDE_INT insv = 0;
2017 if (GET_CODE (operand1) == CONST_INT)
2018 value = INTVAL (operand1);
2021 && GET_CODE (operand1) == CONST_INT
2022 && HOST_BITS_PER_WIDE_INT > 32
2023 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2027 /* Extract the low order 32 bits of the value and sign extend.
2028 If the new value is the same as the original value, we can
2029 can use the original value as-is. If the new value is
2030 different, we use it and insert the most-significant 32-bits
2031 of the original value into the final result. */
2032 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2033 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2036 #if HOST_BITS_PER_WIDE_INT > 32
2037 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2041 operand1 = GEN_INT (nval);
2045 if (reload_in_progress || reload_completed)
2046 temp = scratch_reg ? scratch_reg : operand0;
2048 temp = gen_reg_rtx (mode);
2050 /* We don't directly split DImode constants on 32-bit targets
2051 because PLUS uses an 11-bit immediate and the insn sequence
2052 generated is not as efficient as the one using HIGH/LO_SUM. */
2053 if (GET_CODE (operand1) == CONST_INT
2054 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2057 /* Directly break constant into high and low parts. This
2058 provides better optimization opportunities because various
2059 passes recognize constants split with PLUS but not LO_SUM.
2060 We use a 14-bit signed low part except when the addition
2061 of 0x4000 to the high part might change the sign of the
2063 HOST_WIDE_INT low = value & 0x3fff;
2064 HOST_WIDE_INT high = value & ~ 0x3fff;
2068 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2076 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2077 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2081 emit_insn (gen_rtx_SET (VOIDmode, temp,
2082 gen_rtx_HIGH (mode, operand1)));
2083 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2086 insn = emit_move_insn (operands[0], operands[1]);
2088 /* Now insert the most significant 32 bits of the value
2089 into the register. When we don't have a second register
2090 available, it could take up to nine instructions to load
2091 a 64-bit integer constant. Prior to reload, we force
2092 constants that would take more than three instructions
2093 to load to the constant pool. During and after reload,
2094 we have to handle all possible values. */
2097 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2098 register and the value to be inserted is outside the
2099 range that can be loaded with three depdi instructions. */
2100 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2102 operand1 = GEN_INT (insv);
2104 emit_insn (gen_rtx_SET (VOIDmode, temp,
2105 gen_rtx_HIGH (mode, operand1)));
2106 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2107 emit_insn (gen_insv (operand0, GEN_INT (32),
2112 int len = 5, pos = 27;
2114 /* Insert the bits using the depdi instruction. */
2117 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2118 HOST_WIDE_INT sign = v5 < 0;
2120 /* Left extend the insertion. */
2121 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2122 while (pos > 0 && (insv & 1) == sign)
2124 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2129 emit_insn (gen_insv (operand0, GEN_INT (len),
2130 GEN_INT (pos), GEN_INT (v5)));
2132 len = pos > 0 && pos < 5 ? pos : 5;
2139 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2144 /* Now have insn-emit do whatever it normally does. */
2148 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2149 it will need a link/runtime reloc). */
2152 reloc_needed (tree exp)
2156 switch (TREE_CODE (exp))
2163 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2164 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2169 case NON_LVALUE_EXPR:
2170 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2176 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2177 if (TREE_VALUE (link) != 0)
2178 reloc |= reloc_needed (TREE_VALUE (link));
2191 /* Does operand (which is a symbolic_operand) live in text space?
2192 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2196 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2198 if (GET_CODE (operand) == CONST)
2199 operand = XEXP (XEXP (operand, 0), 0);
2202 if (GET_CODE (operand) == SYMBOL_REF)
2203 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2207 if (GET_CODE (operand) == SYMBOL_REF)
2208 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2214 /* Return the best assembler insn template
2215 for moving operands[1] into operands[0] as a fullword. */
2217 singlemove_string (rtx *operands)
2219 HOST_WIDE_INT intval;
2221 if (GET_CODE (operands[0]) == MEM)
2222 return "stw %r1,%0";
2223 if (GET_CODE (operands[1]) == MEM)
2225 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2230 if (GET_MODE (operands[1]) != SFmode)
2233 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2235 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2236 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2238 operands[1] = GEN_INT (i);
2239 /* Fall through to CONST_INT case. */
2241 if (GET_CODE (operands[1]) == CONST_INT)
2243 intval = INTVAL (operands[1]);
2245 if (VAL_14_BITS_P (intval))
2247 else if ((intval & 0x7ff) == 0)
2248 return "ldil L'%1,%0";
2249 else if (zdepi_cint_p (intval))
2250 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2252 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2254 return "copy %1,%0";
2258 /* Compute position (in OP[1]) and width (in OP[2])
2259 useful for copying IMM to a register using the zdepi
2260 instructions. Store the immediate value to insert in OP[0]. */
2262 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2266 /* Find the least significant set bit in IMM. */
2267 for (lsb = 0; lsb < 32; lsb++)
2274 /* Choose variants based on *sign* of the 5-bit field. */
2275 if ((imm & 0x10) == 0)
2276 len = (lsb <= 28) ? 4 : 32 - lsb;
2279 /* Find the width of the bitstring in IMM. */
2280 for (len = 5; len < 32; len++)
2282 if ((imm & (1 << len)) == 0)
2286 /* Sign extend IMM as a 5-bit value. */
2287 imm = (imm & 0xf) - 0x10;
2295 /* Compute position (in OP[1]) and width (in OP[2])
2296 useful for copying IMM to a register using the depdi,z
2297 instructions. Store the immediate value to insert in OP[0]. */
2299 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2301 HOST_WIDE_INT lsb, len;
2303 /* Find the least significant set bit in IMM. */
2304 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2311 /* Choose variants based on *sign* of the 5-bit field. */
2312 if ((imm & 0x10) == 0)
2313 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2314 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2317 /* Find the width of the bitstring in IMM. */
2318 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2320 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2324 /* Sign extend IMM as a 5-bit value. */
2325 imm = (imm & 0xf) - 0x10;
2333 /* Output assembler code to perform a doubleword move insn
2334 with operands OPERANDS. */
2337 output_move_double (rtx *operands)
2339 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2341 rtx addreg0 = 0, addreg1 = 0;
2343 /* First classify both operands. */
2345 if (REG_P (operands[0]))
2347 else if (offsettable_memref_p (operands[0]))
2349 else if (GET_CODE (operands[0]) == MEM)
2354 if (REG_P (operands[1]))
2356 else if (CONSTANT_P (operands[1]))
2358 else if (offsettable_memref_p (operands[1]))
2360 else if (GET_CODE (operands[1]) == MEM)
2365 /* Check for the cases that the operand constraints are not
2366 supposed to allow to happen. Abort if we get one,
2367 because generating code for these cases is painful. */
2369 if (optype0 != REGOP && optype1 != REGOP)
2372 /* Handle auto decrementing and incrementing loads and stores
2373 specifically, since the structure of the function doesn't work
2374 for them without major modification. Do it better when we learn
2375 this port about the general inc/dec addressing of PA.
2376 (This was written by tege. Chide him if it doesn't work.) */
2378 if (optype0 == MEMOP)
2380 /* We have to output the address syntax ourselves, since print_operand
2381 doesn't deal with the addresses we want to use. Fix this later. */
2383 rtx addr = XEXP (operands[0], 0);
2384 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2386 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2388 operands[0] = XEXP (addr, 0);
2389 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2392 if (!reg_overlap_mentioned_p (high_reg, addr))
2394 /* No overlap between high target register and address
2395 register. (We do this in a non-obvious way to
2396 save a register file writeback) */
2397 if (GET_CODE (addr) == POST_INC)
2398 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2399 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2404 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2406 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2408 operands[0] = XEXP (addr, 0);
2409 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2412 if (!reg_overlap_mentioned_p (high_reg, addr))
2414 /* No overlap between high target register and address
2415 register. (We do this in a non-obvious way to
2416 save a register file writeback) */
2417 if (GET_CODE (addr) == PRE_INC)
2418 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2419 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2425 if (optype1 == MEMOP)
2427 /* We have to output the address syntax ourselves, since print_operand
2428 doesn't deal with the addresses we want to use. Fix this later. */
2430 rtx addr = XEXP (operands[1], 0);
2431 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2433 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2435 operands[1] = XEXP (addr, 0);
2436 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2439 if (!reg_overlap_mentioned_p (high_reg, addr))
2441 /* No overlap between high target register and address
2442 register. (We do this in a non-obvious way to
2443 save a register file writeback) */
2444 if (GET_CODE (addr) == POST_INC)
2445 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2446 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2450 /* This is an undefined situation. We should load into the
2451 address register *and* update that register. Probably
2452 we don't need to handle this at all. */
2453 if (GET_CODE (addr) == POST_INC)
2454 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2455 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2458 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2460 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2462 operands[1] = XEXP (addr, 0);
2463 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2466 if (!reg_overlap_mentioned_p (high_reg, addr))
2468 /* No overlap between high target register and address
2469 register. (We do this in a non-obvious way to
2470 save a register file writeback) */
2471 if (GET_CODE (addr) == PRE_INC)
2472 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2473 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2477 /* This is an undefined situation. We should load into the
2478 address register *and* update that register. Probably
2479 we don't need to handle this at all. */
2480 if (GET_CODE (addr) == PRE_INC)
2481 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2482 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2485 else if (GET_CODE (addr) == PLUS
2486 && GET_CODE (XEXP (addr, 0)) == MULT)
2488 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2490 if (!reg_overlap_mentioned_p (high_reg, addr))
2494 xoperands[0] = high_reg;
2495 xoperands[1] = XEXP (addr, 1);
2496 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2497 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2498 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2500 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2506 xoperands[0] = high_reg;
2507 xoperands[1] = XEXP (addr, 1);
2508 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2509 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2510 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2512 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2517 /* If an operand is an unoffsettable memory ref, find a register
2518 we can increment temporarily to make it refer to the second word. */
2520 if (optype0 == MEMOP)
2521 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2523 if (optype1 == MEMOP)
2524 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2526 /* Ok, we can do one word at a time.
2527 Normally we do the low-numbered word first.
2529 In either case, set up in LATEHALF the operands to use
2530 for the high-numbered word and in some cases alter the
2531 operands in OPERANDS to be suitable for the low-numbered word. */
2533 if (optype0 == REGOP)
2534 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2535 else if (optype0 == OFFSOP)
2536 latehalf[0] = adjust_address (operands[0], SImode, 4);
2538 latehalf[0] = operands[0];
2540 if (optype1 == REGOP)
2541 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2542 else if (optype1 == OFFSOP)
2543 latehalf[1] = adjust_address (operands[1], SImode, 4);
2544 else if (optype1 == CNSTOP)
2545 split_double (operands[1], &operands[1], &latehalf[1]);
2547 latehalf[1] = operands[1];
2549 /* If the first move would clobber the source of the second one,
2550 do them in the other order.
2552 This can happen in two cases:
2554 mem -> register where the first half of the destination register
2555 is the same register used in the memory's address. Reload
2556 can create such insns.
2558 mem in this case will be either register indirect or register
2559 indirect plus a valid offset.
2561 register -> register move where REGNO(dst) == REGNO(src + 1)
2562 someone (Tim/Tege?) claimed this can happen for parameter loads.
2564 Handle mem -> register case first. */
2565 if (optype0 == REGOP
2566 && (optype1 == MEMOP || optype1 == OFFSOP)
2567 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2570 /* Do the late half first. */
2572 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2573 output_asm_insn (singlemove_string (latehalf), latehalf);
2577 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2578 return singlemove_string (operands);
2581 /* Now handle register -> register case. */
2582 if (optype0 == REGOP && optype1 == REGOP
2583 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2585 output_asm_insn (singlemove_string (latehalf), latehalf);
2586 return singlemove_string (operands);
2589 /* Normal case: do the two words, low-numbered first. */
2591 output_asm_insn (singlemove_string (operands), operands);
2593 /* Make any unoffsettable addresses point at high-numbered word. */
2595 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2597 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2600 output_asm_insn (singlemove_string (latehalf), latehalf);
2602 /* Undo the adds we just did. */
2604 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2606 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2612 output_fp_move_double (rtx *operands)
2614 if (FP_REG_P (operands[0]))
2616 if (FP_REG_P (operands[1])
2617 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2618 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2620 output_asm_insn ("fldd%F1 %1,%0", operands);
2622 else if (FP_REG_P (operands[1]))
2624 output_asm_insn ("fstd%F0 %1,%0", operands);
2626 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2628 if (GET_CODE (operands[0]) == REG)
2631 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2632 xoperands[0] = operands[0];
2633 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2635 /* This is a pain. You have to be prepared to deal with an
2636 arbitrary address here including pre/post increment/decrement.
2638 so avoid this in the MD. */
2646 /* Return a REG that occurs in ADDR with coefficient 1.
2647 ADDR can be effectively incremented by incrementing REG. */
2650 find_addr_reg (rtx addr)
2652 while (GET_CODE (addr) == PLUS)
2654 if (GET_CODE (XEXP (addr, 0)) == REG)
2655 addr = XEXP (addr, 0);
2656 else if (GET_CODE (XEXP (addr, 1)) == REG)
2657 addr = XEXP (addr, 1);
2658 else if (CONSTANT_P (XEXP (addr, 0)))
2659 addr = XEXP (addr, 1);
2660 else if (CONSTANT_P (XEXP (addr, 1)))
2661 addr = XEXP (addr, 0);
2665 if (GET_CODE (addr) == REG)
2670 /* Emit code to perform a block move.
2672 OPERANDS[0] is the destination pointer as a REG, clobbered.
2673 OPERANDS[1] is the source pointer as a REG, clobbered.
2674 OPERANDS[2] is a register for temporary storage.
2675 OPERANDS[3] is a register for temporary storage.
2676 OPERANDS[4] is the size as a CONST_INT
2677 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2678 OPERANDS[6] is another temporary register. */
2681 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2683 int align = INTVAL (operands[5]);
2684 unsigned long n_bytes = INTVAL (operands[4]);
2686 /* We can't move more than a word at a time because the PA
2687 has no longer integer move insns. (Could use fp mem ops?) */
2688 if (align > (TARGET_64BIT ? 8 : 4))
2689 align = (TARGET_64BIT ? 8 : 4);
2691 /* Note that we know each loop below will execute at least twice
2692 (else we would have open-coded the copy). */
2696 /* Pre-adjust the loop counter. */
2697 operands[4] = GEN_INT (n_bytes - 16);
2698 output_asm_insn ("ldi %4,%2", operands);
2701 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2702 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2703 output_asm_insn ("std,ma %3,8(%0)", operands);
2704 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2705 output_asm_insn ("std,ma %6,8(%0)", operands);
2707 /* Handle the residual. There could be up to 7 bytes of
2708 residual to copy! */
2709 if (n_bytes % 16 != 0)
2711 operands[4] = GEN_INT (n_bytes % 8);
2712 if (n_bytes % 16 >= 8)
2713 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2714 if (n_bytes % 8 != 0)
2715 output_asm_insn ("ldd 0(%1),%6", operands);
2716 if (n_bytes % 16 >= 8)
2717 output_asm_insn ("std,ma %3,8(%0)", operands);
2718 if (n_bytes % 8 != 0)
2719 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2724 /* Pre-adjust the loop counter. */
2725 operands[4] = GEN_INT (n_bytes - 8);
2726 output_asm_insn ("ldi %4,%2", operands);
2729 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2730 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2731 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2732 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2733 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2735 /* Handle the residual. There could be up to 7 bytes of
2736 residual to copy! */
2737 if (n_bytes % 8 != 0)
2739 operands[4] = GEN_INT (n_bytes % 4);
2740 if (n_bytes % 8 >= 4)
2741 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2742 if (n_bytes % 4 != 0)
2743 output_asm_insn ("ldw 0(%1),%6", operands);
2744 if (n_bytes % 8 >= 4)
2745 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2746 if (n_bytes % 4 != 0)
2747 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2752 /* Pre-adjust the loop counter. */
2753 operands[4] = GEN_INT (n_bytes - 4);
2754 output_asm_insn ("ldi %4,%2", operands);
2757 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2758 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2759 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2760 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2761 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2763 /* Handle the residual. */
2764 if (n_bytes % 4 != 0)
2766 if (n_bytes % 4 >= 2)
2767 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2768 if (n_bytes % 2 != 0)
2769 output_asm_insn ("ldb 0(%1),%6", operands);
2770 if (n_bytes % 4 >= 2)
2771 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2772 if (n_bytes % 2 != 0)
2773 output_asm_insn ("stb %6,0(%0)", operands);
2778 /* Pre-adjust the loop counter. */
2779 operands[4] = GEN_INT (n_bytes - 2);
2780 output_asm_insn ("ldi %4,%2", operands);
2783 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2784 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2785 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2786 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2787 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2789 /* Handle the residual. */
2790 if (n_bytes % 2 != 0)
2792 output_asm_insn ("ldb 0(%1),%3", operands);
2793 output_asm_insn ("stb %3,0(%0)", operands);
2802 /* Count the number of insns necessary to handle this block move.
2804 Basic structure is the same as emit_block_move, except that we
2805 count insns rather than emit them. */
2808 compute_movmem_length (rtx insn)
2810 rtx pat = PATTERN (insn);
2811 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2812 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2813 unsigned int n_insns = 0;
2815 /* We can't move more than four bytes at a time because the PA
2816 has no longer integer move insns. (Could use fp mem ops?) */
2817 if (align > (TARGET_64BIT ? 8 : 4))
2818 align = (TARGET_64BIT ? 8 : 4);
2820 /* The basic copying loop. */
2824 if (n_bytes % (2 * align) != 0)
2826 if ((n_bytes % (2 * align)) >= align)
2829 if ((n_bytes % align) != 0)
2833 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2837 /* Emit code to perform a block clear.
2839 OPERANDS[0] is the destination pointer as a REG, clobbered.
2840 OPERANDS[1] is a register for temporary storage.
2841 OPERANDS[2] is the size as a CONST_INT
2842 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2845 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2847 int align = INTVAL (operands[3]);
2848 unsigned long n_bytes = INTVAL (operands[2]);
2850 /* We can't clear more than a word at a time because the PA
2851 has no longer integer move insns. */
2852 if (align > (TARGET_64BIT ? 8 : 4))
2853 align = (TARGET_64BIT ? 8 : 4);
2855 /* Note that we know each loop below will execute at least twice
2856 (else we would have open-coded the copy). */
2860 /* Pre-adjust the loop counter. */
2861 operands[2] = GEN_INT (n_bytes - 16);
2862 output_asm_insn ("ldi %2,%1", operands);
2865 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2866 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2867 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2869 /* Handle the residual. There could be up to 7 bytes of
2870 residual to copy! */
2871 if (n_bytes % 16 != 0)
2873 operands[2] = GEN_INT (n_bytes % 8);
2874 if (n_bytes % 16 >= 8)
2875 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2876 if (n_bytes % 8 != 0)
2877 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2882 /* Pre-adjust the loop counter. */
2883 operands[2] = GEN_INT (n_bytes - 8);
2884 output_asm_insn ("ldi %2,%1", operands);
2887 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2888 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2889 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2891 /* Handle the residual. There could be up to 7 bytes of
2892 residual to copy! */
2893 if (n_bytes % 8 != 0)
2895 operands[2] = GEN_INT (n_bytes % 4);
2896 if (n_bytes % 8 >= 4)
2897 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2898 if (n_bytes % 4 != 0)
2899 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2904 /* Pre-adjust the loop counter. */
2905 operands[2] = GEN_INT (n_bytes - 4);
2906 output_asm_insn ("ldi %2,%1", operands);
2909 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2910 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2911 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2913 /* Handle the residual. */
2914 if (n_bytes % 4 != 0)
2916 if (n_bytes % 4 >= 2)
2917 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2918 if (n_bytes % 2 != 0)
2919 output_asm_insn ("stb %%r0,0(%0)", operands);
2924 /* Pre-adjust the loop counter. */
2925 operands[2] = GEN_INT (n_bytes - 2);
2926 output_asm_insn ("ldi %2,%1", operands);
2929 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2930 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2931 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2933 /* Handle the residual. */
2934 if (n_bytes % 2 != 0)
2935 output_asm_insn ("stb %%r0,0(%0)", operands);
2944 /* Count the number of insns necessary to handle this block move.
2946 Basic structure is the same as emit_block_move, except that we
2947 count insns rather than emit them. */
2950 compute_clrmem_length (rtx insn)
2952 rtx pat = PATTERN (insn);
2953 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2954 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2955 unsigned int n_insns = 0;
2957 /* We can't clear more than a word at a time because the PA
2958 has no longer integer move insns. */
2959 if (align > (TARGET_64BIT ? 8 : 4))
2960 align = (TARGET_64BIT ? 8 : 4);
2962 /* The basic loop. */
2966 if (n_bytes % (2 * align) != 0)
2968 if ((n_bytes % (2 * align)) >= align)
2971 if ((n_bytes % align) != 0)
2975 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2981 output_and (rtx *operands)
2983 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2985 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2986 int ls0, ls1, ms0, p, len;
2988 for (ls0 = 0; ls0 < 32; ls0++)
2989 if ((mask & (1 << ls0)) == 0)
2992 for (ls1 = ls0; ls1 < 32; ls1++)
2993 if ((mask & (1 << ls1)) != 0)
2996 for (ms0 = ls1; ms0 < 32; ms0++)
2997 if ((mask & (1 << ms0)) == 0)
3010 operands[2] = GEN_INT (len);
3011 return "{extru|extrw,u} %1,31,%2,%0";
3015 /* We could use this `depi' for the case above as well, but `depi'
3016 requires one more register file access than an `extru'. */
3021 operands[2] = GEN_INT (p);
3022 operands[3] = GEN_INT (len);
3023 return "{depi|depwi} 0,%2,%3,%0";
3027 return "and %1,%2,%0";
3030 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3031 storing the result in operands[0]. */
3033 output_64bit_and (rtx *operands)
3035 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3037 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3038 int ls0, ls1, ms0, p, len;
3040 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3041 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3044 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3045 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3048 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3049 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3052 if (ms0 != HOST_BITS_PER_WIDE_INT)
3055 if (ls1 == HOST_BITS_PER_WIDE_INT)
3062 operands[2] = GEN_INT (len);
3063 return "extrd,u %1,63,%2,%0";
3067 /* We could use this `depi' for the case above as well, but `depi'
3068 requires one more register file access than an `extru'. */
3073 operands[2] = GEN_INT (p);
3074 operands[3] = GEN_INT (len);
3075 return "depdi 0,%2,%3,%0";
3079 return "and %1,%2,%0";
3083 output_ior (rtx *operands)
3085 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3086 int bs0, bs1, p, len;
3088 if (INTVAL (operands[2]) == 0)
3089 return "copy %1,%0";
3091 for (bs0 = 0; bs0 < 32; bs0++)
3092 if ((mask & (1 << bs0)) != 0)
3095 for (bs1 = bs0; bs1 < 32; bs1++)
3096 if ((mask & (1 << bs1)) == 0)
3099 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3105 operands[2] = GEN_INT (p);
3106 operands[3] = GEN_INT (len);
3107 return "{depi|depwi} -1,%2,%3,%0";
3110 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3111 storing the result in operands[0]. */
3113 output_64bit_ior (rtx *operands)
3115 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3116 int bs0, bs1, p, len;
3118 if (INTVAL (operands[2]) == 0)
3119 return "copy %1,%0";
3121 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3122 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3125 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3126 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3129 if (bs1 != HOST_BITS_PER_WIDE_INT
3130 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3136 operands[2] = GEN_INT (p);
3137 operands[3] = GEN_INT (len);
3138 return "depdi -1,%2,%3,%0";
3141 /* Target hook for assembling integer objects. This code handles
3142 aligned SI and DI integers specially, since function references must
3143 be preceded by P%. */
3146 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3148 if (size == UNITS_PER_WORD && aligned_p
3149 && function_label_operand (x, VOIDmode))
3151 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3152 output_addr_const (asm_out_file, x);
3153 fputc ('\n', asm_out_file);
3156 return default_assemble_integer (x, size, aligned_p);
3159 /* Output an ascii string. */
3161 output_ascii (FILE *file, const char *p, int size)
3165 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3167 /* The HP assembler can only take strings of 256 characters at one
3168 time. This is a limitation on input line length, *not* the
3169 length of the string. Sigh. Even worse, it seems that the
3170 restriction is in number of input characters (see \xnn &
3171 \whatever). So we have to do this very carefully. */
3173 fputs ("\t.STRING \"", file);
3176 for (i = 0; i < size; i += 4)
3180 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3182 register unsigned int c = (unsigned char) p[i + io];
3184 if (c == '\"' || c == '\\')
3185 partial_output[co++] = '\\';
3186 if (c >= ' ' && c < 0177)
3187 partial_output[co++] = c;
3191 partial_output[co++] = '\\';
3192 partial_output[co++] = 'x';
3193 hexd = c / 16 - 0 + '0';
3195 hexd -= '9' - 'a' + 1;
3196 partial_output[co++] = hexd;
3197 hexd = c % 16 - 0 + '0';
3199 hexd -= '9' - 'a' + 1;
3200 partial_output[co++] = hexd;
3203 if (chars_output + co > 243)
3205 fputs ("\"\n\t.STRING \"", file);
3208 fwrite (partial_output, 1, (size_t) co, file);
3212 fputs ("\"\n", file);
3215 /* Try to rewrite floating point comparisons & branches to avoid
3216 useless add,tr insns.
3218 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3219 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3220 first attempt to remove useless add,tr insns. It is zero
3221 for the second pass as reorg sometimes leaves bogus REG_DEAD
3224 When CHECK_NOTES is zero we can only eliminate add,tr insns
3225 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3228 remove_useless_addtr_insns (int check_notes)
3231 static int pass = 0;
3233 /* This is fairly cheap, so always run it when optimizing. */
3237 int fbranch_count = 0;
3239 /* Walk all the insns in this function looking for fcmp & fbranch
3240 instructions. Keep track of how many of each we find. */
3241 for (insn = get_insns (); insn; insn = next_insn (insn))
3245 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3246 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3249 tmp = PATTERN (insn);
3251 /* It must be a set. */
3252 if (GET_CODE (tmp) != SET)
3255 /* If the destination is CCFP, then we've found an fcmp insn. */
3256 tmp = SET_DEST (tmp);
3257 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3263 tmp = PATTERN (insn);
3264 /* If this is an fbranch instruction, bump the fbranch counter. */
3265 if (GET_CODE (tmp) == SET
3266 && SET_DEST (tmp) == pc_rtx
3267 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3268 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3269 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3270 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3278 /* Find all floating point compare + branch insns. If possible,
3279 reverse the comparison & the branch to avoid add,tr insns. */
3280 for (insn = get_insns (); insn; insn = next_insn (insn))
3284 /* Ignore anything that isn't an INSN. */
3285 if (GET_CODE (insn) != INSN)
3288 tmp = PATTERN (insn);
3290 /* It must be a set. */
3291 if (GET_CODE (tmp) != SET)
3294 /* The destination must be CCFP, which is register zero. */
3295 tmp = SET_DEST (tmp);
3296 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3299 /* INSN should be a set of CCFP.
3301 See if the result of this insn is used in a reversed FP
3302 conditional branch. If so, reverse our condition and
3303 the branch. Doing so avoids useless add,tr insns. */
3304 next = next_insn (insn);
3307 /* Jumps, calls and labels stop our search. */
3308 if (GET_CODE (next) == JUMP_INSN
3309 || GET_CODE (next) == CALL_INSN
3310 || GET_CODE (next) == CODE_LABEL)
3313 /* As does another fcmp insn. */
3314 if (GET_CODE (next) == INSN
3315 && GET_CODE (PATTERN (next)) == SET
3316 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3317 && REGNO (SET_DEST (PATTERN (next))) == 0)
3320 next = next_insn (next);
3323 /* Is NEXT_INSN a branch? */
3325 && GET_CODE (next) == JUMP_INSN)
3327 rtx pattern = PATTERN (next);
3329 /* If it a reversed fp conditional branch (eg uses add,tr)
3330 and CCFP dies, then reverse our conditional and the branch
3331 to avoid the add,tr. */
3332 if (GET_CODE (pattern) == SET
3333 && SET_DEST (pattern) == pc_rtx
3334 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3335 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3336 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3337 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3338 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3339 && (fcmp_count == fbranch_count
3341 && find_regno_note (next, REG_DEAD, 0))))
3343 /* Reverse the branch. */
3344 tmp = XEXP (SET_SRC (pattern), 1);
3345 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3346 XEXP (SET_SRC (pattern), 2) = tmp;
3347 INSN_CODE (next) = -1;
3349 /* Reverse our condition. */
3350 tmp = PATTERN (insn);
3351 PUT_CODE (XEXP (tmp, 1),
3352 (reverse_condition_maybe_unordered
3353 (GET_CODE (XEXP (tmp, 1)))));
3363 /* You may have trouble believing this, but this is the 32 bit HP-PA
3368 Variable arguments (optional; any number may be allocated)
3370 SP-(4*(N+9)) arg word N
3375 Fixed arguments (must be allocated; may remain unused)
3384 SP-32 External Data Pointer (DP)
3386 SP-24 External/stub RP (RP')
3390 SP-8 Calling Stub RP (RP'')
3395 SP-0 Stack Pointer (points to next available address)
3399 /* This function saves registers as follows. Registers marked with ' are
3400 this function's registers (as opposed to the previous function's).
3401 If a frame_pointer isn't needed, r4 is saved as a general register;
3402 the space for the frame pointer is still allocated, though, to keep
3408 SP (FP') Previous FP
3409 SP + 4 Alignment filler (sigh)
3410 SP + 8 Space for locals reserved here.
3414 SP + n All call saved register used.
3418 SP + o All call saved fp registers used.
3422 SP + p (SP') points to next available address.
3426 /* Global variables set by output_function_prologue(). */
3427 /* Size of frame. Need to know this to emit return insns from
3429 static HOST_WIDE_INT actual_fsize, local_fsize;
3430 static int save_fregs;
3432 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3433 Handle case where DISP > 8k by using the add_high_const patterns.
3435 Note in DISP > 8k case, we will leave the high part of the address
3436 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3439 store_reg (int reg, HOST_WIDE_INT disp, int base)
3441 rtx insn, dest, src, basereg;
3443 src = gen_rtx_REG (word_mode, reg);
3444 basereg = gen_rtx_REG (Pmode, base);
3445 if (VAL_14_BITS_P (disp))
3447 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3448 insn = emit_move_insn (dest, src);
3450 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3452 rtx delta = GEN_INT (disp);
3453 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3455 emit_move_insn (tmpreg, delta);
3456 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3457 dest = gen_rtx_MEM (word_mode, tmpreg);
3458 insn = emit_move_insn (dest, src);
3462 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3463 gen_rtx_SET (VOIDmode,
3464 gen_rtx_MEM (word_mode,
3465 gen_rtx_PLUS (word_mode, basereg,
3473 rtx delta = GEN_INT (disp);
3474 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3475 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3477 emit_move_insn (tmpreg, high);
3478 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3479 insn = emit_move_insn (dest, src);
3483 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3484 gen_rtx_SET (VOIDmode,
3485 gen_rtx_MEM (word_mode,
3486 gen_rtx_PLUS (word_mode, basereg,
3494 RTX_FRAME_RELATED_P (insn) = 1;
3497 /* Emit RTL to store REG at the memory location specified by BASE and then
3498 add MOD to BASE. MOD must be <= 8k. */
3501 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3503 rtx insn, basereg, srcreg, delta;
3505 if (!VAL_14_BITS_P (mod))
3508 basereg = gen_rtx_REG (Pmode, base);
3509 srcreg = gen_rtx_REG (word_mode, reg);
3510 delta = GEN_INT (mod);
3512 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3515 RTX_FRAME_RELATED_P (insn) = 1;
3517 /* RTX_FRAME_RELATED_P must be set on each frame related set
3518 in a parallel with more than one element. Don't set
3519 RTX_FRAME_RELATED_P in the first set if reg is temporary
3520 register 1. The effect of this operation is recorded in
3521 the initial copy. */
3524 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3525 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3529 /* The first element of a PARALLEL is always processed if it is
3530 a SET. Thus, we need an expression list for this case. */
3532 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3533 gen_rtx_SET (VOIDmode, basereg,
3534 gen_rtx_PLUS (word_mode, basereg, delta)),
3540 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3541 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3542 whether to add a frame note or not.
3544 In the DISP > 8k case, we leave the high part of the address in %r1.
3545 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3548 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3552 if (VAL_14_BITS_P (disp))
3554 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3555 plus_constant (gen_rtx_REG (Pmode, base), disp));
3557 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3559 rtx basereg = gen_rtx_REG (Pmode, base);
3560 rtx delta = GEN_INT (disp);
3561 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3563 emit_move_insn (tmpreg, delta);
3564 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3565 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3569 rtx basereg = gen_rtx_REG (Pmode, base);
3570 rtx delta = GEN_INT (disp);
3571 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3573 emit_move_insn (tmpreg,
3574 gen_rtx_PLUS (Pmode, basereg,
3575 gen_rtx_HIGH (Pmode, delta)));
3576 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3577 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3580 if (DO_FRAME_NOTES && note)
3581 RTX_FRAME_RELATED_P (insn) = 1;
3585 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3590 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3591 be consistent with the rounding and size calculation done here.
3592 Change them at the same time. */
3594 /* We do our own stack alignment. First, round the size of the
3595 stack locals up to a word boundary. */
3596 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3598 /* Space for previous frame pointer + filler. If any frame is
3599 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3600 waste some space here for the sake of HP compatibility. The
3601 first slot is only used when the frame pointer is needed. */
3602 if (size || frame_pointer_needed)
3603 size += STARTING_FRAME_OFFSET;
3605 /* If the current function calls __builtin_eh_return, then we need
3606 to allocate stack space for registers that will hold data for
3607 the exception handler. */
3608 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3612 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3614 size += i * UNITS_PER_WORD;
3617 /* Account for space used by the callee general register saves. */
3618 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3619 if (regs_ever_live[i])
3620 size += UNITS_PER_WORD;
3622 /* Account for space used by the callee floating point register saves. */
3623 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3624 if (regs_ever_live[i]
3625 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3629 /* We always save both halves of the FP register, so always
3630 increment the frame size by 8 bytes. */
3634 /* If any of the floating registers are saved, account for the
3635 alignment needed for the floating point register save block. */
3638 size = (size + 7) & ~7;
3643 /* The various ABIs include space for the outgoing parameters in the
3644 size of the current function's stack frame. We don't need to align
3645 for the outgoing arguments as their alignment is set by the final
3646 rounding for the frame as a whole. */
3647 size += current_function_outgoing_args_size;
3649 /* Allocate space for the fixed frame marker. This space must be
3650 allocated for any function that makes calls or allocates
3652 if (!current_function_is_leaf || size)
3653 size += TARGET_64BIT ? 48 : 32;
3655 /* Finally, round to the preferred stack boundary. */
3656 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3657 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3660 /* Generate the assembly code for function entry. FILE is a stdio
3661 stream to output the code to. SIZE is an int: how many units of
3662 temporary storage to allocate.
3664 Refer to the array `regs_ever_live' to determine which registers to
3665 save; `regs_ever_live[I]' is nonzero if register number I is ever
3666 used in the function. This function is responsible for knowing
3667 which registers should not be saved even if used. */
3669 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3670 of memory. If any fpu reg is used in the function, we allocate
3671 such a block here, at the bottom of the frame, just in case it's needed.
3673 If this function is a leaf procedure, then we may choose not
3674 to do a "save" insn. The decision about whether or not
3675 to do this is made in regclass.c. */
3678 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3680 /* The function's label and associated .PROC must never be
3681 separated and must be output *after* any profiling declarations
3682 to avoid changing spaces/subspaces within a procedure. */
3683 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3684 fputs ("\t.PROC\n", file);
3686 /* hppa_expand_prologue does the dirty work now. We just need
3687 to output the assembler directives which denote the start
3689 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3690 if (regs_ever_live[2])
3691 fputs (",CALLS,SAVE_RP", file);
3693 fputs (",NO_CALLS", file);
3695 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3696 at the beginning of the frame and that it is used as the frame
3697 pointer for the frame. We do this because our current frame
3698 layout doesn't conform to that specified in the the HP runtime
3699 documentation and we need a way to indicate to programs such as
3700 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3701 isn't used by HP compilers but is supported by the assembler.
3702 However, SAVE_SP is supposed to indicate that the previous stack
3703 pointer has been saved in the frame marker. */
3704 if (frame_pointer_needed)
3705 fputs (",SAVE_SP", file);
3707 /* Pass on information about the number of callee register saves
3708 performed in the prologue.
3710 The compiler is supposed to pass the highest register number
3711 saved, the assembler then has to adjust that number before
3712 entering it into the unwind descriptor (to account for any
3713 caller saved registers with lower register numbers than the
3714 first callee saved register). */
3716 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3719 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3721 fputs ("\n\t.ENTRY\n", file);
3723 remove_useless_addtr_insns (0);
3727 hppa_expand_prologue (void)
3729 int merge_sp_adjust_with_store = 0;
3730 HOST_WIDE_INT size = get_frame_size ();
3731 HOST_WIDE_INT offset;
3739 /* Compute total size for frame pointer, filler, locals and rounding to
3740 the next word boundary. Similar code appears in compute_frame_size
3741 and must be changed in tandem with this code. */
3742 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3743 if (local_fsize || frame_pointer_needed)
3744 local_fsize += STARTING_FRAME_OFFSET;
3746 actual_fsize = compute_frame_size (size, &save_fregs);
3748 /* Compute a few things we will use often. */
3749 tmpreg = gen_rtx_REG (word_mode, 1);
3751 /* Save RP first. The calling conventions manual states RP will
3752 always be stored into the caller's frame at sp - 20 or sp - 16
3753 depending on which ABI is in use. */
3754 if (regs_ever_live[2] || current_function_calls_eh_return)
3755 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3757 /* Allocate the local frame and set up the frame pointer if needed. */
3758 if (actual_fsize != 0)
3760 if (frame_pointer_needed)
3762 /* Copy the old frame pointer temporarily into %r1. Set up the
3763 new stack pointer, then store away the saved old frame pointer
3764 into the stack at sp and at the same time update the stack
3765 pointer by actual_fsize bytes. Two versions, first
3766 handles small (<8k) frames. The second handles large (>=8k)
3768 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3771 /* We need to record the frame pointer save here since the
3772 new frame pointer is set in the following insn. */
3773 RTX_FRAME_RELATED_P (insn) = 1;
3775 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3776 gen_rtx_SET (VOIDmode,
3777 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3782 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3784 RTX_FRAME_RELATED_P (insn) = 1;
3786 if (VAL_14_BITS_P (actual_fsize))
3787 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3790 /* It is incorrect to store the saved frame pointer at *sp,
3791 then increment sp (writes beyond the current stack boundary).
3793 So instead use stwm to store at *sp and post-increment the
3794 stack pointer as an atomic operation. Then increment sp to
3795 finish allocating the new frame. */
3796 HOST_WIDE_INT adjust1 = 8192 - 64;
3797 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3799 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3800 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3804 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3805 we need to store the previous stack pointer (frame pointer)
3806 into the frame marker on targets that use the HP unwind
3807 library. This allows the HP unwind library to be used to
3808 unwind GCC frames. However, we are not fully compatible
3809 with the HP library because our frame layout differs from
3810 that specified in the HP runtime specification.
3812 We don't want a frame note on this instruction as the frame
3813 marker moves during dynamic stack allocation.
3815 This instruction also serves as a blockage to prevent
3816 register spills from being scheduled before the stack
3817 pointer is raised. This is necessary as we store
3818 registers using the frame pointer as a base register,
3819 and the frame pointer is set before sp is raised. */
3820 if (TARGET_HPUX_UNWIND_LIBRARY)
3822 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3823 GEN_INT (TARGET_64BIT ? -8 : -4));
3825 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3829 emit_insn (gen_blockage ());
3831 /* no frame pointer needed. */
3834 /* In some cases we can perform the first callee register save
3835 and allocating the stack frame at the same time. If so, just
3836 make a note of it and defer allocating the frame until saving
3837 the callee registers. */
3838 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3839 merge_sp_adjust_with_store = 1;
3840 /* Can not optimize. Adjust the stack frame by actual_fsize
3843 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3848 /* Normal register save.
3850 Do not save the frame pointer in the frame_pointer_needed case. It
3851 was done earlier. */
3852 if (frame_pointer_needed)
3854 offset = local_fsize;
3856 /* Saving the EH return data registers in the frame is the simplest
3857 way to get the frame unwind information emitted. We put them
3858 just before the general registers. */
3859 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3861 unsigned int i, regno;
3865 regno = EH_RETURN_DATA_REGNO (i);
3866 if (regno == INVALID_REGNUM)
3869 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3870 offset += UNITS_PER_WORD;
3874 for (i = 18; i >= 4; i--)
3875 if (regs_ever_live[i] && ! call_used_regs[i])
3877 store_reg (i, offset, FRAME_POINTER_REGNUM);
3878 offset += UNITS_PER_WORD;
3881 /* Account for %r3 which is saved in a special place. */
3884 /* No frame pointer needed. */
3887 offset = local_fsize - actual_fsize;
3889 /* Saving the EH return data registers in the frame is the simplest
3890 way to get the frame unwind information emitted. */
3891 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3893 unsigned int i, regno;
3897 regno = EH_RETURN_DATA_REGNO (i);
3898 if (regno == INVALID_REGNUM)
3901 /* If merge_sp_adjust_with_store is nonzero, then we can
3902 optimize the first save. */
3903 if (merge_sp_adjust_with_store)
3905 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3906 merge_sp_adjust_with_store = 0;
3909 store_reg (regno, offset, STACK_POINTER_REGNUM);
3910 offset += UNITS_PER_WORD;
3914 for (i = 18; i >= 3; i--)
3915 if (regs_ever_live[i] && ! call_used_regs[i])
3917 /* If merge_sp_adjust_with_store is nonzero, then we can
3918 optimize the first GR save. */
3919 if (merge_sp_adjust_with_store)
3921 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3922 merge_sp_adjust_with_store = 0;
3925 store_reg (i, offset, STACK_POINTER_REGNUM);
3926 offset += UNITS_PER_WORD;
3930 /* If we wanted to merge the SP adjustment with a GR save, but we never
3931 did any GR saves, then just emit the adjustment here. */
3932 if (merge_sp_adjust_with_store)
3933 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3937 /* The hppa calling conventions say that %r19, the pic offset
3938 register, is saved at sp - 32 (in this function's frame)
3939 when generating PIC code. FIXME: What is the correct thing
3940 to do for functions which make no calls and allocate no
3941 frame? Do we need to allocate a frame, or can we just omit
3942 the save? For now we'll just omit the save.
3944 We don't want a note on this insn as the frame marker can
3945 move if there is a dynamic stack allocation. */
3946 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3948 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3950 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3954 /* Align pointer properly (doubleword boundary). */
3955 offset = (offset + 7) & ~7;
3957 /* Floating point register store. */
3962 /* First get the frame or stack pointer to the start of the FP register
3964 if (frame_pointer_needed)
3966 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3967 base = frame_pointer_rtx;
3971 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3972 base = stack_pointer_rtx;
3975 /* Now actually save the FP registers. */
3976 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3978 if (regs_ever_live[i]
3979 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3981 rtx addr, insn, reg;
3982 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3983 reg = gen_rtx_REG (DFmode, i);
3984 insn = emit_move_insn (addr, reg);
3987 RTX_FRAME_RELATED_P (insn) = 1;
3990 rtx mem = gen_rtx_MEM (DFmode,
3991 plus_constant (base, offset));
3993 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3994 gen_rtx_SET (VOIDmode, mem, reg),
3999 rtx meml = gen_rtx_MEM (SFmode,
4000 plus_constant (base, offset));
4001 rtx memr = gen_rtx_MEM (SFmode,
4002 plus_constant (base, offset + 4));
4003 rtx regl = gen_rtx_REG (SFmode, i);
4004 rtx regr = gen_rtx_REG (SFmode, i + 1);
4005 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4006 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4009 RTX_FRAME_RELATED_P (setl) = 1;
4010 RTX_FRAME_RELATED_P (setr) = 1;
4011 vec = gen_rtvec (2, setl, setr);
4013 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4014 gen_rtx_SEQUENCE (VOIDmode, vec),
4018 offset += GET_MODE_SIZE (DFmode);
4025 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4026 Handle case where DISP > 8k by using the add_high_const patterns. */
4029 load_reg (int reg, HOST_WIDE_INT disp, int base)
4031 rtx dest = gen_rtx_REG (word_mode, reg);
4032 rtx basereg = gen_rtx_REG (Pmode, base);
4035 if (VAL_14_BITS_P (disp))
4036 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4037 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4039 rtx delta = GEN_INT (disp);
4040 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4042 emit_move_insn (tmpreg, delta);
4043 if (TARGET_DISABLE_INDEXING)
4045 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4046 src = gen_rtx_MEM (word_mode, tmpreg);
4049 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4053 rtx delta = GEN_INT (disp);
4054 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4055 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4057 emit_move_insn (tmpreg, high);
4058 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4061 emit_move_insn (dest, src);
4064 /* Update the total code bytes output to the text section. */
4067 update_total_code_bytes (int nbytes)
4069 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4070 && !IN_NAMED_SECTION_P (cfun->decl))
4072 if (INSN_ADDRESSES_SET_P ())
4074 unsigned long old_total = total_code_bytes;
4076 total_code_bytes += nbytes;
4078 /* Be prepared to handle overflows. */
4079 if (old_total > total_code_bytes)
4080 total_code_bytes = -1;
4083 total_code_bytes = -1;
4087 /* This function generates the assembly code for function exit.
4088 Args are as for output_function_prologue ().
4090 The function epilogue should not depend on the current stack
4091 pointer! It should use the frame pointer only. This is mandatory
4092 because of alloca; we also take advantage of it to omit stack
4093 adjustments before returning. */
4096 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4098 rtx insn = get_last_insn ();
4102 /* hppa_expand_epilogue does the dirty work now. We just need
4103 to output the assembler directives which denote the end
4106 To make debuggers happy, emit a nop if the epilogue was completely
4107 eliminated due to a volatile call as the last insn in the
4108 current function. That way the return address (in %r2) will
4109 always point to a valid instruction in the current function. */
4111 /* Get the last real insn. */
4112 if (GET_CODE (insn) == NOTE)
4113 insn = prev_real_insn (insn);
4115 /* If it is a sequence, then look inside. */
4116 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4117 insn = XVECEXP (PATTERN (insn), 0, 0);
4119 /* If insn is a CALL_INSN, then it must be a call to a volatile
4120 function (otherwise there would be epilogue insns). */
4121 if (insn && GET_CODE (insn) == CALL_INSN)
4123 fputs ("\tnop\n", file);
4127 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4129 if (INSN_ADDRESSES_SET_P ())
4131 insn = get_last_nonnote_insn ();
4132 last_address += INSN_ADDRESSES (INSN_UID (insn));
4134 last_address += insn_default_length (insn);
4135 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4136 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4139 /* Finally, update the total number of code bytes output so far. */
4140 update_total_code_bytes (last_address);
4144 hppa_expand_epilogue (void)
4147 HOST_WIDE_INT offset;
4148 HOST_WIDE_INT ret_off = 0;
4150 int merge_sp_adjust_with_load = 0;
4152 /* We will use this often. */
4153 tmpreg = gen_rtx_REG (word_mode, 1);
4155 /* Try to restore RP early to avoid load/use interlocks when
4156 RP gets used in the return (bv) instruction. This appears to still
4157 be necessary even when we schedule the prologue and epilogue. */
4158 if (regs_ever_live [2] || current_function_calls_eh_return)
4160 ret_off = TARGET_64BIT ? -16 : -20;
4161 if (frame_pointer_needed)
4163 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4168 /* No frame pointer, and stack is smaller than 8k. */
4169 if (VAL_14_BITS_P (ret_off - actual_fsize))
4171 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4177 /* General register restores. */
4178 if (frame_pointer_needed)
4180 offset = local_fsize;
4182 /* If the current function calls __builtin_eh_return, then we need
4183 to restore the saved EH data registers. */
4184 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4186 unsigned int i, regno;
4190 regno = EH_RETURN_DATA_REGNO (i);
4191 if (regno == INVALID_REGNUM)
4194 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4195 offset += UNITS_PER_WORD;
4199 for (i = 18; i >= 4; i--)
4200 if (regs_ever_live[i] && ! call_used_regs[i])
4202 load_reg (i, offset, FRAME_POINTER_REGNUM);
4203 offset += UNITS_PER_WORD;
4208 offset = local_fsize - actual_fsize;
4210 /* If the current function calls __builtin_eh_return, then we need
4211 to restore the saved EH data registers. */
4212 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4214 unsigned int i, regno;
4218 regno = EH_RETURN_DATA_REGNO (i);
4219 if (regno == INVALID_REGNUM)
4222 /* Only for the first load.
4223 merge_sp_adjust_with_load holds the register load
4224 with which we will merge the sp adjustment. */
4225 if (merge_sp_adjust_with_load == 0
4227 && VAL_14_BITS_P (-actual_fsize))
4228 merge_sp_adjust_with_load = regno;
4230 load_reg (regno, offset, STACK_POINTER_REGNUM);
4231 offset += UNITS_PER_WORD;
4235 for (i = 18; i >= 3; i--)
4237 if (regs_ever_live[i] && ! call_used_regs[i])
4239 /* Only for the first load.
4240 merge_sp_adjust_with_load holds the register load
4241 with which we will merge the sp adjustment. */
4242 if (merge_sp_adjust_with_load == 0
4244 && VAL_14_BITS_P (-actual_fsize))
4245 merge_sp_adjust_with_load = i;
4247 load_reg (i, offset, STACK_POINTER_REGNUM);
4248 offset += UNITS_PER_WORD;
4253 /* Align pointer properly (doubleword boundary). */
4254 offset = (offset + 7) & ~7;
4256 /* FP register restores. */
4259 /* Adjust the register to index off of. */
4260 if (frame_pointer_needed)
4261 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4263 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4265 /* Actually do the restores now. */
4266 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4267 if (regs_ever_live[i]
4268 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4270 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4271 rtx dest = gen_rtx_REG (DFmode, i);
4272 emit_move_insn (dest, src);
4276 /* Emit a blockage insn here to keep these insns from being moved to
4277 an earlier spot in the epilogue, or into the main instruction stream.
4279 This is necessary as we must not cut the stack back before all the
4280 restores are finished. */
4281 emit_insn (gen_blockage ());
4283 /* Reset stack pointer (and possibly frame pointer). The stack
4284 pointer is initially set to fp + 64 to avoid a race condition. */
4285 if (frame_pointer_needed)
4287 rtx delta = GEN_INT (-64);
4289 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4290 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4292 /* If we were deferring a callee register restore, do it now. */
4293 else if (merge_sp_adjust_with_load)
4295 rtx delta = GEN_INT (-actual_fsize);
4296 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4298 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4300 else if (actual_fsize != 0)
4301 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4304 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4305 frame greater than 8k), do so now. */
4307 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4309 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4311 rtx sa = EH_RETURN_STACKADJ_RTX;
4313 emit_insn (gen_blockage ());
4314 emit_insn (TARGET_64BIT
4315 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4316 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4321 hppa_pic_save_rtx (void)
4323 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4327 hppa_profile_hook (int label_no)
4329 /* We use SImode for the address of the function in both 32 and
4330 64-bit code to avoid having to provide DImode versions of the
4331 lcla2 and load_offset_label_address insn patterns. */
4332 rtx reg = gen_reg_rtx (SImode);
4333 rtx label_rtx = gen_label_rtx ();
4334 rtx begin_label_rtx, call_insn;
4335 char begin_label_name[16];
4337 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4339 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4342 emit_move_insn (arg_pointer_rtx,
4343 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4346 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4348 /* The address of the function is loaded into %r25 with a instruction-
4349 relative sequence that avoids the use of relocations. The sequence
4350 is split so that the load_offset_label_address instruction can
4351 occupy the delay slot of the call to _mcount. */
4353 emit_insn (gen_lcla2 (reg, label_rtx));
4355 emit_insn (gen_lcla1 (reg, label_rtx));
4357 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4358 reg, begin_label_rtx, label_rtx));
4360 #ifndef NO_PROFILE_COUNTERS
4362 rtx count_label_rtx, addr, r24;
4363 char count_label_name[16];
4365 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4366 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4368 addr = force_reg (Pmode, count_label_rtx);
4369 r24 = gen_rtx_REG (Pmode, 24);
4370 emit_move_insn (r24, addr);
4373 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4374 gen_rtx_SYMBOL_REF (Pmode,
4376 GEN_INT (TARGET_64BIT ? 24 : 12)));
4378 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4383 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4384 gen_rtx_SYMBOL_REF (Pmode,
4386 GEN_INT (TARGET_64BIT ? 16 : 8)));
4390 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4391 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4393 /* Indicate the _mcount call cannot throw, nor will it execute a
4395 REG_NOTES (call_insn)
4396 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4399 /* Fetch the return address for the frame COUNT steps up from
4400 the current frame, after the prologue. FRAMEADDR is the
4401 frame pointer of the COUNT frame.
4403 We want to ignore any export stub remnants here. To handle this,
4404 we examine the code at the return address, and if it is an export
4405 stub, we return a memory rtx for the stub return address stored
4408 The value returned is used in two different ways:
4410 1. To find a function's caller.
4412 2. To change the return address for a function.
4414 This function handles most instances of case 1; however, it will
4415 fail if there are two levels of stubs to execute on the return
4416 path. The only way I believe that can happen is if the return value
4417 needs a parameter relocation, which never happens for C code.
4419 This function handles most instances of case 2; however, it will
4420 fail if we did not originally have stub code on the return path
4421 but will need stub code on the new return path. This can happen if
4422 the caller & callee are both in the main program, but the new
4423 return location is in a shared library. */
4426 return_addr_rtx (int count, rtx frameaddr)
4436 rp = get_hard_reg_initial_val (Pmode, 2);
4438 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4441 saved_rp = gen_reg_rtx (Pmode);
4442 emit_move_insn (saved_rp, rp);
4444 /* Get pointer to the instruction stream. We have to mask out the
4445 privilege level from the two low order bits of the return address
4446 pointer here so that ins will point to the start of the first
4447 instruction that would have been executed if we returned. */
4448 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4449 label = gen_label_rtx ();
4451 /* Check the instruction stream at the normal return address for the
4454 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4455 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4456 0x00011820 | stub+16: mtsp r1,sr0
4457 0xe0400002 | stub+20: be,n 0(sr0,rp)
4459 If it is an export stub, than our return address is really in
4462 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4463 NULL_RTX, SImode, 1);
4464 emit_jump_insn (gen_bne (label));
4466 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4467 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4468 emit_jump_insn (gen_bne (label));
4470 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4471 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4472 emit_jump_insn (gen_bne (label));
4474 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4475 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4477 /* If there is no export stub then just use the value saved from
4478 the return pointer register. */
4480 emit_jump_insn (gen_bne (label));
4482 /* Here we know that our return address points to an export
4483 stub. We don't want to return the address of the export stub,
4484 but rather the return address of the export stub. That return
4485 address is stored at -24[frameaddr]. */
4487 emit_move_insn (saved_rp,
4489 memory_address (Pmode,
4490 plus_constant (frameaddr,
4497 /* This is only valid once reload has completed because it depends on
4498 knowing exactly how much (if any) frame there is and...
4500 It's only valid if there is no frame marker to de-allocate and...
4502 It's only valid if %r2 hasn't been saved into the caller's frame
4503 (we're not profiling and %r2 isn't live anywhere). */
4505 hppa_can_use_return_insn_p (void)
4507 return (reload_completed
4508 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4509 && ! regs_ever_live[2]
4510 && ! frame_pointer_needed);
4514 emit_bcond_fp (enum rtx_code code, rtx operand0)
4516 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4517 gen_rtx_IF_THEN_ELSE (VOIDmode,
4518 gen_rtx_fmt_ee (code,
4520 gen_rtx_REG (CCFPmode, 0),
4522 gen_rtx_LABEL_REF (VOIDmode, operand0),
4528 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4530 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4531 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4534 /* Adjust the cost of a scheduling dependency. Return the new cost of
4535 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4538 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4540 enum attr_type attr_type;
4542 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4543 true dependencies as they are described with bypasses now. */
4544 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4547 if (! recog_memoized (insn))
4550 attr_type = get_attr_type (insn);
4552 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4554 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4557 if (attr_type == TYPE_FPLOAD)
4559 rtx pat = PATTERN (insn);
4560 rtx dep_pat = PATTERN (dep_insn);
4561 if (GET_CODE (pat) == PARALLEL)
4563 /* This happens for the fldXs,mb patterns. */
4564 pat = XVECEXP (pat, 0, 0);
4566 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4567 /* If this happens, we have to extend this to schedule
4568 optimally. Return 0 for now. */
4571 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4573 if (! recog_memoized (dep_insn))
4575 switch (get_attr_type (dep_insn))
4582 case TYPE_FPSQRTSGL:
4583 case TYPE_FPSQRTDBL:
4584 /* A fpload can't be issued until one cycle before a
4585 preceding arithmetic operation has finished if
4586 the target of the fpload is any of the sources
4587 (or destination) of the arithmetic operation. */
4588 return insn_default_latency (dep_insn) - 1;
4595 else if (attr_type == TYPE_FPALU)
4597 rtx pat = PATTERN (insn);
4598 rtx dep_pat = PATTERN (dep_insn);
4599 if (GET_CODE (pat) == PARALLEL)
4601 /* This happens for the fldXs,mb patterns. */
4602 pat = XVECEXP (pat, 0, 0);
4604 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4605 /* If this happens, we have to extend this to schedule
4606 optimally. Return 0 for now. */
4609 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4611 if (! recog_memoized (dep_insn))
4613 switch (get_attr_type (dep_insn))
4617 case TYPE_FPSQRTSGL:
4618 case TYPE_FPSQRTDBL:
4619 /* An ALU flop can't be issued until two cycles before a
4620 preceding divide or sqrt operation has finished if
4621 the target of the ALU flop is any of the sources
4622 (or destination) of the divide or sqrt operation. */
4623 return insn_default_latency (dep_insn) - 2;
4631 /* For other anti dependencies, the cost is 0. */
4634 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4636 /* Output dependency; DEP_INSN writes a register that INSN writes some
4638 if (attr_type == TYPE_FPLOAD)
4640 rtx pat = PATTERN (insn);
4641 rtx dep_pat = PATTERN (dep_insn);
4642 if (GET_CODE (pat) == PARALLEL)
4644 /* This happens for the fldXs,mb patterns. */
4645 pat = XVECEXP (pat, 0, 0);
4647 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4648 /* If this happens, we have to extend this to schedule
4649 optimally. Return 0 for now. */
4652 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4654 if (! recog_memoized (dep_insn))
4656 switch (get_attr_type (dep_insn))
4663 case TYPE_FPSQRTSGL:
4664 case TYPE_FPSQRTDBL:
4665 /* A fpload can't be issued until one cycle before a
4666 preceding arithmetic operation has finished if
4667 the target of the fpload is the destination of the
4668 arithmetic operation.
4670 Exception: For PA7100LC, PA7200 and PA7300, the cost
4671 is 3 cycles, unless they bundle together. We also
4672 pay the penalty if the second insn is a fpload. */
4673 return insn_default_latency (dep_insn) - 1;
4680 else if (attr_type == TYPE_FPALU)
4682 rtx pat = PATTERN (insn);
4683 rtx dep_pat = PATTERN (dep_insn);
4684 if (GET_CODE (pat) == PARALLEL)
4686 /* This happens for the fldXs,mb patterns. */
4687 pat = XVECEXP (pat, 0, 0);
4689 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4690 /* If this happens, we have to extend this to schedule
4691 optimally. Return 0 for now. */
4694 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4696 if (! recog_memoized (dep_insn))
4698 switch (get_attr_type (dep_insn))
4702 case TYPE_FPSQRTSGL:
4703 case TYPE_FPSQRTDBL:
4704 /* An ALU flop can't be issued until two cycles before a
4705 preceding divide or sqrt operation has finished if
4706 the target of the ALU flop is also the target of
4707 the divide or sqrt operation. */
4708 return insn_default_latency (dep_insn) - 2;
4716 /* For other output dependencies, the cost is 0. */
4723 /* Adjust scheduling priorities. We use this to try and keep addil
4724 and the next use of %r1 close together. */
4726 pa_adjust_priority (rtx insn, int priority)
4728 rtx set = single_set (insn);
4732 src = SET_SRC (set);
4733 dest = SET_DEST (set);
4734 if (GET_CODE (src) == LO_SUM
4735 && symbolic_operand (XEXP (src, 1), VOIDmode)
4736 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4739 else if (GET_CODE (src) == MEM
4740 && GET_CODE (XEXP (src, 0)) == LO_SUM
4741 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4742 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4745 else if (GET_CODE (dest) == MEM
4746 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4747 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4748 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4754 /* The 700 can only issue a single insn at a time.
4755 The 7XXX processors can issue two insns at a time.
4756 The 8000 can issue 4 insns at a time. */
4758 pa_issue_rate (void)
4762 case PROCESSOR_700: return 1;
4763 case PROCESSOR_7100: return 2;
4764 case PROCESSOR_7100LC: return 2;
4765 case PROCESSOR_7200: return 2;
4766 case PROCESSOR_7300: return 2;
4767 case PROCESSOR_8000: return 4;
4776 /* Return any length adjustment needed by INSN which already has its length
4777 computed as LENGTH. Return zero if no adjustment is necessary.
4779 For the PA: function calls, millicode calls, and backwards short
4780 conditional branches with unfilled delay slots need an adjustment by +1
4781 (to account for the NOP which will be inserted into the instruction stream).
4783 Also compute the length of an inline block move here as it is too
4784 complicated to express as a length attribute in pa.md. */
4786 pa_adjust_insn_length (rtx insn, int length)
4788 rtx pat = PATTERN (insn);
4790 /* Jumps inside switch tables which have unfilled delay slots need
4792 if (GET_CODE (insn) == JUMP_INSN
4793 && GET_CODE (pat) == PARALLEL
4794 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4796 /* Millicode insn with an unfilled delay slot. */
4797 else if (GET_CODE (insn) == INSN
4798 && GET_CODE (pat) != SEQUENCE
4799 && GET_CODE (pat) != USE
4800 && GET_CODE (pat) != CLOBBER
4801 && get_attr_type (insn) == TYPE_MILLI)
4803 /* Block move pattern. */
4804 else if (GET_CODE (insn) == INSN
4805 && GET_CODE (pat) == PARALLEL
4806 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4807 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4808 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4809 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4810 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4811 return compute_movmem_length (insn) - 4;
4812 /* Block clear pattern. */
4813 else if (GET_CODE (insn) == INSN
4814 && GET_CODE (pat) == PARALLEL
4815 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4816 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4817 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4818 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4819 return compute_clrmem_length (insn) - 4;
4820 /* Conditional branch with an unfilled delay slot. */
4821 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4823 /* Adjust a short backwards conditional with an unfilled delay slot. */
4824 if (GET_CODE (pat) == SET
4826 && ! forward_branch_p (insn))
4828 else if (GET_CODE (pat) == PARALLEL
4829 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4832 /* Adjust dbra insn with short backwards conditional branch with
4833 unfilled delay slot -- only for case where counter is in a
4834 general register register. */
4835 else if (GET_CODE (pat) == PARALLEL
4836 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4837 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4838 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4840 && ! forward_branch_p (insn))
4848 /* Print operand X (an rtx) in assembler syntax to file FILE.
4849 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4850 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4853 print_operand (FILE *file, rtx x, int code)
4858 /* Output a 'nop' if there's nothing for the delay slot. */
4859 if (dbr_sequence_length () == 0)
4860 fputs ("\n\tnop", file);
4863 /* Output a nullification completer if there's nothing for the */
4864 /* delay slot or nullification is requested. */
4865 if (dbr_sequence_length () == 0 ||
4867 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4871 /* Print out the second register name of a register pair.
4872 I.e., R (6) => 7. */
4873 fputs (reg_names[REGNO (x) + 1], file);
4876 /* A register or zero. */
4878 || (x == CONST0_RTX (DFmode))
4879 || (x == CONST0_RTX (SFmode)))
4881 fputs ("%r0", file);
4887 /* A register or zero (floating point). */
4889 || (x == CONST0_RTX (DFmode))
4890 || (x == CONST0_RTX (SFmode)))
4892 fputs ("%fr0", file);
4901 xoperands[0] = XEXP (XEXP (x, 0), 0);
4902 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4903 output_global_address (file, xoperands[1], 0);
4904 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4908 case 'C': /* Plain (C)ondition */
4910 switch (GET_CODE (x))
4913 fputs ("=", file); break;
4915 fputs ("<>", file); break;
4917 fputs (">", file); break;
4919 fputs (">=", file); break;
4921 fputs (">>=", file); break;
4923 fputs (">>", file); break;
4925 fputs ("<", file); break;
4927 fputs ("<=", file); break;
4929 fputs ("<<=", file); break;
4931 fputs ("<<", file); break;
4936 case 'N': /* Condition, (N)egated */
4937 switch (GET_CODE (x))
4940 fputs ("<>", file); break;
4942 fputs ("=", file); break;
4944 fputs ("<=", file); break;
4946 fputs ("<", file); break;
4948 fputs ("<<", file); break;
4950 fputs ("<<=", file); break;
4952 fputs (">=", file); break;
4954 fputs (">", file); break;
4956 fputs (">>", file); break;
4958 fputs (">>=", file); break;
4963 /* For floating point comparisons. Note that the output
4964 predicates are the complement of the desired mode. */
4966 switch (GET_CODE (x))
4969 fputs ("!=", file); break;
4971 fputs ("=", file); break;
4973 fputs ("!>", file); break;
4975 fputs ("!>=", file); break;
4977 fputs ("!<", file); break;
4979 fputs ("!<=", file); break;
4981 fputs ("!<>", file); break;
4983 fputs (">", file); break;
4985 fputs (">=", file); break;
4987 fputs ("<", file); break;
4989 fputs ("<=", file); break;
4991 fputs ("<>", file); break;
4993 fputs ("<=>", file); break;
4995 fputs ("!<=>", file); break;
5000 case 'S': /* Condition, operands are (S)wapped. */
5001 switch (GET_CODE (x))
5004 fputs ("=", file); break;
5006 fputs ("<>", file); break;
5008 fputs ("<", file); break;
5010 fputs ("<=", file); break;
5012 fputs ("<<=", file); break;
5014 fputs ("<<", file); break;
5016 fputs (">", file); break;
5018 fputs (">=", file); break;
5020 fputs (">>=", file); break;
5022 fputs (">>", file); break;
5027 case 'B': /* Condition, (B)oth swapped and negate. */
5028 switch (GET_CODE (x))
5031 fputs ("<>", file); break;
5033 fputs ("=", file); break;
5035 fputs (">=", file); break;
5037 fputs (">", file); break;
5039 fputs (">>", file); break;
5041 fputs (">>=", file); break;
5043 fputs ("<=", file); break;
5045 fputs ("<", file); break;
5047 fputs ("<<", file); break;
5049 fputs ("<<=", file); break;
5055 if (GET_CODE (x) == CONST_INT)
5057 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5062 if (GET_CODE (x) == CONST_INT)
5064 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5069 if (GET_CODE (x) == CONST_INT)
5071 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5076 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5078 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5083 if (GET_CODE (x) == CONST_INT)
5085 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5090 if (GET_CODE (x) == CONST_INT)
5092 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5097 if (GET_CODE (x) == CONST_INT)
5102 switch (GET_CODE (XEXP (x, 0)))
5106 if (ASSEMBLER_DIALECT == 0)
5107 fputs ("s,mb", file);
5109 fputs (",mb", file);
5113 if (ASSEMBLER_DIALECT == 0)
5114 fputs ("s,ma", file);
5116 fputs (",ma", file);
5119 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5120 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5122 if (ASSEMBLER_DIALECT == 0)
5125 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5126 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5128 if (ASSEMBLER_DIALECT == 0)
5129 fputs ("x,s", file);
5133 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5137 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5143 output_global_address (file, x, 0);
5146 output_global_address (file, x, 1);
5148 case 0: /* Don't do anything special */
5153 compute_zdepwi_operands (INTVAL (x), op);
5154 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5160 compute_zdepdi_operands (INTVAL (x), op);
5161 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5165 /* We can get here from a .vtable_inherit due to our
5166 CONSTANT_ADDRESS_P rejecting perfectly good constant
5172 if (GET_CODE (x) == REG)
5174 fputs (reg_names [REGNO (x)], file);
5175 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5181 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5182 && (REGNO (x) & 1) == 0)
5185 else if (GET_CODE (x) == MEM)
5187 int size = GET_MODE_SIZE (GET_MODE (x));
5188 rtx base = NULL_RTX;
5189 switch (GET_CODE (XEXP (x, 0)))
5193 base = XEXP (XEXP (x, 0), 0);
5194 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5198 base = XEXP (XEXP (x, 0), 0);
5199 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5202 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5203 fprintf (file, "%s(%s)",
5204 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5205 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5206 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5207 fprintf (file, "%s(%s)",
5208 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5209 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5210 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5211 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5213 /* Because the REG_POINTER flag can get lost during reload,
5214 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5215 index and base registers in the combined move patterns. */
5216 rtx base = XEXP (XEXP (x, 0), 1);
5217 rtx index = XEXP (XEXP (x, 0), 0);
5219 fprintf (file, "%s(%s)",
5220 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5223 output_address (XEXP (x, 0));
5226 output_address (XEXP (x, 0));
5231 output_addr_const (file, x);
5234 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5237 output_global_address (FILE *file, rtx x, int round_constant)
5240 /* Imagine (high (const (plus ...))). */
5241 if (GET_CODE (x) == HIGH)
5244 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5245 assemble_name (file, XSTR (x, 0));
5246 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5248 assemble_name (file, XSTR (x, 0));
5249 fputs ("-$global$", file);
5251 else if (GET_CODE (x) == CONST)
5253 const char *sep = "";
5254 int offset = 0; /* assembler wants -$global$ at end */
5255 rtx base = NULL_RTX;
5257 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5259 base = XEXP (XEXP (x, 0), 0);
5260 output_addr_const (file, base);
5262 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5263 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5266 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5268 base = XEXP (XEXP (x, 0), 1);
5269 output_addr_const (file, base);
5271 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5272 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5275 /* How bogus. The compiler is apparently responsible for
5276 rounding the constant if it uses an LR field selector.
5278 The linker and/or assembler seem a better place since
5279 they have to do this kind of thing already.
5281 If we fail to do this, HP's optimizing linker may eliminate
5282 an addil, but not update the ldw/stw/ldo instruction that
5283 uses the result of the addil. */
5285 offset = ((offset + 0x1000) & ~0x1fff);
5287 if (GET_CODE (XEXP (x, 0)) == PLUS)
5297 else if (GET_CODE (XEXP (x, 0)) == MINUS
5298 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5302 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5303 fputs ("-$global$", file);
5305 fprintf (file, "%s%d", sep, offset);
5308 output_addr_const (file, x);
5311 /* Output boilerplate text to appear at the beginning of the file.
5312 There are several possible versions. */
5313 #define aputs(x) fputs(x, asm_out_file)
5315 pa_file_start_level (void)
5318 aputs ("\t.LEVEL 2.0w\n");
5319 else if (TARGET_PA_20)
5320 aputs ("\t.LEVEL 2.0\n");
5321 else if (TARGET_PA_11)
5322 aputs ("\t.LEVEL 1.1\n");
5324 aputs ("\t.LEVEL 1.0\n");
5328 pa_file_start_space (int sortspace)
5330 aputs ("\t.SPACE $PRIVATE$");
5333 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5334 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5335 "\n\t.SPACE $TEXT$");
5338 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5339 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5343 pa_file_start_file (int want_version)
5345 if (write_symbols != NO_DEBUG)
5347 output_file_directive (asm_out_file, main_input_filename);
5349 aputs ("\t.version\t\"01.01\"\n");
5354 pa_file_start_mcount (const char *aswhat)
5357 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5361 pa_elf_file_start (void)
5363 pa_file_start_level ();
5364 pa_file_start_mcount ("ENTRY");
5365 pa_file_start_file (0);
5369 pa_som_file_start (void)
5371 pa_file_start_level ();
5372 pa_file_start_space (0);
5373 aputs ("\t.IMPORT $global$,DATA\n"
5374 "\t.IMPORT $$dyncall,MILLICODE\n");
5375 pa_file_start_mcount ("CODE");
5376 pa_file_start_file (0);
5380 pa_linux_file_start (void)
5382 pa_file_start_file (1);
5383 pa_file_start_level ();
5384 pa_file_start_mcount ("CODE");
5388 pa_hpux64_gas_file_start (void)
5390 pa_file_start_level ();
5391 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5393 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5395 pa_file_start_file (1);
5399 pa_hpux64_hpas_file_start (void)
5401 pa_file_start_level ();
5402 pa_file_start_space (1);
5403 pa_file_start_mcount ("CODE");
5404 pa_file_start_file (0);
5408 static struct deferred_plabel *
5409 get_plabel (const char *fname)
5413 /* See if we have already put this function on the list of deferred
5414 plabels. This list is generally small, so a liner search is not
5415 too ugly. If it proves too slow replace it with something faster. */
5416 for (i = 0; i < n_deferred_plabels; i++)
5417 if (strcmp (fname, deferred_plabels[i].name) == 0)
5420 /* If the deferred plabel list is empty, or this entry was not found
5421 on the list, create a new entry on the list. */
5422 if (deferred_plabels == NULL || i == n_deferred_plabels)
5424 const char *real_name;
5426 if (deferred_plabels == 0)
5427 deferred_plabels = (struct deferred_plabel *)
5428 ggc_alloc (sizeof (struct deferred_plabel));
5430 deferred_plabels = (struct deferred_plabel *)
5431 ggc_realloc (deferred_plabels,
5432 ((n_deferred_plabels + 1)
5433 * sizeof (struct deferred_plabel)));
5435 i = n_deferred_plabels++;
5436 deferred_plabels[i].internal_label = gen_label_rtx ();
5437 deferred_plabels[i].name = ggc_strdup (fname);
5439 /* Gross. We have just implicitly taken the address of this function,
5441 real_name = (*targetm.strip_name_encoding) (fname);
5442 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5445 return &deferred_plabels[i];
5449 output_deferred_plabels (void)
5452 /* If we have deferred plabels, then we need to switch into the data
5453 section and align it to a 4 byte boundary before we output the
5454 deferred plabels. */
5455 if (n_deferred_plabels)
5458 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5461 /* Now output the deferred plabels. */
5462 for (i = 0; i < n_deferred_plabels; i++)
5464 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5465 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5466 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5467 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5471 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5472 /* Initialize optabs to point to HPUX long double emulation routines. */
5474 pa_hpux_init_libfuncs (void)
5476 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5477 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5478 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5479 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5480 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5481 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5482 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5483 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5484 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5486 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5487 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5488 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5489 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5490 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5491 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5492 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5494 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5495 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5496 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5497 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5499 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5500 ? "__U_Qfcnvfxt_quad_to_sgl"
5501 : "_U_Qfcnvfxt_quad_to_sgl");
5502 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5503 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5504 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5506 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5507 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5511 /* HP's millicode routines mean something special to the assembler.
5512 Keep track of which ones we have used. */
5514 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5515 static void import_milli (enum millicodes);
5516 static char imported[(int) end1000];
5517 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5518 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5519 #define MILLI_START 10
5522 import_milli (enum millicodes code)
5524 char str[sizeof (import_string)];
5526 if (!imported[(int) code])
5528 imported[(int) code] = 1;
5529 strcpy (str, import_string);
5530 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5531 output_asm_insn (str, 0);
5535 /* The register constraints have put the operands and return value in
5536 the proper registers. */
5539 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5541 import_milli (mulI);
5542 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5545 /* Emit the rtl for doing a division by a constant. */
5547 /* Do magic division millicodes exist for this value? */
5548 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5551 /* We'll use an array to keep track of the magic millicodes and
5552 whether or not we've used them already. [n][0] is signed, [n][1] is
5555 static int div_milli[16][2];
5558 div_operand (rtx op, enum machine_mode mode)
5560 return (mode == SImode
5561 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5562 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5563 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5567 emit_hpdiv_const (rtx *operands, int unsignedp)
5569 if (GET_CODE (operands[2]) == CONST_INT
5570 && INTVAL (operands[2]) > 0
5571 && INTVAL (operands[2]) < 16
5572 && magic_milli[INTVAL (operands[2])])
5574 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5576 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5580 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5581 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5583 gen_rtx_REG (SImode, 26),
5585 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5586 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5587 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5588 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5589 gen_rtx_CLOBBER (VOIDmode, ret))));
5590 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5597 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5601 /* If the divisor is a constant, try to use one of the special
5603 if (GET_CODE (operands[0]) == CONST_INT)
5605 static char buf[100];
5606 divisor = INTVAL (operands[0]);
5607 if (!div_milli[divisor][unsignedp])
5609 div_milli[divisor][unsignedp] = 1;
5611 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5613 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5617 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5618 INTVAL (operands[0]));
5619 return output_millicode_call (insn,
5620 gen_rtx_SYMBOL_REF (SImode, buf));
5624 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5625 INTVAL (operands[0]));
5626 return output_millicode_call (insn,
5627 gen_rtx_SYMBOL_REF (SImode, buf));
5630 /* Divisor isn't a special constant. */
5635 import_milli (divU);
5636 return output_millicode_call (insn,
5637 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5641 import_milli (divI);
5642 return output_millicode_call (insn,
5643 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5648 /* Output a $$rem millicode to do mod. */
5651 output_mod_insn (int unsignedp, rtx insn)
5655 import_milli (remU);
5656 return output_millicode_call (insn,
5657 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5661 import_milli (remI);
5662 return output_millicode_call (insn,
5663 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5668 output_arg_descriptor (rtx call_insn)
5670 const char *arg_regs[4];
5671 enum machine_mode arg_mode;
5673 int i, output_flag = 0;
5676 /* We neither need nor want argument location descriptors for the
5677 64bit runtime environment or the ELF32 environment. */
5678 if (TARGET_64BIT || TARGET_ELF32)
5681 for (i = 0; i < 4; i++)
5684 /* Specify explicitly that no argument relocations should take place
5685 if using the portable runtime calling conventions. */
5686 if (TARGET_PORTABLE_RUNTIME)
5688 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5693 if (GET_CODE (call_insn) != CALL_INSN)
5695 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5697 rtx use = XEXP (link, 0);
5699 if (! (GET_CODE (use) == USE
5700 && GET_CODE (XEXP (use, 0)) == REG
5701 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5704 arg_mode = GET_MODE (XEXP (use, 0));
5705 regno = REGNO (XEXP (use, 0));
5706 if (regno >= 23 && regno <= 26)
5708 arg_regs[26 - regno] = "GR";
5709 if (arg_mode == DImode)
5710 arg_regs[25 - regno] = "GR";
5712 else if (regno >= 32 && regno <= 39)
5714 if (arg_mode == SFmode)
5715 arg_regs[(regno - 32) / 2] = "FR";
5718 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5719 arg_regs[(regno - 34) / 2] = "FR";
5720 arg_regs[(regno - 34) / 2 + 1] = "FU";
5722 arg_regs[(regno - 34) / 2] = "FU";
5723 arg_regs[(regno - 34) / 2 + 1] = "FR";
5728 fputs ("\t.CALL ", asm_out_file);
5729 for (i = 0; i < 4; i++)
5734 fputc (',', asm_out_file);
5735 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5738 fputc ('\n', asm_out_file);
5741 /* Return the class of any secondary reload register that is needed to
5742 move IN into a register in class CLASS using mode MODE.
5744 Profiling has showed this routine and its descendants account for
5745 a significant amount of compile time (~7%). So it has been
5746 optimized to reduce redundant computations and eliminate useless
5749 It might be worthwhile to try and make this a leaf function too. */
5752 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5754 int regno, is_symbolic;
5756 /* Trying to load a constant into a FP register during PIC code
5757 generation will require %r1 as a scratch register. */
5759 && GET_MODE_CLASS (mode) == MODE_INT
5760 && FP_REG_CLASS_P (class)
5761 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5764 /* Profiling showed the PA port spends about 1.3% of its compilation
5765 time in true_regnum from calls inside secondary_reload_class. */
5767 if (GET_CODE (in) == REG)
5770 if (regno >= FIRST_PSEUDO_REGISTER)
5771 regno = true_regnum (in);
5773 else if (GET_CODE (in) == SUBREG)
5774 regno = true_regnum (in);
5778 /* If we have something like (mem (mem (...)), we can safely assume the
5779 inner MEM will end up in a general register after reloading, so there's
5780 no need for a secondary reload. */
5781 if (GET_CODE (in) == MEM
5782 && GET_CODE (XEXP (in, 0)) == MEM)
5785 /* Handle out of range displacement for integer mode loads/stores of
5787 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5788 && GET_MODE_CLASS (mode) == MODE_INT
5789 && FP_REG_CLASS_P (class))
5790 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5791 return GENERAL_REGS;
5793 /* A SAR<->FP register copy requires a secondary register (GPR) as
5794 well as secondary memory. */
5795 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5796 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5797 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5798 return GENERAL_REGS;
5800 if (GET_CODE (in) == HIGH)
5803 /* Profiling has showed GCC spends about 2.6% of its compilation
5804 time in symbolic_operand from calls inside secondary_reload_class.
5806 We use an inline copy and only compute its return value once to avoid
5808 switch (GET_CODE (in))
5818 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5819 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5820 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5830 && read_only_operand (in, VOIDmode))
5833 if (class != R1_REGS && is_symbolic)
5840 function_arg_padding (enum machine_mode mode, tree type)
5843 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5845 /* Return none if justification is not required. */
5847 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5848 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5851 /* The directions set here are ignored when a BLKmode argument larger
5852 than a word is placed in a register. Different code is used for
5853 the stack and registers. This makes it difficult to have a
5854 consistent data representation for both the stack and registers.
5855 For both runtimes, the justification and padding for arguments on
5856 the stack and in registers should be identical. */
5858 /* The 64-bit runtime specifies left justification for aggregates. */
5861 /* The 32-bit runtime architecture specifies right justification.
5862 When the argument is passed on the stack, the argument is padded
5863 with garbage on the left. The HP compiler pads with zeros. */
5867 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5874 /* Do what is necessary for `va_start'. We look at the current function
5875 to determine if stdargs or varargs is used and fill in an initial
5876 va_list. A pointer to this constructor is returned. */
5879 hppa_builtin_saveregs (void)
5882 tree fntype = TREE_TYPE (current_function_decl);
5883 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5884 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5885 != void_type_node)))
5886 ? UNITS_PER_WORD : 0);
5889 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5891 offset = current_function_arg_offset_rtx;
5897 /* Adjust for varargs/stdarg differences. */
5899 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5901 offset = current_function_arg_offset_rtx;
5903 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5904 from the incoming arg pointer and growing to larger addresses. */
5905 for (i = 26, off = -64; i >= 19; i--, off += 8)
5906 emit_move_insn (gen_rtx_MEM (word_mode,
5907 plus_constant (arg_pointer_rtx, off)),
5908 gen_rtx_REG (word_mode, i));
5910 /* The incoming args pointer points just beyond the flushback area;
5911 normally this is not a serious concern. However, when we are doing
5912 varargs/stdargs we want to make the arg pointer point to the start
5913 of the incoming argument area. */
5914 emit_move_insn (virtual_incoming_args_rtx,
5915 plus_constant (arg_pointer_rtx, -64));
5917 /* Now return a pointer to the first anonymous argument. */
5918 return copy_to_reg (expand_binop (Pmode, add_optab,
5919 virtual_incoming_args_rtx,
5920 offset, 0, 0, OPTAB_LIB_WIDEN));
5923 /* Store general registers on the stack. */
5924 dest = gen_rtx_MEM (BLKmode,
5925 plus_constant (current_function_internal_arg_pointer,
5927 set_mem_alias_set (dest, get_varargs_alias_set ());
5928 set_mem_align (dest, BITS_PER_WORD);
5929 move_block_from_reg (23, dest, 4);
5931 /* move_block_from_reg will emit code to store the argument registers
5932 individually as scalar stores.
5934 However, other insns may later load from the same addresses for
5935 a structure load (passing a struct to a varargs routine).
5937 The alias code assumes that such aliasing can never happen, so we
5938 have to keep memory referencing insns from moving up beyond the
5939 last argument register store. So we emit a blockage insn here. */
5940 emit_insn (gen_blockage ());
5942 return copy_to_reg (expand_binop (Pmode, add_optab,
5943 current_function_internal_arg_pointer,
5944 offset, 0, 0, OPTAB_LIB_WIDEN));
5948 hppa_va_start (tree valist, rtx nextarg)
5950 nextarg = expand_builtin_saveregs ();
5951 std_expand_builtin_va_start (valist, nextarg);
5955 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5959 indirect = FUNCTION_ARG_PASS_BY_REFERENCE (dummy, TYPE_MODE (type), type, 0);
5963 /* Every argument in PA64 is supposed to be passed by value
5964 (including large structs). However, as a GCC extension, we
5965 pass zero and variable sized arguments by reference. Empty
5966 structures are a GCC extension not supported by the HP
5967 compilers. Thus, passing them by reference isn't likely
5968 to conflict with the ABI. For variable sized arguments,
5969 GCC doesn't have the infrastructure to allocate these to
5971 /* Args grow upward. We can use the generic routines. */
5974 return ind_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5976 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5978 else /* !TARGET_64BIT */
5980 tree ptr = build_pointer_type (type);
5983 unsigned int size, ofs;
5988 ptr = build_pointer_type (type);
5990 size = int_size_in_bytes (type);
5991 valist_type = TREE_TYPE (valist);
5993 /* Args grow down. Not handled by generic routines. */
5995 u = fold_convert (valist_type, size_in_bytes (type));
5996 t = build (MINUS_EXPR, valist_type, valist, u);
5998 /* Copied from va-pa.h, but we probably don't need to align to
5999 word size, since we generate and preserve that invariant. */
6000 u = build_int_2 ((size > 4 ? -8 : -4), -1);
6001 u = fold_convert (valist_type, u);
6002 t = build (BIT_AND_EXPR, valist_type, t, u);
6004 t = build (MODIFY_EXPR, valist_type, valist, t);
6006 ofs = (8 - size) % 4;
6009 u = fold_convert (valist_type, size_int (ofs));
6010 t = build (PLUS_EXPR, valist_type, t, u);
6013 t = fold_convert (ptr, t);
6014 t = build_fold_indirect_ref (t);
6017 t = build_fold_indirect_ref (t);
6023 /* This routine handles all the normal conditional branch sequences we
6024 might need to generate. It handles compare immediate vs compare
6025 register, nullification of delay slots, varying length branches,
6026 negated branches, and all combinations of the above. It returns the
6027 output appropriate to emit the branch corresponding to all given
6031 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6033 static char buf[100];
6037 /* A conditional branch to the following instruction (eg the delay slot)
6038 is asking for a disaster. This can happen when not optimizing and
6039 when jump optimization fails.
6041 While it is usually safe to emit nothing, this can fail if the
6042 preceding instruction is a nullified branch with an empty delay
6043 slot and the same branch target as this branch. We could check
6044 for this but jump optimization should eliminate nop jumps. It
6045 is always safe to emit a nop. */
6046 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6049 /* The doubleword form of the cmpib instruction doesn't have the LEU
6050 and GTU conditions while the cmpb instruction does. Since we accept
6051 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6052 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6053 operands[2] = gen_rtx_REG (DImode, 0);
6055 /* If this is a long branch with its delay slot unfilled, set `nullify'
6056 as it can nullify the delay slot and save a nop. */
6057 if (length == 8 && dbr_sequence_length () == 0)
6060 /* If this is a short forward conditional branch which did not get
6061 its delay slot filled, the delay slot can still be nullified. */
6062 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6063 nullify = forward_branch_p (insn);
6065 /* A forward branch over a single nullified insn can be done with a
6066 comclr instruction. This avoids a single cycle penalty due to
6067 mis-predicted branch if we fall through (branch not taken). */
6069 && next_real_insn (insn) != 0
6070 && get_attr_length (next_real_insn (insn)) == 4
6071 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6077 /* All short conditional branches except backwards with an unfilled
6081 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6083 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6084 if (GET_MODE (operands[1]) == DImode)
6087 strcat (buf, "%B3");
6089 strcat (buf, "%S3");
6091 strcat (buf, " %2,%r1,%%r0");
6093 strcat (buf, ",n %2,%r1,%0");
6095 strcat (buf, " %2,%r1,%0");
6098 /* All long conditionals. Note a short backward branch with an
6099 unfilled delay slot is treated just like a long backward branch
6100 with an unfilled delay slot. */
6102 /* Handle weird backwards branch with a filled delay slot
6103 with is nullified. */
6104 if (dbr_sequence_length () != 0
6105 && ! forward_branch_p (insn)
6108 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6109 if (GET_MODE (operands[1]) == DImode)
6112 strcat (buf, "%S3");
6114 strcat (buf, "%B3");
6115 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6117 /* Handle short backwards branch with an unfilled delay slot.
6118 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6119 taken and untaken branches. */
6120 else if (dbr_sequence_length () == 0
6121 && ! forward_branch_p (insn)
6122 && INSN_ADDRESSES_SET_P ()
6123 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6124 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6126 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6127 if (GET_MODE (operands[1]) == DImode)
6130 strcat (buf, "%B3 %2,%r1,%0%#");
6132 strcat (buf, "%S3 %2,%r1,%0%#");
6136 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6137 if (GET_MODE (operands[1]) == DImode)
6140 strcat (buf, "%S3");
6142 strcat (buf, "%B3");
6144 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6146 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6152 xoperands[0] = operands[0];
6153 xoperands[1] = operands[1];
6154 xoperands[2] = operands[2];
6155 xoperands[3] = operands[3];
6157 /* The reversed conditional branch must branch over one additional
6158 instruction if the delay slot is filled. If the delay slot
6159 is empty, the instruction after the reversed condition branch
6160 must be nullified. */
6161 nullify = dbr_sequence_length () == 0;
6162 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6164 /* Create a reversed conditional branch which branches around
6165 the following insns. */
6166 if (GET_MODE (operands[1]) != DImode)
6172 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6175 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6181 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6184 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6193 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6196 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6202 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6205 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6209 output_asm_insn (buf, xoperands);
6210 return output_lbranch (operands[0], insn);
6218 /* This routine handles long unconditional branches that exceed the
6219 maximum range of a simple branch instruction. */
6222 output_lbranch (rtx dest, rtx insn)
6226 xoperands[0] = dest;
6228 /* First, free up the delay slot. */
6229 if (dbr_sequence_length () != 0)
6231 /* We can't handle a jump in the delay slot. */
6232 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6235 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6236 optimize, 0, 0, NULL);
6238 /* Now delete the delay insn. */
6239 PUT_CODE (NEXT_INSN (insn), NOTE);
6240 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6241 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6244 /* Output an insn to save %r1. The runtime documentation doesn't
6245 specify whether the "Clean Up" slot in the callers frame can
6246 be clobbered by the callee. It isn't copied by HP's builtin
6247 alloca, so this suggests that it can be clobbered if necessary.
6248 The "Static Link" location is copied by HP builtin alloca, so
6249 we avoid using it. Using the cleanup slot might be a problem
6250 if we have to interoperate with languages that pass cleanup
6251 information. However, it should be possible to handle these
6252 situations with GCC's asm feature.
6254 The "Current RP" slot is reserved for the called procedure, so
6255 we try to use it when we don't have a frame of our own. It's
6256 rather unlikely that we won't have a frame when we need to emit
6259 Really the way to go long term is a register scavenger; goto
6260 the target of the jump and find a register which we can use
6261 as a scratch to hold the value in %r1. Then, we wouldn't have
6262 to free up the delay slot or clobber a slot that may be needed
6263 for other purposes. */
6266 if (actual_fsize == 0 && !regs_ever_live[2])
6267 /* Use the return pointer slot in the frame marker. */
6268 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6270 /* Use the slot at -40 in the frame marker since HP builtin
6271 alloca doesn't copy it. */
6272 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6276 if (actual_fsize == 0 && !regs_ever_live[2])
6277 /* Use the return pointer slot in the frame marker. */
6278 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6280 /* Use the "Clean Up" slot in the frame marker. In GCC,
6281 the only other use of this location is for copying a
6282 floating point double argument from a floating-point
6283 register to two general registers. The copy is done
6284 as an "atomic" operation when outputting a call, so it
6285 won't interfere with our using the location here. */
6286 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6289 if (TARGET_PORTABLE_RUNTIME)
6291 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6292 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6293 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6297 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6298 if (TARGET_SOM || !TARGET_GAS)
6300 xoperands[1] = gen_label_rtx ();
6301 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6302 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6303 CODE_LABEL_NUMBER (xoperands[1]));
6304 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6308 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6309 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6311 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6314 /* Now output a very long branch to the original target. */
6315 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6317 /* Now restore the value of %r1 in the delay slot. */
6320 if (actual_fsize == 0 && !regs_ever_live[2])
6321 return "ldd -16(%%r30),%%r1";
6323 return "ldd -40(%%r30),%%r1";
6327 if (actual_fsize == 0 && !regs_ever_live[2])
6328 return "ldw -20(%%r30),%%r1";
6330 return "ldw -12(%%r30),%%r1";
6334 /* This routine handles all the branch-on-bit conditional branch sequences we
6335 might need to generate. It handles nullification of delay slots,
6336 varying length branches, negated branches and all combinations of the
6337 above. it returns the appropriate output template to emit the branch. */
6340 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6341 int negated, rtx insn, int which)
6343 static char buf[100];
6346 /* A conditional branch to the following instruction (eg the delay slot) is
6347 asking for a disaster. I do not think this can happen as this pattern
6348 is only used when optimizing; jump optimization should eliminate the
6349 jump. But be prepared just in case. */
6351 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6354 /* If this is a long branch with its delay slot unfilled, set `nullify'
6355 as it can nullify the delay slot and save a nop. */
6356 if (length == 8 && dbr_sequence_length () == 0)
6359 /* If this is a short forward conditional branch which did not get
6360 its delay slot filled, the delay slot can still be nullified. */
6361 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6362 nullify = forward_branch_p (insn);
6364 /* A forward branch over a single nullified insn can be done with a
6365 extrs instruction. This avoids a single cycle penalty due to
6366 mis-predicted branch if we fall through (branch not taken). */
6369 && next_real_insn (insn) != 0
6370 && get_attr_length (next_real_insn (insn)) == 4
6371 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6378 /* All short conditional branches except backwards with an unfilled
6382 strcpy (buf, "{extrs,|extrw,s,}");
6384 strcpy (buf, "bb,");
6385 if (useskip && GET_MODE (operands[0]) == DImode)
6386 strcpy (buf, "extrd,s,*");
6387 else if (GET_MODE (operands[0]) == DImode)
6388 strcpy (buf, "bb,*");
6389 if ((which == 0 && negated)
6390 || (which == 1 && ! negated))
6395 strcat (buf, " %0,%1,1,%%r0");
6396 else if (nullify && negated)
6397 strcat (buf, ",n %0,%1,%3");
6398 else if (nullify && ! negated)
6399 strcat (buf, ",n %0,%1,%2");
6400 else if (! nullify && negated)
6401 strcat (buf, "%0,%1,%3");
6402 else if (! nullify && ! negated)
6403 strcat (buf, " %0,%1,%2");
6406 /* All long conditionals. Note a short backward branch with an
6407 unfilled delay slot is treated just like a long backward branch
6408 with an unfilled delay slot. */
6410 /* Handle weird backwards branch with a filled delay slot
6411 with is nullified. */
6412 if (dbr_sequence_length () != 0
6413 && ! forward_branch_p (insn)
6416 strcpy (buf, "bb,");
6417 if (GET_MODE (operands[0]) == DImode)
6419 if ((which == 0 && negated)
6420 || (which == 1 && ! negated))
6425 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6427 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6429 /* Handle short backwards branch with an unfilled delay slot.
6430 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6431 taken and untaken branches. */
6432 else if (dbr_sequence_length () == 0
6433 && ! forward_branch_p (insn)
6434 && INSN_ADDRESSES_SET_P ()
6435 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6436 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6438 strcpy (buf, "bb,");
6439 if (GET_MODE (operands[0]) == DImode)
6441 if ((which == 0 && negated)
6442 || (which == 1 && ! negated))
6447 strcat (buf, " %0,%1,%3%#");
6449 strcat (buf, " %0,%1,%2%#");
6453 strcpy (buf, "{extrs,|extrw,s,}");
6454 if (GET_MODE (operands[0]) == DImode)
6455 strcpy (buf, "extrd,s,*");
6456 if ((which == 0 && negated)
6457 || (which == 1 && ! negated))
6461 if (nullify && negated)
6462 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6463 else if (nullify && ! negated)
6464 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6466 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6468 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6478 /* This routine handles all the branch-on-variable-bit conditional branch
6479 sequences we might need to generate. It handles nullification of delay
6480 slots, varying length branches, negated branches and all combinations
6481 of the above. it returns the appropriate output template to emit the
6485 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6486 int negated, rtx insn, int which)
6488 static char buf[100];
6491 /* A conditional branch to the following instruction (eg the delay slot) is
6492 asking for a disaster. I do not think this can happen as this pattern
6493 is only used when optimizing; jump optimization should eliminate the
6494 jump. But be prepared just in case. */
6496 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6499 /* If this is a long branch with its delay slot unfilled, set `nullify'
6500 as it can nullify the delay slot and save a nop. */
6501 if (length == 8 && dbr_sequence_length () == 0)
6504 /* If this is a short forward conditional branch which did not get
6505 its delay slot filled, the delay slot can still be nullified. */
6506 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6507 nullify = forward_branch_p (insn);
6509 /* A forward branch over a single nullified insn can be done with a
6510 extrs instruction. This avoids a single cycle penalty due to
6511 mis-predicted branch if we fall through (branch not taken). */
6514 && next_real_insn (insn) != 0
6515 && get_attr_length (next_real_insn (insn)) == 4
6516 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6523 /* All short conditional branches except backwards with an unfilled
6527 strcpy (buf, "{vextrs,|extrw,s,}");
6529 strcpy (buf, "{bvb,|bb,}");
6530 if (useskip && GET_MODE (operands[0]) == DImode)
6531 strcpy (buf, "extrd,s,*");
6532 else if (GET_MODE (operands[0]) == DImode)
6533 strcpy (buf, "bb,*");
6534 if ((which == 0 && negated)
6535 || (which == 1 && ! negated))
6540 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6541 else if (nullify && negated)
6542 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6543 else if (nullify && ! negated)
6544 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6545 else if (! nullify && negated)
6546 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6547 else if (! nullify && ! negated)
6548 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6551 /* All long conditionals. Note a short backward branch with an
6552 unfilled delay slot is treated just like a long backward branch
6553 with an unfilled delay slot. */
6555 /* Handle weird backwards branch with a filled delay slot
6556 with is nullified. */
6557 if (dbr_sequence_length () != 0
6558 && ! forward_branch_p (insn)
6561 strcpy (buf, "{bvb,|bb,}");
6562 if (GET_MODE (operands[0]) == DImode)
6564 if ((which == 0 && negated)
6565 || (which == 1 && ! negated))
6570 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6572 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6574 /* Handle short backwards branch with an unfilled delay slot.
6575 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6576 taken and untaken branches. */
6577 else if (dbr_sequence_length () == 0
6578 && ! forward_branch_p (insn)
6579 && INSN_ADDRESSES_SET_P ()
6580 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6581 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6583 strcpy (buf, "{bvb,|bb,}");
6584 if (GET_MODE (operands[0]) == DImode)
6586 if ((which == 0 && negated)
6587 || (which == 1 && ! negated))
6592 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6594 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6598 strcpy (buf, "{vextrs,|extrw,s,}");
6599 if (GET_MODE (operands[0]) == DImode)
6600 strcpy (buf, "extrd,s,*");
6601 if ((which == 0 && negated)
6602 || (which == 1 && ! negated))
6606 if (nullify && negated)
6607 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6608 else if (nullify && ! negated)
6609 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6611 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6613 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6623 /* Return the output template for emitting a dbra type insn.
6625 Note it may perform some output operations on its own before
6626 returning the final output string. */
6628 output_dbra (rtx *operands, rtx insn, int which_alternative)
6631 /* A conditional branch to the following instruction (eg the delay slot) is
6632 asking for a disaster. Be prepared! */
6634 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6636 if (which_alternative == 0)
6637 return "ldo %1(%0),%0";
6638 else if (which_alternative == 1)
6640 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6641 output_asm_insn ("ldw -16(%%r30),%4", operands);
6642 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6643 return "{fldws|fldw} -16(%%r30),%0";
6647 output_asm_insn ("ldw %0,%4", operands);
6648 return "ldo %1(%4),%4\n\tstw %4,%0";
6652 if (which_alternative == 0)
6654 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6655 int length = get_attr_length (insn);
6657 /* If this is a long branch with its delay slot unfilled, set `nullify'
6658 as it can nullify the delay slot and save a nop. */
6659 if (length == 8 && dbr_sequence_length () == 0)
6662 /* If this is a short forward conditional branch which did not get
6663 its delay slot filled, the delay slot can still be nullified. */
6664 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6665 nullify = forward_branch_p (insn);
6667 /* Handle short versions first. */
6668 if (length == 4 && nullify)
6669 return "addib,%C2,n %1,%0,%3";
6670 else if (length == 4 && ! nullify)
6671 return "addib,%C2 %1,%0,%3";
6672 else if (length == 8)
6674 /* Handle weird backwards branch with a fulled delay slot
6675 which is nullified. */
6676 if (dbr_sequence_length () != 0
6677 && ! forward_branch_p (insn)
6679 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6680 /* Handle short backwards branch with an unfilled delay slot.
6681 Using a addb;nop rather than addi;bl saves 1 cycle for both
6682 taken and untaken branches. */
6683 else if (dbr_sequence_length () == 0
6684 && ! forward_branch_p (insn)
6685 && INSN_ADDRESSES_SET_P ()
6686 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6687 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6688 return "addib,%C2 %1,%0,%3%#";
6690 /* Handle normal cases. */
6692 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6694 return "addi,%N2 %1,%0,%0\n\tb %3";
6699 /* Deal with gross reload from FP register case. */
6700 else if (which_alternative == 1)
6702 /* Move loop counter from FP register to MEM then into a GR,
6703 increment the GR, store the GR into MEM, and finally reload
6704 the FP register from MEM from within the branch's delay slot. */
6705 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6707 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6708 if (get_attr_length (insn) == 24)
6709 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6711 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6713 /* Deal with gross reload from memory case. */
6716 /* Reload loop counter from memory, the store back to memory
6717 happens in the branch's delay slot. */
6718 output_asm_insn ("ldw %0,%4", operands);
6719 if (get_attr_length (insn) == 12)
6720 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6722 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6726 /* Return the output template for emitting a dbra type insn.
6728 Note it may perform some output operations on its own before
6729 returning the final output string. */
6731 output_movb (rtx *operands, rtx insn, int which_alternative,
6732 int reverse_comparison)
6735 /* A conditional branch to the following instruction (eg the delay slot) is
6736 asking for a disaster. Be prepared! */
6738 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6740 if (which_alternative == 0)
6741 return "copy %1,%0";
6742 else if (which_alternative == 1)
6744 output_asm_insn ("stw %1,-16(%%r30)", operands);
6745 return "{fldws|fldw} -16(%%r30),%0";
6747 else if (which_alternative == 2)
6753 /* Support the second variant. */
6754 if (reverse_comparison)
6755 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6757 if (which_alternative == 0)
6759 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6760 int length = get_attr_length (insn);
6762 /* If this is a long branch with its delay slot unfilled, set `nullify'
6763 as it can nullify the delay slot and save a nop. */
6764 if (length == 8 && dbr_sequence_length () == 0)
6767 /* If this is a short forward conditional branch which did not get
6768 its delay slot filled, the delay slot can still be nullified. */
6769 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6770 nullify = forward_branch_p (insn);
6772 /* Handle short versions first. */
6773 if (length == 4 && nullify)
6774 return "movb,%C2,n %1,%0,%3";
6775 else if (length == 4 && ! nullify)
6776 return "movb,%C2 %1,%0,%3";
6777 else if (length == 8)
6779 /* Handle weird backwards branch with a filled delay slot
6780 which is nullified. */
6781 if (dbr_sequence_length () != 0
6782 && ! forward_branch_p (insn)
6784 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6786 /* Handle short backwards branch with an unfilled delay slot.
6787 Using a movb;nop rather than or;bl saves 1 cycle for both
6788 taken and untaken branches. */
6789 else if (dbr_sequence_length () == 0
6790 && ! forward_branch_p (insn)
6791 && INSN_ADDRESSES_SET_P ()
6792 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6793 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6794 return "movb,%C2 %1,%0,%3%#";
6795 /* Handle normal cases. */
6797 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6799 return "or,%N2 %1,%%r0,%0\n\tb %3";
6804 /* Deal with gross reload from FP register case. */
6805 else if (which_alternative == 1)
6807 /* Move loop counter from FP register to MEM then into a GR,
6808 increment the GR, store the GR into MEM, and finally reload
6809 the FP register from MEM from within the branch's delay slot. */
6810 output_asm_insn ("stw %1,-16(%%r30)", operands);
6811 if (get_attr_length (insn) == 12)
6812 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6814 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6816 /* Deal with gross reload from memory case. */
6817 else if (which_alternative == 2)
6819 /* Reload loop counter from memory, the store back to memory
6820 happens in the branch's delay slot. */
6821 if (get_attr_length (insn) == 8)
6822 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6824 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6826 /* Handle SAR as a destination. */
6829 if (get_attr_length (insn) == 8)
6830 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6832 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6836 /* Copy any FP arguments in INSN into integer registers. */
6838 copy_fp_args (rtx insn)
6843 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6845 int arg_mode, regno;
6846 rtx use = XEXP (link, 0);
6848 if (! (GET_CODE (use) == USE
6849 && GET_CODE (XEXP (use, 0)) == REG
6850 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6853 arg_mode = GET_MODE (XEXP (use, 0));
6854 regno = REGNO (XEXP (use, 0));
6856 /* Is it a floating point register? */
6857 if (regno >= 32 && regno <= 39)
6859 /* Copy the FP register into an integer register via memory. */
6860 if (arg_mode == SFmode)
6862 xoperands[0] = XEXP (use, 0);
6863 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6864 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6865 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6869 xoperands[0] = XEXP (use, 0);
6870 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6871 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6872 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6873 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6879 /* Compute length of the FP argument copy sequence for INSN. */
6881 length_fp_args (rtx insn)
6886 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6888 int arg_mode, regno;
6889 rtx use = XEXP (link, 0);
6891 if (! (GET_CODE (use) == USE
6892 && GET_CODE (XEXP (use, 0)) == REG
6893 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6896 arg_mode = GET_MODE (XEXP (use, 0));
6897 regno = REGNO (XEXP (use, 0));
6899 /* Is it a floating point register? */
6900 if (regno >= 32 && regno <= 39)
6902 if (arg_mode == SFmode)
6912 /* Return the attribute length for the millicode call instruction INSN.
6913 The length must match the code generated by output_millicode_call.
6914 We include the delay slot in the returned length as it is better to
6915 over estimate the length than to under estimate it. */
6918 attr_length_millicode_call (rtx insn)
6920 unsigned long distance = -1;
6921 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6923 if (INSN_ADDRESSES_SET_P ())
6925 distance = (total + insn_current_reference_address (insn));
6926 if (distance < total)
6932 if (!TARGET_LONG_CALLS && distance < 7600000)
6937 else if (TARGET_PORTABLE_RUNTIME)
6941 if (!TARGET_LONG_CALLS && distance < 240000)
6944 if (TARGET_LONG_ABS_CALL && !flag_pic)
6951 /* INSN is a function call. It may have an unconditional jump
6954 CALL_DEST is the routine we are calling. */
6957 output_millicode_call (rtx insn, rtx call_dest)
6959 int attr_length = get_attr_length (insn);
6960 int seq_length = dbr_sequence_length ();
6965 xoperands[0] = call_dest;
6966 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6968 /* Handle the common case where we are sure that the branch will
6969 reach the beginning of the $CODE$ subspace. The within reach
6970 form of the $$sh_func_adrs call has a length of 28. Because
6971 it has an attribute type of multi, it never has a nonzero
6972 sequence length. The length of the $$sh_func_adrs is the same
6973 as certain out of reach PIC calls to other routines. */
6974 if (!TARGET_LONG_CALLS
6975 && ((seq_length == 0
6976 && (attr_length == 12
6977 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6978 || (seq_length != 0 && attr_length == 8)))
6980 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6986 /* It might seem that one insn could be saved by accessing
6987 the millicode function using the linkage table. However,
6988 this doesn't work in shared libraries and other dynamically
6989 loaded objects. Using a pc-relative sequence also avoids
6990 problems related to the implicit use of the gp register. */
6991 output_asm_insn ("b,l .+8,%%r1", xoperands);
6995 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6996 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7000 xoperands[1] = gen_label_rtx ();
7001 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7002 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7003 CODE_LABEL_NUMBER (xoperands[1]));
7004 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7007 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7009 else if (TARGET_PORTABLE_RUNTIME)
7011 /* Pure portable runtime doesn't allow be/ble; we also don't
7012 have PIC support in the assembler/linker, so this sequence
7015 /* Get the address of our target into %r1. */
7016 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7017 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7019 /* Get our return address into %r31. */
7020 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7021 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7023 /* Jump to our target address in %r1. */
7024 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7028 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7030 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7032 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7036 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7037 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7039 if (TARGET_SOM || !TARGET_GAS)
7041 /* The HP assembler can generate relocations for the
7042 difference of two symbols. GAS can do this for a
7043 millicode symbol but not an arbitrary external
7044 symbol when generating SOM output. */
7045 xoperands[1] = gen_label_rtx ();
7046 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7047 CODE_LABEL_NUMBER (xoperands[1]));
7048 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7049 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7053 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7054 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7058 /* Jump to our target address in %r1. */
7059 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7063 if (seq_length == 0)
7064 output_asm_insn ("nop", xoperands);
7066 /* We are done if there isn't a jump in the delay slot. */
7067 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7070 /* This call has an unconditional jump in its delay slot. */
7071 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7073 /* See if the return address can be adjusted. Use the containing
7074 sequence insn's address. */
7075 if (INSN_ADDRESSES_SET_P ())
7077 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7078 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7079 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7081 if (VAL_14_BITS_P (distance))
7083 xoperands[1] = gen_label_rtx ();
7084 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7085 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7086 CODE_LABEL_NUMBER (xoperands[1]));
7089 /* ??? This branch may not reach its target. */
7090 output_asm_insn ("nop\n\tb,n %0", xoperands);
7093 /* ??? This branch may not reach its target. */
7094 output_asm_insn ("nop\n\tb,n %0", xoperands);
7096 /* Delete the jump. */
7097 PUT_CODE (NEXT_INSN (insn), NOTE);
7098 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7099 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7104 /* Return the attribute length of the call instruction INSN. The SIBCALL
7105 flag indicates whether INSN is a regular call or a sibling call. The
7106 length returned must be longer than the code actually generated by
7107 output_call. Since branch shortening is done before delay branch
7108 sequencing, there is no way to determine whether or not the delay
7109 slot will be filled during branch shortening. Even when the delay
7110 slot is filled, we may have to add a nop if the delay slot contains
7111 a branch that can't reach its target. Thus, we always have to include
7112 the delay slot in the length estimate. This used to be done in
7113 pa_adjust_insn_length but we do it here now as some sequences always
7114 fill the delay slot and we can save four bytes in the estimate for
7118 attr_length_call (rtx insn, int sibcall)
7124 rtx pat = PATTERN (insn);
7125 unsigned long distance = -1;
7127 if (INSN_ADDRESSES_SET_P ())
7129 unsigned long total;
7131 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7132 distance = (total + insn_current_reference_address (insn));
7133 if (distance < total)
7137 /* Determine if this is a local call. */
7138 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7139 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7141 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7143 call_decl = SYMBOL_REF_DECL (call_dest);
7144 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7146 /* pc-relative branch. */
7147 if (!TARGET_LONG_CALLS
7148 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7149 || distance < 240000))
7152 /* 64-bit plabel sequence. */
7153 else if (TARGET_64BIT && !local_call)
7154 length += sibcall ? 28 : 24;
7156 /* non-pic long absolute branch sequence. */
7157 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7160 /* long pc-relative branch sequence. */
7161 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7162 || (TARGET_64BIT && !TARGET_GAS)
7163 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7167 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7171 /* 32-bit plabel sequence. */
7177 length += length_fp_args (insn);
7187 if (!TARGET_NO_SPACE_REGS)
7195 /* INSN is a function call. It may have an unconditional jump
7198 CALL_DEST is the routine we are calling. */
7201 output_call (rtx insn, rtx call_dest, int sibcall)
7203 int delay_insn_deleted = 0;
7204 int delay_slot_filled = 0;
7205 int seq_length = dbr_sequence_length ();
7206 tree call_decl = SYMBOL_REF_DECL (call_dest);
7207 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7210 xoperands[0] = call_dest;
7212 /* Handle the common case where we're sure that the branch will reach
7213 the beginning of the "$CODE$" subspace. This is the beginning of
7214 the current function if we are in a named section. */
7215 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7217 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7218 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7222 if (TARGET_64BIT && !local_call)
7224 /* ??? As far as I can tell, the HP linker doesn't support the
7225 long pc-relative sequence described in the 64-bit runtime
7226 architecture. So, we use a slightly longer indirect call. */
7227 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7229 xoperands[0] = p->internal_label;
7230 xoperands[1] = gen_label_rtx ();
7232 /* If this isn't a sibcall, we put the load of %r27 into the
7233 delay slot. We can't do this in a sibcall as we don't
7234 have a second call-clobbered scratch register available. */
7236 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7239 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7240 optimize, 0, 0, NULL);
7242 /* Now delete the delay insn. */
7243 PUT_CODE (NEXT_INSN (insn), NOTE);
7244 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7245 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7246 delay_insn_deleted = 1;
7249 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7250 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7251 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7255 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7256 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7257 output_asm_insn ("bve (%%r1)", xoperands);
7261 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7262 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7263 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7264 delay_slot_filled = 1;
7269 int indirect_call = 0;
7271 /* Emit a long call. There are several different sequences
7272 of increasing length and complexity. In most cases,
7273 they don't allow an instruction in the delay slot. */
7274 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7275 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7276 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7281 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7283 && (!TARGET_PA_20 || indirect_call))
7285 /* A non-jump insn in the delay slot. By definition we can
7286 emit this insn before the call (and in fact before argument
7288 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7291 /* Now delete the delay insn. */
7292 PUT_CODE (NEXT_INSN (insn), NOTE);
7293 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7294 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7295 delay_insn_deleted = 1;
7298 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7300 /* This is the best sequence for making long calls in
7301 non-pic code. Unfortunately, GNU ld doesn't provide
7302 the stub needed for external calls, and GAS's support
7303 for this with the SOM linker is buggy. It is safe
7304 to use this for local calls. */
7305 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7307 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7311 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7314 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7316 output_asm_insn ("copy %%r31,%%r2", xoperands);
7317 delay_slot_filled = 1;
7322 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7323 || (TARGET_64BIT && !TARGET_GAS))
7325 /* The HP assembler and linker can handle relocations
7326 for the difference of two symbols. GAS and the HP
7327 linker can't do this when one of the symbols is
7329 xoperands[1] = gen_label_rtx ();
7330 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7331 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7332 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7333 CODE_LABEL_NUMBER (xoperands[1]));
7334 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7336 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7338 /* GAS currently can't generate the relocations that
7339 are needed for the SOM linker under HP-UX using this
7340 sequence. The GNU linker doesn't generate the stubs
7341 that are needed for external calls on TARGET_ELF32
7342 with this sequence. For now, we have to use a
7343 longer plabel sequence when using GAS. */
7344 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7345 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7347 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7352 /* Emit a long plabel-based call sequence. This is
7353 essentially an inline implementation of $$dyncall.
7354 We don't actually try to call $$dyncall as this is
7355 as difficult as calling the function itself. */
7356 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7358 xoperands[0] = p->internal_label;
7359 xoperands[1] = gen_label_rtx ();
7361 /* Since the call is indirect, FP arguments in registers
7362 need to be copied to the general registers. Then, the
7363 argument relocation stub will copy them back. */
7365 copy_fp_args (insn);
7369 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7370 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7371 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7375 output_asm_insn ("addil LR'%0-$global$,%%r27",
7377 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7381 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7382 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7383 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7384 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7386 if (!sibcall && !TARGET_PA_20)
7388 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7389 if (TARGET_NO_SPACE_REGS)
7390 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7392 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7399 output_asm_insn ("bve (%%r1)", xoperands);
7404 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7405 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7406 delay_slot_filled = 1;
7409 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7414 if (!TARGET_NO_SPACE_REGS)
7415 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7420 if (TARGET_NO_SPACE_REGS)
7421 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7423 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7427 if (TARGET_NO_SPACE_REGS)
7428 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7430 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7433 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7435 output_asm_insn ("copy %%r31,%%r2", xoperands);
7436 delay_slot_filled = 1;
7443 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7444 output_asm_insn ("nop", xoperands);
7446 /* We are done if there isn't a jump in the delay slot. */
7448 || delay_insn_deleted
7449 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7452 /* A sibcall should never have a branch in the delay slot. */
7456 /* This call has an unconditional jump in its delay slot. */
7457 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7459 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7461 /* See if the return address can be adjusted. Use the containing
7462 sequence insn's address. */
7463 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7464 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7465 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7467 if (VAL_14_BITS_P (distance))
7469 xoperands[1] = gen_label_rtx ();
7470 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7471 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7472 CODE_LABEL_NUMBER (xoperands[1]));
7475 output_asm_insn ("nop\n\tb,n %0", xoperands);
7478 output_asm_insn ("b,n %0", xoperands);
7480 /* Delete the jump. */
7481 PUT_CODE (NEXT_INSN (insn), NOTE);
7482 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7483 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7488 /* Return the attribute length of the indirect call instruction INSN.
7489 The length must match the code generated by output_indirect call.
7490 The returned length includes the delay slot. Currently, the delay
7491 slot of an indirect call sequence is not exposed and it is used by
7492 the sequence itself. */
7495 attr_length_indirect_call (rtx insn)
7497 unsigned long distance = -1;
7498 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7500 if (INSN_ADDRESSES_SET_P ())
7502 distance = (total + insn_current_reference_address (insn));
7503 if (distance < total)
7510 if (TARGET_FAST_INDIRECT_CALLS
7511 || (!TARGET_PORTABLE_RUNTIME
7512 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7518 if (TARGET_PORTABLE_RUNTIME)
7521 /* Out of reach, can use ble. */
7526 output_indirect_call (rtx insn, rtx call_dest)
7532 xoperands[0] = call_dest;
7533 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7534 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7538 /* First the special case for kernels, level 0 systems, etc. */
7539 if (TARGET_FAST_INDIRECT_CALLS)
7540 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7542 /* Now the normal case -- we can reach $$dyncall directly or
7543 we're sure that we can get there via a long-branch stub.
7545 No need to check target flags as the length uniquely identifies
7546 the remaining cases. */
7547 if (attr_length_indirect_call (insn) == 8)
7548 return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7550 /* Long millicode call, but we are not generating PIC or portable runtime
7552 if (attr_length_indirect_call (insn) == 12)
7553 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7555 /* Long millicode call for portable runtime. */
7556 if (attr_length_indirect_call (insn) == 20)
7557 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7559 /* We need a long PIC call to $$dyncall. */
7560 xoperands[0] = NULL_RTX;
7561 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7562 if (TARGET_SOM || !TARGET_GAS)
7564 xoperands[0] = gen_label_rtx ();
7565 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7566 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7567 CODE_LABEL_NUMBER (xoperands[0]));
7568 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7572 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7573 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7576 output_asm_insn ("blr %%r0,%%r2", xoperands);
7577 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7581 /* Return the total length of the save and restore instructions needed for
7582 the data linkage table pointer (i.e., the PIC register) across the call
7583 instruction INSN. No-return calls do not require a save and restore.
7584 In addition, we may be able to avoid the save and restore for calls
7585 within the same translation unit. */
7588 attr_length_save_restore_dltp (rtx insn)
7590 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7596 /* In HPUX 8.0's shared library scheme, special relocations are needed
7597 for function labels if they might be passed to a function
7598 in a shared library (because shared libraries don't live in code
7599 space), and special magic is needed to construct their address. */
7602 hppa_encode_label (rtx sym)
7604 const char *str = XSTR (sym, 0);
7605 int len = strlen (str) + 1;
7608 p = newstr = alloca (len + 1);
7612 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7616 pa_encode_section_info (tree decl, rtx rtl, int first)
7618 if (first && TEXT_SPACE_P (decl))
7620 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7621 if (TREE_CODE (decl) == FUNCTION_DECL)
7622 hppa_encode_label (XEXP (rtl, 0));
7626 /* This is sort of inverse to pa_encode_section_info. */
7629 pa_strip_name_encoding (const char *str)
7631 str += (*str == '@');
7632 str += (*str == '*');
7637 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7639 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7642 /* Returns 1 if OP is a function label involved in a simple addition
7643 with a constant. Used to keep certain patterns from matching
7644 during instruction combination. */
7646 is_function_label_plus_const (rtx op)
7648 /* Strip off any CONST. */
7649 if (GET_CODE (op) == CONST)
7652 return (GET_CODE (op) == PLUS
7653 && function_label_operand (XEXP (op, 0), Pmode)
7654 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7657 /* Output assembly code for a thunk to FUNCTION. */
7660 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7661 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7664 const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7665 const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
7666 int val_14 = VAL_14_BITS_P (delta);
7668 static unsigned int current_thunk_number;
7671 ASM_OUTPUT_LABEL (file, tname);
7672 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7674 fname = (*targetm.strip_name_encoding) (fname);
7675 tname = (*targetm.strip_name_encoding) (tname);
7677 /* Output the thunk. We know that the function is in the same
7678 translation unit (i.e., the same space) as the thunk, and that
7679 thunks are output after their method. Thus, we don't need an
7680 external branch to reach the function. With SOM and GAS,
7681 functions and thunks are effectively in different sections.
7682 Thus, we can always use a IA-relative branch and the linker
7683 will add a long branch stub if necessary.
7685 However, we have to be careful when generating PIC code on the
7686 SOM port to ensure that the sequence does not transfer to an
7687 import stub for the target function as this could clobber the
7688 return value saved at SP-24. This would also apply to the
7689 32-bit linux port if the multi-space model is implemented. */
7690 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7691 && !(flag_pic && TREE_PUBLIC (function))
7692 && (TARGET_GAS || last_address < 262132))
7693 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7694 && ((targetm.have_named_sections
7695 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7696 /* The GNU 64-bit linker has rather poor stub management.
7697 So, we use a long branch from thunks that aren't in
7698 the same section as the target function. */
7700 && (DECL_SECTION_NAME (thunk_fndecl)
7701 != DECL_SECTION_NAME (function)))
7702 || ((DECL_SECTION_NAME (thunk_fndecl)
7703 == DECL_SECTION_NAME (function))
7704 && last_address < 262132)))
7705 || (!targetm.have_named_sections && last_address < 262132))))
7709 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7710 "(%%r26),%%r26\n", fname, delta);
7715 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7717 fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7718 "(%%r1),%%r26\n", fname, delta);
7722 else if (TARGET_64BIT)
7724 /* We only have one call-clobbered scratch register, so we can't
7725 make use of the delay slot if delta doesn't fit in 14 bits. */
7727 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7728 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7729 "(%%r1),%%r26\n", delta, delta);
7731 fprintf (file, "\tb,l .+8,%%r1\n");
7735 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7736 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname);
7740 int off = val_14 ? 8 : 16;
7741 fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off);
7742 fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off);
7747 fprintf (file, "\tbv %%r0(%%r1)\n\tldo ");
7748 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7753 fprintf (file, "\tbv,n %%r0(%%r1)\n");
7757 else if (TARGET_PORTABLE_RUNTIME)
7759 fprintf (file, "\tldil L'%s,%%r1\n", fname);
7760 fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname);
7764 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7765 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7770 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7772 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7773 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7777 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7779 /* The function is accessible from outside this module. The only
7780 way to avoid an import stub between the thunk and function is to
7781 call the function directly with an indirect sequence similar to
7782 that used by $$dyncall. This is possible because $$dyncall acts
7783 as the import stub in an indirect call. */
7786 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7787 lab = (*targetm.strip_name_encoding) (label);
7789 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7790 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7791 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7792 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7793 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7794 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7795 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7798 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7804 fprintf (file, "\tbve (%%r22)\n\tldo ");
7809 if (TARGET_NO_SPACE_REGS)
7811 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7816 fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
7817 fprintf (file, "\tmtsp %%r21,%%sr0\n");
7818 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7824 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7826 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7831 fprintf (file, "\tb,l .+8,%%r1\n");
7833 fprintf (file, "\tbl .+8,%%r1\n");
7835 if (TARGET_SOM || !TARGET_GAS)
7837 fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname);
7838 fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname);
7842 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7843 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname);
7848 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7849 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7854 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7856 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7857 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7864 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta);
7866 fprintf (file, "\tldil L'%s,%%r22\n", fname);
7867 fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname);
7871 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7876 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7881 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7883 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7886 fprintf (file, "\t.align 4\n");
7887 ASM_OUTPUT_LABEL (file, label);
7888 fprintf (file, "\t.word P'%s\n", fname);
7889 function_section (thunk_fndecl);
7892 current_thunk_number++;
7893 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7894 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7895 last_address += nbytes;
7896 update_total_code_bytes (nbytes);
7899 /* Only direct calls to static functions are allowed to be sibling (tail)
7902 This restriction is necessary because some linker generated stubs will
7903 store return pointers into rp' in some cases which might clobber a
7904 live value already in rp'.
7906 In a sibcall the current function and the target function share stack
7907 space. Thus if the path to the current function and the path to the
7908 target function save a value in rp', they save the value into the
7909 same stack slot, which has undesirable consequences.
7911 Because of the deferred binding nature of shared libraries any function
7912 with external scope could be in a different load module and thus require
7913 rp' to be saved when calling that function. So sibcall optimizations
7914 can only be safe for static function.
7916 Note that GCC never needs return value relocations, so we don't have to
7917 worry about static calls with return value relocations (which require
7920 It is safe to perform a sibcall optimization when the target function
7921 will never return. */
7923 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7925 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7926 single subspace mode and the call is not indirect. As far as I know,
7927 there is no operating system support for the multiple subspace mode.
7928 It might be possible to support indirect calls if we didn't use
7929 $$dyncall (see the indirect sequence generated in output_call). */
7931 return (decl != NULL_TREE);
7933 /* Sibcalls are not ok because the arg pointer register is not a fixed
7934 register. This prevents the sibcall optimization from occurring. In
7935 addition, there are problems with stub placement using GNU ld. This
7936 is because a normal sibcall branch uses a 17-bit relocation while
7937 a regular call branch uses a 22-bit relocation. As a result, more
7938 care needs to be taken in the placement of long-branch stubs. */
7943 && !TARGET_PORTABLE_RUNTIME
7944 && !TREE_PUBLIC (decl));
7947 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7948 use in fmpyadd instructions. */
7950 fmpyaddoperands (rtx *operands)
7952 enum machine_mode mode = GET_MODE (operands[0]);
7954 /* Must be a floating point mode. */
7955 if (mode != SFmode && mode != DFmode)
7958 /* All modes must be the same. */
7959 if (! (mode == GET_MODE (operands[1])
7960 && mode == GET_MODE (operands[2])
7961 && mode == GET_MODE (operands[3])
7962 && mode == GET_MODE (operands[4])
7963 && mode == GET_MODE (operands[5])))
7966 /* All operands must be registers. */
7967 if (! (GET_CODE (operands[1]) == REG
7968 && GET_CODE (operands[2]) == REG
7969 && GET_CODE (operands[3]) == REG
7970 && GET_CODE (operands[4]) == REG
7971 && GET_CODE (operands[5]) == REG))
7974 /* Only 2 real operands to the addition. One of the input operands must
7975 be the same as the output operand. */
7976 if (! rtx_equal_p (operands[3], operands[4])
7977 && ! rtx_equal_p (operands[3], operands[5]))
7980 /* Inout operand of add can not conflict with any operands from multiply. */
7981 if (rtx_equal_p (operands[3], operands[0])
7982 || rtx_equal_p (operands[3], operands[1])
7983 || rtx_equal_p (operands[3], operands[2]))
7986 /* multiply can not feed into addition operands. */
7987 if (rtx_equal_p (operands[4], operands[0])
7988 || rtx_equal_p (operands[5], operands[0]))
7991 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7993 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7994 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7995 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7996 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7997 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7998 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8001 /* Passed. Operands are suitable for fmpyadd. */
8005 #if !defined(USE_COLLECT2)
8007 pa_asm_out_constructor (rtx symbol, int priority)
8009 if (!function_label_operand (symbol, VOIDmode))
8010 hppa_encode_label (symbol);
8012 #ifdef CTORS_SECTION_ASM_OP
8013 default_ctor_section_asm_out_constructor (symbol, priority);
8015 # ifdef TARGET_ASM_NAMED_SECTION
8016 default_named_section_asm_out_constructor (symbol, priority);
8018 default_stabs_asm_out_constructor (symbol, priority);
8024 pa_asm_out_destructor (rtx symbol, int priority)
8026 if (!function_label_operand (symbol, VOIDmode))
8027 hppa_encode_label (symbol);
8029 #ifdef DTORS_SECTION_ASM_OP
8030 default_dtor_section_asm_out_destructor (symbol, priority);
8032 # ifdef TARGET_ASM_NAMED_SECTION
8033 default_named_section_asm_out_destructor (symbol, priority);
8035 default_stabs_asm_out_destructor (symbol, priority);
8041 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8042 use in fmpysub instructions. */
8044 fmpysuboperands (rtx *operands)
8046 enum machine_mode mode = GET_MODE (operands[0]);
8048 /* Must be a floating point mode. */
8049 if (mode != SFmode && mode != DFmode)
8052 /* All modes must be the same. */
8053 if (! (mode == GET_MODE (operands[1])
8054 && mode == GET_MODE (operands[2])
8055 && mode == GET_MODE (operands[3])
8056 && mode == GET_MODE (operands[4])
8057 && mode == GET_MODE (operands[5])))
8060 /* All operands must be registers. */
8061 if (! (GET_CODE (operands[1]) == REG
8062 && GET_CODE (operands[2]) == REG
8063 && GET_CODE (operands[3]) == REG
8064 && GET_CODE (operands[4]) == REG
8065 && GET_CODE (operands[5]) == REG))
8068 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8069 operation, so operands[4] must be the same as operand[3]. */
8070 if (! rtx_equal_p (operands[3], operands[4]))
8073 /* multiply can not feed into subtraction. */
8074 if (rtx_equal_p (operands[5], operands[0]))
8077 /* Inout operand of sub can not conflict with any operands from multiply. */
8078 if (rtx_equal_p (operands[3], operands[0])
8079 || rtx_equal_p (operands[3], operands[1])
8080 || rtx_equal_p (operands[3], operands[2]))
8083 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8085 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8086 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8087 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8088 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8089 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8090 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8093 /* Passed. Operands are suitable for fmpysub. */
8098 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8100 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8101 || GET_CODE (op) == IOR);
8104 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8105 constants for shadd instructions. */
8107 shadd_constant_p (int val)
8109 if (val == 2 || val == 4 || val == 8)
8115 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8116 the valid constant for shadd instructions. */
8118 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8120 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8123 /* Return 1 if OP is valid as a base or index register in a
8127 borx_reg_operand (rtx op, enum machine_mode mode)
8129 if (GET_CODE (op) != REG)
8132 /* We must reject virtual registers as the only expressions that
8133 can be instantiated are REG and REG+CONST. */
8134 if (op == virtual_incoming_args_rtx
8135 || op == virtual_stack_vars_rtx
8136 || op == virtual_stack_dynamic_rtx
8137 || op == virtual_outgoing_args_rtx
8138 || op == virtual_cfa_rtx)
8141 /* While it's always safe to index off the frame pointer, it's not
8142 profitable to do so when the frame pointer is being eliminated. */
8143 if (!reload_completed
8144 && flag_omit_frame_pointer
8145 && !current_function_calls_alloca
8146 && op == frame_pointer_rtx)
8149 return register_operand (op, mode);
8152 /* Return 1 if this operand is anything other than a hard register. */
8155 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8157 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8160 /* Return 1 if INSN branches forward. Should be using insn_addresses
8161 to avoid walking through all the insns... */
8163 forward_branch_p (rtx insn)
8165 rtx label = JUMP_LABEL (insn);
8172 insn = NEXT_INSN (insn);
8175 return (insn == label);
8178 /* Return 1 if OP is an equality comparison, else return 0. */
8180 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8182 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8185 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8187 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8189 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8190 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8193 /* Return 1 if INSN is in the delay slot of a call instruction. */
8195 jump_in_call_delay (rtx insn)
8198 if (GET_CODE (insn) != JUMP_INSN)
8201 if (PREV_INSN (insn)
8202 && PREV_INSN (PREV_INSN (insn))
8203 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8205 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8207 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8208 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8215 /* Output an unconditional move and branch insn. */
8218 output_parallel_movb (rtx *operands, int length)
8220 /* These are the cases in which we win. */
8222 return "mov%I1b,tr %1,%0,%2";
8224 /* None of these cases wins, but they don't lose either. */
8225 if (dbr_sequence_length () == 0)
8227 /* Nothing in the delay slot, fake it by putting the combined
8228 insn (the copy or add) in the delay slot of a bl. */
8229 if (GET_CODE (operands[1]) == CONST_INT)
8230 return "b %2\n\tldi %1,%0";
8232 return "b %2\n\tcopy %1,%0";
8236 /* Something in the delay slot, but we've got a long branch. */
8237 if (GET_CODE (operands[1]) == CONST_INT)
8238 return "ldi %1,%0\n\tb %2";
8240 return "copy %1,%0\n\tb %2";
8244 /* Output an unconditional add and branch insn. */
8247 output_parallel_addb (rtx *operands, int length)
8249 /* To make life easy we want operand0 to be the shared input/output
8250 operand and operand1 to be the readonly operand. */
8251 if (operands[0] == operands[1])
8252 operands[1] = operands[2];
8254 /* These are the cases in which we win. */
8256 return "add%I1b,tr %1,%0,%3";
8258 /* None of these cases win, but they don't lose either. */
8259 if (dbr_sequence_length () == 0)
8261 /* Nothing in the delay slot, fake it by putting the combined
8262 insn (the copy or add) in the delay slot of a bl. */
8263 return "b %3\n\tadd%I1 %1,%0,%0";
8267 /* Something in the delay slot, but we've got a long branch. */
8268 return "add%I1 %1,%0,%0\n\tb %3";
8272 /* Return nonzero if INSN (a jump insn) immediately follows a call
8273 to a named function. This is used to avoid filling the delay slot
8274 of the jump since it can usually be eliminated by modifying RP in
8275 the delay slot of the call. */
8278 following_call (rtx insn)
8280 if (! TARGET_JUMP_IN_DELAY)
8283 /* Find the previous real insn, skipping NOTEs. */
8284 insn = PREV_INSN (insn);
8285 while (insn && GET_CODE (insn) == NOTE)
8286 insn = PREV_INSN (insn);
8288 /* Check for CALL_INSNs and millicode calls. */
8290 && ((GET_CODE (insn) == CALL_INSN
8291 && get_attr_type (insn) != TYPE_DYNCALL)
8292 || (GET_CODE (insn) == INSN
8293 && GET_CODE (PATTERN (insn)) != SEQUENCE
8294 && GET_CODE (PATTERN (insn)) != USE
8295 && GET_CODE (PATTERN (insn)) != CLOBBER
8296 && get_attr_type (insn) == TYPE_MILLI)))
8302 /* We use this hook to perform a PA specific optimization which is difficult
8303 to do in earlier passes.
8305 We want the delay slots of branches within jump tables to be filled.
8306 None of the compiler passes at the moment even has the notion that a
8307 PA jump table doesn't contain addresses, but instead contains actual
8310 Because we actually jump into the table, the addresses of each entry
8311 must stay constant in relation to the beginning of the table (which
8312 itself must stay constant relative to the instruction to jump into
8313 it). I don't believe we can guarantee earlier passes of the compiler
8314 will adhere to those rules.
8316 So, late in the compilation process we find all the jump tables, and
8317 expand them into real code -- eg each entry in the jump table vector
8318 will get an appropriate label followed by a jump to the final target.
8320 Reorg and the final jump pass can then optimize these branches and
8321 fill their delay slots. We end up with smaller, more efficient code.
8323 The jump instructions within the table are special; we must be able
8324 to identify them during assembly output (if the jumps don't get filled
8325 we need to emit a nop rather than nullifying the delay slot)). We
8326 identify jumps in switch tables by using insns with the attribute
8327 type TYPE_BTABLE_BRANCH.
8329 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8330 insns. This serves two purposes, first it prevents jump.c from
8331 noticing that the last N entries in the table jump to the instruction
8332 immediately after the table and deleting the jumps. Second, those
8333 insns mark where we should emit .begin_brtab and .end_brtab directives
8334 when using GAS (allows for better link time optimizations). */
8341 remove_useless_addtr_insns (1);
8343 if (pa_cpu < PROCESSOR_8000)
8344 pa_combine_instructions ();
8347 /* This is fairly cheap, so always run it if optimizing. */
8348 if (optimize > 0 && !TARGET_BIG_SWITCH)
8350 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8351 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8353 rtx pattern, tmp, location, label;
8354 unsigned int length, i;
8356 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8357 if (GET_CODE (insn) != JUMP_INSN
8358 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8359 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8362 /* Emit marker for the beginning of the branch table. */
8363 emit_insn_before (gen_begin_brtab (), insn);
8365 pattern = PATTERN (insn);
8366 location = PREV_INSN (insn);
8367 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8369 for (i = 0; i < length; i++)
8371 /* Emit a label before each jump to keep jump.c from
8372 removing this code. */
8373 tmp = gen_label_rtx ();
8374 LABEL_NUSES (tmp) = 1;
8375 emit_label_after (tmp, location);
8376 location = NEXT_INSN (location);
8378 if (GET_CODE (pattern) == ADDR_VEC)
8379 label = XEXP (XVECEXP (pattern, 0, i), 0);
8381 label = XEXP (XVECEXP (pattern, 1, i), 0);
8383 tmp = gen_short_jump (label);
8385 /* Emit the jump itself. */
8386 tmp = emit_jump_insn_after (tmp, location);
8387 JUMP_LABEL (tmp) = label;
8388 LABEL_NUSES (label)++;
8389 location = NEXT_INSN (location);
8391 /* Emit a BARRIER after the jump. */
8392 emit_barrier_after (location);
8393 location = NEXT_INSN (location);
8396 /* Emit marker for the end of the branch table. */
8397 emit_insn_before (gen_end_brtab (), location);
8398 location = NEXT_INSN (location);
8399 emit_barrier_after (location);
8401 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8407 /* Still need brtab marker insns. FIXME: the presence of these
8408 markers disables output of the branch table to readonly memory,
8409 and any alignment directives that might be needed. Possibly,
8410 the begin_brtab insn should be output before the label for the
8411 table. This doesn't matter at the moment since the tables are
8412 always output in the text section. */
8413 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8415 /* Find an ADDR_VEC insn. */
8416 if (GET_CODE (insn) != JUMP_INSN
8417 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8418 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8421 /* Now generate markers for the beginning and end of the
8423 emit_insn_before (gen_begin_brtab (), insn);
8424 emit_insn_after (gen_end_brtab (), insn);
8429 /* The PA has a number of odd instructions which can perform multiple
8430 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8431 it may be profitable to combine two instructions into one instruction
8432 with two outputs. It's not profitable PA2.0 machines because the
8433 two outputs would take two slots in the reorder buffers.
8435 This routine finds instructions which can be combined and combines
8436 them. We only support some of the potential combinations, and we
8437 only try common ways to find suitable instructions.
8439 * addb can add two registers or a register and a small integer
8440 and jump to a nearby (+-8k) location. Normally the jump to the
8441 nearby location is conditional on the result of the add, but by
8442 using the "true" condition we can make the jump unconditional.
8443 Thus addb can perform two independent operations in one insn.
8445 * movb is similar to addb in that it can perform a reg->reg
8446 or small immediate->reg copy and jump to a nearby (+-8k location).
8448 * fmpyadd and fmpysub can perform a FP multiply and either an
8449 FP add or FP sub if the operands of the multiply and add/sub are
8450 independent (there are other minor restrictions). Note both
8451 the fmpy and fadd/fsub can in theory move to better spots according
8452 to data dependencies, but for now we require the fmpy stay at a
8455 * Many of the memory operations can perform pre & post updates
8456 of index registers. GCC's pre/post increment/decrement addressing
8457 is far too simple to take advantage of all the possibilities. This
8458 pass may not be suitable since those insns may not be independent.
8460 * comclr can compare two ints or an int and a register, nullify
8461 the following instruction and zero some other register. This
8462 is more difficult to use as it's harder to find an insn which
8463 will generate a comclr than finding something like an unconditional
8464 branch. (conditional moves & long branches create comclr insns).
8466 * Most arithmetic operations can conditionally skip the next
8467 instruction. They can be viewed as "perform this operation
8468 and conditionally jump to this nearby location" (where nearby
8469 is an insns away). These are difficult to use due to the
8470 branch length restrictions. */
8473 pa_combine_instructions (void)
8477 /* This can get expensive since the basic algorithm is on the
8478 order of O(n^2) (or worse). Only do it for -O2 or higher
8479 levels of optimization. */
8483 /* Walk down the list of insns looking for "anchor" insns which
8484 may be combined with "floating" insns. As the name implies,
8485 "anchor" instructions don't move, while "floating" insns may
8487 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8488 new = make_insn_raw (new);
8490 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8492 enum attr_pa_combine_type anchor_attr;
8493 enum attr_pa_combine_type floater_attr;
8495 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8496 Also ignore any special USE insns. */
8497 if ((GET_CODE (anchor) != INSN
8498 && GET_CODE (anchor) != JUMP_INSN
8499 && GET_CODE (anchor) != CALL_INSN)
8500 || GET_CODE (PATTERN (anchor)) == USE
8501 || GET_CODE (PATTERN (anchor)) == CLOBBER
8502 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8503 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8506 anchor_attr = get_attr_pa_combine_type (anchor);
8507 /* See if anchor is an insn suitable for combination. */
8508 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8509 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8510 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8511 && ! forward_branch_p (anchor)))
8515 for (floater = PREV_INSN (anchor);
8517 floater = PREV_INSN (floater))
8519 if (GET_CODE (floater) == NOTE
8520 || (GET_CODE (floater) == INSN
8521 && (GET_CODE (PATTERN (floater)) == USE
8522 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8525 /* Anything except a regular INSN will stop our search. */
8526 if (GET_CODE (floater) != INSN
8527 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8528 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8534 /* See if FLOATER is suitable for combination with the
8536 floater_attr = get_attr_pa_combine_type (floater);
8537 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8538 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8539 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8540 && floater_attr == PA_COMBINE_TYPE_FMPY))
8542 /* If ANCHOR and FLOATER can be combined, then we're
8543 done with this pass. */
8544 if (pa_can_combine_p (new, anchor, floater, 0,
8545 SET_DEST (PATTERN (floater)),
8546 XEXP (SET_SRC (PATTERN (floater)), 0),
8547 XEXP (SET_SRC (PATTERN (floater)), 1)))
8551 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8552 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8554 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8556 if (pa_can_combine_p (new, anchor, floater, 0,
8557 SET_DEST (PATTERN (floater)),
8558 XEXP (SET_SRC (PATTERN (floater)), 0),
8559 XEXP (SET_SRC (PATTERN (floater)), 1)))
8564 if (pa_can_combine_p (new, anchor, floater, 0,
8565 SET_DEST (PATTERN (floater)),
8566 SET_SRC (PATTERN (floater)),
8567 SET_SRC (PATTERN (floater))))
8573 /* If we didn't find anything on the backwards scan try forwards. */
8575 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8576 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8578 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8580 if (GET_CODE (floater) == NOTE
8581 || (GET_CODE (floater) == INSN
8582 && (GET_CODE (PATTERN (floater)) == USE
8583 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8587 /* Anything except a regular INSN will stop our search. */
8588 if (GET_CODE (floater) != INSN
8589 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8590 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8596 /* See if FLOATER is suitable for combination with the
8598 floater_attr = get_attr_pa_combine_type (floater);
8599 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8600 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8601 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8602 && floater_attr == PA_COMBINE_TYPE_FMPY))
8604 /* If ANCHOR and FLOATER can be combined, then we're
8605 done with this pass. */
8606 if (pa_can_combine_p (new, anchor, floater, 1,
8607 SET_DEST (PATTERN (floater)),
8608 XEXP (SET_SRC (PATTERN (floater)),
8610 XEXP (SET_SRC (PATTERN (floater)),
8617 /* FLOATER will be nonzero if we found a suitable floating
8618 insn for combination with ANCHOR. */
8620 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8621 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8623 /* Emit the new instruction and delete the old anchor. */
8624 emit_insn_before (gen_rtx_PARALLEL
8626 gen_rtvec (2, PATTERN (anchor),
8627 PATTERN (floater))),
8630 PUT_CODE (anchor, NOTE);
8631 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8632 NOTE_SOURCE_FILE (anchor) = 0;
8634 /* Emit a special USE insn for FLOATER, then delete
8635 the floating insn. */
8636 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8637 delete_insn (floater);
8642 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8645 /* Emit the new_jump instruction and delete the old anchor. */
8647 = emit_jump_insn_before (gen_rtx_PARALLEL
8649 gen_rtvec (2, PATTERN (anchor),
8650 PATTERN (floater))),
8653 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8654 PUT_CODE (anchor, NOTE);
8655 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8656 NOTE_SOURCE_FILE (anchor) = 0;
8658 /* Emit a special USE insn for FLOATER, then delete
8659 the floating insn. */
8660 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8661 delete_insn (floater);
8669 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8672 int insn_code_number;
8675 /* Create a PARALLEL with the patterns of ANCHOR and
8676 FLOATER, try to recognize it, then test constraints
8677 for the resulting pattern.
8679 If the pattern doesn't match or the constraints
8680 aren't met keep searching for a suitable floater
8682 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8683 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8684 INSN_CODE (new) = -1;
8685 insn_code_number = recog_memoized (new);
8686 if (insn_code_number < 0
8687 || (extract_insn (new), ! constrain_operands (1)))
8701 /* There's up to three operands to consider. One
8702 output and two inputs.
8704 The output must not be used between FLOATER & ANCHOR
8705 exclusive. The inputs must not be set between
8706 FLOATER and ANCHOR exclusive. */
8708 if (reg_used_between_p (dest, start, end))
8711 if (reg_set_between_p (src1, start, end))
8714 if (reg_set_between_p (src2, start, end))
8717 /* If we get here, then everything is good. */
8721 /* Return nonzero if references for INSN are delayed.
8723 Millicode insns are actually function calls with some special
8724 constraints on arguments and register usage.
8726 Millicode calls always expect their arguments in the integer argument
8727 registers, and always return their result in %r29 (ret1). They
8728 are expected to clobber their arguments, %r1, %r29, and the return
8729 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8731 This function tells reorg that the references to arguments and
8732 millicode calls do not appear to happen until after the millicode call.
8733 This allows reorg to put insns which set the argument registers into the
8734 delay slot of the millicode call -- thus they act more like traditional
8737 Note we can not consider side effects of the insn to be delayed because
8738 the branch and link insn will clobber the return pointer. If we happened
8739 to use the return pointer in the delay slot of the call, then we lose.
8741 get_attr_type will try to recognize the given insn, so make sure to
8742 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8745 insn_refs_are_delayed (rtx insn)
8747 return ((GET_CODE (insn) == INSN
8748 && GET_CODE (PATTERN (insn)) != SEQUENCE
8749 && GET_CODE (PATTERN (insn)) != USE
8750 && GET_CODE (PATTERN (insn)) != CLOBBER
8751 && get_attr_type (insn) == TYPE_MILLI));
8754 /* On the HP-PA the value is found in register(s) 28(-29), unless
8755 the mode is SF or DF. Then the value is returned in fr4 (32).
8757 This must perform the same promotions as PROMOTE_MODE, else
8758 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8760 Small structures must be returned in a PARALLEL on PA64 in order
8761 to match the HP Compiler ABI. */
8764 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8766 enum machine_mode valmode;
8768 /* Aggregates with a size less than or equal to 128 bits are returned
8769 in GR 28(-29). They are left justified. The pad bits are undefined.
8770 Larger aggregates are returned in memory. */
8771 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8775 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8777 for (i = 0; i < ub; i++)
8779 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8780 gen_rtx_REG (DImode, 28 + i),
8785 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8788 if ((INTEGRAL_TYPE_P (valtype)
8789 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8790 || POINTER_TYPE_P (valtype))
8791 valmode = word_mode;
8793 valmode = TYPE_MODE (valtype);
8795 if (TREE_CODE (valtype) == REAL_TYPE
8796 && TYPE_MODE (valtype) != TFmode
8797 && !TARGET_SOFT_FLOAT)
8798 return gen_rtx_REG (valmode, 32);
8800 return gen_rtx_REG (valmode, 28);
8803 /* Return the location of a parameter that is passed in a register or NULL
8804 if the parameter has any component that is passed in memory.
8806 This is new code and will be pushed to into the net sources after
8809 ??? We might want to restructure this so that it looks more like other
8812 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8813 int named ATTRIBUTE_UNUSED)
8815 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8822 if (mode == VOIDmode)
8825 arg_size = FUNCTION_ARG_SIZE (mode, type);
8827 /* If this arg would be passed partially or totally on the stack, then
8828 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8829 handle arguments which are split between regs and stack slots if
8830 the ABI mandates split arguments. */
8833 /* The 32-bit ABI does not split arguments. */
8834 if (cum->words + arg_size > max_arg_words)
8840 alignment = cum->words & 1;
8841 if (cum->words + alignment >= max_arg_words)
8845 /* The 32bit ABIs and the 64bit ABIs are rather different,
8846 particularly in their handling of FP registers. We might
8847 be able to cleverly share code between them, but I'm not
8848 going to bother in the hope that splitting them up results
8849 in code that is more easily understood. */
8853 /* Advance the base registers to their current locations.
8855 Remember, gprs grow towards smaller register numbers while
8856 fprs grow to higher register numbers. Also remember that
8857 although FP regs are 32-bit addressable, we pretend that
8858 the registers are 64-bits wide. */
8859 gpr_reg_base = 26 - cum->words;
8860 fpr_reg_base = 32 + cum->words;
8862 /* Arguments wider than one word and small aggregates need special
8866 || (type && AGGREGATE_TYPE_P (type)))
8868 /* Double-extended precision (80-bit), quad-precision (128-bit)
8869 and aggregates including complex numbers are aligned on
8870 128-bit boundaries. The first eight 64-bit argument slots
8871 are associated one-to-one, with general registers r26
8872 through r19, and also with floating-point registers fr4
8873 through fr11. Arguments larger than one word are always
8874 passed in general registers.
8876 Using a PARALLEL with a word mode register results in left
8877 justified data on a big-endian target. */
8880 int i, offset = 0, ub = arg_size;
8882 /* Align the base register. */
8883 gpr_reg_base -= alignment;
8885 ub = MIN (ub, max_arg_words - cum->words - alignment);
8886 for (i = 0; i < ub; i++)
8888 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8889 gen_rtx_REG (DImode, gpr_reg_base),
8895 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8900 /* If the argument is larger than a word, then we know precisely
8901 which registers we must use. */
8915 /* Structures 5 to 8 bytes in size are passed in the general
8916 registers in the same manner as other non floating-point
8917 objects. The data is right-justified and zero-extended
8920 This is magic. Normally, using a PARALLEL results in left
8921 justified data on a big-endian target. However, using a
8922 single double-word register provides the required right
8923 justification for 5 to 8 byte structures. This has nothing
8924 to do with the direction of padding specified for the argument.
8925 It has to do with how the data is widened and shifted into
8926 and from the register.
8928 Aside from adding load_multiple and store_multiple patterns,
8929 this is the only way that I have found to obtain right
8930 justification of BLKmode data when it has a size greater
8931 than one word. Splitting the operation into two SImode loads
8932 or returning a DImode REG results in left justified data. */
8933 if (mode == BLKmode)
8935 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8936 gen_rtx_REG (DImode, gpr_reg_base),
8938 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8943 /* We have a single word (32 bits). A simple computation
8944 will get us the register #s we need. */
8945 gpr_reg_base = 26 - cum->words;
8946 fpr_reg_base = 32 + 2 * cum->words;
8950 /* Determine if the argument needs to be passed in both general and
8951 floating point registers. */
8952 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8953 /* If we are doing soft-float with portable runtime, then there
8954 is no need to worry about FP regs. */
8955 && !TARGET_SOFT_FLOAT
8956 /* The parameter must be some kind of float, else we can just
8957 pass it in integer registers. */
8958 && FLOAT_MODE_P (mode)
8959 /* The target function must not have a prototype. */
8960 && cum->nargs_prototype <= 0
8961 /* libcalls do not need to pass items in both FP and general
8963 && type != NULL_TREE
8964 /* All this hair applies to "outgoing" args only. This includes
8965 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8967 /* Also pass outgoing floating arguments in both registers in indirect
8968 calls with the 32 bit ABI and the HP assembler since there is no
8969 way to the specify argument locations in static functions. */
8974 && FLOAT_MODE_P (mode)))
8980 gen_rtx_EXPR_LIST (VOIDmode,
8981 gen_rtx_REG (mode, fpr_reg_base),
8983 gen_rtx_EXPR_LIST (VOIDmode,
8984 gen_rtx_REG (mode, gpr_reg_base),
8989 /* See if we should pass this parameter in a general register. */
8990 if (TARGET_SOFT_FLOAT
8991 /* Indirect calls in the normal 32bit ABI require all arguments
8992 to be passed in general registers. */
8993 || (!TARGET_PORTABLE_RUNTIME
8997 /* If the parameter is not a floating point parameter, then
8998 it belongs in GPRs. */
8999 || !FLOAT_MODE_P (mode))
9000 retval = gen_rtx_REG (mode, gpr_reg_base);
9002 retval = gen_rtx_REG (mode, fpr_reg_base);
9008 /* If this arg would be passed totally in registers or totally on the stack,
9009 then this routine should return zero. It is currently called only for
9010 the 64-bit target. */
9012 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9013 tree type, int named ATTRIBUTE_UNUSED)
9015 unsigned int max_arg_words = 8;
9016 unsigned int offset = 0;
9018 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9021 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9022 /* Arg fits fully into registers. */
9024 else if (cum->words + offset >= max_arg_words)
9025 /* Arg fully on the stack. */
9029 return max_arg_words - cum->words - offset;
9033 /* Return 1 if this is a comparison operator. This allows the use of
9034 MATCH_OPERATOR to recognize all the branch insns. */
9037 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9039 return ((mode == VOIDmode || GET_MODE (op) == mode)
9040 && (GET_CODE (op) == EQ
9041 || GET_CODE (op) == NE
9042 || GET_CODE (op) == GT
9043 || GET_CODE (op) == GTU
9044 || GET_CODE (op) == GE
9045 || GET_CODE (op) == LT
9046 || GET_CODE (op) == LE
9047 || GET_CODE (op) == LEU));
9050 /* On hpux10, the linker will give an error if we have a reference
9051 in the read-only data section to a symbol defined in a shared
9052 library. Therefore, expressions that might require a reloc can
9053 not be placed in the read-only data section. */
9056 pa_select_section (tree exp, int reloc,
9057 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9059 if (TREE_CODE (exp) == VAR_DECL
9060 && TREE_READONLY (exp)
9061 && !TREE_THIS_VOLATILE (exp)
9062 && DECL_INITIAL (exp)
9063 && (DECL_INITIAL (exp) == error_mark_node
9064 || TREE_CONSTANT (DECL_INITIAL (exp)))
9066 readonly_data_section ();
9067 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
9069 readonly_data_section ();
9075 pa_globalize_label (FILE *stream, const char *name)
9077 /* We only handle DATA objects here, functions are globalized in
9078 ASM_DECLARE_FUNCTION_NAME. */
9079 if (! FUNCTION_NAME_P (name))
9081 fputs ("\t.EXPORT ", stream);
9082 assemble_name (stream, name);
9083 fputs (",DATA\n", stream);
9087 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9090 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9091 int incoming ATTRIBUTE_UNUSED)
9093 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9096 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9099 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9101 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9102 PA64 ABI says that objects larger than 128 bits are returned in memory.
9103 Note, int_size_in_bytes can return -1 if the size of the object is
9104 variable or larger than the maximum value that can be expressed as
9105 a HOST_WIDE_INT. It can also return zero for an empty type. The
9106 simplest way to handle variable and empty types is to pass them in
9107 memory. This avoids problems in defining the boundaries of argument
9108 slots, allocating registers, etc. */
9109 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9110 || int_size_in_bytes (type) <= 0);