1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
52 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
54 /* Return nonzero if there is a bypass for the output of
55 OUT_INSN and the fp store IN_INSN. */
57 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
59 enum machine_mode store_mode;
60 enum machine_mode other_mode;
63 if (recog_memoized (in_insn) < 0
64 || get_attr_type (in_insn) != TYPE_FPSTORE
65 || recog_memoized (out_insn) < 0)
68 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
70 set = single_set (out_insn);
74 other_mode = GET_MODE (SET_SRC (set));
76 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
80 #ifndef DO_FRAME_NOTES
81 #ifdef INCOMING_RETURN_ADDR_RTX
82 #define DO_FRAME_NOTES 1
84 #define DO_FRAME_NOTES 0
88 static void copy_reg_pointer (rtx, rtx);
89 static void fix_range (const char *);
90 static int hppa_address_cost (rtx);
91 static bool hppa_rtx_costs (rtx, int, int, int *);
92 static inline rtx force_mode (enum machine_mode, rtx);
93 static void pa_reorg (void);
94 static void pa_combine_instructions (void);
95 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
96 static int forward_branch_p (rtx);
97 static int shadd_constant_p (int);
98 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
99 static int compute_movmem_length (rtx);
100 static int compute_clrmem_length (rtx);
101 static bool pa_assemble_integer (rtx, unsigned int, int);
102 static void remove_useless_addtr_insns (int);
103 static void store_reg (int, HOST_WIDE_INT, int);
104 static void store_reg_modify (int, int, HOST_WIDE_INT);
105 static void load_reg (int, HOST_WIDE_INT, int);
106 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
107 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
108 static void update_total_code_bytes (int);
109 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
110 static int pa_adjust_cost (rtx, rtx, rtx, int);
111 static int pa_adjust_priority (rtx, int);
112 static int pa_issue_rate (void);
113 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
115 static void pa_encode_section_info (tree, rtx, int);
116 static const char *pa_strip_name_encoding (const char *);
117 static bool pa_function_ok_for_sibcall (tree, tree);
118 static void pa_globalize_label (FILE *, const char *)
120 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
121 HOST_WIDE_INT, tree);
122 #if !defined(USE_COLLECT2)
123 static void pa_asm_out_constructor (rtx, int);
124 static void pa_asm_out_destructor (rtx, int);
126 static void pa_init_builtins (void);
127 static rtx hppa_builtin_saveregs (void);
128 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
129 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
130 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
131 static struct deferred_plabel *get_plabel (const char *)
133 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
134 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
135 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
136 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
137 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
139 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
140 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
141 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
142 static void output_deferred_plabels (void);
143 #ifdef HPUX_LONG_DOUBLE_LIBRARY
144 static void pa_hpux_init_libfuncs (void);
146 static rtx pa_struct_value_rtx (tree, int);
147 static bool pa_pass_by_reference (CUMULATIVE_ARGS *ca, enum machine_mode,
151 /* Save the operands last given to a compare for use when we
152 generate a scc or bcc insn. */
153 rtx hppa_compare_op0, hppa_compare_op1;
154 enum cmp_type hppa_branch_type;
156 /* Which architecture we are generating code for. */
157 enum architecture_type pa_arch;
159 /* String to hold which architecture we are generating code for. */
160 const char *pa_arch_string;
162 /* String used with the -mfixed-range= option. */
163 const char *pa_fixed_range_string;
165 /* Which cpu we are scheduling for. */
166 enum processor_type pa_cpu;
168 /* String to hold which cpu we are scheduling for. */
169 const char *pa_cpu_string;
171 /* Counts for the number of callee-saved general and floating point
172 registers which were saved by the current function's prologue. */
173 static int gr_saved, fr_saved;
175 static rtx find_addr_reg (rtx);
177 /* Keep track of the number of bytes we have output in the CODE subspace
178 during this compilation so we'll know when to emit inline long-calls. */
179 unsigned long total_code_bytes;
181 /* The last address of the previous function plus the number of bytes in
182 associated thunks that have been output. This is used to determine if
183 a thunk can use an IA-relative branch to reach its target function. */
184 static int last_address;
186 /* Variables to handle plabels that we discover are necessary at assembly
187 output time. They are output after the current function. */
188 struct deferred_plabel GTY(())
193 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
195 static size_t n_deferred_plabels = 0;
198 /* Initialize the GCC target structure. */
200 #undef TARGET_ASM_ALIGNED_HI_OP
201 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
202 #undef TARGET_ASM_ALIGNED_SI_OP
203 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
204 #undef TARGET_ASM_ALIGNED_DI_OP
205 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
206 #undef TARGET_ASM_UNALIGNED_HI_OP
207 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
208 #undef TARGET_ASM_UNALIGNED_SI_OP
209 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
210 #undef TARGET_ASM_UNALIGNED_DI_OP
211 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
212 #undef TARGET_ASM_INTEGER
213 #define TARGET_ASM_INTEGER pa_assemble_integer
215 #undef TARGET_ASM_FUNCTION_PROLOGUE
216 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
217 #undef TARGET_ASM_FUNCTION_EPILOGUE
218 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
220 #undef TARGET_SCHED_ADJUST_COST
221 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
222 #undef TARGET_SCHED_ADJUST_PRIORITY
223 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
224 #undef TARGET_SCHED_ISSUE_RATE
225 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
227 #undef TARGET_ENCODE_SECTION_INFO
228 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
229 #undef TARGET_STRIP_NAME_ENCODING
230 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
232 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
233 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
235 #undef TARGET_ASM_OUTPUT_MI_THUNK
236 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
237 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
238 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
240 #undef TARGET_ASM_FILE_END
241 #define TARGET_ASM_FILE_END output_deferred_plabels
243 #if !defined(USE_COLLECT2)
244 #undef TARGET_ASM_CONSTRUCTOR
245 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
246 #undef TARGET_ASM_DESTRUCTOR
247 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
250 #undef TARGET_INIT_BUILTINS
251 #define TARGET_INIT_BUILTINS pa_init_builtins
253 #undef TARGET_RTX_COSTS
254 #define TARGET_RTX_COSTS hppa_rtx_costs
255 #undef TARGET_ADDRESS_COST
256 #define TARGET_ADDRESS_COST hppa_address_cost
258 #undef TARGET_MACHINE_DEPENDENT_REORG
259 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
261 #ifdef HPUX_LONG_DOUBLE_LIBRARY
262 #undef TARGET_INIT_LIBFUNCS
263 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
266 #undef TARGET_PROMOTE_FUNCTION_RETURN
267 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
268 #undef TARGET_PROMOTE_PROTOTYPES
269 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
271 #undef TARGET_STRUCT_VALUE_RTX
272 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
273 #undef TARGET_RETURN_IN_MEMORY
274 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
275 #undef TARGET_MUST_PASS_IN_STACK
276 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
277 #undef TARGET_PASS_BY_REFERENCE
278 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
280 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
281 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
282 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
283 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
285 struct gcc_target targetm = TARGET_INITIALIZER;
287 /* Parse the -mfixed-range= option string. */
290 fix_range (const char *const_str)
293 char *str, *dash, *comma;
295 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
296 REG2 are either register names or register numbers. The effect
297 of this option is to mark the registers in the range from REG1 to
298 REG2 as ``fixed'' so they won't be used by the compiler. This is
299 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
301 i = strlen (const_str);
302 str = (char *) alloca (i + 1);
303 memcpy (str, const_str, i + 1);
307 dash = strchr (str, '-');
310 warning ("value of -mfixed-range must have form REG1-REG2");
315 comma = strchr (dash + 1, ',');
319 first = decode_reg_name (str);
322 warning ("unknown register name: %s", str);
326 last = decode_reg_name (dash + 1);
329 warning ("unknown register name: %s", dash + 1);
337 warning ("%s-%s is an empty range", str, dash + 1);
341 for (i = first; i <= last; ++i)
342 fixed_regs[i] = call_used_regs[i] = 1;
351 /* Check if all floating point registers have been fixed. */
352 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
357 target_flags |= MASK_DISABLE_FPREGS;
361 override_options (void)
363 if (pa_cpu_string == NULL)
364 pa_cpu_string = TARGET_SCHED_DEFAULT;
366 if (! strcmp (pa_cpu_string, "8000"))
368 pa_cpu_string = "8000";
369 pa_cpu = PROCESSOR_8000;
371 else if (! strcmp (pa_cpu_string, "7100"))
373 pa_cpu_string = "7100";
374 pa_cpu = PROCESSOR_7100;
376 else if (! strcmp (pa_cpu_string, "700"))
378 pa_cpu_string = "700";
379 pa_cpu = PROCESSOR_700;
381 else if (! strcmp (pa_cpu_string, "7100LC"))
383 pa_cpu_string = "7100LC";
384 pa_cpu = PROCESSOR_7100LC;
386 else if (! strcmp (pa_cpu_string, "7200"))
388 pa_cpu_string = "7200";
389 pa_cpu = PROCESSOR_7200;
391 else if (! strcmp (pa_cpu_string, "7300"))
393 pa_cpu_string = "7300";
394 pa_cpu = PROCESSOR_7300;
398 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
401 /* Set the instruction architecture. */
402 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
404 pa_arch_string = "1.0";
405 pa_arch = ARCHITECTURE_10;
406 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
408 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
410 pa_arch_string = "1.1";
411 pa_arch = ARCHITECTURE_11;
412 target_flags &= ~MASK_PA_20;
413 target_flags |= MASK_PA_11;
415 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
417 pa_arch_string = "2.0";
418 pa_arch = ARCHITECTURE_20;
419 target_flags |= MASK_PA_11 | MASK_PA_20;
421 else if (pa_arch_string)
423 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
426 if (pa_fixed_range_string)
427 fix_range (pa_fixed_range_string);
429 /* Unconditional branches in the delay slot are not compatible with dwarf2
430 call frame information. There is no benefit in using this optimization
431 on PA8000 and later processors. */
432 if (pa_cpu >= PROCESSOR_8000
433 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
434 || flag_unwind_tables)
435 target_flags &= ~MASK_JUMP_IN_DELAY;
437 if (flag_pic && TARGET_PORTABLE_RUNTIME)
439 warning ("PIC code generation is not supported in the portable runtime model\n");
442 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
444 warning ("PIC code generation is not compatible with fast indirect calls\n");
447 if (! TARGET_GAS && write_symbols != NO_DEBUG)
449 warning ("-g is only supported when using GAS on this processor,");
450 warning ("-g option disabled");
451 write_symbols = NO_DEBUG;
454 /* We only support the "big PIC" model now. And we always generate PIC
455 code when in 64bit mode. */
456 if (flag_pic == 1 || TARGET_64BIT)
459 /* We can't guarantee that .dword is available for 32-bit targets. */
460 if (UNITS_PER_WORD == 4)
461 targetm.asm_out.aligned_op.di = NULL;
463 /* The unaligned ops are only available when using GAS. */
466 targetm.asm_out.unaligned_op.hi = NULL;
467 targetm.asm_out.unaligned_op.si = NULL;
468 targetm.asm_out.unaligned_op.di = NULL;
473 pa_init_builtins (void)
475 #ifdef DONT_HAVE_FPUTC_UNLOCKED
476 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
477 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
481 /* If FROM is a probable pointer register, mark TO as a probable
482 pointer register with the same pointer alignment as FROM. */
485 copy_reg_pointer (rtx to, rtx from)
487 if (REG_POINTER (from))
488 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
491 /* Return nonzero only if OP is a register of mode MODE,
494 reg_or_0_operand (rtx op, enum machine_mode mode)
496 return (op == CONST0_RTX (mode) || register_operand (op, mode));
499 /* Return nonzero if OP is suitable for use in a call to a named
502 For 2.5 try to eliminate either call_operand_address or
503 function_label_operand, they perform very similar functions. */
505 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
507 return (GET_MODE (op) == word_mode
508 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
511 /* Return 1 if X contains a symbolic expression. We know these
512 expressions will have one of a few well defined forms, so
513 we need only check those forms. */
515 symbolic_expression_p (rtx x)
518 /* Strip off any HIGH. */
519 if (GET_CODE (x) == HIGH)
522 return (symbolic_operand (x, VOIDmode));
526 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
528 switch (GET_CODE (op))
535 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
536 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
537 && GET_CODE (XEXP (op, 1)) == CONST_INT);
543 /* Return truth value of statement that OP is a symbolic memory
544 operand of mode MODE. */
547 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
549 if (GET_CODE (op) == SUBREG)
550 op = SUBREG_REG (op);
551 if (GET_CODE (op) != MEM)
554 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
555 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
558 /* Return 1 if the operand is either a register, zero, or a memory operand
559 that is not symbolic. */
562 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
564 if (register_operand (op, mode))
567 if (op == CONST0_RTX (mode))
570 if (GET_CODE (op) == SUBREG)
571 op = SUBREG_REG (op);
573 if (GET_CODE (op) != MEM)
576 /* Until problems with management of the REG_POINTER flag are resolved,
577 we need to delay creating move insns with unscaled indexed addresses
578 until CSE is not expected. */
579 if (!TARGET_NO_SPACE_REGS
581 && GET_CODE (XEXP (op, 0)) == PLUS
582 && REG_P (XEXP (XEXP (op, 0), 0))
583 && REG_P (XEXP (XEXP (op, 0), 1)))
586 return (!symbolic_memory_operand (op, mode)
587 && memory_address_p (mode, XEXP (op, 0)));
590 /* Return 1 if the operand is a register operand or a non-symbolic memory
591 operand after reload. This predicate is used for branch patterns that
592 internally handle register reloading. We need to accept non-symbolic
593 memory operands after reload to ensure that the pattern is still valid
594 if reload didn't find a hard register for the operand. */
597 reg_before_reload_operand (rtx op, enum machine_mode mode)
599 /* Don't accept a SUBREG since it will need a reload. */
600 if (GET_CODE (op) == SUBREG)
603 if (register_operand (op, mode))
607 && memory_operand (op, mode)
608 && !symbolic_memory_operand (op, mode))
614 /* Accept any constant that can be moved in one instruction into a
617 cint_ok_for_move (HOST_WIDE_INT intval)
619 /* OK if ldo, ldil, or zdepi, can be used. */
620 return (CONST_OK_FOR_LETTER_P (intval, 'J')
621 || CONST_OK_FOR_LETTER_P (intval, 'N')
622 || CONST_OK_FOR_LETTER_P (intval, 'K'));
625 /* Return 1 iff OP is an indexed memory operand. */
627 indexed_memory_operand (rtx op, enum machine_mode mode)
629 if (GET_MODE (op) != mode)
632 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
633 if (reload_completed && GET_CODE (op) == SUBREG)
634 op = SUBREG_REG (op);
636 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
641 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
644 /* Accept anything that can be used as a destination operand for a
645 move instruction. We don't accept indexed memory operands since
646 they are supported only for floating point stores. */
648 move_dest_operand (rtx op, enum machine_mode mode)
650 if (register_operand (op, mode))
653 if (GET_MODE (op) != mode)
656 if (GET_CODE (op) == SUBREG)
657 op = SUBREG_REG (op);
659 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
664 return (memory_address_p (mode, op)
665 && !IS_INDEX_ADDR_P (op)
666 && !IS_LO_SUM_DLT_ADDR_P (op));
669 /* Accept anything that can be used as a source operand for a move
672 move_src_operand (rtx op, enum machine_mode mode)
674 if (register_operand (op, mode))
677 if (GET_CODE (op) == CONST_INT)
678 return cint_ok_for_move (INTVAL (op));
680 if (GET_MODE (op) != mode)
683 if (GET_CODE (op) == SUBREG)
684 op = SUBREG_REG (op);
686 if (GET_CODE (op) != MEM)
689 /* Until problems with management of the REG_POINTER flag are resolved,
690 we need to delay creating move insns with unscaled indexed addresses
691 until CSE is not expected. */
692 if (!TARGET_NO_SPACE_REGS
694 && GET_CODE (XEXP (op, 0)) == PLUS
695 && REG_P (XEXP (XEXP (op, 0), 0))
696 && REG_P (XEXP (XEXP (op, 0), 1)))
699 return memory_address_p (mode, XEXP (op, 0));
702 /* Accept anything that can be used as the source operand for a prefetch
705 prefetch_operand (rtx op, enum machine_mode mode)
707 if (GET_CODE (op) != MEM)
710 /* Until problems with management of the REG_POINTER flag are resolved,
711 we need to delay creating prefetch insns with unscaled indexed addresses
712 until CSE is not expected. */
713 if (!TARGET_NO_SPACE_REGS
715 && GET_CODE (XEXP (op, 0)) == PLUS
716 && REG_P (XEXP (XEXP (op, 0), 0))
717 && REG_P (XEXP (XEXP (op, 0), 1)))
720 return memory_address_p (mode, XEXP (op, 0));
723 /* Accept REG and any CONST_INT that can be moved in one instruction into a
726 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
728 if (register_operand (op, mode))
731 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
735 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
740 switch (GET_CODE (op))
746 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
747 && GET_CODE (XEXP (op, 1)) == CONST_INT);
754 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
756 return reg_renumber && FP_REG_P (op);
761 /* Return truth value of whether OP can be used as an operand in a
762 three operand arithmetic insn that accepts registers of mode MODE
763 or 14-bit signed integers. */
765 arith_operand (rtx op, enum machine_mode mode)
767 return (register_operand (op, mode)
768 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
771 /* Return truth value of whether OP can be used as an operand in a
772 three operand arithmetic insn that accepts registers of mode MODE
773 or 11-bit signed integers. */
775 arith11_operand (rtx op, enum machine_mode mode)
777 return (register_operand (op, mode)
778 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
781 /* Return truth value of whether OP can be used as an operand in a
784 adddi3_operand (rtx op, enum machine_mode mode)
786 return (register_operand (op, mode)
787 || (GET_CODE (op) == CONST_INT
788 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
791 /* A constant integer suitable for use in a PRE_MODIFY memory
794 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
796 return (GET_CODE (op) == CONST_INT
797 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
800 /* A constant integer suitable for use in a POST_MODIFY memory
803 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
805 return (GET_CODE (op) == CONST_INT
806 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
810 arith_double_operand (rtx op, enum machine_mode mode)
812 return (register_operand (op, mode)
813 || (GET_CODE (op) == CONST_DOUBLE
814 && GET_MODE (op) == mode
815 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
816 && ((CONST_DOUBLE_HIGH (op) >= 0)
817 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
820 /* Return truth value of whether OP is an integer which fits the
821 range constraining immediate operands in three-address insns, or
822 is an integer register. */
825 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
827 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
828 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
831 /* Return nonzero if OP is an integer register, else return zero. */
833 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
835 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
838 /* Return truth value of whether OP is an integer which fits the
839 range constraining immediate operands in three-address insns. */
842 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
844 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
848 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
850 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
854 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
856 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
860 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
862 #if HOST_BITS_PER_WIDE_INT > 32
863 /* All allowed constants will fit a CONST_INT. */
864 return (GET_CODE (op) == CONST_INT
865 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
867 return (GET_CODE (op) == CONST_INT
868 || (GET_CODE (op) == CONST_DOUBLE
869 && CONST_DOUBLE_HIGH (op) == 0));
874 arith5_operand (rtx op, enum machine_mode mode)
876 return register_operand (op, mode) || int5_operand (op, mode);
879 /* True iff zdepi can be used to generate this CONST_INT.
880 zdepi first sign extends a 5 bit signed number to a given field
881 length, then places this field anywhere in a zero. */
883 zdepi_cint_p (unsigned HOST_WIDE_INT x)
885 unsigned HOST_WIDE_INT lsb_mask, t;
887 /* This might not be obvious, but it's at least fast.
888 This function is critical; we don't have the time loops would take. */
890 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
891 /* Return true iff t is a power of two. */
892 return ((t & (t - 1)) == 0);
895 /* True iff depi or extru can be used to compute (reg & mask).
896 Accept bit pattern like these:
901 and_mask_p (unsigned HOST_WIDE_INT mask)
904 mask += mask & -mask;
905 return (mask & (mask - 1)) == 0;
908 /* True iff depi or extru can be used to compute (reg & OP). */
910 and_operand (rtx op, enum machine_mode mode)
912 return (register_operand (op, mode)
913 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
916 /* True iff depi can be used to compute (reg | MASK). */
918 ior_mask_p (unsigned HOST_WIDE_INT mask)
920 mask += mask & -mask;
921 return (mask & (mask - 1)) == 0;
924 /* True iff depi can be used to compute (reg | OP). */
926 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
928 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
932 lhs_lshift_operand (rtx op, enum machine_mode mode)
934 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
937 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
938 Such values can be the left hand side x in (x << r), using the zvdepi
941 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
943 unsigned HOST_WIDE_INT x;
944 if (GET_CODE (op) != CONST_INT)
946 x = INTVAL (op) >> 4;
947 return (x & (x + 1)) == 0;
951 arith32_operand (rtx op, enum machine_mode mode)
953 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
957 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
959 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
962 /* Legitimize PIC addresses. If the address is already
963 position-independent, we return ORIG. Newly generated
964 position-independent addresses go to REG. If we need more
965 than one register, we lose. */
968 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
972 /* Labels need special handling. */
973 if (pic_label_operand (orig, mode))
975 /* We do not want to go through the movXX expanders here since that
976 would create recursion.
978 Nor do we really want to call a generator for a named pattern
979 since that requires multiple patterns if we want to support
982 So instead we just emit the raw set, which avoids the movXX
983 expanders completely. */
984 mark_reg_pointer (reg, BITS_PER_UNIT);
985 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
986 current_function_uses_pic_offset_table = 1;
989 if (GET_CODE (orig) == SYMBOL_REF)
996 /* Before reload, allocate a temporary register for the intermediate
997 result. This allows the sequence to be deleted when the final
998 result is unused and the insns are trivially dead. */
999 tmp_reg = ((reload_in_progress || reload_completed)
1000 ? reg : gen_reg_rtx (Pmode));
1002 emit_move_insn (tmp_reg,
1003 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
1004 gen_rtx_HIGH (word_mode, orig)));
1006 = gen_rtx_MEM (Pmode,
1007 gen_rtx_LO_SUM (Pmode, tmp_reg,
1008 gen_rtx_UNSPEC (Pmode,
1009 gen_rtvec (1, orig),
1010 UNSPEC_DLTIND14R)));
1012 current_function_uses_pic_offset_table = 1;
1013 MEM_NOTRAP_P (pic_ref) = 1;
1014 RTX_UNCHANGING_P (pic_ref) = 1;
1015 mark_reg_pointer (reg, BITS_PER_UNIT);
1016 insn = emit_move_insn (reg, pic_ref);
1018 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
1019 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
1023 else if (GET_CODE (orig) == CONST)
1027 if (GET_CODE (XEXP (orig, 0)) == PLUS
1028 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1034 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1036 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1037 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1038 base == reg ? 0 : reg);
1043 if (GET_CODE (orig) == CONST_INT)
1045 if (INT_14_BITS (orig))
1046 return plus_constant (base, INTVAL (orig));
1047 orig = force_reg (Pmode, orig);
1049 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1050 /* Likewise, should we set special REG_NOTEs here? */
1056 /* Try machine-dependent ways of modifying an illegitimate address
1057 to be legitimate. If we find one, return the new, valid address.
1058 This macro is used in only one place: `memory_address' in explow.c.
1060 OLDX is the address as it was before break_out_memory_refs was called.
1061 In some cases it is useful to look at this to decide what needs to be done.
1063 MODE and WIN are passed so that this macro can use
1064 GO_IF_LEGITIMATE_ADDRESS.
1066 It is always safe for this macro to do nothing. It exists to recognize
1067 opportunities to optimize the output.
1069 For the PA, transform:
1071 memory(X + <large int>)
1075 if (<large int> & mask) >= 16
1076 Y = (<large int> & ~mask) + mask + 1 Round up.
1078 Y = (<large int> & ~mask) Round down.
1080 memory (Z + (<large int> - Y));
1082 This is for CSE to find several similar references, and only use one Z.
1084 X can either be a SYMBOL_REF or REG, but because combine can not
1085 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1086 D will not fit in 14 bits.
1088 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1091 MODE_INT references allow displacements which fit in 14 bits, so use
1094 This relies on the fact that most mode MODE_FLOAT references will use FP
1095 registers and most mode MODE_INT references will use integer registers.
1096 (In the rare case of an FP register used in an integer MODE, we depend
1097 on secondary reloads to clean things up.)
1100 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1101 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1102 addressing modes to be used).
1104 Put X and Z into registers. Then put the entire expression into
1108 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1109 enum machine_mode mode)
1113 /* We need to canonicalize the order of operands in unscaled indexed
1114 addresses since the code that checks if an address is valid doesn't
1115 always try both orders. */
1116 if (!TARGET_NO_SPACE_REGS
1117 && GET_CODE (x) == PLUS
1118 && GET_MODE (x) == Pmode
1119 && REG_P (XEXP (x, 0))
1120 && REG_P (XEXP (x, 1))
1121 && REG_POINTER (XEXP (x, 0))
1122 && !REG_POINTER (XEXP (x, 1)))
1123 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1126 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1128 /* Strip off CONST. */
1129 if (GET_CODE (x) == CONST)
1132 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1133 That should always be safe. */
1134 if (GET_CODE (x) == PLUS
1135 && GET_CODE (XEXP (x, 0)) == REG
1136 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1138 rtx reg = force_reg (Pmode, XEXP (x, 1));
1139 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1142 /* Note we must reject symbols which represent function addresses
1143 since the assembler/linker can't handle arithmetic on plabels. */
1144 if (GET_CODE (x) == PLUS
1145 && GET_CODE (XEXP (x, 1)) == CONST_INT
1146 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1147 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1148 || GET_CODE (XEXP (x, 0)) == REG))
1150 rtx int_part, ptr_reg;
1152 int offset = INTVAL (XEXP (x, 1));
1155 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1156 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1158 /* Choose which way to round the offset. Round up if we
1159 are >= halfway to the next boundary. */
1160 if ((offset & mask) >= ((mask + 1) / 2))
1161 newoffset = (offset & ~ mask) + mask + 1;
1163 newoffset = (offset & ~ mask);
1165 /* If the newoffset will not fit in 14 bits (ldo), then
1166 handling this would take 4 or 5 instructions (2 to load
1167 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1168 add the new offset and the SYMBOL_REF.) Combine can
1169 not handle 4->2 or 5->2 combinations, so do not create
1171 if (! VAL_14_BITS_P (newoffset)
1172 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1174 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1177 gen_rtx_HIGH (Pmode, const_part));
1180 gen_rtx_LO_SUM (Pmode,
1181 tmp_reg, const_part));
1185 if (! VAL_14_BITS_P (newoffset))
1186 int_part = force_reg (Pmode, GEN_INT (newoffset));
1188 int_part = GEN_INT (newoffset);
1190 ptr_reg = force_reg (Pmode,
1191 gen_rtx_PLUS (Pmode,
1192 force_reg (Pmode, XEXP (x, 0)),
1195 return plus_constant (ptr_reg, offset - newoffset);
1198 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1200 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1201 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1202 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1203 && (OBJECT_P (XEXP (x, 1))
1204 || GET_CODE (XEXP (x, 1)) == SUBREG)
1205 && GET_CODE (XEXP (x, 1)) != CONST)
1207 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1211 if (GET_CODE (reg1) != REG)
1212 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1214 reg2 = XEXP (XEXP (x, 0), 0);
1215 if (GET_CODE (reg2) != REG)
1216 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1218 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1219 gen_rtx_MULT (Pmode,
1225 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1227 Only do so for floating point modes since this is more speculative
1228 and we lose if it's an integer store. */
1229 if (GET_CODE (x) == PLUS
1230 && GET_CODE (XEXP (x, 0)) == PLUS
1231 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1232 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1233 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1234 && (mode == SFmode || mode == DFmode))
1237 /* First, try and figure out what to use as a base register. */
1238 rtx reg1, reg2, base, idx, orig_base;
1240 reg1 = XEXP (XEXP (x, 0), 1);
1245 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1246 then emit_move_sequence will turn on REG_POINTER so we'll know
1247 it's a base register below. */
1248 if (GET_CODE (reg1) != REG)
1249 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1251 if (GET_CODE (reg2) != REG)
1252 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1254 /* Figure out what the base and index are. */
1256 if (GET_CODE (reg1) == REG
1257 && REG_POINTER (reg1))
1260 orig_base = XEXP (XEXP (x, 0), 1);
1261 idx = gen_rtx_PLUS (Pmode,
1262 gen_rtx_MULT (Pmode,
1263 XEXP (XEXP (XEXP (x, 0), 0), 0),
1264 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1267 else if (GET_CODE (reg2) == REG
1268 && REG_POINTER (reg2))
1271 orig_base = XEXP (x, 1);
1278 /* If the index adds a large constant, try to scale the
1279 constant so that it can be loaded with only one insn. */
1280 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1281 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1282 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1283 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1285 /* Divide the CONST_INT by the scale factor, then add it to A. */
1286 int val = INTVAL (XEXP (idx, 1));
1288 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1289 reg1 = XEXP (XEXP (idx, 0), 0);
1290 if (GET_CODE (reg1) != REG)
1291 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1293 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1295 /* We can now generate a simple scaled indexed address. */
1298 (Pmode, gen_rtx_PLUS (Pmode,
1299 gen_rtx_MULT (Pmode, reg1,
1300 XEXP (XEXP (idx, 0), 1)),
1304 /* If B + C is still a valid base register, then add them. */
1305 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1306 && INTVAL (XEXP (idx, 1)) <= 4096
1307 && INTVAL (XEXP (idx, 1)) >= -4096)
1309 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1312 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1314 reg2 = XEXP (XEXP (idx, 0), 0);
1315 if (GET_CODE (reg2) != CONST_INT)
1316 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1318 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1319 gen_rtx_MULT (Pmode,
1325 /* Get the index into a register, then add the base + index and
1326 return a register holding the result. */
1328 /* First get A into a register. */
1329 reg1 = XEXP (XEXP (idx, 0), 0);
1330 if (GET_CODE (reg1) != REG)
1331 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1333 /* And get B into a register. */
1334 reg2 = XEXP (idx, 1);
1335 if (GET_CODE (reg2) != REG)
1336 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1338 reg1 = force_reg (Pmode,
1339 gen_rtx_PLUS (Pmode,
1340 gen_rtx_MULT (Pmode, reg1,
1341 XEXP (XEXP (idx, 0), 1)),
1344 /* Add the result to our base register and return. */
1345 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1349 /* Uh-oh. We might have an address for x[n-100000]. This needs
1350 special handling to avoid creating an indexed memory address
1351 with x-100000 as the base.
1353 If the constant part is small enough, then it's still safe because
1354 there is a guard page at the beginning and end of the data segment.
1356 Scaled references are common enough that we want to try and rearrange the
1357 terms so that we can use indexing for these addresses too. Only
1358 do the optimization for floatint point modes. */
1360 if (GET_CODE (x) == PLUS
1361 && symbolic_expression_p (XEXP (x, 1)))
1363 /* Ugly. We modify things here so that the address offset specified
1364 by the index expression is computed first, then added to x to form
1365 the entire address. */
1367 rtx regx1, regx2, regy1, regy2, y;
1369 /* Strip off any CONST. */
1371 if (GET_CODE (y) == CONST)
1374 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1376 /* See if this looks like
1377 (plus (mult (reg) (shadd_const))
1378 (const (plus (symbol_ref) (const_int))))
1380 Where const_int is small. In that case the const
1381 expression is a valid pointer for indexing.
1383 If const_int is big, but can be divided evenly by shadd_const
1384 and added to (reg). This allows more scaled indexed addresses. */
1385 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1386 && GET_CODE (XEXP (x, 0)) == MULT
1387 && GET_CODE (XEXP (y, 1)) == CONST_INT
1388 && INTVAL (XEXP (y, 1)) >= -4096
1389 && INTVAL (XEXP (y, 1)) <= 4095
1390 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1391 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1393 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1397 if (GET_CODE (reg1) != REG)
1398 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1400 reg2 = XEXP (XEXP (x, 0), 0);
1401 if (GET_CODE (reg2) != REG)
1402 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1404 return force_reg (Pmode,
1405 gen_rtx_PLUS (Pmode,
1406 gen_rtx_MULT (Pmode,
1411 else if ((mode == DFmode || mode == SFmode)
1412 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1413 && GET_CODE (XEXP (x, 0)) == MULT
1414 && GET_CODE (XEXP (y, 1)) == CONST_INT
1415 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1416 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1417 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1420 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1421 / INTVAL (XEXP (XEXP (x, 0), 1))));
1422 regx2 = XEXP (XEXP (x, 0), 0);
1423 if (GET_CODE (regx2) != REG)
1424 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1425 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1429 gen_rtx_PLUS (Pmode,
1430 gen_rtx_MULT (Pmode, regx2,
1431 XEXP (XEXP (x, 0), 1)),
1432 force_reg (Pmode, XEXP (y, 0))));
1434 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1435 && INTVAL (XEXP (y, 1)) >= -4096
1436 && INTVAL (XEXP (y, 1)) <= 4095)
1438 /* This is safe because of the guard page at the
1439 beginning and end of the data space. Just
1440 return the original address. */
1445 /* Doesn't look like one we can optimize. */
1446 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1447 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1448 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1449 regx1 = force_reg (Pmode,
1450 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1452 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1460 /* For the HPPA, REG and REG+CONST is cost 0
1461 and addresses involving symbolic constants are cost 2.
1463 PIC addresses are very expensive.
1465 It is no coincidence that this has the same structure
1466 as GO_IF_LEGITIMATE_ADDRESS. */
1469 hppa_address_cost (rtx X)
1471 switch (GET_CODE (X))
1484 /* Compute a (partial) cost for rtx X. Return true if the complete
1485 cost has been computed, and false if subexpressions should be
1486 scanned. In either case, *TOTAL contains the cost result. */
1489 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1494 if (INTVAL (x) == 0)
1496 else if (INT_14_BITS (x))
1513 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1514 && outer_code != SET)
1521 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1522 *total = COSTS_N_INSNS (3);
1523 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1524 *total = COSTS_N_INSNS (8);
1526 *total = COSTS_N_INSNS (20);
1530 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1532 *total = COSTS_N_INSNS (14);
1540 *total = COSTS_N_INSNS (60);
1543 case PLUS: /* this includes shNadd insns */
1545 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1546 *total = COSTS_N_INSNS (3);
1548 *total = COSTS_N_INSNS (1);
1554 *total = COSTS_N_INSNS (1);
1562 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1563 new rtx with the correct mode. */
1565 force_mode (enum machine_mode mode, rtx orig)
1567 if (mode == GET_MODE (orig))
1570 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1573 return gen_rtx_REG (mode, REGNO (orig));
1576 /* Emit insns to move operands[1] into operands[0].
1578 Return 1 if we have written out everything that needs to be done to
1579 do the move. Otherwise, return 0 and the caller will emit the move
1582 Note SCRATCH_REG may not be in the proper mode depending on how it
1583 will be used. This routine is responsible for creating a new copy
1584 of SCRATCH_REG in the proper mode. */
1587 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1589 register rtx operand0 = operands[0];
1590 register rtx operand1 = operands[1];
1593 /* We can only handle indexed addresses in the destination operand
1594 of floating point stores. Thus, we need to break out indexed
1595 addresses from the destination operand. */
1596 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1598 /* This is only safe up to the beginning of life analysis. */
1602 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1603 operand0 = replace_equiv_address (operand0, tem);
1606 /* On targets with non-equivalent space registers, break out unscaled
1607 indexed addresses from the source operand before the final CSE.
1608 We have to do this because the REG_POINTER flag is not correctly
1609 carried through various optimization passes and CSE may substitute
1610 a pseudo without the pointer set for one with the pointer set. As
1611 a result, we loose various opportunities to create insns with
1612 unscaled indexed addresses. */
1613 if (!TARGET_NO_SPACE_REGS
1614 && !cse_not_expected
1615 && GET_CODE (operand1) == MEM
1616 && GET_CODE (XEXP (operand1, 0)) == PLUS
1617 && REG_P (XEXP (XEXP (operand1, 0), 0))
1618 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1620 = replace_equiv_address (operand1,
1621 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1624 && reload_in_progress && GET_CODE (operand0) == REG
1625 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1626 operand0 = reg_equiv_mem[REGNO (operand0)];
1627 else if (scratch_reg
1628 && reload_in_progress && GET_CODE (operand0) == SUBREG
1629 && GET_CODE (SUBREG_REG (operand0)) == REG
1630 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1632 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1633 the code which tracks sets/uses for delete_output_reload. */
1634 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1635 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1636 SUBREG_BYTE (operand0));
1637 operand0 = alter_subreg (&temp);
1641 && reload_in_progress && GET_CODE (operand1) == REG
1642 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1643 operand1 = reg_equiv_mem[REGNO (operand1)];
1644 else if (scratch_reg
1645 && reload_in_progress && GET_CODE (operand1) == SUBREG
1646 && GET_CODE (SUBREG_REG (operand1)) == REG
1647 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1649 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1650 the code which tracks sets/uses for delete_output_reload. */
1651 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1652 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1653 SUBREG_BYTE (operand1));
1654 operand1 = alter_subreg (&temp);
1657 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1658 && ((tem = find_replacement (&XEXP (operand0, 0)))
1659 != XEXP (operand0, 0)))
1660 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1662 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1663 && ((tem = find_replacement (&XEXP (operand1, 0)))
1664 != XEXP (operand1, 0)))
1665 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1667 /* Handle secondary reloads for loads/stores of FP registers from
1668 REG+D addresses where D does not fit in 5 or 14 bits, including
1669 (subreg (mem (addr))) cases. */
1671 && fp_reg_operand (operand0, mode)
1672 && ((GET_CODE (operand1) == MEM
1673 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1674 XEXP (operand1, 0)))
1675 || ((GET_CODE (operand1) == SUBREG
1676 && GET_CODE (XEXP (operand1, 0)) == MEM
1677 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1679 XEXP (XEXP (operand1, 0), 0))))))
1681 if (GET_CODE (operand1) == SUBREG)
1682 operand1 = XEXP (operand1, 0);
1684 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1685 it in WORD_MODE regardless of what mode it was originally given
1687 scratch_reg = force_mode (word_mode, scratch_reg);
1689 /* D might not fit in 14 bits either; for such cases load D into
1691 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1693 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1694 emit_move_insn (scratch_reg,
1695 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1697 XEXP (XEXP (operand1, 0), 0),
1701 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1702 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1703 gen_rtx_MEM (mode, scratch_reg)));
1706 else if (scratch_reg
1707 && fp_reg_operand (operand1, mode)
1708 && ((GET_CODE (operand0) == MEM
1709 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1711 XEXP (operand0, 0)))
1712 || ((GET_CODE (operand0) == SUBREG)
1713 && GET_CODE (XEXP (operand0, 0)) == MEM
1714 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1716 XEXP (XEXP (operand0, 0), 0)))))
1718 if (GET_CODE (operand0) == SUBREG)
1719 operand0 = XEXP (operand0, 0);
1721 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1722 it in WORD_MODE regardless of what mode it was originally given
1724 scratch_reg = force_mode (word_mode, scratch_reg);
1726 /* D might not fit in 14 bits either; for such cases load D into
1728 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1730 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1731 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1734 XEXP (XEXP (operand0, 0),
1739 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1740 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1744 /* Handle secondary reloads for loads of FP registers from constant
1745 expressions by forcing the constant into memory.
1747 Use scratch_reg to hold the address of the memory location.
1749 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1750 NO_REGS when presented with a const_int and a register class
1751 containing only FP registers. Doing so unfortunately creates
1752 more problems than it solves. Fix this for 2.5. */
1753 else if (scratch_reg
1754 && CONSTANT_P (operand1)
1755 && fp_reg_operand (operand0, mode))
1759 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1760 it in WORD_MODE regardless of what mode it was originally given
1762 scratch_reg = force_mode (word_mode, scratch_reg);
1764 /* Force the constant into memory and put the address of the
1765 memory location into scratch_reg. */
1766 xoperands[0] = scratch_reg;
1767 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1768 emit_move_sequence (xoperands, Pmode, 0);
1770 /* Now load the destination register. */
1771 emit_insn (gen_rtx_SET (mode, operand0,
1772 gen_rtx_MEM (mode, scratch_reg)));
1775 /* Handle secondary reloads for SAR. These occur when trying to load
1776 the SAR from memory, FP register, or with a constant. */
1777 else if (scratch_reg
1778 && GET_CODE (operand0) == REG
1779 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1780 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1781 && (GET_CODE (operand1) == MEM
1782 || GET_CODE (operand1) == CONST_INT
1783 || (GET_CODE (operand1) == REG
1784 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1786 /* D might not fit in 14 bits either; for such cases load D into
1788 if (GET_CODE (operand1) == MEM
1789 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1791 /* We are reloading the address into the scratch register, so we
1792 want to make sure the scratch register is a full register. */
1793 scratch_reg = force_mode (word_mode, scratch_reg);
1795 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1796 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1799 XEXP (XEXP (operand1, 0),
1803 /* Now we are going to load the scratch register from memory,
1804 we want to load it in the same width as the original MEM,
1805 which must be the same as the width of the ultimate destination,
1807 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1809 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1814 /* We want to load the scratch register using the same mode as
1815 the ultimate destination. */
1816 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1818 emit_move_insn (scratch_reg, operand1);
1821 /* And emit the insn to set the ultimate destination. We know that
1822 the scratch register has the same mode as the destination at this
1824 emit_move_insn (operand0, scratch_reg);
1827 /* Handle the most common case: storing into a register. */
1828 else if (register_operand (operand0, mode))
1830 if (register_operand (operand1, mode)
1831 || (GET_CODE (operand1) == CONST_INT
1832 && cint_ok_for_move (INTVAL (operand1)))
1833 || (operand1 == CONST0_RTX (mode))
1834 || (GET_CODE (operand1) == HIGH
1835 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1836 /* Only `general_operands' can come here, so MEM is ok. */
1837 || GET_CODE (operand1) == MEM)
1839 /* Various sets are created during RTL generation which don't
1840 have the REG_POINTER flag correctly set. After the CSE pass,
1841 instruction recognition can fail if we don't consistently
1842 set this flag when performing register copies. This should
1843 also improve the opportunities for creating insns that use
1844 unscaled indexing. */
1845 if (REG_P (operand0) && REG_P (operand1))
1847 if (REG_POINTER (operand1)
1848 && !REG_POINTER (operand0)
1849 && !HARD_REGISTER_P (operand0))
1850 copy_reg_pointer (operand0, operand1);
1851 else if (REG_POINTER (operand0)
1852 && !REG_POINTER (operand1)
1853 && !HARD_REGISTER_P (operand1))
1854 copy_reg_pointer (operand1, operand0);
1857 /* When MEMs are broken out, the REG_POINTER flag doesn't
1858 get set. In some cases, we can set the REG_POINTER flag
1859 from the declaration for the MEM. */
1860 if (REG_P (operand0)
1861 && GET_CODE (operand1) == MEM
1862 && !REG_POINTER (operand0))
1864 tree decl = MEM_EXPR (operand1);
1866 /* Set the register pointer flag and register alignment
1867 if the declaration for this memory reference is a
1868 pointer type. Fortran indirect argument references
1871 && !(flag_argument_noalias > 1
1872 && TREE_CODE (decl) == INDIRECT_REF
1873 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1877 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1879 if (TREE_CODE (decl) == COMPONENT_REF)
1880 decl = TREE_OPERAND (decl, 1);
1882 type = TREE_TYPE (decl);
1883 if (TREE_CODE (type) == ARRAY_TYPE)
1884 type = get_inner_array_type (type);
1886 if (POINTER_TYPE_P (type))
1890 type = TREE_TYPE (type);
1891 /* Using TYPE_ALIGN_OK is rather conservative as
1892 only the ada frontend actually sets it. */
1893 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1895 mark_reg_pointer (operand0, align);
1900 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1904 else if (GET_CODE (operand0) == MEM)
1906 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1907 && !(reload_in_progress || reload_completed))
1909 rtx temp = gen_reg_rtx (DFmode);
1911 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1912 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1915 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1917 /* Run this case quickly. */
1918 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1921 if (! (reload_in_progress || reload_completed))
1923 operands[0] = validize_mem (operand0);
1924 operands[1] = operand1 = force_reg (mode, operand1);
1928 /* Simplify the source if we need to.
1929 Note we do have to handle function labels here, even though we do
1930 not consider them legitimate constants. Loop optimizations can
1931 call the emit_move_xxx with one as a source. */
1932 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1933 || function_label_operand (operand1, mode)
1934 || (GET_CODE (operand1) == HIGH
1935 && symbolic_operand (XEXP (operand1, 0), mode)))
1939 if (GET_CODE (operand1) == HIGH)
1942 operand1 = XEXP (operand1, 0);
1944 if (symbolic_operand (operand1, mode))
1946 /* Argh. The assembler and linker can't handle arithmetic
1949 So we force the plabel into memory, load operand0 from
1950 the memory location, then add in the constant part. */
1951 if ((GET_CODE (operand1) == CONST
1952 && GET_CODE (XEXP (operand1, 0)) == PLUS
1953 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1954 || function_label_operand (operand1, mode))
1956 rtx temp, const_part;
1958 /* Figure out what (if any) scratch register to use. */
1959 if (reload_in_progress || reload_completed)
1961 scratch_reg = scratch_reg ? scratch_reg : operand0;
1962 /* SCRATCH_REG will hold an address and maybe the actual
1963 data. We want it in WORD_MODE regardless of what mode it
1964 was originally given to us. */
1965 scratch_reg = force_mode (word_mode, scratch_reg);
1968 scratch_reg = gen_reg_rtx (Pmode);
1970 if (GET_CODE (operand1) == CONST)
1972 /* Save away the constant part of the expression. */
1973 const_part = XEXP (XEXP (operand1, 0), 1);
1974 if (GET_CODE (const_part) != CONST_INT)
1977 /* Force the function label into memory. */
1978 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1982 /* No constant part. */
1983 const_part = NULL_RTX;
1985 /* Force the function label into memory. */
1986 temp = force_const_mem (mode, operand1);
1990 /* Get the address of the memory location. PIC-ify it if
1992 temp = XEXP (temp, 0);
1994 temp = legitimize_pic_address (temp, mode, scratch_reg);
1996 /* Put the address of the memory location into our destination
1999 emit_move_sequence (operands, mode, scratch_reg);
2001 /* Now load from the memory location into our destination
2003 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
2004 emit_move_sequence (operands, mode, scratch_reg);
2006 /* And add back in the constant part. */
2007 if (const_part != NULL_RTX)
2008 expand_inc (operand0, const_part);
2017 if (reload_in_progress || reload_completed)
2019 temp = scratch_reg ? scratch_reg : operand0;
2020 /* TEMP will hold an address and maybe the actual
2021 data. We want it in WORD_MODE regardless of what mode it
2022 was originally given to us. */
2023 temp = force_mode (word_mode, temp);
2026 temp = gen_reg_rtx (Pmode);
2028 /* (const (plus (symbol) (const_int))) must be forced to
2029 memory during/after reload if the const_int will not fit
2031 if (GET_CODE (operand1) == CONST
2032 && GET_CODE (XEXP (operand1, 0)) == PLUS
2033 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
2034 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
2035 && (reload_completed || reload_in_progress)
2038 operands[1] = force_const_mem (mode, operand1);
2039 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
2041 operands[1] = gen_rtx_MEM (mode, operands[1]);
2042 emit_move_sequence (operands, mode, temp);
2046 operands[1] = legitimize_pic_address (operand1, mode, temp);
2047 if (REG_P (operand0) && REG_P (operands[1]))
2048 copy_reg_pointer (operand0, operands[1]);
2049 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2052 /* On the HPPA, references to data space are supposed to use dp,
2053 register 27, but showing it in the RTL inhibits various cse
2054 and loop optimizations. */
2059 if (reload_in_progress || reload_completed)
2061 temp = scratch_reg ? scratch_reg : operand0;
2062 /* TEMP will hold an address and maybe the actual
2063 data. We want it in WORD_MODE regardless of what mode it
2064 was originally given to us. */
2065 temp = force_mode (word_mode, temp);
2068 temp = gen_reg_rtx (mode);
2070 /* Loading a SYMBOL_REF into a register makes that register
2071 safe to be used as the base in an indexed address.
2073 Don't mark hard registers though. That loses. */
2074 if (GET_CODE (operand0) == REG
2075 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2076 mark_reg_pointer (operand0, BITS_PER_UNIT);
2077 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2078 mark_reg_pointer (temp, BITS_PER_UNIT);
2081 set = gen_rtx_SET (mode, operand0, temp);
2083 set = gen_rtx_SET (VOIDmode,
2085 gen_rtx_LO_SUM (mode, temp, operand1));
2087 emit_insn (gen_rtx_SET (VOIDmode,
2089 gen_rtx_HIGH (mode, operand1)));
2095 else if (GET_CODE (operand1) != CONST_INT
2096 || !cint_ok_for_move (INTVAL (operand1)))
2100 HOST_WIDE_INT value = 0;
2101 HOST_WIDE_INT insv = 0;
2104 if (GET_CODE (operand1) == CONST_INT)
2105 value = INTVAL (operand1);
2108 && GET_CODE (operand1) == CONST_INT
2109 && HOST_BITS_PER_WIDE_INT > 32
2110 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2114 /* Extract the low order 32 bits of the value and sign extend.
2115 If the new value is the same as the original value, we can
2116 can use the original value as-is. If the new value is
2117 different, we use it and insert the most-significant 32-bits
2118 of the original value into the final result. */
2119 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2120 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2123 #if HOST_BITS_PER_WIDE_INT > 32
2124 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2128 operand1 = GEN_INT (nval);
2132 if (reload_in_progress || reload_completed)
2133 temp = scratch_reg ? scratch_reg : operand0;
2135 temp = gen_reg_rtx (mode);
2137 /* We don't directly split DImode constants on 32-bit targets
2138 because PLUS uses an 11-bit immediate and the insn sequence
2139 generated is not as efficient as the one using HIGH/LO_SUM. */
2140 if (GET_CODE (operand1) == CONST_INT
2141 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2144 /* Directly break constant into high and low parts. This
2145 provides better optimization opportunities because various
2146 passes recognize constants split with PLUS but not LO_SUM.
2147 We use a 14-bit signed low part except when the addition
2148 of 0x4000 to the high part might change the sign of the
2150 HOST_WIDE_INT low = value & 0x3fff;
2151 HOST_WIDE_INT high = value & ~ 0x3fff;
2155 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2163 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2164 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2168 emit_insn (gen_rtx_SET (VOIDmode, temp,
2169 gen_rtx_HIGH (mode, operand1)));
2170 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2173 insn = emit_move_insn (operands[0], operands[1]);
2175 /* Now insert the most significant 32 bits of the value
2176 into the register. When we don't have a second register
2177 available, it could take up to nine instructions to load
2178 a 64-bit integer constant. Prior to reload, we force
2179 constants that would take more than three instructions
2180 to load to the constant pool. During and after reload,
2181 we have to handle all possible values. */
2184 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2185 register and the value to be inserted is outside the
2186 range that can be loaded with three depdi instructions. */
2187 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2189 operand1 = GEN_INT (insv);
2191 emit_insn (gen_rtx_SET (VOIDmode, temp,
2192 gen_rtx_HIGH (mode, operand1)));
2193 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2194 emit_insn (gen_insv (operand0, GEN_INT (32),
2199 int len = 5, pos = 27;
2201 /* Insert the bits using the depdi instruction. */
2204 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2205 HOST_WIDE_INT sign = v5 < 0;
2207 /* Left extend the insertion. */
2208 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2209 while (pos > 0 && (insv & 1) == sign)
2211 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2216 emit_insn (gen_insv (operand0, GEN_INT (len),
2217 GEN_INT (pos), GEN_INT (v5)));
2219 len = pos > 0 && pos < 5 ? pos : 5;
2226 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2231 /* Now have insn-emit do whatever it normally does. */
2235 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2236 it will need a link/runtime reloc). */
2239 reloc_needed (tree exp)
2243 switch (TREE_CODE (exp))
2250 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2251 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2256 case NON_LVALUE_EXPR:
2257 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2263 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2264 if (TREE_VALUE (link) != 0)
2265 reloc |= reloc_needed (TREE_VALUE (link));
2278 /* Does operand (which is a symbolic_operand) live in text space?
2279 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2283 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2285 if (GET_CODE (operand) == CONST)
2286 operand = XEXP (XEXP (operand, 0), 0);
2289 if (GET_CODE (operand) == SYMBOL_REF)
2290 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2294 if (GET_CODE (operand) == SYMBOL_REF)
2295 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2301 /* Return the best assembler insn template
2302 for moving operands[1] into operands[0] as a fullword. */
2304 singlemove_string (rtx *operands)
2306 HOST_WIDE_INT intval;
2308 if (GET_CODE (operands[0]) == MEM)
2309 return "stw %r1,%0";
2310 if (GET_CODE (operands[1]) == MEM)
2312 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2317 if (GET_MODE (operands[1]) != SFmode)
2320 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2322 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2323 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2325 operands[1] = GEN_INT (i);
2326 /* Fall through to CONST_INT case. */
2328 if (GET_CODE (operands[1]) == CONST_INT)
2330 intval = INTVAL (operands[1]);
2332 if (VAL_14_BITS_P (intval))
2334 else if ((intval & 0x7ff) == 0)
2335 return "ldil L'%1,%0";
2336 else if (zdepi_cint_p (intval))
2337 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2339 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2341 return "copy %1,%0";
2345 /* Compute position (in OP[1]) and width (in OP[2])
2346 useful for copying IMM to a register using the zdepi
2347 instructions. Store the immediate value to insert in OP[0]. */
2349 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2353 /* Find the least significant set bit in IMM. */
2354 for (lsb = 0; lsb < 32; lsb++)
2361 /* Choose variants based on *sign* of the 5-bit field. */
2362 if ((imm & 0x10) == 0)
2363 len = (lsb <= 28) ? 4 : 32 - lsb;
2366 /* Find the width of the bitstring in IMM. */
2367 for (len = 5; len < 32; len++)
2369 if ((imm & (1 << len)) == 0)
2373 /* Sign extend IMM as a 5-bit value. */
2374 imm = (imm & 0xf) - 0x10;
2382 /* Compute position (in OP[1]) and width (in OP[2])
2383 useful for copying IMM to a register using the depdi,z
2384 instructions. Store the immediate value to insert in OP[0]. */
2386 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2388 HOST_WIDE_INT lsb, len;
2390 /* Find the least significant set bit in IMM. */
2391 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2398 /* Choose variants based on *sign* of the 5-bit field. */
2399 if ((imm & 0x10) == 0)
2400 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2401 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2404 /* Find the width of the bitstring in IMM. */
2405 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2407 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2411 /* Sign extend IMM as a 5-bit value. */
2412 imm = (imm & 0xf) - 0x10;
2420 /* Output assembler code to perform a doubleword move insn
2421 with operands OPERANDS. */
2424 output_move_double (rtx *operands)
2426 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2428 rtx addreg0 = 0, addreg1 = 0;
2430 /* First classify both operands. */
2432 if (REG_P (operands[0]))
2434 else if (offsettable_memref_p (operands[0]))
2436 else if (GET_CODE (operands[0]) == MEM)
2441 if (REG_P (operands[1]))
2443 else if (CONSTANT_P (operands[1]))
2445 else if (offsettable_memref_p (operands[1]))
2447 else if (GET_CODE (operands[1]) == MEM)
2452 /* Check for the cases that the operand constraints are not
2453 supposed to allow to happen. Abort if we get one,
2454 because generating code for these cases is painful. */
2456 if (optype0 != REGOP && optype1 != REGOP)
2459 /* Handle auto decrementing and incrementing loads and stores
2460 specifically, since the structure of the function doesn't work
2461 for them without major modification. Do it better when we learn
2462 this port about the general inc/dec addressing of PA.
2463 (This was written by tege. Chide him if it doesn't work.) */
2465 if (optype0 == MEMOP)
2467 /* We have to output the address syntax ourselves, since print_operand
2468 doesn't deal with the addresses we want to use. Fix this later. */
2470 rtx addr = XEXP (operands[0], 0);
2471 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2473 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2475 operands[0] = XEXP (addr, 0);
2476 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2479 if (!reg_overlap_mentioned_p (high_reg, addr))
2481 /* No overlap between high target register and address
2482 register. (We do this in a non-obvious way to
2483 save a register file writeback) */
2484 if (GET_CODE (addr) == POST_INC)
2485 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2486 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2491 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2493 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2495 operands[0] = XEXP (addr, 0);
2496 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2499 if (!reg_overlap_mentioned_p (high_reg, addr))
2501 /* No overlap between high target register and address
2502 register. (We do this in a non-obvious way to
2503 save a register file writeback) */
2504 if (GET_CODE (addr) == PRE_INC)
2505 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2506 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2512 if (optype1 == MEMOP)
2514 /* We have to output the address syntax ourselves, since print_operand
2515 doesn't deal with the addresses we want to use. Fix this later. */
2517 rtx addr = XEXP (operands[1], 0);
2518 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2520 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2522 operands[1] = XEXP (addr, 0);
2523 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2526 if (!reg_overlap_mentioned_p (high_reg, addr))
2528 /* No overlap between high target register and address
2529 register. (We do this in a non-obvious way to
2530 save a register file writeback) */
2531 if (GET_CODE (addr) == POST_INC)
2532 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2533 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2537 /* This is an undefined situation. We should load into the
2538 address register *and* update that register. Probably
2539 we don't need to handle this at all. */
2540 if (GET_CODE (addr) == POST_INC)
2541 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2542 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2545 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2547 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2549 operands[1] = XEXP (addr, 0);
2550 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2553 if (!reg_overlap_mentioned_p (high_reg, addr))
2555 /* No overlap between high target register and address
2556 register. (We do this in a non-obvious way to
2557 save a register file writeback) */
2558 if (GET_CODE (addr) == PRE_INC)
2559 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2560 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2564 /* This is an undefined situation. We should load into the
2565 address register *and* update that register. Probably
2566 we don't need to handle this at all. */
2567 if (GET_CODE (addr) == PRE_INC)
2568 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2569 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2572 else if (GET_CODE (addr) == PLUS
2573 && GET_CODE (XEXP (addr, 0)) == MULT)
2575 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2577 if (!reg_overlap_mentioned_p (high_reg, addr))
2581 xoperands[0] = high_reg;
2582 xoperands[1] = XEXP (addr, 1);
2583 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2584 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2585 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2587 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2593 xoperands[0] = high_reg;
2594 xoperands[1] = XEXP (addr, 1);
2595 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2596 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2597 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2599 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2604 /* If an operand is an unoffsettable memory ref, find a register
2605 we can increment temporarily to make it refer to the second word. */
2607 if (optype0 == MEMOP)
2608 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2610 if (optype1 == MEMOP)
2611 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2613 /* Ok, we can do one word at a time.
2614 Normally we do the low-numbered word first.
2616 In either case, set up in LATEHALF the operands to use
2617 for the high-numbered word and in some cases alter the
2618 operands in OPERANDS to be suitable for the low-numbered word. */
2620 if (optype0 == REGOP)
2621 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2622 else if (optype0 == OFFSOP)
2623 latehalf[0] = adjust_address (operands[0], SImode, 4);
2625 latehalf[0] = operands[0];
2627 if (optype1 == REGOP)
2628 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2629 else if (optype1 == OFFSOP)
2630 latehalf[1] = adjust_address (operands[1], SImode, 4);
2631 else if (optype1 == CNSTOP)
2632 split_double (operands[1], &operands[1], &latehalf[1]);
2634 latehalf[1] = operands[1];
2636 /* If the first move would clobber the source of the second one,
2637 do them in the other order.
2639 This can happen in two cases:
2641 mem -> register where the first half of the destination register
2642 is the same register used in the memory's address. Reload
2643 can create such insns.
2645 mem in this case will be either register indirect or register
2646 indirect plus a valid offset.
2648 register -> register move where REGNO(dst) == REGNO(src + 1)
2649 someone (Tim/Tege?) claimed this can happen for parameter loads.
2651 Handle mem -> register case first. */
2652 if (optype0 == REGOP
2653 && (optype1 == MEMOP || optype1 == OFFSOP)
2654 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2657 /* Do the late half first. */
2659 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2660 output_asm_insn (singlemove_string (latehalf), latehalf);
2664 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2665 return singlemove_string (operands);
2668 /* Now handle register -> register case. */
2669 if (optype0 == REGOP && optype1 == REGOP
2670 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2672 output_asm_insn (singlemove_string (latehalf), latehalf);
2673 return singlemove_string (operands);
2676 /* Normal case: do the two words, low-numbered first. */
2678 output_asm_insn (singlemove_string (operands), operands);
2680 /* Make any unoffsettable addresses point at high-numbered word. */
2682 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2684 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2687 output_asm_insn (singlemove_string (latehalf), latehalf);
2689 /* Undo the adds we just did. */
2691 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2693 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2699 output_fp_move_double (rtx *operands)
2701 if (FP_REG_P (operands[0]))
2703 if (FP_REG_P (operands[1])
2704 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2705 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2707 output_asm_insn ("fldd%F1 %1,%0", operands);
2709 else if (FP_REG_P (operands[1]))
2711 output_asm_insn ("fstd%F0 %1,%0", operands);
2713 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2715 if (GET_CODE (operands[0]) == REG)
2718 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2719 xoperands[0] = operands[0];
2720 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2722 /* This is a pain. You have to be prepared to deal with an
2723 arbitrary address here including pre/post increment/decrement.
2725 so avoid this in the MD. */
2733 /* Return a REG that occurs in ADDR with coefficient 1.
2734 ADDR can be effectively incremented by incrementing REG. */
2737 find_addr_reg (rtx addr)
2739 while (GET_CODE (addr) == PLUS)
2741 if (GET_CODE (XEXP (addr, 0)) == REG)
2742 addr = XEXP (addr, 0);
2743 else if (GET_CODE (XEXP (addr, 1)) == REG)
2744 addr = XEXP (addr, 1);
2745 else if (CONSTANT_P (XEXP (addr, 0)))
2746 addr = XEXP (addr, 1);
2747 else if (CONSTANT_P (XEXP (addr, 1)))
2748 addr = XEXP (addr, 0);
2752 if (GET_CODE (addr) == REG)
2757 /* Emit code to perform a block move.
2759 OPERANDS[0] is the destination pointer as a REG, clobbered.
2760 OPERANDS[1] is the source pointer as a REG, clobbered.
2761 OPERANDS[2] is a register for temporary storage.
2762 OPERANDS[3] is a register for temporary storage.
2763 OPERANDS[4] is the size as a CONST_INT
2764 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2765 OPERANDS[6] is another temporary register. */
2768 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2770 int align = INTVAL (operands[5]);
2771 unsigned long n_bytes = INTVAL (operands[4]);
2773 /* We can't move more than a word at a time because the PA
2774 has no longer integer move insns. (Could use fp mem ops?) */
2775 if (align > (TARGET_64BIT ? 8 : 4))
2776 align = (TARGET_64BIT ? 8 : 4);
2778 /* Note that we know each loop below will execute at least twice
2779 (else we would have open-coded the copy). */
2783 /* Pre-adjust the loop counter. */
2784 operands[4] = GEN_INT (n_bytes - 16);
2785 output_asm_insn ("ldi %4,%2", operands);
2788 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2789 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2790 output_asm_insn ("std,ma %3,8(%0)", operands);
2791 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2792 output_asm_insn ("std,ma %6,8(%0)", operands);
2794 /* Handle the residual. There could be up to 7 bytes of
2795 residual to copy! */
2796 if (n_bytes % 16 != 0)
2798 operands[4] = GEN_INT (n_bytes % 8);
2799 if (n_bytes % 16 >= 8)
2800 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2801 if (n_bytes % 8 != 0)
2802 output_asm_insn ("ldd 0(%1),%6", operands);
2803 if (n_bytes % 16 >= 8)
2804 output_asm_insn ("std,ma %3,8(%0)", operands);
2805 if (n_bytes % 8 != 0)
2806 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2811 /* Pre-adjust the loop counter. */
2812 operands[4] = GEN_INT (n_bytes - 8);
2813 output_asm_insn ("ldi %4,%2", operands);
2816 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2817 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2818 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2819 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2820 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2822 /* Handle the residual. There could be up to 7 bytes of
2823 residual to copy! */
2824 if (n_bytes % 8 != 0)
2826 operands[4] = GEN_INT (n_bytes % 4);
2827 if (n_bytes % 8 >= 4)
2828 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2829 if (n_bytes % 4 != 0)
2830 output_asm_insn ("ldw 0(%1),%6", operands);
2831 if (n_bytes % 8 >= 4)
2832 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2833 if (n_bytes % 4 != 0)
2834 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2839 /* Pre-adjust the loop counter. */
2840 operands[4] = GEN_INT (n_bytes - 4);
2841 output_asm_insn ("ldi %4,%2", operands);
2844 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2845 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2846 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2847 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2848 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2850 /* Handle the residual. */
2851 if (n_bytes % 4 != 0)
2853 if (n_bytes % 4 >= 2)
2854 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2855 if (n_bytes % 2 != 0)
2856 output_asm_insn ("ldb 0(%1),%6", operands);
2857 if (n_bytes % 4 >= 2)
2858 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2859 if (n_bytes % 2 != 0)
2860 output_asm_insn ("stb %6,0(%0)", operands);
2865 /* Pre-adjust the loop counter. */
2866 operands[4] = GEN_INT (n_bytes - 2);
2867 output_asm_insn ("ldi %4,%2", operands);
2870 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2871 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2872 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2873 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2874 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2876 /* Handle the residual. */
2877 if (n_bytes % 2 != 0)
2879 output_asm_insn ("ldb 0(%1),%3", operands);
2880 output_asm_insn ("stb %3,0(%0)", operands);
2889 /* Count the number of insns necessary to handle this block move.
2891 Basic structure is the same as emit_block_move, except that we
2892 count insns rather than emit them. */
2895 compute_movmem_length (rtx insn)
2897 rtx pat = PATTERN (insn);
2898 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2899 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2900 unsigned int n_insns = 0;
2902 /* We can't move more than four bytes at a time because the PA
2903 has no longer integer move insns. (Could use fp mem ops?) */
2904 if (align > (TARGET_64BIT ? 8 : 4))
2905 align = (TARGET_64BIT ? 8 : 4);
2907 /* The basic copying loop. */
2911 if (n_bytes % (2 * align) != 0)
2913 if ((n_bytes % (2 * align)) >= align)
2916 if ((n_bytes % align) != 0)
2920 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2924 /* Emit code to perform a block clear.
2926 OPERANDS[0] is the destination pointer as a REG, clobbered.
2927 OPERANDS[1] is a register for temporary storage.
2928 OPERANDS[2] is the size as a CONST_INT
2929 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2932 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2934 int align = INTVAL (operands[3]);
2935 unsigned long n_bytes = INTVAL (operands[2]);
2937 /* We can't clear more than a word at a time because the PA
2938 has no longer integer move insns. */
2939 if (align > (TARGET_64BIT ? 8 : 4))
2940 align = (TARGET_64BIT ? 8 : 4);
2942 /* Note that we know each loop below will execute at least twice
2943 (else we would have open-coded the copy). */
2947 /* Pre-adjust the loop counter. */
2948 operands[2] = GEN_INT (n_bytes - 16);
2949 output_asm_insn ("ldi %2,%1", operands);
2952 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2953 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2954 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2956 /* Handle the residual. There could be up to 7 bytes of
2957 residual to copy! */
2958 if (n_bytes % 16 != 0)
2960 operands[2] = GEN_INT (n_bytes % 8);
2961 if (n_bytes % 16 >= 8)
2962 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2963 if (n_bytes % 8 != 0)
2964 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2969 /* Pre-adjust the loop counter. */
2970 operands[2] = GEN_INT (n_bytes - 8);
2971 output_asm_insn ("ldi %2,%1", operands);
2974 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2975 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2976 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2978 /* Handle the residual. There could be up to 7 bytes of
2979 residual to copy! */
2980 if (n_bytes % 8 != 0)
2982 operands[2] = GEN_INT (n_bytes % 4);
2983 if (n_bytes % 8 >= 4)
2984 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2985 if (n_bytes % 4 != 0)
2986 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2991 /* Pre-adjust the loop counter. */
2992 operands[2] = GEN_INT (n_bytes - 4);
2993 output_asm_insn ("ldi %2,%1", operands);
2996 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2997 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2998 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3000 /* Handle the residual. */
3001 if (n_bytes % 4 != 0)
3003 if (n_bytes % 4 >= 2)
3004 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3005 if (n_bytes % 2 != 0)
3006 output_asm_insn ("stb %%r0,0(%0)", operands);
3011 /* Pre-adjust the loop counter. */
3012 operands[2] = GEN_INT (n_bytes - 2);
3013 output_asm_insn ("ldi %2,%1", operands);
3016 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3017 output_asm_insn ("addib,>= -2,%1,.-4", operands);
3018 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3020 /* Handle the residual. */
3021 if (n_bytes % 2 != 0)
3022 output_asm_insn ("stb %%r0,0(%0)", operands);
3031 /* Count the number of insns necessary to handle this block move.
3033 Basic structure is the same as emit_block_move, except that we
3034 count insns rather than emit them. */
3037 compute_clrmem_length (rtx insn)
3039 rtx pat = PATTERN (insn);
3040 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
3041 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
3042 unsigned int n_insns = 0;
3044 /* We can't clear more than a word at a time because the PA
3045 has no longer integer move insns. */
3046 if (align > (TARGET_64BIT ? 8 : 4))
3047 align = (TARGET_64BIT ? 8 : 4);
3049 /* The basic loop. */
3053 if (n_bytes % (2 * align) != 0)
3055 if ((n_bytes % (2 * align)) >= align)
3058 if ((n_bytes % align) != 0)
3062 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3068 output_and (rtx *operands)
3070 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3072 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3073 int ls0, ls1, ms0, p, len;
3075 for (ls0 = 0; ls0 < 32; ls0++)
3076 if ((mask & (1 << ls0)) == 0)
3079 for (ls1 = ls0; ls1 < 32; ls1++)
3080 if ((mask & (1 << ls1)) != 0)
3083 for (ms0 = ls1; ms0 < 32; ms0++)
3084 if ((mask & (1 << ms0)) == 0)
3097 operands[2] = GEN_INT (len);
3098 return "{extru|extrw,u} %1,31,%2,%0";
3102 /* We could use this `depi' for the case above as well, but `depi'
3103 requires one more register file access than an `extru'. */
3108 operands[2] = GEN_INT (p);
3109 operands[3] = GEN_INT (len);
3110 return "{depi|depwi} 0,%2,%3,%0";
3114 return "and %1,%2,%0";
3117 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3118 storing the result in operands[0]. */
3120 output_64bit_and (rtx *operands)
3122 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3124 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3125 int ls0, ls1, ms0, p, len;
3127 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3128 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3131 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3132 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3135 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3136 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3139 if (ms0 != HOST_BITS_PER_WIDE_INT)
3142 if (ls1 == HOST_BITS_PER_WIDE_INT)
3149 operands[2] = GEN_INT (len);
3150 return "extrd,u %1,63,%2,%0";
3154 /* We could use this `depi' for the case above as well, but `depi'
3155 requires one more register file access than an `extru'. */
3160 operands[2] = GEN_INT (p);
3161 operands[3] = GEN_INT (len);
3162 return "depdi 0,%2,%3,%0";
3166 return "and %1,%2,%0";
3170 output_ior (rtx *operands)
3172 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3173 int bs0, bs1, p, len;
3175 if (INTVAL (operands[2]) == 0)
3176 return "copy %1,%0";
3178 for (bs0 = 0; bs0 < 32; bs0++)
3179 if ((mask & (1 << bs0)) != 0)
3182 for (bs1 = bs0; bs1 < 32; bs1++)
3183 if ((mask & (1 << bs1)) == 0)
3186 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3192 operands[2] = GEN_INT (p);
3193 operands[3] = GEN_INT (len);
3194 return "{depi|depwi} -1,%2,%3,%0";
3197 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3198 storing the result in operands[0]. */
3200 output_64bit_ior (rtx *operands)
3202 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3203 int bs0, bs1, p, len;
3205 if (INTVAL (operands[2]) == 0)
3206 return "copy %1,%0";
3208 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3209 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3212 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3213 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3216 if (bs1 != HOST_BITS_PER_WIDE_INT
3217 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3223 operands[2] = GEN_INT (p);
3224 operands[3] = GEN_INT (len);
3225 return "depdi -1,%2,%3,%0";
3228 /* Target hook for assembling integer objects. This code handles
3229 aligned SI and DI integers specially, since function references must
3230 be preceded by P%. */
3233 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3235 if (size == UNITS_PER_WORD && aligned_p
3236 && function_label_operand (x, VOIDmode))
3238 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3239 output_addr_const (asm_out_file, x);
3240 fputc ('\n', asm_out_file);
3243 return default_assemble_integer (x, size, aligned_p);
3246 /* Output an ascii string. */
3248 output_ascii (FILE *file, const char *p, int size)
3252 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3254 /* The HP assembler can only take strings of 256 characters at one
3255 time. This is a limitation on input line length, *not* the
3256 length of the string. Sigh. Even worse, it seems that the
3257 restriction is in number of input characters (see \xnn &
3258 \whatever). So we have to do this very carefully. */
3260 fputs ("\t.STRING \"", file);
3263 for (i = 0; i < size; i += 4)
3267 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3269 register unsigned int c = (unsigned char) p[i + io];
3271 if (c == '\"' || c == '\\')
3272 partial_output[co++] = '\\';
3273 if (c >= ' ' && c < 0177)
3274 partial_output[co++] = c;
3278 partial_output[co++] = '\\';
3279 partial_output[co++] = 'x';
3280 hexd = c / 16 - 0 + '0';
3282 hexd -= '9' - 'a' + 1;
3283 partial_output[co++] = hexd;
3284 hexd = c % 16 - 0 + '0';
3286 hexd -= '9' - 'a' + 1;
3287 partial_output[co++] = hexd;
3290 if (chars_output + co > 243)
3292 fputs ("\"\n\t.STRING \"", file);
3295 fwrite (partial_output, 1, (size_t) co, file);
3299 fputs ("\"\n", file);
3302 /* Try to rewrite floating point comparisons & branches to avoid
3303 useless add,tr insns.
3305 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3306 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3307 first attempt to remove useless add,tr insns. It is zero
3308 for the second pass as reorg sometimes leaves bogus REG_DEAD
3311 When CHECK_NOTES is zero we can only eliminate add,tr insns
3312 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3315 remove_useless_addtr_insns (int check_notes)
3318 static int pass = 0;
3320 /* This is fairly cheap, so always run it when optimizing. */
3324 int fbranch_count = 0;
3326 /* Walk all the insns in this function looking for fcmp & fbranch
3327 instructions. Keep track of how many of each we find. */
3328 for (insn = get_insns (); insn; insn = next_insn (insn))
3332 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3333 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3336 tmp = PATTERN (insn);
3338 /* It must be a set. */
3339 if (GET_CODE (tmp) != SET)
3342 /* If the destination is CCFP, then we've found an fcmp insn. */
3343 tmp = SET_DEST (tmp);
3344 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3350 tmp = PATTERN (insn);
3351 /* If this is an fbranch instruction, bump the fbranch counter. */
3352 if (GET_CODE (tmp) == SET
3353 && SET_DEST (tmp) == pc_rtx
3354 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3355 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3356 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3357 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3365 /* Find all floating point compare + branch insns. If possible,
3366 reverse the comparison & the branch to avoid add,tr insns. */
3367 for (insn = get_insns (); insn; insn = next_insn (insn))
3371 /* Ignore anything that isn't an INSN. */
3372 if (GET_CODE (insn) != INSN)
3375 tmp = PATTERN (insn);
3377 /* It must be a set. */
3378 if (GET_CODE (tmp) != SET)
3381 /* The destination must be CCFP, which is register zero. */
3382 tmp = SET_DEST (tmp);
3383 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3386 /* INSN should be a set of CCFP.
3388 See if the result of this insn is used in a reversed FP
3389 conditional branch. If so, reverse our condition and
3390 the branch. Doing so avoids useless add,tr insns. */
3391 next = next_insn (insn);
3394 /* Jumps, calls and labels stop our search. */
3395 if (GET_CODE (next) == JUMP_INSN
3396 || GET_CODE (next) == CALL_INSN
3397 || GET_CODE (next) == CODE_LABEL)
3400 /* As does another fcmp insn. */
3401 if (GET_CODE (next) == INSN
3402 && GET_CODE (PATTERN (next)) == SET
3403 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3404 && REGNO (SET_DEST (PATTERN (next))) == 0)
3407 next = next_insn (next);
3410 /* Is NEXT_INSN a branch? */
3412 && GET_CODE (next) == JUMP_INSN)
3414 rtx pattern = PATTERN (next);
3416 /* If it a reversed fp conditional branch (eg uses add,tr)
3417 and CCFP dies, then reverse our conditional and the branch
3418 to avoid the add,tr. */
3419 if (GET_CODE (pattern) == SET
3420 && SET_DEST (pattern) == pc_rtx
3421 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3422 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3423 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3424 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3425 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3426 && (fcmp_count == fbranch_count
3428 && find_regno_note (next, REG_DEAD, 0))))
3430 /* Reverse the branch. */
3431 tmp = XEXP (SET_SRC (pattern), 1);
3432 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3433 XEXP (SET_SRC (pattern), 2) = tmp;
3434 INSN_CODE (next) = -1;
3436 /* Reverse our condition. */
3437 tmp = PATTERN (insn);
3438 PUT_CODE (XEXP (tmp, 1),
3439 (reverse_condition_maybe_unordered
3440 (GET_CODE (XEXP (tmp, 1)))));
3450 /* You may have trouble believing this, but this is the 32 bit HP-PA
3455 Variable arguments (optional; any number may be allocated)
3457 SP-(4*(N+9)) arg word N
3462 Fixed arguments (must be allocated; may remain unused)
3471 SP-32 External Data Pointer (DP)
3473 SP-24 External/stub RP (RP')
3477 SP-8 Calling Stub RP (RP'')
3482 SP-0 Stack Pointer (points to next available address)
3486 /* This function saves registers as follows. Registers marked with ' are
3487 this function's registers (as opposed to the previous function's).
3488 If a frame_pointer isn't needed, r4 is saved as a general register;
3489 the space for the frame pointer is still allocated, though, to keep
3495 SP (FP') Previous FP
3496 SP + 4 Alignment filler (sigh)
3497 SP + 8 Space for locals reserved here.
3501 SP + n All call saved register used.
3505 SP + o All call saved fp registers used.
3509 SP + p (SP') points to next available address.
3513 /* Global variables set by output_function_prologue(). */
3514 /* Size of frame. Need to know this to emit return insns from
3516 static HOST_WIDE_INT actual_fsize, local_fsize;
3517 static int save_fregs;
3519 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3520 Handle case where DISP > 8k by using the add_high_const patterns.
3522 Note in DISP > 8k case, we will leave the high part of the address
3523 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3526 store_reg (int reg, HOST_WIDE_INT disp, int base)
3528 rtx insn, dest, src, basereg;
3530 src = gen_rtx_REG (word_mode, reg);
3531 basereg = gen_rtx_REG (Pmode, base);
3532 if (VAL_14_BITS_P (disp))
3534 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3535 insn = emit_move_insn (dest, src);
3537 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3539 rtx delta = GEN_INT (disp);
3540 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3542 emit_move_insn (tmpreg, delta);
3543 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3544 dest = gen_rtx_MEM (word_mode, tmpreg);
3545 insn = emit_move_insn (dest, src);
3549 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3550 gen_rtx_SET (VOIDmode,
3551 gen_rtx_MEM (word_mode,
3552 gen_rtx_PLUS (word_mode, basereg,
3560 rtx delta = GEN_INT (disp);
3561 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3562 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3564 emit_move_insn (tmpreg, high);
3565 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3566 insn = emit_move_insn (dest, src);
3570 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3571 gen_rtx_SET (VOIDmode,
3572 gen_rtx_MEM (word_mode,
3573 gen_rtx_PLUS (word_mode, basereg,
3581 RTX_FRAME_RELATED_P (insn) = 1;
3584 /* Emit RTL to store REG at the memory location specified by BASE and then
3585 add MOD to BASE. MOD must be <= 8k. */
3588 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3590 rtx insn, basereg, srcreg, delta;
3592 if (!VAL_14_BITS_P (mod))
3595 basereg = gen_rtx_REG (Pmode, base);
3596 srcreg = gen_rtx_REG (word_mode, reg);
3597 delta = GEN_INT (mod);
3599 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3602 RTX_FRAME_RELATED_P (insn) = 1;
3604 /* RTX_FRAME_RELATED_P must be set on each frame related set
3605 in a parallel with more than one element. Don't set
3606 RTX_FRAME_RELATED_P in the first set if reg is temporary
3607 register 1. The effect of this operation is recorded in
3608 the initial copy. */
3611 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3612 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3616 /* The first element of a PARALLEL is always processed if it is
3617 a SET. Thus, we need an expression list for this case. */
3619 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3620 gen_rtx_SET (VOIDmode, basereg,
3621 gen_rtx_PLUS (word_mode, basereg, delta)),
3627 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3628 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3629 whether to add a frame note or not.
3631 In the DISP > 8k case, we leave the high part of the address in %r1.
3632 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3635 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3639 if (VAL_14_BITS_P (disp))
3641 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3642 plus_constant (gen_rtx_REG (Pmode, base), disp));
3644 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3646 rtx basereg = gen_rtx_REG (Pmode, base);
3647 rtx delta = GEN_INT (disp);
3648 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3650 emit_move_insn (tmpreg, delta);
3651 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3652 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3656 rtx basereg = gen_rtx_REG (Pmode, base);
3657 rtx delta = GEN_INT (disp);
3658 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3660 emit_move_insn (tmpreg,
3661 gen_rtx_PLUS (Pmode, basereg,
3662 gen_rtx_HIGH (Pmode, delta)));
3663 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3664 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3667 if (DO_FRAME_NOTES && note)
3668 RTX_FRAME_RELATED_P (insn) = 1;
3672 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3677 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3678 be consistent with the rounding and size calculation done here.
3679 Change them at the same time. */
3681 /* We do our own stack alignment. First, round the size of the
3682 stack locals up to a word boundary. */
3683 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3685 /* Space for previous frame pointer + filler. If any frame is
3686 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3687 waste some space here for the sake of HP compatibility. The
3688 first slot is only used when the frame pointer is needed. */
3689 if (size || frame_pointer_needed)
3690 size += STARTING_FRAME_OFFSET;
3692 /* If the current function calls __builtin_eh_return, then we need
3693 to allocate stack space for registers that will hold data for
3694 the exception handler. */
3695 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3699 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3701 size += i * UNITS_PER_WORD;
3704 /* Account for space used by the callee general register saves. */
3705 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3706 if (regs_ever_live[i])
3707 size += UNITS_PER_WORD;
3709 /* Account for space used by the callee floating point register saves. */
3710 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3711 if (regs_ever_live[i]
3712 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3716 /* We always save both halves of the FP register, so always
3717 increment the frame size by 8 bytes. */
3721 /* If any of the floating registers are saved, account for the
3722 alignment needed for the floating point register save block. */
3725 size = (size + 7) & ~7;
3730 /* The various ABIs include space for the outgoing parameters in the
3731 size of the current function's stack frame. We don't need to align
3732 for the outgoing arguments as their alignment is set by the final
3733 rounding for the frame as a whole. */
3734 size += current_function_outgoing_args_size;
3736 /* Allocate space for the fixed frame marker. This space must be
3737 allocated for any function that makes calls or allocates
3739 if (!current_function_is_leaf || size)
3740 size += TARGET_64BIT ? 48 : 32;
3742 /* Finally, round to the preferred stack boundary. */
3743 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3744 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3747 /* Generate the assembly code for function entry. FILE is a stdio
3748 stream to output the code to. SIZE is an int: how many units of
3749 temporary storage to allocate.
3751 Refer to the array `regs_ever_live' to determine which registers to
3752 save; `regs_ever_live[I]' is nonzero if register number I is ever
3753 used in the function. This function is responsible for knowing
3754 which registers should not be saved even if used. */
3756 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3757 of memory. If any fpu reg is used in the function, we allocate
3758 such a block here, at the bottom of the frame, just in case it's needed.
3760 If this function is a leaf procedure, then we may choose not
3761 to do a "save" insn. The decision about whether or not
3762 to do this is made in regclass.c. */
3765 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3767 /* The function's label and associated .PROC must never be
3768 separated and must be output *after* any profiling declarations
3769 to avoid changing spaces/subspaces within a procedure. */
3770 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3771 fputs ("\t.PROC\n", file);
3773 /* hppa_expand_prologue does the dirty work now. We just need
3774 to output the assembler directives which denote the start
3776 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3777 if (regs_ever_live[2])
3778 fputs (",CALLS,SAVE_RP", file);
3780 fputs (",NO_CALLS", file);
3782 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3783 at the beginning of the frame and that it is used as the frame
3784 pointer for the frame. We do this because our current frame
3785 layout doesn't conform to that specified in the the HP runtime
3786 documentation and we need a way to indicate to programs such as
3787 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3788 isn't used by HP compilers but is supported by the assembler.
3789 However, SAVE_SP is supposed to indicate that the previous stack
3790 pointer has been saved in the frame marker. */
3791 if (frame_pointer_needed)
3792 fputs (",SAVE_SP", file);
3794 /* Pass on information about the number of callee register saves
3795 performed in the prologue.
3797 The compiler is supposed to pass the highest register number
3798 saved, the assembler then has to adjust that number before
3799 entering it into the unwind descriptor (to account for any
3800 caller saved registers with lower register numbers than the
3801 first callee saved register). */
3803 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3806 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3808 fputs ("\n\t.ENTRY\n", file);
3810 remove_useless_addtr_insns (0);
3814 hppa_expand_prologue (void)
3816 int merge_sp_adjust_with_store = 0;
3817 HOST_WIDE_INT size = get_frame_size ();
3818 HOST_WIDE_INT offset;
3826 /* Compute total size for frame pointer, filler, locals and rounding to
3827 the next word boundary. Similar code appears in compute_frame_size
3828 and must be changed in tandem with this code. */
3829 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3830 if (local_fsize || frame_pointer_needed)
3831 local_fsize += STARTING_FRAME_OFFSET;
3833 actual_fsize = compute_frame_size (size, &save_fregs);
3835 /* Compute a few things we will use often. */
3836 tmpreg = gen_rtx_REG (word_mode, 1);
3838 /* Save RP first. The calling conventions manual states RP will
3839 always be stored into the caller's frame at sp - 20 or sp - 16
3840 depending on which ABI is in use. */
3841 if (regs_ever_live[2] || current_function_calls_eh_return)
3842 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3844 /* Allocate the local frame and set up the frame pointer if needed. */
3845 if (actual_fsize != 0)
3847 if (frame_pointer_needed)
3849 /* Copy the old frame pointer temporarily into %r1. Set up the
3850 new stack pointer, then store away the saved old frame pointer
3851 into the stack at sp and at the same time update the stack
3852 pointer by actual_fsize bytes. Two versions, first
3853 handles small (<8k) frames. The second handles large (>=8k)
3855 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3858 /* We need to record the frame pointer save here since the
3859 new frame pointer is set in the following insn. */
3860 RTX_FRAME_RELATED_P (insn) = 1;
3862 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3863 gen_rtx_SET (VOIDmode,
3864 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3869 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3871 RTX_FRAME_RELATED_P (insn) = 1;
3873 if (VAL_14_BITS_P (actual_fsize))
3874 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3877 /* It is incorrect to store the saved frame pointer at *sp,
3878 then increment sp (writes beyond the current stack boundary).
3880 So instead use stwm to store at *sp and post-increment the
3881 stack pointer as an atomic operation. Then increment sp to
3882 finish allocating the new frame. */
3883 HOST_WIDE_INT adjust1 = 8192 - 64;
3884 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3886 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3887 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3891 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3892 we need to store the previous stack pointer (frame pointer)
3893 into the frame marker on targets that use the HP unwind
3894 library. This allows the HP unwind library to be used to
3895 unwind GCC frames. However, we are not fully compatible
3896 with the HP library because our frame layout differs from
3897 that specified in the HP runtime specification.
3899 We don't want a frame note on this instruction as the frame
3900 marker moves during dynamic stack allocation.
3902 This instruction also serves as a blockage to prevent
3903 register spills from being scheduled before the stack
3904 pointer is raised. This is necessary as we store
3905 registers using the frame pointer as a base register,
3906 and the frame pointer is set before sp is raised. */
3907 if (TARGET_HPUX_UNWIND_LIBRARY)
3909 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3910 GEN_INT (TARGET_64BIT ? -8 : -4));
3912 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3916 emit_insn (gen_blockage ());
3918 /* no frame pointer needed. */
3921 /* In some cases we can perform the first callee register save
3922 and allocating the stack frame at the same time. If so, just
3923 make a note of it and defer allocating the frame until saving
3924 the callee registers. */
3925 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3926 merge_sp_adjust_with_store = 1;
3927 /* Can not optimize. Adjust the stack frame by actual_fsize
3930 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3935 /* Normal register save.
3937 Do not save the frame pointer in the frame_pointer_needed case. It
3938 was done earlier. */
3939 if (frame_pointer_needed)
3941 offset = local_fsize;
3943 /* Saving the EH return data registers in the frame is the simplest
3944 way to get the frame unwind information emitted. We put them
3945 just before the general registers. */
3946 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3948 unsigned int i, regno;
3952 regno = EH_RETURN_DATA_REGNO (i);
3953 if (regno == INVALID_REGNUM)
3956 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3957 offset += UNITS_PER_WORD;
3961 for (i = 18; i >= 4; i--)
3962 if (regs_ever_live[i] && ! call_used_regs[i])
3964 store_reg (i, offset, FRAME_POINTER_REGNUM);
3965 offset += UNITS_PER_WORD;
3968 /* Account for %r3 which is saved in a special place. */
3971 /* No frame pointer needed. */
3974 offset = local_fsize - actual_fsize;
3976 /* Saving the EH return data registers in the frame is the simplest
3977 way to get the frame unwind information emitted. */
3978 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3980 unsigned int i, regno;
3984 regno = EH_RETURN_DATA_REGNO (i);
3985 if (regno == INVALID_REGNUM)
3988 /* If merge_sp_adjust_with_store is nonzero, then we can
3989 optimize the first save. */
3990 if (merge_sp_adjust_with_store)
3992 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3993 merge_sp_adjust_with_store = 0;
3996 store_reg (regno, offset, STACK_POINTER_REGNUM);
3997 offset += UNITS_PER_WORD;
4001 for (i = 18; i >= 3; i--)
4002 if (regs_ever_live[i] && ! call_used_regs[i])
4004 /* If merge_sp_adjust_with_store is nonzero, then we can
4005 optimize the first GR save. */
4006 if (merge_sp_adjust_with_store)
4008 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
4009 merge_sp_adjust_with_store = 0;
4012 store_reg (i, offset, STACK_POINTER_REGNUM);
4013 offset += UNITS_PER_WORD;
4017 /* If we wanted to merge the SP adjustment with a GR save, but we never
4018 did any GR saves, then just emit the adjustment here. */
4019 if (merge_sp_adjust_with_store)
4020 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4024 /* The hppa calling conventions say that %r19, the pic offset
4025 register, is saved at sp - 32 (in this function's frame)
4026 when generating PIC code. FIXME: What is the correct thing
4027 to do for functions which make no calls and allocate no
4028 frame? Do we need to allocate a frame, or can we just omit
4029 the save? For now we'll just omit the save.
4031 We don't want a note on this insn as the frame marker can
4032 move if there is a dynamic stack allocation. */
4033 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
4035 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
4037 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
4041 /* Align pointer properly (doubleword boundary). */
4042 offset = (offset + 7) & ~7;
4044 /* Floating point register store. */
4049 /* First get the frame or stack pointer to the start of the FP register
4051 if (frame_pointer_needed)
4053 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4054 base = frame_pointer_rtx;
4058 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4059 base = stack_pointer_rtx;
4062 /* Now actually save the FP registers. */
4063 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4065 if (regs_ever_live[i]
4066 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4068 rtx addr, insn, reg;
4069 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4070 reg = gen_rtx_REG (DFmode, i);
4071 insn = emit_move_insn (addr, reg);
4074 RTX_FRAME_RELATED_P (insn) = 1;
4077 rtx mem = gen_rtx_MEM (DFmode,
4078 plus_constant (base, offset));
4080 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4081 gen_rtx_SET (VOIDmode, mem, reg),
4086 rtx meml = gen_rtx_MEM (SFmode,
4087 plus_constant (base, offset));
4088 rtx memr = gen_rtx_MEM (SFmode,
4089 plus_constant (base, offset + 4));
4090 rtx regl = gen_rtx_REG (SFmode, i);
4091 rtx regr = gen_rtx_REG (SFmode, i + 1);
4092 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4093 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4096 RTX_FRAME_RELATED_P (setl) = 1;
4097 RTX_FRAME_RELATED_P (setr) = 1;
4098 vec = gen_rtvec (2, setl, setr);
4100 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4101 gen_rtx_SEQUENCE (VOIDmode, vec),
4105 offset += GET_MODE_SIZE (DFmode);
4112 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4113 Handle case where DISP > 8k by using the add_high_const patterns. */
4116 load_reg (int reg, HOST_WIDE_INT disp, int base)
4118 rtx dest = gen_rtx_REG (word_mode, reg);
4119 rtx basereg = gen_rtx_REG (Pmode, base);
4122 if (VAL_14_BITS_P (disp))
4123 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4124 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4126 rtx delta = GEN_INT (disp);
4127 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4129 emit_move_insn (tmpreg, delta);
4130 if (TARGET_DISABLE_INDEXING)
4132 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4133 src = gen_rtx_MEM (word_mode, tmpreg);
4136 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4140 rtx delta = GEN_INT (disp);
4141 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4142 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4144 emit_move_insn (tmpreg, high);
4145 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4148 emit_move_insn (dest, src);
4151 /* Update the total code bytes output to the text section. */
4154 update_total_code_bytes (int nbytes)
4156 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4157 && !IN_NAMED_SECTION_P (cfun->decl))
4159 if (INSN_ADDRESSES_SET_P ())
4161 unsigned long old_total = total_code_bytes;
4163 total_code_bytes += nbytes;
4165 /* Be prepared to handle overflows. */
4166 if (old_total > total_code_bytes)
4167 total_code_bytes = -1;
4170 total_code_bytes = -1;
4174 /* This function generates the assembly code for function exit.
4175 Args are as for output_function_prologue ().
4177 The function epilogue should not depend on the current stack
4178 pointer! It should use the frame pointer only. This is mandatory
4179 because of alloca; we also take advantage of it to omit stack
4180 adjustments before returning. */
4183 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4185 rtx insn = get_last_insn ();
4189 /* hppa_expand_epilogue does the dirty work now. We just need
4190 to output the assembler directives which denote the end
4193 To make debuggers happy, emit a nop if the epilogue was completely
4194 eliminated due to a volatile call as the last insn in the
4195 current function. That way the return address (in %r2) will
4196 always point to a valid instruction in the current function. */
4198 /* Get the last real insn. */
4199 if (GET_CODE (insn) == NOTE)
4200 insn = prev_real_insn (insn);
4202 /* If it is a sequence, then look inside. */
4203 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4204 insn = XVECEXP (PATTERN (insn), 0, 0);
4206 /* If insn is a CALL_INSN, then it must be a call to a volatile
4207 function (otherwise there would be epilogue insns). */
4208 if (insn && GET_CODE (insn) == CALL_INSN)
4210 fputs ("\tnop\n", file);
4214 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4216 if (INSN_ADDRESSES_SET_P ())
4218 insn = get_last_nonnote_insn ();
4219 last_address += INSN_ADDRESSES (INSN_UID (insn));
4221 last_address += insn_default_length (insn);
4222 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4223 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4226 /* Finally, update the total number of code bytes output so far. */
4227 update_total_code_bytes (last_address);
4231 hppa_expand_epilogue (void)
4234 HOST_WIDE_INT offset;
4235 HOST_WIDE_INT ret_off = 0;
4237 int merge_sp_adjust_with_load = 0;
4239 /* We will use this often. */
4240 tmpreg = gen_rtx_REG (word_mode, 1);
4242 /* Try to restore RP early to avoid load/use interlocks when
4243 RP gets used in the return (bv) instruction. This appears to still
4244 be necessary even when we schedule the prologue and epilogue. */
4245 if (regs_ever_live [2] || current_function_calls_eh_return)
4247 ret_off = TARGET_64BIT ? -16 : -20;
4248 if (frame_pointer_needed)
4250 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4255 /* No frame pointer, and stack is smaller than 8k. */
4256 if (VAL_14_BITS_P (ret_off - actual_fsize))
4258 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4264 /* General register restores. */
4265 if (frame_pointer_needed)
4267 offset = local_fsize;
4269 /* If the current function calls __builtin_eh_return, then we need
4270 to restore the saved EH data registers. */
4271 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4273 unsigned int i, regno;
4277 regno = EH_RETURN_DATA_REGNO (i);
4278 if (regno == INVALID_REGNUM)
4281 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4282 offset += UNITS_PER_WORD;
4286 for (i = 18; i >= 4; i--)
4287 if (regs_ever_live[i] && ! call_used_regs[i])
4289 load_reg (i, offset, FRAME_POINTER_REGNUM);
4290 offset += UNITS_PER_WORD;
4295 offset = local_fsize - actual_fsize;
4297 /* If the current function calls __builtin_eh_return, then we need
4298 to restore the saved EH data registers. */
4299 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4301 unsigned int i, regno;
4305 regno = EH_RETURN_DATA_REGNO (i);
4306 if (regno == INVALID_REGNUM)
4309 /* Only for the first load.
4310 merge_sp_adjust_with_load holds the register load
4311 with which we will merge the sp adjustment. */
4312 if (merge_sp_adjust_with_load == 0
4314 && VAL_14_BITS_P (-actual_fsize))
4315 merge_sp_adjust_with_load = regno;
4317 load_reg (regno, offset, STACK_POINTER_REGNUM);
4318 offset += UNITS_PER_WORD;
4322 for (i = 18; i >= 3; i--)
4324 if (regs_ever_live[i] && ! call_used_regs[i])
4326 /* Only for the first load.
4327 merge_sp_adjust_with_load holds the register load
4328 with which we will merge the sp adjustment. */
4329 if (merge_sp_adjust_with_load == 0
4331 && VAL_14_BITS_P (-actual_fsize))
4332 merge_sp_adjust_with_load = i;
4334 load_reg (i, offset, STACK_POINTER_REGNUM);
4335 offset += UNITS_PER_WORD;
4340 /* Align pointer properly (doubleword boundary). */
4341 offset = (offset + 7) & ~7;
4343 /* FP register restores. */
4346 /* Adjust the register to index off of. */
4347 if (frame_pointer_needed)
4348 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4350 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4352 /* Actually do the restores now. */
4353 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4354 if (regs_ever_live[i]
4355 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4357 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4358 rtx dest = gen_rtx_REG (DFmode, i);
4359 emit_move_insn (dest, src);
4363 /* Emit a blockage insn here to keep these insns from being moved to
4364 an earlier spot in the epilogue, or into the main instruction stream.
4366 This is necessary as we must not cut the stack back before all the
4367 restores are finished. */
4368 emit_insn (gen_blockage ());
4370 /* Reset stack pointer (and possibly frame pointer). The stack
4371 pointer is initially set to fp + 64 to avoid a race condition. */
4372 if (frame_pointer_needed)
4374 rtx delta = GEN_INT (-64);
4376 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4377 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4379 /* If we were deferring a callee register restore, do it now. */
4380 else if (merge_sp_adjust_with_load)
4382 rtx delta = GEN_INT (-actual_fsize);
4383 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4385 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4387 else if (actual_fsize != 0)
4388 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4391 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4392 frame greater than 8k), do so now. */
4394 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4396 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4398 rtx sa = EH_RETURN_STACKADJ_RTX;
4400 emit_insn (gen_blockage ());
4401 emit_insn (TARGET_64BIT
4402 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4403 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4408 hppa_pic_save_rtx (void)
4410 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4414 hppa_profile_hook (int label_no)
4416 /* We use SImode for the address of the function in both 32 and
4417 64-bit code to avoid having to provide DImode versions of the
4418 lcla2 and load_offset_label_address insn patterns. */
4419 rtx reg = gen_reg_rtx (SImode);
4420 rtx label_rtx = gen_label_rtx ();
4421 rtx begin_label_rtx, call_insn;
4422 char begin_label_name[16];
4424 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4426 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4429 emit_move_insn (arg_pointer_rtx,
4430 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4433 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4435 /* The address of the function is loaded into %r25 with a instruction-
4436 relative sequence that avoids the use of relocations. The sequence
4437 is split so that the load_offset_label_address instruction can
4438 occupy the delay slot of the call to _mcount. */
4440 emit_insn (gen_lcla2 (reg, label_rtx));
4442 emit_insn (gen_lcla1 (reg, label_rtx));
4444 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4445 reg, begin_label_rtx, label_rtx));
4447 #ifndef NO_PROFILE_COUNTERS
4449 rtx count_label_rtx, addr, r24;
4450 char count_label_name[16];
4452 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4453 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4455 addr = force_reg (Pmode, count_label_rtx);
4456 r24 = gen_rtx_REG (Pmode, 24);
4457 emit_move_insn (r24, addr);
4460 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4461 gen_rtx_SYMBOL_REF (Pmode,
4463 GEN_INT (TARGET_64BIT ? 24 : 12)));
4465 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4470 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4471 gen_rtx_SYMBOL_REF (Pmode,
4473 GEN_INT (TARGET_64BIT ? 16 : 8)));
4477 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4478 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4480 /* Indicate the _mcount call cannot throw, nor will it execute a
4482 REG_NOTES (call_insn)
4483 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4486 /* Fetch the return address for the frame COUNT steps up from
4487 the current frame, after the prologue. FRAMEADDR is the
4488 frame pointer of the COUNT frame.
4490 We want to ignore any export stub remnants here. To handle this,
4491 we examine the code at the return address, and if it is an export
4492 stub, we return a memory rtx for the stub return address stored
4495 The value returned is used in two different ways:
4497 1. To find a function's caller.
4499 2. To change the return address for a function.
4501 This function handles most instances of case 1; however, it will
4502 fail if there are two levels of stubs to execute on the return
4503 path. The only way I believe that can happen is if the return value
4504 needs a parameter relocation, which never happens for C code.
4506 This function handles most instances of case 2; however, it will
4507 fail if we did not originally have stub code on the return path
4508 but will need stub code on the new return path. This can happen if
4509 the caller & callee are both in the main program, but the new
4510 return location is in a shared library. */
4513 return_addr_rtx (int count, rtx frameaddr)
4523 rp = get_hard_reg_initial_val (Pmode, 2);
4525 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4528 saved_rp = gen_reg_rtx (Pmode);
4529 emit_move_insn (saved_rp, rp);
4531 /* Get pointer to the instruction stream. We have to mask out the
4532 privilege level from the two low order bits of the return address
4533 pointer here so that ins will point to the start of the first
4534 instruction that would have been executed if we returned. */
4535 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4536 label = gen_label_rtx ();
4538 /* Check the instruction stream at the normal return address for the
4541 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4542 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4543 0x00011820 | stub+16: mtsp r1,sr0
4544 0xe0400002 | stub+20: be,n 0(sr0,rp)
4546 If it is an export stub, than our return address is really in
4549 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4550 NULL_RTX, SImode, 1);
4551 emit_jump_insn (gen_bne (label));
4553 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4554 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4555 emit_jump_insn (gen_bne (label));
4557 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4558 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4559 emit_jump_insn (gen_bne (label));
4561 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4562 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4564 /* If there is no export stub then just use the value saved from
4565 the return pointer register. */
4567 emit_jump_insn (gen_bne (label));
4569 /* Here we know that our return address points to an export
4570 stub. We don't want to return the address of the export stub,
4571 but rather the return address of the export stub. That return
4572 address is stored at -24[frameaddr]. */
4574 emit_move_insn (saved_rp,
4576 memory_address (Pmode,
4577 plus_constant (frameaddr,
4584 /* This is only valid once reload has completed because it depends on
4585 knowing exactly how much (if any) frame there is and...
4587 It's only valid if there is no frame marker to de-allocate and...
4589 It's only valid if %r2 hasn't been saved into the caller's frame
4590 (we're not profiling and %r2 isn't live anywhere). */
4592 hppa_can_use_return_insn_p (void)
4594 return (reload_completed
4595 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4596 && ! regs_ever_live[2]
4597 && ! frame_pointer_needed);
4601 emit_bcond_fp (enum rtx_code code, rtx operand0)
4603 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4604 gen_rtx_IF_THEN_ELSE (VOIDmode,
4605 gen_rtx_fmt_ee (code,
4607 gen_rtx_REG (CCFPmode, 0),
4609 gen_rtx_LABEL_REF (VOIDmode, operand0),
4615 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4617 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4618 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4621 /* Adjust the cost of a scheduling dependency. Return the new cost of
4622 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4625 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4627 enum attr_type attr_type;
4629 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4630 true dependencies as they are described with bypasses now. */
4631 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4634 if (! recog_memoized (insn))
4637 attr_type = get_attr_type (insn);
4639 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4641 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4644 if (attr_type == TYPE_FPLOAD)
4646 rtx pat = PATTERN (insn);
4647 rtx dep_pat = PATTERN (dep_insn);
4648 if (GET_CODE (pat) == PARALLEL)
4650 /* This happens for the fldXs,mb patterns. */
4651 pat = XVECEXP (pat, 0, 0);
4653 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4654 /* If this happens, we have to extend this to schedule
4655 optimally. Return 0 for now. */
4658 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4660 if (! recog_memoized (dep_insn))
4662 switch (get_attr_type (dep_insn))
4669 case TYPE_FPSQRTSGL:
4670 case TYPE_FPSQRTDBL:
4671 /* A fpload can't be issued until one cycle before a
4672 preceding arithmetic operation has finished if
4673 the target of the fpload is any of the sources
4674 (or destination) of the arithmetic operation. */
4675 return insn_default_latency (dep_insn) - 1;
4682 else if (attr_type == TYPE_FPALU)
4684 rtx pat = PATTERN (insn);
4685 rtx dep_pat = PATTERN (dep_insn);
4686 if (GET_CODE (pat) == PARALLEL)
4688 /* This happens for the fldXs,mb patterns. */
4689 pat = XVECEXP (pat, 0, 0);
4691 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4692 /* If this happens, we have to extend this to schedule
4693 optimally. Return 0 for now. */
4696 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4698 if (! recog_memoized (dep_insn))
4700 switch (get_attr_type (dep_insn))
4704 case TYPE_FPSQRTSGL:
4705 case TYPE_FPSQRTDBL:
4706 /* An ALU flop can't be issued until two cycles before a
4707 preceding divide or sqrt operation has finished if
4708 the target of the ALU flop is any of the sources
4709 (or destination) of the divide or sqrt operation. */
4710 return insn_default_latency (dep_insn) - 2;
4718 /* For other anti dependencies, the cost is 0. */
4721 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4723 /* Output dependency; DEP_INSN writes a register that INSN writes some
4725 if (attr_type == TYPE_FPLOAD)
4727 rtx pat = PATTERN (insn);
4728 rtx dep_pat = PATTERN (dep_insn);
4729 if (GET_CODE (pat) == PARALLEL)
4731 /* This happens for the fldXs,mb patterns. */
4732 pat = XVECEXP (pat, 0, 0);
4734 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4735 /* If this happens, we have to extend this to schedule
4736 optimally. Return 0 for now. */
4739 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4741 if (! recog_memoized (dep_insn))
4743 switch (get_attr_type (dep_insn))
4750 case TYPE_FPSQRTSGL:
4751 case TYPE_FPSQRTDBL:
4752 /* A fpload can't be issued until one cycle before a
4753 preceding arithmetic operation has finished if
4754 the target of the fpload is the destination of the
4755 arithmetic operation.
4757 Exception: For PA7100LC, PA7200 and PA7300, the cost
4758 is 3 cycles, unless they bundle together. We also
4759 pay the penalty if the second insn is a fpload. */
4760 return insn_default_latency (dep_insn) - 1;
4767 else if (attr_type == TYPE_FPALU)
4769 rtx pat = PATTERN (insn);
4770 rtx dep_pat = PATTERN (dep_insn);
4771 if (GET_CODE (pat) == PARALLEL)
4773 /* This happens for the fldXs,mb patterns. */
4774 pat = XVECEXP (pat, 0, 0);
4776 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4777 /* If this happens, we have to extend this to schedule
4778 optimally. Return 0 for now. */
4781 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4783 if (! recog_memoized (dep_insn))
4785 switch (get_attr_type (dep_insn))
4789 case TYPE_FPSQRTSGL:
4790 case TYPE_FPSQRTDBL:
4791 /* An ALU flop can't be issued until two cycles before a
4792 preceding divide or sqrt operation has finished if
4793 the target of the ALU flop is also the target of
4794 the divide or sqrt operation. */
4795 return insn_default_latency (dep_insn) - 2;
4803 /* For other output dependencies, the cost is 0. */
4810 /* Adjust scheduling priorities. We use this to try and keep addil
4811 and the next use of %r1 close together. */
4813 pa_adjust_priority (rtx insn, int priority)
4815 rtx set = single_set (insn);
4819 src = SET_SRC (set);
4820 dest = SET_DEST (set);
4821 if (GET_CODE (src) == LO_SUM
4822 && symbolic_operand (XEXP (src, 1), VOIDmode)
4823 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4826 else if (GET_CODE (src) == MEM
4827 && GET_CODE (XEXP (src, 0)) == LO_SUM
4828 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4829 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4832 else if (GET_CODE (dest) == MEM
4833 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4834 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4835 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4841 /* The 700 can only issue a single insn at a time.
4842 The 7XXX processors can issue two insns at a time.
4843 The 8000 can issue 4 insns at a time. */
4845 pa_issue_rate (void)
4849 case PROCESSOR_700: return 1;
4850 case PROCESSOR_7100: return 2;
4851 case PROCESSOR_7100LC: return 2;
4852 case PROCESSOR_7200: return 2;
4853 case PROCESSOR_7300: return 2;
4854 case PROCESSOR_8000: return 4;
4863 /* Return any length adjustment needed by INSN which already has its length
4864 computed as LENGTH. Return zero if no adjustment is necessary.
4866 For the PA: function calls, millicode calls, and backwards short
4867 conditional branches with unfilled delay slots need an adjustment by +1
4868 (to account for the NOP which will be inserted into the instruction stream).
4870 Also compute the length of an inline block move here as it is too
4871 complicated to express as a length attribute in pa.md. */
4873 pa_adjust_insn_length (rtx insn, int length)
4875 rtx pat = PATTERN (insn);
4877 /* Jumps inside switch tables which have unfilled delay slots need
4879 if (GET_CODE (insn) == JUMP_INSN
4880 && GET_CODE (pat) == PARALLEL
4881 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4883 /* Millicode insn with an unfilled delay slot. */
4884 else if (GET_CODE (insn) == INSN
4885 && GET_CODE (pat) != SEQUENCE
4886 && GET_CODE (pat) != USE
4887 && GET_CODE (pat) != CLOBBER
4888 && get_attr_type (insn) == TYPE_MILLI)
4890 /* Block move pattern. */
4891 else if (GET_CODE (insn) == INSN
4892 && GET_CODE (pat) == PARALLEL
4893 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4894 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4895 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4896 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4897 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4898 return compute_movmem_length (insn) - 4;
4899 /* Block clear pattern. */
4900 else if (GET_CODE (insn) == INSN
4901 && GET_CODE (pat) == PARALLEL
4902 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4903 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4904 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4905 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4906 return compute_clrmem_length (insn) - 4;
4907 /* Conditional branch with an unfilled delay slot. */
4908 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4910 /* Adjust a short backwards conditional with an unfilled delay slot. */
4911 if (GET_CODE (pat) == SET
4913 && ! forward_branch_p (insn))
4915 else if (GET_CODE (pat) == PARALLEL
4916 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4919 /* Adjust dbra insn with short backwards conditional branch with
4920 unfilled delay slot -- only for case where counter is in a
4921 general register register. */
4922 else if (GET_CODE (pat) == PARALLEL
4923 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4924 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4925 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4927 && ! forward_branch_p (insn))
4935 /* Print operand X (an rtx) in assembler syntax to file FILE.
4936 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4937 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4940 print_operand (FILE *file, rtx x, int code)
4945 /* Output a 'nop' if there's nothing for the delay slot. */
4946 if (dbr_sequence_length () == 0)
4947 fputs ("\n\tnop", file);
4950 /* Output a nullification completer if there's nothing for the */
4951 /* delay slot or nullification is requested. */
4952 if (dbr_sequence_length () == 0 ||
4954 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4958 /* Print out the second register name of a register pair.
4959 I.e., R (6) => 7. */
4960 fputs (reg_names[REGNO (x) + 1], file);
4963 /* A register or zero. */
4965 || (x == CONST0_RTX (DFmode))
4966 || (x == CONST0_RTX (SFmode)))
4968 fputs ("%r0", file);
4974 /* A register or zero (floating point). */
4976 || (x == CONST0_RTX (DFmode))
4977 || (x == CONST0_RTX (SFmode)))
4979 fputs ("%fr0", file);
4988 xoperands[0] = XEXP (XEXP (x, 0), 0);
4989 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4990 output_global_address (file, xoperands[1], 0);
4991 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4995 case 'C': /* Plain (C)ondition */
4997 switch (GET_CODE (x))
5000 fputs ("=", file); break;
5002 fputs ("<>", file); break;
5004 fputs (">", file); break;
5006 fputs (">=", file); break;
5008 fputs (">>=", file); break;
5010 fputs (">>", file); break;
5012 fputs ("<", file); break;
5014 fputs ("<=", file); break;
5016 fputs ("<<=", file); break;
5018 fputs ("<<", file); break;
5023 case 'N': /* Condition, (N)egated */
5024 switch (GET_CODE (x))
5027 fputs ("<>", file); break;
5029 fputs ("=", file); break;
5031 fputs ("<=", file); break;
5033 fputs ("<", file); break;
5035 fputs ("<<", file); break;
5037 fputs ("<<=", file); break;
5039 fputs (">=", file); break;
5041 fputs (">", file); break;
5043 fputs (">>", file); break;
5045 fputs (">>=", file); break;
5050 /* For floating point comparisons. Note that the output
5051 predicates are the complement of the desired mode. */
5053 switch (GET_CODE (x))
5056 fputs ("!=", file); break;
5058 fputs ("=", file); break;
5060 fputs ("!>", file); break;
5062 fputs ("!>=", file); break;
5064 fputs ("!<", file); break;
5066 fputs ("!<=", file); break;
5068 fputs ("!<>", file); break;
5070 fputs (">", file); break;
5072 fputs (">=", file); break;
5074 fputs ("<", file); break;
5076 fputs ("<=", file); break;
5078 fputs ("<>", file); break;
5080 fputs ("<=>", file); break;
5082 fputs ("!<=>", file); break;
5087 case 'S': /* Condition, operands are (S)wapped. */
5088 switch (GET_CODE (x))
5091 fputs ("=", file); break;
5093 fputs ("<>", file); break;
5095 fputs ("<", file); break;
5097 fputs ("<=", file); break;
5099 fputs ("<<=", file); break;
5101 fputs ("<<", file); break;
5103 fputs (">", file); break;
5105 fputs (">=", file); break;
5107 fputs (">>=", file); break;
5109 fputs (">>", file); break;
5114 case 'B': /* Condition, (B)oth swapped and negate. */
5115 switch (GET_CODE (x))
5118 fputs ("<>", file); break;
5120 fputs ("=", file); break;
5122 fputs (">=", file); break;
5124 fputs (">", file); break;
5126 fputs (">>", file); break;
5128 fputs (">>=", file); break;
5130 fputs ("<=", file); break;
5132 fputs ("<", file); break;
5134 fputs ("<<", file); break;
5136 fputs ("<<=", file); break;
5142 if (GET_CODE (x) == CONST_INT)
5144 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5149 if (GET_CODE (x) == CONST_INT)
5151 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5156 if (GET_CODE (x) == CONST_INT)
5158 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5163 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5165 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5170 if (GET_CODE (x) == CONST_INT)
5172 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5177 if (GET_CODE (x) == CONST_INT)
5179 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5184 if (GET_CODE (x) == CONST_INT)
5189 switch (GET_CODE (XEXP (x, 0)))
5193 if (ASSEMBLER_DIALECT == 0)
5194 fputs ("s,mb", file);
5196 fputs (",mb", file);
5200 if (ASSEMBLER_DIALECT == 0)
5201 fputs ("s,ma", file);
5203 fputs (",ma", file);
5206 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5207 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5209 if (ASSEMBLER_DIALECT == 0)
5212 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5213 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5215 if (ASSEMBLER_DIALECT == 0)
5216 fputs ("x,s", file);
5220 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5224 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5230 output_global_address (file, x, 0);
5233 output_global_address (file, x, 1);
5235 case 0: /* Don't do anything special */
5240 compute_zdepwi_operands (INTVAL (x), op);
5241 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5247 compute_zdepdi_operands (INTVAL (x), op);
5248 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5252 /* We can get here from a .vtable_inherit due to our
5253 CONSTANT_ADDRESS_P rejecting perfectly good constant
5259 if (GET_CODE (x) == REG)
5261 fputs (reg_names [REGNO (x)], file);
5262 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5268 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5269 && (REGNO (x) & 1) == 0)
5272 else if (GET_CODE (x) == MEM)
5274 int size = GET_MODE_SIZE (GET_MODE (x));
5275 rtx base = NULL_RTX;
5276 switch (GET_CODE (XEXP (x, 0)))
5280 base = XEXP (XEXP (x, 0), 0);
5281 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5285 base = XEXP (XEXP (x, 0), 0);
5286 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5289 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5290 fprintf (file, "%s(%s)",
5291 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5292 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5293 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5294 fprintf (file, "%s(%s)",
5295 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5296 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5297 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5298 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5300 /* Because the REG_POINTER flag can get lost during reload,
5301 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5302 index and base registers in the combined move patterns. */
5303 rtx base = XEXP (XEXP (x, 0), 1);
5304 rtx index = XEXP (XEXP (x, 0), 0);
5306 fprintf (file, "%s(%s)",
5307 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5310 output_address (XEXP (x, 0));
5313 output_address (XEXP (x, 0));
5318 output_addr_const (file, x);
5321 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5324 output_global_address (FILE *file, rtx x, int round_constant)
5327 /* Imagine (high (const (plus ...))). */
5328 if (GET_CODE (x) == HIGH)
5331 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5332 assemble_name (file, XSTR (x, 0));
5333 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5335 assemble_name (file, XSTR (x, 0));
5336 fputs ("-$global$", file);
5338 else if (GET_CODE (x) == CONST)
5340 const char *sep = "";
5341 int offset = 0; /* assembler wants -$global$ at end */
5342 rtx base = NULL_RTX;
5344 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5346 base = XEXP (XEXP (x, 0), 0);
5347 output_addr_const (file, base);
5349 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5350 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5353 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5355 base = XEXP (XEXP (x, 0), 1);
5356 output_addr_const (file, base);
5358 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5359 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5362 /* How bogus. The compiler is apparently responsible for
5363 rounding the constant if it uses an LR field selector.
5365 The linker and/or assembler seem a better place since
5366 they have to do this kind of thing already.
5368 If we fail to do this, HP's optimizing linker may eliminate
5369 an addil, but not update the ldw/stw/ldo instruction that
5370 uses the result of the addil. */
5372 offset = ((offset + 0x1000) & ~0x1fff);
5374 if (GET_CODE (XEXP (x, 0)) == PLUS)
5384 else if (GET_CODE (XEXP (x, 0)) == MINUS
5385 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5389 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5390 fputs ("-$global$", file);
5392 fprintf (file, "%s%d", sep, offset);
5395 output_addr_const (file, x);
5398 /* Output boilerplate text to appear at the beginning of the file.
5399 There are several possible versions. */
5400 #define aputs(x) fputs(x, asm_out_file)
5402 pa_file_start_level (void)
5405 aputs ("\t.LEVEL 2.0w\n");
5406 else if (TARGET_PA_20)
5407 aputs ("\t.LEVEL 2.0\n");
5408 else if (TARGET_PA_11)
5409 aputs ("\t.LEVEL 1.1\n");
5411 aputs ("\t.LEVEL 1.0\n");
5415 pa_file_start_space (int sortspace)
5417 aputs ("\t.SPACE $PRIVATE$");
5420 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5421 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5422 "\n\t.SPACE $TEXT$");
5425 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5426 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5430 pa_file_start_file (int want_version)
5432 if (write_symbols != NO_DEBUG)
5434 output_file_directive (asm_out_file, main_input_filename);
5436 aputs ("\t.version\t\"01.01\"\n");
5441 pa_file_start_mcount (const char *aswhat)
5444 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5448 pa_elf_file_start (void)
5450 pa_file_start_level ();
5451 pa_file_start_mcount ("ENTRY");
5452 pa_file_start_file (0);
5456 pa_som_file_start (void)
5458 pa_file_start_level ();
5459 pa_file_start_space (0);
5460 aputs ("\t.IMPORT $global$,DATA\n"
5461 "\t.IMPORT $$dyncall,MILLICODE\n");
5462 pa_file_start_mcount ("CODE");
5463 pa_file_start_file (0);
5467 pa_linux_file_start (void)
5469 pa_file_start_file (1);
5470 pa_file_start_level ();
5471 pa_file_start_mcount ("CODE");
5475 pa_hpux64_gas_file_start (void)
5477 pa_file_start_level ();
5478 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5480 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5482 pa_file_start_file (1);
5486 pa_hpux64_hpas_file_start (void)
5488 pa_file_start_level ();
5489 pa_file_start_space (1);
5490 pa_file_start_mcount ("CODE");
5491 pa_file_start_file (0);
5495 static struct deferred_plabel *
5496 get_plabel (const char *fname)
5500 /* See if we have already put this function on the list of deferred
5501 plabels. This list is generally small, so a liner search is not
5502 too ugly. If it proves too slow replace it with something faster. */
5503 for (i = 0; i < n_deferred_plabels; i++)
5504 if (strcmp (fname, deferred_plabels[i].name) == 0)
5507 /* If the deferred plabel list is empty, or this entry was not found
5508 on the list, create a new entry on the list. */
5509 if (deferred_plabels == NULL || i == n_deferred_plabels)
5511 const char *real_name;
5513 if (deferred_plabels == 0)
5514 deferred_plabels = (struct deferred_plabel *)
5515 ggc_alloc (sizeof (struct deferred_plabel));
5517 deferred_plabels = (struct deferred_plabel *)
5518 ggc_realloc (deferred_plabels,
5519 ((n_deferred_plabels + 1)
5520 * sizeof (struct deferred_plabel)));
5522 i = n_deferred_plabels++;
5523 deferred_plabels[i].internal_label = gen_label_rtx ();
5524 deferred_plabels[i].name = ggc_strdup (fname);
5526 /* Gross. We have just implicitly taken the address of this function,
5528 real_name = (*targetm.strip_name_encoding) (fname);
5529 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5532 return &deferred_plabels[i];
5536 output_deferred_plabels (void)
5539 /* If we have deferred plabels, then we need to switch into the data
5540 section and align it to a 4 byte boundary before we output the
5541 deferred plabels. */
5542 if (n_deferred_plabels)
5545 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5548 /* Now output the deferred plabels. */
5549 for (i = 0; i < n_deferred_plabels; i++)
5551 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5552 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5553 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5554 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5558 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5559 /* Initialize optabs to point to HPUX long double emulation routines. */
5561 pa_hpux_init_libfuncs (void)
5563 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5564 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5565 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5566 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5567 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5568 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5569 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5570 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5571 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5573 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5574 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5575 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5576 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5577 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5578 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5579 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5581 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5582 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5583 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5584 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5586 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5587 ? "__U_Qfcnvfxt_quad_to_sgl"
5588 : "_U_Qfcnvfxt_quad_to_sgl");
5589 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5590 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5591 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5593 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5594 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5598 /* HP's millicode routines mean something special to the assembler.
5599 Keep track of which ones we have used. */
5601 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5602 static void import_milli (enum millicodes);
5603 static char imported[(int) end1000];
5604 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5605 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5606 #define MILLI_START 10
5609 import_milli (enum millicodes code)
5611 char str[sizeof (import_string)];
5613 if (!imported[(int) code])
5615 imported[(int) code] = 1;
5616 strcpy (str, import_string);
5617 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5618 output_asm_insn (str, 0);
5622 /* The register constraints have put the operands and return value in
5623 the proper registers. */
5626 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5628 import_milli (mulI);
5629 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5632 /* Emit the rtl for doing a division by a constant. */
5634 /* Do magic division millicodes exist for this value? */
5635 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5638 /* We'll use an array to keep track of the magic millicodes and
5639 whether or not we've used them already. [n][0] is signed, [n][1] is
5642 static int div_milli[16][2];
5645 div_operand (rtx op, enum machine_mode mode)
5647 return (mode == SImode
5648 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5649 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5650 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5654 emit_hpdiv_const (rtx *operands, int unsignedp)
5656 if (GET_CODE (operands[2]) == CONST_INT
5657 && INTVAL (operands[2]) > 0
5658 && INTVAL (operands[2]) < 16
5659 && magic_milli[INTVAL (operands[2])])
5661 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5663 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5667 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5668 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5670 gen_rtx_REG (SImode, 26),
5672 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5673 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5674 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5675 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5676 gen_rtx_CLOBBER (VOIDmode, ret))));
5677 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5684 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5688 /* If the divisor is a constant, try to use one of the special
5690 if (GET_CODE (operands[0]) == CONST_INT)
5692 static char buf[100];
5693 divisor = INTVAL (operands[0]);
5694 if (!div_milli[divisor][unsignedp])
5696 div_milli[divisor][unsignedp] = 1;
5698 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5700 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5704 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5705 INTVAL (operands[0]));
5706 return output_millicode_call (insn,
5707 gen_rtx_SYMBOL_REF (SImode, buf));
5711 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5712 INTVAL (operands[0]));
5713 return output_millicode_call (insn,
5714 gen_rtx_SYMBOL_REF (SImode, buf));
5717 /* Divisor isn't a special constant. */
5722 import_milli (divU);
5723 return output_millicode_call (insn,
5724 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5728 import_milli (divI);
5729 return output_millicode_call (insn,
5730 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5735 /* Output a $$rem millicode to do mod. */
5738 output_mod_insn (int unsignedp, rtx insn)
5742 import_milli (remU);
5743 return output_millicode_call (insn,
5744 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5748 import_milli (remI);
5749 return output_millicode_call (insn,
5750 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5755 output_arg_descriptor (rtx call_insn)
5757 const char *arg_regs[4];
5758 enum machine_mode arg_mode;
5760 int i, output_flag = 0;
5763 /* We neither need nor want argument location descriptors for the
5764 64bit runtime environment or the ELF32 environment. */
5765 if (TARGET_64BIT || TARGET_ELF32)
5768 for (i = 0; i < 4; i++)
5771 /* Specify explicitly that no argument relocations should take place
5772 if using the portable runtime calling conventions. */
5773 if (TARGET_PORTABLE_RUNTIME)
5775 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5780 if (GET_CODE (call_insn) != CALL_INSN)
5782 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5784 rtx use = XEXP (link, 0);
5786 if (! (GET_CODE (use) == USE
5787 && GET_CODE (XEXP (use, 0)) == REG
5788 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5791 arg_mode = GET_MODE (XEXP (use, 0));
5792 regno = REGNO (XEXP (use, 0));
5793 if (regno >= 23 && regno <= 26)
5795 arg_regs[26 - regno] = "GR";
5796 if (arg_mode == DImode)
5797 arg_regs[25 - regno] = "GR";
5799 else if (regno >= 32 && regno <= 39)
5801 if (arg_mode == SFmode)
5802 arg_regs[(regno - 32) / 2] = "FR";
5805 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5806 arg_regs[(regno - 34) / 2] = "FR";
5807 arg_regs[(regno - 34) / 2 + 1] = "FU";
5809 arg_regs[(regno - 34) / 2] = "FU";
5810 arg_regs[(regno - 34) / 2 + 1] = "FR";
5815 fputs ("\t.CALL ", asm_out_file);
5816 for (i = 0; i < 4; i++)
5821 fputc (',', asm_out_file);
5822 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5825 fputc ('\n', asm_out_file);
5828 /* Return the class of any secondary reload register that is needed to
5829 move IN into a register in class CLASS using mode MODE.
5831 Profiling has showed this routine and its descendants account for
5832 a significant amount of compile time (~7%). So it has been
5833 optimized to reduce redundant computations and eliminate useless
5836 It might be worthwhile to try and make this a leaf function too. */
5839 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5841 int regno, is_symbolic;
5843 /* Trying to load a constant into a FP register during PIC code
5844 generation will require %r1 as a scratch register. */
5846 && GET_MODE_CLASS (mode) == MODE_INT
5847 && FP_REG_CLASS_P (class)
5848 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5851 /* Profiling showed the PA port spends about 1.3% of its compilation
5852 time in true_regnum from calls inside secondary_reload_class. */
5854 if (GET_CODE (in) == REG)
5857 if (regno >= FIRST_PSEUDO_REGISTER)
5858 regno = true_regnum (in);
5860 else if (GET_CODE (in) == SUBREG)
5861 regno = true_regnum (in);
5865 /* If we have something like (mem (mem (...)), we can safely assume the
5866 inner MEM will end up in a general register after reloading, so there's
5867 no need for a secondary reload. */
5868 if (GET_CODE (in) == MEM
5869 && GET_CODE (XEXP (in, 0)) == MEM)
5872 /* Handle out of range displacement for integer mode loads/stores of
5874 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5875 && GET_MODE_CLASS (mode) == MODE_INT
5876 && FP_REG_CLASS_P (class))
5877 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5878 return GENERAL_REGS;
5880 /* A SAR<->FP register copy requires a secondary register (GPR) as
5881 well as secondary memory. */
5882 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5883 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5884 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5885 return GENERAL_REGS;
5887 if (GET_CODE (in) == HIGH)
5890 /* Profiling has showed GCC spends about 2.6% of its compilation
5891 time in symbolic_operand from calls inside secondary_reload_class.
5893 We use an inline copy and only compute its return value once to avoid
5895 switch (GET_CODE (in))
5905 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5906 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5907 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5917 && read_only_operand (in, VOIDmode))
5920 if (class != R1_REGS && is_symbolic)
5926 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5927 by invisible reference. As a GCC extension, we also pass anything
5928 with a zero or variable size by reference.
5930 The 64-bit runtime does not describe passing any types by invisible
5931 reference. The internals of GCC can't currently handle passing
5932 empty structures, and zero or variable length arrays when they are
5933 not passed entirely on the stack or by reference. Thus, as a GCC
5934 extension, we pass these types by reference. The HP compiler doesn't
5935 support these types, so hopefully there shouldn't be any compatibility
5936 issues. This may have to be revisited when HP releases a C99 compiler
5937 or updates the ABI. */
5940 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5941 enum machine_mode mode, tree type,
5942 bool named ATTRIBUTE_UNUSED)
5947 size = int_size_in_bytes (type);
5949 size = GET_MODE_SIZE (mode);
5954 return size <= 0 || size > 8;
5958 function_arg_padding (enum machine_mode mode, tree type)
5961 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5963 /* Return none if justification is not required. */
5965 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5966 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5969 /* The directions set here are ignored when a BLKmode argument larger
5970 than a word is placed in a register. Different code is used for
5971 the stack and registers. This makes it difficult to have a
5972 consistent data representation for both the stack and registers.
5973 For both runtimes, the justification and padding for arguments on
5974 the stack and in registers should be identical. */
5976 /* The 64-bit runtime specifies left justification for aggregates. */
5979 /* The 32-bit runtime architecture specifies right justification.
5980 When the argument is passed on the stack, the argument is padded
5981 with garbage on the left. The HP compiler pads with zeros. */
5985 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5992 /* Do what is necessary for `va_start'. We look at the current function
5993 to determine if stdargs or varargs is used and fill in an initial
5994 va_list. A pointer to this constructor is returned. */
5997 hppa_builtin_saveregs (void)
6000 tree fntype = TREE_TYPE (current_function_decl);
6001 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
6002 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6003 != void_type_node)))
6004 ? UNITS_PER_WORD : 0);
6007 offset = plus_constant (current_function_arg_offset_rtx, argadj);
6009 offset = current_function_arg_offset_rtx;
6015 /* Adjust for varargs/stdarg differences. */
6017 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
6019 offset = current_function_arg_offset_rtx;
6021 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6022 from the incoming arg pointer and growing to larger addresses. */
6023 for (i = 26, off = -64; i >= 19; i--, off += 8)
6024 emit_move_insn (gen_rtx_MEM (word_mode,
6025 plus_constant (arg_pointer_rtx, off)),
6026 gen_rtx_REG (word_mode, i));
6028 /* The incoming args pointer points just beyond the flushback area;
6029 normally this is not a serious concern. However, when we are doing
6030 varargs/stdargs we want to make the arg pointer point to the start
6031 of the incoming argument area. */
6032 emit_move_insn (virtual_incoming_args_rtx,
6033 plus_constant (arg_pointer_rtx, -64));
6035 /* Now return a pointer to the first anonymous argument. */
6036 return copy_to_reg (expand_binop (Pmode, add_optab,
6037 virtual_incoming_args_rtx,
6038 offset, 0, 0, OPTAB_LIB_WIDEN));
6041 /* Store general registers on the stack. */
6042 dest = gen_rtx_MEM (BLKmode,
6043 plus_constant (current_function_internal_arg_pointer,
6045 set_mem_alias_set (dest, get_varargs_alias_set ());
6046 set_mem_align (dest, BITS_PER_WORD);
6047 move_block_from_reg (23, dest, 4);
6049 /* move_block_from_reg will emit code to store the argument registers
6050 individually as scalar stores.
6052 However, other insns may later load from the same addresses for
6053 a structure load (passing a struct to a varargs routine).
6055 The alias code assumes that such aliasing can never happen, so we
6056 have to keep memory referencing insns from moving up beyond the
6057 last argument register store. So we emit a blockage insn here. */
6058 emit_insn (gen_blockage ());
6060 return copy_to_reg (expand_binop (Pmode, add_optab,
6061 current_function_internal_arg_pointer,
6062 offset, 0, 0, OPTAB_LIB_WIDEN));
6066 hppa_va_start (tree valist, rtx nextarg)
6068 nextarg = expand_builtin_saveregs ();
6069 std_expand_builtin_va_start (valist, nextarg);
6073 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
6077 /* Args grow upward. We can use the generic routines. */
6078 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6080 else /* !TARGET_64BIT */
6082 tree ptr = build_pointer_type (type);
6085 unsigned int size, ofs;
6088 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6092 ptr = build_pointer_type (type);
6094 size = int_size_in_bytes (type);
6095 valist_type = TREE_TYPE (valist);
6097 /* Args grow down. Not handled by generic routines. */
6099 u = fold_convert (valist_type, size_in_bytes (type));
6100 t = build (MINUS_EXPR, valist_type, valist, u);
6102 /* Copied from va-pa.h, but we probably don't need to align to
6103 word size, since we generate and preserve that invariant. */
6104 u = build_int_2 ((size > 4 ? -8 : -4), -1);
6105 u = fold_convert (valist_type, u);
6106 t = build (BIT_AND_EXPR, valist_type, t, u);
6108 t = build (MODIFY_EXPR, valist_type, valist, t);
6110 ofs = (8 - size) % 4;
6113 u = fold_convert (valist_type, size_int (ofs));
6114 t = build (PLUS_EXPR, valist_type, t, u);
6117 t = fold_convert (ptr, t);
6118 t = build_fold_indirect_ref (t);
6121 t = build_fold_indirect_ref (t);
6127 /* This routine handles all the normal conditional branch sequences we
6128 might need to generate. It handles compare immediate vs compare
6129 register, nullification of delay slots, varying length branches,
6130 negated branches, and all combinations of the above. It returns the
6131 output appropriate to emit the branch corresponding to all given
6135 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6137 static char buf[100];
6141 /* A conditional branch to the following instruction (eg the delay slot)
6142 is asking for a disaster. This can happen when not optimizing and
6143 when jump optimization fails.
6145 While it is usually safe to emit nothing, this can fail if the
6146 preceding instruction is a nullified branch with an empty delay
6147 slot and the same branch target as this branch. We could check
6148 for this but jump optimization should eliminate nop jumps. It
6149 is always safe to emit a nop. */
6150 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6153 /* The doubleword form of the cmpib instruction doesn't have the LEU
6154 and GTU conditions while the cmpb instruction does. Since we accept
6155 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6156 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6157 operands[2] = gen_rtx_REG (DImode, 0);
6159 /* If this is a long branch with its delay slot unfilled, set `nullify'
6160 as it can nullify the delay slot and save a nop. */
6161 if (length == 8 && dbr_sequence_length () == 0)
6164 /* If this is a short forward conditional branch which did not get
6165 its delay slot filled, the delay slot can still be nullified. */
6166 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6167 nullify = forward_branch_p (insn);
6169 /* A forward branch over a single nullified insn can be done with a
6170 comclr instruction. This avoids a single cycle penalty due to
6171 mis-predicted branch if we fall through (branch not taken). */
6173 && next_real_insn (insn) != 0
6174 && get_attr_length (next_real_insn (insn)) == 4
6175 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6181 /* All short conditional branches except backwards with an unfilled
6185 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6187 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6188 if (GET_MODE (operands[1]) == DImode)
6191 strcat (buf, "%B3");
6193 strcat (buf, "%S3");
6195 strcat (buf, " %2,%r1,%%r0");
6197 strcat (buf, ",n %2,%r1,%0");
6199 strcat (buf, " %2,%r1,%0");
6202 /* All long conditionals. Note a short backward branch with an
6203 unfilled delay slot is treated just like a long backward branch
6204 with an unfilled delay slot. */
6206 /* Handle weird backwards branch with a filled delay slot
6207 with is nullified. */
6208 if (dbr_sequence_length () != 0
6209 && ! forward_branch_p (insn)
6212 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6213 if (GET_MODE (operands[1]) == DImode)
6216 strcat (buf, "%S3");
6218 strcat (buf, "%B3");
6219 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6221 /* Handle short backwards branch with an unfilled delay slot.
6222 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6223 taken and untaken branches. */
6224 else if (dbr_sequence_length () == 0
6225 && ! forward_branch_p (insn)
6226 && INSN_ADDRESSES_SET_P ()
6227 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6228 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6230 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6231 if (GET_MODE (operands[1]) == DImode)
6234 strcat (buf, "%B3 %2,%r1,%0%#");
6236 strcat (buf, "%S3 %2,%r1,%0%#");
6240 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6241 if (GET_MODE (operands[1]) == DImode)
6244 strcat (buf, "%S3");
6246 strcat (buf, "%B3");
6248 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6250 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6256 xoperands[0] = operands[0];
6257 xoperands[1] = operands[1];
6258 xoperands[2] = operands[2];
6259 xoperands[3] = operands[3];
6261 /* The reversed conditional branch must branch over one additional
6262 instruction if the delay slot is filled. If the delay slot
6263 is empty, the instruction after the reversed condition branch
6264 must be nullified. */
6265 nullify = dbr_sequence_length () == 0;
6266 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6268 /* Create a reversed conditional branch which branches around
6269 the following insns. */
6270 if (GET_MODE (operands[1]) != DImode)
6276 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6279 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6285 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6288 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6297 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6300 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6306 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6309 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6313 output_asm_insn (buf, xoperands);
6314 return output_lbranch (operands[0], insn);
6322 /* This routine handles long unconditional branches that exceed the
6323 maximum range of a simple branch instruction. */
6326 output_lbranch (rtx dest, rtx insn)
6330 xoperands[0] = dest;
6332 /* First, free up the delay slot. */
6333 if (dbr_sequence_length () != 0)
6335 /* We can't handle a jump in the delay slot. */
6336 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6339 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6340 optimize, 0, 0, NULL);
6342 /* Now delete the delay insn. */
6343 PUT_CODE (NEXT_INSN (insn), NOTE);
6344 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6345 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6348 /* Output an insn to save %r1. The runtime documentation doesn't
6349 specify whether the "Clean Up" slot in the callers frame can
6350 be clobbered by the callee. It isn't copied by HP's builtin
6351 alloca, so this suggests that it can be clobbered if necessary.
6352 The "Static Link" location is copied by HP builtin alloca, so
6353 we avoid using it. Using the cleanup slot might be a problem
6354 if we have to interoperate with languages that pass cleanup
6355 information. However, it should be possible to handle these
6356 situations with GCC's asm feature.
6358 The "Current RP" slot is reserved for the called procedure, so
6359 we try to use it when we don't have a frame of our own. It's
6360 rather unlikely that we won't have a frame when we need to emit
6363 Really the way to go long term is a register scavenger; goto
6364 the target of the jump and find a register which we can use
6365 as a scratch to hold the value in %r1. Then, we wouldn't have
6366 to free up the delay slot or clobber a slot that may be needed
6367 for other purposes. */
6370 if (actual_fsize == 0 && !regs_ever_live[2])
6371 /* Use the return pointer slot in the frame marker. */
6372 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6374 /* Use the slot at -40 in the frame marker since HP builtin
6375 alloca doesn't copy it. */
6376 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6380 if (actual_fsize == 0 && !regs_ever_live[2])
6381 /* Use the return pointer slot in the frame marker. */
6382 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6384 /* Use the "Clean Up" slot in the frame marker. In GCC,
6385 the only other use of this location is for copying a
6386 floating point double argument from a floating-point
6387 register to two general registers. The copy is done
6388 as an "atomic" operation when outputting a call, so it
6389 won't interfere with our using the location here. */
6390 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6393 if (TARGET_PORTABLE_RUNTIME)
6395 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6396 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6397 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6401 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6402 if (TARGET_SOM || !TARGET_GAS)
6404 xoperands[1] = gen_label_rtx ();
6405 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6406 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6407 CODE_LABEL_NUMBER (xoperands[1]));
6408 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6412 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6413 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6415 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6418 /* Now output a very long branch to the original target. */
6419 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6421 /* Now restore the value of %r1 in the delay slot. */
6424 if (actual_fsize == 0 && !regs_ever_live[2])
6425 return "ldd -16(%%r30),%%r1";
6427 return "ldd -40(%%r30),%%r1";
6431 if (actual_fsize == 0 && !regs_ever_live[2])
6432 return "ldw -20(%%r30),%%r1";
6434 return "ldw -12(%%r30),%%r1";
6438 /* This routine handles all the branch-on-bit conditional branch sequences we
6439 might need to generate. It handles nullification of delay slots,
6440 varying length branches, negated branches and all combinations of the
6441 above. it returns the appropriate output template to emit the branch. */
6444 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6445 int negated, rtx insn, int which)
6447 static char buf[100];
6450 /* A conditional branch to the following instruction (eg the delay slot) is
6451 asking for a disaster. I do not think this can happen as this pattern
6452 is only used when optimizing; jump optimization should eliminate the
6453 jump. But be prepared just in case. */
6455 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6458 /* If this is a long branch with its delay slot unfilled, set `nullify'
6459 as it can nullify the delay slot and save a nop. */
6460 if (length == 8 && dbr_sequence_length () == 0)
6463 /* If this is a short forward conditional branch which did not get
6464 its delay slot filled, the delay slot can still be nullified. */
6465 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6466 nullify = forward_branch_p (insn);
6468 /* A forward branch over a single nullified insn can be done with a
6469 extrs instruction. This avoids a single cycle penalty due to
6470 mis-predicted branch if we fall through (branch not taken). */
6473 && next_real_insn (insn) != 0
6474 && get_attr_length (next_real_insn (insn)) == 4
6475 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6482 /* All short conditional branches except backwards with an unfilled
6486 strcpy (buf, "{extrs,|extrw,s,}");
6488 strcpy (buf, "bb,");
6489 if (useskip && GET_MODE (operands[0]) == DImode)
6490 strcpy (buf, "extrd,s,*");
6491 else if (GET_MODE (operands[0]) == DImode)
6492 strcpy (buf, "bb,*");
6493 if ((which == 0 && negated)
6494 || (which == 1 && ! negated))
6499 strcat (buf, " %0,%1,1,%%r0");
6500 else if (nullify && negated)
6501 strcat (buf, ",n %0,%1,%3");
6502 else if (nullify && ! negated)
6503 strcat (buf, ",n %0,%1,%2");
6504 else if (! nullify && negated)
6505 strcat (buf, "%0,%1,%3");
6506 else if (! nullify && ! negated)
6507 strcat (buf, " %0,%1,%2");
6510 /* All long conditionals. Note a short backward branch with an
6511 unfilled delay slot is treated just like a long backward branch
6512 with an unfilled delay slot. */
6514 /* Handle weird backwards branch with a filled delay slot
6515 with is nullified. */
6516 if (dbr_sequence_length () != 0
6517 && ! forward_branch_p (insn)
6520 strcpy (buf, "bb,");
6521 if (GET_MODE (operands[0]) == DImode)
6523 if ((which == 0 && negated)
6524 || (which == 1 && ! negated))
6529 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6531 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6533 /* Handle short backwards branch with an unfilled delay slot.
6534 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6535 taken and untaken branches. */
6536 else if (dbr_sequence_length () == 0
6537 && ! forward_branch_p (insn)
6538 && INSN_ADDRESSES_SET_P ()
6539 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6540 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6542 strcpy (buf, "bb,");
6543 if (GET_MODE (operands[0]) == DImode)
6545 if ((which == 0 && negated)
6546 || (which == 1 && ! negated))
6551 strcat (buf, " %0,%1,%3%#");
6553 strcat (buf, " %0,%1,%2%#");
6557 strcpy (buf, "{extrs,|extrw,s,}");
6558 if (GET_MODE (operands[0]) == DImode)
6559 strcpy (buf, "extrd,s,*");
6560 if ((which == 0 && negated)
6561 || (which == 1 && ! negated))
6565 if (nullify && negated)
6566 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6567 else if (nullify && ! negated)
6568 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6570 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6572 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6582 /* This routine handles all the branch-on-variable-bit conditional branch
6583 sequences we might need to generate. It handles nullification of delay
6584 slots, varying length branches, negated branches and all combinations
6585 of the above. it returns the appropriate output template to emit the
6589 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6590 int negated, rtx insn, int which)
6592 static char buf[100];
6595 /* A conditional branch to the following instruction (eg the delay slot) is
6596 asking for a disaster. I do not think this can happen as this pattern
6597 is only used when optimizing; jump optimization should eliminate the
6598 jump. But be prepared just in case. */
6600 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6603 /* If this is a long branch with its delay slot unfilled, set `nullify'
6604 as it can nullify the delay slot and save a nop. */
6605 if (length == 8 && dbr_sequence_length () == 0)
6608 /* If this is a short forward conditional branch which did not get
6609 its delay slot filled, the delay slot can still be nullified. */
6610 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6611 nullify = forward_branch_p (insn);
6613 /* A forward branch over a single nullified insn can be done with a
6614 extrs instruction. This avoids a single cycle penalty due to
6615 mis-predicted branch if we fall through (branch not taken). */
6618 && next_real_insn (insn) != 0
6619 && get_attr_length (next_real_insn (insn)) == 4
6620 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6627 /* All short conditional branches except backwards with an unfilled
6631 strcpy (buf, "{vextrs,|extrw,s,}");
6633 strcpy (buf, "{bvb,|bb,}");
6634 if (useskip && GET_MODE (operands[0]) == DImode)
6635 strcpy (buf, "extrd,s,*");
6636 else if (GET_MODE (operands[0]) == DImode)
6637 strcpy (buf, "bb,*");
6638 if ((which == 0 && negated)
6639 || (which == 1 && ! negated))
6644 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6645 else if (nullify && negated)
6646 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6647 else if (nullify && ! negated)
6648 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6649 else if (! nullify && negated)
6650 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6651 else if (! nullify && ! negated)
6652 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6655 /* All long conditionals. Note a short backward branch with an
6656 unfilled delay slot is treated just like a long backward branch
6657 with an unfilled delay slot. */
6659 /* Handle weird backwards branch with a filled delay slot
6660 with is nullified. */
6661 if (dbr_sequence_length () != 0
6662 && ! forward_branch_p (insn)
6665 strcpy (buf, "{bvb,|bb,}");
6666 if (GET_MODE (operands[0]) == DImode)
6668 if ((which == 0 && negated)
6669 || (which == 1 && ! negated))
6674 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6676 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6678 /* Handle short backwards branch with an unfilled delay slot.
6679 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6680 taken and untaken branches. */
6681 else if (dbr_sequence_length () == 0
6682 && ! forward_branch_p (insn)
6683 && INSN_ADDRESSES_SET_P ()
6684 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6685 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6687 strcpy (buf, "{bvb,|bb,}");
6688 if (GET_MODE (operands[0]) == DImode)
6690 if ((which == 0 && negated)
6691 || (which == 1 && ! negated))
6696 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6698 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6702 strcpy (buf, "{vextrs,|extrw,s,}");
6703 if (GET_MODE (operands[0]) == DImode)
6704 strcpy (buf, "extrd,s,*");
6705 if ((which == 0 && negated)
6706 || (which == 1 && ! negated))
6710 if (nullify && negated)
6711 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6712 else if (nullify && ! negated)
6713 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6715 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6717 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6727 /* Return the output template for emitting a dbra type insn.
6729 Note it may perform some output operations on its own before
6730 returning the final output string. */
6732 output_dbra (rtx *operands, rtx insn, int which_alternative)
6735 /* A conditional branch to the following instruction (eg the delay slot) is
6736 asking for a disaster. Be prepared! */
6738 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6740 if (which_alternative == 0)
6741 return "ldo %1(%0),%0";
6742 else if (which_alternative == 1)
6744 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6745 output_asm_insn ("ldw -16(%%r30),%4", operands);
6746 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6747 return "{fldws|fldw} -16(%%r30),%0";
6751 output_asm_insn ("ldw %0,%4", operands);
6752 return "ldo %1(%4),%4\n\tstw %4,%0";
6756 if (which_alternative == 0)
6758 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6759 int length = get_attr_length (insn);
6761 /* If this is a long branch with its delay slot unfilled, set `nullify'
6762 as it can nullify the delay slot and save a nop. */
6763 if (length == 8 && dbr_sequence_length () == 0)
6766 /* If this is a short forward conditional branch which did not get
6767 its delay slot filled, the delay slot can still be nullified. */
6768 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6769 nullify = forward_branch_p (insn);
6771 /* Handle short versions first. */
6772 if (length == 4 && nullify)
6773 return "addib,%C2,n %1,%0,%3";
6774 else if (length == 4 && ! nullify)
6775 return "addib,%C2 %1,%0,%3";
6776 else if (length == 8)
6778 /* Handle weird backwards branch with a fulled delay slot
6779 which is nullified. */
6780 if (dbr_sequence_length () != 0
6781 && ! forward_branch_p (insn)
6783 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6784 /* Handle short backwards branch with an unfilled delay slot.
6785 Using a addb;nop rather than addi;bl saves 1 cycle for both
6786 taken and untaken branches. */
6787 else if (dbr_sequence_length () == 0
6788 && ! forward_branch_p (insn)
6789 && INSN_ADDRESSES_SET_P ()
6790 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6791 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6792 return "addib,%C2 %1,%0,%3%#";
6794 /* Handle normal cases. */
6796 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6798 return "addi,%N2 %1,%0,%0\n\tb %3";
6803 /* Deal with gross reload from FP register case. */
6804 else if (which_alternative == 1)
6806 /* Move loop counter from FP register to MEM then into a GR,
6807 increment the GR, store the GR into MEM, and finally reload
6808 the FP register from MEM from within the branch's delay slot. */
6809 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6811 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6812 if (get_attr_length (insn) == 24)
6813 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6815 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6817 /* Deal with gross reload from memory case. */
6820 /* Reload loop counter from memory, the store back to memory
6821 happens in the branch's delay slot. */
6822 output_asm_insn ("ldw %0,%4", operands);
6823 if (get_attr_length (insn) == 12)
6824 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6826 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6830 /* Return the output template for emitting a dbra type insn.
6832 Note it may perform some output operations on its own before
6833 returning the final output string. */
6835 output_movb (rtx *operands, rtx insn, int which_alternative,
6836 int reverse_comparison)
6839 /* A conditional branch to the following instruction (eg the delay slot) is
6840 asking for a disaster. Be prepared! */
6842 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6844 if (which_alternative == 0)
6845 return "copy %1,%0";
6846 else if (which_alternative == 1)
6848 output_asm_insn ("stw %1,-16(%%r30)", operands);
6849 return "{fldws|fldw} -16(%%r30),%0";
6851 else if (which_alternative == 2)
6857 /* Support the second variant. */
6858 if (reverse_comparison)
6859 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6861 if (which_alternative == 0)
6863 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6864 int length = get_attr_length (insn);
6866 /* If this is a long branch with its delay slot unfilled, set `nullify'
6867 as it can nullify the delay slot and save a nop. */
6868 if (length == 8 && dbr_sequence_length () == 0)
6871 /* If this is a short forward conditional branch which did not get
6872 its delay slot filled, the delay slot can still be nullified. */
6873 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6874 nullify = forward_branch_p (insn);
6876 /* Handle short versions first. */
6877 if (length == 4 && nullify)
6878 return "movb,%C2,n %1,%0,%3";
6879 else if (length == 4 && ! nullify)
6880 return "movb,%C2 %1,%0,%3";
6881 else if (length == 8)
6883 /* Handle weird backwards branch with a filled delay slot
6884 which is nullified. */
6885 if (dbr_sequence_length () != 0
6886 && ! forward_branch_p (insn)
6888 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6890 /* Handle short backwards branch with an unfilled delay slot.
6891 Using a movb;nop rather than or;bl saves 1 cycle for both
6892 taken and untaken branches. */
6893 else if (dbr_sequence_length () == 0
6894 && ! forward_branch_p (insn)
6895 && INSN_ADDRESSES_SET_P ()
6896 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6897 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6898 return "movb,%C2 %1,%0,%3%#";
6899 /* Handle normal cases. */
6901 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6903 return "or,%N2 %1,%%r0,%0\n\tb %3";
6908 /* Deal with gross reload from FP register case. */
6909 else if (which_alternative == 1)
6911 /* Move loop counter from FP register to MEM then into a GR,
6912 increment the GR, store the GR into MEM, and finally reload
6913 the FP register from MEM from within the branch's delay slot. */
6914 output_asm_insn ("stw %1,-16(%%r30)", operands);
6915 if (get_attr_length (insn) == 12)
6916 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6918 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6920 /* Deal with gross reload from memory case. */
6921 else if (which_alternative == 2)
6923 /* Reload loop counter from memory, the store back to memory
6924 happens in the branch's delay slot. */
6925 if (get_attr_length (insn) == 8)
6926 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6928 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6930 /* Handle SAR as a destination. */
6933 if (get_attr_length (insn) == 8)
6934 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6936 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6940 /* Copy any FP arguments in INSN into integer registers. */
6942 copy_fp_args (rtx insn)
6947 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6949 int arg_mode, regno;
6950 rtx use = XEXP (link, 0);
6952 if (! (GET_CODE (use) == USE
6953 && GET_CODE (XEXP (use, 0)) == REG
6954 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6957 arg_mode = GET_MODE (XEXP (use, 0));
6958 regno = REGNO (XEXP (use, 0));
6960 /* Is it a floating point register? */
6961 if (regno >= 32 && regno <= 39)
6963 /* Copy the FP register into an integer register via memory. */
6964 if (arg_mode == SFmode)
6966 xoperands[0] = XEXP (use, 0);
6967 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6968 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6969 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6973 xoperands[0] = XEXP (use, 0);
6974 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6975 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6976 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6977 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6983 /* Compute length of the FP argument copy sequence for INSN. */
6985 length_fp_args (rtx insn)
6990 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6992 int arg_mode, regno;
6993 rtx use = XEXP (link, 0);
6995 if (! (GET_CODE (use) == USE
6996 && GET_CODE (XEXP (use, 0)) == REG
6997 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7000 arg_mode = GET_MODE (XEXP (use, 0));
7001 regno = REGNO (XEXP (use, 0));
7003 /* Is it a floating point register? */
7004 if (regno >= 32 && regno <= 39)
7006 if (arg_mode == SFmode)
7016 /* Return the attribute length for the millicode call instruction INSN.
7017 The length must match the code generated by output_millicode_call.
7018 We include the delay slot in the returned length as it is better to
7019 over estimate the length than to under estimate it. */
7022 attr_length_millicode_call (rtx insn)
7024 unsigned long distance = -1;
7025 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7027 if (INSN_ADDRESSES_SET_P ())
7029 distance = (total + insn_current_reference_address (insn));
7030 if (distance < total)
7036 if (!TARGET_LONG_CALLS && distance < 7600000)
7041 else if (TARGET_PORTABLE_RUNTIME)
7045 if (!TARGET_LONG_CALLS && distance < 240000)
7048 if (TARGET_LONG_ABS_CALL && !flag_pic)
7055 /* INSN is a function call. It may have an unconditional jump
7058 CALL_DEST is the routine we are calling. */
7061 output_millicode_call (rtx insn, rtx call_dest)
7063 int attr_length = get_attr_length (insn);
7064 int seq_length = dbr_sequence_length ();
7069 xoperands[0] = call_dest;
7070 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7072 /* Handle the common case where we are sure that the branch will
7073 reach the beginning of the $CODE$ subspace. The within reach
7074 form of the $$sh_func_adrs call has a length of 28. Because
7075 it has an attribute type of multi, it never has a nonzero
7076 sequence length. The length of the $$sh_func_adrs is the same
7077 as certain out of reach PIC calls to other routines. */
7078 if (!TARGET_LONG_CALLS
7079 && ((seq_length == 0
7080 && (attr_length == 12
7081 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7082 || (seq_length != 0 && attr_length == 8)))
7084 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7090 /* It might seem that one insn could be saved by accessing
7091 the millicode function using the linkage table. However,
7092 this doesn't work in shared libraries and other dynamically
7093 loaded objects. Using a pc-relative sequence also avoids
7094 problems related to the implicit use of the gp register. */
7095 output_asm_insn ("b,l .+8,%%r1", xoperands);
7099 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7100 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7104 xoperands[1] = gen_label_rtx ();
7105 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7106 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7107 CODE_LABEL_NUMBER (xoperands[1]));
7108 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7111 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7113 else if (TARGET_PORTABLE_RUNTIME)
7115 /* Pure portable runtime doesn't allow be/ble; we also don't
7116 have PIC support in the assembler/linker, so this sequence
7119 /* Get the address of our target into %r1. */
7120 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7121 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7123 /* Get our return address into %r31. */
7124 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7125 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7127 /* Jump to our target address in %r1. */
7128 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7132 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7134 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7136 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7140 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7141 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7143 if (TARGET_SOM || !TARGET_GAS)
7145 /* The HP assembler can generate relocations for the
7146 difference of two symbols. GAS can do this for a
7147 millicode symbol but not an arbitrary external
7148 symbol when generating SOM output. */
7149 xoperands[1] = gen_label_rtx ();
7150 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7151 CODE_LABEL_NUMBER (xoperands[1]));
7152 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7153 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7157 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7158 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7162 /* Jump to our target address in %r1. */
7163 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7167 if (seq_length == 0)
7168 output_asm_insn ("nop", xoperands);
7170 /* We are done if there isn't a jump in the delay slot. */
7171 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7174 /* This call has an unconditional jump in its delay slot. */
7175 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7177 /* See if the return address can be adjusted. Use the containing
7178 sequence insn's address. */
7179 if (INSN_ADDRESSES_SET_P ())
7181 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7182 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7183 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7185 if (VAL_14_BITS_P (distance))
7187 xoperands[1] = gen_label_rtx ();
7188 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7189 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7190 CODE_LABEL_NUMBER (xoperands[1]));
7193 /* ??? This branch may not reach its target. */
7194 output_asm_insn ("nop\n\tb,n %0", xoperands);
7197 /* ??? This branch may not reach its target. */
7198 output_asm_insn ("nop\n\tb,n %0", xoperands);
7200 /* Delete the jump. */
7201 PUT_CODE (NEXT_INSN (insn), NOTE);
7202 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7203 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7208 /* Return the attribute length of the call instruction INSN. The SIBCALL
7209 flag indicates whether INSN is a regular call or a sibling call. The
7210 length returned must be longer than the code actually generated by
7211 output_call. Since branch shortening is done before delay branch
7212 sequencing, there is no way to determine whether or not the delay
7213 slot will be filled during branch shortening. Even when the delay
7214 slot is filled, we may have to add a nop if the delay slot contains
7215 a branch that can't reach its target. Thus, we always have to include
7216 the delay slot in the length estimate. This used to be done in
7217 pa_adjust_insn_length but we do it here now as some sequences always
7218 fill the delay slot and we can save four bytes in the estimate for
7222 attr_length_call (rtx insn, int sibcall)
7228 rtx pat = PATTERN (insn);
7229 unsigned long distance = -1;
7231 if (INSN_ADDRESSES_SET_P ())
7233 unsigned long total;
7235 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7236 distance = (total + insn_current_reference_address (insn));
7237 if (distance < total)
7241 /* Determine if this is a local call. */
7242 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7243 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7245 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7247 call_decl = SYMBOL_REF_DECL (call_dest);
7248 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7250 /* pc-relative branch. */
7251 if (!TARGET_LONG_CALLS
7252 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7253 || distance < 240000))
7256 /* 64-bit plabel sequence. */
7257 else if (TARGET_64BIT && !local_call)
7258 length += sibcall ? 28 : 24;
7260 /* non-pic long absolute branch sequence. */
7261 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7264 /* long pc-relative branch sequence. */
7265 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7266 || (TARGET_64BIT && !TARGET_GAS)
7267 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7271 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7275 /* 32-bit plabel sequence. */
7281 length += length_fp_args (insn);
7291 if (!TARGET_NO_SPACE_REGS)
7299 /* INSN is a function call. It may have an unconditional jump
7302 CALL_DEST is the routine we are calling. */
7305 output_call (rtx insn, rtx call_dest, int sibcall)
7307 int delay_insn_deleted = 0;
7308 int delay_slot_filled = 0;
7309 int seq_length = dbr_sequence_length ();
7310 tree call_decl = SYMBOL_REF_DECL (call_dest);
7311 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7314 xoperands[0] = call_dest;
7316 /* Handle the common case where we're sure that the branch will reach
7317 the beginning of the "$CODE$" subspace. This is the beginning of
7318 the current function if we are in a named section. */
7319 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7321 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7322 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7326 if (TARGET_64BIT && !local_call)
7328 /* ??? As far as I can tell, the HP linker doesn't support the
7329 long pc-relative sequence described in the 64-bit runtime
7330 architecture. So, we use a slightly longer indirect call. */
7331 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7333 xoperands[0] = p->internal_label;
7334 xoperands[1] = gen_label_rtx ();
7336 /* If this isn't a sibcall, we put the load of %r27 into the
7337 delay slot. We can't do this in a sibcall as we don't
7338 have a second call-clobbered scratch register available. */
7340 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7343 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7344 optimize, 0, 0, NULL);
7346 /* Now delete the delay insn. */
7347 PUT_CODE (NEXT_INSN (insn), NOTE);
7348 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7349 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7350 delay_insn_deleted = 1;
7353 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7354 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7355 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7359 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7360 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7361 output_asm_insn ("bve (%%r1)", xoperands);
7365 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7366 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7367 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7368 delay_slot_filled = 1;
7373 int indirect_call = 0;
7375 /* Emit a long call. There are several different sequences
7376 of increasing length and complexity. In most cases,
7377 they don't allow an instruction in the delay slot. */
7378 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7379 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7380 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7385 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7387 && (!TARGET_PA_20 || indirect_call))
7389 /* A non-jump insn in the delay slot. By definition we can
7390 emit this insn before the call (and in fact before argument
7392 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7395 /* Now delete the delay insn. */
7396 PUT_CODE (NEXT_INSN (insn), NOTE);
7397 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7398 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7399 delay_insn_deleted = 1;
7402 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7404 /* This is the best sequence for making long calls in
7405 non-pic code. Unfortunately, GNU ld doesn't provide
7406 the stub needed for external calls, and GAS's support
7407 for this with the SOM linker is buggy. It is safe
7408 to use this for local calls. */
7409 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7411 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7415 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7418 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7420 output_asm_insn ("copy %%r31,%%r2", xoperands);
7421 delay_slot_filled = 1;
7426 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7427 || (TARGET_64BIT && !TARGET_GAS))
7429 /* The HP assembler and linker can handle relocations
7430 for the difference of two symbols. GAS and the HP
7431 linker can't do this when one of the symbols is
7433 xoperands[1] = gen_label_rtx ();
7434 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7435 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7436 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7437 CODE_LABEL_NUMBER (xoperands[1]));
7438 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7440 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7442 /* GAS currently can't generate the relocations that
7443 are needed for the SOM linker under HP-UX using this
7444 sequence. The GNU linker doesn't generate the stubs
7445 that are needed for external calls on TARGET_ELF32
7446 with this sequence. For now, we have to use a
7447 longer plabel sequence when using GAS. */
7448 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7449 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7451 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7456 /* Emit a long plabel-based call sequence. This is
7457 essentially an inline implementation of $$dyncall.
7458 We don't actually try to call $$dyncall as this is
7459 as difficult as calling the function itself. */
7460 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7462 xoperands[0] = p->internal_label;
7463 xoperands[1] = gen_label_rtx ();
7465 /* Since the call is indirect, FP arguments in registers
7466 need to be copied to the general registers. Then, the
7467 argument relocation stub will copy them back. */
7469 copy_fp_args (insn);
7473 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7474 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7475 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7479 output_asm_insn ("addil LR'%0-$global$,%%r27",
7481 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7485 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7486 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7487 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7488 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7490 if (!sibcall && !TARGET_PA_20)
7492 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7493 if (TARGET_NO_SPACE_REGS)
7494 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7496 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7503 output_asm_insn ("bve (%%r1)", xoperands);
7508 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7509 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7510 delay_slot_filled = 1;
7513 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7518 if (!TARGET_NO_SPACE_REGS)
7519 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7524 if (TARGET_NO_SPACE_REGS)
7525 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7527 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7531 if (TARGET_NO_SPACE_REGS)
7532 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7534 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7537 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7539 output_asm_insn ("copy %%r31,%%r2", xoperands);
7540 delay_slot_filled = 1;
7547 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7548 output_asm_insn ("nop", xoperands);
7550 /* We are done if there isn't a jump in the delay slot. */
7552 || delay_insn_deleted
7553 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7556 /* A sibcall should never have a branch in the delay slot. */
7560 /* This call has an unconditional jump in its delay slot. */
7561 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7563 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7565 /* See if the return address can be adjusted. Use the containing
7566 sequence insn's address. */
7567 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7568 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7569 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7571 if (VAL_14_BITS_P (distance))
7573 xoperands[1] = gen_label_rtx ();
7574 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7575 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7576 CODE_LABEL_NUMBER (xoperands[1]));
7579 output_asm_insn ("nop\n\tb,n %0", xoperands);
7582 output_asm_insn ("b,n %0", xoperands);
7584 /* Delete the jump. */
7585 PUT_CODE (NEXT_INSN (insn), NOTE);
7586 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7587 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7592 /* Return the attribute length of the indirect call instruction INSN.
7593 The length must match the code generated by output_indirect call.
7594 The returned length includes the delay slot. Currently, the delay
7595 slot of an indirect call sequence is not exposed and it is used by
7596 the sequence itself. */
7599 attr_length_indirect_call (rtx insn)
7601 unsigned long distance = -1;
7602 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7604 if (INSN_ADDRESSES_SET_P ())
7606 distance = (total + insn_current_reference_address (insn));
7607 if (distance < total)
7614 if (TARGET_FAST_INDIRECT_CALLS
7615 || (!TARGET_PORTABLE_RUNTIME
7616 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7622 if (TARGET_PORTABLE_RUNTIME)
7625 /* Out of reach, can use ble. */
7630 output_indirect_call (rtx insn, rtx call_dest)
7636 xoperands[0] = call_dest;
7637 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7638 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7642 /* First the special case for kernels, level 0 systems, etc. */
7643 if (TARGET_FAST_INDIRECT_CALLS)
7644 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7646 /* Now the normal case -- we can reach $$dyncall directly or
7647 we're sure that we can get there via a long-branch stub.
7649 No need to check target flags as the length uniquely identifies
7650 the remaining cases. */
7651 if (attr_length_indirect_call (insn) == 8)
7653 /* The HP linker substitutes a BLE for millicode calls using
7654 the short PIC PCREL form. Thus, we must use %r31 as the
7655 link register when generating PA 1.x code. */
7657 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7659 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7662 /* Long millicode call, but we are not generating PIC or portable runtime
7664 if (attr_length_indirect_call (insn) == 12)
7665 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7667 /* Long millicode call for portable runtime. */
7668 if (attr_length_indirect_call (insn) == 20)
7669 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7671 /* We need a long PIC call to $$dyncall. */
7672 xoperands[0] = NULL_RTX;
7673 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7674 if (TARGET_SOM || !TARGET_GAS)
7676 xoperands[0] = gen_label_rtx ();
7677 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7678 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7679 CODE_LABEL_NUMBER (xoperands[0]));
7680 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7684 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7685 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7688 output_asm_insn ("blr %%r0,%%r2", xoperands);
7689 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7693 /* Return the total length of the save and restore instructions needed for
7694 the data linkage table pointer (i.e., the PIC register) across the call
7695 instruction INSN. No-return calls do not require a save and restore.
7696 In addition, we may be able to avoid the save and restore for calls
7697 within the same translation unit. */
7700 attr_length_save_restore_dltp (rtx insn)
7702 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7708 /* In HPUX 8.0's shared library scheme, special relocations are needed
7709 for function labels if they might be passed to a function
7710 in a shared library (because shared libraries don't live in code
7711 space), and special magic is needed to construct their address. */
7714 hppa_encode_label (rtx sym)
7716 const char *str = XSTR (sym, 0);
7717 int len = strlen (str) + 1;
7720 p = newstr = alloca (len + 1);
7724 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7728 pa_encode_section_info (tree decl, rtx rtl, int first)
7730 if (first && TEXT_SPACE_P (decl))
7732 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7733 if (TREE_CODE (decl) == FUNCTION_DECL)
7734 hppa_encode_label (XEXP (rtl, 0));
7738 /* This is sort of inverse to pa_encode_section_info. */
7741 pa_strip_name_encoding (const char *str)
7743 str += (*str == '@');
7744 str += (*str == '*');
7749 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7751 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7754 /* Returns 1 if OP is a function label involved in a simple addition
7755 with a constant. Used to keep certain patterns from matching
7756 during instruction combination. */
7758 is_function_label_plus_const (rtx op)
7760 /* Strip off any CONST. */
7761 if (GET_CODE (op) == CONST)
7764 return (GET_CODE (op) == PLUS
7765 && function_label_operand (XEXP (op, 0), Pmode)
7766 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7769 /* Output assembly code for a thunk to FUNCTION. */
7772 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7773 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7776 const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7777 const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
7778 int val_14 = VAL_14_BITS_P (delta);
7780 static unsigned int current_thunk_number;
7783 ASM_OUTPUT_LABEL (file, tname);
7784 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7786 fname = (*targetm.strip_name_encoding) (fname);
7787 tname = (*targetm.strip_name_encoding) (tname);
7789 /* Output the thunk. We know that the function is in the same
7790 translation unit (i.e., the same space) as the thunk, and that
7791 thunks are output after their method. Thus, we don't need an
7792 external branch to reach the function. With SOM and GAS,
7793 functions and thunks are effectively in different sections.
7794 Thus, we can always use a IA-relative branch and the linker
7795 will add a long branch stub if necessary.
7797 However, we have to be careful when generating PIC code on the
7798 SOM port to ensure that the sequence does not transfer to an
7799 import stub for the target function as this could clobber the
7800 return value saved at SP-24. This would also apply to the
7801 32-bit linux port if the multi-space model is implemented. */
7802 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7803 && !(flag_pic && TREE_PUBLIC (function))
7804 && (TARGET_GAS || last_address < 262132))
7805 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7806 && ((targetm.have_named_sections
7807 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7808 /* The GNU 64-bit linker has rather poor stub management.
7809 So, we use a long branch from thunks that aren't in
7810 the same section as the target function. */
7812 && (DECL_SECTION_NAME (thunk_fndecl)
7813 != DECL_SECTION_NAME (function)))
7814 || ((DECL_SECTION_NAME (thunk_fndecl)
7815 == DECL_SECTION_NAME (function))
7816 && last_address < 262132)))
7817 || (!targetm.have_named_sections && last_address < 262132))))
7821 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7822 "(%%r26),%%r26\n", fname, delta);
7827 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7829 fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7830 "(%%r1),%%r26\n", fname, delta);
7834 else if (TARGET_64BIT)
7836 /* We only have one call-clobbered scratch register, so we can't
7837 make use of the delay slot if delta doesn't fit in 14 bits. */
7839 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7840 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7841 "(%%r1),%%r26\n", delta, delta);
7843 fprintf (file, "\tb,l .+8,%%r1\n");
7847 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7848 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname);
7852 int off = val_14 ? 8 : 16;
7853 fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off);
7854 fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off);
7859 fprintf (file, "\tbv %%r0(%%r1)\n\tldo ");
7860 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7865 fprintf (file, "\tbv,n %%r0(%%r1)\n");
7869 else if (TARGET_PORTABLE_RUNTIME)
7871 fprintf (file, "\tldil L'%s,%%r1\n", fname);
7872 fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname);
7876 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7877 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7882 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7884 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7885 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7889 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7891 /* The function is accessible from outside this module. The only
7892 way to avoid an import stub between the thunk and function is to
7893 call the function directly with an indirect sequence similar to
7894 that used by $$dyncall. This is possible because $$dyncall acts
7895 as the import stub in an indirect call. */
7898 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7899 lab = (*targetm.strip_name_encoding) (label);
7901 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7902 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7903 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7904 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7905 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7906 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7907 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7910 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7916 fprintf (file, "\tbve (%%r22)\n\tldo ");
7921 if (TARGET_NO_SPACE_REGS)
7923 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7928 fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
7929 fprintf (file, "\tmtsp %%r21,%%sr0\n");
7930 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7936 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7938 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7943 fprintf (file, "\tb,l .+8,%%r1\n");
7945 fprintf (file, "\tbl .+8,%%r1\n");
7947 if (TARGET_SOM || !TARGET_GAS)
7949 fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname);
7950 fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname);
7954 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7955 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname);
7960 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7961 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7966 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7968 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7969 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7976 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta);
7978 fprintf (file, "\tldil L'%s,%%r22\n", fname);
7979 fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname);
7983 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7988 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7993 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7995 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7998 fprintf (file, "\t.align 4\n");
7999 ASM_OUTPUT_LABEL (file, label);
8000 fprintf (file, "\t.word P'%s\n", fname);
8001 function_section (thunk_fndecl);
8004 current_thunk_number++;
8005 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8006 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8007 last_address += nbytes;
8008 update_total_code_bytes (nbytes);
8011 /* Only direct calls to static functions are allowed to be sibling (tail)
8014 This restriction is necessary because some linker generated stubs will
8015 store return pointers into rp' in some cases which might clobber a
8016 live value already in rp'.
8018 In a sibcall the current function and the target function share stack
8019 space. Thus if the path to the current function and the path to the
8020 target function save a value in rp', they save the value into the
8021 same stack slot, which has undesirable consequences.
8023 Because of the deferred binding nature of shared libraries any function
8024 with external scope could be in a different load module and thus require
8025 rp' to be saved when calling that function. So sibcall optimizations
8026 can only be safe for static function.
8028 Note that GCC never needs return value relocations, so we don't have to
8029 worry about static calls with return value relocations (which require
8032 It is safe to perform a sibcall optimization when the target function
8033 will never return. */
8035 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8037 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8038 single subspace mode and the call is not indirect. As far as I know,
8039 there is no operating system support for the multiple subspace mode.
8040 It might be possible to support indirect calls if we didn't use
8041 $$dyncall (see the indirect sequence generated in output_call). */
8043 return (decl != NULL_TREE);
8045 /* Sibcalls are not ok because the arg pointer register is not a fixed
8046 register. This prevents the sibcall optimization from occurring. In
8047 addition, there are problems with stub placement using GNU ld. This
8048 is because a normal sibcall branch uses a 17-bit relocation while
8049 a regular call branch uses a 22-bit relocation. As a result, more
8050 care needs to be taken in the placement of long-branch stubs. */
8055 && !TARGET_PORTABLE_RUNTIME
8056 && !TREE_PUBLIC (decl));
8059 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8060 use in fmpyadd instructions. */
8062 fmpyaddoperands (rtx *operands)
8064 enum machine_mode mode = GET_MODE (operands[0]);
8066 /* Must be a floating point mode. */
8067 if (mode != SFmode && mode != DFmode)
8070 /* All modes must be the same. */
8071 if (! (mode == GET_MODE (operands[1])
8072 && mode == GET_MODE (operands[2])
8073 && mode == GET_MODE (operands[3])
8074 && mode == GET_MODE (operands[4])
8075 && mode == GET_MODE (operands[5])))
8078 /* All operands must be registers. */
8079 if (! (GET_CODE (operands[1]) == REG
8080 && GET_CODE (operands[2]) == REG
8081 && GET_CODE (operands[3]) == REG
8082 && GET_CODE (operands[4]) == REG
8083 && GET_CODE (operands[5]) == REG))
8086 /* Only 2 real operands to the addition. One of the input operands must
8087 be the same as the output operand. */
8088 if (! rtx_equal_p (operands[3], operands[4])
8089 && ! rtx_equal_p (operands[3], operands[5]))
8092 /* Inout operand of add can not conflict with any operands from multiply. */
8093 if (rtx_equal_p (operands[3], operands[0])
8094 || rtx_equal_p (operands[3], operands[1])
8095 || rtx_equal_p (operands[3], operands[2]))
8098 /* multiply can not feed into addition operands. */
8099 if (rtx_equal_p (operands[4], operands[0])
8100 || rtx_equal_p (operands[5], operands[0]))
8103 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8105 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8106 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8107 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8108 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8109 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8110 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8113 /* Passed. Operands are suitable for fmpyadd. */
8117 #if !defined(USE_COLLECT2)
8119 pa_asm_out_constructor (rtx symbol, int priority)
8121 if (!function_label_operand (symbol, VOIDmode))
8122 hppa_encode_label (symbol);
8124 #ifdef CTORS_SECTION_ASM_OP
8125 default_ctor_section_asm_out_constructor (symbol, priority);
8127 # ifdef TARGET_ASM_NAMED_SECTION
8128 default_named_section_asm_out_constructor (symbol, priority);
8130 default_stabs_asm_out_constructor (symbol, priority);
8136 pa_asm_out_destructor (rtx symbol, int priority)
8138 if (!function_label_operand (symbol, VOIDmode))
8139 hppa_encode_label (symbol);
8141 #ifdef DTORS_SECTION_ASM_OP
8142 default_dtor_section_asm_out_destructor (symbol, priority);
8144 # ifdef TARGET_ASM_NAMED_SECTION
8145 default_named_section_asm_out_destructor (symbol, priority);
8147 default_stabs_asm_out_destructor (symbol, priority);
8153 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8154 use in fmpysub instructions. */
8156 fmpysuboperands (rtx *operands)
8158 enum machine_mode mode = GET_MODE (operands[0]);
8160 /* Must be a floating point mode. */
8161 if (mode != SFmode && mode != DFmode)
8164 /* All modes must be the same. */
8165 if (! (mode == GET_MODE (operands[1])
8166 && mode == GET_MODE (operands[2])
8167 && mode == GET_MODE (operands[3])
8168 && mode == GET_MODE (operands[4])
8169 && mode == GET_MODE (operands[5])))
8172 /* All operands must be registers. */
8173 if (! (GET_CODE (operands[1]) == REG
8174 && GET_CODE (operands[2]) == REG
8175 && GET_CODE (operands[3]) == REG
8176 && GET_CODE (operands[4]) == REG
8177 && GET_CODE (operands[5]) == REG))
8180 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8181 operation, so operands[4] must be the same as operand[3]. */
8182 if (! rtx_equal_p (operands[3], operands[4]))
8185 /* multiply can not feed into subtraction. */
8186 if (rtx_equal_p (operands[5], operands[0]))
8189 /* Inout operand of sub can not conflict with any operands from multiply. */
8190 if (rtx_equal_p (operands[3], operands[0])
8191 || rtx_equal_p (operands[3], operands[1])
8192 || rtx_equal_p (operands[3], operands[2]))
8195 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8197 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8198 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8199 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8200 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8201 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8202 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8205 /* Passed. Operands are suitable for fmpysub. */
8210 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8212 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8213 || GET_CODE (op) == IOR);
8216 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8217 constants for shadd instructions. */
8219 shadd_constant_p (int val)
8221 if (val == 2 || val == 4 || val == 8)
8227 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8228 the valid constant for shadd instructions. */
8230 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8232 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8235 /* Return 1 if OP is valid as a base or index register in a
8239 borx_reg_operand (rtx op, enum machine_mode mode)
8241 if (GET_CODE (op) != REG)
8244 /* We must reject virtual registers as the only expressions that
8245 can be instantiated are REG and REG+CONST. */
8246 if (op == virtual_incoming_args_rtx
8247 || op == virtual_stack_vars_rtx
8248 || op == virtual_stack_dynamic_rtx
8249 || op == virtual_outgoing_args_rtx
8250 || op == virtual_cfa_rtx)
8253 /* While it's always safe to index off the frame pointer, it's not
8254 profitable to do so when the frame pointer is being eliminated. */
8255 if (!reload_completed
8256 && flag_omit_frame_pointer
8257 && !current_function_calls_alloca
8258 && op == frame_pointer_rtx)
8261 return register_operand (op, mode);
8264 /* Return 1 if this operand is anything other than a hard register. */
8267 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8269 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8272 /* Return 1 if INSN branches forward. Should be using insn_addresses
8273 to avoid walking through all the insns... */
8275 forward_branch_p (rtx insn)
8277 rtx label = JUMP_LABEL (insn);
8284 insn = NEXT_INSN (insn);
8287 return (insn == label);
8290 /* Return 1 if OP is an equality comparison, else return 0. */
8292 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8294 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8297 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8299 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8301 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8302 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8305 /* Return 1 if INSN is in the delay slot of a call instruction. */
8307 jump_in_call_delay (rtx insn)
8310 if (GET_CODE (insn) != JUMP_INSN)
8313 if (PREV_INSN (insn)
8314 && PREV_INSN (PREV_INSN (insn))
8315 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8317 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8319 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8320 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8327 /* Output an unconditional move and branch insn. */
8330 output_parallel_movb (rtx *operands, int length)
8332 /* These are the cases in which we win. */
8334 return "mov%I1b,tr %1,%0,%2";
8336 /* None of these cases wins, but they don't lose either. */
8337 if (dbr_sequence_length () == 0)
8339 /* Nothing in the delay slot, fake it by putting the combined
8340 insn (the copy or add) in the delay slot of a bl. */
8341 if (GET_CODE (operands[1]) == CONST_INT)
8342 return "b %2\n\tldi %1,%0";
8344 return "b %2\n\tcopy %1,%0";
8348 /* Something in the delay slot, but we've got a long branch. */
8349 if (GET_CODE (operands[1]) == CONST_INT)
8350 return "ldi %1,%0\n\tb %2";
8352 return "copy %1,%0\n\tb %2";
8356 /* Output an unconditional add and branch insn. */
8359 output_parallel_addb (rtx *operands, int length)
8361 /* To make life easy we want operand0 to be the shared input/output
8362 operand and operand1 to be the readonly operand. */
8363 if (operands[0] == operands[1])
8364 operands[1] = operands[2];
8366 /* These are the cases in which we win. */
8368 return "add%I1b,tr %1,%0,%3";
8370 /* None of these cases win, but they don't lose either. */
8371 if (dbr_sequence_length () == 0)
8373 /* Nothing in the delay slot, fake it by putting the combined
8374 insn (the copy or add) in the delay slot of a bl. */
8375 return "b %3\n\tadd%I1 %1,%0,%0";
8379 /* Something in the delay slot, but we've got a long branch. */
8380 return "add%I1 %1,%0,%0\n\tb %3";
8384 /* Return nonzero if INSN (a jump insn) immediately follows a call
8385 to a named function. This is used to avoid filling the delay slot
8386 of the jump since it can usually be eliminated by modifying RP in
8387 the delay slot of the call. */
8390 following_call (rtx insn)
8392 if (! TARGET_JUMP_IN_DELAY)
8395 /* Find the previous real insn, skipping NOTEs. */
8396 insn = PREV_INSN (insn);
8397 while (insn && GET_CODE (insn) == NOTE)
8398 insn = PREV_INSN (insn);
8400 /* Check for CALL_INSNs and millicode calls. */
8402 && ((GET_CODE (insn) == CALL_INSN
8403 && get_attr_type (insn) != TYPE_DYNCALL)
8404 || (GET_CODE (insn) == INSN
8405 && GET_CODE (PATTERN (insn)) != SEQUENCE
8406 && GET_CODE (PATTERN (insn)) != USE
8407 && GET_CODE (PATTERN (insn)) != CLOBBER
8408 && get_attr_type (insn) == TYPE_MILLI)))
8414 /* We use this hook to perform a PA specific optimization which is difficult
8415 to do in earlier passes.
8417 We want the delay slots of branches within jump tables to be filled.
8418 None of the compiler passes at the moment even has the notion that a
8419 PA jump table doesn't contain addresses, but instead contains actual
8422 Because we actually jump into the table, the addresses of each entry
8423 must stay constant in relation to the beginning of the table (which
8424 itself must stay constant relative to the instruction to jump into
8425 it). I don't believe we can guarantee earlier passes of the compiler
8426 will adhere to those rules.
8428 So, late in the compilation process we find all the jump tables, and
8429 expand them into real code -- eg each entry in the jump table vector
8430 will get an appropriate label followed by a jump to the final target.
8432 Reorg and the final jump pass can then optimize these branches and
8433 fill their delay slots. We end up with smaller, more efficient code.
8435 The jump instructions within the table are special; we must be able
8436 to identify them during assembly output (if the jumps don't get filled
8437 we need to emit a nop rather than nullifying the delay slot)). We
8438 identify jumps in switch tables by using insns with the attribute
8439 type TYPE_BTABLE_BRANCH.
8441 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8442 insns. This serves two purposes, first it prevents jump.c from
8443 noticing that the last N entries in the table jump to the instruction
8444 immediately after the table and deleting the jumps. Second, those
8445 insns mark where we should emit .begin_brtab and .end_brtab directives
8446 when using GAS (allows for better link time optimizations). */
8453 remove_useless_addtr_insns (1);
8455 if (pa_cpu < PROCESSOR_8000)
8456 pa_combine_instructions ();
8459 /* This is fairly cheap, so always run it if optimizing. */
8460 if (optimize > 0 && !TARGET_BIG_SWITCH)
8462 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8463 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8465 rtx pattern, tmp, location, label;
8466 unsigned int length, i;
8468 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8469 if (GET_CODE (insn) != JUMP_INSN
8470 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8471 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8474 /* Emit marker for the beginning of the branch table. */
8475 emit_insn_before (gen_begin_brtab (), insn);
8477 pattern = PATTERN (insn);
8478 location = PREV_INSN (insn);
8479 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8481 for (i = 0; i < length; i++)
8483 /* Emit a label before each jump to keep jump.c from
8484 removing this code. */
8485 tmp = gen_label_rtx ();
8486 LABEL_NUSES (tmp) = 1;
8487 emit_label_after (tmp, location);
8488 location = NEXT_INSN (location);
8490 if (GET_CODE (pattern) == ADDR_VEC)
8491 label = XEXP (XVECEXP (pattern, 0, i), 0);
8493 label = XEXP (XVECEXP (pattern, 1, i), 0);
8495 tmp = gen_short_jump (label);
8497 /* Emit the jump itself. */
8498 tmp = emit_jump_insn_after (tmp, location);
8499 JUMP_LABEL (tmp) = label;
8500 LABEL_NUSES (label)++;
8501 location = NEXT_INSN (location);
8503 /* Emit a BARRIER after the jump. */
8504 emit_barrier_after (location);
8505 location = NEXT_INSN (location);
8508 /* Emit marker for the end of the branch table. */
8509 emit_insn_before (gen_end_brtab (), location);
8510 location = NEXT_INSN (location);
8511 emit_barrier_after (location);
8513 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8519 /* Still need brtab marker insns. FIXME: the presence of these
8520 markers disables output of the branch table to readonly memory,
8521 and any alignment directives that might be needed. Possibly,
8522 the begin_brtab insn should be output before the label for the
8523 table. This doesn't matter at the moment since the tables are
8524 always output in the text section. */
8525 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8527 /* Find an ADDR_VEC insn. */
8528 if (GET_CODE (insn) != JUMP_INSN
8529 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8530 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8533 /* Now generate markers for the beginning and end of the
8535 emit_insn_before (gen_begin_brtab (), insn);
8536 emit_insn_after (gen_end_brtab (), insn);
8541 /* The PA has a number of odd instructions which can perform multiple
8542 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8543 it may be profitable to combine two instructions into one instruction
8544 with two outputs. It's not profitable PA2.0 machines because the
8545 two outputs would take two slots in the reorder buffers.
8547 This routine finds instructions which can be combined and combines
8548 them. We only support some of the potential combinations, and we
8549 only try common ways to find suitable instructions.
8551 * addb can add two registers or a register and a small integer
8552 and jump to a nearby (+-8k) location. Normally the jump to the
8553 nearby location is conditional on the result of the add, but by
8554 using the "true" condition we can make the jump unconditional.
8555 Thus addb can perform two independent operations in one insn.
8557 * movb is similar to addb in that it can perform a reg->reg
8558 or small immediate->reg copy and jump to a nearby (+-8k location).
8560 * fmpyadd and fmpysub can perform a FP multiply and either an
8561 FP add or FP sub if the operands of the multiply and add/sub are
8562 independent (there are other minor restrictions). Note both
8563 the fmpy and fadd/fsub can in theory move to better spots according
8564 to data dependencies, but for now we require the fmpy stay at a
8567 * Many of the memory operations can perform pre & post updates
8568 of index registers. GCC's pre/post increment/decrement addressing
8569 is far too simple to take advantage of all the possibilities. This
8570 pass may not be suitable since those insns may not be independent.
8572 * comclr can compare two ints or an int and a register, nullify
8573 the following instruction and zero some other register. This
8574 is more difficult to use as it's harder to find an insn which
8575 will generate a comclr than finding something like an unconditional
8576 branch. (conditional moves & long branches create comclr insns).
8578 * Most arithmetic operations can conditionally skip the next
8579 instruction. They can be viewed as "perform this operation
8580 and conditionally jump to this nearby location" (where nearby
8581 is an insns away). These are difficult to use due to the
8582 branch length restrictions. */
8585 pa_combine_instructions (void)
8589 /* This can get expensive since the basic algorithm is on the
8590 order of O(n^2) (or worse). Only do it for -O2 or higher
8591 levels of optimization. */
8595 /* Walk down the list of insns looking for "anchor" insns which
8596 may be combined with "floating" insns. As the name implies,
8597 "anchor" instructions don't move, while "floating" insns may
8599 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8600 new = make_insn_raw (new);
8602 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8604 enum attr_pa_combine_type anchor_attr;
8605 enum attr_pa_combine_type floater_attr;
8607 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8608 Also ignore any special USE insns. */
8609 if ((GET_CODE (anchor) != INSN
8610 && GET_CODE (anchor) != JUMP_INSN
8611 && GET_CODE (anchor) != CALL_INSN)
8612 || GET_CODE (PATTERN (anchor)) == USE
8613 || GET_CODE (PATTERN (anchor)) == CLOBBER
8614 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8615 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8618 anchor_attr = get_attr_pa_combine_type (anchor);
8619 /* See if anchor is an insn suitable for combination. */
8620 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8621 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8622 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8623 && ! forward_branch_p (anchor)))
8627 for (floater = PREV_INSN (anchor);
8629 floater = PREV_INSN (floater))
8631 if (GET_CODE (floater) == NOTE
8632 || (GET_CODE (floater) == INSN
8633 && (GET_CODE (PATTERN (floater)) == USE
8634 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8637 /* Anything except a regular INSN will stop our search. */
8638 if (GET_CODE (floater) != INSN
8639 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8640 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8646 /* See if FLOATER is suitable for combination with the
8648 floater_attr = get_attr_pa_combine_type (floater);
8649 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8650 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8651 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8652 && floater_attr == PA_COMBINE_TYPE_FMPY))
8654 /* If ANCHOR and FLOATER can be combined, then we're
8655 done with this pass. */
8656 if (pa_can_combine_p (new, anchor, floater, 0,
8657 SET_DEST (PATTERN (floater)),
8658 XEXP (SET_SRC (PATTERN (floater)), 0),
8659 XEXP (SET_SRC (PATTERN (floater)), 1)))
8663 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8664 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8666 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8668 if (pa_can_combine_p (new, anchor, floater, 0,
8669 SET_DEST (PATTERN (floater)),
8670 XEXP (SET_SRC (PATTERN (floater)), 0),
8671 XEXP (SET_SRC (PATTERN (floater)), 1)))
8676 if (pa_can_combine_p (new, anchor, floater, 0,
8677 SET_DEST (PATTERN (floater)),
8678 SET_SRC (PATTERN (floater)),
8679 SET_SRC (PATTERN (floater))))
8685 /* If we didn't find anything on the backwards scan try forwards. */
8687 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8688 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8690 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8692 if (GET_CODE (floater) == NOTE
8693 || (GET_CODE (floater) == INSN
8694 && (GET_CODE (PATTERN (floater)) == USE
8695 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8699 /* Anything except a regular INSN will stop our search. */
8700 if (GET_CODE (floater) != INSN
8701 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8702 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8708 /* See if FLOATER is suitable for combination with the
8710 floater_attr = get_attr_pa_combine_type (floater);
8711 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8712 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8713 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8714 && floater_attr == PA_COMBINE_TYPE_FMPY))
8716 /* If ANCHOR and FLOATER can be combined, then we're
8717 done with this pass. */
8718 if (pa_can_combine_p (new, anchor, floater, 1,
8719 SET_DEST (PATTERN (floater)),
8720 XEXP (SET_SRC (PATTERN (floater)),
8722 XEXP (SET_SRC (PATTERN (floater)),
8729 /* FLOATER will be nonzero if we found a suitable floating
8730 insn for combination with ANCHOR. */
8732 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8733 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8735 /* Emit the new instruction and delete the old anchor. */
8736 emit_insn_before (gen_rtx_PARALLEL
8738 gen_rtvec (2, PATTERN (anchor),
8739 PATTERN (floater))),
8742 PUT_CODE (anchor, NOTE);
8743 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8744 NOTE_SOURCE_FILE (anchor) = 0;
8746 /* Emit a special USE insn for FLOATER, then delete
8747 the floating insn. */
8748 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8749 delete_insn (floater);
8754 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8757 /* Emit the new_jump instruction and delete the old anchor. */
8759 = emit_jump_insn_before (gen_rtx_PARALLEL
8761 gen_rtvec (2, PATTERN (anchor),
8762 PATTERN (floater))),
8765 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8766 PUT_CODE (anchor, NOTE);
8767 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8768 NOTE_SOURCE_FILE (anchor) = 0;
8770 /* Emit a special USE insn for FLOATER, then delete
8771 the floating insn. */
8772 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8773 delete_insn (floater);
8781 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8784 int insn_code_number;
8787 /* Create a PARALLEL with the patterns of ANCHOR and
8788 FLOATER, try to recognize it, then test constraints
8789 for the resulting pattern.
8791 If the pattern doesn't match or the constraints
8792 aren't met keep searching for a suitable floater
8794 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8795 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8796 INSN_CODE (new) = -1;
8797 insn_code_number = recog_memoized (new);
8798 if (insn_code_number < 0
8799 || (extract_insn (new), ! constrain_operands (1)))
8813 /* There's up to three operands to consider. One
8814 output and two inputs.
8816 The output must not be used between FLOATER & ANCHOR
8817 exclusive. The inputs must not be set between
8818 FLOATER and ANCHOR exclusive. */
8820 if (reg_used_between_p (dest, start, end))
8823 if (reg_set_between_p (src1, start, end))
8826 if (reg_set_between_p (src2, start, end))
8829 /* If we get here, then everything is good. */
8833 /* Return nonzero if references for INSN are delayed.
8835 Millicode insns are actually function calls with some special
8836 constraints on arguments and register usage.
8838 Millicode calls always expect their arguments in the integer argument
8839 registers, and always return their result in %r29 (ret1). They
8840 are expected to clobber their arguments, %r1, %r29, and the return
8841 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8843 This function tells reorg that the references to arguments and
8844 millicode calls do not appear to happen until after the millicode call.
8845 This allows reorg to put insns which set the argument registers into the
8846 delay slot of the millicode call -- thus they act more like traditional
8849 Note we can not consider side effects of the insn to be delayed because
8850 the branch and link insn will clobber the return pointer. If we happened
8851 to use the return pointer in the delay slot of the call, then we lose.
8853 get_attr_type will try to recognize the given insn, so make sure to
8854 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8857 insn_refs_are_delayed (rtx insn)
8859 return ((GET_CODE (insn) == INSN
8860 && GET_CODE (PATTERN (insn)) != SEQUENCE
8861 && GET_CODE (PATTERN (insn)) != USE
8862 && GET_CODE (PATTERN (insn)) != CLOBBER
8863 && get_attr_type (insn) == TYPE_MILLI));
8866 /* On the HP-PA the value is found in register(s) 28(-29), unless
8867 the mode is SF or DF. Then the value is returned in fr4 (32).
8869 This must perform the same promotions as PROMOTE_MODE, else
8870 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8872 Small structures must be returned in a PARALLEL on PA64 in order
8873 to match the HP Compiler ABI. */
8876 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8878 enum machine_mode valmode;
8880 /* Aggregates with a size less than or equal to 128 bits are returned
8881 in GR 28(-29). They are left justified. The pad bits are undefined.
8882 Larger aggregates are returned in memory. */
8883 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8887 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8889 for (i = 0; i < ub; i++)
8891 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8892 gen_rtx_REG (DImode, 28 + i),
8897 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8900 if ((INTEGRAL_TYPE_P (valtype)
8901 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8902 || POINTER_TYPE_P (valtype))
8903 valmode = word_mode;
8905 valmode = TYPE_MODE (valtype);
8907 if (TREE_CODE (valtype) == REAL_TYPE
8908 && TYPE_MODE (valtype) != TFmode
8909 && !TARGET_SOFT_FLOAT)
8910 return gen_rtx_REG (valmode, 32);
8912 return gen_rtx_REG (valmode, 28);
8915 /* Return the location of a parameter that is passed in a register or NULL
8916 if the parameter has any component that is passed in memory.
8918 This is new code and will be pushed to into the net sources after
8921 ??? We might want to restructure this so that it looks more like other
8924 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8925 int named ATTRIBUTE_UNUSED)
8927 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8934 if (mode == VOIDmode)
8937 arg_size = FUNCTION_ARG_SIZE (mode, type);
8939 /* If this arg would be passed partially or totally on the stack, then
8940 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8941 handle arguments which are split between regs and stack slots if
8942 the ABI mandates split arguments. */
8945 /* The 32-bit ABI does not split arguments. */
8946 if (cum->words + arg_size > max_arg_words)
8952 alignment = cum->words & 1;
8953 if (cum->words + alignment >= max_arg_words)
8957 /* The 32bit ABIs and the 64bit ABIs are rather different,
8958 particularly in their handling of FP registers. We might
8959 be able to cleverly share code between them, but I'm not
8960 going to bother in the hope that splitting them up results
8961 in code that is more easily understood. */
8965 /* Advance the base registers to their current locations.
8967 Remember, gprs grow towards smaller register numbers while
8968 fprs grow to higher register numbers. Also remember that
8969 although FP regs are 32-bit addressable, we pretend that
8970 the registers are 64-bits wide. */
8971 gpr_reg_base = 26 - cum->words;
8972 fpr_reg_base = 32 + cum->words;
8974 /* Arguments wider than one word and small aggregates need special
8978 || (type && AGGREGATE_TYPE_P (type)))
8980 /* Double-extended precision (80-bit), quad-precision (128-bit)
8981 and aggregates including complex numbers are aligned on
8982 128-bit boundaries. The first eight 64-bit argument slots
8983 are associated one-to-one, with general registers r26
8984 through r19, and also with floating-point registers fr4
8985 through fr11. Arguments larger than one word are always
8986 passed in general registers.
8988 Using a PARALLEL with a word mode register results in left
8989 justified data on a big-endian target. */
8992 int i, offset = 0, ub = arg_size;
8994 /* Align the base register. */
8995 gpr_reg_base -= alignment;
8997 ub = MIN (ub, max_arg_words - cum->words - alignment);
8998 for (i = 0; i < ub; i++)
9000 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9001 gen_rtx_REG (DImode, gpr_reg_base),
9007 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9012 /* If the argument is larger than a word, then we know precisely
9013 which registers we must use. */
9027 /* Structures 5 to 8 bytes in size are passed in the general
9028 registers in the same manner as other non floating-point
9029 objects. The data is right-justified and zero-extended
9030 to 64 bits. This is opposite to the normal justification
9031 used on big endian targets and requires special treatment.
9032 We now define BLOCK_REG_PADDING to pad these objects. */
9033 if (mode == BLKmode)
9035 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9036 gen_rtx_REG (DImode, gpr_reg_base),
9038 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
9043 /* We have a single word (32 bits). A simple computation
9044 will get us the register #s we need. */
9045 gpr_reg_base = 26 - cum->words;
9046 fpr_reg_base = 32 + 2 * cum->words;
9050 /* Determine if the argument needs to be passed in both general and
9051 floating point registers. */
9052 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9053 /* If we are doing soft-float with portable runtime, then there
9054 is no need to worry about FP regs. */
9055 && !TARGET_SOFT_FLOAT
9056 /* The parameter must be some kind of float, else we can just
9057 pass it in integer registers. */
9058 && FLOAT_MODE_P (mode)
9059 /* The target function must not have a prototype. */
9060 && cum->nargs_prototype <= 0
9061 /* libcalls do not need to pass items in both FP and general
9063 && type != NULL_TREE
9064 /* All this hair applies to "outgoing" args only. This includes
9065 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9067 /* Also pass outgoing floating arguments in both registers in indirect
9068 calls with the 32 bit ABI and the HP assembler since there is no
9069 way to the specify argument locations in static functions. */
9074 && FLOAT_MODE_P (mode)))
9080 gen_rtx_EXPR_LIST (VOIDmode,
9081 gen_rtx_REG (mode, fpr_reg_base),
9083 gen_rtx_EXPR_LIST (VOIDmode,
9084 gen_rtx_REG (mode, gpr_reg_base),
9089 /* See if we should pass this parameter in a general register. */
9090 if (TARGET_SOFT_FLOAT
9091 /* Indirect calls in the normal 32bit ABI require all arguments
9092 to be passed in general registers. */
9093 || (!TARGET_PORTABLE_RUNTIME
9097 /* If the parameter is not a floating point parameter, then
9098 it belongs in GPRs. */
9099 || !FLOAT_MODE_P (mode))
9100 retval = gen_rtx_REG (mode, gpr_reg_base);
9102 retval = gen_rtx_REG (mode, fpr_reg_base);
9108 /* If this arg would be passed totally in registers or totally on the stack,
9109 then this routine should return zero. It is currently called only for
9110 the 64-bit target. */
9112 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9113 tree type, int named ATTRIBUTE_UNUSED)
9115 unsigned int max_arg_words = 8;
9116 unsigned int offset = 0;
9118 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9121 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9122 /* Arg fits fully into registers. */
9124 else if (cum->words + offset >= max_arg_words)
9125 /* Arg fully on the stack. */
9129 return max_arg_words - cum->words - offset;
9133 /* Return 1 if this is a comparison operator. This allows the use of
9134 MATCH_OPERATOR to recognize all the branch insns. */
9137 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9139 return ((mode == VOIDmode || GET_MODE (op) == mode)
9140 && (GET_CODE (op) == EQ
9141 || GET_CODE (op) == NE
9142 || GET_CODE (op) == GT
9143 || GET_CODE (op) == GTU
9144 || GET_CODE (op) == GE
9145 || GET_CODE (op) == LT
9146 || GET_CODE (op) == LE
9147 || GET_CODE (op) == LEU));
9150 /* On hpux10, the linker will give an error if we have a reference
9151 in the read-only data section to a symbol defined in a shared
9152 library. Therefore, expressions that might require a reloc can
9153 not be placed in the read-only data section. */
9156 pa_select_section (tree exp, int reloc,
9157 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9159 if (TREE_CODE (exp) == VAR_DECL
9160 && TREE_READONLY (exp)
9161 && !TREE_THIS_VOLATILE (exp)
9162 && DECL_INITIAL (exp)
9163 && (DECL_INITIAL (exp) == error_mark_node
9164 || TREE_CONSTANT (DECL_INITIAL (exp)))
9166 readonly_data_section ();
9167 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
9169 readonly_data_section ();
9175 pa_globalize_label (FILE *stream, const char *name)
9177 /* We only handle DATA objects here, functions are globalized in
9178 ASM_DECLARE_FUNCTION_NAME. */
9179 if (! FUNCTION_NAME_P (name))
9181 fputs ("\t.EXPORT ", stream);
9182 assemble_name (stream, name);
9183 fputs (",DATA\n", stream);
9187 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9190 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9191 int incoming ATTRIBUTE_UNUSED)
9193 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9196 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9199 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9201 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9202 PA64 ABI says that objects larger than 128 bits are returned in memory.
9203 Note, int_size_in_bytes can return -1 if the size of the object is
9204 variable or larger than the maximum value that can be expressed as
9205 a HOST_WIDE_INT. It can also return zero for an empty type. The
9206 simplest way to handle variable and empty types is to pass them in
9207 memory. This avoids problems in defining the boundaries of argument
9208 slots, allocating registers, etc. */
9209 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9210 || int_size_in_bytes (type) <= 0);