1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static int hppa_address_cost (rtx);
88 static bool hppa_rtx_costs (rtx, int, int, int *);
89 static inline rtx force_mode (enum machine_mode, rtx);
90 static void pa_reorg (void);
91 static void pa_combine_instructions (void);
92 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
93 static int forward_branch_p (rtx);
94 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
95 static int compute_movmem_length (rtx);
96 static int compute_clrmem_length (rtx);
97 static bool pa_assemble_integer (rtx, unsigned int, int);
98 static void remove_useless_addtr_insns (int);
99 static void store_reg (int, HOST_WIDE_INT, int);
100 static void store_reg_modify (int, int, HOST_WIDE_INT);
101 static void load_reg (int, HOST_WIDE_INT, int);
102 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
103 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
104 static void update_total_code_bytes (int);
105 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
106 static int pa_adjust_cost (rtx, rtx, rtx, int);
107 static int pa_adjust_priority (rtx, int);
108 static int pa_issue_rate (void);
109 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
111 static void pa_encode_section_info (tree, rtx, int);
112 static const char *pa_strip_name_encoding (const char *);
113 static bool pa_function_ok_for_sibcall (tree, tree);
114 static void pa_globalize_label (FILE *, const char *)
116 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
117 HOST_WIDE_INT, tree);
118 #if !defined(USE_COLLECT2)
119 static void pa_asm_out_constructor (rtx, int);
120 static void pa_asm_out_destructor (rtx, int);
122 static void pa_init_builtins (void);
123 static rtx hppa_builtin_saveregs (void);
124 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
125 static bool pa_scalar_mode_supported_p (enum machine_mode);
126 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
127 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static struct deferred_plabel *get_plabel (rtx) ATTRIBUTE_UNUSED;
129 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
130 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
133 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
134 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
138 static void output_deferred_plabels (void);
139 #ifdef ASM_OUTPUT_EXTERNAL_REAL
140 static void pa_hpux_file_end (void);
142 #ifdef HPUX_LONG_DOUBLE_LIBRARY
143 static void pa_hpux_init_libfuncs (void);
145 static rtx pa_struct_value_rtx (tree, int);
146 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
148 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
150 static struct machine_function * pa_init_machine_status (void);
153 /* Save the operands last given to a compare for use when we
154 generate a scc or bcc insn. */
155 rtx hppa_compare_op0, hppa_compare_op1;
156 enum cmp_type hppa_branch_type;
158 /* Which architecture we are generating code for. */
159 enum architecture_type pa_arch;
161 /* String to hold which architecture we are generating code for. */
162 const char *pa_arch_string;
164 /* String used with the -mfixed-range= option. */
165 const char *pa_fixed_range_string;
167 /* Which cpu we are scheduling for. */
168 enum processor_type pa_cpu;
170 /* String to hold which cpu we are scheduling for. */
171 const char *pa_cpu_string;
173 /* String used with the -munix= option. */
174 const char *pa_unix_string;
176 /* The UNIX standard to use for predefines and linking. */
179 /* Counts for the number of callee-saved general and floating point
180 registers which were saved by the current function's prologue. */
181 static int gr_saved, fr_saved;
183 static rtx find_addr_reg (rtx);
185 /* Keep track of the number of bytes we have output in the CODE subspace
186 during this compilation so we'll know when to emit inline long-calls. */
187 unsigned long total_code_bytes;
189 /* The last address of the previous function plus the number of bytes in
190 associated thunks that have been output. This is used to determine if
191 a thunk can use an IA-relative branch to reach its target function. */
192 static int last_address;
194 /* Variables to handle plabels that we discover are necessary at assembly
195 output time. They are output after the current function. */
196 struct deferred_plabel GTY(())
201 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
203 static size_t n_deferred_plabels = 0;
206 /* Initialize the GCC target structure. */
208 #undef TARGET_ASM_ALIGNED_HI_OP
209 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
210 #undef TARGET_ASM_ALIGNED_SI_OP
211 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
212 #undef TARGET_ASM_ALIGNED_DI_OP
213 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
214 #undef TARGET_ASM_UNALIGNED_HI_OP
215 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
216 #undef TARGET_ASM_UNALIGNED_SI_OP
217 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
218 #undef TARGET_ASM_UNALIGNED_DI_OP
219 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
220 #undef TARGET_ASM_INTEGER
221 #define TARGET_ASM_INTEGER pa_assemble_integer
223 #undef TARGET_ASM_FUNCTION_PROLOGUE
224 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
225 #undef TARGET_ASM_FUNCTION_EPILOGUE
226 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
228 #undef TARGET_SCHED_ADJUST_COST
229 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
230 #undef TARGET_SCHED_ADJUST_PRIORITY
231 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
232 #undef TARGET_SCHED_ISSUE_RATE
233 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
235 #undef TARGET_ENCODE_SECTION_INFO
236 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
237 #undef TARGET_STRIP_NAME_ENCODING
238 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
240 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
241 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
243 #undef TARGET_ASM_OUTPUT_MI_THUNK
244 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
245 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
246 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
248 #undef TARGET_ASM_FILE_END
249 #ifdef ASM_OUTPUT_EXTERNAL_REAL
250 #define TARGET_ASM_FILE_END pa_hpux_file_end
252 #define TARGET_ASM_FILE_END output_deferred_plabels
255 #if !defined(USE_COLLECT2)
256 #undef TARGET_ASM_CONSTRUCTOR
257 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
258 #undef TARGET_ASM_DESTRUCTOR
259 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
262 #undef TARGET_INIT_BUILTINS
263 #define TARGET_INIT_BUILTINS pa_init_builtins
265 #undef TARGET_RTX_COSTS
266 #define TARGET_RTX_COSTS hppa_rtx_costs
267 #undef TARGET_ADDRESS_COST
268 #define TARGET_ADDRESS_COST hppa_address_cost
270 #undef TARGET_MACHINE_DEPENDENT_REORG
271 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
273 #ifdef HPUX_LONG_DOUBLE_LIBRARY
274 #undef TARGET_INIT_LIBFUNCS
275 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
278 #undef TARGET_PROMOTE_FUNCTION_RETURN
279 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
280 #undef TARGET_PROMOTE_PROTOTYPES
281 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
283 #undef TARGET_STRUCT_VALUE_RTX
284 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
285 #undef TARGET_RETURN_IN_MEMORY
286 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
287 #undef TARGET_MUST_PASS_IN_STACK
288 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
289 #undef TARGET_PASS_BY_REFERENCE
290 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
291 #undef TARGET_CALLEE_COPIES
292 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
293 #undef TARGET_ARG_PARTIAL_BYTES
294 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
296 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
297 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
298 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
299 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
301 #undef TARGET_SCALAR_MODE_SUPPORTED_P
302 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
304 struct gcc_target targetm = TARGET_INITIALIZER;
306 /* Parse the -mfixed-range= option string. */
309 fix_range (const char *const_str)
312 char *str, *dash, *comma;
314 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
315 REG2 are either register names or register numbers. The effect
316 of this option is to mark the registers in the range from REG1 to
317 REG2 as ``fixed'' so they won't be used by the compiler. This is
318 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
320 i = strlen (const_str);
321 str = (char *) alloca (i + 1);
322 memcpy (str, const_str, i + 1);
326 dash = strchr (str, '-');
329 warning ("value of -mfixed-range must have form REG1-REG2");
334 comma = strchr (dash + 1, ',');
338 first = decode_reg_name (str);
341 warning ("unknown register name: %s", str);
345 last = decode_reg_name (dash + 1);
348 warning ("unknown register name: %s", dash + 1);
356 warning ("%s-%s is an empty range", str, dash + 1);
360 for (i = first; i <= last; ++i)
361 fixed_regs[i] = call_used_regs[i] = 1;
370 /* Check if all floating point registers have been fixed. */
371 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
376 target_flags |= MASK_DISABLE_FPREGS;
380 override_options (void)
382 if (pa_cpu_string == NULL)
383 pa_cpu_string = TARGET_SCHED_DEFAULT;
385 if (! strcmp (pa_cpu_string, "8000"))
387 pa_cpu_string = "8000";
388 pa_cpu = PROCESSOR_8000;
390 else if (! strcmp (pa_cpu_string, "7100"))
392 pa_cpu_string = "7100";
393 pa_cpu = PROCESSOR_7100;
395 else if (! strcmp (pa_cpu_string, "700"))
397 pa_cpu_string = "700";
398 pa_cpu = PROCESSOR_700;
400 else if (! strcmp (pa_cpu_string, "7100LC"))
402 pa_cpu_string = "7100LC";
403 pa_cpu = PROCESSOR_7100LC;
405 else if (! strcmp (pa_cpu_string, "7200"))
407 pa_cpu_string = "7200";
408 pa_cpu = PROCESSOR_7200;
410 else if (! strcmp (pa_cpu_string, "7300"))
412 pa_cpu_string = "7300";
413 pa_cpu = PROCESSOR_7300;
417 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
420 /* Set the instruction architecture. */
421 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
423 pa_arch_string = "1.0";
424 pa_arch = ARCHITECTURE_10;
425 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
427 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
429 pa_arch_string = "1.1";
430 pa_arch = ARCHITECTURE_11;
431 target_flags &= ~MASK_PA_20;
432 target_flags |= MASK_PA_11;
434 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
436 pa_arch_string = "2.0";
437 pa_arch = ARCHITECTURE_20;
438 target_flags |= MASK_PA_11 | MASK_PA_20;
440 else if (pa_arch_string)
442 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
447 /* Set the default UNIX standard for HP-UX. This affects the
448 predefines and startfiles used for the target. */
449 if (pa_unix_string == NULL)
451 = TARGET_HPUX_11_11 ? "98" : (TARGET_HPUX_10_10 ? "95" : "93");
453 if (!strcmp (pa_unix_string, "93"))
455 else if (!strcmp (pa_unix_string, "95"))
457 else if (TARGET_HPUX_11_11)
459 if (!strcmp (pa_unix_string, "98"))
462 warning ("unknown -munix= option (%s).\n"
463 "Valid options are 93, 95 and 98.\n",
466 else if (TARGET_HPUX_10_10)
467 warning ("unknown -munix= option (%s)."
468 "\nValid options are 93 and 95.\n",
471 warning ("unknown -munix= option (%s).\nValid option is 93.\n",
475 if (pa_fixed_range_string)
476 fix_range (pa_fixed_range_string);
478 /* Unconditional branches in the delay slot are not compatible with dwarf2
479 call frame information. There is no benefit in using this optimization
480 on PA8000 and later processors. */
481 if (pa_cpu >= PROCESSOR_8000
482 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
483 || flag_unwind_tables)
484 target_flags &= ~MASK_JUMP_IN_DELAY;
486 if (flag_pic && TARGET_PORTABLE_RUNTIME)
488 warning ("PIC code generation is not supported in the portable runtime model\n");
491 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
493 warning ("PIC code generation is not compatible with fast indirect calls\n");
496 if (! TARGET_GAS && write_symbols != NO_DEBUG)
498 warning ("-g is only supported when using GAS on this processor,");
499 warning ("-g option disabled");
500 write_symbols = NO_DEBUG;
503 /* We only support the "big PIC" model now. And we always generate PIC
504 code when in 64bit mode. */
505 if (flag_pic == 1 || TARGET_64BIT)
508 /* We can't guarantee that .dword is available for 32-bit targets. */
509 if (UNITS_PER_WORD == 4)
510 targetm.asm_out.aligned_op.di = NULL;
512 /* The unaligned ops are only available when using GAS. */
515 targetm.asm_out.unaligned_op.hi = NULL;
516 targetm.asm_out.unaligned_op.si = NULL;
517 targetm.asm_out.unaligned_op.di = NULL;
520 init_machine_status = pa_init_machine_status;
524 pa_init_builtins (void)
526 #ifdef DONT_HAVE_FPUTC_UNLOCKED
527 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
528 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
532 /* Function to init struct machine_function.
533 This will be called, via a pointer variable,
534 from push_function_context. */
536 static struct machine_function *
537 pa_init_machine_status (void)
539 return ggc_alloc_cleared (sizeof (machine_function));
542 /* If FROM is a probable pointer register, mark TO as a probable
543 pointer register with the same pointer alignment as FROM. */
546 copy_reg_pointer (rtx to, rtx from)
548 if (REG_POINTER (from))
549 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
552 /* Return 1 if X contains a symbolic expression. We know these
553 expressions will have one of a few well defined forms, so
554 we need only check those forms. */
556 symbolic_expression_p (rtx x)
559 /* Strip off any HIGH. */
560 if (GET_CODE (x) == HIGH)
563 return (symbolic_operand (x, VOIDmode));
566 /* Accept any constant that can be moved in one instruction into a
569 cint_ok_for_move (HOST_WIDE_INT intval)
571 /* OK if ldo, ldil, or zdepi, can be used. */
572 return (CONST_OK_FOR_LETTER_P (intval, 'J')
573 || CONST_OK_FOR_LETTER_P (intval, 'N')
574 || CONST_OK_FOR_LETTER_P (intval, 'K'));
577 /* Return truth value of whether OP can be used as an operand in a
580 adddi3_operand (rtx op, enum machine_mode mode)
582 return (register_operand (op, mode)
583 || (GET_CODE (op) == CONST_INT
584 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
587 /* True iff zdepi can be used to generate this CONST_INT.
588 zdepi first sign extends a 5 bit signed number to a given field
589 length, then places this field anywhere in a zero. */
591 zdepi_cint_p (unsigned HOST_WIDE_INT x)
593 unsigned HOST_WIDE_INT lsb_mask, t;
595 /* This might not be obvious, but it's at least fast.
596 This function is critical; we don't have the time loops would take. */
598 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
599 /* Return true iff t is a power of two. */
600 return ((t & (t - 1)) == 0);
603 /* True iff depi or extru can be used to compute (reg & mask).
604 Accept bit pattern like these:
609 and_mask_p (unsigned HOST_WIDE_INT mask)
612 mask += mask & -mask;
613 return (mask & (mask - 1)) == 0;
616 /* True iff depi can be used to compute (reg | MASK). */
618 ior_mask_p (unsigned HOST_WIDE_INT mask)
620 mask += mask & -mask;
621 return (mask & (mask - 1)) == 0;
624 /* Legitimize PIC addresses. If the address is already
625 position-independent, we return ORIG. Newly generated
626 position-independent addresses go to REG. If we need more
627 than one register, we lose. */
630 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
634 /* Labels need special handling. */
635 if (pic_label_operand (orig, mode))
637 /* We do not want to go through the movXX expanders here since that
638 would create recursion.
640 Nor do we really want to call a generator for a named pattern
641 since that requires multiple patterns if we want to support
644 So instead we just emit the raw set, which avoids the movXX
645 expanders completely. */
646 mark_reg_pointer (reg, BITS_PER_UNIT);
647 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
648 current_function_uses_pic_offset_table = 1;
651 if (GET_CODE (orig) == SYMBOL_REF)
658 /* Before reload, allocate a temporary register for the intermediate
659 result. This allows the sequence to be deleted when the final
660 result is unused and the insns are trivially dead. */
661 tmp_reg = ((reload_in_progress || reload_completed)
662 ? reg : gen_reg_rtx (Pmode));
664 emit_move_insn (tmp_reg,
665 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
666 gen_rtx_HIGH (word_mode, orig)));
668 = gen_const_mem (Pmode,
669 gen_rtx_LO_SUM (Pmode, tmp_reg,
670 gen_rtx_UNSPEC (Pmode,
674 current_function_uses_pic_offset_table = 1;
675 mark_reg_pointer (reg, BITS_PER_UNIT);
676 insn = emit_move_insn (reg, pic_ref);
678 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
679 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
683 else if (GET_CODE (orig) == CONST)
687 if (GET_CODE (XEXP (orig, 0)) == PLUS
688 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
694 if (GET_CODE (XEXP (orig, 0)) == PLUS)
696 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
697 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
698 base == reg ? 0 : reg);
703 if (GET_CODE (orig) == CONST_INT)
705 if (INT_14_BITS (orig))
706 return plus_constant (base, INTVAL (orig));
707 orig = force_reg (Pmode, orig);
709 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
710 /* Likewise, should we set special REG_NOTEs here? */
716 /* Try machine-dependent ways of modifying an illegitimate address
717 to be legitimate. If we find one, return the new, valid address.
718 This macro is used in only one place: `memory_address' in explow.c.
720 OLDX is the address as it was before break_out_memory_refs was called.
721 In some cases it is useful to look at this to decide what needs to be done.
723 MODE and WIN are passed so that this macro can use
724 GO_IF_LEGITIMATE_ADDRESS.
726 It is always safe for this macro to do nothing. It exists to recognize
727 opportunities to optimize the output.
729 For the PA, transform:
731 memory(X + <large int>)
735 if (<large int> & mask) >= 16
736 Y = (<large int> & ~mask) + mask + 1 Round up.
738 Y = (<large int> & ~mask) Round down.
740 memory (Z + (<large int> - Y));
742 This is for CSE to find several similar references, and only use one Z.
744 X can either be a SYMBOL_REF or REG, but because combine cannot
745 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
746 D will not fit in 14 bits.
748 MODE_FLOAT references allow displacements which fit in 5 bits, so use
751 MODE_INT references allow displacements which fit in 14 bits, so use
754 This relies on the fact that most mode MODE_FLOAT references will use FP
755 registers and most mode MODE_INT references will use integer registers.
756 (In the rare case of an FP register used in an integer MODE, we depend
757 on secondary reloads to clean things up.)
760 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
761 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
762 addressing modes to be used).
764 Put X and Z into registers. Then put the entire expression into
768 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
769 enum machine_mode mode)
773 /* We need to canonicalize the order of operands in unscaled indexed
774 addresses since the code that checks if an address is valid doesn't
775 always try both orders. */
776 if (!TARGET_NO_SPACE_REGS
777 && GET_CODE (x) == PLUS
778 && GET_MODE (x) == Pmode
779 && REG_P (XEXP (x, 0))
780 && REG_P (XEXP (x, 1))
781 && REG_POINTER (XEXP (x, 0))
782 && !REG_POINTER (XEXP (x, 1)))
783 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
786 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
788 /* Strip off CONST. */
789 if (GET_CODE (x) == CONST)
792 /* Special case. Get the SYMBOL_REF into a register and use indexing.
793 That should always be safe. */
794 if (GET_CODE (x) == PLUS
795 && GET_CODE (XEXP (x, 0)) == REG
796 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
798 rtx reg = force_reg (Pmode, XEXP (x, 1));
799 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
802 /* Note we must reject symbols which represent function addresses
803 since the assembler/linker can't handle arithmetic on plabels. */
804 if (GET_CODE (x) == PLUS
805 && GET_CODE (XEXP (x, 1)) == CONST_INT
806 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
807 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
808 || GET_CODE (XEXP (x, 0)) == REG))
810 rtx int_part, ptr_reg;
812 int offset = INTVAL (XEXP (x, 1));
815 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
816 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
818 /* Choose which way to round the offset. Round up if we
819 are >= halfway to the next boundary. */
820 if ((offset & mask) >= ((mask + 1) / 2))
821 newoffset = (offset & ~ mask) + mask + 1;
823 newoffset = (offset & ~ mask);
825 /* If the newoffset will not fit in 14 bits (ldo), then
826 handling this would take 4 or 5 instructions (2 to load
827 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
828 add the new offset and the SYMBOL_REF.) Combine can
829 not handle 4->2 or 5->2 combinations, so do not create
831 if (! VAL_14_BITS_P (newoffset)
832 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
834 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
837 gen_rtx_HIGH (Pmode, const_part));
840 gen_rtx_LO_SUM (Pmode,
841 tmp_reg, const_part));
845 if (! VAL_14_BITS_P (newoffset))
846 int_part = force_reg (Pmode, GEN_INT (newoffset));
848 int_part = GEN_INT (newoffset);
850 ptr_reg = force_reg (Pmode,
852 force_reg (Pmode, XEXP (x, 0)),
855 return plus_constant (ptr_reg, offset - newoffset);
858 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
860 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
861 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
862 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
863 && (OBJECT_P (XEXP (x, 1))
864 || GET_CODE (XEXP (x, 1)) == SUBREG)
865 && GET_CODE (XEXP (x, 1)) != CONST)
867 int val = INTVAL (XEXP (XEXP (x, 0), 1));
871 if (GET_CODE (reg1) != REG)
872 reg1 = force_reg (Pmode, force_operand (reg1, 0));
874 reg2 = XEXP (XEXP (x, 0), 0);
875 if (GET_CODE (reg2) != REG)
876 reg2 = force_reg (Pmode, force_operand (reg2, 0));
878 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
885 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
887 Only do so for floating point modes since this is more speculative
888 and we lose if it's an integer store. */
889 if (GET_CODE (x) == PLUS
890 && GET_CODE (XEXP (x, 0)) == PLUS
891 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
892 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
893 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
894 && (mode == SFmode || mode == DFmode))
897 /* First, try and figure out what to use as a base register. */
898 rtx reg1, reg2, base, idx, orig_base;
900 reg1 = XEXP (XEXP (x, 0), 1);
905 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
906 then emit_move_sequence will turn on REG_POINTER so we'll know
907 it's a base register below. */
908 if (GET_CODE (reg1) != REG)
909 reg1 = force_reg (Pmode, force_operand (reg1, 0));
911 if (GET_CODE (reg2) != REG)
912 reg2 = force_reg (Pmode, force_operand (reg2, 0));
914 /* Figure out what the base and index are. */
916 if (GET_CODE (reg1) == REG
917 && REG_POINTER (reg1))
920 orig_base = XEXP (XEXP (x, 0), 1);
921 idx = gen_rtx_PLUS (Pmode,
923 XEXP (XEXP (XEXP (x, 0), 0), 0),
924 XEXP (XEXP (XEXP (x, 0), 0), 1)),
927 else if (GET_CODE (reg2) == REG
928 && REG_POINTER (reg2))
931 orig_base = XEXP (x, 1);
938 /* If the index adds a large constant, try to scale the
939 constant so that it can be loaded with only one insn. */
940 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
941 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
942 / INTVAL (XEXP (XEXP (idx, 0), 1)))
943 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
945 /* Divide the CONST_INT by the scale factor, then add it to A. */
946 int val = INTVAL (XEXP (idx, 1));
948 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
949 reg1 = XEXP (XEXP (idx, 0), 0);
950 if (GET_CODE (reg1) != REG)
951 reg1 = force_reg (Pmode, force_operand (reg1, 0));
953 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
955 /* We can now generate a simple scaled indexed address. */
958 (Pmode, gen_rtx_PLUS (Pmode,
959 gen_rtx_MULT (Pmode, reg1,
960 XEXP (XEXP (idx, 0), 1)),
964 /* If B + C is still a valid base register, then add them. */
965 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
966 && INTVAL (XEXP (idx, 1)) <= 4096
967 && INTVAL (XEXP (idx, 1)) >= -4096)
969 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
972 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
974 reg2 = XEXP (XEXP (idx, 0), 0);
975 if (GET_CODE (reg2) != CONST_INT)
976 reg2 = force_reg (Pmode, force_operand (reg2, 0));
978 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
985 /* Get the index into a register, then add the base + index and
986 return a register holding the result. */
988 /* First get A into a register. */
989 reg1 = XEXP (XEXP (idx, 0), 0);
990 if (GET_CODE (reg1) != REG)
991 reg1 = force_reg (Pmode, force_operand (reg1, 0));
993 /* And get B into a register. */
994 reg2 = XEXP (idx, 1);
995 if (GET_CODE (reg2) != REG)
996 reg2 = force_reg (Pmode, force_operand (reg2, 0));
998 reg1 = force_reg (Pmode,
1000 gen_rtx_MULT (Pmode, reg1,
1001 XEXP (XEXP (idx, 0), 1)),
1004 /* Add the result to our base register and return. */
1005 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1009 /* Uh-oh. We might have an address for x[n-100000]. This needs
1010 special handling to avoid creating an indexed memory address
1011 with x-100000 as the base.
1013 If the constant part is small enough, then it's still safe because
1014 there is a guard page at the beginning and end of the data segment.
1016 Scaled references are common enough that we want to try and rearrange the
1017 terms so that we can use indexing for these addresses too. Only
1018 do the optimization for floatint point modes. */
1020 if (GET_CODE (x) == PLUS
1021 && symbolic_expression_p (XEXP (x, 1)))
1023 /* Ugly. We modify things here so that the address offset specified
1024 by the index expression is computed first, then added to x to form
1025 the entire address. */
1027 rtx regx1, regx2, regy1, regy2, y;
1029 /* Strip off any CONST. */
1031 if (GET_CODE (y) == CONST)
1034 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1036 /* See if this looks like
1037 (plus (mult (reg) (shadd_const))
1038 (const (plus (symbol_ref) (const_int))))
1040 Where const_int is small. In that case the const
1041 expression is a valid pointer for indexing.
1043 If const_int is big, but can be divided evenly by shadd_const
1044 and added to (reg). This allows more scaled indexed addresses. */
1045 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1046 && GET_CODE (XEXP (x, 0)) == MULT
1047 && GET_CODE (XEXP (y, 1)) == CONST_INT
1048 && INTVAL (XEXP (y, 1)) >= -4096
1049 && INTVAL (XEXP (y, 1)) <= 4095
1050 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1051 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1053 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1057 if (GET_CODE (reg1) != REG)
1058 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1060 reg2 = XEXP (XEXP (x, 0), 0);
1061 if (GET_CODE (reg2) != REG)
1062 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1064 return force_reg (Pmode,
1065 gen_rtx_PLUS (Pmode,
1066 gen_rtx_MULT (Pmode,
1071 else if ((mode == DFmode || mode == SFmode)
1072 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1073 && GET_CODE (XEXP (x, 0)) == MULT
1074 && GET_CODE (XEXP (y, 1)) == CONST_INT
1075 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1076 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1077 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1080 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1081 / INTVAL (XEXP (XEXP (x, 0), 1))));
1082 regx2 = XEXP (XEXP (x, 0), 0);
1083 if (GET_CODE (regx2) != REG)
1084 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1085 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1089 gen_rtx_PLUS (Pmode,
1090 gen_rtx_MULT (Pmode, regx2,
1091 XEXP (XEXP (x, 0), 1)),
1092 force_reg (Pmode, XEXP (y, 0))));
1094 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1095 && INTVAL (XEXP (y, 1)) >= -4096
1096 && INTVAL (XEXP (y, 1)) <= 4095)
1098 /* This is safe because of the guard page at the
1099 beginning and end of the data space. Just
1100 return the original address. */
1105 /* Doesn't look like one we can optimize. */
1106 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1107 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1108 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1109 regx1 = force_reg (Pmode,
1110 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1112 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1120 /* For the HPPA, REG and REG+CONST is cost 0
1121 and addresses involving symbolic constants are cost 2.
1123 PIC addresses are very expensive.
1125 It is no coincidence that this has the same structure
1126 as GO_IF_LEGITIMATE_ADDRESS. */
1129 hppa_address_cost (rtx X)
1131 switch (GET_CODE (X))
1144 /* Compute a (partial) cost for rtx X. Return true if the complete
1145 cost has been computed, and false if subexpressions should be
1146 scanned. In either case, *TOTAL contains the cost result. */
1149 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1154 if (INTVAL (x) == 0)
1156 else if (INT_14_BITS (x))
1173 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1174 && outer_code != SET)
1181 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1182 *total = COSTS_N_INSNS (3);
1183 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1184 *total = COSTS_N_INSNS (8);
1186 *total = COSTS_N_INSNS (20);
1190 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1192 *total = COSTS_N_INSNS (14);
1200 *total = COSTS_N_INSNS (60);
1203 case PLUS: /* this includes shNadd insns */
1205 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1206 *total = COSTS_N_INSNS (3);
1208 *total = COSTS_N_INSNS (1);
1214 *total = COSTS_N_INSNS (1);
1222 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1223 new rtx with the correct mode. */
1225 force_mode (enum machine_mode mode, rtx orig)
1227 if (mode == GET_MODE (orig))
1230 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1233 return gen_rtx_REG (mode, REGNO (orig));
1236 /* Emit insns to move operands[1] into operands[0].
1238 Return 1 if we have written out everything that needs to be done to
1239 do the move. Otherwise, return 0 and the caller will emit the move
1242 Note SCRATCH_REG may not be in the proper mode depending on how it
1243 will be used. This routine is responsible for creating a new copy
1244 of SCRATCH_REG in the proper mode. */
1247 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1249 register rtx operand0 = operands[0];
1250 register rtx operand1 = operands[1];
1253 /* We can only handle indexed addresses in the destination operand
1254 of floating point stores. Thus, we need to break out indexed
1255 addresses from the destination operand. */
1256 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1258 /* This is only safe up to the beginning of life analysis. */
1262 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1263 operand0 = replace_equiv_address (operand0, tem);
1266 /* On targets with non-equivalent space registers, break out unscaled
1267 indexed addresses from the source operand before the final CSE.
1268 We have to do this because the REG_POINTER flag is not correctly
1269 carried through various optimization passes and CSE may substitute
1270 a pseudo without the pointer set for one with the pointer set. As
1271 a result, we loose various opportunities to create insns with
1272 unscaled indexed addresses. */
1273 if (!TARGET_NO_SPACE_REGS
1274 && !cse_not_expected
1275 && GET_CODE (operand1) == MEM
1276 && GET_CODE (XEXP (operand1, 0)) == PLUS
1277 && REG_P (XEXP (XEXP (operand1, 0), 0))
1278 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1280 = replace_equiv_address (operand1,
1281 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1284 && reload_in_progress && GET_CODE (operand0) == REG
1285 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1286 operand0 = reg_equiv_mem[REGNO (operand0)];
1287 else if (scratch_reg
1288 && reload_in_progress && GET_CODE (operand0) == SUBREG
1289 && GET_CODE (SUBREG_REG (operand0)) == REG
1290 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1292 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1293 the code which tracks sets/uses for delete_output_reload. */
1294 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1295 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1296 SUBREG_BYTE (operand0));
1297 operand0 = alter_subreg (&temp);
1301 && reload_in_progress && GET_CODE (operand1) == REG
1302 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1303 operand1 = reg_equiv_mem[REGNO (operand1)];
1304 else if (scratch_reg
1305 && reload_in_progress && GET_CODE (operand1) == SUBREG
1306 && GET_CODE (SUBREG_REG (operand1)) == REG
1307 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1309 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1310 the code which tracks sets/uses for delete_output_reload. */
1311 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1312 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1313 SUBREG_BYTE (operand1));
1314 operand1 = alter_subreg (&temp);
1317 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1318 && ((tem = find_replacement (&XEXP (operand0, 0)))
1319 != XEXP (operand0, 0)))
1320 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1322 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1323 && ((tem = find_replacement (&XEXP (operand1, 0)))
1324 != XEXP (operand1, 0)))
1325 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1327 /* Handle secondary reloads for loads/stores of FP registers from
1328 REG+D addresses where D does not fit in 5 or 14 bits, including
1329 (subreg (mem (addr))) cases. */
1331 && fp_reg_operand (operand0, mode)
1332 && ((GET_CODE (operand1) == MEM
1333 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1334 XEXP (operand1, 0)))
1335 || ((GET_CODE (operand1) == SUBREG
1336 && GET_CODE (XEXP (operand1, 0)) == MEM
1337 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1339 XEXP (XEXP (operand1, 0), 0))))))
1341 if (GET_CODE (operand1) == SUBREG)
1342 operand1 = XEXP (operand1, 0);
1344 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1345 it in WORD_MODE regardless of what mode it was originally given
1347 scratch_reg = force_mode (word_mode, scratch_reg);
1349 /* D might not fit in 14 bits either; for such cases load D into
1351 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1353 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1354 emit_move_insn (scratch_reg,
1355 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1357 XEXP (XEXP (operand1, 0), 0),
1361 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1362 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1363 gen_rtx_MEM (mode, scratch_reg)));
1366 else if (scratch_reg
1367 && fp_reg_operand (operand1, mode)
1368 && ((GET_CODE (operand0) == MEM
1369 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1371 XEXP (operand0, 0)))
1372 || ((GET_CODE (operand0) == SUBREG)
1373 && GET_CODE (XEXP (operand0, 0)) == MEM
1374 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1376 XEXP (XEXP (operand0, 0), 0)))))
1378 if (GET_CODE (operand0) == SUBREG)
1379 operand0 = XEXP (operand0, 0);
1381 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1382 it in WORD_MODE regardless of what mode it was originally given
1384 scratch_reg = force_mode (word_mode, scratch_reg);
1386 /* D might not fit in 14 bits either; for such cases load D into
1388 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1390 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1391 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1394 XEXP (XEXP (operand0, 0),
1399 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1400 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1404 /* Handle secondary reloads for loads of FP registers from constant
1405 expressions by forcing the constant into memory.
1407 Use scratch_reg to hold the address of the memory location.
1409 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1410 NO_REGS when presented with a const_int and a register class
1411 containing only FP registers. Doing so unfortunately creates
1412 more problems than it solves. Fix this for 2.5. */
1413 else if (scratch_reg
1414 && CONSTANT_P (operand1)
1415 && fp_reg_operand (operand0, mode))
1419 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1420 it in WORD_MODE regardless of what mode it was originally given
1422 scratch_reg = force_mode (word_mode, scratch_reg);
1424 /* Force the constant into memory and put the address of the
1425 memory location into scratch_reg. */
1426 xoperands[0] = scratch_reg;
1427 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1428 emit_move_sequence (xoperands, Pmode, 0);
1430 /* Now load the destination register. */
1431 emit_insn (gen_rtx_SET (mode, operand0,
1432 gen_rtx_MEM (mode, scratch_reg)));
1435 /* Handle secondary reloads for SAR. These occur when trying to load
1436 the SAR from memory, FP register, or with a constant. */
1437 else if (scratch_reg
1438 && GET_CODE (operand0) == REG
1439 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1440 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1441 && (GET_CODE (operand1) == MEM
1442 || GET_CODE (operand1) == CONST_INT
1443 || (GET_CODE (operand1) == REG
1444 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1446 /* D might not fit in 14 bits either; for such cases load D into
1448 if (GET_CODE (operand1) == MEM
1449 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1451 /* We are reloading the address into the scratch register, so we
1452 want to make sure the scratch register is a full register. */
1453 scratch_reg = force_mode (word_mode, scratch_reg);
1455 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1456 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1459 XEXP (XEXP (operand1, 0),
1463 /* Now we are going to load the scratch register from memory,
1464 we want to load it in the same width as the original MEM,
1465 which must be the same as the width of the ultimate destination,
1467 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1469 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1474 /* We want to load the scratch register using the same mode as
1475 the ultimate destination. */
1476 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1478 emit_move_insn (scratch_reg, operand1);
1481 /* And emit the insn to set the ultimate destination. We know that
1482 the scratch register has the same mode as the destination at this
1484 emit_move_insn (operand0, scratch_reg);
1487 /* Handle the most common case: storing into a register. */
1488 else if (register_operand (operand0, mode))
1490 if (register_operand (operand1, mode)
1491 || (GET_CODE (operand1) == CONST_INT
1492 && cint_ok_for_move (INTVAL (operand1)))
1493 || (operand1 == CONST0_RTX (mode))
1494 || (GET_CODE (operand1) == HIGH
1495 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1496 /* Only `general_operands' can come here, so MEM is ok. */
1497 || GET_CODE (operand1) == MEM)
1499 /* Various sets are created during RTL generation which don't
1500 have the REG_POINTER flag correctly set. After the CSE pass,
1501 instruction recognition can fail if we don't consistently
1502 set this flag when performing register copies. This should
1503 also improve the opportunities for creating insns that use
1504 unscaled indexing. */
1505 if (REG_P (operand0) && REG_P (operand1))
1507 if (REG_POINTER (operand1)
1508 && !REG_POINTER (operand0)
1509 && !HARD_REGISTER_P (operand0))
1510 copy_reg_pointer (operand0, operand1);
1511 else if (REG_POINTER (operand0)
1512 && !REG_POINTER (operand1)
1513 && !HARD_REGISTER_P (operand1))
1514 copy_reg_pointer (operand1, operand0);
1517 /* When MEMs are broken out, the REG_POINTER flag doesn't
1518 get set. In some cases, we can set the REG_POINTER flag
1519 from the declaration for the MEM. */
1520 if (REG_P (operand0)
1521 && GET_CODE (operand1) == MEM
1522 && !REG_POINTER (operand0))
1524 tree decl = MEM_EXPR (operand1);
1526 /* Set the register pointer flag and register alignment
1527 if the declaration for this memory reference is a
1528 pointer type. Fortran indirect argument references
1531 && !(flag_argument_noalias > 1
1532 && TREE_CODE (decl) == INDIRECT_REF
1533 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1537 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1539 if (TREE_CODE (decl) == COMPONENT_REF)
1540 decl = TREE_OPERAND (decl, 1);
1542 type = TREE_TYPE (decl);
1543 if (TREE_CODE (type) == ARRAY_TYPE)
1544 type = get_inner_array_type (type);
1546 if (POINTER_TYPE_P (type))
1550 type = TREE_TYPE (type);
1551 /* Using TYPE_ALIGN_OK is rather conservative as
1552 only the ada frontend actually sets it. */
1553 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1555 mark_reg_pointer (operand0, align);
1560 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1564 else if (GET_CODE (operand0) == MEM)
1566 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1567 && !(reload_in_progress || reload_completed))
1569 rtx temp = gen_reg_rtx (DFmode);
1571 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1572 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1575 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1577 /* Run this case quickly. */
1578 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1581 if (! (reload_in_progress || reload_completed))
1583 operands[0] = validize_mem (operand0);
1584 operands[1] = operand1 = force_reg (mode, operand1);
1588 /* Simplify the source if we need to.
1589 Note we do have to handle function labels here, even though we do
1590 not consider them legitimate constants. Loop optimizations can
1591 call the emit_move_xxx with one as a source. */
1592 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1593 || function_label_operand (operand1, mode)
1594 || (GET_CODE (operand1) == HIGH
1595 && symbolic_operand (XEXP (operand1, 0), mode)))
1599 if (GET_CODE (operand1) == HIGH)
1602 operand1 = XEXP (operand1, 0);
1604 if (symbolic_operand (operand1, mode))
1606 /* Argh. The assembler and linker can't handle arithmetic
1609 So we force the plabel into memory, load operand0 from
1610 the memory location, then add in the constant part. */
1611 if ((GET_CODE (operand1) == CONST
1612 && GET_CODE (XEXP (operand1, 0)) == PLUS
1613 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1614 || function_label_operand (operand1, mode))
1616 rtx temp, const_part;
1618 /* Figure out what (if any) scratch register to use. */
1619 if (reload_in_progress || reload_completed)
1621 scratch_reg = scratch_reg ? scratch_reg : operand0;
1622 /* SCRATCH_REG will hold an address and maybe the actual
1623 data. We want it in WORD_MODE regardless of what mode it
1624 was originally given to us. */
1625 scratch_reg = force_mode (word_mode, scratch_reg);
1628 scratch_reg = gen_reg_rtx (Pmode);
1630 if (GET_CODE (operand1) == CONST)
1632 /* Save away the constant part of the expression. */
1633 const_part = XEXP (XEXP (operand1, 0), 1);
1634 if (GET_CODE (const_part) != CONST_INT)
1637 /* Force the function label into memory. */
1638 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1642 /* No constant part. */
1643 const_part = NULL_RTX;
1645 /* Force the function label into memory. */
1646 temp = force_const_mem (mode, operand1);
1650 /* Get the address of the memory location. PIC-ify it if
1652 temp = XEXP (temp, 0);
1654 temp = legitimize_pic_address (temp, mode, scratch_reg);
1656 /* Put the address of the memory location into our destination
1659 emit_move_sequence (operands, mode, scratch_reg);
1661 /* Now load from the memory location into our destination
1663 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1664 emit_move_sequence (operands, mode, scratch_reg);
1666 /* And add back in the constant part. */
1667 if (const_part != NULL_RTX)
1668 expand_inc (operand0, const_part);
1677 if (reload_in_progress || reload_completed)
1679 temp = scratch_reg ? scratch_reg : operand0;
1680 /* TEMP will hold an address and maybe the actual
1681 data. We want it in WORD_MODE regardless of what mode it
1682 was originally given to us. */
1683 temp = force_mode (word_mode, temp);
1686 temp = gen_reg_rtx (Pmode);
1688 /* (const (plus (symbol) (const_int))) must be forced to
1689 memory during/after reload if the const_int will not fit
1691 if (GET_CODE (operand1) == CONST
1692 && GET_CODE (XEXP (operand1, 0)) == PLUS
1693 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1694 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1695 && (reload_completed || reload_in_progress)
1698 operands[1] = force_const_mem (mode, operand1);
1699 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1701 operands[1] = gen_rtx_MEM (mode, operands[1]);
1702 emit_move_sequence (operands, mode, temp);
1706 operands[1] = legitimize_pic_address (operand1, mode, temp);
1707 if (REG_P (operand0) && REG_P (operands[1]))
1708 copy_reg_pointer (operand0, operands[1]);
1709 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1712 /* On the HPPA, references to data space are supposed to use dp,
1713 register 27, but showing it in the RTL inhibits various cse
1714 and loop optimizations. */
1719 if (reload_in_progress || reload_completed)
1721 temp = scratch_reg ? scratch_reg : operand0;
1722 /* TEMP will hold an address and maybe the actual
1723 data. We want it in WORD_MODE regardless of what mode it
1724 was originally given to us. */
1725 temp = force_mode (word_mode, temp);
1728 temp = gen_reg_rtx (mode);
1730 /* Loading a SYMBOL_REF into a register makes that register
1731 safe to be used as the base in an indexed address.
1733 Don't mark hard registers though. That loses. */
1734 if (GET_CODE (operand0) == REG
1735 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1736 mark_reg_pointer (operand0, BITS_PER_UNIT);
1737 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1738 mark_reg_pointer (temp, BITS_PER_UNIT);
1741 set = gen_rtx_SET (mode, operand0, temp);
1743 set = gen_rtx_SET (VOIDmode,
1745 gen_rtx_LO_SUM (mode, temp, operand1));
1747 emit_insn (gen_rtx_SET (VOIDmode,
1749 gen_rtx_HIGH (mode, operand1)));
1755 else if (GET_CODE (operand1) != CONST_INT
1756 || !cint_ok_for_move (INTVAL (operand1)))
1760 HOST_WIDE_INT value = 0;
1761 HOST_WIDE_INT insv = 0;
1764 if (GET_CODE (operand1) == CONST_INT)
1765 value = INTVAL (operand1);
1768 && GET_CODE (operand1) == CONST_INT
1769 && HOST_BITS_PER_WIDE_INT > 32
1770 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1774 /* Extract the low order 32 bits of the value and sign extend.
1775 If the new value is the same as the original value, we can
1776 can use the original value as-is. If the new value is
1777 different, we use it and insert the most-significant 32-bits
1778 of the original value into the final result. */
1779 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1780 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1783 #if HOST_BITS_PER_WIDE_INT > 32
1784 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1788 operand1 = GEN_INT (nval);
1792 if (reload_in_progress || reload_completed)
1793 temp = scratch_reg ? scratch_reg : operand0;
1795 temp = gen_reg_rtx (mode);
1797 /* We don't directly split DImode constants on 32-bit targets
1798 because PLUS uses an 11-bit immediate and the insn sequence
1799 generated is not as efficient as the one using HIGH/LO_SUM. */
1800 if (GET_CODE (operand1) == CONST_INT
1801 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1804 /* Directly break constant into high and low parts. This
1805 provides better optimization opportunities because various
1806 passes recognize constants split with PLUS but not LO_SUM.
1807 We use a 14-bit signed low part except when the addition
1808 of 0x4000 to the high part might change the sign of the
1810 HOST_WIDE_INT low = value & 0x3fff;
1811 HOST_WIDE_INT high = value & ~ 0x3fff;
1815 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1823 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1824 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1828 emit_insn (gen_rtx_SET (VOIDmode, temp,
1829 gen_rtx_HIGH (mode, operand1)));
1830 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1833 insn = emit_move_insn (operands[0], operands[1]);
1835 /* Now insert the most significant 32 bits of the value
1836 into the register. When we don't have a second register
1837 available, it could take up to nine instructions to load
1838 a 64-bit integer constant. Prior to reload, we force
1839 constants that would take more than three instructions
1840 to load to the constant pool. During and after reload,
1841 we have to handle all possible values. */
1844 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
1845 register and the value to be inserted is outside the
1846 range that can be loaded with three depdi instructions. */
1847 if (temp != operand0 && (insv >= 16384 || insv < -16384))
1849 operand1 = GEN_INT (insv);
1851 emit_insn (gen_rtx_SET (VOIDmode, temp,
1852 gen_rtx_HIGH (mode, operand1)));
1853 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
1854 emit_insn (gen_insv (operand0, GEN_INT (32),
1859 int len = 5, pos = 27;
1861 /* Insert the bits using the depdi instruction. */
1864 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
1865 HOST_WIDE_INT sign = v5 < 0;
1867 /* Left extend the insertion. */
1868 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
1869 while (pos > 0 && (insv & 1) == sign)
1871 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
1876 emit_insn (gen_insv (operand0, GEN_INT (len),
1877 GEN_INT (pos), GEN_INT (v5)));
1879 len = pos > 0 && pos < 5 ? pos : 5;
1886 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
1891 /* Now have insn-emit do whatever it normally does. */
1895 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1896 it will need a link/runtime reloc). */
1899 reloc_needed (tree exp)
1903 switch (TREE_CODE (exp))
1910 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1911 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1916 case NON_LVALUE_EXPR:
1917 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1923 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1924 if (TREE_VALUE (link) != 0)
1925 reloc |= reloc_needed (TREE_VALUE (link));
1938 /* Does operand (which is a symbolic_operand) live in text space?
1939 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1943 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
1945 if (GET_CODE (operand) == CONST)
1946 operand = XEXP (XEXP (operand, 0), 0);
1949 if (GET_CODE (operand) == SYMBOL_REF)
1950 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1954 if (GET_CODE (operand) == SYMBOL_REF)
1955 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1961 /* Return the best assembler insn template
1962 for moving operands[1] into operands[0] as a fullword. */
1964 singlemove_string (rtx *operands)
1966 HOST_WIDE_INT intval;
1968 if (GET_CODE (operands[0]) == MEM)
1969 return "stw %r1,%0";
1970 if (GET_CODE (operands[1]) == MEM)
1972 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1977 if (GET_MODE (operands[1]) != SFmode)
1980 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1982 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1983 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1985 operands[1] = GEN_INT (i);
1986 /* Fall through to CONST_INT case. */
1988 if (GET_CODE (operands[1]) == CONST_INT)
1990 intval = INTVAL (operands[1]);
1992 if (VAL_14_BITS_P (intval))
1994 else if ((intval & 0x7ff) == 0)
1995 return "ldil L'%1,%0";
1996 else if (zdepi_cint_p (intval))
1997 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1999 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2001 return "copy %1,%0";
2005 /* Compute position (in OP[1]) and width (in OP[2])
2006 useful for copying IMM to a register using the zdepi
2007 instructions. Store the immediate value to insert in OP[0]. */
2009 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2013 /* Find the least significant set bit in IMM. */
2014 for (lsb = 0; lsb < 32; lsb++)
2021 /* Choose variants based on *sign* of the 5-bit field. */
2022 if ((imm & 0x10) == 0)
2023 len = (lsb <= 28) ? 4 : 32 - lsb;
2026 /* Find the width of the bitstring in IMM. */
2027 for (len = 5; len < 32; len++)
2029 if ((imm & (1 << len)) == 0)
2033 /* Sign extend IMM as a 5-bit value. */
2034 imm = (imm & 0xf) - 0x10;
2042 /* Compute position (in OP[1]) and width (in OP[2])
2043 useful for copying IMM to a register using the depdi,z
2044 instructions. Store the immediate value to insert in OP[0]. */
2046 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2048 HOST_WIDE_INT lsb, len;
2050 /* Find the least significant set bit in IMM. */
2051 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2058 /* Choose variants based on *sign* of the 5-bit field. */
2059 if ((imm & 0x10) == 0)
2060 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2061 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2064 /* Find the width of the bitstring in IMM. */
2065 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2067 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2071 /* Sign extend IMM as a 5-bit value. */
2072 imm = (imm & 0xf) - 0x10;
2080 /* Output assembler code to perform a doubleword move insn
2081 with operands OPERANDS. */
2084 output_move_double (rtx *operands)
2086 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2088 rtx addreg0 = 0, addreg1 = 0;
2090 /* First classify both operands. */
2092 if (REG_P (operands[0]))
2094 else if (offsettable_memref_p (operands[0]))
2096 else if (GET_CODE (operands[0]) == MEM)
2101 if (REG_P (operands[1]))
2103 else if (CONSTANT_P (operands[1]))
2105 else if (offsettable_memref_p (operands[1]))
2107 else if (GET_CODE (operands[1]) == MEM)
2112 /* Check for the cases that the operand constraints are not
2113 supposed to allow to happen. Abort if we get one,
2114 because generating code for these cases is painful. */
2116 if (optype0 != REGOP && optype1 != REGOP)
2119 /* Handle auto decrementing and incrementing loads and stores
2120 specifically, since the structure of the function doesn't work
2121 for them without major modification. Do it better when we learn
2122 this port about the general inc/dec addressing of PA.
2123 (This was written by tege. Chide him if it doesn't work.) */
2125 if (optype0 == MEMOP)
2127 /* We have to output the address syntax ourselves, since print_operand
2128 doesn't deal with the addresses we want to use. Fix this later. */
2130 rtx addr = XEXP (operands[0], 0);
2131 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2133 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2135 operands[0] = XEXP (addr, 0);
2136 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2139 if (!reg_overlap_mentioned_p (high_reg, addr))
2141 /* No overlap between high target register and address
2142 register. (We do this in a non-obvious way to
2143 save a register file writeback) */
2144 if (GET_CODE (addr) == POST_INC)
2145 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2146 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2151 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2153 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2155 operands[0] = XEXP (addr, 0);
2156 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2159 if (!reg_overlap_mentioned_p (high_reg, addr))
2161 /* No overlap between high target register and address
2162 register. (We do this in a non-obvious way to
2163 save a register file writeback) */
2164 if (GET_CODE (addr) == PRE_INC)
2165 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2166 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2172 if (optype1 == MEMOP)
2174 /* We have to output the address syntax ourselves, since print_operand
2175 doesn't deal with the addresses we want to use. Fix this later. */
2177 rtx addr = XEXP (operands[1], 0);
2178 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2180 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2182 operands[1] = XEXP (addr, 0);
2183 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2186 if (!reg_overlap_mentioned_p (high_reg, addr))
2188 /* No overlap between high target register and address
2189 register. (We do this in a non-obvious way to
2190 save a register file writeback) */
2191 if (GET_CODE (addr) == POST_INC)
2192 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2193 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2197 /* This is an undefined situation. We should load into the
2198 address register *and* update that register. Probably
2199 we don't need to handle this at all. */
2200 if (GET_CODE (addr) == POST_INC)
2201 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2202 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2205 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2207 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2209 operands[1] = XEXP (addr, 0);
2210 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2213 if (!reg_overlap_mentioned_p (high_reg, addr))
2215 /* No overlap between high target register and address
2216 register. (We do this in a non-obvious way to
2217 save a register file writeback) */
2218 if (GET_CODE (addr) == PRE_INC)
2219 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2220 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2224 /* This is an undefined situation. We should load into the
2225 address register *and* update that register. Probably
2226 we don't need to handle this at all. */
2227 if (GET_CODE (addr) == PRE_INC)
2228 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2229 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2232 else if (GET_CODE (addr) == PLUS
2233 && GET_CODE (XEXP (addr, 0)) == MULT)
2235 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2237 if (!reg_overlap_mentioned_p (high_reg, addr))
2241 xoperands[0] = high_reg;
2242 xoperands[1] = XEXP (addr, 1);
2243 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2244 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2245 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2247 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2253 xoperands[0] = high_reg;
2254 xoperands[1] = XEXP (addr, 1);
2255 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2256 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2257 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2259 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2264 /* If an operand is an unoffsettable memory ref, find a register
2265 we can increment temporarily to make it refer to the second word. */
2267 if (optype0 == MEMOP)
2268 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2270 if (optype1 == MEMOP)
2271 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2273 /* Ok, we can do one word at a time.
2274 Normally we do the low-numbered word first.
2276 In either case, set up in LATEHALF the operands to use
2277 for the high-numbered word and in some cases alter the
2278 operands in OPERANDS to be suitable for the low-numbered word. */
2280 if (optype0 == REGOP)
2281 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2282 else if (optype0 == OFFSOP)
2283 latehalf[0] = adjust_address (operands[0], SImode, 4);
2285 latehalf[0] = operands[0];
2287 if (optype1 == REGOP)
2288 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2289 else if (optype1 == OFFSOP)
2290 latehalf[1] = adjust_address (operands[1], SImode, 4);
2291 else if (optype1 == CNSTOP)
2292 split_double (operands[1], &operands[1], &latehalf[1]);
2294 latehalf[1] = operands[1];
2296 /* If the first move would clobber the source of the second one,
2297 do them in the other order.
2299 This can happen in two cases:
2301 mem -> register where the first half of the destination register
2302 is the same register used in the memory's address. Reload
2303 can create such insns.
2305 mem in this case will be either register indirect or register
2306 indirect plus a valid offset.
2308 register -> register move where REGNO(dst) == REGNO(src + 1)
2309 someone (Tim/Tege?) claimed this can happen for parameter loads.
2311 Handle mem -> register case first. */
2312 if (optype0 == REGOP
2313 && (optype1 == MEMOP || optype1 == OFFSOP)
2314 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2317 /* Do the late half first. */
2319 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2320 output_asm_insn (singlemove_string (latehalf), latehalf);
2324 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2325 return singlemove_string (operands);
2328 /* Now handle register -> register case. */
2329 if (optype0 == REGOP && optype1 == REGOP
2330 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2332 output_asm_insn (singlemove_string (latehalf), latehalf);
2333 return singlemove_string (operands);
2336 /* Normal case: do the two words, low-numbered first. */
2338 output_asm_insn (singlemove_string (operands), operands);
2340 /* Make any unoffsettable addresses point at high-numbered word. */
2342 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2344 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2347 output_asm_insn (singlemove_string (latehalf), latehalf);
2349 /* Undo the adds we just did. */
2351 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2353 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2359 output_fp_move_double (rtx *operands)
2361 if (FP_REG_P (operands[0]))
2363 if (FP_REG_P (operands[1])
2364 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2365 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2367 output_asm_insn ("fldd%F1 %1,%0", operands);
2369 else if (FP_REG_P (operands[1]))
2371 output_asm_insn ("fstd%F0 %1,%0", operands);
2373 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2375 if (GET_CODE (operands[0]) == REG)
2378 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2379 xoperands[0] = operands[0];
2380 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2382 /* This is a pain. You have to be prepared to deal with an
2383 arbitrary address here including pre/post increment/decrement.
2385 so avoid this in the MD. */
2393 /* Return a REG that occurs in ADDR with coefficient 1.
2394 ADDR can be effectively incremented by incrementing REG. */
2397 find_addr_reg (rtx addr)
2399 while (GET_CODE (addr) == PLUS)
2401 if (GET_CODE (XEXP (addr, 0)) == REG)
2402 addr = XEXP (addr, 0);
2403 else if (GET_CODE (XEXP (addr, 1)) == REG)
2404 addr = XEXP (addr, 1);
2405 else if (CONSTANT_P (XEXP (addr, 0)))
2406 addr = XEXP (addr, 1);
2407 else if (CONSTANT_P (XEXP (addr, 1)))
2408 addr = XEXP (addr, 0);
2412 if (GET_CODE (addr) == REG)
2417 /* Emit code to perform a block move.
2419 OPERANDS[0] is the destination pointer as a REG, clobbered.
2420 OPERANDS[1] is the source pointer as a REG, clobbered.
2421 OPERANDS[2] is a register for temporary storage.
2422 OPERANDS[3] is a register for temporary storage.
2423 OPERANDS[4] is the size as a CONST_INT
2424 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2425 OPERANDS[6] is another temporary register. */
2428 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2430 int align = INTVAL (operands[5]);
2431 unsigned long n_bytes = INTVAL (operands[4]);
2433 /* We can't move more than a word at a time because the PA
2434 has no longer integer move insns. (Could use fp mem ops?) */
2435 if (align > (TARGET_64BIT ? 8 : 4))
2436 align = (TARGET_64BIT ? 8 : 4);
2438 /* Note that we know each loop below will execute at least twice
2439 (else we would have open-coded the copy). */
2443 /* Pre-adjust the loop counter. */
2444 operands[4] = GEN_INT (n_bytes - 16);
2445 output_asm_insn ("ldi %4,%2", operands);
2448 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2449 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2450 output_asm_insn ("std,ma %3,8(%0)", operands);
2451 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2452 output_asm_insn ("std,ma %6,8(%0)", operands);
2454 /* Handle the residual. There could be up to 7 bytes of
2455 residual to copy! */
2456 if (n_bytes % 16 != 0)
2458 operands[4] = GEN_INT (n_bytes % 8);
2459 if (n_bytes % 16 >= 8)
2460 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2461 if (n_bytes % 8 != 0)
2462 output_asm_insn ("ldd 0(%1),%6", operands);
2463 if (n_bytes % 16 >= 8)
2464 output_asm_insn ("std,ma %3,8(%0)", operands);
2465 if (n_bytes % 8 != 0)
2466 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2471 /* Pre-adjust the loop counter. */
2472 operands[4] = GEN_INT (n_bytes - 8);
2473 output_asm_insn ("ldi %4,%2", operands);
2476 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2477 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2478 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2479 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2480 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2482 /* Handle the residual. There could be up to 7 bytes of
2483 residual to copy! */
2484 if (n_bytes % 8 != 0)
2486 operands[4] = GEN_INT (n_bytes % 4);
2487 if (n_bytes % 8 >= 4)
2488 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2489 if (n_bytes % 4 != 0)
2490 output_asm_insn ("ldw 0(%1),%6", operands);
2491 if (n_bytes % 8 >= 4)
2492 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2493 if (n_bytes % 4 != 0)
2494 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2499 /* Pre-adjust the loop counter. */
2500 operands[4] = GEN_INT (n_bytes - 4);
2501 output_asm_insn ("ldi %4,%2", operands);
2504 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2505 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2506 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2507 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2508 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2510 /* Handle the residual. */
2511 if (n_bytes % 4 != 0)
2513 if (n_bytes % 4 >= 2)
2514 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2515 if (n_bytes % 2 != 0)
2516 output_asm_insn ("ldb 0(%1),%6", operands);
2517 if (n_bytes % 4 >= 2)
2518 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2519 if (n_bytes % 2 != 0)
2520 output_asm_insn ("stb %6,0(%0)", operands);
2525 /* Pre-adjust the loop counter. */
2526 operands[4] = GEN_INT (n_bytes - 2);
2527 output_asm_insn ("ldi %4,%2", operands);
2530 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2531 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2532 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2533 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2534 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2536 /* Handle the residual. */
2537 if (n_bytes % 2 != 0)
2539 output_asm_insn ("ldb 0(%1),%3", operands);
2540 output_asm_insn ("stb %3,0(%0)", operands);
2549 /* Count the number of insns necessary to handle this block move.
2551 Basic structure is the same as emit_block_move, except that we
2552 count insns rather than emit them. */
2555 compute_movmem_length (rtx insn)
2557 rtx pat = PATTERN (insn);
2558 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2559 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2560 unsigned int n_insns = 0;
2562 /* We can't move more than four bytes at a time because the PA
2563 has no longer integer move insns. (Could use fp mem ops?) */
2564 if (align > (TARGET_64BIT ? 8 : 4))
2565 align = (TARGET_64BIT ? 8 : 4);
2567 /* The basic copying loop. */
2571 if (n_bytes % (2 * align) != 0)
2573 if ((n_bytes % (2 * align)) >= align)
2576 if ((n_bytes % align) != 0)
2580 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2584 /* Emit code to perform a block clear.
2586 OPERANDS[0] is the destination pointer as a REG, clobbered.
2587 OPERANDS[1] is a register for temporary storage.
2588 OPERANDS[2] is the size as a CONST_INT
2589 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2592 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2594 int align = INTVAL (operands[3]);
2595 unsigned long n_bytes = INTVAL (operands[2]);
2597 /* We can't clear more than a word at a time because the PA
2598 has no longer integer move insns. */
2599 if (align > (TARGET_64BIT ? 8 : 4))
2600 align = (TARGET_64BIT ? 8 : 4);
2602 /* Note that we know each loop below will execute at least twice
2603 (else we would have open-coded the copy). */
2607 /* Pre-adjust the loop counter. */
2608 operands[2] = GEN_INT (n_bytes - 16);
2609 output_asm_insn ("ldi %2,%1", operands);
2612 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2613 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2614 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2616 /* Handle the residual. There could be up to 7 bytes of
2617 residual to copy! */
2618 if (n_bytes % 16 != 0)
2620 operands[2] = GEN_INT (n_bytes % 8);
2621 if (n_bytes % 16 >= 8)
2622 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2623 if (n_bytes % 8 != 0)
2624 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2629 /* Pre-adjust the loop counter. */
2630 operands[2] = GEN_INT (n_bytes - 8);
2631 output_asm_insn ("ldi %2,%1", operands);
2634 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2635 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2636 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2638 /* Handle the residual. There could be up to 7 bytes of
2639 residual to copy! */
2640 if (n_bytes % 8 != 0)
2642 operands[2] = GEN_INT (n_bytes % 4);
2643 if (n_bytes % 8 >= 4)
2644 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2645 if (n_bytes % 4 != 0)
2646 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2651 /* Pre-adjust the loop counter. */
2652 operands[2] = GEN_INT (n_bytes - 4);
2653 output_asm_insn ("ldi %2,%1", operands);
2656 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2657 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2658 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2660 /* Handle the residual. */
2661 if (n_bytes % 4 != 0)
2663 if (n_bytes % 4 >= 2)
2664 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2665 if (n_bytes % 2 != 0)
2666 output_asm_insn ("stb %%r0,0(%0)", operands);
2671 /* Pre-adjust the loop counter. */
2672 operands[2] = GEN_INT (n_bytes - 2);
2673 output_asm_insn ("ldi %2,%1", operands);
2676 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2677 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2678 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2680 /* Handle the residual. */
2681 if (n_bytes % 2 != 0)
2682 output_asm_insn ("stb %%r0,0(%0)", operands);
2691 /* Count the number of insns necessary to handle this block move.
2693 Basic structure is the same as emit_block_move, except that we
2694 count insns rather than emit them. */
2697 compute_clrmem_length (rtx insn)
2699 rtx pat = PATTERN (insn);
2700 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2701 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2702 unsigned int n_insns = 0;
2704 /* We can't clear more than a word at a time because the PA
2705 has no longer integer move insns. */
2706 if (align > (TARGET_64BIT ? 8 : 4))
2707 align = (TARGET_64BIT ? 8 : 4);
2709 /* The basic loop. */
2713 if (n_bytes % (2 * align) != 0)
2715 if ((n_bytes % (2 * align)) >= align)
2718 if ((n_bytes % align) != 0)
2722 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2728 output_and (rtx *operands)
2730 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2732 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2733 int ls0, ls1, ms0, p, len;
2735 for (ls0 = 0; ls0 < 32; ls0++)
2736 if ((mask & (1 << ls0)) == 0)
2739 for (ls1 = ls0; ls1 < 32; ls1++)
2740 if ((mask & (1 << ls1)) != 0)
2743 for (ms0 = ls1; ms0 < 32; ms0++)
2744 if ((mask & (1 << ms0)) == 0)
2757 operands[2] = GEN_INT (len);
2758 return "{extru|extrw,u} %1,31,%2,%0";
2762 /* We could use this `depi' for the case above as well, but `depi'
2763 requires one more register file access than an `extru'. */
2768 operands[2] = GEN_INT (p);
2769 operands[3] = GEN_INT (len);
2770 return "{depi|depwi} 0,%2,%3,%0";
2774 return "and %1,%2,%0";
2777 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2778 storing the result in operands[0]. */
2780 output_64bit_and (rtx *operands)
2782 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2784 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2785 int ls0, ls1, ms0, p, len;
2787 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2788 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2791 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2792 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2795 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2796 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2799 if (ms0 != HOST_BITS_PER_WIDE_INT)
2802 if (ls1 == HOST_BITS_PER_WIDE_INT)
2809 operands[2] = GEN_INT (len);
2810 return "extrd,u %1,63,%2,%0";
2814 /* We could use this `depi' for the case above as well, but `depi'
2815 requires one more register file access than an `extru'. */
2820 operands[2] = GEN_INT (p);
2821 operands[3] = GEN_INT (len);
2822 return "depdi 0,%2,%3,%0";
2826 return "and %1,%2,%0";
2830 output_ior (rtx *operands)
2832 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2833 int bs0, bs1, p, len;
2835 if (INTVAL (operands[2]) == 0)
2836 return "copy %1,%0";
2838 for (bs0 = 0; bs0 < 32; bs0++)
2839 if ((mask & (1 << bs0)) != 0)
2842 for (bs1 = bs0; bs1 < 32; bs1++)
2843 if ((mask & (1 << bs1)) == 0)
2846 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2852 operands[2] = GEN_INT (p);
2853 operands[3] = GEN_INT (len);
2854 return "{depi|depwi} -1,%2,%3,%0";
2857 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2858 storing the result in operands[0]. */
2860 output_64bit_ior (rtx *operands)
2862 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2863 int bs0, bs1, p, len;
2865 if (INTVAL (operands[2]) == 0)
2866 return "copy %1,%0";
2868 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2869 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2872 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2873 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2876 if (bs1 != HOST_BITS_PER_WIDE_INT
2877 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2883 operands[2] = GEN_INT (p);
2884 operands[3] = GEN_INT (len);
2885 return "depdi -1,%2,%3,%0";
2888 /* Target hook for assembling integer objects. This code handles
2889 aligned SI and DI integers specially since function references
2890 must be preceded by P%. */
2893 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
2895 if (size == UNITS_PER_WORD
2897 && function_label_operand (x, VOIDmode))
2899 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2900 output_addr_const (asm_out_file, x);
2901 fputc ('\n', asm_out_file);
2904 return default_assemble_integer (x, size, aligned_p);
2907 /* Output an ascii string. */
2909 output_ascii (FILE *file, const char *p, int size)
2913 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2915 /* The HP assembler can only take strings of 256 characters at one
2916 time. This is a limitation on input line length, *not* the
2917 length of the string. Sigh. Even worse, it seems that the
2918 restriction is in number of input characters (see \xnn &
2919 \whatever). So we have to do this very carefully. */
2921 fputs ("\t.STRING \"", file);
2924 for (i = 0; i < size; i += 4)
2928 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2930 register unsigned int c = (unsigned char) p[i + io];
2932 if (c == '\"' || c == '\\')
2933 partial_output[co++] = '\\';
2934 if (c >= ' ' && c < 0177)
2935 partial_output[co++] = c;
2939 partial_output[co++] = '\\';
2940 partial_output[co++] = 'x';
2941 hexd = c / 16 - 0 + '0';
2943 hexd -= '9' - 'a' + 1;
2944 partial_output[co++] = hexd;
2945 hexd = c % 16 - 0 + '0';
2947 hexd -= '9' - 'a' + 1;
2948 partial_output[co++] = hexd;
2951 if (chars_output + co > 243)
2953 fputs ("\"\n\t.STRING \"", file);
2956 fwrite (partial_output, 1, (size_t) co, file);
2960 fputs ("\"\n", file);
2963 /* Try to rewrite floating point comparisons & branches to avoid
2964 useless add,tr insns.
2966 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2967 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2968 first attempt to remove useless add,tr insns. It is zero
2969 for the second pass as reorg sometimes leaves bogus REG_DEAD
2972 When CHECK_NOTES is zero we can only eliminate add,tr insns
2973 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2976 remove_useless_addtr_insns (int check_notes)
2979 static int pass = 0;
2981 /* This is fairly cheap, so always run it when optimizing. */
2985 int fbranch_count = 0;
2987 /* Walk all the insns in this function looking for fcmp & fbranch
2988 instructions. Keep track of how many of each we find. */
2989 for (insn = get_insns (); insn; insn = next_insn (insn))
2993 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2994 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2997 tmp = PATTERN (insn);
2999 /* It must be a set. */
3000 if (GET_CODE (tmp) != SET)
3003 /* If the destination is CCFP, then we've found an fcmp insn. */
3004 tmp = SET_DEST (tmp);
3005 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3011 tmp = PATTERN (insn);
3012 /* If this is an fbranch instruction, bump the fbranch counter. */
3013 if (GET_CODE (tmp) == SET
3014 && SET_DEST (tmp) == pc_rtx
3015 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3016 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3017 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3018 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3026 /* Find all floating point compare + branch insns. If possible,
3027 reverse the comparison & the branch to avoid add,tr insns. */
3028 for (insn = get_insns (); insn; insn = next_insn (insn))
3032 /* Ignore anything that isn't an INSN. */
3033 if (GET_CODE (insn) != INSN)
3036 tmp = PATTERN (insn);
3038 /* It must be a set. */
3039 if (GET_CODE (tmp) != SET)
3042 /* The destination must be CCFP, which is register zero. */
3043 tmp = SET_DEST (tmp);
3044 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3047 /* INSN should be a set of CCFP.
3049 See if the result of this insn is used in a reversed FP
3050 conditional branch. If so, reverse our condition and
3051 the branch. Doing so avoids useless add,tr insns. */
3052 next = next_insn (insn);
3055 /* Jumps, calls and labels stop our search. */
3056 if (GET_CODE (next) == JUMP_INSN
3057 || GET_CODE (next) == CALL_INSN
3058 || GET_CODE (next) == CODE_LABEL)
3061 /* As does another fcmp insn. */
3062 if (GET_CODE (next) == INSN
3063 && GET_CODE (PATTERN (next)) == SET
3064 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3065 && REGNO (SET_DEST (PATTERN (next))) == 0)
3068 next = next_insn (next);
3071 /* Is NEXT_INSN a branch? */
3073 && GET_CODE (next) == JUMP_INSN)
3075 rtx pattern = PATTERN (next);
3077 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3078 and CCFP dies, then reverse our conditional and the branch
3079 to avoid the add,tr. */
3080 if (GET_CODE (pattern) == SET
3081 && SET_DEST (pattern) == pc_rtx
3082 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3083 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3084 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3085 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3086 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3087 && (fcmp_count == fbranch_count
3089 && find_regno_note (next, REG_DEAD, 0))))
3091 /* Reverse the branch. */
3092 tmp = XEXP (SET_SRC (pattern), 1);
3093 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3094 XEXP (SET_SRC (pattern), 2) = tmp;
3095 INSN_CODE (next) = -1;
3097 /* Reverse our condition. */
3098 tmp = PATTERN (insn);
3099 PUT_CODE (XEXP (tmp, 1),
3100 (reverse_condition_maybe_unordered
3101 (GET_CODE (XEXP (tmp, 1)))));
3111 /* You may have trouble believing this, but this is the 32 bit HP-PA
3116 Variable arguments (optional; any number may be allocated)
3118 SP-(4*(N+9)) arg word N
3123 Fixed arguments (must be allocated; may remain unused)
3132 SP-32 External Data Pointer (DP)
3134 SP-24 External/stub RP (RP')
3138 SP-8 Calling Stub RP (RP'')
3143 SP-0 Stack Pointer (points to next available address)
3147 /* This function saves registers as follows. Registers marked with ' are
3148 this function's registers (as opposed to the previous function's).
3149 If a frame_pointer isn't needed, r4 is saved as a general register;
3150 the space for the frame pointer is still allocated, though, to keep
3156 SP (FP') Previous FP
3157 SP + 4 Alignment filler (sigh)
3158 SP + 8 Space for locals reserved here.
3162 SP + n All call saved register used.
3166 SP + o All call saved fp registers used.
3170 SP + p (SP') points to next available address.
3174 /* Global variables set by output_function_prologue(). */
3175 /* Size of frame. Need to know this to emit return insns from
3177 static HOST_WIDE_INT actual_fsize, local_fsize;
3178 static int save_fregs;
3180 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3181 Handle case where DISP > 8k by using the add_high_const patterns.
3183 Note in DISP > 8k case, we will leave the high part of the address
3184 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3187 store_reg (int reg, HOST_WIDE_INT disp, int base)
3189 rtx insn, dest, src, basereg;
3191 src = gen_rtx_REG (word_mode, reg);
3192 basereg = gen_rtx_REG (Pmode, base);
3193 if (VAL_14_BITS_P (disp))
3195 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3196 insn = emit_move_insn (dest, src);
3198 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3200 rtx delta = GEN_INT (disp);
3201 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3203 emit_move_insn (tmpreg, delta);
3204 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3205 dest = gen_rtx_MEM (word_mode, tmpreg);
3206 insn = emit_move_insn (dest, src);
3210 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3211 gen_rtx_SET (VOIDmode,
3212 gen_rtx_MEM (word_mode,
3213 gen_rtx_PLUS (word_mode, basereg,
3221 rtx delta = GEN_INT (disp);
3222 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3223 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3225 emit_move_insn (tmpreg, high);
3226 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3227 insn = emit_move_insn (dest, src);
3231 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3232 gen_rtx_SET (VOIDmode,
3233 gen_rtx_MEM (word_mode,
3234 gen_rtx_PLUS (word_mode, basereg,
3242 RTX_FRAME_RELATED_P (insn) = 1;
3245 /* Emit RTL to store REG at the memory location specified by BASE and then
3246 add MOD to BASE. MOD must be <= 8k. */
3249 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3251 rtx insn, basereg, srcreg, delta;
3253 if (!VAL_14_BITS_P (mod))
3256 basereg = gen_rtx_REG (Pmode, base);
3257 srcreg = gen_rtx_REG (word_mode, reg);
3258 delta = GEN_INT (mod);
3260 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3263 RTX_FRAME_RELATED_P (insn) = 1;
3265 /* RTX_FRAME_RELATED_P must be set on each frame related set
3266 in a parallel with more than one element. Don't set
3267 RTX_FRAME_RELATED_P in the first set if reg is temporary
3268 register 1. The effect of this operation is recorded in
3269 the initial copy. */
3272 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3273 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3277 /* The first element of a PARALLEL is always processed if it is
3278 a SET. Thus, we need an expression list for this case. */
3280 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3281 gen_rtx_SET (VOIDmode, basereg,
3282 gen_rtx_PLUS (word_mode, basereg, delta)),
3288 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3289 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3290 whether to add a frame note or not.
3292 In the DISP > 8k case, we leave the high part of the address in %r1.
3293 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3296 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3300 if (VAL_14_BITS_P (disp))
3302 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3303 plus_constant (gen_rtx_REG (Pmode, base), disp));
3305 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3307 rtx basereg = gen_rtx_REG (Pmode, base);
3308 rtx delta = GEN_INT (disp);
3309 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3311 emit_move_insn (tmpreg, delta);
3312 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3313 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3317 rtx basereg = gen_rtx_REG (Pmode, base);
3318 rtx delta = GEN_INT (disp);
3319 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3321 emit_move_insn (tmpreg,
3322 gen_rtx_PLUS (Pmode, basereg,
3323 gen_rtx_HIGH (Pmode, delta)));
3324 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3325 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3328 if (DO_FRAME_NOTES && note)
3329 RTX_FRAME_RELATED_P (insn) = 1;
3333 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3338 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3339 be consistent with the rounding and size calculation done here.
3340 Change them at the same time. */
3342 /* We do our own stack alignment. First, round the size of the
3343 stack locals up to a word boundary. */
3344 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3346 /* Space for previous frame pointer + filler. If any frame is
3347 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3348 waste some space here for the sake of HP compatibility. The
3349 first slot is only used when the frame pointer is needed. */
3350 if (size || frame_pointer_needed)
3351 size += STARTING_FRAME_OFFSET;
3353 /* If the current function calls __builtin_eh_return, then we need
3354 to allocate stack space for registers that will hold data for
3355 the exception handler. */
3356 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3360 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3362 size += i * UNITS_PER_WORD;
3365 /* Account for space used by the callee general register saves. */
3366 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3367 if (regs_ever_live[i])
3368 size += UNITS_PER_WORD;
3370 /* Account for space used by the callee floating point register saves. */
3371 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3372 if (regs_ever_live[i]
3373 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3377 /* We always save both halves of the FP register, so always
3378 increment the frame size by 8 bytes. */
3382 /* If any of the floating registers are saved, account for the
3383 alignment needed for the floating point register save block. */
3386 size = (size + 7) & ~7;
3391 /* The various ABIs include space for the outgoing parameters in the
3392 size of the current function's stack frame. We don't need to align
3393 for the outgoing arguments as their alignment is set by the final
3394 rounding for the frame as a whole. */
3395 size += current_function_outgoing_args_size;
3397 /* Allocate space for the fixed frame marker. This space must be
3398 allocated for any function that makes calls or allocates
3400 if (!current_function_is_leaf || size)
3401 size += TARGET_64BIT ? 48 : 32;
3403 /* Finally, round to the preferred stack boundary. */
3404 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3405 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3408 /* Generate the assembly code for function entry. FILE is a stdio
3409 stream to output the code to. SIZE is an int: how many units of
3410 temporary storage to allocate.
3412 Refer to the array `regs_ever_live' to determine which registers to
3413 save; `regs_ever_live[I]' is nonzero if register number I is ever
3414 used in the function. This function is responsible for knowing
3415 which registers should not be saved even if used. */
3417 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3418 of memory. If any fpu reg is used in the function, we allocate
3419 such a block here, at the bottom of the frame, just in case it's needed.
3421 If this function is a leaf procedure, then we may choose not
3422 to do a "save" insn. The decision about whether or not
3423 to do this is made in regclass.c. */
3426 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3428 /* The function's label and associated .PROC must never be
3429 separated and must be output *after* any profiling declarations
3430 to avoid changing spaces/subspaces within a procedure. */
3431 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3432 fputs ("\t.PROC\n", file);
3434 /* hppa_expand_prologue does the dirty work now. We just need
3435 to output the assembler directives which denote the start
3437 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3438 if (regs_ever_live[2])
3439 fputs (",CALLS,SAVE_RP", file);
3441 fputs (",NO_CALLS", file);
3443 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3444 at the beginning of the frame and that it is used as the frame
3445 pointer for the frame. We do this because our current frame
3446 layout doesn't conform to that specified in the the HP runtime
3447 documentation and we need a way to indicate to programs such as
3448 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3449 isn't used by HP compilers but is supported by the assembler.
3450 However, SAVE_SP is supposed to indicate that the previous stack
3451 pointer has been saved in the frame marker. */
3452 if (frame_pointer_needed)
3453 fputs (",SAVE_SP", file);
3455 /* Pass on information about the number of callee register saves
3456 performed in the prologue.
3458 The compiler is supposed to pass the highest register number
3459 saved, the assembler then has to adjust that number before
3460 entering it into the unwind descriptor (to account for any
3461 caller saved registers with lower register numbers than the
3462 first callee saved register). */
3464 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3467 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3469 fputs ("\n\t.ENTRY\n", file);
3471 remove_useless_addtr_insns (0);
3475 hppa_expand_prologue (void)
3477 int merge_sp_adjust_with_store = 0;
3478 HOST_WIDE_INT size = get_frame_size ();
3479 HOST_WIDE_INT offset;
3487 /* Compute total size for frame pointer, filler, locals and rounding to
3488 the next word boundary. Similar code appears in compute_frame_size
3489 and must be changed in tandem with this code. */
3490 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3491 if (local_fsize || frame_pointer_needed)
3492 local_fsize += STARTING_FRAME_OFFSET;
3494 actual_fsize = compute_frame_size (size, &save_fregs);
3496 /* Compute a few things we will use often. */
3497 tmpreg = gen_rtx_REG (word_mode, 1);
3499 /* Save RP first. The calling conventions manual states RP will
3500 always be stored into the caller's frame at sp - 20 or sp - 16
3501 depending on which ABI is in use. */
3502 if (regs_ever_live[2] || current_function_calls_eh_return)
3503 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3505 /* Allocate the local frame and set up the frame pointer if needed. */
3506 if (actual_fsize != 0)
3508 if (frame_pointer_needed)
3510 /* Copy the old frame pointer temporarily into %r1. Set up the
3511 new stack pointer, then store away the saved old frame pointer
3512 into the stack at sp and at the same time update the stack
3513 pointer by actual_fsize bytes. Two versions, first
3514 handles small (<8k) frames. The second handles large (>=8k)
3516 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3519 /* We need to record the frame pointer save here since the
3520 new frame pointer is set in the following insn. */
3521 RTX_FRAME_RELATED_P (insn) = 1;
3523 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3524 gen_rtx_SET (VOIDmode,
3525 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3530 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3532 RTX_FRAME_RELATED_P (insn) = 1;
3534 if (VAL_14_BITS_P (actual_fsize))
3535 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3538 /* It is incorrect to store the saved frame pointer at *sp,
3539 then increment sp (writes beyond the current stack boundary).
3541 So instead use stwm to store at *sp and post-increment the
3542 stack pointer as an atomic operation. Then increment sp to
3543 finish allocating the new frame. */
3544 HOST_WIDE_INT adjust1 = 8192 - 64;
3545 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3547 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3548 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3552 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3553 we need to store the previous stack pointer (frame pointer)
3554 into the frame marker on targets that use the HP unwind
3555 library. This allows the HP unwind library to be used to
3556 unwind GCC frames. However, we are not fully compatible
3557 with the HP library because our frame layout differs from
3558 that specified in the HP runtime specification.
3560 We don't want a frame note on this instruction as the frame
3561 marker moves during dynamic stack allocation.
3563 This instruction also serves as a blockage to prevent
3564 register spills from being scheduled before the stack
3565 pointer is raised. This is necessary as we store
3566 registers using the frame pointer as a base register,
3567 and the frame pointer is set before sp is raised. */
3568 if (TARGET_HPUX_UNWIND_LIBRARY)
3570 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3571 GEN_INT (TARGET_64BIT ? -8 : -4));
3573 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3577 emit_insn (gen_blockage ());
3579 /* no frame pointer needed. */
3582 /* In some cases we can perform the first callee register save
3583 and allocating the stack frame at the same time. If so, just
3584 make a note of it and defer allocating the frame until saving
3585 the callee registers. */
3586 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3587 merge_sp_adjust_with_store = 1;
3588 /* Can not optimize. Adjust the stack frame by actual_fsize
3591 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3596 /* Normal register save.
3598 Do not save the frame pointer in the frame_pointer_needed case. It
3599 was done earlier. */
3600 if (frame_pointer_needed)
3602 offset = local_fsize;
3604 /* Saving the EH return data registers in the frame is the simplest
3605 way to get the frame unwind information emitted. We put them
3606 just before the general registers. */
3607 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3609 unsigned int i, regno;
3613 regno = EH_RETURN_DATA_REGNO (i);
3614 if (regno == INVALID_REGNUM)
3617 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3618 offset += UNITS_PER_WORD;
3622 for (i = 18; i >= 4; i--)
3623 if (regs_ever_live[i] && ! call_used_regs[i])
3625 store_reg (i, offset, FRAME_POINTER_REGNUM);
3626 offset += UNITS_PER_WORD;
3629 /* Account for %r3 which is saved in a special place. */
3632 /* No frame pointer needed. */
3635 offset = local_fsize - actual_fsize;
3637 /* Saving the EH return data registers in the frame is the simplest
3638 way to get the frame unwind information emitted. */
3639 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3641 unsigned int i, regno;
3645 regno = EH_RETURN_DATA_REGNO (i);
3646 if (regno == INVALID_REGNUM)
3649 /* If merge_sp_adjust_with_store is nonzero, then we can
3650 optimize the first save. */
3651 if (merge_sp_adjust_with_store)
3653 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3654 merge_sp_adjust_with_store = 0;
3657 store_reg (regno, offset, STACK_POINTER_REGNUM);
3658 offset += UNITS_PER_WORD;
3662 for (i = 18; i >= 3; i--)
3663 if (regs_ever_live[i] && ! call_used_regs[i])
3665 /* If merge_sp_adjust_with_store is nonzero, then we can
3666 optimize the first GR save. */
3667 if (merge_sp_adjust_with_store)
3669 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3670 merge_sp_adjust_with_store = 0;
3673 store_reg (i, offset, STACK_POINTER_REGNUM);
3674 offset += UNITS_PER_WORD;
3678 /* If we wanted to merge the SP adjustment with a GR save, but we never
3679 did any GR saves, then just emit the adjustment here. */
3680 if (merge_sp_adjust_with_store)
3681 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3685 /* The hppa calling conventions say that %r19, the pic offset
3686 register, is saved at sp - 32 (in this function's frame)
3687 when generating PIC code. FIXME: What is the correct thing
3688 to do for functions which make no calls and allocate no
3689 frame? Do we need to allocate a frame, or can we just omit
3690 the save? For now we'll just omit the save.
3692 We don't want a note on this insn as the frame marker can
3693 move if there is a dynamic stack allocation. */
3694 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3696 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3698 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3702 /* Align pointer properly (doubleword boundary). */
3703 offset = (offset + 7) & ~7;
3705 /* Floating point register store. */
3710 /* First get the frame or stack pointer to the start of the FP register
3712 if (frame_pointer_needed)
3714 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3715 base = frame_pointer_rtx;
3719 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3720 base = stack_pointer_rtx;
3723 /* Now actually save the FP registers. */
3724 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3726 if (regs_ever_live[i]
3727 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3729 rtx addr, insn, reg;
3730 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3731 reg = gen_rtx_REG (DFmode, i);
3732 insn = emit_move_insn (addr, reg);
3735 RTX_FRAME_RELATED_P (insn) = 1;
3738 rtx mem = gen_rtx_MEM (DFmode,
3739 plus_constant (base, offset));
3741 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3742 gen_rtx_SET (VOIDmode, mem, reg),
3747 rtx meml = gen_rtx_MEM (SFmode,
3748 plus_constant (base, offset));
3749 rtx memr = gen_rtx_MEM (SFmode,
3750 plus_constant (base, offset + 4));
3751 rtx regl = gen_rtx_REG (SFmode, i);
3752 rtx regr = gen_rtx_REG (SFmode, i + 1);
3753 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3754 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3757 RTX_FRAME_RELATED_P (setl) = 1;
3758 RTX_FRAME_RELATED_P (setr) = 1;
3759 vec = gen_rtvec (2, setl, setr);
3761 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3762 gen_rtx_SEQUENCE (VOIDmode, vec),
3766 offset += GET_MODE_SIZE (DFmode);
3773 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3774 Handle case where DISP > 8k by using the add_high_const patterns. */
3777 load_reg (int reg, HOST_WIDE_INT disp, int base)
3779 rtx dest = gen_rtx_REG (word_mode, reg);
3780 rtx basereg = gen_rtx_REG (Pmode, base);
3783 if (VAL_14_BITS_P (disp))
3784 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3785 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3787 rtx delta = GEN_INT (disp);
3788 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3790 emit_move_insn (tmpreg, delta);
3791 if (TARGET_DISABLE_INDEXING)
3793 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3794 src = gen_rtx_MEM (word_mode, tmpreg);
3797 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3801 rtx delta = GEN_INT (disp);
3802 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3803 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3805 emit_move_insn (tmpreg, high);
3806 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3809 emit_move_insn (dest, src);
3812 /* Update the total code bytes output to the text section. */
3815 update_total_code_bytes (int nbytes)
3817 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3818 && !IN_NAMED_SECTION_P (cfun->decl))
3820 if (INSN_ADDRESSES_SET_P ())
3822 unsigned long old_total = total_code_bytes;
3824 total_code_bytes += nbytes;
3826 /* Be prepared to handle overflows. */
3827 if (old_total > total_code_bytes)
3828 total_code_bytes = -1;
3831 total_code_bytes = -1;
3835 /* This function generates the assembly code for function exit.
3836 Args are as for output_function_prologue ().
3838 The function epilogue should not depend on the current stack
3839 pointer! It should use the frame pointer only. This is mandatory
3840 because of alloca; we also take advantage of it to omit stack
3841 adjustments before returning. */
3844 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3846 rtx insn = get_last_insn ();
3850 /* hppa_expand_epilogue does the dirty work now. We just need
3851 to output the assembler directives which denote the end
3854 To make debuggers happy, emit a nop if the epilogue was completely
3855 eliminated due to a volatile call as the last insn in the
3856 current function. That way the return address (in %r2) will
3857 always point to a valid instruction in the current function. */
3859 /* Get the last real insn. */
3860 if (GET_CODE (insn) == NOTE)
3861 insn = prev_real_insn (insn);
3863 /* If it is a sequence, then look inside. */
3864 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3865 insn = XVECEXP (PATTERN (insn), 0, 0);
3867 /* If insn is a CALL_INSN, then it must be a call to a volatile
3868 function (otherwise there would be epilogue insns). */
3869 if (insn && GET_CODE (insn) == CALL_INSN)
3871 fputs ("\tnop\n", file);
3875 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3877 if (TARGET_SOM && TARGET_GAS)
3879 /* We done with this subspace except possibly for some additional
3880 debug information. Forget that we are in this subspace to ensure
3881 that the next function is output in its own subspace. */
3885 if (INSN_ADDRESSES_SET_P ())
3887 insn = get_last_nonnote_insn ();
3888 last_address += INSN_ADDRESSES (INSN_UID (insn));
3890 last_address += insn_default_length (insn);
3891 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
3892 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
3895 /* Finally, update the total number of code bytes output so far. */
3896 update_total_code_bytes (last_address);
3900 hppa_expand_epilogue (void)
3903 HOST_WIDE_INT offset;
3904 HOST_WIDE_INT ret_off = 0;
3906 int merge_sp_adjust_with_load = 0;
3908 /* We will use this often. */
3909 tmpreg = gen_rtx_REG (word_mode, 1);
3911 /* Try to restore RP early to avoid load/use interlocks when
3912 RP gets used in the return (bv) instruction. This appears to still
3913 be necessary even when we schedule the prologue and epilogue. */
3914 if (regs_ever_live [2] || current_function_calls_eh_return)
3916 ret_off = TARGET_64BIT ? -16 : -20;
3917 if (frame_pointer_needed)
3919 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3924 /* No frame pointer, and stack is smaller than 8k. */
3925 if (VAL_14_BITS_P (ret_off - actual_fsize))
3927 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3933 /* General register restores. */
3934 if (frame_pointer_needed)
3936 offset = local_fsize;
3938 /* If the current function calls __builtin_eh_return, then we need
3939 to restore the saved EH data registers. */
3940 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3942 unsigned int i, regno;
3946 regno = EH_RETURN_DATA_REGNO (i);
3947 if (regno == INVALID_REGNUM)
3950 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3951 offset += UNITS_PER_WORD;
3955 for (i = 18; i >= 4; i--)
3956 if (regs_ever_live[i] && ! call_used_regs[i])
3958 load_reg (i, offset, FRAME_POINTER_REGNUM);
3959 offset += UNITS_PER_WORD;
3964 offset = local_fsize - actual_fsize;
3966 /* If the current function calls __builtin_eh_return, then we need
3967 to restore the saved EH data registers. */
3968 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3970 unsigned int i, regno;
3974 regno = EH_RETURN_DATA_REGNO (i);
3975 if (regno == INVALID_REGNUM)
3978 /* Only for the first load.
3979 merge_sp_adjust_with_load holds the register load
3980 with which we will merge the sp adjustment. */
3981 if (merge_sp_adjust_with_load == 0
3983 && VAL_14_BITS_P (-actual_fsize))
3984 merge_sp_adjust_with_load = regno;
3986 load_reg (regno, offset, STACK_POINTER_REGNUM);
3987 offset += UNITS_PER_WORD;
3991 for (i = 18; i >= 3; i--)
3993 if (regs_ever_live[i] && ! call_used_regs[i])
3995 /* Only for the first load.
3996 merge_sp_adjust_with_load holds the register load
3997 with which we will merge the sp adjustment. */
3998 if (merge_sp_adjust_with_load == 0
4000 && VAL_14_BITS_P (-actual_fsize))
4001 merge_sp_adjust_with_load = i;
4003 load_reg (i, offset, STACK_POINTER_REGNUM);
4004 offset += UNITS_PER_WORD;
4009 /* Align pointer properly (doubleword boundary). */
4010 offset = (offset + 7) & ~7;
4012 /* FP register restores. */
4015 /* Adjust the register to index off of. */
4016 if (frame_pointer_needed)
4017 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4019 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4021 /* Actually do the restores now. */
4022 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4023 if (regs_ever_live[i]
4024 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4026 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4027 rtx dest = gen_rtx_REG (DFmode, i);
4028 emit_move_insn (dest, src);
4032 /* Emit a blockage insn here to keep these insns from being moved to
4033 an earlier spot in the epilogue, or into the main instruction stream.
4035 This is necessary as we must not cut the stack back before all the
4036 restores are finished. */
4037 emit_insn (gen_blockage ());
4039 /* Reset stack pointer (and possibly frame pointer). The stack
4040 pointer is initially set to fp + 64 to avoid a race condition. */
4041 if (frame_pointer_needed)
4043 rtx delta = GEN_INT (-64);
4045 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4046 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4048 /* If we were deferring a callee register restore, do it now. */
4049 else if (merge_sp_adjust_with_load)
4051 rtx delta = GEN_INT (-actual_fsize);
4052 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4054 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4056 else if (actual_fsize != 0)
4057 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4060 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4061 frame greater than 8k), do so now. */
4063 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4065 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4067 rtx sa = EH_RETURN_STACKADJ_RTX;
4069 emit_insn (gen_blockage ());
4070 emit_insn (TARGET_64BIT
4071 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4072 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4077 hppa_pic_save_rtx (void)
4079 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4083 hppa_profile_hook (int label_no)
4085 /* We use SImode for the address of the function in both 32 and
4086 64-bit code to avoid having to provide DImode versions of the
4087 lcla2 and load_offset_label_address insn patterns. */
4088 rtx reg = gen_reg_rtx (SImode);
4089 rtx label_rtx = gen_label_rtx ();
4090 rtx begin_label_rtx, call_insn;
4091 char begin_label_name[16];
4093 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4095 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4098 emit_move_insn (arg_pointer_rtx,
4099 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4102 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4104 /* The address of the function is loaded into %r25 with a instruction-
4105 relative sequence that avoids the use of relocations. The sequence
4106 is split so that the load_offset_label_address instruction can
4107 occupy the delay slot of the call to _mcount. */
4109 emit_insn (gen_lcla2 (reg, label_rtx));
4111 emit_insn (gen_lcla1 (reg, label_rtx));
4113 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4114 reg, begin_label_rtx, label_rtx));
4116 #ifndef NO_PROFILE_COUNTERS
4118 rtx count_label_rtx, addr, r24;
4119 char count_label_name[16];
4121 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4122 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4124 addr = force_reg (Pmode, count_label_rtx);
4125 r24 = gen_rtx_REG (Pmode, 24);
4126 emit_move_insn (r24, addr);
4129 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4130 gen_rtx_SYMBOL_REF (Pmode,
4132 GEN_INT (TARGET_64BIT ? 24 : 12)));
4134 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4139 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4140 gen_rtx_SYMBOL_REF (Pmode,
4142 GEN_INT (TARGET_64BIT ? 16 : 8)));
4146 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4147 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4149 /* Indicate the _mcount call cannot throw, nor will it execute a
4151 REG_NOTES (call_insn)
4152 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4155 /* Fetch the return address for the frame COUNT steps up from
4156 the current frame, after the prologue. FRAMEADDR is the
4157 frame pointer of the COUNT frame.
4159 We want to ignore any export stub remnants here. To handle this,
4160 we examine the code at the return address, and if it is an export
4161 stub, we return a memory rtx for the stub return address stored
4164 The value returned is used in two different ways:
4166 1. To find a function's caller.
4168 2. To change the return address for a function.
4170 This function handles most instances of case 1; however, it will
4171 fail if there are two levels of stubs to execute on the return
4172 path. The only way I believe that can happen is if the return value
4173 needs a parameter relocation, which never happens for C code.
4175 This function handles most instances of case 2; however, it will
4176 fail if we did not originally have stub code on the return path
4177 but will need stub code on the new return path. This can happen if
4178 the caller & callee are both in the main program, but the new
4179 return location is in a shared library. */
4182 return_addr_rtx (int count, rtx frameaddr)
4192 rp = get_hard_reg_initial_val (Pmode, 2);
4194 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4197 saved_rp = gen_reg_rtx (Pmode);
4198 emit_move_insn (saved_rp, rp);
4200 /* Get pointer to the instruction stream. We have to mask out the
4201 privilege level from the two low order bits of the return address
4202 pointer here so that ins will point to the start of the first
4203 instruction that would have been executed if we returned. */
4204 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4205 label = gen_label_rtx ();
4207 /* Check the instruction stream at the normal return address for the
4210 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4211 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4212 0x00011820 | stub+16: mtsp r1,sr0
4213 0xe0400002 | stub+20: be,n 0(sr0,rp)
4215 If it is an export stub, than our return address is really in
4218 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4219 NULL_RTX, SImode, 1);
4220 emit_jump_insn (gen_bne (label));
4222 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4223 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4224 emit_jump_insn (gen_bne (label));
4226 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4227 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4228 emit_jump_insn (gen_bne (label));
4230 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4231 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4233 /* If there is no export stub then just use the value saved from
4234 the return pointer register. */
4236 emit_jump_insn (gen_bne (label));
4238 /* Here we know that our return address points to an export
4239 stub. We don't want to return the address of the export stub,
4240 but rather the return address of the export stub. That return
4241 address is stored at -24[frameaddr]. */
4243 emit_move_insn (saved_rp,
4245 memory_address (Pmode,
4246 plus_constant (frameaddr,
4253 /* This is only valid once reload has completed because it depends on
4254 knowing exactly how much (if any) frame there is and...
4256 It's only valid if there is no frame marker to de-allocate and...
4258 It's only valid if %r2 hasn't been saved into the caller's frame
4259 (we're not profiling and %r2 isn't live anywhere). */
4261 hppa_can_use_return_insn_p (void)
4263 return (reload_completed
4264 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4265 && ! regs_ever_live[2]
4266 && ! frame_pointer_needed);
4270 emit_bcond_fp (enum rtx_code code, rtx operand0)
4272 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4273 gen_rtx_IF_THEN_ELSE (VOIDmode,
4274 gen_rtx_fmt_ee (code,
4276 gen_rtx_REG (CCFPmode, 0),
4278 gen_rtx_LABEL_REF (VOIDmode, operand0),
4284 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4286 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4287 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4290 /* Adjust the cost of a scheduling dependency. Return the new cost of
4291 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4294 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4296 enum attr_type attr_type;
4298 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4299 true dependencies as they are described with bypasses now. */
4300 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4303 if (! recog_memoized (insn))
4306 attr_type = get_attr_type (insn);
4308 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4310 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4313 if (attr_type == TYPE_FPLOAD)
4315 rtx pat = PATTERN (insn);
4316 rtx dep_pat = PATTERN (dep_insn);
4317 if (GET_CODE (pat) == PARALLEL)
4319 /* This happens for the fldXs,mb patterns. */
4320 pat = XVECEXP (pat, 0, 0);
4322 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4323 /* If this happens, we have to extend this to schedule
4324 optimally. Return 0 for now. */
4327 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4329 if (! recog_memoized (dep_insn))
4331 switch (get_attr_type (dep_insn))
4338 case TYPE_FPSQRTSGL:
4339 case TYPE_FPSQRTDBL:
4340 /* A fpload can't be issued until one cycle before a
4341 preceding arithmetic operation has finished if
4342 the target of the fpload is any of the sources
4343 (or destination) of the arithmetic operation. */
4344 return insn_default_latency (dep_insn) - 1;
4351 else if (attr_type == TYPE_FPALU)
4353 rtx pat = PATTERN (insn);
4354 rtx dep_pat = PATTERN (dep_insn);
4355 if (GET_CODE (pat) == PARALLEL)
4357 /* This happens for the fldXs,mb patterns. */
4358 pat = XVECEXP (pat, 0, 0);
4360 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4361 /* If this happens, we have to extend this to schedule
4362 optimally. Return 0 for now. */
4365 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4367 if (! recog_memoized (dep_insn))
4369 switch (get_attr_type (dep_insn))
4373 case TYPE_FPSQRTSGL:
4374 case TYPE_FPSQRTDBL:
4375 /* An ALU flop can't be issued until two cycles before a
4376 preceding divide or sqrt operation has finished if
4377 the target of the ALU flop is any of the sources
4378 (or destination) of the divide or sqrt operation. */
4379 return insn_default_latency (dep_insn) - 2;
4387 /* For other anti dependencies, the cost is 0. */
4390 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4392 /* Output dependency; DEP_INSN writes a register that INSN writes some
4394 if (attr_type == TYPE_FPLOAD)
4396 rtx pat = PATTERN (insn);
4397 rtx dep_pat = PATTERN (dep_insn);
4398 if (GET_CODE (pat) == PARALLEL)
4400 /* This happens for the fldXs,mb patterns. */
4401 pat = XVECEXP (pat, 0, 0);
4403 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4404 /* If this happens, we have to extend this to schedule
4405 optimally. Return 0 for now. */
4408 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4410 if (! recog_memoized (dep_insn))
4412 switch (get_attr_type (dep_insn))
4419 case TYPE_FPSQRTSGL:
4420 case TYPE_FPSQRTDBL:
4421 /* A fpload can't be issued until one cycle before a
4422 preceding arithmetic operation has finished if
4423 the target of the fpload is the destination of the
4424 arithmetic operation.
4426 Exception: For PA7100LC, PA7200 and PA7300, the cost
4427 is 3 cycles, unless they bundle together. We also
4428 pay the penalty if the second insn is a fpload. */
4429 return insn_default_latency (dep_insn) - 1;
4436 else if (attr_type == TYPE_FPALU)
4438 rtx pat = PATTERN (insn);
4439 rtx dep_pat = PATTERN (dep_insn);
4440 if (GET_CODE (pat) == PARALLEL)
4442 /* This happens for the fldXs,mb patterns. */
4443 pat = XVECEXP (pat, 0, 0);
4445 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4446 /* If this happens, we have to extend this to schedule
4447 optimally. Return 0 for now. */
4450 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4452 if (! recog_memoized (dep_insn))
4454 switch (get_attr_type (dep_insn))
4458 case TYPE_FPSQRTSGL:
4459 case TYPE_FPSQRTDBL:
4460 /* An ALU flop can't be issued until two cycles before a
4461 preceding divide or sqrt operation has finished if
4462 the target of the ALU flop is also the target of
4463 the divide or sqrt operation. */
4464 return insn_default_latency (dep_insn) - 2;
4472 /* For other output dependencies, the cost is 0. */
4479 /* Adjust scheduling priorities. We use this to try and keep addil
4480 and the next use of %r1 close together. */
4482 pa_adjust_priority (rtx insn, int priority)
4484 rtx set = single_set (insn);
4488 src = SET_SRC (set);
4489 dest = SET_DEST (set);
4490 if (GET_CODE (src) == LO_SUM
4491 && symbolic_operand (XEXP (src, 1), VOIDmode)
4492 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4495 else if (GET_CODE (src) == MEM
4496 && GET_CODE (XEXP (src, 0)) == LO_SUM
4497 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4498 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4501 else if (GET_CODE (dest) == MEM
4502 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4503 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4504 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4510 /* The 700 can only issue a single insn at a time.
4511 The 7XXX processors can issue two insns at a time.
4512 The 8000 can issue 4 insns at a time. */
4514 pa_issue_rate (void)
4518 case PROCESSOR_700: return 1;
4519 case PROCESSOR_7100: return 2;
4520 case PROCESSOR_7100LC: return 2;
4521 case PROCESSOR_7200: return 2;
4522 case PROCESSOR_7300: return 2;
4523 case PROCESSOR_8000: return 4;
4532 /* Return any length adjustment needed by INSN which already has its length
4533 computed as LENGTH. Return zero if no adjustment is necessary.
4535 For the PA: function calls, millicode calls, and backwards short
4536 conditional branches with unfilled delay slots need an adjustment by +1
4537 (to account for the NOP which will be inserted into the instruction stream).
4539 Also compute the length of an inline block move here as it is too
4540 complicated to express as a length attribute in pa.md. */
4542 pa_adjust_insn_length (rtx insn, int length)
4544 rtx pat = PATTERN (insn);
4546 /* Jumps inside switch tables which have unfilled delay slots need
4548 if (GET_CODE (insn) == JUMP_INSN
4549 && GET_CODE (pat) == PARALLEL
4550 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4552 /* Millicode insn with an unfilled delay slot. */
4553 else if (GET_CODE (insn) == INSN
4554 && GET_CODE (pat) != SEQUENCE
4555 && GET_CODE (pat) != USE
4556 && GET_CODE (pat) != CLOBBER
4557 && get_attr_type (insn) == TYPE_MILLI)
4559 /* Block move pattern. */
4560 else if (GET_CODE (insn) == INSN
4561 && GET_CODE (pat) == PARALLEL
4562 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4563 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4564 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4565 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4566 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4567 return compute_movmem_length (insn) - 4;
4568 /* Block clear pattern. */
4569 else if (GET_CODE (insn) == INSN
4570 && GET_CODE (pat) == PARALLEL
4571 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4572 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4573 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4574 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4575 return compute_clrmem_length (insn) - 4;
4576 /* Conditional branch with an unfilled delay slot. */
4577 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4579 /* Adjust a short backwards conditional with an unfilled delay slot. */
4580 if (GET_CODE (pat) == SET
4582 && ! forward_branch_p (insn))
4584 else if (GET_CODE (pat) == PARALLEL
4585 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4588 /* Adjust dbra insn with short backwards conditional branch with
4589 unfilled delay slot -- only for case where counter is in a
4590 general register register. */
4591 else if (GET_CODE (pat) == PARALLEL
4592 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4593 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4594 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4596 && ! forward_branch_p (insn))
4604 /* Print operand X (an rtx) in assembler syntax to file FILE.
4605 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4606 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4609 print_operand (FILE *file, rtx x, int code)
4614 /* Output a 'nop' if there's nothing for the delay slot. */
4615 if (dbr_sequence_length () == 0)
4616 fputs ("\n\tnop", file);
4619 /* Output a nullification completer if there's nothing for the */
4620 /* delay slot or nullification is requested. */
4621 if (dbr_sequence_length () == 0 ||
4623 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4627 /* Print out the second register name of a register pair.
4628 I.e., R (6) => 7. */
4629 fputs (reg_names[REGNO (x) + 1], file);
4632 /* A register or zero. */
4634 || (x == CONST0_RTX (DFmode))
4635 || (x == CONST0_RTX (SFmode)))
4637 fputs ("%r0", file);
4643 /* A register or zero (floating point). */
4645 || (x == CONST0_RTX (DFmode))
4646 || (x == CONST0_RTX (SFmode)))
4648 fputs ("%fr0", file);
4657 xoperands[0] = XEXP (XEXP (x, 0), 0);
4658 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4659 output_global_address (file, xoperands[1], 0);
4660 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4664 case 'C': /* Plain (C)ondition */
4666 switch (GET_CODE (x))
4669 fputs ("=", file); break;
4671 fputs ("<>", file); break;
4673 fputs (">", file); break;
4675 fputs (">=", file); break;
4677 fputs (">>=", file); break;
4679 fputs (">>", file); break;
4681 fputs ("<", file); break;
4683 fputs ("<=", file); break;
4685 fputs ("<<=", file); break;
4687 fputs ("<<", file); break;
4692 case 'N': /* Condition, (N)egated */
4693 switch (GET_CODE (x))
4696 fputs ("<>", file); break;
4698 fputs ("=", file); break;
4700 fputs ("<=", file); break;
4702 fputs ("<", file); break;
4704 fputs ("<<", file); break;
4706 fputs ("<<=", file); break;
4708 fputs (">=", file); break;
4710 fputs (">", file); break;
4712 fputs (">>", file); break;
4714 fputs (">>=", file); break;
4719 /* For floating point comparisons. Note that the output
4720 predicates are the complement of the desired mode. The
4721 conditions for GT, GE, LT, LE and LTGT cause an invalid
4722 operation exception if the result is unordered and this
4723 exception is enabled in the floating-point status register. */
4725 switch (GET_CODE (x))
4728 fputs ("!=", file); break;
4730 fputs ("=", file); break;
4732 fputs ("!>", file); break;
4734 fputs ("!>=", file); break;
4736 fputs ("!<", file); break;
4738 fputs ("!<=", file); break;
4740 fputs ("!<>", file); break;
4742 fputs ("!?<=", file); break;
4744 fputs ("!?<", file); break;
4746 fputs ("!?>=", file); break;
4748 fputs ("!?>", file); break;
4750 fputs ("!?=", file); break;
4752 fputs ("!?", file); break;
4754 fputs ("?", file); break;
4759 case 'S': /* Condition, operands are (S)wapped. */
4760 switch (GET_CODE (x))
4763 fputs ("=", file); break;
4765 fputs ("<>", file); break;
4767 fputs ("<", file); break;
4769 fputs ("<=", file); break;
4771 fputs ("<<=", file); break;
4773 fputs ("<<", file); break;
4775 fputs (">", file); break;
4777 fputs (">=", file); break;
4779 fputs (">>=", file); break;
4781 fputs (">>", file); break;
4786 case 'B': /* Condition, (B)oth swapped and negate. */
4787 switch (GET_CODE (x))
4790 fputs ("<>", file); break;
4792 fputs ("=", file); break;
4794 fputs (">=", file); break;
4796 fputs (">", file); break;
4798 fputs (">>", file); break;
4800 fputs (">>=", file); break;
4802 fputs ("<=", file); break;
4804 fputs ("<", file); break;
4806 fputs ("<<", file); break;
4808 fputs ("<<=", file); break;
4814 if (GET_CODE (x) == CONST_INT)
4816 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4821 if (GET_CODE (x) == CONST_INT)
4823 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4828 if (GET_CODE (x) == CONST_INT)
4830 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4835 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4837 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4842 if (GET_CODE (x) == CONST_INT)
4844 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4849 if (GET_CODE (x) == CONST_INT)
4851 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4856 if (GET_CODE (x) == CONST_INT)
4861 switch (GET_CODE (XEXP (x, 0)))
4865 if (ASSEMBLER_DIALECT == 0)
4866 fputs ("s,mb", file);
4868 fputs (",mb", file);
4872 if (ASSEMBLER_DIALECT == 0)
4873 fputs ("s,ma", file);
4875 fputs (",ma", file);
4878 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4879 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4881 if (ASSEMBLER_DIALECT == 0)
4884 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4885 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4887 if (ASSEMBLER_DIALECT == 0)
4888 fputs ("x,s", file);
4892 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4896 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4902 output_global_address (file, x, 0);
4905 output_global_address (file, x, 1);
4907 case 0: /* Don't do anything special */
4912 compute_zdepwi_operands (INTVAL (x), op);
4913 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4919 compute_zdepdi_operands (INTVAL (x), op);
4920 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4924 /* We can get here from a .vtable_inherit due to our
4925 CONSTANT_ADDRESS_P rejecting perfectly good constant
4931 if (GET_CODE (x) == REG)
4933 fputs (reg_names [REGNO (x)], file);
4934 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4940 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4941 && (REGNO (x) & 1) == 0)
4944 else if (GET_CODE (x) == MEM)
4946 int size = GET_MODE_SIZE (GET_MODE (x));
4947 rtx base = NULL_RTX;
4948 switch (GET_CODE (XEXP (x, 0)))
4952 base = XEXP (XEXP (x, 0), 0);
4953 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4957 base = XEXP (XEXP (x, 0), 0);
4958 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4961 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4962 fprintf (file, "%s(%s)",
4963 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4964 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4965 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4966 fprintf (file, "%s(%s)",
4967 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4968 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4969 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4970 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4972 /* Because the REG_POINTER flag can get lost during reload,
4973 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
4974 index and base registers in the combined move patterns. */
4975 rtx base = XEXP (XEXP (x, 0), 1);
4976 rtx index = XEXP (XEXP (x, 0), 0);
4978 fprintf (file, "%s(%s)",
4979 reg_names [REGNO (index)], reg_names [REGNO (base)]);
4982 output_address (XEXP (x, 0));
4985 output_address (XEXP (x, 0));
4990 output_addr_const (file, x);
4993 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4996 output_global_address (FILE *file, rtx x, int round_constant)
4999 /* Imagine (high (const (plus ...))). */
5000 if (GET_CODE (x) == HIGH)
5003 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5004 output_addr_const (file, x);
5005 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5007 output_addr_const (file, x);
5008 fputs ("-$global$", file);
5010 else if (GET_CODE (x) == CONST)
5012 const char *sep = "";
5013 int offset = 0; /* assembler wants -$global$ at end */
5014 rtx base = NULL_RTX;
5016 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5018 base = XEXP (XEXP (x, 0), 0);
5019 output_addr_const (file, base);
5021 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5022 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5025 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5027 base = XEXP (XEXP (x, 0), 1);
5028 output_addr_const (file, base);
5030 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5031 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5034 /* How bogus. The compiler is apparently responsible for
5035 rounding the constant if it uses an LR field selector.
5037 The linker and/or assembler seem a better place since
5038 they have to do this kind of thing already.
5040 If we fail to do this, HP's optimizing linker may eliminate
5041 an addil, but not update the ldw/stw/ldo instruction that
5042 uses the result of the addil. */
5044 offset = ((offset + 0x1000) & ~0x1fff);
5046 if (GET_CODE (XEXP (x, 0)) == PLUS)
5056 else if (GET_CODE (XEXP (x, 0)) == MINUS
5057 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5061 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5062 fputs ("-$global$", file);
5064 fprintf (file, "%s%d", sep, offset);
5067 output_addr_const (file, x);
5070 /* Output boilerplate text to appear at the beginning of the file.
5071 There are several possible versions. */
5072 #define aputs(x) fputs(x, asm_out_file)
5074 pa_file_start_level (void)
5077 aputs ("\t.LEVEL 2.0w\n");
5078 else if (TARGET_PA_20)
5079 aputs ("\t.LEVEL 2.0\n");
5080 else if (TARGET_PA_11)
5081 aputs ("\t.LEVEL 1.1\n");
5083 aputs ("\t.LEVEL 1.0\n");
5087 pa_file_start_space (int sortspace)
5089 aputs ("\t.SPACE $PRIVATE$");
5092 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5093 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5094 "\n\t.SPACE $TEXT$");
5097 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5098 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5102 pa_file_start_file (int want_version)
5104 if (write_symbols != NO_DEBUG)
5106 output_file_directive (asm_out_file, main_input_filename);
5108 aputs ("\t.version\t\"01.01\"\n");
5113 pa_file_start_mcount (const char *aswhat)
5116 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5120 pa_elf_file_start (void)
5122 pa_file_start_level ();
5123 pa_file_start_mcount ("ENTRY");
5124 pa_file_start_file (0);
5128 pa_som_file_start (void)
5130 pa_file_start_level ();
5131 pa_file_start_space (0);
5132 aputs ("\t.IMPORT $global$,DATA\n"
5133 "\t.IMPORT $$dyncall,MILLICODE\n");
5134 pa_file_start_mcount ("CODE");
5135 pa_file_start_file (0);
5139 pa_linux_file_start (void)
5141 pa_file_start_file (1);
5142 pa_file_start_level ();
5143 pa_file_start_mcount ("CODE");
5147 pa_hpux64_gas_file_start (void)
5149 pa_file_start_level ();
5150 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5152 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5154 pa_file_start_file (1);
5158 pa_hpux64_hpas_file_start (void)
5160 pa_file_start_level ();
5161 pa_file_start_space (1);
5162 pa_file_start_mcount ("CODE");
5163 pa_file_start_file (0);
5167 static struct deferred_plabel *
5168 get_plabel (rtx symbol)
5170 const char *fname = XSTR (symbol, 0);
5173 /* See if we have already put this function on the list of deferred
5174 plabels. This list is generally small, so a liner search is not
5175 too ugly. If it proves too slow replace it with something faster. */
5176 for (i = 0; i < n_deferred_plabels; i++)
5177 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5180 /* If the deferred plabel list is empty, or this entry was not found
5181 on the list, create a new entry on the list. */
5182 if (deferred_plabels == NULL || i == n_deferred_plabels)
5186 if (deferred_plabels == 0)
5187 deferred_plabels = (struct deferred_plabel *)
5188 ggc_alloc (sizeof (struct deferred_plabel));
5190 deferred_plabels = (struct deferred_plabel *)
5191 ggc_realloc (deferred_plabels,
5192 ((n_deferred_plabels + 1)
5193 * sizeof (struct deferred_plabel)));
5195 i = n_deferred_plabels++;
5196 deferred_plabels[i].internal_label = gen_label_rtx ();
5197 deferred_plabels[i].symbol = symbol;
5199 /* Gross. We have just implicitly taken the address of this
5200 function. Mark it in the same manner as assemble_name. */
5201 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5203 mark_referenced (id);
5206 return &deferred_plabels[i];
5210 output_deferred_plabels (void)
5213 /* If we have deferred plabels, then we need to switch into the data
5214 section and align it to a 4 byte boundary before we output the
5215 deferred plabels. */
5216 if (n_deferred_plabels)
5219 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5222 /* Now output the deferred plabels. */
5223 for (i = 0; i < n_deferred_plabels; i++)
5225 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5226 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5227 assemble_integer (deferred_plabels[i].symbol,
5228 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5232 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5233 /* Initialize optabs to point to HPUX long double emulation routines. */
5235 pa_hpux_init_libfuncs (void)
5237 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5238 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5239 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5240 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5241 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5242 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5243 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5244 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5245 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5247 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5248 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5249 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5250 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5251 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5252 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5253 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5255 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5256 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5257 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5258 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5260 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5261 ? "__U_Qfcnvfxt_quad_to_sgl"
5262 : "_U_Qfcnvfxt_quad_to_sgl");
5263 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5264 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5265 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5267 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5268 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5272 /* HP's millicode routines mean something special to the assembler.
5273 Keep track of which ones we have used. */
5275 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5276 static void import_milli (enum millicodes);
5277 static char imported[(int) end1000];
5278 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5279 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5280 #define MILLI_START 10
5283 import_milli (enum millicodes code)
5285 char str[sizeof (import_string)];
5287 if (!imported[(int) code])
5289 imported[(int) code] = 1;
5290 strcpy (str, import_string);
5291 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5292 output_asm_insn (str, 0);
5296 /* The register constraints have put the operands and return value in
5297 the proper registers. */
5300 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5302 import_milli (mulI);
5303 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5306 /* Emit the rtl for doing a division by a constant. */
5308 /* Do magic division millicodes exist for this value? */
5309 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5311 /* We'll use an array to keep track of the magic millicodes and
5312 whether or not we've used them already. [n][0] is signed, [n][1] is
5315 static int div_milli[16][2];
5318 emit_hpdiv_const (rtx *operands, int unsignedp)
5320 if (GET_CODE (operands[2]) == CONST_INT
5321 && INTVAL (operands[2]) > 0
5322 && INTVAL (operands[2]) < 16
5323 && magic_milli[INTVAL (operands[2])])
5325 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5327 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5331 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5332 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5334 gen_rtx_REG (SImode, 26),
5336 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5337 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5338 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5339 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5340 gen_rtx_CLOBBER (VOIDmode, ret))));
5341 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5348 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5352 /* If the divisor is a constant, try to use one of the special
5354 if (GET_CODE (operands[0]) == CONST_INT)
5356 static char buf[100];
5357 divisor = INTVAL (operands[0]);
5358 if (!div_milli[divisor][unsignedp])
5360 div_milli[divisor][unsignedp] = 1;
5362 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5364 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5368 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5369 INTVAL (operands[0]));
5370 return output_millicode_call (insn,
5371 gen_rtx_SYMBOL_REF (SImode, buf));
5375 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5376 INTVAL (operands[0]));
5377 return output_millicode_call (insn,
5378 gen_rtx_SYMBOL_REF (SImode, buf));
5381 /* Divisor isn't a special constant. */
5386 import_milli (divU);
5387 return output_millicode_call (insn,
5388 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5392 import_milli (divI);
5393 return output_millicode_call (insn,
5394 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5399 /* Output a $$rem millicode to do mod. */
5402 output_mod_insn (int unsignedp, rtx insn)
5406 import_milli (remU);
5407 return output_millicode_call (insn,
5408 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5412 import_milli (remI);
5413 return output_millicode_call (insn,
5414 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5419 output_arg_descriptor (rtx call_insn)
5421 const char *arg_regs[4];
5422 enum machine_mode arg_mode;
5424 int i, output_flag = 0;
5427 /* We neither need nor want argument location descriptors for the
5428 64bit runtime environment or the ELF32 environment. */
5429 if (TARGET_64BIT || TARGET_ELF32)
5432 for (i = 0; i < 4; i++)
5435 /* Specify explicitly that no argument relocations should take place
5436 if using the portable runtime calling conventions. */
5437 if (TARGET_PORTABLE_RUNTIME)
5439 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5444 if (GET_CODE (call_insn) != CALL_INSN)
5446 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5448 rtx use = XEXP (link, 0);
5450 if (! (GET_CODE (use) == USE
5451 && GET_CODE (XEXP (use, 0)) == REG
5452 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5455 arg_mode = GET_MODE (XEXP (use, 0));
5456 regno = REGNO (XEXP (use, 0));
5457 if (regno >= 23 && regno <= 26)
5459 arg_regs[26 - regno] = "GR";
5460 if (arg_mode == DImode)
5461 arg_regs[25 - regno] = "GR";
5463 else if (regno >= 32 && regno <= 39)
5465 if (arg_mode == SFmode)
5466 arg_regs[(regno - 32) / 2] = "FR";
5469 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5470 arg_regs[(regno - 34) / 2] = "FR";
5471 arg_regs[(regno - 34) / 2 + 1] = "FU";
5473 arg_regs[(regno - 34) / 2] = "FU";
5474 arg_regs[(regno - 34) / 2 + 1] = "FR";
5479 fputs ("\t.CALL ", asm_out_file);
5480 for (i = 0; i < 4; i++)
5485 fputc (',', asm_out_file);
5486 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5489 fputc ('\n', asm_out_file);
5492 /* Return the class of any secondary reload register that is needed to
5493 move IN into a register in class CLASS using mode MODE.
5495 Profiling has showed this routine and its descendants account for
5496 a significant amount of compile time (~7%). So it has been
5497 optimized to reduce redundant computations and eliminate useless
5500 It might be worthwhile to try and make this a leaf function too. */
5503 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5505 int regno, is_symbolic;
5507 /* Trying to load a constant into a FP register during PIC code
5508 generation will require %r1 as a scratch register. */
5510 && GET_MODE_CLASS (mode) == MODE_INT
5511 && FP_REG_CLASS_P (class)
5512 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5515 /* Profiling showed the PA port spends about 1.3% of its compilation
5516 time in true_regnum from calls inside secondary_reload_class. */
5518 if (GET_CODE (in) == REG)
5521 if (regno >= FIRST_PSEUDO_REGISTER)
5522 regno = true_regnum (in);
5524 else if (GET_CODE (in) == SUBREG)
5525 regno = true_regnum (in);
5529 /* If we have something like (mem (mem (...)), we can safely assume the
5530 inner MEM will end up in a general register after reloading, so there's
5531 no need for a secondary reload. */
5532 if (GET_CODE (in) == MEM
5533 && GET_CODE (XEXP (in, 0)) == MEM)
5536 /* Handle out of range displacement for integer mode loads/stores of
5538 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5539 && GET_MODE_CLASS (mode) == MODE_INT
5540 && FP_REG_CLASS_P (class))
5541 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5542 return GENERAL_REGS;
5544 /* A SAR<->FP register copy requires a secondary register (GPR) as
5545 well as secondary memory. */
5546 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5547 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5548 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5549 return GENERAL_REGS;
5551 if (GET_CODE (in) == HIGH)
5554 /* Profiling has showed GCC spends about 2.6% of its compilation
5555 time in symbolic_operand from calls inside secondary_reload_class.
5557 We use an inline copy and only compute its return value once to avoid
5559 switch (GET_CODE (in))
5569 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5570 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5571 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5581 && read_only_operand (in, VOIDmode))
5584 if (class != R1_REGS && is_symbolic)
5590 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5591 by invisible reference. As a GCC extension, we also pass anything
5592 with a zero or variable size by reference.
5594 The 64-bit runtime does not describe passing any types by invisible
5595 reference. The internals of GCC can't currently handle passing
5596 empty structures, and zero or variable length arrays when they are
5597 not passed entirely on the stack or by reference. Thus, as a GCC
5598 extension, we pass these types by reference. The HP compiler doesn't
5599 support these types, so hopefully there shouldn't be any compatibility
5600 issues. This may have to be revisited when HP releases a C99 compiler
5601 or updates the ABI. */
5604 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5605 enum machine_mode mode, tree type,
5606 bool named ATTRIBUTE_UNUSED)
5611 size = int_size_in_bytes (type);
5613 size = GET_MODE_SIZE (mode);
5618 return size <= 0 || size > 8;
5622 function_arg_padding (enum machine_mode mode, tree type)
5625 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5627 /* Return none if justification is not required. */
5629 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5630 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5633 /* The directions set here are ignored when a BLKmode argument larger
5634 than a word is placed in a register. Different code is used for
5635 the stack and registers. This makes it difficult to have a
5636 consistent data representation for both the stack and registers.
5637 For both runtimes, the justification and padding for arguments on
5638 the stack and in registers should be identical. */
5640 /* The 64-bit runtime specifies left justification for aggregates. */
5643 /* The 32-bit runtime architecture specifies right justification.
5644 When the argument is passed on the stack, the argument is padded
5645 with garbage on the left. The HP compiler pads with zeros. */
5649 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5656 /* Do what is necessary for `va_start'. We look at the current function
5657 to determine if stdargs or varargs is used and fill in an initial
5658 va_list. A pointer to this constructor is returned. */
5661 hppa_builtin_saveregs (void)
5664 tree fntype = TREE_TYPE (current_function_decl);
5665 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5666 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5667 != void_type_node)))
5668 ? UNITS_PER_WORD : 0);
5671 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5673 offset = current_function_arg_offset_rtx;
5679 /* Adjust for varargs/stdarg differences. */
5681 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5683 offset = current_function_arg_offset_rtx;
5685 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5686 from the incoming arg pointer and growing to larger addresses. */
5687 for (i = 26, off = -64; i >= 19; i--, off += 8)
5688 emit_move_insn (gen_rtx_MEM (word_mode,
5689 plus_constant (arg_pointer_rtx, off)),
5690 gen_rtx_REG (word_mode, i));
5692 /* The incoming args pointer points just beyond the flushback area;
5693 normally this is not a serious concern. However, when we are doing
5694 varargs/stdargs we want to make the arg pointer point to the start
5695 of the incoming argument area. */
5696 emit_move_insn (virtual_incoming_args_rtx,
5697 plus_constant (arg_pointer_rtx, -64));
5699 /* Now return a pointer to the first anonymous argument. */
5700 return copy_to_reg (expand_binop (Pmode, add_optab,
5701 virtual_incoming_args_rtx,
5702 offset, 0, 0, OPTAB_LIB_WIDEN));
5705 /* Store general registers on the stack. */
5706 dest = gen_rtx_MEM (BLKmode,
5707 plus_constant (current_function_internal_arg_pointer,
5709 set_mem_alias_set (dest, get_varargs_alias_set ());
5710 set_mem_align (dest, BITS_PER_WORD);
5711 move_block_from_reg (23, dest, 4);
5713 /* move_block_from_reg will emit code to store the argument registers
5714 individually as scalar stores.
5716 However, other insns may later load from the same addresses for
5717 a structure load (passing a struct to a varargs routine).
5719 The alias code assumes that such aliasing can never happen, so we
5720 have to keep memory referencing insns from moving up beyond the
5721 last argument register store. So we emit a blockage insn here. */
5722 emit_insn (gen_blockage ());
5724 return copy_to_reg (expand_binop (Pmode, add_optab,
5725 current_function_internal_arg_pointer,
5726 offset, 0, 0, OPTAB_LIB_WIDEN));
5730 hppa_va_start (tree valist, rtx nextarg)
5732 nextarg = expand_builtin_saveregs ();
5733 std_expand_builtin_va_start (valist, nextarg);
5737 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5741 /* Args grow upward. We can use the generic routines. */
5742 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5744 else /* !TARGET_64BIT */
5746 tree ptr = build_pointer_type (type);
5749 unsigned int size, ofs;
5752 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5756 ptr = build_pointer_type (type);
5758 size = int_size_in_bytes (type);
5759 valist_type = TREE_TYPE (valist);
5761 /* Args grow down. Not handled by generic routines. */
5763 u = fold_convert (valist_type, size_in_bytes (type));
5764 t = build (MINUS_EXPR, valist_type, valist, u);
5766 /* Copied from va-pa.h, but we probably don't need to align to
5767 word size, since we generate and preserve that invariant. */
5768 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
5769 t = build (BIT_AND_EXPR, valist_type, t, u);
5771 t = build (MODIFY_EXPR, valist_type, valist, t);
5773 ofs = (8 - size) % 4;
5776 u = fold_convert (valist_type, size_int (ofs));
5777 t = build (PLUS_EXPR, valist_type, t, u);
5780 t = fold_convert (ptr, t);
5781 t = build_fold_indirect_ref (t);
5784 t = build_fold_indirect_ref (t);
5790 /* True if MODE is valid for the target. By "valid", we mean able to
5791 be manipulated in non-trivial ways. In particular, this means all
5792 the arithmetic is supported.
5794 Currently, TImode is not valid as the HP 64-bit runtime documentation
5795 doesn't document the alignment and calling conventions for this type.
5796 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
5797 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
5800 pa_scalar_mode_supported_p (enum machine_mode mode)
5802 int precision = GET_MODE_PRECISION (mode);
5804 switch (GET_MODE_CLASS (mode))
5806 case MODE_PARTIAL_INT:
5808 if (precision == CHAR_TYPE_SIZE)
5810 if (precision == SHORT_TYPE_SIZE)
5812 if (precision == INT_TYPE_SIZE)
5814 if (precision == LONG_TYPE_SIZE)
5816 if (precision == LONG_LONG_TYPE_SIZE)
5821 if (precision == FLOAT_TYPE_SIZE)
5823 if (precision == DOUBLE_TYPE_SIZE)
5825 if (precision == LONG_DOUBLE_TYPE_SIZE)
5834 /* This routine handles all the normal conditional branch sequences we
5835 might need to generate. It handles compare immediate vs compare
5836 register, nullification of delay slots, varying length branches,
5837 negated branches, and all combinations of the above. It returns the
5838 output appropriate to emit the branch corresponding to all given
5842 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
5844 static char buf[100];
5848 /* A conditional branch to the following instruction (e.g. the delay slot)
5849 is asking for a disaster. This can happen when not optimizing and
5850 when jump optimization fails.
5852 While it is usually safe to emit nothing, this can fail if the
5853 preceding instruction is a nullified branch with an empty delay
5854 slot and the same branch target as this branch. We could check
5855 for this but jump optimization should eliminate nop jumps. It
5856 is always safe to emit a nop. */
5857 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5860 /* The doubleword form of the cmpib instruction doesn't have the LEU
5861 and GTU conditions while the cmpb instruction does. Since we accept
5862 zero for cmpb, we must ensure that we use cmpb for the comparison. */
5863 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
5864 operands[2] = gen_rtx_REG (DImode, 0);
5866 /* If this is a long branch with its delay slot unfilled, set `nullify'
5867 as it can nullify the delay slot and save a nop. */
5868 if (length == 8 && dbr_sequence_length () == 0)
5871 /* If this is a short forward conditional branch which did not get
5872 its delay slot filled, the delay slot can still be nullified. */
5873 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5874 nullify = forward_branch_p (insn);
5876 /* A forward branch over a single nullified insn can be done with a
5877 comclr instruction. This avoids a single cycle penalty due to
5878 mis-predicted branch if we fall through (branch not taken). */
5880 && next_real_insn (insn) != 0
5881 && get_attr_length (next_real_insn (insn)) == 4
5882 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5888 /* All short conditional branches except backwards with an unfilled
5892 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5894 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5895 if (GET_MODE (operands[1]) == DImode)
5898 strcat (buf, "%B3");
5900 strcat (buf, "%S3");
5902 strcat (buf, " %2,%r1,%%r0");
5904 strcat (buf, ",n %2,%r1,%0");
5906 strcat (buf, " %2,%r1,%0");
5909 /* All long conditionals. Note a short backward branch with an
5910 unfilled delay slot is treated just like a long backward branch
5911 with an unfilled delay slot. */
5913 /* Handle weird backwards branch with a filled delay slot
5914 with is nullified. */
5915 if (dbr_sequence_length () != 0
5916 && ! forward_branch_p (insn)
5919 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5920 if (GET_MODE (operands[1]) == DImode)
5923 strcat (buf, "%S3");
5925 strcat (buf, "%B3");
5926 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5928 /* Handle short backwards branch with an unfilled delay slot.
5929 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5930 taken and untaken branches. */
5931 else if (dbr_sequence_length () == 0
5932 && ! forward_branch_p (insn)
5933 && INSN_ADDRESSES_SET_P ()
5934 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5935 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5937 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5938 if (GET_MODE (operands[1]) == DImode)
5941 strcat (buf, "%B3 %2,%r1,%0%#");
5943 strcat (buf, "%S3 %2,%r1,%0%#");
5947 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5948 if (GET_MODE (operands[1]) == DImode)
5951 strcat (buf, "%S3");
5953 strcat (buf, "%B3");
5955 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5957 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5963 xoperands[0] = operands[0];
5964 xoperands[1] = operands[1];
5965 xoperands[2] = operands[2];
5966 xoperands[3] = operands[3];
5968 /* The reversed conditional branch must branch over one additional
5969 instruction if the delay slot is filled. If the delay slot
5970 is empty, the instruction after the reversed condition branch
5971 must be nullified. */
5972 nullify = dbr_sequence_length () == 0;
5973 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
5975 /* Create a reversed conditional branch which branches around
5976 the following insns. */
5977 if (GET_MODE (operands[1]) != DImode)
5983 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
5986 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
5992 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
5995 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6004 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6007 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6013 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6016 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6020 output_asm_insn (buf, xoperands);
6021 return output_lbranch (operands[0], insn);
6029 /* This routine handles long unconditional branches that exceed the
6030 maximum range of a simple branch instruction. */
6033 output_lbranch (rtx dest, rtx insn)
6037 xoperands[0] = dest;
6039 /* First, free up the delay slot. */
6040 if (dbr_sequence_length () != 0)
6042 /* We can't handle a jump in the delay slot. */
6043 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6046 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6049 /* Now delete the delay insn. */
6050 PUT_CODE (NEXT_INSN (insn), NOTE);
6051 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6052 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6055 /* Output an insn to save %r1. The runtime documentation doesn't
6056 specify whether the "Clean Up" slot in the callers frame can
6057 be clobbered by the callee. It isn't copied by HP's builtin
6058 alloca, so this suggests that it can be clobbered if necessary.
6059 The "Static Link" location is copied by HP builtin alloca, so
6060 we avoid using it. Using the cleanup slot might be a problem
6061 if we have to interoperate with languages that pass cleanup
6062 information. However, it should be possible to handle these
6063 situations with GCC's asm feature.
6065 The "Current RP" slot is reserved for the called procedure, so
6066 we try to use it when we don't have a frame of our own. It's
6067 rather unlikely that we won't have a frame when we need to emit
6070 Really the way to go long term is a register scavenger; goto
6071 the target of the jump and find a register which we can use
6072 as a scratch to hold the value in %r1. Then, we wouldn't have
6073 to free up the delay slot or clobber a slot that may be needed
6074 for other purposes. */
6077 if (actual_fsize == 0 && !regs_ever_live[2])
6078 /* Use the return pointer slot in the frame marker. */
6079 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6081 /* Use the slot at -40 in the frame marker since HP builtin
6082 alloca doesn't copy it. */
6083 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6087 if (actual_fsize == 0 && !regs_ever_live[2])
6088 /* Use the return pointer slot in the frame marker. */
6089 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6091 /* Use the "Clean Up" slot in the frame marker. In GCC,
6092 the only other use of this location is for copying a
6093 floating point double argument from a floating-point
6094 register to two general registers. The copy is done
6095 as an "atomic" operation when outputting a call, so it
6096 won't interfere with our using the location here. */
6097 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6100 if (TARGET_PORTABLE_RUNTIME)
6102 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6103 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6104 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6108 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6109 if (TARGET_SOM || !TARGET_GAS)
6111 xoperands[1] = gen_label_rtx ();
6112 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6113 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6114 CODE_LABEL_NUMBER (xoperands[1]));
6115 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6119 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6120 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6122 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6125 /* Now output a very long branch to the original target. */
6126 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6128 /* Now restore the value of %r1 in the delay slot. */
6131 if (actual_fsize == 0 && !regs_ever_live[2])
6132 return "ldd -16(%%r30),%%r1";
6134 return "ldd -40(%%r30),%%r1";
6138 if (actual_fsize == 0 && !regs_ever_live[2])
6139 return "ldw -20(%%r30),%%r1";
6141 return "ldw -12(%%r30),%%r1";
6145 /* This routine handles all the branch-on-bit conditional branch sequences we
6146 might need to generate. It handles nullification of delay slots,
6147 varying length branches, negated branches and all combinations of the
6148 above. it returns the appropriate output template to emit the branch. */
6151 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6152 int negated, rtx insn, int which)
6154 static char buf[100];
6157 /* A conditional branch to the following instruction (e.g. the delay slot) is
6158 asking for a disaster. I do not think this can happen as this pattern
6159 is only used when optimizing; jump optimization should eliminate the
6160 jump. But be prepared just in case. */
6162 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6165 /* If this is a long branch with its delay slot unfilled, set `nullify'
6166 as it can nullify the delay slot and save a nop. */
6167 if (length == 8 && dbr_sequence_length () == 0)
6170 /* If this is a short forward conditional branch which did not get
6171 its delay slot filled, the delay slot can still be nullified. */
6172 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6173 nullify = forward_branch_p (insn);
6175 /* A forward branch over a single nullified insn can be done with a
6176 extrs instruction. This avoids a single cycle penalty due to
6177 mis-predicted branch if we fall through (branch not taken). */
6180 && next_real_insn (insn) != 0
6181 && get_attr_length (next_real_insn (insn)) == 4
6182 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6189 /* All short conditional branches except backwards with an unfilled
6193 strcpy (buf, "{extrs,|extrw,s,}");
6195 strcpy (buf, "bb,");
6196 if (useskip && GET_MODE (operands[0]) == DImode)
6197 strcpy (buf, "extrd,s,*");
6198 else if (GET_MODE (operands[0]) == DImode)
6199 strcpy (buf, "bb,*");
6200 if ((which == 0 && negated)
6201 || (which == 1 && ! negated))
6206 strcat (buf, " %0,%1,1,%%r0");
6207 else if (nullify && negated)
6208 strcat (buf, ",n %0,%1,%3");
6209 else if (nullify && ! negated)
6210 strcat (buf, ",n %0,%1,%2");
6211 else if (! nullify && negated)
6212 strcat (buf, "%0,%1,%3");
6213 else if (! nullify && ! negated)
6214 strcat (buf, " %0,%1,%2");
6217 /* All long conditionals. Note a short backward branch with an
6218 unfilled delay slot is treated just like a long backward branch
6219 with an unfilled delay slot. */
6221 /* Handle weird backwards branch with a filled delay slot
6222 with is nullified. */
6223 if (dbr_sequence_length () != 0
6224 && ! forward_branch_p (insn)
6227 strcpy (buf, "bb,");
6228 if (GET_MODE (operands[0]) == DImode)
6230 if ((which == 0 && negated)
6231 || (which == 1 && ! negated))
6236 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6238 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6240 /* Handle short backwards branch with an unfilled delay slot.
6241 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6242 taken and untaken branches. */
6243 else if (dbr_sequence_length () == 0
6244 && ! forward_branch_p (insn)
6245 && INSN_ADDRESSES_SET_P ()
6246 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6247 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6249 strcpy (buf, "bb,");
6250 if (GET_MODE (operands[0]) == DImode)
6252 if ((which == 0 && negated)
6253 || (which == 1 && ! negated))
6258 strcat (buf, " %0,%1,%3%#");
6260 strcat (buf, " %0,%1,%2%#");
6264 strcpy (buf, "{extrs,|extrw,s,}");
6265 if (GET_MODE (operands[0]) == DImode)
6266 strcpy (buf, "extrd,s,*");
6267 if ((which == 0 && negated)
6268 || (which == 1 && ! negated))
6272 if (nullify && negated)
6273 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6274 else if (nullify && ! negated)
6275 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6277 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6279 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6289 /* This routine handles all the branch-on-variable-bit conditional branch
6290 sequences we might need to generate. It handles nullification of delay
6291 slots, varying length branches, negated branches and all combinations
6292 of the above. it returns the appropriate output template to emit the
6296 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6297 int negated, rtx insn, int which)
6299 static char buf[100];
6302 /* A conditional branch to the following instruction (e.g. the delay slot) is
6303 asking for a disaster. I do not think this can happen as this pattern
6304 is only used when optimizing; jump optimization should eliminate the
6305 jump. But be prepared just in case. */
6307 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6310 /* If this is a long branch with its delay slot unfilled, set `nullify'
6311 as it can nullify the delay slot and save a nop. */
6312 if (length == 8 && dbr_sequence_length () == 0)
6315 /* If this is a short forward conditional branch which did not get
6316 its delay slot filled, the delay slot can still be nullified. */
6317 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6318 nullify = forward_branch_p (insn);
6320 /* A forward branch over a single nullified insn can be done with a
6321 extrs instruction. This avoids a single cycle penalty due to
6322 mis-predicted branch if we fall through (branch not taken). */
6325 && next_real_insn (insn) != 0
6326 && get_attr_length (next_real_insn (insn)) == 4
6327 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6334 /* All short conditional branches except backwards with an unfilled
6338 strcpy (buf, "{vextrs,|extrw,s,}");
6340 strcpy (buf, "{bvb,|bb,}");
6341 if (useskip && GET_MODE (operands[0]) == DImode)
6342 strcpy (buf, "extrd,s,*");
6343 else if (GET_MODE (operands[0]) == DImode)
6344 strcpy (buf, "bb,*");
6345 if ((which == 0 && negated)
6346 || (which == 1 && ! negated))
6351 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6352 else if (nullify && negated)
6353 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6354 else if (nullify && ! negated)
6355 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6356 else if (! nullify && negated)
6357 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6358 else if (! nullify && ! negated)
6359 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6362 /* All long conditionals. Note a short backward branch with an
6363 unfilled delay slot is treated just like a long backward branch
6364 with an unfilled delay slot. */
6366 /* Handle weird backwards branch with a filled delay slot
6367 with is nullified. */
6368 if (dbr_sequence_length () != 0
6369 && ! forward_branch_p (insn)
6372 strcpy (buf, "{bvb,|bb,}");
6373 if (GET_MODE (operands[0]) == DImode)
6375 if ((which == 0 && negated)
6376 || (which == 1 && ! negated))
6381 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6383 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6385 /* Handle short backwards branch with an unfilled delay slot.
6386 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6387 taken and untaken branches. */
6388 else if (dbr_sequence_length () == 0
6389 && ! forward_branch_p (insn)
6390 && INSN_ADDRESSES_SET_P ()
6391 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6392 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6394 strcpy (buf, "{bvb,|bb,}");
6395 if (GET_MODE (operands[0]) == DImode)
6397 if ((which == 0 && negated)
6398 || (which == 1 && ! negated))
6403 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6405 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6409 strcpy (buf, "{vextrs,|extrw,s,}");
6410 if (GET_MODE (operands[0]) == DImode)
6411 strcpy (buf, "extrd,s,*");
6412 if ((which == 0 && negated)
6413 || (which == 1 && ! negated))
6417 if (nullify && negated)
6418 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6419 else if (nullify && ! negated)
6420 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6422 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6424 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6434 /* Return the output template for emitting a dbra type insn.
6436 Note it may perform some output operations on its own before
6437 returning the final output string. */
6439 output_dbra (rtx *operands, rtx insn, int which_alternative)
6442 /* A conditional branch to the following instruction (e.g. the delay slot) is
6443 asking for a disaster. Be prepared! */
6445 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6447 if (which_alternative == 0)
6448 return "ldo %1(%0),%0";
6449 else if (which_alternative == 1)
6451 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6452 output_asm_insn ("ldw -16(%%r30),%4", operands);
6453 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6454 return "{fldws|fldw} -16(%%r30),%0";
6458 output_asm_insn ("ldw %0,%4", operands);
6459 return "ldo %1(%4),%4\n\tstw %4,%0";
6463 if (which_alternative == 0)
6465 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6466 int length = get_attr_length (insn);
6468 /* If this is a long branch with its delay slot unfilled, set `nullify'
6469 as it can nullify the delay slot and save a nop. */
6470 if (length == 8 && dbr_sequence_length () == 0)
6473 /* If this is a short forward conditional branch which did not get
6474 its delay slot filled, the delay slot can still be nullified. */
6475 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6476 nullify = forward_branch_p (insn);
6478 /* Handle short versions first. */
6479 if (length == 4 && nullify)
6480 return "addib,%C2,n %1,%0,%3";
6481 else if (length == 4 && ! nullify)
6482 return "addib,%C2 %1,%0,%3";
6483 else if (length == 8)
6485 /* Handle weird backwards branch with a fulled delay slot
6486 which is nullified. */
6487 if (dbr_sequence_length () != 0
6488 && ! forward_branch_p (insn)
6490 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6491 /* Handle short backwards branch with an unfilled delay slot.
6492 Using a addb;nop rather than addi;bl saves 1 cycle for both
6493 taken and untaken branches. */
6494 else if (dbr_sequence_length () == 0
6495 && ! forward_branch_p (insn)
6496 && INSN_ADDRESSES_SET_P ()
6497 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6498 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6499 return "addib,%C2 %1,%0,%3%#";
6501 /* Handle normal cases. */
6503 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6505 return "addi,%N2 %1,%0,%0\n\tb %3";
6510 /* Deal with gross reload from FP register case. */
6511 else if (which_alternative == 1)
6513 /* Move loop counter from FP register to MEM then into a GR,
6514 increment the GR, store the GR into MEM, and finally reload
6515 the FP register from MEM from within the branch's delay slot. */
6516 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6518 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6519 if (get_attr_length (insn) == 24)
6520 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6522 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6524 /* Deal with gross reload from memory case. */
6527 /* Reload loop counter from memory, the store back to memory
6528 happens in the branch's delay slot. */
6529 output_asm_insn ("ldw %0,%4", operands);
6530 if (get_attr_length (insn) == 12)
6531 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6533 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6537 /* Return the output template for emitting a dbra type insn.
6539 Note it may perform some output operations on its own before
6540 returning the final output string. */
6542 output_movb (rtx *operands, rtx insn, int which_alternative,
6543 int reverse_comparison)
6546 /* A conditional branch to the following instruction (e.g. the delay slot) is
6547 asking for a disaster. Be prepared! */
6549 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6551 if (which_alternative == 0)
6552 return "copy %1,%0";
6553 else if (which_alternative == 1)
6555 output_asm_insn ("stw %1,-16(%%r30)", operands);
6556 return "{fldws|fldw} -16(%%r30),%0";
6558 else if (which_alternative == 2)
6564 /* Support the second variant. */
6565 if (reverse_comparison)
6566 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6568 if (which_alternative == 0)
6570 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6571 int length = get_attr_length (insn);
6573 /* If this is a long branch with its delay slot unfilled, set `nullify'
6574 as it can nullify the delay slot and save a nop. */
6575 if (length == 8 && dbr_sequence_length () == 0)
6578 /* If this is a short forward conditional branch which did not get
6579 its delay slot filled, the delay slot can still be nullified. */
6580 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6581 nullify = forward_branch_p (insn);
6583 /* Handle short versions first. */
6584 if (length == 4 && nullify)
6585 return "movb,%C2,n %1,%0,%3";
6586 else if (length == 4 && ! nullify)
6587 return "movb,%C2 %1,%0,%3";
6588 else if (length == 8)
6590 /* Handle weird backwards branch with a filled delay slot
6591 which is nullified. */
6592 if (dbr_sequence_length () != 0
6593 && ! forward_branch_p (insn)
6595 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6597 /* Handle short backwards branch with an unfilled delay slot.
6598 Using a movb;nop rather than or;bl saves 1 cycle for both
6599 taken and untaken branches. */
6600 else if (dbr_sequence_length () == 0
6601 && ! forward_branch_p (insn)
6602 && INSN_ADDRESSES_SET_P ()
6603 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6604 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6605 return "movb,%C2 %1,%0,%3%#";
6606 /* Handle normal cases. */
6608 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6610 return "or,%N2 %1,%%r0,%0\n\tb %3";
6615 /* Deal with gross reload from FP register case. */
6616 else if (which_alternative == 1)
6618 /* Move loop counter from FP register to MEM then into a GR,
6619 increment the GR, store the GR into MEM, and finally reload
6620 the FP register from MEM from within the branch's delay slot. */
6621 output_asm_insn ("stw %1,-16(%%r30)", operands);
6622 if (get_attr_length (insn) == 12)
6623 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6625 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6627 /* Deal with gross reload from memory case. */
6628 else if (which_alternative == 2)
6630 /* Reload loop counter from memory, the store back to memory
6631 happens in the branch's delay slot. */
6632 if (get_attr_length (insn) == 8)
6633 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6635 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6637 /* Handle SAR as a destination. */
6640 if (get_attr_length (insn) == 8)
6641 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6643 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6647 /* Copy any FP arguments in INSN into integer registers. */
6649 copy_fp_args (rtx insn)
6654 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6656 int arg_mode, regno;
6657 rtx use = XEXP (link, 0);
6659 if (! (GET_CODE (use) == USE
6660 && GET_CODE (XEXP (use, 0)) == REG
6661 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6664 arg_mode = GET_MODE (XEXP (use, 0));
6665 regno = REGNO (XEXP (use, 0));
6667 /* Is it a floating point register? */
6668 if (regno >= 32 && regno <= 39)
6670 /* Copy the FP register into an integer register via memory. */
6671 if (arg_mode == SFmode)
6673 xoperands[0] = XEXP (use, 0);
6674 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6675 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6676 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6680 xoperands[0] = XEXP (use, 0);
6681 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6682 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6683 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6684 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6690 /* Compute length of the FP argument copy sequence for INSN. */
6692 length_fp_args (rtx insn)
6697 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6699 int arg_mode, regno;
6700 rtx use = XEXP (link, 0);
6702 if (! (GET_CODE (use) == USE
6703 && GET_CODE (XEXP (use, 0)) == REG
6704 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6707 arg_mode = GET_MODE (XEXP (use, 0));
6708 regno = REGNO (XEXP (use, 0));
6710 /* Is it a floating point register? */
6711 if (regno >= 32 && regno <= 39)
6713 if (arg_mode == SFmode)
6723 /* Return the attribute length for the millicode call instruction INSN.
6724 The length must match the code generated by output_millicode_call.
6725 We include the delay slot in the returned length as it is better to
6726 over estimate the length than to under estimate it. */
6729 attr_length_millicode_call (rtx insn)
6731 unsigned long distance = -1;
6732 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6734 if (INSN_ADDRESSES_SET_P ())
6736 distance = (total + insn_current_reference_address (insn));
6737 if (distance < total)
6743 if (!TARGET_LONG_CALLS && distance < 7600000)
6748 else if (TARGET_PORTABLE_RUNTIME)
6752 if (!TARGET_LONG_CALLS && distance < 240000)
6755 if (TARGET_LONG_ABS_CALL && !flag_pic)
6762 /* INSN is a function call. It may have an unconditional jump
6765 CALL_DEST is the routine we are calling. */
6768 output_millicode_call (rtx insn, rtx call_dest)
6770 int attr_length = get_attr_length (insn);
6771 int seq_length = dbr_sequence_length ();
6776 xoperands[0] = call_dest;
6777 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6779 /* Handle the common case where we are sure that the branch will
6780 reach the beginning of the $CODE$ subspace. The within reach
6781 form of the $$sh_func_adrs call has a length of 28. Because
6782 it has an attribute type of multi, it never has a nonzero
6783 sequence length. The length of the $$sh_func_adrs is the same
6784 as certain out of reach PIC calls to other routines. */
6785 if (!TARGET_LONG_CALLS
6786 && ((seq_length == 0
6787 && (attr_length == 12
6788 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6789 || (seq_length != 0 && attr_length == 8)))
6791 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6797 /* It might seem that one insn could be saved by accessing
6798 the millicode function using the linkage table. However,
6799 this doesn't work in shared libraries and other dynamically
6800 loaded objects. Using a pc-relative sequence also avoids
6801 problems related to the implicit use of the gp register. */
6802 output_asm_insn ("b,l .+8,%%r1", xoperands);
6806 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6807 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6811 xoperands[1] = gen_label_rtx ();
6812 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6813 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6814 CODE_LABEL_NUMBER (xoperands[1]));
6815 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6818 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6820 else if (TARGET_PORTABLE_RUNTIME)
6822 /* Pure portable runtime doesn't allow be/ble; we also don't
6823 have PIC support in the assembler/linker, so this sequence
6826 /* Get the address of our target into %r1. */
6827 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6828 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6830 /* Get our return address into %r31. */
6831 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6832 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6834 /* Jump to our target address in %r1. */
6835 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6839 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6841 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6843 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6847 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6848 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6850 if (TARGET_SOM || !TARGET_GAS)
6852 /* The HP assembler can generate relocations for the
6853 difference of two symbols. GAS can do this for a
6854 millicode symbol but not an arbitrary external
6855 symbol when generating SOM output. */
6856 xoperands[1] = gen_label_rtx ();
6857 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6858 CODE_LABEL_NUMBER (xoperands[1]));
6859 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6860 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6864 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6865 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6869 /* Jump to our target address in %r1. */
6870 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6874 if (seq_length == 0)
6875 output_asm_insn ("nop", xoperands);
6877 /* We are done if there isn't a jump in the delay slot. */
6878 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6881 /* This call has an unconditional jump in its delay slot. */
6882 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6884 /* See if the return address can be adjusted. Use the containing
6885 sequence insn's address. */
6886 if (INSN_ADDRESSES_SET_P ())
6888 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6889 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6890 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6892 if (VAL_14_BITS_P (distance))
6894 xoperands[1] = gen_label_rtx ();
6895 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6896 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6897 CODE_LABEL_NUMBER (xoperands[1]));
6900 /* ??? This branch may not reach its target. */
6901 output_asm_insn ("nop\n\tb,n %0", xoperands);
6904 /* ??? This branch may not reach its target. */
6905 output_asm_insn ("nop\n\tb,n %0", xoperands);
6907 /* Delete the jump. */
6908 PUT_CODE (NEXT_INSN (insn), NOTE);
6909 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6910 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6915 /* Return the attribute length of the call instruction INSN. The SIBCALL
6916 flag indicates whether INSN is a regular call or a sibling call. The
6917 length returned must be longer than the code actually generated by
6918 output_call. Since branch shortening is done before delay branch
6919 sequencing, there is no way to determine whether or not the delay
6920 slot will be filled during branch shortening. Even when the delay
6921 slot is filled, we may have to add a nop if the delay slot contains
6922 a branch that can't reach its target. Thus, we always have to include
6923 the delay slot in the length estimate. This used to be done in
6924 pa_adjust_insn_length but we do it here now as some sequences always
6925 fill the delay slot and we can save four bytes in the estimate for
6929 attr_length_call (rtx insn, int sibcall)
6935 rtx pat = PATTERN (insn);
6936 unsigned long distance = -1;
6938 if (INSN_ADDRESSES_SET_P ())
6940 unsigned long total;
6942 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6943 distance = (total + insn_current_reference_address (insn));
6944 if (distance < total)
6948 /* Determine if this is a local call. */
6949 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
6950 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
6952 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
6954 call_decl = SYMBOL_REF_DECL (call_dest);
6955 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
6957 /* pc-relative branch. */
6958 if (!TARGET_LONG_CALLS
6959 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
6960 || distance < 240000))
6963 /* 64-bit plabel sequence. */
6964 else if (TARGET_64BIT && !local_call)
6965 length += sibcall ? 28 : 24;
6967 /* non-pic long absolute branch sequence. */
6968 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
6971 /* long pc-relative branch sequence. */
6972 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6973 || (TARGET_64BIT && !TARGET_GAS)
6974 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
6978 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
6982 /* 32-bit plabel sequence. */
6988 length += length_fp_args (insn);
6998 if (!TARGET_NO_SPACE_REGS)
7006 /* INSN is a function call. It may have an unconditional jump
7009 CALL_DEST is the routine we are calling. */
7012 output_call (rtx insn, rtx call_dest, int sibcall)
7014 int delay_insn_deleted = 0;
7015 int delay_slot_filled = 0;
7016 int seq_length = dbr_sequence_length ();
7017 tree call_decl = SYMBOL_REF_DECL (call_dest);
7018 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7021 xoperands[0] = call_dest;
7023 /* Handle the common case where we're sure that the branch will reach
7024 the beginning of the "$CODE$" subspace. This is the beginning of
7025 the current function if we are in a named section. */
7026 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7028 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7029 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7033 if (TARGET_64BIT && !local_call)
7035 /* ??? As far as I can tell, the HP linker doesn't support the
7036 long pc-relative sequence described in the 64-bit runtime
7037 architecture. So, we use a slightly longer indirect call. */
7038 struct deferred_plabel *p = get_plabel (call_dest);
7040 xoperands[0] = p->internal_label;
7041 xoperands[1] = gen_label_rtx ();
7043 /* If this isn't a sibcall, we put the load of %r27 into the
7044 delay slot. We can't do this in a sibcall as we don't
7045 have a second call-clobbered scratch register available. */
7047 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7050 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7053 /* Now delete the delay insn. */
7054 PUT_CODE (NEXT_INSN (insn), NOTE);
7055 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7056 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7057 delay_insn_deleted = 1;
7060 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7061 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7062 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7066 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7067 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7068 output_asm_insn ("bve (%%r1)", xoperands);
7072 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7073 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7074 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7075 delay_slot_filled = 1;
7080 int indirect_call = 0;
7082 /* Emit a long call. There are several different sequences
7083 of increasing length and complexity. In most cases,
7084 they don't allow an instruction in the delay slot. */
7085 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7086 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7087 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7092 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7094 && (!TARGET_PA_20 || indirect_call))
7096 /* A non-jump insn in the delay slot. By definition we can
7097 emit this insn before the call (and in fact before argument
7099 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7102 /* Now delete the delay insn. */
7103 PUT_CODE (NEXT_INSN (insn), NOTE);
7104 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7105 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7106 delay_insn_deleted = 1;
7109 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7111 /* This is the best sequence for making long calls in
7112 non-pic code. Unfortunately, GNU ld doesn't provide
7113 the stub needed for external calls, and GAS's support
7114 for this with the SOM linker is buggy. It is safe
7115 to use this for local calls. */
7116 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7118 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7122 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7125 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7127 output_asm_insn ("copy %%r31,%%r2", xoperands);
7128 delay_slot_filled = 1;
7133 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7134 || (TARGET_64BIT && !TARGET_GAS))
7136 /* The HP assembler and linker can handle relocations
7137 for the difference of two symbols. GAS and the HP
7138 linker can't do this when one of the symbols is
7140 xoperands[1] = gen_label_rtx ();
7141 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7142 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7143 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7144 CODE_LABEL_NUMBER (xoperands[1]));
7145 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7147 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7149 /* GAS currently can't generate the relocations that
7150 are needed for the SOM linker under HP-UX using this
7151 sequence. The GNU linker doesn't generate the stubs
7152 that are needed for external calls on TARGET_ELF32
7153 with this sequence. For now, we have to use a
7154 longer plabel sequence when using GAS. */
7155 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7156 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7158 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7163 /* Emit a long plabel-based call sequence. This is
7164 essentially an inline implementation of $$dyncall.
7165 We don't actually try to call $$dyncall as this is
7166 as difficult as calling the function itself. */
7167 struct deferred_plabel *p = get_plabel (call_dest);
7169 xoperands[0] = p->internal_label;
7170 xoperands[1] = gen_label_rtx ();
7172 /* Since the call is indirect, FP arguments in registers
7173 need to be copied to the general registers. Then, the
7174 argument relocation stub will copy them back. */
7176 copy_fp_args (insn);
7180 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7181 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7182 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7186 output_asm_insn ("addil LR'%0-$global$,%%r27",
7188 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7192 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7193 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7194 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7195 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7197 if (!sibcall && !TARGET_PA_20)
7199 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7200 if (TARGET_NO_SPACE_REGS)
7201 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7203 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7210 output_asm_insn ("bve (%%r1)", xoperands);
7215 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7216 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7217 delay_slot_filled = 1;
7220 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7225 if (!TARGET_NO_SPACE_REGS)
7226 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7231 if (TARGET_NO_SPACE_REGS)
7232 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7234 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7238 if (TARGET_NO_SPACE_REGS)
7239 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7241 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7244 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7246 output_asm_insn ("copy %%r31,%%r2", xoperands);
7247 delay_slot_filled = 1;
7254 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7255 output_asm_insn ("nop", xoperands);
7257 /* We are done if there isn't a jump in the delay slot. */
7259 || delay_insn_deleted
7260 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7263 /* A sibcall should never have a branch in the delay slot. */
7267 /* This call has an unconditional jump in its delay slot. */
7268 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7270 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7272 /* See if the return address can be adjusted. Use the containing
7273 sequence insn's address. */
7274 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7275 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7276 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7278 if (VAL_14_BITS_P (distance))
7280 xoperands[1] = gen_label_rtx ();
7281 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7282 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7283 CODE_LABEL_NUMBER (xoperands[1]));
7286 output_asm_insn ("nop\n\tb,n %0", xoperands);
7289 output_asm_insn ("b,n %0", xoperands);
7291 /* Delete the jump. */
7292 PUT_CODE (NEXT_INSN (insn), NOTE);
7293 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7294 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7299 /* Return the attribute length of the indirect call instruction INSN.
7300 The length must match the code generated by output_indirect call.
7301 The returned length includes the delay slot. Currently, the delay
7302 slot of an indirect call sequence is not exposed and it is used by
7303 the sequence itself. */
7306 attr_length_indirect_call (rtx insn)
7308 unsigned long distance = -1;
7309 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7311 if (INSN_ADDRESSES_SET_P ())
7313 distance = (total + insn_current_reference_address (insn));
7314 if (distance < total)
7321 if (TARGET_FAST_INDIRECT_CALLS
7322 || (!TARGET_PORTABLE_RUNTIME
7323 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7329 if (TARGET_PORTABLE_RUNTIME)
7332 /* Out of reach, can use ble. */
7337 output_indirect_call (rtx insn, rtx call_dest)
7343 xoperands[0] = call_dest;
7344 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7345 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7349 /* First the special case for kernels, level 0 systems, etc. */
7350 if (TARGET_FAST_INDIRECT_CALLS)
7351 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7353 /* Now the normal case -- we can reach $$dyncall directly or
7354 we're sure that we can get there via a long-branch stub.
7356 No need to check target flags as the length uniquely identifies
7357 the remaining cases. */
7358 if (attr_length_indirect_call (insn) == 8)
7360 /* The HP linker substitutes a BLE for millicode calls using
7361 the short PIC PCREL form. Thus, we must use %r31 as the
7362 link register when generating PA 1.x code. */
7364 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7366 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7369 /* Long millicode call, but we are not generating PIC or portable runtime
7371 if (attr_length_indirect_call (insn) == 12)
7372 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7374 /* Long millicode call for portable runtime. */
7375 if (attr_length_indirect_call (insn) == 20)
7376 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7378 /* We need a long PIC call to $$dyncall. */
7379 xoperands[0] = NULL_RTX;
7380 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7381 if (TARGET_SOM || !TARGET_GAS)
7383 xoperands[0] = gen_label_rtx ();
7384 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7385 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7386 CODE_LABEL_NUMBER (xoperands[0]));
7387 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7391 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7392 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7395 output_asm_insn ("blr %%r0,%%r2", xoperands);
7396 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7400 /* Return the total length of the save and restore instructions needed for
7401 the data linkage table pointer (i.e., the PIC register) across the call
7402 instruction INSN. No-return calls do not require a save and restore.
7403 In addition, we may be able to avoid the save and restore for calls
7404 within the same translation unit. */
7407 attr_length_save_restore_dltp (rtx insn)
7409 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7415 /* In HPUX 8.0's shared library scheme, special relocations are needed
7416 for function labels if they might be passed to a function
7417 in a shared library (because shared libraries don't live in code
7418 space), and special magic is needed to construct their address. */
7421 hppa_encode_label (rtx sym)
7423 const char *str = XSTR (sym, 0);
7424 int len = strlen (str) + 1;
7427 p = newstr = alloca (len + 1);
7431 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7435 pa_encode_section_info (tree decl, rtx rtl, int first)
7437 if (first && TEXT_SPACE_P (decl))
7439 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7440 if (TREE_CODE (decl) == FUNCTION_DECL)
7441 hppa_encode_label (XEXP (rtl, 0));
7445 /* This is sort of inverse to pa_encode_section_info. */
7448 pa_strip_name_encoding (const char *str)
7450 str += (*str == '@');
7451 str += (*str == '*');
7456 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7458 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7461 /* Returns 1 if OP is a function label involved in a simple addition
7462 with a constant. Used to keep certain patterns from matching
7463 during instruction combination. */
7465 is_function_label_plus_const (rtx op)
7467 /* Strip off any CONST. */
7468 if (GET_CODE (op) == CONST)
7471 return (GET_CODE (op) == PLUS
7472 && function_label_operand (XEXP (op, 0), Pmode)
7473 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7476 /* Output assembly code for a thunk to FUNCTION. */
7479 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7480 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7483 static unsigned int current_thunk_number;
7484 int val_14 = VAL_14_BITS_P (delta);
7489 xoperands[0] = XEXP (DECL_RTL (function), 0);
7490 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7491 xoperands[2] = GEN_INT (delta);
7493 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7494 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7496 /* Output the thunk. We know that the function is in the same
7497 translation unit (i.e., the same space) as the thunk, and that
7498 thunks are output after their method. Thus, we don't need an
7499 external branch to reach the function. With SOM and GAS,
7500 functions and thunks are effectively in different sections.
7501 Thus, we can always use a IA-relative branch and the linker
7502 will add a long branch stub if necessary.
7504 However, we have to be careful when generating PIC code on the
7505 SOM port to ensure that the sequence does not transfer to an
7506 import stub for the target function as this could clobber the
7507 return value saved at SP-24. This would also apply to the
7508 32-bit linux port if the multi-space model is implemented. */
7509 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7510 && !(flag_pic && TREE_PUBLIC (function))
7511 && (TARGET_GAS || last_address < 262132))
7512 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7513 && ((targetm.have_named_sections
7514 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7515 /* The GNU 64-bit linker has rather poor stub management.
7516 So, we use a long branch from thunks that aren't in
7517 the same section as the target function. */
7519 && (DECL_SECTION_NAME (thunk_fndecl)
7520 != DECL_SECTION_NAME (function)))
7521 || ((DECL_SECTION_NAME (thunk_fndecl)
7522 == DECL_SECTION_NAME (function))
7523 && last_address < 262132)))
7524 || (!targetm.have_named_sections && last_address < 262132))))
7527 output_asm_insn ("addil L'%2,%%r26", xoperands);
7529 output_asm_insn ("b %0", xoperands);
7533 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7538 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7542 else if (TARGET_64BIT)
7544 /* We only have one call-clobbered scratch register, so we can't
7545 make use of the delay slot if delta doesn't fit in 14 bits. */
7548 output_asm_insn ("addil L'%2,%%r26", xoperands);
7549 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7552 output_asm_insn ("b,l .+8,%%r1", xoperands);
7556 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7557 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7561 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7562 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7567 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7568 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7573 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7577 else if (TARGET_PORTABLE_RUNTIME)
7579 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7580 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7583 output_asm_insn ("addil L'%2,%%r26", xoperands);
7585 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7589 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7594 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7598 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7600 /* The function is accessible from outside this module. The only
7601 way to avoid an import stub between the thunk and function is to
7602 call the function directly with an indirect sequence similar to
7603 that used by $$dyncall. This is possible because $$dyncall acts
7604 as the import stub in an indirect call. */
7605 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7606 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7607 output_asm_insn ("addil LT'%3,%%r19", xoperands);
7608 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
7609 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7610 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
7611 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
7612 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
7613 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7617 output_asm_insn ("addil L'%2,%%r26", xoperands);
7623 output_asm_insn ("bve (%%r22)", xoperands);
7626 else if (TARGET_NO_SPACE_REGS)
7628 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
7633 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
7634 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
7635 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
7640 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7642 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7646 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7648 if (TARGET_SOM || !TARGET_GAS)
7650 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
7651 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
7655 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7656 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
7660 output_asm_insn ("addil L'%2,%%r26", xoperands);
7662 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7666 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7671 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7678 output_asm_insn ("addil L'%2,%%r26", xoperands);
7680 output_asm_insn ("ldil L'%0,%%r22", xoperands);
7681 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
7685 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7690 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7695 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7697 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7700 output_asm_insn (".align 4", xoperands);
7701 ASM_OUTPUT_LABEL (file, label);
7702 output_asm_insn (".word P'%0", xoperands);
7704 else if (TARGET_SOM && TARGET_GAS)
7707 current_thunk_number++;
7708 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7709 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7710 last_address += nbytes;
7711 update_total_code_bytes (nbytes);
7714 /* Only direct calls to static functions are allowed to be sibling (tail)
7717 This restriction is necessary because some linker generated stubs will
7718 store return pointers into rp' in some cases which might clobber a
7719 live value already in rp'.
7721 In a sibcall the current function and the target function share stack
7722 space. Thus if the path to the current function and the path to the
7723 target function save a value in rp', they save the value into the
7724 same stack slot, which has undesirable consequences.
7726 Because of the deferred binding nature of shared libraries any function
7727 with external scope could be in a different load module and thus require
7728 rp' to be saved when calling that function. So sibcall optimizations
7729 can only be safe for static function.
7731 Note that GCC never needs return value relocations, so we don't have to
7732 worry about static calls with return value relocations (which require
7735 It is safe to perform a sibcall optimization when the target function
7736 will never return. */
7738 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7740 if (TARGET_PORTABLE_RUNTIME)
7743 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7744 single subspace mode and the call is not indirect. As far as I know,
7745 there is no operating system support for the multiple subspace mode.
7746 It might be possible to support indirect calls if we didn't use
7747 $$dyncall (see the indirect sequence generated in output_call). */
7749 return (decl != NULL_TREE);
7751 /* Sibcalls are not ok because the arg pointer register is not a fixed
7752 register. This prevents the sibcall optimization from occurring. In
7753 addition, there are problems with stub placement using GNU ld. This
7754 is because a normal sibcall branch uses a 17-bit relocation while
7755 a regular call branch uses a 22-bit relocation. As a result, more
7756 care needs to be taken in the placement of long-branch stubs. */
7760 /* Sibcalls are only ok within a translation unit. */
7761 return (decl && !TREE_PUBLIC (decl));
7764 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7765 use in fmpyadd instructions. */
7767 fmpyaddoperands (rtx *operands)
7769 enum machine_mode mode = GET_MODE (operands[0]);
7771 /* Must be a floating point mode. */
7772 if (mode != SFmode && mode != DFmode)
7775 /* All modes must be the same. */
7776 if (! (mode == GET_MODE (operands[1])
7777 && mode == GET_MODE (operands[2])
7778 && mode == GET_MODE (operands[3])
7779 && mode == GET_MODE (operands[4])
7780 && mode == GET_MODE (operands[5])))
7783 /* All operands must be registers. */
7784 if (! (GET_CODE (operands[1]) == REG
7785 && GET_CODE (operands[2]) == REG
7786 && GET_CODE (operands[3]) == REG
7787 && GET_CODE (operands[4]) == REG
7788 && GET_CODE (operands[5]) == REG))
7791 /* Only 2 real operands to the addition. One of the input operands must
7792 be the same as the output operand. */
7793 if (! rtx_equal_p (operands[3], operands[4])
7794 && ! rtx_equal_p (operands[3], operands[5]))
7797 /* Inout operand of add cannot conflict with any operands from multiply. */
7798 if (rtx_equal_p (operands[3], operands[0])
7799 || rtx_equal_p (operands[3], operands[1])
7800 || rtx_equal_p (operands[3], operands[2]))
7803 /* multiply cannot feed into addition operands. */
7804 if (rtx_equal_p (operands[4], operands[0])
7805 || rtx_equal_p (operands[5], operands[0]))
7808 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7810 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7811 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7812 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7813 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7814 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7815 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7818 /* Passed. Operands are suitable for fmpyadd. */
7822 #if !defined(USE_COLLECT2)
7824 pa_asm_out_constructor (rtx symbol, int priority)
7826 if (!function_label_operand (symbol, VOIDmode))
7827 hppa_encode_label (symbol);
7829 #ifdef CTORS_SECTION_ASM_OP
7830 default_ctor_section_asm_out_constructor (symbol, priority);
7832 # ifdef TARGET_ASM_NAMED_SECTION
7833 default_named_section_asm_out_constructor (symbol, priority);
7835 default_stabs_asm_out_constructor (symbol, priority);
7841 pa_asm_out_destructor (rtx symbol, int priority)
7843 if (!function_label_operand (symbol, VOIDmode))
7844 hppa_encode_label (symbol);
7846 #ifdef DTORS_SECTION_ASM_OP
7847 default_dtor_section_asm_out_destructor (symbol, priority);
7849 # ifdef TARGET_ASM_NAMED_SECTION
7850 default_named_section_asm_out_destructor (symbol, priority);
7852 default_stabs_asm_out_destructor (symbol, priority);
7858 /* This function places uninitialized global data in the bss section.
7859 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
7860 function on the SOM port to prevent uninitialized global data from
7861 being placed in the data section. */
7864 pa_asm_output_aligned_bss (FILE *stream,
7866 unsigned HOST_WIDE_INT size,
7870 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7872 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7873 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7876 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7877 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7880 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7881 ASM_OUTPUT_LABEL (stream, name);
7882 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
7885 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
7886 that doesn't allow the alignment of global common storage to be directly
7887 specified. The SOM linker aligns common storage based on the rounded
7888 value of the NUM_BYTES parameter in the .comm directive. It's not
7889 possible to use the .align directive as it doesn't affect the alignment
7890 of the label associated with a .comm directive. */
7893 pa_asm_output_aligned_common (FILE *stream,
7895 unsigned HOST_WIDE_INT size,
7898 unsigned int max_common_align;
7900 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
7901 if (align > max_common_align)
7903 warning ("alignment (%u) for %s exceeds maximum alignment "
7904 "for global common data. Using %u",
7905 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
7906 align = max_common_align;
7911 assemble_name (stream, name);
7912 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
7913 MAX (size, align / BITS_PER_UNIT));
7916 /* We can't use .comm for local common storage as the SOM linker effectively
7917 treats the symbol as universal and uses the same storage for local symbols
7918 with the same name in different object files. The .block directive
7919 reserves an uninitialized block of storage. However, it's not common
7920 storage. Fortunately, GCC never requests common storage with the same
7921 name in any given translation unit. */
7924 pa_asm_output_aligned_local (FILE *stream,
7926 unsigned HOST_WIDE_INT size,
7930 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7933 fprintf (stream, "%s", LOCAL_ASM_OP);
7934 assemble_name (stream, name);
7935 fprintf (stream, "\n");
7938 ASM_OUTPUT_LABEL (stream, name);
7939 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
7942 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7943 use in fmpysub instructions. */
7945 fmpysuboperands (rtx *operands)
7947 enum machine_mode mode = GET_MODE (operands[0]);
7949 /* Must be a floating point mode. */
7950 if (mode != SFmode && mode != DFmode)
7953 /* All modes must be the same. */
7954 if (! (mode == GET_MODE (operands[1])
7955 && mode == GET_MODE (operands[2])
7956 && mode == GET_MODE (operands[3])
7957 && mode == GET_MODE (operands[4])
7958 && mode == GET_MODE (operands[5])))
7961 /* All operands must be registers. */
7962 if (! (GET_CODE (operands[1]) == REG
7963 && GET_CODE (operands[2]) == REG
7964 && GET_CODE (operands[3]) == REG
7965 && GET_CODE (operands[4]) == REG
7966 && GET_CODE (operands[5]) == REG))
7969 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
7970 operation, so operands[4] must be the same as operand[3]. */
7971 if (! rtx_equal_p (operands[3], operands[4]))
7974 /* multiply cannot feed into subtraction. */
7975 if (rtx_equal_p (operands[5], operands[0]))
7978 /* Inout operand of sub cannot conflict with any operands from multiply. */
7979 if (rtx_equal_p (operands[3], operands[0])
7980 || rtx_equal_p (operands[3], operands[1])
7981 || rtx_equal_p (operands[3], operands[2]))
7984 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7986 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7987 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7988 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7989 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7990 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7991 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7994 /* Passed. Operands are suitable for fmpysub. */
7998 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
7999 constants for shadd instructions. */
8001 shadd_constant_p (int val)
8003 if (val == 2 || val == 4 || val == 8)
8009 /* Return 1 if OP is valid as a base or index register in a
8013 borx_reg_operand (rtx op, enum machine_mode mode)
8015 if (GET_CODE (op) != REG)
8018 /* We must reject virtual registers as the only expressions that
8019 can be instantiated are REG and REG+CONST. */
8020 if (op == virtual_incoming_args_rtx
8021 || op == virtual_stack_vars_rtx
8022 || op == virtual_stack_dynamic_rtx
8023 || op == virtual_outgoing_args_rtx
8024 || op == virtual_cfa_rtx)
8027 /* While it's always safe to index off the frame pointer, it's not
8028 profitable to do so when the frame pointer is being eliminated. */
8029 if (!reload_completed
8030 && flag_omit_frame_pointer
8031 && !current_function_calls_alloca
8032 && op == frame_pointer_rtx)
8035 return register_operand (op, mode);
8038 /* Return 1 if this operand is anything other than a hard register. */
8041 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8043 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8046 /* Return 1 if INSN branches forward. Should be using insn_addresses
8047 to avoid walking through all the insns... */
8049 forward_branch_p (rtx insn)
8051 rtx label = JUMP_LABEL (insn);
8058 insn = NEXT_INSN (insn);
8061 return (insn == label);
8064 /* Return 1 if OP is an equality comparison, else return 0. */
8066 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8068 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8071 /* Return 1 if INSN is in the delay slot of a call instruction. */
8073 jump_in_call_delay (rtx insn)
8076 if (GET_CODE (insn) != JUMP_INSN)
8079 if (PREV_INSN (insn)
8080 && PREV_INSN (PREV_INSN (insn))
8081 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8083 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8085 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8086 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8093 /* Output an unconditional move and branch insn. */
8096 output_parallel_movb (rtx *operands, int length)
8098 /* These are the cases in which we win. */
8100 return "mov%I1b,tr %1,%0,%2";
8102 /* None of these cases wins, but they don't lose either. */
8103 if (dbr_sequence_length () == 0)
8105 /* Nothing in the delay slot, fake it by putting the combined
8106 insn (the copy or add) in the delay slot of a bl. */
8107 if (GET_CODE (operands[1]) == CONST_INT)
8108 return "b %2\n\tldi %1,%0";
8110 return "b %2\n\tcopy %1,%0";
8114 /* Something in the delay slot, but we've got a long branch. */
8115 if (GET_CODE (operands[1]) == CONST_INT)
8116 return "ldi %1,%0\n\tb %2";
8118 return "copy %1,%0\n\tb %2";
8122 /* Output an unconditional add and branch insn. */
8125 output_parallel_addb (rtx *operands, int length)
8127 /* To make life easy we want operand0 to be the shared input/output
8128 operand and operand1 to be the readonly operand. */
8129 if (operands[0] == operands[1])
8130 operands[1] = operands[2];
8132 /* These are the cases in which we win. */
8134 return "add%I1b,tr %1,%0,%3";
8136 /* None of these cases win, but they don't lose either. */
8137 if (dbr_sequence_length () == 0)
8139 /* Nothing in the delay slot, fake it by putting the combined
8140 insn (the copy or add) in the delay slot of a bl. */
8141 return "b %3\n\tadd%I1 %1,%0,%0";
8145 /* Something in the delay slot, but we've got a long branch. */
8146 return "add%I1 %1,%0,%0\n\tb %3";
8150 /* Return nonzero if INSN (a jump insn) immediately follows a call
8151 to a named function. This is used to avoid filling the delay slot
8152 of the jump since it can usually be eliminated by modifying RP in
8153 the delay slot of the call. */
8156 following_call (rtx insn)
8158 if (! TARGET_JUMP_IN_DELAY)
8161 /* Find the previous real insn, skipping NOTEs. */
8162 insn = PREV_INSN (insn);
8163 while (insn && GET_CODE (insn) == NOTE)
8164 insn = PREV_INSN (insn);
8166 /* Check for CALL_INSNs and millicode calls. */
8168 && ((GET_CODE (insn) == CALL_INSN
8169 && get_attr_type (insn) != TYPE_DYNCALL)
8170 || (GET_CODE (insn) == INSN
8171 && GET_CODE (PATTERN (insn)) != SEQUENCE
8172 && GET_CODE (PATTERN (insn)) != USE
8173 && GET_CODE (PATTERN (insn)) != CLOBBER
8174 && get_attr_type (insn) == TYPE_MILLI)))
8180 /* We use this hook to perform a PA specific optimization which is difficult
8181 to do in earlier passes.
8183 We want the delay slots of branches within jump tables to be filled.
8184 None of the compiler passes at the moment even has the notion that a
8185 PA jump table doesn't contain addresses, but instead contains actual
8188 Because we actually jump into the table, the addresses of each entry
8189 must stay constant in relation to the beginning of the table (which
8190 itself must stay constant relative to the instruction to jump into
8191 it). I don't believe we can guarantee earlier passes of the compiler
8192 will adhere to those rules.
8194 So, late in the compilation process we find all the jump tables, and
8195 expand them into real code -- e.g. each entry in the jump table vector
8196 will get an appropriate label followed by a jump to the final target.
8198 Reorg and the final jump pass can then optimize these branches and
8199 fill their delay slots. We end up with smaller, more efficient code.
8201 The jump instructions within the table are special; we must be able
8202 to identify them during assembly output (if the jumps don't get filled
8203 we need to emit a nop rather than nullifying the delay slot)). We
8204 identify jumps in switch tables by using insns with the attribute
8205 type TYPE_BTABLE_BRANCH.
8207 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8208 insns. This serves two purposes, first it prevents jump.c from
8209 noticing that the last N entries in the table jump to the instruction
8210 immediately after the table and deleting the jumps. Second, those
8211 insns mark where we should emit .begin_brtab and .end_brtab directives
8212 when using GAS (allows for better link time optimizations). */
8219 remove_useless_addtr_insns (1);
8221 if (pa_cpu < PROCESSOR_8000)
8222 pa_combine_instructions ();
8225 /* This is fairly cheap, so always run it if optimizing. */
8226 if (optimize > 0 && !TARGET_BIG_SWITCH)
8228 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8229 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8231 rtx pattern, tmp, location, label;
8232 unsigned int length, i;
8234 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8235 if (GET_CODE (insn) != JUMP_INSN
8236 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8237 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8240 /* Emit marker for the beginning of the branch table. */
8241 emit_insn_before (gen_begin_brtab (), insn);
8243 pattern = PATTERN (insn);
8244 location = PREV_INSN (insn);
8245 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8247 for (i = 0; i < length; i++)
8249 /* Emit a label before each jump to keep jump.c from
8250 removing this code. */
8251 tmp = gen_label_rtx ();
8252 LABEL_NUSES (tmp) = 1;
8253 emit_label_after (tmp, location);
8254 location = NEXT_INSN (location);
8256 if (GET_CODE (pattern) == ADDR_VEC)
8257 label = XEXP (XVECEXP (pattern, 0, i), 0);
8259 label = XEXP (XVECEXP (pattern, 1, i), 0);
8261 tmp = gen_short_jump (label);
8263 /* Emit the jump itself. */
8264 tmp = emit_jump_insn_after (tmp, location);
8265 JUMP_LABEL (tmp) = label;
8266 LABEL_NUSES (label)++;
8267 location = NEXT_INSN (location);
8269 /* Emit a BARRIER after the jump. */
8270 emit_barrier_after (location);
8271 location = NEXT_INSN (location);
8274 /* Emit marker for the end of the branch table. */
8275 emit_insn_before (gen_end_brtab (), location);
8276 location = NEXT_INSN (location);
8277 emit_barrier_after (location);
8279 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8285 /* Still need brtab marker insns. FIXME: the presence of these
8286 markers disables output of the branch table to readonly memory,
8287 and any alignment directives that might be needed. Possibly,
8288 the begin_brtab insn should be output before the label for the
8289 table. This doesn't matter at the moment since the tables are
8290 always output in the text section. */
8291 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8293 /* Find an ADDR_VEC insn. */
8294 if (GET_CODE (insn) != JUMP_INSN
8295 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8296 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8299 /* Now generate markers for the beginning and end of the
8301 emit_insn_before (gen_begin_brtab (), insn);
8302 emit_insn_after (gen_end_brtab (), insn);
8307 /* The PA has a number of odd instructions which can perform multiple
8308 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8309 it may be profitable to combine two instructions into one instruction
8310 with two outputs. It's not profitable PA2.0 machines because the
8311 two outputs would take two slots in the reorder buffers.
8313 This routine finds instructions which can be combined and combines
8314 them. We only support some of the potential combinations, and we
8315 only try common ways to find suitable instructions.
8317 * addb can add two registers or a register and a small integer
8318 and jump to a nearby (+-8k) location. Normally the jump to the
8319 nearby location is conditional on the result of the add, but by
8320 using the "true" condition we can make the jump unconditional.
8321 Thus addb can perform two independent operations in one insn.
8323 * movb is similar to addb in that it can perform a reg->reg
8324 or small immediate->reg copy and jump to a nearby (+-8k location).
8326 * fmpyadd and fmpysub can perform a FP multiply and either an
8327 FP add or FP sub if the operands of the multiply and add/sub are
8328 independent (there are other minor restrictions). Note both
8329 the fmpy and fadd/fsub can in theory move to better spots according
8330 to data dependencies, but for now we require the fmpy stay at a
8333 * Many of the memory operations can perform pre & post updates
8334 of index registers. GCC's pre/post increment/decrement addressing
8335 is far too simple to take advantage of all the possibilities. This
8336 pass may not be suitable since those insns may not be independent.
8338 * comclr can compare two ints or an int and a register, nullify
8339 the following instruction and zero some other register. This
8340 is more difficult to use as it's harder to find an insn which
8341 will generate a comclr than finding something like an unconditional
8342 branch. (conditional moves & long branches create comclr insns).
8344 * Most arithmetic operations can conditionally skip the next
8345 instruction. They can be viewed as "perform this operation
8346 and conditionally jump to this nearby location" (where nearby
8347 is an insns away). These are difficult to use due to the
8348 branch length restrictions. */
8351 pa_combine_instructions (void)
8355 /* This can get expensive since the basic algorithm is on the
8356 order of O(n^2) (or worse). Only do it for -O2 or higher
8357 levels of optimization. */
8361 /* Walk down the list of insns looking for "anchor" insns which
8362 may be combined with "floating" insns. As the name implies,
8363 "anchor" instructions don't move, while "floating" insns may
8365 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8366 new = make_insn_raw (new);
8368 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8370 enum attr_pa_combine_type anchor_attr;
8371 enum attr_pa_combine_type floater_attr;
8373 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8374 Also ignore any special USE insns. */
8375 if ((GET_CODE (anchor) != INSN
8376 && GET_CODE (anchor) != JUMP_INSN
8377 && GET_CODE (anchor) != CALL_INSN)
8378 || GET_CODE (PATTERN (anchor)) == USE
8379 || GET_CODE (PATTERN (anchor)) == CLOBBER
8380 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8381 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8384 anchor_attr = get_attr_pa_combine_type (anchor);
8385 /* See if anchor is an insn suitable for combination. */
8386 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8387 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8388 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8389 && ! forward_branch_p (anchor)))
8393 for (floater = PREV_INSN (anchor);
8395 floater = PREV_INSN (floater))
8397 if (GET_CODE (floater) == NOTE
8398 || (GET_CODE (floater) == INSN
8399 && (GET_CODE (PATTERN (floater)) == USE
8400 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8403 /* Anything except a regular INSN will stop our search. */
8404 if (GET_CODE (floater) != INSN
8405 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8406 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8412 /* See if FLOATER is suitable for combination with the
8414 floater_attr = get_attr_pa_combine_type (floater);
8415 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8416 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8417 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8418 && floater_attr == PA_COMBINE_TYPE_FMPY))
8420 /* If ANCHOR and FLOATER can be combined, then we're
8421 done with this pass. */
8422 if (pa_can_combine_p (new, anchor, floater, 0,
8423 SET_DEST (PATTERN (floater)),
8424 XEXP (SET_SRC (PATTERN (floater)), 0),
8425 XEXP (SET_SRC (PATTERN (floater)), 1)))
8429 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8430 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8432 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8434 if (pa_can_combine_p (new, anchor, floater, 0,
8435 SET_DEST (PATTERN (floater)),
8436 XEXP (SET_SRC (PATTERN (floater)), 0),
8437 XEXP (SET_SRC (PATTERN (floater)), 1)))
8442 if (pa_can_combine_p (new, anchor, floater, 0,
8443 SET_DEST (PATTERN (floater)),
8444 SET_SRC (PATTERN (floater)),
8445 SET_SRC (PATTERN (floater))))
8451 /* If we didn't find anything on the backwards scan try forwards. */
8453 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8454 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8456 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8458 if (GET_CODE (floater) == NOTE
8459 || (GET_CODE (floater) == INSN
8460 && (GET_CODE (PATTERN (floater)) == USE
8461 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8465 /* Anything except a regular INSN will stop our search. */
8466 if (GET_CODE (floater) != INSN
8467 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8468 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8474 /* See if FLOATER is suitable for combination with the
8476 floater_attr = get_attr_pa_combine_type (floater);
8477 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8478 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8479 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8480 && floater_attr == PA_COMBINE_TYPE_FMPY))
8482 /* If ANCHOR and FLOATER can be combined, then we're
8483 done with this pass. */
8484 if (pa_can_combine_p (new, anchor, floater, 1,
8485 SET_DEST (PATTERN (floater)),
8486 XEXP (SET_SRC (PATTERN (floater)),
8488 XEXP (SET_SRC (PATTERN (floater)),
8495 /* FLOATER will be nonzero if we found a suitable floating
8496 insn for combination with ANCHOR. */
8498 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8499 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8501 /* Emit the new instruction and delete the old anchor. */
8502 emit_insn_before (gen_rtx_PARALLEL
8504 gen_rtvec (2, PATTERN (anchor),
8505 PATTERN (floater))),
8508 PUT_CODE (anchor, NOTE);
8509 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8510 NOTE_SOURCE_FILE (anchor) = 0;
8512 /* Emit a special USE insn for FLOATER, then delete
8513 the floating insn. */
8514 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8515 delete_insn (floater);
8520 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8523 /* Emit the new_jump instruction and delete the old anchor. */
8525 = emit_jump_insn_before (gen_rtx_PARALLEL
8527 gen_rtvec (2, PATTERN (anchor),
8528 PATTERN (floater))),
8531 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8532 PUT_CODE (anchor, NOTE);
8533 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8534 NOTE_SOURCE_FILE (anchor) = 0;
8536 /* Emit a special USE insn for FLOATER, then delete
8537 the floating insn. */
8538 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8539 delete_insn (floater);
8547 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8550 int insn_code_number;
8553 /* Create a PARALLEL with the patterns of ANCHOR and
8554 FLOATER, try to recognize it, then test constraints
8555 for the resulting pattern.
8557 If the pattern doesn't match or the constraints
8558 aren't met keep searching for a suitable floater
8560 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8561 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8562 INSN_CODE (new) = -1;
8563 insn_code_number = recog_memoized (new);
8564 if (insn_code_number < 0
8565 || (extract_insn (new), ! constrain_operands (1)))
8579 /* There's up to three operands to consider. One
8580 output and two inputs.
8582 The output must not be used between FLOATER & ANCHOR
8583 exclusive. The inputs must not be set between
8584 FLOATER and ANCHOR exclusive. */
8586 if (reg_used_between_p (dest, start, end))
8589 if (reg_set_between_p (src1, start, end))
8592 if (reg_set_between_p (src2, start, end))
8595 /* If we get here, then everything is good. */
8599 /* Return nonzero if references for INSN are delayed.
8601 Millicode insns are actually function calls with some special
8602 constraints on arguments and register usage.
8604 Millicode calls always expect their arguments in the integer argument
8605 registers, and always return their result in %r29 (ret1). They
8606 are expected to clobber their arguments, %r1, %r29, and the return
8607 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8609 This function tells reorg that the references to arguments and
8610 millicode calls do not appear to happen until after the millicode call.
8611 This allows reorg to put insns which set the argument registers into the
8612 delay slot of the millicode call -- thus they act more like traditional
8615 Note we cannot consider side effects of the insn to be delayed because
8616 the branch and link insn will clobber the return pointer. If we happened
8617 to use the return pointer in the delay slot of the call, then we lose.
8619 get_attr_type will try to recognize the given insn, so make sure to
8620 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8623 insn_refs_are_delayed (rtx insn)
8625 return ((GET_CODE (insn) == INSN
8626 && GET_CODE (PATTERN (insn)) != SEQUENCE
8627 && GET_CODE (PATTERN (insn)) != USE
8628 && GET_CODE (PATTERN (insn)) != CLOBBER
8629 && get_attr_type (insn) == TYPE_MILLI));
8632 /* On the HP-PA the value is found in register(s) 28(-29), unless
8633 the mode is SF or DF. Then the value is returned in fr4 (32).
8635 This must perform the same promotions as PROMOTE_MODE, else
8636 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8638 Small structures must be returned in a PARALLEL on PA64 in order
8639 to match the HP Compiler ABI. */
8642 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8644 enum machine_mode valmode;
8646 /* Aggregates with a size less than or equal to 128 bits are returned
8647 in GR 28(-29). They are left justified. The pad bits are undefined.
8648 Larger aggregates are returned in memory. */
8649 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8653 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8655 for (i = 0; i < ub; i++)
8657 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8658 gen_rtx_REG (DImode, 28 + i),
8663 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8666 if ((INTEGRAL_TYPE_P (valtype)
8667 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8668 || POINTER_TYPE_P (valtype))
8669 valmode = word_mode;
8671 valmode = TYPE_MODE (valtype);
8673 if (TREE_CODE (valtype) == REAL_TYPE
8674 && TYPE_MODE (valtype) != TFmode
8675 && !TARGET_SOFT_FLOAT)
8676 return gen_rtx_REG (valmode, 32);
8678 return gen_rtx_REG (valmode, 28);
8681 /* Return the location of a parameter that is passed in a register or NULL
8682 if the parameter has any component that is passed in memory.
8684 This is new code and will be pushed to into the net sources after
8687 ??? We might want to restructure this so that it looks more like other
8690 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8691 int named ATTRIBUTE_UNUSED)
8693 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8700 if (mode == VOIDmode)
8703 arg_size = FUNCTION_ARG_SIZE (mode, type);
8705 /* If this arg would be passed partially or totally on the stack, then
8706 this routine should return zero. pa_arg_partial_bytes will
8707 handle arguments which are split between regs and stack slots if
8708 the ABI mandates split arguments. */
8711 /* The 32-bit ABI does not split arguments. */
8712 if (cum->words + arg_size > max_arg_words)
8718 alignment = cum->words & 1;
8719 if (cum->words + alignment >= max_arg_words)
8723 /* The 32bit ABIs and the 64bit ABIs are rather different,
8724 particularly in their handling of FP registers. We might
8725 be able to cleverly share code between them, but I'm not
8726 going to bother in the hope that splitting them up results
8727 in code that is more easily understood. */
8731 /* Advance the base registers to their current locations.
8733 Remember, gprs grow towards smaller register numbers while
8734 fprs grow to higher register numbers. Also remember that
8735 although FP regs are 32-bit addressable, we pretend that
8736 the registers are 64-bits wide. */
8737 gpr_reg_base = 26 - cum->words;
8738 fpr_reg_base = 32 + cum->words;
8740 /* Arguments wider than one word and small aggregates need special
8744 || (type && AGGREGATE_TYPE_P (type)))
8746 /* Double-extended precision (80-bit), quad-precision (128-bit)
8747 and aggregates including complex numbers are aligned on
8748 128-bit boundaries. The first eight 64-bit argument slots
8749 are associated one-to-one, with general registers r26
8750 through r19, and also with floating-point registers fr4
8751 through fr11. Arguments larger than one word are always
8752 passed in general registers.
8754 Using a PARALLEL with a word mode register results in left
8755 justified data on a big-endian target. */
8758 int i, offset = 0, ub = arg_size;
8760 /* Align the base register. */
8761 gpr_reg_base -= alignment;
8763 ub = MIN (ub, max_arg_words - cum->words - alignment);
8764 for (i = 0; i < ub; i++)
8766 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8767 gen_rtx_REG (DImode, gpr_reg_base),
8773 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8778 /* If the argument is larger than a word, then we know precisely
8779 which registers we must use. */
8793 /* Structures 5 to 8 bytes in size are passed in the general
8794 registers in the same manner as other non floating-point
8795 objects. The data is right-justified and zero-extended
8796 to 64 bits. This is opposite to the normal justification
8797 used on big endian targets and requires special treatment.
8798 We now define BLOCK_REG_PADDING to pad these objects. */
8799 if (mode == BLKmode)
8801 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8802 gen_rtx_REG (DImode, gpr_reg_base),
8804 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8809 /* We have a single word (32 bits). A simple computation
8810 will get us the register #s we need. */
8811 gpr_reg_base = 26 - cum->words;
8812 fpr_reg_base = 32 + 2 * cum->words;
8816 /* Determine if the argument needs to be passed in both general and
8817 floating point registers. */
8818 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8819 /* If we are doing soft-float with portable runtime, then there
8820 is no need to worry about FP regs. */
8821 && !TARGET_SOFT_FLOAT
8822 /* The parameter must be some kind of float, else we can just
8823 pass it in integer registers. */
8824 && FLOAT_MODE_P (mode)
8825 /* The target function must not have a prototype. */
8826 && cum->nargs_prototype <= 0
8827 /* libcalls do not need to pass items in both FP and general
8829 && type != NULL_TREE
8830 /* All this hair applies to "outgoing" args only. This includes
8831 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8833 /* Also pass outgoing floating arguments in both registers in indirect
8834 calls with the 32 bit ABI and the HP assembler since there is no
8835 way to the specify argument locations in static functions. */
8840 && FLOAT_MODE_P (mode)))
8846 gen_rtx_EXPR_LIST (VOIDmode,
8847 gen_rtx_REG (mode, fpr_reg_base),
8849 gen_rtx_EXPR_LIST (VOIDmode,
8850 gen_rtx_REG (mode, gpr_reg_base),
8855 /* See if we should pass this parameter in a general register. */
8856 if (TARGET_SOFT_FLOAT
8857 /* Indirect calls in the normal 32bit ABI require all arguments
8858 to be passed in general registers. */
8859 || (!TARGET_PORTABLE_RUNTIME
8863 /* If the parameter is not a floating point parameter, then
8864 it belongs in GPRs. */
8865 || !FLOAT_MODE_P (mode))
8866 retval = gen_rtx_REG (mode, gpr_reg_base);
8868 retval = gen_rtx_REG (mode, fpr_reg_base);
8874 /* If this arg would be passed totally in registers or totally on the stack,
8875 then this routine should return zero. */
8878 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8879 tree type, bool named ATTRIBUTE_UNUSED)
8881 unsigned int max_arg_words = 8;
8882 unsigned int offset = 0;
8887 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8890 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8891 /* Arg fits fully into registers. */
8893 else if (cum->words + offset >= max_arg_words)
8894 /* Arg fully on the stack. */
8898 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
8902 /* Return a string to output before text in the current function.
8904 This function is only used with SOM. Because we don't support
8905 named subspaces, we can only create a new subspace or switch back
8906 to the default text subspace. */
8908 som_text_section_asm_op (void)
8915 if (cfun && !cfun->machine->in_nsubspa)
8917 /* We only want to emit a .nsubspa directive once at the
8918 start of the function. */
8919 cfun->machine->in_nsubspa = 1;
8921 /* Create a new subspace for the text. This provides
8922 better stub placement and one-only functions. */
8924 && DECL_ONE_ONLY (cfun->decl)
8925 && !DECL_WEAK (cfun->decl))
8927 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
8929 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
8933 /* There isn't a current function or the body of the current
8934 function has been completed. So, we are changing to the
8935 text section to output debugging information. Do this in
8936 the default text section. We need to forget that we are
8937 in the text section so that the function text_section in
8938 varasm.c will call us the next time around. */
8943 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
8946 /* On hpux10, the linker will give an error if we have a reference
8947 in the read-only data section to a symbol defined in a shared
8948 library. Therefore, expressions that might require a reloc can
8949 not be placed in the read-only data section. */
8952 pa_select_section (tree exp, int reloc,
8953 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
8955 if (TREE_CODE (exp) == VAR_DECL
8956 && TREE_READONLY (exp)
8957 && !TREE_THIS_VOLATILE (exp)
8958 && DECL_INITIAL (exp)
8959 && (DECL_INITIAL (exp) == error_mark_node
8960 || TREE_CONSTANT (DECL_INITIAL (exp)))
8964 && DECL_ONE_ONLY (exp)
8965 && !DECL_WEAK (exp))
8966 som_one_only_readonly_data_section ();
8968 readonly_data_section ();
8970 else if (CONSTANT_CLASS_P (exp) && !reloc)
8971 readonly_data_section ();
8973 && TREE_CODE (exp) == VAR_DECL
8974 && DECL_ONE_ONLY (exp)
8975 && !DECL_WEAK (exp))
8976 som_one_only_data_section ();
8982 pa_globalize_label (FILE *stream, const char *name)
8984 /* We only handle DATA objects here, functions are globalized in
8985 ASM_DECLARE_FUNCTION_NAME. */
8986 if (! FUNCTION_NAME_P (name))
8988 fputs ("\t.EXPORT ", stream);
8989 assemble_name (stream, name);
8990 fputs (",DATA\n", stream);
8994 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
8997 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
8998 int incoming ATTRIBUTE_UNUSED)
9000 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9003 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9006 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9008 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9009 PA64 ABI says that objects larger than 128 bits are returned in memory.
9010 Note, int_size_in_bytes can return -1 if the size of the object is
9011 variable or larger than the maximum value that can be expressed as
9012 a HOST_WIDE_INT. It can also return zero for an empty type. The
9013 simplest way to handle variable and empty types is to pass them in
9014 memory. This avoids problems in defining the boundaries of argument
9015 slots, allocating registers, etc. */
9016 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9017 || int_size_in_bytes (type) <= 0);
9020 /* Structure to hold declaration and name of external symbols that are
9021 emitted by GCC. We generate a vector of these symbols and output them
9022 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9023 This avoids putting out names that are never really used. */
9025 typedef struct extern_symbol GTY(())
9031 /* Define gc'd vector type for extern_symbol. */
9032 DEF_VEC_O(extern_symbol);
9033 DEF_VEC_ALLOC_O(extern_symbol,gc);
9035 /* Vector of extern_symbol pointers. */
9036 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9038 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9039 /* Mark DECL (name NAME) as an external reference (assembler output
9040 file FILE). This saves the names to output at the end of the file
9041 if actually referenced. */
9044 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9046 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9048 gcc_assert (file == asm_out_file);
9053 /* Output text required at the end of an assembler file.
9054 This includes deferred plabels and .import directives for
9055 all external symbols that were actually referenced. */
9058 pa_hpux_file_end (void)
9063 output_deferred_plabels ();
9065 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9067 tree decl = p->decl;
9069 if (!TREE_ASM_WRITTEN (decl)
9070 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9071 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9074 VEC_free (extern_symbol, gc, extern_symbols);