1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static int hppa_address_cost (rtx);
88 static bool hppa_rtx_costs (rtx, int, int, int *);
89 static inline rtx force_mode (enum machine_mode, rtx);
90 static void pa_reorg (void);
91 static void pa_combine_instructions (void);
92 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
93 static int forward_branch_p (rtx);
94 static int shadd_constant_p (int);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static bool pa_scalar_mode_supported_p (enum machine_mode);
127 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
129 static struct deferred_plabel *get_plabel (rtx) ATTRIBUTE_UNUSED;
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 #ifdef ASM_OUTPUT_EXTERNAL_REAL
141 static void pa_hpux_file_end (void);
143 #ifdef HPUX_LONG_DOUBLE_LIBRARY
144 static void pa_hpux_init_libfuncs (void);
146 static rtx pa_struct_value_rtx (tree, int);
147 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
149 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
151 static struct machine_function * pa_init_machine_status (void);
154 /* Save the operands last given to a compare for use when we
155 generate a scc or bcc insn. */
156 rtx hppa_compare_op0, hppa_compare_op1;
157 enum cmp_type hppa_branch_type;
159 /* Which architecture we are generating code for. */
160 enum architecture_type pa_arch;
162 /* String to hold which architecture we are generating code for. */
163 const char *pa_arch_string;
165 /* String used with the -mfixed-range= option. */
166 const char *pa_fixed_range_string;
168 /* Which cpu we are scheduling for. */
169 enum processor_type pa_cpu;
171 /* String to hold which cpu we are scheduling for. */
172 const char *pa_cpu_string;
174 /* String used with the -munix= option. */
175 const char *pa_unix_string;
177 /* The UNIX standard to use for predefines and linking. */
180 /* Counts for the number of callee-saved general and floating point
181 registers which were saved by the current function's prologue. */
182 static int gr_saved, fr_saved;
184 static rtx find_addr_reg (rtx);
186 /* Keep track of the number of bytes we have output in the CODE subspace
187 during this compilation so we'll know when to emit inline long-calls. */
188 unsigned long total_code_bytes;
190 /* The last address of the previous function plus the number of bytes in
191 associated thunks that have been output. This is used to determine if
192 a thunk can use an IA-relative branch to reach its target function. */
193 static int last_address;
195 /* Variables to handle plabels that we discover are necessary at assembly
196 output time. They are output after the current function. */
197 struct deferred_plabel GTY(())
202 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
204 static size_t n_deferred_plabels = 0;
207 /* Initialize the GCC target structure. */
209 #undef TARGET_ASM_ALIGNED_HI_OP
210 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
211 #undef TARGET_ASM_ALIGNED_SI_OP
212 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
213 #undef TARGET_ASM_ALIGNED_DI_OP
214 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
215 #undef TARGET_ASM_UNALIGNED_HI_OP
216 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
217 #undef TARGET_ASM_UNALIGNED_SI_OP
218 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
219 #undef TARGET_ASM_UNALIGNED_DI_OP
220 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
221 #undef TARGET_ASM_INTEGER
222 #define TARGET_ASM_INTEGER pa_assemble_integer
224 #undef TARGET_ASM_FUNCTION_PROLOGUE
225 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
226 #undef TARGET_ASM_FUNCTION_EPILOGUE
227 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
229 #undef TARGET_SCHED_ADJUST_COST
230 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
231 #undef TARGET_SCHED_ADJUST_PRIORITY
232 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
233 #undef TARGET_SCHED_ISSUE_RATE
234 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
236 #undef TARGET_ENCODE_SECTION_INFO
237 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
238 #undef TARGET_STRIP_NAME_ENCODING
239 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
241 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
242 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
244 #undef TARGET_ASM_OUTPUT_MI_THUNK
245 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
246 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
247 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
249 #undef TARGET_ASM_FILE_END
250 #ifdef ASM_OUTPUT_EXTERNAL_REAL
251 #define TARGET_ASM_FILE_END pa_hpux_file_end
253 #define TARGET_ASM_FILE_END output_deferred_plabels
256 #if !defined(USE_COLLECT2)
257 #undef TARGET_ASM_CONSTRUCTOR
258 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
259 #undef TARGET_ASM_DESTRUCTOR
260 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
263 #undef TARGET_INIT_BUILTINS
264 #define TARGET_INIT_BUILTINS pa_init_builtins
266 #undef TARGET_RTX_COSTS
267 #define TARGET_RTX_COSTS hppa_rtx_costs
268 #undef TARGET_ADDRESS_COST
269 #define TARGET_ADDRESS_COST hppa_address_cost
271 #undef TARGET_MACHINE_DEPENDENT_REORG
272 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
274 #ifdef HPUX_LONG_DOUBLE_LIBRARY
275 #undef TARGET_INIT_LIBFUNCS
276 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
279 #undef TARGET_PROMOTE_FUNCTION_RETURN
280 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
281 #undef TARGET_PROMOTE_PROTOTYPES
282 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
284 #undef TARGET_STRUCT_VALUE_RTX
285 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
286 #undef TARGET_RETURN_IN_MEMORY
287 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
288 #undef TARGET_MUST_PASS_IN_STACK
289 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
290 #undef TARGET_PASS_BY_REFERENCE
291 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
292 #undef TARGET_CALLEE_COPIES
293 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
294 #undef TARGET_ARG_PARTIAL_BYTES
295 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
297 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
298 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
299 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
300 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
302 #undef TARGET_SCALAR_MODE_SUPPORTED_P
303 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
305 struct gcc_target targetm = TARGET_INITIALIZER;
307 /* Parse the -mfixed-range= option string. */
310 fix_range (const char *const_str)
313 char *str, *dash, *comma;
315 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
316 REG2 are either register names or register numbers. The effect
317 of this option is to mark the registers in the range from REG1 to
318 REG2 as ``fixed'' so they won't be used by the compiler. This is
319 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
321 i = strlen (const_str);
322 str = (char *) alloca (i + 1);
323 memcpy (str, const_str, i + 1);
327 dash = strchr (str, '-');
330 warning ("value of -mfixed-range must have form REG1-REG2");
335 comma = strchr (dash + 1, ',');
339 first = decode_reg_name (str);
342 warning ("unknown register name: %s", str);
346 last = decode_reg_name (dash + 1);
349 warning ("unknown register name: %s", dash + 1);
357 warning ("%s-%s is an empty range", str, dash + 1);
361 for (i = first; i <= last; ++i)
362 fixed_regs[i] = call_used_regs[i] = 1;
371 /* Check if all floating point registers have been fixed. */
372 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
377 target_flags |= MASK_DISABLE_FPREGS;
381 override_options (void)
383 if (pa_cpu_string == NULL)
384 pa_cpu_string = TARGET_SCHED_DEFAULT;
386 if (! strcmp (pa_cpu_string, "8000"))
388 pa_cpu_string = "8000";
389 pa_cpu = PROCESSOR_8000;
391 else if (! strcmp (pa_cpu_string, "7100"))
393 pa_cpu_string = "7100";
394 pa_cpu = PROCESSOR_7100;
396 else if (! strcmp (pa_cpu_string, "700"))
398 pa_cpu_string = "700";
399 pa_cpu = PROCESSOR_700;
401 else if (! strcmp (pa_cpu_string, "7100LC"))
403 pa_cpu_string = "7100LC";
404 pa_cpu = PROCESSOR_7100LC;
406 else if (! strcmp (pa_cpu_string, "7200"))
408 pa_cpu_string = "7200";
409 pa_cpu = PROCESSOR_7200;
411 else if (! strcmp (pa_cpu_string, "7300"))
413 pa_cpu_string = "7300";
414 pa_cpu = PROCESSOR_7300;
418 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
421 /* Set the instruction architecture. */
422 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
424 pa_arch_string = "1.0";
425 pa_arch = ARCHITECTURE_10;
426 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
428 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
430 pa_arch_string = "1.1";
431 pa_arch = ARCHITECTURE_11;
432 target_flags &= ~MASK_PA_20;
433 target_flags |= MASK_PA_11;
435 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
437 pa_arch_string = "2.0";
438 pa_arch = ARCHITECTURE_20;
439 target_flags |= MASK_PA_11 | MASK_PA_20;
441 else if (pa_arch_string)
443 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
448 /* Set the default UNIX standard for HP-UX. This affects the
449 predefines and startfiles used for the target. */
450 if (pa_unix_string == NULL)
452 = TARGET_HPUX_11_11 ? "98" : (TARGET_HPUX_10_10 ? "95" : "93");
454 if (!strcmp (pa_unix_string, "93"))
456 else if (!strcmp (pa_unix_string, "95"))
458 else if (TARGET_HPUX_11_11)
460 if (!strcmp (pa_unix_string, "98"))
463 warning ("unknown -munix= option (%s).\n"
464 "Valid options are 93, 95 and 98.\n",
467 else if (TARGET_HPUX_10_10)
468 warning ("unknown -munix= option (%s)."
469 "\nValid options are 93 and 95.\n",
472 warning ("unknown -munix= option (%s).\nValid option is 93.\n",
476 if (pa_fixed_range_string)
477 fix_range (pa_fixed_range_string);
479 /* Unconditional branches in the delay slot are not compatible with dwarf2
480 call frame information. There is no benefit in using this optimization
481 on PA8000 and later processors. */
482 if (pa_cpu >= PROCESSOR_8000
483 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
484 || flag_unwind_tables)
485 target_flags &= ~MASK_JUMP_IN_DELAY;
487 if (flag_pic && TARGET_PORTABLE_RUNTIME)
489 warning ("PIC code generation is not supported in the portable runtime model\n");
492 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
494 warning ("PIC code generation is not compatible with fast indirect calls\n");
497 if (! TARGET_GAS && write_symbols != NO_DEBUG)
499 warning ("-g is only supported when using GAS on this processor,");
500 warning ("-g option disabled");
501 write_symbols = NO_DEBUG;
504 /* We only support the "big PIC" model now. And we always generate PIC
505 code when in 64bit mode. */
506 if (flag_pic == 1 || TARGET_64BIT)
509 /* We can't guarantee that .dword is available for 32-bit targets. */
510 if (UNITS_PER_WORD == 4)
511 targetm.asm_out.aligned_op.di = NULL;
513 /* The unaligned ops are only available when using GAS. */
516 targetm.asm_out.unaligned_op.hi = NULL;
517 targetm.asm_out.unaligned_op.si = NULL;
518 targetm.asm_out.unaligned_op.di = NULL;
521 init_machine_status = pa_init_machine_status;
525 pa_init_builtins (void)
527 #ifdef DONT_HAVE_FPUTC_UNLOCKED
528 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
529 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
533 /* Function to init struct machine_function.
534 This will be called, via a pointer variable,
535 from push_function_context. */
537 static struct machine_function *
538 pa_init_machine_status (void)
540 return ggc_alloc_cleared (sizeof (machine_function));
543 /* If FROM is a probable pointer register, mark TO as a probable
544 pointer register with the same pointer alignment as FROM. */
547 copy_reg_pointer (rtx to, rtx from)
549 if (REG_POINTER (from))
550 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
553 /* Return nonzero only if OP is a register of mode MODE,
556 reg_or_0_operand (rtx op, enum machine_mode mode)
558 return (op == CONST0_RTX (mode) || register_operand (op, mode));
561 /* Return nonzero if OP is suitable for use in a call to a named
564 For 2.5 try to eliminate either call_operand_address or
565 function_label_operand, they perform very similar functions. */
567 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
569 return (GET_MODE (op) == word_mode
570 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
573 /* Return 1 if X contains a symbolic expression. We know these
574 expressions will have one of a few well defined forms, so
575 we need only check those forms. */
577 symbolic_expression_p (rtx x)
580 /* Strip off any HIGH. */
581 if (GET_CODE (x) == HIGH)
584 return (symbolic_operand (x, VOIDmode));
588 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
590 switch (GET_CODE (op))
597 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
598 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
599 && GET_CODE (XEXP (op, 1)) == CONST_INT);
605 /* Return truth value of statement that OP is a symbolic memory
606 operand of mode MODE. */
609 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
611 if (GET_CODE (op) == SUBREG)
612 op = SUBREG_REG (op);
613 if (GET_CODE (op) != MEM)
616 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
617 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
620 /* Return 1 if the operand is either a register, zero, or a memory operand
621 that is not symbolic. */
624 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
626 if (register_operand (op, mode))
629 if (op == CONST0_RTX (mode))
632 if (GET_CODE (op) == SUBREG)
633 op = SUBREG_REG (op);
635 if (GET_CODE (op) != MEM)
638 /* Until problems with management of the REG_POINTER flag are resolved,
639 we need to delay creating move insns with unscaled indexed addresses
640 until CSE is not expected. */
641 if (!TARGET_NO_SPACE_REGS
643 && GET_CODE (XEXP (op, 0)) == PLUS
644 && REG_P (XEXP (XEXP (op, 0), 0))
645 && REG_P (XEXP (XEXP (op, 0), 1)))
648 return (!symbolic_memory_operand (op, mode)
649 && memory_address_p (mode, XEXP (op, 0)));
652 /* Return 1 if the operand is a register operand or a non-symbolic memory
653 operand after reload. This predicate is used for branch patterns that
654 internally handle register reloading. We need to accept non-symbolic
655 memory operands after reload to ensure that the pattern is still valid
656 if reload didn't find a hard register for the operand. */
659 reg_before_reload_operand (rtx op, enum machine_mode mode)
661 /* Don't accept a SUBREG since it will need a reload. */
662 if (GET_CODE (op) == SUBREG)
665 if (register_operand (op, mode))
669 && memory_operand (op, mode)
670 && !symbolic_memory_operand (op, mode))
676 /* Accept any constant that can be moved in one instruction into a
679 cint_ok_for_move (HOST_WIDE_INT intval)
681 /* OK if ldo, ldil, or zdepi, can be used. */
682 return (CONST_OK_FOR_LETTER_P (intval, 'J')
683 || CONST_OK_FOR_LETTER_P (intval, 'N')
684 || CONST_OK_FOR_LETTER_P (intval, 'K'));
687 /* Return 1 iff OP is an indexed memory operand. */
689 indexed_memory_operand (rtx op, enum machine_mode mode)
691 if (GET_MODE (op) != mode)
694 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
695 if (reload_completed && GET_CODE (op) == SUBREG)
696 op = SUBREG_REG (op);
698 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
703 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
706 /* Accept anything that can be used as a destination operand for a
707 move instruction. We don't accept indexed memory operands since
708 they are supported only for floating point stores. */
710 move_dest_operand (rtx op, enum machine_mode mode)
712 if (register_operand (op, mode))
715 if (GET_MODE (op) != mode)
718 if (GET_CODE (op) == SUBREG)
719 op = SUBREG_REG (op);
721 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
726 return (memory_address_p (mode, op)
727 && !IS_INDEX_ADDR_P (op)
728 && !IS_LO_SUM_DLT_ADDR_P (op));
731 /* Accept anything that can be used as a source operand for a move
734 move_src_operand (rtx op, enum machine_mode mode)
736 if (register_operand (op, mode))
739 if (GET_CODE (op) == CONST_INT)
740 return cint_ok_for_move (INTVAL (op));
742 if (GET_MODE (op) != mode)
745 if (GET_CODE (op) == SUBREG)
746 op = SUBREG_REG (op);
748 if (GET_CODE (op) != MEM)
751 /* Until problems with management of the REG_POINTER flag are resolved,
752 we need to delay creating move insns with unscaled indexed addresses
753 until CSE is not expected. */
754 if (!TARGET_NO_SPACE_REGS
756 && GET_CODE (XEXP (op, 0)) == PLUS
757 && REG_P (XEXP (XEXP (op, 0), 0))
758 && REG_P (XEXP (XEXP (op, 0), 1)))
761 return memory_address_p (mode, XEXP (op, 0));
764 /* Accept anything that can be used as the source operand for a prefetch
765 instruction with a cache-control completer. */
767 prefetch_cc_operand (rtx op, enum machine_mode mode)
769 if (GET_CODE (op) != MEM)
774 /* We must reject virtual registers as we don't allow REG+D. */
775 if (op == virtual_incoming_args_rtx
776 || op == virtual_stack_vars_rtx
777 || op == virtual_stack_dynamic_rtx
778 || op == virtual_outgoing_args_rtx
779 || op == virtual_cfa_rtx)
782 if (!REG_P (op) && !IS_INDEX_ADDR_P (op))
785 /* Until problems with management of the REG_POINTER flag are resolved,
786 we need to delay creating prefetch insns with unscaled indexed addresses
787 until CSE is not expected. */
788 if (!TARGET_NO_SPACE_REGS
790 && GET_CODE (op) == PLUS
791 && REG_P (XEXP (op, 0)))
794 return memory_address_p (mode, op);
797 /* Accept anything that can be used as the source operand for a prefetch
798 instruction with no cache-control completer. */
800 prefetch_nocc_operand (rtx op, enum machine_mode mode)
802 if (GET_CODE (op) != MEM)
807 /* Until problems with management of the REG_POINTER flag are resolved,
808 we need to delay creating prefetch insns with unscaled indexed addresses
809 until CSE is not expected. */
810 if (!TARGET_NO_SPACE_REGS
812 && GET_CODE (op) == PLUS
813 && REG_P (XEXP (op, 0))
814 && REG_P (XEXP (op, 1)))
817 return memory_address_p (mode, op);
820 /* Accept REG and any CONST_INT that can be moved in one instruction into a
823 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
825 if (register_operand (op, mode))
828 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
832 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
837 switch (GET_CODE (op))
843 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
844 && GET_CODE (XEXP (op, 1)) == CONST_INT);
851 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
853 return reg_renumber && FP_REG_P (op);
858 /* Return truth value of whether OP can be used as an operand in a
859 three operand arithmetic insn that accepts registers of mode MODE
860 or 14-bit signed integers. */
862 arith_operand (rtx op, enum machine_mode mode)
864 return (register_operand (op, mode)
865 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
868 /* Return truth value of whether OP can be used as an operand in a
869 three operand arithmetic insn that accepts registers of mode MODE
870 or 11-bit signed integers. */
872 arith11_operand (rtx op, enum machine_mode mode)
874 return (register_operand (op, mode)
875 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
878 /* Return truth value of whether OP can be used as an operand in a
881 adddi3_operand (rtx op, enum machine_mode mode)
883 return (register_operand (op, mode)
884 || (GET_CODE (op) == CONST_INT
885 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
888 /* A constant integer suitable for use in a PRE_MODIFY memory
891 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
893 return (GET_CODE (op) == CONST_INT
894 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
897 /* A constant integer suitable for use in a POST_MODIFY memory
900 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
902 return (GET_CODE (op) == CONST_INT
903 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
907 arith_double_operand (rtx op, enum machine_mode mode)
909 return (register_operand (op, mode)
910 || (GET_CODE (op) == CONST_DOUBLE
911 && GET_MODE (op) == mode
912 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
913 && ((CONST_DOUBLE_HIGH (op) >= 0)
914 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
917 /* Return truth value of whether OP is an integer which fits the
918 range constraining immediate operands in three-address insns, or
919 is an integer register. */
922 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
924 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
925 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
928 /* Return nonzero if OP is an integer register, else return zero. */
930 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
932 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
935 /* Return truth value of whether OP is an integer which fits the
936 range constraining immediate operands in three-address insns. */
939 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
941 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
945 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
947 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
951 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
953 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
957 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
959 #if HOST_BITS_PER_WIDE_INT > 32
960 /* All allowed constants will fit a CONST_INT. */
961 return (GET_CODE (op) == CONST_INT
962 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
964 return (GET_CODE (op) == CONST_INT
965 || (GET_CODE (op) == CONST_DOUBLE
966 && CONST_DOUBLE_HIGH (op) == 0));
971 arith5_operand (rtx op, enum machine_mode mode)
973 return register_operand (op, mode) || int5_operand (op, mode);
976 /* True iff zdepi can be used to generate this CONST_INT.
977 zdepi first sign extends a 5 bit signed number to a given field
978 length, then places this field anywhere in a zero. */
980 zdepi_cint_p (unsigned HOST_WIDE_INT x)
982 unsigned HOST_WIDE_INT lsb_mask, t;
984 /* This might not be obvious, but it's at least fast.
985 This function is critical; we don't have the time loops would take. */
987 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
988 /* Return true iff t is a power of two. */
989 return ((t & (t - 1)) == 0);
992 /* True iff depi or extru can be used to compute (reg & mask).
993 Accept bit pattern like these:
998 and_mask_p (unsigned HOST_WIDE_INT mask)
1001 mask += mask & -mask;
1002 return (mask & (mask - 1)) == 0;
1005 /* True iff depi or extru can be used to compute (reg & OP). */
1007 and_operand (rtx op, enum machine_mode mode)
1009 return (register_operand (op, mode)
1010 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
1013 /* True iff depi can be used to compute (reg | MASK). */
1015 ior_mask_p (unsigned HOST_WIDE_INT mask)
1017 mask += mask & -mask;
1018 return (mask & (mask - 1)) == 0;
1021 /* True iff depi can be used to compute (reg | OP). */
1023 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1025 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
1029 lhs_lshift_operand (rtx op, enum machine_mode mode)
1031 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
1034 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
1035 Such values can be the left hand side x in (x << r), using the zvdepi
1038 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1040 unsigned HOST_WIDE_INT x;
1041 if (GET_CODE (op) != CONST_INT)
1043 x = INTVAL (op) >> 4;
1044 return (x & (x + 1)) == 0;
1048 arith32_operand (rtx op, enum machine_mode mode)
1050 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
1054 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1056 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
1059 /* Legitimize PIC addresses. If the address is already
1060 position-independent, we return ORIG. Newly generated
1061 position-independent addresses go to REG. If we need more
1062 than one register, we lose. */
1065 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
1069 /* Labels need special handling. */
1070 if (pic_label_operand (orig, mode))
1072 /* We do not want to go through the movXX expanders here since that
1073 would create recursion.
1075 Nor do we really want to call a generator for a named pattern
1076 since that requires multiple patterns if we want to support
1077 multiple word sizes.
1079 So instead we just emit the raw set, which avoids the movXX
1080 expanders completely. */
1081 mark_reg_pointer (reg, BITS_PER_UNIT);
1082 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
1083 current_function_uses_pic_offset_table = 1;
1086 if (GET_CODE (orig) == SYMBOL_REF)
1093 /* Before reload, allocate a temporary register for the intermediate
1094 result. This allows the sequence to be deleted when the final
1095 result is unused and the insns are trivially dead. */
1096 tmp_reg = ((reload_in_progress || reload_completed)
1097 ? reg : gen_reg_rtx (Pmode));
1099 emit_move_insn (tmp_reg,
1100 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
1101 gen_rtx_HIGH (word_mode, orig)));
1103 = gen_const_mem (Pmode,
1104 gen_rtx_LO_SUM (Pmode, tmp_reg,
1105 gen_rtx_UNSPEC (Pmode,
1106 gen_rtvec (1, orig),
1107 UNSPEC_DLTIND14R)));
1109 current_function_uses_pic_offset_table = 1;
1110 mark_reg_pointer (reg, BITS_PER_UNIT);
1111 insn = emit_move_insn (reg, pic_ref);
1113 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
1114 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
1118 else if (GET_CODE (orig) == CONST)
1122 if (GET_CODE (XEXP (orig, 0)) == PLUS
1123 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1129 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1131 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1132 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1133 base == reg ? 0 : reg);
1138 if (GET_CODE (orig) == CONST_INT)
1140 if (INT_14_BITS (orig))
1141 return plus_constant (base, INTVAL (orig));
1142 orig = force_reg (Pmode, orig);
1144 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1145 /* Likewise, should we set special REG_NOTEs here? */
1151 /* Try machine-dependent ways of modifying an illegitimate address
1152 to be legitimate. If we find one, return the new, valid address.
1153 This macro is used in only one place: `memory_address' in explow.c.
1155 OLDX is the address as it was before break_out_memory_refs was called.
1156 In some cases it is useful to look at this to decide what needs to be done.
1158 MODE and WIN are passed so that this macro can use
1159 GO_IF_LEGITIMATE_ADDRESS.
1161 It is always safe for this macro to do nothing. It exists to recognize
1162 opportunities to optimize the output.
1164 For the PA, transform:
1166 memory(X + <large int>)
1170 if (<large int> & mask) >= 16
1171 Y = (<large int> & ~mask) + mask + 1 Round up.
1173 Y = (<large int> & ~mask) Round down.
1175 memory (Z + (<large int> - Y));
1177 This is for CSE to find several similar references, and only use one Z.
1179 X can either be a SYMBOL_REF or REG, but because combine cannot
1180 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1181 D will not fit in 14 bits.
1183 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1186 MODE_INT references allow displacements which fit in 14 bits, so use
1189 This relies on the fact that most mode MODE_FLOAT references will use FP
1190 registers and most mode MODE_INT references will use integer registers.
1191 (In the rare case of an FP register used in an integer MODE, we depend
1192 on secondary reloads to clean things up.)
1195 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1196 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1197 addressing modes to be used).
1199 Put X and Z into registers. Then put the entire expression into
1203 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1204 enum machine_mode mode)
1208 /* We need to canonicalize the order of operands in unscaled indexed
1209 addresses since the code that checks if an address is valid doesn't
1210 always try both orders. */
1211 if (!TARGET_NO_SPACE_REGS
1212 && GET_CODE (x) == PLUS
1213 && GET_MODE (x) == Pmode
1214 && REG_P (XEXP (x, 0))
1215 && REG_P (XEXP (x, 1))
1216 && REG_POINTER (XEXP (x, 0))
1217 && !REG_POINTER (XEXP (x, 1)))
1218 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1221 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1223 /* Strip off CONST. */
1224 if (GET_CODE (x) == CONST)
1227 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1228 That should always be safe. */
1229 if (GET_CODE (x) == PLUS
1230 && GET_CODE (XEXP (x, 0)) == REG
1231 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1233 rtx reg = force_reg (Pmode, XEXP (x, 1));
1234 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1237 /* Note we must reject symbols which represent function addresses
1238 since the assembler/linker can't handle arithmetic on plabels. */
1239 if (GET_CODE (x) == PLUS
1240 && GET_CODE (XEXP (x, 1)) == CONST_INT
1241 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1242 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1243 || GET_CODE (XEXP (x, 0)) == REG))
1245 rtx int_part, ptr_reg;
1247 int offset = INTVAL (XEXP (x, 1));
1250 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1251 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1253 /* Choose which way to round the offset. Round up if we
1254 are >= halfway to the next boundary. */
1255 if ((offset & mask) >= ((mask + 1) / 2))
1256 newoffset = (offset & ~ mask) + mask + 1;
1258 newoffset = (offset & ~ mask);
1260 /* If the newoffset will not fit in 14 bits (ldo), then
1261 handling this would take 4 or 5 instructions (2 to load
1262 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1263 add the new offset and the SYMBOL_REF.) Combine can
1264 not handle 4->2 or 5->2 combinations, so do not create
1266 if (! VAL_14_BITS_P (newoffset)
1267 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1269 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1272 gen_rtx_HIGH (Pmode, const_part));
1275 gen_rtx_LO_SUM (Pmode,
1276 tmp_reg, const_part));
1280 if (! VAL_14_BITS_P (newoffset))
1281 int_part = force_reg (Pmode, GEN_INT (newoffset));
1283 int_part = GEN_INT (newoffset);
1285 ptr_reg = force_reg (Pmode,
1286 gen_rtx_PLUS (Pmode,
1287 force_reg (Pmode, XEXP (x, 0)),
1290 return plus_constant (ptr_reg, offset - newoffset);
1293 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1295 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1296 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1297 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1298 && (OBJECT_P (XEXP (x, 1))
1299 || GET_CODE (XEXP (x, 1)) == SUBREG)
1300 && GET_CODE (XEXP (x, 1)) != CONST)
1302 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1306 if (GET_CODE (reg1) != REG)
1307 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1309 reg2 = XEXP (XEXP (x, 0), 0);
1310 if (GET_CODE (reg2) != REG)
1311 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1313 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1314 gen_rtx_MULT (Pmode,
1320 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1322 Only do so for floating point modes since this is more speculative
1323 and we lose if it's an integer store. */
1324 if (GET_CODE (x) == PLUS
1325 && GET_CODE (XEXP (x, 0)) == PLUS
1326 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1327 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1328 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1329 && (mode == SFmode || mode == DFmode))
1332 /* First, try and figure out what to use as a base register. */
1333 rtx reg1, reg2, base, idx, orig_base;
1335 reg1 = XEXP (XEXP (x, 0), 1);
1340 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1341 then emit_move_sequence will turn on REG_POINTER so we'll know
1342 it's a base register below. */
1343 if (GET_CODE (reg1) != REG)
1344 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1346 if (GET_CODE (reg2) != REG)
1347 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1349 /* Figure out what the base and index are. */
1351 if (GET_CODE (reg1) == REG
1352 && REG_POINTER (reg1))
1355 orig_base = XEXP (XEXP (x, 0), 1);
1356 idx = gen_rtx_PLUS (Pmode,
1357 gen_rtx_MULT (Pmode,
1358 XEXP (XEXP (XEXP (x, 0), 0), 0),
1359 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1362 else if (GET_CODE (reg2) == REG
1363 && REG_POINTER (reg2))
1366 orig_base = XEXP (x, 1);
1373 /* If the index adds a large constant, try to scale the
1374 constant so that it can be loaded with only one insn. */
1375 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1376 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1377 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1378 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1380 /* Divide the CONST_INT by the scale factor, then add it to A. */
1381 int val = INTVAL (XEXP (idx, 1));
1383 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1384 reg1 = XEXP (XEXP (idx, 0), 0);
1385 if (GET_CODE (reg1) != REG)
1386 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1388 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1390 /* We can now generate a simple scaled indexed address. */
1393 (Pmode, gen_rtx_PLUS (Pmode,
1394 gen_rtx_MULT (Pmode, reg1,
1395 XEXP (XEXP (idx, 0), 1)),
1399 /* If B + C is still a valid base register, then add them. */
1400 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1401 && INTVAL (XEXP (idx, 1)) <= 4096
1402 && INTVAL (XEXP (idx, 1)) >= -4096)
1404 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1407 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1409 reg2 = XEXP (XEXP (idx, 0), 0);
1410 if (GET_CODE (reg2) != CONST_INT)
1411 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1413 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1414 gen_rtx_MULT (Pmode,
1420 /* Get the index into a register, then add the base + index and
1421 return a register holding the result. */
1423 /* First get A into a register. */
1424 reg1 = XEXP (XEXP (idx, 0), 0);
1425 if (GET_CODE (reg1) != REG)
1426 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1428 /* And get B into a register. */
1429 reg2 = XEXP (idx, 1);
1430 if (GET_CODE (reg2) != REG)
1431 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1433 reg1 = force_reg (Pmode,
1434 gen_rtx_PLUS (Pmode,
1435 gen_rtx_MULT (Pmode, reg1,
1436 XEXP (XEXP (idx, 0), 1)),
1439 /* Add the result to our base register and return. */
1440 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1444 /* Uh-oh. We might have an address for x[n-100000]. This needs
1445 special handling to avoid creating an indexed memory address
1446 with x-100000 as the base.
1448 If the constant part is small enough, then it's still safe because
1449 there is a guard page at the beginning and end of the data segment.
1451 Scaled references are common enough that we want to try and rearrange the
1452 terms so that we can use indexing for these addresses too. Only
1453 do the optimization for floatint point modes. */
1455 if (GET_CODE (x) == PLUS
1456 && symbolic_expression_p (XEXP (x, 1)))
1458 /* Ugly. We modify things here so that the address offset specified
1459 by the index expression is computed first, then added to x to form
1460 the entire address. */
1462 rtx regx1, regx2, regy1, regy2, y;
1464 /* Strip off any CONST. */
1466 if (GET_CODE (y) == CONST)
1469 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1471 /* See if this looks like
1472 (plus (mult (reg) (shadd_const))
1473 (const (plus (symbol_ref) (const_int))))
1475 Where const_int is small. In that case the const
1476 expression is a valid pointer for indexing.
1478 If const_int is big, but can be divided evenly by shadd_const
1479 and added to (reg). This allows more scaled indexed addresses. */
1480 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1481 && GET_CODE (XEXP (x, 0)) == MULT
1482 && GET_CODE (XEXP (y, 1)) == CONST_INT
1483 && INTVAL (XEXP (y, 1)) >= -4096
1484 && INTVAL (XEXP (y, 1)) <= 4095
1485 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1486 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1488 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1492 if (GET_CODE (reg1) != REG)
1493 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1495 reg2 = XEXP (XEXP (x, 0), 0);
1496 if (GET_CODE (reg2) != REG)
1497 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1499 return force_reg (Pmode,
1500 gen_rtx_PLUS (Pmode,
1501 gen_rtx_MULT (Pmode,
1506 else if ((mode == DFmode || mode == SFmode)
1507 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1508 && GET_CODE (XEXP (x, 0)) == MULT
1509 && GET_CODE (XEXP (y, 1)) == CONST_INT
1510 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1511 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1512 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1515 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1516 / INTVAL (XEXP (XEXP (x, 0), 1))));
1517 regx2 = XEXP (XEXP (x, 0), 0);
1518 if (GET_CODE (regx2) != REG)
1519 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1520 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1524 gen_rtx_PLUS (Pmode,
1525 gen_rtx_MULT (Pmode, regx2,
1526 XEXP (XEXP (x, 0), 1)),
1527 force_reg (Pmode, XEXP (y, 0))));
1529 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1530 && INTVAL (XEXP (y, 1)) >= -4096
1531 && INTVAL (XEXP (y, 1)) <= 4095)
1533 /* This is safe because of the guard page at the
1534 beginning and end of the data space. Just
1535 return the original address. */
1540 /* Doesn't look like one we can optimize. */
1541 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1542 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1543 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1544 regx1 = force_reg (Pmode,
1545 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1547 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1555 /* For the HPPA, REG and REG+CONST is cost 0
1556 and addresses involving symbolic constants are cost 2.
1558 PIC addresses are very expensive.
1560 It is no coincidence that this has the same structure
1561 as GO_IF_LEGITIMATE_ADDRESS. */
1564 hppa_address_cost (rtx X)
1566 switch (GET_CODE (X))
1579 /* Compute a (partial) cost for rtx X. Return true if the complete
1580 cost has been computed, and false if subexpressions should be
1581 scanned. In either case, *TOTAL contains the cost result. */
1584 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1589 if (INTVAL (x) == 0)
1591 else if (INT_14_BITS (x))
1608 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1609 && outer_code != SET)
1616 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1617 *total = COSTS_N_INSNS (3);
1618 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1619 *total = COSTS_N_INSNS (8);
1621 *total = COSTS_N_INSNS (20);
1625 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1627 *total = COSTS_N_INSNS (14);
1635 *total = COSTS_N_INSNS (60);
1638 case PLUS: /* this includes shNadd insns */
1640 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1641 *total = COSTS_N_INSNS (3);
1643 *total = COSTS_N_INSNS (1);
1649 *total = COSTS_N_INSNS (1);
1657 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1658 new rtx with the correct mode. */
1660 force_mode (enum machine_mode mode, rtx orig)
1662 if (mode == GET_MODE (orig))
1665 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1668 return gen_rtx_REG (mode, REGNO (orig));
1671 /* Emit insns to move operands[1] into operands[0].
1673 Return 1 if we have written out everything that needs to be done to
1674 do the move. Otherwise, return 0 and the caller will emit the move
1677 Note SCRATCH_REG may not be in the proper mode depending on how it
1678 will be used. This routine is responsible for creating a new copy
1679 of SCRATCH_REG in the proper mode. */
1682 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1684 register rtx operand0 = operands[0];
1685 register rtx operand1 = operands[1];
1688 /* We can only handle indexed addresses in the destination operand
1689 of floating point stores. Thus, we need to break out indexed
1690 addresses from the destination operand. */
1691 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1693 /* This is only safe up to the beginning of life analysis. */
1697 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1698 operand0 = replace_equiv_address (operand0, tem);
1701 /* On targets with non-equivalent space registers, break out unscaled
1702 indexed addresses from the source operand before the final CSE.
1703 We have to do this because the REG_POINTER flag is not correctly
1704 carried through various optimization passes and CSE may substitute
1705 a pseudo without the pointer set for one with the pointer set. As
1706 a result, we loose various opportunities to create insns with
1707 unscaled indexed addresses. */
1708 if (!TARGET_NO_SPACE_REGS
1709 && !cse_not_expected
1710 && GET_CODE (operand1) == MEM
1711 && GET_CODE (XEXP (operand1, 0)) == PLUS
1712 && REG_P (XEXP (XEXP (operand1, 0), 0))
1713 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1715 = replace_equiv_address (operand1,
1716 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1719 && reload_in_progress && GET_CODE (operand0) == REG
1720 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1721 operand0 = reg_equiv_mem[REGNO (operand0)];
1722 else if (scratch_reg
1723 && reload_in_progress && GET_CODE (operand0) == SUBREG
1724 && GET_CODE (SUBREG_REG (operand0)) == REG
1725 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1727 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1728 the code which tracks sets/uses for delete_output_reload. */
1729 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1730 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1731 SUBREG_BYTE (operand0));
1732 operand0 = alter_subreg (&temp);
1736 && reload_in_progress && GET_CODE (operand1) == REG
1737 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1738 operand1 = reg_equiv_mem[REGNO (operand1)];
1739 else if (scratch_reg
1740 && reload_in_progress && GET_CODE (operand1) == SUBREG
1741 && GET_CODE (SUBREG_REG (operand1)) == REG
1742 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1744 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1745 the code which tracks sets/uses for delete_output_reload. */
1746 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1747 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1748 SUBREG_BYTE (operand1));
1749 operand1 = alter_subreg (&temp);
1752 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1753 && ((tem = find_replacement (&XEXP (operand0, 0)))
1754 != XEXP (operand0, 0)))
1755 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1757 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1758 && ((tem = find_replacement (&XEXP (operand1, 0)))
1759 != XEXP (operand1, 0)))
1760 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1762 /* Handle secondary reloads for loads/stores of FP registers from
1763 REG+D addresses where D does not fit in 5 or 14 bits, including
1764 (subreg (mem (addr))) cases. */
1766 && fp_reg_operand (operand0, mode)
1767 && ((GET_CODE (operand1) == MEM
1768 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1769 XEXP (operand1, 0)))
1770 || ((GET_CODE (operand1) == SUBREG
1771 && GET_CODE (XEXP (operand1, 0)) == MEM
1772 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1774 XEXP (XEXP (operand1, 0), 0))))))
1776 if (GET_CODE (operand1) == SUBREG)
1777 operand1 = XEXP (operand1, 0);
1779 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1780 it in WORD_MODE regardless of what mode it was originally given
1782 scratch_reg = force_mode (word_mode, scratch_reg);
1784 /* D might not fit in 14 bits either; for such cases load D into
1786 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1788 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1789 emit_move_insn (scratch_reg,
1790 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1792 XEXP (XEXP (operand1, 0), 0),
1796 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1797 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1798 gen_rtx_MEM (mode, scratch_reg)));
1801 else if (scratch_reg
1802 && fp_reg_operand (operand1, mode)
1803 && ((GET_CODE (operand0) == MEM
1804 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1806 XEXP (operand0, 0)))
1807 || ((GET_CODE (operand0) == SUBREG)
1808 && GET_CODE (XEXP (operand0, 0)) == MEM
1809 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1811 XEXP (XEXP (operand0, 0), 0)))))
1813 if (GET_CODE (operand0) == SUBREG)
1814 operand0 = XEXP (operand0, 0);
1816 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1817 it in WORD_MODE regardless of what mode it was originally given
1819 scratch_reg = force_mode (word_mode, scratch_reg);
1821 /* D might not fit in 14 bits either; for such cases load D into
1823 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1825 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1826 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1829 XEXP (XEXP (operand0, 0),
1834 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1835 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1839 /* Handle secondary reloads for loads of FP registers from constant
1840 expressions by forcing the constant into memory.
1842 Use scratch_reg to hold the address of the memory location.
1844 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1845 NO_REGS when presented with a const_int and a register class
1846 containing only FP registers. Doing so unfortunately creates
1847 more problems than it solves. Fix this for 2.5. */
1848 else if (scratch_reg
1849 && CONSTANT_P (operand1)
1850 && fp_reg_operand (operand0, mode))
1854 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1855 it in WORD_MODE regardless of what mode it was originally given
1857 scratch_reg = force_mode (word_mode, scratch_reg);
1859 /* Force the constant into memory and put the address of the
1860 memory location into scratch_reg. */
1861 xoperands[0] = scratch_reg;
1862 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1863 emit_move_sequence (xoperands, Pmode, 0);
1865 /* Now load the destination register. */
1866 emit_insn (gen_rtx_SET (mode, operand0,
1867 gen_rtx_MEM (mode, scratch_reg)));
1870 /* Handle secondary reloads for SAR. These occur when trying to load
1871 the SAR from memory, FP register, or with a constant. */
1872 else if (scratch_reg
1873 && GET_CODE (operand0) == REG
1874 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1875 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1876 && (GET_CODE (operand1) == MEM
1877 || GET_CODE (operand1) == CONST_INT
1878 || (GET_CODE (operand1) == REG
1879 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1881 /* D might not fit in 14 bits either; for such cases load D into
1883 if (GET_CODE (operand1) == MEM
1884 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1886 /* We are reloading the address into the scratch register, so we
1887 want to make sure the scratch register is a full register. */
1888 scratch_reg = force_mode (word_mode, scratch_reg);
1890 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1891 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1894 XEXP (XEXP (operand1, 0),
1898 /* Now we are going to load the scratch register from memory,
1899 we want to load it in the same width as the original MEM,
1900 which must be the same as the width of the ultimate destination,
1902 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1904 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1909 /* We want to load the scratch register using the same mode as
1910 the ultimate destination. */
1911 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1913 emit_move_insn (scratch_reg, operand1);
1916 /* And emit the insn to set the ultimate destination. We know that
1917 the scratch register has the same mode as the destination at this
1919 emit_move_insn (operand0, scratch_reg);
1922 /* Handle the most common case: storing into a register. */
1923 else if (register_operand (operand0, mode))
1925 if (register_operand (operand1, mode)
1926 || (GET_CODE (operand1) == CONST_INT
1927 && cint_ok_for_move (INTVAL (operand1)))
1928 || (operand1 == CONST0_RTX (mode))
1929 || (GET_CODE (operand1) == HIGH
1930 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1931 /* Only `general_operands' can come here, so MEM is ok. */
1932 || GET_CODE (operand1) == MEM)
1934 /* Various sets are created during RTL generation which don't
1935 have the REG_POINTER flag correctly set. After the CSE pass,
1936 instruction recognition can fail if we don't consistently
1937 set this flag when performing register copies. This should
1938 also improve the opportunities for creating insns that use
1939 unscaled indexing. */
1940 if (REG_P (operand0) && REG_P (operand1))
1942 if (REG_POINTER (operand1)
1943 && !REG_POINTER (operand0)
1944 && !HARD_REGISTER_P (operand0))
1945 copy_reg_pointer (operand0, operand1);
1946 else if (REG_POINTER (operand0)
1947 && !REG_POINTER (operand1)
1948 && !HARD_REGISTER_P (operand1))
1949 copy_reg_pointer (operand1, operand0);
1952 /* When MEMs are broken out, the REG_POINTER flag doesn't
1953 get set. In some cases, we can set the REG_POINTER flag
1954 from the declaration for the MEM. */
1955 if (REG_P (operand0)
1956 && GET_CODE (operand1) == MEM
1957 && !REG_POINTER (operand0))
1959 tree decl = MEM_EXPR (operand1);
1961 /* Set the register pointer flag and register alignment
1962 if the declaration for this memory reference is a
1963 pointer type. Fortran indirect argument references
1966 && !(flag_argument_noalias > 1
1967 && TREE_CODE (decl) == INDIRECT_REF
1968 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1972 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1974 if (TREE_CODE (decl) == COMPONENT_REF)
1975 decl = TREE_OPERAND (decl, 1);
1977 type = TREE_TYPE (decl);
1978 if (TREE_CODE (type) == ARRAY_TYPE)
1979 type = get_inner_array_type (type);
1981 if (POINTER_TYPE_P (type))
1985 type = TREE_TYPE (type);
1986 /* Using TYPE_ALIGN_OK is rather conservative as
1987 only the ada frontend actually sets it. */
1988 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1990 mark_reg_pointer (operand0, align);
1995 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1999 else if (GET_CODE (operand0) == MEM)
2001 if (mode == DFmode && operand1 == CONST0_RTX (mode)
2002 && !(reload_in_progress || reload_completed))
2004 rtx temp = gen_reg_rtx (DFmode);
2006 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
2007 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
2010 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
2012 /* Run this case quickly. */
2013 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
2016 if (! (reload_in_progress || reload_completed))
2018 operands[0] = validize_mem (operand0);
2019 operands[1] = operand1 = force_reg (mode, operand1);
2023 /* Simplify the source if we need to.
2024 Note we do have to handle function labels here, even though we do
2025 not consider them legitimate constants. Loop optimizations can
2026 call the emit_move_xxx with one as a source. */
2027 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
2028 || function_label_operand (operand1, mode)
2029 || (GET_CODE (operand1) == HIGH
2030 && symbolic_operand (XEXP (operand1, 0), mode)))
2034 if (GET_CODE (operand1) == HIGH)
2037 operand1 = XEXP (operand1, 0);
2039 if (symbolic_operand (operand1, mode))
2041 /* Argh. The assembler and linker can't handle arithmetic
2044 So we force the plabel into memory, load operand0 from
2045 the memory location, then add in the constant part. */
2046 if ((GET_CODE (operand1) == CONST
2047 && GET_CODE (XEXP (operand1, 0)) == PLUS
2048 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
2049 || function_label_operand (operand1, mode))
2051 rtx temp, const_part;
2053 /* Figure out what (if any) scratch register to use. */
2054 if (reload_in_progress || reload_completed)
2056 scratch_reg = scratch_reg ? scratch_reg : operand0;
2057 /* SCRATCH_REG will hold an address and maybe the actual
2058 data. We want it in WORD_MODE regardless of what mode it
2059 was originally given to us. */
2060 scratch_reg = force_mode (word_mode, scratch_reg);
2063 scratch_reg = gen_reg_rtx (Pmode);
2065 if (GET_CODE (operand1) == CONST)
2067 /* Save away the constant part of the expression. */
2068 const_part = XEXP (XEXP (operand1, 0), 1);
2069 if (GET_CODE (const_part) != CONST_INT)
2072 /* Force the function label into memory. */
2073 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
2077 /* No constant part. */
2078 const_part = NULL_RTX;
2080 /* Force the function label into memory. */
2081 temp = force_const_mem (mode, operand1);
2085 /* Get the address of the memory location. PIC-ify it if
2087 temp = XEXP (temp, 0);
2089 temp = legitimize_pic_address (temp, mode, scratch_reg);
2091 /* Put the address of the memory location into our destination
2094 emit_move_sequence (operands, mode, scratch_reg);
2096 /* Now load from the memory location into our destination
2098 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
2099 emit_move_sequence (operands, mode, scratch_reg);
2101 /* And add back in the constant part. */
2102 if (const_part != NULL_RTX)
2103 expand_inc (operand0, const_part);
2112 if (reload_in_progress || reload_completed)
2114 temp = scratch_reg ? scratch_reg : operand0;
2115 /* TEMP will hold an address and maybe the actual
2116 data. We want it in WORD_MODE regardless of what mode it
2117 was originally given to us. */
2118 temp = force_mode (word_mode, temp);
2121 temp = gen_reg_rtx (Pmode);
2123 /* (const (plus (symbol) (const_int))) must be forced to
2124 memory during/after reload if the const_int will not fit
2126 if (GET_CODE (operand1) == CONST
2127 && GET_CODE (XEXP (operand1, 0)) == PLUS
2128 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
2129 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
2130 && (reload_completed || reload_in_progress)
2133 operands[1] = force_const_mem (mode, operand1);
2134 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
2136 operands[1] = gen_rtx_MEM (mode, operands[1]);
2137 emit_move_sequence (operands, mode, temp);
2141 operands[1] = legitimize_pic_address (operand1, mode, temp);
2142 if (REG_P (operand0) && REG_P (operands[1]))
2143 copy_reg_pointer (operand0, operands[1]);
2144 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2147 /* On the HPPA, references to data space are supposed to use dp,
2148 register 27, but showing it in the RTL inhibits various cse
2149 and loop optimizations. */
2154 if (reload_in_progress || reload_completed)
2156 temp = scratch_reg ? scratch_reg : operand0;
2157 /* TEMP will hold an address and maybe the actual
2158 data. We want it in WORD_MODE regardless of what mode it
2159 was originally given to us. */
2160 temp = force_mode (word_mode, temp);
2163 temp = gen_reg_rtx (mode);
2165 /* Loading a SYMBOL_REF into a register makes that register
2166 safe to be used as the base in an indexed address.
2168 Don't mark hard registers though. That loses. */
2169 if (GET_CODE (operand0) == REG
2170 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2171 mark_reg_pointer (operand0, BITS_PER_UNIT);
2172 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2173 mark_reg_pointer (temp, BITS_PER_UNIT);
2176 set = gen_rtx_SET (mode, operand0, temp);
2178 set = gen_rtx_SET (VOIDmode,
2180 gen_rtx_LO_SUM (mode, temp, operand1));
2182 emit_insn (gen_rtx_SET (VOIDmode,
2184 gen_rtx_HIGH (mode, operand1)));
2190 else if (GET_CODE (operand1) != CONST_INT
2191 || !cint_ok_for_move (INTVAL (operand1)))
2195 HOST_WIDE_INT value = 0;
2196 HOST_WIDE_INT insv = 0;
2199 if (GET_CODE (operand1) == CONST_INT)
2200 value = INTVAL (operand1);
2203 && GET_CODE (operand1) == CONST_INT
2204 && HOST_BITS_PER_WIDE_INT > 32
2205 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2209 /* Extract the low order 32 bits of the value and sign extend.
2210 If the new value is the same as the original value, we can
2211 can use the original value as-is. If the new value is
2212 different, we use it and insert the most-significant 32-bits
2213 of the original value into the final result. */
2214 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2215 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2218 #if HOST_BITS_PER_WIDE_INT > 32
2219 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2223 operand1 = GEN_INT (nval);
2227 if (reload_in_progress || reload_completed)
2228 temp = scratch_reg ? scratch_reg : operand0;
2230 temp = gen_reg_rtx (mode);
2232 /* We don't directly split DImode constants on 32-bit targets
2233 because PLUS uses an 11-bit immediate and the insn sequence
2234 generated is not as efficient as the one using HIGH/LO_SUM. */
2235 if (GET_CODE (operand1) == CONST_INT
2236 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2239 /* Directly break constant into high and low parts. This
2240 provides better optimization opportunities because various
2241 passes recognize constants split with PLUS but not LO_SUM.
2242 We use a 14-bit signed low part except when the addition
2243 of 0x4000 to the high part might change the sign of the
2245 HOST_WIDE_INT low = value & 0x3fff;
2246 HOST_WIDE_INT high = value & ~ 0x3fff;
2250 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2258 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2259 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2263 emit_insn (gen_rtx_SET (VOIDmode, temp,
2264 gen_rtx_HIGH (mode, operand1)));
2265 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2268 insn = emit_move_insn (operands[0], operands[1]);
2270 /* Now insert the most significant 32 bits of the value
2271 into the register. When we don't have a second register
2272 available, it could take up to nine instructions to load
2273 a 64-bit integer constant. Prior to reload, we force
2274 constants that would take more than three instructions
2275 to load to the constant pool. During and after reload,
2276 we have to handle all possible values. */
2279 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2280 register and the value to be inserted is outside the
2281 range that can be loaded with three depdi instructions. */
2282 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2284 operand1 = GEN_INT (insv);
2286 emit_insn (gen_rtx_SET (VOIDmode, temp,
2287 gen_rtx_HIGH (mode, operand1)));
2288 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2289 emit_insn (gen_insv (operand0, GEN_INT (32),
2294 int len = 5, pos = 27;
2296 /* Insert the bits using the depdi instruction. */
2299 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2300 HOST_WIDE_INT sign = v5 < 0;
2302 /* Left extend the insertion. */
2303 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2304 while (pos > 0 && (insv & 1) == sign)
2306 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2311 emit_insn (gen_insv (operand0, GEN_INT (len),
2312 GEN_INT (pos), GEN_INT (v5)));
2314 len = pos > 0 && pos < 5 ? pos : 5;
2321 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2326 /* Now have insn-emit do whatever it normally does. */
2330 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2331 it will need a link/runtime reloc). */
2334 reloc_needed (tree exp)
2338 switch (TREE_CODE (exp))
2345 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2346 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2351 case NON_LVALUE_EXPR:
2352 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2358 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2359 if (TREE_VALUE (link) != 0)
2360 reloc |= reloc_needed (TREE_VALUE (link));
2373 /* Does operand (which is a symbolic_operand) live in text space?
2374 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2378 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2380 if (GET_CODE (operand) == CONST)
2381 operand = XEXP (XEXP (operand, 0), 0);
2384 if (GET_CODE (operand) == SYMBOL_REF)
2385 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2389 if (GET_CODE (operand) == SYMBOL_REF)
2390 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2396 /* Return the best assembler insn template
2397 for moving operands[1] into operands[0] as a fullword. */
2399 singlemove_string (rtx *operands)
2401 HOST_WIDE_INT intval;
2403 if (GET_CODE (operands[0]) == MEM)
2404 return "stw %r1,%0";
2405 if (GET_CODE (operands[1]) == MEM)
2407 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2412 if (GET_MODE (operands[1]) != SFmode)
2415 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2417 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2418 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2420 operands[1] = GEN_INT (i);
2421 /* Fall through to CONST_INT case. */
2423 if (GET_CODE (operands[1]) == CONST_INT)
2425 intval = INTVAL (operands[1]);
2427 if (VAL_14_BITS_P (intval))
2429 else if ((intval & 0x7ff) == 0)
2430 return "ldil L'%1,%0";
2431 else if (zdepi_cint_p (intval))
2432 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2434 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2436 return "copy %1,%0";
2440 /* Compute position (in OP[1]) and width (in OP[2])
2441 useful for copying IMM to a register using the zdepi
2442 instructions. Store the immediate value to insert in OP[0]. */
2444 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2448 /* Find the least significant set bit in IMM. */
2449 for (lsb = 0; lsb < 32; lsb++)
2456 /* Choose variants based on *sign* of the 5-bit field. */
2457 if ((imm & 0x10) == 0)
2458 len = (lsb <= 28) ? 4 : 32 - lsb;
2461 /* Find the width of the bitstring in IMM. */
2462 for (len = 5; len < 32; len++)
2464 if ((imm & (1 << len)) == 0)
2468 /* Sign extend IMM as a 5-bit value. */
2469 imm = (imm & 0xf) - 0x10;
2477 /* Compute position (in OP[1]) and width (in OP[2])
2478 useful for copying IMM to a register using the depdi,z
2479 instructions. Store the immediate value to insert in OP[0]. */
2481 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2483 HOST_WIDE_INT lsb, len;
2485 /* Find the least significant set bit in IMM. */
2486 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2493 /* Choose variants based on *sign* of the 5-bit field. */
2494 if ((imm & 0x10) == 0)
2495 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2496 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2499 /* Find the width of the bitstring in IMM. */
2500 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2502 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2506 /* Sign extend IMM as a 5-bit value. */
2507 imm = (imm & 0xf) - 0x10;
2515 /* Output assembler code to perform a doubleword move insn
2516 with operands OPERANDS. */
2519 output_move_double (rtx *operands)
2521 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2523 rtx addreg0 = 0, addreg1 = 0;
2525 /* First classify both operands. */
2527 if (REG_P (operands[0]))
2529 else if (offsettable_memref_p (operands[0]))
2531 else if (GET_CODE (operands[0]) == MEM)
2536 if (REG_P (operands[1]))
2538 else if (CONSTANT_P (operands[1]))
2540 else if (offsettable_memref_p (operands[1]))
2542 else if (GET_CODE (operands[1]) == MEM)
2547 /* Check for the cases that the operand constraints are not
2548 supposed to allow to happen. Abort if we get one,
2549 because generating code for these cases is painful. */
2551 if (optype0 != REGOP && optype1 != REGOP)
2554 /* Handle auto decrementing and incrementing loads and stores
2555 specifically, since the structure of the function doesn't work
2556 for them without major modification. Do it better when we learn
2557 this port about the general inc/dec addressing of PA.
2558 (This was written by tege. Chide him if it doesn't work.) */
2560 if (optype0 == MEMOP)
2562 /* We have to output the address syntax ourselves, since print_operand
2563 doesn't deal with the addresses we want to use. Fix this later. */
2565 rtx addr = XEXP (operands[0], 0);
2566 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2568 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2570 operands[0] = XEXP (addr, 0);
2571 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2574 if (!reg_overlap_mentioned_p (high_reg, addr))
2576 /* No overlap between high target register and address
2577 register. (We do this in a non-obvious way to
2578 save a register file writeback) */
2579 if (GET_CODE (addr) == POST_INC)
2580 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2581 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2586 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2588 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2590 operands[0] = XEXP (addr, 0);
2591 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2594 if (!reg_overlap_mentioned_p (high_reg, addr))
2596 /* No overlap between high target register and address
2597 register. (We do this in a non-obvious way to
2598 save a register file writeback) */
2599 if (GET_CODE (addr) == PRE_INC)
2600 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2601 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2607 if (optype1 == MEMOP)
2609 /* We have to output the address syntax ourselves, since print_operand
2610 doesn't deal with the addresses we want to use. Fix this later. */
2612 rtx addr = XEXP (operands[1], 0);
2613 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2615 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2617 operands[1] = XEXP (addr, 0);
2618 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2621 if (!reg_overlap_mentioned_p (high_reg, addr))
2623 /* No overlap between high target register and address
2624 register. (We do this in a non-obvious way to
2625 save a register file writeback) */
2626 if (GET_CODE (addr) == POST_INC)
2627 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2628 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2632 /* This is an undefined situation. We should load into the
2633 address register *and* update that register. Probably
2634 we don't need to handle this at all. */
2635 if (GET_CODE (addr) == POST_INC)
2636 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2637 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2640 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2642 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2644 operands[1] = XEXP (addr, 0);
2645 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2648 if (!reg_overlap_mentioned_p (high_reg, addr))
2650 /* No overlap between high target register and address
2651 register. (We do this in a non-obvious way to
2652 save a register file writeback) */
2653 if (GET_CODE (addr) == PRE_INC)
2654 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2655 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2659 /* This is an undefined situation. We should load into the
2660 address register *and* update that register. Probably
2661 we don't need to handle this at all. */
2662 if (GET_CODE (addr) == PRE_INC)
2663 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2664 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2667 else if (GET_CODE (addr) == PLUS
2668 && GET_CODE (XEXP (addr, 0)) == MULT)
2670 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2672 if (!reg_overlap_mentioned_p (high_reg, addr))
2676 xoperands[0] = high_reg;
2677 xoperands[1] = XEXP (addr, 1);
2678 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2679 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2680 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2682 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2688 xoperands[0] = high_reg;
2689 xoperands[1] = XEXP (addr, 1);
2690 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2691 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2692 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2694 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2699 /* If an operand is an unoffsettable memory ref, find a register
2700 we can increment temporarily to make it refer to the second word. */
2702 if (optype0 == MEMOP)
2703 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2705 if (optype1 == MEMOP)
2706 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2708 /* Ok, we can do one word at a time.
2709 Normally we do the low-numbered word first.
2711 In either case, set up in LATEHALF the operands to use
2712 for the high-numbered word and in some cases alter the
2713 operands in OPERANDS to be suitable for the low-numbered word. */
2715 if (optype0 == REGOP)
2716 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2717 else if (optype0 == OFFSOP)
2718 latehalf[0] = adjust_address (operands[0], SImode, 4);
2720 latehalf[0] = operands[0];
2722 if (optype1 == REGOP)
2723 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2724 else if (optype1 == OFFSOP)
2725 latehalf[1] = adjust_address (operands[1], SImode, 4);
2726 else if (optype1 == CNSTOP)
2727 split_double (operands[1], &operands[1], &latehalf[1]);
2729 latehalf[1] = operands[1];
2731 /* If the first move would clobber the source of the second one,
2732 do them in the other order.
2734 This can happen in two cases:
2736 mem -> register where the first half of the destination register
2737 is the same register used in the memory's address. Reload
2738 can create such insns.
2740 mem in this case will be either register indirect or register
2741 indirect plus a valid offset.
2743 register -> register move where REGNO(dst) == REGNO(src + 1)
2744 someone (Tim/Tege?) claimed this can happen for parameter loads.
2746 Handle mem -> register case first. */
2747 if (optype0 == REGOP
2748 && (optype1 == MEMOP || optype1 == OFFSOP)
2749 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2752 /* Do the late half first. */
2754 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2755 output_asm_insn (singlemove_string (latehalf), latehalf);
2759 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2760 return singlemove_string (operands);
2763 /* Now handle register -> register case. */
2764 if (optype0 == REGOP && optype1 == REGOP
2765 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2767 output_asm_insn (singlemove_string (latehalf), latehalf);
2768 return singlemove_string (operands);
2771 /* Normal case: do the two words, low-numbered first. */
2773 output_asm_insn (singlemove_string (operands), operands);
2775 /* Make any unoffsettable addresses point at high-numbered word. */
2777 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2779 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2782 output_asm_insn (singlemove_string (latehalf), latehalf);
2784 /* Undo the adds we just did. */
2786 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2788 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2794 output_fp_move_double (rtx *operands)
2796 if (FP_REG_P (operands[0]))
2798 if (FP_REG_P (operands[1])
2799 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2800 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2802 output_asm_insn ("fldd%F1 %1,%0", operands);
2804 else if (FP_REG_P (operands[1]))
2806 output_asm_insn ("fstd%F0 %1,%0", operands);
2808 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2810 if (GET_CODE (operands[0]) == REG)
2813 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2814 xoperands[0] = operands[0];
2815 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2817 /* This is a pain. You have to be prepared to deal with an
2818 arbitrary address here including pre/post increment/decrement.
2820 so avoid this in the MD. */
2828 /* Return a REG that occurs in ADDR with coefficient 1.
2829 ADDR can be effectively incremented by incrementing REG. */
2832 find_addr_reg (rtx addr)
2834 while (GET_CODE (addr) == PLUS)
2836 if (GET_CODE (XEXP (addr, 0)) == REG)
2837 addr = XEXP (addr, 0);
2838 else if (GET_CODE (XEXP (addr, 1)) == REG)
2839 addr = XEXP (addr, 1);
2840 else if (CONSTANT_P (XEXP (addr, 0)))
2841 addr = XEXP (addr, 1);
2842 else if (CONSTANT_P (XEXP (addr, 1)))
2843 addr = XEXP (addr, 0);
2847 if (GET_CODE (addr) == REG)
2852 /* Emit code to perform a block move.
2854 OPERANDS[0] is the destination pointer as a REG, clobbered.
2855 OPERANDS[1] is the source pointer as a REG, clobbered.
2856 OPERANDS[2] is a register for temporary storage.
2857 OPERANDS[3] is a register for temporary storage.
2858 OPERANDS[4] is the size as a CONST_INT
2859 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2860 OPERANDS[6] is another temporary register. */
2863 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2865 int align = INTVAL (operands[5]);
2866 unsigned long n_bytes = INTVAL (operands[4]);
2868 /* We can't move more than a word at a time because the PA
2869 has no longer integer move insns. (Could use fp mem ops?) */
2870 if (align > (TARGET_64BIT ? 8 : 4))
2871 align = (TARGET_64BIT ? 8 : 4);
2873 /* Note that we know each loop below will execute at least twice
2874 (else we would have open-coded the copy). */
2878 /* Pre-adjust the loop counter. */
2879 operands[4] = GEN_INT (n_bytes - 16);
2880 output_asm_insn ("ldi %4,%2", operands);
2883 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2884 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2885 output_asm_insn ("std,ma %3,8(%0)", operands);
2886 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2887 output_asm_insn ("std,ma %6,8(%0)", operands);
2889 /* Handle the residual. There could be up to 7 bytes of
2890 residual to copy! */
2891 if (n_bytes % 16 != 0)
2893 operands[4] = GEN_INT (n_bytes % 8);
2894 if (n_bytes % 16 >= 8)
2895 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2896 if (n_bytes % 8 != 0)
2897 output_asm_insn ("ldd 0(%1),%6", operands);
2898 if (n_bytes % 16 >= 8)
2899 output_asm_insn ("std,ma %3,8(%0)", operands);
2900 if (n_bytes % 8 != 0)
2901 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2906 /* Pre-adjust the loop counter. */
2907 operands[4] = GEN_INT (n_bytes - 8);
2908 output_asm_insn ("ldi %4,%2", operands);
2911 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2912 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2913 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2914 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2915 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2917 /* Handle the residual. There could be up to 7 bytes of
2918 residual to copy! */
2919 if (n_bytes % 8 != 0)
2921 operands[4] = GEN_INT (n_bytes % 4);
2922 if (n_bytes % 8 >= 4)
2923 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2924 if (n_bytes % 4 != 0)
2925 output_asm_insn ("ldw 0(%1),%6", operands);
2926 if (n_bytes % 8 >= 4)
2927 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2928 if (n_bytes % 4 != 0)
2929 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2934 /* Pre-adjust the loop counter. */
2935 operands[4] = GEN_INT (n_bytes - 4);
2936 output_asm_insn ("ldi %4,%2", operands);
2939 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2940 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2941 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2942 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2943 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2945 /* Handle the residual. */
2946 if (n_bytes % 4 != 0)
2948 if (n_bytes % 4 >= 2)
2949 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2950 if (n_bytes % 2 != 0)
2951 output_asm_insn ("ldb 0(%1),%6", operands);
2952 if (n_bytes % 4 >= 2)
2953 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2954 if (n_bytes % 2 != 0)
2955 output_asm_insn ("stb %6,0(%0)", operands);
2960 /* Pre-adjust the loop counter. */
2961 operands[4] = GEN_INT (n_bytes - 2);
2962 output_asm_insn ("ldi %4,%2", operands);
2965 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2966 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2967 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2968 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2969 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2971 /* Handle the residual. */
2972 if (n_bytes % 2 != 0)
2974 output_asm_insn ("ldb 0(%1),%3", operands);
2975 output_asm_insn ("stb %3,0(%0)", operands);
2984 /* Count the number of insns necessary to handle this block move.
2986 Basic structure is the same as emit_block_move, except that we
2987 count insns rather than emit them. */
2990 compute_movmem_length (rtx insn)
2992 rtx pat = PATTERN (insn);
2993 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2994 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2995 unsigned int n_insns = 0;
2997 /* We can't move more than four bytes at a time because the PA
2998 has no longer integer move insns. (Could use fp mem ops?) */
2999 if (align > (TARGET_64BIT ? 8 : 4))
3000 align = (TARGET_64BIT ? 8 : 4);
3002 /* The basic copying loop. */
3006 if (n_bytes % (2 * align) != 0)
3008 if ((n_bytes % (2 * align)) >= align)
3011 if ((n_bytes % align) != 0)
3015 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3019 /* Emit code to perform a block clear.
3021 OPERANDS[0] is the destination pointer as a REG, clobbered.
3022 OPERANDS[1] is a register for temporary storage.
3023 OPERANDS[2] is the size as a CONST_INT
3024 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
3027 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
3029 int align = INTVAL (operands[3]);
3030 unsigned long n_bytes = INTVAL (operands[2]);
3032 /* We can't clear more than a word at a time because the PA
3033 has no longer integer move insns. */
3034 if (align > (TARGET_64BIT ? 8 : 4))
3035 align = (TARGET_64BIT ? 8 : 4);
3037 /* Note that we know each loop below will execute at least twice
3038 (else we would have open-coded the copy). */
3042 /* Pre-adjust the loop counter. */
3043 operands[2] = GEN_INT (n_bytes - 16);
3044 output_asm_insn ("ldi %2,%1", operands);
3047 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3048 output_asm_insn ("addib,>= -16,%1,.-4", operands);
3049 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3051 /* Handle the residual. There could be up to 7 bytes of
3052 residual to copy! */
3053 if (n_bytes % 16 != 0)
3055 operands[2] = GEN_INT (n_bytes % 8);
3056 if (n_bytes % 16 >= 8)
3057 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3058 if (n_bytes % 8 != 0)
3059 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
3064 /* Pre-adjust the loop counter. */
3065 operands[2] = GEN_INT (n_bytes - 8);
3066 output_asm_insn ("ldi %2,%1", operands);
3069 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3070 output_asm_insn ("addib,>= -8,%1,.-4", operands);
3071 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3073 /* Handle the residual. There could be up to 7 bytes of
3074 residual to copy! */
3075 if (n_bytes % 8 != 0)
3077 operands[2] = GEN_INT (n_bytes % 4);
3078 if (n_bytes % 8 >= 4)
3079 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3080 if (n_bytes % 4 != 0)
3081 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
3086 /* Pre-adjust the loop counter. */
3087 operands[2] = GEN_INT (n_bytes - 4);
3088 output_asm_insn ("ldi %2,%1", operands);
3091 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3092 output_asm_insn ("addib,>= -4,%1,.-4", operands);
3093 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3095 /* Handle the residual. */
3096 if (n_bytes % 4 != 0)
3098 if (n_bytes % 4 >= 2)
3099 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3100 if (n_bytes % 2 != 0)
3101 output_asm_insn ("stb %%r0,0(%0)", operands);
3106 /* Pre-adjust the loop counter. */
3107 operands[2] = GEN_INT (n_bytes - 2);
3108 output_asm_insn ("ldi %2,%1", operands);
3111 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3112 output_asm_insn ("addib,>= -2,%1,.-4", operands);
3113 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3115 /* Handle the residual. */
3116 if (n_bytes % 2 != 0)
3117 output_asm_insn ("stb %%r0,0(%0)", operands);
3126 /* Count the number of insns necessary to handle this block move.
3128 Basic structure is the same as emit_block_move, except that we
3129 count insns rather than emit them. */
3132 compute_clrmem_length (rtx insn)
3134 rtx pat = PATTERN (insn);
3135 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
3136 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
3137 unsigned int n_insns = 0;
3139 /* We can't clear more than a word at a time because the PA
3140 has no longer integer move insns. */
3141 if (align > (TARGET_64BIT ? 8 : 4))
3142 align = (TARGET_64BIT ? 8 : 4);
3144 /* The basic loop. */
3148 if (n_bytes % (2 * align) != 0)
3150 if ((n_bytes % (2 * align)) >= align)
3153 if ((n_bytes % align) != 0)
3157 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3163 output_and (rtx *operands)
3165 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3167 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3168 int ls0, ls1, ms0, p, len;
3170 for (ls0 = 0; ls0 < 32; ls0++)
3171 if ((mask & (1 << ls0)) == 0)
3174 for (ls1 = ls0; ls1 < 32; ls1++)
3175 if ((mask & (1 << ls1)) != 0)
3178 for (ms0 = ls1; ms0 < 32; ms0++)
3179 if ((mask & (1 << ms0)) == 0)
3192 operands[2] = GEN_INT (len);
3193 return "{extru|extrw,u} %1,31,%2,%0";
3197 /* We could use this `depi' for the case above as well, but `depi'
3198 requires one more register file access than an `extru'. */
3203 operands[2] = GEN_INT (p);
3204 operands[3] = GEN_INT (len);
3205 return "{depi|depwi} 0,%2,%3,%0";
3209 return "and %1,%2,%0";
3212 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3213 storing the result in operands[0]. */
3215 output_64bit_and (rtx *operands)
3217 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3219 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3220 int ls0, ls1, ms0, p, len;
3222 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3223 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3226 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3227 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3230 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3231 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3234 if (ms0 != HOST_BITS_PER_WIDE_INT)
3237 if (ls1 == HOST_BITS_PER_WIDE_INT)
3244 operands[2] = GEN_INT (len);
3245 return "extrd,u %1,63,%2,%0";
3249 /* We could use this `depi' for the case above as well, but `depi'
3250 requires one more register file access than an `extru'. */
3255 operands[2] = GEN_INT (p);
3256 operands[3] = GEN_INT (len);
3257 return "depdi 0,%2,%3,%0";
3261 return "and %1,%2,%0";
3265 output_ior (rtx *operands)
3267 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3268 int bs0, bs1, p, len;
3270 if (INTVAL (operands[2]) == 0)
3271 return "copy %1,%0";
3273 for (bs0 = 0; bs0 < 32; bs0++)
3274 if ((mask & (1 << bs0)) != 0)
3277 for (bs1 = bs0; bs1 < 32; bs1++)
3278 if ((mask & (1 << bs1)) == 0)
3281 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3287 operands[2] = GEN_INT (p);
3288 operands[3] = GEN_INT (len);
3289 return "{depi|depwi} -1,%2,%3,%0";
3292 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3293 storing the result in operands[0]. */
3295 output_64bit_ior (rtx *operands)
3297 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3298 int bs0, bs1, p, len;
3300 if (INTVAL (operands[2]) == 0)
3301 return "copy %1,%0";
3303 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3304 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3307 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3308 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3311 if (bs1 != HOST_BITS_PER_WIDE_INT
3312 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3318 operands[2] = GEN_INT (p);
3319 operands[3] = GEN_INT (len);
3320 return "depdi -1,%2,%3,%0";
3323 /* Target hook for assembling integer objects. This code handles
3324 aligned SI and DI integers specially since function references
3325 must be preceded by P%. */
3328 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3330 if (size == UNITS_PER_WORD
3332 && function_label_operand (x, VOIDmode))
3334 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3335 output_addr_const (asm_out_file, x);
3336 fputc ('\n', asm_out_file);
3339 return default_assemble_integer (x, size, aligned_p);
3342 /* Output an ascii string. */
3344 output_ascii (FILE *file, const char *p, int size)
3348 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3350 /* The HP assembler can only take strings of 256 characters at one
3351 time. This is a limitation on input line length, *not* the
3352 length of the string. Sigh. Even worse, it seems that the
3353 restriction is in number of input characters (see \xnn &
3354 \whatever). So we have to do this very carefully. */
3356 fputs ("\t.STRING \"", file);
3359 for (i = 0; i < size; i += 4)
3363 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3365 register unsigned int c = (unsigned char) p[i + io];
3367 if (c == '\"' || c == '\\')
3368 partial_output[co++] = '\\';
3369 if (c >= ' ' && c < 0177)
3370 partial_output[co++] = c;
3374 partial_output[co++] = '\\';
3375 partial_output[co++] = 'x';
3376 hexd = c / 16 - 0 + '0';
3378 hexd -= '9' - 'a' + 1;
3379 partial_output[co++] = hexd;
3380 hexd = c % 16 - 0 + '0';
3382 hexd -= '9' - 'a' + 1;
3383 partial_output[co++] = hexd;
3386 if (chars_output + co > 243)
3388 fputs ("\"\n\t.STRING \"", file);
3391 fwrite (partial_output, 1, (size_t) co, file);
3395 fputs ("\"\n", file);
3398 /* Try to rewrite floating point comparisons & branches to avoid
3399 useless add,tr insns.
3401 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3402 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3403 first attempt to remove useless add,tr insns. It is zero
3404 for the second pass as reorg sometimes leaves bogus REG_DEAD
3407 When CHECK_NOTES is zero we can only eliminate add,tr insns
3408 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3411 remove_useless_addtr_insns (int check_notes)
3414 static int pass = 0;
3416 /* This is fairly cheap, so always run it when optimizing. */
3420 int fbranch_count = 0;
3422 /* Walk all the insns in this function looking for fcmp & fbranch
3423 instructions. Keep track of how many of each we find. */
3424 for (insn = get_insns (); insn; insn = next_insn (insn))
3428 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3429 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3432 tmp = PATTERN (insn);
3434 /* It must be a set. */
3435 if (GET_CODE (tmp) != SET)
3438 /* If the destination is CCFP, then we've found an fcmp insn. */
3439 tmp = SET_DEST (tmp);
3440 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3446 tmp = PATTERN (insn);
3447 /* If this is an fbranch instruction, bump the fbranch counter. */
3448 if (GET_CODE (tmp) == SET
3449 && SET_DEST (tmp) == pc_rtx
3450 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3451 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3452 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3453 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3461 /* Find all floating point compare + branch insns. If possible,
3462 reverse the comparison & the branch to avoid add,tr insns. */
3463 for (insn = get_insns (); insn; insn = next_insn (insn))
3467 /* Ignore anything that isn't an INSN. */
3468 if (GET_CODE (insn) != INSN)
3471 tmp = PATTERN (insn);
3473 /* It must be a set. */
3474 if (GET_CODE (tmp) != SET)
3477 /* The destination must be CCFP, which is register zero. */
3478 tmp = SET_DEST (tmp);
3479 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3482 /* INSN should be a set of CCFP.
3484 See if the result of this insn is used in a reversed FP
3485 conditional branch. If so, reverse our condition and
3486 the branch. Doing so avoids useless add,tr insns. */
3487 next = next_insn (insn);
3490 /* Jumps, calls and labels stop our search. */
3491 if (GET_CODE (next) == JUMP_INSN
3492 || GET_CODE (next) == CALL_INSN
3493 || GET_CODE (next) == CODE_LABEL)
3496 /* As does another fcmp insn. */
3497 if (GET_CODE (next) == INSN
3498 && GET_CODE (PATTERN (next)) == SET
3499 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3500 && REGNO (SET_DEST (PATTERN (next))) == 0)
3503 next = next_insn (next);
3506 /* Is NEXT_INSN a branch? */
3508 && GET_CODE (next) == JUMP_INSN)
3510 rtx pattern = PATTERN (next);
3512 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3513 and CCFP dies, then reverse our conditional and the branch
3514 to avoid the add,tr. */
3515 if (GET_CODE (pattern) == SET
3516 && SET_DEST (pattern) == pc_rtx
3517 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3518 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3519 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3520 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3521 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3522 && (fcmp_count == fbranch_count
3524 && find_regno_note (next, REG_DEAD, 0))))
3526 /* Reverse the branch. */
3527 tmp = XEXP (SET_SRC (pattern), 1);
3528 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3529 XEXP (SET_SRC (pattern), 2) = tmp;
3530 INSN_CODE (next) = -1;
3532 /* Reverse our condition. */
3533 tmp = PATTERN (insn);
3534 PUT_CODE (XEXP (tmp, 1),
3535 (reverse_condition_maybe_unordered
3536 (GET_CODE (XEXP (tmp, 1)))));
3546 /* You may have trouble believing this, but this is the 32 bit HP-PA
3551 Variable arguments (optional; any number may be allocated)
3553 SP-(4*(N+9)) arg word N
3558 Fixed arguments (must be allocated; may remain unused)
3567 SP-32 External Data Pointer (DP)
3569 SP-24 External/stub RP (RP')
3573 SP-8 Calling Stub RP (RP'')
3578 SP-0 Stack Pointer (points to next available address)
3582 /* This function saves registers as follows. Registers marked with ' are
3583 this function's registers (as opposed to the previous function's).
3584 If a frame_pointer isn't needed, r4 is saved as a general register;
3585 the space for the frame pointer is still allocated, though, to keep
3591 SP (FP') Previous FP
3592 SP + 4 Alignment filler (sigh)
3593 SP + 8 Space for locals reserved here.
3597 SP + n All call saved register used.
3601 SP + o All call saved fp registers used.
3605 SP + p (SP') points to next available address.
3609 /* Global variables set by output_function_prologue(). */
3610 /* Size of frame. Need to know this to emit return insns from
3612 static HOST_WIDE_INT actual_fsize, local_fsize;
3613 static int save_fregs;
3615 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3616 Handle case where DISP > 8k by using the add_high_const patterns.
3618 Note in DISP > 8k case, we will leave the high part of the address
3619 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3622 store_reg (int reg, HOST_WIDE_INT disp, int base)
3624 rtx insn, dest, src, basereg;
3626 src = gen_rtx_REG (word_mode, reg);
3627 basereg = gen_rtx_REG (Pmode, base);
3628 if (VAL_14_BITS_P (disp))
3630 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3631 insn = emit_move_insn (dest, src);
3633 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3635 rtx delta = GEN_INT (disp);
3636 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3638 emit_move_insn (tmpreg, delta);
3639 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3640 dest = gen_rtx_MEM (word_mode, tmpreg);
3641 insn = emit_move_insn (dest, src);
3645 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3646 gen_rtx_SET (VOIDmode,
3647 gen_rtx_MEM (word_mode,
3648 gen_rtx_PLUS (word_mode, basereg,
3656 rtx delta = GEN_INT (disp);
3657 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3658 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3660 emit_move_insn (tmpreg, high);
3661 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3662 insn = emit_move_insn (dest, src);
3666 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3667 gen_rtx_SET (VOIDmode,
3668 gen_rtx_MEM (word_mode,
3669 gen_rtx_PLUS (word_mode, basereg,
3677 RTX_FRAME_RELATED_P (insn) = 1;
3680 /* Emit RTL to store REG at the memory location specified by BASE and then
3681 add MOD to BASE. MOD must be <= 8k. */
3684 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3686 rtx insn, basereg, srcreg, delta;
3688 if (!VAL_14_BITS_P (mod))
3691 basereg = gen_rtx_REG (Pmode, base);
3692 srcreg = gen_rtx_REG (word_mode, reg);
3693 delta = GEN_INT (mod);
3695 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3698 RTX_FRAME_RELATED_P (insn) = 1;
3700 /* RTX_FRAME_RELATED_P must be set on each frame related set
3701 in a parallel with more than one element. Don't set
3702 RTX_FRAME_RELATED_P in the first set if reg is temporary
3703 register 1. The effect of this operation is recorded in
3704 the initial copy. */
3707 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3708 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3712 /* The first element of a PARALLEL is always processed if it is
3713 a SET. Thus, we need an expression list for this case. */
3715 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3716 gen_rtx_SET (VOIDmode, basereg,
3717 gen_rtx_PLUS (word_mode, basereg, delta)),
3723 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3724 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3725 whether to add a frame note or not.
3727 In the DISP > 8k case, we leave the high part of the address in %r1.
3728 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3731 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3735 if (VAL_14_BITS_P (disp))
3737 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3738 plus_constant (gen_rtx_REG (Pmode, base), disp));
3740 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3742 rtx basereg = gen_rtx_REG (Pmode, base);
3743 rtx delta = GEN_INT (disp);
3744 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3746 emit_move_insn (tmpreg, delta);
3747 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3748 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3752 rtx basereg = gen_rtx_REG (Pmode, base);
3753 rtx delta = GEN_INT (disp);
3754 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3756 emit_move_insn (tmpreg,
3757 gen_rtx_PLUS (Pmode, basereg,
3758 gen_rtx_HIGH (Pmode, delta)));
3759 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3760 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3763 if (DO_FRAME_NOTES && note)
3764 RTX_FRAME_RELATED_P (insn) = 1;
3768 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3773 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3774 be consistent with the rounding and size calculation done here.
3775 Change them at the same time. */
3777 /* We do our own stack alignment. First, round the size of the
3778 stack locals up to a word boundary. */
3779 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3781 /* Space for previous frame pointer + filler. If any frame is
3782 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3783 waste some space here for the sake of HP compatibility. The
3784 first slot is only used when the frame pointer is needed. */
3785 if (size || frame_pointer_needed)
3786 size += STARTING_FRAME_OFFSET;
3788 /* If the current function calls __builtin_eh_return, then we need
3789 to allocate stack space for registers that will hold data for
3790 the exception handler. */
3791 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3795 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3797 size += i * UNITS_PER_WORD;
3800 /* Account for space used by the callee general register saves. */
3801 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3802 if (regs_ever_live[i])
3803 size += UNITS_PER_WORD;
3805 /* Account for space used by the callee floating point register saves. */
3806 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3807 if (regs_ever_live[i]
3808 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3812 /* We always save both halves of the FP register, so always
3813 increment the frame size by 8 bytes. */
3817 /* If any of the floating registers are saved, account for the
3818 alignment needed for the floating point register save block. */
3821 size = (size + 7) & ~7;
3826 /* The various ABIs include space for the outgoing parameters in the
3827 size of the current function's stack frame. We don't need to align
3828 for the outgoing arguments as their alignment is set by the final
3829 rounding for the frame as a whole. */
3830 size += current_function_outgoing_args_size;
3832 /* Allocate space for the fixed frame marker. This space must be
3833 allocated for any function that makes calls or allocates
3835 if (!current_function_is_leaf || size)
3836 size += TARGET_64BIT ? 48 : 32;
3838 /* Finally, round to the preferred stack boundary. */
3839 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3840 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3843 /* Generate the assembly code for function entry. FILE is a stdio
3844 stream to output the code to. SIZE is an int: how many units of
3845 temporary storage to allocate.
3847 Refer to the array `regs_ever_live' to determine which registers to
3848 save; `regs_ever_live[I]' is nonzero if register number I is ever
3849 used in the function. This function is responsible for knowing
3850 which registers should not be saved even if used. */
3852 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3853 of memory. If any fpu reg is used in the function, we allocate
3854 such a block here, at the bottom of the frame, just in case it's needed.
3856 If this function is a leaf procedure, then we may choose not
3857 to do a "save" insn. The decision about whether or not
3858 to do this is made in regclass.c. */
3861 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3863 /* The function's label and associated .PROC must never be
3864 separated and must be output *after* any profiling declarations
3865 to avoid changing spaces/subspaces within a procedure. */
3866 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3867 fputs ("\t.PROC\n", file);
3869 /* hppa_expand_prologue does the dirty work now. We just need
3870 to output the assembler directives which denote the start
3872 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3873 if (regs_ever_live[2])
3874 fputs (",CALLS,SAVE_RP", file);
3876 fputs (",NO_CALLS", file);
3878 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3879 at the beginning of the frame and that it is used as the frame
3880 pointer for the frame. We do this because our current frame
3881 layout doesn't conform to that specified in the the HP runtime
3882 documentation and we need a way to indicate to programs such as
3883 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3884 isn't used by HP compilers but is supported by the assembler.
3885 However, SAVE_SP is supposed to indicate that the previous stack
3886 pointer has been saved in the frame marker. */
3887 if (frame_pointer_needed)
3888 fputs (",SAVE_SP", file);
3890 /* Pass on information about the number of callee register saves
3891 performed in the prologue.
3893 The compiler is supposed to pass the highest register number
3894 saved, the assembler then has to adjust that number before
3895 entering it into the unwind descriptor (to account for any
3896 caller saved registers with lower register numbers than the
3897 first callee saved register). */
3899 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3902 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3904 fputs ("\n\t.ENTRY\n", file);
3906 remove_useless_addtr_insns (0);
3910 hppa_expand_prologue (void)
3912 int merge_sp_adjust_with_store = 0;
3913 HOST_WIDE_INT size = get_frame_size ();
3914 HOST_WIDE_INT offset;
3922 /* Compute total size for frame pointer, filler, locals and rounding to
3923 the next word boundary. Similar code appears in compute_frame_size
3924 and must be changed in tandem with this code. */
3925 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3926 if (local_fsize || frame_pointer_needed)
3927 local_fsize += STARTING_FRAME_OFFSET;
3929 actual_fsize = compute_frame_size (size, &save_fregs);
3931 /* Compute a few things we will use often. */
3932 tmpreg = gen_rtx_REG (word_mode, 1);
3934 /* Save RP first. The calling conventions manual states RP will
3935 always be stored into the caller's frame at sp - 20 or sp - 16
3936 depending on which ABI is in use. */
3937 if (regs_ever_live[2] || current_function_calls_eh_return)
3938 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3940 /* Allocate the local frame and set up the frame pointer if needed. */
3941 if (actual_fsize != 0)
3943 if (frame_pointer_needed)
3945 /* Copy the old frame pointer temporarily into %r1. Set up the
3946 new stack pointer, then store away the saved old frame pointer
3947 into the stack at sp and at the same time update the stack
3948 pointer by actual_fsize bytes. Two versions, first
3949 handles small (<8k) frames. The second handles large (>=8k)
3951 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3954 /* We need to record the frame pointer save here since the
3955 new frame pointer is set in the following insn. */
3956 RTX_FRAME_RELATED_P (insn) = 1;
3958 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3959 gen_rtx_SET (VOIDmode,
3960 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3965 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3967 RTX_FRAME_RELATED_P (insn) = 1;
3969 if (VAL_14_BITS_P (actual_fsize))
3970 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3973 /* It is incorrect to store the saved frame pointer at *sp,
3974 then increment sp (writes beyond the current stack boundary).
3976 So instead use stwm to store at *sp and post-increment the
3977 stack pointer as an atomic operation. Then increment sp to
3978 finish allocating the new frame. */
3979 HOST_WIDE_INT adjust1 = 8192 - 64;
3980 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3982 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3983 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3987 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3988 we need to store the previous stack pointer (frame pointer)
3989 into the frame marker on targets that use the HP unwind
3990 library. This allows the HP unwind library to be used to
3991 unwind GCC frames. However, we are not fully compatible
3992 with the HP library because our frame layout differs from
3993 that specified in the HP runtime specification.
3995 We don't want a frame note on this instruction as the frame
3996 marker moves during dynamic stack allocation.
3998 This instruction also serves as a blockage to prevent
3999 register spills from being scheduled before the stack
4000 pointer is raised. This is necessary as we store
4001 registers using the frame pointer as a base register,
4002 and the frame pointer is set before sp is raised. */
4003 if (TARGET_HPUX_UNWIND_LIBRARY)
4005 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
4006 GEN_INT (TARGET_64BIT ? -8 : -4));
4008 emit_move_insn (gen_rtx_MEM (word_mode, addr),
4012 emit_insn (gen_blockage ());
4014 /* no frame pointer needed. */
4017 /* In some cases we can perform the first callee register save
4018 and allocating the stack frame at the same time. If so, just
4019 make a note of it and defer allocating the frame until saving
4020 the callee registers. */
4021 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
4022 merge_sp_adjust_with_store = 1;
4023 /* Can not optimize. Adjust the stack frame by actual_fsize
4026 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4031 /* Normal register save.
4033 Do not save the frame pointer in the frame_pointer_needed case. It
4034 was done earlier. */
4035 if (frame_pointer_needed)
4037 offset = local_fsize;
4039 /* Saving the EH return data registers in the frame is the simplest
4040 way to get the frame unwind information emitted. We put them
4041 just before the general registers. */
4042 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4044 unsigned int i, regno;
4048 regno = EH_RETURN_DATA_REGNO (i);
4049 if (regno == INVALID_REGNUM)
4052 store_reg (regno, offset, FRAME_POINTER_REGNUM);
4053 offset += UNITS_PER_WORD;
4057 for (i = 18; i >= 4; i--)
4058 if (regs_ever_live[i] && ! call_used_regs[i])
4060 store_reg (i, offset, FRAME_POINTER_REGNUM);
4061 offset += UNITS_PER_WORD;
4064 /* Account for %r3 which is saved in a special place. */
4067 /* No frame pointer needed. */
4070 offset = local_fsize - actual_fsize;
4072 /* Saving the EH return data registers in the frame is the simplest
4073 way to get the frame unwind information emitted. */
4074 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4076 unsigned int i, regno;
4080 regno = EH_RETURN_DATA_REGNO (i);
4081 if (regno == INVALID_REGNUM)
4084 /* If merge_sp_adjust_with_store is nonzero, then we can
4085 optimize the first save. */
4086 if (merge_sp_adjust_with_store)
4088 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
4089 merge_sp_adjust_with_store = 0;
4092 store_reg (regno, offset, STACK_POINTER_REGNUM);
4093 offset += UNITS_PER_WORD;
4097 for (i = 18; i >= 3; i--)
4098 if (regs_ever_live[i] && ! call_used_regs[i])
4100 /* If merge_sp_adjust_with_store is nonzero, then we can
4101 optimize the first GR save. */
4102 if (merge_sp_adjust_with_store)
4104 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
4105 merge_sp_adjust_with_store = 0;
4108 store_reg (i, offset, STACK_POINTER_REGNUM);
4109 offset += UNITS_PER_WORD;
4113 /* If we wanted to merge the SP adjustment with a GR save, but we never
4114 did any GR saves, then just emit the adjustment here. */
4115 if (merge_sp_adjust_with_store)
4116 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4120 /* The hppa calling conventions say that %r19, the pic offset
4121 register, is saved at sp - 32 (in this function's frame)
4122 when generating PIC code. FIXME: What is the correct thing
4123 to do for functions which make no calls and allocate no
4124 frame? Do we need to allocate a frame, or can we just omit
4125 the save? For now we'll just omit the save.
4127 We don't want a note on this insn as the frame marker can
4128 move if there is a dynamic stack allocation. */
4129 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
4131 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
4133 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
4137 /* Align pointer properly (doubleword boundary). */
4138 offset = (offset + 7) & ~7;
4140 /* Floating point register store. */
4145 /* First get the frame or stack pointer to the start of the FP register
4147 if (frame_pointer_needed)
4149 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4150 base = frame_pointer_rtx;
4154 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4155 base = stack_pointer_rtx;
4158 /* Now actually save the FP registers. */
4159 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4161 if (regs_ever_live[i]
4162 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4164 rtx addr, insn, reg;
4165 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4166 reg = gen_rtx_REG (DFmode, i);
4167 insn = emit_move_insn (addr, reg);
4170 RTX_FRAME_RELATED_P (insn) = 1;
4173 rtx mem = gen_rtx_MEM (DFmode,
4174 plus_constant (base, offset));
4176 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4177 gen_rtx_SET (VOIDmode, mem, reg),
4182 rtx meml = gen_rtx_MEM (SFmode,
4183 plus_constant (base, offset));
4184 rtx memr = gen_rtx_MEM (SFmode,
4185 plus_constant (base, offset + 4));
4186 rtx regl = gen_rtx_REG (SFmode, i);
4187 rtx regr = gen_rtx_REG (SFmode, i + 1);
4188 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4189 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4192 RTX_FRAME_RELATED_P (setl) = 1;
4193 RTX_FRAME_RELATED_P (setr) = 1;
4194 vec = gen_rtvec (2, setl, setr);
4196 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4197 gen_rtx_SEQUENCE (VOIDmode, vec),
4201 offset += GET_MODE_SIZE (DFmode);
4208 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4209 Handle case where DISP > 8k by using the add_high_const patterns. */
4212 load_reg (int reg, HOST_WIDE_INT disp, int base)
4214 rtx dest = gen_rtx_REG (word_mode, reg);
4215 rtx basereg = gen_rtx_REG (Pmode, base);
4218 if (VAL_14_BITS_P (disp))
4219 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4220 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4222 rtx delta = GEN_INT (disp);
4223 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4225 emit_move_insn (tmpreg, delta);
4226 if (TARGET_DISABLE_INDEXING)
4228 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4229 src = gen_rtx_MEM (word_mode, tmpreg);
4232 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4236 rtx delta = GEN_INT (disp);
4237 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4238 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4240 emit_move_insn (tmpreg, high);
4241 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4244 emit_move_insn (dest, src);
4247 /* Update the total code bytes output to the text section. */
4250 update_total_code_bytes (int nbytes)
4252 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4253 && !IN_NAMED_SECTION_P (cfun->decl))
4255 if (INSN_ADDRESSES_SET_P ())
4257 unsigned long old_total = total_code_bytes;
4259 total_code_bytes += nbytes;
4261 /* Be prepared to handle overflows. */
4262 if (old_total > total_code_bytes)
4263 total_code_bytes = -1;
4266 total_code_bytes = -1;
4270 /* This function generates the assembly code for function exit.
4271 Args are as for output_function_prologue ().
4273 The function epilogue should not depend on the current stack
4274 pointer! It should use the frame pointer only. This is mandatory
4275 because of alloca; we also take advantage of it to omit stack
4276 adjustments before returning. */
4279 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4281 rtx insn = get_last_insn ();
4285 /* hppa_expand_epilogue does the dirty work now. We just need
4286 to output the assembler directives which denote the end
4289 To make debuggers happy, emit a nop if the epilogue was completely
4290 eliminated due to a volatile call as the last insn in the
4291 current function. That way the return address (in %r2) will
4292 always point to a valid instruction in the current function. */
4294 /* Get the last real insn. */
4295 if (GET_CODE (insn) == NOTE)
4296 insn = prev_real_insn (insn);
4298 /* If it is a sequence, then look inside. */
4299 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4300 insn = XVECEXP (PATTERN (insn), 0, 0);
4302 /* If insn is a CALL_INSN, then it must be a call to a volatile
4303 function (otherwise there would be epilogue insns). */
4304 if (insn && GET_CODE (insn) == CALL_INSN)
4306 fputs ("\tnop\n", file);
4310 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4312 if (TARGET_SOM && TARGET_GAS)
4314 /* We done with this subspace except possibly for some additional
4315 debug information. Forget that we are in this subspace to ensure
4316 that the next function is output in its own subspace. */
4320 if (INSN_ADDRESSES_SET_P ())
4322 insn = get_last_nonnote_insn ();
4323 last_address += INSN_ADDRESSES (INSN_UID (insn));
4325 last_address += insn_default_length (insn);
4326 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4327 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4330 /* Finally, update the total number of code bytes output so far. */
4331 update_total_code_bytes (last_address);
4335 hppa_expand_epilogue (void)
4338 HOST_WIDE_INT offset;
4339 HOST_WIDE_INT ret_off = 0;
4341 int merge_sp_adjust_with_load = 0;
4343 /* We will use this often. */
4344 tmpreg = gen_rtx_REG (word_mode, 1);
4346 /* Try to restore RP early to avoid load/use interlocks when
4347 RP gets used in the return (bv) instruction. This appears to still
4348 be necessary even when we schedule the prologue and epilogue. */
4349 if (regs_ever_live [2] || current_function_calls_eh_return)
4351 ret_off = TARGET_64BIT ? -16 : -20;
4352 if (frame_pointer_needed)
4354 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4359 /* No frame pointer, and stack is smaller than 8k. */
4360 if (VAL_14_BITS_P (ret_off - actual_fsize))
4362 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4368 /* General register restores. */
4369 if (frame_pointer_needed)
4371 offset = local_fsize;
4373 /* If the current function calls __builtin_eh_return, then we need
4374 to restore the saved EH data registers. */
4375 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4377 unsigned int i, regno;
4381 regno = EH_RETURN_DATA_REGNO (i);
4382 if (regno == INVALID_REGNUM)
4385 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4386 offset += UNITS_PER_WORD;
4390 for (i = 18; i >= 4; i--)
4391 if (regs_ever_live[i] && ! call_used_regs[i])
4393 load_reg (i, offset, FRAME_POINTER_REGNUM);
4394 offset += UNITS_PER_WORD;
4399 offset = local_fsize - actual_fsize;
4401 /* If the current function calls __builtin_eh_return, then we need
4402 to restore the saved EH data registers. */
4403 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4405 unsigned int i, regno;
4409 regno = EH_RETURN_DATA_REGNO (i);
4410 if (regno == INVALID_REGNUM)
4413 /* Only for the first load.
4414 merge_sp_adjust_with_load holds the register load
4415 with which we will merge the sp adjustment. */
4416 if (merge_sp_adjust_with_load == 0
4418 && VAL_14_BITS_P (-actual_fsize))
4419 merge_sp_adjust_with_load = regno;
4421 load_reg (regno, offset, STACK_POINTER_REGNUM);
4422 offset += UNITS_PER_WORD;
4426 for (i = 18; i >= 3; i--)
4428 if (regs_ever_live[i] && ! call_used_regs[i])
4430 /* Only for the first load.
4431 merge_sp_adjust_with_load holds the register load
4432 with which we will merge the sp adjustment. */
4433 if (merge_sp_adjust_with_load == 0
4435 && VAL_14_BITS_P (-actual_fsize))
4436 merge_sp_adjust_with_load = i;
4438 load_reg (i, offset, STACK_POINTER_REGNUM);
4439 offset += UNITS_PER_WORD;
4444 /* Align pointer properly (doubleword boundary). */
4445 offset = (offset + 7) & ~7;
4447 /* FP register restores. */
4450 /* Adjust the register to index off of. */
4451 if (frame_pointer_needed)
4452 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4454 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4456 /* Actually do the restores now. */
4457 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4458 if (regs_ever_live[i]
4459 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4461 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4462 rtx dest = gen_rtx_REG (DFmode, i);
4463 emit_move_insn (dest, src);
4467 /* Emit a blockage insn here to keep these insns from being moved to
4468 an earlier spot in the epilogue, or into the main instruction stream.
4470 This is necessary as we must not cut the stack back before all the
4471 restores are finished. */
4472 emit_insn (gen_blockage ());
4474 /* Reset stack pointer (and possibly frame pointer). The stack
4475 pointer is initially set to fp + 64 to avoid a race condition. */
4476 if (frame_pointer_needed)
4478 rtx delta = GEN_INT (-64);
4480 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4481 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4483 /* If we were deferring a callee register restore, do it now. */
4484 else if (merge_sp_adjust_with_load)
4486 rtx delta = GEN_INT (-actual_fsize);
4487 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4489 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4491 else if (actual_fsize != 0)
4492 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4495 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4496 frame greater than 8k), do so now. */
4498 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4500 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4502 rtx sa = EH_RETURN_STACKADJ_RTX;
4504 emit_insn (gen_blockage ());
4505 emit_insn (TARGET_64BIT
4506 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4507 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4512 hppa_pic_save_rtx (void)
4514 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4518 hppa_profile_hook (int label_no)
4520 /* We use SImode for the address of the function in both 32 and
4521 64-bit code to avoid having to provide DImode versions of the
4522 lcla2 and load_offset_label_address insn patterns. */
4523 rtx reg = gen_reg_rtx (SImode);
4524 rtx label_rtx = gen_label_rtx ();
4525 rtx begin_label_rtx, call_insn;
4526 char begin_label_name[16];
4528 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4530 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4533 emit_move_insn (arg_pointer_rtx,
4534 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4537 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4539 /* The address of the function is loaded into %r25 with a instruction-
4540 relative sequence that avoids the use of relocations. The sequence
4541 is split so that the load_offset_label_address instruction can
4542 occupy the delay slot of the call to _mcount. */
4544 emit_insn (gen_lcla2 (reg, label_rtx));
4546 emit_insn (gen_lcla1 (reg, label_rtx));
4548 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4549 reg, begin_label_rtx, label_rtx));
4551 #ifndef NO_PROFILE_COUNTERS
4553 rtx count_label_rtx, addr, r24;
4554 char count_label_name[16];
4556 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4557 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4559 addr = force_reg (Pmode, count_label_rtx);
4560 r24 = gen_rtx_REG (Pmode, 24);
4561 emit_move_insn (r24, addr);
4564 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4565 gen_rtx_SYMBOL_REF (Pmode,
4567 GEN_INT (TARGET_64BIT ? 24 : 12)));
4569 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4574 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4575 gen_rtx_SYMBOL_REF (Pmode,
4577 GEN_INT (TARGET_64BIT ? 16 : 8)));
4581 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4582 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4584 /* Indicate the _mcount call cannot throw, nor will it execute a
4586 REG_NOTES (call_insn)
4587 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4590 /* Fetch the return address for the frame COUNT steps up from
4591 the current frame, after the prologue. FRAMEADDR is the
4592 frame pointer of the COUNT frame.
4594 We want to ignore any export stub remnants here. To handle this,
4595 we examine the code at the return address, and if it is an export
4596 stub, we return a memory rtx for the stub return address stored
4599 The value returned is used in two different ways:
4601 1. To find a function's caller.
4603 2. To change the return address for a function.
4605 This function handles most instances of case 1; however, it will
4606 fail if there are two levels of stubs to execute on the return
4607 path. The only way I believe that can happen is if the return value
4608 needs a parameter relocation, which never happens for C code.
4610 This function handles most instances of case 2; however, it will
4611 fail if we did not originally have stub code on the return path
4612 but will need stub code on the new return path. This can happen if
4613 the caller & callee are both in the main program, but the new
4614 return location is in a shared library. */
4617 return_addr_rtx (int count, rtx frameaddr)
4627 rp = get_hard_reg_initial_val (Pmode, 2);
4629 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4632 saved_rp = gen_reg_rtx (Pmode);
4633 emit_move_insn (saved_rp, rp);
4635 /* Get pointer to the instruction stream. We have to mask out the
4636 privilege level from the two low order bits of the return address
4637 pointer here so that ins will point to the start of the first
4638 instruction that would have been executed if we returned. */
4639 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4640 label = gen_label_rtx ();
4642 /* Check the instruction stream at the normal return address for the
4645 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4646 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4647 0x00011820 | stub+16: mtsp r1,sr0
4648 0xe0400002 | stub+20: be,n 0(sr0,rp)
4650 If it is an export stub, than our return address is really in
4653 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4654 NULL_RTX, SImode, 1);
4655 emit_jump_insn (gen_bne (label));
4657 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4658 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4659 emit_jump_insn (gen_bne (label));
4661 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4662 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4663 emit_jump_insn (gen_bne (label));
4665 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4666 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4668 /* If there is no export stub then just use the value saved from
4669 the return pointer register. */
4671 emit_jump_insn (gen_bne (label));
4673 /* Here we know that our return address points to an export
4674 stub. We don't want to return the address of the export stub,
4675 but rather the return address of the export stub. That return
4676 address is stored at -24[frameaddr]. */
4678 emit_move_insn (saved_rp,
4680 memory_address (Pmode,
4681 plus_constant (frameaddr,
4688 /* This is only valid once reload has completed because it depends on
4689 knowing exactly how much (if any) frame there is and...
4691 It's only valid if there is no frame marker to de-allocate and...
4693 It's only valid if %r2 hasn't been saved into the caller's frame
4694 (we're not profiling and %r2 isn't live anywhere). */
4696 hppa_can_use_return_insn_p (void)
4698 return (reload_completed
4699 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4700 && ! regs_ever_live[2]
4701 && ! frame_pointer_needed);
4705 emit_bcond_fp (enum rtx_code code, rtx operand0)
4707 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4708 gen_rtx_IF_THEN_ELSE (VOIDmode,
4709 gen_rtx_fmt_ee (code,
4711 gen_rtx_REG (CCFPmode, 0),
4713 gen_rtx_LABEL_REF (VOIDmode, operand0),
4719 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4721 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4722 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4725 /* Adjust the cost of a scheduling dependency. Return the new cost of
4726 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4729 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4731 enum attr_type attr_type;
4733 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4734 true dependencies as they are described with bypasses now. */
4735 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4738 if (! recog_memoized (insn))
4741 attr_type = get_attr_type (insn);
4743 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4745 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4748 if (attr_type == TYPE_FPLOAD)
4750 rtx pat = PATTERN (insn);
4751 rtx dep_pat = PATTERN (dep_insn);
4752 if (GET_CODE (pat) == PARALLEL)
4754 /* This happens for the fldXs,mb patterns. */
4755 pat = XVECEXP (pat, 0, 0);
4757 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4758 /* If this happens, we have to extend this to schedule
4759 optimally. Return 0 for now. */
4762 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4764 if (! recog_memoized (dep_insn))
4766 switch (get_attr_type (dep_insn))
4773 case TYPE_FPSQRTSGL:
4774 case TYPE_FPSQRTDBL:
4775 /* A fpload can't be issued until one cycle before a
4776 preceding arithmetic operation has finished if
4777 the target of the fpload is any of the sources
4778 (or destination) of the arithmetic operation. */
4779 return insn_default_latency (dep_insn) - 1;
4786 else if (attr_type == TYPE_FPALU)
4788 rtx pat = PATTERN (insn);
4789 rtx dep_pat = PATTERN (dep_insn);
4790 if (GET_CODE (pat) == PARALLEL)
4792 /* This happens for the fldXs,mb patterns. */
4793 pat = XVECEXP (pat, 0, 0);
4795 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4796 /* If this happens, we have to extend this to schedule
4797 optimally. Return 0 for now. */
4800 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4802 if (! recog_memoized (dep_insn))
4804 switch (get_attr_type (dep_insn))
4808 case TYPE_FPSQRTSGL:
4809 case TYPE_FPSQRTDBL:
4810 /* An ALU flop can't be issued until two cycles before a
4811 preceding divide or sqrt operation has finished if
4812 the target of the ALU flop is any of the sources
4813 (or destination) of the divide or sqrt operation. */
4814 return insn_default_latency (dep_insn) - 2;
4822 /* For other anti dependencies, the cost is 0. */
4825 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4827 /* Output dependency; DEP_INSN writes a register that INSN writes some
4829 if (attr_type == TYPE_FPLOAD)
4831 rtx pat = PATTERN (insn);
4832 rtx dep_pat = PATTERN (dep_insn);
4833 if (GET_CODE (pat) == PARALLEL)
4835 /* This happens for the fldXs,mb patterns. */
4836 pat = XVECEXP (pat, 0, 0);
4838 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4839 /* If this happens, we have to extend this to schedule
4840 optimally. Return 0 for now. */
4843 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4845 if (! recog_memoized (dep_insn))
4847 switch (get_attr_type (dep_insn))
4854 case TYPE_FPSQRTSGL:
4855 case TYPE_FPSQRTDBL:
4856 /* A fpload can't be issued until one cycle before a
4857 preceding arithmetic operation has finished if
4858 the target of the fpload is the destination of the
4859 arithmetic operation.
4861 Exception: For PA7100LC, PA7200 and PA7300, the cost
4862 is 3 cycles, unless they bundle together. We also
4863 pay the penalty if the second insn is a fpload. */
4864 return insn_default_latency (dep_insn) - 1;
4871 else if (attr_type == TYPE_FPALU)
4873 rtx pat = PATTERN (insn);
4874 rtx dep_pat = PATTERN (dep_insn);
4875 if (GET_CODE (pat) == PARALLEL)
4877 /* This happens for the fldXs,mb patterns. */
4878 pat = XVECEXP (pat, 0, 0);
4880 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4881 /* If this happens, we have to extend this to schedule
4882 optimally. Return 0 for now. */
4885 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4887 if (! recog_memoized (dep_insn))
4889 switch (get_attr_type (dep_insn))
4893 case TYPE_FPSQRTSGL:
4894 case TYPE_FPSQRTDBL:
4895 /* An ALU flop can't be issued until two cycles before a
4896 preceding divide or sqrt operation has finished if
4897 the target of the ALU flop is also the target of
4898 the divide or sqrt operation. */
4899 return insn_default_latency (dep_insn) - 2;
4907 /* For other output dependencies, the cost is 0. */
4914 /* Adjust scheduling priorities. We use this to try and keep addil
4915 and the next use of %r1 close together. */
4917 pa_adjust_priority (rtx insn, int priority)
4919 rtx set = single_set (insn);
4923 src = SET_SRC (set);
4924 dest = SET_DEST (set);
4925 if (GET_CODE (src) == LO_SUM
4926 && symbolic_operand (XEXP (src, 1), VOIDmode)
4927 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4930 else if (GET_CODE (src) == MEM
4931 && GET_CODE (XEXP (src, 0)) == LO_SUM
4932 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4933 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4936 else if (GET_CODE (dest) == MEM
4937 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4938 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4939 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4945 /* The 700 can only issue a single insn at a time.
4946 The 7XXX processors can issue two insns at a time.
4947 The 8000 can issue 4 insns at a time. */
4949 pa_issue_rate (void)
4953 case PROCESSOR_700: return 1;
4954 case PROCESSOR_7100: return 2;
4955 case PROCESSOR_7100LC: return 2;
4956 case PROCESSOR_7200: return 2;
4957 case PROCESSOR_7300: return 2;
4958 case PROCESSOR_8000: return 4;
4967 /* Return any length adjustment needed by INSN which already has its length
4968 computed as LENGTH. Return zero if no adjustment is necessary.
4970 For the PA: function calls, millicode calls, and backwards short
4971 conditional branches with unfilled delay slots need an adjustment by +1
4972 (to account for the NOP which will be inserted into the instruction stream).
4974 Also compute the length of an inline block move here as it is too
4975 complicated to express as a length attribute in pa.md. */
4977 pa_adjust_insn_length (rtx insn, int length)
4979 rtx pat = PATTERN (insn);
4981 /* Jumps inside switch tables which have unfilled delay slots need
4983 if (GET_CODE (insn) == JUMP_INSN
4984 && GET_CODE (pat) == PARALLEL
4985 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4987 /* Millicode insn with an unfilled delay slot. */
4988 else if (GET_CODE (insn) == INSN
4989 && GET_CODE (pat) != SEQUENCE
4990 && GET_CODE (pat) != USE
4991 && GET_CODE (pat) != CLOBBER
4992 && get_attr_type (insn) == TYPE_MILLI)
4994 /* Block move pattern. */
4995 else if (GET_CODE (insn) == INSN
4996 && GET_CODE (pat) == PARALLEL
4997 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4998 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4999 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
5000 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
5001 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
5002 return compute_movmem_length (insn) - 4;
5003 /* Block clear pattern. */
5004 else if (GET_CODE (insn) == INSN
5005 && GET_CODE (pat) == PARALLEL
5006 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
5007 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
5008 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
5009 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
5010 return compute_clrmem_length (insn) - 4;
5011 /* Conditional branch with an unfilled delay slot. */
5012 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
5014 /* Adjust a short backwards conditional with an unfilled delay slot. */
5015 if (GET_CODE (pat) == SET
5017 && ! forward_branch_p (insn))
5019 else if (GET_CODE (pat) == PARALLEL
5020 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
5023 /* Adjust dbra insn with short backwards conditional branch with
5024 unfilled delay slot -- only for case where counter is in a
5025 general register register. */
5026 else if (GET_CODE (pat) == PARALLEL
5027 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
5028 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
5029 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
5031 && ! forward_branch_p (insn))
5039 /* Print operand X (an rtx) in assembler syntax to file FILE.
5040 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5041 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5044 print_operand (FILE *file, rtx x, int code)
5049 /* Output a 'nop' if there's nothing for the delay slot. */
5050 if (dbr_sequence_length () == 0)
5051 fputs ("\n\tnop", file);
5054 /* Output a nullification completer if there's nothing for the */
5055 /* delay slot or nullification is requested. */
5056 if (dbr_sequence_length () == 0 ||
5058 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
5062 /* Print out the second register name of a register pair.
5063 I.e., R (6) => 7. */
5064 fputs (reg_names[REGNO (x) + 1], file);
5067 /* A register or zero. */
5069 || (x == CONST0_RTX (DFmode))
5070 || (x == CONST0_RTX (SFmode)))
5072 fputs ("%r0", file);
5078 /* A register or zero (floating point). */
5080 || (x == CONST0_RTX (DFmode))
5081 || (x == CONST0_RTX (SFmode)))
5083 fputs ("%fr0", file);
5092 xoperands[0] = XEXP (XEXP (x, 0), 0);
5093 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
5094 output_global_address (file, xoperands[1], 0);
5095 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
5099 case 'C': /* Plain (C)ondition */
5101 switch (GET_CODE (x))
5104 fputs ("=", file); break;
5106 fputs ("<>", file); break;
5108 fputs (">", file); break;
5110 fputs (">=", file); break;
5112 fputs (">>=", file); break;
5114 fputs (">>", file); break;
5116 fputs ("<", file); break;
5118 fputs ("<=", file); break;
5120 fputs ("<<=", file); break;
5122 fputs ("<<", file); break;
5127 case 'N': /* Condition, (N)egated */
5128 switch (GET_CODE (x))
5131 fputs ("<>", file); break;
5133 fputs ("=", file); break;
5135 fputs ("<=", file); break;
5137 fputs ("<", file); break;
5139 fputs ("<<", file); break;
5141 fputs ("<<=", file); break;
5143 fputs (">=", file); break;
5145 fputs (">", file); break;
5147 fputs (">>", file); break;
5149 fputs (">>=", file); break;
5154 /* For floating point comparisons. Note that the output
5155 predicates are the complement of the desired mode. The
5156 conditions for GT, GE, LT, LE and LTGT cause an invalid
5157 operation exception if the result is unordered and this
5158 exception is enabled in the floating-point status register. */
5160 switch (GET_CODE (x))
5163 fputs ("!=", file); break;
5165 fputs ("=", file); break;
5167 fputs ("!>", file); break;
5169 fputs ("!>=", file); break;
5171 fputs ("!<", file); break;
5173 fputs ("!<=", file); break;
5175 fputs ("!<>", file); break;
5177 fputs ("!?<=", file); break;
5179 fputs ("!?<", file); break;
5181 fputs ("!?>=", file); break;
5183 fputs ("!?>", file); break;
5185 fputs ("!?=", file); break;
5187 fputs ("!?", file); break;
5189 fputs ("?", file); break;
5194 case 'S': /* Condition, operands are (S)wapped. */
5195 switch (GET_CODE (x))
5198 fputs ("=", file); break;
5200 fputs ("<>", file); break;
5202 fputs ("<", file); break;
5204 fputs ("<=", file); break;
5206 fputs ("<<=", file); break;
5208 fputs ("<<", file); break;
5210 fputs (">", file); break;
5212 fputs (">=", file); break;
5214 fputs (">>=", file); break;
5216 fputs (">>", file); break;
5221 case 'B': /* Condition, (B)oth swapped and negate. */
5222 switch (GET_CODE (x))
5225 fputs ("<>", file); break;
5227 fputs ("=", file); break;
5229 fputs (">=", file); break;
5231 fputs (">", file); break;
5233 fputs (">>", file); break;
5235 fputs (">>=", file); break;
5237 fputs ("<=", file); break;
5239 fputs ("<", file); break;
5241 fputs ("<<", file); break;
5243 fputs ("<<=", file); break;
5249 if (GET_CODE (x) == CONST_INT)
5251 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5256 if (GET_CODE (x) == CONST_INT)
5258 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5263 if (GET_CODE (x) == CONST_INT)
5265 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5270 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5272 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5277 if (GET_CODE (x) == CONST_INT)
5279 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5284 if (GET_CODE (x) == CONST_INT)
5286 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5291 if (GET_CODE (x) == CONST_INT)
5296 switch (GET_CODE (XEXP (x, 0)))
5300 if (ASSEMBLER_DIALECT == 0)
5301 fputs ("s,mb", file);
5303 fputs (",mb", file);
5307 if (ASSEMBLER_DIALECT == 0)
5308 fputs ("s,ma", file);
5310 fputs (",ma", file);
5313 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5314 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5316 if (ASSEMBLER_DIALECT == 0)
5319 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5320 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5322 if (ASSEMBLER_DIALECT == 0)
5323 fputs ("x,s", file);
5327 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5331 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5337 output_global_address (file, x, 0);
5340 output_global_address (file, x, 1);
5342 case 0: /* Don't do anything special */
5347 compute_zdepwi_operands (INTVAL (x), op);
5348 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5354 compute_zdepdi_operands (INTVAL (x), op);
5355 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5359 /* We can get here from a .vtable_inherit due to our
5360 CONSTANT_ADDRESS_P rejecting perfectly good constant
5366 if (GET_CODE (x) == REG)
5368 fputs (reg_names [REGNO (x)], file);
5369 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5375 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5376 && (REGNO (x) & 1) == 0)
5379 else if (GET_CODE (x) == MEM)
5381 int size = GET_MODE_SIZE (GET_MODE (x));
5382 rtx base = NULL_RTX;
5383 switch (GET_CODE (XEXP (x, 0)))
5387 base = XEXP (XEXP (x, 0), 0);
5388 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5392 base = XEXP (XEXP (x, 0), 0);
5393 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5396 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5397 fprintf (file, "%s(%s)",
5398 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5399 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5400 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5401 fprintf (file, "%s(%s)",
5402 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5403 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5404 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5405 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5407 /* Because the REG_POINTER flag can get lost during reload,
5408 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5409 index and base registers in the combined move patterns. */
5410 rtx base = XEXP (XEXP (x, 0), 1);
5411 rtx index = XEXP (XEXP (x, 0), 0);
5413 fprintf (file, "%s(%s)",
5414 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5417 output_address (XEXP (x, 0));
5420 output_address (XEXP (x, 0));
5425 output_addr_const (file, x);
5428 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5431 output_global_address (FILE *file, rtx x, int round_constant)
5434 /* Imagine (high (const (plus ...))). */
5435 if (GET_CODE (x) == HIGH)
5438 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5439 output_addr_const (file, x);
5440 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5442 output_addr_const (file, x);
5443 fputs ("-$global$", file);
5445 else if (GET_CODE (x) == CONST)
5447 const char *sep = "";
5448 int offset = 0; /* assembler wants -$global$ at end */
5449 rtx base = NULL_RTX;
5451 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5453 base = XEXP (XEXP (x, 0), 0);
5454 output_addr_const (file, base);
5456 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5457 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5460 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5462 base = XEXP (XEXP (x, 0), 1);
5463 output_addr_const (file, base);
5465 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5466 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5469 /* How bogus. The compiler is apparently responsible for
5470 rounding the constant if it uses an LR field selector.
5472 The linker and/or assembler seem a better place since
5473 they have to do this kind of thing already.
5475 If we fail to do this, HP's optimizing linker may eliminate
5476 an addil, but not update the ldw/stw/ldo instruction that
5477 uses the result of the addil. */
5479 offset = ((offset + 0x1000) & ~0x1fff);
5481 if (GET_CODE (XEXP (x, 0)) == PLUS)
5491 else if (GET_CODE (XEXP (x, 0)) == MINUS
5492 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5496 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5497 fputs ("-$global$", file);
5499 fprintf (file, "%s%d", sep, offset);
5502 output_addr_const (file, x);
5505 /* Output boilerplate text to appear at the beginning of the file.
5506 There are several possible versions. */
5507 #define aputs(x) fputs(x, asm_out_file)
5509 pa_file_start_level (void)
5512 aputs ("\t.LEVEL 2.0w\n");
5513 else if (TARGET_PA_20)
5514 aputs ("\t.LEVEL 2.0\n");
5515 else if (TARGET_PA_11)
5516 aputs ("\t.LEVEL 1.1\n");
5518 aputs ("\t.LEVEL 1.0\n");
5522 pa_file_start_space (int sortspace)
5524 aputs ("\t.SPACE $PRIVATE$");
5527 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5528 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5529 "\n\t.SPACE $TEXT$");
5532 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5533 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5537 pa_file_start_file (int want_version)
5539 if (write_symbols != NO_DEBUG)
5541 output_file_directive (asm_out_file, main_input_filename);
5543 aputs ("\t.version\t\"01.01\"\n");
5548 pa_file_start_mcount (const char *aswhat)
5551 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5555 pa_elf_file_start (void)
5557 pa_file_start_level ();
5558 pa_file_start_mcount ("ENTRY");
5559 pa_file_start_file (0);
5563 pa_som_file_start (void)
5565 pa_file_start_level ();
5566 pa_file_start_space (0);
5567 aputs ("\t.IMPORT $global$,DATA\n"
5568 "\t.IMPORT $$dyncall,MILLICODE\n");
5569 pa_file_start_mcount ("CODE");
5570 pa_file_start_file (0);
5574 pa_linux_file_start (void)
5576 pa_file_start_file (1);
5577 pa_file_start_level ();
5578 pa_file_start_mcount ("CODE");
5582 pa_hpux64_gas_file_start (void)
5584 pa_file_start_level ();
5585 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5587 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5589 pa_file_start_file (1);
5593 pa_hpux64_hpas_file_start (void)
5595 pa_file_start_level ();
5596 pa_file_start_space (1);
5597 pa_file_start_mcount ("CODE");
5598 pa_file_start_file (0);
5602 static struct deferred_plabel *
5603 get_plabel (rtx symbol)
5605 const char *fname = XSTR (symbol, 0);
5608 /* See if we have already put this function on the list of deferred
5609 plabels. This list is generally small, so a liner search is not
5610 too ugly. If it proves too slow replace it with something faster. */
5611 for (i = 0; i < n_deferred_plabels; i++)
5612 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5615 /* If the deferred plabel list is empty, or this entry was not found
5616 on the list, create a new entry on the list. */
5617 if (deferred_plabels == NULL || i == n_deferred_plabels)
5621 if (deferred_plabels == 0)
5622 deferred_plabels = (struct deferred_plabel *)
5623 ggc_alloc (sizeof (struct deferred_plabel));
5625 deferred_plabels = (struct deferred_plabel *)
5626 ggc_realloc (deferred_plabels,
5627 ((n_deferred_plabels + 1)
5628 * sizeof (struct deferred_plabel)));
5630 i = n_deferred_plabels++;
5631 deferred_plabels[i].internal_label = gen_label_rtx ();
5632 deferred_plabels[i].symbol = symbol;
5634 /* Gross. We have just implicitly taken the address of this
5635 function. Mark it in the same manner as assemble_name. */
5636 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5638 mark_referenced (id);
5641 return &deferred_plabels[i];
5645 output_deferred_plabels (void)
5648 /* If we have deferred plabels, then we need to switch into the data
5649 section and align it to a 4 byte boundary before we output the
5650 deferred plabels. */
5651 if (n_deferred_plabels)
5654 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5657 /* Now output the deferred plabels. */
5658 for (i = 0; i < n_deferred_plabels; i++)
5660 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5661 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5662 assemble_integer (deferred_plabels[i].symbol,
5663 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5667 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5668 /* Initialize optabs to point to HPUX long double emulation routines. */
5670 pa_hpux_init_libfuncs (void)
5672 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5673 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5674 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5675 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5676 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5677 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5678 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5679 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5680 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5682 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5683 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5684 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5685 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5686 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5687 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5688 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5690 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5691 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5692 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5693 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5695 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5696 ? "__U_Qfcnvfxt_quad_to_sgl"
5697 : "_U_Qfcnvfxt_quad_to_sgl");
5698 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5699 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5700 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5702 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5703 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5707 /* HP's millicode routines mean something special to the assembler.
5708 Keep track of which ones we have used. */
5710 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5711 static void import_milli (enum millicodes);
5712 static char imported[(int) end1000];
5713 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5714 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5715 #define MILLI_START 10
5718 import_milli (enum millicodes code)
5720 char str[sizeof (import_string)];
5722 if (!imported[(int) code])
5724 imported[(int) code] = 1;
5725 strcpy (str, import_string);
5726 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5727 output_asm_insn (str, 0);
5731 /* The register constraints have put the operands and return value in
5732 the proper registers. */
5735 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5737 import_milli (mulI);
5738 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5741 /* Emit the rtl for doing a division by a constant. */
5743 /* Do magic division millicodes exist for this value? */
5744 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5747 /* We'll use an array to keep track of the magic millicodes and
5748 whether or not we've used them already. [n][0] is signed, [n][1] is
5751 static int div_milli[16][2];
5754 div_operand (rtx op, enum machine_mode mode)
5756 return (mode == SImode
5757 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5758 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5759 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5763 emit_hpdiv_const (rtx *operands, int unsignedp)
5765 if (GET_CODE (operands[2]) == CONST_INT
5766 && INTVAL (operands[2]) > 0
5767 && INTVAL (operands[2]) < 16
5768 && magic_milli[INTVAL (operands[2])])
5770 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5772 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5776 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5777 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5779 gen_rtx_REG (SImode, 26),
5781 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5782 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5783 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5784 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5785 gen_rtx_CLOBBER (VOIDmode, ret))));
5786 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5793 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5797 /* If the divisor is a constant, try to use one of the special
5799 if (GET_CODE (operands[0]) == CONST_INT)
5801 static char buf[100];
5802 divisor = INTVAL (operands[0]);
5803 if (!div_milli[divisor][unsignedp])
5805 div_milli[divisor][unsignedp] = 1;
5807 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5809 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5813 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5814 INTVAL (operands[0]));
5815 return output_millicode_call (insn,
5816 gen_rtx_SYMBOL_REF (SImode, buf));
5820 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5821 INTVAL (operands[0]));
5822 return output_millicode_call (insn,
5823 gen_rtx_SYMBOL_REF (SImode, buf));
5826 /* Divisor isn't a special constant. */
5831 import_milli (divU);
5832 return output_millicode_call (insn,
5833 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5837 import_milli (divI);
5838 return output_millicode_call (insn,
5839 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5844 /* Output a $$rem millicode to do mod. */
5847 output_mod_insn (int unsignedp, rtx insn)
5851 import_milli (remU);
5852 return output_millicode_call (insn,
5853 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5857 import_milli (remI);
5858 return output_millicode_call (insn,
5859 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5864 output_arg_descriptor (rtx call_insn)
5866 const char *arg_regs[4];
5867 enum machine_mode arg_mode;
5869 int i, output_flag = 0;
5872 /* We neither need nor want argument location descriptors for the
5873 64bit runtime environment or the ELF32 environment. */
5874 if (TARGET_64BIT || TARGET_ELF32)
5877 for (i = 0; i < 4; i++)
5880 /* Specify explicitly that no argument relocations should take place
5881 if using the portable runtime calling conventions. */
5882 if (TARGET_PORTABLE_RUNTIME)
5884 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5889 if (GET_CODE (call_insn) != CALL_INSN)
5891 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5893 rtx use = XEXP (link, 0);
5895 if (! (GET_CODE (use) == USE
5896 && GET_CODE (XEXP (use, 0)) == REG
5897 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5900 arg_mode = GET_MODE (XEXP (use, 0));
5901 regno = REGNO (XEXP (use, 0));
5902 if (regno >= 23 && regno <= 26)
5904 arg_regs[26 - regno] = "GR";
5905 if (arg_mode == DImode)
5906 arg_regs[25 - regno] = "GR";
5908 else if (regno >= 32 && regno <= 39)
5910 if (arg_mode == SFmode)
5911 arg_regs[(regno - 32) / 2] = "FR";
5914 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5915 arg_regs[(regno - 34) / 2] = "FR";
5916 arg_regs[(regno - 34) / 2 + 1] = "FU";
5918 arg_regs[(regno - 34) / 2] = "FU";
5919 arg_regs[(regno - 34) / 2 + 1] = "FR";
5924 fputs ("\t.CALL ", asm_out_file);
5925 for (i = 0; i < 4; i++)
5930 fputc (',', asm_out_file);
5931 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5934 fputc ('\n', asm_out_file);
5937 /* Return the class of any secondary reload register that is needed to
5938 move IN into a register in class CLASS using mode MODE.
5940 Profiling has showed this routine and its descendants account for
5941 a significant amount of compile time (~7%). So it has been
5942 optimized to reduce redundant computations and eliminate useless
5945 It might be worthwhile to try and make this a leaf function too. */
5948 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5950 int regno, is_symbolic;
5952 /* Trying to load a constant into a FP register during PIC code
5953 generation will require %r1 as a scratch register. */
5955 && GET_MODE_CLASS (mode) == MODE_INT
5956 && FP_REG_CLASS_P (class)
5957 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5960 /* Profiling showed the PA port spends about 1.3% of its compilation
5961 time in true_regnum from calls inside secondary_reload_class. */
5963 if (GET_CODE (in) == REG)
5966 if (regno >= FIRST_PSEUDO_REGISTER)
5967 regno = true_regnum (in);
5969 else if (GET_CODE (in) == SUBREG)
5970 regno = true_regnum (in);
5974 /* If we have something like (mem (mem (...)), we can safely assume the
5975 inner MEM will end up in a general register after reloading, so there's
5976 no need for a secondary reload. */
5977 if (GET_CODE (in) == MEM
5978 && GET_CODE (XEXP (in, 0)) == MEM)
5981 /* Handle out of range displacement for integer mode loads/stores of
5983 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5984 && GET_MODE_CLASS (mode) == MODE_INT
5985 && FP_REG_CLASS_P (class))
5986 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5987 return GENERAL_REGS;
5989 /* A SAR<->FP register copy requires a secondary register (GPR) as
5990 well as secondary memory. */
5991 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5992 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5993 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5994 return GENERAL_REGS;
5996 if (GET_CODE (in) == HIGH)
5999 /* Profiling has showed GCC spends about 2.6% of its compilation
6000 time in symbolic_operand from calls inside secondary_reload_class.
6002 We use an inline copy and only compute its return value once to avoid
6004 switch (GET_CODE (in))
6014 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
6015 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
6016 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
6026 && read_only_operand (in, VOIDmode))
6029 if (class != R1_REGS && is_symbolic)
6035 /* In the 32-bit runtime, arguments larger than eight bytes are passed
6036 by invisible reference. As a GCC extension, we also pass anything
6037 with a zero or variable size by reference.
6039 The 64-bit runtime does not describe passing any types by invisible
6040 reference. The internals of GCC can't currently handle passing
6041 empty structures, and zero or variable length arrays when they are
6042 not passed entirely on the stack or by reference. Thus, as a GCC
6043 extension, we pass these types by reference. The HP compiler doesn't
6044 support these types, so hopefully there shouldn't be any compatibility
6045 issues. This may have to be revisited when HP releases a C99 compiler
6046 or updates the ABI. */
6049 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
6050 enum machine_mode mode, tree type,
6051 bool named ATTRIBUTE_UNUSED)
6056 size = int_size_in_bytes (type);
6058 size = GET_MODE_SIZE (mode);
6063 return size <= 0 || size > 8;
6067 function_arg_padding (enum machine_mode mode, tree type)
6070 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
6072 /* Return none if justification is not required. */
6074 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
6075 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
6078 /* The directions set here are ignored when a BLKmode argument larger
6079 than a word is placed in a register. Different code is used for
6080 the stack and registers. This makes it difficult to have a
6081 consistent data representation for both the stack and registers.
6082 For both runtimes, the justification and padding for arguments on
6083 the stack and in registers should be identical. */
6085 /* The 64-bit runtime specifies left justification for aggregates. */
6088 /* The 32-bit runtime architecture specifies right justification.
6089 When the argument is passed on the stack, the argument is padded
6090 with garbage on the left. The HP compiler pads with zeros. */
6094 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6101 /* Do what is necessary for `va_start'. We look at the current function
6102 to determine if stdargs or varargs is used and fill in an initial
6103 va_list. A pointer to this constructor is returned. */
6106 hppa_builtin_saveregs (void)
6109 tree fntype = TREE_TYPE (current_function_decl);
6110 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
6111 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6112 != void_type_node)))
6113 ? UNITS_PER_WORD : 0);
6116 offset = plus_constant (current_function_arg_offset_rtx, argadj);
6118 offset = current_function_arg_offset_rtx;
6124 /* Adjust for varargs/stdarg differences. */
6126 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
6128 offset = current_function_arg_offset_rtx;
6130 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6131 from the incoming arg pointer and growing to larger addresses. */
6132 for (i = 26, off = -64; i >= 19; i--, off += 8)
6133 emit_move_insn (gen_rtx_MEM (word_mode,
6134 plus_constant (arg_pointer_rtx, off)),
6135 gen_rtx_REG (word_mode, i));
6137 /* The incoming args pointer points just beyond the flushback area;
6138 normally this is not a serious concern. However, when we are doing
6139 varargs/stdargs we want to make the arg pointer point to the start
6140 of the incoming argument area. */
6141 emit_move_insn (virtual_incoming_args_rtx,
6142 plus_constant (arg_pointer_rtx, -64));
6144 /* Now return a pointer to the first anonymous argument. */
6145 return copy_to_reg (expand_binop (Pmode, add_optab,
6146 virtual_incoming_args_rtx,
6147 offset, 0, 0, OPTAB_LIB_WIDEN));
6150 /* Store general registers on the stack. */
6151 dest = gen_rtx_MEM (BLKmode,
6152 plus_constant (current_function_internal_arg_pointer,
6154 set_mem_alias_set (dest, get_varargs_alias_set ());
6155 set_mem_align (dest, BITS_PER_WORD);
6156 move_block_from_reg (23, dest, 4);
6158 /* move_block_from_reg will emit code to store the argument registers
6159 individually as scalar stores.
6161 However, other insns may later load from the same addresses for
6162 a structure load (passing a struct to a varargs routine).
6164 The alias code assumes that such aliasing can never happen, so we
6165 have to keep memory referencing insns from moving up beyond the
6166 last argument register store. So we emit a blockage insn here. */
6167 emit_insn (gen_blockage ());
6169 return copy_to_reg (expand_binop (Pmode, add_optab,
6170 current_function_internal_arg_pointer,
6171 offset, 0, 0, OPTAB_LIB_WIDEN));
6175 hppa_va_start (tree valist, rtx nextarg)
6177 nextarg = expand_builtin_saveregs ();
6178 std_expand_builtin_va_start (valist, nextarg);
6182 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
6186 /* Args grow upward. We can use the generic routines. */
6187 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6189 else /* !TARGET_64BIT */
6191 tree ptr = build_pointer_type (type);
6194 unsigned int size, ofs;
6197 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6201 ptr = build_pointer_type (type);
6203 size = int_size_in_bytes (type);
6204 valist_type = TREE_TYPE (valist);
6206 /* Args grow down. Not handled by generic routines. */
6208 u = fold_convert (valist_type, size_in_bytes (type));
6209 t = build (MINUS_EXPR, valist_type, valist, u);
6211 /* Copied from va-pa.h, but we probably don't need to align to
6212 word size, since we generate and preserve that invariant. */
6213 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
6214 t = build (BIT_AND_EXPR, valist_type, t, u);
6216 t = build (MODIFY_EXPR, valist_type, valist, t);
6218 ofs = (8 - size) % 4;
6221 u = fold_convert (valist_type, size_int (ofs));
6222 t = build (PLUS_EXPR, valist_type, t, u);
6225 t = fold_convert (ptr, t);
6226 t = build_fold_indirect_ref (t);
6229 t = build_fold_indirect_ref (t);
6235 /* True if MODE is valid for the target. By "valid", we mean able to
6236 be manipulated in non-trivial ways. In particular, this means all
6237 the arithmetic is supported.
6239 Currently, TImode is not valid as the HP 64-bit runtime documentation
6240 doesn't document the alignment and calling conventions for this type.
6241 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6242 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6245 pa_scalar_mode_supported_p (enum machine_mode mode)
6247 int precision = GET_MODE_PRECISION (mode);
6249 switch (GET_MODE_CLASS (mode))
6251 case MODE_PARTIAL_INT:
6253 if (precision == CHAR_TYPE_SIZE)
6255 if (precision == SHORT_TYPE_SIZE)
6257 if (precision == INT_TYPE_SIZE)
6259 if (precision == LONG_TYPE_SIZE)
6261 if (precision == LONG_LONG_TYPE_SIZE)
6266 if (precision == FLOAT_TYPE_SIZE)
6268 if (precision == DOUBLE_TYPE_SIZE)
6270 if (precision == LONG_DOUBLE_TYPE_SIZE)
6279 /* This routine handles all the normal conditional branch sequences we
6280 might need to generate. It handles compare immediate vs compare
6281 register, nullification of delay slots, varying length branches,
6282 negated branches, and all combinations of the above. It returns the
6283 output appropriate to emit the branch corresponding to all given
6287 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6289 static char buf[100];
6293 /* A conditional branch to the following instruction (e.g. the delay slot)
6294 is asking for a disaster. This can happen when not optimizing and
6295 when jump optimization fails.
6297 While it is usually safe to emit nothing, this can fail if the
6298 preceding instruction is a nullified branch with an empty delay
6299 slot and the same branch target as this branch. We could check
6300 for this but jump optimization should eliminate nop jumps. It
6301 is always safe to emit a nop. */
6302 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6305 /* The doubleword form of the cmpib instruction doesn't have the LEU
6306 and GTU conditions while the cmpb instruction does. Since we accept
6307 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6308 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6309 operands[2] = gen_rtx_REG (DImode, 0);
6311 /* If this is a long branch with its delay slot unfilled, set `nullify'
6312 as it can nullify the delay slot and save a nop. */
6313 if (length == 8 && dbr_sequence_length () == 0)
6316 /* If this is a short forward conditional branch which did not get
6317 its delay slot filled, the delay slot can still be nullified. */
6318 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6319 nullify = forward_branch_p (insn);
6321 /* A forward branch over a single nullified insn can be done with a
6322 comclr instruction. This avoids a single cycle penalty due to
6323 mis-predicted branch if we fall through (branch not taken). */
6325 && next_real_insn (insn) != 0
6326 && get_attr_length (next_real_insn (insn)) == 4
6327 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6333 /* All short conditional branches except backwards with an unfilled
6337 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6339 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6340 if (GET_MODE (operands[1]) == DImode)
6343 strcat (buf, "%B3");
6345 strcat (buf, "%S3");
6347 strcat (buf, " %2,%r1,%%r0");
6349 strcat (buf, ",n %2,%r1,%0");
6351 strcat (buf, " %2,%r1,%0");
6354 /* All long conditionals. Note a short backward branch with an
6355 unfilled delay slot is treated just like a long backward branch
6356 with an unfilled delay slot. */
6358 /* Handle weird backwards branch with a filled delay slot
6359 with is nullified. */
6360 if (dbr_sequence_length () != 0
6361 && ! forward_branch_p (insn)
6364 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6365 if (GET_MODE (operands[1]) == DImode)
6368 strcat (buf, "%S3");
6370 strcat (buf, "%B3");
6371 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6373 /* Handle short backwards branch with an unfilled delay slot.
6374 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6375 taken and untaken branches. */
6376 else if (dbr_sequence_length () == 0
6377 && ! forward_branch_p (insn)
6378 && INSN_ADDRESSES_SET_P ()
6379 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6380 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6382 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6383 if (GET_MODE (operands[1]) == DImode)
6386 strcat (buf, "%B3 %2,%r1,%0%#");
6388 strcat (buf, "%S3 %2,%r1,%0%#");
6392 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6393 if (GET_MODE (operands[1]) == DImode)
6396 strcat (buf, "%S3");
6398 strcat (buf, "%B3");
6400 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6402 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6408 xoperands[0] = operands[0];
6409 xoperands[1] = operands[1];
6410 xoperands[2] = operands[2];
6411 xoperands[3] = operands[3];
6413 /* The reversed conditional branch must branch over one additional
6414 instruction if the delay slot is filled. If the delay slot
6415 is empty, the instruction after the reversed condition branch
6416 must be nullified. */
6417 nullify = dbr_sequence_length () == 0;
6418 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6420 /* Create a reversed conditional branch which branches around
6421 the following insns. */
6422 if (GET_MODE (operands[1]) != DImode)
6428 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6431 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6437 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6440 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6449 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6452 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6458 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6461 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6465 output_asm_insn (buf, xoperands);
6466 return output_lbranch (operands[0], insn);
6474 /* This routine handles long unconditional branches that exceed the
6475 maximum range of a simple branch instruction. */
6478 output_lbranch (rtx dest, rtx insn)
6482 xoperands[0] = dest;
6484 /* First, free up the delay slot. */
6485 if (dbr_sequence_length () != 0)
6487 /* We can't handle a jump in the delay slot. */
6488 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6491 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6492 optimize, 0, 0, NULL);
6494 /* Now delete the delay insn. */
6495 PUT_CODE (NEXT_INSN (insn), NOTE);
6496 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6497 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6500 /* Output an insn to save %r1. The runtime documentation doesn't
6501 specify whether the "Clean Up" slot in the callers frame can
6502 be clobbered by the callee. It isn't copied by HP's builtin
6503 alloca, so this suggests that it can be clobbered if necessary.
6504 The "Static Link" location is copied by HP builtin alloca, so
6505 we avoid using it. Using the cleanup slot might be a problem
6506 if we have to interoperate with languages that pass cleanup
6507 information. However, it should be possible to handle these
6508 situations with GCC's asm feature.
6510 The "Current RP" slot is reserved for the called procedure, so
6511 we try to use it when we don't have a frame of our own. It's
6512 rather unlikely that we won't have a frame when we need to emit
6515 Really the way to go long term is a register scavenger; goto
6516 the target of the jump and find a register which we can use
6517 as a scratch to hold the value in %r1. Then, we wouldn't have
6518 to free up the delay slot or clobber a slot that may be needed
6519 for other purposes. */
6522 if (actual_fsize == 0 && !regs_ever_live[2])
6523 /* Use the return pointer slot in the frame marker. */
6524 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6526 /* Use the slot at -40 in the frame marker since HP builtin
6527 alloca doesn't copy it. */
6528 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6532 if (actual_fsize == 0 && !regs_ever_live[2])
6533 /* Use the return pointer slot in the frame marker. */
6534 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6536 /* Use the "Clean Up" slot in the frame marker. In GCC,
6537 the only other use of this location is for copying a
6538 floating point double argument from a floating-point
6539 register to two general registers. The copy is done
6540 as an "atomic" operation when outputting a call, so it
6541 won't interfere with our using the location here. */
6542 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6545 if (TARGET_PORTABLE_RUNTIME)
6547 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6548 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6549 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6553 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6554 if (TARGET_SOM || !TARGET_GAS)
6556 xoperands[1] = gen_label_rtx ();
6557 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6558 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6559 CODE_LABEL_NUMBER (xoperands[1]));
6560 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6564 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6565 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6567 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6570 /* Now output a very long branch to the original target. */
6571 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6573 /* Now restore the value of %r1 in the delay slot. */
6576 if (actual_fsize == 0 && !regs_ever_live[2])
6577 return "ldd -16(%%r30),%%r1";
6579 return "ldd -40(%%r30),%%r1";
6583 if (actual_fsize == 0 && !regs_ever_live[2])
6584 return "ldw -20(%%r30),%%r1";
6586 return "ldw -12(%%r30),%%r1";
6590 /* This routine handles all the branch-on-bit conditional branch sequences we
6591 might need to generate. It handles nullification of delay slots,
6592 varying length branches, negated branches and all combinations of the
6593 above. it returns the appropriate output template to emit the branch. */
6596 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6597 int negated, rtx insn, int which)
6599 static char buf[100];
6602 /* A conditional branch to the following instruction (e.g. the delay slot) is
6603 asking for a disaster. I do not think this can happen as this pattern
6604 is only used when optimizing; jump optimization should eliminate the
6605 jump. But be prepared just in case. */
6607 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6610 /* If this is a long branch with its delay slot unfilled, set `nullify'
6611 as it can nullify the delay slot and save a nop. */
6612 if (length == 8 && dbr_sequence_length () == 0)
6615 /* If this is a short forward conditional branch which did not get
6616 its delay slot filled, the delay slot can still be nullified. */
6617 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6618 nullify = forward_branch_p (insn);
6620 /* A forward branch over a single nullified insn can be done with a
6621 extrs instruction. This avoids a single cycle penalty due to
6622 mis-predicted branch if we fall through (branch not taken). */
6625 && next_real_insn (insn) != 0
6626 && get_attr_length (next_real_insn (insn)) == 4
6627 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6634 /* All short conditional branches except backwards with an unfilled
6638 strcpy (buf, "{extrs,|extrw,s,}");
6640 strcpy (buf, "bb,");
6641 if (useskip && GET_MODE (operands[0]) == DImode)
6642 strcpy (buf, "extrd,s,*");
6643 else if (GET_MODE (operands[0]) == DImode)
6644 strcpy (buf, "bb,*");
6645 if ((which == 0 && negated)
6646 || (which == 1 && ! negated))
6651 strcat (buf, " %0,%1,1,%%r0");
6652 else if (nullify && negated)
6653 strcat (buf, ",n %0,%1,%3");
6654 else if (nullify && ! negated)
6655 strcat (buf, ",n %0,%1,%2");
6656 else if (! nullify && negated)
6657 strcat (buf, "%0,%1,%3");
6658 else if (! nullify && ! negated)
6659 strcat (buf, " %0,%1,%2");
6662 /* All long conditionals. Note a short backward branch with an
6663 unfilled delay slot is treated just like a long backward branch
6664 with an unfilled delay slot. */
6666 /* Handle weird backwards branch with a filled delay slot
6667 with is nullified. */
6668 if (dbr_sequence_length () != 0
6669 && ! forward_branch_p (insn)
6672 strcpy (buf, "bb,");
6673 if (GET_MODE (operands[0]) == DImode)
6675 if ((which == 0 && negated)
6676 || (which == 1 && ! negated))
6681 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6683 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6685 /* Handle short backwards branch with an unfilled delay slot.
6686 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6687 taken and untaken branches. */
6688 else if (dbr_sequence_length () == 0
6689 && ! forward_branch_p (insn)
6690 && INSN_ADDRESSES_SET_P ()
6691 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6692 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6694 strcpy (buf, "bb,");
6695 if (GET_MODE (operands[0]) == DImode)
6697 if ((which == 0 && negated)
6698 || (which == 1 && ! negated))
6703 strcat (buf, " %0,%1,%3%#");
6705 strcat (buf, " %0,%1,%2%#");
6709 strcpy (buf, "{extrs,|extrw,s,}");
6710 if (GET_MODE (operands[0]) == DImode)
6711 strcpy (buf, "extrd,s,*");
6712 if ((which == 0 && negated)
6713 || (which == 1 && ! negated))
6717 if (nullify && negated)
6718 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6719 else if (nullify && ! negated)
6720 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6722 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6724 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6734 /* This routine handles all the branch-on-variable-bit conditional branch
6735 sequences we might need to generate. It handles nullification of delay
6736 slots, varying length branches, negated branches and all combinations
6737 of the above. it returns the appropriate output template to emit the
6741 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6742 int negated, rtx insn, int which)
6744 static char buf[100];
6747 /* A conditional branch to the following instruction (e.g. the delay slot) is
6748 asking for a disaster. I do not think this can happen as this pattern
6749 is only used when optimizing; jump optimization should eliminate the
6750 jump. But be prepared just in case. */
6752 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6755 /* If this is a long branch with its delay slot unfilled, set `nullify'
6756 as it can nullify the delay slot and save a nop. */
6757 if (length == 8 && dbr_sequence_length () == 0)
6760 /* If this is a short forward conditional branch which did not get
6761 its delay slot filled, the delay slot can still be nullified. */
6762 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6763 nullify = forward_branch_p (insn);
6765 /* A forward branch over a single nullified insn can be done with a
6766 extrs instruction. This avoids a single cycle penalty due to
6767 mis-predicted branch if we fall through (branch not taken). */
6770 && next_real_insn (insn) != 0
6771 && get_attr_length (next_real_insn (insn)) == 4
6772 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6779 /* All short conditional branches except backwards with an unfilled
6783 strcpy (buf, "{vextrs,|extrw,s,}");
6785 strcpy (buf, "{bvb,|bb,}");
6786 if (useskip && GET_MODE (operands[0]) == DImode)
6787 strcpy (buf, "extrd,s,*");
6788 else if (GET_MODE (operands[0]) == DImode)
6789 strcpy (buf, "bb,*");
6790 if ((which == 0 && negated)
6791 || (which == 1 && ! negated))
6796 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6797 else if (nullify && negated)
6798 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6799 else if (nullify && ! negated)
6800 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6801 else if (! nullify && negated)
6802 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6803 else if (! nullify && ! negated)
6804 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6807 /* All long conditionals. Note a short backward branch with an
6808 unfilled delay slot is treated just like a long backward branch
6809 with an unfilled delay slot. */
6811 /* Handle weird backwards branch with a filled delay slot
6812 with is nullified. */
6813 if (dbr_sequence_length () != 0
6814 && ! forward_branch_p (insn)
6817 strcpy (buf, "{bvb,|bb,}");
6818 if (GET_MODE (operands[0]) == DImode)
6820 if ((which == 0 && negated)
6821 || (which == 1 && ! negated))
6826 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6828 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6830 /* Handle short backwards branch with an unfilled delay slot.
6831 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6832 taken and untaken branches. */
6833 else if (dbr_sequence_length () == 0
6834 && ! forward_branch_p (insn)
6835 && INSN_ADDRESSES_SET_P ()
6836 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6837 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6839 strcpy (buf, "{bvb,|bb,}");
6840 if (GET_MODE (operands[0]) == DImode)
6842 if ((which == 0 && negated)
6843 || (which == 1 && ! negated))
6848 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6850 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6854 strcpy (buf, "{vextrs,|extrw,s,}");
6855 if (GET_MODE (operands[0]) == DImode)
6856 strcpy (buf, "extrd,s,*");
6857 if ((which == 0 && negated)
6858 || (which == 1 && ! negated))
6862 if (nullify && negated)
6863 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6864 else if (nullify && ! negated)
6865 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6867 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6869 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6879 /* Return the output template for emitting a dbra type insn.
6881 Note it may perform some output operations on its own before
6882 returning the final output string. */
6884 output_dbra (rtx *operands, rtx insn, int which_alternative)
6887 /* A conditional branch to the following instruction (e.g. the delay slot) is
6888 asking for a disaster. Be prepared! */
6890 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6892 if (which_alternative == 0)
6893 return "ldo %1(%0),%0";
6894 else if (which_alternative == 1)
6896 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6897 output_asm_insn ("ldw -16(%%r30),%4", operands);
6898 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6899 return "{fldws|fldw} -16(%%r30),%0";
6903 output_asm_insn ("ldw %0,%4", operands);
6904 return "ldo %1(%4),%4\n\tstw %4,%0";
6908 if (which_alternative == 0)
6910 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6911 int length = get_attr_length (insn);
6913 /* If this is a long branch with its delay slot unfilled, set `nullify'
6914 as it can nullify the delay slot and save a nop. */
6915 if (length == 8 && dbr_sequence_length () == 0)
6918 /* If this is a short forward conditional branch which did not get
6919 its delay slot filled, the delay slot can still be nullified. */
6920 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6921 nullify = forward_branch_p (insn);
6923 /* Handle short versions first. */
6924 if (length == 4 && nullify)
6925 return "addib,%C2,n %1,%0,%3";
6926 else if (length == 4 && ! nullify)
6927 return "addib,%C2 %1,%0,%3";
6928 else if (length == 8)
6930 /* Handle weird backwards branch with a fulled delay slot
6931 which is nullified. */
6932 if (dbr_sequence_length () != 0
6933 && ! forward_branch_p (insn)
6935 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6936 /* Handle short backwards branch with an unfilled delay slot.
6937 Using a addb;nop rather than addi;bl saves 1 cycle for both
6938 taken and untaken branches. */
6939 else if (dbr_sequence_length () == 0
6940 && ! forward_branch_p (insn)
6941 && INSN_ADDRESSES_SET_P ()
6942 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6943 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6944 return "addib,%C2 %1,%0,%3%#";
6946 /* Handle normal cases. */
6948 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6950 return "addi,%N2 %1,%0,%0\n\tb %3";
6955 /* Deal with gross reload from FP register case. */
6956 else if (which_alternative == 1)
6958 /* Move loop counter from FP register to MEM then into a GR,
6959 increment the GR, store the GR into MEM, and finally reload
6960 the FP register from MEM from within the branch's delay slot. */
6961 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6963 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6964 if (get_attr_length (insn) == 24)
6965 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6967 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6969 /* Deal with gross reload from memory case. */
6972 /* Reload loop counter from memory, the store back to memory
6973 happens in the branch's delay slot. */
6974 output_asm_insn ("ldw %0,%4", operands);
6975 if (get_attr_length (insn) == 12)
6976 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6978 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6982 /* Return the output template for emitting a dbra type insn.
6984 Note it may perform some output operations on its own before
6985 returning the final output string. */
6987 output_movb (rtx *operands, rtx insn, int which_alternative,
6988 int reverse_comparison)
6991 /* A conditional branch to the following instruction (e.g. the delay slot) is
6992 asking for a disaster. Be prepared! */
6994 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6996 if (which_alternative == 0)
6997 return "copy %1,%0";
6998 else if (which_alternative == 1)
7000 output_asm_insn ("stw %1,-16(%%r30)", operands);
7001 return "{fldws|fldw} -16(%%r30),%0";
7003 else if (which_alternative == 2)
7009 /* Support the second variant. */
7010 if (reverse_comparison)
7011 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
7013 if (which_alternative == 0)
7015 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7016 int length = get_attr_length (insn);
7018 /* If this is a long branch with its delay slot unfilled, set `nullify'
7019 as it can nullify the delay slot and save a nop. */
7020 if (length == 8 && dbr_sequence_length () == 0)
7023 /* If this is a short forward conditional branch which did not get
7024 its delay slot filled, the delay slot can still be nullified. */
7025 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7026 nullify = forward_branch_p (insn);
7028 /* Handle short versions first. */
7029 if (length == 4 && nullify)
7030 return "movb,%C2,n %1,%0,%3";
7031 else if (length == 4 && ! nullify)
7032 return "movb,%C2 %1,%0,%3";
7033 else if (length == 8)
7035 /* Handle weird backwards branch with a filled delay slot
7036 which is nullified. */
7037 if (dbr_sequence_length () != 0
7038 && ! forward_branch_p (insn)
7040 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7042 /* Handle short backwards branch with an unfilled delay slot.
7043 Using a movb;nop rather than or;bl saves 1 cycle for both
7044 taken and untaken branches. */
7045 else if (dbr_sequence_length () == 0
7046 && ! forward_branch_p (insn)
7047 && INSN_ADDRESSES_SET_P ()
7048 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7049 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7050 return "movb,%C2 %1,%0,%3%#";
7051 /* Handle normal cases. */
7053 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7055 return "or,%N2 %1,%%r0,%0\n\tb %3";
7060 /* Deal with gross reload from FP register case. */
7061 else if (which_alternative == 1)
7063 /* Move loop counter from FP register to MEM then into a GR,
7064 increment the GR, store the GR into MEM, and finally reload
7065 the FP register from MEM from within the branch's delay slot. */
7066 output_asm_insn ("stw %1,-16(%%r30)", operands);
7067 if (get_attr_length (insn) == 12)
7068 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7070 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7072 /* Deal with gross reload from memory case. */
7073 else if (which_alternative == 2)
7075 /* Reload loop counter from memory, the store back to memory
7076 happens in the branch's delay slot. */
7077 if (get_attr_length (insn) == 8)
7078 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7080 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7082 /* Handle SAR as a destination. */
7085 if (get_attr_length (insn) == 8)
7086 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7088 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7092 /* Copy any FP arguments in INSN into integer registers. */
7094 copy_fp_args (rtx insn)
7099 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7101 int arg_mode, regno;
7102 rtx use = XEXP (link, 0);
7104 if (! (GET_CODE (use) == USE
7105 && GET_CODE (XEXP (use, 0)) == REG
7106 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7109 arg_mode = GET_MODE (XEXP (use, 0));
7110 regno = REGNO (XEXP (use, 0));
7112 /* Is it a floating point register? */
7113 if (regno >= 32 && regno <= 39)
7115 /* Copy the FP register into an integer register via memory. */
7116 if (arg_mode == SFmode)
7118 xoperands[0] = XEXP (use, 0);
7119 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7120 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7121 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7125 xoperands[0] = XEXP (use, 0);
7126 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7127 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7128 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7129 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7135 /* Compute length of the FP argument copy sequence for INSN. */
7137 length_fp_args (rtx insn)
7142 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7144 int arg_mode, regno;
7145 rtx use = XEXP (link, 0);
7147 if (! (GET_CODE (use) == USE
7148 && GET_CODE (XEXP (use, 0)) == REG
7149 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7152 arg_mode = GET_MODE (XEXP (use, 0));
7153 regno = REGNO (XEXP (use, 0));
7155 /* Is it a floating point register? */
7156 if (regno >= 32 && regno <= 39)
7158 if (arg_mode == SFmode)
7168 /* Return the attribute length for the millicode call instruction INSN.
7169 The length must match the code generated by output_millicode_call.
7170 We include the delay slot in the returned length as it is better to
7171 over estimate the length than to under estimate it. */
7174 attr_length_millicode_call (rtx insn)
7176 unsigned long distance = -1;
7177 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7179 if (INSN_ADDRESSES_SET_P ())
7181 distance = (total + insn_current_reference_address (insn));
7182 if (distance < total)
7188 if (!TARGET_LONG_CALLS && distance < 7600000)
7193 else if (TARGET_PORTABLE_RUNTIME)
7197 if (!TARGET_LONG_CALLS && distance < 240000)
7200 if (TARGET_LONG_ABS_CALL && !flag_pic)
7207 /* INSN is a function call. It may have an unconditional jump
7210 CALL_DEST is the routine we are calling. */
7213 output_millicode_call (rtx insn, rtx call_dest)
7215 int attr_length = get_attr_length (insn);
7216 int seq_length = dbr_sequence_length ();
7221 xoperands[0] = call_dest;
7222 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7224 /* Handle the common case where we are sure that the branch will
7225 reach the beginning of the $CODE$ subspace. The within reach
7226 form of the $$sh_func_adrs call has a length of 28. Because
7227 it has an attribute type of multi, it never has a nonzero
7228 sequence length. The length of the $$sh_func_adrs is the same
7229 as certain out of reach PIC calls to other routines. */
7230 if (!TARGET_LONG_CALLS
7231 && ((seq_length == 0
7232 && (attr_length == 12
7233 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7234 || (seq_length != 0 && attr_length == 8)))
7236 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7242 /* It might seem that one insn could be saved by accessing
7243 the millicode function using the linkage table. However,
7244 this doesn't work in shared libraries and other dynamically
7245 loaded objects. Using a pc-relative sequence also avoids
7246 problems related to the implicit use of the gp register. */
7247 output_asm_insn ("b,l .+8,%%r1", xoperands);
7251 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7252 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7256 xoperands[1] = gen_label_rtx ();
7257 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7258 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7259 CODE_LABEL_NUMBER (xoperands[1]));
7260 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7263 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7265 else if (TARGET_PORTABLE_RUNTIME)
7267 /* Pure portable runtime doesn't allow be/ble; we also don't
7268 have PIC support in the assembler/linker, so this sequence
7271 /* Get the address of our target into %r1. */
7272 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7273 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7275 /* Get our return address into %r31. */
7276 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7277 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7279 /* Jump to our target address in %r1. */
7280 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7284 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7286 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7288 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7292 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7293 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7295 if (TARGET_SOM || !TARGET_GAS)
7297 /* The HP assembler can generate relocations for the
7298 difference of two symbols. GAS can do this for a
7299 millicode symbol but not an arbitrary external
7300 symbol when generating SOM output. */
7301 xoperands[1] = gen_label_rtx ();
7302 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7303 CODE_LABEL_NUMBER (xoperands[1]));
7304 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7305 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7309 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7310 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7314 /* Jump to our target address in %r1. */
7315 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7319 if (seq_length == 0)
7320 output_asm_insn ("nop", xoperands);
7322 /* We are done if there isn't a jump in the delay slot. */
7323 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7326 /* This call has an unconditional jump in its delay slot. */
7327 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7329 /* See if the return address can be adjusted. Use the containing
7330 sequence insn's address. */
7331 if (INSN_ADDRESSES_SET_P ())
7333 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7334 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7335 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7337 if (VAL_14_BITS_P (distance))
7339 xoperands[1] = gen_label_rtx ();
7340 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7341 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7342 CODE_LABEL_NUMBER (xoperands[1]));
7345 /* ??? This branch may not reach its target. */
7346 output_asm_insn ("nop\n\tb,n %0", xoperands);
7349 /* ??? This branch may not reach its target. */
7350 output_asm_insn ("nop\n\tb,n %0", xoperands);
7352 /* Delete the jump. */
7353 PUT_CODE (NEXT_INSN (insn), NOTE);
7354 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7355 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7360 /* Return the attribute length of the call instruction INSN. The SIBCALL
7361 flag indicates whether INSN is a regular call or a sibling call. The
7362 length returned must be longer than the code actually generated by
7363 output_call. Since branch shortening is done before delay branch
7364 sequencing, there is no way to determine whether or not the delay
7365 slot will be filled during branch shortening. Even when the delay
7366 slot is filled, we may have to add a nop if the delay slot contains
7367 a branch that can't reach its target. Thus, we always have to include
7368 the delay slot in the length estimate. This used to be done in
7369 pa_adjust_insn_length but we do it here now as some sequences always
7370 fill the delay slot and we can save four bytes in the estimate for
7374 attr_length_call (rtx insn, int sibcall)
7380 rtx pat = PATTERN (insn);
7381 unsigned long distance = -1;
7383 if (INSN_ADDRESSES_SET_P ())
7385 unsigned long total;
7387 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7388 distance = (total + insn_current_reference_address (insn));
7389 if (distance < total)
7393 /* Determine if this is a local call. */
7394 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7395 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7397 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7399 call_decl = SYMBOL_REF_DECL (call_dest);
7400 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7402 /* pc-relative branch. */
7403 if (!TARGET_LONG_CALLS
7404 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7405 || distance < 240000))
7408 /* 64-bit plabel sequence. */
7409 else if (TARGET_64BIT && !local_call)
7410 length += sibcall ? 28 : 24;
7412 /* non-pic long absolute branch sequence. */
7413 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7416 /* long pc-relative branch sequence. */
7417 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7418 || (TARGET_64BIT && !TARGET_GAS)
7419 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7423 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7427 /* 32-bit plabel sequence. */
7433 length += length_fp_args (insn);
7443 if (!TARGET_NO_SPACE_REGS)
7451 /* INSN is a function call. It may have an unconditional jump
7454 CALL_DEST is the routine we are calling. */
7457 output_call (rtx insn, rtx call_dest, int sibcall)
7459 int delay_insn_deleted = 0;
7460 int delay_slot_filled = 0;
7461 int seq_length = dbr_sequence_length ();
7462 tree call_decl = SYMBOL_REF_DECL (call_dest);
7463 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7466 xoperands[0] = call_dest;
7468 /* Handle the common case where we're sure that the branch will reach
7469 the beginning of the "$CODE$" subspace. This is the beginning of
7470 the current function if we are in a named section. */
7471 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7473 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7474 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7478 if (TARGET_64BIT && !local_call)
7480 /* ??? As far as I can tell, the HP linker doesn't support the
7481 long pc-relative sequence described in the 64-bit runtime
7482 architecture. So, we use a slightly longer indirect call. */
7483 struct deferred_plabel *p = get_plabel (call_dest);
7485 xoperands[0] = p->internal_label;
7486 xoperands[1] = gen_label_rtx ();
7488 /* If this isn't a sibcall, we put the load of %r27 into the
7489 delay slot. We can't do this in a sibcall as we don't
7490 have a second call-clobbered scratch register available. */
7492 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7495 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7496 optimize, 0, 0, NULL);
7498 /* Now delete the delay insn. */
7499 PUT_CODE (NEXT_INSN (insn), NOTE);
7500 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7501 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7502 delay_insn_deleted = 1;
7505 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7506 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7507 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7511 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7512 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7513 output_asm_insn ("bve (%%r1)", xoperands);
7517 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7518 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7519 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7520 delay_slot_filled = 1;
7525 int indirect_call = 0;
7527 /* Emit a long call. There are several different sequences
7528 of increasing length and complexity. In most cases,
7529 they don't allow an instruction in the delay slot. */
7530 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7531 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7532 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7537 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7539 && (!TARGET_PA_20 || indirect_call))
7541 /* A non-jump insn in the delay slot. By definition we can
7542 emit this insn before the call (and in fact before argument
7544 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7547 /* Now delete the delay insn. */
7548 PUT_CODE (NEXT_INSN (insn), NOTE);
7549 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7550 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7551 delay_insn_deleted = 1;
7554 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7556 /* This is the best sequence for making long calls in
7557 non-pic code. Unfortunately, GNU ld doesn't provide
7558 the stub needed for external calls, and GAS's support
7559 for this with the SOM linker is buggy. It is safe
7560 to use this for local calls. */
7561 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7563 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7567 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7570 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7572 output_asm_insn ("copy %%r31,%%r2", xoperands);
7573 delay_slot_filled = 1;
7578 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7579 || (TARGET_64BIT && !TARGET_GAS))
7581 /* The HP assembler and linker can handle relocations
7582 for the difference of two symbols. GAS and the HP
7583 linker can't do this when one of the symbols is
7585 xoperands[1] = gen_label_rtx ();
7586 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7587 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7588 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7589 CODE_LABEL_NUMBER (xoperands[1]));
7590 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7592 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7594 /* GAS currently can't generate the relocations that
7595 are needed for the SOM linker under HP-UX using this
7596 sequence. The GNU linker doesn't generate the stubs
7597 that are needed for external calls on TARGET_ELF32
7598 with this sequence. For now, we have to use a
7599 longer plabel sequence when using GAS. */
7600 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7601 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7603 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7608 /* Emit a long plabel-based call sequence. This is
7609 essentially an inline implementation of $$dyncall.
7610 We don't actually try to call $$dyncall as this is
7611 as difficult as calling the function itself. */
7612 struct deferred_plabel *p = get_plabel (call_dest);
7614 xoperands[0] = p->internal_label;
7615 xoperands[1] = gen_label_rtx ();
7617 /* Since the call is indirect, FP arguments in registers
7618 need to be copied to the general registers. Then, the
7619 argument relocation stub will copy them back. */
7621 copy_fp_args (insn);
7625 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7626 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7627 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7631 output_asm_insn ("addil LR'%0-$global$,%%r27",
7633 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7637 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7638 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7639 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7640 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7642 if (!sibcall && !TARGET_PA_20)
7644 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7645 if (TARGET_NO_SPACE_REGS)
7646 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7648 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7655 output_asm_insn ("bve (%%r1)", xoperands);
7660 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7661 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7662 delay_slot_filled = 1;
7665 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7670 if (!TARGET_NO_SPACE_REGS)
7671 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7676 if (TARGET_NO_SPACE_REGS)
7677 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7679 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7683 if (TARGET_NO_SPACE_REGS)
7684 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7686 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7689 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7691 output_asm_insn ("copy %%r31,%%r2", xoperands);
7692 delay_slot_filled = 1;
7699 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7700 output_asm_insn ("nop", xoperands);
7702 /* We are done if there isn't a jump in the delay slot. */
7704 || delay_insn_deleted
7705 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7708 /* A sibcall should never have a branch in the delay slot. */
7712 /* This call has an unconditional jump in its delay slot. */
7713 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7715 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7717 /* See if the return address can be adjusted. Use the containing
7718 sequence insn's address. */
7719 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7720 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7721 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7723 if (VAL_14_BITS_P (distance))
7725 xoperands[1] = gen_label_rtx ();
7726 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7727 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7728 CODE_LABEL_NUMBER (xoperands[1]));
7731 output_asm_insn ("nop\n\tb,n %0", xoperands);
7734 output_asm_insn ("b,n %0", xoperands);
7736 /* Delete the jump. */
7737 PUT_CODE (NEXT_INSN (insn), NOTE);
7738 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7739 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7744 /* Return the attribute length of the indirect call instruction INSN.
7745 The length must match the code generated by output_indirect call.
7746 The returned length includes the delay slot. Currently, the delay
7747 slot of an indirect call sequence is not exposed and it is used by
7748 the sequence itself. */
7751 attr_length_indirect_call (rtx insn)
7753 unsigned long distance = -1;
7754 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7756 if (INSN_ADDRESSES_SET_P ())
7758 distance = (total + insn_current_reference_address (insn));
7759 if (distance < total)
7766 if (TARGET_FAST_INDIRECT_CALLS
7767 || (!TARGET_PORTABLE_RUNTIME
7768 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7774 if (TARGET_PORTABLE_RUNTIME)
7777 /* Out of reach, can use ble. */
7782 output_indirect_call (rtx insn, rtx call_dest)
7788 xoperands[0] = call_dest;
7789 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7790 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7794 /* First the special case for kernels, level 0 systems, etc. */
7795 if (TARGET_FAST_INDIRECT_CALLS)
7796 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7798 /* Now the normal case -- we can reach $$dyncall directly or
7799 we're sure that we can get there via a long-branch stub.
7801 No need to check target flags as the length uniquely identifies
7802 the remaining cases. */
7803 if (attr_length_indirect_call (insn) == 8)
7805 /* The HP linker substitutes a BLE for millicode calls using
7806 the short PIC PCREL form. Thus, we must use %r31 as the
7807 link register when generating PA 1.x code. */
7809 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7811 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7814 /* Long millicode call, but we are not generating PIC or portable runtime
7816 if (attr_length_indirect_call (insn) == 12)
7817 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7819 /* Long millicode call for portable runtime. */
7820 if (attr_length_indirect_call (insn) == 20)
7821 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7823 /* We need a long PIC call to $$dyncall. */
7824 xoperands[0] = NULL_RTX;
7825 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7826 if (TARGET_SOM || !TARGET_GAS)
7828 xoperands[0] = gen_label_rtx ();
7829 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7830 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7831 CODE_LABEL_NUMBER (xoperands[0]));
7832 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7836 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7837 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7840 output_asm_insn ("blr %%r0,%%r2", xoperands);
7841 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7845 /* Return the total length of the save and restore instructions needed for
7846 the data linkage table pointer (i.e., the PIC register) across the call
7847 instruction INSN. No-return calls do not require a save and restore.
7848 In addition, we may be able to avoid the save and restore for calls
7849 within the same translation unit. */
7852 attr_length_save_restore_dltp (rtx insn)
7854 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7860 /* In HPUX 8.0's shared library scheme, special relocations are needed
7861 for function labels if they might be passed to a function
7862 in a shared library (because shared libraries don't live in code
7863 space), and special magic is needed to construct their address. */
7866 hppa_encode_label (rtx sym)
7868 const char *str = XSTR (sym, 0);
7869 int len = strlen (str) + 1;
7872 p = newstr = alloca (len + 1);
7876 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7880 pa_encode_section_info (tree decl, rtx rtl, int first)
7882 if (first && TEXT_SPACE_P (decl))
7884 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7885 if (TREE_CODE (decl) == FUNCTION_DECL)
7886 hppa_encode_label (XEXP (rtl, 0));
7890 /* This is sort of inverse to pa_encode_section_info. */
7893 pa_strip_name_encoding (const char *str)
7895 str += (*str == '@');
7896 str += (*str == '*');
7901 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7903 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7906 /* Returns 1 if OP is a function label involved in a simple addition
7907 with a constant. Used to keep certain patterns from matching
7908 during instruction combination. */
7910 is_function_label_plus_const (rtx op)
7912 /* Strip off any CONST. */
7913 if (GET_CODE (op) == CONST)
7916 return (GET_CODE (op) == PLUS
7917 && function_label_operand (XEXP (op, 0), Pmode)
7918 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7921 /* Output assembly code for a thunk to FUNCTION. */
7924 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7925 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7928 static unsigned int current_thunk_number;
7929 int val_14 = VAL_14_BITS_P (delta);
7934 xoperands[0] = XEXP (DECL_RTL (function), 0);
7935 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7936 xoperands[2] = GEN_INT (delta);
7938 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7939 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7941 /* Output the thunk. We know that the function is in the same
7942 translation unit (i.e., the same space) as the thunk, and that
7943 thunks are output after their method. Thus, we don't need an
7944 external branch to reach the function. With SOM and GAS,
7945 functions and thunks are effectively in different sections.
7946 Thus, we can always use a IA-relative branch and the linker
7947 will add a long branch stub if necessary.
7949 However, we have to be careful when generating PIC code on the
7950 SOM port to ensure that the sequence does not transfer to an
7951 import stub for the target function as this could clobber the
7952 return value saved at SP-24. This would also apply to the
7953 32-bit linux port if the multi-space model is implemented. */
7954 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7955 && !(flag_pic && TREE_PUBLIC (function))
7956 && (TARGET_GAS || last_address < 262132))
7957 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7958 && ((targetm.have_named_sections
7959 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7960 /* The GNU 64-bit linker has rather poor stub management.
7961 So, we use a long branch from thunks that aren't in
7962 the same section as the target function. */
7964 && (DECL_SECTION_NAME (thunk_fndecl)
7965 != DECL_SECTION_NAME (function)))
7966 || ((DECL_SECTION_NAME (thunk_fndecl)
7967 == DECL_SECTION_NAME (function))
7968 && last_address < 262132)))
7969 || (!targetm.have_named_sections && last_address < 262132))))
7972 output_asm_insn ("addil L'%2,%%r26", xoperands);
7974 output_asm_insn ("b %0", xoperands);
7978 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7983 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7987 else if (TARGET_64BIT)
7989 /* We only have one call-clobbered scratch register, so we can't
7990 make use of the delay slot if delta doesn't fit in 14 bits. */
7993 output_asm_insn ("addil L'%2,%%r26", xoperands);
7994 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7997 output_asm_insn ("b,l .+8,%%r1", xoperands);
8001 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8002 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
8006 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
8007 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
8012 output_asm_insn ("bv %%r0(%%r1)", xoperands);
8013 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8018 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
8022 else if (TARGET_PORTABLE_RUNTIME)
8024 output_asm_insn ("ldil L'%0,%%r1", xoperands);
8025 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
8028 output_asm_insn ("addil L'%2,%%r26", xoperands);
8030 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8034 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8039 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8043 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8045 /* The function is accessible from outside this module. The only
8046 way to avoid an import stub between the thunk and function is to
8047 call the function directly with an indirect sequence similar to
8048 that used by $$dyncall. This is possible because $$dyncall acts
8049 as the import stub in an indirect call. */
8050 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
8051 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8052 output_asm_insn ("addil LT'%3,%%r19", xoperands);
8053 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
8054 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8055 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
8056 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
8057 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
8058 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8062 output_asm_insn ("addil L'%2,%%r26", xoperands);
8068 output_asm_insn ("bve (%%r22)", xoperands);
8071 else if (TARGET_NO_SPACE_REGS)
8073 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
8078 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
8079 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
8080 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
8085 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8087 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8091 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8093 if (TARGET_SOM || !TARGET_GAS)
8095 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
8096 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
8100 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8101 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
8105 output_asm_insn ("addil L'%2,%%r26", xoperands);
8107 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8111 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8116 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8123 output_asm_insn ("addil L'%2,%%r26", xoperands);
8125 output_asm_insn ("ldil L'%0,%%r22", xoperands);
8126 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
8130 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8135 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8140 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8142 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8145 output_asm_insn (".align 4", xoperands);
8146 ASM_OUTPUT_LABEL (file, label);
8147 output_asm_insn (".word P'%0", xoperands);
8149 else if (TARGET_SOM && TARGET_GAS)
8152 current_thunk_number++;
8153 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8154 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8155 last_address += nbytes;
8156 update_total_code_bytes (nbytes);
8159 /* Only direct calls to static functions are allowed to be sibling (tail)
8162 This restriction is necessary because some linker generated stubs will
8163 store return pointers into rp' in some cases which might clobber a
8164 live value already in rp'.
8166 In a sibcall the current function and the target function share stack
8167 space. Thus if the path to the current function and the path to the
8168 target function save a value in rp', they save the value into the
8169 same stack slot, which has undesirable consequences.
8171 Because of the deferred binding nature of shared libraries any function
8172 with external scope could be in a different load module and thus require
8173 rp' to be saved when calling that function. So sibcall optimizations
8174 can only be safe for static function.
8176 Note that GCC never needs return value relocations, so we don't have to
8177 worry about static calls with return value relocations (which require
8180 It is safe to perform a sibcall optimization when the target function
8181 will never return. */
8183 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8185 if (TARGET_PORTABLE_RUNTIME)
8188 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8189 single subspace mode and the call is not indirect. As far as I know,
8190 there is no operating system support for the multiple subspace mode.
8191 It might be possible to support indirect calls if we didn't use
8192 $$dyncall (see the indirect sequence generated in output_call). */
8194 return (decl != NULL_TREE);
8196 /* Sibcalls are not ok because the arg pointer register is not a fixed
8197 register. This prevents the sibcall optimization from occurring. In
8198 addition, there are problems with stub placement using GNU ld. This
8199 is because a normal sibcall branch uses a 17-bit relocation while
8200 a regular call branch uses a 22-bit relocation. As a result, more
8201 care needs to be taken in the placement of long-branch stubs. */
8205 /* Sibcalls are only ok within a translation unit. */
8206 return (decl && !TREE_PUBLIC (decl));
8209 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8210 use in fmpyadd instructions. */
8212 fmpyaddoperands (rtx *operands)
8214 enum machine_mode mode = GET_MODE (operands[0]);
8216 /* Must be a floating point mode. */
8217 if (mode != SFmode && mode != DFmode)
8220 /* All modes must be the same. */
8221 if (! (mode == GET_MODE (operands[1])
8222 && mode == GET_MODE (operands[2])
8223 && mode == GET_MODE (operands[3])
8224 && mode == GET_MODE (operands[4])
8225 && mode == GET_MODE (operands[5])))
8228 /* All operands must be registers. */
8229 if (! (GET_CODE (operands[1]) == REG
8230 && GET_CODE (operands[2]) == REG
8231 && GET_CODE (operands[3]) == REG
8232 && GET_CODE (operands[4]) == REG
8233 && GET_CODE (operands[5]) == REG))
8236 /* Only 2 real operands to the addition. One of the input operands must
8237 be the same as the output operand. */
8238 if (! rtx_equal_p (operands[3], operands[4])
8239 && ! rtx_equal_p (operands[3], operands[5]))
8242 /* Inout operand of add cannot conflict with any operands from multiply. */
8243 if (rtx_equal_p (operands[3], operands[0])
8244 || rtx_equal_p (operands[3], operands[1])
8245 || rtx_equal_p (operands[3], operands[2]))
8248 /* multiply cannot feed into addition operands. */
8249 if (rtx_equal_p (operands[4], operands[0])
8250 || rtx_equal_p (operands[5], operands[0]))
8253 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8255 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8256 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8257 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8258 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8259 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8260 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8263 /* Passed. Operands are suitable for fmpyadd. */
8267 #if !defined(USE_COLLECT2)
8269 pa_asm_out_constructor (rtx symbol, int priority)
8271 if (!function_label_operand (symbol, VOIDmode))
8272 hppa_encode_label (symbol);
8274 #ifdef CTORS_SECTION_ASM_OP
8275 default_ctor_section_asm_out_constructor (symbol, priority);
8277 # ifdef TARGET_ASM_NAMED_SECTION
8278 default_named_section_asm_out_constructor (symbol, priority);
8280 default_stabs_asm_out_constructor (symbol, priority);
8286 pa_asm_out_destructor (rtx symbol, int priority)
8288 if (!function_label_operand (symbol, VOIDmode))
8289 hppa_encode_label (symbol);
8291 #ifdef DTORS_SECTION_ASM_OP
8292 default_dtor_section_asm_out_destructor (symbol, priority);
8294 # ifdef TARGET_ASM_NAMED_SECTION
8295 default_named_section_asm_out_destructor (symbol, priority);
8297 default_stabs_asm_out_destructor (symbol, priority);
8303 /* This function places uninitialized global data in the bss section.
8304 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8305 function on the SOM port to prevent uninitialized global data from
8306 being placed in the data section. */
8309 pa_asm_output_aligned_bss (FILE *stream,
8311 unsigned HOST_WIDE_INT size,
8315 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8317 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8318 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8321 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8322 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8325 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8326 ASM_OUTPUT_LABEL (stream, name);
8327 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8330 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8331 that doesn't allow the alignment of global common storage to be directly
8332 specified. The SOM linker aligns common storage based on the rounded
8333 value of the NUM_BYTES parameter in the .comm directive. It's not
8334 possible to use the .align directive as it doesn't affect the alignment
8335 of the label associated with a .comm directive. */
8338 pa_asm_output_aligned_common (FILE *stream,
8340 unsigned HOST_WIDE_INT size,
8343 unsigned int max_common_align;
8345 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8346 if (align > max_common_align)
8348 warning ("alignment (%u) for %s exceeds maximum alignment "
8349 "for global common data. Using %u",
8350 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8351 align = max_common_align;
8356 assemble_name (stream, name);
8357 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8358 MAX (size, align / BITS_PER_UNIT));
8361 /* We can't use .comm for local common storage as the SOM linker effectively
8362 treats the symbol as universal and uses the same storage for local symbols
8363 with the same name in different object files. The .block directive
8364 reserves an uninitialized block of storage. However, it's not common
8365 storage. Fortunately, GCC never requests common storage with the same
8366 name in any given translation unit. */
8369 pa_asm_output_aligned_local (FILE *stream,
8371 unsigned HOST_WIDE_INT size,
8375 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8378 fprintf (stream, "%s", LOCAL_ASM_OP);
8379 assemble_name (stream, name);
8380 fprintf (stream, "\n");
8383 ASM_OUTPUT_LABEL (stream, name);
8384 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8387 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8388 use in fmpysub instructions. */
8390 fmpysuboperands (rtx *operands)
8392 enum machine_mode mode = GET_MODE (operands[0]);
8394 /* Must be a floating point mode. */
8395 if (mode != SFmode && mode != DFmode)
8398 /* All modes must be the same. */
8399 if (! (mode == GET_MODE (operands[1])
8400 && mode == GET_MODE (operands[2])
8401 && mode == GET_MODE (operands[3])
8402 && mode == GET_MODE (operands[4])
8403 && mode == GET_MODE (operands[5])))
8406 /* All operands must be registers. */
8407 if (! (GET_CODE (operands[1]) == REG
8408 && GET_CODE (operands[2]) == REG
8409 && GET_CODE (operands[3]) == REG
8410 && GET_CODE (operands[4]) == REG
8411 && GET_CODE (operands[5]) == REG))
8414 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8415 operation, so operands[4] must be the same as operand[3]. */
8416 if (! rtx_equal_p (operands[3], operands[4]))
8419 /* multiply cannot feed into subtraction. */
8420 if (rtx_equal_p (operands[5], operands[0]))
8423 /* Inout operand of sub cannot conflict with any operands from multiply. */
8424 if (rtx_equal_p (operands[3], operands[0])
8425 || rtx_equal_p (operands[3], operands[1])
8426 || rtx_equal_p (operands[3], operands[2]))
8429 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8431 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8432 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8433 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8434 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8435 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8436 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8439 /* Passed. Operands are suitable for fmpysub. */
8444 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8446 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8447 || GET_CODE (op) == IOR);
8450 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8451 constants for shadd instructions. */
8453 shadd_constant_p (int val)
8455 if (val == 2 || val == 4 || val == 8)
8461 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8462 the valid constant for shadd instructions. */
8464 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8466 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8469 /* Return 1 if OP is valid as a base or index register in a
8473 borx_reg_operand (rtx op, enum machine_mode mode)
8475 if (GET_CODE (op) != REG)
8478 /* We must reject virtual registers as the only expressions that
8479 can be instantiated are REG and REG+CONST. */
8480 if (op == virtual_incoming_args_rtx
8481 || op == virtual_stack_vars_rtx
8482 || op == virtual_stack_dynamic_rtx
8483 || op == virtual_outgoing_args_rtx
8484 || op == virtual_cfa_rtx)
8487 /* While it's always safe to index off the frame pointer, it's not
8488 profitable to do so when the frame pointer is being eliminated. */
8489 if (!reload_completed
8490 && flag_omit_frame_pointer
8491 && !current_function_calls_alloca
8492 && op == frame_pointer_rtx)
8495 return register_operand (op, mode);
8498 /* Return 1 if this operand is anything other than a hard register. */
8501 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8503 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8506 /* Return 1 if INSN branches forward. Should be using insn_addresses
8507 to avoid walking through all the insns... */
8509 forward_branch_p (rtx insn)
8511 rtx label = JUMP_LABEL (insn);
8518 insn = NEXT_INSN (insn);
8521 return (insn == label);
8524 /* Return 1 if OP is an equality comparison, else return 0. */
8526 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8528 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8531 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8533 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8535 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8536 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8539 /* Return 1 if INSN is in the delay slot of a call instruction. */
8541 jump_in_call_delay (rtx insn)
8544 if (GET_CODE (insn) != JUMP_INSN)
8547 if (PREV_INSN (insn)
8548 && PREV_INSN (PREV_INSN (insn))
8549 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8551 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8553 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8554 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8561 /* Output an unconditional move and branch insn. */
8564 output_parallel_movb (rtx *operands, int length)
8566 /* These are the cases in which we win. */
8568 return "mov%I1b,tr %1,%0,%2";
8570 /* None of these cases wins, but they don't lose either. */
8571 if (dbr_sequence_length () == 0)
8573 /* Nothing in the delay slot, fake it by putting the combined
8574 insn (the copy or add) in the delay slot of a bl. */
8575 if (GET_CODE (operands[1]) == CONST_INT)
8576 return "b %2\n\tldi %1,%0";
8578 return "b %2\n\tcopy %1,%0";
8582 /* Something in the delay slot, but we've got a long branch. */
8583 if (GET_CODE (operands[1]) == CONST_INT)
8584 return "ldi %1,%0\n\tb %2";
8586 return "copy %1,%0\n\tb %2";
8590 /* Output an unconditional add and branch insn. */
8593 output_parallel_addb (rtx *operands, int length)
8595 /* To make life easy we want operand0 to be the shared input/output
8596 operand and operand1 to be the readonly operand. */
8597 if (operands[0] == operands[1])
8598 operands[1] = operands[2];
8600 /* These are the cases in which we win. */
8602 return "add%I1b,tr %1,%0,%3";
8604 /* None of these cases win, but they don't lose either. */
8605 if (dbr_sequence_length () == 0)
8607 /* Nothing in the delay slot, fake it by putting the combined
8608 insn (the copy or add) in the delay slot of a bl. */
8609 return "b %3\n\tadd%I1 %1,%0,%0";
8613 /* Something in the delay slot, but we've got a long branch. */
8614 return "add%I1 %1,%0,%0\n\tb %3";
8618 /* Return nonzero if INSN (a jump insn) immediately follows a call
8619 to a named function. This is used to avoid filling the delay slot
8620 of the jump since it can usually be eliminated by modifying RP in
8621 the delay slot of the call. */
8624 following_call (rtx insn)
8626 if (! TARGET_JUMP_IN_DELAY)
8629 /* Find the previous real insn, skipping NOTEs. */
8630 insn = PREV_INSN (insn);
8631 while (insn && GET_CODE (insn) == NOTE)
8632 insn = PREV_INSN (insn);
8634 /* Check for CALL_INSNs and millicode calls. */
8636 && ((GET_CODE (insn) == CALL_INSN
8637 && get_attr_type (insn) != TYPE_DYNCALL)
8638 || (GET_CODE (insn) == INSN
8639 && GET_CODE (PATTERN (insn)) != SEQUENCE
8640 && GET_CODE (PATTERN (insn)) != USE
8641 && GET_CODE (PATTERN (insn)) != CLOBBER
8642 && get_attr_type (insn) == TYPE_MILLI)))
8648 /* We use this hook to perform a PA specific optimization which is difficult
8649 to do in earlier passes.
8651 We want the delay slots of branches within jump tables to be filled.
8652 None of the compiler passes at the moment even has the notion that a
8653 PA jump table doesn't contain addresses, but instead contains actual
8656 Because we actually jump into the table, the addresses of each entry
8657 must stay constant in relation to the beginning of the table (which
8658 itself must stay constant relative to the instruction to jump into
8659 it). I don't believe we can guarantee earlier passes of the compiler
8660 will adhere to those rules.
8662 So, late in the compilation process we find all the jump tables, and
8663 expand them into real code -- e.g. each entry in the jump table vector
8664 will get an appropriate label followed by a jump to the final target.
8666 Reorg and the final jump pass can then optimize these branches and
8667 fill their delay slots. We end up with smaller, more efficient code.
8669 The jump instructions within the table are special; we must be able
8670 to identify them during assembly output (if the jumps don't get filled
8671 we need to emit a nop rather than nullifying the delay slot)). We
8672 identify jumps in switch tables by using insns with the attribute
8673 type TYPE_BTABLE_BRANCH.
8675 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8676 insns. This serves two purposes, first it prevents jump.c from
8677 noticing that the last N entries in the table jump to the instruction
8678 immediately after the table and deleting the jumps. Second, those
8679 insns mark where we should emit .begin_brtab and .end_brtab directives
8680 when using GAS (allows for better link time optimizations). */
8687 remove_useless_addtr_insns (1);
8689 if (pa_cpu < PROCESSOR_8000)
8690 pa_combine_instructions ();
8693 /* This is fairly cheap, so always run it if optimizing. */
8694 if (optimize > 0 && !TARGET_BIG_SWITCH)
8696 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8697 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8699 rtx pattern, tmp, location, label;
8700 unsigned int length, i;
8702 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8703 if (GET_CODE (insn) != JUMP_INSN
8704 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8705 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8708 /* Emit marker for the beginning of the branch table. */
8709 emit_insn_before (gen_begin_brtab (), insn);
8711 pattern = PATTERN (insn);
8712 location = PREV_INSN (insn);
8713 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8715 for (i = 0; i < length; i++)
8717 /* Emit a label before each jump to keep jump.c from
8718 removing this code. */
8719 tmp = gen_label_rtx ();
8720 LABEL_NUSES (tmp) = 1;
8721 emit_label_after (tmp, location);
8722 location = NEXT_INSN (location);
8724 if (GET_CODE (pattern) == ADDR_VEC)
8725 label = XEXP (XVECEXP (pattern, 0, i), 0);
8727 label = XEXP (XVECEXP (pattern, 1, i), 0);
8729 tmp = gen_short_jump (label);
8731 /* Emit the jump itself. */
8732 tmp = emit_jump_insn_after (tmp, location);
8733 JUMP_LABEL (tmp) = label;
8734 LABEL_NUSES (label)++;
8735 location = NEXT_INSN (location);
8737 /* Emit a BARRIER after the jump. */
8738 emit_barrier_after (location);
8739 location = NEXT_INSN (location);
8742 /* Emit marker for the end of the branch table. */
8743 emit_insn_before (gen_end_brtab (), location);
8744 location = NEXT_INSN (location);
8745 emit_barrier_after (location);
8747 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8753 /* Still need brtab marker insns. FIXME: the presence of these
8754 markers disables output of the branch table to readonly memory,
8755 and any alignment directives that might be needed. Possibly,
8756 the begin_brtab insn should be output before the label for the
8757 table. This doesn't matter at the moment since the tables are
8758 always output in the text section. */
8759 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8761 /* Find an ADDR_VEC insn. */
8762 if (GET_CODE (insn) != JUMP_INSN
8763 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8764 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8767 /* Now generate markers for the beginning and end of the
8769 emit_insn_before (gen_begin_brtab (), insn);
8770 emit_insn_after (gen_end_brtab (), insn);
8775 /* The PA has a number of odd instructions which can perform multiple
8776 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8777 it may be profitable to combine two instructions into one instruction
8778 with two outputs. It's not profitable PA2.0 machines because the
8779 two outputs would take two slots in the reorder buffers.
8781 This routine finds instructions which can be combined and combines
8782 them. We only support some of the potential combinations, and we
8783 only try common ways to find suitable instructions.
8785 * addb can add two registers or a register and a small integer
8786 and jump to a nearby (+-8k) location. Normally the jump to the
8787 nearby location is conditional on the result of the add, but by
8788 using the "true" condition we can make the jump unconditional.
8789 Thus addb can perform two independent operations in one insn.
8791 * movb is similar to addb in that it can perform a reg->reg
8792 or small immediate->reg copy and jump to a nearby (+-8k location).
8794 * fmpyadd and fmpysub can perform a FP multiply and either an
8795 FP add or FP sub if the operands of the multiply and add/sub are
8796 independent (there are other minor restrictions). Note both
8797 the fmpy and fadd/fsub can in theory move to better spots according
8798 to data dependencies, but for now we require the fmpy stay at a
8801 * Many of the memory operations can perform pre & post updates
8802 of index registers. GCC's pre/post increment/decrement addressing
8803 is far too simple to take advantage of all the possibilities. This
8804 pass may not be suitable since those insns may not be independent.
8806 * comclr can compare two ints or an int and a register, nullify
8807 the following instruction and zero some other register. This
8808 is more difficult to use as it's harder to find an insn which
8809 will generate a comclr than finding something like an unconditional
8810 branch. (conditional moves & long branches create comclr insns).
8812 * Most arithmetic operations can conditionally skip the next
8813 instruction. They can be viewed as "perform this operation
8814 and conditionally jump to this nearby location" (where nearby
8815 is an insns away). These are difficult to use due to the
8816 branch length restrictions. */
8819 pa_combine_instructions (void)
8823 /* This can get expensive since the basic algorithm is on the
8824 order of O(n^2) (or worse). Only do it for -O2 or higher
8825 levels of optimization. */
8829 /* Walk down the list of insns looking for "anchor" insns which
8830 may be combined with "floating" insns. As the name implies,
8831 "anchor" instructions don't move, while "floating" insns may
8833 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8834 new = make_insn_raw (new);
8836 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8838 enum attr_pa_combine_type anchor_attr;
8839 enum attr_pa_combine_type floater_attr;
8841 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8842 Also ignore any special USE insns. */
8843 if ((GET_CODE (anchor) != INSN
8844 && GET_CODE (anchor) != JUMP_INSN
8845 && GET_CODE (anchor) != CALL_INSN)
8846 || GET_CODE (PATTERN (anchor)) == USE
8847 || GET_CODE (PATTERN (anchor)) == CLOBBER
8848 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8849 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8852 anchor_attr = get_attr_pa_combine_type (anchor);
8853 /* See if anchor is an insn suitable for combination. */
8854 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8855 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8856 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8857 && ! forward_branch_p (anchor)))
8861 for (floater = PREV_INSN (anchor);
8863 floater = PREV_INSN (floater))
8865 if (GET_CODE (floater) == NOTE
8866 || (GET_CODE (floater) == INSN
8867 && (GET_CODE (PATTERN (floater)) == USE
8868 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8871 /* Anything except a regular INSN will stop our search. */
8872 if (GET_CODE (floater) != INSN
8873 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8874 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8880 /* See if FLOATER is suitable for combination with the
8882 floater_attr = get_attr_pa_combine_type (floater);
8883 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8884 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8885 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8886 && floater_attr == PA_COMBINE_TYPE_FMPY))
8888 /* If ANCHOR and FLOATER can be combined, then we're
8889 done with this pass. */
8890 if (pa_can_combine_p (new, anchor, floater, 0,
8891 SET_DEST (PATTERN (floater)),
8892 XEXP (SET_SRC (PATTERN (floater)), 0),
8893 XEXP (SET_SRC (PATTERN (floater)), 1)))
8897 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8898 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8900 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8902 if (pa_can_combine_p (new, anchor, floater, 0,
8903 SET_DEST (PATTERN (floater)),
8904 XEXP (SET_SRC (PATTERN (floater)), 0),
8905 XEXP (SET_SRC (PATTERN (floater)), 1)))
8910 if (pa_can_combine_p (new, anchor, floater, 0,
8911 SET_DEST (PATTERN (floater)),
8912 SET_SRC (PATTERN (floater)),
8913 SET_SRC (PATTERN (floater))))
8919 /* If we didn't find anything on the backwards scan try forwards. */
8921 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8922 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8924 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8926 if (GET_CODE (floater) == NOTE
8927 || (GET_CODE (floater) == INSN
8928 && (GET_CODE (PATTERN (floater)) == USE
8929 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8933 /* Anything except a regular INSN will stop our search. */
8934 if (GET_CODE (floater) != INSN
8935 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8936 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8942 /* See if FLOATER is suitable for combination with the
8944 floater_attr = get_attr_pa_combine_type (floater);
8945 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8946 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8947 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8948 && floater_attr == PA_COMBINE_TYPE_FMPY))
8950 /* If ANCHOR and FLOATER can be combined, then we're
8951 done with this pass. */
8952 if (pa_can_combine_p (new, anchor, floater, 1,
8953 SET_DEST (PATTERN (floater)),
8954 XEXP (SET_SRC (PATTERN (floater)),
8956 XEXP (SET_SRC (PATTERN (floater)),
8963 /* FLOATER will be nonzero if we found a suitable floating
8964 insn for combination with ANCHOR. */
8966 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8967 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8969 /* Emit the new instruction and delete the old anchor. */
8970 emit_insn_before (gen_rtx_PARALLEL
8972 gen_rtvec (2, PATTERN (anchor),
8973 PATTERN (floater))),
8976 PUT_CODE (anchor, NOTE);
8977 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8978 NOTE_SOURCE_FILE (anchor) = 0;
8980 /* Emit a special USE insn for FLOATER, then delete
8981 the floating insn. */
8982 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8983 delete_insn (floater);
8988 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8991 /* Emit the new_jump instruction and delete the old anchor. */
8993 = emit_jump_insn_before (gen_rtx_PARALLEL
8995 gen_rtvec (2, PATTERN (anchor),
8996 PATTERN (floater))),
8999 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
9000 PUT_CODE (anchor, NOTE);
9001 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
9002 NOTE_SOURCE_FILE (anchor) = 0;
9004 /* Emit a special USE insn for FLOATER, then delete
9005 the floating insn. */
9006 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9007 delete_insn (floater);
9015 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
9018 int insn_code_number;
9021 /* Create a PARALLEL with the patterns of ANCHOR and
9022 FLOATER, try to recognize it, then test constraints
9023 for the resulting pattern.
9025 If the pattern doesn't match or the constraints
9026 aren't met keep searching for a suitable floater
9028 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
9029 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
9030 INSN_CODE (new) = -1;
9031 insn_code_number = recog_memoized (new);
9032 if (insn_code_number < 0
9033 || (extract_insn (new), ! constrain_operands (1)))
9047 /* There's up to three operands to consider. One
9048 output and two inputs.
9050 The output must not be used between FLOATER & ANCHOR
9051 exclusive. The inputs must not be set between
9052 FLOATER and ANCHOR exclusive. */
9054 if (reg_used_between_p (dest, start, end))
9057 if (reg_set_between_p (src1, start, end))
9060 if (reg_set_between_p (src2, start, end))
9063 /* If we get here, then everything is good. */
9067 /* Return nonzero if references for INSN are delayed.
9069 Millicode insns are actually function calls with some special
9070 constraints on arguments and register usage.
9072 Millicode calls always expect their arguments in the integer argument
9073 registers, and always return their result in %r29 (ret1). They
9074 are expected to clobber their arguments, %r1, %r29, and the return
9075 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9077 This function tells reorg that the references to arguments and
9078 millicode calls do not appear to happen until after the millicode call.
9079 This allows reorg to put insns which set the argument registers into the
9080 delay slot of the millicode call -- thus they act more like traditional
9083 Note we cannot consider side effects of the insn to be delayed because
9084 the branch and link insn will clobber the return pointer. If we happened
9085 to use the return pointer in the delay slot of the call, then we lose.
9087 get_attr_type will try to recognize the given insn, so make sure to
9088 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9091 insn_refs_are_delayed (rtx insn)
9093 return ((GET_CODE (insn) == INSN
9094 && GET_CODE (PATTERN (insn)) != SEQUENCE
9095 && GET_CODE (PATTERN (insn)) != USE
9096 && GET_CODE (PATTERN (insn)) != CLOBBER
9097 && get_attr_type (insn) == TYPE_MILLI));
9100 /* On the HP-PA the value is found in register(s) 28(-29), unless
9101 the mode is SF or DF. Then the value is returned in fr4 (32).
9103 This must perform the same promotions as PROMOTE_MODE, else
9104 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
9106 Small structures must be returned in a PARALLEL on PA64 in order
9107 to match the HP Compiler ABI. */
9110 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
9112 enum machine_mode valmode;
9114 /* Aggregates with a size less than or equal to 128 bits are returned
9115 in GR 28(-29). They are left justified. The pad bits are undefined.
9116 Larger aggregates are returned in memory. */
9117 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
9121 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9123 for (i = 0; i < ub; i++)
9125 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9126 gen_rtx_REG (DImode, 28 + i),
9131 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9134 if ((INTEGRAL_TYPE_P (valtype)
9135 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
9136 || POINTER_TYPE_P (valtype))
9137 valmode = word_mode;
9139 valmode = TYPE_MODE (valtype);
9141 if (TREE_CODE (valtype) == REAL_TYPE
9142 && TYPE_MODE (valtype) != TFmode
9143 && !TARGET_SOFT_FLOAT)
9144 return gen_rtx_REG (valmode, 32);
9146 return gen_rtx_REG (valmode, 28);
9149 /* Return the location of a parameter that is passed in a register or NULL
9150 if the parameter has any component that is passed in memory.
9152 This is new code and will be pushed to into the net sources after
9155 ??? We might want to restructure this so that it looks more like other
9158 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
9159 int named ATTRIBUTE_UNUSED)
9161 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9168 if (mode == VOIDmode)
9171 arg_size = FUNCTION_ARG_SIZE (mode, type);
9173 /* If this arg would be passed partially or totally on the stack, then
9174 this routine should return zero. pa_arg_partial_bytes will
9175 handle arguments which are split between regs and stack slots if
9176 the ABI mandates split arguments. */
9179 /* The 32-bit ABI does not split arguments. */
9180 if (cum->words + arg_size > max_arg_words)
9186 alignment = cum->words & 1;
9187 if (cum->words + alignment >= max_arg_words)
9191 /* The 32bit ABIs and the 64bit ABIs are rather different,
9192 particularly in their handling of FP registers. We might
9193 be able to cleverly share code between them, but I'm not
9194 going to bother in the hope that splitting them up results
9195 in code that is more easily understood. */
9199 /* Advance the base registers to their current locations.
9201 Remember, gprs grow towards smaller register numbers while
9202 fprs grow to higher register numbers. Also remember that
9203 although FP regs are 32-bit addressable, we pretend that
9204 the registers are 64-bits wide. */
9205 gpr_reg_base = 26 - cum->words;
9206 fpr_reg_base = 32 + cum->words;
9208 /* Arguments wider than one word and small aggregates need special
9212 || (type && AGGREGATE_TYPE_P (type)))
9214 /* Double-extended precision (80-bit), quad-precision (128-bit)
9215 and aggregates including complex numbers are aligned on
9216 128-bit boundaries. The first eight 64-bit argument slots
9217 are associated one-to-one, with general registers r26
9218 through r19, and also with floating-point registers fr4
9219 through fr11. Arguments larger than one word are always
9220 passed in general registers.
9222 Using a PARALLEL with a word mode register results in left
9223 justified data on a big-endian target. */
9226 int i, offset = 0, ub = arg_size;
9228 /* Align the base register. */
9229 gpr_reg_base -= alignment;
9231 ub = MIN (ub, max_arg_words - cum->words - alignment);
9232 for (i = 0; i < ub; i++)
9234 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9235 gen_rtx_REG (DImode, gpr_reg_base),
9241 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9246 /* If the argument is larger than a word, then we know precisely
9247 which registers we must use. */
9261 /* Structures 5 to 8 bytes in size are passed in the general
9262 registers in the same manner as other non floating-point
9263 objects. The data is right-justified and zero-extended
9264 to 64 bits. This is opposite to the normal justification
9265 used on big endian targets and requires special treatment.
9266 We now define BLOCK_REG_PADDING to pad these objects. */
9267 if (mode == BLKmode)
9269 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9270 gen_rtx_REG (DImode, gpr_reg_base),
9272 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
9277 /* We have a single word (32 bits). A simple computation
9278 will get us the register #s we need. */
9279 gpr_reg_base = 26 - cum->words;
9280 fpr_reg_base = 32 + 2 * cum->words;
9284 /* Determine if the argument needs to be passed in both general and
9285 floating point registers. */
9286 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9287 /* If we are doing soft-float with portable runtime, then there
9288 is no need to worry about FP regs. */
9289 && !TARGET_SOFT_FLOAT
9290 /* The parameter must be some kind of float, else we can just
9291 pass it in integer registers. */
9292 && FLOAT_MODE_P (mode)
9293 /* The target function must not have a prototype. */
9294 && cum->nargs_prototype <= 0
9295 /* libcalls do not need to pass items in both FP and general
9297 && type != NULL_TREE
9298 /* All this hair applies to "outgoing" args only. This includes
9299 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9301 /* Also pass outgoing floating arguments in both registers in indirect
9302 calls with the 32 bit ABI and the HP assembler since there is no
9303 way to the specify argument locations in static functions. */
9308 && FLOAT_MODE_P (mode)))
9314 gen_rtx_EXPR_LIST (VOIDmode,
9315 gen_rtx_REG (mode, fpr_reg_base),
9317 gen_rtx_EXPR_LIST (VOIDmode,
9318 gen_rtx_REG (mode, gpr_reg_base),
9323 /* See if we should pass this parameter in a general register. */
9324 if (TARGET_SOFT_FLOAT
9325 /* Indirect calls in the normal 32bit ABI require all arguments
9326 to be passed in general registers. */
9327 || (!TARGET_PORTABLE_RUNTIME
9331 /* If the parameter is not a floating point parameter, then
9332 it belongs in GPRs. */
9333 || !FLOAT_MODE_P (mode))
9334 retval = gen_rtx_REG (mode, gpr_reg_base);
9336 retval = gen_rtx_REG (mode, fpr_reg_base);
9342 /* If this arg would be passed totally in registers or totally on the stack,
9343 then this routine should return zero. */
9346 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9347 tree type, bool named ATTRIBUTE_UNUSED)
9349 unsigned int max_arg_words = 8;
9350 unsigned int offset = 0;
9355 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9358 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9359 /* Arg fits fully into registers. */
9361 else if (cum->words + offset >= max_arg_words)
9362 /* Arg fully on the stack. */
9366 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9370 /* Return 1 if this is a comparison operator. This allows the use of
9371 MATCH_OPERATOR to recognize all the branch insns. */
9374 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9376 return ((mode == VOIDmode || GET_MODE (op) == mode)
9377 && (GET_CODE (op) == EQ
9378 || GET_CODE (op) == NE
9379 || GET_CODE (op) == GT
9380 || GET_CODE (op) == GTU
9381 || GET_CODE (op) == GE
9382 || GET_CODE (op) == LT
9383 || GET_CODE (op) == LE
9384 || GET_CODE (op) == LEU));
9387 /* Return a string to output before text in the current function.
9389 This function is only used with SOM. Because we don't support
9390 named subspaces, we can only create a new subspace or switch back
9391 to the default text subspace. */
9393 som_text_section_asm_op (void)
9400 if (cfun && !cfun->machine->in_nsubspa)
9402 /* We only want to emit a .nsubspa directive once at the
9403 start of the function. */
9404 cfun->machine->in_nsubspa = 1;
9406 /* Create a new subspace for the text. This provides
9407 better stub placement and one-only functions. */
9409 && DECL_ONE_ONLY (cfun->decl)
9410 && !DECL_WEAK (cfun->decl))
9412 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
9414 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
9418 /* There isn't a current function or the body of the current
9419 function has been completed. So, we are changing to the
9420 text section to output debugging information. Do this in
9421 the default text section. We need to forget that we are
9422 in the text section so that the function text_section in
9423 varasm.c will call us the next time around. */
9428 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
9431 /* On hpux10, the linker will give an error if we have a reference
9432 in the read-only data section to a symbol defined in a shared
9433 library. Therefore, expressions that might require a reloc can
9434 not be placed in the read-only data section. */
9437 pa_select_section (tree exp, int reloc,
9438 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9440 if (TREE_CODE (exp) == VAR_DECL
9441 && TREE_READONLY (exp)
9442 && !TREE_THIS_VOLATILE (exp)
9443 && DECL_INITIAL (exp)
9444 && (DECL_INITIAL (exp) == error_mark_node
9445 || TREE_CONSTANT (DECL_INITIAL (exp)))
9449 && DECL_ONE_ONLY (exp)
9450 && !DECL_WEAK (exp))
9451 som_one_only_readonly_data_section ();
9453 readonly_data_section ();
9455 else if (CONSTANT_CLASS_P (exp) && !reloc)
9456 readonly_data_section ();
9458 && TREE_CODE (exp) == VAR_DECL
9459 && DECL_ONE_ONLY (exp)
9460 && !DECL_WEAK (exp))
9461 som_one_only_data_section ();
9467 pa_globalize_label (FILE *stream, const char *name)
9469 /* We only handle DATA objects here, functions are globalized in
9470 ASM_DECLARE_FUNCTION_NAME. */
9471 if (! FUNCTION_NAME_P (name))
9473 fputs ("\t.EXPORT ", stream);
9474 assemble_name (stream, name);
9475 fputs (",DATA\n", stream);
9479 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9482 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9483 int incoming ATTRIBUTE_UNUSED)
9485 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9488 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9491 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9493 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9494 PA64 ABI says that objects larger than 128 bits are returned in memory.
9495 Note, int_size_in_bytes can return -1 if the size of the object is
9496 variable or larger than the maximum value that can be expressed as
9497 a HOST_WIDE_INT. It can also return zero for an empty type. The
9498 simplest way to handle variable and empty types is to pass them in
9499 memory. This avoids problems in defining the boundaries of argument
9500 slots, allocating registers, etc. */
9501 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9502 || int_size_in_bytes (type) <= 0);
9505 /* Structure to hold declaration and name of external symbols that are
9506 emitted by GCC. We generate a vector of these symbols and output them
9507 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9508 This avoids putting out names that are never really used. */
9510 struct extern_symbol GTY(())
9515 typedef struct extern_symbol *extern_symbol;
9517 /* Define gc'd vector type for extern_symbol. */
9518 DEF_VEC_GC_P(extern_symbol);
9520 /* Vector of extern_symbol pointers. */
9521 static GTY(()) VEC(extern_symbol) *extern_symbols;
9523 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9524 /* Mark DECL (name NAME) as an external reference (assembler output
9525 file FILE). This saves the names to output at the end of the file
9526 if actually referenced. */
9529 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9531 extern_symbol p = ggc_alloc (sizeof (struct extern_symbol));
9533 gcc_assert (file == asm_out_file);
9536 VEC_safe_push (extern_symbol, extern_symbols, p);
9539 /* Output text required at the end of an assembler file.
9540 This includes deferred plabels and .import directives for
9541 all external symbols that were actually referenced. */
9544 pa_hpux_file_end (void)
9549 output_deferred_plabels ();
9551 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9553 tree decl = p->decl;
9555 if (!TREE_ASM_WRITTEN (decl)
9556 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9557 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9560 extern_symbols = NULL;