1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 static void restore_unscaled_index_insn_codes PROTO((rtx));
43 static void record_unscaled_index_insn_codes PROTO((rtx));
44 static void pa_combine_instructions PROTO((rtx));
45 static int pa_can_combine_p PROTO((rtx, rtx, rtx, int, rtx, rtx, rtx));
46 static int forward_branch_p PROTO((rtx));
47 static int shadd_constant_p PROTO((int));
49 /* Save the operands last given to a compare for use when we
50 generate a scc or bcc insn. */
52 rtx hppa_compare_op0, hppa_compare_op1;
53 enum cmp_type hppa_branch_type;
55 /* Which cpu we are scheduling for. */
56 enum processor_type pa_cpu;
58 /* String to hold which cpu we are scheduling for. */
61 /* Which architecture we are generating code for. */
62 enum architecture_type pa_arch;
64 /* String to hold which architecture we are generating code for. */
67 /* Set by the FUNCTION_PROFILER macro. */
68 int hp_profile_labelno;
70 /* Counts for the number of callee-saved general and floating point
71 registers which were saved by the current function's prologue. */
72 static int gr_saved, fr_saved;
74 /* Whether or not the current function uses an out-of-line prologue
76 static int out_of_line_prologue_epilogue;
78 static rtx find_addr_reg ();
80 /* Keep track of the number of bytes we have output in the CODE subspaces
81 during this compilation so we'll know when to emit inline long-calls. */
83 unsigned int total_code_bytes;
85 /* Variables to handle plabels that we discover are necessary at assembly
86 output time. They are output after the current function. */
88 struct deferred_plabel
92 } *deferred_plabels = 0;
93 int n_deferred_plabels = 0;
95 /* Array indexed by INSN_UIDs holding the INSN_CODE of an insn which
96 uses an unscaled indexed address before delay slot scheduling. */
97 static int *unscaled_index_insn_codes;
99 /* Upper bound for the array. */
100 static int max_unscaled_index_insn_codes_uid;
105 /* Default to 7100LC scheduling. */
106 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
108 pa_cpu_string = "7100";
109 pa_cpu = PROCESSOR_7100;
111 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
113 pa_cpu_string = "700";
114 pa_cpu = PROCESSOR_700;
116 else if (pa_cpu_string == NULL
117 || ! strcmp (pa_cpu_string, "7100LC"))
119 pa_cpu_string = "7100LC";
120 pa_cpu = PROCESSOR_7100LC;
122 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
124 pa_cpu_string = "7200";
125 pa_cpu = PROCESSOR_7200;
127 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
129 pa_cpu_string = "8000";
130 pa_cpu = PROCESSOR_8000;
134 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
137 /* Set the instruction set architecture. */
138 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
140 pa_arch_string = "1.0";
141 pa_arch = ARCHITECTURE_10;
142 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
144 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
146 pa_arch_string = "1.1";
147 pa_arch = ARCHITECTURE_11;
148 target_flags &= ~MASK_PA_20;
149 target_flags |= MASK_PA_11;
151 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
153 pa_arch_string = "2.0";
154 pa_arch = ARCHITECTURE_20;
155 target_flags |= MASK_PA_11 | MASK_PA_20;
157 else if (pa_arch_string)
159 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
162 if (flag_pic && TARGET_PORTABLE_RUNTIME)
164 warning ("PIC code generation is not supported in the portable runtime model\n");
167 if (flag_pic && (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS))
169 warning ("PIC code generation is not compatible with fast indirect calls\n");
172 if (flag_pic && profile_flag)
174 warning ("PIC code generation is not compatible with profiling\n");
177 if (TARGET_SPACE && (flag_pic || profile_flag))
179 warning ("Out of line entry/exit sequences are not compatible\n");
180 warning ("with PIC or profiling\n");
183 if (! TARGET_GAS && write_symbols != NO_DEBUG)
185 warning ("-g is only supported when using GAS on this processor,");
186 warning ("-g option disabled.");
187 write_symbols = NO_DEBUG;
192 /* Return non-zero only if OP is a register of mode MODE,
195 reg_or_0_operand (op, mode)
197 enum machine_mode mode;
199 return (op == CONST0_RTX (mode) || register_operand (op, mode));
202 /* Return non-zero if OP is suitable for use in a call to a named
205 (???) For 2.5 try to eliminate either call_operand_address or
206 function_label_operand, they perform very similar functions. */
208 call_operand_address (op, mode)
210 enum machine_mode mode ATTRIBUTE_UNUSED;
212 return (CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
215 /* Return 1 if X contains a symbolic expression. We know these
216 expressions will have one of a few well defined forms, so
217 we need only check those forms. */
219 symbolic_expression_p (x)
223 /* Strip off any HIGH. */
224 if (GET_CODE (x) == HIGH)
227 return (symbolic_operand (x, VOIDmode));
231 symbolic_operand (op, mode)
233 enum machine_mode mode ATTRIBUTE_UNUSED;
235 switch (GET_CODE (op))
242 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
243 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
244 && GET_CODE (XEXP (op, 1)) == CONST_INT);
250 /* Return truth value of statement that OP is a symbolic memory
251 operand of mode MODE. */
254 symbolic_memory_operand (op, mode)
256 enum machine_mode mode ATTRIBUTE_UNUSED;
258 if (GET_CODE (op) == SUBREG)
259 op = SUBREG_REG (op);
260 if (GET_CODE (op) != MEM)
263 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
264 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
267 /* Return 1 if the operand is either a register or a memory operand that is
271 reg_or_nonsymb_mem_operand (op, mode)
273 enum machine_mode mode;
275 if (register_operand (op, mode))
278 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
284 /* Return 1 if the operand is either a register, zero, or a memory operand
285 that is not symbolic. */
288 reg_or_0_or_nonsymb_mem_operand (op, mode)
290 enum machine_mode mode;
292 if (register_operand (op, mode))
295 if (op == CONST0_RTX (mode))
298 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
304 /* Accept any constant that can be moved in one instructions into a
307 cint_ok_for_move (intval)
308 HOST_WIDE_INT intval;
310 /* OK if ldo, ldil, or zdepi, can be used. */
311 return (VAL_14_BITS_P (intval) || (intval & 0x7ff) == 0
312 || zdepi_cint_p (intval));
315 /* Accept anything that can be moved in one instruction into a general
318 move_operand (op, mode)
320 enum machine_mode mode;
322 if (register_operand (op, mode))
325 if (GET_CODE (op) == CONSTANT_P_RTX)
328 if (GET_CODE (op) == CONST_INT)
329 return cint_ok_for_move (INTVAL (op));
331 if (GET_CODE (op) == SUBREG)
332 op = SUBREG_REG (op);
333 if (GET_CODE (op) != MEM)
337 if (GET_CODE (op) == LO_SUM)
338 return (register_operand (XEXP (op, 0), Pmode)
339 && CONSTANT_P (XEXP (op, 1)));
341 /* Since move_operand is only used for source operands, we can always
342 allow scaled indexing! */
343 if (! TARGET_DISABLE_INDEXING
344 && GET_CODE (op) == PLUS
345 && ((GET_CODE (XEXP (op, 0)) == MULT
346 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
347 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
348 && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
349 && GET_CODE (XEXP (op, 1)) == REG)
350 || (GET_CODE (XEXP (op, 1)) == MULT
351 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
352 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
353 && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
354 && GET_CODE (XEXP (op, 0)) == REG)))
357 return memory_address_p (mode, op);
360 /* Accept REG and any CONST_INT that can be moved in one instruction into a
363 reg_or_cint_move_operand (op, mode)
365 enum machine_mode mode;
367 if (register_operand (op, mode))
370 if (GET_CODE (op) == CONST_INT)
371 return cint_ok_for_move (INTVAL (op));
377 pic_label_operand (op, mode)
379 enum machine_mode mode ATTRIBUTE_UNUSED;
384 switch (GET_CODE (op))
390 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
391 && GET_CODE (XEXP (op, 1)) == CONST_INT);
398 fp_reg_operand (op, mode)
400 enum machine_mode mode ATTRIBUTE_UNUSED;
402 return reg_renumber && FP_REG_P (op);
407 /* Return truth value of whether OP can be used as an operand in a
408 three operand arithmetic insn that accepts registers of mode MODE
409 or 14-bit signed integers. */
411 arith_operand (op, mode)
413 enum machine_mode mode;
415 return (register_operand (op, mode)
416 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
419 /* Return truth value of whether OP can be used as an operand in a
420 three operand arithmetic insn that accepts registers of mode MODE
421 or 11-bit signed integers. */
423 arith11_operand (op, mode)
425 enum machine_mode mode;
427 return (register_operand (op, mode)
428 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
431 /* A constant integer suitable for use in a PRE_MODIFY memory
434 pre_cint_operand (op, mode)
436 enum machine_mode mode ATTRIBUTE_UNUSED;
438 return (GET_CODE (op) == CONST_INT
439 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
442 /* A constant integer suitable for use in a POST_MODIFY memory
445 post_cint_operand (op, mode)
447 enum machine_mode mode ATTRIBUTE_UNUSED;
449 return (GET_CODE (op) == CONST_INT
450 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
454 arith_double_operand (op, mode)
456 enum machine_mode mode;
458 return (register_operand (op, mode)
459 || (GET_CODE (op) == CONST_DOUBLE
460 && GET_MODE (op) == mode
461 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
462 && ((CONST_DOUBLE_HIGH (op) >= 0)
463 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
466 /* Return truth value of whether OP is a integer which fits the
467 range constraining immediate operands in three-address insns, or
468 is an integer register. */
471 ireg_or_int5_operand (op, mode)
473 enum machine_mode mode ATTRIBUTE_UNUSED;
475 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
476 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
479 /* Return truth value of whether OP is a integer which fits the
480 range constraining immediate operands in three-address insns. */
483 int5_operand (op, mode)
485 enum machine_mode mode ATTRIBUTE_UNUSED;
487 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
491 uint5_operand (op, mode)
493 enum machine_mode mode ATTRIBUTE_UNUSED;
495 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
499 int11_operand (op, mode)
501 enum machine_mode mode ATTRIBUTE_UNUSED;
503 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
507 uint32_operand (op, mode)
509 enum machine_mode mode ATTRIBUTE_UNUSED;
511 #if HOST_BITS_PER_WIDE_INT > 32
512 /* All allowed constants will fit a CONST_INT. */
513 return (GET_CODE (op) == CONST_INT
514 && (INTVAL (op) >= 0 && INTVAL (op) < 0x100000000L));
516 return (GET_CODE (op) == CONST_INT
517 || (GET_CODE (op) == CONST_DOUBLE
518 && CONST_DOUBLE_HIGH (op) == 0));
523 arith5_operand (op, mode)
525 enum machine_mode mode;
527 return register_operand (op, mode) || int5_operand (op, mode);
530 /* True iff zdepi can be used to generate this CONST_INT. */
533 unsigned HOST_WIDE_INT x;
535 unsigned HOST_WIDE_INT lsb_mask, t;
537 /* This might not be obvious, but it's at least fast.
538 This function is critical; we don't have the time loops would take. */
540 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
541 /* Return true iff t is a power of two. */
542 return ((t & (t - 1)) == 0);
545 /* True iff depi or extru can be used to compute (reg & mask).
546 Accept bit pattern like these:
552 unsigned HOST_WIDE_INT mask;
555 mask += mask & -mask;
556 return (mask & (mask - 1)) == 0;
559 /* True iff depi or extru can be used to compute (reg & OP). */
561 and_operand (op, mode)
563 enum machine_mode mode;
565 return (register_operand (op, mode)
566 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
569 /* True iff depi can be used to compute (reg | MASK). */
572 unsigned HOST_WIDE_INT mask;
574 mask += mask & -mask;
575 return (mask & (mask - 1)) == 0;
578 /* True iff depi can be used to compute (reg | OP). */
580 ior_operand (op, mode)
582 enum machine_mode mode ATTRIBUTE_UNUSED;
584 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
588 lhs_lshift_operand (op, mode)
590 enum machine_mode mode;
592 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
595 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
596 Such values can be the left hand side x in (x << r), using the zvdepi
599 lhs_lshift_cint_operand (op, mode)
601 enum machine_mode mode ATTRIBUTE_UNUSED;
603 unsigned HOST_WIDE_INT x;
604 if (GET_CODE (op) != CONST_INT)
606 x = INTVAL (op) >> 4;
607 return (x & (x + 1)) == 0;
611 arith32_operand (op, mode)
613 enum machine_mode mode;
615 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
619 pc_or_label_operand (op, mode)
621 enum machine_mode mode ATTRIBUTE_UNUSED;
623 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
626 /* Legitimize PIC addresses. If the address is already
627 position-independent, we return ORIG. Newly generated
628 position-independent addresses go to REG. If we need more
629 than one register, we lose. */
632 legitimize_pic_address (orig, mode, reg)
634 enum machine_mode mode ATTRIBUTE_UNUSED;
638 /* Labels need special handling. */
639 if (pic_label_operand (orig))
641 emit_insn (gen_pic_load_label (reg, orig));
642 current_function_uses_pic_offset_table = 1;
645 if (GET_CODE (orig) == SYMBOL_REF)
652 emit_insn (gen_pic2_highpart (reg, pic_offset_table_rtx, orig));
654 = gen_rtx_MEM (Pmode,
655 gen_rtx_LO_SUM (Pmode, reg,
656 gen_rtx_UNSPEC (SImode,
661 pic_ref = gen_rtx_MEM (Pmode,
663 pic_offset_table_rtx, orig));
664 current_function_uses_pic_offset_table = 1;
665 RTX_UNCHANGING_P (pic_ref) = 1;
666 emit_move_insn (reg, pic_ref);
669 else if (GET_CODE (orig) == CONST)
673 if (GET_CODE (XEXP (orig, 0)) == PLUS
674 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
680 if (GET_CODE (XEXP (orig, 0)) == PLUS)
682 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
683 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
684 base == reg ? 0 : reg);
687 if (GET_CODE (orig) == CONST_INT)
689 if (INT_14_BITS (orig))
690 return plus_constant_for_output (base, INTVAL (orig));
691 orig = force_reg (Pmode, orig);
693 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
694 /* Likewise, should we set special REG_NOTEs here? */
699 /* Try machine-dependent ways of modifying an illegitimate address
700 to be legitimate. If we find one, return the new, valid address.
701 This macro is used in only one place: `memory_address' in explow.c.
703 OLDX is the address as it was before break_out_memory_refs was called.
704 In some cases it is useful to look at this to decide what needs to be done.
706 MODE and WIN are passed so that this macro can use
707 GO_IF_LEGITIMATE_ADDRESS.
709 It is always safe for this macro to do nothing. It exists to recognize
710 opportunities to optimize the output.
712 For the PA, transform:
714 memory(X + <large int>)
718 if (<large int> & mask) >= 16
719 Y = (<large int> & ~mask) + mask + 1 Round up.
721 Y = (<large int> & ~mask) Round down.
723 memory (Z + (<large int> - Y));
725 This is for CSE to find several similar references, and only use one Z.
727 X can either be a SYMBOL_REF or REG, but because combine can not
728 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
729 D will not fit in 14 bits.
731 MODE_FLOAT references allow displacements which fit in 5 bits, so use
734 MODE_INT references allow displacements which fit in 14 bits, so use
737 This relies on the fact that most mode MODE_FLOAT references will use FP
738 registers and most mode MODE_INT references will use integer registers.
739 (In the rare case of an FP register used in an integer MODE, we depend
740 on secondary reloads to clean things up.)
743 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
744 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
745 addressing modes to be used).
747 Put X and Z into registers. Then put the entire expression into
751 hppa_legitimize_address (x, oldx, mode)
752 rtx x, oldx ATTRIBUTE_UNUSED;
753 enum machine_mode mode;
758 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
760 /* Strip off CONST. */
761 if (GET_CODE (x) == CONST)
764 /* Special case. Get the SYMBOL_REF into a register and use indexing.
765 That should always be safe. */
766 if (GET_CODE (x) == PLUS
767 && GET_CODE (XEXP (x, 0)) == REG
768 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
770 rtx reg = force_reg (SImode, XEXP (x, 1));
771 return force_reg (SImode, gen_rtx_PLUS (SImode, reg, XEXP (x, 0)));
774 /* Note we must reject symbols which represent function addresses
775 since the assembler/linker can't handle arithmetic on plabels. */
776 if (GET_CODE (x) == PLUS
777 && GET_CODE (XEXP (x, 1)) == CONST_INT
778 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
779 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
780 || GET_CODE (XEXP (x, 0)) == REG))
782 rtx int_part, ptr_reg;
784 int offset = INTVAL (XEXP (x, 1));
785 int mask = GET_MODE_CLASS (mode) == MODE_FLOAT ? 0x1f : 0x3fff;
787 /* Choose which way to round the offset. Round up if we
788 are >= halfway to the next boundary. */
789 if ((offset & mask) >= ((mask + 1) / 2))
790 newoffset = (offset & ~ mask) + mask + 1;
792 newoffset = (offset & ~ mask);
794 /* If the newoffset will not fit in 14 bits (ldo), then
795 handling this would take 4 or 5 instructions (2 to load
796 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
797 add the new offset and the SYMBOL_REF.) Combine can
798 not handle 4->2 or 5->2 combinations, so do not create
800 if (! VAL_14_BITS_P (newoffset)
801 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
804 = gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (Pmode,
806 GEN_INT (newoffset)));
809 gen_rtx_HIGH (Pmode, const_part));
812 gen_rtx_LO_SUM (Pmode, tmp_reg, const_part));
816 if (! VAL_14_BITS_P (newoffset))
817 int_part = force_reg (Pmode, GEN_INT (newoffset));
819 int_part = GEN_INT (newoffset);
821 ptr_reg = force_reg (Pmode,
823 force_reg (Pmode, XEXP (x, 0)),
826 return plus_constant (ptr_reg, offset - newoffset);
829 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
831 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
832 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
833 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
834 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
835 || GET_CODE (XEXP (x, 1)) == SUBREG)
836 && GET_CODE (XEXP (x, 1)) != CONST)
838 int val = INTVAL (XEXP (XEXP (x, 0), 1));
842 if (GET_CODE (reg1) != REG)
843 reg1 = force_reg (Pmode, force_operand (reg1, 0));
845 reg2 = XEXP (XEXP (x, 0), 0);
846 if (GET_CODE (reg2) != REG)
847 reg2 = force_reg (Pmode, force_operand (reg2, 0));
849 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
850 gen_rtx_MULT (Pmode, reg2,
855 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
857 Only do so for floating point modes since this is more speculative
858 and we lose if it's an integer store. */
859 if (GET_CODE (x) == PLUS
860 && GET_CODE (XEXP (x, 0)) == PLUS
861 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
862 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
863 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
864 && (mode == SFmode || mode == DFmode))
867 /* First, try and figure out what to use as a base register. */
868 rtx reg1, reg2, base, idx, orig_base;
870 reg1 = XEXP (XEXP (x, 0), 1);
875 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
876 then emit_move_sequence will turn on REGNO_POINTER_FLAG so we'll
877 know it's a base register below. */
878 if (GET_CODE (reg1) != REG)
879 reg1 = force_reg (Pmode, force_operand (reg1, 0));
881 if (GET_CODE (reg2) != REG)
882 reg2 = force_reg (Pmode, force_operand (reg2, 0));
884 /* Figure out what the base and index are. */
886 if (GET_CODE (reg1) == REG
887 && REGNO_POINTER_FLAG (REGNO (reg1)))
890 orig_base = XEXP (XEXP (x, 0), 1);
891 idx = gen_rtx_PLUS (Pmode,
893 XEXP (XEXP (XEXP (x, 0), 0), 0),
894 XEXP (XEXP (XEXP (x, 0), 0), 1)),
897 else if (GET_CODE (reg2) == REG
898 && REGNO_POINTER_FLAG (REGNO (reg2)))
901 orig_base = XEXP (x, 1);
908 /* If the index adds a large constant, try to scale the
909 constant so that it can be loaded with only one insn. */
910 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
911 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
912 / INTVAL (XEXP (XEXP (idx, 0), 1)))
913 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
915 /* Divide the CONST_INT by the scale factor, then add it to A. */
916 int val = INTVAL (XEXP (idx, 1));
918 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
919 reg1 = XEXP (XEXP (idx, 0), 0);
920 if (GET_CODE (reg1) != REG)
921 reg1 = force_reg (Pmode, force_operand (reg1, 0));
923 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
925 /* We can now generate a simple scaled indexed address. */
926 return force_reg (Pmode,
928 gen_rtx_MULT (Pmode, reg1,
929 XEXP (XEXP (idx, 0), 1)),
933 /* If B + C is still a valid base register, then add them. */
934 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
935 && INTVAL (XEXP (idx, 1)) <= 4096
936 && INTVAL (XEXP (idx, 1)) >= -4096)
938 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
941 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
943 reg2 = XEXP (XEXP (idx, 0), 0);
944 if (GET_CODE (reg2) != CONST_INT)
945 reg2 = force_reg (Pmode, force_operand (reg2, 0));
947 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
948 gen_rtx_MULT (Pmode, reg2,
953 /* Get the index into a register, then add the base + index and
954 return a register holding the result. */
956 /* First get A into a register. */
957 reg1 = XEXP (XEXP (idx, 0), 0);
958 if (GET_CODE (reg1) != REG)
959 reg1 = force_reg (Pmode, force_operand (reg1, 0));
961 /* And get B into a register. */
962 reg2 = XEXP (idx, 1);
963 if (GET_CODE (reg2) != REG)
964 reg2 = force_reg (Pmode, force_operand (reg2, 0));
966 reg1 = force_reg (Pmode,
968 gen_rtx_MULT (Pmode, reg1,
969 XEXP (XEXP (idx, 0), 1)),
972 /* Add the result to our base register and return. */
973 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
977 /* Uh-oh. We might have an address for x[n-100000]. This needs
978 special handling to avoid creating an indexed memory address
979 with x-100000 as the base.
981 If the constant part is small enough, then it's still safe because
982 there is a guard page at the beginning and end of the data segment.
984 Scaled references are common enough that we want to try and rearrange the
985 terms so that we can use indexing for these addresses too. Only
986 do the optimization for floatint point modes. */
988 if (GET_CODE (x) == PLUS
989 && symbolic_expression_p (XEXP (x, 1)))
991 /* Ugly. We modify things here so that the address offset specified
992 by the index expression is computed first, then added to x to form
993 the entire address. */
995 rtx regx1, regx2, regy1, regy2, y;
997 /* Strip off any CONST. */
999 if (GET_CODE (y) == CONST)
1002 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1004 /* See if this looks like
1005 (plus (mult (reg) (shadd_const))
1006 (const (plus (symbol_ref) (const_int))))
1008 Where const_int is small. In that case the const
1009 expression is a valid pointer for indexing.
1011 If const_int is big, but can be divided evenly by shadd_const
1012 and added to (reg). This allows more scaled indexed addresses. */
1013 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1014 && GET_CODE (XEXP (x, 0)) == MULT
1015 && GET_CODE (XEXP (y, 1)) == CONST_INT
1016 && INTVAL (XEXP (y, 1)) >= -4096
1017 && INTVAL (XEXP (y, 1)) <= 4095
1018 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1019 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1021 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1025 if (GET_CODE (reg1) != REG)
1026 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1028 reg2 = XEXP (XEXP (x, 0), 0);
1029 if (GET_CODE (reg2) != REG)
1030 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1032 return force_reg (Pmode,
1033 gen_rtx_PLUS (Pmode,
1034 gen_rtx_MULT (Pmode, reg2,
1038 else if ((mode == DFmode || mode == SFmode)
1039 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1040 && GET_CODE (XEXP (x, 0)) == MULT
1041 && GET_CODE (XEXP (y, 1)) == CONST_INT
1042 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1043 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1044 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1047 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1048 / INTVAL (XEXP (XEXP (x, 0), 1))));
1049 regx2 = XEXP (XEXP (x, 0), 0);
1050 if (GET_CODE (regx2) != REG)
1051 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1052 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1054 return force_reg (Pmode,
1055 gen_rtx_PLUS (Pmode,
1056 gen_rtx_MULT (Pmode, regx2,
1059 force_reg (Pmode, XEXP (y, 0))));
1061 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1062 && INTVAL (XEXP (y, 1)) >= -4096
1063 && INTVAL (XEXP (y, 1)) <= 4095)
1065 /* This is safe because of the guard page at the
1066 beginning and end of the data space. Just
1067 return the original address. */
1072 /* Doesn't look like one we can optimize. */
1073 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1074 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1075 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1076 regx1 = force_reg (Pmode,
1077 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1079 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1087 /* For the HPPA, REG and REG+CONST is cost 0
1088 and addresses involving symbolic constants are cost 2.
1090 PIC addresses are very expensive.
1092 It is no coincidence that this has the same structure
1093 as GO_IF_LEGITIMATE_ADDRESS. */
1095 hppa_address_cost (X)
1098 if (GET_CODE (X) == PLUS)
1100 else if (GET_CODE (X) == LO_SUM)
1102 else if (GET_CODE (X) == HIGH)
1107 /* Emit insns to move operands[1] into operands[0].
1109 Return 1 if we have written out everything that needs to be done to
1110 do the move. Otherwise, return 0 and the caller will emit the move
1114 emit_move_sequence (operands, mode, scratch_reg)
1116 enum machine_mode mode;
1119 register rtx operand0 = operands[0];
1120 register rtx operand1 = operands[1];
1124 && reload_in_progress && GET_CODE (operand0) == REG
1125 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1126 operand0 = reg_equiv_mem[REGNO (operand0)];
1127 else if (scratch_reg
1128 && reload_in_progress && GET_CODE (operand0) == SUBREG
1129 && GET_CODE (SUBREG_REG (operand0)) == REG
1130 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1132 SUBREG_REG (operand0) = reg_equiv_mem[REGNO (SUBREG_REG (operand0))];
1133 operand0 = alter_subreg (operand0);
1137 && reload_in_progress && GET_CODE (operand1) == REG
1138 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1139 operand1 = reg_equiv_mem[REGNO (operand1)];
1140 else if (scratch_reg
1141 && reload_in_progress && GET_CODE (operand1) == SUBREG
1142 && GET_CODE (SUBREG_REG (operand1)) == REG
1143 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1145 SUBREG_REG (operand1) = reg_equiv_mem[REGNO (SUBREG_REG (operand1))];
1146 operand1 = alter_subreg (operand1);
1149 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1150 && ((tem = find_replacement (&XEXP (operand0, 0)))
1151 != XEXP (operand0, 0)))
1152 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1153 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1154 && ((tem = find_replacement (&XEXP (operand1, 0)))
1155 != XEXP (operand1, 0)))
1156 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1158 /* Handle secondary reloads for loads/stores of FP registers from
1159 REG+D addresses where D does not fit in 5 bits, including
1160 (subreg (mem (addr))) cases. */
1161 if (fp_reg_operand (operand0, mode)
1162 && ((GET_CODE (operand1) == MEM
1163 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1164 || ((GET_CODE (operand1) == SUBREG
1165 && GET_CODE (XEXP (operand1, 0)) == MEM
1166 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1169 if (GET_CODE (operand1) == SUBREG)
1170 operand1 = XEXP (operand1, 0);
1172 scratch_reg = gen_rtx_REG (SImode, REGNO (scratch_reg));
1174 /* D might not fit in 14 bits either; for such cases load D into
1176 if (!memory_address_p (SImode, XEXP (operand1, 0)))
1178 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1179 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1181 XEXP (XEXP (operand1, 0), 0),
1185 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1186 emit_insn (gen_rtx_SET (VOIDmode, operand0, gen_rtx_MEM (mode,
1190 else if (fp_reg_operand (operand1, mode)
1191 && ((GET_CODE (operand0) == MEM
1192 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1193 || ((GET_CODE (operand0) == SUBREG)
1194 && GET_CODE (XEXP (operand0, 0)) == MEM
1195 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1198 if (GET_CODE (operand0) == SUBREG)
1199 operand0 = XEXP (operand0, 0);
1201 scratch_reg = gen_rtx_REG (SImode, REGNO (scratch_reg));
1202 /* D might not fit in 14 bits either; for such cases load D into
1204 if (!memory_address_p (SImode, XEXP (operand0, 0)))
1206 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1207 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1210 XEXP (XEXP (operand0, 0),
1215 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1216 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1220 /* Handle secondary reloads for loads of FP registers from constant
1221 expressions by forcing the constant into memory.
1223 use scratch_reg to hold the address of the memory location.
1225 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
1226 NO_REGS when presented with a const_int and an register class
1227 containing only FP registers. Doing so unfortunately creates
1228 more problems than it solves. Fix this for 2.5. */
1229 else if (fp_reg_operand (operand0, mode)
1230 && CONSTANT_P (operand1)
1235 /* Force the constant into memory and put the address of the
1236 memory location into scratch_reg. */
1237 xoperands[0] = scratch_reg;
1238 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1239 emit_move_sequence (xoperands, Pmode, 0);
1241 /* Now load the destination register. */
1242 emit_insn (gen_rtx_SET (mode, operand0, gen_rtx_MEM (mode, scratch_reg)));
1245 /* Handle secondary reloads for SAR. These occur when trying to load
1246 the SAR from memory a FP register, or with a constant. */
1247 else if (GET_CODE (operand0) == REG
1248 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1249 && (GET_CODE (operand1) == MEM
1250 || GET_CODE (operand1) == CONST_INT
1251 || (GET_CODE (operand1) == REG
1252 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1255 /* D might not fit in 14 bits either; for such cases load D into
1257 if (GET_CODE (operand1) == MEM
1258 && !memory_address_p (SImode, XEXP (operand1, 0)))
1260 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1261 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1264 XEXP (XEXP (operand1, 0),
1267 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand1),
1271 emit_move_insn (scratch_reg, operand1);
1272 emit_move_insn (operand0, scratch_reg);
1275 /* Handle most common case: storing into a register. */
1276 else if (register_operand (operand0, mode))
1278 if (register_operand (operand1, mode)
1279 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1280 || (operand1 == CONST0_RTX (mode))
1281 || (GET_CODE (operand1) == HIGH
1282 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1283 /* Only `general_operands' can come here, so MEM is ok. */
1284 || GET_CODE (operand1) == MEM)
1286 /* Run this case quickly. */
1287 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1291 else if (GET_CODE (operand0) == MEM)
1293 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1294 && !(reload_in_progress || reload_completed))
1296 rtx temp = gen_reg_rtx (DFmode);
1298 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1299 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1302 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1304 /* Run this case quickly. */
1305 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1308 if (! (reload_in_progress || reload_completed))
1310 operands[0] = validize_mem (operand0);
1311 operands[1] = operand1 = force_reg (mode, operand1);
1315 /* Simplify the source if we need to.
1316 Note we do have to handle function labels here, even though we do
1317 not consider them legitimate constants. Loop optimizations can
1318 call the emit_move_xxx with one as a source. */
1319 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1320 || function_label_operand (operand1, mode)
1321 || (GET_CODE (operand1) == HIGH
1322 && symbolic_operand (XEXP (operand1, 0), mode)))
1326 if (GET_CODE (operand1) == HIGH)
1329 operand1 = XEXP (operand1, 0);
1331 if (symbolic_operand (operand1, mode))
1333 /* Argh. The assembler and linker can't handle arithmetic
1336 So we force the plabel into memory, load operand0 from
1337 the memory location, then add in the constant part. */
1338 if ((GET_CODE (operand1) == CONST
1339 && GET_CODE (XEXP (operand1, 0)) == PLUS
1340 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1341 || function_label_operand (operand1, mode))
1343 rtx temp, const_part;
1345 /* Figure out what (if any) scratch register to use. */
1346 if (reload_in_progress || reload_completed)
1347 scratch_reg = scratch_reg ? scratch_reg : operand0;
1349 scratch_reg = gen_reg_rtx (Pmode);
1351 if (GET_CODE (operand1) == CONST)
1353 /* Save away the constant part of the expression. */
1354 const_part = XEXP (XEXP (operand1, 0), 1);
1355 if (GET_CODE (const_part) != CONST_INT)
1358 /* Force the function label into memory. */
1359 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1363 /* No constant part. */
1364 const_part = NULL_RTX;
1366 /* Force the function label into memory. */
1367 temp = force_const_mem (mode, operand1);
1371 /* Get the address of the memory location. PIC-ify it if
1373 temp = XEXP (temp, 0);
1375 temp = legitimize_pic_address (temp, mode, scratch_reg);
1377 /* Put the address of the memory location into our destination
1380 emit_move_sequence (operands, mode, scratch_reg);
1382 /* Now load from the memory location into our destination
1384 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1385 emit_move_sequence (operands, mode, scratch_reg);
1387 /* And add back in the constant part. */
1388 if (const_part != NULL_RTX)
1389 expand_inc (operand0, const_part);
1398 if (reload_in_progress || reload_completed)
1399 temp = scratch_reg ? scratch_reg : operand0;
1401 temp = gen_reg_rtx (Pmode);
1403 /* (const (plus (symbol) (const_int))) must be forced to
1404 memory during/after reload if the const_int will not fit
1406 if (GET_CODE (operand1) == CONST
1407 && GET_CODE (XEXP (operand1, 0)) == PLUS
1408 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1409 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1410 && (reload_completed || reload_in_progress)
1413 operands[1] = force_const_mem (mode, operand1);
1414 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1416 emit_move_sequence (operands, mode, temp);
1420 operands[1] = legitimize_pic_address (operand1, mode, temp);
1421 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1424 /* On the HPPA, references to data space are supposed to use dp,
1425 register 27, but showing it in the RTL inhibits various cse
1426 and loop optimizations. */
1431 if (reload_in_progress || reload_completed)
1432 temp = scratch_reg ? scratch_reg : operand0;
1434 temp = gen_reg_rtx (mode);
1436 /* Loading a SYMBOL_REF into a register makes that register
1437 safe to be used as the base in an indexed address.
1439 Don't mark hard registers though. That loses. */
1440 if (GET_CODE (operand0) == REG
1441 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1442 REGNO_POINTER_FLAG (REGNO (operand0)) = 1;
1443 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1444 REGNO_POINTER_FLAG (REGNO (temp)) = 1;
1446 set = gen_rtx_SET (mode, operand0, temp);
1448 set = gen_rtx_SET (VOIDmode, operand0,
1449 gen_rtx_LO_SUM (mode, temp, operand1));
1451 emit_insn (gen_rtx_SET (VOIDmode,
1453 gen_rtx_HIGH (mode, operand1)));
1459 else if (GET_CODE (operand1) != CONST_INT
1460 || ! cint_ok_for_move (INTVAL (operand1)))
1464 if (reload_in_progress || reload_completed)
1467 temp = gen_reg_rtx (mode);
1469 emit_insn (gen_rtx_SET (VOIDmode, temp,
1470 gen_rtx_HIGH (mode, operand1)));
1471 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1474 /* Now have insn-emit do whatever it normally does. */
1478 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1479 it will need a link/runtime reloc). */
1487 switch (TREE_CODE (exp))
1494 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1495 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1500 case NON_LVALUE_EXPR:
1501 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1507 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1508 if (TREE_VALUE (link) != 0)
1509 reloc |= reloc_needed (TREE_VALUE (link));
1522 /* Does operand (which is a symbolic_operand) live in text space? If
1523 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1526 read_only_operand (operand)
1529 if (GET_CODE (operand) == CONST)
1530 operand = XEXP (XEXP (operand, 0), 0);
1533 if (GET_CODE (operand) == SYMBOL_REF)
1534 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1538 if (GET_CODE (operand) == SYMBOL_REF)
1539 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1545 /* Return the best assembler insn template
1546 for moving operands[1] into operands[0] as a fullword. */
1548 singlemove_string (operands)
1551 HOST_WIDE_INT intval;
1553 if (GET_CODE (operands[0]) == MEM)
1554 return "stw %r1,%0";
1555 if (GET_CODE (operands[1]) == MEM)
1557 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1562 if (GET_MODE (operands[1]) != SFmode)
1565 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1567 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1568 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1570 operands[1] = GEN_INT (i);
1571 /* Fall through to CONST_INT case. */
1573 if (GET_CODE (operands[1]) == CONST_INT)
1575 intval = INTVAL (operands[1]);
1577 if (VAL_14_BITS_P (intval))
1579 else if ((intval & 0x7ff) == 0)
1580 return "ldil L'%1,%0";
1581 else if (zdepi_cint_p (intval))
1582 return "zdepi %Z1,%0";
1584 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1586 return "copy %1,%0";
1590 /* Compute position (in OP[1]) and width (in OP[2])
1591 useful for copying IMM to a register using the zdepi
1592 instructions. Store the immediate value to insert in OP[0]. */
1594 compute_zdepi_operands (imm, op)
1595 unsigned HOST_WIDE_INT imm;
1600 /* Find the least significant set bit in IMM. */
1601 for (lsb = 0; lsb < 32; lsb++)
1608 /* Choose variants based on *sign* of the 5-bit field. */
1609 if ((imm & 0x10) == 0)
1610 len = (lsb <= 28) ? 4 : 32 - lsb;
1613 /* Find the width of the bitstring in IMM. */
1614 for (len = 5; len < 32; len++)
1616 if ((imm & (1 << len)) == 0)
1620 /* Sign extend IMM as a 5-bit value. */
1621 imm = (imm & 0xf) - 0x10;
1629 /* Output assembler code to perform a doubleword move insn
1630 with operands OPERANDS. */
1633 output_move_double (operands)
1636 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1638 rtx addreg0 = 0, addreg1 = 0;
1640 /* First classify both operands. */
1642 if (REG_P (operands[0]))
1644 else if (offsettable_memref_p (operands[0]))
1646 else if (GET_CODE (operands[0]) == MEM)
1651 if (REG_P (operands[1]))
1653 else if (CONSTANT_P (operands[1]))
1655 else if (offsettable_memref_p (operands[1]))
1657 else if (GET_CODE (operands[1]) == MEM)
1662 /* Check for the cases that the operand constraints are not
1663 supposed to allow to happen. Abort if we get one,
1664 because generating code for these cases is painful. */
1666 if (optype0 != REGOP && optype1 != REGOP)
1669 /* Handle auto decrementing and incrementing loads and stores
1670 specifically, since the structure of the function doesn't work
1671 for them without major modification. Do it better when we learn
1672 this port about the general inc/dec addressing of PA.
1673 (This was written by tege. Chide him if it doesn't work.) */
1675 if (optype0 == MEMOP)
1677 /* We have to output the address syntax ourselves, since print_operand
1678 doesn't deal with the addresses we want to use. Fix this later. */
1680 rtx addr = XEXP (operands[0], 0);
1681 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1683 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1685 operands[0] = XEXP (addr, 0);
1686 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1689 if (!reg_overlap_mentioned_p (high_reg, addr))
1691 /* No overlap between high target register and address
1692 register. (We do this in a non-obvious way to
1693 save a register file writeback) */
1694 if (GET_CODE (addr) == POST_INC)
1695 return "stws,ma %1,8(%0)\n\tstw %R1,-4(%0)";
1696 return "stws,ma %1,-8(%0)\n\tstw %R1,12(%0)";
1701 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1703 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1705 operands[0] = XEXP (addr, 0);
1706 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1709 if (!reg_overlap_mentioned_p (high_reg, addr))
1711 /* No overlap between high target register and address
1712 register. (We do this in a non-obvious way to
1713 save a register file writeback) */
1714 if (GET_CODE (addr) == PRE_INC)
1715 return "stws,mb %1,8(%0)\n\tstw %R1,4(%0)";
1716 return "stws,mb %1,-8(%0)\n\tstw %R1,4(%0)";
1722 if (optype1 == MEMOP)
1724 /* We have to output the address syntax ourselves, since print_operand
1725 doesn't deal with the addresses we want to use. Fix this later. */
1727 rtx addr = XEXP (operands[1], 0);
1728 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1730 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1732 operands[1] = XEXP (addr, 0);
1733 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1736 if (!reg_overlap_mentioned_p (high_reg, addr))
1738 /* No overlap between high target register and address
1739 register. (We do this in a non-obvious way to
1740 save a register file writeback) */
1741 if (GET_CODE (addr) == POST_INC)
1742 return "ldws,ma 8(%1),%0\n\tldw -4(%1),%R0";
1743 return "ldws,ma -8(%1),%0\n\tldw 12(%1),%R0";
1747 /* This is an undefined situation. We should load into the
1748 address register *and* update that register. Probably
1749 we don't need to handle this at all. */
1750 if (GET_CODE (addr) == POST_INC)
1751 return "ldw 4(%1),%R0\n\tldws,ma 8(%1),%0";
1752 return "ldw 4(%1),%R0\n\tldws,ma -8(%1),%0";
1755 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1757 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1759 operands[1] = XEXP (addr, 0);
1760 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1763 if (!reg_overlap_mentioned_p (high_reg, addr))
1765 /* No overlap between high target register and address
1766 register. (We do this in a non-obvious way to
1767 save a register file writeback) */
1768 if (GET_CODE (addr) == PRE_INC)
1769 return "ldws,mb 8(%1),%0\n\tldw 4(%1),%R0";
1770 return "ldws,mb -8(%1),%0\n\tldw 4(%1),%R0";
1774 /* This is an undefined situation. We should load into the
1775 address register *and* update that register. Probably
1776 we don't need to handle this at all. */
1777 if (GET_CODE (addr) == PRE_INC)
1778 return "ldw 12(%1),%R0\n\tldws,mb 8(%1),%0";
1779 return "ldw -4(%1),%R0\n\tldws,mb -8(%1),%0";
1782 else if (GET_CODE (addr) == PLUS
1783 && GET_CODE (XEXP (addr, 0)) == MULT)
1785 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1787 if (!reg_overlap_mentioned_p (high_reg, addr))
1791 xoperands[0] = high_reg;
1792 xoperands[1] = XEXP (addr, 1);
1793 xoperands[2] = XEXP (XEXP (addr, 0), 0);
1794 xoperands[3] = XEXP (XEXP (addr, 0), 1);
1795 output_asm_insn ("sh%O3addl %2,%1,%0", xoperands);
1796 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
1802 xoperands[0] = high_reg;
1803 xoperands[1] = XEXP (addr, 1);
1804 xoperands[2] = XEXP (XEXP (addr, 0), 0);
1805 xoperands[3] = XEXP (XEXP (addr, 0), 1);
1806 output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands);
1807 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
1813 /* If an operand is an unoffsettable memory ref, find a register
1814 we can increment temporarily to make it refer to the second word. */
1816 if (optype0 == MEMOP)
1817 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1819 if (optype1 == MEMOP)
1820 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1822 /* Ok, we can do one word at a time.
1823 Normally we do the low-numbered word first.
1825 In either case, set up in LATEHALF the operands to use
1826 for the high-numbered word and in some cases alter the
1827 operands in OPERANDS to be suitable for the low-numbered word. */
1829 if (optype0 == REGOP)
1830 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1831 else if (optype0 == OFFSOP)
1832 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1834 latehalf[0] = operands[0];
1836 if (optype1 == REGOP)
1837 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1838 else if (optype1 == OFFSOP)
1839 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1840 else if (optype1 == CNSTOP)
1841 split_double (operands[1], &operands[1], &latehalf[1]);
1843 latehalf[1] = operands[1];
1845 /* If the first move would clobber the source of the second one,
1846 do them in the other order.
1848 This can happen in two cases:
1850 mem -> register where the first half of the destination register
1851 is the same register used in the memory's address. Reload
1852 can create such insns.
1854 mem in this case will be either register indirect or register
1855 indirect plus a valid offset.
1857 register -> register move where REGNO(dst) == REGNO(src + 1)
1858 someone (Tim/Tege?) claimed this can happen for parameter loads.
1860 Handle mem -> register case first. */
1861 if (optype0 == REGOP
1862 && (optype1 == MEMOP || optype1 == OFFSOP)
1863 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
1866 /* Do the late half first. */
1868 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1869 output_asm_insn (singlemove_string (latehalf), latehalf);
1873 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1874 return singlemove_string (operands);
1877 /* Now handle register -> register case. */
1878 if (optype0 == REGOP && optype1 == REGOP
1879 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1881 output_asm_insn (singlemove_string (latehalf), latehalf);
1882 return singlemove_string (operands);
1885 /* Normal case: do the two words, low-numbered first. */
1887 output_asm_insn (singlemove_string (operands), operands);
1889 /* Make any unoffsettable addresses point at high-numbered word. */
1891 output_asm_insn ("ldo 4(%0),%0", &addreg0);
1893 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1896 output_asm_insn (singlemove_string (latehalf), latehalf);
1898 /* Undo the adds we just did. */
1900 output_asm_insn ("ldo -4(%0),%0", &addreg0);
1902 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1908 output_fp_move_double (operands)
1911 if (FP_REG_P (operands[0]))
1913 if (FP_REG_P (operands[1])
1914 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1915 output_asm_insn ("fcpy,dbl %f1,%0", operands);
1917 output_asm_insn ("fldd%F1 %1,%0", operands);
1919 else if (FP_REG_P (operands[1]))
1921 output_asm_insn ("fstd%F0 %1,%0", operands);
1923 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1925 if (GET_CODE (operands[0]) == REG)
1928 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1929 xoperands[0] = operands[0];
1930 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
1932 /* This is a pain. You have to be prepared to deal with an
1933 arbitrary address here including pre/post increment/decrement.
1935 so avoid this in the MD. */
1943 /* Return a REG that occurs in ADDR with coefficient 1.
1944 ADDR can be effectively incremented by incrementing REG. */
1947 find_addr_reg (addr)
1950 while (GET_CODE (addr) == PLUS)
1952 if (GET_CODE (XEXP (addr, 0)) == REG)
1953 addr = XEXP (addr, 0);
1954 else if (GET_CODE (XEXP (addr, 1)) == REG)
1955 addr = XEXP (addr, 1);
1956 else if (CONSTANT_P (XEXP (addr, 0)))
1957 addr = XEXP (addr, 1);
1958 else if (CONSTANT_P (XEXP (addr, 1)))
1959 addr = XEXP (addr, 0);
1963 if (GET_CODE (addr) == REG)
1968 /* Emit code to perform a block move.
1970 OPERANDS[0] is the destination pointer as a REG, clobbered.
1971 OPERANDS[1] is the source pointer as a REG, clobbered.
1972 OPERANDS[2] is a register for temporary storage.
1973 OPERANDS[4] is the size as a CONST_INT
1974 OPERANDS[3] is a register for temporary storage.
1975 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
1976 OPERANDS[6] is another temporary register. */
1979 output_block_move (operands, size_is_constant)
1981 int size_is_constant ATTRIBUTE_UNUSED;
1983 int align = INTVAL (operands[5]);
1984 unsigned long n_bytes = INTVAL (operands[4]);
1986 /* We can't move more than four bytes at a time because the PA
1987 has no longer integer move insns. (Could use fp mem ops?) */
1991 /* Note that we know each loop below will execute at least twice
1992 (else we would have open-coded the copy). */
1996 /* Pre-adjust the loop counter. */
1997 operands[4] = GEN_INT (n_bytes - 8);
1998 output_asm_insn ("ldi %4,%2", operands);
2001 output_asm_insn ("ldws,ma 4(%1),%3", operands);
2002 output_asm_insn ("ldws,ma 4(%1),%6", operands);
2003 output_asm_insn ("stws,ma %3,4(%0)", operands);
2004 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2005 output_asm_insn ("stws,ma %6,4(%0)", operands);
2007 /* Handle the residual. There could be up to 7 bytes of
2008 residual to copy! */
2009 if (n_bytes % 8 != 0)
2011 operands[4] = GEN_INT (n_bytes % 4);
2012 if (n_bytes % 8 >= 4)
2013 output_asm_insn ("ldws,ma 4(%1),%3", operands);
2014 if (n_bytes % 4 != 0)
2015 output_asm_insn ("ldw 0(%1),%6", operands);
2016 if (n_bytes % 8 >= 4)
2017 output_asm_insn ("stws,ma %3,4(%0)", operands);
2018 if (n_bytes % 4 != 0)
2019 output_asm_insn ("stbys,e %6,%4(%0)", operands);
2024 /* Pre-adjust the loop counter. */
2025 operands[4] = GEN_INT (n_bytes - 4);
2026 output_asm_insn ("ldi %4,%2", operands);
2029 output_asm_insn ("ldhs,ma 2(%1),%3", operands);
2030 output_asm_insn ("ldhs,ma 2(%1),%6", operands);
2031 output_asm_insn ("sths,ma %3,2(%0)", operands);
2032 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2033 output_asm_insn ("sths,ma %6,2(%0)", operands);
2035 /* Handle the residual. */
2036 if (n_bytes % 4 != 0)
2038 if (n_bytes % 4 >= 2)
2039 output_asm_insn ("ldhs,ma 2(%1),%3", operands);
2040 if (n_bytes % 2 != 0)
2041 output_asm_insn ("ldb 0(%1),%6", operands);
2042 if (n_bytes % 4 >= 2)
2043 output_asm_insn ("sths,ma %3,2(%0)", operands);
2044 if (n_bytes % 2 != 0)
2045 output_asm_insn ("stb %6,0(%0)", operands);
2050 /* Pre-adjust the loop counter. */
2051 operands[4] = GEN_INT (n_bytes - 2);
2052 output_asm_insn ("ldi %4,%2", operands);
2055 output_asm_insn ("ldbs,ma 1(%1),%3", operands);
2056 output_asm_insn ("ldbs,ma 1(%1),%6", operands);
2057 output_asm_insn ("stbs,ma %3,1(%0)", operands);
2058 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2059 output_asm_insn ("stbs,ma %6,1(%0)", operands);
2061 /* Handle the residual. */
2062 if (n_bytes % 2 != 0)
2064 output_asm_insn ("ldb 0(%1),%3", operands);
2065 output_asm_insn ("stb %3,0(%0)", operands);
2074 /* Count the number of insns necessary to handle this block move.
2076 Basic structure is the same as emit_block_move, except that we
2077 count insns rather than emit them. */
2080 compute_movstrsi_length (insn)
2083 rtx pat = PATTERN (insn);
2084 int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2085 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2086 unsigned int n_insns = 0;
2088 /* We can't move more than four bytes at a time because the PA
2089 has no longer integer move insns. (Could use fp mem ops?) */
2093 /* The basic copying loop. */
2097 if (n_bytes % (2 * align) != 0)
2099 if ((n_bytes % (2 * align)) >= align)
2102 if ((n_bytes % align) != 0)
2106 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2112 output_and (operands)
2115 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2117 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2118 int ls0, ls1, ms0, p, len;
2120 for (ls0 = 0; ls0 < 32; ls0++)
2121 if ((mask & (1 << ls0)) == 0)
2124 for (ls1 = ls0; ls1 < 32; ls1++)
2125 if ((mask & (1 << ls1)) != 0)
2128 for (ms0 = ls1; ms0 < 32; ms0++)
2129 if ((mask & (1 << ms0)) == 0)
2142 operands[2] = GEN_INT (len);
2143 return "extru %1,31,%2,%0";
2147 /* We could use this `depi' for the case above as well, but `depi'
2148 requires one more register file access than an `extru'. */
2153 operands[2] = GEN_INT (p);
2154 operands[3] = GEN_INT (len);
2155 return "depi 0,%2,%3,%0";
2159 return "and %1,%2,%0";
2163 output_ior (operands)
2166 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2167 int bs0, bs1, p, len;
2169 if (INTVAL (operands[2]) == 0)
2170 return "copy %1,%0";
2172 for (bs0 = 0; bs0 < 32; bs0++)
2173 if ((mask & (1 << bs0)) != 0)
2176 for (bs1 = bs0; bs1 < 32; bs1++)
2177 if ((mask & (1 << bs1)) == 0)
2180 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2186 operands[2] = GEN_INT (p);
2187 operands[3] = GEN_INT (len);
2188 return "depi -1,%2,%3,%0";
2191 /* Output an ascii string. */
2193 output_ascii (file, p, size)
2200 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2202 /* The HP assembler can only take strings of 256 characters at one
2203 time. This is a limitation on input line length, *not* the
2204 length of the string. Sigh. Even worse, it seems that the
2205 restriction is in number of input characters (see \xnn &
2206 \whatever). So we have to do this very carefully. */
2208 fputs ("\t.STRING \"", file);
2211 for (i = 0; i < size; i += 4)
2215 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2217 register unsigned int c = p[i + io];
2219 if (c == '\"' || c == '\\')
2220 partial_output[co++] = '\\';
2221 if (c >= ' ' && c < 0177)
2222 partial_output[co++] = c;
2226 partial_output[co++] = '\\';
2227 partial_output[co++] = 'x';
2228 hexd = c / 16 - 0 + '0';
2230 hexd -= '9' - 'a' + 1;
2231 partial_output[co++] = hexd;
2232 hexd = c % 16 - 0 + '0';
2234 hexd -= '9' - 'a' + 1;
2235 partial_output[co++] = hexd;
2238 if (chars_output + co > 243)
2240 fputs ("\"\n\t.STRING \"", file);
2243 fwrite (partial_output, 1, co, file);
2247 fputs ("\"\n", file);
2250 /* Try to rewrite floating point comparisons & branches to avoid
2251 useless add,tr insns.
2253 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2254 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2255 first attempt to remove useless add,tr insns. It is zero
2256 for the second pass as reorg sometimes leaves bogus REG_DEAD
2259 When CHECK_NOTES is zero we can only eliminate add,tr insns
2260 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2263 remove_useless_addtr_insns (insns, check_notes)
2268 static int pass = 0;
2270 /* This is fairly cheap, so always run it when optimizing. */
2274 int fbranch_count = 0;
2276 /* Walk all the insns in this function looking for fcmp & fbranch
2277 instructions. Keep track of how many of each we find. */
2278 insns = get_insns ();
2279 for (insn = insns; insn; insn = next_insn (insn))
2283 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2284 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2287 tmp = PATTERN (insn);
2289 /* It must be a set. */
2290 if (GET_CODE (tmp) != SET)
2293 /* If the destination is CCFP, then we've found an fcmp insn. */
2294 tmp = SET_DEST (tmp);
2295 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2301 tmp = PATTERN (insn);
2302 /* If this is an fbranch instruction, bump the fbranch counter. */
2303 if (GET_CODE (tmp) == SET
2304 && SET_DEST (tmp) == pc_rtx
2305 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2306 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2307 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2308 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2316 /* Find all floating point compare + branch insns. If possible,
2317 reverse the comparison & the branch to avoid add,tr insns. */
2318 for (insn = insns; insn; insn = next_insn (insn))
2322 /* Ignore anything that isn't an INSN. */
2323 if (GET_CODE (insn) != INSN)
2326 tmp = PATTERN (insn);
2328 /* It must be a set. */
2329 if (GET_CODE (tmp) != SET)
2332 /* The destination must be CCFP, which is register zero. */
2333 tmp = SET_DEST (tmp);
2334 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2337 /* INSN should be a set of CCFP.
2339 See if the result of this insn is used in a reversed FP
2340 conditional branch. If so, reverse our condition and
2341 the branch. Doing so avoids useless add,tr insns. */
2342 next = next_insn (insn);
2345 /* Jumps, calls and labels stop our search. */
2346 if (GET_CODE (next) == JUMP_INSN
2347 || GET_CODE (next) == CALL_INSN
2348 || GET_CODE (next) == CODE_LABEL)
2351 /* As does another fcmp insn. */
2352 if (GET_CODE (next) == INSN
2353 && GET_CODE (PATTERN (next)) == SET
2354 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2355 && REGNO (SET_DEST (PATTERN (next))) == 0)
2358 next = next_insn (next);
2361 /* Is NEXT_INSN a branch? */
2363 && GET_CODE (next) == JUMP_INSN)
2365 rtx pattern = PATTERN (next);
2367 /* If it a reversed fp conditional branch (eg uses add,tr)
2368 and CCFP dies, then reverse our conditional and the branch
2369 to avoid the add,tr. */
2370 if (GET_CODE (pattern) == SET
2371 && SET_DEST (pattern) == pc_rtx
2372 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2373 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2374 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2375 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2376 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2377 && (fcmp_count == fbranch_count
2379 && find_regno_note (next, REG_DEAD, 0))))
2381 /* Reverse the branch. */
2382 tmp = XEXP (SET_SRC (pattern), 1);
2383 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2384 XEXP (SET_SRC (pattern), 2) = tmp;
2385 INSN_CODE (next) = -1;
2387 /* Reverse our condition. */
2388 tmp = PATTERN (insn);
2389 PUT_CODE (XEXP (tmp, 1),
2390 reverse_condition (GET_CODE (XEXP (tmp, 1))));
2400 /* You may have trouble believing this, but this is the HP-PA stack
2405 Variable arguments (optional; any number may be allocated)
2407 SP-(4*(N+9)) arg word N
2412 Fixed arguments (must be allocated; may remain unused)
2421 SP-32 External Data Pointer (DP)
2423 SP-24 External/stub RP (RP')
2427 SP-8 Calling Stub RP (RP'')
2432 SP-0 Stack Pointer (points to next available address)
2436 /* This function saves registers as follows. Registers marked with ' are
2437 this function's registers (as opposed to the previous function's).
2438 If a frame_pointer isn't needed, r4 is saved as a general register;
2439 the space for the frame pointer is still allocated, though, to keep
2445 SP (FP') Previous FP
2446 SP + 4 Alignment filler (sigh)
2447 SP + 8 Space for locals reserved here.
2451 SP + n All call saved register used.
2455 SP + o All call saved fp registers used.
2459 SP + p (SP') points to next available address.
2463 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2464 Handle case where DISP > 8k by using the add_high_const pattern.
2466 Note in DISP > 8k case, we will leave the high part of the address
2467 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2469 store_reg (reg, disp, base)
2470 int reg, disp, base;
2472 if (VAL_14_BITS_P (disp))
2474 emit_move_insn (gen_rtx_MEM (SImode,
2475 gen_rtx_PLUS (SImode,
2476 gen_rtx_REG (SImode, base),
2478 gen_rtx_REG (SImode, reg));
2482 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2483 gen_rtx_REG (SImode, base),
2485 emit_move_insn (gen_rtx_MEM (SImode,
2486 gen_rtx_LO_SUM (SImode,
2487 gen_rtx_REG (SImode, 1),
2489 gen_rtx_REG (SImode, reg));
2493 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
2494 Handle case where DISP > 8k by using the add_high_const pattern.
2496 Note in DISP > 8k case, we will leave the high part of the address
2497 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2499 load_reg (reg, disp, base)
2500 int reg, disp, base;
2502 if (VAL_14_BITS_P (disp))
2504 emit_move_insn (gen_rtx_REG (SImode, reg),
2505 gen_rtx_MEM (SImode,
2506 gen_rtx_PLUS (SImode,
2507 gen_rtx_REG (SImode, base),
2512 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2513 gen_rtx_REG (SImode, base),
2515 emit_move_insn (gen_rtx_REG (SImode, reg),
2516 gen_rtx_MEM (SImode,
2517 gen_rtx_LO_SUM (SImode,
2518 gen_rtx_REG (SImode, 1),
2523 /* Emit RTL to set REG to the value specified by BASE+DISP.
2524 Handle case where DISP > 8k by using the add_high_const pattern.
2526 Note in DISP > 8k case, we will leave the high part of the address
2527 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2529 set_reg_plus_d(reg, base, disp)
2530 int reg, base, disp;
2532 if (VAL_14_BITS_P (disp))
2534 emit_move_insn (gen_rtx_REG (SImode, reg),
2535 gen_rtx_PLUS (SImode,
2536 gen_rtx_REG (SImode, base),
2541 emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
2542 gen_rtx_REG (SImode, base),
2544 emit_move_insn (gen_rtx_REG (SImode, reg),
2545 gen_rtx_LO_SUM (SImode,
2546 gen_rtx_REG (SImode, 1),
2551 /* Global variables set by FUNCTION_PROLOGUE. */
2552 /* Size of frame. Need to know this to emit return insns from
2554 static int actual_fsize;
2555 static int local_fsize, save_fregs;
2558 compute_frame_size (size, fregs_live)
2562 extern int current_function_outgoing_args_size;
2565 /* 8 is space for frame pointer + filler. If any frame is allocated
2566 we need to add this in because of STARTING_FRAME_OFFSET. */
2567 fsize = size + (size || frame_pointer_needed ? 8 : 0);
2569 /* We must leave enough space for all the callee saved registers
2570 from 3 .. highest used callee save register since we don't
2571 know if we're going to have an inline or out of line prologue
2573 for (i = 18; i >= 3; i--)
2574 if (regs_ever_live[i])
2576 fsize += 4 * (i - 2);
2580 /* Round the stack. */
2581 fsize = (fsize + 7) & ~7;
2583 /* We must leave enough space for all the callee saved registers
2584 from 3 .. highest used callee save register since we don't
2585 know if we're going to have an inline or out of line prologue
2587 for (i = 66; i >= 48; i -= 2)
2588 if (regs_ever_live[i] || regs_ever_live[i + 1])
2593 fsize += 4 * (i - 46);
2597 fsize += current_function_outgoing_args_size;
2598 if (! leaf_function_p () || fsize)
2600 return (fsize + 63) & ~63;
2603 rtx hp_profile_label_rtx;
2604 static char hp_profile_label_name[8];
2606 output_function_prologue (file, size)
2608 int size ATTRIBUTE_UNUSED;
2610 /* The function's label and associated .PROC must never be
2611 separated and must be output *after* any profiling declarations
2612 to avoid changing spaces/subspaces within a procedure. */
2613 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2614 fputs ("\t.PROC\n", file);
2616 /* hppa_expand_prologue does the dirty work now. We just need
2617 to output the assembler directives which denote the start
2619 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2620 if (regs_ever_live[2] || profile_flag)
2621 fputs (",CALLS,SAVE_RP", file);
2623 fputs (",NO_CALLS", file);
2625 if (frame_pointer_needed)
2626 fputs (",SAVE_SP", file);
2628 /* Pass on information about the number of callee register saves
2629 performed in the prologue.
2631 The compiler is supposed to pass the highest register number
2632 saved, the assembler then has to adjust that number before
2633 entering it into the unwind descriptor (to account for any
2634 caller saved registers with lower register numbers than the
2635 first callee saved register). */
2637 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2640 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2642 fputs ("\n\t.ENTRY\n", file);
2644 /* Horrid hack. emit_function_prologue will modify this RTL in
2645 place to get the expected results. */
2647 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name, "LP",
2648 hp_profile_labelno);
2650 /* If we're using GAS and not using the portable runtime model, then
2651 we don't need to accumulate the total number of code bytes. */
2652 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2653 total_code_bytes = 0;
2654 else if (insn_addresses)
2656 unsigned int old_total = total_code_bytes;
2658 total_code_bytes += insn_addresses[INSN_UID (get_last_insn())];
2659 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2661 /* Be prepared to handle overflows. */
2662 total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
2665 total_code_bytes = -1;
2667 remove_useless_addtr_insns (get_insns (), 0);
2669 /* Restore INSN_CODEs for insn which use unscaled indexed addresses. */
2670 restore_unscaled_index_insn_codes (get_insns ());
2674 hppa_expand_prologue()
2676 extern char call_used_regs[];
2677 int size = get_frame_size ();
2678 int merge_sp_adjust_with_store = 0;
2680 rtx tmpreg, size_rtx;
2685 local_fsize = size + (size || frame_pointer_needed ? 8 : 0);
2686 actual_fsize = compute_frame_size (size, &save_fregs);
2688 /* Compute a few things we will use often. */
2689 tmpreg = gen_rtx_REG (SImode, 1);
2690 size_rtx = GEN_INT (actual_fsize);
2692 /* Handle out of line prologues and epilogues. */
2697 int outline_insn_count = 0;
2698 int inline_insn_count = 0;
2700 /* Count the number of insns for the inline and out of line
2701 variants so we can choose one appropriately.
2703 No need to screw with counting actual_fsize operations -- they're
2704 done for both inline and out of line prologues. */
2705 if (regs_ever_live[2])
2706 inline_insn_count += 1;
2708 if (! cint_ok_for_move (local_fsize))
2709 outline_insn_count += 2;
2711 outline_insn_count += 1;
2713 /* Put the register save info into %r22. */
2714 for (i = 18; i >= 3; i--)
2715 if (regs_ever_live[i] && ! call_used_regs[i])
2717 /* -1 because the stack adjustment is normally done in
2718 the same insn as a register save. */
2719 inline_insn_count += (i - 2) - 1;
2724 for (i = 66; i >= 48; i -= 2)
2725 if (regs_ever_live[i] || regs_ever_live[i + 1])
2727 /* +1 needed as we load %r1 with the start of the freg
2729 inline_insn_count += (i/2 - 23) + 1;
2730 saves |= ((i/2 - 12 ) << 16);
2734 if (frame_pointer_needed)
2735 inline_insn_count += 3;
2737 if (! cint_ok_for_move (saves))
2738 outline_insn_count += 2;
2740 outline_insn_count += 1;
2742 if (TARGET_PORTABLE_RUNTIME)
2743 outline_insn_count += 2;
2745 outline_insn_count += 1;
2747 /* If there's a lot of insns in the prologue, then do it as
2748 an out-of-line sequence. */
2749 if (inline_insn_count > outline_insn_count)
2751 /* Put the local_fisze into %r19. */
2752 operands[0] = gen_rtx_REG (SImode, 19);
2753 operands[1] = GEN_INT (local_fsize);
2754 emit_move_insn (operands[0], operands[1]);
2756 /* Put the stack size into %r21. */
2757 operands[0] = gen_rtx_REG (SImode, 21);
2758 operands[1] = size_rtx;
2759 emit_move_insn (operands[0], operands[1]);
2761 operands[0] = gen_rtx_REG (SImode, 22);
2762 operands[1] = GEN_INT (saves);
2763 emit_move_insn (operands[0], operands[1]);
2765 /* Now call the out-of-line prologue. */
2766 emit_insn (gen_outline_prologue_call ());
2767 emit_insn (gen_blockage ());
2769 /* Note that we're using an out-of-line prologue. */
2770 out_of_line_prologue_epilogue = 1;
2775 out_of_line_prologue_epilogue = 0;
2777 /* Save RP first. The calling conventions manual states RP will
2778 always be stored into the caller's frame at sp-20. */
2779 if (regs_ever_live[2] || profile_flag)
2780 store_reg (2, -20, STACK_POINTER_REGNUM);
2782 /* Allocate the local frame and set up the frame pointer if needed. */
2785 if (frame_pointer_needed)
2787 /* Copy the old frame pointer temporarily into %r1. Set up the
2788 new stack pointer, then store away the saved old frame pointer
2789 into the stack at sp+actual_fsize and at the same time update
2790 the stack pointer by actual_fsize bytes. Two versions, first
2791 handles small (<8k) frames. The second handles large (>8k)
2793 emit_move_insn (tmpreg, frame_pointer_rtx);
2794 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2795 if (VAL_14_BITS_P (actual_fsize))
2796 emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, size_rtx));
2799 /* It is incorrect to store the saved frame pointer at *sp,
2800 then increment sp (writes beyond the current stack boundary).
2802 So instead use stwm to store at *sp and post-increment the
2803 stack pointer as an atomic operation. Then increment sp to
2804 finish allocating the new frame. */
2805 emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, GEN_INT (64)));
2806 set_reg_plus_d (STACK_POINTER_REGNUM,
2807 STACK_POINTER_REGNUM,
2811 /* no frame pointer needed. */
2814 /* In some cases we can perform the first callee register save
2815 and allocating the stack frame at the same time. If so, just
2816 make a note of it and defer allocating the frame until saving
2817 the callee registers. */
2818 if (VAL_14_BITS_P (-actual_fsize)
2822 merge_sp_adjust_with_store = 1;
2823 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2824 else if (actual_fsize != 0)
2825 set_reg_plus_d (STACK_POINTER_REGNUM,
2826 STACK_POINTER_REGNUM,
2831 /* The hppa calling conventions say that %r19, the pic offset
2832 register, is saved at sp - 32 (in this function's frame) when
2833 generating PIC code. FIXME: What is the correct thing to do
2834 for functions which make no calls and allocate no frame? Do
2835 we need to allocate a frame, or can we just omit the save? For
2836 now we'll just omit the save. */
2837 if (actual_fsize != 0 && flag_pic)
2838 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
2842 Instead of taking one argument, the counter label, as most normal
2843 mcounts do, _mcount appears to behave differently on the HPPA. It
2844 takes the return address of the caller, the address of this routine,
2845 and the address of the label. Also, it isn't magic, so
2846 argument registers have to be preserved. */
2849 int pc_offset, i, arg_offset, basereg, offsetadj;
2851 pc_offset = 4 + (frame_pointer_needed
2852 ? (VAL_14_BITS_P (actual_fsize) ? 12 : 20)
2853 : (VAL_14_BITS_P (actual_fsize) ? 4 : 8));
2855 /* When the function has a frame pointer, use it as the base
2856 register for saving/restore registers. Else use the stack
2857 pointer. Adjust the offset according to the frame size if
2858 this function does not have a frame pointer. */
2860 basereg = frame_pointer_needed ? FRAME_POINTER_REGNUM
2861 : STACK_POINTER_REGNUM;
2862 offsetadj = frame_pointer_needed ? 0 : actual_fsize;
2864 /* Horrid hack. emit_function_prologue will modify this RTL in
2865 place to get the expected results. sprintf here is just to
2866 put something in the name. */
2867 sprintf(hp_profile_label_name, "LP$%04d", -1);
2868 hp_profile_label_rtx = gen_rtx_SYMBOL_REF (SImode, hp_profile_label_name);
2869 if (current_function_returns_struct)
2870 store_reg (STRUCT_VALUE_REGNUM, - 12 - offsetadj, basereg);
2871 if (current_function_needs_context)
2872 store_reg (STATIC_CHAIN_REGNUM, - 16 - offsetadj, basereg);
2874 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2875 if (regs_ever_live [i])
2877 store_reg (i, arg_offset, basereg);
2878 /* Deal with arg_offset not fitting in 14 bits. */
2879 pc_offset += VAL_14_BITS_P (arg_offset) ? 4 : 8;
2882 emit_move_insn (gen_rtx_REG (SImode, 26), gen_rtx_REG (SImode, 2));
2883 emit_move_insn (tmpreg, gen_rtx_HIGH (SImode, hp_profile_label_rtx));
2884 emit_move_insn (gen_rtx_REG (SImode, 24),
2885 gen_rtx_LO_SUM (SImode, tmpreg, hp_profile_label_rtx));
2886 /* %r25 is set from within the output pattern. */
2887 emit_insn (gen_call_profiler (GEN_INT (- pc_offset - 20)));
2889 /* Restore argument registers. */
2890 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2891 if (regs_ever_live [i])
2892 load_reg (i, arg_offset, basereg);
2894 if (current_function_returns_struct)
2895 load_reg (STRUCT_VALUE_REGNUM, -12 - offsetadj, basereg);
2897 if (current_function_needs_context)
2898 load_reg (STATIC_CHAIN_REGNUM, -16 - offsetadj, basereg);
2901 /* Normal register save.
2903 Do not save the frame pointer in the frame_pointer_needed case. It
2904 was done earlier. */
2905 if (frame_pointer_needed)
2907 for (i = 18, offset = local_fsize; i >= 4; i--)
2908 if (regs_ever_live[i] && ! call_used_regs[i])
2910 store_reg (i, offset, FRAME_POINTER_REGNUM);
2914 /* Account for %r3 which is saved in a special place. */
2917 /* No frame pointer needed. */
2920 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2921 if (regs_ever_live[i] && ! call_used_regs[i])
2923 /* If merge_sp_adjust_with_store is nonzero, then we can
2924 optimize the first GR save. */
2925 if (merge_sp_adjust_with_store)
2927 merge_sp_adjust_with_store = 0;
2928 emit_insn (gen_post_stwm (stack_pointer_rtx,
2929 gen_rtx_REG (SImode, i),
2930 GEN_INT (-offset)));
2933 store_reg (i, offset, STACK_POINTER_REGNUM);
2938 /* If we wanted to merge the SP adjustment with a GR save, but we never
2939 did any GR saves, then just emit the adjustment here. */
2940 if (merge_sp_adjust_with_store)
2941 set_reg_plus_d (STACK_POINTER_REGNUM,
2942 STACK_POINTER_REGNUM,
2946 /* Align pointer properly (doubleword boundary). */
2947 offset = (offset + 7) & ~7;
2949 /* Floating point register store. */
2952 /* First get the frame or stack pointer to the start of the FP register
2954 if (frame_pointer_needed)
2955 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2957 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2959 /* Now actually save the FP registers. */
2960 for (i = 66; i >= 48; i -= 2)
2962 if (regs_ever_live[i] || regs_ever_live[i + 1])
2964 emit_move_insn (gen_rtx_MEM (DFmode,
2965 gen_rtx_POST_INC (DFmode, tmpreg)),
2966 gen_rtx_REG (DFmode, i));
2972 /* When generating PIC code it is necessary to save/restore the
2973 PIC register around each function call. We used to do this
2974 in the call patterns themselves, but that implementation
2975 made incorrect assumptions about using global variables to hold
2976 per-function rtl code generated in the backend.
2978 So instead, we copy the PIC register into a reserved callee saved
2979 register in the prologue. Then after each call we reload the PIC
2980 register from the callee saved register. We also reload the PIC
2981 register from the callee saved register in the epilogue ensure the
2982 PIC register is valid at function exit.
2984 This may (depending on the exact characteristics of the function)
2985 even be more efficient.
2987 Avoid this if the callee saved register wasn't used (these are
2989 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM_SAVED])
2990 emit_move_insn (gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM_SAVED),
2991 gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM));
2996 output_function_epilogue (file, size)
2998 int size ATTRIBUTE_UNUSED;
3000 rtx insn = get_last_insn ();
3002 /* hppa_expand_epilogue does the dirty work now. We just need
3003 to output the assembler directives which denote the end
3006 To make debuggers happy, emit a nop if the epilogue was completely
3007 eliminated due to a volatile call as the last insn in the
3008 current function. That way the return address (in %r2) will
3009 always point to a valid instruction in the current function. */
3011 /* Get the last real insn. */
3012 if (GET_CODE (insn) == NOTE)
3013 insn = prev_real_insn (insn);
3015 /* If it is a sequence, then look inside. */
3016 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3017 insn = XVECEXP (PATTERN (insn), 0, 0);
3019 /* If insn is a CALL_INSN, then it must be a call to a volatile
3020 function (otherwise there would be epilogue insns). */
3021 if (insn && GET_CODE (insn) == CALL_INSN)
3022 fputs ("\tnop\n", file);
3024 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3026 /* Free up stuff we don't need anymore. */
3027 if (unscaled_index_insn_codes)
3028 free (unscaled_index_insn_codes);
3029 max_unscaled_index_insn_codes_uid = 0;
3033 hppa_expand_epilogue ()
3037 int merge_sp_adjust_with_load = 0;
3039 /* Handle out of line prologues and epilogues. */
3040 if (TARGET_SPACE && out_of_line_prologue_epilogue)
3045 /* Put the register save info into %r22. */
3046 for (i = 18; i >= 3; i--)
3047 if (regs_ever_live[i] && ! call_used_regs[i])
3053 for (i = 66; i >= 48; i -= 2)
3054 if (regs_ever_live[i] || regs_ever_live[i + 1])
3056 saves |= ((i/2 - 12 ) << 16);
3060 emit_insn (gen_blockage ());
3062 /* Put the local_fisze into %r19. */
3063 operands[0] = gen_rtx_REG (SImode, 19);
3064 operands[1] = GEN_INT (local_fsize);
3065 emit_move_insn (operands[0], operands[1]);
3067 /* Put the stack size into %r21. */
3068 operands[0] = gen_rtx_REG (SImode, 21);
3069 operands[1] = GEN_INT (actual_fsize);
3070 emit_move_insn (operands[0], operands[1]);
3072 operands[0] = gen_rtx_REG (SImode, 22);
3073 operands[1] = GEN_INT (saves);
3074 emit_move_insn (operands[0], operands[1]);
3076 /* Now call the out-of-line epilogue. */
3077 emit_insn (gen_outline_epilogue_call ());
3081 /* We will use this often. */
3082 tmpreg = gen_rtx_REG (SImode, 1);
3084 /* Try to restore RP early to avoid load/use interlocks when
3085 RP gets used in the return (bv) instruction. This appears to still
3086 be necessary even when we schedule the prologue and epilogue. */
3087 if (frame_pointer_needed
3088 && (regs_ever_live [2] || profile_flag))
3089 load_reg (2, -20, FRAME_POINTER_REGNUM);
3091 /* No frame pointer, and stack is smaller than 8k. */
3092 else if (! frame_pointer_needed
3093 && VAL_14_BITS_P (actual_fsize + 20)
3094 && (regs_ever_live[2] || profile_flag))
3095 load_reg (2, - (actual_fsize + 20), STACK_POINTER_REGNUM);
3097 /* General register restores. */
3098 if (frame_pointer_needed)
3100 for (i = 18, offset = local_fsize; i >= 4; i--)
3101 if (regs_ever_live[i] && ! call_used_regs[i])
3103 load_reg (i, offset, FRAME_POINTER_REGNUM);
3109 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
3111 if (regs_ever_live[i] && ! call_used_regs[i])
3113 /* Only for the first load.
3114 merge_sp_adjust_with_load holds the register load
3115 with which we will merge the sp adjustment. */
3116 if (VAL_14_BITS_P (actual_fsize + 20)
3118 && ! merge_sp_adjust_with_load)
3119 merge_sp_adjust_with_load = i;
3121 load_reg (i, offset, STACK_POINTER_REGNUM);
3127 /* Align pointer properly (doubleword boundary). */
3128 offset = (offset + 7) & ~7;
3130 /* FP register restores. */
3133 /* Adjust the register to index off of. */
3134 if (frame_pointer_needed)
3135 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
3137 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
3139 /* Actually do the restores now. */
3140 for (i = 66; i >= 48; i -= 2)
3142 if (regs_ever_live[i] || regs_ever_live[i + 1])
3144 emit_move_insn (gen_rtx_REG (DFmode, i),
3145 gen_rtx_MEM (DFmode,
3146 gen_rtx_POST_INC (DFmode, tmpreg)));
3151 /* Emit a blockage insn here to keep these insns from being moved to
3152 an earlier spot in the epilogue, or into the main instruction stream.
3154 This is necessary as we must not cut the stack back before all the
3155 restores are finished. */
3156 emit_insn (gen_blockage ());
3157 /* No frame pointer, but we have a stack greater than 8k. We restore
3158 %r2 very late in this case. (All other cases are restored as early
3160 if (! frame_pointer_needed
3161 && ! VAL_14_BITS_P (actual_fsize + 20)
3162 && (regs_ever_live[2] || profile_flag))
3164 set_reg_plus_d (STACK_POINTER_REGNUM,
3165 STACK_POINTER_REGNUM,
3168 /* This used to try and be clever by not depending on the value in
3169 %r30 and instead use the value held in %r1 (so that the 2nd insn
3170 which sets %r30 could be put in the delay slot of the return insn).
3172 That won't work since if the stack is exactly 8k set_reg_plus_d
3173 doesn't set %r1, just %r30. */
3174 load_reg (2, - 20, STACK_POINTER_REGNUM);
3177 /* Reset stack pointer (and possibly frame pointer). The stack
3178 pointer is initially set to fp + 64 to avoid a race condition. */
3179 else if (frame_pointer_needed)
3181 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
3182 emit_insn (gen_pre_ldwm (frame_pointer_rtx,
3186 /* If we were deferring a callee register restore, do it now. */
3187 else if (! frame_pointer_needed && merge_sp_adjust_with_load)
3188 emit_insn (gen_pre_ldwm (gen_rtx_REG (SImode, merge_sp_adjust_with_load),
3190 GEN_INT (- actual_fsize)));
3191 else if (actual_fsize != 0)
3192 set_reg_plus_d (STACK_POINTER_REGNUM,
3193 STACK_POINTER_REGNUM,
3197 /* Fetch the return address for the frame COUNT steps up from
3198 the current frame, after the prologue. FRAMEADDR is the
3199 frame pointer of the COUNT frame.
3201 We want to ignore any export stub remnants here.
3203 The value returned is used in two different ways:
3205 1. To find a function's caller.
3207 2. To change the return address for a function.
3209 This function handles most instances of case 1; however, it will
3210 fail if there are two levels of stubs to execute on the return
3211 path. The only way I believe that can happen is if the return value
3212 needs a parameter relocation, which never happens for C code.
3214 This function handles most instances of case 2; however, it will
3215 fail if we did not originally have stub code on the return path
3216 but will need code on the new return path. This can happen if
3217 the caller & callee are both in the main program, but the new
3218 return location is in a shared library.
3220 To handle this correctly we need to set the return pointer at
3221 frame-20 to point to a return stub frame-24 to point to the
3222 location we wish to return to. */
3225 return_addr_rtx (count, frameaddr)
3226 int count ATTRIBUTE_UNUSED;
3233 saved_rp = gen_reg_rtx (Pmode);
3235 /* First, we start off with the normal return address pointer from
3238 emit_move_insn (saved_rp, plus_constant (frameaddr, -5 * UNITS_PER_WORD));
3240 /* Get pointer to the instruction stream. We have to mask out the
3241 privilege level from the two low order bits of the return address
3242 pointer here so that ins will point to the start of the first
3243 instruction that would have been executed if we returned. */
3244 ins = copy_to_reg (gen_rtx_AND (Pmode,
3245 copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
3247 label = gen_label_rtx ();
3249 /* Check the instruction stream at the normal return address for the
3252 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3253 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3254 0x00011820 | stub+16: mtsp r1,sr0
3255 0xe0400002 | stub+20: be,n 0(sr0,rp)
3257 If it is an export stub, than our return address is really in
3260 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3261 GEN_INT (0x4bc23fd1),
3262 NE, NULL_RTX, SImode, 1, 0);
3263 emit_jump_insn (gen_bne (label));
3265 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3266 GEN_INT (0x004010a1),
3267 NE, NULL_RTX, SImode, 1, 0);
3268 emit_jump_insn (gen_bne (label));
3270 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3271 GEN_INT (0x00011820),
3272 NE, NULL_RTX, SImode, 1, 0);
3273 emit_jump_insn (gen_bne (label));
3275 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3276 GEN_INT (0xe0400002),
3277 NE, NULL_RTX, SImode, 1, 0);
3279 /* If there is no export stub then just use our initial guess of
3282 emit_jump_insn (gen_bne (label));
3284 /* Here we know that our return address pointer points to an export
3285 stub. We don't want to return the address of the export stub,
3286 but rather the return address that leads back into user code.
3287 That return address is stored at -24[frameaddr]. */
3289 emit_move_insn (saved_rp, plus_constant (frameaddr, -6 * UNITS_PER_WORD));
3292 return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
3295 /* This is only valid once reload has completed because it depends on
3296 knowing exactly how much (if any) frame there is and...
3298 It's only valid if there is no frame marker to de-allocate and...
3300 It's only valid if %r2 hasn't been saved into the caller's frame
3301 (we're not profiling and %r2 isn't live anywhere). */
3303 hppa_can_use_return_insn_p ()
3305 return (reload_completed
3306 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3308 && ! regs_ever_live[2]
3309 && ! frame_pointer_needed);
3313 emit_bcond_fp (code, operand0)
3317 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3318 gen_rtx_IF_THEN_ELSE (VOIDmode,
3319 gen_rtx_fmt_ee (code,
3321 gen_rtx_REG (CCFPmode, 0),
3323 gen_rtx_LABEL_REF (VOIDmode, operand0),
3329 gen_cmp_fp (code, operand0, operand1)
3331 rtx operand0, operand1;
3333 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3334 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3337 /* Adjust the cost of a scheduling dependency. Return the new cost of
3338 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3341 pa_adjust_cost (insn, link, dep_insn, cost)
3347 enum attr_type attr_type;
3349 /* Don't adjust costs for a pa8000 chip. */
3350 if (pa_cpu >= PROCESSOR_8000)
3353 if (! recog_memoized (insn))
3356 attr_type = get_attr_type (insn);
3358 if (REG_NOTE_KIND (link) == 0)
3360 /* Data dependency; DEP_INSN writes a register that INSN reads some
3363 if (attr_type == TYPE_FPSTORE)
3365 rtx pat = PATTERN (insn);
3366 rtx dep_pat = PATTERN (dep_insn);
3367 if (GET_CODE (pat) == PARALLEL)
3369 /* This happens for the fstXs,mb patterns. */
3370 pat = XVECEXP (pat, 0, 0);
3372 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3373 /* If this happens, we have to extend this to schedule
3374 optimally. Return 0 for now. */
3377 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3379 if (! recog_memoized (dep_insn))
3381 /* DEP_INSN is writing its result to the register
3382 being stored in the fpstore INSN. */
3383 switch (get_attr_type (dep_insn))
3386 /* This cost 3 cycles, not 2 as the md says for the
3395 case TYPE_FPSQRTSGL:
3396 case TYPE_FPSQRTDBL:
3397 /* In these important cases, we save one cycle compared to
3398 when flop instruction feed each other. */
3407 /* For other data dependencies, the default cost specified in the
3411 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3413 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3416 if (attr_type == TYPE_FPLOAD)
3418 rtx pat = PATTERN (insn);
3419 rtx dep_pat = PATTERN (dep_insn);
3420 if (GET_CODE (pat) == PARALLEL)
3422 /* This happens for the fldXs,mb patterns. */
3423 pat = XVECEXP (pat, 0, 0);
3425 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3426 /* If this happens, we have to extend this to schedule
3427 optimally. Return 0 for now. */
3430 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3432 if (! recog_memoized (dep_insn))
3434 switch (get_attr_type (dep_insn))
3441 case TYPE_FPSQRTSGL:
3442 case TYPE_FPSQRTDBL:
3443 /* A fpload can't be issued until one cycle before a
3444 preceding arithmetic operation has finished if
3445 the target of the fpload is any of the sources
3446 (or destination) of the arithmetic operation. */
3454 else if (attr_type == TYPE_FPALU)
3456 rtx pat = PATTERN (insn);
3457 rtx dep_pat = PATTERN (dep_insn);
3458 if (GET_CODE (pat) == PARALLEL)
3460 /* This happens for the fldXs,mb patterns. */
3461 pat = XVECEXP (pat, 0, 0);
3463 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3464 /* If this happens, we have to extend this to schedule
3465 optimally. Return 0 for now. */
3468 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3470 if (! recog_memoized (dep_insn))
3472 switch (get_attr_type (dep_insn))
3476 case TYPE_FPSQRTSGL:
3477 case TYPE_FPSQRTDBL:
3478 /* An ALU flop can't be issued until two cycles before a
3479 preceding divide or sqrt operation has finished if
3480 the target of the ALU flop is any of the sources
3481 (or destination) of the divide or sqrt operation. */
3490 /* For other anti dependencies, the cost is 0. */
3493 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3495 /* Output dependency; DEP_INSN writes a register that INSN writes some
3497 if (attr_type == TYPE_FPLOAD)
3499 rtx pat = PATTERN (insn);
3500 rtx dep_pat = PATTERN (dep_insn);
3501 if (GET_CODE (pat) == PARALLEL)
3503 /* This happens for the fldXs,mb patterns. */
3504 pat = XVECEXP (pat, 0, 0);
3506 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3507 /* If this happens, we have to extend this to schedule
3508 optimally. Return 0 for now. */
3511 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3513 if (! recog_memoized (dep_insn))
3515 switch (get_attr_type (dep_insn))
3522 case TYPE_FPSQRTSGL:
3523 case TYPE_FPSQRTDBL:
3524 /* A fpload can't be issued until one cycle before a
3525 preceding arithmetic operation has finished if
3526 the target of the fpload is the destination of the
3527 arithmetic operation. */
3535 else if (attr_type == TYPE_FPALU)
3537 rtx pat = PATTERN (insn);
3538 rtx dep_pat = PATTERN (dep_insn);
3539 if (GET_CODE (pat) == PARALLEL)
3541 /* This happens for the fldXs,mb patterns. */
3542 pat = XVECEXP (pat, 0, 0);
3544 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3545 /* If this happens, we have to extend this to schedule
3546 optimally. Return 0 for now. */
3549 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3551 if (! recog_memoized (dep_insn))
3553 switch (get_attr_type (dep_insn))
3557 case TYPE_FPSQRTSGL:
3558 case TYPE_FPSQRTDBL:
3559 /* An ALU flop can't be issued until two cycles before a
3560 preceding divide or sqrt operation has finished if
3561 the target of the ALU flop is also the target of
3562 the divide or sqrt operation. */
3571 /* For other output dependencies, the cost is 0. */
3578 /* Return any length adjustment needed by INSN which already has its length
3579 computed as LENGTH. Return zero if no adjustment is necessary.
3581 For the PA: function calls, millicode calls, and backwards short
3582 conditional branches with unfilled delay slots need an adjustment by +1
3583 (to account for the NOP which will be inserted into the instruction stream).
3585 Also compute the length of an inline block move here as it is too
3586 complicated to express as a length attribute in pa.md. */
3588 pa_adjust_insn_length (insn, length)
3592 rtx pat = PATTERN (insn);
3594 /* Call insns which are *not* indirect and have unfilled delay slots. */
3595 if (GET_CODE (insn) == CALL_INSN)
3598 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3599 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3601 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3602 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3608 /* Jumps inside switch tables which have unfilled delay slots
3609 also need adjustment. */
3610 else if (GET_CODE (insn) == JUMP_INSN
3611 && simplejump_p (insn)
3612 && GET_MODE (insn) == SImode)
3614 /* Millicode insn with an unfilled delay slot. */
3615 else if (GET_CODE (insn) == INSN
3616 && GET_CODE (pat) != SEQUENCE
3617 && GET_CODE (pat) != USE
3618 && GET_CODE (pat) != CLOBBER
3619 && get_attr_type (insn) == TYPE_MILLI)
3621 /* Block move pattern. */
3622 else if (GET_CODE (insn) == INSN
3623 && GET_CODE (pat) == PARALLEL
3624 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3625 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3626 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3627 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3628 return compute_movstrsi_length (insn) - 4;
3629 /* Conditional branch with an unfilled delay slot. */
3630 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3632 /* Adjust a short backwards conditional with an unfilled delay slot. */
3633 if (GET_CODE (pat) == SET
3635 && ! forward_branch_p (insn))
3637 else if (GET_CODE (pat) == PARALLEL
3638 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3641 /* Adjust dbra insn with short backwards conditional branch with
3642 unfilled delay slot -- only for case where counter is in a
3643 general register register. */
3644 else if (GET_CODE (pat) == PARALLEL
3645 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3646 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3647 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3649 && ! forward_branch_p (insn))
3657 /* Print operand X (an rtx) in assembler syntax to file FILE.
3658 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3659 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3662 print_operand (file, x, code)
3670 /* Output a 'nop' if there's nothing for the delay slot. */
3671 if (dbr_sequence_length () == 0)
3672 fputs ("\n\tnop", file);
3675 /* Output an nullification completer if there's nothing for the */
3676 /* delay slot or nullification is requested. */
3677 if (dbr_sequence_length () == 0 ||
3679 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
3683 /* Print out the second register name of a register pair.
3684 I.e., R (6) => 7. */
3685 fputs (reg_names[REGNO (x)+1], file);
3688 /* A register or zero. */
3690 || (x == CONST0_RTX (DFmode))
3691 || (x == CONST0_RTX (SFmode)))
3693 fputs ("%r0", file);
3699 /* A register or zero (floating point). */
3701 || (x == CONST0_RTX (DFmode))
3702 || (x == CONST0_RTX (SFmode)))
3704 fputs ("%fr0", file);
3709 case 'C': /* Plain (C)ondition */
3711 switch (GET_CODE (x))
3714 fputs ("=", file); break;
3716 fputs ("<>", file); break;
3718 fputs (">", file); break;
3720 fputs (">=", file); break;
3722 fputs (">>=", file); break;
3724 fputs (">>", file); break;
3726 fputs ("<", file); break;
3728 fputs ("<=", file); break;
3730 fputs ("<<=", file); break;
3732 fputs ("<<", file); break;
3737 case 'N': /* Condition, (N)egated */
3738 switch (GET_CODE (x))
3741 fputs ("<>", file); break;
3743 fputs ("=", file); break;
3745 fputs ("<=", file); break;
3747 fputs ("<", file); break;
3749 fputs ("<<", file); break;
3751 fputs ("<<=", file); break;
3753 fputs (">=", file); break;
3755 fputs (">", file); break;
3757 fputs (">>", file); break;
3759 fputs (">>=", file); break;
3764 /* For floating point comparisons. Need special conditions to deal
3765 with NaNs properly. */
3767 switch (GET_CODE (x))
3770 fputs ("!=", file); break;
3772 fputs ("=", file); break;
3774 fputs ("<=", file); break;
3776 fputs ("<", file); break;
3778 fputs (">=", file); break;
3780 fputs (">", file); break;
3785 case 'S': /* Condition, operands are (S)wapped. */
3786 switch (GET_CODE (x))
3789 fputs ("=", file); break;
3791 fputs ("<>", file); break;
3793 fputs ("<", file); break;
3795 fputs ("<=", file); break;
3797 fputs ("<<=", file); break;
3799 fputs ("<<", file); break;
3801 fputs (">", file); break;
3803 fputs (">=", file); break;
3805 fputs (">>=", file); break;
3807 fputs (">>", file); break;
3812 case 'B': /* Condition, (B)oth swapped and negate. */
3813 switch (GET_CODE (x))
3816 fputs ("<>", file); break;
3818 fputs ("=", file); break;
3820 fputs (">=", file); break;
3822 fputs (">", file); break;
3824 fputs (">>", file); break;
3826 fputs (">>=", file); break;
3828 fputs ("<=", file); break;
3830 fputs ("<", file); break;
3832 fputs ("<<", file); break;
3834 fputs ("<<=", file); break;
3840 if (GET_CODE (x) == CONST_INT)
3842 fprintf (file, "%d", ~INTVAL (x));
3847 if (GET_CODE (x) == CONST_INT)
3849 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
3854 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
3856 fprintf (file, "%d", exact_log2 (INTVAL (x)));
3861 if (GET_CODE (x) == CONST_INT)
3863 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
3868 if (GET_CODE (x) == CONST_INT)
3873 switch (GET_CODE (XEXP (x, 0)))
3877 fputs ("s,mb", file);
3881 fputs ("s,ma", file);
3884 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3885 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3886 fputs ("x,s", file);
3887 else if (code == 'F')
3897 output_global_address (file, x, 0);
3900 output_global_address (file, x, 1);
3902 case 0: /* Don't do anything special */
3907 compute_zdepi_operands (INTVAL (x), op);
3908 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
3914 if (GET_CODE (x) == REG)
3916 fputs (reg_names [REGNO (x)], file);
3917 if (FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4 && (REGNO (x) & 1) == 0)
3920 else if (GET_CODE (x) == MEM)
3922 int size = GET_MODE_SIZE (GET_MODE (x));
3923 rtx base = XEXP (XEXP (x, 0), 0);
3924 switch (GET_CODE (XEXP (x, 0)))
3928 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
3932 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
3935 if (GET_CODE (XEXP (x, 0)) == PLUS
3936 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
3937 fprintf (file, "%s(%s)",
3938 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
3939 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
3940 else if (GET_CODE (XEXP (x, 0)) == PLUS
3941 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3942 fprintf (file, "%s(%s)",
3943 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
3944 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
3946 output_address (XEXP (x, 0));
3951 output_addr_const (file, x);
3954 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
3957 output_global_address (file, x, round_constant)
3963 /* Imagine (high (const (plus ...))). */
3964 if (GET_CODE (x) == HIGH)
3967 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x))
3968 assemble_name (file, XSTR (x, 0));
3969 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
3971 assemble_name (file, XSTR (x, 0));
3972 fputs ("-$global$", file);
3974 else if (GET_CODE (x) == CONST)
3977 int offset = 0; /* assembler wants -$global$ at end */
3978 rtx base = NULL_RTX;
3980 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
3982 base = XEXP (XEXP (x, 0), 0);
3983 output_addr_const (file, base);
3985 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
3986 offset = INTVAL (XEXP (XEXP (x, 0), 0));
3989 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
3991 base = XEXP (XEXP (x, 0), 1);
3992 output_addr_const (file, base);
3994 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
3995 offset = INTVAL (XEXP (XEXP (x, 0),1));
3998 /* How bogus. The compiler is apparently responsible for
3999 rounding the constant if it uses an LR field selector.
4001 The linker and/or assembler seem a better place since
4002 they have to do this kind of thing already.
4004 If we fail to do this, HP's optimizing linker may eliminate
4005 an addil, but not update the ldw/stw/ldo instruction that
4006 uses the result of the addil. */
4008 offset = ((offset + 0x1000) & ~0x1fff);
4010 if (GET_CODE (XEXP (x, 0)) == PLUS)
4020 else if (GET_CODE (XEXP (x, 0)) == MINUS
4021 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4025 if (!read_only_operand (base) && !flag_pic)
4026 fputs ("-$global$", file);
4028 fprintf (file,"%s%d", sep, offset);
4031 output_addr_const (file, x);
4035 output_deferred_plabels (file)
4039 /* If we have deferred plabels, then we need to switch into the data
4040 section and align it to a 4 byte boundary before we output the
4041 deferred plabels. */
4042 if (n_deferred_plabels)
4045 ASM_OUTPUT_ALIGN (file, 2);
4048 /* Now output the deferred plabels. */
4049 for (i = 0; i < n_deferred_plabels; i++)
4051 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4052 assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode,
4053 deferred_plabels[i].name), 4, 1);
4057 /* HP's millicode routines mean something special to the assembler.
4058 Keep track of which ones we have used. */
4060 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
4061 static char imported[(int)end1000];
4062 static char *milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
4063 static char import_string[] = ".IMPORT $$....,MILLICODE";
4064 #define MILLI_START 10
4068 enum millicodes code;
4070 char str[sizeof (import_string)];
4072 if (!imported[(int)code])
4074 imported[(int)code] = 1;
4075 strcpy (str, import_string);
4076 strncpy (str + MILLI_START, milli_names[(int)code], 4);
4077 output_asm_insn (str, 0);
4081 /* The register constraints have put the operands and return value in
4082 the proper registers. */
4085 output_mul_insn (unsignedp, insn)
4086 int unsignedp ATTRIBUTE_UNUSED;
4089 import_milli (mulI);
4090 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (SImode, "$$mulI"));
4093 /* Emit the rtl for doing a division by a constant. */
4095 /* Do magic division millicodes exist for this value? */
4096 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4099 /* We'll use an array to keep track of the magic millicodes and
4100 whether or not we've used them already. [n][0] is signed, [n][1] is
4103 static int div_milli[16][2];
4106 div_operand (op, mode)
4108 enum machine_mode mode;
4110 return (mode == SImode
4111 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4112 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4113 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4117 emit_hpdiv_const (operands, unsignedp)
4121 if (GET_CODE (operands[2]) == CONST_INT
4122 && INTVAL (operands[2]) > 0
4123 && INTVAL (operands[2]) < 16
4124 && magic_milli[INTVAL (operands[2])])
4126 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4129 (PARALLEL, VOIDmode,
4130 gen_rtvec (5, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4131 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4133 gen_rtx_REG (SImode, 26),
4135 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4136 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4137 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4138 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
4139 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4146 output_div_insn (operands, unsignedp, insn)
4153 /* If the divisor is a constant, try to use one of the special
4155 if (GET_CODE (operands[0]) == CONST_INT)
4157 static char buf[100];
4158 divisor = INTVAL (operands[0]);
4159 if (!div_milli[divisor][unsignedp])
4161 div_milli[divisor][unsignedp] = 1;
4163 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4165 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4169 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
4170 return output_millicode_call (insn,
4171 gen_rtx_SYMBOL_REF (SImode, buf));
4175 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
4176 return output_millicode_call (insn,
4177 gen_rtx_SYMBOL_REF (SImode, buf));
4180 /* Divisor isn't a special constant. */
4185 import_milli (divU);
4186 return output_millicode_call (insn,
4187 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4191 import_milli (divI);
4192 return output_millicode_call (insn,
4193 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4198 /* Output a $$rem millicode to do mod. */
4201 output_mod_insn (unsignedp, insn)
4207 import_milli (remU);
4208 return output_millicode_call (insn,
4209 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4213 import_milli (remI);
4214 return output_millicode_call (insn,
4215 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4220 output_arg_descriptor (call_insn)
4224 enum machine_mode arg_mode;
4226 int i, output_flag = 0;
4229 for (i = 0; i < 4; i++)
4232 /* Specify explicitly that no argument relocations should take place
4233 if using the portable runtime calling conventions. */
4234 if (TARGET_PORTABLE_RUNTIME)
4236 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4241 if (GET_CODE (call_insn) != CALL_INSN)
4243 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4245 rtx use = XEXP (link, 0);
4247 if (! (GET_CODE (use) == USE
4248 && GET_CODE (XEXP (use, 0)) == REG
4249 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4252 arg_mode = GET_MODE (XEXP (use, 0));
4253 regno = REGNO (XEXP (use, 0));
4254 if (regno >= 23 && regno <= 26)
4256 arg_regs[26 - regno] = "GR";
4257 if (arg_mode == DImode)
4258 arg_regs[25 - regno] = "GR";
4260 else if (regno >= 32 && regno <= 39)
4262 if (arg_mode == SFmode)
4263 arg_regs[(regno - 32) / 2] = "FR";
4266 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4267 arg_regs[(regno - 34) / 2] = "FR";
4268 arg_regs[(regno - 34) / 2 + 1] = "FU";
4270 arg_regs[(regno - 34) / 2] = "FU";
4271 arg_regs[(regno - 34) / 2 + 1] = "FR";
4276 fputs ("\t.CALL ", asm_out_file);
4277 for (i = 0; i < 4; i++)
4282 fputc (',', asm_out_file);
4283 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4286 fputc ('\n', asm_out_file);
4289 /* Return the class of any secondary reload register that is needed to
4290 move IN into a register in class CLASS using mode MODE.
4292 Profiling has showed this routine and its descendants account for
4293 a significant amount of compile time (~7%). So it has been
4294 optimized to reduce redundant computations and eliminate useless
4297 It might be worthwhile to try and make this a leaf function too. */
4300 secondary_reload_class (class, mode, in)
4301 enum reg_class class;
4302 enum machine_mode mode;
4305 int regno, is_symbolic;
4307 /* Trying to load a constant into a FP register during PIC code
4308 generation will require %r1 as a scratch register. */
4310 && GET_MODE_CLASS (mode) == MODE_INT
4311 && FP_REG_CLASS_P (class)
4312 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4315 /* Profiling showed the PA port spends about 1.3% of its compilation
4316 time in true_regnum from calls inside secondary_reload_class. */
4318 if (GET_CODE (in) == REG)
4321 if (regno >= FIRST_PSEUDO_REGISTER)
4322 regno = true_regnum (in);
4324 else if (GET_CODE (in) == SUBREG)
4325 regno = true_regnum (in);
4329 /* If we have something like (mem (mem (...)), we can safely assume the
4330 inner MEM will end up in a general register after reloading, so there's
4331 no need for a secondary reload. */
4332 if (GET_CODE (in) == MEM
4333 && GET_CODE (XEXP (in, 0)) == MEM)
4336 /* Handle out of range displacement for integer mode loads/stores of
4338 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4339 && GET_MODE_CLASS (mode) == MODE_INT
4340 && FP_REG_CLASS_P (class))
4341 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4342 return GENERAL_REGS;
4344 if (GET_CODE (in) == HIGH)
4347 /* Profiling has showed GCC spends about 2.6% of its compilation
4348 time in symbolic_operand from calls inside secondary_reload_class.
4350 We use an inline copy and only compute its return value once to avoid
4352 switch (GET_CODE (in))
4362 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4363 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4364 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4374 && read_only_operand (in))
4377 if (class != R1_REGS && is_symbolic)
4384 function_arg_padding (mode, type)
4385 enum machine_mode mode;
4390 if (mode == BLKmode)
4392 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4393 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4395 return upward; /* Don't know if this is right, but */
4396 /* same as old definition. */
4399 size = GET_MODE_BITSIZE (mode);
4400 if (size < PARM_BOUNDARY)
4402 else if (size % PARM_BOUNDARY)
4409 /* Do what is necessary for `va_start'. The argument is ignored;
4410 We look at the current function to determine if stdargs or varargs
4411 is used and fill in an initial va_list. A pointer to this constructor
4415 hppa_builtin_saveregs (arglist)
4416 tree arglist ATTRIBUTE_UNUSED;
4419 tree fntype = TREE_TYPE (current_function_decl);
4420 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4421 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4422 != void_type_node)))
4423 ? UNITS_PER_WORD : 0);
4426 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4428 offset = current_function_arg_offset_rtx;
4430 /* Store general registers on the stack. */
4431 dest = gen_rtx_MEM (BLKmode,
4432 plus_constant (current_function_internal_arg_pointer,
4434 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4436 /* move_block_from_reg will emit code to store the argument registers
4437 individually as scalar stores.
4439 However, other insns may later load from the same addresses for
4440 a structure load (passing a struct to a varargs routine).
4442 The alias code assumes that such aliasing can never happen, so we
4443 have to keep memory referencing insns from moving up beyond the
4444 last argument register store. So we emit a blockage insn here. */
4445 emit_insn (gen_blockage ());
4447 if (current_function_check_memory_usage)
4448 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4450 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4451 GEN_INT (MEMORY_USE_RW),
4452 TYPE_MODE (integer_type_node));
4454 return copy_to_reg (expand_binop (Pmode, add_optab,
4455 current_function_internal_arg_pointer,
4456 offset, 0, 0, OPTAB_LIB_WIDEN));
4459 /* This routine handles all the normal conditional branch sequences we
4460 might need to generate. It handles compare immediate vs compare
4461 register, nullification of delay slots, varying length branches,
4462 negated branches, and all combinations of the above. It returns the
4463 output appropriate to emit the branch corresponding to all given
4467 output_cbranch (operands, nullify, length, negated, insn)
4469 int nullify, length, negated;
4472 static char buf[100];
4475 /* A conditional branch to the following instruction (eg the delay slot) is
4476 asking for a disaster. This can happen when not optimizing.
4478 In such cases it is safe to emit nothing. */
4480 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4483 /* If this is a long branch with its delay slot unfilled, set `nullify'
4484 as it can nullify the delay slot and save a nop. */
4485 if (length == 8 && dbr_sequence_length () == 0)
4488 /* If this is a short forward conditional branch which did not get
4489 its delay slot filled, the delay slot can still be nullified. */
4490 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4491 nullify = forward_branch_p (insn);
4493 /* A forward branch over a single nullified insn can be done with a
4494 comclr instruction. This avoids a single cycle penalty due to
4495 mis-predicted branch if we fall through (branch not taken). */
4497 && next_real_insn (insn) != 0
4498 && get_attr_length (next_real_insn (insn)) == 4
4499 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4505 /* All short conditional branches except backwards with an unfilled
4509 strcpy (buf, "com%I2clr,");
4511 strcpy (buf, "com%I2b,");
4513 strcat (buf, "%B3");
4515 strcat (buf, "%S3");
4517 strcat (buf, " %2,%r1,%%r0");
4519 strcat (buf, ",n %2,%r1,%0");
4521 strcat (buf, " %2,%r1,%0");
4524 /* All long conditionals. Note an short backward branch with an
4525 unfilled delay slot is treated just like a long backward branch
4526 with an unfilled delay slot. */
4528 /* Handle weird backwards branch with a filled delay slot
4529 with is nullified. */
4530 if (dbr_sequence_length () != 0
4531 && ! forward_branch_p (insn)
4534 strcpy (buf, "com%I2b,");
4536 strcat (buf, "%S3");
4538 strcat (buf, "%B3");
4539 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
4541 /* Handle short backwards branch with an unfilled delay slot.
4542 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4543 taken and untaken branches. */
4544 else if (dbr_sequence_length () == 0
4545 && ! forward_branch_p (insn)
4547 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4548 - insn_addresses[INSN_UID (insn)] - 8))
4550 strcpy (buf, "com%I2b,");
4552 strcat (buf, "%B3 %2,%r1,%0%#");
4554 strcat (buf, "%S3 %2,%r1,%0%#");
4558 strcpy (buf, "com%I2clr,");
4560 strcat (buf, "%S3");
4562 strcat (buf, "%B3");
4564 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
4566 strcat (buf, " %2,%r1,%%r0\n\tb %0");
4571 /* Very long branch. Right now we only handle these when not
4572 optimizing. See "jump" pattern in pa.md for details. */
4576 /* Create a reversed conditional branch which branches around
4577 the following insns. */
4579 strcpy (buf, "com%I2b,%S3,n %2,%r1,.+20");
4581 strcpy (buf, "com%I2b,%B3,n %2,%r1,.+20");
4582 output_asm_insn (buf, operands);
4584 /* Output an insn to save %r1. */
4585 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4587 /* Now output a very long branch to the original target. */
4588 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
4590 /* Now restore the value of %r1 in the delay slot. We're not
4591 optimizing so we know nothing else can be in the delay slot. */
4592 return "ldw -16(%%r30),%%r1";
4595 /* Very long branch when generating PIC code. Right now we only
4596 handle these when not optimizing. See "jump" pattern in pa.md
4601 /* Create a reversed conditional branch which branches around
4602 the following insns. */
4604 strcpy (buf, "com%I2b,%S3,n %2,%r1,.+28");
4606 strcpy (buf, "com%I2b,%B3,n %2,%r1,.+28");
4607 output_asm_insn (buf, operands);
4609 /* Output an insn to save %r1. */
4610 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4612 /* Now output a very long PIC branch to the original target. */
4616 xoperands[0] = operands[0];
4617 xoperands[1] = operands[1];
4618 xoperands[2] = operands[2];
4619 xoperands[3] = operands[3];
4620 xoperands[4] = gen_label_rtx ();
4622 output_asm_insn ("bl .+8,%%r1\n\taddil L'%l0-%l4,%%r1", xoperands);
4623 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4624 CODE_LABEL_NUMBER (xoperands[4]));
4625 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
4629 /* Now restore the value of %r1 in the delay slot. We're not
4630 optimizing so we know nothing else can be in the delay slot. */
4631 return "ldw -16(%%r30),%%r1";
4639 /* This routine handles all the branch-on-bit conditional branch sequences we
4640 might need to generate. It handles nullification of delay slots,
4641 varying length branches, negated branches and all combinations of the
4642 above. it returns the appropriate output template to emit the branch. */
4645 output_bb (operands, nullify, length, negated, insn, which)
4646 rtx *operands ATTRIBUTE_UNUSED;
4647 int nullify, length, negated;
4651 static char buf[100];
4654 /* A conditional branch to the following instruction (eg the delay slot) is
4655 asking for a disaster. I do not think this can happen as this pattern
4656 is only used when optimizing; jump optimization should eliminate the
4657 jump. But be prepared just in case. */
4659 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4662 /* If this is a long branch with its delay slot unfilled, set `nullify'
4663 as it can nullify the delay slot and save a nop. */
4664 if (length == 8 && dbr_sequence_length () == 0)
4667 /* If this is a short forward conditional branch which did not get
4668 its delay slot filled, the delay slot can still be nullified. */
4669 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4670 nullify = forward_branch_p (insn);
4672 /* A forward branch over a single nullified insn can be done with a
4673 extrs instruction. This avoids a single cycle penalty due to
4674 mis-predicted branch if we fall through (branch not taken). */
4677 && next_real_insn (insn) != 0
4678 && get_attr_length (next_real_insn (insn)) == 4
4679 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4686 /* All short conditional branches except backwards with an unfilled
4690 strcpy (buf, "extrs,");
4692 strcpy (buf, "bb,");
4693 if ((which == 0 && negated)
4694 || (which == 1 && ! negated))
4699 strcat (buf, " %0,%1,1,%%r0");
4700 else if (nullify && negated)
4701 strcat (buf, ",n %0,%1,%3");
4702 else if (nullify && ! negated)
4703 strcat (buf, ",n %0,%1,%2");
4704 else if (! nullify && negated)
4705 strcat (buf, "%0,%1,%3");
4706 else if (! nullify && ! negated)
4707 strcat (buf, " %0,%1,%2");
4710 /* All long conditionals. Note an short backward branch with an
4711 unfilled delay slot is treated just like a long backward branch
4712 with an unfilled delay slot. */
4714 /* Handle weird backwards branch with a filled delay slot
4715 with is nullified. */
4716 if (dbr_sequence_length () != 0
4717 && ! forward_branch_p (insn)
4720 strcpy (buf, "bb,");
4721 if ((which == 0 && negated)
4722 || (which == 1 && ! negated))
4727 strcat (buf, ",n %0,%1,.+12\n\tb %3");
4729 strcat (buf, ",n %0,%1,.+12\n\tb %2");
4731 /* Handle short backwards branch with an unfilled delay slot.
4732 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4733 taken and untaken branches. */
4734 else if (dbr_sequence_length () == 0
4735 && ! forward_branch_p (insn)
4737 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4738 - insn_addresses[INSN_UID (insn)] - 8))
4740 strcpy (buf, "bb,");
4741 if ((which == 0 && negated)
4742 || (which == 1 && ! negated))
4747 strcat (buf, " %0,%1,%3%#");
4749 strcat (buf, " %0,%1,%2%#");
4753 strcpy (buf, "extrs,");
4754 if ((which == 0 && negated)
4755 || (which == 1 && ! negated))
4759 if (nullify && negated)
4760 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
4761 else if (nullify && ! negated)
4762 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
4764 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
4766 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
4776 /* This routine handles all the branch-on-variable-bit conditional branch
4777 sequences we might need to generate. It handles nullification of delay
4778 slots, varying length branches, negated branches and all combinations
4779 of the above. it returns the appropriate output template to emit the
4783 output_bvb (operands, nullify, length, negated, insn, which)
4784 rtx *operands ATTRIBUTE_UNUSED;
4785 int nullify, length, negated;
4789 static char buf[100];
4792 /* A conditional branch to the following instruction (eg the delay slot) is
4793 asking for a disaster. I do not think this can happen as this pattern
4794 is only used when optimizing; jump optimization should eliminate the
4795 jump. But be prepared just in case. */
4797 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4800 /* If this is a long branch with its delay slot unfilled, set `nullify'
4801 as it can nullify the delay slot and save a nop. */
4802 if (length == 8 && dbr_sequence_length () == 0)
4805 /* If this is a short forward conditional branch which did not get
4806 its delay slot filled, the delay slot can still be nullified. */
4807 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4808 nullify = forward_branch_p (insn);
4810 /* A forward branch over a single nullified insn can be done with a
4811 extrs instruction. This avoids a single cycle penalty due to
4812 mis-predicted branch if we fall through (branch not taken). */
4815 && next_real_insn (insn) != 0
4816 && get_attr_length (next_real_insn (insn)) == 4
4817 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4824 /* All short conditional branches except backwards with an unfilled
4828 strcpy (buf, "vextrs,");
4830 strcpy (buf, "bvb,");
4831 if ((which == 0 && negated)
4832 || (which == 1 && ! negated))
4837 strcat (buf, " %0,1,%%r0");
4838 else if (nullify && negated)
4839 strcat (buf, ",n %0,%3");
4840 else if (nullify && ! negated)
4841 strcat (buf, ",n %0,%2");
4842 else if (! nullify && negated)
4843 strcat (buf, "%0,%3");
4844 else if (! nullify && ! negated)
4845 strcat (buf, " %0,%2");
4848 /* All long conditionals. Note an short backward branch with an
4849 unfilled delay slot is treated just like a long backward branch
4850 with an unfilled delay slot. */
4852 /* Handle weird backwards branch with a filled delay slot
4853 with is nullified. */
4854 if (dbr_sequence_length () != 0
4855 && ! forward_branch_p (insn)
4858 strcpy (buf, "bvb,");
4859 if ((which == 0 && negated)
4860 || (which == 1 && ! negated))
4865 strcat (buf, ",n %0,.+12\n\tb %3");
4867 strcat (buf, ",n %0,.+12\n\tb %2");
4869 /* Handle short backwards branch with an unfilled delay slot.
4870 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4871 taken and untaken branches. */
4872 else if (dbr_sequence_length () == 0
4873 && ! forward_branch_p (insn)
4875 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4876 - insn_addresses[INSN_UID (insn)] - 8))
4878 strcpy (buf, "bvb,");
4879 if ((which == 0 && negated)
4880 || (which == 1 && ! negated))
4885 strcat (buf, " %0,%3%#");
4887 strcat (buf, " %0,%2%#");
4891 strcpy (buf, "vextrs,");
4892 if ((which == 0 && negated)
4893 || (which == 1 && ! negated))
4897 if (nullify && negated)
4898 strcat (buf, " %0,1,%%r0\n\tb,n %3");
4899 else if (nullify && ! negated)
4900 strcat (buf, " %0,1,%%r0\n\tb,n %2");
4902 strcat (buf, " %0,1,%%r0\n\tb %3");
4904 strcat (buf, " %0,1,%%r0\n\tb %2");
4914 /* Return the output template for emitting a dbra type insn.
4916 Note it may perform some output operations on its own before
4917 returning the final output string. */
4919 output_dbra (operands, insn, which_alternative)
4922 int which_alternative;
4925 /* A conditional branch to the following instruction (eg the delay slot) is
4926 asking for a disaster. Be prepared! */
4928 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4930 if (which_alternative == 0)
4931 return "ldo %1(%0),%0";
4932 else if (which_alternative == 1)
4934 output_asm_insn ("fstws %0,-16(%%r30)",operands);
4935 output_asm_insn ("ldw -16(%%r30),%4",operands);
4936 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
4937 return "fldws -16(%%r30),%0";
4941 output_asm_insn ("ldw %0,%4", operands);
4942 return "ldo %1(%4),%4\n\tstw %4,%0";
4946 if (which_alternative == 0)
4948 int nullify = INSN_ANNULLED_BRANCH_P (insn);
4949 int length = get_attr_length (insn);
4951 /* If this is a long branch with its delay slot unfilled, set `nullify'
4952 as it can nullify the delay slot and save a nop. */
4953 if (length == 8 && dbr_sequence_length () == 0)
4956 /* If this is a short forward conditional branch which did not get
4957 its delay slot filled, the delay slot can still be nullified. */
4958 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4959 nullify = forward_branch_p (insn);
4961 /* Handle short versions first. */
4962 if (length == 4 && nullify)
4963 return "addib,%C2,n %1,%0,%3";
4964 else if (length == 4 && ! nullify)
4965 return "addib,%C2 %1,%0,%3";
4966 else if (length == 8)
4968 /* Handle weird backwards branch with a fulled delay slot
4969 which is nullified. */
4970 if (dbr_sequence_length () != 0
4971 && ! forward_branch_p (insn)
4973 return "addib,%N2,n %1,%0,.+12\n\tb %3";
4974 /* Handle short backwards branch with an unfilled delay slot.
4975 Using a addb;nop rather than addi;bl saves 1 cycle for both
4976 taken and untaken branches. */
4977 else if (dbr_sequence_length () == 0
4978 && ! forward_branch_p (insn)
4980 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4981 - insn_addresses[INSN_UID (insn)] - 8))
4982 return "addib,%C2 %1,%0,%3%#";
4984 /* Handle normal cases. */
4986 return "addi,%N2 %1,%0,%0\n\tb,n %3";
4988 return "addi,%N2 %1,%0,%0\n\tb %3";
4993 /* Deal with gross reload from FP register case. */
4994 else if (which_alternative == 1)
4996 /* Move loop counter from FP register to MEM then into a GR,
4997 increment the GR, store the GR into MEM, and finally reload
4998 the FP register from MEM from within the branch's delay slot. */
4999 output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
5000 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5001 if (get_attr_length (insn) == 24)
5002 return "comb,%S2 %%r0,%4,%3\n\tfldws -16(%%r30),%0";
5004 return "comclr,%B2 %%r0,%4,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
5006 /* Deal with gross reload from memory case. */
5009 /* Reload loop counter from memory, the store back to memory
5010 happens in the branch's delay slot. */
5011 output_asm_insn ("ldw %0,%4", operands);
5012 if (get_attr_length (insn) == 12)
5013 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5015 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5019 /* Return the output template for emitting a dbra type insn.
5021 Note it may perform some output operations on its own before
5022 returning the final output string. */
5024 output_movb (operands, insn, which_alternative, reverse_comparison)
5027 int which_alternative;
5028 int reverse_comparison;
5031 /* A conditional branch to the following instruction (eg the delay slot) is
5032 asking for a disaster. Be prepared! */
5034 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5036 if (which_alternative == 0)
5037 return "copy %1,%0";
5038 else if (which_alternative == 1)
5040 output_asm_insn ("stw %1,-16(%%r30)",operands);
5041 return "fldws -16(%%r30),%0";
5043 else if (which_alternative == 2)
5049 /* Support the second variant. */
5050 if (reverse_comparison)
5051 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5053 if (which_alternative == 0)
5055 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5056 int length = get_attr_length (insn);
5058 /* If this is a long branch with its delay slot unfilled, set `nullify'
5059 as it can nullify the delay slot and save a nop. */
5060 if (length == 8 && dbr_sequence_length () == 0)
5063 /* If this is a short forward conditional branch which did not get
5064 its delay slot filled, the delay slot can still be nullified. */
5065 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5066 nullify = forward_branch_p (insn);
5068 /* Handle short versions first. */
5069 if (length == 4 && nullify)
5070 return "movb,%C2,n %1,%0,%3";
5071 else if (length == 4 && ! nullify)
5072 return "movb,%C2 %1,%0,%3";
5073 else if (length == 8)
5075 /* Handle weird backwards branch with a filled delay slot
5076 which is nullified. */
5077 if (dbr_sequence_length () != 0
5078 && ! forward_branch_p (insn)
5080 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5082 /* Handle short backwards branch with an unfilled delay slot.
5083 Using a movb;nop rather than or;bl saves 1 cycle for both
5084 taken and untaken branches. */
5085 else if (dbr_sequence_length () == 0
5086 && ! forward_branch_p (insn)
5088 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
5089 - insn_addresses[INSN_UID (insn)] - 8))
5090 return "movb,%C2 %1,%0,%3%#";
5091 /* Handle normal cases. */
5093 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5095 return "or,%N2 %1,%%r0,%0\n\tb %3";
5100 /* Deal with gross reload from FP register case. */
5101 else if (which_alternative == 1)
5103 /* Move loop counter from FP register to MEM then into a GR,
5104 increment the GR, store the GR into MEM, and finally reload
5105 the FP register from MEM from within the branch's delay slot. */
5106 output_asm_insn ("stw %1,-16(%%r30)",operands);
5107 if (get_attr_length (insn) == 12)
5108 return "comb,%S2 %%r0,%1,%3\n\tfldws -16(%%r30),%0";
5110 return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
5112 /* Deal with gross reload from memory case. */
5113 else if (which_alternative == 2)
5115 /* Reload loop counter from memory, the store back to memory
5116 happens in the branch's delay slot. */
5117 if (get_attr_length (insn) == 8)
5118 return "comb,%S2 %%r0,%1,%3\n\tstw %1,%0";
5120 return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5122 /* Handle SAR as a destination. */
5125 if (get_attr_length (insn) == 8)
5126 return "comb,%S2 %%r0,%1,%3\n\tmtsar %r1";
5128 return "comclr,%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5133 /* INSN is a millicode call. It may have an unconditional jump in its delay
5136 CALL_DEST is the routine we are calling. */
5139 output_millicode_call (insn, call_dest)
5147 /* Handle common case -- empty delay slot or no jump in the delay slot,
5148 and we're sure that the branch will reach the beginning of the $CODE$
5150 if ((dbr_sequence_length () == 0
5151 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5152 || (dbr_sequence_length () != 0
5153 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5154 && get_attr_length (insn) == 4))
5156 xoperands[0] = call_dest;
5157 output_asm_insn ("bl %0,%%r31%#", xoperands);
5161 /* This call may not reach the beginning of the $CODE$ subspace. */
5162 if (get_attr_length (insn) > 4)
5164 int delay_insn_deleted = 0;
5167 /* We need to emit an inline long-call branch. */
5168 if (dbr_sequence_length () != 0
5169 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5171 /* A non-jump insn in the delay slot. By definition we can
5172 emit this insn before the call. */
5173 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5175 /* Now delete the delay insn. */
5176 PUT_CODE (NEXT_INSN (insn), NOTE);
5177 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5178 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5179 delay_insn_deleted = 1;
5182 /* If we're allowed to use be/ble instructions, then this is the
5183 best sequence to use for a long millicode call. */
5184 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS
5185 || ! (flag_pic || TARGET_PORTABLE_RUNTIME))
5187 xoperands[0] = call_dest;
5188 output_asm_insn ("ldil L%%%0,%%r31", xoperands);
5189 output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands);
5190 output_asm_insn ("nop", xoperands);
5192 /* Pure portable runtime doesn't allow be/ble; we also don't have
5193 PIC support int he assembler/linker, so this sequence is needed. */
5194 else if (TARGET_PORTABLE_RUNTIME)
5196 xoperands[0] = call_dest;
5197 /* Get the address of our target into %r29. */
5198 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5199 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5201 /* Get our return address into %r31. */
5202 output_asm_insn ("blr %%r0,%%r31", xoperands);
5204 /* Jump to our target address in %r29. */
5205 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5207 /* Empty delay slot. Note this insn gets fetched twice and
5208 executed once. To be safe we use a nop. */
5209 output_asm_insn ("nop", xoperands);
5212 /* PIC long millicode call sequence. */
5215 xoperands[0] = call_dest;
5216 xoperands[1] = gen_label_rtx ();
5217 /* Get our address + 8 into %r1. */
5218 output_asm_insn ("bl .+8,%%r1", xoperands);
5220 /* Add %r1 to the offset of our target from the next insn. */
5221 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5222 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5223 CODE_LABEL_NUMBER (xoperands[1]));
5224 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5226 /* Get the return address into %r31. */
5227 output_asm_insn ("blr 0,%%r31", xoperands);
5229 /* Branch to our target which is in %r1. */
5230 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5232 /* Empty delay slot. Note this insn gets fetched twice and
5233 executed once. To be safe we use a nop. */
5234 output_asm_insn ("nop", xoperands);
5237 /* If we had a jump in the call's delay slot, output it now. */
5238 if (dbr_sequence_length () != 0
5239 && !delay_insn_deleted)
5241 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5242 output_asm_insn ("b,n %0", xoperands);
5244 /* Now delete the delay insn. */
5245 PUT_CODE (NEXT_INSN (insn), NOTE);
5246 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5247 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5252 /* This call has an unconditional jump in its delay slot and the
5253 call is known to reach its target or the beginning of the current
5256 /* Use the containing sequence insn's address. */
5257 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5259 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
5260 - insn_addresses[INSN_UID (seq_insn)] - 8;
5262 /* If the branch was too far away, emit a normal call followed
5263 by a nop, followed by the unconditional branch.
5265 If the branch is close, then adjust %r2 from within the
5266 call's delay slot. */
5268 xoperands[0] = call_dest;
5269 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5270 if (! VAL_14_BITS_P (distance))
5271 output_asm_insn ("bl %0,%%r31\n\tnop\n\tb,n %1", xoperands);
5274 xoperands[3] = gen_label_rtx ();
5275 output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands);
5276 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5277 CODE_LABEL_NUMBER (xoperands[3]));
5280 /* Delete the jump. */
5281 PUT_CODE (NEXT_INSN (insn), NOTE);
5282 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5283 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5287 extern struct obstack permanent_obstack;
5288 extern struct obstack *saveable_obstack;
5289 extern struct obstack *rtl_obstack;
5290 extern struct obstack *current_obstack;
5292 /* INSN is either a function call. It may have an unconditional jump
5295 CALL_DEST is the routine we are calling. */
5298 output_call (insn, call_dest)
5306 /* Handle common case -- empty delay slot or no jump in the delay slot,
5307 and we're sure that the branch will reach the beginning of the $CODE$
5309 if ((dbr_sequence_length () == 0
5310 && get_attr_length (insn) == 8)
5311 || (dbr_sequence_length () != 0
5312 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5313 && get_attr_length (insn) == 4))
5315 xoperands[0] = call_dest;
5316 output_asm_insn ("bl %0,%%r2%#", xoperands);
5320 /* This call may not reach the beginning of the $CODE$ subspace. */
5321 if (get_attr_length (insn) > 8)
5323 int delay_insn_deleted = 0;
5327 /* We need to emit an inline long-call branch. Furthermore,
5328 because we're changing a named function call into an indirect
5329 function call well after the parameters have been set up, we
5330 need to make sure any FP args appear in both the integer
5331 and FP registers. Also, we need move any delay slot insn
5332 out of the delay slot. And finally, we can't rely on the linker
5333 being able to fix the call to $$dyncall! -- Yuk!. */
5334 if (dbr_sequence_length () != 0
5335 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5337 /* A non-jump insn in the delay slot. By definition we can
5338 emit this insn before the call (and in fact before argument
5340 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5342 /* Now delete the delay insn. */
5343 PUT_CODE (NEXT_INSN (insn), NOTE);
5344 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5345 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5346 delay_insn_deleted = 1;
5349 /* Now copy any FP arguments into integer registers. */
5350 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5352 int arg_mode, regno;
5353 rtx use = XEXP (link, 0);
5354 if (! (GET_CODE (use) == USE
5355 && GET_CODE (XEXP (use, 0)) == REG
5356 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5359 arg_mode = GET_MODE (XEXP (use, 0));
5360 regno = REGNO (XEXP (use, 0));
5361 /* Is it a floating point register? */
5362 if (regno >= 32 && regno <= 39)
5364 /* Copy from the FP register into an integer register
5366 if (arg_mode == SFmode)
5368 xoperands[0] = XEXP (use, 0);
5369 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5370 output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands);
5371 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5375 xoperands[0] = XEXP (use, 0);
5376 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5377 output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands);
5378 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5379 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5384 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5385 we don't have any direct calls in that case. */
5388 char *name = XSTR (call_dest, 0);
5390 /* See if we have already put this function on the list
5391 of deferred plabels. This list is generally small,
5392 so a liner search is not too ugly. If it proves too
5393 slow replace it with something faster. */
5394 for (i = 0; i < n_deferred_plabels; i++)
5395 if (strcmp (name, deferred_plabels[i].name) == 0)
5398 /* If the deferred plabel list is empty, or this entry was
5399 not found on the list, create a new entry on the list. */
5400 if (deferred_plabels == NULL || i == n_deferred_plabels)
5402 struct obstack *ambient_obstack = current_obstack;
5403 struct obstack *ambient_rtl_obstack = rtl_obstack;
5406 /* Any RTL we create here needs to live until the end of
5407 the compilation unit and therefore must live on the
5408 permanent obstack. */
5409 current_obstack = &permanent_obstack;
5410 rtl_obstack = &permanent_obstack;
5412 if (deferred_plabels == 0)
5413 deferred_plabels = (struct deferred_plabel *)
5414 xmalloc (1 * sizeof (struct deferred_plabel));
5416 deferred_plabels = (struct deferred_plabel *)
5417 xrealloc (deferred_plabels,
5418 ((n_deferred_plabels + 1)
5419 * sizeof (struct deferred_plabel)));
5421 i = n_deferred_plabels++;
5422 deferred_plabels[i].internal_label = gen_label_rtx ();
5423 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
5425 strcpy (deferred_plabels[i].name, name);
5427 /* Switch back to normal obstack allocation. */
5428 current_obstack = ambient_obstack;
5429 rtl_obstack = ambient_rtl_obstack;
5431 /* Gross. We have just implicitly taken the address of this
5432 function, mark it as such. */
5433 STRIP_NAME_ENCODING (real_name, name);
5434 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5437 /* We have to load the address of the function using a procedure
5438 label (plabel). Inline plabels can lose for PIC and other
5439 cases, so avoid them by creating a 32bit plabel in the data
5443 xoperands[0] = deferred_plabels[i].internal_label;
5444 xoperands[1] = gen_label_rtx ();
5446 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
5447 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
5448 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
5450 /* Get our address + 8 into %r1. */
5451 output_asm_insn ("bl .+8,%%r1", xoperands);
5453 /* Add %r1 to the offset of dyncall from the next insn. */
5454 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
5455 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5456 CODE_LABEL_NUMBER (xoperands[1]));
5457 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
5459 /* Get the return address into %r31. */
5460 output_asm_insn ("blr %%r0,%%r31", xoperands);
5462 /* Branch to our target which is in %r1. */
5463 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5465 /* Copy the return address into %r2 also. */
5466 output_asm_insn ("copy %%r31,%%r2", xoperands);
5470 xoperands[0] = deferred_plabels[i].internal_label;
5472 /* Get the address of our target into %r22. */
5473 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
5474 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
5476 /* Get the high part of the address of $dyncall into %r2, then
5477 add in the low part in the branch instruction. */
5478 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
5479 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
5481 /* Copy the return pointer into both %r31 and %r2. */
5482 output_asm_insn ("copy %%r31,%%r2", xoperands);
5486 /* If we had a jump in the call's delay slot, output it now. */
5487 if (dbr_sequence_length () != 0
5488 && !delay_insn_deleted)
5490 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5491 output_asm_insn ("b,n %0", xoperands);
5493 /* Now delete the delay insn. */
5494 PUT_CODE (NEXT_INSN (insn), NOTE);
5495 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5496 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5501 /* This call has an unconditional jump in its delay slot and the
5502 call is known to reach its target or the beginning of the current
5505 /* Use the containing sequence insn's address. */
5506 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5508 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
5509 - insn_addresses[INSN_UID (seq_insn)] - 8;
5511 /* If the branch was too far away, emit a normal call followed
5512 by a nop, followed by the unconditional branch.
5514 If the branch is close, then adjust %r2 from within the
5515 call's delay slot. */
5517 xoperands[0] = call_dest;
5518 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5519 if (! VAL_14_BITS_P (distance))
5520 output_asm_insn ("bl %0,%%r2\n\tnop\n\tb,n %1", xoperands);
5523 xoperands[3] = gen_label_rtx ();
5524 output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands);
5525 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5526 CODE_LABEL_NUMBER (xoperands[3]));
5529 /* Delete the jump. */
5530 PUT_CODE (NEXT_INSN (insn), NOTE);
5531 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5532 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5536 /* In HPUX 8.0's shared library scheme, special relocations are needed
5537 for function labels if they might be passed to a function
5538 in a shared library (because shared libraries don't live in code
5539 space), and special magic is needed to construct their address.
5541 For reasons too disgusting to describe storage for the new name
5542 is allocated either on the saveable_obstack (released at function
5543 exit) or on the permanent_obstack for things that can never change
5544 (libcall names for example). */
5547 hppa_encode_label (sym, permanent)
5551 char *str = XSTR (sym, 0);
5552 int len = strlen (str);
5555 newstr = obstack_alloc ((permanent ? &permanent_obstack : saveable_obstack),
5560 strcpy (newstr + 1, str);
5562 XSTR (sym,0) = newstr;
5566 function_label_operand (op, mode)
5568 enum machine_mode mode ATTRIBUTE_UNUSED;
5570 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
5573 /* Returns 1 if OP is a function label involved in a simple addition
5574 with a constant. Used to keep certain patterns from matching
5575 during instruction combination. */
5577 is_function_label_plus_const (op)
5580 /* Strip off any CONST. */
5581 if (GET_CODE (op) == CONST)
5584 return (GET_CODE (op) == PLUS
5585 && function_label_operand (XEXP (op, 0), Pmode)
5586 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5589 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5590 use in fmpyadd instructions. */
5592 fmpyaddoperands (operands)
5595 enum machine_mode mode = GET_MODE (operands[0]);
5597 /* Must be a floating point mode. */
5598 if (mode != SFmode && mode != DFmode)
5601 /* All modes must be the same. */
5602 if (! (mode == GET_MODE (operands[1])
5603 && mode == GET_MODE (operands[2])
5604 && mode == GET_MODE (operands[3])
5605 && mode == GET_MODE (operands[4])
5606 && mode == GET_MODE (operands[5])))
5609 /* All operands must be registers. */
5610 if (! (GET_CODE (operands[1]) == REG
5611 && GET_CODE (operands[2]) == REG
5612 && GET_CODE (operands[3]) == REG
5613 && GET_CODE (operands[4]) == REG
5614 && GET_CODE (operands[5]) == REG))
5617 /* Only 2 real operands to the addition. One of the input operands must
5618 be the same as the output operand. */
5619 if (! rtx_equal_p (operands[3], operands[4])
5620 && ! rtx_equal_p (operands[3], operands[5]))
5623 /* Inout operand of add can not conflict with any operands from multiply. */
5624 if (rtx_equal_p (operands[3], operands[0])
5625 || rtx_equal_p (operands[3], operands[1])
5626 || rtx_equal_p (operands[3], operands[2]))
5629 /* multiply can not feed into addition operands. */
5630 if (rtx_equal_p (operands[4], operands[0])
5631 || rtx_equal_p (operands[5], operands[0]))
5634 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5636 && (REGNO (operands[0]) < 57
5637 || REGNO (operands[1]) < 57
5638 || REGNO (operands[2]) < 57
5639 || REGNO (operands[3]) < 57
5640 || REGNO (operands[4]) < 57
5641 || REGNO (operands[5]) < 57))
5644 /* Passed. Operands are suitable for fmpyadd. */
5648 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5649 use in fmpysub instructions. */
5651 fmpysuboperands (operands)
5654 enum machine_mode mode = GET_MODE (operands[0]);
5656 /* Must be a floating point mode. */
5657 if (mode != SFmode && mode != DFmode)
5660 /* All modes must be the same. */
5661 if (! (mode == GET_MODE (operands[1])
5662 && mode == GET_MODE (operands[2])
5663 && mode == GET_MODE (operands[3])
5664 && mode == GET_MODE (operands[4])
5665 && mode == GET_MODE (operands[5])))
5668 /* All operands must be registers. */
5669 if (! (GET_CODE (operands[1]) == REG
5670 && GET_CODE (operands[2]) == REG
5671 && GET_CODE (operands[3]) == REG
5672 && GET_CODE (operands[4]) == REG
5673 && GET_CODE (operands[5]) == REG))
5676 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
5677 operation, so operands[4] must be the same as operand[3]. */
5678 if (! rtx_equal_p (operands[3], operands[4]))
5681 /* multiply can not feed into subtraction. */
5682 if (rtx_equal_p (operands[5], operands[0]))
5685 /* Inout operand of sub can not conflict with any operands from multiply. */
5686 if (rtx_equal_p (operands[3], operands[0])
5687 || rtx_equal_p (operands[3], operands[1])
5688 || rtx_equal_p (operands[3], operands[2]))
5691 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5693 && (REGNO (operands[0]) < 57
5694 || REGNO (operands[1]) < 57
5695 || REGNO (operands[2]) < 57
5696 || REGNO (operands[3]) < 57
5697 || REGNO (operands[4]) < 57
5698 || REGNO (operands[5]) < 57))
5701 /* Passed. Operands are suitable for fmpysub. */
5706 plus_xor_ior_operator (op, mode)
5708 enum machine_mode mode ATTRIBUTE_UNUSED;
5710 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
5711 || GET_CODE (op) == IOR);
5714 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
5715 constants for shadd instructions. */
5717 shadd_constant_p (val)
5720 if (val == 2 || val == 4 || val == 8)
5726 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
5727 the valid constant for shadd instructions. */
5729 shadd_operand (op, mode)
5731 enum machine_mode mode ATTRIBUTE_UNUSED;
5733 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
5736 /* Return 1 if OP is valid as a base register in a reg + reg address. */
5739 basereg_operand (op, mode)
5741 enum machine_mode mode;
5743 /* cse will create some unscaled indexed addresses, however; it
5744 generally isn't a win on the PA, so avoid creating unscaled
5745 indexed addresses until after cse is finished. */
5746 if (!cse_not_expected)
5749 /* Once reload has started everything is considered valid. Reload should
5750 only create indexed addresses using the stack/frame pointer, and any
5751 others were checked for validity when created by the combine pass.
5753 Also allow any register when TARGET_NO_SPACE_REGS is in effect since
5754 we don't have to worry about the braindamaged implicit space register
5755 selection using the basereg only (rather than effective address)
5756 screwing us over. */
5757 if (TARGET_NO_SPACE_REGS || reload_in_progress || reload_completed)
5758 return (GET_CODE (op) == REG);
5760 /* Stack is always OK for indexing. */
5761 if (op == stack_pointer_rtx)
5764 /* While it's always safe to index off the frame pointer, it's not
5765 always profitable, particularly when the frame pointer is being
5767 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
5770 /* The only other valid OPs are pseudo registers with
5771 REGNO_POINTER_FLAG set. */
5772 if (GET_CODE (op) != REG
5773 || REGNO (op) < FIRST_PSEUDO_REGISTER
5774 || ! register_operand (op, mode))
5777 return REGNO_POINTER_FLAG (REGNO (op));
5780 /* Return 1 if this operand is anything other than a hard register. */
5783 non_hard_reg_operand (op, mode)
5785 enum machine_mode mode ATTRIBUTE_UNUSED;
5787 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
5790 /* Return 1 if INSN branches forward. Should be using insn_addresses
5791 to avoid walking through all the insns... */
5793 forward_branch_p (insn)
5796 rtx label = JUMP_LABEL (insn);
5803 insn = NEXT_INSN (insn);
5806 return (insn == label);
5809 /* Return 1 if OP is an equality comparison, else return 0. */
5811 eq_neq_comparison_operator (op, mode)
5813 enum machine_mode mode ATTRIBUTE_UNUSED;
5815 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
5818 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
5820 movb_comparison_operator (op, mode)
5822 enum machine_mode mode ATTRIBUTE_UNUSED;
5824 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
5825 || GET_CODE (op) == LT || GET_CODE (op) == GE);
5828 /* Return 1 if INSN is in the delay slot of a call instruction. */
5830 jump_in_call_delay (insn)
5834 if (GET_CODE (insn) != JUMP_INSN)
5837 if (PREV_INSN (insn)
5838 && PREV_INSN (PREV_INSN (insn))
5839 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
5841 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
5843 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
5844 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
5851 /* Output an unconditional move and branch insn. */
5854 output_parallel_movb (operands, length)
5858 /* These are the cases in which we win. */
5860 return "mov%I1b,tr %1,%0,%2";
5862 /* None of these cases wins, but they don't lose either. */
5863 if (dbr_sequence_length () == 0)
5865 /* Nothing in the delay slot, fake it by putting the combined
5866 insn (the copy or add) in the delay slot of a bl. */
5867 if (GET_CODE (operands[1]) == CONST_INT)
5868 return "b %2\n\tldi %1,%0";
5870 return "b %2\n\tcopy %1,%0";
5874 /* Something in the delay slot, but we've got a long branch. */
5875 if (GET_CODE (operands[1]) == CONST_INT)
5876 return "ldi %1,%0\n\tb %2";
5878 return "copy %1,%0\n\tb %2";
5882 /* Output an unconditional add and branch insn. */
5885 output_parallel_addb (operands, length)
5889 /* To make life easy we want operand0 to be the shared input/output
5890 operand and operand1 to be the readonly operand. */
5891 if (operands[0] == operands[1])
5892 operands[1] = operands[2];
5894 /* These are the cases in which we win. */
5896 return "add%I1b,tr %1,%0,%3";
5898 /* None of these cases win, but they don't lose either. */
5899 if (dbr_sequence_length () == 0)
5901 /* Nothing in the delay slot, fake it by putting the combined
5902 insn (the copy or add) in the delay slot of a bl. */
5903 return "b %3\n\tadd%I1 %1,%0,%0";
5907 /* Something in the delay slot, but we've got a long branch. */
5908 return "add%I1 %1,%0,%0\n\tb %3";
5912 /* Return nonzero if INSN (a jump insn) immediately follows a call to
5913 a named function. This is used to discourage creating parallel movb/addb
5914 insns since a jump which immediately follows a call can execute in the
5915 delay slot of the call.
5917 It is also used to avoid filling the delay slot of a jump which
5918 immediately follows a call since the jump can usually be eliminated
5919 completely by modifying RP in the delay slot of the call. */
5922 following_call (insn)
5925 /* Find the previous real insn, skipping NOTEs. */
5926 insn = PREV_INSN (insn);
5927 while (insn && GET_CODE (insn) == NOTE)
5928 insn = PREV_INSN (insn);
5930 /* Check for CALL_INSNs and millicode calls. */
5932 && ((GET_CODE (insn) == CALL_INSN
5933 && get_attr_type (insn) != TYPE_DYNCALL)
5934 || (GET_CODE (insn) == INSN
5935 && GET_CODE (PATTERN (insn)) != SEQUENCE
5936 && GET_CODE (PATTERN (insn)) != USE
5937 && GET_CODE (PATTERN (insn)) != CLOBBER
5938 && get_attr_type (insn) == TYPE_MILLI)))
5944 /* Restore any INSN_CODEs for insns with unscaled indexed addresses since
5945 the INSN_CODE might be clobberd by rerecognition triggered by reorg. */
5948 restore_unscaled_index_insn_codes (insns)
5953 for (insn = insns; insn; insn = NEXT_INSN (insn))
5955 if (INSN_UID (insn) < max_unscaled_index_insn_codes_uid
5956 && unscaled_index_insn_codes[INSN_UID (insn)] != -1)
5957 INSN_CODE (insn) = unscaled_index_insn_codes[INSN_UID (insn)];
5961 /* Severe braindamage:
5963 On the PA, address computations within MEM expressions are not
5964 commutative because of the implicit space register selection
5965 from the base register (instead of the entire effective address).
5967 Because of this mis-feature we have to know which register in a reg+reg
5968 address is the base and which is the index.
5970 Before reload, the base can be identified by REGNO_POINTER_FLAG. We use
5971 this to force base + index addresses to match a different insn than
5972 index + base addresses.
5974 We assume that no pass during or after reload creates new unscaled indexed
5975 addresses, so any unscaled indexed address we find after reload must have
5976 at one time been recognized a base + index or index + base and we accept
5977 any register as a base register.
5979 This scheme assumes that no pass during/after reload will rerecognize an
5980 insn with an unscaled indexed address. This failed due to a reorg call
5981 to rerecognize certain insns.
5983 So, we record if an insn uses an unscaled indexed address and which
5984 register is the base (via recording of the INSN_CODE for such insns).
5986 Just before we output code for the function, we make sure all the insns
5987 using unscaled indexed addresses have the same INSN_CODE as they did
5988 immediately before delay slot scheduling.
5990 This is extremely gross. Long term, I'd like to be able to look at
5991 REG_POINTER_FLAG to handle these kinds of problems. */
5994 record_unscaled_index_insn_codes (insns)
5999 max_unscaled_index_insn_codes_uid = get_max_uid ();
6000 unscaled_index_insn_codes
6001 = (int *)xmalloc (max_unscaled_index_insn_codes_uid * sizeof (int));
6002 memset (unscaled_index_insn_codes, -1,
6003 max_unscaled_index_insn_codes_uid * sizeof (int));
6005 for (insn = insns; insn; insn = NEXT_INSN (insn))
6007 rtx set = single_set (insn);
6010 /* Ignore anything that isn't a normal SET. */
6011 if (set == NULL_RTX)
6014 /* No insns can have more than one MEM. */
6015 if (GET_CODE (SET_SRC (set)) == MEM)
6016 mem = SET_SRC (set);
6018 if (GET_CODE (SET_DEST (set)) == MEM)
6019 mem = SET_DEST (set);
6021 /* If neither operand is a mem, then there's nothing to do. */
6022 if (mem == NULL_RTX)
6025 if (GET_CODE (XEXP (mem, 0)) != PLUS)
6028 /* If both are REGs (or SUBREGs), then record the insn code for
6030 if (REG_P (XEXP (XEXP (mem, 0), 0)) && REG_P (XEXP (XEXP (mem, 0), 1)))
6031 unscaled_index_insn_codes[INSN_UID (insn)] = INSN_CODE (insn);
6035 /* We use this hook to perform a PA specific optimization which is difficult
6036 to do in earlier passes.
6038 We want the delay slots of branches within jump tables to be filled.
6039 None of the compiler passes at the moment even has the notion that a
6040 PA jump table doesn't contain addresses, but instead contains actual
6043 Because we actually jump into the table, the addresses of each entry
6044 must stay constant in relation to the beginning of the table (which
6045 itself must stay constant relative to the instruction to jump into
6046 it). I don't believe we can guarantee earlier passes of the compiler
6047 will adhere to those rules.
6049 So, late in the compilation process we find all the jump tables, and
6050 expand them into real code -- eg each entry in the jump table vector
6051 will get an appropriate label followed by a jump to the final target.
6053 Reorg and the final jump pass can then optimize these branches and
6054 fill their delay slots. We end up with smaller, more efficient code.
6056 The jump instructions within the table are special; we must be able
6057 to identify them during assembly output (if the jumps don't get filled
6058 we need to emit a nop rather than nullifying the delay slot)). We
6059 identify jumps in switch tables by marking the SET with DImode.
6061 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6062 insns. This serves two purposes, first it prevents jump.c from
6063 noticing that the last N entries in the table jump to the instruction
6064 immediately after the table and deleting the jumps. Second, those
6065 insns mark where we should emit .begin_brtab and .end_brtab directives
6066 when using GAS (allows for better link time optimizations). */
6074 /* Keep track of which insns have unscaled indexed addresses, and which
6075 register is the base address in such insns. */
6076 record_unscaled_index_insn_codes (insns);
6078 remove_useless_addtr_insns (insns, 1);
6080 if (pa_cpu < PROCESSOR_8000)
6081 pa_combine_instructions (get_insns ());
6084 /* This is fairly cheap, so always run it if optimizing. */
6085 if (optimize > 0 && !TARGET_BIG_SWITCH)
6087 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6088 insns = get_insns ();
6089 for (insn = insns; insn; insn = NEXT_INSN (insn))
6091 rtx pattern, tmp, location;
6092 unsigned int length, i;
6094 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6095 if (GET_CODE (insn) != JUMP_INSN
6096 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6097 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6100 /* Emit marker for the beginning of the branch table. */
6101 emit_insn_before (gen_begin_brtab (), insn);
6103 pattern = PATTERN (insn);
6104 location = PREV_INSN (insn);
6105 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6107 for (i = 0; i < length; i++)
6109 /* Emit a label before each jump to keep jump.c from
6110 removing this code. */
6111 tmp = gen_label_rtx ();
6112 LABEL_NUSES (tmp) = 1;
6113 emit_label_after (tmp, location);
6114 location = NEXT_INSN (location);
6116 if (GET_CODE (pattern) == ADDR_VEC)
6118 /* Emit the jump itself. */
6119 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6120 tmp = emit_jump_insn_after (tmp, location);
6121 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6122 /* It is easy to rely on the branch table markers
6123 during assembly output to trigger the correct code
6124 for a switch table jump with an unfilled delay slot,
6126 However, that requires state and assumes that we look
6129 We can't make such assumptions when computing the length
6130 of instructions. Ugh. We could walk the insn chain to
6131 determine if this instruction is in a branch table, but
6132 that can get rather expensive, particularly during the
6133 branch shortening phase of the compiler.
6135 So instead we mark this jump as being special. This is
6136 far from ideal and knows that no code after this will
6137 muck around with the mode of the JUMP_INSN itself. */
6138 PUT_MODE (tmp, SImode);
6139 LABEL_NUSES (JUMP_LABEL (tmp))++;
6140 location = NEXT_INSN (location);
6144 /* Emit the jump itself. */
6145 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6146 tmp = emit_jump_insn_after (tmp, location);
6147 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6148 /* It is easy to rely on the branch table markers
6149 during assembly output to trigger the correct code
6150 for a switch table jump with an unfilled delay slot,
6152 However, that requires state and assumes that we look
6155 We can't make such assumptions when computing the length
6156 of instructions. Ugh. We could walk the insn chain to
6157 determine if this instruction is in a branch table, but
6158 that can get rather expensive, particularly during the
6159 branch shortening phase of the compiler.
6161 So instead we mark this jump as being special. This is
6162 far from ideal and knows that no code after this will
6163 muck around with the mode of the JUMP_INSN itself. */
6164 PUT_MODE (tmp, SImode);
6165 LABEL_NUSES (JUMP_LABEL (tmp))++;
6166 location = NEXT_INSN (location);
6169 /* Emit a BARRIER after the jump. */
6170 emit_barrier_after (location);
6171 location = NEXT_INSN (location);
6174 /* Emit marker for the end of the branch table. */
6175 emit_insn_before (gen_end_brtab (), location);
6176 location = NEXT_INSN (location);
6177 emit_barrier_after (location);
6179 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6185 /* Sill need an end_brtab insn. */
6186 insns = get_insns ();
6187 for (insn = insns; insn; insn = NEXT_INSN (insn))
6189 /* Find an ADDR_VEC insn. */
6190 if (GET_CODE (insn) != JUMP_INSN
6191 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6192 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6195 /* Now generate markers for the beginning and end of the
6197 emit_insn_before (gen_begin_brtab (), insn);
6198 emit_insn_after (gen_end_brtab (), insn);
6203 /* The PA has a number of odd instructions which can perform multiple
6204 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6205 it may be profitable to combine two instructions into one instruction
6206 with two outputs. It's not profitable PA2.0 machines because the
6207 two outputs would take two slots in the reorder buffers.
6209 This routine finds instructions which can be combined and combines
6210 them. We only support some of the potential combinations, and we
6211 only try common ways to find suitable instructions.
6213 * addb can add two registers or a register and a small integer
6214 and jump to a nearby (+-8k) location. Normally the jump to the
6215 nearby location is conditional on the result of the add, but by
6216 using the "true" condition we can make the jump unconditional.
6217 Thus addb can perform two independent operations in one insn.
6219 * movb is similar to addb in that it can perform a reg->reg
6220 or small immediate->reg copy and jump to a nearby (+-8k location).
6222 * fmpyadd and fmpysub can perform a FP multiply and either an
6223 FP add or FP sub if the operands of the multiply and add/sub are
6224 independent (there are other minor restrictions). Note both
6225 the fmpy and fadd/fsub can in theory move to better spots according
6226 to data dependencies, but for now we require the fmpy stay at a
6229 * Many of the memory operations can perform pre & post updates
6230 of index registers. GCC's pre/post increment/decrement addressing
6231 is far too simple to take advantage of all the possibilities. This
6232 pass may not be suitable since those insns may not be independent.
6234 * comclr can compare two ints or an int and a register, nullify
6235 the following instruction and zero some other register. This
6236 is more difficult to use as it's harder to find an insn which
6237 will generate a comclr than finding something like an unconditional
6238 branch. (conditional moves & long branches create comclr insns).
6240 * Most arithmetic operations can conditionally skip the next
6241 instruction. They can be viewed as "perform this operation
6242 and conditionally jump to this nearby location" (where nearby
6243 is an insns away). These are difficult to use due to the
6244 branch length restrictions. */
6247 pa_combine_instructions (insns)
6248 rtx insns ATTRIBUTE_UNUSED;
6252 /* This can get expensive since the basic algorithm is on the
6253 order of O(n^2) (or worse). Only do it for -O2 or higher
6254 levels of optimization. */
6258 /* Walk down the list of insns looking for "anchor" insns which
6259 may be combined with "floating" insns. As the name implies,
6260 "anchor" instructions don't move, while "floating" insns may
6262 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6263 new = make_insn_raw (new);
6265 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6267 enum attr_pa_combine_type anchor_attr;
6268 enum attr_pa_combine_type floater_attr;
6270 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6271 Also ignore any special USE insns. */
6272 if ((GET_CODE (anchor) != INSN
6273 && GET_CODE (anchor) != JUMP_INSN
6274 && GET_CODE (anchor) != CALL_INSN)
6275 || GET_CODE (PATTERN (anchor)) == USE
6276 || GET_CODE (PATTERN (anchor)) == CLOBBER
6277 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6278 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6281 anchor_attr = get_attr_pa_combine_type (anchor);
6282 /* See if anchor is an insn suitable for combination. */
6283 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6284 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6285 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6286 && ! forward_branch_p (anchor)))
6290 for (floater = PREV_INSN (anchor);
6292 floater = PREV_INSN (floater))
6294 if (GET_CODE (floater) == NOTE
6295 || (GET_CODE (floater) == INSN
6296 && (GET_CODE (PATTERN (floater)) == USE
6297 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6300 /* Anything except a regular INSN will stop our search. */
6301 if (GET_CODE (floater) != INSN
6302 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6303 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6309 /* See if FLOATER is suitable for combination with the
6311 floater_attr = get_attr_pa_combine_type (floater);
6312 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6313 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6314 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6315 && floater_attr == PA_COMBINE_TYPE_FMPY))
6317 /* If ANCHOR and FLOATER can be combined, then we're
6318 done with this pass. */
6319 if (pa_can_combine_p (new, anchor, floater, 0,
6320 SET_DEST (PATTERN (floater)),
6321 XEXP (SET_SRC (PATTERN (floater)), 0),
6322 XEXP (SET_SRC (PATTERN (floater)), 1)))
6326 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6327 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6329 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6331 if (pa_can_combine_p (new, anchor, floater, 0,
6332 SET_DEST (PATTERN (floater)),
6333 XEXP (SET_SRC (PATTERN (floater)), 0),
6334 XEXP (SET_SRC (PATTERN (floater)), 1)))
6339 if (pa_can_combine_p (new, anchor, floater, 0,
6340 SET_DEST (PATTERN (floater)),
6341 SET_SRC (PATTERN (floater)),
6342 SET_SRC (PATTERN (floater))))
6348 /* If we didn't find anything on the backwards scan try forwards. */
6350 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6351 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6353 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6355 if (GET_CODE (floater) == NOTE
6356 || (GET_CODE (floater) == INSN
6357 && (GET_CODE (PATTERN (floater)) == USE
6358 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6362 /* Anything except a regular INSN will stop our search. */
6363 if (GET_CODE (floater) != INSN
6364 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6365 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6371 /* See if FLOATER is suitable for combination with the
6373 floater_attr = get_attr_pa_combine_type (floater);
6374 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6375 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6376 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6377 && floater_attr == PA_COMBINE_TYPE_FMPY))
6379 /* If ANCHOR and FLOATER can be combined, then we're
6380 done with this pass. */
6381 if (pa_can_combine_p (new, anchor, floater, 1,
6382 SET_DEST (PATTERN (floater)),
6383 XEXP (SET_SRC (PATTERN(floater)),0),
6384 XEXP(SET_SRC(PATTERN(floater)),1)))
6390 /* FLOATER will be nonzero if we found a suitable floating
6391 insn for combination with ANCHOR. */
6393 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6394 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6396 /* Emit the new instruction and delete the old anchor. */
6397 emit_insn_before (gen_rtx_PARALLEL (VOIDmode,
6400 PATTERN (floater))),
6402 PUT_CODE (anchor, NOTE);
6403 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6404 NOTE_SOURCE_FILE (anchor) = 0;
6406 /* Emit a special USE insn for FLOATER, then delete
6407 the floating insn. */
6408 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6409 delete_insn (floater);
6414 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6417 /* Emit the new_jump instruction and delete the old anchor. */
6418 temp = emit_jump_insn_before (gen_rtx_PARALLEL (VOIDmode,
6419 gen_rtvec (2, PATTERN (anchor),
6420 PATTERN (floater))),
6422 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6423 PUT_CODE (anchor, NOTE);
6424 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6425 NOTE_SOURCE_FILE (anchor) = 0;
6427 /* Emit a special USE insn for FLOATER, then delete
6428 the floating insn. */
6429 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6430 delete_insn (floater);
6438 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6439 rtx new, anchor, floater;
6441 rtx dest, src1, src2;
6443 int insn_code_number;
6446 /* Create a PARALLEL with the patterns of ANCHOR and
6447 FLOATER, try to recognize it, then test constraints
6448 for the resulting pattern.
6450 If the pattern doesn't match or the constraints
6451 aren't met keep searching for a suitable floater
6453 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6454 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6455 INSN_CODE (new) = -1;
6456 insn_code_number = recog_memoized (new);
6457 if (insn_code_number < 0
6458 || !constrain_operands (insn_code_number, 1))
6472 /* There's up to three operands to consider. One
6473 output and two inputs.
6475 The output must not be used between FLOATER & ANCHOR
6476 exclusive. The inputs must not be set between
6477 FLOATER and ANCHOR exclusive. */
6479 if (reg_used_between_p (dest, start, end))
6482 if (reg_set_between_p (src1, start, end))
6485 if (reg_set_between_p (src2, start, end))
6488 /* If we get here, then everything is good. */
6492 /* Return nonzero if sets and references for INSN are delayed.
6494 Millicode insns are actually function calls with some special
6495 constraints on arguments and register usage.
6497 Millicode calls always expect their arguments in the integer argument
6498 registers, and always return their result in %r29 (ret1). They
6499 are expected to clobber their arguments, %r1, %r29, and %r31 and
6502 By considering this effects delayed reorg reorg can put insns
6503 which set the argument registers into the delay slot of the millicode
6504 call -- thus they act more like traditional CALL_INSNs.
6506 get_attr_type will try to recognize the given insn, so make sure to
6507 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6510 insn_sets_and_refs_are_delayed (insn)
6513 return ((GET_CODE (insn) == INSN
6514 && GET_CODE (PATTERN (insn)) != SEQUENCE
6515 && GET_CODE (PATTERN (insn)) != USE
6516 && GET_CODE (PATTERN (insn)) != CLOBBER
6517 && get_attr_type (insn) == TYPE_MILLI));