1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
42 #include "diagnostic-core.h"
48 #include "common/common-target.h"
49 #include "target-def.h"
50 #include "langhooks.h"
54 /* Return nonzero if there is a bypass for the output of
55 OUT_INSN and the fp store IN_INSN. */
57 pa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
59 enum machine_mode store_mode;
60 enum machine_mode other_mode;
63 if (recog_memoized (in_insn) < 0
64 || (get_attr_type (in_insn) != TYPE_FPSTORE
65 && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD)
66 || recog_memoized (out_insn) < 0)
69 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
71 set = single_set (out_insn);
75 other_mode = GET_MODE (SET_SRC (set));
77 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
81 #ifndef DO_FRAME_NOTES
82 #ifdef INCOMING_RETURN_ADDR_RTX
83 #define DO_FRAME_NOTES 1
85 #define DO_FRAME_NOTES 0
89 static void pa_option_override (void);
90 static void copy_reg_pointer (rtx, rtx);
91 static void fix_range (const char *);
92 static int hppa_register_move_cost (enum machine_mode mode, reg_class_t,
94 static int hppa_address_cost (rtx, bool);
95 static bool hppa_rtx_costs (rtx, int, int, int, int *, bool);
96 static inline rtx force_mode (enum machine_mode, rtx);
97 static void pa_reorg (void);
98 static void pa_combine_instructions (void);
99 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
100 static bool forward_branch_p (rtx);
101 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
102 static void compute_zdepdi_operands (unsigned HOST_WIDE_INT, unsigned *);
103 static int compute_movmem_length (rtx);
104 static int compute_clrmem_length (rtx);
105 static bool pa_assemble_integer (rtx, unsigned int, int);
106 static void remove_useless_addtr_insns (int);
107 static void store_reg (int, HOST_WIDE_INT, int);
108 static void store_reg_modify (int, int, HOST_WIDE_INT);
109 static void load_reg (int, HOST_WIDE_INT, int);
110 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
111 static rtx pa_function_value (const_tree, const_tree, bool);
112 static rtx pa_libcall_value (enum machine_mode, const_rtx);
113 static bool pa_function_value_regno_p (const unsigned int);
114 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static void update_total_code_bytes (unsigned int);
116 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
117 static int pa_adjust_cost (rtx, rtx, rtx, int);
118 static int pa_adjust_priority (rtx, int);
119 static int pa_issue_rate (void);
120 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
121 static section *pa_som_tm_clone_table_section (void) ATTRIBUTE_UNUSED;
122 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
124 static void pa_encode_section_info (tree, rtx, int);
125 static const char *pa_strip_name_encoding (const char *);
126 static bool pa_function_ok_for_sibcall (tree, tree);
127 static void pa_globalize_label (FILE *, const char *)
129 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
130 HOST_WIDE_INT, tree);
131 #if !defined(USE_COLLECT2)
132 static void pa_asm_out_constructor (rtx, int);
133 static void pa_asm_out_destructor (rtx, int);
135 static void pa_init_builtins (void);
136 static rtx pa_expand_builtin (tree, rtx, rtx, enum machine_mode mode, int);
137 static rtx hppa_builtin_saveregs (void);
138 static void hppa_va_start (tree, rtx);
139 static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
140 static bool pa_scalar_mode_supported_p (enum machine_mode);
141 static bool pa_commutative_p (const_rtx x, int outer_code);
142 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
143 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
144 static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode);
145 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
146 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
147 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
148 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
149 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
150 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
151 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
152 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
153 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
154 static void output_deferred_plabels (void);
155 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
156 #ifdef ASM_OUTPUT_EXTERNAL_REAL
157 static void pa_hpux_file_end (void);
159 static void pa_init_libfuncs (void);
160 static rtx pa_struct_value_rtx (tree, int);
161 static bool pa_pass_by_reference (cumulative_args_t, enum machine_mode,
163 static int pa_arg_partial_bytes (cumulative_args_t, enum machine_mode,
165 static void pa_function_arg_advance (cumulative_args_t, enum machine_mode,
167 static rtx pa_function_arg (cumulative_args_t, enum machine_mode,
169 static unsigned int pa_function_arg_boundary (enum machine_mode, const_tree);
170 static struct machine_function * pa_init_machine_status (void);
171 static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t,
173 secondary_reload_info *);
174 static void pa_extra_live_on_entry (bitmap);
175 static enum machine_mode pa_promote_function_mode (const_tree,
176 enum machine_mode, int *,
179 static void pa_asm_trampoline_template (FILE *);
180 static void pa_trampoline_init (rtx, tree, rtx);
181 static rtx pa_trampoline_adjust_address (rtx);
182 static rtx pa_delegitimize_address (rtx);
183 static bool pa_print_operand_punct_valid_p (unsigned char);
184 static rtx pa_internal_arg_pointer (void);
185 static bool pa_can_eliminate (const int, const int);
186 static void pa_conditional_register_usage (void);
187 static enum machine_mode pa_c_mode_for_suffix (char);
188 static section *pa_function_section (tree, enum node_frequency, bool, bool);
189 static unsigned int pa_section_type_flags (tree, const char *, int);
191 /* The following extra sections are only used for SOM. */
192 static GTY(()) section *som_readonly_data_section;
193 static GTY(()) section *som_one_only_readonly_data_section;
194 static GTY(()) section *som_one_only_data_section;
195 static GTY(()) section *som_tm_clone_table_section;
197 /* Counts for the number of callee-saved general and floating point
198 registers which were saved by the current function's prologue. */
199 static int gr_saved, fr_saved;
201 /* Boolean indicating whether the return pointer was saved by the
202 current function's prologue. */
203 static bool rp_saved;
205 static rtx find_addr_reg (rtx);
207 /* Keep track of the number of bytes we have output in the CODE subspace
208 during this compilation so we'll know when to emit inline long-calls. */
209 unsigned long total_code_bytes;
211 /* The last address of the previous function plus the number of bytes in
212 associated thunks that have been output. This is used to determine if
213 a thunk can use an IA-relative branch to reach its target function. */
214 static unsigned int last_address;
216 /* Variables to handle plabels that we discover are necessary at assembly
217 output time. They are output after the current function. */
218 struct GTY(()) deferred_plabel
223 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
225 static size_t n_deferred_plabels = 0;
227 /* Initialize the GCC target structure. */
229 #undef TARGET_OPTION_OVERRIDE
230 #define TARGET_OPTION_OVERRIDE pa_option_override
232 #undef TARGET_ASM_ALIGNED_HI_OP
233 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
234 #undef TARGET_ASM_ALIGNED_SI_OP
235 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
236 #undef TARGET_ASM_ALIGNED_DI_OP
237 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
238 #undef TARGET_ASM_UNALIGNED_HI_OP
239 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
240 #undef TARGET_ASM_UNALIGNED_SI_OP
241 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
242 #undef TARGET_ASM_UNALIGNED_DI_OP
243 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
244 #undef TARGET_ASM_INTEGER
245 #define TARGET_ASM_INTEGER pa_assemble_integer
247 #undef TARGET_ASM_FUNCTION_PROLOGUE
248 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
249 #undef TARGET_ASM_FUNCTION_EPILOGUE
250 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
252 #undef TARGET_FUNCTION_VALUE
253 #define TARGET_FUNCTION_VALUE pa_function_value
254 #undef TARGET_LIBCALL_VALUE
255 #define TARGET_LIBCALL_VALUE pa_libcall_value
256 #undef TARGET_FUNCTION_VALUE_REGNO_P
257 #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p
259 #undef TARGET_LEGITIMIZE_ADDRESS
260 #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address
262 #undef TARGET_SCHED_ADJUST_COST
263 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
264 #undef TARGET_SCHED_ADJUST_PRIORITY
265 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
266 #undef TARGET_SCHED_ISSUE_RATE
267 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
269 #undef TARGET_ENCODE_SECTION_INFO
270 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
271 #undef TARGET_STRIP_NAME_ENCODING
272 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
274 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
275 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
277 #undef TARGET_COMMUTATIVE_P
278 #define TARGET_COMMUTATIVE_P pa_commutative_p
280 #undef TARGET_ASM_OUTPUT_MI_THUNK
281 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
282 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
283 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
285 #undef TARGET_ASM_FILE_END
286 #ifdef ASM_OUTPUT_EXTERNAL_REAL
287 #define TARGET_ASM_FILE_END pa_hpux_file_end
289 #define TARGET_ASM_FILE_END output_deferred_plabels
292 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
293 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p
295 #if !defined(USE_COLLECT2)
296 #undef TARGET_ASM_CONSTRUCTOR
297 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
298 #undef TARGET_ASM_DESTRUCTOR
299 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
302 #undef TARGET_INIT_BUILTINS
303 #define TARGET_INIT_BUILTINS pa_init_builtins
305 #undef TARGET_EXPAND_BUILTIN
306 #define TARGET_EXPAND_BUILTIN pa_expand_builtin
308 #undef TARGET_REGISTER_MOVE_COST
309 #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
310 #undef TARGET_RTX_COSTS
311 #define TARGET_RTX_COSTS hppa_rtx_costs
312 #undef TARGET_ADDRESS_COST
313 #define TARGET_ADDRESS_COST hppa_address_cost
315 #undef TARGET_MACHINE_DEPENDENT_REORG
316 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
318 #undef TARGET_INIT_LIBFUNCS
319 #define TARGET_INIT_LIBFUNCS pa_init_libfuncs
321 #undef TARGET_PROMOTE_FUNCTION_MODE
322 #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode
323 #undef TARGET_PROMOTE_PROTOTYPES
324 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
326 #undef TARGET_STRUCT_VALUE_RTX
327 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
328 #undef TARGET_RETURN_IN_MEMORY
329 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
330 #undef TARGET_MUST_PASS_IN_STACK
331 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
332 #undef TARGET_PASS_BY_REFERENCE
333 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
334 #undef TARGET_CALLEE_COPIES
335 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
336 #undef TARGET_ARG_PARTIAL_BYTES
337 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
338 #undef TARGET_FUNCTION_ARG
339 #define TARGET_FUNCTION_ARG pa_function_arg
340 #undef TARGET_FUNCTION_ARG_ADVANCE
341 #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance
342 #undef TARGET_FUNCTION_ARG_BOUNDARY
343 #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary
345 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
346 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
347 #undef TARGET_EXPAND_BUILTIN_VA_START
348 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
349 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
350 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
352 #undef TARGET_SCALAR_MODE_SUPPORTED_P
353 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
355 #undef TARGET_CANNOT_FORCE_CONST_MEM
356 #define TARGET_CANNOT_FORCE_CONST_MEM pa_cannot_force_const_mem
358 #undef TARGET_SECONDARY_RELOAD
359 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
361 #undef TARGET_EXTRA_LIVE_ON_ENTRY
362 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
364 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
365 #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template
366 #undef TARGET_TRAMPOLINE_INIT
367 #define TARGET_TRAMPOLINE_INIT pa_trampoline_init
368 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
369 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address
370 #undef TARGET_DELEGITIMIZE_ADDRESS
371 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
372 #undef TARGET_INTERNAL_ARG_POINTER
373 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
374 #undef TARGET_CAN_ELIMINATE
375 #define TARGET_CAN_ELIMINATE pa_can_eliminate
376 #undef TARGET_CONDITIONAL_REGISTER_USAGE
377 #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage
378 #undef TARGET_C_MODE_FOR_SUFFIX
379 #define TARGET_C_MODE_FOR_SUFFIX pa_c_mode_for_suffix
380 #undef TARGET_ASM_FUNCTION_SECTION
381 #define TARGET_ASM_FUNCTION_SECTION pa_function_section
383 #undef TARGET_SECTION_TYPE_FLAGS
384 #define TARGET_SECTION_TYPE_FLAGS pa_section_type_flags
386 struct gcc_target targetm = TARGET_INITIALIZER;
388 /* Parse the -mfixed-range= option string. */
391 fix_range (const char *const_str)
394 char *str, *dash, *comma;
396 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
397 REG2 are either register names or register numbers. The effect
398 of this option is to mark the registers in the range from REG1 to
399 REG2 as ``fixed'' so they won't be used by the compiler. This is
400 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
402 i = strlen (const_str);
403 str = (char *) alloca (i + 1);
404 memcpy (str, const_str, i + 1);
408 dash = strchr (str, '-');
411 warning (0, "value of -mfixed-range must have form REG1-REG2");
416 comma = strchr (dash + 1, ',');
420 first = decode_reg_name (str);
423 warning (0, "unknown register name: %s", str);
427 last = decode_reg_name (dash + 1);
430 warning (0, "unknown register name: %s", dash + 1);
438 warning (0, "%s-%s is an empty range", str, dash + 1);
442 for (i = first; i <= last; ++i)
443 fixed_regs[i] = call_used_regs[i] = 1;
452 /* Check if all floating point registers have been fixed. */
453 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
458 target_flags |= MASK_DISABLE_FPREGS;
461 /* Implement the TARGET_OPTION_OVERRIDE hook. */
464 pa_option_override (void)
467 cl_deferred_option *opt;
468 VEC(cl_deferred_option,heap) *vec
469 = (VEC(cl_deferred_option,heap) *) pa_deferred_options;
471 FOR_EACH_VEC_ELT (cl_deferred_option, vec, i, opt)
473 switch (opt->opt_index)
475 case OPT_mfixed_range_:
476 fix_range (opt->arg);
484 /* Unconditional branches in the delay slot are not compatible with dwarf2
485 call frame information. There is no benefit in using this optimization
486 on PA8000 and later processors. */
487 if (pa_cpu >= PROCESSOR_8000
488 || (targetm_common.except_unwind_info (&global_options) == UI_DWARF2
490 || flag_unwind_tables)
491 target_flags &= ~MASK_JUMP_IN_DELAY;
493 if (flag_pic && TARGET_PORTABLE_RUNTIME)
495 warning (0, "PIC code generation is not supported in the portable runtime model");
498 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
500 warning (0, "PIC code generation is not compatible with fast indirect calls");
503 if (! TARGET_GAS && write_symbols != NO_DEBUG)
505 warning (0, "-g is only supported when using GAS on this processor,");
506 warning (0, "-g option disabled");
507 write_symbols = NO_DEBUG;
510 /* We only support the "big PIC" model now. And we always generate PIC
511 code when in 64bit mode. */
512 if (flag_pic == 1 || TARGET_64BIT)
515 /* Disable -freorder-blocks-and-partition as we don't support hot and
516 cold partitioning. */
517 if (flag_reorder_blocks_and_partition)
519 inform (input_location,
520 "-freorder-blocks-and-partition does not work "
521 "on this architecture");
522 flag_reorder_blocks_and_partition = 0;
523 flag_reorder_blocks = 1;
526 /* We can't guarantee that .dword is available for 32-bit targets. */
527 if (UNITS_PER_WORD == 4)
528 targetm.asm_out.aligned_op.di = NULL;
530 /* The unaligned ops are only available when using GAS. */
533 targetm.asm_out.unaligned_op.hi = NULL;
534 targetm.asm_out.unaligned_op.si = NULL;
535 targetm.asm_out.unaligned_op.di = NULL;
538 init_machine_status = pa_init_machine_status;
543 PA_BUILTIN_COPYSIGNQ,
546 PA_BUILTIN_HUGE_VALQ,
550 static GTY(()) tree pa_builtins[(int) PA_BUILTIN_max];
553 pa_init_builtins (void)
555 #ifdef DONT_HAVE_FPUTC_UNLOCKED
557 tree decl = builtin_decl_explicit (BUILT_IN_PUTC_UNLOCKED);
558 set_builtin_decl (BUILT_IN_FPUTC_UNLOCKED, decl,
559 builtin_decl_implicit_p (BUILT_IN_PUTC_UNLOCKED));
566 if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE)
567 set_user_assembler_name (decl, "_Isfinite");
568 if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE)
569 set_user_assembler_name (decl, "_Isfinitef");
573 if (HPUX_LONG_DOUBLE_LIBRARY)
577 /* Under HPUX, the __float128 type is a synonym for "long double". */
578 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
581 /* TFmode support builtins. */
582 ftype = build_function_type_list (long_double_type_node,
583 long_double_type_node,
585 decl = add_builtin_function ("__builtin_fabsq", ftype,
586 PA_BUILTIN_FABSQ, BUILT_IN_MD,
587 "_U_Qfabs", NULL_TREE);
588 TREE_READONLY (decl) = 1;
589 pa_builtins[PA_BUILTIN_FABSQ] = decl;
591 ftype = build_function_type_list (long_double_type_node,
592 long_double_type_node,
593 long_double_type_node,
595 decl = add_builtin_function ("__builtin_copysignq", ftype,
596 PA_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
597 "_U_Qfcopysign", NULL_TREE);
598 TREE_READONLY (decl) = 1;
599 pa_builtins[PA_BUILTIN_COPYSIGNQ] = decl;
601 ftype = build_function_type_list (long_double_type_node, NULL_TREE);
602 decl = add_builtin_function ("__builtin_infq", ftype,
603 PA_BUILTIN_INFQ, BUILT_IN_MD,
605 pa_builtins[PA_BUILTIN_INFQ] = decl;
607 decl = add_builtin_function ("__builtin_huge_valq", ftype,
608 PA_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
610 pa_builtins[PA_BUILTIN_HUGE_VALQ] = decl;
615 pa_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
616 enum machine_mode mode ATTRIBUTE_UNUSED,
617 int ignore ATTRIBUTE_UNUSED)
619 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
620 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
624 case PA_BUILTIN_FABSQ:
625 case PA_BUILTIN_COPYSIGNQ:
626 return expand_call (exp, target, ignore);
628 case PA_BUILTIN_INFQ:
629 case PA_BUILTIN_HUGE_VALQ:
631 enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp));
636 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode);
638 tmp = validize_mem (force_const_mem (target_mode, tmp));
641 target = gen_reg_rtx (target_mode);
643 emit_move_insn (target, tmp);
654 /* Function to init struct machine_function.
655 This will be called, via a pointer variable,
656 from push_function_context. */
658 static struct machine_function *
659 pa_init_machine_status (void)
661 return ggc_alloc_cleared_machine_function ();
664 /* If FROM is a probable pointer register, mark TO as a probable
665 pointer register with the same pointer alignment as FROM. */
668 copy_reg_pointer (rtx to, rtx from)
670 if (REG_POINTER (from))
671 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
674 /* Return 1 if X contains a symbolic expression. We know these
675 expressions will have one of a few well defined forms, so
676 we need only check those forms. */
678 pa_symbolic_expression_p (rtx x)
681 /* Strip off any HIGH. */
682 if (GET_CODE (x) == HIGH)
685 return (symbolic_operand (x, VOIDmode));
688 /* Accept any constant that can be moved in one instruction into a
691 pa_cint_ok_for_move (HOST_WIDE_INT ival)
693 /* OK if ldo, ldil, or zdepi, can be used. */
694 return (VAL_14_BITS_P (ival)
695 || pa_ldil_cint_p (ival)
696 || pa_zdepi_cint_p (ival));
699 /* True iff ldil can be used to load this CONST_INT. The least
700 significant 11 bits of the value must be zero and the value must
701 not change sign when extended from 32 to 64 bits. */
703 pa_ldil_cint_p (HOST_WIDE_INT ival)
705 HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff);
707 return x == 0 || x == ((HOST_WIDE_INT) -1 << 31);
710 /* True iff zdepi can be used to generate this CONST_INT.
711 zdepi first sign extends a 5-bit signed number to a given field
712 length, then places this field anywhere in a zero. */
714 pa_zdepi_cint_p (unsigned HOST_WIDE_INT x)
716 unsigned HOST_WIDE_INT lsb_mask, t;
718 /* This might not be obvious, but it's at least fast.
719 This function is critical; we don't have the time loops would take. */
721 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
722 /* Return true iff t is a power of two. */
723 return ((t & (t - 1)) == 0);
726 /* True iff depi or extru can be used to compute (reg & mask).
727 Accept bit pattern like these:
732 pa_and_mask_p (unsigned HOST_WIDE_INT mask)
735 mask += mask & -mask;
736 return (mask & (mask - 1)) == 0;
739 /* True iff depi can be used to compute (reg | MASK). */
741 pa_ior_mask_p (unsigned HOST_WIDE_INT mask)
743 mask += mask & -mask;
744 return (mask & (mask - 1)) == 0;
747 /* Legitimize PIC addresses. If the address is already
748 position-independent, we return ORIG. Newly generated
749 position-independent addresses go to REG. If we need more
750 than one register, we lose. */
753 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
757 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
759 /* Labels need special handling. */
760 if (pic_label_operand (orig, mode))
764 /* We do not want to go through the movXX expanders here since that
765 would create recursion.
767 Nor do we really want to call a generator for a named pattern
768 since that requires multiple patterns if we want to support
771 So instead we just emit the raw set, which avoids the movXX
772 expanders completely. */
773 mark_reg_pointer (reg, BITS_PER_UNIT);
774 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
776 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
777 add_reg_note (insn, REG_EQUAL, orig);
779 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
780 and update LABEL_NUSES because this is not done automatically. */
781 if (reload_in_progress || reload_completed)
783 /* Extract LABEL_REF. */
784 if (GET_CODE (orig) == CONST)
785 orig = XEXP (XEXP (orig, 0), 0);
786 /* Extract CODE_LABEL. */
787 orig = XEXP (orig, 0);
788 add_reg_note (insn, REG_LABEL_OPERAND, orig);
789 LABEL_NUSES (orig)++;
791 crtl->uses_pic_offset_table = 1;
794 if (GET_CODE (orig) == SYMBOL_REF)
800 /* Before reload, allocate a temporary register for the intermediate
801 result. This allows the sequence to be deleted when the final
802 result is unused and the insns are trivially dead. */
803 tmp_reg = ((reload_in_progress || reload_completed)
804 ? reg : gen_reg_rtx (Pmode));
806 if (function_label_operand (orig, VOIDmode))
808 /* Force function label into memory in word mode. */
809 orig = XEXP (force_const_mem (word_mode, orig), 0);
810 /* Load plabel address from DLT. */
811 emit_move_insn (tmp_reg,
812 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
813 gen_rtx_HIGH (word_mode, orig)));
815 = gen_const_mem (Pmode,
816 gen_rtx_LO_SUM (Pmode, tmp_reg,
817 gen_rtx_UNSPEC (Pmode,
820 emit_move_insn (reg, pic_ref);
821 /* Now load address of function descriptor. */
822 pic_ref = gen_rtx_MEM (Pmode, reg);
826 /* Load symbol reference from DLT. */
827 emit_move_insn (tmp_reg,
828 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
829 gen_rtx_HIGH (word_mode, orig)));
831 = gen_const_mem (Pmode,
832 gen_rtx_LO_SUM (Pmode, tmp_reg,
833 gen_rtx_UNSPEC (Pmode,
838 crtl->uses_pic_offset_table = 1;
839 mark_reg_pointer (reg, BITS_PER_UNIT);
840 insn = emit_move_insn (reg, pic_ref);
842 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
843 set_unique_reg_note (insn, REG_EQUAL, orig);
847 else if (GET_CODE (orig) == CONST)
851 if (GET_CODE (XEXP (orig, 0)) == PLUS
852 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
856 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
858 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
859 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
860 base == reg ? 0 : reg);
862 if (GET_CODE (orig) == CONST_INT)
864 if (INT_14_BITS (orig))
865 return plus_constant (base, INTVAL (orig));
866 orig = force_reg (Pmode, orig);
868 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
869 /* Likewise, should we set special REG_NOTEs here? */
875 static GTY(()) rtx gen_tls_tga;
878 gen_tls_get_addr (void)
881 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
886 hppa_tls_call (rtx arg)
890 ret = gen_reg_rtx (Pmode);
891 emit_library_call_value (gen_tls_get_addr (), ret,
892 LCT_CONST, Pmode, 1, arg, Pmode);
898 legitimize_tls_address (rtx addr)
900 rtx ret, insn, tmp, t1, t2, tp;
901 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
905 case TLS_MODEL_GLOBAL_DYNAMIC:
906 tmp = gen_reg_rtx (Pmode);
908 emit_insn (gen_tgd_load_pic (tmp, addr));
910 emit_insn (gen_tgd_load (tmp, addr));
911 ret = hppa_tls_call (tmp);
914 case TLS_MODEL_LOCAL_DYNAMIC:
915 ret = gen_reg_rtx (Pmode);
916 tmp = gen_reg_rtx (Pmode);
919 emit_insn (gen_tld_load_pic (tmp, addr));
921 emit_insn (gen_tld_load (tmp, addr));
922 t1 = hppa_tls_call (tmp);
925 t2 = gen_reg_rtx (Pmode);
926 emit_libcall_block (insn, t2, t1,
927 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
929 emit_insn (gen_tld_offset_load (ret, addr, t2));
932 case TLS_MODEL_INITIAL_EXEC:
933 tp = gen_reg_rtx (Pmode);
934 tmp = gen_reg_rtx (Pmode);
935 ret = gen_reg_rtx (Pmode);
936 emit_insn (gen_tp_load (tp));
938 emit_insn (gen_tie_load_pic (tmp, addr));
940 emit_insn (gen_tie_load (tmp, addr));
941 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
944 case TLS_MODEL_LOCAL_EXEC:
945 tp = gen_reg_rtx (Pmode);
946 ret = gen_reg_rtx (Pmode);
947 emit_insn (gen_tp_load (tp));
948 emit_insn (gen_tle_load (ret, addr, tp));
958 /* Try machine-dependent ways of modifying an illegitimate address
959 to be legitimate. If we find one, return the new, valid address.
960 This macro is used in only one place: `memory_address' in explow.c.
962 OLDX is the address as it was before break_out_memory_refs was called.
963 In some cases it is useful to look at this to decide what needs to be done.
965 It is always safe for this macro to do nothing. It exists to recognize
966 opportunities to optimize the output.
968 For the PA, transform:
970 memory(X + <large int>)
974 if (<large int> & mask) >= 16
975 Y = (<large int> & ~mask) + mask + 1 Round up.
977 Y = (<large int> & ~mask) Round down.
979 memory (Z + (<large int> - Y));
981 This is for CSE to find several similar references, and only use one Z.
983 X can either be a SYMBOL_REF or REG, but because combine cannot
984 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
985 D will not fit in 14 bits.
987 MODE_FLOAT references allow displacements which fit in 5 bits, so use
990 MODE_INT references allow displacements which fit in 14 bits, so use
993 This relies on the fact that most mode MODE_FLOAT references will use FP
994 registers and most mode MODE_INT references will use integer registers.
995 (In the rare case of an FP register used in an integer MODE, we depend
996 on secondary reloads to clean things up.)
999 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1000 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1001 addressing modes to be used).
1003 Put X and Z into registers. Then put the entire expression into
1007 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1008 enum machine_mode mode)
1012 /* We need to canonicalize the order of operands in unscaled indexed
1013 addresses since the code that checks if an address is valid doesn't
1014 always try both orders. */
1015 if (!TARGET_NO_SPACE_REGS
1016 && GET_CODE (x) == PLUS
1017 && GET_MODE (x) == Pmode
1018 && REG_P (XEXP (x, 0))
1019 && REG_P (XEXP (x, 1))
1020 && REG_POINTER (XEXP (x, 0))
1021 && !REG_POINTER (XEXP (x, 1)))
1022 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1024 if (PA_SYMBOL_REF_TLS_P (x))
1025 return legitimize_tls_address (x);
1027 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1029 /* Strip off CONST. */
1030 if (GET_CODE (x) == CONST)
1033 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1034 That should always be safe. */
1035 if (GET_CODE (x) == PLUS
1036 && GET_CODE (XEXP (x, 0)) == REG
1037 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1039 rtx reg = force_reg (Pmode, XEXP (x, 1));
1040 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1043 /* Note we must reject symbols which represent function addresses
1044 since the assembler/linker can't handle arithmetic on plabels. */
1045 if (GET_CODE (x) == PLUS
1046 && GET_CODE (XEXP (x, 1)) == CONST_INT
1047 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1048 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1049 || GET_CODE (XEXP (x, 0)) == REG))
1051 rtx int_part, ptr_reg;
1053 int offset = INTVAL (XEXP (x, 1));
1056 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1057 ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff);
1059 /* Choose which way to round the offset. Round up if we
1060 are >= halfway to the next boundary. */
1061 if ((offset & mask) >= ((mask + 1) / 2))
1062 newoffset = (offset & ~ mask) + mask + 1;
1064 newoffset = (offset & ~ mask);
1066 /* If the newoffset will not fit in 14 bits (ldo), then
1067 handling this would take 4 or 5 instructions (2 to load
1068 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1069 add the new offset and the SYMBOL_REF.) Combine can
1070 not handle 4->2 or 5->2 combinations, so do not create
1072 if (! VAL_14_BITS_P (newoffset)
1073 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1075 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1078 gen_rtx_HIGH (Pmode, const_part));
1081 gen_rtx_LO_SUM (Pmode,
1082 tmp_reg, const_part));
1086 if (! VAL_14_BITS_P (newoffset))
1087 int_part = force_reg (Pmode, GEN_INT (newoffset));
1089 int_part = GEN_INT (newoffset);
1091 ptr_reg = force_reg (Pmode,
1092 gen_rtx_PLUS (Pmode,
1093 force_reg (Pmode, XEXP (x, 0)),
1096 return plus_constant (ptr_reg, offset - newoffset);
1099 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1101 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1102 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1103 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1104 && (OBJECT_P (XEXP (x, 1))
1105 || GET_CODE (XEXP (x, 1)) == SUBREG)
1106 && GET_CODE (XEXP (x, 1)) != CONST)
1108 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1112 if (GET_CODE (reg1) != REG)
1113 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1115 reg2 = XEXP (XEXP (x, 0), 0);
1116 if (GET_CODE (reg2) != REG)
1117 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1119 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1120 gen_rtx_MULT (Pmode,
1126 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1128 Only do so for floating point modes since this is more speculative
1129 and we lose if it's an integer store. */
1130 if (GET_CODE (x) == PLUS
1131 && GET_CODE (XEXP (x, 0)) == PLUS
1132 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1133 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1134 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1135 && (mode == SFmode || mode == DFmode))
1138 /* First, try and figure out what to use as a base register. */
1139 rtx reg1, reg2, base, idx;
1141 reg1 = XEXP (XEXP (x, 0), 1);
1146 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1147 then pa_emit_move_sequence will turn on REG_POINTER so we'll know
1148 it's a base register below. */
1149 if (GET_CODE (reg1) != REG)
1150 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1152 if (GET_CODE (reg2) != REG)
1153 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1155 /* Figure out what the base and index are. */
1157 if (GET_CODE (reg1) == REG
1158 && REG_POINTER (reg1))
1161 idx = gen_rtx_PLUS (Pmode,
1162 gen_rtx_MULT (Pmode,
1163 XEXP (XEXP (XEXP (x, 0), 0), 0),
1164 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1167 else if (GET_CODE (reg2) == REG
1168 && REG_POINTER (reg2))
1177 /* If the index adds a large constant, try to scale the
1178 constant so that it can be loaded with only one insn. */
1179 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1180 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1181 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1182 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1184 /* Divide the CONST_INT by the scale factor, then add it to A. */
1185 int val = INTVAL (XEXP (idx, 1));
1187 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1188 reg1 = XEXP (XEXP (idx, 0), 0);
1189 if (GET_CODE (reg1) != REG)
1190 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1192 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1194 /* We can now generate a simple scaled indexed address. */
1197 (Pmode, gen_rtx_PLUS (Pmode,
1198 gen_rtx_MULT (Pmode, reg1,
1199 XEXP (XEXP (idx, 0), 1)),
1203 /* If B + C is still a valid base register, then add them. */
1204 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1205 && INTVAL (XEXP (idx, 1)) <= 4096
1206 && INTVAL (XEXP (idx, 1)) >= -4096)
1208 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1211 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1213 reg2 = XEXP (XEXP (idx, 0), 0);
1214 if (GET_CODE (reg2) != CONST_INT)
1215 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1217 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1218 gen_rtx_MULT (Pmode,
1224 /* Get the index into a register, then add the base + index and
1225 return a register holding the result. */
1227 /* First get A into a register. */
1228 reg1 = XEXP (XEXP (idx, 0), 0);
1229 if (GET_CODE (reg1) != REG)
1230 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1232 /* And get B into a register. */
1233 reg2 = XEXP (idx, 1);
1234 if (GET_CODE (reg2) != REG)
1235 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1237 reg1 = force_reg (Pmode,
1238 gen_rtx_PLUS (Pmode,
1239 gen_rtx_MULT (Pmode, reg1,
1240 XEXP (XEXP (idx, 0), 1)),
1243 /* Add the result to our base register and return. */
1244 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1248 /* Uh-oh. We might have an address for x[n-100000]. This needs
1249 special handling to avoid creating an indexed memory address
1250 with x-100000 as the base.
1252 If the constant part is small enough, then it's still safe because
1253 there is a guard page at the beginning and end of the data segment.
1255 Scaled references are common enough that we want to try and rearrange the
1256 terms so that we can use indexing for these addresses too. Only
1257 do the optimization for floatint point modes. */
1259 if (GET_CODE (x) == PLUS
1260 && pa_symbolic_expression_p (XEXP (x, 1)))
1262 /* Ugly. We modify things here so that the address offset specified
1263 by the index expression is computed first, then added to x to form
1264 the entire address. */
1266 rtx regx1, regx2, regy1, regy2, y;
1268 /* Strip off any CONST. */
1270 if (GET_CODE (y) == CONST)
1273 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1275 /* See if this looks like
1276 (plus (mult (reg) (shadd_const))
1277 (const (plus (symbol_ref) (const_int))))
1279 Where const_int is small. In that case the const
1280 expression is a valid pointer for indexing.
1282 If const_int is big, but can be divided evenly by shadd_const
1283 and added to (reg). This allows more scaled indexed addresses. */
1284 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1285 && GET_CODE (XEXP (x, 0)) == MULT
1286 && GET_CODE (XEXP (y, 1)) == CONST_INT
1287 && INTVAL (XEXP (y, 1)) >= -4096
1288 && INTVAL (XEXP (y, 1)) <= 4095
1289 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1290 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1292 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1296 if (GET_CODE (reg1) != REG)
1297 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1299 reg2 = XEXP (XEXP (x, 0), 0);
1300 if (GET_CODE (reg2) != REG)
1301 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1303 return force_reg (Pmode,
1304 gen_rtx_PLUS (Pmode,
1305 gen_rtx_MULT (Pmode,
1310 else if ((mode == DFmode || mode == SFmode)
1311 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1312 && GET_CODE (XEXP (x, 0)) == MULT
1313 && GET_CODE (XEXP (y, 1)) == CONST_INT
1314 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1315 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1316 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1319 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1320 / INTVAL (XEXP (XEXP (x, 0), 1))));
1321 regx2 = XEXP (XEXP (x, 0), 0);
1322 if (GET_CODE (regx2) != REG)
1323 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1324 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1328 gen_rtx_PLUS (Pmode,
1329 gen_rtx_MULT (Pmode, regx2,
1330 XEXP (XEXP (x, 0), 1)),
1331 force_reg (Pmode, XEXP (y, 0))));
1333 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1334 && INTVAL (XEXP (y, 1)) >= -4096
1335 && INTVAL (XEXP (y, 1)) <= 4095)
1337 /* This is safe because of the guard page at the
1338 beginning and end of the data space. Just
1339 return the original address. */
1344 /* Doesn't look like one we can optimize. */
1345 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1346 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1347 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1348 regx1 = force_reg (Pmode,
1349 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1351 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1359 /* Implement the TARGET_REGISTER_MOVE_COST hook.
1361 Compute extra cost of moving data between one register class
1364 Make moves from SAR so expensive they should never happen. We used to
1365 have 0xffff here, but that generates overflow in rare cases.
1367 Copies involving a FP register and a non-FP register are relatively
1368 expensive because they must go through memory.
1370 Other copies are reasonably cheap. */
1373 hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1374 reg_class_t from, reg_class_t to)
1376 if (from == SHIFT_REGS)
1378 else if (to == SHIFT_REGS && FP_REG_CLASS_P (from))
1380 else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to))
1381 || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from)))
1387 /* For the HPPA, REG and REG+CONST is cost 0
1388 and addresses involving symbolic constants are cost 2.
1390 PIC addresses are very expensive.
1392 It is no coincidence that this has the same structure
1393 as GO_IF_LEGITIMATE_ADDRESS. */
1396 hppa_address_cost (rtx X,
1397 bool speed ATTRIBUTE_UNUSED)
1399 switch (GET_CODE (X))
1412 /* Compute a (partial) cost for rtx X. Return true if the complete
1413 cost has been computed, and false if subexpressions should be
1414 scanned. In either case, *TOTAL contains the cost result. */
1417 hppa_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1418 int *total, bool speed ATTRIBUTE_UNUSED)
1423 if (INTVAL (x) == 0)
1425 else if (INT_14_BITS (x))
1442 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1443 && outer_code != SET)
1450 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1451 *total = COSTS_N_INSNS (3);
1452 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1453 *total = COSTS_N_INSNS (8);
1455 *total = COSTS_N_INSNS (20);
1459 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1461 *total = COSTS_N_INSNS (14);
1469 *total = COSTS_N_INSNS (60);
1472 case PLUS: /* this includes shNadd insns */
1474 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1475 *total = COSTS_N_INSNS (3);
1477 *total = COSTS_N_INSNS (1);
1483 *total = COSTS_N_INSNS (1);
1491 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1492 new rtx with the correct mode. */
1494 force_mode (enum machine_mode mode, rtx orig)
1496 if (mode == GET_MODE (orig))
1499 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1501 return gen_rtx_REG (mode, REGNO (orig));
1504 /* Return 1 if *X is a thread-local symbol. */
1507 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1509 return PA_SYMBOL_REF_TLS_P (*x);
1512 /* Return 1 if X contains a thread-local symbol. */
1515 pa_tls_referenced_p (rtx x)
1517 if (!TARGET_HAVE_TLS)
1520 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1523 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1526 pa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1528 return pa_tls_referenced_p (x);
1531 /* Emit insns to move operands[1] into operands[0].
1533 Return 1 if we have written out everything that needs to be done to
1534 do the move. Otherwise, return 0 and the caller will emit the move
1537 Note SCRATCH_REG may not be in the proper mode depending on how it
1538 will be used. This routine is responsible for creating a new copy
1539 of SCRATCH_REG in the proper mode. */
1542 pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1544 register rtx operand0 = operands[0];
1545 register rtx operand1 = operands[1];
1548 /* We can only handle indexed addresses in the destination operand
1549 of floating point stores. Thus, we need to break out indexed
1550 addresses from the destination operand. */
1551 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1553 gcc_assert (can_create_pseudo_p ());
1555 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1556 operand0 = replace_equiv_address (operand0, tem);
1559 /* On targets with non-equivalent space registers, break out unscaled
1560 indexed addresses from the source operand before the final CSE.
1561 We have to do this because the REG_POINTER flag is not correctly
1562 carried through various optimization passes and CSE may substitute
1563 a pseudo without the pointer set for one with the pointer set. As
1564 a result, we loose various opportunities to create insns with
1565 unscaled indexed addresses. */
1566 if (!TARGET_NO_SPACE_REGS
1567 && !cse_not_expected
1568 && GET_CODE (operand1) == MEM
1569 && GET_CODE (XEXP (operand1, 0)) == PLUS
1570 && REG_P (XEXP (XEXP (operand1, 0), 0))
1571 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1573 = replace_equiv_address (operand1,
1574 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1577 && reload_in_progress && GET_CODE (operand0) == REG
1578 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1579 operand0 = reg_equiv_mem (REGNO (operand0));
1580 else if (scratch_reg
1581 && reload_in_progress && GET_CODE (operand0) == SUBREG
1582 && GET_CODE (SUBREG_REG (operand0)) == REG
1583 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1585 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1586 the code which tracks sets/uses for delete_output_reload. */
1587 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1588 reg_equiv_mem (REGNO (SUBREG_REG (operand0))),
1589 SUBREG_BYTE (operand0));
1590 operand0 = alter_subreg (&temp);
1594 && reload_in_progress && GET_CODE (operand1) == REG
1595 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1596 operand1 = reg_equiv_mem (REGNO (operand1));
1597 else if (scratch_reg
1598 && reload_in_progress && GET_CODE (operand1) == SUBREG
1599 && GET_CODE (SUBREG_REG (operand1)) == REG
1600 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1602 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1603 the code which tracks sets/uses for delete_output_reload. */
1604 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1605 reg_equiv_mem (REGNO (SUBREG_REG (operand1))),
1606 SUBREG_BYTE (operand1));
1607 operand1 = alter_subreg (&temp);
1610 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1611 && ((tem = find_replacement (&XEXP (operand0, 0)))
1612 != XEXP (operand0, 0)))
1613 operand0 = replace_equiv_address (operand0, tem);
1615 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1616 && ((tem = find_replacement (&XEXP (operand1, 0)))
1617 != XEXP (operand1, 0)))
1618 operand1 = replace_equiv_address (operand1, tem);
1620 /* Handle secondary reloads for loads/stores of FP registers from
1621 REG+D addresses where D does not fit in 5 or 14 bits, including
1622 (subreg (mem (addr))) cases. */
1624 && fp_reg_operand (operand0, mode)
1625 && ((GET_CODE (operand1) == MEM
1626 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1627 XEXP (operand1, 0)))
1628 || ((GET_CODE (operand1) == SUBREG
1629 && GET_CODE (XEXP (operand1, 0)) == MEM
1630 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1632 XEXP (XEXP (operand1, 0), 0))))))
1634 if (GET_CODE (operand1) == SUBREG)
1635 operand1 = XEXP (operand1, 0);
1637 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1638 it in WORD_MODE regardless of what mode it was originally given
1640 scratch_reg = force_mode (word_mode, scratch_reg);
1642 /* D might not fit in 14 bits either; for such cases load D into
1644 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1646 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1647 emit_move_insn (scratch_reg,
1648 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1650 XEXP (XEXP (operand1, 0), 0),
1654 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1655 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1656 replace_equiv_address (operand1, scratch_reg)));
1659 else if (scratch_reg
1660 && fp_reg_operand (operand1, mode)
1661 && ((GET_CODE (operand0) == MEM
1662 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1664 XEXP (operand0, 0)))
1665 || ((GET_CODE (operand0) == SUBREG)
1666 && GET_CODE (XEXP (operand0, 0)) == MEM
1667 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1669 XEXP (XEXP (operand0, 0), 0)))))
1671 if (GET_CODE (operand0) == SUBREG)
1672 operand0 = XEXP (operand0, 0);
1674 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1675 it in WORD_MODE regardless of what mode it was originally given
1677 scratch_reg = force_mode (word_mode, scratch_reg);
1679 /* D might not fit in 14 bits either; for such cases load D into
1681 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1683 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1684 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1687 XEXP (XEXP (operand0, 0),
1692 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1693 emit_insn (gen_rtx_SET (VOIDmode,
1694 replace_equiv_address (operand0, scratch_reg),
1698 /* Handle secondary reloads for loads of FP registers from constant
1699 expressions by forcing the constant into memory.
1701 Use scratch_reg to hold the address of the memory location.
1703 The proper fix is to change TARGET_PREFERRED_RELOAD_CLASS to return
1704 NO_REGS when presented with a const_int and a register class
1705 containing only FP registers. Doing so unfortunately creates
1706 more problems than it solves. Fix this for 2.5. */
1707 else if (scratch_reg
1708 && CONSTANT_P (operand1)
1709 && fp_reg_operand (operand0, mode))
1711 rtx const_mem, xoperands[2];
1713 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1714 it in WORD_MODE regardless of what mode it was originally given
1716 scratch_reg = force_mode (word_mode, scratch_reg);
1718 /* Force the constant into memory and put the address of the
1719 memory location into scratch_reg. */
1720 const_mem = force_const_mem (mode, operand1);
1721 xoperands[0] = scratch_reg;
1722 xoperands[1] = XEXP (const_mem, 0);
1723 pa_emit_move_sequence (xoperands, Pmode, 0);
1725 /* Now load the destination register. */
1726 emit_insn (gen_rtx_SET (mode, operand0,
1727 replace_equiv_address (const_mem, scratch_reg)));
1730 /* Handle secondary reloads for SAR. These occur when trying to load
1731 the SAR from memory or a constant. */
1732 else if (scratch_reg
1733 && GET_CODE (operand0) == REG
1734 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1735 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1736 && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT))
1738 /* D might not fit in 14 bits either; for such cases load D into
1740 if (GET_CODE (operand1) == MEM
1741 && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0)))
1743 /* We are reloading the address into the scratch register, so we
1744 want to make sure the scratch register is a full register. */
1745 scratch_reg = force_mode (word_mode, scratch_reg);
1747 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1748 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1751 XEXP (XEXP (operand1, 0),
1755 /* Now we are going to load the scratch register from memory,
1756 we want to load it in the same width as the original MEM,
1757 which must be the same as the width of the ultimate destination,
1759 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1761 emit_move_insn (scratch_reg,
1762 replace_equiv_address (operand1, scratch_reg));
1766 /* We want to load the scratch register using the same mode as
1767 the ultimate destination. */
1768 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1770 emit_move_insn (scratch_reg, operand1);
1773 /* And emit the insn to set the ultimate destination. We know that
1774 the scratch register has the same mode as the destination at this
1776 emit_move_insn (operand0, scratch_reg);
1779 /* Handle the most common case: storing into a register. */
1780 else if (register_operand (operand0, mode))
1782 /* Legitimize TLS symbol references. This happens for references
1783 that aren't a legitimate constant. */
1784 if (PA_SYMBOL_REF_TLS_P (operand1))
1785 operand1 = legitimize_tls_address (operand1);
1787 if (register_operand (operand1, mode)
1788 || (GET_CODE (operand1) == CONST_INT
1789 && pa_cint_ok_for_move (INTVAL (operand1)))
1790 || (operand1 == CONST0_RTX (mode))
1791 || (GET_CODE (operand1) == HIGH
1792 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1793 /* Only `general_operands' can come here, so MEM is ok. */
1794 || GET_CODE (operand1) == MEM)
1796 /* Various sets are created during RTL generation which don't
1797 have the REG_POINTER flag correctly set. After the CSE pass,
1798 instruction recognition can fail if we don't consistently
1799 set this flag when performing register copies. This should
1800 also improve the opportunities for creating insns that use
1801 unscaled indexing. */
1802 if (REG_P (operand0) && REG_P (operand1))
1804 if (REG_POINTER (operand1)
1805 && !REG_POINTER (operand0)
1806 && !HARD_REGISTER_P (operand0))
1807 copy_reg_pointer (operand0, operand1);
1810 /* When MEMs are broken out, the REG_POINTER flag doesn't
1811 get set. In some cases, we can set the REG_POINTER flag
1812 from the declaration for the MEM. */
1813 if (REG_P (operand0)
1814 && GET_CODE (operand1) == MEM
1815 && !REG_POINTER (operand0))
1817 tree decl = MEM_EXPR (operand1);
1819 /* Set the register pointer flag and register alignment
1820 if the declaration for this memory reference is a
1826 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1828 if (TREE_CODE (decl) == COMPONENT_REF)
1829 decl = TREE_OPERAND (decl, 1);
1831 type = TREE_TYPE (decl);
1832 type = strip_array_types (type);
1834 if (POINTER_TYPE_P (type))
1838 type = TREE_TYPE (type);
1839 /* Using TYPE_ALIGN_OK is rather conservative as
1840 only the ada frontend actually sets it. */
1841 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1843 mark_reg_pointer (operand0, align);
1848 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1852 else if (GET_CODE (operand0) == MEM)
1854 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1855 && !(reload_in_progress || reload_completed))
1857 rtx temp = gen_reg_rtx (DFmode);
1859 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1860 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1863 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1865 /* Run this case quickly. */
1866 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1869 if (! (reload_in_progress || reload_completed))
1871 operands[0] = validize_mem (operand0);
1872 operands[1] = operand1 = force_reg (mode, operand1);
1876 /* Simplify the source if we need to.
1877 Note we do have to handle function labels here, even though we do
1878 not consider them legitimate constants. Loop optimizations can
1879 call the emit_move_xxx with one as a source. */
1880 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1881 || function_label_operand (operand1, VOIDmode)
1882 || (GET_CODE (operand1) == HIGH
1883 && symbolic_operand (XEXP (operand1, 0), mode)))
1887 if (GET_CODE (operand1) == HIGH)
1890 operand1 = XEXP (operand1, 0);
1892 if (symbolic_operand (operand1, mode))
1894 /* Argh. The assembler and linker can't handle arithmetic
1897 So we force the plabel into memory, load operand0 from
1898 the memory location, then add in the constant part. */
1899 if ((GET_CODE (operand1) == CONST
1900 && GET_CODE (XEXP (operand1, 0)) == PLUS
1901 && function_label_operand (XEXP (XEXP (operand1, 0), 0),
1903 || function_label_operand (operand1, VOIDmode))
1905 rtx temp, const_part;
1907 /* Figure out what (if any) scratch register to use. */
1908 if (reload_in_progress || reload_completed)
1910 scratch_reg = scratch_reg ? scratch_reg : operand0;
1911 /* SCRATCH_REG will hold an address and maybe the actual
1912 data. We want it in WORD_MODE regardless of what mode it
1913 was originally given to us. */
1914 scratch_reg = force_mode (word_mode, scratch_reg);
1917 scratch_reg = gen_reg_rtx (Pmode);
1919 if (GET_CODE (operand1) == CONST)
1921 /* Save away the constant part of the expression. */
1922 const_part = XEXP (XEXP (operand1, 0), 1);
1923 gcc_assert (GET_CODE (const_part) == CONST_INT);
1925 /* Force the function label into memory. */
1926 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1930 /* No constant part. */
1931 const_part = NULL_RTX;
1933 /* Force the function label into memory. */
1934 temp = force_const_mem (mode, operand1);
1938 /* Get the address of the memory location. PIC-ify it if
1940 temp = XEXP (temp, 0);
1942 temp = legitimize_pic_address (temp, mode, scratch_reg);
1944 /* Put the address of the memory location into our destination
1947 pa_emit_move_sequence (operands, mode, scratch_reg);
1949 /* Now load from the memory location into our destination
1951 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1952 pa_emit_move_sequence (operands, mode, scratch_reg);
1954 /* And add back in the constant part. */
1955 if (const_part != NULL_RTX)
1956 expand_inc (operand0, const_part);
1965 if (reload_in_progress || reload_completed)
1967 temp = scratch_reg ? scratch_reg : operand0;
1968 /* TEMP will hold an address and maybe the actual
1969 data. We want it in WORD_MODE regardless of what mode it
1970 was originally given to us. */
1971 temp = force_mode (word_mode, temp);
1974 temp = gen_reg_rtx (Pmode);
1976 /* (const (plus (symbol) (const_int))) must be forced to
1977 memory during/after reload if the const_int will not fit
1979 if (GET_CODE (operand1) == CONST
1980 && GET_CODE (XEXP (operand1, 0)) == PLUS
1981 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1982 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1983 && (reload_completed || reload_in_progress)
1986 rtx const_mem = force_const_mem (mode, operand1);
1987 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1989 operands[1] = replace_equiv_address (const_mem, operands[1]);
1990 pa_emit_move_sequence (operands, mode, temp);
1994 operands[1] = legitimize_pic_address (operand1, mode, temp);
1995 if (REG_P (operand0) && REG_P (operands[1]))
1996 copy_reg_pointer (operand0, operands[1]);
1997 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2000 /* On the HPPA, references to data space are supposed to use dp,
2001 register 27, but showing it in the RTL inhibits various cse
2002 and loop optimizations. */
2007 if (reload_in_progress || reload_completed)
2009 temp = scratch_reg ? scratch_reg : operand0;
2010 /* TEMP will hold an address and maybe the actual
2011 data. We want it in WORD_MODE regardless of what mode it
2012 was originally given to us. */
2013 temp = force_mode (word_mode, temp);
2016 temp = gen_reg_rtx (mode);
2018 /* Loading a SYMBOL_REF into a register makes that register
2019 safe to be used as the base in an indexed address.
2021 Don't mark hard registers though. That loses. */
2022 if (GET_CODE (operand0) == REG
2023 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2024 mark_reg_pointer (operand0, BITS_PER_UNIT);
2025 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2026 mark_reg_pointer (temp, BITS_PER_UNIT);
2029 set = gen_rtx_SET (mode, operand0, temp);
2031 set = gen_rtx_SET (VOIDmode,
2033 gen_rtx_LO_SUM (mode, temp, operand1));
2035 emit_insn (gen_rtx_SET (VOIDmode,
2037 gen_rtx_HIGH (mode, operand1)));
2043 else if (pa_tls_referenced_p (operand1))
2048 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
2050 addend = XEXP (XEXP (tmp, 0), 1);
2051 tmp = XEXP (XEXP (tmp, 0), 0);
2054 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
2055 tmp = legitimize_tls_address (tmp);
2058 tmp = gen_rtx_PLUS (mode, tmp, addend);
2059 tmp = force_operand (tmp, operands[0]);
2063 else if (GET_CODE (operand1) != CONST_INT
2064 || !pa_cint_ok_for_move (INTVAL (operand1)))
2068 HOST_WIDE_INT value = 0;
2069 HOST_WIDE_INT insv = 0;
2072 if (GET_CODE (operand1) == CONST_INT)
2073 value = INTVAL (operand1);
2076 && GET_CODE (operand1) == CONST_INT
2077 && HOST_BITS_PER_WIDE_INT > 32
2078 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2082 /* Extract the low order 32 bits of the value and sign extend.
2083 If the new value is the same as the original value, we can
2084 can use the original value as-is. If the new value is
2085 different, we use it and insert the most-significant 32-bits
2086 of the original value into the final result. */
2087 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2088 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2091 #if HOST_BITS_PER_WIDE_INT > 32
2092 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2096 operand1 = GEN_INT (nval);
2100 if (reload_in_progress || reload_completed)
2101 temp = scratch_reg ? scratch_reg : operand0;
2103 temp = gen_reg_rtx (mode);
2105 /* We don't directly split DImode constants on 32-bit targets
2106 because PLUS uses an 11-bit immediate and the insn sequence
2107 generated is not as efficient as the one using HIGH/LO_SUM. */
2108 if (GET_CODE (operand1) == CONST_INT
2109 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
2110 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2113 /* Directly break constant into high and low parts. This
2114 provides better optimization opportunities because various
2115 passes recognize constants split with PLUS but not LO_SUM.
2116 We use a 14-bit signed low part except when the addition
2117 of 0x4000 to the high part might change the sign of the
2119 HOST_WIDE_INT low = value & 0x3fff;
2120 HOST_WIDE_INT high = value & ~ 0x3fff;
2124 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2132 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2133 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2137 emit_insn (gen_rtx_SET (VOIDmode, temp,
2138 gen_rtx_HIGH (mode, operand1)));
2139 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2142 insn = emit_move_insn (operands[0], operands[1]);
2144 /* Now insert the most significant 32 bits of the value
2145 into the register. When we don't have a second register
2146 available, it could take up to nine instructions to load
2147 a 64-bit integer constant. Prior to reload, we force
2148 constants that would take more than three instructions
2149 to load to the constant pool. During and after reload,
2150 we have to handle all possible values. */
2153 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2154 register and the value to be inserted is outside the
2155 range that can be loaded with three depdi instructions. */
2156 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2158 operand1 = GEN_INT (insv);
2160 emit_insn (gen_rtx_SET (VOIDmode, temp,
2161 gen_rtx_HIGH (mode, operand1)));
2162 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2163 emit_insn (gen_insv (operand0, GEN_INT (32),
2168 int len = 5, pos = 27;
2170 /* Insert the bits using the depdi instruction. */
2173 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2174 HOST_WIDE_INT sign = v5 < 0;
2176 /* Left extend the insertion. */
2177 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2178 while (pos > 0 && (insv & 1) == sign)
2180 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2185 emit_insn (gen_insv (operand0, GEN_INT (len),
2186 GEN_INT (pos), GEN_INT (v5)));
2188 len = pos > 0 && pos < 5 ? pos : 5;
2194 set_unique_reg_note (insn, REG_EQUAL, op1);
2199 /* Now have insn-emit do whatever it normally does. */
2203 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2204 it will need a link/runtime reloc). */
2207 pa_reloc_needed (tree exp)
2211 switch (TREE_CODE (exp))
2216 case POINTER_PLUS_EXPR:
2219 reloc = pa_reloc_needed (TREE_OPERAND (exp, 0));
2220 reloc |= pa_reloc_needed (TREE_OPERAND (exp, 1));
2224 case NON_LVALUE_EXPR:
2225 reloc = pa_reloc_needed (TREE_OPERAND (exp, 0));
2231 unsigned HOST_WIDE_INT ix;
2233 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2235 reloc |= pa_reloc_needed (value);
2249 /* Return the best assembler insn template
2250 for moving operands[1] into operands[0] as a fullword. */
2252 pa_singlemove_string (rtx *operands)
2254 HOST_WIDE_INT intval;
2256 if (GET_CODE (operands[0]) == MEM)
2257 return "stw %r1,%0";
2258 if (GET_CODE (operands[1]) == MEM)
2260 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2265 gcc_assert (GET_MODE (operands[1]) == SFmode);
2267 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2269 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2270 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2272 operands[1] = GEN_INT (i);
2273 /* Fall through to CONST_INT case. */
2275 if (GET_CODE (operands[1]) == CONST_INT)
2277 intval = INTVAL (operands[1]);
2279 if (VAL_14_BITS_P (intval))
2281 else if ((intval & 0x7ff) == 0)
2282 return "ldil L'%1,%0";
2283 else if (pa_zdepi_cint_p (intval))
2284 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2286 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2288 return "copy %1,%0";
2292 /* Compute position (in OP[1]) and width (in OP[2])
2293 useful for copying IMM to a register using the zdepi
2294 instructions. Store the immediate value to insert in OP[0]. */
2296 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2300 /* Find the least significant set bit in IMM. */
2301 for (lsb = 0; lsb < 32; lsb++)
2308 /* Choose variants based on *sign* of the 5-bit field. */
2309 if ((imm & 0x10) == 0)
2310 len = (lsb <= 28) ? 4 : 32 - lsb;
2313 /* Find the width of the bitstring in IMM. */
2314 for (len = 5; len < 32 - lsb; len++)
2316 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2320 /* Sign extend IMM as a 5-bit value. */
2321 imm = (imm & 0xf) - 0x10;
2329 /* Compute position (in OP[1]) and width (in OP[2])
2330 useful for copying IMM to a register using the depdi,z
2331 instructions. Store the immediate value to insert in OP[0]. */
2334 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2336 int lsb, len, maxlen;
2338 maxlen = MIN (HOST_BITS_PER_WIDE_INT, 64);
2340 /* Find the least significant set bit in IMM. */
2341 for (lsb = 0; lsb < maxlen; lsb++)
2348 /* Choose variants based on *sign* of the 5-bit field. */
2349 if ((imm & 0x10) == 0)
2350 len = (lsb <= maxlen - 4) ? 4 : maxlen - lsb;
2353 /* Find the width of the bitstring in IMM. */
2354 for (len = 5; len < maxlen - lsb; len++)
2356 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2360 /* Extend length if host is narrow and IMM is negative. */
2361 if (HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb)
2364 /* Sign extend IMM as a 5-bit value. */
2365 imm = (imm & 0xf) - 0x10;
2373 /* Output assembler code to perform a doubleword move insn
2374 with operands OPERANDS. */
2377 pa_output_move_double (rtx *operands)
2379 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2381 rtx addreg0 = 0, addreg1 = 0;
2383 /* First classify both operands. */
2385 if (REG_P (operands[0]))
2387 else if (offsettable_memref_p (operands[0]))
2389 else if (GET_CODE (operands[0]) == MEM)
2394 if (REG_P (operands[1]))
2396 else if (CONSTANT_P (operands[1]))
2398 else if (offsettable_memref_p (operands[1]))
2400 else if (GET_CODE (operands[1]) == MEM)
2405 /* Check for the cases that the operand constraints are not
2406 supposed to allow to happen. */
2407 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2409 /* Handle copies between general and floating registers. */
2411 if (optype0 == REGOP && optype1 == REGOP
2412 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2414 if (FP_REG_P (operands[0]))
2416 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2417 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2418 return "{fldds|fldd} -16(%%sp),%0";
2422 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2423 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2424 return "{ldws|ldw} -12(%%sp),%R0";
2428 /* Handle auto decrementing and incrementing loads and stores
2429 specifically, since the structure of the function doesn't work
2430 for them without major modification. Do it better when we learn
2431 this port about the general inc/dec addressing of PA.
2432 (This was written by tege. Chide him if it doesn't work.) */
2434 if (optype0 == MEMOP)
2436 /* We have to output the address syntax ourselves, since print_operand
2437 doesn't deal with the addresses we want to use. Fix this later. */
2439 rtx addr = XEXP (operands[0], 0);
2440 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2442 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2444 operands[0] = XEXP (addr, 0);
2445 gcc_assert (GET_CODE (operands[1]) == REG
2446 && GET_CODE (operands[0]) == REG);
2448 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2450 /* No overlap between high target register and address
2451 register. (We do this in a non-obvious way to
2452 save a register file writeback) */
2453 if (GET_CODE (addr) == POST_INC)
2454 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2455 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2457 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2459 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2461 operands[0] = XEXP (addr, 0);
2462 gcc_assert (GET_CODE (operands[1]) == REG
2463 && GET_CODE (operands[0]) == REG);
2465 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2466 /* No overlap between high target register and address
2467 register. (We do this in a non-obvious way to save a
2468 register file writeback) */
2469 if (GET_CODE (addr) == PRE_INC)
2470 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2471 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2474 if (optype1 == MEMOP)
2476 /* We have to output the address syntax ourselves, since print_operand
2477 doesn't deal with the addresses we want to use. Fix this later. */
2479 rtx addr = XEXP (operands[1], 0);
2480 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2482 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2484 operands[1] = XEXP (addr, 0);
2485 gcc_assert (GET_CODE (operands[0]) == REG
2486 && GET_CODE (operands[1]) == REG);
2488 if (!reg_overlap_mentioned_p (high_reg, addr))
2490 /* No overlap between high target register and address
2491 register. (We do this in a non-obvious way to
2492 save a register file writeback) */
2493 if (GET_CODE (addr) == POST_INC)
2494 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2495 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2499 /* This is an undefined situation. We should load into the
2500 address register *and* update that register. Probably
2501 we don't need to handle this at all. */
2502 if (GET_CODE (addr) == POST_INC)
2503 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2504 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2507 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2509 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2511 operands[1] = XEXP (addr, 0);
2512 gcc_assert (GET_CODE (operands[0]) == REG
2513 && GET_CODE (operands[1]) == REG);
2515 if (!reg_overlap_mentioned_p (high_reg, addr))
2517 /* No overlap between high target register and address
2518 register. (We do this in a non-obvious way to
2519 save a register file writeback) */
2520 if (GET_CODE (addr) == PRE_INC)
2521 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2522 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2526 /* This is an undefined situation. We should load into the
2527 address register *and* update that register. Probably
2528 we don't need to handle this at all. */
2529 if (GET_CODE (addr) == PRE_INC)
2530 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2531 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2534 else if (GET_CODE (addr) == PLUS
2535 && GET_CODE (XEXP (addr, 0)) == MULT)
2538 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2540 if (!reg_overlap_mentioned_p (high_reg, addr))
2542 xoperands[0] = high_reg;
2543 xoperands[1] = XEXP (addr, 1);
2544 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2545 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2546 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2548 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2552 xoperands[0] = high_reg;
2553 xoperands[1] = XEXP (addr, 1);
2554 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2555 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2556 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2558 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2563 /* If an operand is an unoffsettable memory ref, find a register
2564 we can increment temporarily to make it refer to the second word. */
2566 if (optype0 == MEMOP)
2567 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2569 if (optype1 == MEMOP)
2570 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2572 /* Ok, we can do one word at a time.
2573 Normally we do the low-numbered word first.
2575 In either case, set up in LATEHALF the operands to use
2576 for the high-numbered word and in some cases alter the
2577 operands in OPERANDS to be suitable for the low-numbered word. */
2579 if (optype0 == REGOP)
2580 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2581 else if (optype0 == OFFSOP)
2582 latehalf[0] = adjust_address (operands[0], SImode, 4);
2584 latehalf[0] = operands[0];
2586 if (optype1 == REGOP)
2587 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2588 else if (optype1 == OFFSOP)
2589 latehalf[1] = adjust_address (operands[1], SImode, 4);
2590 else if (optype1 == CNSTOP)
2591 split_double (operands[1], &operands[1], &latehalf[1]);
2593 latehalf[1] = operands[1];
2595 /* If the first move would clobber the source of the second one,
2596 do them in the other order.
2598 This can happen in two cases:
2600 mem -> register where the first half of the destination register
2601 is the same register used in the memory's address. Reload
2602 can create such insns.
2604 mem in this case will be either register indirect or register
2605 indirect plus a valid offset.
2607 register -> register move where REGNO(dst) == REGNO(src + 1)
2608 someone (Tim/Tege?) claimed this can happen for parameter loads.
2610 Handle mem -> register case first. */
2611 if (optype0 == REGOP
2612 && (optype1 == MEMOP || optype1 == OFFSOP)
2613 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2616 /* Do the late half first. */
2618 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2619 output_asm_insn (pa_singlemove_string (latehalf), latehalf);
2623 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2624 return pa_singlemove_string (operands);
2627 /* Now handle register -> register case. */
2628 if (optype0 == REGOP && optype1 == REGOP
2629 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2631 output_asm_insn (pa_singlemove_string (latehalf), latehalf);
2632 return pa_singlemove_string (operands);
2635 /* Normal case: do the two words, low-numbered first. */
2637 output_asm_insn (pa_singlemove_string (operands), operands);
2639 /* Make any unoffsettable addresses point at high-numbered word. */
2641 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2643 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2646 output_asm_insn (pa_singlemove_string (latehalf), latehalf);
2648 /* Undo the adds we just did. */
2650 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2652 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2658 pa_output_fp_move_double (rtx *operands)
2660 if (FP_REG_P (operands[0]))
2662 if (FP_REG_P (operands[1])
2663 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2664 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2666 output_asm_insn ("fldd%F1 %1,%0", operands);
2668 else if (FP_REG_P (operands[1]))
2670 output_asm_insn ("fstd%F0 %1,%0", operands);
2676 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2678 /* This is a pain. You have to be prepared to deal with an
2679 arbitrary address here including pre/post increment/decrement.
2681 so avoid this in the MD. */
2682 gcc_assert (GET_CODE (operands[0]) == REG);
2684 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2685 xoperands[0] = operands[0];
2686 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2691 /* Return a REG that occurs in ADDR with coefficient 1.
2692 ADDR can be effectively incremented by incrementing REG. */
2695 find_addr_reg (rtx addr)
2697 while (GET_CODE (addr) == PLUS)
2699 if (GET_CODE (XEXP (addr, 0)) == REG)
2700 addr = XEXP (addr, 0);
2701 else if (GET_CODE (XEXP (addr, 1)) == REG)
2702 addr = XEXP (addr, 1);
2703 else if (CONSTANT_P (XEXP (addr, 0)))
2704 addr = XEXP (addr, 1);
2705 else if (CONSTANT_P (XEXP (addr, 1)))
2706 addr = XEXP (addr, 0);
2710 gcc_assert (GET_CODE (addr) == REG);
2714 /* Emit code to perform a block move.
2716 OPERANDS[0] is the destination pointer as a REG, clobbered.
2717 OPERANDS[1] is the source pointer as a REG, clobbered.
2718 OPERANDS[2] is a register for temporary storage.
2719 OPERANDS[3] is a register for temporary storage.
2720 OPERANDS[4] is the size as a CONST_INT
2721 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2722 OPERANDS[6] is another temporary register. */
2725 pa_output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2727 int align = INTVAL (operands[5]);
2728 unsigned long n_bytes = INTVAL (operands[4]);
2730 /* We can't move more than a word at a time because the PA
2731 has no longer integer move insns. (Could use fp mem ops?) */
2732 if (align > (TARGET_64BIT ? 8 : 4))
2733 align = (TARGET_64BIT ? 8 : 4);
2735 /* Note that we know each loop below will execute at least twice
2736 (else we would have open-coded the copy). */
2740 /* Pre-adjust the loop counter. */
2741 operands[4] = GEN_INT (n_bytes - 16);
2742 output_asm_insn ("ldi %4,%2", operands);
2745 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2746 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2747 output_asm_insn ("std,ma %3,8(%0)", operands);
2748 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2749 output_asm_insn ("std,ma %6,8(%0)", operands);
2751 /* Handle the residual. There could be up to 7 bytes of
2752 residual to copy! */
2753 if (n_bytes % 16 != 0)
2755 operands[4] = GEN_INT (n_bytes % 8);
2756 if (n_bytes % 16 >= 8)
2757 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2758 if (n_bytes % 8 != 0)
2759 output_asm_insn ("ldd 0(%1),%6", operands);
2760 if (n_bytes % 16 >= 8)
2761 output_asm_insn ("std,ma %3,8(%0)", operands);
2762 if (n_bytes % 8 != 0)
2763 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2768 /* Pre-adjust the loop counter. */
2769 operands[4] = GEN_INT (n_bytes - 8);
2770 output_asm_insn ("ldi %4,%2", operands);
2773 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2774 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2775 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2776 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2777 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2779 /* Handle the residual. There could be up to 7 bytes of
2780 residual to copy! */
2781 if (n_bytes % 8 != 0)
2783 operands[4] = GEN_INT (n_bytes % 4);
2784 if (n_bytes % 8 >= 4)
2785 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2786 if (n_bytes % 4 != 0)
2787 output_asm_insn ("ldw 0(%1),%6", operands);
2788 if (n_bytes % 8 >= 4)
2789 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2790 if (n_bytes % 4 != 0)
2791 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2796 /* Pre-adjust the loop counter. */
2797 operands[4] = GEN_INT (n_bytes - 4);
2798 output_asm_insn ("ldi %4,%2", operands);
2801 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2802 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2803 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2804 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2805 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2807 /* Handle the residual. */
2808 if (n_bytes % 4 != 0)
2810 if (n_bytes % 4 >= 2)
2811 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2812 if (n_bytes % 2 != 0)
2813 output_asm_insn ("ldb 0(%1),%6", operands);
2814 if (n_bytes % 4 >= 2)
2815 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2816 if (n_bytes % 2 != 0)
2817 output_asm_insn ("stb %6,0(%0)", operands);
2822 /* Pre-adjust the loop counter. */
2823 operands[4] = GEN_INT (n_bytes - 2);
2824 output_asm_insn ("ldi %4,%2", operands);
2827 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2828 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2829 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2830 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2831 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2833 /* Handle the residual. */
2834 if (n_bytes % 2 != 0)
2836 output_asm_insn ("ldb 0(%1),%3", operands);
2837 output_asm_insn ("stb %3,0(%0)", operands);
2846 /* Count the number of insns necessary to handle this block move.
2848 Basic structure is the same as emit_block_move, except that we
2849 count insns rather than emit them. */
2852 compute_movmem_length (rtx insn)
2854 rtx pat = PATTERN (insn);
2855 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2856 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2857 unsigned int n_insns = 0;
2859 /* We can't move more than four bytes at a time because the PA
2860 has no longer integer move insns. (Could use fp mem ops?) */
2861 if (align > (TARGET_64BIT ? 8 : 4))
2862 align = (TARGET_64BIT ? 8 : 4);
2864 /* The basic copying loop. */
2868 if (n_bytes % (2 * align) != 0)
2870 if ((n_bytes % (2 * align)) >= align)
2873 if ((n_bytes % align) != 0)
2877 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2881 /* Emit code to perform a block clear.
2883 OPERANDS[0] is the destination pointer as a REG, clobbered.
2884 OPERANDS[1] is a register for temporary storage.
2885 OPERANDS[2] is the size as a CONST_INT
2886 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2889 pa_output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2891 int align = INTVAL (operands[3]);
2892 unsigned long n_bytes = INTVAL (operands[2]);
2894 /* We can't clear more than a word at a time because the PA
2895 has no longer integer move insns. */
2896 if (align > (TARGET_64BIT ? 8 : 4))
2897 align = (TARGET_64BIT ? 8 : 4);
2899 /* Note that we know each loop below will execute at least twice
2900 (else we would have open-coded the copy). */
2904 /* Pre-adjust the loop counter. */
2905 operands[2] = GEN_INT (n_bytes - 16);
2906 output_asm_insn ("ldi %2,%1", operands);
2909 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2910 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2911 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2913 /* Handle the residual. There could be up to 7 bytes of
2914 residual to copy! */
2915 if (n_bytes % 16 != 0)
2917 operands[2] = GEN_INT (n_bytes % 8);
2918 if (n_bytes % 16 >= 8)
2919 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2920 if (n_bytes % 8 != 0)
2921 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2926 /* Pre-adjust the loop counter. */
2927 operands[2] = GEN_INT (n_bytes - 8);
2928 output_asm_insn ("ldi %2,%1", operands);
2931 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2932 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2933 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2935 /* Handle the residual. There could be up to 7 bytes of
2936 residual to copy! */
2937 if (n_bytes % 8 != 0)
2939 operands[2] = GEN_INT (n_bytes % 4);
2940 if (n_bytes % 8 >= 4)
2941 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2942 if (n_bytes % 4 != 0)
2943 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2948 /* Pre-adjust the loop counter. */
2949 operands[2] = GEN_INT (n_bytes - 4);
2950 output_asm_insn ("ldi %2,%1", operands);
2953 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2954 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2955 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2957 /* Handle the residual. */
2958 if (n_bytes % 4 != 0)
2960 if (n_bytes % 4 >= 2)
2961 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2962 if (n_bytes % 2 != 0)
2963 output_asm_insn ("stb %%r0,0(%0)", operands);
2968 /* Pre-adjust the loop counter. */
2969 operands[2] = GEN_INT (n_bytes - 2);
2970 output_asm_insn ("ldi %2,%1", operands);
2973 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2974 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2975 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2977 /* Handle the residual. */
2978 if (n_bytes % 2 != 0)
2979 output_asm_insn ("stb %%r0,0(%0)", operands);
2988 /* Count the number of insns necessary to handle this block move.
2990 Basic structure is the same as emit_block_move, except that we
2991 count insns rather than emit them. */
2994 compute_clrmem_length (rtx insn)
2996 rtx pat = PATTERN (insn);
2997 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2998 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2999 unsigned int n_insns = 0;
3001 /* We can't clear more than a word at a time because the PA
3002 has no longer integer move insns. */
3003 if (align > (TARGET_64BIT ? 8 : 4))
3004 align = (TARGET_64BIT ? 8 : 4);
3006 /* The basic loop. */
3010 if (n_bytes % (2 * align) != 0)
3012 if ((n_bytes % (2 * align)) >= align)
3015 if ((n_bytes % align) != 0)
3019 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3025 pa_output_and (rtx *operands)
3027 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3029 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3030 int ls0, ls1, ms0, p, len;
3032 for (ls0 = 0; ls0 < 32; ls0++)
3033 if ((mask & (1 << ls0)) == 0)
3036 for (ls1 = ls0; ls1 < 32; ls1++)
3037 if ((mask & (1 << ls1)) != 0)
3040 for (ms0 = ls1; ms0 < 32; ms0++)
3041 if ((mask & (1 << ms0)) == 0)
3044 gcc_assert (ms0 == 32);
3052 operands[2] = GEN_INT (len);
3053 return "{extru|extrw,u} %1,31,%2,%0";
3057 /* We could use this `depi' for the case above as well, but `depi'
3058 requires one more register file access than an `extru'. */
3063 operands[2] = GEN_INT (p);
3064 operands[3] = GEN_INT (len);
3065 return "{depi|depwi} 0,%2,%3,%0";
3069 return "and %1,%2,%0";
3072 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3073 storing the result in operands[0]. */
3075 pa_output_64bit_and (rtx *operands)
3077 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3079 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3080 int ls0, ls1, ms0, p, len;
3082 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3083 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3086 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3087 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3090 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3091 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3094 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
3096 if (ls1 == HOST_BITS_PER_WIDE_INT)
3102 operands[2] = GEN_INT (len);
3103 return "extrd,u %1,63,%2,%0";
3107 /* We could use this `depi' for the case above as well, but `depi'
3108 requires one more register file access than an `extru'. */
3113 operands[2] = GEN_INT (p);
3114 operands[3] = GEN_INT (len);
3115 return "depdi 0,%2,%3,%0";
3119 return "and %1,%2,%0";
3123 pa_output_ior (rtx *operands)
3125 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3126 int bs0, bs1, p, len;
3128 if (INTVAL (operands[2]) == 0)
3129 return "copy %1,%0";
3131 for (bs0 = 0; bs0 < 32; bs0++)
3132 if ((mask & (1 << bs0)) != 0)
3135 for (bs1 = bs0; bs1 < 32; bs1++)
3136 if ((mask & (1 << bs1)) == 0)
3139 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3144 operands[2] = GEN_INT (p);
3145 operands[3] = GEN_INT (len);
3146 return "{depi|depwi} -1,%2,%3,%0";
3149 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3150 storing the result in operands[0]. */
3152 pa_output_64bit_ior (rtx *operands)
3154 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3155 int bs0, bs1, p, len;
3157 if (INTVAL (operands[2]) == 0)
3158 return "copy %1,%0";
3160 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3161 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3164 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3165 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3168 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
3169 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3174 operands[2] = GEN_INT (p);
3175 operands[3] = GEN_INT (len);
3176 return "depdi -1,%2,%3,%0";
3179 /* Target hook for assembling integer objects. This code handles
3180 aligned SI and DI integers specially since function references
3181 must be preceded by P%. */
3184 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3186 if (size == UNITS_PER_WORD
3188 && function_label_operand (x, VOIDmode))
3190 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3191 output_addr_const (asm_out_file, x);
3192 fputc ('\n', asm_out_file);
3195 return default_assemble_integer (x, size, aligned_p);
3198 /* Output an ascii string. */
3200 pa_output_ascii (FILE *file, const char *p, int size)
3204 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3206 /* The HP assembler can only take strings of 256 characters at one
3207 time. This is a limitation on input line length, *not* the
3208 length of the string. Sigh. Even worse, it seems that the
3209 restriction is in number of input characters (see \xnn &
3210 \whatever). So we have to do this very carefully. */
3212 fputs ("\t.STRING \"", file);
3215 for (i = 0; i < size; i += 4)
3219 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3221 register unsigned int c = (unsigned char) p[i + io];
3223 if (c == '\"' || c == '\\')
3224 partial_output[co++] = '\\';
3225 if (c >= ' ' && c < 0177)
3226 partial_output[co++] = c;
3230 partial_output[co++] = '\\';
3231 partial_output[co++] = 'x';
3232 hexd = c / 16 - 0 + '0';
3234 hexd -= '9' - 'a' + 1;
3235 partial_output[co++] = hexd;
3236 hexd = c % 16 - 0 + '0';
3238 hexd -= '9' - 'a' + 1;
3239 partial_output[co++] = hexd;
3242 if (chars_output + co > 243)
3244 fputs ("\"\n\t.STRING \"", file);
3247 fwrite (partial_output, 1, (size_t) co, file);
3251 fputs ("\"\n", file);
3254 /* Try to rewrite floating point comparisons & branches to avoid
3255 useless add,tr insns.
3257 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3258 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3259 first attempt to remove useless add,tr insns. It is zero
3260 for the second pass as reorg sometimes leaves bogus REG_DEAD
3263 When CHECK_NOTES is zero we can only eliminate add,tr insns
3264 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3267 remove_useless_addtr_insns (int check_notes)
3270 static int pass = 0;
3272 /* This is fairly cheap, so always run it when optimizing. */
3276 int fbranch_count = 0;
3278 /* Walk all the insns in this function looking for fcmp & fbranch
3279 instructions. Keep track of how many of each we find. */
3280 for (insn = get_insns (); insn; insn = next_insn (insn))
3284 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3285 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3288 tmp = PATTERN (insn);
3290 /* It must be a set. */
3291 if (GET_CODE (tmp) != SET)
3294 /* If the destination is CCFP, then we've found an fcmp insn. */
3295 tmp = SET_DEST (tmp);
3296 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3302 tmp = PATTERN (insn);
3303 /* If this is an fbranch instruction, bump the fbranch counter. */
3304 if (GET_CODE (tmp) == SET
3305 && SET_DEST (tmp) == pc_rtx
3306 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3307 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3308 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3309 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3317 /* Find all floating point compare + branch insns. If possible,
3318 reverse the comparison & the branch to avoid add,tr insns. */
3319 for (insn = get_insns (); insn; insn = next_insn (insn))
3323 /* Ignore anything that isn't an INSN. */
3324 if (GET_CODE (insn) != INSN)
3327 tmp = PATTERN (insn);
3329 /* It must be a set. */
3330 if (GET_CODE (tmp) != SET)
3333 /* The destination must be CCFP, which is register zero. */
3334 tmp = SET_DEST (tmp);
3335 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3338 /* INSN should be a set of CCFP.
3340 See if the result of this insn is used in a reversed FP
3341 conditional branch. If so, reverse our condition and
3342 the branch. Doing so avoids useless add,tr insns. */
3343 next = next_insn (insn);
3346 /* Jumps, calls and labels stop our search. */
3347 if (GET_CODE (next) == JUMP_INSN
3348 || GET_CODE (next) == CALL_INSN
3349 || GET_CODE (next) == CODE_LABEL)
3352 /* As does another fcmp insn. */
3353 if (GET_CODE (next) == INSN
3354 && GET_CODE (PATTERN (next)) == SET
3355 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3356 && REGNO (SET_DEST (PATTERN (next))) == 0)
3359 next = next_insn (next);
3362 /* Is NEXT_INSN a branch? */
3364 && GET_CODE (next) == JUMP_INSN)
3366 rtx pattern = PATTERN (next);
3368 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3369 and CCFP dies, then reverse our conditional and the branch
3370 to avoid the add,tr. */
3371 if (GET_CODE (pattern) == SET
3372 && SET_DEST (pattern) == pc_rtx
3373 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3374 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3375 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3376 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3377 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3378 && (fcmp_count == fbranch_count
3380 && find_regno_note (next, REG_DEAD, 0))))
3382 /* Reverse the branch. */
3383 tmp = XEXP (SET_SRC (pattern), 1);
3384 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3385 XEXP (SET_SRC (pattern), 2) = tmp;
3386 INSN_CODE (next) = -1;
3388 /* Reverse our condition. */
3389 tmp = PATTERN (insn);
3390 PUT_CODE (XEXP (tmp, 1),
3391 (reverse_condition_maybe_unordered
3392 (GET_CODE (XEXP (tmp, 1)))));
3402 /* You may have trouble believing this, but this is the 32 bit HP-PA
3407 Variable arguments (optional; any number may be allocated)
3409 SP-(4*(N+9)) arg word N
3414 Fixed arguments (must be allocated; may remain unused)
3423 SP-32 External Data Pointer (DP)
3425 SP-24 External/stub RP (RP')
3429 SP-8 Calling Stub RP (RP'')
3434 SP-0 Stack Pointer (points to next available address)
3438 /* This function saves registers as follows. Registers marked with ' are
3439 this function's registers (as opposed to the previous function's).
3440 If a frame_pointer isn't needed, r4 is saved as a general register;
3441 the space for the frame pointer is still allocated, though, to keep
3447 SP (FP') Previous FP
3448 SP + 4 Alignment filler (sigh)
3449 SP + 8 Space for locals reserved here.
3453 SP + n All call saved register used.
3457 SP + o All call saved fp registers used.
3461 SP + p (SP') points to next available address.
3465 /* Global variables set by output_function_prologue(). */
3466 /* Size of frame. Need to know this to emit return insns from
3468 static HOST_WIDE_INT actual_fsize, local_fsize;
3469 static int save_fregs;
3471 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3472 Handle case where DISP > 8k by using the add_high_const patterns.
3474 Note in DISP > 8k case, we will leave the high part of the address
3475 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3478 store_reg (int reg, HOST_WIDE_INT disp, int base)
3480 rtx insn, dest, src, basereg;
3482 src = gen_rtx_REG (word_mode, reg);
3483 basereg = gen_rtx_REG (Pmode, base);
3484 if (VAL_14_BITS_P (disp))
3486 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3487 insn = emit_move_insn (dest, src);
3489 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3491 rtx delta = GEN_INT (disp);
3492 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3494 emit_move_insn (tmpreg, delta);
3495 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3498 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3499 gen_rtx_SET (VOIDmode, tmpreg,
3500 gen_rtx_PLUS (Pmode, basereg, delta)));
3501 RTX_FRAME_RELATED_P (insn) = 1;
3503 dest = gen_rtx_MEM (word_mode, tmpreg);
3504 insn = emit_move_insn (dest, src);
3508 rtx delta = GEN_INT (disp);
3509 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3510 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3512 emit_move_insn (tmpreg, high);
3513 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3514 insn = emit_move_insn (dest, src);
3516 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3517 gen_rtx_SET (VOIDmode,
3518 gen_rtx_MEM (word_mode,
3519 gen_rtx_PLUS (word_mode,
3526 RTX_FRAME_RELATED_P (insn) = 1;
3529 /* Emit RTL to store REG at the memory location specified by BASE and then
3530 add MOD to BASE. MOD must be <= 8k. */
3533 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3535 rtx insn, basereg, srcreg, delta;
3537 gcc_assert (VAL_14_BITS_P (mod));
3539 basereg = gen_rtx_REG (Pmode, base);
3540 srcreg = gen_rtx_REG (word_mode, reg);
3541 delta = GEN_INT (mod);
3543 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3546 RTX_FRAME_RELATED_P (insn) = 1;
3548 /* RTX_FRAME_RELATED_P must be set on each frame related set
3549 in a parallel with more than one element. */
3550 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3551 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3555 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3556 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3557 whether to add a frame note or not.
3559 In the DISP > 8k case, we leave the high part of the address in %r1.
3560 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3563 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3567 if (VAL_14_BITS_P (disp))
3569 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3570 plus_constant (gen_rtx_REG (Pmode, base), disp));
3572 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3574 rtx basereg = gen_rtx_REG (Pmode, base);
3575 rtx delta = GEN_INT (disp);
3576 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3578 emit_move_insn (tmpreg, delta);
3579 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3580 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3582 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3583 gen_rtx_SET (VOIDmode, tmpreg,
3584 gen_rtx_PLUS (Pmode, basereg, delta)));
3588 rtx basereg = gen_rtx_REG (Pmode, base);
3589 rtx delta = GEN_INT (disp);
3590 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3592 emit_move_insn (tmpreg,
3593 gen_rtx_PLUS (Pmode, basereg,
3594 gen_rtx_HIGH (Pmode, delta)));
3595 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3596 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3599 if (DO_FRAME_NOTES && note)
3600 RTX_FRAME_RELATED_P (insn) = 1;
3604 pa_compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3609 /* The code in pa_expand_prologue and pa_expand_epilogue must
3610 be consistent with the rounding and size calculation done here.
3611 Change them at the same time. */
3613 /* We do our own stack alignment. First, round the size of the
3614 stack locals up to a word boundary. */
3615 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3617 /* Space for previous frame pointer + filler. If any frame is
3618 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3619 waste some space here for the sake of HP compatibility. The
3620 first slot is only used when the frame pointer is needed. */
3621 if (size || frame_pointer_needed)
3622 size += STARTING_FRAME_OFFSET;
3624 /* If the current function calls __builtin_eh_return, then we need
3625 to allocate stack space for registers that will hold data for
3626 the exception handler. */
3627 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3631 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3633 size += i * UNITS_PER_WORD;
3636 /* Account for space used by the callee general register saves. */
3637 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3638 if (df_regs_ever_live_p (i))
3639 size += UNITS_PER_WORD;
3641 /* Account for space used by the callee floating point register saves. */
3642 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3643 if (df_regs_ever_live_p (i)
3644 || (!TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3648 /* We always save both halves of the FP register, so always
3649 increment the frame size by 8 bytes. */
3653 /* If any of the floating registers are saved, account for the
3654 alignment needed for the floating point register save block. */
3657 size = (size + 7) & ~7;
3662 /* The various ABIs include space for the outgoing parameters in the
3663 size of the current function's stack frame. We don't need to align
3664 for the outgoing arguments as their alignment is set by the final
3665 rounding for the frame as a whole. */
3666 size += crtl->outgoing_args_size;
3668 /* Allocate space for the fixed frame marker. This space must be
3669 allocated for any function that makes calls or allocates
3671 if (!current_function_is_leaf || size)
3672 size += TARGET_64BIT ? 48 : 32;
3674 /* Finally, round to the preferred stack boundary. */
3675 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3676 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3679 /* Generate the assembly code for function entry. FILE is a stdio
3680 stream to output the code to. SIZE is an int: how many units of
3681 temporary storage to allocate.
3683 Refer to the array `regs_ever_live' to determine which registers to
3684 save; `regs_ever_live[I]' is nonzero if register number I is ever
3685 used in the function. This function is responsible for knowing
3686 which registers should not be saved even if used. */
3688 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3689 of memory. If any fpu reg is used in the function, we allocate
3690 such a block here, at the bottom of the frame, just in case it's needed.
3692 If this function is a leaf procedure, then we may choose not
3693 to do a "save" insn. The decision about whether or not
3694 to do this is made in regclass.c. */
3697 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3699 /* The function's label and associated .PROC must never be
3700 separated and must be output *after* any profiling declarations
3701 to avoid changing spaces/subspaces within a procedure. */
3702 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3703 fputs ("\t.PROC\n", file);
3705 /* pa_expand_prologue does the dirty work now. We just need
3706 to output the assembler directives which denote the start
3708 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3709 if (current_function_is_leaf)
3710 fputs (",NO_CALLS", file);
3712 fputs (",CALLS", file);
3714 fputs (",SAVE_RP", file);
3716 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3717 at the beginning of the frame and that it is used as the frame
3718 pointer for the frame. We do this because our current frame
3719 layout doesn't conform to that specified in the HP runtime
3720 documentation and we need a way to indicate to programs such as
3721 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3722 isn't used by HP compilers but is supported by the assembler.
3723 However, SAVE_SP is supposed to indicate that the previous stack
3724 pointer has been saved in the frame marker. */
3725 if (frame_pointer_needed)
3726 fputs (",SAVE_SP", file);
3728 /* Pass on information about the number of callee register saves
3729 performed in the prologue.
3731 The compiler is supposed to pass the highest register number
3732 saved, the assembler then has to adjust that number before
3733 entering it into the unwind descriptor (to account for any
3734 caller saved registers with lower register numbers than the
3735 first callee saved register). */
3737 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3740 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3742 fputs ("\n\t.ENTRY\n", file);
3744 remove_useless_addtr_insns (0);
3748 pa_expand_prologue (void)
3750 int merge_sp_adjust_with_store = 0;
3751 HOST_WIDE_INT size = get_frame_size ();
3752 HOST_WIDE_INT offset;
3760 /* Compute total size for frame pointer, filler, locals and rounding to
3761 the next word boundary. Similar code appears in pa_compute_frame_size
3762 and must be changed in tandem with this code. */
3763 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3764 if (local_fsize || frame_pointer_needed)
3765 local_fsize += STARTING_FRAME_OFFSET;
3767 actual_fsize = pa_compute_frame_size (size, &save_fregs);
3768 if (flag_stack_usage_info)
3769 current_function_static_stack_size = actual_fsize;
3771 /* Compute a few things we will use often. */
3772 tmpreg = gen_rtx_REG (word_mode, 1);
3774 /* Save RP first. The calling conventions manual states RP will
3775 always be stored into the caller's frame at sp - 20 or sp - 16
3776 depending on which ABI is in use. */
3777 if (df_regs_ever_live_p (2) || crtl->calls_eh_return)
3779 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3785 /* Allocate the local frame and set up the frame pointer if needed. */
3786 if (actual_fsize != 0)
3788 if (frame_pointer_needed)
3790 /* Copy the old frame pointer temporarily into %r1. Set up the
3791 new stack pointer, then store away the saved old frame pointer
3792 into the stack at sp and at the same time update the stack
3793 pointer by actual_fsize bytes. Two versions, first
3794 handles small (<8k) frames. The second handles large (>=8k)
3796 insn = emit_move_insn (tmpreg, hard_frame_pointer_rtx);
3798 RTX_FRAME_RELATED_P (insn) = 1;
3800 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3802 RTX_FRAME_RELATED_P (insn) = 1;
3804 if (VAL_14_BITS_P (actual_fsize))
3805 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3808 /* It is incorrect to store the saved frame pointer at *sp,
3809 then increment sp (writes beyond the current stack boundary).
3811 So instead use stwm to store at *sp and post-increment the
3812 stack pointer as an atomic operation. Then increment sp to
3813 finish allocating the new frame. */
3814 HOST_WIDE_INT adjust1 = 8192 - 64;
3815 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3817 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3818 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3822 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3823 we need to store the previous stack pointer (frame pointer)
3824 into the frame marker on targets that use the HP unwind
3825 library. This allows the HP unwind library to be used to
3826 unwind GCC frames. However, we are not fully compatible
3827 with the HP library because our frame layout differs from
3828 that specified in the HP runtime specification.
3830 We don't want a frame note on this instruction as the frame
3831 marker moves during dynamic stack allocation.
3833 This instruction also serves as a blockage to prevent
3834 register spills from being scheduled before the stack
3835 pointer is raised. This is necessary as we store
3836 registers using the frame pointer as a base register,
3837 and the frame pointer is set before sp is raised. */
3838 if (TARGET_HPUX_UNWIND_LIBRARY)
3840 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3841 GEN_INT (TARGET_64BIT ? -8 : -4));
3843 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3844 hard_frame_pointer_rtx);
3847 emit_insn (gen_blockage ());
3849 /* no frame pointer needed. */
3852 /* In some cases we can perform the first callee register save
3853 and allocating the stack frame at the same time. If so, just
3854 make a note of it and defer allocating the frame until saving
3855 the callee registers. */
3856 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3857 merge_sp_adjust_with_store = 1;
3858 /* Can not optimize. Adjust the stack frame by actual_fsize
3861 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3866 /* Normal register save.
3868 Do not save the frame pointer in the frame_pointer_needed case. It
3869 was done earlier. */
3870 if (frame_pointer_needed)
3872 offset = local_fsize;
3874 /* Saving the EH return data registers in the frame is the simplest
3875 way to get the frame unwind information emitted. We put them
3876 just before the general registers. */
3877 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3879 unsigned int i, regno;
3883 regno = EH_RETURN_DATA_REGNO (i);
3884 if (regno == INVALID_REGNUM)
3887 store_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
3888 offset += UNITS_PER_WORD;
3892 for (i = 18; i >= 4; i--)
3893 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3895 store_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
3896 offset += UNITS_PER_WORD;
3899 /* Account for %r3 which is saved in a special place. */
3902 /* No frame pointer needed. */
3905 offset = local_fsize - actual_fsize;
3907 /* Saving the EH return data registers in the frame is the simplest
3908 way to get the frame unwind information emitted. */
3909 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3911 unsigned int i, regno;
3915 regno = EH_RETURN_DATA_REGNO (i);
3916 if (regno == INVALID_REGNUM)
3919 /* If merge_sp_adjust_with_store is nonzero, then we can
3920 optimize the first save. */
3921 if (merge_sp_adjust_with_store)
3923 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3924 merge_sp_adjust_with_store = 0;
3927 store_reg (regno, offset, STACK_POINTER_REGNUM);
3928 offset += UNITS_PER_WORD;
3932 for (i = 18; i >= 3; i--)
3933 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3935 /* If merge_sp_adjust_with_store is nonzero, then we can
3936 optimize the first GR save. */
3937 if (merge_sp_adjust_with_store)
3939 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3940 merge_sp_adjust_with_store = 0;
3943 store_reg (i, offset, STACK_POINTER_REGNUM);
3944 offset += UNITS_PER_WORD;
3948 /* If we wanted to merge the SP adjustment with a GR save, but we never
3949 did any GR saves, then just emit the adjustment here. */
3950 if (merge_sp_adjust_with_store)
3951 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3955 /* The hppa calling conventions say that %r19, the pic offset
3956 register, is saved at sp - 32 (in this function's frame)
3957 when generating PIC code. FIXME: What is the correct thing
3958 to do for functions which make no calls and allocate no
3959 frame? Do we need to allocate a frame, or can we just omit
3960 the save? For now we'll just omit the save.
3962 We don't want a note on this insn as the frame marker can
3963 move if there is a dynamic stack allocation. */
3964 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3966 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3968 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3972 /* Align pointer properly (doubleword boundary). */
3973 offset = (offset + 7) & ~7;
3975 /* Floating point register store. */
3980 /* First get the frame or stack pointer to the start of the FP register
3982 if (frame_pointer_needed)
3984 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
3985 base = hard_frame_pointer_rtx;
3989 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3990 base = stack_pointer_rtx;
3993 /* Now actually save the FP registers. */
3994 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3996 if (df_regs_ever_live_p (i)
3997 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3999 rtx addr, insn, reg;
4000 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4001 reg = gen_rtx_REG (DFmode, i);
4002 insn = emit_move_insn (addr, reg);
4005 RTX_FRAME_RELATED_P (insn) = 1;
4008 rtx mem = gen_rtx_MEM (DFmode,
4009 plus_constant (base, offset));
4010 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4011 gen_rtx_SET (VOIDmode, mem, reg));
4015 rtx meml = gen_rtx_MEM (SFmode,
4016 plus_constant (base, offset));
4017 rtx memr = gen_rtx_MEM (SFmode,
4018 plus_constant (base, offset + 4));
4019 rtx regl = gen_rtx_REG (SFmode, i);
4020 rtx regr = gen_rtx_REG (SFmode, i + 1);
4021 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4022 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4025 RTX_FRAME_RELATED_P (setl) = 1;
4026 RTX_FRAME_RELATED_P (setr) = 1;
4027 vec = gen_rtvec (2, setl, setr);
4028 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4029 gen_rtx_SEQUENCE (VOIDmode, vec));
4032 offset += GET_MODE_SIZE (DFmode);
4039 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4040 Handle case where DISP > 8k by using the add_high_const patterns. */
4043 load_reg (int reg, HOST_WIDE_INT disp, int base)
4045 rtx dest = gen_rtx_REG (word_mode, reg);
4046 rtx basereg = gen_rtx_REG (Pmode, base);
4049 if (VAL_14_BITS_P (disp))
4050 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4051 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4053 rtx delta = GEN_INT (disp);
4054 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4056 emit_move_insn (tmpreg, delta);
4057 if (TARGET_DISABLE_INDEXING)
4059 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4060 src = gen_rtx_MEM (word_mode, tmpreg);
4063 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4067 rtx delta = GEN_INT (disp);
4068 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4069 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4071 emit_move_insn (tmpreg, high);
4072 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4075 emit_move_insn (dest, src);
4078 /* Update the total code bytes output to the text section. */
4081 update_total_code_bytes (unsigned int nbytes)
4083 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4084 && !IN_NAMED_SECTION_P (cfun->decl))
4086 unsigned int old_total = total_code_bytes;
4088 total_code_bytes += nbytes;
4090 /* Be prepared to handle overflows. */
4091 if (old_total > total_code_bytes)
4092 total_code_bytes = UINT_MAX;
4096 /* This function generates the assembly code for function exit.
4097 Args are as for output_function_prologue ().
4099 The function epilogue should not depend on the current stack
4100 pointer! It should use the frame pointer only. This is mandatory
4101 because of alloca; we also take advantage of it to omit stack
4102 adjustments before returning. */
4105 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4107 rtx insn = get_last_insn ();
4111 /* pa_expand_epilogue does the dirty work now. We just need
4112 to output the assembler directives which denote the end
4115 To make debuggers happy, emit a nop if the epilogue was completely
4116 eliminated due to a volatile call as the last insn in the
4117 current function. That way the return address (in %r2) will
4118 always point to a valid instruction in the current function. */
4120 /* Get the last real insn. */
4121 if (GET_CODE (insn) == NOTE)
4122 insn = prev_real_insn (insn);
4124 /* If it is a sequence, then look inside. */
4125 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4126 insn = XVECEXP (PATTERN (insn), 0, 0);
4128 /* If insn is a CALL_INSN, then it must be a call to a volatile
4129 function (otherwise there would be epilogue insns). */
4130 if (insn && GET_CODE (insn) == CALL_INSN)
4132 fputs ("\tnop\n", file);
4136 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4138 if (TARGET_SOM && TARGET_GAS)
4140 /* We done with this subspace except possibly for some additional
4141 debug information. Forget that we are in this subspace to ensure
4142 that the next function is output in its own subspace. */
4144 cfun->machine->in_nsubspa = 2;
4147 if (INSN_ADDRESSES_SET_P ())
4149 insn = get_last_nonnote_insn ();
4150 last_address += INSN_ADDRESSES (INSN_UID (insn));
4152 last_address += insn_default_length (insn);
4153 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4154 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4157 last_address = UINT_MAX;
4159 /* Finally, update the total number of code bytes output so far. */
4160 update_total_code_bytes (last_address);
4164 pa_expand_epilogue (void)
4167 HOST_WIDE_INT offset;
4168 HOST_WIDE_INT ret_off = 0;
4170 int merge_sp_adjust_with_load = 0;
4172 /* We will use this often. */
4173 tmpreg = gen_rtx_REG (word_mode, 1);
4175 /* Try to restore RP early to avoid load/use interlocks when
4176 RP gets used in the return (bv) instruction. This appears to still
4177 be necessary even when we schedule the prologue and epilogue. */
4180 ret_off = TARGET_64BIT ? -16 : -20;
4181 if (frame_pointer_needed)
4183 load_reg (2, ret_off, HARD_FRAME_POINTER_REGNUM);
4188 /* No frame pointer, and stack is smaller than 8k. */
4189 if (VAL_14_BITS_P (ret_off - actual_fsize))
4191 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4197 /* General register restores. */
4198 if (frame_pointer_needed)
4200 offset = local_fsize;
4202 /* If the current function calls __builtin_eh_return, then we need
4203 to restore the saved EH data registers. */
4204 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4206 unsigned int i, regno;
4210 regno = EH_RETURN_DATA_REGNO (i);
4211 if (regno == INVALID_REGNUM)
4214 load_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
4215 offset += UNITS_PER_WORD;
4219 for (i = 18; i >= 4; i--)
4220 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4222 load_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
4223 offset += UNITS_PER_WORD;
4228 offset = local_fsize - actual_fsize;
4230 /* If the current function calls __builtin_eh_return, then we need
4231 to restore the saved EH data registers. */
4232 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4234 unsigned int i, regno;
4238 regno = EH_RETURN_DATA_REGNO (i);
4239 if (regno == INVALID_REGNUM)
4242 /* Only for the first load.
4243 merge_sp_adjust_with_load holds the register load
4244 with which we will merge the sp adjustment. */
4245 if (merge_sp_adjust_with_load == 0
4247 && VAL_14_BITS_P (-actual_fsize))
4248 merge_sp_adjust_with_load = regno;
4250 load_reg (regno, offset, STACK_POINTER_REGNUM);
4251 offset += UNITS_PER_WORD;
4255 for (i = 18; i >= 3; i--)
4257 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4259 /* Only for the first load.
4260 merge_sp_adjust_with_load holds the register load
4261 with which we will merge the sp adjustment. */
4262 if (merge_sp_adjust_with_load == 0
4264 && VAL_14_BITS_P (-actual_fsize))
4265 merge_sp_adjust_with_load = i;
4267 load_reg (i, offset, STACK_POINTER_REGNUM);
4268 offset += UNITS_PER_WORD;
4273 /* Align pointer properly (doubleword boundary). */
4274 offset = (offset + 7) & ~7;
4276 /* FP register restores. */
4279 /* Adjust the register to index off of. */
4280 if (frame_pointer_needed)
4281 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
4283 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4285 /* Actually do the restores now. */
4286 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4287 if (df_regs_ever_live_p (i)
4288 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4290 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4291 rtx dest = gen_rtx_REG (DFmode, i);
4292 emit_move_insn (dest, src);
4296 /* Emit a blockage insn here to keep these insns from being moved to
4297 an earlier spot in the epilogue, or into the main instruction stream.
4299 This is necessary as we must not cut the stack back before all the
4300 restores are finished. */
4301 emit_insn (gen_blockage ());
4303 /* Reset stack pointer (and possibly frame pointer). The stack
4304 pointer is initially set to fp + 64 to avoid a race condition. */
4305 if (frame_pointer_needed)
4307 rtx delta = GEN_INT (-64);
4309 set_reg_plus_d (STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM, 64, 0);
4310 emit_insn (gen_pre_load (hard_frame_pointer_rtx,
4311 stack_pointer_rtx, delta));
4313 /* If we were deferring a callee register restore, do it now. */
4314 else if (merge_sp_adjust_with_load)
4316 rtx delta = GEN_INT (-actual_fsize);
4317 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4319 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4321 else if (actual_fsize != 0)
4322 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4325 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4326 frame greater than 8k), do so now. */
4328 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4330 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4332 rtx sa = EH_RETURN_STACKADJ_RTX;
4334 emit_insn (gen_blockage ());
4335 emit_insn (TARGET_64BIT
4336 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4337 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4342 pa_can_use_return_insn (void)
4344 if (!reload_completed)
4347 if (frame_pointer_needed)
4350 if (df_regs_ever_live_p (2))
4356 return compute_frame_size (get_frame_size (), 0) == 0;
4360 hppa_pic_save_rtx (void)
4362 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4365 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4366 #define NO_DEFERRED_PROFILE_COUNTERS 0
4370 /* Vector of funcdef numbers. */
4371 static VEC(int,heap) *funcdef_nos;
4373 /* Output deferred profile counters. */
4375 output_deferred_profile_counters (void)
4380 if (VEC_empty (int, funcdef_nos))
4383 switch_to_section (data_section);
4384 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4385 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4387 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4389 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4390 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4393 VEC_free (int, heap, funcdef_nos);
4397 hppa_profile_hook (int label_no)
4399 /* We use SImode for the address of the function in both 32 and
4400 64-bit code to avoid having to provide DImode versions of the
4401 lcla2 and load_offset_label_address insn patterns. */
4402 rtx reg = gen_reg_rtx (SImode);
4403 rtx label_rtx = gen_label_rtx ();
4404 rtx begin_label_rtx, call_insn;
4405 char begin_label_name[16];
4407 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4409 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4412 emit_move_insn (arg_pointer_rtx,
4413 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4416 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4418 /* The address of the function is loaded into %r25 with an instruction-
4419 relative sequence that avoids the use of relocations. The sequence
4420 is split so that the load_offset_label_address instruction can
4421 occupy the delay slot of the call to _mcount. */
4423 emit_insn (gen_lcla2 (reg, label_rtx));
4425 emit_insn (gen_lcla1 (reg, label_rtx));
4427 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4428 reg, begin_label_rtx, label_rtx));
4430 #if !NO_DEFERRED_PROFILE_COUNTERS
4432 rtx count_label_rtx, addr, r24;
4433 char count_label_name[16];
4435 VEC_safe_push (int, heap, funcdef_nos, label_no);
4436 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4437 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4439 addr = force_reg (Pmode, count_label_rtx);
4440 r24 = gen_rtx_REG (Pmode, 24);
4441 emit_move_insn (r24, addr);
4444 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4445 gen_rtx_SYMBOL_REF (Pmode,
4447 GEN_INT (TARGET_64BIT ? 24 : 12)));
4449 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4454 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4455 gen_rtx_SYMBOL_REF (Pmode,
4457 GEN_INT (TARGET_64BIT ? 16 : 8)));
4461 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4462 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4464 /* Indicate the _mcount call cannot throw, nor will it execute a
4466 make_reg_eh_region_note_nothrow_nononlocal (call_insn);
4469 /* Fetch the return address for the frame COUNT steps up from
4470 the current frame, after the prologue. FRAMEADDR is the
4471 frame pointer of the COUNT frame.
4473 We want to ignore any export stub remnants here. To handle this,
4474 we examine the code at the return address, and if it is an export
4475 stub, we return a memory rtx for the stub return address stored
4478 The value returned is used in two different ways:
4480 1. To find a function's caller.
4482 2. To change the return address for a function.
4484 This function handles most instances of case 1; however, it will
4485 fail if there are two levels of stubs to execute on the return
4486 path. The only way I believe that can happen is if the return value
4487 needs a parameter relocation, which never happens for C code.
4489 This function handles most instances of case 2; however, it will
4490 fail if we did not originally have stub code on the return path
4491 but will need stub code on the new return path. This can happen if
4492 the caller & callee are both in the main program, but the new
4493 return location is in a shared library. */
4496 pa_return_addr_rtx (int count, rtx frameaddr)
4503 /* The instruction stream at the return address of a PA1.X export stub is:
4505 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4506 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4507 0x00011820 | stub+16: mtsp r1,sr0
4508 0xe0400002 | stub+20: be,n 0(sr0,rp)
4510 0xe0400002 must be specified as -532676606 so that it won't be
4511 rejected as an invalid immediate operand on 64-bit hosts.
4513 The instruction stream at the return address of a PA2.0 export stub is:
4515 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4516 0xe840d002 | stub+12: bve,n (rp)
4519 HOST_WIDE_INT insns[4];
4525 rp = get_hard_reg_initial_val (Pmode, 2);
4527 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4530 /* If there is no export stub then just use the value saved from
4531 the return pointer register. */
4533 saved_rp = gen_reg_rtx (Pmode);
4534 emit_move_insn (saved_rp, rp);
4536 /* Get pointer to the instruction stream. We have to mask out the
4537 privilege level from the two low order bits of the return address
4538 pointer here so that ins will point to the start of the first
4539 instruction that would have been executed if we returned. */
4540 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4541 label = gen_label_rtx ();
4545 insns[0] = 0x4bc23fd1;
4546 insns[1] = -398405630;
4551 insns[0] = 0x4bc23fd1;
4552 insns[1] = 0x004010a1;
4553 insns[2] = 0x00011820;
4554 insns[3] = -532676606;
4558 /* Check the instruction stream at the normal return address for the
4559 export stub. If it is an export stub, than our return address is
4560 really in -24[frameaddr]. */
4562 for (i = 0; i < len; i++)
4564 rtx op0 = gen_rtx_MEM (SImode, plus_constant (ins, i * 4));
4565 rtx op1 = GEN_INT (insns[i]);
4566 emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label);
4569 /* Here we know that our return address points to an export
4570 stub. We don't want to return the address of the export stub,
4571 but rather the return address of the export stub. That return
4572 address is stored at -24[frameaddr]. */
4574 emit_move_insn (saved_rp,
4576 memory_address (Pmode,
4577 plus_constant (frameaddr,
4586 pa_emit_bcond_fp (rtx operands[])
4588 enum rtx_code code = GET_CODE (operands[0]);
4589 rtx operand0 = operands[1];
4590 rtx operand1 = operands[2];
4591 rtx label = operands[3];
4593 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4594 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)));
4596 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4597 gen_rtx_IF_THEN_ELSE (VOIDmode,
4600 gen_rtx_REG (CCFPmode, 0),
4602 gen_rtx_LABEL_REF (VOIDmode, label),
4607 /* Adjust the cost of a scheduling dependency. Return the new cost of
4608 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4611 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4613 enum attr_type attr_type;
4615 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4616 true dependencies as they are described with bypasses now. */
4617 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4620 if (! recog_memoized (insn))
4623 attr_type = get_attr_type (insn);
4625 switch (REG_NOTE_KIND (link))
4628 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4631 if (attr_type == TYPE_FPLOAD)
4633 rtx pat = PATTERN (insn);
4634 rtx dep_pat = PATTERN (dep_insn);
4635 if (GET_CODE (pat) == PARALLEL)
4637 /* This happens for the fldXs,mb patterns. */
4638 pat = XVECEXP (pat, 0, 0);
4640 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4641 /* If this happens, we have to extend this to schedule
4642 optimally. Return 0 for now. */
4645 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4647 if (! recog_memoized (dep_insn))
4649 switch (get_attr_type (dep_insn))
4656 case TYPE_FPSQRTSGL:
4657 case TYPE_FPSQRTDBL:
4658 /* A fpload can't be issued until one cycle before a
4659 preceding arithmetic operation has finished if
4660 the target of the fpload is any of the sources
4661 (or destination) of the arithmetic operation. */
4662 return insn_default_latency (dep_insn) - 1;
4669 else if (attr_type == TYPE_FPALU)
4671 rtx pat = PATTERN (insn);
4672 rtx dep_pat = PATTERN (dep_insn);
4673 if (GET_CODE (pat) == PARALLEL)
4675 /* This happens for the fldXs,mb patterns. */
4676 pat = XVECEXP (pat, 0, 0);
4678 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4679 /* If this happens, we have to extend this to schedule
4680 optimally. Return 0 for now. */
4683 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4685 if (! recog_memoized (dep_insn))
4687 switch (get_attr_type (dep_insn))
4691 case TYPE_FPSQRTSGL:
4692 case TYPE_FPSQRTDBL:
4693 /* An ALU flop can't be issued until two cycles before a
4694 preceding divide or sqrt operation has finished if
4695 the target of the ALU flop is any of the sources
4696 (or destination) of the divide or sqrt operation. */
4697 return insn_default_latency (dep_insn) - 2;
4705 /* For other anti dependencies, the cost is 0. */
4708 case REG_DEP_OUTPUT:
4709 /* Output dependency; DEP_INSN writes a register that INSN writes some
4711 if (attr_type == TYPE_FPLOAD)
4713 rtx pat = PATTERN (insn);
4714 rtx dep_pat = PATTERN (dep_insn);
4715 if (GET_CODE (pat) == PARALLEL)
4717 /* This happens for the fldXs,mb patterns. */
4718 pat = XVECEXP (pat, 0, 0);
4720 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4721 /* If this happens, we have to extend this to schedule
4722 optimally. Return 0 for now. */
4725 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4727 if (! recog_memoized (dep_insn))
4729 switch (get_attr_type (dep_insn))
4736 case TYPE_FPSQRTSGL:
4737 case TYPE_FPSQRTDBL:
4738 /* A fpload can't be issued until one cycle before a
4739 preceding arithmetic operation has finished if
4740 the target of the fpload is the destination of the
4741 arithmetic operation.
4743 Exception: For PA7100LC, PA7200 and PA7300, the cost
4744 is 3 cycles, unless they bundle together. We also
4745 pay the penalty if the second insn is a fpload. */
4746 return insn_default_latency (dep_insn) - 1;
4753 else if (attr_type == TYPE_FPALU)
4755 rtx pat = PATTERN (insn);
4756 rtx dep_pat = PATTERN (dep_insn);
4757 if (GET_CODE (pat) == PARALLEL)
4759 /* This happens for the fldXs,mb patterns. */
4760 pat = XVECEXP (pat, 0, 0);
4762 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4763 /* If this happens, we have to extend this to schedule
4764 optimally. Return 0 for now. */
4767 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4769 if (! recog_memoized (dep_insn))
4771 switch (get_attr_type (dep_insn))
4775 case TYPE_FPSQRTSGL:
4776 case TYPE_FPSQRTDBL:
4777 /* An ALU flop can't be issued until two cycles before a
4778 preceding divide or sqrt operation has finished if
4779 the target of the ALU flop is also the target of
4780 the divide or sqrt operation. */
4781 return insn_default_latency (dep_insn) - 2;
4789 /* For other output dependencies, the cost is 0. */
4797 /* Adjust scheduling priorities. We use this to try and keep addil
4798 and the next use of %r1 close together. */
4800 pa_adjust_priority (rtx insn, int priority)
4802 rtx set = single_set (insn);
4806 src = SET_SRC (set);
4807 dest = SET_DEST (set);
4808 if (GET_CODE (src) == LO_SUM
4809 && symbolic_operand (XEXP (src, 1), VOIDmode)
4810 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4813 else if (GET_CODE (src) == MEM
4814 && GET_CODE (XEXP (src, 0)) == LO_SUM
4815 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4816 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4819 else if (GET_CODE (dest) == MEM
4820 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4821 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4822 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4828 /* The 700 can only issue a single insn at a time.
4829 The 7XXX processors can issue two insns at a time.
4830 The 8000 can issue 4 insns at a time. */
4832 pa_issue_rate (void)
4836 case PROCESSOR_700: return 1;
4837 case PROCESSOR_7100: return 2;
4838 case PROCESSOR_7100LC: return 2;
4839 case PROCESSOR_7200: return 2;
4840 case PROCESSOR_7300: return 2;
4841 case PROCESSOR_8000: return 4;
4850 /* Return any length adjustment needed by INSN which already has its length
4851 computed as LENGTH. Return zero if no adjustment is necessary.
4853 For the PA: function calls, millicode calls, and backwards short
4854 conditional branches with unfilled delay slots need an adjustment by +1
4855 (to account for the NOP which will be inserted into the instruction stream).
4857 Also compute the length of an inline block move here as it is too
4858 complicated to express as a length attribute in pa.md. */
4860 pa_adjust_insn_length (rtx insn, int length)
4862 rtx pat = PATTERN (insn);
4864 /* Jumps inside switch tables which have unfilled delay slots need
4866 if (GET_CODE (insn) == JUMP_INSN
4867 && GET_CODE (pat) == PARALLEL
4868 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4870 /* Millicode insn with an unfilled delay slot. */
4871 else if (GET_CODE (insn) == INSN
4872 && GET_CODE (pat) != SEQUENCE
4873 && GET_CODE (pat) != USE
4874 && GET_CODE (pat) != CLOBBER
4875 && get_attr_type (insn) == TYPE_MILLI)
4877 /* Block move pattern. */
4878 else if (GET_CODE (insn) == INSN
4879 && GET_CODE (pat) == PARALLEL
4880 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4881 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4882 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4883 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4884 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4885 return compute_movmem_length (insn) - 4;
4886 /* Block clear pattern. */
4887 else if (GET_CODE (insn) == INSN
4888 && GET_CODE (pat) == PARALLEL
4889 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4890 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4891 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4892 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4893 return compute_clrmem_length (insn) - 4;
4894 /* Conditional branch with an unfilled delay slot. */
4895 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4897 /* Adjust a short backwards conditional with an unfilled delay slot. */
4898 if (GET_CODE (pat) == SET
4900 && JUMP_LABEL (insn) != NULL_RTX
4901 && ! forward_branch_p (insn))
4903 else if (GET_CODE (pat) == PARALLEL
4904 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4907 /* Adjust dbra insn with short backwards conditional branch with
4908 unfilled delay slot -- only for case where counter is in a
4909 general register register. */
4910 else if (GET_CODE (pat) == PARALLEL
4911 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4912 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4913 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4915 && ! forward_branch_p (insn))
4923 /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */
4926 pa_print_operand_punct_valid_p (unsigned char code)
4937 /* Print operand X (an rtx) in assembler syntax to file FILE.
4938 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4939 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4942 pa_print_operand (FILE *file, rtx x, int code)
4947 /* Output a 'nop' if there's nothing for the delay slot. */
4948 if (dbr_sequence_length () == 0)
4949 fputs ("\n\tnop", file);
4952 /* Output a nullification completer if there's nothing for the */
4953 /* delay slot or nullification is requested. */
4954 if (dbr_sequence_length () == 0 ||
4956 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4960 /* Print out the second register name of a register pair.
4961 I.e., R (6) => 7. */
4962 fputs (reg_names[REGNO (x) + 1], file);
4965 /* A register or zero. */
4967 || (x == CONST0_RTX (DFmode))
4968 || (x == CONST0_RTX (SFmode)))
4970 fputs ("%r0", file);
4976 /* A register or zero (floating point). */
4978 || (x == CONST0_RTX (DFmode))
4979 || (x == CONST0_RTX (SFmode)))
4981 fputs ("%fr0", file);
4990 xoperands[0] = XEXP (XEXP (x, 0), 0);
4991 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4992 pa_output_global_address (file, xoperands[1], 0);
4993 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4997 case 'C': /* Plain (C)ondition */
4999 switch (GET_CODE (x))
5002 fputs ("=", file); break;
5004 fputs ("<>", file); break;
5006 fputs (">", file); break;
5008 fputs (">=", file); break;
5010 fputs (">>=", file); break;
5012 fputs (">>", file); break;
5014 fputs ("<", file); break;
5016 fputs ("<=", file); break;
5018 fputs ("<<=", file); break;
5020 fputs ("<<", file); break;
5025 case 'N': /* Condition, (N)egated */
5026 switch (GET_CODE (x))
5029 fputs ("<>", file); break;
5031 fputs ("=", file); break;
5033 fputs ("<=", file); break;
5035 fputs ("<", file); break;
5037 fputs ("<<", file); break;
5039 fputs ("<<=", file); break;
5041 fputs (">=", file); break;
5043 fputs (">", file); break;
5045 fputs (">>", file); break;
5047 fputs (">>=", file); break;
5052 /* For floating point comparisons. Note that the output
5053 predicates are the complement of the desired mode. The
5054 conditions for GT, GE, LT, LE and LTGT cause an invalid
5055 operation exception if the result is unordered and this
5056 exception is enabled in the floating-point status register. */
5058 switch (GET_CODE (x))
5061 fputs ("!=", file); break;
5063 fputs ("=", file); break;
5065 fputs ("!>", file); break;
5067 fputs ("!>=", file); break;
5069 fputs ("!<", file); break;
5071 fputs ("!<=", file); break;
5073 fputs ("!<>", file); break;
5075 fputs ("!?<=", file); break;
5077 fputs ("!?<", file); break;
5079 fputs ("!?>=", file); break;
5081 fputs ("!?>", file); break;
5083 fputs ("!?=", file); break;
5085 fputs ("!?", file); break;
5087 fputs ("?", file); break;
5092 case 'S': /* Condition, operands are (S)wapped. */
5093 switch (GET_CODE (x))
5096 fputs ("=", file); break;
5098 fputs ("<>", file); break;
5100 fputs ("<", file); break;
5102 fputs ("<=", file); break;
5104 fputs ("<<=", file); break;
5106 fputs ("<<", file); break;
5108 fputs (">", file); break;
5110 fputs (">=", file); break;
5112 fputs (">>=", file); break;
5114 fputs (">>", file); break;
5119 case 'B': /* Condition, (B)oth swapped and negate. */
5120 switch (GET_CODE (x))
5123 fputs ("<>", file); break;
5125 fputs ("=", file); break;
5127 fputs (">=", file); break;
5129 fputs (">", file); break;
5131 fputs (">>", file); break;
5133 fputs (">>=", file); break;
5135 fputs ("<=", file); break;
5137 fputs ("<", file); break;
5139 fputs ("<<", file); break;
5141 fputs ("<<=", file); break;
5147 gcc_assert (GET_CODE (x) == CONST_INT);
5148 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5151 gcc_assert (GET_CODE (x) == CONST_INT);
5152 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5155 gcc_assert (GET_CODE (x) == CONST_INT);
5156 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5159 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
5160 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5163 gcc_assert (GET_CODE (x) == CONST_INT);
5164 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5167 gcc_assert (GET_CODE (x) == CONST_INT);
5168 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5171 if (GET_CODE (x) == CONST_INT)
5176 switch (GET_CODE (XEXP (x, 0)))
5180 if (ASSEMBLER_DIALECT == 0)
5181 fputs ("s,mb", file);
5183 fputs (",mb", file);
5187 if (ASSEMBLER_DIALECT == 0)
5188 fputs ("s,ma", file);
5190 fputs (",ma", file);
5193 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5194 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5196 if (ASSEMBLER_DIALECT == 0)
5199 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5200 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5202 if (ASSEMBLER_DIALECT == 0)
5203 fputs ("x,s", file);
5207 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5211 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5217 pa_output_global_address (file, x, 0);
5220 pa_output_global_address (file, x, 1);
5222 case 0: /* Don't do anything special */
5227 compute_zdepwi_operands (INTVAL (x), op);
5228 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5234 compute_zdepdi_operands (INTVAL (x), op);
5235 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5239 /* We can get here from a .vtable_inherit due to our
5240 CONSTANT_ADDRESS_P rejecting perfectly good constant
5246 if (GET_CODE (x) == REG)
5248 fputs (reg_names [REGNO (x)], file);
5249 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5255 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5256 && (REGNO (x) & 1) == 0)
5259 else if (GET_CODE (x) == MEM)
5261 int size = GET_MODE_SIZE (GET_MODE (x));
5262 rtx base = NULL_RTX;
5263 switch (GET_CODE (XEXP (x, 0)))
5267 base = XEXP (XEXP (x, 0), 0);
5268 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5272 base = XEXP (XEXP (x, 0), 0);
5273 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5276 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5277 fprintf (file, "%s(%s)",
5278 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5279 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5280 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5281 fprintf (file, "%s(%s)",
5282 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5283 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5284 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5285 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5287 /* Because the REG_POINTER flag can get lost during reload,
5288 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5289 index and base registers in the combined move patterns. */
5290 rtx base = XEXP (XEXP (x, 0), 1);
5291 rtx index = XEXP (XEXP (x, 0), 0);
5293 fprintf (file, "%s(%s)",
5294 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5297 output_address (XEXP (x, 0));
5300 output_address (XEXP (x, 0));
5305 output_addr_const (file, x);
5308 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5311 pa_output_global_address (FILE *file, rtx x, int round_constant)
5314 /* Imagine (high (const (plus ...))). */
5315 if (GET_CODE (x) == HIGH)
5318 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5319 output_addr_const (file, x);
5320 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5322 output_addr_const (file, x);
5323 fputs ("-$global$", file);
5325 else if (GET_CODE (x) == CONST)
5327 const char *sep = "";
5328 int offset = 0; /* assembler wants -$global$ at end */
5329 rtx base = NULL_RTX;
5331 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5334 base = XEXP (XEXP (x, 0), 0);
5335 output_addr_const (file, base);
5338 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5344 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5347 base = XEXP (XEXP (x, 0), 1);
5348 output_addr_const (file, base);
5351 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5357 /* How bogus. The compiler is apparently responsible for
5358 rounding the constant if it uses an LR field selector.
5360 The linker and/or assembler seem a better place since
5361 they have to do this kind of thing already.
5363 If we fail to do this, HP's optimizing linker may eliminate
5364 an addil, but not update the ldw/stw/ldo instruction that
5365 uses the result of the addil. */
5367 offset = ((offset + 0x1000) & ~0x1fff);
5369 switch (GET_CODE (XEXP (x, 0)))
5382 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5390 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5391 fputs ("-$global$", file);
5393 fprintf (file, "%s%d", sep, offset);
5396 output_addr_const (file, x);
5399 /* Output boilerplate text to appear at the beginning of the file.
5400 There are several possible versions. */
5401 #define aputs(x) fputs(x, asm_out_file)
5403 pa_file_start_level (void)
5406 aputs ("\t.LEVEL 2.0w\n");
5407 else if (TARGET_PA_20)
5408 aputs ("\t.LEVEL 2.0\n");
5409 else if (TARGET_PA_11)
5410 aputs ("\t.LEVEL 1.1\n");
5412 aputs ("\t.LEVEL 1.0\n");
5416 pa_file_start_space (int sortspace)
5418 aputs ("\t.SPACE $PRIVATE$");
5421 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31");
5423 aputs ("\n\t.SUBSPA $TM_CLONE_TABLE$,QUAD=1,ALIGN=8,ACCESS=31");
5424 aputs ("\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5425 "\n\t.SPACE $TEXT$");
5428 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5429 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5433 pa_file_start_file (int want_version)
5435 if (write_symbols != NO_DEBUG)
5437 output_file_directive (asm_out_file, main_input_filename);
5439 aputs ("\t.version\t\"01.01\"\n");
5444 pa_file_start_mcount (const char *aswhat)
5447 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5451 pa_elf_file_start (void)
5453 pa_file_start_level ();
5454 pa_file_start_mcount ("ENTRY");
5455 pa_file_start_file (0);
5459 pa_som_file_start (void)
5461 pa_file_start_level ();
5462 pa_file_start_space (0);
5463 aputs ("\t.IMPORT $global$,DATA\n"
5464 "\t.IMPORT $$dyncall,MILLICODE\n");
5465 pa_file_start_mcount ("CODE");
5466 pa_file_start_file (0);
5470 pa_linux_file_start (void)
5472 pa_file_start_file (1);
5473 pa_file_start_level ();
5474 pa_file_start_mcount ("CODE");
5478 pa_hpux64_gas_file_start (void)
5480 pa_file_start_level ();
5481 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5483 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5485 pa_file_start_file (1);
5489 pa_hpux64_hpas_file_start (void)
5491 pa_file_start_level ();
5492 pa_file_start_space (1);
5493 pa_file_start_mcount ("CODE");
5494 pa_file_start_file (0);
5498 /* Search the deferred plabel list for SYMBOL and return its internal
5499 label. If an entry for SYMBOL is not found, a new entry is created. */
5502 pa_get_deferred_plabel (rtx symbol)
5504 const char *fname = XSTR (symbol, 0);
5507 /* See if we have already put this function on the list of deferred
5508 plabels. This list is generally small, so a liner search is not
5509 too ugly. If it proves too slow replace it with something faster. */
5510 for (i = 0; i < n_deferred_plabels; i++)
5511 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5514 /* If the deferred plabel list is empty, or this entry was not found
5515 on the list, create a new entry on the list. */
5516 if (deferred_plabels == NULL || i == n_deferred_plabels)
5520 if (deferred_plabels == 0)
5521 deferred_plabels = ggc_alloc_deferred_plabel ();
5523 deferred_plabels = GGC_RESIZEVEC (struct deferred_plabel,
5525 n_deferred_plabels + 1);
5527 i = n_deferred_plabels++;
5528 deferred_plabels[i].internal_label = gen_label_rtx ();
5529 deferred_plabels[i].symbol = symbol;
5531 /* Gross. We have just implicitly taken the address of this
5532 function. Mark it in the same manner as assemble_name. */
5533 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5535 mark_referenced (id);
5538 return deferred_plabels[i].internal_label;
5542 output_deferred_plabels (void)
5546 /* If we have some deferred plabels, then we need to switch into the
5547 data or readonly data section, and align it to a 4 byte boundary
5548 before outputting the deferred plabels. */
5549 if (n_deferred_plabels)
5551 switch_to_section (flag_pic ? data_section : readonly_data_section);
5552 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5555 /* Now output the deferred plabels. */
5556 for (i = 0; i < n_deferred_plabels; i++)
5558 targetm.asm_out.internal_label (asm_out_file, "L",
5559 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5560 assemble_integer (deferred_plabels[i].symbol,
5561 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5565 /* Initialize optabs to point to emulation routines. */
5568 pa_init_libfuncs (void)
5570 if (HPUX_LONG_DOUBLE_LIBRARY)
5572 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5573 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5574 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5575 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5576 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5577 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5578 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5579 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5580 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5582 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5583 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5584 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5585 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5586 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5587 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5588 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5590 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5591 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5592 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5593 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5595 set_conv_libfunc (sfix_optab, SImode, TFmode,
5596 TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl"
5597 : "_U_Qfcnvfxt_quad_to_sgl");
5598 set_conv_libfunc (sfix_optab, DImode, TFmode,
5599 "_U_Qfcnvfxt_quad_to_dbl");
5600 set_conv_libfunc (ufix_optab, SImode, TFmode,
5601 "_U_Qfcnvfxt_quad_to_usgl");
5602 set_conv_libfunc (ufix_optab, DImode, TFmode,
5603 "_U_Qfcnvfxt_quad_to_udbl");
5605 set_conv_libfunc (sfloat_optab, TFmode, SImode,
5606 "_U_Qfcnvxf_sgl_to_quad");
5607 set_conv_libfunc (sfloat_optab, TFmode, DImode,
5608 "_U_Qfcnvxf_dbl_to_quad");
5609 set_conv_libfunc (ufloat_optab, TFmode, SImode,
5610 "_U_Qfcnvxf_usgl_to_quad");
5611 set_conv_libfunc (ufloat_optab, TFmode, DImode,
5612 "_U_Qfcnvxf_udbl_to_quad");
5615 if (TARGET_SYNC_LIBCALL)
5616 init_sync_libfuncs (UNITS_PER_WORD);
5619 /* HP's millicode routines mean something special to the assembler.
5620 Keep track of which ones we have used. */
5622 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5623 static void import_milli (enum millicodes);
5624 static char imported[(int) end1000];
5625 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5626 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5627 #define MILLI_START 10
5630 import_milli (enum millicodes code)
5632 char str[sizeof (import_string)];
5634 if (!imported[(int) code])
5636 imported[(int) code] = 1;
5637 strcpy (str, import_string);
5638 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5639 output_asm_insn (str, 0);
5643 /* The register constraints have put the operands and return value in
5644 the proper registers. */
5647 pa_output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5649 import_milli (mulI);
5650 return pa_output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5653 /* Emit the rtl for doing a division by a constant. */
5655 /* Do magic division millicodes exist for this value? */
5656 const int pa_magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5658 /* We'll use an array to keep track of the magic millicodes and
5659 whether or not we've used them already. [n][0] is signed, [n][1] is
5662 static int div_milli[16][2];
5665 pa_emit_hpdiv_const (rtx *operands, int unsignedp)
5667 if (GET_CODE (operands[2]) == CONST_INT
5668 && INTVAL (operands[2]) > 0
5669 && INTVAL (operands[2]) < 16
5670 && pa_magic_milli[INTVAL (operands[2])])
5672 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5674 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5678 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5679 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5681 gen_rtx_REG (SImode, 26),
5683 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5684 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5685 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5686 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5687 gen_rtx_CLOBBER (VOIDmode, ret))));
5688 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5695 pa_output_div_insn (rtx *operands, int unsignedp, rtx insn)
5699 /* If the divisor is a constant, try to use one of the special
5701 if (GET_CODE (operands[0]) == CONST_INT)
5703 static char buf[100];
5704 divisor = INTVAL (operands[0]);
5705 if (!div_milli[divisor][unsignedp])
5707 div_milli[divisor][unsignedp] = 1;
5709 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5711 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5715 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5716 INTVAL (operands[0]));
5717 return pa_output_millicode_call (insn,
5718 gen_rtx_SYMBOL_REF (SImode, buf));
5722 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5723 INTVAL (operands[0]));
5724 return pa_output_millicode_call (insn,
5725 gen_rtx_SYMBOL_REF (SImode, buf));
5728 /* Divisor isn't a special constant. */
5733 import_milli (divU);
5734 return pa_output_millicode_call (insn,
5735 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5739 import_milli (divI);
5740 return pa_output_millicode_call (insn,
5741 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5746 /* Output a $$rem millicode to do mod. */
5749 pa_output_mod_insn (int unsignedp, rtx insn)
5753 import_milli (remU);
5754 return pa_output_millicode_call (insn,
5755 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5759 import_milli (remI);
5760 return pa_output_millicode_call (insn,
5761 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5766 pa_output_arg_descriptor (rtx call_insn)
5768 const char *arg_regs[4];
5769 enum machine_mode arg_mode;
5771 int i, output_flag = 0;
5774 /* We neither need nor want argument location descriptors for the
5775 64bit runtime environment or the ELF32 environment. */
5776 if (TARGET_64BIT || TARGET_ELF32)
5779 for (i = 0; i < 4; i++)
5782 /* Specify explicitly that no argument relocations should take place
5783 if using the portable runtime calling conventions. */
5784 if (TARGET_PORTABLE_RUNTIME)
5786 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5791 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5792 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5793 link; link = XEXP (link, 1))
5795 rtx use = XEXP (link, 0);
5797 if (! (GET_CODE (use) == USE
5798 && GET_CODE (XEXP (use, 0)) == REG
5799 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5802 arg_mode = GET_MODE (XEXP (use, 0));
5803 regno = REGNO (XEXP (use, 0));
5804 if (regno >= 23 && regno <= 26)
5806 arg_regs[26 - regno] = "GR";
5807 if (arg_mode == DImode)
5808 arg_regs[25 - regno] = "GR";
5810 else if (regno >= 32 && regno <= 39)
5812 if (arg_mode == SFmode)
5813 arg_regs[(regno - 32) / 2] = "FR";
5816 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5817 arg_regs[(regno - 34) / 2] = "FR";
5818 arg_regs[(regno - 34) / 2 + 1] = "FU";
5820 arg_regs[(regno - 34) / 2] = "FU";
5821 arg_regs[(regno - 34) / 2 + 1] = "FR";
5826 fputs ("\t.CALL ", asm_out_file);
5827 for (i = 0; i < 4; i++)
5832 fputc (',', asm_out_file);
5833 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5836 fputc ('\n', asm_out_file);
5839 /* Inform reload about cases where moving X with a mode MODE to a register in
5840 RCLASS requires an extra scratch or immediate register. Return the class
5841 needed for the immediate register. */
5844 pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
5845 enum machine_mode mode, secondary_reload_info *sri)
5848 enum reg_class rclass = (enum reg_class) rclass_i;
5850 /* Handle the easy stuff first. */
5851 if (rclass == R1_REGS)
5857 if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5863 /* If we have something like (mem (mem (...)), we can safely assume the
5864 inner MEM will end up in a general register after reloading, so there's
5865 no need for a secondary reload. */
5866 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5869 /* Trying to load a constant into a FP register during PIC code
5870 generation requires %r1 as a scratch register. */
5872 && (mode == SImode || mode == DImode)
5873 && FP_REG_CLASS_P (rclass)
5874 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5876 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5877 : CODE_FOR_reload_indi_r1);
5881 /* Secondary reloads of symbolic operands require %r1 as a scratch
5882 register when we're generating PIC code and when the operand isn't
5884 if (pa_symbolic_expression_p (x))
5886 if (GET_CODE (x) == HIGH)
5889 if (flag_pic || !read_only_operand (x, VOIDmode))
5891 gcc_assert (mode == SImode || mode == DImode);
5892 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5893 : CODE_FOR_reload_indi_r1);
5898 /* Profiling showed the PA port spends about 1.3% of its compilation
5899 time in true_regnum from calls inside pa_secondary_reload_class. */
5900 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5901 regno = true_regnum (x);
5903 /* In order to allow 14-bit displacements in integer loads and stores,
5904 we need to prevent reload from generating out of range integer mode
5905 loads and stores to the floating point registers. Previously, we
5906 used to call for a secondary reload and have pa_emit_move_sequence()
5907 fix the instruction sequence. However, reload occasionally wouldn't
5908 generate the reload and we would end up with an invalid REG+D memory
5909 address. So, now we use an intermediate general register for most
5910 memory loads and stores. */
5911 if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5912 && GET_MODE_CLASS (mode) == MODE_INT
5913 && FP_REG_CLASS_P (rclass))
5915 /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check
5916 the secondary reload needed for a pseudo. It never passes a
5918 if (GET_CODE (x) == MEM)
5922 /* We don't need an intermediate for indexed and LO_SUM DLT
5923 memory addresses. When INT14_OK_STRICT is true, it might
5924 appear that we could directly allow register indirect
5925 memory addresses. However, this doesn't work because we
5926 don't support SUBREGs in floating-point register copies
5927 and reload doesn't tell us when it's going to use a SUBREG. */
5928 if (IS_INDEX_ADDR_P (x)
5929 || IS_LO_SUM_DLT_ADDR_P (x))
5932 /* Otherwise, we need an intermediate general register. */
5933 return GENERAL_REGS;
5936 /* Request a secondary reload with a general scratch register
5937 for everthing else. ??? Could symbolic operands be handled
5938 directly when generating non-pic PA 2.0 code? */
5940 ? direct_optab_handler (reload_in_optab, mode)
5941 : direct_optab_handler (reload_out_optab, mode));
5945 /* A SAR<->FP register copy requires an intermediate general register
5946 and secondary memory. We need a secondary reload with a general
5947 scratch register for spills. */
5948 if (rclass == SHIFT_REGS)
5951 if (regno >= FIRST_PSEUDO_REGISTER || regno < 0)
5954 ? direct_optab_handler (reload_in_optab, mode)
5955 : direct_optab_handler (reload_out_optab, mode));
5959 /* Handle FP copy. */
5960 if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))
5961 return GENERAL_REGS;
5964 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5965 && REGNO_REG_CLASS (regno) == SHIFT_REGS
5966 && FP_REG_CLASS_P (rclass))
5967 return GENERAL_REGS;
5972 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
5973 is only marked as live on entry by df-scan when it is a fixed
5974 register. It isn't a fixed register in the 64-bit runtime,
5975 so we need to mark it here. */
5978 pa_extra_live_on_entry (bitmap regs)
5981 bitmap_set_bit (regs, ARG_POINTER_REGNUM);
5984 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
5985 to prevent it from being deleted. */
5988 pa_eh_return_handler_rtx (void)
5992 tmp = gen_rtx_PLUS (word_mode, hard_frame_pointer_rtx,
5993 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20));
5994 tmp = gen_rtx_MEM (word_mode, tmp);
5999 /* In the 32-bit runtime, arguments larger than eight bytes are passed
6000 by invisible reference. As a GCC extension, we also pass anything
6001 with a zero or variable size by reference.
6003 The 64-bit runtime does not describe passing any types by invisible
6004 reference. The internals of GCC can't currently handle passing
6005 empty structures, and zero or variable length arrays when they are
6006 not passed entirely on the stack or by reference. Thus, as a GCC
6007 extension, we pass these types by reference. The HP compiler doesn't
6008 support these types, so hopefully there shouldn't be any compatibility
6009 issues. This may have to be revisited when HP releases a C99 compiler
6010 or updates the ABI. */
6013 pa_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
6014 enum machine_mode mode, const_tree type,
6015 bool named ATTRIBUTE_UNUSED)
6020 size = int_size_in_bytes (type);
6022 size = GET_MODE_SIZE (mode);
6027 return size <= 0 || size > 8;
6031 pa_function_arg_padding (enum machine_mode mode, const_tree type)
6036 && (AGGREGATE_TYPE_P (type)
6037 || TREE_CODE (type) == COMPLEX_TYPE
6038 || TREE_CODE (type) == VECTOR_TYPE)))
6040 /* Return none if justification is not required. */
6042 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
6043 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
6046 /* The directions set here are ignored when a BLKmode argument larger
6047 than a word is placed in a register. Different code is used for
6048 the stack and registers. This makes it difficult to have a
6049 consistent data representation for both the stack and registers.
6050 For both runtimes, the justification and padding for arguments on
6051 the stack and in registers should be identical. */
6053 /* The 64-bit runtime specifies left justification for aggregates. */
6056 /* The 32-bit runtime architecture specifies right justification.
6057 When the argument is passed on the stack, the argument is padded
6058 with garbage on the left. The HP compiler pads with zeros. */
6062 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6069 /* Do what is necessary for `va_start'. We look at the current function
6070 to determine if stdargs or varargs is used and fill in an initial
6071 va_list. A pointer to this constructor is returned. */
6074 hppa_builtin_saveregs (void)
6077 tree fntype = TREE_TYPE (current_function_decl);
6078 int argadj = ((!stdarg_p (fntype))
6079 ? UNITS_PER_WORD : 0);
6082 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
6084 offset = crtl->args.arg_offset_rtx;
6090 /* Adjust for varargs/stdarg differences. */
6092 offset = plus_constant (crtl->args.arg_offset_rtx, -argadj);
6094 offset = crtl->args.arg_offset_rtx;
6096 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6097 from the incoming arg pointer and growing to larger addresses. */
6098 for (i = 26, off = -64; i >= 19; i--, off += 8)
6099 emit_move_insn (gen_rtx_MEM (word_mode,
6100 plus_constant (arg_pointer_rtx, off)),
6101 gen_rtx_REG (word_mode, i));
6103 /* The incoming args pointer points just beyond the flushback area;
6104 normally this is not a serious concern. However, when we are doing
6105 varargs/stdargs we want to make the arg pointer point to the start
6106 of the incoming argument area. */
6107 emit_move_insn (virtual_incoming_args_rtx,
6108 plus_constant (arg_pointer_rtx, -64));
6110 /* Now return a pointer to the first anonymous argument. */
6111 return copy_to_reg (expand_binop (Pmode, add_optab,
6112 virtual_incoming_args_rtx,
6113 offset, 0, 0, OPTAB_LIB_WIDEN));
6116 /* Store general registers on the stack. */
6117 dest = gen_rtx_MEM (BLKmode,
6118 plus_constant (crtl->args.internal_arg_pointer,
6120 set_mem_alias_set (dest, get_varargs_alias_set ());
6121 set_mem_align (dest, BITS_PER_WORD);
6122 move_block_from_reg (23, dest, 4);
6124 /* move_block_from_reg will emit code to store the argument registers
6125 individually as scalar stores.
6127 However, other insns may later load from the same addresses for
6128 a structure load (passing a struct to a varargs routine).
6130 The alias code assumes that such aliasing can never happen, so we
6131 have to keep memory referencing insns from moving up beyond the
6132 last argument register store. So we emit a blockage insn here. */
6133 emit_insn (gen_blockage ());
6135 return copy_to_reg (expand_binop (Pmode, add_optab,
6136 crtl->args.internal_arg_pointer,
6137 offset, 0, 0, OPTAB_LIB_WIDEN));
6141 hppa_va_start (tree valist, rtx nextarg)
6143 nextarg = expand_builtin_saveregs ();
6144 std_expand_builtin_va_start (valist, nextarg);
6148 hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6153 /* Args grow upward. We can use the generic routines. */
6154 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6156 else /* !TARGET_64BIT */
6158 tree ptr = build_pointer_type (type);
6161 unsigned int size, ofs;
6164 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6168 ptr = build_pointer_type (type);
6170 size = int_size_in_bytes (type);
6171 valist_type = TREE_TYPE (valist);
6173 /* Args grow down. Not handled by generic routines. */
6175 u = fold_convert (sizetype, size_in_bytes (type));
6176 u = fold_build1 (NEGATE_EXPR, sizetype, u);
6177 t = fold_build_pointer_plus (valist, u);
6179 /* Align to 4 or 8 byte boundary depending on argument size. */
6181 u = build_int_cst (TREE_TYPE (t), (HOST_WIDE_INT)(size > 4 ? -8 : -4));
6182 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6183 t = fold_convert (valist_type, t);
6185 t = build2 (MODIFY_EXPR, valist_type, valist, t);
6187 ofs = (8 - size) % 4;
6189 t = fold_build_pointer_plus_hwi (t, ofs);
6191 t = fold_convert (ptr, t);
6192 t = build_va_arg_indirect_ref (t);
6195 t = build_va_arg_indirect_ref (t);
6201 /* True if MODE is valid for the target. By "valid", we mean able to
6202 be manipulated in non-trivial ways. In particular, this means all
6203 the arithmetic is supported.
6205 Currently, TImode is not valid as the HP 64-bit runtime documentation
6206 doesn't document the alignment and calling conventions for this type.
6207 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6208 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6211 pa_scalar_mode_supported_p (enum machine_mode mode)
6213 int precision = GET_MODE_PRECISION (mode);
6215 switch (GET_MODE_CLASS (mode))
6217 case MODE_PARTIAL_INT:
6219 if (precision == CHAR_TYPE_SIZE)
6221 if (precision == SHORT_TYPE_SIZE)
6223 if (precision == INT_TYPE_SIZE)
6225 if (precision == LONG_TYPE_SIZE)
6227 if (precision == LONG_LONG_TYPE_SIZE)
6232 if (precision == FLOAT_TYPE_SIZE)
6234 if (precision == DOUBLE_TYPE_SIZE)
6236 if (precision == LONG_DOUBLE_TYPE_SIZE)
6240 case MODE_DECIMAL_FLOAT:
6248 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
6249 it branches into the delay slot. Otherwise, return FALSE. */
6252 branch_to_delay_slot_p (rtx insn)
6256 if (dbr_sequence_length ())
6259 jump_insn = next_active_insn (JUMP_LABEL (insn));
6262 insn = next_active_insn (insn);
6263 if (jump_insn == insn)
6266 /* We can't rely on the length of asms. So, we return FALSE when
6267 the branch is followed by an asm. */
6269 || GET_CODE (PATTERN (insn)) == ASM_INPUT
6270 || extract_asm_operands (PATTERN (insn)) != NULL_RTX
6271 || get_attr_length (insn) > 0)
6278 /* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot.
6280 This occurs when INSN has an unfilled delay slot and is followed
6281 by an asm. Disaster can occur if the asm is empty and the jump
6282 branches into the delay slot. So, we add a nop in the delay slot
6283 when this occurs. */
6286 branch_needs_nop_p (rtx insn)
6290 if (dbr_sequence_length ())
6293 jump_insn = next_active_insn (JUMP_LABEL (insn));
6296 insn = next_active_insn (insn);
6297 if (!insn || jump_insn == insn)
6300 if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT
6301 || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
6302 && get_attr_length (insn) > 0)
6309 /* Return TRUE if INSN, a forward jump insn, can use nullification
6310 to skip the following instruction. This avoids an extra cycle due
6311 to a mis-predicted branch when we fall through. */
6314 use_skip_p (rtx insn)
6316 rtx jump_insn = next_active_insn (JUMP_LABEL (insn));
6320 insn = next_active_insn (insn);
6322 /* We can't rely on the length of asms, so we can't skip asms. */
6324 || GET_CODE (PATTERN (insn)) == ASM_INPUT
6325 || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
6327 if (get_attr_length (insn) == 4
6328 && jump_insn == next_active_insn (insn))
6330 if (get_attr_length (insn) > 0)
6337 /* This routine handles all the normal conditional branch sequences we
6338 might need to generate. It handles compare immediate vs compare
6339 register, nullification of delay slots, varying length branches,
6340 negated branches, and all combinations of the above. It returns the
6341 output appropriate to emit the branch corresponding to all given
6345 pa_output_cbranch (rtx *operands, int negated, rtx insn)
6347 static char buf[100];
6349 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6350 int length = get_attr_length (insn);
6353 /* A conditional branch to the following instruction (e.g. the delay slot)
6354 is asking for a disaster. This can happen when not optimizing and
6355 when jump optimization fails.
6357 While it is usually safe to emit nothing, this can fail if the
6358 preceding instruction is a nullified branch with an empty delay
6359 slot and the same branch target as this branch. We could check
6360 for this but jump optimization should eliminate nop jumps. It
6361 is always safe to emit a nop. */
6362 if (branch_to_delay_slot_p (insn))
6365 /* The doubleword form of the cmpib instruction doesn't have the LEU
6366 and GTU conditions while the cmpb instruction does. Since we accept
6367 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6368 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6369 operands[2] = gen_rtx_REG (DImode, 0);
6370 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
6371 operands[1] = gen_rtx_REG (DImode, 0);
6373 /* If this is a long branch with its delay slot unfilled, set `nullify'
6374 as it can nullify the delay slot and save a nop. */
6375 if (length == 8 && dbr_sequence_length () == 0)
6378 /* If this is a short forward conditional branch which did not get
6379 its delay slot filled, the delay slot can still be nullified. */
6380 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6381 nullify = forward_branch_p (insn);
6383 /* A forward branch over a single nullified insn can be done with a
6384 comclr instruction. This avoids a single cycle penalty due to
6385 mis-predicted branch if we fall through (branch not taken). */
6386 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6390 /* All short conditional branches except backwards with an unfilled
6394 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6396 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6397 if (GET_MODE (operands[1]) == DImode)
6400 strcat (buf, "%B3");
6402 strcat (buf, "%S3");
6404 strcat (buf, " %2,%r1,%%r0");
6407 if (branch_needs_nop_p (insn))
6408 strcat (buf, ",n %2,%r1,%0%#");
6410 strcat (buf, ",n %2,%r1,%0");
6413 strcat (buf, " %2,%r1,%0");
6416 /* All long conditionals. Note a short backward branch with an
6417 unfilled delay slot is treated just like a long backward branch
6418 with an unfilled delay slot. */
6420 /* Handle weird backwards branch with a filled delay slot
6421 which is nullified. */
6422 if (dbr_sequence_length () != 0
6423 && ! forward_branch_p (insn)
6426 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6427 if (GET_MODE (operands[1]) == DImode)
6430 strcat (buf, "%S3");
6432 strcat (buf, "%B3");
6433 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6435 /* Handle short backwards branch with an unfilled delay slot.
6436 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6437 taken and untaken branches. */
6438 else if (dbr_sequence_length () == 0
6439 && ! forward_branch_p (insn)
6440 && INSN_ADDRESSES_SET_P ()
6441 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6442 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6444 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6445 if (GET_MODE (operands[1]) == DImode)
6448 strcat (buf, "%B3 %2,%r1,%0%#");
6450 strcat (buf, "%S3 %2,%r1,%0%#");
6454 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6455 if (GET_MODE (operands[1]) == DImode)
6458 strcat (buf, "%S3");
6460 strcat (buf, "%B3");
6462 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6464 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6469 /* The reversed conditional branch must branch over one additional
6470 instruction if the delay slot is filled and needs to be extracted
6471 by pa_output_lbranch. If the delay slot is empty or this is a
6472 nullified forward branch, the instruction after the reversed
6473 condition branch must be nullified. */
6474 if (dbr_sequence_length () == 0
6475 || (nullify && forward_branch_p (insn)))
6479 operands[4] = GEN_INT (length);
6484 operands[4] = GEN_INT (length + 4);
6487 /* Create a reversed conditional branch which branches around
6488 the following insns. */
6489 if (GET_MODE (operands[1]) != DImode)
6495 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6498 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6504 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6507 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6516 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6519 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6525 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6528 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6532 output_asm_insn (buf, operands);
6533 return pa_output_lbranch (operands[0], insn, xdelay);
6538 /* This routine handles output of long unconditional branches that
6539 exceed the maximum range of a simple branch instruction. Since
6540 we don't have a register available for the branch, we save register
6541 %r1 in the frame marker, load the branch destination DEST into %r1,
6542 execute the branch, and restore %r1 in the delay slot of the branch.
6544 Since long branches may have an insn in the delay slot and the
6545 delay slot is used to restore %r1, we in general need to extract
6546 this insn and execute it before the branch. However, to facilitate
6547 use of this function by conditional branches, we also provide an
6548 option to not extract the delay insn so that it will be emitted
6549 after the long branch. So, if there is an insn in the delay slot,
6550 it is extracted if XDELAY is nonzero.
6552 The lengths of the various long-branch sequences are 20, 16 and 24
6553 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6556 pa_output_lbranch (rtx dest, rtx insn, int xdelay)
6560 xoperands[0] = dest;
6562 /* First, free up the delay slot. */
6563 if (xdelay && dbr_sequence_length () != 0)
6565 /* We can't handle a jump in the delay slot. */
6566 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6568 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6571 /* Now delete the delay insn. */
6572 SET_INSN_DELETED (NEXT_INSN (insn));
6575 /* Output an insn to save %r1. The runtime documentation doesn't
6576 specify whether the "Clean Up" slot in the callers frame can
6577 be clobbered by the callee. It isn't copied by HP's builtin
6578 alloca, so this suggests that it can be clobbered if necessary.
6579 The "Static Link" location is copied by HP builtin alloca, so
6580 we avoid using it. Using the cleanup slot might be a problem
6581 if we have to interoperate with languages that pass cleanup
6582 information. However, it should be possible to handle these
6583 situations with GCC's asm feature.
6585 The "Current RP" slot is reserved for the called procedure, so
6586 we try to use it when we don't have a frame of our own. It's
6587 rather unlikely that we won't have a frame when we need to emit
6590 Really the way to go long term is a register scavenger; goto
6591 the target of the jump and find a register which we can use
6592 as a scratch to hold the value in %r1. Then, we wouldn't have
6593 to free up the delay slot or clobber a slot that may be needed
6594 for other purposes. */
6597 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6598 /* Use the return pointer slot in the frame marker. */
6599 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6601 /* Use the slot at -40 in the frame marker since HP builtin
6602 alloca doesn't copy it. */
6603 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6607 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6608 /* Use the return pointer slot in the frame marker. */
6609 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6611 /* Use the "Clean Up" slot in the frame marker. In GCC,
6612 the only other use of this location is for copying a
6613 floating point double argument from a floating-point
6614 register to two general registers. The copy is done
6615 as an "atomic" operation when outputting a call, so it
6616 won't interfere with our using the location here. */
6617 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6620 if (TARGET_PORTABLE_RUNTIME)
6622 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6623 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6624 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6628 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6629 if (TARGET_SOM || !TARGET_GAS)
6631 xoperands[1] = gen_label_rtx ();
6632 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6633 targetm.asm_out.internal_label (asm_out_file, "L",
6634 CODE_LABEL_NUMBER (xoperands[1]));
6635 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6639 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6640 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6642 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6645 /* Now output a very long branch to the original target. */
6646 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6648 /* Now restore the value of %r1 in the delay slot. */
6651 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6652 return "ldd -16(%%r30),%%r1";
6654 return "ldd -40(%%r30),%%r1";
6658 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6659 return "ldw -20(%%r30),%%r1";
6661 return "ldw -12(%%r30),%%r1";
6665 /* This routine handles all the branch-on-bit conditional branch sequences we
6666 might need to generate. It handles nullification of delay slots,
6667 varying length branches, negated branches and all combinations of the
6668 above. it returns the appropriate output template to emit the branch. */
6671 pa_output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6673 static char buf[100];
6675 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6676 int length = get_attr_length (insn);
6679 /* A conditional branch to the following instruction (e.g. the delay slot) is
6680 asking for a disaster. I do not think this can happen as this pattern
6681 is only used when optimizing; jump optimization should eliminate the
6682 jump. But be prepared just in case. */
6684 if (branch_to_delay_slot_p (insn))
6687 /* If this is a long branch with its delay slot unfilled, set `nullify'
6688 as it can nullify the delay slot and save a nop. */
6689 if (length == 8 && dbr_sequence_length () == 0)
6692 /* If this is a short forward conditional branch which did not get
6693 its delay slot filled, the delay slot can still be nullified. */
6694 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6695 nullify = forward_branch_p (insn);
6697 /* A forward branch over a single nullified insn can be done with a
6698 extrs instruction. This avoids a single cycle penalty due to
6699 mis-predicted branch if we fall through (branch not taken). */
6700 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6705 /* All short conditional branches except backwards with an unfilled
6709 strcpy (buf, "{extrs,|extrw,s,}");
6711 strcpy (buf, "bb,");
6712 if (useskip && GET_MODE (operands[0]) == DImode)
6713 strcpy (buf, "extrd,s,*");
6714 else if (GET_MODE (operands[0]) == DImode)
6715 strcpy (buf, "bb,*");
6716 if ((which == 0 && negated)
6717 || (which == 1 && ! negated))
6722 strcat (buf, " %0,%1,1,%%r0");
6723 else if (nullify && negated)
6725 if (branch_needs_nop_p (insn))
6726 strcat (buf, ",n %0,%1,%3%#");
6728 strcat (buf, ",n %0,%1,%3");
6730 else if (nullify && ! negated)
6732 if (branch_needs_nop_p (insn))
6733 strcat (buf, ",n %0,%1,%2%#");
6735 strcat (buf, ",n %0,%1,%2");
6737 else if (! nullify && negated)
6738 strcat (buf, " %0,%1,%3");
6739 else if (! nullify && ! negated)
6740 strcat (buf, " %0,%1,%2");
6743 /* All long conditionals. Note a short backward branch with an
6744 unfilled delay slot is treated just like a long backward branch
6745 with an unfilled delay slot. */
6747 /* Handle weird backwards branch with a filled delay slot
6748 which is nullified. */
6749 if (dbr_sequence_length () != 0
6750 && ! forward_branch_p (insn)
6753 strcpy (buf, "bb,");
6754 if (GET_MODE (operands[0]) == DImode)
6756 if ((which == 0 && negated)
6757 || (which == 1 && ! negated))
6762 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6764 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6766 /* Handle short backwards branch with an unfilled delay slot.
6767 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6768 taken and untaken branches. */
6769 else if (dbr_sequence_length () == 0
6770 && ! forward_branch_p (insn)
6771 && INSN_ADDRESSES_SET_P ()
6772 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6773 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6775 strcpy (buf, "bb,");
6776 if (GET_MODE (operands[0]) == DImode)
6778 if ((which == 0 && negated)
6779 || (which == 1 && ! negated))
6784 strcat (buf, " %0,%1,%3%#");
6786 strcat (buf, " %0,%1,%2%#");
6790 if (GET_MODE (operands[0]) == DImode)
6791 strcpy (buf, "extrd,s,*");
6793 strcpy (buf, "{extrs,|extrw,s,}");
6794 if ((which == 0 && negated)
6795 || (which == 1 && ! negated))
6799 if (nullify && negated)
6800 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6801 else if (nullify && ! negated)
6802 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6804 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6806 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6811 /* The reversed conditional branch must branch over one additional
6812 instruction if the delay slot is filled and needs to be extracted
6813 by pa_output_lbranch. If the delay slot is empty or this is a
6814 nullified forward branch, the instruction after the reversed
6815 condition branch must be nullified. */
6816 if (dbr_sequence_length () == 0
6817 || (nullify && forward_branch_p (insn)))
6821 operands[4] = GEN_INT (length);
6826 operands[4] = GEN_INT (length + 4);
6829 if (GET_MODE (operands[0]) == DImode)
6830 strcpy (buf, "bb,*");
6832 strcpy (buf, "bb,");
6833 if ((which == 0 && negated)
6834 || (which == 1 && !negated))
6839 strcat (buf, ",n %0,%1,.+%4");
6841 strcat (buf, " %0,%1,.+%4");
6842 output_asm_insn (buf, operands);
6843 return pa_output_lbranch (negated ? operands[3] : operands[2],
6849 /* This routine handles all the branch-on-variable-bit conditional branch
6850 sequences we might need to generate. It handles nullification of delay
6851 slots, varying length branches, negated branches and all combinations
6852 of the above. it returns the appropriate output template to emit the
6856 pa_output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn,
6859 static char buf[100];
6861 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6862 int length = get_attr_length (insn);
6865 /* A conditional branch to the following instruction (e.g. the delay slot) is
6866 asking for a disaster. I do not think this can happen as this pattern
6867 is only used when optimizing; jump optimization should eliminate the
6868 jump. But be prepared just in case. */
6870 if (branch_to_delay_slot_p (insn))
6873 /* If this is a long branch with its delay slot unfilled, set `nullify'
6874 as it can nullify the delay slot and save a nop. */
6875 if (length == 8 && dbr_sequence_length () == 0)
6878 /* If this is a short forward conditional branch which did not get
6879 its delay slot filled, the delay slot can still be nullified. */
6880 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6881 nullify = forward_branch_p (insn);
6883 /* A forward branch over a single nullified insn can be done with a
6884 extrs instruction. This avoids a single cycle penalty due to
6885 mis-predicted branch if we fall through (branch not taken). */
6886 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6891 /* All short conditional branches except backwards with an unfilled
6895 strcpy (buf, "{vextrs,|extrw,s,}");
6897 strcpy (buf, "{bvb,|bb,}");
6898 if (useskip && GET_MODE (operands[0]) == DImode)
6899 strcpy (buf, "extrd,s,*");
6900 else if (GET_MODE (operands[0]) == DImode)
6901 strcpy (buf, "bb,*");
6902 if ((which == 0 && negated)
6903 || (which == 1 && ! negated))
6908 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6909 else if (nullify && negated)
6911 if (branch_needs_nop_p (insn))
6912 strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}");
6914 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6916 else if (nullify && ! negated)
6918 if (branch_needs_nop_p (insn))
6919 strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}");
6921 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6923 else if (! nullify && negated)
6924 strcat (buf, "{ %0,%3| %0,%%sar,%3}");
6925 else if (! nullify && ! negated)
6926 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6929 /* All long conditionals. Note a short backward branch with an
6930 unfilled delay slot is treated just like a long backward branch
6931 with an unfilled delay slot. */
6933 /* Handle weird backwards branch with a filled delay slot
6934 which is nullified. */
6935 if (dbr_sequence_length () != 0
6936 && ! forward_branch_p (insn)
6939 strcpy (buf, "{bvb,|bb,}");
6940 if (GET_MODE (operands[0]) == DImode)
6942 if ((which == 0 && negated)
6943 || (which == 1 && ! negated))
6948 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6950 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6952 /* Handle short backwards branch with an unfilled delay slot.
6953 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6954 taken and untaken branches. */
6955 else if (dbr_sequence_length () == 0
6956 && ! forward_branch_p (insn)
6957 && INSN_ADDRESSES_SET_P ()
6958 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6959 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6961 strcpy (buf, "{bvb,|bb,}");
6962 if (GET_MODE (operands[0]) == DImode)
6964 if ((which == 0 && negated)
6965 || (which == 1 && ! negated))
6970 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6972 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6976 strcpy (buf, "{vextrs,|extrw,s,}");
6977 if (GET_MODE (operands[0]) == DImode)
6978 strcpy (buf, "extrd,s,*");
6979 if ((which == 0 && negated)
6980 || (which == 1 && ! negated))
6984 if (nullify && negated)
6985 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6986 else if (nullify && ! negated)
6987 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6989 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6991 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6996 /* The reversed conditional branch must branch over one additional
6997 instruction if the delay slot is filled and needs to be extracted
6998 by pa_output_lbranch. If the delay slot is empty or this is a
6999 nullified forward branch, the instruction after the reversed
7000 condition branch must be nullified. */
7001 if (dbr_sequence_length () == 0
7002 || (nullify && forward_branch_p (insn)))
7006 operands[4] = GEN_INT (length);
7011 operands[4] = GEN_INT (length + 4);
7014 if (GET_MODE (operands[0]) == DImode)
7015 strcpy (buf, "bb,*");
7017 strcpy (buf, "{bvb,|bb,}");
7018 if ((which == 0 && negated)
7019 || (which == 1 && !negated))
7024 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
7026 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
7027 output_asm_insn (buf, operands);
7028 return pa_output_lbranch (negated ? operands[3] : operands[2],
7034 /* Return the output template for emitting a dbra type insn.
7036 Note it may perform some output operations on its own before
7037 returning the final output string. */
7039 pa_output_dbra (rtx *operands, rtx insn, int which_alternative)
7041 int length = get_attr_length (insn);
7043 /* A conditional branch to the following instruction (e.g. the delay slot) is
7044 asking for a disaster. Be prepared! */
7046 if (branch_to_delay_slot_p (insn))
7048 if (which_alternative == 0)
7049 return "ldo %1(%0),%0";
7050 else if (which_alternative == 1)
7052 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
7053 output_asm_insn ("ldw -16(%%r30),%4", operands);
7054 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
7055 return "{fldws|fldw} -16(%%r30),%0";
7059 output_asm_insn ("ldw %0,%4", operands);
7060 return "ldo %1(%4),%4\n\tstw %4,%0";
7064 if (which_alternative == 0)
7066 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7069 /* If this is a long branch with its delay slot unfilled, set `nullify'
7070 as it can nullify the delay slot and save a nop. */
7071 if (length == 8 && dbr_sequence_length () == 0)
7074 /* If this is a short forward conditional branch which did not get
7075 its delay slot filled, the delay slot can still be nullified. */
7076 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7077 nullify = forward_branch_p (insn);
7084 if (branch_needs_nop_p (insn))
7085 return "addib,%C2,n %1,%0,%3%#";
7087 return "addib,%C2,n %1,%0,%3";
7090 return "addib,%C2 %1,%0,%3";
7093 /* Handle weird backwards branch with a fulled delay slot
7094 which is nullified. */
7095 if (dbr_sequence_length () != 0
7096 && ! forward_branch_p (insn)
7098 return "addib,%N2,n %1,%0,.+12\n\tb %3";
7099 /* Handle short backwards branch with an unfilled delay slot.
7100 Using a addb;nop rather than addi;bl saves 1 cycle for both
7101 taken and untaken branches. */
7102 else if (dbr_sequence_length () == 0
7103 && ! forward_branch_p (insn)
7104 && INSN_ADDRESSES_SET_P ()
7105 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7106 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7107 return "addib,%C2 %1,%0,%3%#";
7109 /* Handle normal cases. */
7111 return "addi,%N2 %1,%0,%0\n\tb,n %3";
7113 return "addi,%N2 %1,%0,%0\n\tb %3";
7116 /* The reversed conditional branch must branch over one additional
7117 instruction if the delay slot is filled and needs to be extracted
7118 by pa_output_lbranch. If the delay slot is empty or this is a
7119 nullified forward branch, the instruction after the reversed
7120 condition branch must be nullified. */
7121 if (dbr_sequence_length () == 0
7122 || (nullify && forward_branch_p (insn)))
7126 operands[4] = GEN_INT (length);
7131 operands[4] = GEN_INT (length + 4);
7135 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
7137 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
7139 return pa_output_lbranch (operands[3], insn, xdelay);
7143 /* Deal with gross reload from FP register case. */
7144 else if (which_alternative == 1)
7146 /* Move loop counter from FP register to MEM then into a GR,
7147 increment the GR, store the GR into MEM, and finally reload
7148 the FP register from MEM from within the branch's delay slot. */
7149 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
7151 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
7153 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
7154 else if (length == 28)
7155 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7158 operands[5] = GEN_INT (length - 16);
7159 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
7160 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7161 return pa_output_lbranch (operands[3], insn, 0);
7164 /* Deal with gross reload from memory case. */
7167 /* Reload loop counter from memory, the store back to memory
7168 happens in the branch's delay slot. */
7169 output_asm_insn ("ldw %0,%4", operands);
7171 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
7172 else if (length == 16)
7173 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
7176 operands[5] = GEN_INT (length - 4);
7177 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
7178 return pa_output_lbranch (operands[3], insn, 0);
7183 /* Return the output template for emitting a movb type insn.
7185 Note it may perform some output operations on its own before
7186 returning the final output string. */
7188 pa_output_movb (rtx *operands, rtx insn, int which_alternative,
7189 int reverse_comparison)
7191 int length = get_attr_length (insn);
7193 /* A conditional branch to the following instruction (e.g. the delay slot) is
7194 asking for a disaster. Be prepared! */
7196 if (branch_to_delay_slot_p (insn))
7198 if (which_alternative == 0)
7199 return "copy %1,%0";
7200 else if (which_alternative == 1)
7202 output_asm_insn ("stw %1,-16(%%r30)", operands);
7203 return "{fldws|fldw} -16(%%r30),%0";
7205 else if (which_alternative == 2)
7211 /* Support the second variant. */
7212 if (reverse_comparison)
7213 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
7215 if (which_alternative == 0)
7217 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7220 /* If this is a long branch with its delay slot unfilled, set `nullify'
7221 as it can nullify the delay slot and save a nop. */
7222 if (length == 8 && dbr_sequence_length () == 0)
7225 /* If this is a short forward conditional branch which did not get
7226 its delay slot filled, the delay slot can still be nullified. */
7227 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7228 nullify = forward_branch_p (insn);
7235 if (branch_needs_nop_p (insn))
7236 return "movb,%C2,n %1,%0,%3%#";
7238 return "movb,%C2,n %1,%0,%3";
7241 return "movb,%C2 %1,%0,%3";
7244 /* Handle weird backwards branch with a filled delay slot
7245 which is nullified. */
7246 if (dbr_sequence_length () != 0
7247 && ! forward_branch_p (insn)
7249 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7251 /* Handle short backwards branch with an unfilled delay slot.
7252 Using a movb;nop rather than or;bl saves 1 cycle for both
7253 taken and untaken branches. */
7254 else if (dbr_sequence_length () == 0
7255 && ! forward_branch_p (insn)
7256 && INSN_ADDRESSES_SET_P ()
7257 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7258 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7259 return "movb,%C2 %1,%0,%3%#";
7260 /* Handle normal cases. */
7262 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7264 return "or,%N2 %1,%%r0,%0\n\tb %3";
7267 /* The reversed conditional branch must branch over one additional
7268 instruction if the delay slot is filled and needs to be extracted
7269 by pa_output_lbranch. If the delay slot is empty or this is a
7270 nullified forward branch, the instruction after the reversed
7271 condition branch must be nullified. */
7272 if (dbr_sequence_length () == 0
7273 || (nullify && forward_branch_p (insn)))
7277 operands[4] = GEN_INT (length);
7282 operands[4] = GEN_INT (length + 4);
7286 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
7288 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
7290 return pa_output_lbranch (operands[3], insn, xdelay);
7293 /* Deal with gross reload for FP destination register case. */
7294 else if (which_alternative == 1)
7296 /* Move source register to MEM, perform the branch test, then
7297 finally load the FP register from MEM from within the branch's
7299 output_asm_insn ("stw %1,-16(%%r30)", operands);
7301 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7302 else if (length == 16)
7303 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7306 operands[4] = GEN_INT (length - 4);
7307 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
7308 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7309 return pa_output_lbranch (operands[3], insn, 0);
7312 /* Deal with gross reload from memory case. */
7313 else if (which_alternative == 2)
7315 /* Reload loop counter from memory, the store back to memory
7316 happens in the branch's delay slot. */
7318 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7319 else if (length == 12)
7320 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7323 operands[4] = GEN_INT (length);
7324 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7326 return pa_output_lbranch (operands[3], insn, 0);
7329 /* Handle SAR as a destination. */
7333 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7334 else if (length == 12)
7335 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7338 operands[4] = GEN_INT (length);
7339 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7341 return pa_output_lbranch (operands[3], insn, 0);
7346 /* Copy any FP arguments in INSN into integer registers. */
7348 copy_fp_args (rtx insn)
7353 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7355 int arg_mode, regno;
7356 rtx use = XEXP (link, 0);
7358 if (! (GET_CODE (use) == USE
7359 && GET_CODE (XEXP (use, 0)) == REG
7360 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7363 arg_mode = GET_MODE (XEXP (use, 0));
7364 regno = REGNO (XEXP (use, 0));
7366 /* Is it a floating point register? */
7367 if (regno >= 32 && regno <= 39)
7369 /* Copy the FP register into an integer register via memory. */
7370 if (arg_mode == SFmode)
7372 xoperands[0] = XEXP (use, 0);
7373 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7374 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7375 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7379 xoperands[0] = XEXP (use, 0);
7380 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7381 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7382 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7383 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7389 /* Compute length of the FP argument copy sequence for INSN. */
7391 length_fp_args (rtx insn)
7396 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7398 int arg_mode, regno;
7399 rtx use = XEXP (link, 0);
7401 if (! (GET_CODE (use) == USE
7402 && GET_CODE (XEXP (use, 0)) == REG
7403 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7406 arg_mode = GET_MODE (XEXP (use, 0));
7407 regno = REGNO (XEXP (use, 0));
7409 /* Is it a floating point register? */
7410 if (regno >= 32 && regno <= 39)
7412 if (arg_mode == SFmode)
7422 /* Return the attribute length for the millicode call instruction INSN.
7423 The length must match the code generated by pa_output_millicode_call.
7424 We include the delay slot in the returned length as it is better to
7425 over estimate the length than to under estimate it. */
7428 pa_attr_length_millicode_call (rtx insn)
7430 unsigned long distance = -1;
7431 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7433 if (INSN_ADDRESSES_SET_P ())
7435 distance = (total + insn_current_reference_address (insn));
7436 if (distance < total)
7442 if (!TARGET_LONG_CALLS && distance < 7600000)
7447 else if (TARGET_PORTABLE_RUNTIME)
7451 if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET)
7454 if (TARGET_LONG_ABS_CALL && !flag_pic)
7461 /* INSN is a function call. It may have an unconditional jump
7464 CALL_DEST is the routine we are calling. */
7467 pa_output_millicode_call (rtx insn, rtx call_dest)
7469 int attr_length = get_attr_length (insn);
7470 int seq_length = dbr_sequence_length ();
7475 xoperands[0] = call_dest;
7476 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7478 /* Handle the common case where we are sure that the branch will
7479 reach the beginning of the $CODE$ subspace. The within reach
7480 form of the $$sh_func_adrs call has a length of 28. Because
7481 it has an attribute type of multi, it never has a nonzero
7482 sequence length. The length of the $$sh_func_adrs is the same
7483 as certain out of reach PIC calls to other routines. */
7484 if (!TARGET_LONG_CALLS
7485 && ((seq_length == 0
7486 && (attr_length == 12
7487 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7488 || (seq_length != 0 && attr_length == 8)))
7490 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7496 /* It might seem that one insn could be saved by accessing
7497 the millicode function using the linkage table. However,
7498 this doesn't work in shared libraries and other dynamically
7499 loaded objects. Using a pc-relative sequence also avoids
7500 problems related to the implicit use of the gp register. */
7501 output_asm_insn ("b,l .+8,%%r1", xoperands);
7505 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7506 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7510 xoperands[1] = gen_label_rtx ();
7511 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7512 targetm.asm_out.internal_label (asm_out_file, "L",
7513 CODE_LABEL_NUMBER (xoperands[1]));
7514 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7517 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7519 else if (TARGET_PORTABLE_RUNTIME)
7521 /* Pure portable runtime doesn't allow be/ble; we also don't
7522 have PIC support in the assembler/linker, so this sequence
7525 /* Get the address of our target into %r1. */
7526 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7527 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7529 /* Get our return address into %r31. */
7530 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7531 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7533 /* Jump to our target address in %r1. */
7534 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7538 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7540 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7542 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7546 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7547 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7549 if (TARGET_SOM || !TARGET_GAS)
7551 /* The HP assembler can generate relocations for the
7552 difference of two symbols. GAS can do this for a
7553 millicode symbol but not an arbitrary external
7554 symbol when generating SOM output. */
7555 xoperands[1] = gen_label_rtx ();
7556 targetm.asm_out.internal_label (asm_out_file, "L",
7557 CODE_LABEL_NUMBER (xoperands[1]));
7558 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7559 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7563 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7564 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7568 /* Jump to our target address in %r1. */
7569 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7573 if (seq_length == 0)
7574 output_asm_insn ("nop", xoperands);
7576 /* We are done if there isn't a jump in the delay slot. */
7577 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7580 /* This call has an unconditional jump in its delay slot. */
7581 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7583 /* See if the return address can be adjusted. Use the containing
7584 sequence insn's address. */
7585 if (INSN_ADDRESSES_SET_P ())
7587 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7588 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7589 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7591 if (VAL_14_BITS_P (distance))
7593 xoperands[1] = gen_label_rtx ();
7594 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7595 targetm.asm_out.internal_label (asm_out_file, "L",
7596 CODE_LABEL_NUMBER (xoperands[1]));
7599 /* ??? This branch may not reach its target. */
7600 output_asm_insn ("nop\n\tb,n %0", xoperands);
7603 /* ??? This branch may not reach its target. */
7604 output_asm_insn ("nop\n\tb,n %0", xoperands);
7606 /* Delete the jump. */
7607 SET_INSN_DELETED (NEXT_INSN (insn));
7612 /* Return the attribute length of the call instruction INSN. The SIBCALL
7613 flag indicates whether INSN is a regular call or a sibling call. The
7614 length returned must be longer than the code actually generated by
7615 pa_output_call. Since branch shortening is done before delay branch
7616 sequencing, there is no way to determine whether or not the delay
7617 slot will be filled during branch shortening. Even when the delay
7618 slot is filled, we may have to add a nop if the delay slot contains
7619 a branch that can't reach its target. Thus, we always have to include
7620 the delay slot in the length estimate. This used to be done in
7621 pa_adjust_insn_length but we do it here now as some sequences always
7622 fill the delay slot and we can save four bytes in the estimate for
7626 pa_attr_length_call (rtx insn, int sibcall)
7629 rtx call, call_dest;
7632 rtx pat = PATTERN (insn);
7633 unsigned long distance = -1;
7635 gcc_assert (GET_CODE (insn) == CALL_INSN);
7637 if (INSN_ADDRESSES_SET_P ())
7639 unsigned long total;
7641 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7642 distance = (total + insn_current_reference_address (insn));
7643 if (distance < total)
7647 gcc_assert (GET_CODE (pat) == PARALLEL);
7649 /* Get the call rtx. */
7650 call = XVECEXP (pat, 0, 0);
7651 if (GET_CODE (call) == SET)
7652 call = SET_SRC (call);
7654 gcc_assert (GET_CODE (call) == CALL);
7656 /* Determine if this is a local call. */
7657 call_dest = XEXP (XEXP (call, 0), 0);
7658 call_decl = SYMBOL_REF_DECL (call_dest);
7659 local_call = call_decl && targetm.binds_local_p (call_decl);
7661 /* pc-relative branch. */
7662 if (!TARGET_LONG_CALLS
7663 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7664 || distance < MAX_PCREL17F_OFFSET))
7667 /* 64-bit plabel sequence. */
7668 else if (TARGET_64BIT && !local_call)
7669 length += sibcall ? 28 : 24;
7671 /* non-pic long absolute branch sequence. */
7672 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7675 /* long pc-relative branch sequence. */
7676 else if (TARGET_LONG_PIC_SDIFF_CALL
7677 || (TARGET_GAS && !TARGET_SOM
7678 && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7682 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7686 /* 32-bit plabel sequence. */
7692 length += length_fp_args (insn);
7702 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7710 /* INSN is a function call. It may have an unconditional jump
7713 CALL_DEST is the routine we are calling. */
7716 pa_output_call (rtx insn, rtx call_dest, int sibcall)
7718 int delay_insn_deleted = 0;
7719 int delay_slot_filled = 0;
7720 int seq_length = dbr_sequence_length ();
7721 tree call_decl = SYMBOL_REF_DECL (call_dest);
7722 int local_call = call_decl && targetm.binds_local_p (call_decl);
7725 xoperands[0] = call_dest;
7727 /* Handle the common case where we're sure that the branch will reach
7728 the beginning of the "$CODE$" subspace. This is the beginning of
7729 the current function if we are in a named section. */
7730 if (!TARGET_LONG_CALLS && pa_attr_length_call (insn, sibcall) == 8)
7732 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7733 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7737 if (TARGET_64BIT && !local_call)
7739 /* ??? As far as I can tell, the HP linker doesn't support the
7740 long pc-relative sequence described in the 64-bit runtime
7741 architecture. So, we use a slightly longer indirect call. */
7742 xoperands[0] = pa_get_deferred_plabel (call_dest);
7743 xoperands[1] = gen_label_rtx ();
7745 /* If this isn't a sibcall, we put the load of %r27 into the
7746 delay slot. We can't do this in a sibcall as we don't
7747 have a second call-clobbered scratch register available. */
7749 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7752 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7755 /* Now delete the delay insn. */
7756 SET_INSN_DELETED (NEXT_INSN (insn));
7757 delay_insn_deleted = 1;
7760 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7761 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7762 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7766 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7767 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7768 output_asm_insn ("bve (%%r1)", xoperands);
7772 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7773 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7774 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7775 delay_slot_filled = 1;
7780 int indirect_call = 0;
7782 /* Emit a long call. There are several different sequences
7783 of increasing length and complexity. In most cases,
7784 they don't allow an instruction in the delay slot. */
7785 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7786 && !TARGET_LONG_PIC_SDIFF_CALL
7787 && !(TARGET_GAS && !TARGET_SOM
7788 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7793 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7797 || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)))
7799 /* A non-jump insn in the delay slot. By definition we can
7800 emit this insn before the call (and in fact before argument
7802 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7805 /* Now delete the delay insn. */
7806 SET_INSN_DELETED (NEXT_INSN (insn));
7807 delay_insn_deleted = 1;
7810 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7812 /* This is the best sequence for making long calls in
7813 non-pic code. Unfortunately, GNU ld doesn't provide
7814 the stub needed for external calls, and GAS's support
7815 for this with the SOM linker is buggy. It is safe
7816 to use this for local calls. */
7817 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7819 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7823 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7826 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7828 output_asm_insn ("copy %%r31,%%r2", xoperands);
7829 delay_slot_filled = 1;
7834 if (TARGET_LONG_PIC_SDIFF_CALL)
7836 /* The HP assembler and linker can handle relocations
7837 for the difference of two symbols. The HP assembler
7838 recognizes the sequence as a pc-relative call and
7839 the linker provides stubs when needed. */
7840 xoperands[1] = gen_label_rtx ();
7841 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7842 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7843 targetm.asm_out.internal_label (asm_out_file, "L",
7844 CODE_LABEL_NUMBER (xoperands[1]));
7845 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7847 else if (TARGET_GAS && !TARGET_SOM
7848 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7850 /* GAS currently can't generate the relocations that
7851 are needed for the SOM linker under HP-UX using this
7852 sequence. The GNU linker doesn't generate the stubs
7853 that are needed for external calls on TARGET_ELF32
7854 with this sequence. For now, we have to use a
7855 longer plabel sequence when using GAS. */
7856 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7857 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7859 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7864 /* Emit a long plabel-based call sequence. This is
7865 essentially an inline implementation of $$dyncall.
7866 We don't actually try to call $$dyncall as this is
7867 as difficult as calling the function itself. */
7868 xoperands[0] = pa_get_deferred_plabel (call_dest);
7869 xoperands[1] = gen_label_rtx ();
7871 /* Since the call is indirect, FP arguments in registers
7872 need to be copied to the general registers. Then, the
7873 argument relocation stub will copy them back. */
7875 copy_fp_args (insn);
7879 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7880 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7881 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7885 output_asm_insn ("addil LR'%0-$global$,%%r27",
7887 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7891 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7892 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7893 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7894 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7896 if (!sibcall && !TARGET_PA_20)
7898 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7899 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7900 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7902 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7909 output_asm_insn ("bve (%%r1)", xoperands);
7914 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7915 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7916 delay_slot_filled = 1;
7919 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7924 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7925 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7930 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7931 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7933 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7937 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7938 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7940 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7943 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7945 output_asm_insn ("copy %%r31,%%r2", xoperands);
7946 delay_slot_filled = 1;
7953 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7954 output_asm_insn ("nop", xoperands);
7956 /* We are done if there isn't a jump in the delay slot. */
7958 || delay_insn_deleted
7959 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7962 /* A sibcall should never have a branch in the delay slot. */
7963 gcc_assert (!sibcall);
7965 /* This call has an unconditional jump in its delay slot. */
7966 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7968 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7970 /* See if the return address can be adjusted. Use the containing
7971 sequence insn's address. This would break the regular call/return@
7972 relationship assumed by the table based eh unwinder, so only do that
7973 if the call is not possibly throwing. */
7974 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7975 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7976 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7978 if (VAL_14_BITS_P (distance)
7979 && !(can_throw_internal (insn) || can_throw_external (insn)))
7981 xoperands[1] = gen_label_rtx ();
7982 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7983 targetm.asm_out.internal_label (asm_out_file, "L",
7984 CODE_LABEL_NUMBER (xoperands[1]));
7987 output_asm_insn ("nop\n\tb,n %0", xoperands);
7990 output_asm_insn ("b,n %0", xoperands);
7992 /* Delete the jump. */
7993 SET_INSN_DELETED (NEXT_INSN (insn));
7998 /* Return the attribute length of the indirect call instruction INSN.
7999 The length must match the code generated by output_indirect call.
8000 The returned length includes the delay slot. Currently, the delay
8001 slot of an indirect call sequence is not exposed and it is used by
8002 the sequence itself. */
8005 pa_attr_length_indirect_call (rtx insn)
8007 unsigned long distance = -1;
8008 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
8010 if (INSN_ADDRESSES_SET_P ())
8012 distance = (total + insn_current_reference_address (insn));
8013 if (distance < total)
8020 if (TARGET_FAST_INDIRECT_CALLS
8021 || (!TARGET_PORTABLE_RUNTIME
8022 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
8023 || distance < MAX_PCREL17F_OFFSET)))
8029 if (TARGET_PORTABLE_RUNTIME)
8032 /* Out of reach, can use ble. */
8037 pa_output_indirect_call (rtx insn, rtx call_dest)
8043 xoperands[0] = call_dest;
8044 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
8045 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
8049 /* First the special case for kernels, level 0 systems, etc. */
8050 if (TARGET_FAST_INDIRECT_CALLS)
8051 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
8053 /* Now the normal case -- we can reach $$dyncall directly or
8054 we're sure that we can get there via a long-branch stub.
8056 No need to check target flags as the length uniquely identifies
8057 the remaining cases. */
8058 if (pa_attr_length_indirect_call (insn) == 8)
8060 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
8061 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
8062 variant of the B,L instruction can't be used on the SOM target. */
8063 if (TARGET_PA_20 && !TARGET_SOM)
8064 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
8066 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
8069 /* Long millicode call, but we are not generating PIC or portable runtime
8071 if (pa_attr_length_indirect_call (insn) == 12)
8072 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
8074 /* Long millicode call for portable runtime. */
8075 if (pa_attr_length_indirect_call (insn) == 20)
8076 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
8078 /* We need a long PIC call to $$dyncall. */
8079 xoperands[0] = NULL_RTX;
8080 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8081 if (TARGET_SOM || !TARGET_GAS)
8083 xoperands[0] = gen_label_rtx ();
8084 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
8085 targetm.asm_out.internal_label (asm_out_file, "L",
8086 CODE_LABEL_NUMBER (xoperands[0]));
8087 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
8091 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
8092 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
8095 output_asm_insn ("blr %%r0,%%r2", xoperands);
8096 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
8100 /* In HPUX 8.0's shared library scheme, special relocations are needed
8101 for function labels if they might be passed to a function
8102 in a shared library (because shared libraries don't live in code
8103 space), and special magic is needed to construct their address. */
8106 pa_encode_label (rtx sym)
8108 const char *str = XSTR (sym, 0);
8109 int len = strlen (str) + 1;
8112 p = newstr = XALLOCAVEC (char, len + 1);
8116 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
8120 pa_encode_section_info (tree decl, rtx rtl, int first)
8122 int old_referenced = 0;
8124 if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
8126 = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED;
8128 default_encode_section_info (decl, rtl, first);
8130 if (first && TEXT_SPACE_P (decl))
8132 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
8133 if (TREE_CODE (decl) == FUNCTION_DECL)
8134 pa_encode_label (XEXP (rtl, 0));
8136 else if (old_referenced)
8137 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced;
8140 /* This is sort of inverse to pa_encode_section_info. */
8143 pa_strip_name_encoding (const char *str)
8145 str += (*str == '@');
8146 str += (*str == '*');
8150 /* Returns 1 if OP is a function label involved in a simple addition
8151 with a constant. Used to keep certain patterns from matching
8152 during instruction combination. */
8154 pa_is_function_label_plus_const (rtx op)
8156 /* Strip off any CONST. */
8157 if (GET_CODE (op) == CONST)
8160 return (GET_CODE (op) == PLUS
8161 && function_label_operand (XEXP (op, 0), VOIDmode)
8162 && GET_CODE (XEXP (op, 1)) == CONST_INT);
8165 /* Output assembly code for a thunk to FUNCTION. */
8168 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
8169 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8172 static unsigned int current_thunk_number;
8173 int val_14 = VAL_14_BITS_P (delta);
8174 unsigned int old_last_address = last_address, nbytes = 0;
8178 xoperands[0] = XEXP (DECL_RTL (function), 0);
8179 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
8180 xoperands[2] = GEN_INT (delta);
8182 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
8183 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
8185 /* Output the thunk. We know that the function is in the same
8186 translation unit (i.e., the same space) as the thunk, and that
8187 thunks are output after their method. Thus, we don't need an
8188 external branch to reach the function. With SOM and GAS,
8189 functions and thunks are effectively in different sections.
8190 Thus, we can always use a IA-relative branch and the linker
8191 will add a long branch stub if necessary.
8193 However, we have to be careful when generating PIC code on the
8194 SOM port to ensure that the sequence does not transfer to an
8195 import stub for the target function as this could clobber the
8196 return value saved at SP-24. This would also apply to the
8197 32-bit linux port if the multi-space model is implemented. */
8198 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8199 && !(flag_pic && TREE_PUBLIC (function))
8200 && (TARGET_GAS || last_address < 262132))
8201 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8202 && ((targetm_common.have_named_sections
8203 && DECL_SECTION_NAME (thunk_fndecl) != NULL
8204 /* The GNU 64-bit linker has rather poor stub management.
8205 So, we use a long branch from thunks that aren't in
8206 the same section as the target function. */
8208 && (DECL_SECTION_NAME (thunk_fndecl)
8209 != DECL_SECTION_NAME (function)))
8210 || ((DECL_SECTION_NAME (thunk_fndecl)
8211 == DECL_SECTION_NAME (function))
8212 && last_address < 262132)))
8213 || (targetm_common.have_named_sections
8214 && DECL_SECTION_NAME (thunk_fndecl) == NULL
8215 && DECL_SECTION_NAME (function) == NULL
8216 && last_address < 262132)
8217 || (!targetm_common.have_named_sections
8218 && last_address < 262132))))
8221 output_asm_insn ("addil L'%2,%%r26", xoperands);
8223 output_asm_insn ("b %0", xoperands);
8227 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8232 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8236 else if (TARGET_64BIT)
8238 /* We only have one call-clobbered scratch register, so we can't
8239 make use of the delay slot if delta doesn't fit in 14 bits. */
8242 output_asm_insn ("addil L'%2,%%r26", xoperands);
8243 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8246 output_asm_insn ("b,l .+8,%%r1", xoperands);
8250 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8251 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
8255 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
8256 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
8261 output_asm_insn ("bv %%r0(%%r1)", xoperands);
8262 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8267 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
8271 else if (TARGET_PORTABLE_RUNTIME)
8273 output_asm_insn ("ldil L'%0,%%r1", xoperands);
8274 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
8277 output_asm_insn ("addil L'%2,%%r26", xoperands);
8279 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8283 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8288 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8292 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8294 /* The function is accessible from outside this module. The only
8295 way to avoid an import stub between the thunk and function is to
8296 call the function directly with an indirect sequence similar to
8297 that used by $$dyncall. This is possible because $$dyncall acts
8298 as the import stub in an indirect call. */
8299 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
8300 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8301 output_asm_insn ("addil LT'%3,%%r19", xoperands);
8302 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
8303 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8304 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
8305 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
8306 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
8307 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8311 output_asm_insn ("addil L'%2,%%r26", xoperands);
8317 output_asm_insn ("bve (%%r22)", xoperands);
8320 else if (TARGET_NO_SPACE_REGS)
8322 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
8327 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
8328 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
8329 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
8334 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8336 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8340 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8342 if (TARGET_SOM || !TARGET_GAS)
8344 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
8345 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
8349 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8350 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
8354 output_asm_insn ("addil L'%2,%%r26", xoperands);
8356 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8360 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8365 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8372 output_asm_insn ("addil L'%2,%%r26", xoperands);
8374 output_asm_insn ("ldil L'%0,%%r22", xoperands);
8375 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
8379 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8384 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8389 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8391 if (TARGET_SOM && TARGET_GAS)
8393 /* We done with this subspace except possibly for some additional
8394 debug information. Forget that we are in this subspace to ensure
8395 that the next function is output in its own subspace. */
8397 cfun->machine->in_nsubspa = 2;
8400 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8402 switch_to_section (data_section);
8403 output_asm_insn (".align 4", xoperands);
8404 ASM_OUTPUT_LABEL (file, label);
8405 output_asm_insn (".word P'%0", xoperands);
8408 current_thunk_number++;
8409 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8410 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8411 last_address += nbytes;
8412 if (old_last_address > last_address)
8413 last_address = UINT_MAX;
8414 update_total_code_bytes (nbytes);
8417 /* Only direct calls to static functions are allowed to be sibling (tail)
8420 This restriction is necessary because some linker generated stubs will
8421 store return pointers into rp' in some cases which might clobber a
8422 live value already in rp'.
8424 In a sibcall the current function and the target function share stack
8425 space. Thus if the path to the current function and the path to the
8426 target function save a value in rp', they save the value into the
8427 same stack slot, which has undesirable consequences.
8429 Because of the deferred binding nature of shared libraries any function
8430 with external scope could be in a different load module and thus require
8431 rp' to be saved when calling that function. So sibcall optimizations
8432 can only be safe for static function.
8434 Note that GCC never needs return value relocations, so we don't have to
8435 worry about static calls with return value relocations (which require
8438 It is safe to perform a sibcall optimization when the target function
8439 will never return. */
8441 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8443 if (TARGET_PORTABLE_RUNTIME)
8446 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8447 single subspace mode and the call is not indirect. As far as I know,
8448 there is no operating system support for the multiple subspace mode.
8449 It might be possible to support indirect calls if we didn't use
8450 $$dyncall (see the indirect sequence generated in pa_output_call). */
8452 return (decl != NULL_TREE);
8454 /* Sibcalls are not ok because the arg pointer register is not a fixed
8455 register. This prevents the sibcall optimization from occurring. In
8456 addition, there are problems with stub placement using GNU ld. This
8457 is because a normal sibcall branch uses a 17-bit relocation while
8458 a regular call branch uses a 22-bit relocation. As a result, more
8459 care needs to be taken in the placement of long-branch stubs. */
8463 /* Sibcalls are only ok within a translation unit. */
8464 return (decl && !TREE_PUBLIC (decl));
8467 /* ??? Addition is not commutative on the PA due to the weird implicit
8468 space register selection rules for memory addresses. Therefore, we
8469 don't consider a + b == b + a, as this might be inside a MEM. */
8471 pa_commutative_p (const_rtx x, int outer_code)
8473 return (COMMUTATIVE_P (x)
8474 && (TARGET_NO_SPACE_REGS
8475 || (outer_code != UNKNOWN && outer_code != MEM)
8476 || GET_CODE (x) != PLUS));
8479 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8480 use in fmpyadd instructions. */
8482 pa_fmpyaddoperands (rtx *operands)
8484 enum machine_mode mode = GET_MODE (operands[0]);
8486 /* Must be a floating point mode. */
8487 if (mode != SFmode && mode != DFmode)
8490 /* All modes must be the same. */
8491 if (! (mode == GET_MODE (operands[1])
8492 && mode == GET_MODE (operands[2])
8493 && mode == GET_MODE (operands[3])
8494 && mode == GET_MODE (operands[4])
8495 && mode == GET_MODE (operands[5])))
8498 /* All operands must be registers. */
8499 if (! (GET_CODE (operands[1]) == REG
8500 && GET_CODE (operands[2]) == REG
8501 && GET_CODE (operands[3]) == REG
8502 && GET_CODE (operands[4]) == REG
8503 && GET_CODE (operands[5]) == REG))
8506 /* Only 2 real operands to the addition. One of the input operands must
8507 be the same as the output operand. */
8508 if (! rtx_equal_p (operands[3], operands[4])
8509 && ! rtx_equal_p (operands[3], operands[5]))
8512 /* Inout operand of add cannot conflict with any operands from multiply. */
8513 if (rtx_equal_p (operands[3], operands[0])
8514 || rtx_equal_p (operands[3], operands[1])
8515 || rtx_equal_p (operands[3], operands[2]))
8518 /* multiply cannot feed into addition operands. */
8519 if (rtx_equal_p (operands[4], operands[0])
8520 || rtx_equal_p (operands[5], operands[0]))
8523 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8525 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8526 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8527 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8528 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8529 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8530 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8533 /* Passed. Operands are suitable for fmpyadd. */
8537 #if !defined(USE_COLLECT2)
8539 pa_asm_out_constructor (rtx symbol, int priority)
8541 if (!function_label_operand (symbol, VOIDmode))
8542 pa_encode_label (symbol);
8544 #ifdef CTORS_SECTION_ASM_OP
8545 default_ctor_section_asm_out_constructor (symbol, priority);
8547 # ifdef TARGET_ASM_NAMED_SECTION
8548 default_named_section_asm_out_constructor (symbol, priority);
8550 default_stabs_asm_out_constructor (symbol, priority);
8556 pa_asm_out_destructor (rtx symbol, int priority)
8558 if (!function_label_operand (symbol, VOIDmode))
8559 pa_encode_label (symbol);
8561 #ifdef DTORS_SECTION_ASM_OP
8562 default_dtor_section_asm_out_destructor (symbol, priority);
8564 # ifdef TARGET_ASM_NAMED_SECTION
8565 default_named_section_asm_out_destructor (symbol, priority);
8567 default_stabs_asm_out_destructor (symbol, priority);
8573 /* This function places uninitialized global data in the bss section.
8574 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8575 function on the SOM port to prevent uninitialized global data from
8576 being placed in the data section. */
8579 pa_asm_output_aligned_bss (FILE *stream,
8581 unsigned HOST_WIDE_INT size,
8584 switch_to_section (bss_section);
8585 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8587 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8588 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8591 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8592 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8595 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8596 ASM_OUTPUT_LABEL (stream, name);
8597 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8600 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8601 that doesn't allow the alignment of global common storage to be directly
8602 specified. The SOM linker aligns common storage based on the rounded
8603 value of the NUM_BYTES parameter in the .comm directive. It's not
8604 possible to use the .align directive as it doesn't affect the alignment
8605 of the label associated with a .comm directive. */
8608 pa_asm_output_aligned_common (FILE *stream,
8610 unsigned HOST_WIDE_INT size,
8613 unsigned int max_common_align;
8615 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8616 if (align > max_common_align)
8618 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8619 "for global common data. Using %u",
8620 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8621 align = max_common_align;
8624 switch_to_section (bss_section);
8626 assemble_name (stream, name);
8627 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8628 MAX (size, align / BITS_PER_UNIT));
8631 /* We can't use .comm for local common storage as the SOM linker effectively
8632 treats the symbol as universal and uses the same storage for local symbols
8633 with the same name in different object files. The .block directive
8634 reserves an uninitialized block of storage. However, it's not common
8635 storage. Fortunately, GCC never requests common storage with the same
8636 name in any given translation unit. */
8639 pa_asm_output_aligned_local (FILE *stream,
8641 unsigned HOST_WIDE_INT size,
8644 switch_to_section (bss_section);
8645 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8648 fprintf (stream, "%s", LOCAL_ASM_OP);
8649 assemble_name (stream, name);
8650 fprintf (stream, "\n");
8653 ASM_OUTPUT_LABEL (stream, name);
8654 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8657 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8658 use in fmpysub instructions. */
8660 pa_fmpysuboperands (rtx *operands)
8662 enum machine_mode mode = GET_MODE (operands[0]);
8664 /* Must be a floating point mode. */
8665 if (mode != SFmode && mode != DFmode)
8668 /* All modes must be the same. */
8669 if (! (mode == GET_MODE (operands[1])
8670 && mode == GET_MODE (operands[2])
8671 && mode == GET_MODE (operands[3])
8672 && mode == GET_MODE (operands[4])
8673 && mode == GET_MODE (operands[5])))
8676 /* All operands must be registers. */
8677 if (! (GET_CODE (operands[1]) == REG
8678 && GET_CODE (operands[2]) == REG
8679 && GET_CODE (operands[3]) == REG
8680 && GET_CODE (operands[4]) == REG
8681 && GET_CODE (operands[5]) == REG))
8684 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8685 operation, so operands[4] must be the same as operand[3]. */
8686 if (! rtx_equal_p (operands[3], operands[4]))
8689 /* multiply cannot feed into subtraction. */
8690 if (rtx_equal_p (operands[5], operands[0]))
8693 /* Inout operand of sub cannot conflict with any operands from multiply. */
8694 if (rtx_equal_p (operands[3], operands[0])
8695 || rtx_equal_p (operands[3], operands[1])
8696 || rtx_equal_p (operands[3], operands[2]))
8699 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8701 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8702 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8703 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8704 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8705 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8706 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8709 /* Passed. Operands are suitable for fmpysub. */
8713 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8714 constants for shadd instructions. */
8716 pa_shadd_constant_p (int val)
8718 if (val == 2 || val == 4 || val == 8)
8724 /* Return TRUE if INSN branches forward. */
8727 forward_branch_p (rtx insn)
8729 rtx lab = JUMP_LABEL (insn);
8731 /* The INSN must have a jump label. */
8732 gcc_assert (lab != NULL_RTX);
8734 if (INSN_ADDRESSES_SET_P ())
8735 return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn));
8742 insn = NEXT_INSN (insn);
8748 /* Return 1 if INSN is in the delay slot of a call instruction. */
8750 pa_jump_in_call_delay (rtx insn)
8753 if (GET_CODE (insn) != JUMP_INSN)
8756 if (PREV_INSN (insn)
8757 && PREV_INSN (PREV_INSN (insn))
8758 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8760 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8762 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8763 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8770 /* Output an unconditional move and branch insn. */
8773 pa_output_parallel_movb (rtx *operands, rtx insn)
8775 int length = get_attr_length (insn);
8777 /* These are the cases in which we win. */
8779 return "mov%I1b,tr %1,%0,%2";
8781 /* None of the following cases win, but they don't lose either. */
8784 if (dbr_sequence_length () == 0)
8786 /* Nothing in the delay slot, fake it by putting the combined
8787 insn (the copy or add) in the delay slot of a bl. */
8788 if (GET_CODE (operands[1]) == CONST_INT)
8789 return "b %2\n\tldi %1,%0";
8791 return "b %2\n\tcopy %1,%0";
8795 /* Something in the delay slot, but we've got a long branch. */
8796 if (GET_CODE (operands[1]) == CONST_INT)
8797 return "ldi %1,%0\n\tb %2";
8799 return "copy %1,%0\n\tb %2";
8803 if (GET_CODE (operands[1]) == CONST_INT)
8804 output_asm_insn ("ldi %1,%0", operands);
8806 output_asm_insn ("copy %1,%0", operands);
8807 return pa_output_lbranch (operands[2], insn, 1);
8810 /* Output an unconditional add and branch insn. */
8813 pa_output_parallel_addb (rtx *operands, rtx insn)
8815 int length = get_attr_length (insn);
8817 /* To make life easy we want operand0 to be the shared input/output
8818 operand and operand1 to be the readonly operand. */
8819 if (operands[0] == operands[1])
8820 operands[1] = operands[2];
8822 /* These are the cases in which we win. */
8824 return "add%I1b,tr %1,%0,%3";
8826 /* None of the following cases win, but they don't lose either. */
8829 if (dbr_sequence_length () == 0)
8830 /* Nothing in the delay slot, fake it by putting the combined
8831 insn (the copy or add) in the delay slot of a bl. */
8832 return "b %3\n\tadd%I1 %1,%0,%0";
8834 /* Something in the delay slot, but we've got a long branch. */
8835 return "add%I1 %1,%0,%0\n\tb %3";
8838 output_asm_insn ("add%I1 %1,%0,%0", operands);
8839 return pa_output_lbranch (operands[3], insn, 1);
8842 /* Return nonzero if INSN (a jump insn) immediately follows a call
8843 to a named function. This is used to avoid filling the delay slot
8844 of the jump since it can usually be eliminated by modifying RP in
8845 the delay slot of the call. */
8848 pa_following_call (rtx insn)
8850 if (! TARGET_JUMP_IN_DELAY)
8853 /* Find the previous real insn, skipping NOTEs. */
8854 insn = PREV_INSN (insn);
8855 while (insn && GET_CODE (insn) == NOTE)
8856 insn = PREV_INSN (insn);
8858 /* Check for CALL_INSNs and millicode calls. */
8860 && ((GET_CODE (insn) == CALL_INSN
8861 && get_attr_type (insn) != TYPE_DYNCALL)
8862 || (GET_CODE (insn) == INSN
8863 && GET_CODE (PATTERN (insn)) != SEQUENCE
8864 && GET_CODE (PATTERN (insn)) != USE
8865 && GET_CODE (PATTERN (insn)) != CLOBBER
8866 && get_attr_type (insn) == TYPE_MILLI)))
8872 /* We use this hook to perform a PA specific optimization which is difficult
8873 to do in earlier passes.
8875 We want the delay slots of branches within jump tables to be filled.
8876 None of the compiler passes at the moment even has the notion that a
8877 PA jump table doesn't contain addresses, but instead contains actual
8880 Because we actually jump into the table, the addresses of each entry
8881 must stay constant in relation to the beginning of the table (which
8882 itself must stay constant relative to the instruction to jump into
8883 it). I don't believe we can guarantee earlier passes of the compiler
8884 will adhere to those rules.
8886 So, late in the compilation process we find all the jump tables, and
8887 expand them into real code -- e.g. each entry in the jump table vector
8888 will get an appropriate label followed by a jump to the final target.
8890 Reorg and the final jump pass can then optimize these branches and
8891 fill their delay slots. We end up with smaller, more efficient code.
8893 The jump instructions within the table are special; we must be able
8894 to identify them during assembly output (if the jumps don't get filled
8895 we need to emit a nop rather than nullifying the delay slot)). We
8896 identify jumps in switch tables by using insns with the attribute
8897 type TYPE_BTABLE_BRANCH.
8899 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8900 insns. This serves two purposes, first it prevents jump.c from
8901 noticing that the last N entries in the table jump to the instruction
8902 immediately after the table and deleting the jumps. Second, those
8903 insns mark where we should emit .begin_brtab and .end_brtab directives
8904 when using GAS (allows for better link time optimizations). */
8911 remove_useless_addtr_insns (1);
8913 if (pa_cpu < PROCESSOR_8000)
8914 pa_combine_instructions ();
8917 /* This is fairly cheap, so always run it if optimizing. */
8918 if (optimize > 0 && !TARGET_BIG_SWITCH)
8920 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8921 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8923 rtx pattern, tmp, location, label;
8924 unsigned int length, i;
8926 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8927 if (GET_CODE (insn) != JUMP_INSN
8928 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8929 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8932 /* Emit marker for the beginning of the branch table. */
8933 emit_insn_before (gen_begin_brtab (), insn);
8935 pattern = PATTERN (insn);
8936 location = PREV_INSN (insn);
8937 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8939 for (i = 0; i < length; i++)
8941 /* Emit a label before each jump to keep jump.c from
8942 removing this code. */
8943 tmp = gen_label_rtx ();
8944 LABEL_NUSES (tmp) = 1;
8945 emit_label_after (tmp, location);
8946 location = NEXT_INSN (location);
8948 if (GET_CODE (pattern) == ADDR_VEC)
8949 label = XEXP (XVECEXP (pattern, 0, i), 0);
8951 label = XEXP (XVECEXP (pattern, 1, i), 0);
8953 tmp = gen_short_jump (label);
8955 /* Emit the jump itself. */
8956 tmp = emit_jump_insn_after (tmp, location);
8957 JUMP_LABEL (tmp) = label;
8958 LABEL_NUSES (label)++;
8959 location = NEXT_INSN (location);
8961 /* Emit a BARRIER after the jump. */
8962 emit_barrier_after (location);
8963 location = NEXT_INSN (location);
8966 /* Emit marker for the end of the branch table. */
8967 emit_insn_before (gen_end_brtab (), location);
8968 location = NEXT_INSN (location);
8969 emit_barrier_after (location);
8971 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8977 /* Still need brtab marker insns. FIXME: the presence of these
8978 markers disables output of the branch table to readonly memory,
8979 and any alignment directives that might be needed. Possibly,
8980 the begin_brtab insn should be output before the label for the
8981 table. This doesn't matter at the moment since the tables are
8982 always output in the text section. */
8983 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8985 /* Find an ADDR_VEC insn. */
8986 if (GET_CODE (insn) != JUMP_INSN
8987 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8988 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8991 /* Now generate markers for the beginning and end of the
8993 emit_insn_before (gen_begin_brtab (), insn);
8994 emit_insn_after (gen_end_brtab (), insn);
8999 /* The PA has a number of odd instructions which can perform multiple
9000 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
9001 it may be profitable to combine two instructions into one instruction
9002 with two outputs. It's not profitable PA2.0 machines because the
9003 two outputs would take two slots in the reorder buffers.
9005 This routine finds instructions which can be combined and combines
9006 them. We only support some of the potential combinations, and we
9007 only try common ways to find suitable instructions.
9009 * addb can add two registers or a register and a small integer
9010 and jump to a nearby (+-8k) location. Normally the jump to the
9011 nearby location is conditional on the result of the add, but by
9012 using the "true" condition we can make the jump unconditional.
9013 Thus addb can perform two independent operations in one insn.
9015 * movb is similar to addb in that it can perform a reg->reg
9016 or small immediate->reg copy and jump to a nearby (+-8k location).
9018 * fmpyadd and fmpysub can perform a FP multiply and either an
9019 FP add or FP sub if the operands of the multiply and add/sub are
9020 independent (there are other minor restrictions). Note both
9021 the fmpy and fadd/fsub can in theory move to better spots according
9022 to data dependencies, but for now we require the fmpy stay at a
9025 * Many of the memory operations can perform pre & post updates
9026 of index registers. GCC's pre/post increment/decrement addressing
9027 is far too simple to take advantage of all the possibilities. This
9028 pass may not be suitable since those insns may not be independent.
9030 * comclr can compare two ints or an int and a register, nullify
9031 the following instruction and zero some other register. This
9032 is more difficult to use as it's harder to find an insn which
9033 will generate a comclr than finding something like an unconditional
9034 branch. (conditional moves & long branches create comclr insns).
9036 * Most arithmetic operations can conditionally skip the next
9037 instruction. They can be viewed as "perform this operation
9038 and conditionally jump to this nearby location" (where nearby
9039 is an insns away). These are difficult to use due to the
9040 branch length restrictions. */
9043 pa_combine_instructions (void)
9045 rtx anchor, new_rtx;
9047 /* This can get expensive since the basic algorithm is on the
9048 order of O(n^2) (or worse). Only do it for -O2 or higher
9049 levels of optimization. */
9053 /* Walk down the list of insns looking for "anchor" insns which
9054 may be combined with "floating" insns. As the name implies,
9055 "anchor" instructions don't move, while "floating" insns may
9057 new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
9058 new_rtx = make_insn_raw (new_rtx);
9060 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
9062 enum attr_pa_combine_type anchor_attr;
9063 enum attr_pa_combine_type floater_attr;
9065 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
9066 Also ignore any special USE insns. */
9067 if ((GET_CODE (anchor) != INSN
9068 && GET_CODE (anchor) != JUMP_INSN
9069 && GET_CODE (anchor) != CALL_INSN)
9070 || GET_CODE (PATTERN (anchor)) == USE
9071 || GET_CODE (PATTERN (anchor)) == CLOBBER
9072 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
9073 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
9076 anchor_attr = get_attr_pa_combine_type (anchor);
9077 /* See if anchor is an insn suitable for combination. */
9078 if (anchor_attr == PA_COMBINE_TYPE_FMPY
9079 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
9080 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9081 && ! forward_branch_p (anchor)))
9085 for (floater = PREV_INSN (anchor);
9087 floater = PREV_INSN (floater))
9089 if (GET_CODE (floater) == NOTE
9090 || (GET_CODE (floater) == INSN
9091 && (GET_CODE (PATTERN (floater)) == USE
9092 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9095 /* Anything except a regular INSN will stop our search. */
9096 if (GET_CODE (floater) != INSN
9097 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9098 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9104 /* See if FLOATER is suitable for combination with the
9106 floater_attr = get_attr_pa_combine_type (floater);
9107 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9108 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9109 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9110 && floater_attr == PA_COMBINE_TYPE_FMPY))
9112 /* If ANCHOR and FLOATER can be combined, then we're
9113 done with this pass. */
9114 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9115 SET_DEST (PATTERN (floater)),
9116 XEXP (SET_SRC (PATTERN (floater)), 0),
9117 XEXP (SET_SRC (PATTERN (floater)), 1)))
9121 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9122 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
9124 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
9126 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9127 SET_DEST (PATTERN (floater)),
9128 XEXP (SET_SRC (PATTERN (floater)), 0),
9129 XEXP (SET_SRC (PATTERN (floater)), 1)))
9134 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9135 SET_DEST (PATTERN (floater)),
9136 SET_SRC (PATTERN (floater)),
9137 SET_SRC (PATTERN (floater))))
9143 /* If we didn't find anything on the backwards scan try forwards. */
9145 && (anchor_attr == PA_COMBINE_TYPE_FMPY
9146 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
9148 for (floater = anchor; floater; floater = NEXT_INSN (floater))
9150 if (GET_CODE (floater) == NOTE
9151 || (GET_CODE (floater) == INSN
9152 && (GET_CODE (PATTERN (floater)) == USE
9153 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9157 /* Anything except a regular INSN will stop our search. */
9158 if (GET_CODE (floater) != INSN
9159 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9160 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9166 /* See if FLOATER is suitable for combination with the
9168 floater_attr = get_attr_pa_combine_type (floater);
9169 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9170 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9171 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9172 && floater_attr == PA_COMBINE_TYPE_FMPY))
9174 /* If ANCHOR and FLOATER can be combined, then we're
9175 done with this pass. */
9176 if (pa_can_combine_p (new_rtx, anchor, floater, 1,
9177 SET_DEST (PATTERN (floater)),
9178 XEXP (SET_SRC (PATTERN (floater)),
9180 XEXP (SET_SRC (PATTERN (floater)),
9187 /* FLOATER will be nonzero if we found a suitable floating
9188 insn for combination with ANCHOR. */
9190 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9191 || anchor_attr == PA_COMBINE_TYPE_FMPY))
9193 /* Emit the new instruction and delete the old anchor. */
9194 emit_insn_before (gen_rtx_PARALLEL
9196 gen_rtvec (2, PATTERN (anchor),
9197 PATTERN (floater))),
9200 SET_INSN_DELETED (anchor);
9202 /* Emit a special USE insn for FLOATER, then delete
9203 the floating insn. */
9204 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9205 delete_insn (floater);
9210 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
9213 /* Emit the new_jump instruction and delete the old anchor. */
9215 = emit_jump_insn_before (gen_rtx_PARALLEL
9217 gen_rtvec (2, PATTERN (anchor),
9218 PATTERN (floater))),
9221 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
9222 SET_INSN_DELETED (anchor);
9224 /* Emit a special USE insn for FLOATER, then delete
9225 the floating insn. */
9226 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9227 delete_insn (floater);
9235 pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest,
9238 int insn_code_number;
9241 /* Create a PARALLEL with the patterns of ANCHOR and
9242 FLOATER, try to recognize it, then test constraints
9243 for the resulting pattern.
9245 If the pattern doesn't match or the constraints
9246 aren't met keep searching for a suitable floater
9248 XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor);
9249 XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater);
9250 INSN_CODE (new_rtx) = -1;
9251 insn_code_number = recog_memoized (new_rtx);
9252 if (insn_code_number < 0
9253 || (extract_insn (new_rtx), ! constrain_operands (1)))
9267 /* There's up to three operands to consider. One
9268 output and two inputs.
9270 The output must not be used between FLOATER & ANCHOR
9271 exclusive. The inputs must not be set between
9272 FLOATER and ANCHOR exclusive. */
9274 if (reg_used_between_p (dest, start, end))
9277 if (reg_set_between_p (src1, start, end))
9280 if (reg_set_between_p (src2, start, end))
9283 /* If we get here, then everything is good. */
9287 /* Return nonzero if references for INSN are delayed.
9289 Millicode insns are actually function calls with some special
9290 constraints on arguments and register usage.
9292 Millicode calls always expect their arguments in the integer argument
9293 registers, and always return their result in %r29 (ret1). They
9294 are expected to clobber their arguments, %r1, %r29, and the return
9295 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9297 This function tells reorg that the references to arguments and
9298 millicode calls do not appear to happen until after the millicode call.
9299 This allows reorg to put insns which set the argument registers into the
9300 delay slot of the millicode call -- thus they act more like traditional
9303 Note we cannot consider side effects of the insn to be delayed because
9304 the branch and link insn will clobber the return pointer. If we happened
9305 to use the return pointer in the delay slot of the call, then we lose.
9307 get_attr_type will try to recognize the given insn, so make sure to
9308 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9311 pa_insn_refs_are_delayed (rtx insn)
9313 return ((GET_CODE (insn) == INSN
9314 && GET_CODE (PATTERN (insn)) != SEQUENCE
9315 && GET_CODE (PATTERN (insn)) != USE
9316 && GET_CODE (PATTERN (insn)) != CLOBBER
9317 && get_attr_type (insn) == TYPE_MILLI));
9320 /* Promote the return value, but not the arguments. */
9322 static enum machine_mode
9323 pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
9324 enum machine_mode mode,
9325 int *punsignedp ATTRIBUTE_UNUSED,
9326 const_tree fntype ATTRIBUTE_UNUSED,
9329 if (for_return == 0)
9331 return promote_mode (type, mode, punsignedp);
9334 /* On the HP-PA the value is found in register(s) 28(-29), unless
9335 the mode is SF or DF. Then the value is returned in fr4 (32).
9337 This must perform the same promotions as PROMOTE_MODE, else promoting
9338 return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly.
9340 Small structures must be returned in a PARALLEL on PA64 in order
9341 to match the HP Compiler ABI. */
9344 pa_function_value (const_tree valtype,
9345 const_tree func ATTRIBUTE_UNUSED,
9346 bool outgoing ATTRIBUTE_UNUSED)
9348 enum machine_mode valmode;
9350 if (AGGREGATE_TYPE_P (valtype)
9351 || TREE_CODE (valtype) == COMPLEX_TYPE
9352 || TREE_CODE (valtype) == VECTOR_TYPE)
9356 /* Aggregates with a size less than or equal to 128 bits are
9357 returned in GR 28(-29). They are left justified. The pad
9358 bits are undefined. Larger aggregates are returned in
9362 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9364 for (i = 0; i < ub; i++)
9366 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9367 gen_rtx_REG (DImode, 28 + i),
9372 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9374 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9376 /* Aggregates 5 to 8 bytes in size are returned in general
9377 registers r28-r29 in the same manner as other non
9378 floating-point objects. The data is right-justified and
9379 zero-extended to 64 bits. This is opposite to the normal
9380 justification used on big endian targets and requires
9381 special treatment. */
9382 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9383 gen_rtx_REG (DImode, 28), const0_rtx);
9384 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9388 if ((INTEGRAL_TYPE_P (valtype)
9389 && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD)
9390 || POINTER_TYPE_P (valtype))
9391 valmode = word_mode;
9393 valmode = TYPE_MODE (valtype);
9395 if (TREE_CODE (valtype) == REAL_TYPE
9396 && !AGGREGATE_TYPE_P (valtype)
9397 && TYPE_MODE (valtype) != TFmode
9398 && !TARGET_SOFT_FLOAT)
9399 return gen_rtx_REG (valmode, 32);
9401 return gen_rtx_REG (valmode, 28);
9404 /* Implement the TARGET_LIBCALL_VALUE hook. */
9407 pa_libcall_value (enum machine_mode mode,
9408 const_rtx fun ATTRIBUTE_UNUSED)
9410 if (! TARGET_SOFT_FLOAT
9411 && (mode == SFmode || mode == DFmode))
9412 return gen_rtx_REG (mode, 32);
9414 return gen_rtx_REG (mode, 28);
9417 /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */
9420 pa_function_value_regno_p (const unsigned int regno)
9423 || (! TARGET_SOFT_FLOAT && regno == 32))
9429 /* Update the data in CUM to advance over an argument
9430 of mode MODE and data type TYPE.
9431 (TYPE is null for libcalls where that information may not be available.) */
9434 pa_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
9435 const_tree type, bool named ATTRIBUTE_UNUSED)
9437 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9438 int arg_size = FUNCTION_ARG_SIZE (mode, type);
9440 cum->nargs_prototype--;
9441 cum->words += (arg_size
9442 + ((cum->words & 01)
9443 && type != NULL_TREE
9447 /* Return the location of a parameter that is passed in a register or NULL
9448 if the parameter has any component that is passed in memory.
9450 This is new code and will be pushed to into the net sources after
9453 ??? We might want to restructure this so that it looks more like other
9456 pa_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
9457 const_tree type, bool named ATTRIBUTE_UNUSED)
9459 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9460 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9467 if (mode == VOIDmode)
9470 arg_size = FUNCTION_ARG_SIZE (mode, type);
9472 /* If this arg would be passed partially or totally on the stack, then
9473 this routine should return zero. pa_arg_partial_bytes will
9474 handle arguments which are split between regs and stack slots if
9475 the ABI mandates split arguments. */
9478 /* The 32-bit ABI does not split arguments. */
9479 if (cum->words + arg_size > max_arg_words)
9485 alignment = cum->words & 1;
9486 if (cum->words + alignment >= max_arg_words)
9490 /* The 32bit ABIs and the 64bit ABIs are rather different,
9491 particularly in their handling of FP registers. We might
9492 be able to cleverly share code between them, but I'm not
9493 going to bother in the hope that splitting them up results
9494 in code that is more easily understood. */
9498 /* Advance the base registers to their current locations.
9500 Remember, gprs grow towards smaller register numbers while
9501 fprs grow to higher register numbers. Also remember that
9502 although FP regs are 32-bit addressable, we pretend that
9503 the registers are 64-bits wide. */
9504 gpr_reg_base = 26 - cum->words;
9505 fpr_reg_base = 32 + cum->words;
9507 /* Arguments wider than one word and small aggregates need special
9511 || (type && (AGGREGATE_TYPE_P (type)
9512 || TREE_CODE (type) == COMPLEX_TYPE
9513 || TREE_CODE (type) == VECTOR_TYPE)))
9515 /* Double-extended precision (80-bit), quad-precision (128-bit)
9516 and aggregates including complex numbers are aligned on
9517 128-bit boundaries. The first eight 64-bit argument slots
9518 are associated one-to-one, with general registers r26
9519 through r19, and also with floating-point registers fr4
9520 through fr11. Arguments larger than one word are always
9521 passed in general registers.
9523 Using a PARALLEL with a word mode register results in left
9524 justified data on a big-endian target. */
9527 int i, offset = 0, ub = arg_size;
9529 /* Align the base register. */
9530 gpr_reg_base -= alignment;
9532 ub = MIN (ub, max_arg_words - cum->words - alignment);
9533 for (i = 0; i < ub; i++)
9535 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9536 gen_rtx_REG (DImode, gpr_reg_base),
9542 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9547 /* If the argument is larger than a word, then we know precisely
9548 which registers we must use. */
9562 /* Structures 5 to 8 bytes in size are passed in the general
9563 registers in the same manner as other non floating-point
9564 objects. The data is right-justified and zero-extended
9565 to 64 bits. This is opposite to the normal justification
9566 used on big endian targets and requires special treatment.
9567 We now define BLOCK_REG_PADDING to pad these objects.
9568 Aggregates, complex and vector types are passed in the same
9569 manner as structures. */
9571 || (type && (AGGREGATE_TYPE_P (type)
9572 || TREE_CODE (type) == COMPLEX_TYPE
9573 || TREE_CODE (type) == VECTOR_TYPE)))
9575 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9576 gen_rtx_REG (DImode, gpr_reg_base),
9578 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9583 /* We have a single word (32 bits). A simple computation
9584 will get us the register #s we need. */
9585 gpr_reg_base = 26 - cum->words;
9586 fpr_reg_base = 32 + 2 * cum->words;
9590 /* Determine if the argument needs to be passed in both general and
9591 floating point registers. */
9592 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9593 /* If we are doing soft-float with portable runtime, then there
9594 is no need to worry about FP regs. */
9595 && !TARGET_SOFT_FLOAT
9596 /* The parameter must be some kind of scalar float, else we just
9597 pass it in integer registers. */
9598 && GET_MODE_CLASS (mode) == MODE_FLOAT
9599 /* The target function must not have a prototype. */
9600 && cum->nargs_prototype <= 0
9601 /* libcalls do not need to pass items in both FP and general
9603 && type != NULL_TREE
9604 /* All this hair applies to "outgoing" args only. This includes
9605 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9607 /* Also pass outgoing floating arguments in both registers in indirect
9608 calls with the 32 bit ABI and the HP assembler since there is no
9609 way to the specify argument locations in static functions. */
9614 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9620 gen_rtx_EXPR_LIST (VOIDmode,
9621 gen_rtx_REG (mode, fpr_reg_base),
9623 gen_rtx_EXPR_LIST (VOIDmode,
9624 gen_rtx_REG (mode, gpr_reg_base),
9629 /* See if we should pass this parameter in a general register. */
9630 if (TARGET_SOFT_FLOAT
9631 /* Indirect calls in the normal 32bit ABI require all arguments
9632 to be passed in general registers. */
9633 || (!TARGET_PORTABLE_RUNTIME
9637 /* If the parameter is not a scalar floating-point parameter,
9638 then it belongs in GPRs. */
9639 || GET_MODE_CLASS (mode) != MODE_FLOAT
9640 /* Structure with single SFmode field belongs in GPR. */
9641 || (type && AGGREGATE_TYPE_P (type)))
9642 retval = gen_rtx_REG (mode, gpr_reg_base);
9644 retval = gen_rtx_REG (mode, fpr_reg_base);
9649 /* Arguments larger than one word are double word aligned. */
9652 pa_function_arg_boundary (enum machine_mode mode, const_tree type)
9654 bool singleword = (type
9655 ? (integer_zerop (TYPE_SIZE (type))
9656 || !TREE_CONSTANT (TYPE_SIZE (type))
9657 || int_size_in_bytes (type) <= UNITS_PER_WORD)
9658 : GET_MODE_SIZE (mode) <= UNITS_PER_WORD);
9660 return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY;
9663 /* If this arg would be passed totally in registers or totally on the stack,
9664 then this routine should return zero. */
9667 pa_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
9668 tree type, bool named ATTRIBUTE_UNUSED)
9670 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9671 unsigned int max_arg_words = 8;
9672 unsigned int offset = 0;
9677 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9680 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9681 /* Arg fits fully into registers. */
9683 else if (cum->words + offset >= max_arg_words)
9684 /* Arg fully on the stack. */
9688 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9692 /* A get_unnamed_section callback for switching to the text section.
9694 This function is only used with SOM. Because we don't support
9695 named subspaces, we can only create a new subspace or switch back
9696 to the default text subspace. */
9699 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9701 gcc_assert (TARGET_SOM);
9704 if (cfun && cfun->machine && !cfun->machine->in_nsubspa)
9706 /* We only want to emit a .nsubspa directive once at the
9707 start of the function. */
9708 cfun->machine->in_nsubspa = 1;
9710 /* Create a new subspace for the text. This provides
9711 better stub placement and one-only functions. */
9713 && DECL_ONE_ONLY (cfun->decl)
9714 && !DECL_WEAK (cfun->decl))
9716 output_section_asm_op ("\t.SPACE $TEXT$\n"
9717 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9718 "ACCESS=44,SORT=24,COMDAT");
9724 /* There isn't a current function or the body of the current
9725 function has been completed. So, we are changing to the
9726 text section to output debugging information. Thus, we
9727 need to forget that we are in the text section so that
9728 varasm.c will call us when text_section is selected again. */
9729 gcc_assert (!cfun || !cfun->machine
9730 || cfun->machine->in_nsubspa == 2);
9733 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9736 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9739 /* A get_unnamed_section callback for switching to comdat data
9740 sections. This function is only used with SOM. */
9743 som_output_comdat_data_section_asm_op (const void *data)
9746 output_section_asm_op (data);
9749 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9752 pa_som_asm_init_sections (void)
9755 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9757 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9758 is not being generated. */
9759 som_readonly_data_section
9760 = get_unnamed_section (0, output_section_asm_op,
9761 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9763 /* When secondary definitions are not supported, SOM makes readonly
9764 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9766 som_one_only_readonly_data_section
9767 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9769 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9770 "ACCESS=0x2c,SORT=16,COMDAT");
9773 /* When secondary definitions are not supported, SOM makes data one-only
9774 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9775 som_one_only_data_section
9776 = get_unnamed_section (SECTION_WRITE,
9777 som_output_comdat_data_section_asm_op,
9778 "\t.SPACE $PRIVATE$\n"
9779 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9780 "ACCESS=31,SORT=24,COMDAT");
9783 som_tm_clone_table_section
9784 = get_unnamed_section (0, output_section_asm_op,
9785 "\t.SPACE $PRIVATE$\n\t.SUBSPA $TM_CLONE_TABLE$");
9787 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9788 which reference data within the $TEXT$ space (for example constant
9789 strings in the $LIT$ subspace).
9791 The assemblers (GAS and HP as) both have problems with handling
9792 the difference of two symbols which is the other correct way to
9793 reference constant data during PIC code generation.
9795 So, there's no way to reference constant data which is in the
9796 $TEXT$ space during PIC generation. Instead place all constant
9797 data into the $PRIVATE$ subspace (this reduces sharing, but it
9798 works correctly). */
9799 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9801 /* We must not have a reference to an external symbol defined in a
9802 shared library in a readonly section, else the SOM linker will
9805 So, we force exception information into the data section. */
9806 exception_section = data_section;
9809 /* Implement TARGET_ASM_TM_CLONE_TABLE_SECTION. */
9812 pa_som_tm_clone_table_section (void)
9814 return som_tm_clone_table_section;
9817 /* On hpux10, the linker will give an error if we have a reference
9818 in the read-only data section to a symbol defined in a shared
9819 library. Therefore, expressions that might require a reloc can
9820 not be placed in the read-only data section. */
9823 pa_select_section (tree exp, int reloc,
9824 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9826 if (TREE_CODE (exp) == VAR_DECL
9827 && TREE_READONLY (exp)
9828 && !TREE_THIS_VOLATILE (exp)
9829 && DECL_INITIAL (exp)
9830 && (DECL_INITIAL (exp) == error_mark_node
9831 || TREE_CONSTANT (DECL_INITIAL (exp)))
9835 && DECL_ONE_ONLY (exp)
9836 && !DECL_WEAK (exp))
9837 return som_one_only_readonly_data_section;
9839 return readonly_data_section;
9841 else if (CONSTANT_CLASS_P (exp) && !reloc)
9842 return readonly_data_section;
9844 && TREE_CODE (exp) == VAR_DECL
9845 && DECL_ONE_ONLY (exp)
9846 && !DECL_WEAK (exp))
9847 return som_one_only_data_section;
9849 return data_section;
9853 pa_globalize_label (FILE *stream, const char *name)
9855 /* We only handle DATA objects here, functions are globalized in
9856 ASM_DECLARE_FUNCTION_NAME. */
9857 if (! FUNCTION_NAME_P (name))
9859 fputs ("\t.EXPORT ", stream);
9860 assemble_name (stream, name);
9861 fputs (",DATA\n", stream);
9865 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9868 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9869 int incoming ATTRIBUTE_UNUSED)
9871 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9874 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9877 pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
9879 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9880 PA64 ABI says that objects larger than 128 bits are returned in memory.
9881 Note, int_size_in_bytes can return -1 if the size of the object is
9882 variable or larger than the maximum value that can be expressed as
9883 a HOST_WIDE_INT. It can also return zero for an empty type. The
9884 simplest way to handle variable and empty types is to pass them in
9885 memory. This avoids problems in defining the boundaries of argument
9886 slots, allocating registers, etc. */
9887 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9888 || int_size_in_bytes (type) <= 0);
9891 /* Structure to hold declaration and name of external symbols that are
9892 emitted by GCC. We generate a vector of these symbols and output them
9893 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9894 This avoids putting out names that are never really used. */
9896 typedef struct GTY(()) extern_symbol
9902 /* Define gc'd vector type for extern_symbol. */
9903 DEF_VEC_O(extern_symbol);
9904 DEF_VEC_ALLOC_O(extern_symbol,gc);
9906 /* Vector of extern_symbol pointers. */
9907 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9909 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9910 /* Mark DECL (name NAME) as an external reference (assembler output
9911 file FILE). This saves the names to output at the end of the file
9912 if actually referenced. */
9915 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9917 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9919 gcc_assert (file == asm_out_file);
9924 /* Output text required at the end of an assembler file.
9925 This includes deferred plabels and .import directives for
9926 all external symbols that were actually referenced. */
9929 pa_hpux_file_end (void)
9934 if (!NO_DEFERRED_PROFILE_COUNTERS)
9935 output_deferred_profile_counters ();
9937 output_deferred_plabels ();
9939 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9941 tree decl = p->decl;
9943 if (!TREE_ASM_WRITTEN (decl)
9944 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9945 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9948 VEC_free (extern_symbol, gc, extern_symbols);
9952 /* Return true if a change from mode FROM to mode TO for a register
9953 in register class RCLASS is invalid. */
9956 pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9957 enum reg_class rclass)
9962 /* Reject changes to/from complex and vector modes. */
9963 if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from)
9964 || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to))
9967 if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to))
9970 /* There is no way to load QImode or HImode values directly from
9971 memory. SImode loads to the FP registers are not zero extended.
9972 On the 64-bit target, this conflicts with the definition of
9973 LOAD_EXTEND_OP. Thus, we can't allow changing between modes
9974 with different sizes in the floating-point registers. */
9975 if (MAYBE_FP_REG_CLASS_P (rclass))
9978 /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
9979 in specific sets of registers. Thus, we cannot allow changing
9980 to a larger mode when it's larger than a word. */
9981 if (GET_MODE_SIZE (to) > UNITS_PER_WORD
9982 && GET_MODE_SIZE (to) > GET_MODE_SIZE (from))
9988 /* Returns TRUE if it is a good idea to tie two pseudo registers
9989 when one has mode MODE1 and one has mode MODE2.
9990 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
9991 for any hard reg, then this must be FALSE for correct output.
9993 We should return FALSE for QImode and HImode because these modes
9994 are not ok in the floating-point registers. However, this prevents
9995 tieing these modes to SImode and DImode in the general registers.
9996 So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
9997 CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
9998 in the floating-point registers. */
10001 pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10003 /* Don't tie modes in different classes. */
10004 if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2))
10011 /* Length in units of the trampoline instruction code. */
10013 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
10016 /* Output assembler code for a block containing the constant parts
10017 of a trampoline, leaving space for the variable parts.\
10019 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
10020 and then branches to the specified routine.
10022 This code template is copied from text segment to stack location
10023 and then patched with pa_trampoline_init to contain valid values,
10024 and then entered as a subroutine.
10026 It is best to keep this as small as possible to avoid having to
10027 flush multiple lines in the cache. */
10030 pa_asm_trampoline_template (FILE *f)
10034 fputs ("\tldw 36(%r22),%r21\n", f);
10035 fputs ("\tbb,>=,n %r21,30,.+16\n", f);
10036 if (ASSEMBLER_DIALECT == 0)
10037 fputs ("\tdepi 0,31,2,%r21\n", f);
10039 fputs ("\tdepwi 0,31,2,%r21\n", f);
10040 fputs ("\tldw 4(%r21),%r19\n", f);
10041 fputs ("\tldw 0(%r21),%r21\n", f);
10044 fputs ("\tbve (%r21)\n", f);
10045 fputs ("\tldw 40(%r22),%r29\n", f);
10046 fputs ("\t.word 0\n", f);
10047 fputs ("\t.word 0\n", f);
10051 fputs ("\tldsid (%r21),%r1\n", f);
10052 fputs ("\tmtsp %r1,%sr0\n", f);
10053 fputs ("\tbe 0(%sr0,%r21)\n", f);
10054 fputs ("\tldw 40(%r22),%r29\n", f);
10056 fputs ("\t.word 0\n", f);
10057 fputs ("\t.word 0\n", f);
10058 fputs ("\t.word 0\n", f);
10059 fputs ("\t.word 0\n", f);
10063 fputs ("\t.dword 0\n", f);
10064 fputs ("\t.dword 0\n", f);
10065 fputs ("\t.dword 0\n", f);
10066 fputs ("\t.dword 0\n", f);
10067 fputs ("\tmfia %r31\n", f);
10068 fputs ("\tldd 24(%r31),%r1\n", f);
10069 fputs ("\tldd 24(%r1),%r27\n", f);
10070 fputs ("\tldd 16(%r1),%r1\n", f);
10071 fputs ("\tbve (%r1)\n", f);
10072 fputs ("\tldd 32(%r31),%r31\n", f);
10073 fputs ("\t.dword 0 ; fptr\n", f);
10074 fputs ("\t.dword 0 ; static link\n", f);
10078 /* Emit RTL insns to initialize the variable parts of a trampoline.
10079 FNADDR is an RTX for the address of the function's pure code.
10080 CXT is an RTX for the static chain value for the function.
10082 Move the function address to the trampoline template at offset 36.
10083 Move the static chain value to trampoline template at offset 40.
10084 Move the trampoline address to trampoline template at offset 44.
10085 Move r19 to trampoline template at offset 48. The latter two
10086 words create a plabel for the indirect call to the trampoline.
10088 A similar sequence is used for the 64-bit port but the plabel is
10089 at the beginning of the trampoline.
10091 Finally, the cache entries for the trampoline code are flushed.
10092 This is necessary to ensure that the trampoline instruction sequence
10093 is written to memory prior to any attempts at prefetching the code
10097 pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
10099 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10100 rtx start_addr = gen_reg_rtx (Pmode);
10101 rtx end_addr = gen_reg_rtx (Pmode);
10102 rtx line_length = gen_reg_rtx (Pmode);
10105 emit_block_move (m_tramp, assemble_trampoline_template (),
10106 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
10107 r_tramp = force_reg (Pmode, XEXP (m_tramp, 0));
10111 tmp = adjust_address (m_tramp, Pmode, 36);
10112 emit_move_insn (tmp, fnaddr);
10113 tmp = adjust_address (m_tramp, Pmode, 40);
10114 emit_move_insn (tmp, chain_value);
10116 /* Create a fat pointer for the trampoline. */
10117 tmp = adjust_address (m_tramp, Pmode, 44);
10118 emit_move_insn (tmp, r_tramp);
10119 tmp = adjust_address (m_tramp, Pmode, 48);
10120 emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
10122 /* fdc and fic only use registers for the address to flush,
10123 they do not accept integer displacements. We align the
10124 start and end addresses to the beginning of their respective
10125 cache lines to minimize the number of lines flushed. */
10126 emit_insn (gen_andsi3 (start_addr, r_tramp,
10127 GEN_INT (-MIN_CACHELINE_SIZE)));
10128 tmp = force_reg (Pmode, plus_constant (r_tramp, TRAMPOLINE_CODE_SIZE-1));
10129 emit_insn (gen_andsi3 (end_addr, tmp,
10130 GEN_INT (-MIN_CACHELINE_SIZE)));
10131 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10132 emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));
10133 emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length,
10134 gen_reg_rtx (Pmode),
10135 gen_reg_rtx (Pmode)));
10139 tmp = adjust_address (m_tramp, Pmode, 56);
10140 emit_move_insn (tmp, fnaddr);
10141 tmp = adjust_address (m_tramp, Pmode, 64);
10142 emit_move_insn (tmp, chain_value);
10144 /* Create a fat pointer for the trampoline. */
10145 tmp = adjust_address (m_tramp, Pmode, 16);
10146 emit_move_insn (tmp, force_reg (Pmode, plus_constant (r_tramp, 32)));
10147 tmp = adjust_address (m_tramp, Pmode, 24);
10148 emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
10150 /* fdc and fic only use registers for the address to flush,
10151 they do not accept integer displacements. We align the
10152 start and end addresses to the beginning of their respective
10153 cache lines to minimize the number of lines flushed. */
10154 tmp = force_reg (Pmode, plus_constant (r_tramp, 32));
10155 emit_insn (gen_anddi3 (start_addr, tmp,
10156 GEN_INT (-MIN_CACHELINE_SIZE)));
10157 tmp = force_reg (Pmode, plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));
10158 emit_insn (gen_anddi3 (end_addr, tmp,
10159 GEN_INT (-MIN_CACHELINE_SIZE)));
10160 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10161 emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));
10162 emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length,
10163 gen_reg_rtx (Pmode),
10164 gen_reg_rtx (Pmode)));
10168 /* Perform any machine-specific adjustment in the address of the trampoline.
10169 ADDR contains the address that was passed to pa_trampoline_init.
10170 Adjust the trampoline address to point to the plabel at offset 44. */
10173 pa_trampoline_adjust_address (rtx addr)
10176 addr = memory_address (Pmode, plus_constant (addr, 46));
10181 pa_delegitimize_address (rtx orig_x)
10183 rtx x = delegitimize_mem_from_attrs (orig_x);
10185 if (GET_CODE (x) == LO_SUM
10186 && GET_CODE (XEXP (x, 1)) == UNSPEC
10187 && XINT (XEXP (x, 1), 1) == UNSPEC_DLTIND14R)
10188 return gen_const_mem (Pmode, XVECEXP (XEXP (x, 1), 0, 0));
10193 pa_internal_arg_pointer (void)
10195 /* The argument pointer and the hard frame pointer are the same in
10196 the 32-bit runtime, so we don't need a copy. */
10198 return copy_to_reg (virtual_incoming_args_rtx);
10200 return virtual_incoming_args_rtx;
10203 /* Given FROM and TO register numbers, say whether this elimination is allowed.
10204 Frame pointer elimination is automatically handled. */
10207 pa_can_eliminate (const int from, const int to)
10209 /* The argument cannot be eliminated in the 64-bit runtime. */
10210 if (TARGET_64BIT && from == ARG_POINTER_REGNUM)
10213 return (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM
10214 ? ! frame_pointer_needed
10218 /* Define the offset between two registers, FROM to be eliminated and its
10219 replacement TO, at the start of a routine. */
10221 pa_initial_elimination_offset (int from, int to)
10223 HOST_WIDE_INT offset;
10225 if ((from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM)
10226 && to == STACK_POINTER_REGNUM)
10227 offset = -pa_compute_frame_size (get_frame_size (), 0);
10228 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10231 gcc_unreachable ();
10237 pa_conditional_register_usage (void)
10241 if (!TARGET_64BIT && !TARGET_PA_11)
10243 for (i = 56; i <= FP_REG_LAST; i++)
10244 fixed_regs[i] = call_used_regs[i] = 1;
10245 for (i = 33; i < 56; i += 2)
10246 fixed_regs[i] = call_used_regs[i] = 1;
10248 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10250 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
10251 fixed_regs[i] = call_used_regs[i] = 1;
10254 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10257 /* Target hook for c_mode_for_suffix. */
10259 static enum machine_mode
10260 pa_c_mode_for_suffix (char suffix)
10262 if (HPUX_LONG_DOUBLE_LIBRARY)
10271 /* Target hook for function_section. */
10274 pa_function_section (tree decl, enum node_frequency freq,
10275 bool startup, bool exit)
10277 /* Put functions in text section if target doesn't have named sections. */
10278 if (!targetm_common.have_named_sections)
10279 return text_section;
10281 /* Force nested functions into the same section as the containing
10284 && DECL_SECTION_NAME (decl) == NULL_TREE
10285 && DECL_CONTEXT (decl) != NULL_TREE
10286 && TREE_CODE (DECL_CONTEXT (decl)) == FUNCTION_DECL
10287 && DECL_SECTION_NAME (DECL_CONTEXT (decl)) == NULL_TREE)
10288 return function_section (DECL_CONTEXT (decl));
10290 /* Otherwise, use the default function section. */
10291 return default_function_section (decl, freq, startup, exit);
10294 /* Implement TARGET_SECTION_TYPE_FLAGS. */
10296 static unsigned int
10297 pa_section_type_flags (tree decl, const char *name, int reloc)
10299 unsigned int flags;
10301 flags = default_section_type_flags (decl, name, reloc);
10303 /* Function labels are placed in the constant pool. This can
10304 cause a section conflict if decls are put in ".data.rel.ro"
10305 or ".data.rel.ro.local" using the __attribute__ construct. */
10306 if (strcmp (name, ".data.rel.ro") == 0
10307 || strcmp (name, ".data.rel.ro.local") == 0)
10308 flags |= SECTION_WRITE | SECTION_RELRO;