1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static bool pa_handle_option (size_t, const char *, int);
88 static int hppa_address_cost (rtx);
89 static bool hppa_rtx_costs (rtx, int, int, int *);
90 static inline rtx force_mode (enum machine_mode, rtx);
91 static void pa_reorg (void);
92 static void pa_combine_instructions (void);
93 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
94 static int forward_branch_p (rtx);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static bool pa_scalar_mode_supported_p (enum machine_mode);
127 static bool pa_commutative_p (rtx x, int outer_code);
128 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
129 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
141 #ifdef ASM_OUTPUT_EXTERNAL_REAL
142 static void pa_hpux_file_end (void);
144 #ifdef HPUX_LONG_DOUBLE_LIBRARY
145 static void pa_hpux_init_libfuncs (void);
147 static rtx pa_struct_value_rtx (tree, int);
148 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
150 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
152 static struct machine_function * pa_init_machine_status (void);
155 /* Save the operands last given to a compare for use when we
156 generate a scc or bcc insn. */
157 rtx hppa_compare_op0, hppa_compare_op1;
158 enum cmp_type hppa_branch_type;
160 /* Which cpu we are scheduling for. */
161 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
163 /* The UNIX standard to use for predefines and linking. */
164 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
166 /* Counts for the number of callee-saved general and floating point
167 registers which were saved by the current function's prologue. */
168 static int gr_saved, fr_saved;
170 static rtx find_addr_reg (rtx);
172 /* Keep track of the number of bytes we have output in the CODE subspace
173 during this compilation so we'll know when to emit inline long-calls. */
174 unsigned long total_code_bytes;
176 /* The last address of the previous function plus the number of bytes in
177 associated thunks that have been output. This is used to determine if
178 a thunk can use an IA-relative branch to reach its target function. */
179 static int last_address;
181 /* Variables to handle plabels that we discover are necessary at assembly
182 output time. They are output after the current function. */
183 struct deferred_plabel GTY(())
188 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
190 static size_t n_deferred_plabels = 0;
193 /* Initialize the GCC target structure. */
195 #undef TARGET_ASM_ALIGNED_HI_OP
196 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
197 #undef TARGET_ASM_ALIGNED_SI_OP
198 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
199 #undef TARGET_ASM_ALIGNED_DI_OP
200 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
201 #undef TARGET_ASM_UNALIGNED_HI_OP
202 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
203 #undef TARGET_ASM_UNALIGNED_SI_OP
204 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
205 #undef TARGET_ASM_UNALIGNED_DI_OP
206 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
207 #undef TARGET_ASM_INTEGER
208 #define TARGET_ASM_INTEGER pa_assemble_integer
210 #undef TARGET_ASM_FUNCTION_PROLOGUE
211 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
212 #undef TARGET_ASM_FUNCTION_EPILOGUE
213 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
215 #undef TARGET_SCHED_ADJUST_COST
216 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
217 #undef TARGET_SCHED_ADJUST_PRIORITY
218 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
219 #undef TARGET_SCHED_ISSUE_RATE
220 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
222 #undef TARGET_ENCODE_SECTION_INFO
223 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
224 #undef TARGET_STRIP_NAME_ENCODING
225 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
227 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
228 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
230 #undef TARGET_COMMUTATIVE_P
231 #define TARGET_COMMUTATIVE_P pa_commutative_p
233 #undef TARGET_ASM_OUTPUT_MI_THUNK
234 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
235 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
236 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
238 #undef TARGET_ASM_FILE_END
239 #ifdef ASM_OUTPUT_EXTERNAL_REAL
240 #define TARGET_ASM_FILE_END pa_hpux_file_end
242 #define TARGET_ASM_FILE_END output_deferred_plabels
245 #if !defined(USE_COLLECT2)
246 #undef TARGET_ASM_CONSTRUCTOR
247 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
248 #undef TARGET_ASM_DESTRUCTOR
249 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
252 #undef TARGET_DEFAULT_TARGET_FLAGS
253 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
254 #undef TARGET_HANDLE_OPTION
255 #define TARGET_HANDLE_OPTION pa_handle_option
257 #undef TARGET_INIT_BUILTINS
258 #define TARGET_INIT_BUILTINS pa_init_builtins
260 #undef TARGET_RTX_COSTS
261 #define TARGET_RTX_COSTS hppa_rtx_costs
262 #undef TARGET_ADDRESS_COST
263 #define TARGET_ADDRESS_COST hppa_address_cost
265 #undef TARGET_MACHINE_DEPENDENT_REORG
266 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
268 #ifdef HPUX_LONG_DOUBLE_LIBRARY
269 #undef TARGET_INIT_LIBFUNCS
270 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
273 #undef TARGET_PROMOTE_FUNCTION_RETURN
274 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
275 #undef TARGET_PROMOTE_PROTOTYPES
276 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
278 #undef TARGET_STRUCT_VALUE_RTX
279 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
280 #undef TARGET_RETURN_IN_MEMORY
281 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
282 #undef TARGET_MUST_PASS_IN_STACK
283 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
284 #undef TARGET_PASS_BY_REFERENCE
285 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
286 #undef TARGET_CALLEE_COPIES
287 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
288 #undef TARGET_ARG_PARTIAL_BYTES
289 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
291 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
292 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
293 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
294 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
296 #undef TARGET_SCALAR_MODE_SUPPORTED_P
297 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
299 #undef TARGET_CANNOT_FORCE_CONST_MEM
300 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
302 struct gcc_target targetm = TARGET_INITIALIZER;
304 /* Parse the -mfixed-range= option string. */
307 fix_range (const char *const_str)
310 char *str, *dash, *comma;
312 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
313 REG2 are either register names or register numbers. The effect
314 of this option is to mark the registers in the range from REG1 to
315 REG2 as ``fixed'' so they won't be used by the compiler. This is
316 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
318 i = strlen (const_str);
319 str = (char *) alloca (i + 1);
320 memcpy (str, const_str, i + 1);
324 dash = strchr (str, '-');
327 warning (0, "value of -mfixed-range must have form REG1-REG2");
332 comma = strchr (dash + 1, ',');
336 first = decode_reg_name (str);
339 warning (0, "unknown register name: %s", str);
343 last = decode_reg_name (dash + 1);
346 warning (0, "unknown register name: %s", dash + 1);
354 warning (0, "%s-%s is an empty range", str, dash + 1);
358 for (i = first; i <= last; ++i)
359 fixed_regs[i] = call_used_regs[i] = 1;
368 /* Check if all floating point registers have been fixed. */
369 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
374 target_flags |= MASK_DISABLE_FPREGS;
377 /* Implement TARGET_HANDLE_OPTION. */
380 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
385 case OPT_mpa_risc_1_0:
387 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
391 case OPT_mpa_risc_1_1:
393 target_flags &= ~MASK_PA_20;
394 target_flags |= MASK_PA_11;
397 case OPT_mpa_risc_2_0:
399 target_flags |= MASK_PA_11 | MASK_PA_20;
403 if (strcmp (arg, "8000") == 0)
404 pa_cpu = PROCESSOR_8000;
405 else if (strcmp (arg, "7100") == 0)
406 pa_cpu = PROCESSOR_7100;
407 else if (strcmp (arg, "700") == 0)
408 pa_cpu = PROCESSOR_700;
409 else if (strcmp (arg, "7100LC") == 0)
410 pa_cpu = PROCESSOR_7100LC;
411 else if (strcmp (arg, "7200") == 0)
412 pa_cpu = PROCESSOR_7200;
413 else if (strcmp (arg, "7300") == 0)
414 pa_cpu = PROCESSOR_7300;
419 case OPT_mfixed_range_:
429 #if TARGET_HPUX_10_10
435 #if TARGET_HPUX_11_11
447 override_options (void)
449 /* Unconditional branches in the delay slot are not compatible with dwarf2
450 call frame information. There is no benefit in using this optimization
451 on PA8000 and later processors. */
452 if (pa_cpu >= PROCESSOR_8000
453 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
454 || flag_unwind_tables)
455 target_flags &= ~MASK_JUMP_IN_DELAY;
457 if (flag_pic && TARGET_PORTABLE_RUNTIME)
459 warning (0, "PIC code generation is not supported in the portable runtime model");
462 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
464 warning (0, "PIC code generation is not compatible with fast indirect calls");
467 if (! TARGET_GAS && write_symbols != NO_DEBUG)
469 warning (0, "-g is only supported when using GAS on this processor,");
470 warning (0, "-g option disabled");
471 write_symbols = NO_DEBUG;
474 /* We only support the "big PIC" model now. And we always generate PIC
475 code when in 64bit mode. */
476 if (flag_pic == 1 || TARGET_64BIT)
479 /* We can't guarantee that .dword is available for 32-bit targets. */
480 if (UNITS_PER_WORD == 4)
481 targetm.asm_out.aligned_op.di = NULL;
483 /* The unaligned ops are only available when using GAS. */
486 targetm.asm_out.unaligned_op.hi = NULL;
487 targetm.asm_out.unaligned_op.si = NULL;
488 targetm.asm_out.unaligned_op.di = NULL;
491 init_machine_status = pa_init_machine_status;
495 pa_init_builtins (void)
497 #ifdef DONT_HAVE_FPUTC_UNLOCKED
498 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
499 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
503 /* Function to init struct machine_function.
504 This will be called, via a pointer variable,
505 from push_function_context. */
507 static struct machine_function *
508 pa_init_machine_status (void)
510 return ggc_alloc_cleared (sizeof (machine_function));
513 /* If FROM is a probable pointer register, mark TO as a probable
514 pointer register with the same pointer alignment as FROM. */
517 copy_reg_pointer (rtx to, rtx from)
519 if (REG_POINTER (from))
520 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
523 /* Return 1 if X contains a symbolic expression. We know these
524 expressions will have one of a few well defined forms, so
525 we need only check those forms. */
527 symbolic_expression_p (rtx x)
530 /* Strip off any HIGH. */
531 if (GET_CODE (x) == HIGH)
534 return (symbolic_operand (x, VOIDmode));
537 /* Accept any constant that can be moved in one instruction into a
540 cint_ok_for_move (HOST_WIDE_INT intval)
542 /* OK if ldo, ldil, or zdepi, can be used. */
543 return (CONST_OK_FOR_LETTER_P (intval, 'J')
544 || CONST_OK_FOR_LETTER_P (intval, 'N')
545 || CONST_OK_FOR_LETTER_P (intval, 'K'));
548 /* Return truth value of whether OP can be used as an operand in a
551 adddi3_operand (rtx op, enum machine_mode mode)
553 return (register_operand (op, mode)
554 || (GET_CODE (op) == CONST_INT
555 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
558 /* True iff zdepi can be used to generate this CONST_INT.
559 zdepi first sign extends a 5 bit signed number to a given field
560 length, then places this field anywhere in a zero. */
562 zdepi_cint_p (unsigned HOST_WIDE_INT x)
564 unsigned HOST_WIDE_INT lsb_mask, t;
566 /* This might not be obvious, but it's at least fast.
567 This function is critical; we don't have the time loops would take. */
569 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
570 /* Return true iff t is a power of two. */
571 return ((t & (t - 1)) == 0);
574 /* True iff depi or extru can be used to compute (reg & mask).
575 Accept bit pattern like these:
580 and_mask_p (unsigned HOST_WIDE_INT mask)
583 mask += mask & -mask;
584 return (mask & (mask - 1)) == 0;
587 /* True iff depi can be used to compute (reg | MASK). */
589 ior_mask_p (unsigned HOST_WIDE_INT mask)
591 mask += mask & -mask;
592 return (mask & (mask - 1)) == 0;
595 /* Legitimize PIC addresses. If the address is already
596 position-independent, we return ORIG. Newly generated
597 position-independent addresses go to REG. If we need more
598 than one register, we lose. */
601 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
605 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
607 /* Labels need special handling. */
608 if (pic_label_operand (orig, mode))
610 /* We do not want to go through the movXX expanders here since that
611 would create recursion.
613 Nor do we really want to call a generator for a named pattern
614 since that requires multiple patterns if we want to support
617 So instead we just emit the raw set, which avoids the movXX
618 expanders completely. */
619 mark_reg_pointer (reg, BITS_PER_UNIT);
620 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
621 current_function_uses_pic_offset_table = 1;
624 if (GET_CODE (orig) == SYMBOL_REF)
630 /* Before reload, allocate a temporary register for the intermediate
631 result. This allows the sequence to be deleted when the final
632 result is unused and the insns are trivially dead. */
633 tmp_reg = ((reload_in_progress || reload_completed)
634 ? reg : gen_reg_rtx (Pmode));
636 emit_move_insn (tmp_reg,
637 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
638 gen_rtx_HIGH (word_mode, orig)));
640 = gen_const_mem (Pmode,
641 gen_rtx_LO_SUM (Pmode, tmp_reg,
642 gen_rtx_UNSPEC (Pmode,
646 current_function_uses_pic_offset_table = 1;
647 mark_reg_pointer (reg, BITS_PER_UNIT);
648 insn = emit_move_insn (reg, pic_ref);
650 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
651 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
655 else if (GET_CODE (orig) == CONST)
659 if (GET_CODE (XEXP (orig, 0)) == PLUS
660 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
664 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
666 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
667 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
668 base == reg ? 0 : reg);
670 if (GET_CODE (orig) == CONST_INT)
672 if (INT_14_BITS (orig))
673 return plus_constant (base, INTVAL (orig));
674 orig = force_reg (Pmode, orig);
676 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
677 /* Likewise, should we set special REG_NOTEs here? */
683 static GTY(()) rtx gen_tls_tga;
686 gen_tls_get_addr (void)
689 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
694 hppa_tls_call (rtx arg)
698 ret = gen_reg_rtx (Pmode);
699 emit_library_call_value (gen_tls_get_addr (), ret,
700 LCT_CONST, Pmode, 1, arg, Pmode);
706 legitimize_tls_address (rtx addr)
708 rtx ret, insn, tmp, t1, t2, tp;
709 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
713 case TLS_MODEL_GLOBAL_DYNAMIC:
714 tmp = gen_reg_rtx (Pmode);
715 emit_insn (gen_tgd_load (tmp, addr));
716 ret = hppa_tls_call (tmp);
719 case TLS_MODEL_LOCAL_DYNAMIC:
720 ret = gen_reg_rtx (Pmode);
721 tmp = gen_reg_rtx (Pmode);
723 emit_insn (gen_tld_load (tmp, addr));
724 t1 = hppa_tls_call (tmp);
727 t2 = gen_reg_rtx (Pmode);
728 emit_libcall_block (insn, t2, t1,
729 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
731 emit_insn (gen_tld_offset_load (ret, addr, t2));
734 case TLS_MODEL_INITIAL_EXEC:
735 tp = gen_reg_rtx (Pmode);
736 tmp = gen_reg_rtx (Pmode);
737 ret = gen_reg_rtx (Pmode);
738 emit_insn (gen_tp_load (tp));
739 emit_insn (gen_tie_load (tmp, addr));
740 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
743 case TLS_MODEL_LOCAL_EXEC:
744 tp = gen_reg_rtx (Pmode);
745 ret = gen_reg_rtx (Pmode);
746 emit_insn (gen_tp_load (tp));
747 emit_insn (gen_tle_load (ret, addr, tp));
757 /* Try machine-dependent ways of modifying an illegitimate address
758 to be legitimate. If we find one, return the new, valid address.
759 This macro is used in only one place: `memory_address' in explow.c.
761 OLDX is the address as it was before break_out_memory_refs was called.
762 In some cases it is useful to look at this to decide what needs to be done.
764 MODE and WIN are passed so that this macro can use
765 GO_IF_LEGITIMATE_ADDRESS.
767 It is always safe for this macro to do nothing. It exists to recognize
768 opportunities to optimize the output.
770 For the PA, transform:
772 memory(X + <large int>)
776 if (<large int> & mask) >= 16
777 Y = (<large int> & ~mask) + mask + 1 Round up.
779 Y = (<large int> & ~mask) Round down.
781 memory (Z + (<large int> - Y));
783 This is for CSE to find several similar references, and only use one Z.
785 X can either be a SYMBOL_REF or REG, but because combine cannot
786 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
787 D will not fit in 14 bits.
789 MODE_FLOAT references allow displacements which fit in 5 bits, so use
792 MODE_INT references allow displacements which fit in 14 bits, so use
795 This relies on the fact that most mode MODE_FLOAT references will use FP
796 registers and most mode MODE_INT references will use integer registers.
797 (In the rare case of an FP register used in an integer MODE, we depend
798 on secondary reloads to clean things up.)
801 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
802 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
803 addressing modes to be used).
805 Put X and Z into registers. Then put the entire expression into
809 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
810 enum machine_mode mode)
814 /* We need to canonicalize the order of operands in unscaled indexed
815 addresses since the code that checks if an address is valid doesn't
816 always try both orders. */
817 if (!TARGET_NO_SPACE_REGS
818 && GET_CODE (x) == PLUS
819 && GET_MODE (x) == Pmode
820 && REG_P (XEXP (x, 0))
821 && REG_P (XEXP (x, 1))
822 && REG_POINTER (XEXP (x, 0))
823 && !REG_POINTER (XEXP (x, 1)))
824 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
826 if (PA_SYMBOL_REF_TLS_P (x))
827 return legitimize_tls_address (x);
829 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
831 /* Strip off CONST. */
832 if (GET_CODE (x) == CONST)
835 /* Special case. Get the SYMBOL_REF into a register and use indexing.
836 That should always be safe. */
837 if (GET_CODE (x) == PLUS
838 && GET_CODE (XEXP (x, 0)) == REG
839 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
841 rtx reg = force_reg (Pmode, XEXP (x, 1));
842 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
845 /* Note we must reject symbols which represent function addresses
846 since the assembler/linker can't handle arithmetic on plabels. */
847 if (GET_CODE (x) == PLUS
848 && GET_CODE (XEXP (x, 1)) == CONST_INT
849 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
850 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
851 || GET_CODE (XEXP (x, 0)) == REG))
853 rtx int_part, ptr_reg;
855 int offset = INTVAL (XEXP (x, 1));
858 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
859 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
861 /* Choose which way to round the offset. Round up if we
862 are >= halfway to the next boundary. */
863 if ((offset & mask) >= ((mask + 1) / 2))
864 newoffset = (offset & ~ mask) + mask + 1;
866 newoffset = (offset & ~ mask);
868 /* If the newoffset will not fit in 14 bits (ldo), then
869 handling this would take 4 or 5 instructions (2 to load
870 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
871 add the new offset and the SYMBOL_REF.) Combine can
872 not handle 4->2 or 5->2 combinations, so do not create
874 if (! VAL_14_BITS_P (newoffset)
875 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
877 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
880 gen_rtx_HIGH (Pmode, const_part));
883 gen_rtx_LO_SUM (Pmode,
884 tmp_reg, const_part));
888 if (! VAL_14_BITS_P (newoffset))
889 int_part = force_reg (Pmode, GEN_INT (newoffset));
891 int_part = GEN_INT (newoffset);
893 ptr_reg = force_reg (Pmode,
895 force_reg (Pmode, XEXP (x, 0)),
898 return plus_constant (ptr_reg, offset - newoffset);
901 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
903 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
904 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
905 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
906 && (OBJECT_P (XEXP (x, 1))
907 || GET_CODE (XEXP (x, 1)) == SUBREG)
908 && GET_CODE (XEXP (x, 1)) != CONST)
910 int val = INTVAL (XEXP (XEXP (x, 0), 1));
914 if (GET_CODE (reg1) != REG)
915 reg1 = force_reg (Pmode, force_operand (reg1, 0));
917 reg2 = XEXP (XEXP (x, 0), 0);
918 if (GET_CODE (reg2) != REG)
919 reg2 = force_reg (Pmode, force_operand (reg2, 0));
921 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
928 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
930 Only do so for floating point modes since this is more speculative
931 and we lose if it's an integer store. */
932 if (GET_CODE (x) == PLUS
933 && GET_CODE (XEXP (x, 0)) == PLUS
934 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
935 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
936 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
937 && (mode == SFmode || mode == DFmode))
940 /* First, try and figure out what to use as a base register. */
941 rtx reg1, reg2, base, idx, orig_base;
943 reg1 = XEXP (XEXP (x, 0), 1);
948 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
949 then emit_move_sequence will turn on REG_POINTER so we'll know
950 it's a base register below. */
951 if (GET_CODE (reg1) != REG)
952 reg1 = force_reg (Pmode, force_operand (reg1, 0));
954 if (GET_CODE (reg2) != REG)
955 reg2 = force_reg (Pmode, force_operand (reg2, 0));
957 /* Figure out what the base and index are. */
959 if (GET_CODE (reg1) == REG
960 && REG_POINTER (reg1))
963 orig_base = XEXP (XEXP (x, 0), 1);
964 idx = gen_rtx_PLUS (Pmode,
966 XEXP (XEXP (XEXP (x, 0), 0), 0),
967 XEXP (XEXP (XEXP (x, 0), 0), 1)),
970 else if (GET_CODE (reg2) == REG
971 && REG_POINTER (reg2))
974 orig_base = XEXP (x, 1);
981 /* If the index adds a large constant, try to scale the
982 constant so that it can be loaded with only one insn. */
983 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
984 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
985 / INTVAL (XEXP (XEXP (idx, 0), 1)))
986 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
988 /* Divide the CONST_INT by the scale factor, then add it to A. */
989 int val = INTVAL (XEXP (idx, 1));
991 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
992 reg1 = XEXP (XEXP (idx, 0), 0);
993 if (GET_CODE (reg1) != REG)
994 reg1 = force_reg (Pmode, force_operand (reg1, 0));
996 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
998 /* We can now generate a simple scaled indexed address. */
1001 (Pmode, gen_rtx_PLUS (Pmode,
1002 gen_rtx_MULT (Pmode, reg1,
1003 XEXP (XEXP (idx, 0), 1)),
1007 /* If B + C is still a valid base register, then add them. */
1008 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1009 && INTVAL (XEXP (idx, 1)) <= 4096
1010 && INTVAL (XEXP (idx, 1)) >= -4096)
1012 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1015 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1017 reg2 = XEXP (XEXP (idx, 0), 0);
1018 if (GET_CODE (reg2) != CONST_INT)
1019 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1021 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1022 gen_rtx_MULT (Pmode,
1028 /* Get the index into a register, then add the base + index and
1029 return a register holding the result. */
1031 /* First get A into a register. */
1032 reg1 = XEXP (XEXP (idx, 0), 0);
1033 if (GET_CODE (reg1) != REG)
1034 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1036 /* And get B into a register. */
1037 reg2 = XEXP (idx, 1);
1038 if (GET_CODE (reg2) != REG)
1039 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1041 reg1 = force_reg (Pmode,
1042 gen_rtx_PLUS (Pmode,
1043 gen_rtx_MULT (Pmode, reg1,
1044 XEXP (XEXP (idx, 0), 1)),
1047 /* Add the result to our base register and return. */
1048 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1052 /* Uh-oh. We might have an address for x[n-100000]. This needs
1053 special handling to avoid creating an indexed memory address
1054 with x-100000 as the base.
1056 If the constant part is small enough, then it's still safe because
1057 there is a guard page at the beginning and end of the data segment.
1059 Scaled references are common enough that we want to try and rearrange the
1060 terms so that we can use indexing for these addresses too. Only
1061 do the optimization for floatint point modes. */
1063 if (GET_CODE (x) == PLUS
1064 && symbolic_expression_p (XEXP (x, 1)))
1066 /* Ugly. We modify things here so that the address offset specified
1067 by the index expression is computed first, then added to x to form
1068 the entire address. */
1070 rtx regx1, regx2, regy1, regy2, y;
1072 /* Strip off any CONST. */
1074 if (GET_CODE (y) == CONST)
1077 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1079 /* See if this looks like
1080 (plus (mult (reg) (shadd_const))
1081 (const (plus (symbol_ref) (const_int))))
1083 Where const_int is small. In that case the const
1084 expression is a valid pointer for indexing.
1086 If const_int is big, but can be divided evenly by shadd_const
1087 and added to (reg). This allows more scaled indexed addresses. */
1088 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1089 && GET_CODE (XEXP (x, 0)) == MULT
1090 && GET_CODE (XEXP (y, 1)) == CONST_INT
1091 && INTVAL (XEXP (y, 1)) >= -4096
1092 && INTVAL (XEXP (y, 1)) <= 4095
1093 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1094 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1096 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1100 if (GET_CODE (reg1) != REG)
1101 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1103 reg2 = XEXP (XEXP (x, 0), 0);
1104 if (GET_CODE (reg2) != REG)
1105 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1107 return force_reg (Pmode,
1108 gen_rtx_PLUS (Pmode,
1109 gen_rtx_MULT (Pmode,
1114 else if ((mode == DFmode || mode == SFmode)
1115 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1116 && GET_CODE (XEXP (x, 0)) == MULT
1117 && GET_CODE (XEXP (y, 1)) == CONST_INT
1118 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1119 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1120 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1123 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1124 / INTVAL (XEXP (XEXP (x, 0), 1))));
1125 regx2 = XEXP (XEXP (x, 0), 0);
1126 if (GET_CODE (regx2) != REG)
1127 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1128 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1132 gen_rtx_PLUS (Pmode,
1133 gen_rtx_MULT (Pmode, regx2,
1134 XEXP (XEXP (x, 0), 1)),
1135 force_reg (Pmode, XEXP (y, 0))));
1137 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1138 && INTVAL (XEXP (y, 1)) >= -4096
1139 && INTVAL (XEXP (y, 1)) <= 4095)
1141 /* This is safe because of the guard page at the
1142 beginning and end of the data space. Just
1143 return the original address. */
1148 /* Doesn't look like one we can optimize. */
1149 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1150 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1151 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1152 regx1 = force_reg (Pmode,
1153 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1155 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1163 /* For the HPPA, REG and REG+CONST is cost 0
1164 and addresses involving symbolic constants are cost 2.
1166 PIC addresses are very expensive.
1168 It is no coincidence that this has the same structure
1169 as GO_IF_LEGITIMATE_ADDRESS. */
1172 hppa_address_cost (rtx X)
1174 switch (GET_CODE (X))
1187 /* Compute a (partial) cost for rtx X. Return true if the complete
1188 cost has been computed, and false if subexpressions should be
1189 scanned. In either case, *TOTAL contains the cost result. */
1192 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1197 if (INTVAL (x) == 0)
1199 else if (INT_14_BITS (x))
1216 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1217 && outer_code != SET)
1224 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1225 *total = COSTS_N_INSNS (3);
1226 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1227 *total = COSTS_N_INSNS (8);
1229 *total = COSTS_N_INSNS (20);
1233 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1235 *total = COSTS_N_INSNS (14);
1243 *total = COSTS_N_INSNS (60);
1246 case PLUS: /* this includes shNadd insns */
1248 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1249 *total = COSTS_N_INSNS (3);
1251 *total = COSTS_N_INSNS (1);
1257 *total = COSTS_N_INSNS (1);
1265 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1266 new rtx with the correct mode. */
1268 force_mode (enum machine_mode mode, rtx orig)
1270 if (mode == GET_MODE (orig))
1273 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1275 return gen_rtx_REG (mode, REGNO (orig));
1278 /* Return 1 if *X is a thread-local symbol. */
1281 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1283 return PA_SYMBOL_REF_TLS_P (*x);
1286 /* Return 1 if X contains a thread-local symbol. */
1289 pa_tls_referenced_p (rtx x)
1291 if (!TARGET_HAVE_TLS)
1294 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1297 /* Emit insns to move operands[1] into operands[0].
1299 Return 1 if we have written out everything that needs to be done to
1300 do the move. Otherwise, return 0 and the caller will emit the move
1303 Note SCRATCH_REG may not be in the proper mode depending on how it
1304 will be used. This routine is responsible for creating a new copy
1305 of SCRATCH_REG in the proper mode. */
1308 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1310 register rtx operand0 = operands[0];
1311 register rtx operand1 = operands[1];
1314 /* We can only handle indexed addresses in the destination operand
1315 of floating point stores. Thus, we need to break out indexed
1316 addresses from the destination operand. */
1317 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1319 /* This is only safe up to the beginning of life analysis. */
1320 gcc_assert (!no_new_pseudos);
1322 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1323 operand0 = replace_equiv_address (operand0, tem);
1326 /* On targets with non-equivalent space registers, break out unscaled
1327 indexed addresses from the source operand before the final CSE.
1328 We have to do this because the REG_POINTER flag is not correctly
1329 carried through various optimization passes and CSE may substitute
1330 a pseudo without the pointer set for one with the pointer set. As
1331 a result, we loose various opportunities to create insns with
1332 unscaled indexed addresses. */
1333 if (!TARGET_NO_SPACE_REGS
1334 && !cse_not_expected
1335 && GET_CODE (operand1) == MEM
1336 && GET_CODE (XEXP (operand1, 0)) == PLUS
1337 && REG_P (XEXP (XEXP (operand1, 0), 0))
1338 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1340 = replace_equiv_address (operand1,
1341 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1344 && reload_in_progress && GET_CODE (operand0) == REG
1345 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1346 operand0 = reg_equiv_mem[REGNO (operand0)];
1347 else if (scratch_reg
1348 && reload_in_progress && GET_CODE (operand0) == SUBREG
1349 && GET_CODE (SUBREG_REG (operand0)) == REG
1350 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1352 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1353 the code which tracks sets/uses for delete_output_reload. */
1354 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1355 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1356 SUBREG_BYTE (operand0));
1357 operand0 = alter_subreg (&temp);
1361 && reload_in_progress && GET_CODE (operand1) == REG
1362 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1363 operand1 = reg_equiv_mem[REGNO (operand1)];
1364 else if (scratch_reg
1365 && reload_in_progress && GET_CODE (operand1) == SUBREG
1366 && GET_CODE (SUBREG_REG (operand1)) == REG
1367 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1369 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1370 the code which tracks sets/uses for delete_output_reload. */
1371 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1372 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1373 SUBREG_BYTE (operand1));
1374 operand1 = alter_subreg (&temp);
1377 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1378 && ((tem = find_replacement (&XEXP (operand0, 0)))
1379 != XEXP (operand0, 0)))
1380 operand0 = replace_equiv_address (operand0, tem);
1382 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1383 && ((tem = find_replacement (&XEXP (operand1, 0)))
1384 != XEXP (operand1, 0)))
1385 operand1 = replace_equiv_address (operand1, tem);
1387 /* Handle secondary reloads for loads/stores of FP registers from
1388 REG+D addresses where D does not fit in 5 or 14 bits, including
1389 (subreg (mem (addr))) cases. */
1391 && fp_reg_operand (operand0, mode)
1392 && ((GET_CODE (operand1) == MEM
1393 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1394 XEXP (operand1, 0)))
1395 || ((GET_CODE (operand1) == SUBREG
1396 && GET_CODE (XEXP (operand1, 0)) == MEM
1397 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1399 XEXP (XEXP (operand1, 0), 0))))))
1401 if (GET_CODE (operand1) == SUBREG)
1402 operand1 = XEXP (operand1, 0);
1404 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1405 it in WORD_MODE regardless of what mode it was originally given
1407 scratch_reg = force_mode (word_mode, scratch_reg);
1409 /* D might not fit in 14 bits either; for such cases load D into
1411 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1413 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1414 emit_move_insn (scratch_reg,
1415 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1417 XEXP (XEXP (operand1, 0), 0),
1421 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1422 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1423 replace_equiv_address (operand1, scratch_reg)));
1426 else if (scratch_reg
1427 && fp_reg_operand (operand1, mode)
1428 && ((GET_CODE (operand0) == MEM
1429 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1431 XEXP (operand0, 0)))
1432 || ((GET_CODE (operand0) == SUBREG)
1433 && GET_CODE (XEXP (operand0, 0)) == MEM
1434 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1436 XEXP (XEXP (operand0, 0), 0)))))
1438 if (GET_CODE (operand0) == SUBREG)
1439 operand0 = XEXP (operand0, 0);
1441 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1442 it in WORD_MODE regardless of what mode it was originally given
1444 scratch_reg = force_mode (word_mode, scratch_reg);
1446 /* D might not fit in 14 bits either; for such cases load D into
1448 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1450 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1451 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1454 XEXP (XEXP (operand0, 0),
1459 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1460 emit_insn (gen_rtx_SET (VOIDmode,
1461 replace_equiv_address (operand0, scratch_reg),
1465 /* Handle secondary reloads for loads of FP registers from constant
1466 expressions by forcing the constant into memory.
1468 Use scratch_reg to hold the address of the memory location.
1470 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1471 NO_REGS when presented with a const_int and a register class
1472 containing only FP registers. Doing so unfortunately creates
1473 more problems than it solves. Fix this for 2.5. */
1474 else if (scratch_reg
1475 && CONSTANT_P (operand1)
1476 && fp_reg_operand (operand0, mode))
1478 rtx const_mem, xoperands[2];
1480 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1481 it in WORD_MODE regardless of what mode it was originally given
1483 scratch_reg = force_mode (word_mode, scratch_reg);
1485 /* Force the constant into memory and put the address of the
1486 memory location into scratch_reg. */
1487 const_mem = force_const_mem (mode, operand1);
1488 xoperands[0] = scratch_reg;
1489 xoperands[1] = XEXP (const_mem, 0);
1490 emit_move_sequence (xoperands, Pmode, 0);
1492 /* Now load the destination register. */
1493 emit_insn (gen_rtx_SET (mode, operand0,
1494 replace_equiv_address (const_mem, scratch_reg)));
1497 /* Handle secondary reloads for SAR. These occur when trying to load
1498 the SAR from memory, FP register, or with a constant. */
1499 else if (scratch_reg
1500 && GET_CODE (operand0) == REG
1501 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1502 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1503 && (GET_CODE (operand1) == MEM
1504 || GET_CODE (operand1) == CONST_INT
1505 || (GET_CODE (operand1) == REG
1506 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1508 /* D might not fit in 14 bits either; for such cases load D into
1510 if (GET_CODE (operand1) == MEM
1511 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1513 /* We are reloading the address into the scratch register, so we
1514 want to make sure the scratch register is a full register. */
1515 scratch_reg = force_mode (word_mode, scratch_reg);
1517 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1518 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1521 XEXP (XEXP (operand1, 0),
1525 /* Now we are going to load the scratch register from memory,
1526 we want to load it in the same width as the original MEM,
1527 which must be the same as the width of the ultimate destination,
1529 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1531 emit_move_insn (scratch_reg,
1532 replace_equiv_address (operand1, scratch_reg));
1536 /* We want to load the scratch register using the same mode as
1537 the ultimate destination. */
1538 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1540 emit_move_insn (scratch_reg, operand1);
1543 /* And emit the insn to set the ultimate destination. We know that
1544 the scratch register has the same mode as the destination at this
1546 emit_move_insn (operand0, scratch_reg);
1549 /* Handle the most common case: storing into a register. */
1550 else if (register_operand (operand0, mode))
1552 if (register_operand (operand1, mode)
1553 || (GET_CODE (operand1) == CONST_INT
1554 && cint_ok_for_move (INTVAL (operand1)))
1555 || (operand1 == CONST0_RTX (mode))
1556 || (GET_CODE (operand1) == HIGH
1557 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1558 /* Only `general_operands' can come here, so MEM is ok. */
1559 || GET_CODE (operand1) == MEM)
1561 /* Various sets are created during RTL generation which don't
1562 have the REG_POINTER flag correctly set. After the CSE pass,
1563 instruction recognition can fail if we don't consistently
1564 set this flag when performing register copies. This should
1565 also improve the opportunities for creating insns that use
1566 unscaled indexing. */
1567 if (REG_P (operand0) && REG_P (operand1))
1569 if (REG_POINTER (operand1)
1570 && !REG_POINTER (operand0)
1571 && !HARD_REGISTER_P (operand0))
1572 copy_reg_pointer (operand0, operand1);
1573 else if (REG_POINTER (operand0)
1574 && !REG_POINTER (operand1)
1575 && !HARD_REGISTER_P (operand1))
1576 copy_reg_pointer (operand1, operand0);
1579 /* When MEMs are broken out, the REG_POINTER flag doesn't
1580 get set. In some cases, we can set the REG_POINTER flag
1581 from the declaration for the MEM. */
1582 if (REG_P (operand0)
1583 && GET_CODE (operand1) == MEM
1584 && !REG_POINTER (operand0))
1586 tree decl = MEM_EXPR (operand1);
1588 /* Set the register pointer flag and register alignment
1589 if the declaration for this memory reference is a
1590 pointer type. Fortran indirect argument references
1593 && !(flag_argument_noalias > 1
1594 && TREE_CODE (decl) == INDIRECT_REF
1595 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1599 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1601 if (TREE_CODE (decl) == COMPONENT_REF)
1602 decl = TREE_OPERAND (decl, 1);
1604 type = TREE_TYPE (decl);
1605 if (TREE_CODE (type) == ARRAY_TYPE)
1606 type = get_inner_array_type (type);
1608 if (POINTER_TYPE_P (type))
1612 type = TREE_TYPE (type);
1613 /* Using TYPE_ALIGN_OK is rather conservative as
1614 only the ada frontend actually sets it. */
1615 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1617 mark_reg_pointer (operand0, align);
1622 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1626 else if (GET_CODE (operand0) == MEM)
1628 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1629 && !(reload_in_progress || reload_completed))
1631 rtx temp = gen_reg_rtx (DFmode);
1633 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1634 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1637 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1639 /* Run this case quickly. */
1640 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1643 if (! (reload_in_progress || reload_completed))
1645 operands[0] = validize_mem (operand0);
1646 operands[1] = operand1 = force_reg (mode, operand1);
1650 /* Simplify the source if we need to.
1651 Note we do have to handle function labels here, even though we do
1652 not consider them legitimate constants. Loop optimizations can
1653 call the emit_move_xxx with one as a source. */
1654 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1655 || function_label_operand (operand1, mode)
1656 || (GET_CODE (operand1) == HIGH
1657 && symbolic_operand (XEXP (operand1, 0), mode)))
1661 if (GET_CODE (operand1) == HIGH)
1664 operand1 = XEXP (operand1, 0);
1666 if (symbolic_operand (operand1, mode))
1668 /* Argh. The assembler and linker can't handle arithmetic
1671 So we force the plabel into memory, load operand0 from
1672 the memory location, then add in the constant part. */
1673 if ((GET_CODE (operand1) == CONST
1674 && GET_CODE (XEXP (operand1, 0)) == PLUS
1675 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1676 || function_label_operand (operand1, mode))
1678 rtx temp, const_part;
1680 /* Figure out what (if any) scratch register to use. */
1681 if (reload_in_progress || reload_completed)
1683 scratch_reg = scratch_reg ? scratch_reg : operand0;
1684 /* SCRATCH_REG will hold an address and maybe the actual
1685 data. We want it in WORD_MODE regardless of what mode it
1686 was originally given to us. */
1687 scratch_reg = force_mode (word_mode, scratch_reg);
1690 scratch_reg = gen_reg_rtx (Pmode);
1692 if (GET_CODE (operand1) == CONST)
1694 /* Save away the constant part of the expression. */
1695 const_part = XEXP (XEXP (operand1, 0), 1);
1696 gcc_assert (GET_CODE (const_part) == CONST_INT);
1698 /* Force the function label into memory. */
1699 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1703 /* No constant part. */
1704 const_part = NULL_RTX;
1706 /* Force the function label into memory. */
1707 temp = force_const_mem (mode, operand1);
1711 /* Get the address of the memory location. PIC-ify it if
1713 temp = XEXP (temp, 0);
1715 temp = legitimize_pic_address (temp, mode, scratch_reg);
1717 /* Put the address of the memory location into our destination
1720 emit_move_sequence (operands, mode, scratch_reg);
1722 /* Now load from the memory location into our destination
1724 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1725 emit_move_sequence (operands, mode, scratch_reg);
1727 /* And add back in the constant part. */
1728 if (const_part != NULL_RTX)
1729 expand_inc (operand0, const_part);
1738 if (reload_in_progress || reload_completed)
1740 temp = scratch_reg ? scratch_reg : operand0;
1741 /* TEMP will hold an address and maybe the actual
1742 data. We want it in WORD_MODE regardless of what mode it
1743 was originally given to us. */
1744 temp = force_mode (word_mode, temp);
1747 temp = gen_reg_rtx (Pmode);
1749 /* (const (plus (symbol) (const_int))) must be forced to
1750 memory during/after reload if the const_int will not fit
1752 if (GET_CODE (operand1) == CONST
1753 && GET_CODE (XEXP (operand1, 0)) == PLUS
1754 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1755 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1756 && (reload_completed || reload_in_progress)
1759 rtx const_mem = force_const_mem (mode, operand1);
1760 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1762 operands[1] = replace_equiv_address (const_mem, operands[1]);
1763 emit_move_sequence (operands, mode, temp);
1767 operands[1] = legitimize_pic_address (operand1, mode, temp);
1768 if (REG_P (operand0) && REG_P (operands[1]))
1769 copy_reg_pointer (operand0, operands[1]);
1770 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1773 /* On the HPPA, references to data space are supposed to use dp,
1774 register 27, but showing it in the RTL inhibits various cse
1775 and loop optimizations. */
1780 if (reload_in_progress || reload_completed)
1782 temp = scratch_reg ? scratch_reg : operand0;
1783 /* TEMP will hold an address and maybe the actual
1784 data. We want it in WORD_MODE regardless of what mode it
1785 was originally given to us. */
1786 temp = force_mode (word_mode, temp);
1789 temp = gen_reg_rtx (mode);
1791 /* Loading a SYMBOL_REF into a register makes that register
1792 safe to be used as the base in an indexed address.
1794 Don't mark hard registers though. That loses. */
1795 if (GET_CODE (operand0) == REG
1796 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1797 mark_reg_pointer (operand0, BITS_PER_UNIT);
1798 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1799 mark_reg_pointer (temp, BITS_PER_UNIT);
1802 set = gen_rtx_SET (mode, operand0, temp);
1804 set = gen_rtx_SET (VOIDmode,
1806 gen_rtx_LO_SUM (mode, temp, operand1));
1808 emit_insn (gen_rtx_SET (VOIDmode,
1810 gen_rtx_HIGH (mode, operand1)));
1816 else if (pa_tls_referenced_p (operand1))
1821 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
1823 addend = XEXP (XEXP (tmp, 0), 1);
1824 tmp = XEXP (XEXP (tmp, 0), 0);
1827 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
1828 tmp = legitimize_tls_address (tmp);
1831 tmp = gen_rtx_PLUS (mode, tmp, addend);
1832 tmp = force_operand (tmp, operands[0]);
1836 else if (GET_CODE (operand1) != CONST_INT
1837 || !cint_ok_for_move (INTVAL (operand1)))
1841 HOST_WIDE_INT value = 0;
1842 HOST_WIDE_INT insv = 0;
1845 if (GET_CODE (operand1) == CONST_INT)
1846 value = INTVAL (operand1);
1849 && GET_CODE (operand1) == CONST_INT
1850 && HOST_BITS_PER_WIDE_INT > 32
1851 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1855 /* Extract the low order 32 bits of the value and sign extend.
1856 If the new value is the same as the original value, we can
1857 can use the original value as-is. If the new value is
1858 different, we use it and insert the most-significant 32-bits
1859 of the original value into the final result. */
1860 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1861 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1864 #if HOST_BITS_PER_WIDE_INT > 32
1865 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1869 operand1 = GEN_INT (nval);
1873 if (reload_in_progress || reload_completed)
1874 temp = scratch_reg ? scratch_reg : operand0;
1876 temp = gen_reg_rtx (mode);
1878 /* We don't directly split DImode constants on 32-bit targets
1879 because PLUS uses an 11-bit immediate and the insn sequence
1880 generated is not as efficient as the one using HIGH/LO_SUM. */
1881 if (GET_CODE (operand1) == CONST_INT
1882 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1885 /* Directly break constant into high and low parts. This
1886 provides better optimization opportunities because various
1887 passes recognize constants split with PLUS but not LO_SUM.
1888 We use a 14-bit signed low part except when the addition
1889 of 0x4000 to the high part might change the sign of the
1891 HOST_WIDE_INT low = value & 0x3fff;
1892 HOST_WIDE_INT high = value & ~ 0x3fff;
1896 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1904 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1905 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1909 emit_insn (gen_rtx_SET (VOIDmode, temp,
1910 gen_rtx_HIGH (mode, operand1)));
1911 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1914 insn = emit_move_insn (operands[0], operands[1]);
1916 /* Now insert the most significant 32 bits of the value
1917 into the register. When we don't have a second register
1918 available, it could take up to nine instructions to load
1919 a 64-bit integer constant. Prior to reload, we force
1920 constants that would take more than three instructions
1921 to load to the constant pool. During and after reload,
1922 we have to handle all possible values. */
1925 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
1926 register and the value to be inserted is outside the
1927 range that can be loaded with three depdi instructions. */
1928 if (temp != operand0 && (insv >= 16384 || insv < -16384))
1930 operand1 = GEN_INT (insv);
1932 emit_insn (gen_rtx_SET (VOIDmode, temp,
1933 gen_rtx_HIGH (mode, operand1)));
1934 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
1935 emit_insn (gen_insv (operand0, GEN_INT (32),
1940 int len = 5, pos = 27;
1942 /* Insert the bits using the depdi instruction. */
1945 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
1946 HOST_WIDE_INT sign = v5 < 0;
1948 /* Left extend the insertion. */
1949 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
1950 while (pos > 0 && (insv & 1) == sign)
1952 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
1957 emit_insn (gen_insv (operand0, GEN_INT (len),
1958 GEN_INT (pos), GEN_INT (v5)));
1960 len = pos > 0 && pos < 5 ? pos : 5;
1967 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
1972 /* Now have insn-emit do whatever it normally does. */
1976 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1977 it will need a link/runtime reloc). */
1980 reloc_needed (tree exp)
1984 switch (TREE_CODE (exp))
1991 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1992 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1997 case NON_LVALUE_EXPR:
1998 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2004 unsigned HOST_WIDE_INT ix;
2006 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2008 reloc |= reloc_needed (value);
2021 /* Does operand (which is a symbolic_operand) live in text space?
2022 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2026 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2028 if (GET_CODE (operand) == CONST)
2029 operand = XEXP (XEXP (operand, 0), 0);
2032 if (GET_CODE (operand) == SYMBOL_REF)
2033 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2037 if (GET_CODE (operand) == SYMBOL_REF)
2038 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2044 /* Return the best assembler insn template
2045 for moving operands[1] into operands[0] as a fullword. */
2047 singlemove_string (rtx *operands)
2049 HOST_WIDE_INT intval;
2051 if (GET_CODE (operands[0]) == MEM)
2052 return "stw %r1,%0";
2053 if (GET_CODE (operands[1]) == MEM)
2055 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2060 gcc_assert (GET_MODE (operands[1]) == SFmode);
2062 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2064 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2065 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2067 operands[1] = GEN_INT (i);
2068 /* Fall through to CONST_INT case. */
2070 if (GET_CODE (operands[1]) == CONST_INT)
2072 intval = INTVAL (operands[1]);
2074 if (VAL_14_BITS_P (intval))
2076 else if ((intval & 0x7ff) == 0)
2077 return "ldil L'%1,%0";
2078 else if (zdepi_cint_p (intval))
2079 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2081 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2083 return "copy %1,%0";
2087 /* Compute position (in OP[1]) and width (in OP[2])
2088 useful for copying IMM to a register using the zdepi
2089 instructions. Store the immediate value to insert in OP[0]. */
2091 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2095 /* Find the least significant set bit in IMM. */
2096 for (lsb = 0; lsb < 32; lsb++)
2103 /* Choose variants based on *sign* of the 5-bit field. */
2104 if ((imm & 0x10) == 0)
2105 len = (lsb <= 28) ? 4 : 32 - lsb;
2108 /* Find the width of the bitstring in IMM. */
2109 for (len = 5; len < 32; len++)
2111 if ((imm & (1 << len)) == 0)
2115 /* Sign extend IMM as a 5-bit value. */
2116 imm = (imm & 0xf) - 0x10;
2124 /* Compute position (in OP[1]) and width (in OP[2])
2125 useful for copying IMM to a register using the depdi,z
2126 instructions. Store the immediate value to insert in OP[0]. */
2128 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2130 HOST_WIDE_INT lsb, len;
2132 /* Find the least significant set bit in IMM. */
2133 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2140 /* Choose variants based on *sign* of the 5-bit field. */
2141 if ((imm & 0x10) == 0)
2142 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2143 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2146 /* Find the width of the bitstring in IMM. */
2147 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2149 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2153 /* Sign extend IMM as a 5-bit value. */
2154 imm = (imm & 0xf) - 0x10;
2162 /* Output assembler code to perform a doubleword move insn
2163 with operands OPERANDS. */
2166 output_move_double (rtx *operands)
2168 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2170 rtx addreg0 = 0, addreg1 = 0;
2172 /* First classify both operands. */
2174 if (REG_P (operands[0]))
2176 else if (offsettable_memref_p (operands[0]))
2178 else if (GET_CODE (operands[0]) == MEM)
2183 if (REG_P (operands[1]))
2185 else if (CONSTANT_P (operands[1]))
2187 else if (offsettable_memref_p (operands[1]))
2189 else if (GET_CODE (operands[1]) == MEM)
2194 /* Check for the cases that the operand constraints are not
2195 supposed to allow to happen. */
2196 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2198 /* Handle auto decrementing and incrementing loads and stores
2199 specifically, since the structure of the function doesn't work
2200 for them without major modification. Do it better when we learn
2201 this port about the general inc/dec addressing of PA.
2202 (This was written by tege. Chide him if it doesn't work.) */
2204 if (optype0 == MEMOP)
2206 /* We have to output the address syntax ourselves, since print_operand
2207 doesn't deal with the addresses we want to use. Fix this later. */
2209 rtx addr = XEXP (operands[0], 0);
2210 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2212 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2214 operands[0] = XEXP (addr, 0);
2215 gcc_assert (GET_CODE (operands[1]) == REG
2216 && GET_CODE (operands[0]) == REG);
2218 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2220 /* No overlap between high target register and address
2221 register. (We do this in a non-obvious way to
2222 save a register file writeback) */
2223 if (GET_CODE (addr) == POST_INC)
2224 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2225 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2227 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2229 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2231 operands[0] = XEXP (addr, 0);
2232 gcc_assert (GET_CODE (operands[1]) == REG
2233 && GET_CODE (operands[0]) == REG);
2235 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2236 /* No overlap between high target register and address
2237 register. (We do this in a non-obvious way to save a
2238 register file writeback) */
2239 if (GET_CODE (addr) == PRE_INC)
2240 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2241 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2244 if (optype1 == MEMOP)
2246 /* We have to output the address syntax ourselves, since print_operand
2247 doesn't deal with the addresses we want to use. Fix this later. */
2249 rtx addr = XEXP (operands[1], 0);
2250 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2252 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2254 operands[1] = XEXP (addr, 0);
2255 gcc_assert (GET_CODE (operands[0]) == REG
2256 && GET_CODE (operands[1]) == REG);
2258 if (!reg_overlap_mentioned_p (high_reg, addr))
2260 /* No overlap between high target register and address
2261 register. (We do this in a non-obvious way to
2262 save a register file writeback) */
2263 if (GET_CODE (addr) == POST_INC)
2264 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2265 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2269 /* This is an undefined situation. We should load into the
2270 address register *and* update that register. Probably
2271 we don't need to handle this at all. */
2272 if (GET_CODE (addr) == POST_INC)
2273 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2274 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2277 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2279 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2281 operands[1] = XEXP (addr, 0);
2282 gcc_assert (GET_CODE (operands[0]) == REG
2283 && GET_CODE (operands[1]) == REG);
2285 if (!reg_overlap_mentioned_p (high_reg, addr))
2287 /* No overlap between high target register and address
2288 register. (We do this in a non-obvious way to
2289 save a register file writeback) */
2290 if (GET_CODE (addr) == PRE_INC)
2291 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2292 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2296 /* This is an undefined situation. We should load into the
2297 address register *and* update that register. Probably
2298 we don't need to handle this at all. */
2299 if (GET_CODE (addr) == PRE_INC)
2300 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2301 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2304 else if (GET_CODE (addr) == PLUS
2305 && GET_CODE (XEXP (addr, 0)) == MULT)
2307 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2309 if (!reg_overlap_mentioned_p (high_reg, addr))
2313 xoperands[0] = high_reg;
2314 xoperands[1] = XEXP (addr, 1);
2315 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2316 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2317 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2319 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2325 xoperands[0] = high_reg;
2326 xoperands[1] = XEXP (addr, 1);
2327 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2328 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2329 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2331 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2336 /* If an operand is an unoffsettable memory ref, find a register
2337 we can increment temporarily to make it refer to the second word. */
2339 if (optype0 == MEMOP)
2340 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2342 if (optype1 == MEMOP)
2343 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2345 /* Ok, we can do one word at a time.
2346 Normally we do the low-numbered word first.
2348 In either case, set up in LATEHALF the operands to use
2349 for the high-numbered word and in some cases alter the
2350 operands in OPERANDS to be suitable for the low-numbered word. */
2352 if (optype0 == REGOP)
2353 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2354 else if (optype0 == OFFSOP)
2355 latehalf[0] = adjust_address (operands[0], SImode, 4);
2357 latehalf[0] = operands[0];
2359 if (optype1 == REGOP)
2360 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2361 else if (optype1 == OFFSOP)
2362 latehalf[1] = adjust_address (operands[1], SImode, 4);
2363 else if (optype1 == CNSTOP)
2364 split_double (operands[1], &operands[1], &latehalf[1]);
2366 latehalf[1] = operands[1];
2368 /* If the first move would clobber the source of the second one,
2369 do them in the other order.
2371 This can happen in two cases:
2373 mem -> register where the first half of the destination register
2374 is the same register used in the memory's address. Reload
2375 can create such insns.
2377 mem in this case will be either register indirect or register
2378 indirect plus a valid offset.
2380 register -> register move where REGNO(dst) == REGNO(src + 1)
2381 someone (Tim/Tege?) claimed this can happen for parameter loads.
2383 Handle mem -> register case first. */
2384 if (optype0 == REGOP
2385 && (optype1 == MEMOP || optype1 == OFFSOP)
2386 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2389 /* Do the late half first. */
2391 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2392 output_asm_insn (singlemove_string (latehalf), latehalf);
2396 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2397 return singlemove_string (operands);
2400 /* Now handle register -> register case. */
2401 if (optype0 == REGOP && optype1 == REGOP
2402 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2404 output_asm_insn (singlemove_string (latehalf), latehalf);
2405 return singlemove_string (operands);
2408 /* Normal case: do the two words, low-numbered first. */
2410 output_asm_insn (singlemove_string (operands), operands);
2412 /* Make any unoffsettable addresses point at high-numbered word. */
2414 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2416 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2419 output_asm_insn (singlemove_string (latehalf), latehalf);
2421 /* Undo the adds we just did. */
2423 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2425 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2431 output_fp_move_double (rtx *operands)
2433 if (FP_REG_P (operands[0]))
2435 if (FP_REG_P (operands[1])
2436 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2437 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2439 output_asm_insn ("fldd%F1 %1,%0", operands);
2441 else if (FP_REG_P (operands[1]))
2443 output_asm_insn ("fstd%F0 %1,%0", operands);
2449 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2451 /* This is a pain. You have to be prepared to deal with an
2452 arbitrary address here including pre/post increment/decrement.
2454 so avoid this in the MD. */
2455 gcc_assert (GET_CODE (operands[0]) == REG);
2457 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2458 xoperands[0] = operands[0];
2459 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2464 /* Return a REG that occurs in ADDR with coefficient 1.
2465 ADDR can be effectively incremented by incrementing REG. */
2468 find_addr_reg (rtx addr)
2470 while (GET_CODE (addr) == PLUS)
2472 if (GET_CODE (XEXP (addr, 0)) == REG)
2473 addr = XEXP (addr, 0);
2474 else if (GET_CODE (XEXP (addr, 1)) == REG)
2475 addr = XEXP (addr, 1);
2476 else if (CONSTANT_P (XEXP (addr, 0)))
2477 addr = XEXP (addr, 1);
2478 else if (CONSTANT_P (XEXP (addr, 1)))
2479 addr = XEXP (addr, 0);
2483 gcc_assert (GET_CODE (addr) == REG);
2487 /* Emit code to perform a block move.
2489 OPERANDS[0] is the destination pointer as a REG, clobbered.
2490 OPERANDS[1] is the source pointer as a REG, clobbered.
2491 OPERANDS[2] is a register for temporary storage.
2492 OPERANDS[3] is a register for temporary storage.
2493 OPERANDS[4] is the size as a CONST_INT
2494 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2495 OPERANDS[6] is another temporary register. */
2498 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2500 int align = INTVAL (operands[5]);
2501 unsigned long n_bytes = INTVAL (operands[4]);
2503 /* We can't move more than a word at a time because the PA
2504 has no longer integer move insns. (Could use fp mem ops?) */
2505 if (align > (TARGET_64BIT ? 8 : 4))
2506 align = (TARGET_64BIT ? 8 : 4);
2508 /* Note that we know each loop below will execute at least twice
2509 (else we would have open-coded the copy). */
2513 /* Pre-adjust the loop counter. */
2514 operands[4] = GEN_INT (n_bytes - 16);
2515 output_asm_insn ("ldi %4,%2", operands);
2518 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2519 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2520 output_asm_insn ("std,ma %3,8(%0)", operands);
2521 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2522 output_asm_insn ("std,ma %6,8(%0)", operands);
2524 /* Handle the residual. There could be up to 7 bytes of
2525 residual to copy! */
2526 if (n_bytes % 16 != 0)
2528 operands[4] = GEN_INT (n_bytes % 8);
2529 if (n_bytes % 16 >= 8)
2530 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2531 if (n_bytes % 8 != 0)
2532 output_asm_insn ("ldd 0(%1),%6", operands);
2533 if (n_bytes % 16 >= 8)
2534 output_asm_insn ("std,ma %3,8(%0)", operands);
2535 if (n_bytes % 8 != 0)
2536 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2541 /* Pre-adjust the loop counter. */
2542 operands[4] = GEN_INT (n_bytes - 8);
2543 output_asm_insn ("ldi %4,%2", operands);
2546 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2547 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2548 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2549 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2550 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2552 /* Handle the residual. There could be up to 7 bytes of
2553 residual to copy! */
2554 if (n_bytes % 8 != 0)
2556 operands[4] = GEN_INT (n_bytes % 4);
2557 if (n_bytes % 8 >= 4)
2558 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2559 if (n_bytes % 4 != 0)
2560 output_asm_insn ("ldw 0(%1),%6", operands);
2561 if (n_bytes % 8 >= 4)
2562 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2563 if (n_bytes % 4 != 0)
2564 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2569 /* Pre-adjust the loop counter. */
2570 operands[4] = GEN_INT (n_bytes - 4);
2571 output_asm_insn ("ldi %4,%2", operands);
2574 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2575 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2576 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2577 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2578 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2580 /* Handle the residual. */
2581 if (n_bytes % 4 != 0)
2583 if (n_bytes % 4 >= 2)
2584 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2585 if (n_bytes % 2 != 0)
2586 output_asm_insn ("ldb 0(%1),%6", operands);
2587 if (n_bytes % 4 >= 2)
2588 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2589 if (n_bytes % 2 != 0)
2590 output_asm_insn ("stb %6,0(%0)", operands);
2595 /* Pre-adjust the loop counter. */
2596 operands[4] = GEN_INT (n_bytes - 2);
2597 output_asm_insn ("ldi %4,%2", operands);
2600 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2601 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2602 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2603 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2604 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2606 /* Handle the residual. */
2607 if (n_bytes % 2 != 0)
2609 output_asm_insn ("ldb 0(%1),%3", operands);
2610 output_asm_insn ("stb %3,0(%0)", operands);
2619 /* Count the number of insns necessary to handle this block move.
2621 Basic structure is the same as emit_block_move, except that we
2622 count insns rather than emit them. */
2625 compute_movmem_length (rtx insn)
2627 rtx pat = PATTERN (insn);
2628 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2629 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2630 unsigned int n_insns = 0;
2632 /* We can't move more than four bytes at a time because the PA
2633 has no longer integer move insns. (Could use fp mem ops?) */
2634 if (align > (TARGET_64BIT ? 8 : 4))
2635 align = (TARGET_64BIT ? 8 : 4);
2637 /* The basic copying loop. */
2641 if (n_bytes % (2 * align) != 0)
2643 if ((n_bytes % (2 * align)) >= align)
2646 if ((n_bytes % align) != 0)
2650 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2654 /* Emit code to perform a block clear.
2656 OPERANDS[0] is the destination pointer as a REG, clobbered.
2657 OPERANDS[1] is a register for temporary storage.
2658 OPERANDS[2] is the size as a CONST_INT
2659 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2662 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2664 int align = INTVAL (operands[3]);
2665 unsigned long n_bytes = INTVAL (operands[2]);
2667 /* We can't clear more than a word at a time because the PA
2668 has no longer integer move insns. */
2669 if (align > (TARGET_64BIT ? 8 : 4))
2670 align = (TARGET_64BIT ? 8 : 4);
2672 /* Note that we know each loop below will execute at least twice
2673 (else we would have open-coded the copy). */
2677 /* Pre-adjust the loop counter. */
2678 operands[2] = GEN_INT (n_bytes - 16);
2679 output_asm_insn ("ldi %2,%1", operands);
2682 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2683 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2684 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2686 /* Handle the residual. There could be up to 7 bytes of
2687 residual to copy! */
2688 if (n_bytes % 16 != 0)
2690 operands[2] = GEN_INT (n_bytes % 8);
2691 if (n_bytes % 16 >= 8)
2692 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2693 if (n_bytes % 8 != 0)
2694 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2699 /* Pre-adjust the loop counter. */
2700 operands[2] = GEN_INT (n_bytes - 8);
2701 output_asm_insn ("ldi %2,%1", operands);
2704 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2705 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2706 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2708 /* Handle the residual. There could be up to 7 bytes of
2709 residual to copy! */
2710 if (n_bytes % 8 != 0)
2712 operands[2] = GEN_INT (n_bytes % 4);
2713 if (n_bytes % 8 >= 4)
2714 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2715 if (n_bytes % 4 != 0)
2716 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2721 /* Pre-adjust the loop counter. */
2722 operands[2] = GEN_INT (n_bytes - 4);
2723 output_asm_insn ("ldi %2,%1", operands);
2726 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2727 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2728 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2730 /* Handle the residual. */
2731 if (n_bytes % 4 != 0)
2733 if (n_bytes % 4 >= 2)
2734 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2735 if (n_bytes % 2 != 0)
2736 output_asm_insn ("stb %%r0,0(%0)", operands);
2741 /* Pre-adjust the loop counter. */
2742 operands[2] = GEN_INT (n_bytes - 2);
2743 output_asm_insn ("ldi %2,%1", operands);
2746 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2747 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2748 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2750 /* Handle the residual. */
2751 if (n_bytes % 2 != 0)
2752 output_asm_insn ("stb %%r0,0(%0)", operands);
2761 /* Count the number of insns necessary to handle this block move.
2763 Basic structure is the same as emit_block_move, except that we
2764 count insns rather than emit them. */
2767 compute_clrmem_length (rtx insn)
2769 rtx pat = PATTERN (insn);
2770 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2771 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2772 unsigned int n_insns = 0;
2774 /* We can't clear more than a word at a time because the PA
2775 has no longer integer move insns. */
2776 if (align > (TARGET_64BIT ? 8 : 4))
2777 align = (TARGET_64BIT ? 8 : 4);
2779 /* The basic loop. */
2783 if (n_bytes % (2 * align) != 0)
2785 if ((n_bytes % (2 * align)) >= align)
2788 if ((n_bytes % align) != 0)
2792 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2798 output_and (rtx *operands)
2800 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2802 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2803 int ls0, ls1, ms0, p, len;
2805 for (ls0 = 0; ls0 < 32; ls0++)
2806 if ((mask & (1 << ls0)) == 0)
2809 for (ls1 = ls0; ls1 < 32; ls1++)
2810 if ((mask & (1 << ls1)) != 0)
2813 for (ms0 = ls1; ms0 < 32; ms0++)
2814 if ((mask & (1 << ms0)) == 0)
2817 gcc_assert (ms0 == 32);
2825 operands[2] = GEN_INT (len);
2826 return "{extru|extrw,u} %1,31,%2,%0";
2830 /* We could use this `depi' for the case above as well, but `depi'
2831 requires one more register file access than an `extru'. */
2836 operands[2] = GEN_INT (p);
2837 operands[3] = GEN_INT (len);
2838 return "{depi|depwi} 0,%2,%3,%0";
2842 return "and %1,%2,%0";
2845 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2846 storing the result in operands[0]. */
2848 output_64bit_and (rtx *operands)
2850 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2852 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2853 int ls0, ls1, ms0, p, len;
2855 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2856 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2859 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2860 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2863 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2864 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2867 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2869 if (ls1 == HOST_BITS_PER_WIDE_INT)
2875 operands[2] = GEN_INT (len);
2876 return "extrd,u %1,63,%2,%0";
2880 /* We could use this `depi' for the case above as well, but `depi'
2881 requires one more register file access than an `extru'. */
2886 operands[2] = GEN_INT (p);
2887 operands[3] = GEN_INT (len);
2888 return "depdi 0,%2,%3,%0";
2892 return "and %1,%2,%0";
2896 output_ior (rtx *operands)
2898 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2899 int bs0, bs1, p, len;
2901 if (INTVAL (operands[2]) == 0)
2902 return "copy %1,%0";
2904 for (bs0 = 0; bs0 < 32; bs0++)
2905 if ((mask & (1 << bs0)) != 0)
2908 for (bs1 = bs0; bs1 < 32; bs1++)
2909 if ((mask & (1 << bs1)) == 0)
2912 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2917 operands[2] = GEN_INT (p);
2918 operands[3] = GEN_INT (len);
2919 return "{depi|depwi} -1,%2,%3,%0";
2922 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2923 storing the result in operands[0]. */
2925 output_64bit_ior (rtx *operands)
2927 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2928 int bs0, bs1, p, len;
2930 if (INTVAL (operands[2]) == 0)
2931 return "copy %1,%0";
2933 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2934 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2937 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2938 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2941 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
2942 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2947 operands[2] = GEN_INT (p);
2948 operands[3] = GEN_INT (len);
2949 return "depdi -1,%2,%3,%0";
2952 /* Target hook for assembling integer objects. This code handles
2953 aligned SI and DI integers specially since function references
2954 must be preceded by P%. */
2957 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
2959 if (size == UNITS_PER_WORD
2961 && function_label_operand (x, VOIDmode))
2963 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2964 output_addr_const (asm_out_file, x);
2965 fputc ('\n', asm_out_file);
2968 return default_assemble_integer (x, size, aligned_p);
2971 /* Output an ascii string. */
2973 output_ascii (FILE *file, const char *p, int size)
2977 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2979 /* The HP assembler can only take strings of 256 characters at one
2980 time. This is a limitation on input line length, *not* the
2981 length of the string. Sigh. Even worse, it seems that the
2982 restriction is in number of input characters (see \xnn &
2983 \whatever). So we have to do this very carefully. */
2985 fputs ("\t.STRING \"", file);
2988 for (i = 0; i < size; i += 4)
2992 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2994 register unsigned int c = (unsigned char) p[i + io];
2996 if (c == '\"' || c == '\\')
2997 partial_output[co++] = '\\';
2998 if (c >= ' ' && c < 0177)
2999 partial_output[co++] = c;
3003 partial_output[co++] = '\\';
3004 partial_output[co++] = 'x';
3005 hexd = c / 16 - 0 + '0';
3007 hexd -= '9' - 'a' + 1;
3008 partial_output[co++] = hexd;
3009 hexd = c % 16 - 0 + '0';
3011 hexd -= '9' - 'a' + 1;
3012 partial_output[co++] = hexd;
3015 if (chars_output + co > 243)
3017 fputs ("\"\n\t.STRING \"", file);
3020 fwrite (partial_output, 1, (size_t) co, file);
3024 fputs ("\"\n", file);
3027 /* Try to rewrite floating point comparisons & branches to avoid
3028 useless add,tr insns.
3030 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3031 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3032 first attempt to remove useless add,tr insns. It is zero
3033 for the second pass as reorg sometimes leaves bogus REG_DEAD
3036 When CHECK_NOTES is zero we can only eliminate add,tr insns
3037 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3040 remove_useless_addtr_insns (int check_notes)
3043 static int pass = 0;
3045 /* This is fairly cheap, so always run it when optimizing. */
3049 int fbranch_count = 0;
3051 /* Walk all the insns in this function looking for fcmp & fbranch
3052 instructions. Keep track of how many of each we find. */
3053 for (insn = get_insns (); insn; insn = next_insn (insn))
3057 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3058 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3061 tmp = PATTERN (insn);
3063 /* It must be a set. */
3064 if (GET_CODE (tmp) != SET)
3067 /* If the destination is CCFP, then we've found an fcmp insn. */
3068 tmp = SET_DEST (tmp);
3069 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3075 tmp = PATTERN (insn);
3076 /* If this is an fbranch instruction, bump the fbranch counter. */
3077 if (GET_CODE (tmp) == SET
3078 && SET_DEST (tmp) == pc_rtx
3079 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3080 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3081 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3082 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3090 /* Find all floating point compare + branch insns. If possible,
3091 reverse the comparison & the branch to avoid add,tr insns. */
3092 for (insn = get_insns (); insn; insn = next_insn (insn))
3096 /* Ignore anything that isn't an INSN. */
3097 if (GET_CODE (insn) != INSN)
3100 tmp = PATTERN (insn);
3102 /* It must be a set. */
3103 if (GET_CODE (tmp) != SET)
3106 /* The destination must be CCFP, which is register zero. */
3107 tmp = SET_DEST (tmp);
3108 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3111 /* INSN should be a set of CCFP.
3113 See if the result of this insn is used in a reversed FP
3114 conditional branch. If so, reverse our condition and
3115 the branch. Doing so avoids useless add,tr insns. */
3116 next = next_insn (insn);
3119 /* Jumps, calls and labels stop our search. */
3120 if (GET_CODE (next) == JUMP_INSN
3121 || GET_CODE (next) == CALL_INSN
3122 || GET_CODE (next) == CODE_LABEL)
3125 /* As does another fcmp insn. */
3126 if (GET_CODE (next) == INSN
3127 && GET_CODE (PATTERN (next)) == SET
3128 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3129 && REGNO (SET_DEST (PATTERN (next))) == 0)
3132 next = next_insn (next);
3135 /* Is NEXT_INSN a branch? */
3137 && GET_CODE (next) == JUMP_INSN)
3139 rtx pattern = PATTERN (next);
3141 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3142 and CCFP dies, then reverse our conditional and the branch
3143 to avoid the add,tr. */
3144 if (GET_CODE (pattern) == SET
3145 && SET_DEST (pattern) == pc_rtx
3146 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3147 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3148 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3149 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3150 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3151 && (fcmp_count == fbranch_count
3153 && find_regno_note (next, REG_DEAD, 0))))
3155 /* Reverse the branch. */
3156 tmp = XEXP (SET_SRC (pattern), 1);
3157 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3158 XEXP (SET_SRC (pattern), 2) = tmp;
3159 INSN_CODE (next) = -1;
3161 /* Reverse our condition. */
3162 tmp = PATTERN (insn);
3163 PUT_CODE (XEXP (tmp, 1),
3164 (reverse_condition_maybe_unordered
3165 (GET_CODE (XEXP (tmp, 1)))));
3175 /* You may have trouble believing this, but this is the 32 bit HP-PA
3180 Variable arguments (optional; any number may be allocated)
3182 SP-(4*(N+9)) arg word N
3187 Fixed arguments (must be allocated; may remain unused)
3196 SP-32 External Data Pointer (DP)
3198 SP-24 External/stub RP (RP')
3202 SP-8 Calling Stub RP (RP'')
3207 SP-0 Stack Pointer (points to next available address)
3211 /* This function saves registers as follows. Registers marked with ' are
3212 this function's registers (as opposed to the previous function's).
3213 If a frame_pointer isn't needed, r4 is saved as a general register;
3214 the space for the frame pointer is still allocated, though, to keep
3220 SP (FP') Previous FP
3221 SP + 4 Alignment filler (sigh)
3222 SP + 8 Space for locals reserved here.
3226 SP + n All call saved register used.
3230 SP + o All call saved fp registers used.
3234 SP + p (SP') points to next available address.
3238 /* Global variables set by output_function_prologue(). */
3239 /* Size of frame. Need to know this to emit return insns from
3241 static HOST_WIDE_INT actual_fsize, local_fsize;
3242 static int save_fregs;
3244 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3245 Handle case where DISP > 8k by using the add_high_const patterns.
3247 Note in DISP > 8k case, we will leave the high part of the address
3248 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3251 store_reg (int reg, HOST_WIDE_INT disp, int base)
3253 rtx insn, dest, src, basereg;
3255 src = gen_rtx_REG (word_mode, reg);
3256 basereg = gen_rtx_REG (Pmode, base);
3257 if (VAL_14_BITS_P (disp))
3259 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3260 insn = emit_move_insn (dest, src);
3262 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3264 rtx delta = GEN_INT (disp);
3265 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3267 emit_move_insn (tmpreg, delta);
3268 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3272 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3273 gen_rtx_SET (VOIDmode, tmpreg,
3274 gen_rtx_PLUS (Pmode, basereg, delta)),
3276 RTX_FRAME_RELATED_P (insn) = 1;
3278 dest = gen_rtx_MEM (word_mode, tmpreg);
3279 insn = emit_move_insn (dest, src);
3283 rtx delta = GEN_INT (disp);
3284 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3285 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3287 emit_move_insn (tmpreg, high);
3288 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3289 insn = emit_move_insn (dest, src);
3293 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3294 gen_rtx_SET (VOIDmode,
3295 gen_rtx_MEM (word_mode,
3296 gen_rtx_PLUS (word_mode, basereg,
3304 RTX_FRAME_RELATED_P (insn) = 1;
3307 /* Emit RTL to store REG at the memory location specified by BASE and then
3308 add MOD to BASE. MOD must be <= 8k. */
3311 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3313 rtx insn, basereg, srcreg, delta;
3315 gcc_assert (VAL_14_BITS_P (mod));
3317 basereg = gen_rtx_REG (Pmode, base);
3318 srcreg = gen_rtx_REG (word_mode, reg);
3319 delta = GEN_INT (mod);
3321 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3324 RTX_FRAME_RELATED_P (insn) = 1;
3326 /* RTX_FRAME_RELATED_P must be set on each frame related set
3327 in a parallel with more than one element. */
3328 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3329 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3333 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3334 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3335 whether to add a frame note or not.
3337 In the DISP > 8k case, we leave the high part of the address in %r1.
3338 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3341 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3345 if (VAL_14_BITS_P (disp))
3347 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3348 plus_constant (gen_rtx_REG (Pmode, base), disp));
3350 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3352 rtx basereg = gen_rtx_REG (Pmode, base);
3353 rtx delta = GEN_INT (disp);
3354 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3356 emit_move_insn (tmpreg, delta);
3357 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3358 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3361 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3362 gen_rtx_SET (VOIDmode, tmpreg,
3363 gen_rtx_PLUS (Pmode, basereg, delta)),
3368 rtx basereg = gen_rtx_REG (Pmode, base);
3369 rtx delta = GEN_INT (disp);
3370 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3372 emit_move_insn (tmpreg,
3373 gen_rtx_PLUS (Pmode, basereg,
3374 gen_rtx_HIGH (Pmode, delta)));
3375 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3376 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3379 if (DO_FRAME_NOTES && note)
3380 RTX_FRAME_RELATED_P (insn) = 1;
3384 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3389 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3390 be consistent with the rounding and size calculation done here.
3391 Change them at the same time. */
3393 /* We do our own stack alignment. First, round the size of the
3394 stack locals up to a word boundary. */
3395 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3397 /* Space for previous frame pointer + filler. If any frame is
3398 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3399 waste some space here for the sake of HP compatibility. The
3400 first slot is only used when the frame pointer is needed. */
3401 if (size || frame_pointer_needed)
3402 size += STARTING_FRAME_OFFSET;
3404 /* If the current function calls __builtin_eh_return, then we need
3405 to allocate stack space for registers that will hold data for
3406 the exception handler. */
3407 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3411 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3413 size += i * UNITS_PER_WORD;
3416 /* Account for space used by the callee general register saves. */
3417 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3418 if (regs_ever_live[i])
3419 size += UNITS_PER_WORD;
3421 /* Account for space used by the callee floating point register saves. */
3422 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3423 if (regs_ever_live[i]
3424 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3428 /* We always save both halves of the FP register, so always
3429 increment the frame size by 8 bytes. */
3433 /* If any of the floating registers are saved, account for the
3434 alignment needed for the floating point register save block. */
3437 size = (size + 7) & ~7;
3442 /* The various ABIs include space for the outgoing parameters in the
3443 size of the current function's stack frame. We don't need to align
3444 for the outgoing arguments as their alignment is set by the final
3445 rounding for the frame as a whole. */
3446 size += current_function_outgoing_args_size;
3448 /* Allocate space for the fixed frame marker. This space must be
3449 allocated for any function that makes calls or allocates
3451 if (!current_function_is_leaf || size)
3452 size += TARGET_64BIT ? 48 : 32;
3454 /* Finally, round to the preferred stack boundary. */
3455 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3456 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3459 /* Generate the assembly code for function entry. FILE is a stdio
3460 stream to output the code to. SIZE is an int: how many units of
3461 temporary storage to allocate.
3463 Refer to the array `regs_ever_live' to determine which registers to
3464 save; `regs_ever_live[I]' is nonzero if register number I is ever
3465 used in the function. This function is responsible for knowing
3466 which registers should not be saved even if used. */
3468 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3469 of memory. If any fpu reg is used in the function, we allocate
3470 such a block here, at the bottom of the frame, just in case it's needed.
3472 If this function is a leaf procedure, then we may choose not
3473 to do a "save" insn. The decision about whether or not
3474 to do this is made in regclass.c. */
3477 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3479 /* The function's label and associated .PROC must never be
3480 separated and must be output *after* any profiling declarations
3481 to avoid changing spaces/subspaces within a procedure. */
3482 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3483 fputs ("\t.PROC\n", file);
3485 /* hppa_expand_prologue does the dirty work now. We just need
3486 to output the assembler directives which denote the start
3488 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3489 if (regs_ever_live[2])
3490 fputs (",CALLS,SAVE_RP", file);
3492 fputs (",NO_CALLS", file);
3494 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3495 at the beginning of the frame and that it is used as the frame
3496 pointer for the frame. We do this because our current frame
3497 layout doesn't conform to that specified in the HP runtime
3498 documentation and we need a way to indicate to programs such as
3499 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3500 isn't used by HP compilers but is supported by the assembler.
3501 However, SAVE_SP is supposed to indicate that the previous stack
3502 pointer has been saved in the frame marker. */
3503 if (frame_pointer_needed)
3504 fputs (",SAVE_SP", file);
3506 /* Pass on information about the number of callee register saves
3507 performed in the prologue.
3509 The compiler is supposed to pass the highest register number
3510 saved, the assembler then has to adjust that number before
3511 entering it into the unwind descriptor (to account for any
3512 caller saved registers with lower register numbers than the
3513 first callee saved register). */
3515 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3518 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3520 fputs ("\n\t.ENTRY\n", file);
3522 remove_useless_addtr_insns (0);
3526 hppa_expand_prologue (void)
3528 int merge_sp_adjust_with_store = 0;
3529 HOST_WIDE_INT size = get_frame_size ();
3530 HOST_WIDE_INT offset;
3538 /* Compute total size for frame pointer, filler, locals and rounding to
3539 the next word boundary. Similar code appears in compute_frame_size
3540 and must be changed in tandem with this code. */
3541 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3542 if (local_fsize || frame_pointer_needed)
3543 local_fsize += STARTING_FRAME_OFFSET;
3545 actual_fsize = compute_frame_size (size, &save_fregs);
3547 /* Compute a few things we will use often. */
3548 tmpreg = gen_rtx_REG (word_mode, 1);
3550 /* Save RP first. The calling conventions manual states RP will
3551 always be stored into the caller's frame at sp - 20 or sp - 16
3552 depending on which ABI is in use. */
3553 if (regs_ever_live[2] || current_function_calls_eh_return)
3554 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3556 /* Allocate the local frame and set up the frame pointer if needed. */
3557 if (actual_fsize != 0)
3559 if (frame_pointer_needed)
3561 /* Copy the old frame pointer temporarily into %r1. Set up the
3562 new stack pointer, then store away the saved old frame pointer
3563 into the stack at sp and at the same time update the stack
3564 pointer by actual_fsize bytes. Two versions, first
3565 handles small (<8k) frames. The second handles large (>=8k)
3567 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3569 RTX_FRAME_RELATED_P (insn) = 1;
3571 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3573 RTX_FRAME_RELATED_P (insn) = 1;
3575 if (VAL_14_BITS_P (actual_fsize))
3576 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3579 /* It is incorrect to store the saved frame pointer at *sp,
3580 then increment sp (writes beyond the current stack boundary).
3582 So instead use stwm to store at *sp and post-increment the
3583 stack pointer as an atomic operation. Then increment sp to
3584 finish allocating the new frame. */
3585 HOST_WIDE_INT adjust1 = 8192 - 64;
3586 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3588 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3589 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3593 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3594 we need to store the previous stack pointer (frame pointer)
3595 into the frame marker on targets that use the HP unwind
3596 library. This allows the HP unwind library to be used to
3597 unwind GCC frames. However, we are not fully compatible
3598 with the HP library because our frame layout differs from
3599 that specified in the HP runtime specification.
3601 We don't want a frame note on this instruction as the frame
3602 marker moves during dynamic stack allocation.
3604 This instruction also serves as a blockage to prevent
3605 register spills from being scheduled before the stack
3606 pointer is raised. This is necessary as we store
3607 registers using the frame pointer as a base register,
3608 and the frame pointer is set before sp is raised. */
3609 if (TARGET_HPUX_UNWIND_LIBRARY)
3611 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3612 GEN_INT (TARGET_64BIT ? -8 : -4));
3614 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3618 emit_insn (gen_blockage ());
3620 /* no frame pointer needed. */
3623 /* In some cases we can perform the first callee register save
3624 and allocating the stack frame at the same time. If so, just
3625 make a note of it and defer allocating the frame until saving
3626 the callee registers. */
3627 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3628 merge_sp_adjust_with_store = 1;
3629 /* Can not optimize. Adjust the stack frame by actual_fsize
3632 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3637 /* Normal register save.
3639 Do not save the frame pointer in the frame_pointer_needed case. It
3640 was done earlier. */
3641 if (frame_pointer_needed)
3643 offset = local_fsize;
3645 /* Saving the EH return data registers in the frame is the simplest
3646 way to get the frame unwind information emitted. We put them
3647 just before the general registers. */
3648 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3650 unsigned int i, regno;
3654 regno = EH_RETURN_DATA_REGNO (i);
3655 if (regno == INVALID_REGNUM)
3658 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3659 offset += UNITS_PER_WORD;
3663 for (i = 18; i >= 4; i--)
3664 if (regs_ever_live[i] && ! call_used_regs[i])
3666 store_reg (i, offset, FRAME_POINTER_REGNUM);
3667 offset += UNITS_PER_WORD;
3670 /* Account for %r3 which is saved in a special place. */
3673 /* No frame pointer needed. */
3676 offset = local_fsize - actual_fsize;
3678 /* Saving the EH return data registers in the frame is the simplest
3679 way to get the frame unwind information emitted. */
3680 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3682 unsigned int i, regno;
3686 regno = EH_RETURN_DATA_REGNO (i);
3687 if (regno == INVALID_REGNUM)
3690 /* If merge_sp_adjust_with_store is nonzero, then we can
3691 optimize the first save. */
3692 if (merge_sp_adjust_with_store)
3694 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3695 merge_sp_adjust_with_store = 0;
3698 store_reg (regno, offset, STACK_POINTER_REGNUM);
3699 offset += UNITS_PER_WORD;
3703 for (i = 18; i >= 3; i--)
3704 if (regs_ever_live[i] && ! call_used_regs[i])
3706 /* If merge_sp_adjust_with_store is nonzero, then we can
3707 optimize the first GR save. */
3708 if (merge_sp_adjust_with_store)
3710 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3711 merge_sp_adjust_with_store = 0;
3714 store_reg (i, offset, STACK_POINTER_REGNUM);
3715 offset += UNITS_PER_WORD;
3719 /* If we wanted to merge the SP adjustment with a GR save, but we never
3720 did any GR saves, then just emit the adjustment here. */
3721 if (merge_sp_adjust_with_store)
3722 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3726 /* The hppa calling conventions say that %r19, the pic offset
3727 register, is saved at sp - 32 (in this function's frame)
3728 when generating PIC code. FIXME: What is the correct thing
3729 to do for functions which make no calls and allocate no
3730 frame? Do we need to allocate a frame, or can we just omit
3731 the save? For now we'll just omit the save.
3733 We don't want a note on this insn as the frame marker can
3734 move if there is a dynamic stack allocation. */
3735 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3737 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3739 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3743 /* Align pointer properly (doubleword boundary). */
3744 offset = (offset + 7) & ~7;
3746 /* Floating point register store. */
3751 /* First get the frame or stack pointer to the start of the FP register
3753 if (frame_pointer_needed)
3755 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3756 base = frame_pointer_rtx;
3760 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3761 base = stack_pointer_rtx;
3764 /* Now actually save the FP registers. */
3765 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3767 if (regs_ever_live[i]
3768 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3770 rtx addr, insn, reg;
3771 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3772 reg = gen_rtx_REG (DFmode, i);
3773 insn = emit_move_insn (addr, reg);
3776 RTX_FRAME_RELATED_P (insn) = 1;
3779 rtx mem = gen_rtx_MEM (DFmode,
3780 plus_constant (base, offset));
3782 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3783 gen_rtx_SET (VOIDmode, mem, reg),
3788 rtx meml = gen_rtx_MEM (SFmode,
3789 plus_constant (base, offset));
3790 rtx memr = gen_rtx_MEM (SFmode,
3791 plus_constant (base, offset + 4));
3792 rtx regl = gen_rtx_REG (SFmode, i);
3793 rtx regr = gen_rtx_REG (SFmode, i + 1);
3794 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3795 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3798 RTX_FRAME_RELATED_P (setl) = 1;
3799 RTX_FRAME_RELATED_P (setr) = 1;
3800 vec = gen_rtvec (2, setl, setr);
3802 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3803 gen_rtx_SEQUENCE (VOIDmode, vec),
3807 offset += GET_MODE_SIZE (DFmode);
3814 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3815 Handle case where DISP > 8k by using the add_high_const patterns. */
3818 load_reg (int reg, HOST_WIDE_INT disp, int base)
3820 rtx dest = gen_rtx_REG (word_mode, reg);
3821 rtx basereg = gen_rtx_REG (Pmode, base);
3824 if (VAL_14_BITS_P (disp))
3825 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3826 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3828 rtx delta = GEN_INT (disp);
3829 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3831 emit_move_insn (tmpreg, delta);
3832 if (TARGET_DISABLE_INDEXING)
3834 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3835 src = gen_rtx_MEM (word_mode, tmpreg);
3838 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3842 rtx delta = GEN_INT (disp);
3843 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3844 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3846 emit_move_insn (tmpreg, high);
3847 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3850 emit_move_insn (dest, src);
3853 /* Update the total code bytes output to the text section. */
3856 update_total_code_bytes (int nbytes)
3858 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3859 && !IN_NAMED_SECTION_P (cfun->decl))
3861 if (INSN_ADDRESSES_SET_P ())
3863 unsigned long old_total = total_code_bytes;
3865 total_code_bytes += nbytes;
3867 /* Be prepared to handle overflows. */
3868 if (old_total > total_code_bytes)
3869 total_code_bytes = -1;
3872 total_code_bytes = -1;
3876 /* This function generates the assembly code for function exit.
3877 Args are as for output_function_prologue ().
3879 The function epilogue should not depend on the current stack
3880 pointer! It should use the frame pointer only. This is mandatory
3881 because of alloca; we also take advantage of it to omit stack
3882 adjustments before returning. */
3885 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3887 rtx insn = get_last_insn ();
3891 /* hppa_expand_epilogue does the dirty work now. We just need
3892 to output the assembler directives which denote the end
3895 To make debuggers happy, emit a nop if the epilogue was completely
3896 eliminated due to a volatile call as the last insn in the
3897 current function. That way the return address (in %r2) will
3898 always point to a valid instruction in the current function. */
3900 /* Get the last real insn. */
3901 if (GET_CODE (insn) == NOTE)
3902 insn = prev_real_insn (insn);
3904 /* If it is a sequence, then look inside. */
3905 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3906 insn = XVECEXP (PATTERN (insn), 0, 0);
3908 /* If insn is a CALL_INSN, then it must be a call to a volatile
3909 function (otherwise there would be epilogue insns). */
3910 if (insn && GET_CODE (insn) == CALL_INSN)
3912 fputs ("\tnop\n", file);
3916 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3918 if (TARGET_SOM && TARGET_GAS)
3920 /* We done with this subspace except possibly for some additional
3921 debug information. Forget that we are in this subspace to ensure
3922 that the next function is output in its own subspace. */
3926 if (INSN_ADDRESSES_SET_P ())
3928 insn = get_last_nonnote_insn ();
3929 last_address += INSN_ADDRESSES (INSN_UID (insn));
3931 last_address += insn_default_length (insn);
3932 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
3933 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
3936 /* Finally, update the total number of code bytes output so far. */
3937 update_total_code_bytes (last_address);
3941 hppa_expand_epilogue (void)
3944 HOST_WIDE_INT offset;
3945 HOST_WIDE_INT ret_off = 0;
3947 int merge_sp_adjust_with_load = 0;
3949 /* We will use this often. */
3950 tmpreg = gen_rtx_REG (word_mode, 1);
3952 /* Try to restore RP early to avoid load/use interlocks when
3953 RP gets used in the return (bv) instruction. This appears to still
3954 be necessary even when we schedule the prologue and epilogue. */
3955 if (regs_ever_live [2] || current_function_calls_eh_return)
3957 ret_off = TARGET_64BIT ? -16 : -20;
3958 if (frame_pointer_needed)
3960 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3965 /* No frame pointer, and stack is smaller than 8k. */
3966 if (VAL_14_BITS_P (ret_off - actual_fsize))
3968 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3974 /* General register restores. */
3975 if (frame_pointer_needed)
3977 offset = local_fsize;
3979 /* If the current function calls __builtin_eh_return, then we need
3980 to restore the saved EH data registers. */
3981 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3983 unsigned int i, regno;
3987 regno = EH_RETURN_DATA_REGNO (i);
3988 if (regno == INVALID_REGNUM)
3991 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3992 offset += UNITS_PER_WORD;
3996 for (i = 18; i >= 4; i--)
3997 if (regs_ever_live[i] && ! call_used_regs[i])
3999 load_reg (i, offset, FRAME_POINTER_REGNUM);
4000 offset += UNITS_PER_WORD;
4005 offset = local_fsize - actual_fsize;
4007 /* If the current function calls __builtin_eh_return, then we need
4008 to restore the saved EH data registers. */
4009 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4011 unsigned int i, regno;
4015 regno = EH_RETURN_DATA_REGNO (i);
4016 if (regno == INVALID_REGNUM)
4019 /* Only for the first load.
4020 merge_sp_adjust_with_load holds the register load
4021 with which we will merge the sp adjustment. */
4022 if (merge_sp_adjust_with_load == 0
4024 && VAL_14_BITS_P (-actual_fsize))
4025 merge_sp_adjust_with_load = regno;
4027 load_reg (regno, offset, STACK_POINTER_REGNUM);
4028 offset += UNITS_PER_WORD;
4032 for (i = 18; i >= 3; i--)
4034 if (regs_ever_live[i] && ! call_used_regs[i])
4036 /* Only for the first load.
4037 merge_sp_adjust_with_load holds the register load
4038 with which we will merge the sp adjustment. */
4039 if (merge_sp_adjust_with_load == 0
4041 && VAL_14_BITS_P (-actual_fsize))
4042 merge_sp_adjust_with_load = i;
4044 load_reg (i, offset, STACK_POINTER_REGNUM);
4045 offset += UNITS_PER_WORD;
4050 /* Align pointer properly (doubleword boundary). */
4051 offset = (offset + 7) & ~7;
4053 /* FP register restores. */
4056 /* Adjust the register to index off of. */
4057 if (frame_pointer_needed)
4058 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4060 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4062 /* Actually do the restores now. */
4063 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4064 if (regs_ever_live[i]
4065 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4067 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4068 rtx dest = gen_rtx_REG (DFmode, i);
4069 emit_move_insn (dest, src);
4073 /* Emit a blockage insn here to keep these insns from being moved to
4074 an earlier spot in the epilogue, or into the main instruction stream.
4076 This is necessary as we must not cut the stack back before all the
4077 restores are finished. */
4078 emit_insn (gen_blockage ());
4080 /* Reset stack pointer (and possibly frame pointer). The stack
4081 pointer is initially set to fp + 64 to avoid a race condition. */
4082 if (frame_pointer_needed)
4084 rtx delta = GEN_INT (-64);
4086 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4087 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4089 /* If we were deferring a callee register restore, do it now. */
4090 else if (merge_sp_adjust_with_load)
4092 rtx delta = GEN_INT (-actual_fsize);
4093 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4095 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4097 else if (actual_fsize != 0)
4098 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4101 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4102 frame greater than 8k), do so now. */
4104 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4106 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4108 rtx sa = EH_RETURN_STACKADJ_RTX;
4110 emit_insn (gen_blockage ());
4111 emit_insn (TARGET_64BIT
4112 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4113 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4118 hppa_pic_save_rtx (void)
4120 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4123 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4124 #define NO_DEFERRED_PROFILE_COUNTERS 0
4127 /* Define heap vector type for funcdef numbers. */
4129 DEF_VEC_ALLOC_I(int,heap);
4131 /* Vector of funcdef numbers. */
4132 static VEC(int,heap) *funcdef_nos;
4134 /* Output deferred profile counters. */
4136 output_deferred_profile_counters (void)
4141 if (VEC_empty (int, funcdef_nos))
4145 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4146 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4148 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4150 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4151 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4154 VEC_free (int, heap, funcdef_nos);
4158 hppa_profile_hook (int label_no)
4160 /* We use SImode for the address of the function in both 32 and
4161 64-bit code to avoid having to provide DImode versions of the
4162 lcla2 and load_offset_label_address insn patterns. */
4163 rtx reg = gen_reg_rtx (SImode);
4164 rtx label_rtx = gen_label_rtx ();
4165 rtx begin_label_rtx, call_insn;
4166 char begin_label_name[16];
4168 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4170 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4173 emit_move_insn (arg_pointer_rtx,
4174 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4177 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4179 /* The address of the function is loaded into %r25 with a instruction-
4180 relative sequence that avoids the use of relocations. The sequence
4181 is split so that the load_offset_label_address instruction can
4182 occupy the delay slot of the call to _mcount. */
4184 emit_insn (gen_lcla2 (reg, label_rtx));
4186 emit_insn (gen_lcla1 (reg, label_rtx));
4188 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4189 reg, begin_label_rtx, label_rtx));
4191 #if !NO_DEFERRED_PROFILE_COUNTERS
4193 rtx count_label_rtx, addr, r24;
4194 char count_label_name[16];
4196 VEC_safe_push (int, heap, funcdef_nos, label_no);
4197 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4198 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4200 addr = force_reg (Pmode, count_label_rtx);
4201 r24 = gen_rtx_REG (Pmode, 24);
4202 emit_move_insn (r24, addr);
4205 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4206 gen_rtx_SYMBOL_REF (Pmode,
4208 GEN_INT (TARGET_64BIT ? 24 : 12)));
4210 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4215 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4216 gen_rtx_SYMBOL_REF (Pmode,
4218 GEN_INT (TARGET_64BIT ? 16 : 8)));
4222 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4223 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4225 /* Indicate the _mcount call cannot throw, nor will it execute a
4227 REG_NOTES (call_insn)
4228 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4231 /* Fetch the return address for the frame COUNT steps up from
4232 the current frame, after the prologue. FRAMEADDR is the
4233 frame pointer of the COUNT frame.
4235 We want to ignore any export stub remnants here. To handle this,
4236 we examine the code at the return address, and if it is an export
4237 stub, we return a memory rtx for the stub return address stored
4240 The value returned is used in two different ways:
4242 1. To find a function's caller.
4244 2. To change the return address for a function.
4246 This function handles most instances of case 1; however, it will
4247 fail if there are two levels of stubs to execute on the return
4248 path. The only way I believe that can happen is if the return value
4249 needs a parameter relocation, which never happens for C code.
4251 This function handles most instances of case 2; however, it will
4252 fail if we did not originally have stub code on the return path
4253 but will need stub code on the new return path. This can happen if
4254 the caller & callee are both in the main program, but the new
4255 return location is in a shared library. */
4258 return_addr_rtx (int count, rtx frameaddr)
4268 rp = get_hard_reg_initial_val (Pmode, 2);
4270 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4273 saved_rp = gen_reg_rtx (Pmode);
4274 emit_move_insn (saved_rp, rp);
4276 /* Get pointer to the instruction stream. We have to mask out the
4277 privilege level from the two low order bits of the return address
4278 pointer here so that ins will point to the start of the first
4279 instruction that would have been executed if we returned. */
4280 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4281 label = gen_label_rtx ();
4283 /* Check the instruction stream at the normal return address for the
4286 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4287 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4288 0x00011820 | stub+16: mtsp r1,sr0
4289 0xe0400002 | stub+20: be,n 0(sr0,rp)
4291 If it is an export stub, than our return address is really in
4294 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4295 NULL_RTX, SImode, 1);
4296 emit_jump_insn (gen_bne (label));
4298 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4299 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4300 emit_jump_insn (gen_bne (label));
4302 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4303 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4304 emit_jump_insn (gen_bne (label));
4306 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4307 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4309 /* If there is no export stub then just use the value saved from
4310 the return pointer register. */
4312 emit_jump_insn (gen_bne (label));
4314 /* Here we know that our return address points to an export
4315 stub. We don't want to return the address of the export stub,
4316 but rather the return address of the export stub. That return
4317 address is stored at -24[frameaddr]. */
4319 emit_move_insn (saved_rp,
4321 memory_address (Pmode,
4322 plus_constant (frameaddr,
4329 /* This is only valid once reload has completed because it depends on
4330 knowing exactly how much (if any) frame there is and...
4332 It's only valid if there is no frame marker to de-allocate and...
4334 It's only valid if %r2 hasn't been saved into the caller's frame
4335 (we're not profiling and %r2 isn't live anywhere). */
4337 hppa_can_use_return_insn_p (void)
4339 return (reload_completed
4340 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4341 && ! regs_ever_live[2]
4342 && ! frame_pointer_needed);
4346 emit_bcond_fp (enum rtx_code code, rtx operand0)
4348 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4349 gen_rtx_IF_THEN_ELSE (VOIDmode,
4350 gen_rtx_fmt_ee (code,
4352 gen_rtx_REG (CCFPmode, 0),
4354 gen_rtx_LABEL_REF (VOIDmode, operand0),
4360 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4362 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4363 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4366 /* Adjust the cost of a scheduling dependency. Return the new cost of
4367 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4370 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4372 enum attr_type attr_type;
4374 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4375 true dependencies as they are described with bypasses now. */
4376 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4379 if (! recog_memoized (insn))
4382 attr_type = get_attr_type (insn);
4384 switch (REG_NOTE_KIND (link))
4387 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4390 if (attr_type == TYPE_FPLOAD)
4392 rtx pat = PATTERN (insn);
4393 rtx dep_pat = PATTERN (dep_insn);
4394 if (GET_CODE (pat) == PARALLEL)
4396 /* This happens for the fldXs,mb patterns. */
4397 pat = XVECEXP (pat, 0, 0);
4399 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4400 /* If this happens, we have to extend this to schedule
4401 optimally. Return 0 for now. */
4404 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4406 if (! recog_memoized (dep_insn))
4408 switch (get_attr_type (dep_insn))
4415 case TYPE_FPSQRTSGL:
4416 case TYPE_FPSQRTDBL:
4417 /* A fpload can't be issued until one cycle before a
4418 preceding arithmetic operation has finished if
4419 the target of the fpload is any of the sources
4420 (or destination) of the arithmetic operation. */
4421 return insn_default_latency (dep_insn) - 1;
4428 else if (attr_type == TYPE_FPALU)
4430 rtx pat = PATTERN (insn);
4431 rtx dep_pat = PATTERN (dep_insn);
4432 if (GET_CODE (pat) == PARALLEL)
4434 /* This happens for the fldXs,mb patterns. */
4435 pat = XVECEXP (pat, 0, 0);
4437 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4438 /* If this happens, we have to extend this to schedule
4439 optimally. Return 0 for now. */
4442 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4444 if (! recog_memoized (dep_insn))
4446 switch (get_attr_type (dep_insn))
4450 case TYPE_FPSQRTSGL:
4451 case TYPE_FPSQRTDBL:
4452 /* An ALU flop can't be issued until two cycles before a
4453 preceding divide or sqrt operation has finished if
4454 the target of the ALU flop is any of the sources
4455 (or destination) of the divide or sqrt operation. */
4456 return insn_default_latency (dep_insn) - 2;
4464 /* For other anti dependencies, the cost is 0. */
4467 case REG_DEP_OUTPUT:
4468 /* Output dependency; DEP_INSN writes a register that INSN writes some
4470 if (attr_type == TYPE_FPLOAD)
4472 rtx pat = PATTERN (insn);
4473 rtx dep_pat = PATTERN (dep_insn);
4474 if (GET_CODE (pat) == PARALLEL)
4476 /* This happens for the fldXs,mb patterns. */
4477 pat = XVECEXP (pat, 0, 0);
4479 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4480 /* If this happens, we have to extend this to schedule
4481 optimally. Return 0 for now. */
4484 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4486 if (! recog_memoized (dep_insn))
4488 switch (get_attr_type (dep_insn))
4495 case TYPE_FPSQRTSGL:
4496 case TYPE_FPSQRTDBL:
4497 /* A fpload can't be issued until one cycle before a
4498 preceding arithmetic operation has finished if
4499 the target of the fpload is the destination of the
4500 arithmetic operation.
4502 Exception: For PA7100LC, PA7200 and PA7300, the cost
4503 is 3 cycles, unless they bundle together. We also
4504 pay the penalty if the second insn is a fpload. */
4505 return insn_default_latency (dep_insn) - 1;
4512 else if (attr_type == TYPE_FPALU)
4514 rtx pat = PATTERN (insn);
4515 rtx dep_pat = PATTERN (dep_insn);
4516 if (GET_CODE (pat) == PARALLEL)
4518 /* This happens for the fldXs,mb patterns. */
4519 pat = XVECEXP (pat, 0, 0);
4521 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4522 /* If this happens, we have to extend this to schedule
4523 optimally. Return 0 for now. */
4526 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4528 if (! recog_memoized (dep_insn))
4530 switch (get_attr_type (dep_insn))
4534 case TYPE_FPSQRTSGL:
4535 case TYPE_FPSQRTDBL:
4536 /* An ALU flop can't be issued until two cycles before a
4537 preceding divide or sqrt operation has finished if
4538 the target of the ALU flop is also the target of
4539 the divide or sqrt operation. */
4540 return insn_default_latency (dep_insn) - 2;
4548 /* For other output dependencies, the cost is 0. */
4556 /* Adjust scheduling priorities. We use this to try and keep addil
4557 and the next use of %r1 close together. */
4559 pa_adjust_priority (rtx insn, int priority)
4561 rtx set = single_set (insn);
4565 src = SET_SRC (set);
4566 dest = SET_DEST (set);
4567 if (GET_CODE (src) == LO_SUM
4568 && symbolic_operand (XEXP (src, 1), VOIDmode)
4569 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4572 else if (GET_CODE (src) == MEM
4573 && GET_CODE (XEXP (src, 0)) == LO_SUM
4574 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4575 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4578 else if (GET_CODE (dest) == MEM
4579 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4580 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4581 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4587 /* The 700 can only issue a single insn at a time.
4588 The 7XXX processors can issue two insns at a time.
4589 The 8000 can issue 4 insns at a time. */
4591 pa_issue_rate (void)
4595 case PROCESSOR_700: return 1;
4596 case PROCESSOR_7100: return 2;
4597 case PROCESSOR_7100LC: return 2;
4598 case PROCESSOR_7200: return 2;
4599 case PROCESSOR_7300: return 2;
4600 case PROCESSOR_8000: return 4;
4609 /* Return any length adjustment needed by INSN which already has its length
4610 computed as LENGTH. Return zero if no adjustment is necessary.
4612 For the PA: function calls, millicode calls, and backwards short
4613 conditional branches with unfilled delay slots need an adjustment by +1
4614 (to account for the NOP which will be inserted into the instruction stream).
4616 Also compute the length of an inline block move here as it is too
4617 complicated to express as a length attribute in pa.md. */
4619 pa_adjust_insn_length (rtx insn, int length)
4621 rtx pat = PATTERN (insn);
4623 /* Jumps inside switch tables which have unfilled delay slots need
4625 if (GET_CODE (insn) == JUMP_INSN
4626 && GET_CODE (pat) == PARALLEL
4627 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4629 /* Millicode insn with an unfilled delay slot. */
4630 else if (GET_CODE (insn) == INSN
4631 && GET_CODE (pat) != SEQUENCE
4632 && GET_CODE (pat) != USE
4633 && GET_CODE (pat) != CLOBBER
4634 && get_attr_type (insn) == TYPE_MILLI)
4636 /* Block move pattern. */
4637 else if (GET_CODE (insn) == INSN
4638 && GET_CODE (pat) == PARALLEL
4639 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4640 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4641 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4642 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4643 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4644 return compute_movmem_length (insn) - 4;
4645 /* Block clear pattern. */
4646 else if (GET_CODE (insn) == INSN
4647 && GET_CODE (pat) == PARALLEL
4648 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4649 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4650 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4651 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4652 return compute_clrmem_length (insn) - 4;
4653 /* Conditional branch with an unfilled delay slot. */
4654 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4656 /* Adjust a short backwards conditional with an unfilled delay slot. */
4657 if (GET_CODE (pat) == SET
4659 && ! forward_branch_p (insn))
4661 else if (GET_CODE (pat) == PARALLEL
4662 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4665 /* Adjust dbra insn with short backwards conditional branch with
4666 unfilled delay slot -- only for case where counter is in a
4667 general register register. */
4668 else if (GET_CODE (pat) == PARALLEL
4669 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4670 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4671 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4673 && ! forward_branch_p (insn))
4681 /* Print operand X (an rtx) in assembler syntax to file FILE.
4682 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4683 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4686 print_operand (FILE *file, rtx x, int code)
4691 /* Output a 'nop' if there's nothing for the delay slot. */
4692 if (dbr_sequence_length () == 0)
4693 fputs ("\n\tnop", file);
4696 /* Output a nullification completer if there's nothing for the */
4697 /* delay slot or nullification is requested. */
4698 if (dbr_sequence_length () == 0 ||
4700 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4704 /* Print out the second register name of a register pair.
4705 I.e., R (6) => 7. */
4706 fputs (reg_names[REGNO (x) + 1], file);
4709 /* A register or zero. */
4711 || (x == CONST0_RTX (DFmode))
4712 || (x == CONST0_RTX (SFmode)))
4714 fputs ("%r0", file);
4720 /* A register or zero (floating point). */
4722 || (x == CONST0_RTX (DFmode))
4723 || (x == CONST0_RTX (SFmode)))
4725 fputs ("%fr0", file);
4734 xoperands[0] = XEXP (XEXP (x, 0), 0);
4735 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4736 output_global_address (file, xoperands[1], 0);
4737 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4741 case 'C': /* Plain (C)ondition */
4743 switch (GET_CODE (x))
4746 fputs ("=", file); break;
4748 fputs ("<>", file); break;
4750 fputs (">", file); break;
4752 fputs (">=", file); break;
4754 fputs (">>=", file); break;
4756 fputs (">>", file); break;
4758 fputs ("<", file); break;
4760 fputs ("<=", file); break;
4762 fputs ("<<=", file); break;
4764 fputs ("<<", file); break;
4769 case 'N': /* Condition, (N)egated */
4770 switch (GET_CODE (x))
4773 fputs ("<>", file); break;
4775 fputs ("=", file); break;
4777 fputs ("<=", file); break;
4779 fputs ("<", file); break;
4781 fputs ("<<", file); break;
4783 fputs ("<<=", file); break;
4785 fputs (">=", file); break;
4787 fputs (">", file); break;
4789 fputs (">>", file); break;
4791 fputs (">>=", file); break;
4796 /* For floating point comparisons. Note that the output
4797 predicates are the complement of the desired mode. The
4798 conditions for GT, GE, LT, LE and LTGT cause an invalid
4799 operation exception if the result is unordered and this
4800 exception is enabled in the floating-point status register. */
4802 switch (GET_CODE (x))
4805 fputs ("!=", file); break;
4807 fputs ("=", file); break;
4809 fputs ("!>", file); break;
4811 fputs ("!>=", file); break;
4813 fputs ("!<", file); break;
4815 fputs ("!<=", file); break;
4817 fputs ("!<>", file); break;
4819 fputs ("!?<=", file); break;
4821 fputs ("!?<", file); break;
4823 fputs ("!?>=", file); break;
4825 fputs ("!?>", file); break;
4827 fputs ("!?=", file); break;
4829 fputs ("!?", file); break;
4831 fputs ("?", file); break;
4836 case 'S': /* Condition, operands are (S)wapped. */
4837 switch (GET_CODE (x))
4840 fputs ("=", file); break;
4842 fputs ("<>", file); break;
4844 fputs ("<", file); break;
4846 fputs ("<=", file); break;
4848 fputs ("<<=", file); break;
4850 fputs ("<<", file); break;
4852 fputs (">", file); break;
4854 fputs (">=", file); break;
4856 fputs (">>=", file); break;
4858 fputs (">>", file); break;
4863 case 'B': /* Condition, (B)oth swapped and negate. */
4864 switch (GET_CODE (x))
4867 fputs ("<>", file); break;
4869 fputs ("=", file); break;
4871 fputs (">=", file); break;
4873 fputs (">", file); break;
4875 fputs (">>", file); break;
4877 fputs (">>=", file); break;
4879 fputs ("<=", file); break;
4881 fputs ("<", file); break;
4883 fputs ("<<", file); break;
4885 fputs ("<<=", file); break;
4891 gcc_assert (GET_CODE (x) == CONST_INT);
4892 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4895 gcc_assert (GET_CODE (x) == CONST_INT);
4896 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4899 gcc_assert (GET_CODE (x) == CONST_INT);
4900 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4903 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
4904 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4907 gcc_assert (GET_CODE (x) == CONST_INT);
4908 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4911 gcc_assert (GET_CODE (x) == CONST_INT);
4912 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4915 if (GET_CODE (x) == CONST_INT)
4920 switch (GET_CODE (XEXP (x, 0)))
4924 if (ASSEMBLER_DIALECT == 0)
4925 fputs ("s,mb", file);
4927 fputs (",mb", file);
4931 if (ASSEMBLER_DIALECT == 0)
4932 fputs ("s,ma", file);
4934 fputs (",ma", file);
4937 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4938 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4940 if (ASSEMBLER_DIALECT == 0)
4943 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4944 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4946 if (ASSEMBLER_DIALECT == 0)
4947 fputs ("x,s", file);
4951 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4955 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4961 output_global_address (file, x, 0);
4964 output_global_address (file, x, 1);
4966 case 0: /* Don't do anything special */
4971 compute_zdepwi_operands (INTVAL (x), op);
4972 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4978 compute_zdepdi_operands (INTVAL (x), op);
4979 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4983 /* We can get here from a .vtable_inherit due to our
4984 CONSTANT_ADDRESS_P rejecting perfectly good constant
4990 if (GET_CODE (x) == REG)
4992 fputs (reg_names [REGNO (x)], file);
4993 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4999 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5000 && (REGNO (x) & 1) == 0)
5003 else if (GET_CODE (x) == MEM)
5005 int size = GET_MODE_SIZE (GET_MODE (x));
5006 rtx base = NULL_RTX;
5007 switch (GET_CODE (XEXP (x, 0)))
5011 base = XEXP (XEXP (x, 0), 0);
5012 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5016 base = XEXP (XEXP (x, 0), 0);
5017 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5020 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5021 fprintf (file, "%s(%s)",
5022 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5023 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5024 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5025 fprintf (file, "%s(%s)",
5026 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5027 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5028 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5029 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5031 /* Because the REG_POINTER flag can get lost during reload,
5032 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5033 index and base registers in the combined move patterns. */
5034 rtx base = XEXP (XEXP (x, 0), 1);
5035 rtx index = XEXP (XEXP (x, 0), 0);
5037 fprintf (file, "%s(%s)",
5038 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5041 output_address (XEXP (x, 0));
5044 output_address (XEXP (x, 0));
5049 output_addr_const (file, x);
5052 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5055 output_global_address (FILE *file, rtx x, int round_constant)
5058 /* Imagine (high (const (plus ...))). */
5059 if (GET_CODE (x) == HIGH)
5062 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5063 output_addr_const (file, x);
5064 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5066 output_addr_const (file, x);
5067 fputs ("-$global$", file);
5069 else if (GET_CODE (x) == CONST)
5071 const char *sep = "";
5072 int offset = 0; /* assembler wants -$global$ at end */
5073 rtx base = NULL_RTX;
5075 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5078 base = XEXP (XEXP (x, 0), 0);
5079 output_addr_const (file, base);
5082 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5088 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5091 base = XEXP (XEXP (x, 0), 1);
5092 output_addr_const (file, base);
5095 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5101 /* How bogus. The compiler is apparently responsible for
5102 rounding the constant if it uses an LR field selector.
5104 The linker and/or assembler seem a better place since
5105 they have to do this kind of thing already.
5107 If we fail to do this, HP's optimizing linker may eliminate
5108 an addil, but not update the ldw/stw/ldo instruction that
5109 uses the result of the addil. */
5111 offset = ((offset + 0x1000) & ~0x1fff);
5113 switch (GET_CODE (XEXP (x, 0)))
5126 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5134 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5135 fputs ("-$global$", file);
5137 fprintf (file, "%s%d", sep, offset);
5140 output_addr_const (file, x);
5143 /* Output boilerplate text to appear at the beginning of the file.
5144 There are several possible versions. */
5145 #define aputs(x) fputs(x, asm_out_file)
5147 pa_file_start_level (void)
5150 aputs ("\t.LEVEL 2.0w\n");
5151 else if (TARGET_PA_20)
5152 aputs ("\t.LEVEL 2.0\n");
5153 else if (TARGET_PA_11)
5154 aputs ("\t.LEVEL 1.1\n");
5156 aputs ("\t.LEVEL 1.0\n");
5160 pa_file_start_space (int sortspace)
5162 aputs ("\t.SPACE $PRIVATE$");
5165 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5166 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5167 "\n\t.SPACE $TEXT$");
5170 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5171 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5175 pa_file_start_file (int want_version)
5177 if (write_symbols != NO_DEBUG)
5179 output_file_directive (asm_out_file, main_input_filename);
5181 aputs ("\t.version\t\"01.01\"\n");
5186 pa_file_start_mcount (const char *aswhat)
5189 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5193 pa_elf_file_start (void)
5195 pa_file_start_level ();
5196 pa_file_start_mcount ("ENTRY");
5197 pa_file_start_file (0);
5201 pa_som_file_start (void)
5203 pa_file_start_level ();
5204 pa_file_start_space (0);
5205 aputs ("\t.IMPORT $global$,DATA\n"
5206 "\t.IMPORT $$dyncall,MILLICODE\n");
5207 pa_file_start_mcount ("CODE");
5208 pa_file_start_file (0);
5212 pa_linux_file_start (void)
5214 pa_file_start_file (1);
5215 pa_file_start_level ();
5216 pa_file_start_mcount ("CODE");
5220 pa_hpux64_gas_file_start (void)
5222 pa_file_start_level ();
5223 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5225 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5227 pa_file_start_file (1);
5231 pa_hpux64_hpas_file_start (void)
5233 pa_file_start_level ();
5234 pa_file_start_space (1);
5235 pa_file_start_mcount ("CODE");
5236 pa_file_start_file (0);
5240 /* Search the deferred plabel list for SYMBOL and return its internal
5241 label. If an entry for SYMBOL is not found, a new entry is created. */
5244 get_deferred_plabel (rtx symbol)
5246 const char *fname = XSTR (symbol, 0);
5249 /* See if we have already put this function on the list of deferred
5250 plabels. This list is generally small, so a liner search is not
5251 too ugly. If it proves too slow replace it with something faster. */
5252 for (i = 0; i < n_deferred_plabels; i++)
5253 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5256 /* If the deferred plabel list is empty, or this entry was not found
5257 on the list, create a new entry on the list. */
5258 if (deferred_plabels == NULL || i == n_deferred_plabels)
5262 if (deferred_plabels == 0)
5263 deferred_plabels = (struct deferred_plabel *)
5264 ggc_alloc (sizeof (struct deferred_plabel));
5266 deferred_plabels = (struct deferred_plabel *)
5267 ggc_realloc (deferred_plabels,
5268 ((n_deferred_plabels + 1)
5269 * sizeof (struct deferred_plabel)));
5271 i = n_deferred_plabels++;
5272 deferred_plabels[i].internal_label = gen_label_rtx ();
5273 deferred_plabels[i].symbol = symbol;
5275 /* Gross. We have just implicitly taken the address of this
5276 function. Mark it in the same manner as assemble_name. */
5277 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5279 mark_referenced (id);
5282 return deferred_plabels[i].internal_label;
5286 output_deferred_plabels (void)
5289 /* If we have deferred plabels, then we need to switch into the data
5290 section and align it to a 4 byte boundary before we output the
5291 deferred plabels. */
5292 if (n_deferred_plabels)
5295 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5298 /* Now output the deferred plabels. */
5299 for (i = 0; i < n_deferred_plabels; i++)
5301 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5302 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5303 assemble_integer (deferred_plabels[i].symbol,
5304 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5308 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5309 /* Initialize optabs to point to HPUX long double emulation routines. */
5311 pa_hpux_init_libfuncs (void)
5313 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5314 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5315 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5316 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5317 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5318 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5319 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5320 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5321 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5323 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5324 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5325 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5326 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5327 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5328 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5329 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5331 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5332 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5333 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5334 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5336 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5337 ? "__U_Qfcnvfxt_quad_to_sgl"
5338 : "_U_Qfcnvfxt_quad_to_sgl");
5339 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5340 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5341 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5343 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5344 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5348 /* HP's millicode routines mean something special to the assembler.
5349 Keep track of which ones we have used. */
5351 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5352 static void import_milli (enum millicodes);
5353 static char imported[(int) end1000];
5354 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5355 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5356 #define MILLI_START 10
5359 import_milli (enum millicodes code)
5361 char str[sizeof (import_string)];
5363 if (!imported[(int) code])
5365 imported[(int) code] = 1;
5366 strcpy (str, import_string);
5367 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5368 output_asm_insn (str, 0);
5372 /* The register constraints have put the operands and return value in
5373 the proper registers. */
5376 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5378 import_milli (mulI);
5379 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5382 /* Emit the rtl for doing a division by a constant. */
5384 /* Do magic division millicodes exist for this value? */
5385 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5387 /* We'll use an array to keep track of the magic millicodes and
5388 whether or not we've used them already. [n][0] is signed, [n][1] is
5391 static int div_milli[16][2];
5394 emit_hpdiv_const (rtx *operands, int unsignedp)
5396 if (GET_CODE (operands[2]) == CONST_INT
5397 && INTVAL (operands[2]) > 0
5398 && INTVAL (operands[2]) < 16
5399 && magic_milli[INTVAL (operands[2])])
5401 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5403 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5407 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5408 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5410 gen_rtx_REG (SImode, 26),
5412 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5413 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5414 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5415 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5416 gen_rtx_CLOBBER (VOIDmode, ret))));
5417 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5424 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5428 /* If the divisor is a constant, try to use one of the special
5430 if (GET_CODE (operands[0]) == CONST_INT)
5432 static char buf[100];
5433 divisor = INTVAL (operands[0]);
5434 if (!div_milli[divisor][unsignedp])
5436 div_milli[divisor][unsignedp] = 1;
5438 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5440 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5444 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5445 INTVAL (operands[0]));
5446 return output_millicode_call (insn,
5447 gen_rtx_SYMBOL_REF (SImode, buf));
5451 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5452 INTVAL (operands[0]));
5453 return output_millicode_call (insn,
5454 gen_rtx_SYMBOL_REF (SImode, buf));
5457 /* Divisor isn't a special constant. */
5462 import_milli (divU);
5463 return output_millicode_call (insn,
5464 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5468 import_milli (divI);
5469 return output_millicode_call (insn,
5470 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5475 /* Output a $$rem millicode to do mod. */
5478 output_mod_insn (int unsignedp, rtx insn)
5482 import_milli (remU);
5483 return output_millicode_call (insn,
5484 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5488 import_milli (remI);
5489 return output_millicode_call (insn,
5490 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5495 output_arg_descriptor (rtx call_insn)
5497 const char *arg_regs[4];
5498 enum machine_mode arg_mode;
5500 int i, output_flag = 0;
5503 /* We neither need nor want argument location descriptors for the
5504 64bit runtime environment or the ELF32 environment. */
5505 if (TARGET_64BIT || TARGET_ELF32)
5508 for (i = 0; i < 4; i++)
5511 /* Specify explicitly that no argument relocations should take place
5512 if using the portable runtime calling conventions. */
5513 if (TARGET_PORTABLE_RUNTIME)
5515 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5520 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5521 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5522 link; link = XEXP (link, 1))
5524 rtx use = XEXP (link, 0);
5526 if (! (GET_CODE (use) == USE
5527 && GET_CODE (XEXP (use, 0)) == REG
5528 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5531 arg_mode = GET_MODE (XEXP (use, 0));
5532 regno = REGNO (XEXP (use, 0));
5533 if (regno >= 23 && regno <= 26)
5535 arg_regs[26 - regno] = "GR";
5536 if (arg_mode == DImode)
5537 arg_regs[25 - regno] = "GR";
5539 else if (regno >= 32 && regno <= 39)
5541 if (arg_mode == SFmode)
5542 arg_regs[(regno - 32) / 2] = "FR";
5545 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5546 arg_regs[(regno - 34) / 2] = "FR";
5547 arg_regs[(regno - 34) / 2 + 1] = "FU";
5549 arg_regs[(regno - 34) / 2] = "FU";
5550 arg_regs[(regno - 34) / 2 + 1] = "FR";
5555 fputs ("\t.CALL ", asm_out_file);
5556 for (i = 0; i < 4; i++)
5561 fputc (',', asm_out_file);
5562 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5565 fputc ('\n', asm_out_file);
5568 /* Return the class of any secondary reload register that is needed to
5569 move IN into a register in class CLASS using mode MODE.
5571 Profiling has showed this routine and its descendants account for
5572 a significant amount of compile time (~7%). So it has been
5573 optimized to reduce redundant computations and eliminate useless
5576 It might be worthwhile to try and make this a leaf function too. */
5579 pa_secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5581 int regno, is_symbolic;
5583 /* Trying to load a constant into a FP register during PIC code
5584 generation will require %r1 as a scratch register. */
5586 && GET_MODE_CLASS (mode) == MODE_INT
5587 && FP_REG_CLASS_P (class)
5588 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5591 /* Profiling showed the PA port spends about 1.3% of its compilation
5592 time in true_regnum from calls inside pa_secondary_reload_class. */
5594 if (GET_CODE (in) == REG)
5597 if (regno >= FIRST_PSEUDO_REGISTER)
5598 regno = true_regnum (in);
5600 else if (GET_CODE (in) == SUBREG)
5601 regno = true_regnum (in);
5605 /* If we have something like (mem (mem (...)), we can safely assume the
5606 inner MEM will end up in a general register after reloading, so there's
5607 no need for a secondary reload. */
5608 if (GET_CODE (in) == MEM
5609 && GET_CODE (XEXP (in, 0)) == MEM)
5612 /* Handle out of range displacement for integer mode loads/stores of
5614 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5615 && GET_MODE_CLASS (mode) == MODE_INT
5616 && FP_REG_CLASS_P (class))
5617 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5618 return GENERAL_REGS;
5620 /* A SAR<->FP register copy requires a secondary register (GPR) as
5621 well as secondary memory. */
5622 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5623 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5624 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5625 return GENERAL_REGS;
5627 if (GET_CODE (in) == HIGH)
5630 /* Profiling has showed GCC spends about 2.6% of its compilation
5631 time in symbolic_operand from calls inside pa_secondary_reload_class.
5633 We use an inline copy and only compute its return value once to avoid
5635 switch (GET_CODE (in))
5645 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5646 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5647 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5657 && read_only_operand (in, VOIDmode))
5660 if (class != R1_REGS && is_symbolic)
5666 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5667 by invisible reference. As a GCC extension, we also pass anything
5668 with a zero or variable size by reference.
5670 The 64-bit runtime does not describe passing any types by invisible
5671 reference. The internals of GCC can't currently handle passing
5672 empty structures, and zero or variable length arrays when they are
5673 not passed entirely on the stack or by reference. Thus, as a GCC
5674 extension, we pass these types by reference. The HP compiler doesn't
5675 support these types, so hopefully there shouldn't be any compatibility
5676 issues. This may have to be revisited when HP releases a C99 compiler
5677 or updates the ABI. */
5680 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5681 enum machine_mode mode, tree type,
5682 bool named ATTRIBUTE_UNUSED)
5687 size = int_size_in_bytes (type);
5689 size = GET_MODE_SIZE (mode);
5694 return size <= 0 || size > 8;
5698 function_arg_padding (enum machine_mode mode, tree type)
5701 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5703 /* Return none if justification is not required. */
5705 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5706 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5709 /* The directions set here are ignored when a BLKmode argument larger
5710 than a word is placed in a register. Different code is used for
5711 the stack and registers. This makes it difficult to have a
5712 consistent data representation for both the stack and registers.
5713 For both runtimes, the justification and padding for arguments on
5714 the stack and in registers should be identical. */
5716 /* The 64-bit runtime specifies left justification for aggregates. */
5719 /* The 32-bit runtime architecture specifies right justification.
5720 When the argument is passed on the stack, the argument is padded
5721 with garbage on the left. The HP compiler pads with zeros. */
5725 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5732 /* Do what is necessary for `va_start'. We look at the current function
5733 to determine if stdargs or varargs is used and fill in an initial
5734 va_list. A pointer to this constructor is returned. */
5737 hppa_builtin_saveregs (void)
5740 tree fntype = TREE_TYPE (current_function_decl);
5741 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5742 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5743 != void_type_node)))
5744 ? UNITS_PER_WORD : 0);
5747 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5749 offset = current_function_arg_offset_rtx;
5755 /* Adjust for varargs/stdarg differences. */
5757 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5759 offset = current_function_arg_offset_rtx;
5761 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5762 from the incoming arg pointer and growing to larger addresses. */
5763 for (i = 26, off = -64; i >= 19; i--, off += 8)
5764 emit_move_insn (gen_rtx_MEM (word_mode,
5765 plus_constant (arg_pointer_rtx, off)),
5766 gen_rtx_REG (word_mode, i));
5768 /* The incoming args pointer points just beyond the flushback area;
5769 normally this is not a serious concern. However, when we are doing
5770 varargs/stdargs we want to make the arg pointer point to the start
5771 of the incoming argument area. */
5772 emit_move_insn (virtual_incoming_args_rtx,
5773 plus_constant (arg_pointer_rtx, -64));
5775 /* Now return a pointer to the first anonymous argument. */
5776 return copy_to_reg (expand_binop (Pmode, add_optab,
5777 virtual_incoming_args_rtx,
5778 offset, 0, 0, OPTAB_LIB_WIDEN));
5781 /* Store general registers on the stack. */
5782 dest = gen_rtx_MEM (BLKmode,
5783 plus_constant (current_function_internal_arg_pointer,
5785 set_mem_alias_set (dest, get_varargs_alias_set ());
5786 set_mem_align (dest, BITS_PER_WORD);
5787 move_block_from_reg (23, dest, 4);
5789 /* move_block_from_reg will emit code to store the argument registers
5790 individually as scalar stores.
5792 However, other insns may later load from the same addresses for
5793 a structure load (passing a struct to a varargs routine).
5795 The alias code assumes that such aliasing can never happen, so we
5796 have to keep memory referencing insns from moving up beyond the
5797 last argument register store. So we emit a blockage insn here. */
5798 emit_insn (gen_blockage ());
5800 return copy_to_reg (expand_binop (Pmode, add_optab,
5801 current_function_internal_arg_pointer,
5802 offset, 0, 0, OPTAB_LIB_WIDEN));
5806 hppa_va_start (tree valist, rtx nextarg)
5808 nextarg = expand_builtin_saveregs ();
5809 std_expand_builtin_va_start (valist, nextarg);
5813 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5817 /* Args grow upward. We can use the generic routines. */
5818 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5820 else /* !TARGET_64BIT */
5822 tree ptr = build_pointer_type (type);
5825 unsigned int size, ofs;
5828 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5832 ptr = build_pointer_type (type);
5834 size = int_size_in_bytes (type);
5835 valist_type = TREE_TYPE (valist);
5837 /* Args grow down. Not handled by generic routines. */
5839 u = fold_convert (valist_type, size_in_bytes (type));
5840 t = build (MINUS_EXPR, valist_type, valist, u);
5842 /* Copied from va-pa.h, but we probably don't need to align to
5843 word size, since we generate and preserve that invariant. */
5844 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
5845 t = build (BIT_AND_EXPR, valist_type, t, u);
5847 t = build (MODIFY_EXPR, valist_type, valist, t);
5849 ofs = (8 - size) % 4;
5852 u = fold_convert (valist_type, size_int (ofs));
5853 t = build (PLUS_EXPR, valist_type, t, u);
5856 t = fold_convert (ptr, t);
5857 t = build_va_arg_indirect_ref (t);
5860 t = build_va_arg_indirect_ref (t);
5866 /* True if MODE is valid for the target. By "valid", we mean able to
5867 be manipulated in non-trivial ways. In particular, this means all
5868 the arithmetic is supported.
5870 Currently, TImode is not valid as the HP 64-bit runtime documentation
5871 doesn't document the alignment and calling conventions for this type.
5872 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
5873 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
5876 pa_scalar_mode_supported_p (enum machine_mode mode)
5878 int precision = GET_MODE_PRECISION (mode);
5880 switch (GET_MODE_CLASS (mode))
5882 case MODE_PARTIAL_INT:
5884 if (precision == CHAR_TYPE_SIZE)
5886 if (precision == SHORT_TYPE_SIZE)
5888 if (precision == INT_TYPE_SIZE)
5890 if (precision == LONG_TYPE_SIZE)
5892 if (precision == LONG_LONG_TYPE_SIZE)
5897 if (precision == FLOAT_TYPE_SIZE)
5899 if (precision == DOUBLE_TYPE_SIZE)
5901 if (precision == LONG_DOUBLE_TYPE_SIZE)
5910 /* This routine handles all the normal conditional branch sequences we
5911 might need to generate. It handles compare immediate vs compare
5912 register, nullification of delay slots, varying length branches,
5913 negated branches, and all combinations of the above. It returns the
5914 output appropriate to emit the branch corresponding to all given
5918 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
5920 static char buf[100];
5924 /* A conditional branch to the following instruction (e.g. the delay slot)
5925 is asking for a disaster. This can happen when not optimizing and
5926 when jump optimization fails.
5928 While it is usually safe to emit nothing, this can fail if the
5929 preceding instruction is a nullified branch with an empty delay
5930 slot and the same branch target as this branch. We could check
5931 for this but jump optimization should eliminate nop jumps. It
5932 is always safe to emit a nop. */
5933 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5936 /* The doubleword form of the cmpib instruction doesn't have the LEU
5937 and GTU conditions while the cmpb instruction does. Since we accept
5938 zero for cmpb, we must ensure that we use cmpb for the comparison. */
5939 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
5940 operands[2] = gen_rtx_REG (DImode, 0);
5941 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
5942 operands[1] = gen_rtx_REG (DImode, 0);
5944 /* If this is a long branch with its delay slot unfilled, set `nullify'
5945 as it can nullify the delay slot and save a nop. */
5946 if (length == 8 && dbr_sequence_length () == 0)
5949 /* If this is a short forward conditional branch which did not get
5950 its delay slot filled, the delay slot can still be nullified. */
5951 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5952 nullify = forward_branch_p (insn);
5954 /* A forward branch over a single nullified insn can be done with a
5955 comclr instruction. This avoids a single cycle penalty due to
5956 mis-predicted branch if we fall through (branch not taken). */
5958 && next_real_insn (insn) != 0
5959 && get_attr_length (next_real_insn (insn)) == 4
5960 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5966 /* All short conditional branches except backwards with an unfilled
5970 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5972 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5973 if (GET_MODE (operands[1]) == DImode)
5976 strcat (buf, "%B3");
5978 strcat (buf, "%S3");
5980 strcat (buf, " %2,%r1,%%r0");
5982 strcat (buf, ",n %2,%r1,%0");
5984 strcat (buf, " %2,%r1,%0");
5987 /* All long conditionals. Note a short backward branch with an
5988 unfilled delay slot is treated just like a long backward branch
5989 with an unfilled delay slot. */
5991 /* Handle weird backwards branch with a filled delay slot
5992 with is nullified. */
5993 if (dbr_sequence_length () != 0
5994 && ! forward_branch_p (insn)
5997 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5998 if (GET_MODE (operands[1]) == DImode)
6001 strcat (buf, "%S3");
6003 strcat (buf, "%B3");
6004 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6006 /* Handle short backwards branch with an unfilled delay slot.
6007 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6008 taken and untaken branches. */
6009 else if (dbr_sequence_length () == 0
6010 && ! forward_branch_p (insn)
6011 && INSN_ADDRESSES_SET_P ()
6012 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6013 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6015 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6016 if (GET_MODE (operands[1]) == DImode)
6019 strcat (buf, "%B3 %2,%r1,%0%#");
6021 strcat (buf, "%S3 %2,%r1,%0%#");
6025 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6026 if (GET_MODE (operands[1]) == DImode)
6029 strcat (buf, "%S3");
6031 strcat (buf, "%B3");
6033 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6035 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6041 xoperands[0] = operands[0];
6042 xoperands[1] = operands[1];
6043 xoperands[2] = operands[2];
6044 xoperands[3] = operands[3];
6046 /* The reversed conditional branch must branch over one additional
6047 instruction if the delay slot is filled. If the delay slot
6048 is empty, the instruction after the reversed condition branch
6049 must be nullified. */
6050 nullify = dbr_sequence_length () == 0;
6051 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6053 /* Create a reversed conditional branch which branches around
6054 the following insns. */
6055 if (GET_MODE (operands[1]) != DImode)
6061 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6064 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6070 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6073 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6082 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6085 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6091 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6094 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6098 output_asm_insn (buf, xoperands);
6099 return output_lbranch (operands[0], insn);
6107 /* This routine handles long unconditional branches that exceed the
6108 maximum range of a simple branch instruction. */
6111 output_lbranch (rtx dest, rtx insn)
6115 xoperands[0] = dest;
6117 /* First, free up the delay slot. */
6118 if (dbr_sequence_length () != 0)
6120 /* We can't handle a jump in the delay slot. */
6121 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6123 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6126 /* Now delete the delay insn. */
6127 PUT_CODE (NEXT_INSN (insn), NOTE);
6128 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6129 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6132 /* Output an insn to save %r1. The runtime documentation doesn't
6133 specify whether the "Clean Up" slot in the callers frame can
6134 be clobbered by the callee. It isn't copied by HP's builtin
6135 alloca, so this suggests that it can be clobbered if necessary.
6136 The "Static Link" location is copied by HP builtin alloca, so
6137 we avoid using it. Using the cleanup slot might be a problem
6138 if we have to interoperate with languages that pass cleanup
6139 information. However, it should be possible to handle these
6140 situations with GCC's asm feature.
6142 The "Current RP" slot is reserved for the called procedure, so
6143 we try to use it when we don't have a frame of our own. It's
6144 rather unlikely that we won't have a frame when we need to emit
6147 Really the way to go long term is a register scavenger; goto
6148 the target of the jump and find a register which we can use
6149 as a scratch to hold the value in %r1. Then, we wouldn't have
6150 to free up the delay slot or clobber a slot that may be needed
6151 for other purposes. */
6154 if (actual_fsize == 0 && !regs_ever_live[2])
6155 /* Use the return pointer slot in the frame marker. */
6156 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6158 /* Use the slot at -40 in the frame marker since HP builtin
6159 alloca doesn't copy it. */
6160 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6164 if (actual_fsize == 0 && !regs_ever_live[2])
6165 /* Use the return pointer slot in the frame marker. */
6166 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6168 /* Use the "Clean Up" slot in the frame marker. In GCC,
6169 the only other use of this location is for copying a
6170 floating point double argument from a floating-point
6171 register to two general registers. The copy is done
6172 as an "atomic" operation when outputting a call, so it
6173 won't interfere with our using the location here. */
6174 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6177 if (TARGET_PORTABLE_RUNTIME)
6179 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6180 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6181 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6185 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6186 if (TARGET_SOM || !TARGET_GAS)
6188 xoperands[1] = gen_label_rtx ();
6189 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6190 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6191 CODE_LABEL_NUMBER (xoperands[1]));
6192 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6196 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6197 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6199 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6202 /* Now output a very long branch to the original target. */
6203 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6205 /* Now restore the value of %r1 in the delay slot. */
6208 if (actual_fsize == 0 && !regs_ever_live[2])
6209 return "ldd -16(%%r30),%%r1";
6211 return "ldd -40(%%r30),%%r1";
6215 if (actual_fsize == 0 && !regs_ever_live[2])
6216 return "ldw -20(%%r30),%%r1";
6218 return "ldw -12(%%r30),%%r1";
6222 /* This routine handles all the branch-on-bit conditional branch sequences we
6223 might need to generate. It handles nullification of delay slots,
6224 varying length branches, negated branches and all combinations of the
6225 above. it returns the appropriate output template to emit the branch. */
6228 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6229 int negated, rtx insn, int which)
6231 static char buf[100];
6234 /* A conditional branch to the following instruction (e.g. the delay slot) is
6235 asking for a disaster. I do not think this can happen as this pattern
6236 is only used when optimizing; jump optimization should eliminate the
6237 jump. But be prepared just in case. */
6239 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6242 /* If this is a long branch with its delay slot unfilled, set `nullify'
6243 as it can nullify the delay slot and save a nop. */
6244 if (length == 8 && dbr_sequence_length () == 0)
6247 /* If this is a short forward conditional branch which did not get
6248 its delay slot filled, the delay slot can still be nullified. */
6249 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6250 nullify = forward_branch_p (insn);
6252 /* A forward branch over a single nullified insn can be done with a
6253 extrs instruction. This avoids a single cycle penalty due to
6254 mis-predicted branch if we fall through (branch not taken). */
6257 && next_real_insn (insn) != 0
6258 && get_attr_length (next_real_insn (insn)) == 4
6259 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6266 /* All short conditional branches except backwards with an unfilled
6270 strcpy (buf, "{extrs,|extrw,s,}");
6272 strcpy (buf, "bb,");
6273 if (useskip && GET_MODE (operands[0]) == DImode)
6274 strcpy (buf, "extrd,s,*");
6275 else if (GET_MODE (operands[0]) == DImode)
6276 strcpy (buf, "bb,*");
6277 if ((which == 0 && negated)
6278 || (which == 1 && ! negated))
6283 strcat (buf, " %0,%1,1,%%r0");
6284 else if (nullify && negated)
6285 strcat (buf, ",n %0,%1,%3");
6286 else if (nullify && ! negated)
6287 strcat (buf, ",n %0,%1,%2");
6288 else if (! nullify && negated)
6289 strcat (buf, "%0,%1,%3");
6290 else if (! nullify && ! negated)
6291 strcat (buf, " %0,%1,%2");
6294 /* All long conditionals. Note a short backward branch with an
6295 unfilled delay slot is treated just like a long backward branch
6296 with an unfilled delay slot. */
6298 /* Handle weird backwards branch with a filled delay slot
6299 with is nullified. */
6300 if (dbr_sequence_length () != 0
6301 && ! forward_branch_p (insn)
6304 strcpy (buf, "bb,");
6305 if (GET_MODE (operands[0]) == DImode)
6307 if ((which == 0 && negated)
6308 || (which == 1 && ! negated))
6313 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6315 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6317 /* Handle short backwards branch with an unfilled delay slot.
6318 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6319 taken and untaken branches. */
6320 else if (dbr_sequence_length () == 0
6321 && ! forward_branch_p (insn)
6322 && INSN_ADDRESSES_SET_P ()
6323 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6324 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6326 strcpy (buf, "bb,");
6327 if (GET_MODE (operands[0]) == DImode)
6329 if ((which == 0 && negated)
6330 || (which == 1 && ! negated))
6335 strcat (buf, " %0,%1,%3%#");
6337 strcat (buf, " %0,%1,%2%#");
6341 strcpy (buf, "{extrs,|extrw,s,}");
6342 if (GET_MODE (operands[0]) == DImode)
6343 strcpy (buf, "extrd,s,*");
6344 if ((which == 0 && negated)
6345 || (which == 1 && ! negated))
6349 if (nullify && negated)
6350 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6351 else if (nullify && ! negated)
6352 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6354 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6356 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6366 /* This routine handles all the branch-on-variable-bit conditional branch
6367 sequences we might need to generate. It handles nullification of delay
6368 slots, varying length branches, negated branches and all combinations
6369 of the above. it returns the appropriate output template to emit the
6373 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6374 int negated, rtx insn, int which)
6376 static char buf[100];
6379 /* A conditional branch to the following instruction (e.g. the delay slot) is
6380 asking for a disaster. I do not think this can happen as this pattern
6381 is only used when optimizing; jump optimization should eliminate the
6382 jump. But be prepared just in case. */
6384 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6387 /* If this is a long branch with its delay slot unfilled, set `nullify'
6388 as it can nullify the delay slot and save a nop. */
6389 if (length == 8 && dbr_sequence_length () == 0)
6392 /* If this is a short forward conditional branch which did not get
6393 its delay slot filled, the delay slot can still be nullified. */
6394 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6395 nullify = forward_branch_p (insn);
6397 /* A forward branch over a single nullified insn can be done with a
6398 extrs instruction. This avoids a single cycle penalty due to
6399 mis-predicted branch if we fall through (branch not taken). */
6402 && next_real_insn (insn) != 0
6403 && get_attr_length (next_real_insn (insn)) == 4
6404 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6411 /* All short conditional branches except backwards with an unfilled
6415 strcpy (buf, "{vextrs,|extrw,s,}");
6417 strcpy (buf, "{bvb,|bb,}");
6418 if (useskip && GET_MODE (operands[0]) == DImode)
6419 strcpy (buf, "extrd,s,*");
6420 else if (GET_MODE (operands[0]) == DImode)
6421 strcpy (buf, "bb,*");
6422 if ((which == 0 && negated)
6423 || (which == 1 && ! negated))
6428 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6429 else if (nullify && negated)
6430 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6431 else if (nullify && ! negated)
6432 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6433 else if (! nullify && negated)
6434 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6435 else if (! nullify && ! negated)
6436 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6439 /* All long conditionals. Note a short backward branch with an
6440 unfilled delay slot is treated just like a long backward branch
6441 with an unfilled delay slot. */
6443 /* Handle weird backwards branch with a filled delay slot
6444 with is nullified. */
6445 if (dbr_sequence_length () != 0
6446 && ! forward_branch_p (insn)
6449 strcpy (buf, "{bvb,|bb,}");
6450 if (GET_MODE (operands[0]) == DImode)
6452 if ((which == 0 && negated)
6453 || (which == 1 && ! negated))
6458 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6460 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6462 /* Handle short backwards branch with an unfilled delay slot.
6463 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6464 taken and untaken branches. */
6465 else if (dbr_sequence_length () == 0
6466 && ! forward_branch_p (insn)
6467 && INSN_ADDRESSES_SET_P ()
6468 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6469 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6471 strcpy (buf, "{bvb,|bb,}");
6472 if (GET_MODE (operands[0]) == DImode)
6474 if ((which == 0 && negated)
6475 || (which == 1 && ! negated))
6480 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6482 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6486 strcpy (buf, "{vextrs,|extrw,s,}");
6487 if (GET_MODE (operands[0]) == DImode)
6488 strcpy (buf, "extrd,s,*");
6489 if ((which == 0 && negated)
6490 || (which == 1 && ! negated))
6494 if (nullify && negated)
6495 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6496 else if (nullify && ! negated)
6497 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6499 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6501 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6511 /* Return the output template for emitting a dbra type insn.
6513 Note it may perform some output operations on its own before
6514 returning the final output string. */
6516 output_dbra (rtx *operands, rtx insn, int which_alternative)
6519 /* A conditional branch to the following instruction (e.g. the delay slot) is
6520 asking for a disaster. Be prepared! */
6522 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6524 if (which_alternative == 0)
6525 return "ldo %1(%0),%0";
6526 else if (which_alternative == 1)
6528 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6529 output_asm_insn ("ldw -16(%%r30),%4", operands);
6530 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6531 return "{fldws|fldw} -16(%%r30),%0";
6535 output_asm_insn ("ldw %0,%4", operands);
6536 return "ldo %1(%4),%4\n\tstw %4,%0";
6540 if (which_alternative == 0)
6542 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6543 int length = get_attr_length (insn);
6545 /* If this is a long branch with its delay slot unfilled, set `nullify'
6546 as it can nullify the delay slot and save a nop. */
6547 if (length == 8 && dbr_sequence_length () == 0)
6550 /* If this is a short forward conditional branch which did not get
6551 its delay slot filled, the delay slot can still be nullified. */
6552 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6553 nullify = forward_branch_p (insn);
6559 return "addib,%C2,n %1,%0,%3";
6561 return "addib,%C2 %1,%0,%3";
6564 /* Handle weird backwards branch with a fulled delay slot
6565 which is nullified. */
6566 if (dbr_sequence_length () != 0
6567 && ! forward_branch_p (insn)
6569 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6570 /* Handle short backwards branch with an unfilled delay slot.
6571 Using a addb;nop rather than addi;bl saves 1 cycle for both
6572 taken and untaken branches. */
6573 else if (dbr_sequence_length () == 0
6574 && ! forward_branch_p (insn)
6575 && INSN_ADDRESSES_SET_P ()
6576 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6577 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6578 return "addib,%C2 %1,%0,%3%#";
6580 /* Handle normal cases. */
6582 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6584 return "addi,%N2 %1,%0,%0\n\tb %3";
6591 /* Deal with gross reload from FP register case. */
6592 else if (which_alternative == 1)
6594 /* Move loop counter from FP register to MEM then into a GR,
6595 increment the GR, store the GR into MEM, and finally reload
6596 the FP register from MEM from within the branch's delay slot. */
6597 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6599 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6600 if (get_attr_length (insn) == 24)
6601 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6603 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6605 /* Deal with gross reload from memory case. */
6608 /* Reload loop counter from memory, the store back to memory
6609 happens in the branch's delay slot. */
6610 output_asm_insn ("ldw %0,%4", operands);
6611 if (get_attr_length (insn) == 12)
6612 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6614 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6618 /* Return the output template for emitting a dbra type insn.
6620 Note it may perform some output operations on its own before
6621 returning the final output string. */
6623 output_movb (rtx *operands, rtx insn, int which_alternative,
6624 int reverse_comparison)
6627 /* A conditional branch to the following instruction (e.g. the delay slot) is
6628 asking for a disaster. Be prepared! */
6630 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6632 if (which_alternative == 0)
6633 return "copy %1,%0";
6634 else if (which_alternative == 1)
6636 output_asm_insn ("stw %1,-16(%%r30)", operands);
6637 return "{fldws|fldw} -16(%%r30),%0";
6639 else if (which_alternative == 2)
6645 /* Support the second variant. */
6646 if (reverse_comparison)
6647 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6649 if (which_alternative == 0)
6651 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6652 int length = get_attr_length (insn);
6654 /* If this is a long branch with its delay slot unfilled, set `nullify'
6655 as it can nullify the delay slot and save a nop. */
6656 if (length == 8 && dbr_sequence_length () == 0)
6659 /* If this is a short forward conditional branch which did not get
6660 its delay slot filled, the delay slot can still be nullified. */
6661 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6662 nullify = forward_branch_p (insn);
6668 return "movb,%C2,n %1,%0,%3";
6670 return "movb,%C2 %1,%0,%3";
6673 /* Handle weird backwards branch with a filled delay slot
6674 which is nullified. */
6675 if (dbr_sequence_length () != 0
6676 && ! forward_branch_p (insn)
6678 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6680 /* Handle short backwards branch with an unfilled delay slot.
6681 Using a movb;nop rather than or;bl saves 1 cycle for both
6682 taken and untaken branches. */
6683 else if (dbr_sequence_length () == 0
6684 && ! forward_branch_p (insn)
6685 && INSN_ADDRESSES_SET_P ()
6686 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6687 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6688 return "movb,%C2 %1,%0,%3%#";
6689 /* Handle normal cases. */
6691 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6693 return "or,%N2 %1,%%r0,%0\n\tb %3";
6699 /* Deal with gross reload from FP register case. */
6700 else if (which_alternative == 1)
6702 /* Move loop counter from FP register to MEM then into a GR,
6703 increment the GR, store the GR into MEM, and finally reload
6704 the FP register from MEM from within the branch's delay slot. */
6705 output_asm_insn ("stw %1,-16(%%r30)", operands);
6706 if (get_attr_length (insn) == 12)
6707 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6709 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6711 /* Deal with gross reload from memory case. */
6712 else if (which_alternative == 2)
6714 /* Reload loop counter from memory, the store back to memory
6715 happens in the branch's delay slot. */
6716 if (get_attr_length (insn) == 8)
6717 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6719 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6721 /* Handle SAR as a destination. */
6724 if (get_attr_length (insn) == 8)
6725 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6727 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6731 /* Copy any FP arguments in INSN into integer registers. */
6733 copy_fp_args (rtx insn)
6738 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6740 int arg_mode, regno;
6741 rtx use = XEXP (link, 0);
6743 if (! (GET_CODE (use) == USE
6744 && GET_CODE (XEXP (use, 0)) == REG
6745 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6748 arg_mode = GET_MODE (XEXP (use, 0));
6749 regno = REGNO (XEXP (use, 0));
6751 /* Is it a floating point register? */
6752 if (regno >= 32 && regno <= 39)
6754 /* Copy the FP register into an integer register via memory. */
6755 if (arg_mode == SFmode)
6757 xoperands[0] = XEXP (use, 0);
6758 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6759 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6760 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6764 xoperands[0] = XEXP (use, 0);
6765 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6766 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6767 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6768 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6774 /* Compute length of the FP argument copy sequence for INSN. */
6776 length_fp_args (rtx insn)
6781 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6783 int arg_mode, regno;
6784 rtx use = XEXP (link, 0);
6786 if (! (GET_CODE (use) == USE
6787 && GET_CODE (XEXP (use, 0)) == REG
6788 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6791 arg_mode = GET_MODE (XEXP (use, 0));
6792 regno = REGNO (XEXP (use, 0));
6794 /* Is it a floating point register? */
6795 if (regno >= 32 && regno <= 39)
6797 if (arg_mode == SFmode)
6807 /* Return the attribute length for the millicode call instruction INSN.
6808 The length must match the code generated by output_millicode_call.
6809 We include the delay slot in the returned length as it is better to
6810 over estimate the length than to under estimate it. */
6813 attr_length_millicode_call (rtx insn)
6815 unsigned long distance = -1;
6816 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6818 if (INSN_ADDRESSES_SET_P ())
6820 distance = (total + insn_current_reference_address (insn));
6821 if (distance < total)
6827 if (!TARGET_LONG_CALLS && distance < 7600000)
6832 else if (TARGET_PORTABLE_RUNTIME)
6836 if (!TARGET_LONG_CALLS && distance < 240000)
6839 if (TARGET_LONG_ABS_CALL && !flag_pic)
6846 /* INSN is a function call. It may have an unconditional jump
6849 CALL_DEST is the routine we are calling. */
6852 output_millicode_call (rtx insn, rtx call_dest)
6854 int attr_length = get_attr_length (insn);
6855 int seq_length = dbr_sequence_length ();
6860 xoperands[0] = call_dest;
6861 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6863 /* Handle the common case where we are sure that the branch will
6864 reach the beginning of the $CODE$ subspace. The within reach
6865 form of the $$sh_func_adrs call has a length of 28. Because
6866 it has an attribute type of multi, it never has a nonzero
6867 sequence length. The length of the $$sh_func_adrs is the same
6868 as certain out of reach PIC calls to other routines. */
6869 if (!TARGET_LONG_CALLS
6870 && ((seq_length == 0
6871 && (attr_length == 12
6872 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6873 || (seq_length != 0 && attr_length == 8)))
6875 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6881 /* It might seem that one insn could be saved by accessing
6882 the millicode function using the linkage table. However,
6883 this doesn't work in shared libraries and other dynamically
6884 loaded objects. Using a pc-relative sequence also avoids
6885 problems related to the implicit use of the gp register. */
6886 output_asm_insn ("b,l .+8,%%r1", xoperands);
6890 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6891 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6895 xoperands[1] = gen_label_rtx ();
6896 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6897 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6898 CODE_LABEL_NUMBER (xoperands[1]));
6899 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6902 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6904 else if (TARGET_PORTABLE_RUNTIME)
6906 /* Pure portable runtime doesn't allow be/ble; we also don't
6907 have PIC support in the assembler/linker, so this sequence
6910 /* Get the address of our target into %r1. */
6911 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6912 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6914 /* Get our return address into %r31. */
6915 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6916 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6918 /* Jump to our target address in %r1. */
6919 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6923 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6925 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6927 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6931 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6932 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6934 if (TARGET_SOM || !TARGET_GAS)
6936 /* The HP assembler can generate relocations for the
6937 difference of two symbols. GAS can do this for a
6938 millicode symbol but not an arbitrary external
6939 symbol when generating SOM output. */
6940 xoperands[1] = gen_label_rtx ();
6941 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6942 CODE_LABEL_NUMBER (xoperands[1]));
6943 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6944 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6948 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6949 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6953 /* Jump to our target address in %r1. */
6954 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6958 if (seq_length == 0)
6959 output_asm_insn ("nop", xoperands);
6961 /* We are done if there isn't a jump in the delay slot. */
6962 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6965 /* This call has an unconditional jump in its delay slot. */
6966 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6968 /* See if the return address can be adjusted. Use the containing
6969 sequence insn's address. */
6970 if (INSN_ADDRESSES_SET_P ())
6972 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6973 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6974 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6976 if (VAL_14_BITS_P (distance))
6978 xoperands[1] = gen_label_rtx ();
6979 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6980 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6981 CODE_LABEL_NUMBER (xoperands[1]));
6984 /* ??? This branch may not reach its target. */
6985 output_asm_insn ("nop\n\tb,n %0", xoperands);
6988 /* ??? This branch may not reach its target. */
6989 output_asm_insn ("nop\n\tb,n %0", xoperands);
6991 /* Delete the jump. */
6992 PUT_CODE (NEXT_INSN (insn), NOTE);
6993 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6994 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6999 /* Return the attribute length of the call instruction INSN. The SIBCALL
7000 flag indicates whether INSN is a regular call or a sibling call. The
7001 length returned must be longer than the code actually generated by
7002 output_call. Since branch shortening is done before delay branch
7003 sequencing, there is no way to determine whether or not the delay
7004 slot will be filled during branch shortening. Even when the delay
7005 slot is filled, we may have to add a nop if the delay slot contains
7006 a branch that can't reach its target. Thus, we always have to include
7007 the delay slot in the length estimate. This used to be done in
7008 pa_adjust_insn_length but we do it here now as some sequences always
7009 fill the delay slot and we can save four bytes in the estimate for
7013 attr_length_call (rtx insn, int sibcall)
7019 rtx pat = PATTERN (insn);
7020 unsigned long distance = -1;
7022 if (INSN_ADDRESSES_SET_P ())
7024 unsigned long total;
7026 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7027 distance = (total + insn_current_reference_address (insn));
7028 if (distance < total)
7032 /* Determine if this is a local call. */
7033 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7034 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7036 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7038 call_decl = SYMBOL_REF_DECL (call_dest);
7039 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7041 /* pc-relative branch. */
7042 if (!TARGET_LONG_CALLS
7043 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7044 || distance < 240000))
7047 /* 64-bit plabel sequence. */
7048 else if (TARGET_64BIT && !local_call)
7049 length += sibcall ? 28 : 24;
7051 /* non-pic long absolute branch sequence. */
7052 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7055 /* long pc-relative branch sequence. */
7056 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7057 || (TARGET_64BIT && !TARGET_GAS)
7058 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7062 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7066 /* 32-bit plabel sequence. */
7072 length += length_fp_args (insn);
7082 if (!TARGET_NO_SPACE_REGS)
7090 /* INSN is a function call. It may have an unconditional jump
7093 CALL_DEST is the routine we are calling. */
7096 output_call (rtx insn, rtx call_dest, int sibcall)
7098 int delay_insn_deleted = 0;
7099 int delay_slot_filled = 0;
7100 int seq_length = dbr_sequence_length ();
7101 tree call_decl = SYMBOL_REF_DECL (call_dest);
7102 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7105 xoperands[0] = call_dest;
7107 /* Handle the common case where we're sure that the branch will reach
7108 the beginning of the "$CODE$" subspace. This is the beginning of
7109 the current function if we are in a named section. */
7110 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7112 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7113 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7117 if (TARGET_64BIT && !local_call)
7119 /* ??? As far as I can tell, the HP linker doesn't support the
7120 long pc-relative sequence described in the 64-bit runtime
7121 architecture. So, we use a slightly longer indirect call. */
7122 xoperands[0] = get_deferred_plabel (call_dest);
7123 xoperands[1] = gen_label_rtx ();
7125 /* If this isn't a sibcall, we put the load of %r27 into the
7126 delay slot. We can't do this in a sibcall as we don't
7127 have a second call-clobbered scratch register available. */
7129 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7132 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7135 /* Now delete the delay insn. */
7136 PUT_CODE (NEXT_INSN (insn), NOTE);
7137 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7138 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7139 delay_insn_deleted = 1;
7142 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7143 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7144 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7148 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7149 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7150 output_asm_insn ("bve (%%r1)", xoperands);
7154 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7155 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7156 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7157 delay_slot_filled = 1;
7162 int indirect_call = 0;
7164 /* Emit a long call. There are several different sequences
7165 of increasing length and complexity. In most cases,
7166 they don't allow an instruction in the delay slot. */
7167 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7168 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7169 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7174 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7176 && (!TARGET_PA_20 || indirect_call))
7178 /* A non-jump insn in the delay slot. By definition we can
7179 emit this insn before the call (and in fact before argument
7181 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7184 /* Now delete the delay insn. */
7185 PUT_CODE (NEXT_INSN (insn), NOTE);
7186 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7187 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7188 delay_insn_deleted = 1;
7191 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7193 /* This is the best sequence for making long calls in
7194 non-pic code. Unfortunately, GNU ld doesn't provide
7195 the stub needed for external calls, and GAS's support
7196 for this with the SOM linker is buggy. It is safe
7197 to use this for local calls. */
7198 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7200 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7204 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7207 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7209 output_asm_insn ("copy %%r31,%%r2", xoperands);
7210 delay_slot_filled = 1;
7215 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7216 || (TARGET_64BIT && !TARGET_GAS))
7218 /* The HP assembler and linker can handle relocations
7219 for the difference of two symbols. GAS and the HP
7220 linker can't do this when one of the symbols is
7222 xoperands[1] = gen_label_rtx ();
7223 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7224 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7225 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7226 CODE_LABEL_NUMBER (xoperands[1]));
7227 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7229 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7231 /* GAS currently can't generate the relocations that
7232 are needed for the SOM linker under HP-UX using this
7233 sequence. The GNU linker doesn't generate the stubs
7234 that are needed for external calls on TARGET_ELF32
7235 with this sequence. For now, we have to use a
7236 longer plabel sequence when using GAS. */
7237 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7238 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7240 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7245 /* Emit a long plabel-based call sequence. This is
7246 essentially an inline implementation of $$dyncall.
7247 We don't actually try to call $$dyncall as this is
7248 as difficult as calling the function itself. */
7249 xoperands[0] = get_deferred_plabel (call_dest);
7250 xoperands[1] = gen_label_rtx ();
7252 /* Since the call is indirect, FP arguments in registers
7253 need to be copied to the general registers. Then, the
7254 argument relocation stub will copy them back. */
7256 copy_fp_args (insn);
7260 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7261 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7262 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7266 output_asm_insn ("addil LR'%0-$global$,%%r27",
7268 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7272 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7273 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7274 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7275 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7277 if (!sibcall && !TARGET_PA_20)
7279 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7280 if (TARGET_NO_SPACE_REGS)
7281 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7283 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7290 output_asm_insn ("bve (%%r1)", xoperands);
7295 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7296 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7297 delay_slot_filled = 1;
7300 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7305 if (!TARGET_NO_SPACE_REGS)
7306 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7311 if (TARGET_NO_SPACE_REGS)
7312 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7314 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7318 if (TARGET_NO_SPACE_REGS)
7319 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7321 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7324 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7326 output_asm_insn ("copy %%r31,%%r2", xoperands);
7327 delay_slot_filled = 1;
7334 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7335 output_asm_insn ("nop", xoperands);
7337 /* We are done if there isn't a jump in the delay slot. */
7339 || delay_insn_deleted
7340 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7343 /* A sibcall should never have a branch in the delay slot. */
7344 gcc_assert (!sibcall);
7346 /* This call has an unconditional jump in its delay slot. */
7347 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7349 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7351 /* See if the return address can be adjusted. Use the containing
7352 sequence insn's address. */
7353 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7354 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7355 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7357 if (VAL_14_BITS_P (distance))
7359 xoperands[1] = gen_label_rtx ();
7360 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7361 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7362 CODE_LABEL_NUMBER (xoperands[1]));
7365 output_asm_insn ("nop\n\tb,n %0", xoperands);
7368 output_asm_insn ("b,n %0", xoperands);
7370 /* Delete the jump. */
7371 PUT_CODE (NEXT_INSN (insn), NOTE);
7372 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7373 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7378 /* Return the attribute length of the indirect call instruction INSN.
7379 The length must match the code generated by output_indirect call.
7380 The returned length includes the delay slot. Currently, the delay
7381 slot of an indirect call sequence is not exposed and it is used by
7382 the sequence itself. */
7385 attr_length_indirect_call (rtx insn)
7387 unsigned long distance = -1;
7388 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7390 if (INSN_ADDRESSES_SET_P ())
7392 distance = (total + insn_current_reference_address (insn));
7393 if (distance < total)
7400 if (TARGET_FAST_INDIRECT_CALLS
7401 || (!TARGET_PORTABLE_RUNTIME
7402 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7408 if (TARGET_PORTABLE_RUNTIME)
7411 /* Out of reach, can use ble. */
7416 output_indirect_call (rtx insn, rtx call_dest)
7422 xoperands[0] = call_dest;
7423 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7424 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7428 /* First the special case for kernels, level 0 systems, etc. */
7429 if (TARGET_FAST_INDIRECT_CALLS)
7430 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7432 /* Now the normal case -- we can reach $$dyncall directly or
7433 we're sure that we can get there via a long-branch stub.
7435 No need to check target flags as the length uniquely identifies
7436 the remaining cases. */
7437 if (attr_length_indirect_call (insn) == 8)
7439 /* The HP linker substitutes a BLE for millicode calls using
7440 the short PIC PCREL form. Thus, we must use %r31 as the
7441 link register when generating PA 1.x code. */
7443 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7445 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7448 /* Long millicode call, but we are not generating PIC or portable runtime
7450 if (attr_length_indirect_call (insn) == 12)
7451 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7453 /* Long millicode call for portable runtime. */
7454 if (attr_length_indirect_call (insn) == 20)
7455 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7457 /* We need a long PIC call to $$dyncall. */
7458 xoperands[0] = NULL_RTX;
7459 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7460 if (TARGET_SOM || !TARGET_GAS)
7462 xoperands[0] = gen_label_rtx ();
7463 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7464 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7465 CODE_LABEL_NUMBER (xoperands[0]));
7466 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7470 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7471 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7474 output_asm_insn ("blr %%r0,%%r2", xoperands);
7475 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7479 /* Return the total length of the save and restore instructions needed for
7480 the data linkage table pointer (i.e., the PIC register) across the call
7481 instruction INSN. No-return calls do not require a save and restore.
7482 In addition, we may be able to avoid the save and restore for calls
7483 within the same translation unit. */
7486 attr_length_save_restore_dltp (rtx insn)
7488 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7494 /* In HPUX 8.0's shared library scheme, special relocations are needed
7495 for function labels if they might be passed to a function
7496 in a shared library (because shared libraries don't live in code
7497 space), and special magic is needed to construct their address. */
7500 hppa_encode_label (rtx sym)
7502 const char *str = XSTR (sym, 0);
7503 int len = strlen (str) + 1;
7506 p = newstr = alloca (len + 1);
7510 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7514 pa_encode_section_info (tree decl, rtx rtl, int first)
7516 default_encode_section_info (decl, rtl, first);
7518 if (first && TEXT_SPACE_P (decl))
7520 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7521 if (TREE_CODE (decl) == FUNCTION_DECL)
7522 hppa_encode_label (XEXP (rtl, 0));
7526 /* This is sort of inverse to pa_encode_section_info. */
7529 pa_strip_name_encoding (const char *str)
7531 str += (*str == '@');
7532 str += (*str == '*');
7537 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7539 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7542 /* Returns 1 if OP is a function label involved in a simple addition
7543 with a constant. Used to keep certain patterns from matching
7544 during instruction combination. */
7546 is_function_label_plus_const (rtx op)
7548 /* Strip off any CONST. */
7549 if (GET_CODE (op) == CONST)
7552 return (GET_CODE (op) == PLUS
7553 && function_label_operand (XEXP (op, 0), Pmode)
7554 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7557 /* Output assembly code for a thunk to FUNCTION. */
7560 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7561 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7564 static unsigned int current_thunk_number;
7565 int val_14 = VAL_14_BITS_P (delta);
7570 xoperands[0] = XEXP (DECL_RTL (function), 0);
7571 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7572 xoperands[2] = GEN_INT (delta);
7574 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7575 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7577 /* Output the thunk. We know that the function is in the same
7578 translation unit (i.e., the same space) as the thunk, and that
7579 thunks are output after their method. Thus, we don't need an
7580 external branch to reach the function. With SOM and GAS,
7581 functions and thunks are effectively in different sections.
7582 Thus, we can always use a IA-relative branch and the linker
7583 will add a long branch stub if necessary.
7585 However, we have to be careful when generating PIC code on the
7586 SOM port to ensure that the sequence does not transfer to an
7587 import stub for the target function as this could clobber the
7588 return value saved at SP-24. This would also apply to the
7589 32-bit linux port if the multi-space model is implemented. */
7590 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7591 && !(flag_pic && TREE_PUBLIC (function))
7592 && (TARGET_GAS || last_address < 262132))
7593 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7594 && ((targetm.have_named_sections
7595 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7596 /* The GNU 64-bit linker has rather poor stub management.
7597 So, we use a long branch from thunks that aren't in
7598 the same section as the target function. */
7600 && (DECL_SECTION_NAME (thunk_fndecl)
7601 != DECL_SECTION_NAME (function)))
7602 || ((DECL_SECTION_NAME (thunk_fndecl)
7603 == DECL_SECTION_NAME (function))
7604 && last_address < 262132)))
7605 || (!targetm.have_named_sections && last_address < 262132))))
7608 output_asm_insn ("addil L'%2,%%r26", xoperands);
7610 output_asm_insn ("b %0", xoperands);
7614 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7619 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7623 else if (TARGET_64BIT)
7625 /* We only have one call-clobbered scratch register, so we can't
7626 make use of the delay slot if delta doesn't fit in 14 bits. */
7629 output_asm_insn ("addil L'%2,%%r26", xoperands);
7630 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7633 output_asm_insn ("b,l .+8,%%r1", xoperands);
7637 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7638 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7642 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7643 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7648 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7649 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7654 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7658 else if (TARGET_PORTABLE_RUNTIME)
7660 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7661 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7664 output_asm_insn ("addil L'%2,%%r26", xoperands);
7666 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7670 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7675 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7679 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7681 /* The function is accessible from outside this module. The only
7682 way to avoid an import stub between the thunk and function is to
7683 call the function directly with an indirect sequence similar to
7684 that used by $$dyncall. This is possible because $$dyncall acts
7685 as the import stub in an indirect call. */
7686 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7687 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7688 output_asm_insn ("addil LT'%3,%%r19", xoperands);
7689 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
7690 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7691 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
7692 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
7693 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
7694 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7698 output_asm_insn ("addil L'%2,%%r26", xoperands);
7704 output_asm_insn ("bve (%%r22)", xoperands);
7707 else if (TARGET_NO_SPACE_REGS)
7709 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
7714 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
7715 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
7716 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
7721 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7723 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7727 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7729 if (TARGET_SOM || !TARGET_GAS)
7731 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
7732 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
7736 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7737 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
7741 output_asm_insn ("addil L'%2,%%r26", xoperands);
7743 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7747 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7752 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7759 output_asm_insn ("addil L'%2,%%r26", xoperands);
7761 output_asm_insn ("ldil L'%0,%%r22", xoperands);
7762 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
7766 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7771 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7776 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7778 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7781 output_asm_insn (".align 4", xoperands);
7782 ASM_OUTPUT_LABEL (file, label);
7783 output_asm_insn (".word P'%0", xoperands);
7785 else if (TARGET_SOM && TARGET_GAS)
7788 current_thunk_number++;
7789 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7790 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7791 last_address += nbytes;
7792 update_total_code_bytes (nbytes);
7795 /* Only direct calls to static functions are allowed to be sibling (tail)
7798 This restriction is necessary because some linker generated stubs will
7799 store return pointers into rp' in some cases which might clobber a
7800 live value already in rp'.
7802 In a sibcall the current function and the target function share stack
7803 space. Thus if the path to the current function and the path to the
7804 target function save a value in rp', they save the value into the
7805 same stack slot, which has undesirable consequences.
7807 Because of the deferred binding nature of shared libraries any function
7808 with external scope could be in a different load module and thus require
7809 rp' to be saved when calling that function. So sibcall optimizations
7810 can only be safe for static function.
7812 Note that GCC never needs return value relocations, so we don't have to
7813 worry about static calls with return value relocations (which require
7816 It is safe to perform a sibcall optimization when the target function
7817 will never return. */
7819 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7821 if (TARGET_PORTABLE_RUNTIME)
7824 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7825 single subspace mode and the call is not indirect. As far as I know,
7826 there is no operating system support for the multiple subspace mode.
7827 It might be possible to support indirect calls if we didn't use
7828 $$dyncall (see the indirect sequence generated in output_call). */
7830 return (decl != NULL_TREE);
7832 /* Sibcalls are not ok because the arg pointer register is not a fixed
7833 register. This prevents the sibcall optimization from occurring. In
7834 addition, there are problems with stub placement using GNU ld. This
7835 is because a normal sibcall branch uses a 17-bit relocation while
7836 a regular call branch uses a 22-bit relocation. As a result, more
7837 care needs to be taken in the placement of long-branch stubs. */
7841 /* Sibcalls are only ok within a translation unit. */
7842 return (decl && !TREE_PUBLIC (decl));
7845 /* ??? Addition is not commutative on the PA due to the weird implicit
7846 space register selection rules for memory addresses. Therefore, we
7847 don't consider a + b == b + a, as this might be inside a MEM. */
7849 pa_commutative_p (rtx x, int outer_code)
7851 return (COMMUTATIVE_P (x)
7852 && (TARGET_NO_SPACE_REGS
7853 || (outer_code != UNKNOWN && outer_code != MEM)
7854 || GET_CODE (x) != PLUS));
7857 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7858 use in fmpyadd instructions. */
7860 fmpyaddoperands (rtx *operands)
7862 enum machine_mode mode = GET_MODE (operands[0]);
7864 /* Must be a floating point mode. */
7865 if (mode != SFmode && mode != DFmode)
7868 /* All modes must be the same. */
7869 if (! (mode == GET_MODE (operands[1])
7870 && mode == GET_MODE (operands[2])
7871 && mode == GET_MODE (operands[3])
7872 && mode == GET_MODE (operands[4])
7873 && mode == GET_MODE (operands[5])))
7876 /* All operands must be registers. */
7877 if (! (GET_CODE (operands[1]) == REG
7878 && GET_CODE (operands[2]) == REG
7879 && GET_CODE (operands[3]) == REG
7880 && GET_CODE (operands[4]) == REG
7881 && GET_CODE (operands[5]) == REG))
7884 /* Only 2 real operands to the addition. One of the input operands must
7885 be the same as the output operand. */
7886 if (! rtx_equal_p (operands[3], operands[4])
7887 && ! rtx_equal_p (operands[3], operands[5]))
7890 /* Inout operand of add cannot conflict with any operands from multiply. */
7891 if (rtx_equal_p (operands[3], operands[0])
7892 || rtx_equal_p (operands[3], operands[1])
7893 || rtx_equal_p (operands[3], operands[2]))
7896 /* multiply cannot feed into addition operands. */
7897 if (rtx_equal_p (operands[4], operands[0])
7898 || rtx_equal_p (operands[5], operands[0]))
7901 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7903 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7904 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7905 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7906 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7907 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7908 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7911 /* Passed. Operands are suitable for fmpyadd. */
7915 #if !defined(USE_COLLECT2)
7917 pa_asm_out_constructor (rtx symbol, int priority)
7919 if (!function_label_operand (symbol, VOIDmode))
7920 hppa_encode_label (symbol);
7922 #ifdef CTORS_SECTION_ASM_OP
7923 default_ctor_section_asm_out_constructor (symbol, priority);
7925 # ifdef TARGET_ASM_NAMED_SECTION
7926 default_named_section_asm_out_constructor (symbol, priority);
7928 default_stabs_asm_out_constructor (symbol, priority);
7934 pa_asm_out_destructor (rtx symbol, int priority)
7936 if (!function_label_operand (symbol, VOIDmode))
7937 hppa_encode_label (symbol);
7939 #ifdef DTORS_SECTION_ASM_OP
7940 default_dtor_section_asm_out_destructor (symbol, priority);
7942 # ifdef TARGET_ASM_NAMED_SECTION
7943 default_named_section_asm_out_destructor (symbol, priority);
7945 default_stabs_asm_out_destructor (symbol, priority);
7951 /* This function places uninitialized global data in the bss section.
7952 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
7953 function on the SOM port to prevent uninitialized global data from
7954 being placed in the data section. */
7957 pa_asm_output_aligned_bss (FILE *stream,
7959 unsigned HOST_WIDE_INT size,
7963 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7965 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7966 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7969 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7970 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7973 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7974 ASM_OUTPUT_LABEL (stream, name);
7975 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
7978 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
7979 that doesn't allow the alignment of global common storage to be directly
7980 specified. The SOM linker aligns common storage based on the rounded
7981 value of the NUM_BYTES parameter in the .comm directive. It's not
7982 possible to use the .align directive as it doesn't affect the alignment
7983 of the label associated with a .comm directive. */
7986 pa_asm_output_aligned_common (FILE *stream,
7988 unsigned HOST_WIDE_INT size,
7991 unsigned int max_common_align;
7993 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
7994 if (align > max_common_align)
7996 warning (0, "alignment (%u) for %s exceeds maximum alignment "
7997 "for global common data. Using %u",
7998 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
7999 align = max_common_align;
8004 assemble_name (stream, name);
8005 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8006 MAX (size, align / BITS_PER_UNIT));
8009 /* We can't use .comm for local common storage as the SOM linker effectively
8010 treats the symbol as universal and uses the same storage for local symbols
8011 with the same name in different object files. The .block directive
8012 reserves an uninitialized block of storage. However, it's not common
8013 storage. Fortunately, GCC never requests common storage with the same
8014 name in any given translation unit. */
8017 pa_asm_output_aligned_local (FILE *stream,
8019 unsigned HOST_WIDE_INT size,
8023 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8026 fprintf (stream, "%s", LOCAL_ASM_OP);
8027 assemble_name (stream, name);
8028 fprintf (stream, "\n");
8031 ASM_OUTPUT_LABEL (stream, name);
8032 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8035 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8036 use in fmpysub instructions. */
8038 fmpysuboperands (rtx *operands)
8040 enum machine_mode mode = GET_MODE (operands[0]);
8042 /* Must be a floating point mode. */
8043 if (mode != SFmode && mode != DFmode)
8046 /* All modes must be the same. */
8047 if (! (mode == GET_MODE (operands[1])
8048 && mode == GET_MODE (operands[2])
8049 && mode == GET_MODE (operands[3])
8050 && mode == GET_MODE (operands[4])
8051 && mode == GET_MODE (operands[5])))
8054 /* All operands must be registers. */
8055 if (! (GET_CODE (operands[1]) == REG
8056 && GET_CODE (operands[2]) == REG
8057 && GET_CODE (operands[3]) == REG
8058 && GET_CODE (operands[4]) == REG
8059 && GET_CODE (operands[5]) == REG))
8062 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8063 operation, so operands[4] must be the same as operand[3]. */
8064 if (! rtx_equal_p (operands[3], operands[4]))
8067 /* multiply cannot feed into subtraction. */
8068 if (rtx_equal_p (operands[5], operands[0]))
8071 /* Inout operand of sub cannot conflict with any operands from multiply. */
8072 if (rtx_equal_p (operands[3], operands[0])
8073 || rtx_equal_p (operands[3], operands[1])
8074 || rtx_equal_p (operands[3], operands[2]))
8077 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8079 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8080 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8081 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8082 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8083 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8084 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8087 /* Passed. Operands are suitable for fmpysub. */
8091 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8092 constants for shadd instructions. */
8094 shadd_constant_p (int val)
8096 if (val == 2 || val == 4 || val == 8)
8102 /* Return 1 if OP is valid as a base or index register in a
8106 borx_reg_operand (rtx op, enum machine_mode mode)
8108 if (GET_CODE (op) != REG)
8111 /* We must reject virtual registers as the only expressions that
8112 can be instantiated are REG and REG+CONST. */
8113 if (op == virtual_incoming_args_rtx
8114 || op == virtual_stack_vars_rtx
8115 || op == virtual_stack_dynamic_rtx
8116 || op == virtual_outgoing_args_rtx
8117 || op == virtual_cfa_rtx)
8120 /* While it's always safe to index off the frame pointer, it's not
8121 profitable to do so when the frame pointer is being eliminated. */
8122 if (!reload_completed
8123 && flag_omit_frame_pointer
8124 && !current_function_calls_alloca
8125 && op == frame_pointer_rtx)
8128 return register_operand (op, mode);
8131 /* Return 1 if this operand is anything other than a hard register. */
8134 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8136 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8139 /* Return 1 if INSN branches forward. Should be using insn_addresses
8140 to avoid walking through all the insns... */
8142 forward_branch_p (rtx insn)
8144 rtx label = JUMP_LABEL (insn);
8151 insn = NEXT_INSN (insn);
8154 return (insn == label);
8157 /* Return 1 if OP is an equality comparison, else return 0. */
8159 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8161 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8164 /* Return 1 if INSN is in the delay slot of a call instruction. */
8166 jump_in_call_delay (rtx insn)
8169 if (GET_CODE (insn) != JUMP_INSN)
8172 if (PREV_INSN (insn)
8173 && PREV_INSN (PREV_INSN (insn))
8174 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8176 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8178 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8179 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8186 /* Output an unconditional move and branch insn. */
8189 output_parallel_movb (rtx *operands, int length)
8191 /* These are the cases in which we win. */
8193 return "mov%I1b,tr %1,%0,%2";
8195 /* None of these cases wins, but they don't lose either. */
8196 if (dbr_sequence_length () == 0)
8198 /* Nothing in the delay slot, fake it by putting the combined
8199 insn (the copy or add) in the delay slot of a bl. */
8200 if (GET_CODE (operands[1]) == CONST_INT)
8201 return "b %2\n\tldi %1,%0";
8203 return "b %2\n\tcopy %1,%0";
8207 /* Something in the delay slot, but we've got a long branch. */
8208 if (GET_CODE (operands[1]) == CONST_INT)
8209 return "ldi %1,%0\n\tb %2";
8211 return "copy %1,%0\n\tb %2";
8215 /* Output an unconditional add and branch insn. */
8218 output_parallel_addb (rtx *operands, int length)
8220 /* To make life easy we want operand0 to be the shared input/output
8221 operand and operand1 to be the readonly operand. */
8222 if (operands[0] == operands[1])
8223 operands[1] = operands[2];
8225 /* These are the cases in which we win. */
8227 return "add%I1b,tr %1,%0,%3";
8229 /* None of these cases win, but they don't lose either. */
8230 if (dbr_sequence_length () == 0)
8232 /* Nothing in the delay slot, fake it by putting the combined
8233 insn (the copy or add) in the delay slot of a bl. */
8234 return "b %3\n\tadd%I1 %1,%0,%0";
8238 /* Something in the delay slot, but we've got a long branch. */
8239 return "add%I1 %1,%0,%0\n\tb %3";
8243 /* Return nonzero if INSN (a jump insn) immediately follows a call
8244 to a named function. This is used to avoid filling the delay slot
8245 of the jump since it can usually be eliminated by modifying RP in
8246 the delay slot of the call. */
8249 following_call (rtx insn)
8251 if (! TARGET_JUMP_IN_DELAY)
8254 /* Find the previous real insn, skipping NOTEs. */
8255 insn = PREV_INSN (insn);
8256 while (insn && GET_CODE (insn) == NOTE)
8257 insn = PREV_INSN (insn);
8259 /* Check for CALL_INSNs and millicode calls. */
8261 && ((GET_CODE (insn) == CALL_INSN
8262 && get_attr_type (insn) != TYPE_DYNCALL)
8263 || (GET_CODE (insn) == INSN
8264 && GET_CODE (PATTERN (insn)) != SEQUENCE
8265 && GET_CODE (PATTERN (insn)) != USE
8266 && GET_CODE (PATTERN (insn)) != CLOBBER
8267 && get_attr_type (insn) == TYPE_MILLI)))
8273 /* We use this hook to perform a PA specific optimization which is difficult
8274 to do in earlier passes.
8276 We want the delay slots of branches within jump tables to be filled.
8277 None of the compiler passes at the moment even has the notion that a
8278 PA jump table doesn't contain addresses, but instead contains actual
8281 Because we actually jump into the table, the addresses of each entry
8282 must stay constant in relation to the beginning of the table (which
8283 itself must stay constant relative to the instruction to jump into
8284 it). I don't believe we can guarantee earlier passes of the compiler
8285 will adhere to those rules.
8287 So, late in the compilation process we find all the jump tables, and
8288 expand them into real code -- e.g. each entry in the jump table vector
8289 will get an appropriate label followed by a jump to the final target.
8291 Reorg and the final jump pass can then optimize these branches and
8292 fill their delay slots. We end up with smaller, more efficient code.
8294 The jump instructions within the table are special; we must be able
8295 to identify them during assembly output (if the jumps don't get filled
8296 we need to emit a nop rather than nullifying the delay slot)). We
8297 identify jumps in switch tables by using insns with the attribute
8298 type TYPE_BTABLE_BRANCH.
8300 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8301 insns. This serves two purposes, first it prevents jump.c from
8302 noticing that the last N entries in the table jump to the instruction
8303 immediately after the table and deleting the jumps. Second, those
8304 insns mark where we should emit .begin_brtab and .end_brtab directives
8305 when using GAS (allows for better link time optimizations). */
8312 remove_useless_addtr_insns (1);
8314 if (pa_cpu < PROCESSOR_8000)
8315 pa_combine_instructions ();
8318 /* This is fairly cheap, so always run it if optimizing. */
8319 if (optimize > 0 && !TARGET_BIG_SWITCH)
8321 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8322 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8324 rtx pattern, tmp, location, label;
8325 unsigned int length, i;
8327 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8328 if (GET_CODE (insn) != JUMP_INSN
8329 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8330 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8333 /* Emit marker for the beginning of the branch table. */
8334 emit_insn_before (gen_begin_brtab (), insn);
8336 pattern = PATTERN (insn);
8337 location = PREV_INSN (insn);
8338 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8340 for (i = 0; i < length; i++)
8342 /* Emit a label before each jump to keep jump.c from
8343 removing this code. */
8344 tmp = gen_label_rtx ();
8345 LABEL_NUSES (tmp) = 1;
8346 emit_label_after (tmp, location);
8347 location = NEXT_INSN (location);
8349 if (GET_CODE (pattern) == ADDR_VEC)
8350 label = XEXP (XVECEXP (pattern, 0, i), 0);
8352 label = XEXP (XVECEXP (pattern, 1, i), 0);
8354 tmp = gen_short_jump (label);
8356 /* Emit the jump itself. */
8357 tmp = emit_jump_insn_after (tmp, location);
8358 JUMP_LABEL (tmp) = label;
8359 LABEL_NUSES (label)++;
8360 location = NEXT_INSN (location);
8362 /* Emit a BARRIER after the jump. */
8363 emit_barrier_after (location);
8364 location = NEXT_INSN (location);
8367 /* Emit marker for the end of the branch table. */
8368 emit_insn_before (gen_end_brtab (), location);
8369 location = NEXT_INSN (location);
8370 emit_barrier_after (location);
8372 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8378 /* Still need brtab marker insns. FIXME: the presence of these
8379 markers disables output of the branch table to readonly memory,
8380 and any alignment directives that might be needed. Possibly,
8381 the begin_brtab insn should be output before the label for the
8382 table. This doesn't matter at the moment since the tables are
8383 always output in the text section. */
8384 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8386 /* Find an ADDR_VEC insn. */
8387 if (GET_CODE (insn) != JUMP_INSN
8388 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8389 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8392 /* Now generate markers for the beginning and end of the
8394 emit_insn_before (gen_begin_brtab (), insn);
8395 emit_insn_after (gen_end_brtab (), insn);
8400 /* The PA has a number of odd instructions which can perform multiple
8401 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8402 it may be profitable to combine two instructions into one instruction
8403 with two outputs. It's not profitable PA2.0 machines because the
8404 two outputs would take two slots in the reorder buffers.
8406 This routine finds instructions which can be combined and combines
8407 them. We only support some of the potential combinations, and we
8408 only try common ways to find suitable instructions.
8410 * addb can add two registers or a register and a small integer
8411 and jump to a nearby (+-8k) location. Normally the jump to the
8412 nearby location is conditional on the result of the add, but by
8413 using the "true" condition we can make the jump unconditional.
8414 Thus addb can perform two independent operations in one insn.
8416 * movb is similar to addb in that it can perform a reg->reg
8417 or small immediate->reg copy and jump to a nearby (+-8k location).
8419 * fmpyadd and fmpysub can perform a FP multiply and either an
8420 FP add or FP sub if the operands of the multiply and add/sub are
8421 independent (there are other minor restrictions). Note both
8422 the fmpy and fadd/fsub can in theory move to better spots according
8423 to data dependencies, but for now we require the fmpy stay at a
8426 * Many of the memory operations can perform pre & post updates
8427 of index registers. GCC's pre/post increment/decrement addressing
8428 is far too simple to take advantage of all the possibilities. This
8429 pass may not be suitable since those insns may not be independent.
8431 * comclr can compare two ints or an int and a register, nullify
8432 the following instruction and zero some other register. This
8433 is more difficult to use as it's harder to find an insn which
8434 will generate a comclr than finding something like an unconditional
8435 branch. (conditional moves & long branches create comclr insns).
8437 * Most arithmetic operations can conditionally skip the next
8438 instruction. They can be viewed as "perform this operation
8439 and conditionally jump to this nearby location" (where nearby
8440 is an insns away). These are difficult to use due to the
8441 branch length restrictions. */
8444 pa_combine_instructions (void)
8448 /* This can get expensive since the basic algorithm is on the
8449 order of O(n^2) (or worse). Only do it for -O2 or higher
8450 levels of optimization. */
8454 /* Walk down the list of insns looking for "anchor" insns which
8455 may be combined with "floating" insns. As the name implies,
8456 "anchor" instructions don't move, while "floating" insns may
8458 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8459 new = make_insn_raw (new);
8461 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8463 enum attr_pa_combine_type anchor_attr;
8464 enum attr_pa_combine_type floater_attr;
8466 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8467 Also ignore any special USE insns. */
8468 if ((GET_CODE (anchor) != INSN
8469 && GET_CODE (anchor) != JUMP_INSN
8470 && GET_CODE (anchor) != CALL_INSN)
8471 || GET_CODE (PATTERN (anchor)) == USE
8472 || GET_CODE (PATTERN (anchor)) == CLOBBER
8473 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8474 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8477 anchor_attr = get_attr_pa_combine_type (anchor);
8478 /* See if anchor is an insn suitable for combination. */
8479 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8480 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8481 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8482 && ! forward_branch_p (anchor)))
8486 for (floater = PREV_INSN (anchor);
8488 floater = PREV_INSN (floater))
8490 if (GET_CODE (floater) == NOTE
8491 || (GET_CODE (floater) == INSN
8492 && (GET_CODE (PATTERN (floater)) == USE
8493 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8496 /* Anything except a regular INSN will stop our search. */
8497 if (GET_CODE (floater) != INSN
8498 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8499 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8505 /* See if FLOATER is suitable for combination with the
8507 floater_attr = get_attr_pa_combine_type (floater);
8508 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8509 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8510 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8511 && floater_attr == PA_COMBINE_TYPE_FMPY))
8513 /* If ANCHOR and FLOATER can be combined, then we're
8514 done with this pass. */
8515 if (pa_can_combine_p (new, anchor, floater, 0,
8516 SET_DEST (PATTERN (floater)),
8517 XEXP (SET_SRC (PATTERN (floater)), 0),
8518 XEXP (SET_SRC (PATTERN (floater)), 1)))
8522 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8523 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8525 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8527 if (pa_can_combine_p (new, anchor, floater, 0,
8528 SET_DEST (PATTERN (floater)),
8529 XEXP (SET_SRC (PATTERN (floater)), 0),
8530 XEXP (SET_SRC (PATTERN (floater)), 1)))
8535 if (pa_can_combine_p (new, anchor, floater, 0,
8536 SET_DEST (PATTERN (floater)),
8537 SET_SRC (PATTERN (floater)),
8538 SET_SRC (PATTERN (floater))))
8544 /* If we didn't find anything on the backwards scan try forwards. */
8546 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8547 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8549 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8551 if (GET_CODE (floater) == NOTE
8552 || (GET_CODE (floater) == INSN
8553 && (GET_CODE (PATTERN (floater)) == USE
8554 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8558 /* Anything except a regular INSN will stop our search. */
8559 if (GET_CODE (floater) != INSN
8560 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8561 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8567 /* See if FLOATER is suitable for combination with the
8569 floater_attr = get_attr_pa_combine_type (floater);
8570 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8571 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8572 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8573 && floater_attr == PA_COMBINE_TYPE_FMPY))
8575 /* If ANCHOR and FLOATER can be combined, then we're
8576 done with this pass. */
8577 if (pa_can_combine_p (new, anchor, floater, 1,
8578 SET_DEST (PATTERN (floater)),
8579 XEXP (SET_SRC (PATTERN (floater)),
8581 XEXP (SET_SRC (PATTERN (floater)),
8588 /* FLOATER will be nonzero if we found a suitable floating
8589 insn for combination with ANCHOR. */
8591 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8592 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8594 /* Emit the new instruction and delete the old anchor. */
8595 emit_insn_before (gen_rtx_PARALLEL
8597 gen_rtvec (2, PATTERN (anchor),
8598 PATTERN (floater))),
8601 PUT_CODE (anchor, NOTE);
8602 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8603 NOTE_SOURCE_FILE (anchor) = 0;
8605 /* Emit a special USE insn for FLOATER, then delete
8606 the floating insn. */
8607 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8608 delete_insn (floater);
8613 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8616 /* Emit the new_jump instruction and delete the old anchor. */
8618 = emit_jump_insn_before (gen_rtx_PARALLEL
8620 gen_rtvec (2, PATTERN (anchor),
8621 PATTERN (floater))),
8624 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8625 PUT_CODE (anchor, NOTE);
8626 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8627 NOTE_SOURCE_FILE (anchor) = 0;
8629 /* Emit a special USE insn for FLOATER, then delete
8630 the floating insn. */
8631 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8632 delete_insn (floater);
8640 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8643 int insn_code_number;
8646 /* Create a PARALLEL with the patterns of ANCHOR and
8647 FLOATER, try to recognize it, then test constraints
8648 for the resulting pattern.
8650 If the pattern doesn't match or the constraints
8651 aren't met keep searching for a suitable floater
8653 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8654 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8655 INSN_CODE (new) = -1;
8656 insn_code_number = recog_memoized (new);
8657 if (insn_code_number < 0
8658 || (extract_insn (new), ! constrain_operands (1)))
8672 /* There's up to three operands to consider. One
8673 output and two inputs.
8675 The output must not be used between FLOATER & ANCHOR
8676 exclusive. The inputs must not be set between
8677 FLOATER and ANCHOR exclusive. */
8679 if (reg_used_between_p (dest, start, end))
8682 if (reg_set_between_p (src1, start, end))
8685 if (reg_set_between_p (src2, start, end))
8688 /* If we get here, then everything is good. */
8692 /* Return nonzero if references for INSN are delayed.
8694 Millicode insns are actually function calls with some special
8695 constraints on arguments and register usage.
8697 Millicode calls always expect their arguments in the integer argument
8698 registers, and always return their result in %r29 (ret1). They
8699 are expected to clobber their arguments, %r1, %r29, and the return
8700 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8702 This function tells reorg that the references to arguments and
8703 millicode calls do not appear to happen until after the millicode call.
8704 This allows reorg to put insns which set the argument registers into the
8705 delay slot of the millicode call -- thus they act more like traditional
8708 Note we cannot consider side effects of the insn to be delayed because
8709 the branch and link insn will clobber the return pointer. If we happened
8710 to use the return pointer in the delay slot of the call, then we lose.
8712 get_attr_type will try to recognize the given insn, so make sure to
8713 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8716 insn_refs_are_delayed (rtx insn)
8718 return ((GET_CODE (insn) == INSN
8719 && GET_CODE (PATTERN (insn)) != SEQUENCE
8720 && GET_CODE (PATTERN (insn)) != USE
8721 && GET_CODE (PATTERN (insn)) != CLOBBER
8722 && get_attr_type (insn) == TYPE_MILLI));
8725 /* On the HP-PA the value is found in register(s) 28(-29), unless
8726 the mode is SF or DF. Then the value is returned in fr4 (32).
8728 This must perform the same promotions as PROMOTE_MODE, else
8729 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8731 Small structures must be returned in a PARALLEL on PA64 in order
8732 to match the HP Compiler ABI. */
8735 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8737 enum machine_mode valmode;
8739 if (AGGREGATE_TYPE_P (valtype))
8743 /* Aggregates with a size less than or equal to 128 bits are
8744 returned in GR 28(-29). They are left justified. The pad
8745 bits are undefined. Larger aggregates are returned in
8749 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8751 for (i = 0; i < ub; i++)
8753 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8754 gen_rtx_REG (DImode, 28 + i),
8759 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8761 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
8763 /* Aggregates 5 to 8 bytes in size are returned in general
8764 registers r28-r29 in the same manner as other non
8765 floating-point objects. The data is right-justified and
8766 zero-extended to 64 bits. This is opposite to the normal
8767 justification used on big endian targets and requires
8768 special treatment. */
8769 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8770 gen_rtx_REG (DImode, 28), const0_rtx);
8771 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
8775 if ((INTEGRAL_TYPE_P (valtype)
8776 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8777 || POINTER_TYPE_P (valtype))
8778 valmode = word_mode;
8780 valmode = TYPE_MODE (valtype);
8782 if (TREE_CODE (valtype) == REAL_TYPE
8783 && !AGGREGATE_TYPE_P (valtype)
8784 && TYPE_MODE (valtype) != TFmode
8785 && !TARGET_SOFT_FLOAT)
8786 return gen_rtx_REG (valmode, 32);
8788 return gen_rtx_REG (valmode, 28);
8791 /* Return the location of a parameter that is passed in a register or NULL
8792 if the parameter has any component that is passed in memory.
8794 This is new code and will be pushed to into the net sources after
8797 ??? We might want to restructure this so that it looks more like other
8800 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8801 int named ATTRIBUTE_UNUSED)
8803 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8810 if (mode == VOIDmode)
8813 arg_size = FUNCTION_ARG_SIZE (mode, type);
8815 /* If this arg would be passed partially or totally on the stack, then
8816 this routine should return zero. pa_arg_partial_bytes will
8817 handle arguments which are split between regs and stack slots if
8818 the ABI mandates split arguments. */
8821 /* The 32-bit ABI does not split arguments. */
8822 if (cum->words + arg_size > max_arg_words)
8828 alignment = cum->words & 1;
8829 if (cum->words + alignment >= max_arg_words)
8833 /* The 32bit ABIs and the 64bit ABIs are rather different,
8834 particularly in their handling of FP registers. We might
8835 be able to cleverly share code between them, but I'm not
8836 going to bother in the hope that splitting them up results
8837 in code that is more easily understood. */
8841 /* Advance the base registers to their current locations.
8843 Remember, gprs grow towards smaller register numbers while
8844 fprs grow to higher register numbers. Also remember that
8845 although FP regs are 32-bit addressable, we pretend that
8846 the registers are 64-bits wide. */
8847 gpr_reg_base = 26 - cum->words;
8848 fpr_reg_base = 32 + cum->words;
8850 /* Arguments wider than one word and small aggregates need special
8854 || (type && AGGREGATE_TYPE_P (type)))
8856 /* Double-extended precision (80-bit), quad-precision (128-bit)
8857 and aggregates including complex numbers are aligned on
8858 128-bit boundaries. The first eight 64-bit argument slots
8859 are associated one-to-one, with general registers r26
8860 through r19, and also with floating-point registers fr4
8861 through fr11. Arguments larger than one word are always
8862 passed in general registers.
8864 Using a PARALLEL with a word mode register results in left
8865 justified data on a big-endian target. */
8868 int i, offset = 0, ub = arg_size;
8870 /* Align the base register. */
8871 gpr_reg_base -= alignment;
8873 ub = MIN (ub, max_arg_words - cum->words - alignment);
8874 for (i = 0; i < ub; i++)
8876 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8877 gen_rtx_REG (DImode, gpr_reg_base),
8883 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8888 /* If the argument is larger than a word, then we know precisely
8889 which registers we must use. */
8903 /* Structures 5 to 8 bytes in size are passed in the general
8904 registers in the same manner as other non floating-point
8905 objects. The data is right-justified and zero-extended
8906 to 64 bits. This is opposite to the normal justification
8907 used on big endian targets and requires special treatment.
8908 We now define BLOCK_REG_PADDING to pad these objects. */
8909 if (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
8911 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8912 gen_rtx_REG (DImode, gpr_reg_base),
8914 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
8919 /* We have a single word (32 bits). A simple computation
8920 will get us the register #s we need. */
8921 gpr_reg_base = 26 - cum->words;
8922 fpr_reg_base = 32 + 2 * cum->words;
8926 /* Determine if the argument needs to be passed in both general and
8927 floating point registers. */
8928 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8929 /* If we are doing soft-float with portable runtime, then there
8930 is no need to worry about FP regs. */
8931 && !TARGET_SOFT_FLOAT
8932 /* The parameter must be some kind of float, else we can just
8933 pass it in integer registers. */
8934 && FLOAT_MODE_P (mode)
8935 /* The target function must not have a prototype. */
8936 && cum->nargs_prototype <= 0
8937 /* libcalls do not need to pass items in both FP and general
8939 && type != NULL_TREE
8940 /* All this hair applies to "outgoing" args only. This includes
8941 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8943 /* Also pass outgoing floating arguments in both registers in indirect
8944 calls with the 32 bit ABI and the HP assembler since there is no
8945 way to the specify argument locations in static functions. */
8950 && FLOAT_MODE_P (mode)))
8956 gen_rtx_EXPR_LIST (VOIDmode,
8957 gen_rtx_REG (mode, fpr_reg_base),
8959 gen_rtx_EXPR_LIST (VOIDmode,
8960 gen_rtx_REG (mode, gpr_reg_base),
8965 /* See if we should pass this parameter in a general register. */
8966 if (TARGET_SOFT_FLOAT
8967 /* Indirect calls in the normal 32bit ABI require all arguments
8968 to be passed in general registers. */
8969 || (!TARGET_PORTABLE_RUNTIME
8973 /* If the parameter is not a floating point parameter, then
8974 it belongs in GPRs. */
8975 || !FLOAT_MODE_P (mode)
8976 /* Structure with single SFmode field belongs in GPR. */
8977 || (type && AGGREGATE_TYPE_P (type)))
8978 retval = gen_rtx_REG (mode, gpr_reg_base);
8980 retval = gen_rtx_REG (mode, fpr_reg_base);
8986 /* If this arg would be passed totally in registers or totally on the stack,
8987 then this routine should return zero. */
8990 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8991 tree type, bool named ATTRIBUTE_UNUSED)
8993 unsigned int max_arg_words = 8;
8994 unsigned int offset = 0;
8999 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9002 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9003 /* Arg fits fully into registers. */
9005 else if (cum->words + offset >= max_arg_words)
9006 /* Arg fully on the stack. */
9010 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9014 /* Return a string to output before text in the current function.
9016 This function is only used with SOM. Because we don't support
9017 named subspaces, we can only create a new subspace or switch back
9018 to the default text subspace. */
9020 som_text_section_asm_op (void)
9027 if (cfun && !cfun->machine->in_nsubspa)
9029 /* We only want to emit a .nsubspa directive once at the
9030 start of the function. */
9031 cfun->machine->in_nsubspa = 1;
9033 /* Create a new subspace for the text. This provides
9034 better stub placement and one-only functions. */
9036 && DECL_ONE_ONLY (cfun->decl)
9037 && !DECL_WEAK (cfun->decl))
9039 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
9041 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
9045 /* There isn't a current function or the body of the current
9046 function has been completed. So, we are changing to the
9047 text section to output debugging information. Do this in
9048 the default text section. We need to forget that we are
9049 in the text section so that the function text_section in
9050 varasm.c will call us the next time around. */
9055 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
9058 /* On hpux10, the linker will give an error if we have a reference
9059 in the read-only data section to a symbol defined in a shared
9060 library. Therefore, expressions that might require a reloc can
9061 not be placed in the read-only data section. */
9064 pa_select_section (tree exp, int reloc,
9065 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9067 if (TREE_CODE (exp) == VAR_DECL
9068 && TREE_READONLY (exp)
9069 && !TREE_THIS_VOLATILE (exp)
9070 && DECL_INITIAL (exp)
9071 && (DECL_INITIAL (exp) == error_mark_node
9072 || TREE_CONSTANT (DECL_INITIAL (exp)))
9076 && DECL_ONE_ONLY (exp)
9077 && !DECL_WEAK (exp))
9078 som_one_only_readonly_data_section ();
9080 readonly_data_section ();
9082 else if (CONSTANT_CLASS_P (exp) && !reloc)
9083 readonly_data_section ();
9085 && TREE_CODE (exp) == VAR_DECL
9086 && DECL_ONE_ONLY (exp)
9087 && !DECL_WEAK (exp))
9088 som_one_only_data_section ();
9094 pa_globalize_label (FILE *stream, const char *name)
9096 /* We only handle DATA objects here, functions are globalized in
9097 ASM_DECLARE_FUNCTION_NAME. */
9098 if (! FUNCTION_NAME_P (name))
9100 fputs ("\t.EXPORT ", stream);
9101 assemble_name (stream, name);
9102 fputs (",DATA\n", stream);
9106 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9109 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9110 int incoming ATTRIBUTE_UNUSED)
9112 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9115 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9118 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9120 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9121 PA64 ABI says that objects larger than 128 bits are returned in memory.
9122 Note, int_size_in_bytes can return -1 if the size of the object is
9123 variable or larger than the maximum value that can be expressed as
9124 a HOST_WIDE_INT. It can also return zero for an empty type. The
9125 simplest way to handle variable and empty types is to pass them in
9126 memory. This avoids problems in defining the boundaries of argument
9127 slots, allocating registers, etc. */
9128 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9129 || int_size_in_bytes (type) <= 0);
9132 /* Structure to hold declaration and name of external symbols that are
9133 emitted by GCC. We generate a vector of these symbols and output them
9134 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9135 This avoids putting out names that are never really used. */
9137 typedef struct extern_symbol GTY(())
9143 /* Define gc'd vector type for extern_symbol. */
9144 DEF_VEC_O(extern_symbol);
9145 DEF_VEC_ALLOC_O(extern_symbol,gc);
9147 /* Vector of extern_symbol pointers. */
9148 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9150 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9151 /* Mark DECL (name NAME) as an external reference (assembler output
9152 file FILE). This saves the names to output at the end of the file
9153 if actually referenced. */
9156 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9158 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9160 gcc_assert (file == asm_out_file);
9165 /* Output text required at the end of an assembler file.
9166 This includes deferred plabels and .import directives for
9167 all external symbols that were actually referenced. */
9170 pa_hpux_file_end (void)
9175 if (!NO_DEFERRED_PROFILE_COUNTERS)
9176 output_deferred_profile_counters ();
9178 output_deferred_plabels ();
9180 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9182 tree decl = p->decl;
9184 if (!TREE_ASM_WRITTEN (decl)
9185 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9186 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9189 VEC_free (extern_symbol, gc, extern_symbols);