1 /* Subroutines for assembler code output on the NS32000.
2 Copyright (C) 1988, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 /* Some output-actions in ns32k.md need these. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
34 int ns32k_num_files = 0;
41 fprintf (stderr, s, s1, s2);
44 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
47 hard_regno_mode_ok (regno, mode)
49 enum machine_mode mode;
60 if (regno < 8 || regno == 16 || regno == 17)
66 if (regno < 8 && (regno & 1) == 0)
111 /* Used to abort here, but simply saying "no" handles TImode
116 /* ADDRESS_COST calls this. This function is not optimal
117 for the 32032 & 32332, but it probably is better than
121 calc_address_cost (operand)
127 if (GET_CODE (operand) == MEM)
129 if (GET_CODE (operand) == MULT)
132 if (GET_CODE (operand) == REG)
133 cost += 1; /* not really, but the documentation
134 says different amount of registers
135 shouldn't return the same costs */
137 switch (GET_CODE (operand))
151 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (operand)); i++)
153 cost += calc_address_cost (XEXP (operand, i));
161 /* Return the register class of a scratch register needed to copy IN into
162 or out of a register in CLASS in MODE. If it can be done directly,
163 NO_REGS is returned. */
166 secondary_reload_class (class, mode, in)
167 enum reg_class class;
168 enum machine_mode mode;
171 int regno = true_regnum (in);
173 if (regno >= FIRST_PSEUDO_REGISTER)
176 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
178 if (class == GENERAL_REGS || (regno >= 0 && regno < 8))
181 /* Constants, memory, and FP registers can go into FP registers. */
182 if ((regno == -1 || (regno >= 8 && regno < 16)) && (class == FLOAT_REGS))
185 #if 0 /* This isn't strictly true (can't move fp to sp or vice versa),
186 so it's cleaner to use PREFERRED_RELOAD_CLASS
187 to make the right things happen. */
188 if (regno >= 16 && class == GEN_AND_MEM_REGS)
192 /* Otherwise, we need GENERAL_REGS. */
195 /* Generate the rtx that comes from an address expression in the md file */
196 /* The expression to be build is BASE[INDEX:SCALE]. To recognize this,
197 scale must be converted from an exponent (from ASHIFT) to a
198 multiplier (for MULT). */
200 gen_indexed_expr (base, index, scale)
201 rtx base, index, scale;
205 /* This generates an illegal addressing mode, if BASE is
206 fp or sp. This is handled by PRINT_OPERAND_ADDRESS. */
207 if (GET_CODE (base) != REG && GET_CODE (base) != CONST_INT)
208 base = gen_rtx (MEM, SImode, base);
209 addr = gen_rtx (MULT, SImode, index,
210 gen_rtx (CONST_INT, VOIDmode, 1 << INTVAL (scale)));
211 addr = gen_rtx (PLUS, SImode, base, addr);
215 /* Return 1 if OP is a valid operand of mode MODE. This
216 predicate rejects operands which do not have a mode
217 (such as CONST_INT which are VOIDmode). */
219 reg_or_mem_operand (op, mode)
221 enum machine_mode mode;
223 return (GET_MODE (op) == mode
224 && (GET_CODE (op) == REG
225 || GET_CODE (op) == SUBREG
226 || GET_CODE (op) == MEM));
229 /* Return the best assembler insn template
230 for moving operands[1] into operands[0] as a fullword. */
233 singlemove_string (operands)
236 if (GET_CODE (operands[1]) == CONST_INT
237 && INTVAL (operands[1]) <= 7
238 && INTVAL (operands[1]) >= -8)
239 return "movqd %1,%0";
244 output_move_double (operands)
247 enum anon1 { REGOP, OFFSOP, PUSHOP, CNSTOP, RNDOP } optype0, optype1;
250 /* First classify both operands. */
252 if (REG_P (operands[0]))
254 else if (offsettable_memref_p (operands[0]))
256 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
261 if (REG_P (operands[1]))
263 else if (CONSTANT_ADDRESS_P (operands[1])
264 || GET_CODE (operands[1]) == CONST_DOUBLE)
266 else if (offsettable_memref_p (operands[1]))
268 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
273 /* Check for the cases that the operand constraints are not
274 supposed to allow to happen. Abort if we get one,
275 because generating code for these cases is painful. */
277 if (optype0 == RNDOP || optype1 == RNDOP)
280 /* Ok, we can do one word at a time.
281 Normally we do the low-numbered word first,
282 but if either operand is autodecrementing then we
283 do the high-numbered word first.
285 In either case, set up in LATEHALF the operands to use
286 for the high-numbered word and in some cases alter the
287 operands in OPERANDS to be suitable for the low-numbered word. */
289 if (optype0 == REGOP)
290 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
291 else if (optype0 == OFFSOP)
292 latehalf[0] = adj_offsettable_operand (operands[0], 4);
294 latehalf[0] = operands[0];
296 if (optype1 == REGOP)
297 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
298 else if (optype1 == OFFSOP)
299 latehalf[1] = adj_offsettable_operand (operands[1], 4);
300 else if (optype1 == CNSTOP)
302 if (CONSTANT_ADDRESS_P (operands[1]))
303 latehalf[1] = const0_rtx;
304 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
305 split_double (operands[1], &operands[1], &latehalf[1]);
308 latehalf[1] = operands[1];
310 /* If insn is effectively movd N(sp),tos then we will do the
311 high word first. We should use the adjusted operand 1 (which is N+4(sp))
312 for the low word as well, to compensate for the first decrement of sp.
313 Given this, it doesn't matter which half we do "first". */
314 if (optype0 == PUSHOP
315 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
316 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
317 operands[1] = latehalf[1];
319 /* If one or both operands autodecrementing,
320 do the two words, high-numbered first. */
321 else if (optype0 == PUSHOP || optype1 == PUSHOP)
323 output_asm_insn (singlemove_string (latehalf), latehalf);
324 return singlemove_string (operands);
327 /* If the first move would clobber the source of the second one,
328 do them in the other order. */
330 /* Overlapping registers. */
331 if (optype0 == REGOP && optype1 == REGOP
332 && REGNO (operands[0]) == REGNO (latehalf[1]))
335 output_asm_insn (singlemove_string (latehalf), latehalf);
336 /* Do low-numbered word. */
337 return singlemove_string (operands);
339 /* Loading into a register which overlaps a register used in the address. */
340 else if (optype0 == REGOP && optype1 != REGOP
341 && reg_overlap_mentioned_p (operands[0], operands[1]))
343 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
344 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
346 /* If both halves of dest are used in the src memory address,
347 add the two regs and put them in the low reg (operands[0]).
348 Then it works to load latehalf first. */
350 xops[0] = latehalf[0];
351 xops[1] = operands[0];
352 output_asm_insn ("addd %0,%1", xops);
353 operands[1] = gen_rtx (MEM, DImode, operands[0]);
354 latehalf[1] = adj_offsettable_operand (operands[1], 4);
355 /* The first half has the overlap, Do the late half first. */
356 output_asm_insn (singlemove_string (latehalf), latehalf);
358 return singlemove_string (operands);
360 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
362 /* The first half has the overlap, Do the late half first. */
363 output_asm_insn (singlemove_string (latehalf), latehalf);
365 return singlemove_string (operands);
369 /* Normal case. Do the two words, low-numbered first. */
371 output_asm_insn (singlemove_string (operands), operands);
373 operands[0] = latehalf[0];
374 operands[1] = latehalf[1];
375 return singlemove_string (operands);
379 check_reg (oper, reg)
387 switch (GET_CODE(oper))
390 return (REGNO(oper) == reg) ? 1 : 0;
392 return check_reg(XEXP(oper, 0), reg);
395 return check_reg(XEXP(oper, 0), reg) || check_reg(XEXP(oper, 1), reg);
400 /* Returns 1 if OP contains a global symbol reference */
403 global_symbolic_reference_mentioned_p (op)
409 if (GET_CODE (op) == SYMBOL_REF)
411 if (! SYMBOL_REF_FLAG (op))
416 else if (GET_CODE (op) != CONST)
419 fmt = GET_RTX_FORMAT (GET_CODE (op));
420 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
426 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
427 if (global_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
430 else if (fmt[i] == 'e'
431 && global_symbolic_reference_mentioned_p (XEXP (op, i)))
439 /* PRINT_OPERAND is defined to call this function,
440 which is easier to debug than putting all the code in
441 a macro definition in ns32k.h. */
444 print_operand (file, x, code)
450 PUT_IMMEDIATE_PREFIX (file);
451 else if (code == '?')
452 PUT_EXTERNAL_PREFIX (file);
453 else if (GET_CODE (x) == REG)
454 fprintf (file, "%s", reg_names[REGNO (x)]);
455 else if (GET_CODE (x) == MEM)
457 rtx tmp = XEXP (x, 0);
458 #if ! (defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC))
459 if (GET_CODE (tmp) != CONST_INT)
461 char *out = XSTR (tmp, 0);
464 PUT_ABSOLUTE_PREFIX (file);
465 fprintf (file, "%s", &out[1]);
468 ASM_OUTPUT_LABELREF (file, out);
472 output_address (XEXP (x, 0));
474 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != DImode)
476 if (GET_MODE (x) == DFmode)
478 union { double d; int i[2]; } u;
479 u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
480 PUT_IMMEDIATE_PREFIX(file);
482 /* Sequent likes it's floating point constants as integers */
483 fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
486 fprintf (file, "0f%.20e", u.d);
488 fprintf (file, "0d%.20e", u.d);
494 union { double d; int i[2]; } u;
495 u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
496 PUT_IMMEDIATE_PREFIX (file);
498 /* We have no way of winning if we can't get the bits
499 for a sequent floating point number. */
500 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
504 union { float f; long l; } uu;
506 fprintf (file, "0Fx%08x", uu.l);
509 fprintf (file, "0f%.20e", u.d);
515 #ifdef NO_IMMEDIATE_PREFIX_IF_SYMBOLIC
516 if (GET_CODE (x) == CONST_INT)
518 PUT_IMMEDIATE_PREFIX (file);
519 output_addr_const (file, x);
523 /* PRINT_OPERAND_ADDRESS is defined to call this function,
524 which is easier to debug than putting all the code in
525 a macro definition in ns32k.h . */
527 /* Completely rewritten to get this to work with Gas for PC532 Mach.
528 This function didn't work and I just wasn't able (nor very willing) to
529 figure out how it worked.
530 90-11-25 Tatu Yl|nen <ylo@cs.hut.fi> */
532 print_operand_address (file, addr)
536 static char scales[] = { 'b', 'w', 'd', 0, 'q', };
537 rtx offset, base, indexexp, tmp;
541 if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_DEC)
543 fprintf (file, "tos");
552 if (GET_CODE (addr) == PLUS)
554 if (GET_CODE (XEXP (addr, 0)) == PLUS)
556 tmp = XEXP (addr, 1);
557 addr = XEXP (addr, 0);
562 addr = XEXP (addr,1);
570 switch (GET_CODE (tmp))
604 if (flag_pic && ! CONSTANT_POOL_ADDRESS_P (tmp)
605 && ! SYMBOL_REF_FLAG (tmp))
617 if (flag_pic && GET_CODE (tmp) == CONST)
621 if (GET_CODE (tmp1) != PLUS)
625 if (GET_CODE (sym) != SYMBOL_REF)
632 if (GET_CODE (sym) == SYMBOL_REF)
634 if (GET_CODE (off) != CONST_INT)
637 if (CONSTANT_POOL_ADDRESS_P (sym)
638 || SYMBOL_REF_FLAG (sym))
640 SYMBOL_REF_FLAG (tmp) = 1;
664 offset = gen_rtx (PLUS, SImode, tmp, offset);
675 #ifdef INDEX_RATHER_THAN_BASE
676 /* This is a re-implementation of the SEQUENT_ADDRESS_BUG fix. */
677 if (base && !indexexp && GET_CODE (base) == REG
678 && REG_OK_FOR_INDEX_P (base))
685 /* now, offset, base and indexexp are set */
688 #if defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC)
689 if (GET_CODE (offset) == CONST_INT)
690 /* if (! (GET_CODE (offset) == LABEL_REF
691 || GET_CODE (offset) == SYMBOL_REF)) */
693 PUT_ABSOLUTE_PREFIX (file);
696 output_addr_const (file, offset);
697 if (base) /* base can be (REG ...) or (MEM ...) */
698 switch (GET_CODE (base))
700 /* now we must output base. Possible alternatives are:
704 (pc) (REG ...) used for SYMBOL_REF and LABEL_REF, output
705 (disp(fp)) (MEM ...) just before possible [rX:y]
710 fprintf (file, "(%s)", reg_names[REGNO (base)]);
717 output_addr_const (file, base);
718 fprintf (file, "(sb))");
726 if (GET_CODE (addr) == PLUS)
728 if (GET_CODE (XEXP (addr, 0)) == PLUS)
730 tmp = XEXP (addr, 1);
731 addr = XEXP (addr, 0);
735 tmp = XEXP (addr, 0);
736 addr = XEXP (addr, 1);
744 switch (GET_CODE (tmp))
754 offset = gen_rtx (PLUS, SImode, tmp, offset);
765 output_addr_const (file, offset);
767 fprintf (file, "(%s)", reg_names[REGNO (base)]);
768 #ifdef BASE_REG_NEEDED
770 fprintf (file, "(sb)");
781 else if (flag_pic && SYMBOL_REF_FLAG (offset))
782 fprintf (file, "(sb)");
785 else if (GET_CODE (offset) == LABEL_REF
786 || GET_CODE (offset) == SYMBOL_REF
787 || GET_CODE (offset) == CONST)
788 fprintf (file, "(pc)");
790 #ifdef BASE_REG_NEEDED /* this is defined if the assembler always
791 needs a base register */
793 fprintf (file, "(sb)");
797 /* now print index if we have one */
800 if (GET_CODE (indexexp) == MULT)
802 scale = INTVAL (XEXP (indexexp, 1)) >> 1;
803 indexexp = XEXP (indexexp, 0);
807 if (GET_CODE (indexexp) != REG || REGNO (indexexp) >= 8)
811 fprintf (file, "[%c`%s]",
813 reg_names[REGNO (indexexp)]);
815 fprintf (file, "[%s:%c]",
816 reg_names[REGNO (indexexp)],
822 /* National 32032 shifting is so bad that we can get
823 better performance in many common cases by using other
826 output_shift_insn (operands)
829 if (GET_CODE (operands[2]) == CONST_INT
830 && INTVAL (operands[2]) > 0
831 && INTVAL (operands[2]) <= 3)
832 if (GET_CODE (operands[0]) == REG)
834 if (GET_CODE (operands[1]) == REG)
836 if (REGNO (operands[0]) == REGNO (operands[1]))
838 if (operands[2] == const1_rtx)
840 else if (INTVAL (operands[2]) == 2)
841 return "addd %0,%0\n\taddd %0,%0";
843 if (operands[2] == const1_rtx)
844 return "movd %1,%0\n\taddd %0,%0";
846 operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
847 return "addr %a1,%0";
849 if (operands[2] == const1_rtx)
850 return "movd %1,%0\n\taddd %0,%0";
852 else if (GET_CODE (operands[1]) == REG)
854 operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
855 return "addr %a1,%0";
857 else if (INTVAL (operands[2]) == 1
858 && GET_CODE (operands[1]) == MEM
859 && rtx_equal_p (operands [0], operands[1]))
861 rtx temp = XEXP (operands[1], 0);
863 if (GET_CODE (temp) == REG
864 || (GET_CODE (temp) == PLUS
865 && GET_CODE (XEXP (temp, 0)) == REG
866 && GET_CODE (XEXP (temp, 1)) == CONST_INT))
869 else return "ashd %2,%0";
874 output_move_dconst (n, s)
881 strcpy (r, "movqd ");
882 else if (n > 0 && n < 256)
883 strcpy (r, "movzbd ");
884 else if (n > 0 && n < 65536)
885 strcpy (r, "movzwd ");
886 else if (n < 0 && n > -257)
887 strcpy (r, "movxbd ");
888 else if (n < 0 && n > -65537)
889 strcpy (r, "movxwd ");