1 /* Subroutines for assembler code output on the NS32000.
2 Copyright (C) 1988, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 /* Some output-actions in ns32k.md need these. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
34 int ns32k_num_files = 0;
41 fprintf (stderr, s, s1, s2);
44 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
47 hard_regno_mode_ok (regno, mode)
49 enum machine_mode mode;
60 if (regno < 8 || regno == 16 || regno == 17)
66 if (regno < 8 && (regno & 1) == 0)
111 /* Used to abort here, but simply saying "no" handles TImode
116 /* ADDRESS_COST calls this. This function is not optimal
117 for the 32032 & 32332, but it probably is better than
121 calc_address_cost (operand)
127 if (GET_CODE (operand) == MEM)
129 if (GET_CODE (operand) == MULT)
132 if (GET_CODE (operand) == REG)
133 cost += 1; /* not really, but the documentation
134 says different amount of registers
135 shouldn't return the same costs */
137 switch (GET_CODE (operand))
151 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (operand)); i++)
153 cost += calc_address_cost (XEXP (operand, i));
161 /* Return the register class of a scratch register needed to copy IN into
162 or out of a register in CLASS in MODE. If it can be done directly,
163 NO_REGS is returned. */
166 secondary_reload_class (class, mode, in)
167 enum reg_class class;
168 enum machine_mode mode;
171 int regno = true_regnum (in);
173 if (regno >= FIRST_PSEUDO_REGISTER)
176 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
178 if (class == GENERAL_REGS || (regno >= 0 && regno < 8))
181 /* Constants, memory, and FP registers can go into FP registers. */
182 if ((regno == -1 || (regno >= 8 && regno < 16)) && (class == FLOAT_REGS))
185 #if 0 /* This isn't strictly true (can't move fp to sp or vice versa),
186 so it's cleaner to use PREFERRED_RELOAD_CLASS
187 to make the right things happen. */
188 if (regno >= 16 && class == GEN_AND_MEM_REGS)
192 /* Otherwise, we need GENERAL_REGS. */
195 /* Generate the rtx that comes from an address expression in the md file */
196 /* The expression to be build is BASE[INDEX:SCALE]. To recognize this,
197 scale must be converted from an exponent (from ASHIFT) to a
198 multiplier (for MULT). */
200 gen_indexed_expr (base, index, scale)
201 rtx base, index, scale;
205 /* This generates an illegal addressing mode, if BASE is
206 fp or sp. This is handled by PRINT_OPERAND_ADDRESS. */
207 if (GET_CODE (base) != REG && GET_CODE (base) != CONST_INT)
208 base = gen_rtx (MEM, SImode, base);
209 addr = gen_rtx (MULT, SImode, index,
210 gen_rtx (CONST_INT, VOIDmode, 1 << INTVAL (scale)));
211 addr = gen_rtx (PLUS, SImode, base, addr);
215 /* Return 1 if OP is a valid operand of mode MODE. This
216 predicate rejects operands which do not have a mode
217 (such as CONST_INT which are VOIDmode). */
219 reg_or_mem_operand (op, mode)
221 enum machine_mode mode;
223 return (GET_MODE (op) == mode
224 && (GET_CODE (op) == REG
225 || GET_CODE (op) == SUBREG
226 || GET_CODE (op) == MEM));
229 /* Return the best assembler insn template
230 for moving operands[1] into operands[0] as a fullword. */
233 singlemove_string (operands)
236 if (GET_CODE (operands[1]) == CONST_INT
237 && INTVAL (operands[1]) <= 7
238 && INTVAL (operands[1]) >= -8)
239 return "movqd %1,%0";
244 output_move_double (operands)
247 enum anon1 { REGOP, OFFSOP, PUSHOP, CNSTOP, RNDOP } optype0, optype1;
250 /* First classify both operands. */
252 if (REG_P (operands[0]))
254 else if (offsettable_memref_p (operands[0]))
256 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
261 if (REG_P (operands[1]))
263 else if (CONSTANT_P (operands[1])
264 || GET_CODE (operands[1]) == CONST_DOUBLE)
266 else if (offsettable_memref_p (operands[1]))
268 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
273 /* Check for the cases that the operand constraints are not
274 supposed to allow to happen. Abort if we get one,
275 because generating code for these cases is painful. */
277 if (optype0 == RNDOP || optype1 == RNDOP)
280 /* Ok, we can do one word at a time.
281 Normally we do the low-numbered word first,
282 but if either operand is autodecrementing then we
283 do the high-numbered word first.
285 In either case, set up in LATEHALF the operands to use
286 for the high-numbered word and in some cases alter the
287 operands in OPERANDS to be suitable for the low-numbered word. */
289 if (optype0 == REGOP)
290 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
291 else if (optype0 == OFFSOP)
292 latehalf[0] = adj_offsettable_operand (operands[0], 4);
294 latehalf[0] = operands[0];
296 if (optype1 == REGOP)
297 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
298 else if (optype1 == OFFSOP)
299 latehalf[1] = adj_offsettable_operand (operands[1], 4);
300 else if (optype1 == CNSTOP)
301 split_double (operands[1], &operands[1], &latehalf[1]);
303 latehalf[1] = operands[1];
305 /* If insn is effectively movd N(sp),tos then we will do the
306 high word first. We should use the adjusted operand 1 (which is N+4(sp))
307 for the low word as well, to compensate for the first decrement of sp.
308 Given this, it doesn't matter which half we do "first". */
309 if (optype0 == PUSHOP
310 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
311 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
312 operands[1] = latehalf[1];
314 /* If one or both operands autodecrementing,
315 do the two words, high-numbered first. */
316 else if (optype0 == PUSHOP || optype1 == PUSHOP)
318 output_asm_insn (singlemove_string (latehalf), latehalf);
319 return singlemove_string (operands);
322 /* If the first move would clobber the source of the second one,
323 do them in the other order. */
325 /* Overlapping registers. */
326 if (optype0 == REGOP && optype1 == REGOP
327 && REGNO (operands[0]) == REGNO (latehalf[1]))
330 output_asm_insn (singlemove_string (latehalf), latehalf);
331 /* Do low-numbered word. */
332 return singlemove_string (operands);
334 /* Loading into a register which overlaps a register used in the address. */
335 else if (optype0 == REGOP && optype1 != REGOP
336 && reg_overlap_mentioned_p (operands[0], operands[1]))
338 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
339 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
341 /* If both halves of dest are used in the src memory address,
342 add the two regs and put them in the low reg (operands[0]).
343 Then it works to load latehalf first. */
345 xops[0] = latehalf[0];
346 xops[1] = operands[0];
347 output_asm_insn ("addd %0,%1", xops);
348 operands[1] = gen_rtx (MEM, DImode, operands[0]);
349 latehalf[1] = adj_offsettable_operand (operands[1], 4);
350 /* The first half has the overlap, Do the late half first. */
351 output_asm_insn (singlemove_string (latehalf), latehalf);
353 return singlemove_string (operands);
355 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
357 /* The first half has the overlap, Do the late half first. */
358 output_asm_insn (singlemove_string (latehalf), latehalf);
360 return singlemove_string (operands);
364 /* Normal case. Do the two words, low-numbered first. */
366 output_asm_insn (singlemove_string (operands), operands);
368 operands[0] = latehalf[0];
369 operands[1] = latehalf[1];
370 return singlemove_string (operands);
374 check_reg (oper, reg)
382 switch (GET_CODE(oper))
385 return (REGNO(oper) == reg) ? 1 : 0;
387 return check_reg(XEXP(oper, 0), reg);
390 return check_reg(XEXP(oper, 0), reg) || check_reg(XEXP(oper, 1), reg);
395 /* Returns 1 if OP contains a global symbol reference */
398 global_symbolic_reference_mentioned_p (op, f)
405 if (GET_CODE (op) == SYMBOL_REF)
407 if (! SYMBOL_REF_FLAG (op))
412 else if (f && GET_CODE (op) != CONST)
415 fmt = GET_RTX_FORMAT (GET_CODE (op));
416 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
422 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
423 if (global_symbolic_reference_mentioned_p (XVECEXP (op, i, j), 0))
426 else if (fmt[i] == 'e'
427 && global_symbolic_reference_mentioned_p (XEXP (op, i), 0))
435 /* PRINT_OPERAND is defined to call this function,
436 which is easier to debug than putting all the code in
437 a macro definition in ns32k.h. */
440 print_operand (file, x, code)
446 PUT_IMMEDIATE_PREFIX (file);
447 else if (code == '?')
448 PUT_EXTERNAL_PREFIX (file);
449 else if (GET_CODE (x) == REG)
450 fprintf (file, "%s", reg_names[REGNO (x)]);
451 else if (GET_CODE (x) == MEM)
453 rtx tmp = XEXP (x, 0);
454 #if ! (defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC))
455 if (GET_CODE (tmp) != CONST_INT)
457 char *out = XSTR (tmp, 0);
460 PUT_ABSOLUTE_PREFIX (file);
461 fprintf (file, "%s", &out[1]);
464 ASM_OUTPUT_LABELREF (file, out);
468 output_address (XEXP (x, 0));
470 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != DImode)
472 if (GET_MODE (x) == DFmode)
474 union { double d; int i[2]; } u;
475 u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
476 PUT_IMMEDIATE_PREFIX(file);
478 /* Sequent likes it's floating point constants as integers */
479 fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
482 fprintf (file, "0f%.20e", u.d);
484 fprintf (file, "0d%.20e", u.d);
490 union { double d; int i[2]; } u;
491 u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
492 PUT_IMMEDIATE_PREFIX (file);
494 /* We have no way of winning if we can't get the bits
495 for a sequent floating point number. */
496 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
500 union { float f; long l; } uu;
502 fprintf (file, "0Fx%08x", uu.l);
505 fprintf (file, "0f%.20e", u.d);
511 #ifdef NO_IMMEDIATE_PREFIX_IF_SYMBOLIC
512 if (GET_CODE (x) == CONST_INT)
514 PUT_IMMEDIATE_PREFIX (file);
515 output_addr_const (file, x);
519 /* PRINT_OPERAND_ADDRESS is defined to call this function,
520 which is easier to debug than putting all the code in
521 a macro definition in ns32k.h . */
523 /* Completely rewritten to get this to work with Gas for PC532 Mach.
524 This function didn't work and I just wasn't able (nor very willing) to
525 figure out how it worked.
526 90-11-25 Tatu Yl|nen <ylo@cs.hut.fi> */
528 print_operand_address (file, addr)
532 static char scales[] = { 'b', 'w', 'd', 0, 'q', };
533 rtx offset, base, indexexp, tmp;
537 if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_DEC)
539 fprintf (file, "tos");
548 if (GET_CODE (addr) == PLUS)
550 if (GET_CODE (XEXP (addr, 0)) == PLUS)
552 tmp = XEXP (addr, 1);
553 addr = XEXP (addr, 0);
558 addr = XEXP (addr,1);
566 switch (GET_CODE (tmp))
600 if (flag_pic && ! CONSTANT_POOL_ADDRESS_P (tmp)
601 && ! SYMBOL_REF_FLAG (tmp))
613 if (flag_pic && GET_CODE (tmp) == CONST)
617 if (GET_CODE (tmp1) != PLUS)
621 if (GET_CODE (sym) != SYMBOL_REF)
628 if (GET_CODE (sym) == SYMBOL_REF)
630 if (GET_CODE (off) != CONST_INT)
633 if (CONSTANT_POOL_ADDRESS_P (sym)
634 || SYMBOL_REF_FLAG (sym))
636 SYMBOL_REF_FLAG (tmp) = 1;
660 offset = gen_rtx (PLUS, SImode, tmp, offset);
672 #ifndef INDEX_RATHER_THAN_BASE
674 && GET_CODE (base) != SYMBOL_REF
675 && GET_CODE (offset) != CONST_INT
677 /* This is a re-implementation of the SEQUENT_ADDRESS_BUG fix. */
679 && !indexexp && GET_CODE (base) == REG
680 && REG_OK_FOR_INDEX_P (base))
686 /* now, offset, base and indexexp are set */
689 #if defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC)
690 if (GET_CODE (offset) == CONST_INT)
691 /* if (! (GET_CODE (offset) == LABEL_REF
692 || GET_CODE (offset) == SYMBOL_REF)) */
694 PUT_ABSOLUTE_PREFIX (file);
697 output_addr_const (file, offset);
698 if (base) /* base can be (REG ...) or (MEM ...) */
699 switch (GET_CODE (base))
701 /* now we must output base. Possible alternatives are:
705 (pc) (REG ...) used for SYMBOL_REF and LABEL_REF, output
706 (disp(fp)) (MEM ...) just before possible [rX:y]
711 fprintf (file, "(%s)", reg_names[REGNO (base)]);
718 output_addr_const (file, base);
719 fprintf (file, "(sb))");
727 if (GET_CODE (addr) == PLUS)
729 if (GET_CODE (XEXP (addr, 0)) == PLUS)
731 tmp = XEXP (addr, 1);
732 addr = XEXP (addr, 0);
736 tmp = XEXP (addr, 0);
737 addr = XEXP (addr, 1);
745 switch (GET_CODE (tmp))
755 offset = gen_rtx (PLUS, SImode, tmp, offset);
766 output_addr_const (file, offset);
768 fprintf (file, "(%s)", reg_names[REGNO (base)]);
769 #ifdef BASE_REG_NEEDED
772 /* Abs. addresses don't need a base (I think). */
773 if (GET_CODE (offset) != CONST_INT
775 && GET_CODE (offset) != LABEL_REF
776 && GET_CODE (offset) != SYMBOL_REF
777 && GET_CODE (offset) != CONST
778 && GET_CODE (offset) != PLUS
783 fprintf (file, "(sb)");
796 else if (GET_CODE (offset) == LABEL_REF
797 || GET_CODE (offset) == SYMBOL_REF
798 || GET_CODE (offset) == CONST
799 || GET_CODE (offset) == PLUS)
800 fprintf (file, "(pc)");
802 #ifdef BASE_REG_NEEDED /* this is defined if the assembler always
803 needs a base register */
805 fprintf (file, "(sb)");
809 /* now print index if we have one */
812 if (GET_CODE (indexexp) == MULT)
814 scale = INTVAL (XEXP (indexexp, 1)) >> 1;
815 indexexp = XEXP (indexexp, 0);
819 if (GET_CODE (indexexp) != REG || REGNO (indexexp) >= 8)
823 fprintf (file, "[%c`%s]",
825 reg_names[REGNO (indexexp)]);
827 fprintf (file, "[%s:%c]",
828 reg_names[REGNO (indexexp)],
834 /* National 32032 shifting is so bad that we can get
835 better performance in many common cases by using other
838 output_shift_insn (operands)
841 if (GET_CODE (operands[2]) == CONST_INT
842 && INTVAL (operands[2]) > 0
843 && INTVAL (operands[2]) <= 3)
844 if (GET_CODE (operands[0]) == REG)
846 if (GET_CODE (operands[1]) == REG)
848 if (REGNO (operands[0]) == REGNO (operands[1]))
850 if (operands[2] == const1_rtx)
852 else if (INTVAL (operands[2]) == 2)
853 return "addd %0,%0\n\taddd %0,%0";
855 if (operands[2] == const1_rtx)
856 return "movd %1,%0\n\taddd %0,%0";
858 operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
859 return "addr %a1,%0";
861 if (operands[2] == const1_rtx)
862 return "movd %1,%0\n\taddd %0,%0";
864 else if (GET_CODE (operands[1]) == REG)
866 operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
867 return "addr %a1,%0";
869 else if (INTVAL (operands[2]) == 1
870 && GET_CODE (operands[1]) == MEM
871 && rtx_equal_p (operands [0], operands[1]))
873 rtx temp = XEXP (operands[1], 0);
875 if (GET_CODE (temp) == REG
876 || (GET_CODE (temp) == PLUS
877 && GET_CODE (XEXP (temp, 0)) == REG
878 && GET_CODE (XEXP (temp, 1)) == CONST_INT))
881 else return "ashd %2,%0";
886 output_move_dconst (n, s)
893 strcpy (r, "movqd ");
894 else if (n > 0 && n < 256)
895 strcpy (r, "movzbd ");
896 else if (n > 0 && n < 65536)
897 strcpy (r, "movzwd ");
898 else if (n < 0 && n > -129)
899 strcpy (r, "movxbd ");
900 else if (n < 0 && n > -32769)
901 strcpy (r, "movxwd ");