1 ;; GCC machine description for Matsushita MN10300
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
3 ;; Contributed by Jeff Law (law@cygnus.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
27 ;; Condition code settings.
28 ;; none - insn does not affect cc
29 ;; none_0hit - insn does not affect cc but it does modify operand 0
30 ;; This attribute is used to keep track of when operand 0 changes.
31 ;; See the description of NOTICE_UPDATE_CC for more info.
32 ;; set_znv - insn sets z,n,v to usable values; c is unusable.
33 ;; set_zn - insn sets z,n to usable values; v,c are unusable.
34 ;; compare - compare instruction
35 ;; invert -- like compare, but flags are inverted.
36 ;; clobber - value of cc is unknown
37 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber,invert"
38 (const_string "clobber"))
40 ;; ----------------------------------------------------------------------
42 ;; ----------------------------------------------------------------------
46 (define_expand "movqi"
47 [(set (match_operand:QI 0 "general_operand" "")
48 (match_operand:QI 1 "general_operand" ""))]
52 /* One of the ops has to be in a register */
53 if (!register_operand (operand0, QImode)
54 && !register_operand (operand1, QImode))
55 operands[1] = copy_to_mode_reg (QImode, operand1);
59 [(set (match_operand:QI 0 "nonimmediate_operand" "=d*x*a,d*x,d*x*a,d*x*a,m")
60 (match_operand:QI 1 "general_operand" "0,I,d*xai,m,d*xa"))]
62 && (register_operand (operands[0], QImode)
63 || register_operand (operands[1], QImode))"
66 switch (which_alternative)
73 if (GET_CODE (operands[1]) == CONST_DOUBLE)
76 xoperands[0] = operands[0];
77 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
78 output_asm_insn (\"mov %1,%0\", xoperands);
82 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
83 && GET_CODE (operands[1]) == CONST_INT)
85 HOST_WIDE_INT val = INTVAL (operands[1]);
87 if (((val & 0x80) && ! (val & 0xffffff00))
88 || ((val & 0x800000) && ! (val & 0xff000000)))
89 return \"movu %1,%0\";
94 return \"movbu %1,%0\";
99 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
102 [(set (match_operand:QI 0 "nonimmediate_operand" "=d*a,d,d*a,d,m")
103 (match_operand:QI 1 "general_operand" "0,I,dai,m,d"))]
104 "register_operand (operands[0], QImode)
105 || register_operand (operands[1], QImode)"
108 switch (which_alternative)
115 if (GET_CODE (operands[1]) == CONST_DOUBLE)
118 xoperands[0] = operands[0];
119 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
120 output_asm_insn (\"mov %1,%0\", xoperands);
124 return \"mov %1,%0\";
127 return \"movbu %1,%0\";
132 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
136 (define_expand "movhi"
137 [(set (match_operand:HI 0 "general_operand" "")
138 (match_operand:HI 1 "general_operand" ""))]
142 /* One of the ops has to be in a register */
143 if (!register_operand (operand1, HImode)
144 && !register_operand (operand0, HImode))
145 operands[1] = copy_to_mode_reg (HImode, operand1);
149 [(set (match_operand:HI 0 "nonimmediate_operand" "=d*x*a,d*x,d*x*a,d*x*a,m")
150 (match_operand:HI 1 "general_operand" "0,I,d*x*ai,m,d*x*a"))]
152 && (register_operand (operands[0], HImode)
153 || register_operand (operands[1], HImode))"
156 switch (which_alternative)
163 if (GET_CODE (operands[1]) == CONST_DOUBLE)
166 xoperands[0] = operands[0];
167 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
168 output_asm_insn (\"mov %1,%0\", xoperands);
172 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
173 && GET_CODE (operands[1]) == CONST_INT)
175 HOST_WIDE_INT val = INTVAL (operands[1]);
177 if (((val & 0x80) && ! (val & 0xffffff00))
178 || ((val & 0x800000) && ! (val & 0xff000000)))
179 return \"movu %1,%0\";
181 return \"mov %1,%0\";
184 return \"movhu %1,%0\";
189 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
192 [(set (match_operand:HI 0 "nonimmediate_operand" "=d*a,d,d*a,d,m")
193 (match_operand:HI 1 "general_operand" "0,I,dai,m,d"))]
194 "register_operand (operands[0], HImode)
195 || register_operand (operands[1], HImode)"
198 switch (which_alternative)
205 if (GET_CODE (operands[1]) == CONST_DOUBLE)
208 xoperands[0] = operands[0];
209 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
210 output_asm_insn (\"mov %1,%0\", xoperands);
213 return \"mov %1,%0\";
216 return \"movhu %1,%0\";
221 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
225 ;; We use this to handle addition of two values when one operand is the
226 ;; stack pointer and the other is a memory reference of some kind. Reload
227 ;; does not handle them correctly without this expander.
228 (define_expand "reload_insi"
229 [(set (match_operand:SI 0 "register_operand" "=a")
230 (match_operand:SI 1 "impossible_plus_operand" ""))
231 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
235 if (XEXP (operands[1], 0) == stack_pointer_rtx)
237 if (GET_CODE (XEXP (operands[1], 1)) == SUBREG
238 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 1)))
239 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 1))))))
240 emit_move_insn (operands[2],
242 (GET_MODE (XEXP (operands[1], 1)),
243 SUBREG_REG (XEXP (operands[1], 1))));
245 emit_move_insn (operands[2], XEXP (operands[1], 1));
246 emit_move_insn (operands[0], XEXP (operands[1], 0));
250 if (GET_CODE (XEXP (operands[1], 0)) == SUBREG
251 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 0)))
252 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 0))))))
253 emit_move_insn (operands[2],
255 (GET_MODE (XEXP (operands[1], 0)),
256 SUBREG_REG (XEXP (operands[1], 0))));
258 emit_move_insn (operands[2], XEXP (operands[1], 0));
259 emit_move_insn (operands[0], XEXP (operands[1], 1));
261 emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
265 (define_expand "movsi"
266 [(set (match_operand:SI 0 "general_operand" "")
267 (match_operand:SI 1 "general_operand" ""))]
271 /* One of the ops has to be in a register */
272 if (!register_operand (operand1, SImode)
273 && !register_operand (operand0, SImode))
274 operands[1] = copy_to_mode_reg (SImode, operand1);
278 [(set (match_operand:SI 0 "nonimmediate_operand"
279 "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,!*y")
280 (match_operand:SI 1 "general_operand"
281 "0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,!*y,axR"))]
282 "register_operand (operands[0], SImode)
283 || register_operand (operands[1], SImode)"
286 switch (which_alternative)
304 if (GET_CODE (operands[1]) == CONST_DOUBLE)
307 xoperands[0] = operands[0];
308 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
309 output_asm_insn (\"mov %1,%0\", xoperands);
313 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
314 && GET_CODE (operands[1]) == CONST_INT)
316 HOST_WIDE_INT val = INTVAL (operands[1]);
318 if (((val & 0x80) && ! (val & 0xffffff00))
319 || ((val & 0x800000) && ! (val & 0xff000000)))
320 return \"movu %1,%0\";
322 return \"mov %1,%0\";
327 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
329 (define_expand "movsf"
330 [(set (match_operand:SF 0 "general_operand" "")
331 (match_operand:SF 1 "general_operand" ""))]
335 /* One of the ops has to be in a register */
336 if (!register_operand (operand1, SFmode)
337 && !register_operand (operand0, SFmode))
338 operands[1] = copy_to_mode_reg (SFmode, operand1);
342 [(set (match_operand:SF 0 "nonimmediate_operand" "=dx,ax,dx,a,daxm,dax")
343 (match_operand:SF 1 "general_operand" "0,0,G,G,dax,daxFm"))]
344 "register_operand (operands[0], SFmode)
345 || register_operand (operands[1], SFmode)"
348 switch (which_alternative)
358 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
359 && GET_CODE (operands[1]) == CONST_INT)
361 HOST_WIDE_INT val = INTVAL (operands[1]);
363 if (((val & 0x80) && ! (val & 0xffffff00))
364 || ((val & 0x800000) && ! (val & 0xff000000)))
365 return \"movu %1,%0\";
367 return \"mov %1,%0\";
372 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit")])
374 (define_expand "movdi"
375 [(set (match_operand:DI 0 "general_operand" "")
376 (match_operand:DI 1 "general_operand" ""))]
380 /* One of the ops has to be in a register */
381 if (!register_operand (operand1, DImode)
382 && !register_operand (operand0, DImode))
383 operands[1] = copy_to_mode_reg (DImode, operand1);
387 [(set (match_operand:DI 0 "nonimmediate_operand"
388 "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
389 (match_operand:DI 1 "general_operand"
390 "0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
391 "register_operand (operands[0], DImode)
392 || register_operand (operands[1], DImode)"
398 switch (which_alternative)
405 return \"clr %L0\;clr %H0\";
408 if (rtx_equal_p (operands[0], operands[1]))
409 return \"sub %L1,%L0\;mov %L0,%H0\";
411 return \"mov %1,%L0\;mov %L0,%H0\";
420 if (GET_CODE (operands[1]) == CONST_INT)
423 split_double (operands[1], &low, &high);
424 val[0] = INTVAL (low);
425 val[1] = INTVAL (high);
427 if (GET_CODE (operands[1]) == CONST_DOUBLE)
429 if (GET_MODE (operands[1]) == DFmode)
431 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
432 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
434 else if (GET_MODE (operands[1]) == VOIDmode
435 || GET_MODE (operands[1]) == DImode)
437 val[0] = CONST_DOUBLE_LOW (operands[1]);
438 val[1] = CONST_DOUBLE_HIGH (operands[1]);
442 if (GET_CODE (operands[1]) == MEM
443 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
445 rtx temp = operands[0];
447 while (GET_CODE (temp) == SUBREG)
448 temp = SUBREG_REG (temp);
450 if (GET_CODE (temp) != REG)
453 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
454 XEXP (operands[1], 0)))
455 return \"mov %H1,%H0\;mov %L1,%L0\";
457 return \"mov %L1,%L0\;mov %H1,%H0\";
460 else if (GET_CODE (operands[1]) == MEM
461 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
462 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
466 xoperands[0] = operands[0];
467 xoperands[1] = XEXP (operands[1], 0);
469 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
475 if ((GET_CODE (operands[1]) == CONST_INT
476 || GET_CODE (operands[1]) == CONST_DOUBLE)
479 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
480 output_asm_insn (\"clr %L0\", operands);
482 output_asm_insn (\"mov %L1,%L0\", operands);
484 else if ((GET_CODE (operands[1]) == CONST_INT
485 || GET_CODE (operands[1]) == CONST_DOUBLE)
486 && (REGNO_REG_CLASS (true_regnum (operands[0]))
488 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
489 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
490 output_asm_insn (\"movu %1,%0\", operands);
492 output_asm_insn (\"mov %L1,%L0\", operands);
494 if ((GET_CODE (operands[1]) == CONST_INT
495 || GET_CODE (operands[1]) == CONST_DOUBLE)
498 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
499 output_asm_insn (\"clr %H0\", operands);
501 output_asm_insn (\"mov %H1,%H0\", operands);
503 else if ((GET_CODE (operands[1]) == CONST_INT
504 || GET_CODE (operands[1]) == CONST_DOUBLE)
506 output_asm_insn (\"mov %L0,%H0\", operands);
507 else if ((GET_CODE (operands[1]) == CONST_INT
508 || GET_CODE (operands[1]) == CONST_DOUBLE)
509 && (REGNO_REG_CLASS (true_regnum (operands[0]))
511 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
512 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
513 output_asm_insn (\"movu %1,%0\", operands);
515 output_asm_insn (\"mov %H1,%H0\", operands);
522 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
524 (define_expand "movdf"
525 [(set (match_operand:DF 0 "general_operand" "")
526 (match_operand:DF 1 "general_operand" ""))]
530 /* One of the ops has to be in a register */
531 if (!register_operand (operand1, DFmode)
532 && !register_operand (operand0, DFmode))
533 operands[1] = copy_to_mode_reg (DFmode, operand1);
537 [(set (match_operand:DF 0 "nonimmediate_operand"
538 "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
539 (match_operand:DF 1 "general_operand"
540 "0,0,G,G,dx,ax,dx,ax,dxFm,axFm,dxFm,axFm"))]
541 "register_operand (operands[0], DFmode)
542 || register_operand (operands[1], DFmode)"
548 switch (which_alternative)
555 return \"clr %L0\;clr %H0\";
558 if (rtx_equal_p (operands[0], operands[1]))
559 return \"sub %L1,%L0\;mov %L0,%H0\";
561 return \"mov %1,%L0\;mov %L0,%H0\";
570 if (GET_CODE (operands[1]) == CONST_INT)
573 split_double (operands[1], &low, &high);
574 val[0] = INTVAL (low);
575 val[1] = INTVAL (high);
577 if (GET_CODE (operands[1]) == CONST_DOUBLE)
579 if (GET_MODE (operands[1]) == DFmode)
581 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
582 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
584 else if (GET_MODE (operands[1]) == VOIDmode
585 || GET_MODE (operands[1]) == DImode)
587 val[0] = CONST_DOUBLE_LOW (operands[1]);
588 val[1] = CONST_DOUBLE_HIGH (operands[1]);
592 if (GET_CODE (operands[1]) == MEM
593 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
595 rtx temp = operands[0];
597 while (GET_CODE (temp) == SUBREG)
598 temp = SUBREG_REG (temp);
600 if (GET_CODE (temp) != REG)
603 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
604 XEXP (operands[1], 0)))
605 return \"mov %H1,%H0\;mov %L1,%L0\";
607 return \"mov %L1,%L0\;mov %H1,%H0\";
610 else if (GET_CODE (operands[1]) == MEM
611 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
612 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
616 xoperands[0] = operands[0];
617 xoperands[1] = XEXP (operands[1], 0);
619 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
625 if ((GET_CODE (operands[1]) == CONST_INT
626 || GET_CODE (operands[1]) == CONST_DOUBLE)
629 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
630 output_asm_insn (\"clr %L0\", operands);
632 output_asm_insn (\"mov %L1,%L0\", operands);
634 else if ((GET_CODE (operands[1]) == CONST_INT
635 || GET_CODE (operands[1]) == CONST_DOUBLE)
636 && (REGNO_REG_CLASS (true_regnum (operands[0]))
638 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
639 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
640 output_asm_insn (\"movu %1,%0\", operands);
642 output_asm_insn (\"mov %L1,%L0\", operands);
644 if ((GET_CODE (operands[1]) == CONST_INT
645 || GET_CODE (operands[1]) == CONST_DOUBLE)
648 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
649 output_asm_insn (\"clr %H0\", operands);
651 output_asm_insn (\"mov %H1,%H0\", operands);
653 else if ((GET_CODE (operands[1]) == CONST_INT
654 || GET_CODE (operands[1]) == CONST_DOUBLE)
656 output_asm_insn (\"mov %L0,%H0\", operands);
657 else if ((GET_CODE (operands[1]) == CONST_INT
658 || GET_CODE (operands[1]) == CONST_DOUBLE)
659 && (REGNO_REG_CLASS (true_regnum (operands[0]))
661 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
662 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
663 output_asm_insn (\"movu %1,%0\", operands);
665 output_asm_insn (\"mov %H1,%H0\", operands);
672 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
676 ;; ----------------------------------------------------------------------
678 ;; ----------------------------------------------------------------------
680 ;; Go ahead and define tstsi so we can eliminate redundant tst insns
681 ;; when we start trying to optimize this port.
683 [(set (cc0) (match_operand:SI 0 "register_operand" "dax"))]
685 "* return output_tst (operands[0], insn);"
686 [(set_attr "cc" "set_znv")])
689 [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx,!a")))]
691 "* return output_tst (operands[0], insn);"
692 [(set_attr "cc" "set_znv")])
695 [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
697 "* return output_tst (operands[0], insn);"
698 [(set_attr "cc" "set_znv")])
701 [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx,!a")))]
703 "* return output_tst (operands[0], insn);"
704 [(set_attr "cc" "set_znv")])
707 [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
709 "* return output_tst (operands[0], insn);"
710 [(set_attr "cc" "set_znv")])
714 (compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax")
715 (match_operand:SI 1 "nonmemory_operand" "!*0,daxi")))]
720 [(set_attr "cc" "invert,compare")])
722 ;; ----------------------------------------------------------------------
724 ;; ----------------------------------------------------------------------
726 (define_expand "addsi3"
727 [(set (match_operand:SI 0 "register_operand" "")
728 (plus:SI (match_operand:SI 1 "register_operand" "")
729 (match_operand:SI 2 "nonmemory_operand" "")))]
734 [(set (match_operand:SI 0 "register_operand" "=dx,a,x,a,dax,!*y,!dax")
735 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,dax")
736 (match_operand:SI 2 "nonmemory_operand" "J,J,L,L,daxi,i,dax")))]
740 switch (which_alternative)
750 return \"add %2,%0\";
753 enum reg_class src1_class, src2_class, dst_class;
755 src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
756 src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
757 dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
759 /* I'm not sure if this can happen or not. Might as well be prepared
760 and generate the best possible code if it does happen. */
761 if (true_regnum (operands[0]) == true_regnum (operands[1]))
762 return \"add %2,%0\";
763 if (true_regnum (operands[0]) == true_regnum (operands[2]))
764 return \"add %1,%0\";
766 /* Catch cases where no extended register was used. These should be
767 handled just like the mn10300. */
768 if (src1_class != EXTENDED_REGS
769 && src2_class != EXTENDED_REGS
770 && dst_class != EXTENDED_REGS)
772 /* We have to copy one of the sources into the destination, then
773 add the other source to the destination.
775 Carefully select which source to copy to the destination; a naive
776 implementation will waste a byte when the source classes are
777 different and the destination is an address register. Selecting
778 the lowest cost register copy will optimize this sequence. */
779 if (REGNO_REG_CLASS (true_regnum (operands[1]))
780 == REGNO_REG_CLASS (true_regnum (operands[0])))
781 return \"mov %1,%0\;add %2,%0\";
782 return \"mov %2,%0\;add %1,%0\";
785 /* At least one register is an extended register. */
787 /* The three operand add instruction on the am33 is a win iff the
788 output register is an extended register, or if both source
789 registers are extended registers. */
790 if (dst_class == EXTENDED_REGS
791 || src1_class == src2_class)
792 return \"add %2,%1,%0\";
794 /* It is better to copy one of the sources to the destination, then
795 perform a 2 address add. The destination in this case must be
796 an address or data register and one of the sources must be an
797 extended register and the remaining source must not be an extended
800 The best code for this case is to copy the extended reg to the
801 destination, then emit a two address add. */
802 if (src1_class == EXTENDED_REGS)
803 return \"mov %1,%0\;add %2,%0\";
804 return \"mov %2,%0\;add %1,%0\";
810 [(set_attr "cc" "set_zn,none_0hit,set_zn,none_0hit,set_zn,none_0hit,set_zn")])
813 [(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,!*y,!dax")
814 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
815 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
819 switch (which_alternative)
828 return \"add %2,%0\";
830 /* I'm not sure if this can happen or not. Might as well be prepared
831 and generate the best possible code if it does happen. */
832 if (true_regnum (operands[0]) == true_regnum (operands[1]))
833 return \"add %2,%0\";
834 if (true_regnum (operands[0]) == true_regnum (operands[2]))
835 return \"add %1,%0\";
837 /* We have to copy one of the sources into the destination, then add
838 the other source to the destination.
840 Carefully select which source to copy to the destination; a naive
841 implementation will waste a byte when the source classes are different
842 and the destination is an address register. Selecting the lowest
843 cost register copy will optimize this sequence. */
844 if (REGNO_REG_CLASS (true_regnum (operands[1]))
845 == REGNO_REG_CLASS (true_regnum (operands[0])))
846 return \"mov %1,%0\;add %2,%0\";
847 return \"mov %2,%0\;add %1,%0\";
852 [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
854 ;; ----------------------------------------------------------------------
855 ;; SUBTRACT INSTRUCTIONS
856 ;; ----------------------------------------------------------------------
858 (define_expand "subsi3"
859 [(set (match_operand:SI 0 "register_operand" "")
860 (minus:SI (match_operand:SI 1 "register_operand" "")
861 (match_operand:SI 2 "nonmemory_operand" "")))]
866 [(set (match_operand:SI 0 "register_operand" "=dax,!dax")
867 (minus:SI (match_operand:SI 1 "register_operand" "0,dax")
868 (match_operand:SI 2 "nonmemory_operand" "daxi,dax")))]
872 if (true_regnum (operands[0]) == true_regnum (operands[1]))
873 return \"sub %2,%0\";
876 enum reg_class src1_class, src2_class, dst_class;
878 src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
879 src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
880 dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
882 /* If no extended registers are used, then the best way to handle
883 this is to copy the first source operand into the destination
884 and emit a two address subtraction. */
885 if (src1_class != EXTENDED_REGS
886 && src2_class != EXTENDED_REGS
887 && dst_class != EXTENDED_REGS
888 && true_regnum (operands[0]) != true_regnum (operands[2]))
889 return \"mov %1,%0\;sub %2,%0\";
890 return \"sub %2,%1,%0\";
893 [(set_attr "cc" "set_zn")])
896 [(set (match_operand:SI 0 "register_operand" "=dax")
897 (minus:SI (match_operand:SI 1 "register_operand" "0")
898 (match_operand:SI 2 "nonmemory_operand" "daxi")))]
901 [(set_attr "cc" "set_zn")])
903 (define_expand "negsi2"
904 [(set (match_operand:SI 0 "register_operand" "")
905 (neg:SI (match_operand:SI 1 "register_operand" "")))]
909 rtx target = gen_reg_rtx (SImode);
911 emit_move_insn (target, GEN_INT (0));
912 emit_insn (gen_subsi3 (target, target, operands[1]));
913 emit_move_insn (operands[0], target);
917 ;; ----------------------------------------------------------------------
918 ;; MULTIPLY INSTRUCTIONS
919 ;; ----------------------------------------------------------------------
921 (define_insn "mulsidi3"
922 [(set (match_operand:DI 0 "register_operand" "=dax")
923 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "dax"))
924 (sign_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
927 [(set_attr "cc" "set_zn")])
929 (define_insn "umulsidi3"
930 [(set (match_operand:DI 0 "register_operand" "=dax")
931 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax"))
932 (zero_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
935 [(set_attr "cc" "set_zn")])
937 (define_expand "mulsi3"
938 [(set (match_operand:SI 0 "register_operand" "")
939 (mult:SI (match_operand:SI 1 "register_operand" "")
940 (match_operand:SI 2 "register_operand" "")))]
945 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
946 (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
947 (match_operand:SI 2 "nonmemory_operand" "dx,daxi")))]
952 return \"nop\;nop\;mul %2,%0\";
954 return \"mul %2,%0\";
956 [(set_attr "cc" "set_zn")])
959 [(set (match_operand:SI 0 "register_operand" "=dx")
960 (mult:SI (match_operand:SI 1 "register_operand" "%0")
961 (match_operand:SI 2 "register_operand" "dx")))]
966 return \"nop\;nop\;mul %2,%0\";
968 return \"mul %2,%0\";
970 [(set_attr "cc" "set_zn")])
972 (define_insn "udivmodsi4"
973 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx")
974 (udiv:SI (match_operand:SI 1 "general_operand" "0")
975 (match_operand:SI 2 "general_operand" "dx")))
976 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
977 (umod:SI (match_dup 1) (match_dup 2)))]
981 output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
983 if (find_reg_note (insn, REG_UNUSED, operands[3]))
984 return \"divu %2,%0\";
986 return \"divu %2,%0\;mov mdr,%3\";
988 [(set_attr "cc" "set_zn")])
990 (define_insn "divmodsi4"
991 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx")
992 (div:SI (match_operand:SI 1 "general_operand" "0")
993 (match_operand:SI 2 "general_operand" "dx")))
994 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
995 (mod:SI (match_dup 1) (match_dup 2)))]
999 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1000 return \"ext %0\;div %2,%0\";
1002 return \"ext %0\;div %2,%0\;mov mdr,%3\";
1004 [(set_attr "cc" "set_zn")])
1007 ;; ----------------------------------------------------------------------
1009 ;; ----------------------------------------------------------------------
1011 (define_expand "andsi3"
1012 [(set (match_operand:SI 0 "register_operand" "")
1013 (and:SI (match_operand:SI 1 "register_operand" "")
1014 (match_operand:SI 2 "nonmemory_operand" "")))]
1019 [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
1020 (and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
1021 (match_operand:SI 2 "nonmemory_operand" "N,dxi,dax")))]
1025 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
1026 return \"extbu %0\";
1027 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
1028 return \"exthu %0\";
1029 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
1030 return \"add %0,%0\;lsr 1,%0\";
1031 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
1032 return \"asl2 %0\;lsr 2,%0\";
1033 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
1034 return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
1035 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
1036 return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
1037 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
1038 return \"lsr 1,%0\;add %0,%0\";
1039 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
1040 return \"lsr 2,%0\;asl2 %0\";
1041 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
1042 return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
1043 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
1044 return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
1045 if (REG_P (operands[2]) && REG_P (operands[1])
1046 && true_regnum (operands[0]) != true_regnum (operands[1])
1047 && true_regnum (operands[0]) != true_regnum (operands[2])
1048 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1049 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1050 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1051 return \"mov %1,%0\;and %2,%0\";
1052 if (REG_P (operands[2]) && REG_P (operands[1])
1053 && true_regnum (operands[0]) != true_regnum (operands[1])
1054 && true_regnum (operands[0]) != true_regnum (operands[2]))
1055 return \"and %1,%2,%0\";
1056 if (REG_P (operands[2]) && REG_P (operands[0])
1057 && true_regnum (operands[2]) == true_regnum (operands[0]))
1058 return \"and %1,%0\";
1059 return \"and %2,%0\";
1061 [(set_attr "cc" "none_0hit,set_znv,set_znv")])
1064 [(set (match_operand:SI 0 "register_operand" "=dx,dx")
1065 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1066 (match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
1070 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
1071 return \"extbu %0\";
1072 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
1073 return \"exthu %0\";
1074 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
1075 return \"add %0,%0\;lsr 1,%0\";
1076 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
1077 return \"asl2 %0\;lsr 2,%0\";
1078 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
1079 return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
1080 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
1081 return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
1082 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
1083 return \"lsr 1,%0\;add %0,%0\";
1084 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
1085 return \"lsr 2,%0\;asl2 %0\";
1086 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
1087 return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
1088 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
1089 return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
1090 return \"and %2,%0\";
1092 [(set_attr "cc" "none_0hit,set_znv")])
1094 ;; ----------------------------------------------------------------------
1096 ;; ----------------------------------------------------------------------
1098 (define_expand "iorsi3"
1099 [(set (match_operand:SI 0 "register_operand" "")
1100 (ior:SI (match_operand:SI 1 "register_operand" "")
1101 (match_operand:SI 2 "nonmemory_operand" "")))]
1106 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1107 (ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
1108 (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
1112 if (REG_P (operands[2]) && REG_P (operands[1])
1113 && true_regnum (operands[0]) != true_regnum (operands[1])
1114 && true_regnum (operands[0]) != true_regnum (operands[2])
1115 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1116 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1117 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1118 return \"mov %1,%0\;or %2,%0\";
1119 if (REG_P (operands[2]) && REG_P (operands[1])
1120 && true_regnum (operands[0]) != true_regnum (operands[1])
1121 && true_regnum (operands[0]) != true_regnum (operands[2]))
1122 return \"or %1,%2,%0\";
1123 if (REG_P (operands[2]) && REG_P (operands[0])
1124 && true_regnum (operands[2]) == true_regnum (operands[0]))
1125 return \"or %1,%0\";
1126 return \"or %2,%0\";
1128 [(set_attr "cc" "set_znv")])
1131 [(set (match_operand:SI 0 "register_operand" "=dx")
1132 (ior:SI (match_operand:SI 1 "register_operand" "%0")
1133 (match_operand:SI 2 "nonmemory_operand" "dxi")))]
1136 [(set_attr "cc" "set_znv")])
1138 ;; ----------------------------------------------------------------------
1140 ;; ----------------------------------------------------------------------
1142 (define_expand "xorsi3"
1143 [(set (match_operand:SI 0 "register_operand" "")
1144 (xor:SI (match_operand:SI 1 "register_operand" "")
1145 (match_operand:SI 2 "nonmemory_operand" "")))]
1150 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1151 (xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
1152 (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
1156 if (REG_P (operands[2]) && REG_P (operands[1])
1157 && true_regnum (operands[0]) != true_regnum (operands[1])
1158 && true_regnum (operands[0]) != true_regnum (operands[2])
1159 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1160 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1161 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1162 return \"mov %1,%0\;xor %2,%0\";
1163 if (REG_P (operands[2]) && REG_P (operands[1])
1164 && true_regnum (operands[0]) != true_regnum (operands[1])
1165 && true_regnum (operands[0]) != true_regnum (operands[2]))
1166 return \"xor %1,%2,%0\";
1167 if (REG_P (operands[2]) && REG_P (operands[0])
1168 && true_regnum (operands[2]) == true_regnum (operands[0]))
1169 return \"xor %1,%0\";
1170 return \"xor %2,%0\";
1172 [(set_attr "cc" "set_znv")])
1175 [(set (match_operand:SI 0 "register_operand" "=dx")
1176 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1177 (match_operand:SI 2 "nonmemory_operand" "dxi")))]
1180 [(set_attr "cc" "set_znv")])
1182 ;; ----------------------------------------------------------------------
1184 ;; ----------------------------------------------------------------------
1186 (define_expand "one_cmplsi2"
1187 [(set (match_operand:SI 0 "register_operand" "")
1188 (not:SI (match_operand:SI 1 "register_operand" "")))]
1193 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1194 (not:SI (match_operand:SI 1 "register_operand" "0,0")))]
1197 [(set_attr "cc" "set_znv")])
1200 [(set (match_operand:SI 0 "register_operand" "=dx")
1201 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1204 [(set_attr "cc" "set_znv")])
1206 ;; -----------------------------------------------------------------
1208 ;; -----------------------------------------------------------------
1211 ;; These set/clear memory in byte sized chunks.
1213 ;; They are no smaller/faster than loading the value into a register
1214 ;; and storing the register, but they don't need a scratch register
1215 ;; which may allow for better code generation.
1217 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int 0))]
1222 [(set_attr "cc" "clobber")])
1225 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int -1))]
1230 [(set_attr "cc" "clobber,none_0hit")])
1233 [(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1235 (and:SI (subreg:SI (match_dup 0) 0)
1236 (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
1241 [(set_attr "cc" "clobber,set_znv")])
1244 [(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1246 (ior:SI (subreg:SI (match_dup 0) 0)
1247 (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
1252 [(set_attr "cc" "clobber,set_znv")])
1256 (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
1257 (match_operand 1 "const_int_operand" "")
1258 (match_operand 2 "const_int_operand" "")))]
1262 int len = INTVAL (operands[1]);
1263 int bit = INTVAL (operands[2]);
1274 xoperands[0] = operands[0];
1275 xoperands[1] = GEN_INT (mask);
1276 output_asm_insn (\"btst %1,%0\", xoperands);
1279 [(set_attr "cc" "clobber")])
1283 (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
1284 (match_operand 1 "const_int_operand" "")
1285 (match_operand 2 "const_int_operand" "")))]
1286 "mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
1289 int len = INTVAL (operands[1]);
1290 int bit = INTVAL (operands[2]);
1301 /* If the source operand is not a reg (ie it is memory), then extract the
1302 bits from mask that we actually want to test. Note that the mask will
1303 never cross a byte boundary. */
1304 if (!REG_P (operands[0]))
1308 else if (mask & 0xff00)
1309 mask = (mask >> 8) & 0xff;
1310 else if (mask & 0xff0000)
1311 mask = (mask >> 16) & 0xff;
1312 else if (mask & 0xff000000)
1313 mask = (mask >> 24) & 0xff;
1316 xoperands[0] = operands[0];
1317 xoperands[1] = GEN_INT (mask);
1318 if (GET_CODE (operands[0]) == REG)
1319 output_asm_insn (\"btst %1,%0\", xoperands);
1321 output_asm_insn (\"btst %1,%A0\", xoperands);
1324 [(set_attr "cc" "clobber")])
1327 [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx")
1328 (match_operand:SI 1 "const_int_operand" "")))]
1331 [(set_attr "cc" "clobber")])
1336 (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
1337 (match_operand:SI 1 "const_8bit_operand" "")))]
1342 [(set_attr "cc" "clobber")])
1345 ;; ----------------------------------------------------------------------
1346 ;; JUMP INSTRUCTIONS
1347 ;; ----------------------------------------------------------------------
1349 ;; Conditional jump instructions
1351 (define_expand "ble"
1353 (if_then_else (le (cc0)
1355 (label_ref (match_operand 0 "" ""))
1360 (define_expand "bleu"
1362 (if_then_else (leu (cc0)
1364 (label_ref (match_operand 0 "" ""))
1369 (define_expand "bge"
1371 (if_then_else (ge (cc0)
1373 (label_ref (match_operand 0 "" ""))
1378 (define_expand "bgeu"
1380 (if_then_else (geu (cc0)
1382 (label_ref (match_operand 0 "" ""))
1387 (define_expand "blt"
1389 (if_then_else (lt (cc0)
1391 (label_ref (match_operand 0 "" ""))
1396 (define_expand "bltu"
1398 (if_then_else (ltu (cc0)
1400 (label_ref (match_operand 0 "" ""))
1405 (define_expand "bgt"
1407 (if_then_else (gt (cc0)
1409 (label_ref (match_operand 0 "" ""))
1414 (define_expand "bgtu"
1416 (if_then_else (gtu (cc0)
1418 (label_ref (match_operand 0 "" ""))
1423 (define_expand "beq"
1425 (if_then_else (eq (cc0)
1427 (label_ref (match_operand 0 "" ""))
1432 (define_expand "bne"
1434 (if_then_else (ne (cc0)
1436 (label_ref (match_operand 0 "" ""))
1443 (if_then_else (match_operator 1 "comparison_operator"
1444 [(cc0) (const_int 0)])
1445 (label_ref (match_operand 0 "" ""))
1450 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1451 && (GET_CODE (operands[1]) == GT
1452 || GET_CODE (operands[1]) == GE
1453 || GET_CODE (operands[1]) == LE
1454 || GET_CODE (operands[1]) == LT))
1458 [(set_attr "cc" "none")])
1462 (if_then_else (match_operator 1 "comparison_operator"
1463 [(cc0) (const_int 0)])
1465 (label_ref (match_operand 0 "" ""))))]
1469 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1470 && (GET_CODE (operands[1]) == GT
1471 || GET_CODE (operands[1]) == GE
1472 || GET_CODE (operands[1]) == LE
1473 || GET_CODE (operands[1]) == LT))
1477 [(set_attr "cc" "none")])
1479 ;; Unconditional and other jump instructions.
1483 (label_ref (match_operand 0 "" "")))]
1486 [(set_attr "cc" "none")])
1488 (define_insn "indirect_jump"
1489 [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1492 [(set_attr "cc" "none")])
1494 (define_insn "tablejump"
1495 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1496 (use (label_ref (match_operand 1 "" "")))]
1499 [(set_attr "cc" "none")])
1501 ;; Call subroutine with no return value.
1503 (define_expand "call"
1504 [(call (match_operand:QI 0 "general_operand" "")
1505 (match_operand:SI 1 "general_operand" ""))]
1509 if (! call_address_operand (XEXP (operands[0], 0), VOIDmode))
1510 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1511 emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
1515 (define_insn "call_internal"
1516 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "aS"))
1517 (match_operand:SI 1 "general_operand" "g"))]
1521 if (REG_P (operands[0]))
1522 return \"calls %C0\";
1524 return \"call %C0,[],0\";
1526 [(set_attr "cc" "clobber")])
1528 ;; Call subroutine, returning value in operand 0
1529 ;; (which must be a hard register).
1531 (define_expand "call_value"
1532 [(set (match_operand 0 "" "")
1533 (call (match_operand:QI 1 "general_operand" "")
1534 (match_operand:SI 2 "general_operand" "")))]
1538 if (! call_address_operand (XEXP (operands[1], 0), VOIDmode))
1539 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1540 emit_call_insn (gen_call_value_internal (operands[0],
1541 XEXP (operands[1], 0),
1546 (define_insn "call_value_internal"
1547 [(set (match_operand 0 "" "=dax")
1548 (call (mem:QI (match_operand:SI 1 "call_address_operand" "aS"))
1549 (match_operand:SI 2 "general_operand" "g")))]
1553 if (REG_P (operands[1]))
1554 return \"calls %C1\";
1556 return \"call %C1,[],0\";
1558 [(set_attr "cc" "clobber")])
1560 (define_expand "untyped_call"
1561 [(parallel [(call (match_operand 0 "" "")
1563 (match_operand 1 "" "")
1564 (match_operand 2 "" "")])]
1570 emit_call_insn (gen_call (operands[0], const0_rtx));
1572 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1574 rtx set = XVECEXP (operands[2], 0, i);
1575 emit_move_insn (SET_DEST (set), SET_SRC (set));
1584 [(set_attr "cc" "none")])
1586 ;; ----------------------------------------------------------------------
1587 ;; EXTEND INSTRUCTIONS
1588 ;; ----------------------------------------------------------------------
1590 (define_expand "zero_extendqisi2"
1591 [(set (match_operand:SI 0 "general_operand" "")
1593 (match_operand:QI 1 "general_operand" "")))]
1598 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax")
1600 (match_operand:QI 1 "general_operand" "0,dax,m,0,dax,m")))]
1609 [(set_attr "cc" "none_0hit")])
1612 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx")
1614 (match_operand:QI 1 "general_operand" "0,d,m")))]
1620 [(set_attr "cc" "none_0hit")])
1622 (define_expand "zero_extendhisi2"
1623 [(set (match_operand:SI 0 "general_operand" "")
1625 (match_operand:HI 1 "general_operand" "")))]
1630 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax")
1632 (match_operand:HI 1 "general_operand" "0,dax,m,0,dax,m")))]
1641 [(set_attr "cc" "none_0hit")])
1644 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx")
1646 (match_operand:HI 1 "general_operand" "0,dx,m")))]
1652 [(set_attr "cc" "none_0hit")])
1654 ;;- sign extension instructions
1656 (define_expand "extendqisi2"
1657 [(set (match_operand:SI 0 "general_operand" "")
1659 (match_operand:QI 1 "general_operand" "")))]
1664 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax")
1666 (match_operand:QI 1 "general_operand" "0,dx,0,dax")))]
1673 [(set_attr "cc" "none_0hit")])
1676 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx")
1678 (match_operand:QI 1 "general_operand" "0,dx")))]
1683 [(set_attr "cc" "none_0hit")])
1685 (define_expand "extendhisi2"
1686 [(set (match_operand:SI 0 "general_operand" "")
1688 (match_operand:HI 1 "general_operand" "")))]
1693 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax")
1695 (match_operand:HI 1 "general_operand" "0,dax,0,dax")))]
1702 [(set_attr "cc" "none_0hit")])
1705 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx")
1707 (match_operand:HI 1 "general_operand" "0,dx")))]
1712 [(set_attr "cc" "none_0hit")])
1714 ;; ----------------------------------------------------------------------
1716 ;; ----------------------------------------------------------------------
1718 (define_expand "ashlsi3"
1719 [(set (match_operand:SI 0 "register_operand" "")
1721 (match_operand:SI 1 "register_operand" "")
1722 (match_operand:QI 2 "nonmemory_operand" "")))]
1727 [(set (match_operand:SI 0 "register_operand" "=dax,dx,!dax")
1729 (match_operand:SI 1 "register_operand" "0,0,dax")
1730 (match_operand:QI 2 "nonmemory_operand" "J,dxi,dax")))]
1734 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1)
1735 return \"add %0,%0\";
1737 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 2)
1740 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 3
1741 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
1742 return \"asl2 %0\;add %0,%0\";
1744 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 4
1745 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
1746 return \"asl2 %0\;asl2 %0\";
1748 if (true_regnum (operands[1]) == true_regnum (operands[0]))
1749 return \"asl %S2,%0\";
1751 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1752 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1753 && true_regnum (operands[0]) != true_regnum (operands[2]))
1754 return \"mov %1,%0\;asl %S2,%0\";
1755 return \"asl %2,%1,%0\";
1757 [(set_attr "cc" "set_zn")])
1760 [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
1762 (match_operand:SI 1 "register_operand" "0,0,0,0,0")
1763 (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))]
1771 [(set_attr "cc" "set_zn")])
1773 (define_expand "lshrsi3"
1774 [(set (match_operand:SI 0 "register_operand" "")
1776 (match_operand:SI 1 "register_operand" "")
1777 (match_operand:QI 2 "nonmemory_operand" "")))]
1782 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1784 (match_operand:SI 1 "register_operand" "0,dax")
1785 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
1789 if (true_regnum (operands[1]) == true_regnum (operands[0]))
1790 return \"lsr %S2,%0\";
1792 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1793 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1794 && true_regnum (operands[0]) != true_regnum (operands[2]))
1795 return \"mov %1,%0\;lsr %S2,%0\";
1796 return \"lsr %2,%1,%0\";
1798 [(set_attr "cc" "set_zn")])
1801 [(set (match_operand:SI 0 "register_operand" "=dx")
1803 (match_operand:SI 1 "register_operand" "0")
1804 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
1807 [(set_attr "cc" "set_zn")])
1809 (define_expand "ashrsi3"
1810 [(set (match_operand:SI 0 "register_operand" "")
1812 (match_operand:SI 1 "register_operand" "")
1813 (match_operand:QI 2 "nonmemory_operand" "")))]
1818 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1820 (match_operand:SI 1 "register_operand" "0,dax")
1821 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
1825 if (true_regnum (operands[1]) == true_regnum (operands[0]))
1826 return \"asr %S2,%0\";
1828 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1829 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1830 && true_regnum (operands[0]) != true_regnum (operands[2]))
1831 return \"mov %1,%0\;asr %S2,%0\";
1832 return \"asr %2,%1,%0\";
1834 [(set_attr "cc" "set_zn")])
1837 [(set (match_operand:SI 0 "register_operand" "=dx")
1839 (match_operand:SI 1 "register_operand" "0")
1840 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
1843 [(set_attr "cc" "set_zn")])
1845 ;; ----------------------------------------------------------------------
1847 ;; ----------------------------------------------------------------------
1849 ;; The mn103 series does not have floating point instructions, but since
1850 ;; FP values are held in integer regs, we can clear the high bit easily
1851 ;; which gives us an efficient inline floating point absolute value.
1853 ;; Similarly for negation of a FP value.
1856 (define_expand "absdf2"
1857 [(set (match_operand:DF 0 "register_operand" "")
1858 (abs:DF (match_operand:DF 1 "register_operand" "")))]
1862 rtx target, result, insns;
1865 target = operand_subword (operands[0], 1, 1, DFmode);
1866 result = expand_binop (SImode, and_optab,
1867 operand_subword_force (operands[1], 1, DFmode),
1868 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
1873 if (result != target)
1874 emit_move_insn (result, target);
1876 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
1877 operand_subword_force (operands[1], 0, DFmode));
1879 insns = get_insns ();
1882 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1886 (define_expand "abssf2"
1887 [(set (match_operand:SF 0 "register_operand" "")
1888 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1895 target = operand_subword_force (operands[0], 0, SFmode);
1896 result = expand_binop (SImode, and_optab,
1897 operand_subword_force (operands[1], 0, SFmode),
1898 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
1902 if (result != target)
1903 emit_move_insn (result, target);
1905 /* Make a place for REG_EQUAL. */
1906 emit_move_insn (operands[0], operands[0]);
1911 (define_expand "negdf2"
1912 [(set (match_operand:DF 0 "register_operand" "")
1913 (neg:DF (match_operand:DF 1 "register_operand" "")))]
1917 rtx target, result, insns;
1920 target = operand_subword (operands[0], 1, 1, DFmode);
1921 result = expand_binop (SImode, xor_optab,
1922 operand_subword_force (operands[1], 1, DFmode),
1923 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
1928 if (result != target)
1929 emit_move_insn (result, target);
1931 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
1932 operand_subword_force (operands[1], 0, DFmode));
1934 insns = get_insns ();
1937 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1941 (define_expand "negsf2"
1942 [(set (match_operand:SF 0 "register_operand" "")
1943 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1950 target = operand_subword_force (operands[0], 0, SFmode);
1951 result = expand_binop (SImode, xor_optab,
1952 operand_subword_force (operands[1], 0, SFmode),
1953 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
1957 if (result != target)
1958 emit_move_insn (result, target);
1960 /* Make a place for REG_EQUAL. */
1961 emit_move_insn (operands[0], operands[0]);
1966 ;; ----------------------------------------------------------------------
1967 ;; PROLOGUE/EPILOGUE
1968 ;; ----------------------------------------------------------------------
1969 (define_expand "prologue"
1972 "expand_prologue (); DONE;")
1974 (define_expand "epilogue"
1983 (define_insn "return_internal"
1988 [(set_attr "cc" "clobber")])
1990 ;; This insn restores the callee saved registers and does a return, it
1991 ;; can also deallocate stack space.
1992 (define_insn "return_internal_regs"
1994 (match_operand:SI 0 "const_int_operand" "i")
2002 fputs (\"\\tret [\", asm_out_file);
2003 if (regs_ever_live[2])
2005 fputs (\"d2\", asm_out_file);
2008 if (regs_ever_live[3])
2011 fputc (',', asm_out_file);
2012 fputs (\"d3\", asm_out_file);
2015 if (regs_ever_live[6])
2018 fputc (',', asm_out_file);
2019 fputs (\"a2\", asm_out_file);
2022 if (regs_ever_live[7])
2025 fputc (',', asm_out_file);
2026 fputs (\"a3\", asm_out_file);
2029 if (regs_ever_live[14] || regs_ever_live[15]
2030 || regs_ever_live[16] || regs_ever_live[17])
2033 fputc (',', asm_out_file);
2034 fputs (\"exreg1\", asm_out_file);
2037 fprintf (asm_out_file, \"],%d\\n\", INTVAL (operands[0]));
2040 [(set_attr "cc" "clobber")])
2042 (define_insn "store_movm"
2050 fputs (\"\\tmovm [\", asm_out_file);
2051 if (regs_ever_live[2])
2053 fputs (\"d2\", asm_out_file);
2056 if (regs_ever_live[3])
2059 fputc (',', asm_out_file);
2060 fputs (\"d3\", asm_out_file);
2063 if (regs_ever_live[6])
2066 fputc (',', asm_out_file);
2067 fputs (\"a2\", asm_out_file);
2070 if (regs_ever_live[7])
2073 fputc (',', asm_out_file);
2074 fputs (\"a3\", asm_out_file);
2077 if (regs_ever_live[14] || regs_ever_live[15]
2078 || regs_ever_live[16] || regs_ever_live[17])
2081 fputc (',', asm_out_file);
2082 fputs (\"exreg1\", asm_out_file);
2085 fputs (\"],(sp)\\n\", asm_out_file);
2088 [(set_attr "cc" "clobber")])
2090 (define_insn "return"
2092 "can_use_return_insn ()"
2095 rtx next = next_active_insn (insn);
2098 && GET_CODE (next) == JUMP_INSN
2099 && GET_CODE (PATTERN (next)) == RETURN)
2104 [(set_attr "cc" "clobber")])
2106 ;; Try to combine consecutive updates of the stack pointer (or any
2107 ;; other register for that matter).
2109 [(set (match_operand:SI 0 "register_operand" "=dxay")
2110 (plus:SI (match_dup 0)
2111 (match_operand 1 "const_int_operand" "")))
2113 (plus:SI (match_dup 0)
2114 (match_operand 2 "const_int_operand" "")))]
2118 operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
2119 return \"add %1,%0\";
2121 [(set_attr "cc" "clobber")])
2124 ;; We had patterns to check eq/ne, but the they don't work because
2125 ;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
2127 ;; The Z flag and C flag would be set, and we have no way to
2128 ;; check for the Z flag set and C flag clear.
2130 ;; This will work on the mn10200 because we can check the ZX flag
2131 ;; if the comparison is in HImode.
2133 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2134 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2135 (match_operand 1 "" "")
2137 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2139 [(set_attr "cc" "clobber")])
2142 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2143 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2144 (match_operand 1 "" "")
2146 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2148 [(set_attr "cc" "clobber")])
2151 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2152 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2154 (match_operand 1 "" "")))]
2155 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2157 [(set_attr "cc" "clobber")])
2160 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2161 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2163 (match_operand 1 "" "")))]
2164 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2166 [(set_attr "cc" "clobber")])