1 ;; GCC machine description for Matsushita MN10300
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Jeff Law (law@cygnus.com).
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;; The original PO technology requires these to be ordered by speed,
24 ;; so that assigner will pick the fastest.
26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Condition code settings.
29 ;; none - insn does not affect cc
30 ;; none_0hit - insn does not affect cc but it does modify operand 0
31 ;; This attribute is used to keep track of when operand 0 changes.
32 ;; See the description of NOTICE_UPDATE_CC for more info.
33 ;; set_znv - insn sets z,n,v to usable values; c is unusable.
34 ;; set_zn - insn sets z,n to usable values; v,c are unusable.
35 ;; compare - compare instruction
36 ;; invert -- like compare, but flags are inverted.
37 ;; clobber - value of cc is unknown
38 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber,invert"
39 (const_string "clobber"))
41 ;; ----------------------------------------------------------------------
43 ;; ----------------------------------------------------------------------
47 (define_expand "movqi"
48 [(set (match_operand:QI 0 "general_operand" "")
49 (match_operand:QI 1 "general_operand" ""))]
53 /* One of the ops has to be in a register */
54 if (!register_operand (operand0, QImode)
55 && !register_operand (operand1, QImode))
56 operands[1] = copy_to_mode_reg (QImode, operand1);
60 [(set (match_operand:QI 0 "nonimmediate_operand" "=d*x*a,d*x,d*x*a,d*x*a,m")
61 (match_operand:QI 1 "general_operand" "0,I,d*xai,m,d*xa"))]
63 && (register_operand (operands[0], QImode)
64 || register_operand (operands[1], QImode))"
67 switch (which_alternative)
74 if (GET_CODE (operands[1]) == CONST_DOUBLE)
77 xoperands[0] = operands[0];
78 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
79 output_asm_insn (\"mov %1,%0\", xoperands);
83 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
84 && GET_CODE (operands[1]) == CONST_INT)
86 HOST_WIDE_INT val = INTVAL (operands[1]);
88 if (((val & 0x80) && ! (val & 0xffffff00))
89 || ((val & 0x800000) && ! (val & 0xff000000)))
90 return \"movu %1,%0\";
95 return \"movbu %1,%0\";
100 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
103 [(set (match_operand:QI 0 "nonimmediate_operand" "=d*a,d,d*a,d,m")
104 (match_operand:QI 1 "general_operand" "0,I,dai,m,d"))]
105 "register_operand (operands[0], QImode)
106 || register_operand (operands[1], QImode)"
109 switch (which_alternative)
116 if (GET_CODE (operands[1]) == CONST_DOUBLE)
119 xoperands[0] = operands[0];
120 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
121 output_asm_insn (\"mov %1,%0\", xoperands);
125 return \"mov %1,%0\";
128 return \"movbu %1,%0\";
133 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
137 (define_expand "movhi"
138 [(set (match_operand:HI 0 "general_operand" "")
139 (match_operand:HI 1 "general_operand" ""))]
143 /* One of the ops has to be in a register */
144 if (!register_operand (operand1, HImode)
145 && !register_operand (operand0, HImode))
146 operands[1] = copy_to_mode_reg (HImode, operand1);
150 [(set (match_operand:HI 0 "nonimmediate_operand" "=d*x*a,d*x,d*x*a,d*x*a,m")
151 (match_operand:HI 1 "general_operand" "0,I,d*x*ai,m,d*x*a"))]
153 && (register_operand (operands[0], HImode)
154 || register_operand (operands[1], HImode))"
157 switch (which_alternative)
164 if (GET_CODE (operands[1]) == CONST_DOUBLE)
167 xoperands[0] = operands[0];
168 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
169 output_asm_insn (\"mov %1,%0\", xoperands);
173 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
174 && GET_CODE (operands[1]) == CONST_INT)
176 HOST_WIDE_INT val = INTVAL (operands[1]);
178 if (((val & 0x80) && ! (val & 0xffffff00))
179 || ((val & 0x800000) && ! (val & 0xff000000)))
180 return \"movu %1,%0\";
182 return \"mov %1,%0\";
185 return \"movhu %1,%0\";
190 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
193 [(set (match_operand:HI 0 "nonimmediate_operand" "=d*a,d,d*a,d,m")
194 (match_operand:HI 1 "general_operand" "0,I,dai,m,d"))]
195 "register_operand (operands[0], HImode)
196 || register_operand (operands[1], HImode)"
199 switch (which_alternative)
206 if (GET_CODE (operands[1]) == CONST_DOUBLE)
209 xoperands[0] = operands[0];
210 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
211 output_asm_insn (\"mov %1,%0\", xoperands);
214 return \"mov %1,%0\";
217 return \"movhu %1,%0\";
222 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
226 ;; We use this to handle addition of two values when one operand is the
227 ;; stack pointer and the other is a memory reference of some kind. Reload
228 ;; does not handle them correctly without this expander.
229 (define_expand "reload_insi"
230 [(set (match_operand:SI 0 "register_operand" "=a")
231 (match_operand:SI 1 "impossible_plus_operand" ""))
232 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
236 if (XEXP (operands[1], 0) == stack_pointer_rtx)
238 if (GET_CODE (XEXP (operands[1], 1)) == SUBREG
239 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 1)))
240 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 1))))))
241 emit_move_insn (operands[2],
243 (GET_MODE (XEXP (operands[1], 1)),
244 SUBREG_REG (XEXP (operands[1], 1))));
246 emit_move_insn (operands[2], XEXP (operands[1], 1));
247 emit_move_insn (operands[0], XEXP (operands[1], 0));
251 if (GET_CODE (XEXP (operands[1], 0)) == SUBREG
252 && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 0)))
253 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 0))))))
254 emit_move_insn (operands[2],
256 (GET_MODE (XEXP (operands[1], 0)),
257 SUBREG_REG (XEXP (operands[1], 0))));
259 emit_move_insn (operands[2], XEXP (operands[1], 0));
260 emit_move_insn (operands[0], XEXP (operands[1], 1));
262 emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
266 (define_expand "movsi"
267 [(set (match_operand:SI 0 "general_operand" "")
268 (match_operand:SI 1 "general_operand" ""))]
272 /* One of the ops has to be in a register */
273 if (!register_operand (operand1, SImode)
274 && !register_operand (operand0, SImode))
275 operands[1] = copy_to_mode_reg (SImode, operand1);
279 [(set (match_operand:SI 0 "nonimmediate_operand"
280 "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,!*y")
281 (match_operand:SI 1 "general_operand"
282 "0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,!*y,axR"))]
283 "register_operand (operands[0], SImode)
284 || register_operand (operands[1], SImode)"
287 switch (which_alternative)
305 if (GET_CODE (operands[1]) == CONST_DOUBLE)
308 xoperands[0] = operands[0];
309 xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
310 output_asm_insn (\"mov %1,%0\", xoperands);
314 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
315 && GET_CODE (operands[1]) == CONST_INT)
317 HOST_WIDE_INT val = INTVAL (operands[1]);
319 if (((val & 0x80) && ! (val & 0xffffff00))
320 || ((val & 0x800000) && ! (val & 0xff000000)))
321 return \"movu %1,%0\";
323 return \"mov %1,%0\";
328 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
330 (define_expand "movsf"
331 [(set (match_operand:SF 0 "general_operand" "")
332 (match_operand:SF 1 "general_operand" ""))]
336 /* One of the ops has to be in a register */
337 if (!register_operand (operand1, SFmode)
338 && !register_operand (operand0, SFmode))
339 operands[1] = copy_to_mode_reg (SFmode, operand1);
343 [(set (match_operand:SF 0 "nonimmediate_operand" "=dx,ax,dx,a,daxm,dax")
344 (match_operand:SF 1 "general_operand" "0,0,G,G,dax,daxFm"))]
345 "register_operand (operands[0], SFmode)
346 || register_operand (operands[1], SFmode)"
349 switch (which_alternative)
359 if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
360 && GET_CODE (operands[1]) == CONST_INT)
362 HOST_WIDE_INT val = INTVAL (operands[1]);
364 if (((val & 0x80) && ! (val & 0xffffff00))
365 || ((val & 0x800000) && ! (val & 0xff000000)))
366 return \"movu %1,%0\";
368 return \"mov %1,%0\";
373 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit")])
375 (define_expand "movdi"
376 [(set (match_operand:DI 0 "general_operand" "")
377 (match_operand:DI 1 "general_operand" ""))]
381 /* One of the ops has to be in a register */
382 if (!register_operand (operand1, DImode)
383 && !register_operand (operand0, DImode))
384 operands[1] = copy_to_mode_reg (DImode, operand1);
388 [(set (match_operand:DI 0 "nonimmediate_operand"
389 "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
390 (match_operand:DI 1 "general_operand"
391 "0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
392 "register_operand (operands[0], DImode)
393 || register_operand (operands[1], DImode)"
399 switch (which_alternative)
406 return \"clr %L0\;clr %H0\";
409 if (rtx_equal_p (operands[0], operands[1]))
410 return \"sub %L1,%L0\;mov %L0,%H0\";
412 return \"mov %1,%L0\;mov %L0,%H0\";
421 if (GET_CODE (operands[1]) == CONST_INT)
424 split_double (operands[1], &low, &high);
425 val[0] = INTVAL (low);
426 val[1] = INTVAL (high);
428 if (GET_CODE (operands[1]) == CONST_DOUBLE)
430 if (GET_MODE (operands[1]) == DFmode)
432 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
433 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
435 else if (GET_MODE (operands[1]) == VOIDmode
436 || GET_MODE (operands[1]) == DImode)
438 val[0] = CONST_DOUBLE_LOW (operands[1]);
439 val[1] = CONST_DOUBLE_HIGH (operands[1]);
443 if (GET_CODE (operands[1]) == MEM
444 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
446 rtx temp = operands[0];
448 while (GET_CODE (temp) == SUBREG)
449 temp = SUBREG_REG (temp);
451 if (GET_CODE (temp) != REG)
454 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
455 XEXP (operands[1], 0)))
456 return \"mov %H1,%H0\;mov %L1,%L0\";
458 return \"mov %L1,%L0\;mov %H1,%H0\";
461 else if (GET_CODE (operands[1]) == MEM
462 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
463 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
467 xoperands[0] = operands[0];
468 xoperands[1] = XEXP (operands[1], 0);
470 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
476 if ((GET_CODE (operands[1]) == CONST_INT
477 || GET_CODE (operands[1]) == CONST_DOUBLE)
480 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
481 output_asm_insn (\"clr %L0\", operands);
483 output_asm_insn (\"mov %L1,%L0\", operands);
485 else if ((GET_CODE (operands[1]) == CONST_INT
486 || GET_CODE (operands[1]) == CONST_DOUBLE)
487 && (REGNO_REG_CLASS (true_regnum (operands[0]))
489 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
490 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
491 output_asm_insn (\"movu %1,%0\", operands);
493 output_asm_insn (\"mov %L1,%L0\", operands);
495 if ((GET_CODE (operands[1]) == CONST_INT
496 || GET_CODE (operands[1]) == CONST_DOUBLE)
499 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
500 output_asm_insn (\"clr %H0\", operands);
502 output_asm_insn (\"mov %H1,%H0\", operands);
504 else if ((GET_CODE (operands[1]) == CONST_INT
505 || GET_CODE (operands[1]) == CONST_DOUBLE)
507 output_asm_insn (\"mov %L0,%H0\", operands);
508 else if ((GET_CODE (operands[1]) == CONST_INT
509 || GET_CODE (operands[1]) == CONST_DOUBLE)
510 && (REGNO_REG_CLASS (true_regnum (operands[0]))
512 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
513 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
514 output_asm_insn (\"movu %1,%0\", operands);
516 output_asm_insn (\"mov %H1,%H0\", operands);
523 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
525 (define_expand "movdf"
526 [(set (match_operand:DF 0 "general_operand" "")
527 (match_operand:DF 1 "general_operand" ""))]
531 /* One of the ops has to be in a register */
532 if (!register_operand (operand1, DFmode)
533 && !register_operand (operand0, DFmode))
534 operands[1] = copy_to_mode_reg (DFmode, operand1);
538 [(set (match_operand:DF 0 "nonimmediate_operand"
539 "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
540 (match_operand:DF 1 "general_operand"
541 "0,0,G,G,dx,ax,dx,ax,dxFm,axFm,dxFm,axFm"))]
542 "register_operand (operands[0], DFmode)
543 || register_operand (operands[1], DFmode)"
549 switch (which_alternative)
556 return \"clr %L0\;clr %H0\";
559 if (rtx_equal_p (operands[0], operands[1]))
560 return \"sub %L1,%L0\;mov %L0,%H0\";
562 return \"mov %1,%L0\;mov %L0,%H0\";
571 if (GET_CODE (operands[1]) == CONST_INT)
574 split_double (operands[1], &low, &high);
575 val[0] = INTVAL (low);
576 val[1] = INTVAL (high);
578 if (GET_CODE (operands[1]) == CONST_DOUBLE)
580 if (GET_MODE (operands[1]) == DFmode)
582 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
583 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
585 else if (GET_MODE (operands[1]) == VOIDmode
586 || GET_MODE (operands[1]) == DImode)
588 val[0] = CONST_DOUBLE_LOW (operands[1]);
589 val[1] = CONST_DOUBLE_HIGH (operands[1]);
593 if (GET_CODE (operands[1]) == MEM
594 && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
596 rtx temp = operands[0];
598 while (GET_CODE (temp) == SUBREG)
599 temp = SUBREG_REG (temp);
601 if (GET_CODE (temp) != REG)
604 if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
605 XEXP (operands[1], 0)))
606 return \"mov %H1,%H0\;mov %L1,%L0\";
608 return \"mov %L1,%L0\;mov %H1,%H0\";
611 else if (GET_CODE (operands[1]) == MEM
612 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
613 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
617 xoperands[0] = operands[0];
618 xoperands[1] = XEXP (operands[1], 0);
620 output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
626 if ((GET_CODE (operands[1]) == CONST_INT
627 || GET_CODE (operands[1]) == CONST_DOUBLE)
630 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
631 output_asm_insn (\"clr %L0\", operands);
633 output_asm_insn (\"mov %L1,%L0\", operands);
635 else if ((GET_CODE (operands[1]) == CONST_INT
636 || GET_CODE (operands[1]) == CONST_DOUBLE)
637 && (REGNO_REG_CLASS (true_regnum (operands[0]))
639 && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
640 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
641 output_asm_insn (\"movu %1,%0\", operands);
643 output_asm_insn (\"mov %L1,%L0\", operands);
645 if ((GET_CODE (operands[1]) == CONST_INT
646 || GET_CODE (operands[1]) == CONST_DOUBLE)
649 if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
650 output_asm_insn (\"clr %H0\", operands);
652 output_asm_insn (\"mov %H1,%H0\", operands);
654 else if ((GET_CODE (operands[1]) == CONST_INT
655 || GET_CODE (operands[1]) == CONST_DOUBLE)
657 output_asm_insn (\"mov %L0,%H0\", operands);
658 else if ((GET_CODE (operands[1]) == CONST_INT
659 || GET_CODE (operands[1]) == CONST_DOUBLE)
660 && (REGNO_REG_CLASS (true_regnum (operands[0]))
662 && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
663 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
664 output_asm_insn (\"movu %1,%0\", operands);
666 output_asm_insn (\"mov %H1,%H0\", operands);
673 [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
677 ;; ----------------------------------------------------------------------
679 ;; ----------------------------------------------------------------------
681 ;; Go ahead and define tstsi so we can eliminate redundant tst insns
682 ;; when we start trying to optimize this port.
684 [(set (cc0) (match_operand:SI 0 "register_operand" "dax"))]
686 "* return output_tst (operands[0], insn);"
687 [(set_attr "cc" "set_znv")])
690 [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx,!a")))]
692 "* return output_tst (operands[0], insn);"
693 [(set_attr "cc" "set_znv")])
696 [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
698 "* return output_tst (operands[0], insn);"
699 [(set_attr "cc" "set_znv")])
702 [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx,!a")))]
704 "* return output_tst (operands[0], insn);"
705 [(set_attr "cc" "set_znv")])
708 [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
710 "* return output_tst (operands[0], insn);"
711 [(set_attr "cc" "set_znv")])
713 ;; Ordinarily, the cmp instruction will set the Z bit of cc0 to 1 if
714 ;; its operands hold equal values, but the operands of a cmp
715 ;; instruction must be distinct registers. In the case where we'd
716 ;; like to compare a register to itself, we can achieve this effect
717 ;; with a btst 0,d0 instead. (This will not alter the contents of d0
718 ;; but will have the proper effect on cc0. Using d0 is arbitrary; any
719 ;; data register would work.)
721 ;; Even though the first alternative would be preferrable if it can
722 ;; possibly match, reload must not be given the opportunity to attempt
723 ;; to use it. It assumes that such matches can only occur when one of
724 ;; the operands is used for input and the other for output. Since
725 ;; this is not the case, it abort()s. Indeed, such a reload cannot be
726 ;; possibly satisfied, so just mark the alternative with a `!', so
727 ;; that it is not considered by reload.
731 (compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax")
732 (match_operand:SI 1 "nonmemory_operand" "*0,daxi")))]
737 [(set_attr "cc" "compare,compare")])
739 ;; ----------------------------------------------------------------------
741 ;; ----------------------------------------------------------------------
743 (define_expand "addsi3"
744 [(set (match_operand:SI 0 "register_operand" "")
745 (plus:SI (match_operand:SI 1 "register_operand" "")
746 (match_operand:SI 2 "nonmemory_operand" "")))]
751 [(set (match_operand:SI 0 "register_operand" "=dx,a,x,a,dax,!*y,!dax")
752 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,dax")
753 (match_operand:SI 2 "nonmemory_operand" "J,J,L,L,daxi,i,dax")))]
757 switch (which_alternative)
767 return \"add %2,%0\";
770 enum reg_class src1_class, src2_class, dst_class;
772 src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
773 src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
774 dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
776 /* I'm not sure if this can happen or not. Might as well be prepared
777 and generate the best possible code if it does happen. */
778 if (true_regnum (operands[0]) == true_regnum (operands[1]))
779 return \"add %2,%0\";
780 if (true_regnum (operands[0]) == true_regnum (operands[2]))
781 return \"add %1,%0\";
783 /* Catch cases where no extended register was used. These should be
784 handled just like the mn10300. */
785 if (src1_class != EXTENDED_REGS
786 && src2_class != EXTENDED_REGS
787 && dst_class != EXTENDED_REGS)
789 /* We have to copy one of the sources into the destination, then
790 add the other source to the destination.
792 Carefully select which source to copy to the destination; a naive
793 implementation will waste a byte when the source classes are
794 different and the destination is an address register. Selecting
795 the lowest cost register copy will optimize this sequence. */
796 if (REGNO_REG_CLASS (true_regnum (operands[1]))
797 == REGNO_REG_CLASS (true_regnum (operands[0])))
798 return \"mov %1,%0\;add %2,%0\";
799 return \"mov %2,%0\;add %1,%0\";
802 /* At least one register is an extended register. */
804 /* The three operand add instruction on the am33 is a win iff the
805 output register is an extended register, or if both source
806 registers are extended registers. */
807 if (dst_class == EXTENDED_REGS
808 || src1_class == src2_class)
809 return \"add %2,%1,%0\";
811 /* It is better to copy one of the sources to the destination, then
812 perform a 2 address add. The destination in this case must be
813 an address or data register and one of the sources must be an
814 extended register and the remaining source must not be an extended
817 The best code for this case is to copy the extended reg to the
818 destination, then emit a two address add. */
819 if (src1_class == EXTENDED_REGS)
820 return \"mov %1,%0\;add %2,%0\";
821 return \"mov %2,%0\;add %1,%0\";
827 [(set_attr "cc" "set_zn,none_0hit,set_zn,none_0hit,set_zn,none_0hit,set_zn")])
830 [(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,!*y,!dax")
831 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
832 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
836 switch (which_alternative)
845 return \"add %2,%0\";
847 /* I'm not sure if this can happen or not. Might as well be prepared
848 and generate the best possible code if it does happen. */
849 if (true_regnum (operands[0]) == true_regnum (operands[1]))
850 return \"add %2,%0\";
851 if (true_regnum (operands[0]) == true_regnum (operands[2]))
852 return \"add %1,%0\";
854 /* We have to copy one of the sources into the destination, then add
855 the other source to the destination.
857 Carefully select which source to copy to the destination; a naive
858 implementation will waste a byte when the source classes are different
859 and the destination is an address register. Selecting the lowest
860 cost register copy will optimize this sequence. */
861 if (REGNO_REG_CLASS (true_regnum (operands[1]))
862 == REGNO_REG_CLASS (true_regnum (operands[0])))
863 return \"mov %1,%0\;add %2,%0\";
864 return \"mov %2,%0\;add %1,%0\";
869 [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
871 ;; ----------------------------------------------------------------------
872 ;; SUBTRACT INSTRUCTIONS
873 ;; ----------------------------------------------------------------------
875 (define_expand "subsi3"
876 [(set (match_operand:SI 0 "register_operand" "")
877 (minus:SI (match_operand:SI 1 "register_operand" "")
878 (match_operand:SI 2 "nonmemory_operand" "")))]
883 [(set (match_operand:SI 0 "register_operand" "=dax,!dax")
884 (minus:SI (match_operand:SI 1 "register_operand" "0,dax")
885 (match_operand:SI 2 "nonmemory_operand" "daxi,dax")))]
889 if (true_regnum (operands[0]) == true_regnum (operands[1]))
890 return \"sub %2,%0\";
893 enum reg_class src1_class, src2_class, dst_class;
895 src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
896 src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
897 dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
899 /* If no extended registers are used, then the best way to handle
900 this is to copy the first source operand into the destination
901 and emit a two address subtraction. */
902 if (src1_class != EXTENDED_REGS
903 && src2_class != EXTENDED_REGS
904 && dst_class != EXTENDED_REGS
905 && true_regnum (operands[0]) != true_regnum (operands[2]))
906 return \"mov %1,%0\;sub %2,%0\";
907 return \"sub %2,%1,%0\";
910 [(set_attr "cc" "set_zn")])
913 [(set (match_operand:SI 0 "register_operand" "=dax")
914 (minus:SI (match_operand:SI 1 "register_operand" "0")
915 (match_operand:SI 2 "nonmemory_operand" "daxi")))]
918 [(set_attr "cc" "set_zn")])
920 (define_expand "negsi2"
921 [(set (match_operand:SI 0 "register_operand" "")
922 (neg:SI (match_operand:SI 1 "register_operand" "")))]
926 rtx target = gen_reg_rtx (SImode);
928 emit_move_insn (target, GEN_INT (0));
929 emit_insn (gen_subsi3 (target, target, operands[1]));
930 emit_move_insn (operands[0], target);
934 ;; ----------------------------------------------------------------------
935 ;; MULTIPLY INSTRUCTIONS
936 ;; ----------------------------------------------------------------------
938 (define_insn "mulsidi3"
939 [(set (match_operand:DI 0 "register_operand" "=dax")
940 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "dax"))
941 (sign_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
944 [(set_attr "cc" "set_zn")])
946 (define_insn "umulsidi3"
947 [(set (match_operand:DI 0 "register_operand" "=dax")
948 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax"))
949 (zero_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
952 [(set_attr "cc" "set_zn")])
954 (define_expand "mulsi3"
955 [(set (match_operand:SI 0 "register_operand" "")
956 (mult:SI (match_operand:SI 1 "register_operand" "")
957 (match_operand:SI 2 "register_operand" "")))]
962 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
963 (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
964 (match_operand:SI 2 "nonmemory_operand" "dx,daxi")))]
969 return \"nop\;nop\;mul %2,%0\";
971 return \"mul %2,%0\";
973 [(set_attr "cc" "set_zn")])
976 [(set (match_operand:SI 0 "register_operand" "=dx")
977 (mult:SI (match_operand:SI 1 "register_operand" "%0")
978 (match_operand:SI 2 "register_operand" "dx")))]
983 return \"nop\;nop\;mul %2,%0\";
985 return \"mul %2,%0\";
987 [(set_attr "cc" "set_zn")])
989 (define_insn "udivmodsi4"
990 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx")
991 (udiv:SI (match_operand:SI 1 "general_operand" "0")
992 (match_operand:SI 2 "general_operand" "dx")))
993 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
994 (umod:SI (match_dup 1) (match_dup 2)))]
998 output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
1000 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1001 return \"divu %2,%0\";
1003 return \"divu %2,%0\;mov mdr,%3\";
1005 [(set_attr "cc" "set_zn")])
1007 (define_insn "divmodsi4"
1008 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx")
1009 (div:SI (match_operand:SI 1 "general_operand" "0")
1010 (match_operand:SI 2 "general_operand" "dx")))
1011 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
1012 (mod:SI (match_dup 1) (match_dup 2)))]
1016 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1017 return \"ext %0\;div %2,%0\";
1019 return \"ext %0\;div %2,%0\;mov mdr,%3\";
1021 [(set_attr "cc" "set_zn")])
1024 ;; ----------------------------------------------------------------------
1026 ;; ----------------------------------------------------------------------
1028 (define_expand "andsi3"
1029 [(set (match_operand:SI 0 "register_operand" "")
1030 (and:SI (match_operand:SI 1 "register_operand" "")
1031 (match_operand:SI 2 "nonmemory_operand" "")))]
1036 [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
1037 (and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
1038 (match_operand:SI 2 "nonmemory_operand" "N,dxi,dax")))]
1042 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
1043 return \"extbu %0\";
1044 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
1045 return \"exthu %0\";
1046 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
1047 return \"add %0,%0\;lsr 1,%0\";
1048 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
1049 return \"asl2 %0\;lsr 2,%0\";
1050 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
1051 return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
1052 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
1053 return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
1054 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
1055 return \"lsr 1,%0\;add %0,%0\";
1056 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
1057 return \"lsr 2,%0\;asl2 %0\";
1058 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
1059 return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
1060 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
1061 return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
1062 if (REG_P (operands[2]) && REG_P (operands[1])
1063 && true_regnum (operands[0]) != true_regnum (operands[1])
1064 && true_regnum (operands[0]) != true_regnum (operands[2])
1065 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1066 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1067 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1068 return \"mov %1,%0\;and %2,%0\";
1069 if (REG_P (operands[2]) && REG_P (operands[1])
1070 && true_regnum (operands[0]) != true_regnum (operands[1])
1071 && true_regnum (operands[0]) != true_regnum (operands[2]))
1072 return \"and %1,%2,%0\";
1073 if (REG_P (operands[2]) && REG_P (operands[0])
1074 && true_regnum (operands[2]) == true_regnum (operands[0]))
1075 return \"and %1,%0\";
1076 return \"and %2,%0\";
1078 [(set_attr "cc" "none_0hit,set_znv,set_znv")])
1081 [(set (match_operand:SI 0 "register_operand" "=dx,dx")
1082 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1083 (match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
1087 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
1088 return \"extbu %0\";
1089 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
1090 return \"exthu %0\";
1091 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
1092 return \"add %0,%0\;lsr 1,%0\";
1093 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
1094 return \"asl2 %0\;lsr 2,%0\";
1095 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
1096 return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
1097 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
1098 return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
1099 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
1100 return \"lsr 1,%0\;add %0,%0\";
1101 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
1102 return \"lsr 2,%0\;asl2 %0\";
1103 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
1104 return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
1105 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
1106 return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
1107 return \"and %2,%0\";
1109 [(set_attr "cc" "none_0hit,set_znv")])
1111 ;; ----------------------------------------------------------------------
1113 ;; ----------------------------------------------------------------------
1115 (define_expand "iorsi3"
1116 [(set (match_operand:SI 0 "register_operand" "")
1117 (ior:SI (match_operand:SI 1 "register_operand" "")
1118 (match_operand:SI 2 "nonmemory_operand" "")))]
1123 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1124 (ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
1125 (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
1129 if (REG_P (operands[2]) && REG_P (operands[1])
1130 && true_regnum (operands[0]) != true_regnum (operands[1])
1131 && true_regnum (operands[0]) != true_regnum (operands[2])
1132 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1133 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1134 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1135 return \"mov %1,%0\;or %2,%0\";
1136 if (REG_P (operands[2]) && REG_P (operands[1])
1137 && true_regnum (operands[0]) != true_regnum (operands[1])
1138 && true_regnum (operands[0]) != true_regnum (operands[2]))
1139 return \"or %1,%2,%0\";
1140 if (REG_P (operands[2]) && REG_P (operands[0])
1141 && true_regnum (operands[2]) == true_regnum (operands[0]))
1142 return \"or %1,%0\";
1143 return \"or %2,%0\";
1145 [(set_attr "cc" "set_znv")])
1148 [(set (match_operand:SI 0 "register_operand" "=dx")
1149 (ior:SI (match_operand:SI 1 "register_operand" "%0")
1150 (match_operand:SI 2 "nonmemory_operand" "dxi")))]
1153 [(set_attr "cc" "set_znv")])
1155 ;; ----------------------------------------------------------------------
1157 ;; ----------------------------------------------------------------------
1159 (define_expand "xorsi3"
1160 [(set (match_operand:SI 0 "register_operand" "")
1161 (xor:SI (match_operand:SI 1 "register_operand" "")
1162 (match_operand:SI 2 "nonmemory_operand" "")))]
1167 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1168 (xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
1169 (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
1173 if (REG_P (operands[2]) && REG_P (operands[1])
1174 && true_regnum (operands[0]) != true_regnum (operands[1])
1175 && true_regnum (operands[0]) != true_regnum (operands[2])
1176 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1177 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1178 && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1179 return \"mov %1,%0\;xor %2,%0\";
1180 if (REG_P (operands[2]) && REG_P (operands[1])
1181 && true_regnum (operands[0]) != true_regnum (operands[1])
1182 && true_regnum (operands[0]) != true_regnum (operands[2]))
1183 return \"xor %1,%2,%0\";
1184 if (REG_P (operands[2]) && REG_P (operands[0])
1185 && true_regnum (operands[2]) == true_regnum (operands[0]))
1186 return \"xor %1,%0\";
1187 return \"xor %2,%0\";
1189 [(set_attr "cc" "set_znv")])
1192 [(set (match_operand:SI 0 "register_operand" "=dx")
1193 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1194 (match_operand:SI 2 "nonmemory_operand" "dxi")))]
1197 [(set_attr "cc" "set_znv")])
1199 ;; ----------------------------------------------------------------------
1201 ;; ----------------------------------------------------------------------
1203 (define_expand "one_cmplsi2"
1204 [(set (match_operand:SI 0 "register_operand" "")
1205 (not:SI (match_operand:SI 1 "register_operand" "")))]
1210 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1211 (not:SI (match_operand:SI 1 "register_operand" "0,0")))]
1214 [(set_attr "cc" "set_znv")])
1217 [(set (match_operand:SI 0 "register_operand" "=dx")
1218 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1221 [(set_attr "cc" "set_znv")])
1223 ;; -----------------------------------------------------------------
1225 ;; -----------------------------------------------------------------
1228 ;; These set/clear memory in byte sized chunks.
1230 ;; They are no smaller/faster than loading the value into a register
1231 ;; and storing the register, but they don't need a scratch register
1232 ;; which may allow for better code generation.
1234 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int 0))]
1239 [(set_attr "cc" "clobber")])
1242 [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int -1))]
1247 [(set_attr "cc" "clobber,none_0hit")])
1250 [(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1252 (and:SI (subreg:SI (match_dup 0) 0)
1253 (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
1258 [(set_attr "cc" "clobber,set_znv")])
1261 [(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1263 (ior:SI (subreg:SI (match_dup 0) 0)
1264 (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
1269 [(set_attr "cc" "clobber,set_znv")])
1273 (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
1274 (match_operand 1 "const_int_operand" "")
1275 (match_operand 2 "const_int_operand" "")))]
1279 int len = INTVAL (operands[1]);
1280 int bit = INTVAL (operands[2]);
1291 xoperands[0] = operands[0];
1292 xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
1293 output_asm_insn (\"btst %1,%0\", xoperands);
1296 [(set_attr "cc" "clobber")])
1300 (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
1301 (match_operand 1 "const_int_operand" "")
1302 (match_operand 2 "const_int_operand" "")))]
1303 "mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
1306 int len = INTVAL (operands[1]);
1307 int bit = INTVAL (operands[2]);
1318 /* If the source operand is not a reg (ie it is memory), then extract the
1319 bits from mask that we actually want to test. Note that the mask will
1320 never cross a byte boundary. */
1321 if (!REG_P (operands[0]))
1325 else if (mask & 0xff00)
1326 mask = (mask >> 8) & 0xff;
1327 else if (mask & 0xff0000)
1328 mask = (mask >> 16) & 0xff;
1329 else if (mask & 0xff000000)
1330 mask = (mask >> 24) & 0xff;
1333 xoperands[0] = operands[0];
1334 xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
1335 if (GET_CODE (operands[0]) == REG)
1336 output_asm_insn (\"btst %1,%0\", xoperands);
1338 output_asm_insn (\"btst %1,%A0\", xoperands);
1341 [(set_attr "cc" "clobber")])
1344 [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx")
1345 (match_operand:SI 1 "const_int_operand" "")))]
1348 [(set_attr "cc" "clobber")])
1353 (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
1354 (match_operand:SI 1 "const_8bit_operand" "")))]
1359 [(set_attr "cc" "clobber")])
1362 ;; ----------------------------------------------------------------------
1363 ;; JUMP INSTRUCTIONS
1364 ;; ----------------------------------------------------------------------
1366 ;; Conditional jump instructions
1368 (define_expand "ble"
1370 (if_then_else (le (cc0)
1372 (label_ref (match_operand 0 "" ""))
1377 (define_expand "bleu"
1379 (if_then_else (leu (cc0)
1381 (label_ref (match_operand 0 "" ""))
1386 (define_expand "bge"
1388 (if_then_else (ge (cc0)
1390 (label_ref (match_operand 0 "" ""))
1395 (define_expand "bgeu"
1397 (if_then_else (geu (cc0)
1399 (label_ref (match_operand 0 "" ""))
1404 (define_expand "blt"
1406 (if_then_else (lt (cc0)
1408 (label_ref (match_operand 0 "" ""))
1413 (define_expand "bltu"
1415 (if_then_else (ltu (cc0)
1417 (label_ref (match_operand 0 "" ""))
1422 (define_expand "bgt"
1424 (if_then_else (gt (cc0)
1426 (label_ref (match_operand 0 "" ""))
1431 (define_expand "bgtu"
1433 (if_then_else (gtu (cc0)
1435 (label_ref (match_operand 0 "" ""))
1440 (define_expand "beq"
1442 (if_then_else (eq (cc0)
1444 (label_ref (match_operand 0 "" ""))
1449 (define_expand "bne"
1451 (if_then_else (ne (cc0)
1453 (label_ref (match_operand 0 "" ""))
1460 (if_then_else (match_operator 1 "comparison_operator"
1461 [(cc0) (const_int 0)])
1462 (label_ref (match_operand 0 "" ""))
1467 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1468 && (GET_CODE (operands[1]) == GT
1469 || GET_CODE (operands[1]) == GE
1470 || GET_CODE (operands[1]) == LE
1471 || GET_CODE (operands[1]) == LT))
1475 [(set_attr "cc" "none")])
1479 (if_then_else (match_operator 1 "comparison_operator"
1480 [(cc0) (const_int 0)])
1482 (label_ref (match_operand 0 "" ""))))]
1486 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1487 && (GET_CODE (operands[1]) == GT
1488 || GET_CODE (operands[1]) == GE
1489 || GET_CODE (operands[1]) == LE
1490 || GET_CODE (operands[1]) == LT))
1494 [(set_attr "cc" "none")])
1496 ;; Unconditional and other jump instructions.
1500 (label_ref (match_operand 0 "" "")))]
1503 [(set_attr "cc" "none")])
1505 (define_insn "indirect_jump"
1506 [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1509 [(set_attr "cc" "none")])
1511 (define_insn "tablejump"
1512 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1513 (use (label_ref (match_operand 1 "" "")))]
1516 [(set_attr "cc" "none")])
1518 ;; Call subroutine with no return value.
1520 (define_expand "call"
1521 [(call (match_operand:QI 0 "general_operand" "")
1522 (match_operand:SI 1 "general_operand" ""))]
1526 if (! call_address_operand (XEXP (operands[0], 0), VOIDmode))
1527 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1528 emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
1532 (define_insn "call_internal"
1533 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "aS"))
1534 (match_operand:SI 1 "general_operand" "g"))]
1538 if (REG_P (operands[0]))
1539 return \"calls %C0\";
1541 return \"call %C0,[],0\";
1543 [(set_attr "cc" "clobber")])
1545 ;; Call subroutine, returning value in operand 0
1546 ;; (which must be a hard register).
1548 (define_expand "call_value"
1549 [(set (match_operand 0 "" "")
1550 (call (match_operand:QI 1 "general_operand" "")
1551 (match_operand:SI 2 "general_operand" "")))]
1555 if (! call_address_operand (XEXP (operands[1], 0), VOIDmode))
1556 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1557 emit_call_insn (gen_call_value_internal (operands[0],
1558 XEXP (operands[1], 0),
1563 (define_insn "call_value_internal"
1564 [(set (match_operand 0 "" "=dax")
1565 (call (mem:QI (match_operand:SI 1 "call_address_operand" "aS"))
1566 (match_operand:SI 2 "general_operand" "g")))]
1570 if (REG_P (operands[1]))
1571 return \"calls %C1\";
1573 return \"call %C1,[],0\";
1575 [(set_attr "cc" "clobber")])
1577 (define_expand "untyped_call"
1578 [(parallel [(call (match_operand 0 "" "")
1580 (match_operand 1 "" "")
1581 (match_operand 2 "" "")])]
1587 emit_call_insn (gen_call (operands[0], const0_rtx));
1589 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1591 rtx set = XVECEXP (operands[2], 0, i);
1592 emit_move_insn (SET_DEST (set), SET_SRC (set));
1601 [(set_attr "cc" "none")])
1603 ;; ----------------------------------------------------------------------
1604 ;; EXTEND INSTRUCTIONS
1605 ;; ----------------------------------------------------------------------
1607 (define_expand "zero_extendqisi2"
1608 [(set (match_operand:SI 0 "general_operand" "")
1610 (match_operand:QI 1 "general_operand" "")))]
1615 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax")
1617 (match_operand:QI 1 "general_operand" "0,dax,m,0,dax,m")))]
1626 [(set_attr "cc" "none_0hit")])
1629 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx")
1631 (match_operand:QI 1 "general_operand" "0,d,m")))]
1637 [(set_attr "cc" "none_0hit")])
1639 (define_expand "zero_extendhisi2"
1640 [(set (match_operand:SI 0 "general_operand" "")
1642 (match_operand:HI 1 "general_operand" "")))]
1647 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax")
1649 (match_operand:HI 1 "general_operand" "0,dax,m,0,dax,m")))]
1658 [(set_attr "cc" "none_0hit")])
1661 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx")
1663 (match_operand:HI 1 "general_operand" "0,dx,m")))]
1669 [(set_attr "cc" "none_0hit")])
1671 ;;- sign extension instructions
1673 (define_expand "extendqisi2"
1674 [(set (match_operand:SI 0 "general_operand" "")
1676 (match_operand:QI 1 "general_operand" "")))]
1681 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax")
1683 (match_operand:QI 1 "general_operand" "0,dx,0,dax")))]
1690 [(set_attr "cc" "none_0hit")])
1693 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx")
1695 (match_operand:QI 1 "general_operand" "0,dx")))]
1700 [(set_attr "cc" "none_0hit")])
1702 (define_expand "extendhisi2"
1703 [(set (match_operand:SI 0 "general_operand" "")
1705 (match_operand:HI 1 "general_operand" "")))]
1710 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax")
1712 (match_operand:HI 1 "general_operand" "0,dax,0,dax")))]
1719 [(set_attr "cc" "none_0hit")])
1722 [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx")
1724 (match_operand:HI 1 "general_operand" "0,dx")))]
1729 [(set_attr "cc" "none_0hit")])
1731 ;; ----------------------------------------------------------------------
1733 ;; ----------------------------------------------------------------------
1735 (define_expand "ashlsi3"
1736 [(set (match_operand:SI 0 "register_operand" "")
1738 (match_operand:SI 1 "register_operand" "")
1739 (match_operand:QI 2 "nonmemory_operand" "")))]
1744 [(set (match_operand:SI 0 "register_operand" "=dax,dx,!dax")
1746 (match_operand:SI 1 "register_operand" "0,0,dax")
1747 (match_operand:QI 2 "nonmemory_operand" "J,dxi,dax")))]
1751 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1)
1752 return \"add %0,%0\";
1754 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 2)
1757 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 3
1758 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
1759 return \"asl2 %0\;add %0,%0\";
1761 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 4
1762 && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
1763 return \"asl2 %0\;asl2 %0\";
1765 if (true_regnum (operands[1]) == true_regnum (operands[0]))
1766 return \"asl %S2,%0\";
1768 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1769 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1770 && true_regnum (operands[0]) != true_regnum (operands[2]))
1771 return \"mov %1,%0\;asl %S2,%0\";
1772 return \"asl %2,%1,%0\";
1774 [(set_attr "cc" "set_zn")])
1777 [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
1779 (match_operand:SI 1 "register_operand" "0,0,0,0,0")
1780 (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))]
1788 [(set_attr "cc" "set_zn")])
1790 (define_expand "lshrsi3"
1791 [(set (match_operand:SI 0 "register_operand" "")
1793 (match_operand:SI 1 "register_operand" "")
1794 (match_operand:QI 2 "nonmemory_operand" "")))]
1799 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1801 (match_operand:SI 1 "register_operand" "0,dax")
1802 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
1806 if (true_regnum (operands[1]) == true_regnum (operands[0]))
1807 return \"lsr %S2,%0\";
1809 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1810 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1811 && true_regnum (operands[0]) != true_regnum (operands[2]))
1812 return \"mov %1,%0\;lsr %S2,%0\";
1813 return \"lsr %2,%1,%0\";
1815 [(set_attr "cc" "set_zn")])
1818 [(set (match_operand:SI 0 "register_operand" "=dx")
1820 (match_operand:SI 1 "register_operand" "0")
1821 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
1824 [(set_attr "cc" "set_zn")])
1826 (define_expand "ashrsi3"
1827 [(set (match_operand:SI 0 "register_operand" "")
1829 (match_operand:SI 1 "register_operand" "")
1830 (match_operand:QI 2 "nonmemory_operand" "")))]
1835 [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1837 (match_operand:SI 1 "register_operand" "0,dax")
1838 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
1842 if (true_regnum (operands[1]) == true_regnum (operands[0]))
1843 return \"asr %S2,%0\";
1845 if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1846 && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1847 && true_regnum (operands[0]) != true_regnum (operands[2]))
1848 return \"mov %1,%0\;asr %S2,%0\";
1849 return \"asr %2,%1,%0\";
1851 [(set_attr "cc" "set_zn")])
1854 [(set (match_operand:SI 0 "register_operand" "=dx")
1856 (match_operand:SI 1 "register_operand" "0")
1857 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
1860 [(set_attr "cc" "set_zn")])
1862 ;; ----------------------------------------------------------------------
1864 ;; ----------------------------------------------------------------------
1866 ;; The mn103 series does not have floating point instructions, but since
1867 ;; FP values are held in integer regs, we can clear the high bit easily
1868 ;; which gives us an efficient inline floating point absolute value.
1870 ;; Similarly for negation of a FP value.
1873 (define_expand "absdf2"
1874 [(set (match_operand:DF 0 "register_operand" "")
1875 (abs:DF (match_operand:DF 1 "register_operand" "")))]
1879 rtx target, result, insns;
1882 target = operand_subword (operands[0], 1, 1, DFmode);
1883 result = expand_binop (SImode, and_optab,
1884 operand_subword_force (operands[1], 1, DFmode),
1885 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
1890 if (result != target)
1891 emit_move_insn (result, target);
1893 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
1894 operand_subword_force (operands[1], 0, DFmode));
1896 insns = get_insns ();
1899 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1903 (define_expand "abssf2"
1904 [(set (match_operand:SF 0 "register_operand" "")
1905 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1912 target = operand_subword_force (operands[0], 0, SFmode);
1913 result = expand_binop (SImode, and_optab,
1914 operand_subword_force (operands[1], 0, SFmode),
1915 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
1919 if (result != target)
1920 emit_move_insn (result, target);
1922 /* Make a place for REG_EQUAL. */
1923 emit_move_insn (operands[0], operands[0]);
1928 (define_expand "negdf2"
1929 [(set (match_operand:DF 0 "register_operand" "")
1930 (neg:DF (match_operand:DF 1 "register_operand" "")))]
1934 rtx target, result, insns;
1937 target = operand_subword (operands[0], 1, 1, DFmode);
1938 result = expand_binop (SImode, xor_optab,
1939 operand_subword_force (operands[1], 1, DFmode),
1940 GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
1941 target, 0, OPTAB_WIDEN);
1946 if (result != target)
1947 emit_move_insn (result, target);
1949 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
1950 operand_subword_force (operands[1], 0, DFmode));
1952 insns = get_insns ();
1955 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1959 (define_expand "negsf2"
1960 [(set (match_operand:SF 0 "register_operand" "")
1961 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1968 target = operand_subword_force (operands[0], 0, SFmode);
1969 result = expand_binop (SImode, xor_optab,
1970 operand_subword_force (operands[1], 0, SFmode),
1971 GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
1972 target, 0, OPTAB_WIDEN);
1976 if (result != target)
1977 emit_move_insn (result, target);
1979 /* Make a place for REG_EQUAL. */
1980 emit_move_insn (operands[0], operands[0]);
1985 ;; ----------------------------------------------------------------------
1986 ;; PROLOGUE/EPILOGUE
1987 ;; ----------------------------------------------------------------------
1988 (define_expand "prologue"
1991 "expand_prologue (); DONE;")
1993 (define_expand "epilogue"
2002 (define_insn "return_internal"
2007 [(set_attr "cc" "clobber")])
2009 ;; This insn restores the callee saved registers and does a return, it
2010 ;; can also deallocate stack space.
2011 (define_insn "return_internal_regs"
2013 (match_operand:SI 0 "const_int_operand" "i")
2018 fputs (\"\\tret \", asm_out_file);
2019 mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ());
2020 fprintf (asm_out_file, \",%d\\n\", (int) INTVAL (operands[0]));
2023 [(set_attr "cc" "clobber")])
2025 ;; This instruction matches one generated by mn10300_gen_multiple_store()
2026 (define_insn "store_movm"
2027 [(match_parallel 0 "store_multiple_operation"
2028 [(set (reg:SI 9) (plus:SI (reg:SI 9) (match_operand 1 "" "")))])]
2032 fputs (\"\\tmovm \", asm_out_file);
2033 mn10300_print_reg_list (asm_out_file,
2034 store_multiple_operation (operands[0], VOIDmode));
2035 fprintf (asm_out_file, \",(sp)\\n\");
2038 [(set_attr "cc" "clobber")])
2040 (define_insn "return"
2042 "can_use_return_insn ()"
2045 rtx next = next_active_insn (insn);
2048 && GET_CODE (next) == JUMP_INSN
2049 && GET_CODE (PATTERN (next)) == RETURN)
2054 [(set_attr "cc" "clobber")])
2056 ;; Try to combine consecutive updates of the stack pointer (or any
2057 ;; other register for that matter).
2059 [(set (match_operand:SI 0 "register_operand" "=dxay")
2060 (plus:SI (match_dup 0)
2061 (match_operand 1 "const_int_operand" "")))
2063 (plus:SI (match_dup 0)
2064 (match_operand 2 "const_int_operand" "")))]
2068 operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
2069 return \"add %1,%0\";
2071 [(set_attr "cc" "clobber")])
2074 ;; We had patterns to check eq/ne, but the they don't work because
2075 ;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
2077 ;; The Z flag and C flag would be set, and we have no way to
2078 ;; check for the Z flag set and C flag clear.
2080 ;; This will work on the mn10200 because we can check the ZX flag
2081 ;; if the comparison is in HImode.
2083 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2084 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2085 (match_operand 1 "" "")
2087 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2089 [(set_attr "cc" "clobber")])
2092 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2093 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2094 (match_operand 1 "" "")
2096 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2098 [(set_attr "cc" "clobber")])
2101 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2102 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2104 (match_operand 1 "" "")))]
2105 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2107 [(set_attr "cc" "clobber")])
2110 [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2111 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2113 (match_operand 1 "" "")))]
2114 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2116 [(set_attr "cc" "clobber")])