1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
42 #include "target-def.h"
44 /* The size of the callee register save area. Right now we save everything
45 on entry since it costs us nothing in code size. It does cost us from a
46 speed standpoint, so we want to optimize this sooner or later. */
47 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
48 + 4 * regs_ever_live[3] \
49 + 4 * regs_ever_live[6] \
50 + 4 * regs_ever_live[7] \
51 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
52 || regs_ever_live[16] || regs_ever_live[17]))
54 /* Initialize the GCC target structure. */
56 struct gcc_target target = TARGET_INITIALIZER;
62 fprintf (file, "#\tGCC For the Matsushita MN10300\n");
64 fprintf (file, "# -O%d\n", optimize);
66 fprintf (file, "\n\n");
69 fprintf (file, "\t.am33\n");
70 output_file_directive (file, main_input_filename);
74 /* Print operand X using operand code CODE to assembly language output file
78 print_operand (file, x, code)
87 /* These are normal and reversed branches. */
88 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
100 fprintf (file, "gt");
103 fprintf (file, "le");
106 fprintf (file, "lt");
109 fprintf (file, "cc");
112 fprintf (file, "hi");
115 fprintf (file, "ls");
118 fprintf (file, "cs");
125 /* This is used for the operand to a call instruction;
126 if it's a REG, enclose it in parens, else output
127 the operand normally. */
128 if (GET_CODE (x) == REG)
131 print_operand (file, x, 0);
135 print_operand (file, x, 0);
138 /* These are the least significant word in a 64bit value. */
140 switch (GET_CODE (x))
144 output_address (XEXP (x, 0));
149 fprintf (file, "%s", reg_names[REGNO (x)]);
153 fprintf (file, "%s", reg_names[subreg_regno (x)]);
161 switch (GET_MODE (x))
164 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
165 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
166 fprintf (file, "0x%lx", val[0]);
169 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
170 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
171 fprintf (file, "0x%lx", val[0]);
175 print_operand_address (file,
176 GEN_INT (CONST_DOUBLE_LOW (x)));
187 split_double (x, &low, &high);
188 fprintf (file, "%ld", (long)INTVAL (low));
197 /* Similarly, but for the most significant word. */
199 switch (GET_CODE (x))
203 x = adjust_address (x, SImode, 4);
204 output_address (XEXP (x, 0));
209 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
213 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
221 switch (GET_MODE (x))
224 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
225 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
226 fprintf (file, "0x%lx", val[1]);
232 print_operand_address (file,
233 GEN_INT (CONST_DOUBLE_HIGH (x)));
244 split_double (x, &low, &high);
245 fprintf (file, "%ld", (long)INTVAL (high));
256 if (GET_CODE (XEXP (x, 0)) == REG)
257 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
259 output_address (XEXP (x, 0));
264 output_address (GEN_INT ((~INTVAL (x)) & 0xff));
267 /* For shift counts. The hardware ignores the upper bits of
268 any immediate, but the assembler will flag an out of range
269 shift count as an error. So we mask off the high bits
270 of the immediate here. */
272 if (GET_CODE (x) == CONST_INT)
274 fprintf (file, "%d", INTVAL (x) & 0x1f);
280 switch (GET_CODE (x))
284 output_address (XEXP (x, 0));
293 fprintf (file, "%s", reg_names[REGNO (x)]);
297 fprintf (file, "%s", reg_names[subreg_regno (x)]);
300 /* This will only be single precision.... */
306 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
307 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
308 fprintf (file, "0x%lx", val);
317 print_operand_address (file, x);
326 /* Output assembly language output for the address ADDR to FILE. */
329 print_operand_address (file, addr)
333 switch (GET_CODE (addr))
336 print_operand_address (file, XEXP (addr, 0));
340 print_operand (file, addr, 0);
345 if (REG_P (XEXP (addr, 0))
346 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
347 base = XEXP (addr, 0), index = XEXP (addr, 1);
348 else if (REG_P (XEXP (addr, 1))
349 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
350 base = XEXP (addr, 1), index = XEXP (addr, 0);
353 print_operand (file, index, 0);
355 print_operand (file, base, 0);;
359 output_addr_const (file, addr);
362 output_addr_const (file, addr);
367 /* Print a set of registers in the format required by "movm" and "ret".
368 Register K is saved if bit K of MASK is set. The data and address
369 registers can be stored individually, but the extended registers cannot.
370 We assume that the mask alread takes that into account. For instance,
371 bits 14 to 17 must have the same value. */
374 mn10300_print_reg_list (file, mask)
384 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
385 if ((mask & (1 << i)) != 0)
389 fputs (reg_names [i], file);
393 if ((mask & 0x3c000) != 0)
395 if ((mask & 0x3c000) != 0x3c000)
399 fputs ("exreg1", file);
407 can_use_return_insn ()
409 /* size includes the fixed stack space needed for function calls. */
410 int size = get_frame_size () + current_function_outgoing_args_size;
412 /* And space for the return pointer. */
413 size += current_function_outgoing_args_size ? 4 : 0;
415 return (reload_completed
417 && !regs_ever_live[2]
418 && !regs_ever_live[3]
419 && !regs_ever_live[6]
420 && !regs_ever_live[7]
421 && !regs_ever_live[14]
422 && !regs_ever_live[15]
423 && !regs_ever_live[16]
424 && !regs_ever_live[17]
425 && !frame_pointer_needed);
428 /* Returns the set of live, callee-saved registers as a bitmask. The
429 callee-saved extended registers cannot be stored individually, so
430 all of them will be included in the mask if any one of them is used. */
433 mn10300_get_live_callee_saved_regs ()
439 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
440 if (regs_ever_live[i] && ! call_used_regs[i])
442 if ((mask & 0x3c000) != 0)
448 /* Generate an instruction that pushes several registers onto the stack.
449 Register K will be saved if bit K in MASK is set. The function does
450 nothing if MASK is zero.
452 To be compatible with the "movm" instruction, the lowest-numbered
453 register must be stored in the lowest slot. If MASK is the set
454 { R1,...,RN }, where R1...RN are ordered least first, the generated
455 instruction will have the form:
458 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
459 (set (mem:SI (plus:SI (reg:SI 9)
463 (set (mem:SI (plus:SI (reg:SI 9)
468 mn10300_gen_multiple_store (mask)
478 /* Count how many registers need to be saved. */
480 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
481 if ((mask & (1 << i)) != 0)
484 /* We need one PARALLEL element to update the stack pointer and
485 an additional element for each register that is stored. */
486 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
488 /* Create the instruction that updates the stack pointer. */
490 = gen_rtx_SET (SImode,
492 gen_rtx_PLUS (SImode,
494 GEN_INT (-count * 4)));
496 /* Create each store. */
498 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
499 if ((mask & (1 << i)) != 0)
501 rtx address = gen_rtx_PLUS (SImode,
503 GEN_INT (-pari * 4));
504 XVECEXP(par, 0, pari)
505 = gen_rtx_SET (VOIDmode,
506 gen_rtx_MEM (SImode, address),
507 gen_rtx_REG (SImode, i));
511 par = emit_insn (par);
512 RTX_FRAME_RELATED_P (par) = 1;
521 /* SIZE includes the fixed stack space needed for function calls. */
522 size = get_frame_size () + current_function_outgoing_args_size;
523 size += (current_function_outgoing_args_size ? 4 : 0);
525 /* If this is an old-style varargs function, then its arguments
526 need to be flushed back to the stack. */
527 if (current_function_varargs)
529 emit_move_insn (gen_rtx_MEM (SImode,
530 plus_constant (stack_pointer_rtx, 4)),
531 gen_rtx_REG (SImode, 0));
532 emit_move_insn (gen_rtx_MEM (SImode,
533 plus_constant (stack_pointer_rtx, 8)),
534 gen_rtx_REG (SImode, 1));
537 /* If we use any of the callee-saved registers, save them now. */
538 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
540 /* Now put the frame pointer into the frame pointer register. */
541 if (frame_pointer_needed)
542 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
544 /* Allocate stack for this frame. */
546 emit_insn (gen_addsi3 (stack_pointer_rtx,
556 /* SIZE includes the fixed stack space needed for function calls. */
557 size = get_frame_size () + current_function_outgoing_args_size;
558 size += (current_function_outgoing_args_size ? 4 : 0);
560 /* Maybe cut back the stack, except for the register save area.
562 If the frame pointer exists, then use the frame pointer to
565 If the stack size + register save area is more than 255 bytes,
566 then the stack must be cut back here since the size + register
567 save size is too big for a ret/retf instruction.
569 Else leave it alone, it will be cut back as part of the
570 ret/retf instruction, or there wasn't any stack to begin with.
572 Under no circumstanes should the register save area be
573 deallocated here, that would leave a window where an interrupt
574 could occur and trash the register save area. */
575 if (frame_pointer_needed)
577 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
580 else if (size + REG_SAVE_BYTES > 255)
582 emit_insn (gen_addsi3 (stack_pointer_rtx,
588 /* Adjust the stack and restore callee-saved registers, if any. */
589 if (size || regs_ever_live[2] || regs_ever_live[3]
590 || regs_ever_live[6] || regs_ever_live[7]
591 || regs_ever_live[14] || regs_ever_live[15]
592 || regs_ever_live[16] || regs_ever_live[17]
593 || frame_pointer_needed)
594 emit_jump_insn (gen_return_internal_regs
595 (GEN_INT (size + REG_SAVE_BYTES)));
597 emit_jump_insn (gen_return_internal ());
600 /* Update the condition code from the insn. */
603 notice_update_cc (body, insn)
607 switch (get_attr_cc (insn))
610 /* Insn does not affect CC at all. */
614 /* Insn does not change CC, but the 0'th operand has been changed. */
615 if (cc_status.value1 != 0
616 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
617 cc_status.value1 = 0;
621 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
624 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
625 cc_status.value1 = recog_data.operand[0];
629 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
632 cc_status.flags |= CC_NO_CARRY;
633 cc_status.value1 = recog_data.operand[0];
637 /* The insn is a compare instruction. */
639 cc_status.value1 = SET_SRC (body);
643 /* The insn is a compare instruction. */
645 cc_status.value1 = SET_SRC (body);
646 cc_status.flags |= CC_INVERTED;
650 /* Insn doesn't leave CC in a usable state. */
659 /* Recognise the PARALLEL rtx generated by mn10300_gen_multiple_store().
660 This function is for MATCH_PARALLEL and so assumes OP is known to be
661 parallel. If OP is a multiple store, return a mask indicating which
662 registers it saves. Return 0 otherwise. */
665 store_multiple_operation (op, mode)
667 enum machine_mode mode ATTRIBUTE_UNUSED;
675 count = XVECLEN (op, 0);
679 /* Check that first instruction has the form (set (sp) (plus A B)) */
680 elt = XVECEXP (op, 0, 0);
681 if (GET_CODE (elt) != SET
682 || GET_CODE (SET_DEST (elt)) != REG
683 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
684 || GET_CODE (SET_SRC (elt)) != PLUS)
687 /* Check that A is the stack pointer and B is the expected stack size.
688 For OP to match, each subsequent instruction should push a word onto
689 the stack. We therefore expect the first instruction to create
690 COUNT-1 stack slots. */
692 if (GET_CODE (XEXP (elt, 0)) != REG
693 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
694 || GET_CODE (XEXP (elt, 1)) != CONST_INT
695 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
698 /* Now go through the rest of the vector elements. They must be
699 ordered so that the first instruction stores the highest-numbered
700 register to the highest stack slot and that subsequent instructions
701 store a lower-numbered register to the slot below.
703 LAST keeps track of the smallest-numbered register stored so far.
704 MASK is the set of stored registers. */
705 last = FIRST_PSEUDO_REGISTER;
707 for (i = 1; i < count; i++)
709 /* Check that element i is a (set (mem M) R) and that R is valid. */
710 elt = XVECEXP (op, 0, i);
711 if (GET_CODE (elt) != SET
712 || GET_CODE (SET_DEST (elt)) != MEM
713 || GET_CODE (SET_SRC (elt)) != REG
714 || REGNO (SET_SRC (elt)) >= last)
717 /* R was OK, so provisionally add it to MASK. We return 0 in any
718 case if the rest of the instruction has a flaw. */
719 last = REGNO (SET_SRC (elt));
722 /* Check that M has the form (plus (sp) (const_int -I*4)) */
723 elt = XEXP (SET_DEST (elt), 0);
724 if (GET_CODE (elt) != PLUS
725 || GET_CODE (XEXP (elt, 0)) != REG
726 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
727 || GET_CODE (XEXP (elt, 1)) != CONST_INT
728 || INTVAL (XEXP (elt, 1)) != -i * 4)
732 /* All or none of the callee-saved extended registers must be in the set. */
733 if ((mask & 0x3c000) != 0
734 && (mask & 0x3c000) != 0x3c000)
740 /* Return true if OP is a valid call operand. */
743 call_address_operand (op, mode)
745 enum machine_mode mode ATTRIBUTE_UNUSED;
747 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
750 /* What (if any) secondary registers are needed to move IN with mode
751 MODE into a register in register class CLASS.
753 We might be able to simplify this. */
755 secondary_reload_class (class, mode, in)
756 enum reg_class class;
757 enum machine_mode mode;
760 /* Memory loads less than a full word wide can't have an
761 address or stack pointer destination. They must use
762 a data register as an intermediate register. */
763 if ((GET_CODE (in) == MEM
764 || (GET_CODE (in) == REG
765 && REGNO (in) >= FIRST_PSEUDO_REGISTER)
766 || (GET_CODE (in) == SUBREG
767 && GET_CODE (SUBREG_REG (in)) == REG
768 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
769 && (mode == QImode || mode == HImode)
770 && (class == ADDRESS_REGS || class == SP_REGS
771 || class == SP_OR_ADDRESS_REGS))
774 return DATA_OR_EXTENDED_REGS;
778 /* We can't directly load sp + const_int into a data register;
779 we must use an address register as an intermediate. */
781 && class != ADDRESS_REGS
782 && class != SP_OR_ADDRESS_REGS
783 && class != SP_OR_EXTENDED_REGS
784 && class != ADDRESS_OR_EXTENDED_REGS
785 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
786 && (in == stack_pointer_rtx
787 || (GET_CODE (in) == PLUS
788 && (XEXP (in, 0) == stack_pointer_rtx
789 || XEXP (in, 1) == stack_pointer_rtx))))
792 if (GET_CODE (in) == PLUS
793 && (XEXP (in, 0) == stack_pointer_rtx
794 || XEXP (in, 1) == stack_pointer_rtx))
797 return DATA_OR_EXTENDED_REGS;
801 /* Otherwise assume no secondary reloads are needed. */
806 initial_offset (from, to)
809 /* The difference between the argument pointer and the frame pointer
810 is the size of the callee register save area. */
811 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
813 if (regs_ever_live[2] || regs_ever_live[3]
814 || regs_ever_live[6] || regs_ever_live[7]
815 || regs_ever_live[14] || regs_ever_live[15]
816 || regs_ever_live[16] || regs_ever_live[17]
817 || frame_pointer_needed)
818 return REG_SAVE_BYTES;
823 /* The difference between the argument pointer and the stack pointer is
824 the sum of the size of this function's frame, the callee register save
825 area, and the fixed stack space needed for function calls (if any). */
826 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
828 if (regs_ever_live[2] || regs_ever_live[3]
829 || regs_ever_live[6] || regs_ever_live[7]
830 || regs_ever_live[14] || regs_ever_live[15]
831 || regs_ever_live[16] || regs_ever_live[17]
832 || frame_pointer_needed)
833 return (get_frame_size () + REG_SAVE_BYTES
834 + (current_function_outgoing_args_size
835 ? current_function_outgoing_args_size + 4 : 0));
837 return (get_frame_size ()
838 + (current_function_outgoing_args_size
839 ? current_function_outgoing_args_size + 4 : 0));
842 /* The difference between the frame pointer and stack pointer is the sum
843 of the size of this function's frame and the fixed stack space needed
844 for function calls (if any). */
845 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
846 return (get_frame_size ()
847 + (current_function_outgoing_args_size
848 ? current_function_outgoing_args_size + 4 : 0));
853 /* Flush the argument registers to the stack for a stdarg function;
854 return the new argument pointer. */
856 mn10300_builtin_saveregs ()
859 tree fntype = TREE_TYPE (current_function_decl);
860 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
861 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
863 ? UNITS_PER_WORD : 0);
864 int set = get_varargs_alias_set ();
867 offset = plus_constant (current_function_arg_offset_rtx, argadj);
869 offset = current_function_arg_offset_rtx;
871 mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
872 MEM_ALIAS_SET (mem) = set;
873 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
875 mem = gen_rtx_MEM (SImode,
876 plus_constant (current_function_internal_arg_pointer, 4));
877 MEM_ALIAS_SET (mem) = set;
878 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
880 return copy_to_reg (expand_binop (Pmode, add_optab,
881 current_function_internal_arg_pointer,
882 offset, 0, 0, OPTAB_LIB_WIDEN));
886 mn10300_va_start (stdarg_p, valist, nextarg)
892 nextarg = expand_builtin_saveregs ();
894 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
898 mn10300_va_arg (valist, type)
901 HOST_WIDE_INT align, rsize;
904 /* Compute the rounded size of the type. */
905 align = PARM_BOUNDARY / BITS_PER_UNIT;
906 rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
908 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
909 build_int_2 ((rsize > 8 ? 4 : rsize), 0));
910 TREE_SIDE_EFFECTS (t) = 1;
912 ptr = build_pointer_type (type);
914 /* "Large" types are passed by reference. */
917 pptr = build_pointer_type (ptr);
918 t = build1 (NOP_EXPR, pptr, t);
919 TREE_SIDE_EFFECTS (t) = 1;
921 t = build1 (INDIRECT_REF, ptr, t);
922 TREE_SIDE_EFFECTS (t) = 1;
926 t = build1 (NOP_EXPR, ptr, t);
927 TREE_SIDE_EFFECTS (t) = 1;
931 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
934 /* Return an RTX to represent where a value with mode MODE will be returned
935 from a function. If the result is 0, the argument is pushed. */
938 function_arg (cum, mode, type, named)
939 CUMULATIVE_ARGS *cum;
940 enum machine_mode mode;
942 int named ATTRIBUTE_UNUSED;
947 /* We only support using 2 data registers as argument registers. */
950 /* Figure out the size of the object to be passed. */
952 size = int_size_in_bytes (type);
954 size = GET_MODE_SIZE (mode);
956 /* Figure out the alignment of the object to be passed. */
959 cum->nbytes = (cum->nbytes + 3) & ~3;
961 /* Don't pass this arg via a register if all the argument registers
963 if (cum->nbytes > nregs * UNITS_PER_WORD)
966 /* Don't pass this arg via a register if it would be split between
967 registers and memory. */
968 if (type == NULL_TREE
969 && cum->nbytes + size > nregs * UNITS_PER_WORD)
972 switch (cum->nbytes / UNITS_PER_WORD)
975 result = gen_rtx_REG (mode, 0);
978 result = gen_rtx_REG (mode, 1);
987 /* Return the number of registers to use for an argument passed partially
988 in registers and partially in memory. */
991 function_arg_partial_nregs (cum, mode, type, named)
992 CUMULATIVE_ARGS *cum;
993 enum machine_mode mode;
995 int named ATTRIBUTE_UNUSED;
999 /* We only support using 2 data registers as argument registers. */
1002 /* Figure out the size of the object to be passed. */
1003 if (mode == BLKmode)
1004 size = int_size_in_bytes (type);
1006 size = GET_MODE_SIZE (mode);
1008 /* Figure out the alignment of the object to be passed. */
1011 cum->nbytes = (cum->nbytes + 3) & ~3;
1013 /* Don't pass this arg via a register if all the argument registers
1015 if (cum->nbytes > nregs * UNITS_PER_WORD)
1018 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1021 /* Don't pass this arg via a register if it would be split between
1022 registers and memory. */
1023 if (type == NULL_TREE
1024 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1027 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1030 /* Output a tst insn. */
1032 output_tst (operand, insn)
1038 /* We can save a byte if we can find a register which has the value
1040 temp = PREV_INSN (insn);
1041 while (optimize && temp)
1045 /* We allow the search to go through call insns. We record
1046 the fact that we've past a CALL_INSN and reject matches which
1047 use call clobbered registers. */
1048 if (GET_CODE (temp) == CODE_LABEL
1049 || GET_CODE (temp) == JUMP_INSN
1050 || GET_CODE (temp) == BARRIER)
1053 if (GET_CODE (temp) == CALL_INSN)
1056 if (GET_CODE (temp) == NOTE)
1058 temp = PREV_INSN (temp);
1062 /* It must be an insn, see if it is a simple set. */
1063 set = single_set (temp);
1066 temp = PREV_INSN (temp);
1070 /* Are we setting a data register to zero (this does not win for
1073 If it's a call clobbered register, have we past a call?
1075 Make sure the register we find isn't the same as ourself;
1076 the mn10300 can't encode that.
1078 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1079 so the code to detect calls here isn't doing anything useful. */
1080 if (REG_P (SET_DEST (set))
1081 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1082 && !reg_set_between_p (SET_DEST (set), temp, insn)
1083 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1084 == REGNO_REG_CLASS (REGNO (operand)))
1085 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1086 && REGNO (SET_DEST (set)) != REGNO (operand)
1088 || !call_used_regs[REGNO (SET_DEST (set))]))
1091 xoperands[0] = operand;
1092 xoperands[1] = SET_DEST (set);
1094 output_asm_insn ("cmp %1,%0", xoperands);
1098 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1099 && REG_P (SET_DEST (set))
1100 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1101 && !reg_set_between_p (SET_DEST (set), temp, insn)
1102 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1103 != REGNO_REG_CLASS (REGNO (operand)))
1104 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1105 && REGNO (SET_DEST (set)) != REGNO (operand)
1107 || !call_used_regs[REGNO (SET_DEST (set))]))
1110 xoperands[0] = operand;
1111 xoperands[1] = SET_DEST (set);
1113 output_asm_insn ("cmp %1,%0", xoperands);
1116 temp = PREV_INSN (temp);
1122 impossible_plus_operand (op, mode)
1124 enum machine_mode mode ATTRIBUTE_UNUSED;
1126 if (GET_CODE (op) != PLUS)
1129 if (XEXP (op, 0) == stack_pointer_rtx
1130 || XEXP (op, 1) == stack_pointer_rtx)
1136 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1137 for the btst insn which may examine memory or a register (the memory
1138 variant only allows an unsigned 8 bit integer). */
1140 const_8bit_operand (op, mode)
1142 enum machine_mode mode ATTRIBUTE_UNUSED;
1144 return (GET_CODE (op) == CONST_INT
1146 && INTVAL (op) < 256);
1149 /* Similarly, but when using a zero_extract pattern for a btst where
1150 the source operand might end up in memory. */
1152 mask_ok_for_mem_btst (len, bit)
1165 /* MASK must bit into an 8bit value. */
1166 return (((mask & 0xff) == mask)
1167 || ((mask & 0xff00) == mask)
1168 || ((mask & 0xff0000) == mask)
1169 || ((mask & 0xff000000) == mask));
1172 /* Return 1 if X contains a symbolic expression. We know these
1173 expressions will have one of a few well defined forms, so
1174 we need only check those forms. */
1176 symbolic_operand (op, mode)
1178 enum machine_mode mode ATTRIBUTE_UNUSED;
1180 switch (GET_CODE (op))
1187 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1188 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1189 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1195 /* Try machine dependent ways of modifying an illegitimate address
1196 to be legitimate. If we find one, return the new valid address.
1197 This macro is used in only one place: `memory_address' in explow.c.
1199 OLDX is the address as it was before break_out_memory_refs was called.
1200 In some cases it is useful to look at this to decide what needs to be done.
1202 MODE and WIN are passed so that this macro can use
1203 GO_IF_LEGITIMATE_ADDRESS.
1205 Normally it is always safe for this macro to do nothing. It exists to
1206 recognize opportunities to optimize the output.
1208 But on a few ports with segmented architectures and indexed addressing
1209 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1211 legitimize_address (x, oldx, mode)
1213 rtx oldx ATTRIBUTE_UNUSED;
1214 enum machine_mode mode ATTRIBUTE_UNUSED;
1216 /* Uh-oh. We might have an address for x[n-100000]. This needs
1217 special handling to avoid creating an indexed memory address
1218 with x-100000 as the base. */
1219 if (GET_CODE (x) == PLUS
1220 && symbolic_operand (XEXP (x, 1), VOIDmode))
1222 /* Ugly. We modify things here so that the address offset specified
1223 by the index expression is computed first, then added to x to form
1224 the entire address. */
1226 rtx regx1, regy1, regy2, y;
1228 /* Strip off any CONST. */
1230 if (GET_CODE (y) == CONST)
1233 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1235 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1236 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1237 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1238 regx1 = force_reg (Pmode,
1239 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1240 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1247 mn10300_address_cost (x, unsig)
1255 switch (GET_CODE (x))
1258 switch (REGNO_REG_CLASS (REGNO (x)))
1283 return (mn10300_address_cost (XEXP (x, 0), unsig)
1284 + mn10300_address_cost (XEXP (x, 1), unsig));
1289 return ADDRESS_COST (XEXP (x, 0));
1293 return mn10300_address_cost (XEXP (x, 0), unsig);
1296 if (INTVAL (x) == 0)
1298 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1300 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1302 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1312 switch (GET_CODE (XEXP (x, 0)))
1315 return ADDRESS_COST (XEXP (x, 0));