1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
45 #include "target-def.h"
47 /* The size of the callee register save area. Right now we save everything
48 on entry since it costs us nothing in code size. It does cost us from a
49 speed standpoint, so we want to optimize this sooner or later. */
50 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
51 + 4 * regs_ever_live[3] \
52 + 4 * regs_ever_live[6] \
53 + 4 * regs_ever_live[7] \
54 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
55 || regs_ever_live[16] || regs_ever_live[17]))
58 static int mn10300_address_cost_1 PARAMS ((rtx, int *));
59 static int mn10300_address_cost PARAMS ((rtx));
60 static bool mn10300_rtx_costs PARAMS ((rtx, int, int, int *));
61 static void mn10300_file_start PARAMS ((void));
64 /* Initialize the GCC target structure. */
65 #undef TARGET_ASM_ALIGNED_HI_OP
66 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
68 #undef TARGET_RTX_COSTS
69 #define TARGET_RTX_COSTS mn10300_rtx_costs
70 #undef TARGET_ADDRESS_COST
71 #define TARGET_ADDRESS_COST mn10300_address_cost
73 #undef TARGET_ASM_FILE_START
74 #define TARGET_ASM_FILE_START mn10300_file_start
75 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
76 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
78 struct gcc_target targetm = TARGET_INITIALIZER;
83 default_file_start ();
86 fprintf (asm_out_file, "\t.am33_2\n");
88 fprintf (asm_out_file, "\t.am33\n");
92 /* Print operand X using operand code CODE to assembly language output file
96 print_operand (file, x, code)
105 if (cc_status.mdep.fpCC)
107 switch (code == 'b' ? GET_CODE (x)
108 : reverse_condition_maybe_unordered (GET_CODE (x)))
111 fprintf (file, "ne");
114 fprintf (file, "eq");
117 fprintf (file, "ge");
120 fprintf (file, "gt");
123 fprintf (file, "le");
126 fprintf (file, "lt");
129 fprintf (file, "lge");
132 fprintf (file, "uo");
135 fprintf (file, "lg");
138 fprintf (file, "ue");
141 fprintf (file, "uge");
144 fprintf (file, "ug");
147 fprintf (file, "ule");
150 fprintf (file, "ul");
157 /* These are normal and reversed branches. */
158 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
161 fprintf (file, "ne");
164 fprintf (file, "eq");
167 fprintf (file, "ge");
170 fprintf (file, "gt");
173 fprintf (file, "le");
176 fprintf (file, "lt");
179 fprintf (file, "cc");
182 fprintf (file, "hi");
185 fprintf (file, "ls");
188 fprintf (file, "cs");
195 /* This is used for the operand to a call instruction;
196 if it's a REG, enclose it in parens, else output
197 the operand normally. */
198 if (GET_CODE (x) == REG)
201 print_operand (file, x, 0);
205 print_operand (file, x, 0);
209 switch (GET_CODE (x))
213 output_address (XEXP (x, 0));
218 fprintf (file, "fd%d", REGNO (x) - 18);
226 /* These are the least significant word in a 64bit value. */
228 switch (GET_CODE (x))
232 output_address (XEXP (x, 0));
237 fprintf (file, "%s", reg_names[REGNO (x)]);
241 fprintf (file, "%s", reg_names[subreg_regno (x)]);
249 switch (GET_MODE (x))
252 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
253 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
254 fprintf (file, "0x%lx", val[0]);
257 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
258 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
259 fprintf (file, "0x%lx", val[0]);
263 print_operand_address (file,
264 GEN_INT (CONST_DOUBLE_LOW (x)));
275 split_double (x, &low, &high);
276 fprintf (file, "%ld", (long)INTVAL (low));
285 /* Similarly, but for the most significant word. */
287 switch (GET_CODE (x))
291 x = adjust_address (x, SImode, 4);
292 output_address (XEXP (x, 0));
297 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
301 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
309 switch (GET_MODE (x))
312 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
313 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
314 fprintf (file, "0x%lx", val[1]);
320 print_operand_address (file,
321 GEN_INT (CONST_DOUBLE_HIGH (x)));
332 split_double (x, &low, &high);
333 fprintf (file, "%ld", (long)INTVAL (high));
344 if (GET_CODE (XEXP (x, 0)) == REG)
345 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
347 output_address (XEXP (x, 0));
352 if (INTVAL (x) < -128 || INTVAL (x) > 255)
354 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
358 if (INTVAL (x) < -128 || INTVAL (x) > 255)
360 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
363 /* For shift counts. The hardware ignores the upper bits of
364 any immediate, but the assembler will flag an out of range
365 shift count as an error. So we mask off the high bits
366 of the immediate here. */
368 if (GET_CODE (x) == CONST_INT)
370 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
376 switch (GET_CODE (x))
380 output_address (XEXP (x, 0));
389 fprintf (file, "%s", reg_names[REGNO (x)]);
393 fprintf (file, "%s", reg_names[subreg_regno (x)]);
396 /* This will only be single precision.... */
402 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
403 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
404 fprintf (file, "0x%lx", val);
413 print_operand_address (file, x);
422 /* Output assembly language output for the address ADDR to FILE. */
425 print_operand_address (file, addr)
429 switch (GET_CODE (addr))
432 print_operand_address (file, XEXP (addr, 0));
436 print_operand (file, addr, 0);
441 if (REG_P (XEXP (addr, 0))
442 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
443 base = XEXP (addr, 0), index = XEXP (addr, 1);
444 else if (REG_P (XEXP (addr, 1))
445 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
446 base = XEXP (addr, 1), index = XEXP (addr, 0);
449 print_operand (file, index, 0);
451 print_operand (file, base, 0);;
455 output_addr_const (file, addr);
458 output_addr_const (file, addr);
463 /* Count the number of FP registers that have to be saved. */
472 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
473 if (regs_ever_live[i] && ! call_used_regs[i])
479 /* Print a set of registers in the format required by "movm" and "ret".
480 Register K is saved if bit K of MASK is set. The data and address
481 registers can be stored individually, but the extended registers cannot.
482 We assume that the mask alread takes that into account. For instance,
483 bits 14 to 17 must have the same value. */
486 mn10300_print_reg_list (file, mask)
496 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
497 if ((mask & (1 << i)) != 0)
501 fputs (reg_names [i], file);
505 if ((mask & 0x3c000) != 0)
507 if ((mask & 0x3c000) != 0x3c000)
511 fputs ("exreg1", file);
519 can_use_return_insn ()
521 /* size includes the fixed stack space needed for function calls. */
522 int size = get_frame_size () + current_function_outgoing_args_size;
524 /* And space for the return pointer. */
525 size += current_function_outgoing_args_size ? 4 : 0;
527 return (reload_completed
529 && !regs_ever_live[2]
530 && !regs_ever_live[3]
531 && !regs_ever_live[6]
532 && !regs_ever_live[7]
533 && !regs_ever_live[14]
534 && !regs_ever_live[15]
535 && !regs_ever_live[16]
536 && !regs_ever_live[17]
537 && fp_regs_to_save () == 0
538 && !frame_pointer_needed);
541 /* Returns the set of live, callee-saved registers as a bitmask. The
542 callee-saved extended registers cannot be stored individually, so
543 all of them will be included in the mask if any one of them is used. */
546 mn10300_get_live_callee_saved_regs ()
552 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
553 if (regs_ever_live[i] && ! call_used_regs[i])
555 if ((mask & 0x3c000) != 0)
561 /* Generate an instruction that pushes several registers onto the stack.
562 Register K will be saved if bit K in MASK is set. The function does
563 nothing if MASK is zero.
565 To be compatible with the "movm" instruction, the lowest-numbered
566 register must be stored in the lowest slot. If MASK is the set
567 { R1,...,RN }, where R1...RN are ordered least first, the generated
568 instruction will have the form:
571 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
572 (set (mem:SI (plus:SI (reg:SI 9)
576 (set (mem:SI (plus:SI (reg:SI 9)
581 mn10300_gen_multiple_store (mask)
591 /* Count how many registers need to be saved. */
593 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
594 if ((mask & (1 << i)) != 0)
597 /* We need one PARALLEL element to update the stack pointer and
598 an additional element for each register that is stored. */
599 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
601 /* Create the instruction that updates the stack pointer. */
603 = gen_rtx_SET (SImode,
605 gen_rtx_PLUS (SImode,
607 GEN_INT (-count * 4)));
609 /* Create each store. */
611 for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
612 if ((mask & (1 << i)) != 0)
614 rtx address = gen_rtx_PLUS (SImode,
616 GEN_INT (-pari * 4));
617 XVECEXP(par, 0, pari)
618 = gen_rtx_SET (VOIDmode,
619 gen_rtx_MEM (SImode, address),
620 gen_rtx_REG (SImode, i));
624 par = emit_insn (par);
625 RTX_FRAME_RELATED_P (par) = 1;
634 /* SIZE includes the fixed stack space needed for function calls. */
635 size = get_frame_size () + current_function_outgoing_args_size;
636 size += (current_function_outgoing_args_size ? 4 : 0);
638 /* If we use any of the callee-saved registers, save them now. */
639 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
641 if (TARGET_AM33_2 && fp_regs_to_save ())
643 int num_regs_to_save = fp_regs_to_save (), i;
645 enum { save_sp_merge,
647 save_sp_partial_merge,
649 save_a0_no_merge } strategy;
650 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
654 /* We have several different strategies to save FP registers.
655 We can store them using SP offsets, which is beneficial if
656 there are just a few registers to save, or we can use `a0' in
657 post-increment mode (`a0' is the only call-clobbered address
658 register that is never used to pass information to a
659 function). Furthermore, if we don't need a frame pointer, we
660 can merge the two SP adds into a single one, but this isn't
661 always beneficial; sometimes we can just split the two adds
662 so that we don't exceed a 16-bit constant size. The code
663 below will select which strategy to use, so as to generate
664 smallest code. Ties are broken in favor or shorter sequences
665 (in terms of number of instructions). */
667 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
668 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
669 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
670 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
671 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
672 (((S) >= (L)) ? (SIZE1) * (N) \
673 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
674 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
676 #define SIZE_FMOV_SP_(S,N) \
677 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
678 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
679 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
680 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
682 /* Consider alternative save_sp_merge only if we don't need the
683 frame pointer and size is non-zero. */
684 if (! frame_pointer_needed && size)
686 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
687 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
688 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
689 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
691 if (this_strategy_size < strategy_size)
693 strategy = save_sp_merge;
694 strategy_size = this_strategy_size;
698 /* Consider alternative save_sp_no_merge unconditionally. */
699 /* Insn: add -4 * num_regs_to_save, sp. */
700 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
701 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
702 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
705 /* Insn: add -size, sp. */
706 this_strategy_size += SIZE_ADD_SP (-size);
709 if (this_strategy_size < strategy_size)
711 strategy = save_sp_no_merge;
712 strategy_size = this_strategy_size;
715 /* Consider alternative save_sp_partial_merge only if we don't
716 need a frame pointer and size is reasonably large. */
717 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
719 /* Insn: add -128, sp. */
720 this_strategy_size = SIZE_ADD_SP (-128);
721 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
722 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
726 /* Insn: add 128-size, sp. */
727 this_strategy_size += SIZE_ADD_SP (128 - size);
730 if (this_strategy_size < strategy_size)
732 strategy = save_sp_partial_merge;
733 strategy_size = this_strategy_size;
737 /* Consider alternative save_a0_merge only if we don't need a
738 frame pointer, size is non-zero and the user hasn't
739 changed the calling conventions of a0. */
740 if (! frame_pointer_needed && size
741 && call_used_regs[FIRST_ADDRESS_REGNUM]
742 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
744 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
745 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
746 /* Insn: mov sp, a0. */
747 this_strategy_size++;
750 /* Insn: add size, a0. */
751 this_strategy_size += SIZE_ADD_AX (size);
753 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
754 this_strategy_size += 3 * num_regs_to_save;
756 if (this_strategy_size < strategy_size)
758 strategy = save_a0_merge;
759 strategy_size = this_strategy_size;
763 /* Consider alternative save_a0_no_merge if the user hasn't
764 changed the calling conventions of a0. */
765 if (call_used_regs[FIRST_ADDRESS_REGNUM]
766 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
768 /* Insn: add -4 * num_regs_to_save, sp. */
769 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
770 /* Insn: mov sp, a0. */
771 this_strategy_size++;
772 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
773 this_strategy_size += 3 * num_regs_to_save;
776 /* Insn: add -size, sp. */
777 this_strategy_size += SIZE_ADD_SP (-size);
780 if (this_strategy_size < strategy_size)
782 strategy = save_a0_no_merge;
783 strategy_size = this_strategy_size;
787 /* Emit the initial SP add, common to all strategies. */
790 case save_sp_no_merge:
791 case save_a0_no_merge:
792 emit_insn (gen_addsi3 (stack_pointer_rtx,
794 GEN_INT (-4 * num_regs_to_save)));
798 case save_sp_partial_merge:
799 emit_insn (gen_addsi3 (stack_pointer_rtx,
802 xsize = 128 - 4 * num_regs_to_save;
808 emit_insn (gen_addsi3 (stack_pointer_rtx,
810 GEN_INT (-(size + 4 * num_regs_to_save))));
811 /* We'll have to adjust FP register saves according to the
814 /* Since we've already created the stack frame, don't do it
815 again at the end of the function. */
823 /* Now prepare register a0, if we have decided to use it. */
827 case save_sp_no_merge:
828 case save_sp_partial_merge:
833 case save_a0_no_merge:
834 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
835 emit_insn (gen_movsi (reg, stack_pointer_rtx));
837 emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
838 reg = gen_rtx_POST_INC (SImode, reg);
845 /* Now actually save the FP registers. */
846 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
847 if (regs_ever_live[i] && ! call_used_regs[i])
855 /* If we aren't using `a0', use an SP offset. */
858 addr = gen_rtx_PLUS (SImode,
863 addr = stack_pointer_rtx;
868 insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
869 gen_rtx_REG (SImode, i)));
871 RTX_FRAME_RELATED_P (insn) = 1;
875 /* Now put the frame pointer into the frame pointer register. */
876 if (frame_pointer_needed)
877 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
879 /* Allocate stack for this frame. */
881 emit_insn (gen_addsi3 (stack_pointer_rtx,
891 /* SIZE includes the fixed stack space needed for function calls. */
892 size = get_frame_size () + current_function_outgoing_args_size;
893 size += (current_function_outgoing_args_size ? 4 : 0);
895 if (TARGET_AM33_2 && fp_regs_to_save ())
897 int num_regs_to_save = fp_regs_to_save (), i;
900 /* We have several options to restore FP registers. We could
901 load them from SP offsets, but, if there are enough FP
902 registers to restore, we win if we use a post-increment
905 /* If we have a frame pointer, it's the best option, because we
906 already know it has the value we want. */
907 if (frame_pointer_needed)
908 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
909 /* Otherwise, we may use `a1', since it's call-clobbered and
910 it's never used for return values. But only do so if it's
911 smaller than using SP offsets. */
914 enum { restore_sp_post_adjust,
915 restore_sp_pre_adjust,
916 restore_sp_partial_adjust,
917 restore_a1 } strategy;
918 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
920 /* Consider using sp offsets before adjusting sp. */
921 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
922 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
923 /* If size is too large, we'll have to adjust SP with an
925 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
927 /* Insn: add size + 4 * num_regs_to_save, sp. */
928 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
930 /* If we don't have to restore any non-FP registers,
931 we'll be able to save one byte by using rets. */
932 if (! REG_SAVE_BYTES)
933 this_strategy_size--;
935 if (this_strategy_size < strategy_size)
937 strategy = restore_sp_post_adjust;
938 strategy_size = this_strategy_size;
941 /* Consider using sp offsets after adjusting sp. */
942 /* Insn: add size, sp. */
943 this_strategy_size = SIZE_ADD_SP (size);
944 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
945 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
946 /* We're going to use ret to release the FP registers
947 save area, so, no savings. */
949 if (this_strategy_size < strategy_size)
951 strategy = restore_sp_pre_adjust;
952 strategy_size = this_strategy_size;
955 /* Consider using sp offsets after partially adjusting sp.
956 When size is close to 32Kb, we may be able to adjust SP
957 with an imm16 add instruction while still using fmov
959 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
961 /* Insn: add size + 4 * num_regs_to_save
962 + REG_SAVE_BYTES - 252,sp. */
963 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
964 + REG_SAVE_BYTES - 252);
965 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
966 this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
967 - 4 * num_regs_to_save,
969 /* We're going to use ret to release the FP registers
970 save area, so, no savings. */
972 if (this_strategy_size < strategy_size)
974 strategy = restore_sp_partial_adjust;
975 strategy_size = this_strategy_size;
979 /* Consider using a1 in post-increment mode, as long as the
980 user hasn't changed the calling conventions of a1. */
981 if (call_used_regs[FIRST_ADDRESS_REGNUM+1]
982 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
984 /* Insn: mov sp,a1. */
985 this_strategy_size = 1;
988 /* Insn: add size,a1. */
989 this_strategy_size += SIZE_ADD_AX (size);
991 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
992 this_strategy_size += 3 * num_regs_to_save;
993 /* If size is large enough, we may be able to save a
995 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
997 /* Insn: mov a1,sp. */
998 this_strategy_size += 2;
1000 /* If we don't have to restore any non-FP registers,
1001 we'll be able to save one byte by using rets. */
1002 if (! REG_SAVE_BYTES)
1003 this_strategy_size--;
1005 if (this_strategy_size < strategy_size)
1007 strategy = restore_a1;
1008 strategy_size = this_strategy_size;
1014 case restore_sp_post_adjust:
1017 case restore_sp_pre_adjust:
1018 emit_insn (gen_addsi3 (stack_pointer_rtx,
1024 case restore_sp_partial_adjust:
1025 emit_insn (gen_addsi3 (stack_pointer_rtx,
1027 GEN_INT (size + 4 * num_regs_to_save
1028 + REG_SAVE_BYTES - 252)));
1029 size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1033 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1034 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1036 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1044 /* Adjust the selected register, if any, for post-increment. */
1046 reg = gen_rtx_POST_INC (SImode, reg);
1048 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1049 if (regs_ever_live[i] && ! call_used_regs[i])
1057 /* If we aren't using a post-increment register, use an
1059 addr = gen_rtx_PLUS (SImode,
1064 addr = stack_pointer_rtx;
1068 emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
1069 gen_rtx_MEM (SImode, addr)));
1072 /* If we were using the restore_a1 strategy and the number of
1073 bytes to be released won't fit in the `ret' byte, copy `a1'
1074 to `sp', to avoid having to use `add' to adjust it. */
1075 if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1077 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1082 /* Maybe cut back the stack, except for the register save area.
1084 If the frame pointer exists, then use the frame pointer to
1087 If the stack size + register save area is more than 255 bytes,
1088 then the stack must be cut back here since the size + register
1089 save size is too big for a ret/retf instruction.
1091 Else leave it alone, it will be cut back as part of the
1092 ret/retf instruction, or there wasn't any stack to begin with.
1094 Under no circumstances should the register save area be
1095 deallocated here, that would leave a window where an interrupt
1096 could occur and trash the register save area. */
1097 if (frame_pointer_needed)
1099 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1102 else if (size + REG_SAVE_BYTES > 255)
1104 emit_insn (gen_addsi3 (stack_pointer_rtx,
1110 /* Adjust the stack and restore callee-saved registers, if any. */
1111 if (size || regs_ever_live[2] || regs_ever_live[3]
1112 || regs_ever_live[6] || regs_ever_live[7]
1113 || regs_ever_live[14] || regs_ever_live[15]
1114 || regs_ever_live[16] || regs_ever_live[17]
1115 || frame_pointer_needed)
1116 emit_jump_insn (gen_return_internal_regs
1117 (GEN_INT (size + REG_SAVE_BYTES)));
1119 emit_jump_insn (gen_return_internal ());
1122 /* Update the condition code from the insn. */
1125 notice_update_cc (body, insn)
1129 switch (get_attr_cc (insn))
1132 /* Insn does not affect CC at all. */
1136 /* Insn does not change CC, but the 0'th operand has been changed. */
1137 if (cc_status.value1 != 0
1138 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1139 cc_status.value1 = 0;
1143 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1144 V,C are unusable. */
1146 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
1147 cc_status.value1 = recog_data.operand[0];
1151 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1154 cc_status.flags |= CC_NO_CARRY;
1155 cc_status.value1 = recog_data.operand[0];
1159 /* The insn is a compare instruction. */
1161 cc_status.value1 = SET_SRC (body);
1162 if (GET_CODE (cc_status.value1) == COMPARE
1163 && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
1164 cc_status.mdep.fpCC = 1;
1168 /* The insn is a compare instruction. */
1170 cc_status.value1 = SET_SRC (body);
1171 cc_status.flags |= CC_INVERTED;
1175 /* Insn doesn't leave CC in a usable state. */
1184 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1185 This function is for MATCH_PARALLEL and so assumes OP is known to be
1186 parallel. If OP is a multiple store, return a mask indicating which
1187 registers it saves. Return 0 otherwise. */
1190 store_multiple_operation (op, mode)
1192 enum machine_mode mode ATTRIBUTE_UNUSED;
1200 count = XVECLEN (op, 0);
1204 /* Check that first instruction has the form (set (sp) (plus A B)) */
1205 elt = XVECEXP (op, 0, 0);
1206 if (GET_CODE (elt) != SET
1207 || GET_CODE (SET_DEST (elt)) != REG
1208 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1209 || GET_CODE (SET_SRC (elt)) != PLUS)
1212 /* Check that A is the stack pointer and B is the expected stack size.
1213 For OP to match, each subsequent instruction should push a word onto
1214 the stack. We therefore expect the first instruction to create
1215 COUNT-1 stack slots. */
1216 elt = SET_SRC (elt);
1217 if (GET_CODE (XEXP (elt, 0)) != REG
1218 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1219 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1220 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1223 /* Now go through the rest of the vector elements. They must be
1224 ordered so that the first instruction stores the highest-numbered
1225 register to the highest stack slot and that subsequent instructions
1226 store a lower-numbered register to the slot below.
1228 LAST keeps track of the smallest-numbered register stored so far.
1229 MASK is the set of stored registers. */
1230 last = LAST_EXTENDED_REGNUM + 1;
1232 for (i = 1; i < count; i++)
1234 /* Check that element i is a (set (mem M) R) and that R is valid. */
1235 elt = XVECEXP (op, 0, i);
1236 if (GET_CODE (elt) != SET
1237 || GET_CODE (SET_DEST (elt)) != MEM
1238 || GET_CODE (SET_SRC (elt)) != REG
1239 || REGNO (SET_SRC (elt)) >= last)
1242 /* R was OK, so provisionally add it to MASK. We return 0 in any
1243 case if the rest of the instruction has a flaw. */
1244 last = REGNO (SET_SRC (elt));
1245 mask |= (1 << last);
1247 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1248 elt = XEXP (SET_DEST (elt), 0);
1249 if (GET_CODE (elt) != PLUS
1250 || GET_CODE (XEXP (elt, 0)) != REG
1251 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1252 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1253 || INTVAL (XEXP (elt, 1)) != -i * 4)
1257 /* All or none of the callee-saved extended registers must be in the set. */
1258 if ((mask & 0x3c000) != 0
1259 && (mask & 0x3c000) != 0x3c000)
1265 /* Return true if OP is a valid call operand. */
1268 call_address_operand (op, mode)
1270 enum machine_mode mode ATTRIBUTE_UNUSED;
1272 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
1275 /* What (if any) secondary registers are needed to move IN with mode
1276 MODE into a register in register class CLASS.
1278 We might be able to simplify this. */
1280 secondary_reload_class (class, mode, in)
1281 enum reg_class class;
1282 enum machine_mode mode;
1285 /* Memory loads less than a full word wide can't have an
1286 address or stack pointer destination. They must use
1287 a data register as an intermediate register. */
1288 if ((GET_CODE (in) == MEM
1289 || (GET_CODE (in) == REG
1290 && REGNO (in) >= FIRST_PSEUDO_REGISTER)
1291 || (GET_CODE (in) == SUBREG
1292 && GET_CODE (SUBREG_REG (in)) == REG
1293 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
1294 && (mode == QImode || mode == HImode)
1295 && (class == ADDRESS_REGS || class == SP_REGS
1296 || class == SP_OR_ADDRESS_REGS))
1299 return DATA_OR_EXTENDED_REGS;
1303 /* We can't directly load sp + const_int into a data register;
1304 we must use an address register as an intermediate. */
1305 if (class != SP_REGS
1306 && class != ADDRESS_REGS
1307 && class != SP_OR_ADDRESS_REGS
1308 && class != SP_OR_EXTENDED_REGS
1309 && class != ADDRESS_OR_EXTENDED_REGS
1310 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
1311 && (in == stack_pointer_rtx
1312 || (GET_CODE (in) == PLUS
1313 && (XEXP (in, 0) == stack_pointer_rtx
1314 || XEXP (in, 1) == stack_pointer_rtx))))
1315 return ADDRESS_REGS;
1317 if (GET_CODE (in) == PLUS
1318 && (XEXP (in, 0) == stack_pointer_rtx
1319 || XEXP (in, 1) == stack_pointer_rtx))
1322 return DATA_OR_EXTENDED_REGS;
1326 if (TARGET_AM33_2 && class == FP_REGS
1327 && GET_CODE (in) == MEM && ! OK_FOR_Q (in))
1330 return DATA_OR_EXTENDED_REGS;
1334 /* Otherwise assume no secondary reloads are needed. */
1339 initial_offset (from, to)
1342 /* The difference between the argument pointer and the frame pointer
1343 is the size of the callee register save area. */
1344 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1346 if (regs_ever_live[2] || regs_ever_live[3]
1347 || regs_ever_live[6] || regs_ever_live[7]
1348 || regs_ever_live[14] || regs_ever_live[15]
1349 || regs_ever_live[16] || regs_ever_live[17]
1350 || fp_regs_to_save ()
1351 || frame_pointer_needed)
1352 return REG_SAVE_BYTES
1353 + 4 * fp_regs_to_save ();
1358 /* The difference between the argument pointer and the stack pointer is
1359 the sum of the size of this function's frame, the callee register save
1360 area, and the fixed stack space needed for function calls (if any). */
1361 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1363 if (regs_ever_live[2] || regs_ever_live[3]
1364 || regs_ever_live[6] || regs_ever_live[7]
1365 || regs_ever_live[14] || regs_ever_live[15]
1366 || regs_ever_live[16] || regs_ever_live[17]
1367 || fp_regs_to_save ()
1368 || frame_pointer_needed)
1369 return (get_frame_size () + REG_SAVE_BYTES
1370 + 4 * fp_regs_to_save ()
1371 + (current_function_outgoing_args_size
1372 ? current_function_outgoing_args_size + 4 : 0));
1374 return (get_frame_size ()
1375 + (current_function_outgoing_args_size
1376 ? current_function_outgoing_args_size + 4 : 0));
1379 /* The difference between the frame pointer and stack pointer is the sum
1380 of the size of this function's frame and the fixed stack space needed
1381 for function calls (if any). */
1382 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1383 return (get_frame_size ()
1384 + (current_function_outgoing_args_size
1385 ? current_function_outgoing_args_size + 4 : 0));
1390 /* Flush the argument registers to the stack for a stdarg function;
1391 return the new argument pointer. */
1393 mn10300_builtin_saveregs ()
1396 tree fntype = TREE_TYPE (current_function_decl);
1397 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
1398 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1399 != void_type_node)))
1400 ? UNITS_PER_WORD : 0);
1401 int set = get_varargs_alias_set ();
1404 offset = plus_constant (current_function_arg_offset_rtx, argadj);
1406 offset = current_function_arg_offset_rtx;
1408 mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
1409 set_mem_alias_set (mem, set);
1410 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1412 mem = gen_rtx_MEM (SImode,
1413 plus_constant (current_function_internal_arg_pointer, 4));
1414 set_mem_alias_set (mem, set);
1415 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1417 return copy_to_reg (expand_binop (Pmode, add_optab,
1418 current_function_internal_arg_pointer,
1419 offset, 0, 0, OPTAB_LIB_WIDEN));
1423 mn10300_va_start (valist, nextarg)
1427 nextarg = expand_builtin_saveregs ();
1428 std_expand_builtin_va_start (valist, nextarg);
1432 mn10300_va_arg (valist, type)
1435 HOST_WIDE_INT align, rsize;
1438 /* Compute the rounded size of the type. */
1439 align = PARM_BOUNDARY / BITS_PER_UNIT;
1440 rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
1442 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
1443 build_int_2 ((rsize > 8 ? 4 : rsize), 0));
1444 TREE_SIDE_EFFECTS (t) = 1;
1446 ptr = build_pointer_type (type);
1448 /* "Large" types are passed by reference. */
1451 pptr = build_pointer_type (ptr);
1452 t = build1 (NOP_EXPR, pptr, t);
1453 TREE_SIDE_EFFECTS (t) = 1;
1455 t = build1 (INDIRECT_REF, ptr, t);
1456 TREE_SIDE_EFFECTS (t) = 1;
1460 t = build1 (NOP_EXPR, ptr, t);
1461 TREE_SIDE_EFFECTS (t) = 1;
1465 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1468 /* Return an RTX to represent where a value with mode MODE will be returned
1469 from a function. If the result is 0, the argument is pushed. */
1472 function_arg (cum, mode, type, named)
1473 CUMULATIVE_ARGS *cum;
1474 enum machine_mode mode;
1476 int named ATTRIBUTE_UNUSED;
1481 /* We only support using 2 data registers as argument registers. */
1484 /* Figure out the size of the object to be passed. */
1485 if (mode == BLKmode)
1486 size = int_size_in_bytes (type);
1488 size = GET_MODE_SIZE (mode);
1490 /* Figure out the alignment of the object to be passed. */
1493 cum->nbytes = (cum->nbytes + 3) & ~3;
1495 /* Don't pass this arg via a register if all the argument registers
1497 if (cum->nbytes > nregs * UNITS_PER_WORD)
1500 /* Don't pass this arg via a register if it would be split between
1501 registers and memory. */
1502 if (type == NULL_TREE
1503 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1506 switch (cum->nbytes / UNITS_PER_WORD)
1509 result = gen_rtx_REG (mode, 0);
1512 result = gen_rtx_REG (mode, 1);
1521 /* Return the number of registers to use for an argument passed partially
1522 in registers and partially in memory. */
1525 function_arg_partial_nregs (cum, mode, type, named)
1526 CUMULATIVE_ARGS *cum;
1527 enum machine_mode mode;
1529 int named ATTRIBUTE_UNUSED;
1533 /* We only support using 2 data registers as argument registers. */
1536 /* Figure out the size of the object to be passed. */
1537 if (mode == BLKmode)
1538 size = int_size_in_bytes (type);
1540 size = GET_MODE_SIZE (mode);
1542 /* Figure out the alignment of the object to be passed. */
1545 cum->nbytes = (cum->nbytes + 3) & ~3;
1547 /* Don't pass this arg via a register if all the argument registers
1549 if (cum->nbytes > nregs * UNITS_PER_WORD)
1552 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1555 /* Don't pass this arg via a register if it would be split between
1556 registers and memory. */
1557 if (type == NULL_TREE
1558 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1561 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1564 /* Output a tst insn. */
1566 output_tst (operand, insn)
1572 /* We can save a byte if we can find a register which has the value
1574 temp = PREV_INSN (insn);
1575 while (optimize && temp)
1579 /* We allow the search to go through call insns. We record
1580 the fact that we've past a CALL_INSN and reject matches which
1581 use call clobbered registers. */
1582 if (GET_CODE (temp) == CODE_LABEL
1583 || GET_CODE (temp) == JUMP_INSN
1584 || GET_CODE (temp) == BARRIER)
1587 if (GET_CODE (temp) == CALL_INSN)
1590 if (GET_CODE (temp) == NOTE)
1592 temp = PREV_INSN (temp);
1596 /* It must be an insn, see if it is a simple set. */
1597 set = single_set (temp);
1600 temp = PREV_INSN (temp);
1604 /* Are we setting a data register to zero (this does not win for
1607 If it's a call clobbered register, have we past a call?
1609 Make sure the register we find isn't the same as ourself;
1610 the mn10300 can't encode that.
1612 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1613 so the code to detect calls here isn't doing anything useful. */
1614 if (REG_P (SET_DEST (set))
1615 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1616 && !reg_set_between_p (SET_DEST (set), temp, insn)
1617 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1618 == REGNO_REG_CLASS (REGNO (operand)))
1619 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1620 && REGNO (SET_DEST (set)) != REGNO (operand)
1622 || !call_used_regs[REGNO (SET_DEST (set))]))
1625 xoperands[0] = operand;
1626 xoperands[1] = SET_DEST (set);
1628 output_asm_insn ("cmp %1,%0", xoperands);
1632 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1633 && REG_P (SET_DEST (set))
1634 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1635 && !reg_set_between_p (SET_DEST (set), temp, insn)
1636 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1637 != REGNO_REG_CLASS (REGNO (operand)))
1638 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1639 && REGNO (SET_DEST (set)) != REGNO (operand)
1641 || !call_used_regs[REGNO (SET_DEST (set))]))
1644 xoperands[0] = operand;
1645 xoperands[1] = SET_DEST (set);
1647 output_asm_insn ("cmp %1,%0", xoperands);
1650 temp = PREV_INSN (temp);
1656 impossible_plus_operand (op, mode)
1658 enum machine_mode mode ATTRIBUTE_UNUSED;
1660 if (GET_CODE (op) != PLUS)
1663 if (XEXP (op, 0) == stack_pointer_rtx
1664 || XEXP (op, 1) == stack_pointer_rtx)
1670 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1671 for the btst insn which may examine memory or a register (the memory
1672 variant only allows an unsigned 8 bit integer). */
1674 const_8bit_operand (op, mode)
1676 enum machine_mode mode ATTRIBUTE_UNUSED;
1678 return (GET_CODE (op) == CONST_INT
1680 && INTVAL (op) < 256);
1683 /* Return true if the operand is the 1.0f constant. */
1685 const_1f_operand (op, mode)
1687 enum machine_mode mode ATTRIBUTE_UNUSED;
1689 return (op == CONST1_RTX (SFmode));
1692 /* Similarly, but when using a zero_extract pattern for a btst where
1693 the source operand might end up in memory. */
1695 mask_ok_for_mem_btst (len, bit)
1699 unsigned int mask = 0;
1708 /* MASK must bit into an 8bit value. */
1709 return (((mask & 0xff) == mask)
1710 || ((mask & 0xff00) == mask)
1711 || ((mask & 0xff0000) == mask)
1712 || ((mask & 0xff000000) == mask));
1715 /* Return 1 if X contains a symbolic expression. We know these
1716 expressions will have one of a few well defined forms, so
1717 we need only check those forms. */
1719 symbolic_operand (op, mode)
1721 enum machine_mode mode ATTRIBUTE_UNUSED;
1723 switch (GET_CODE (op))
1730 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1731 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1732 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1738 /* Try machine dependent ways of modifying an illegitimate address
1739 to be legitimate. If we find one, return the new valid address.
1740 This macro is used in only one place: `memory_address' in explow.c.
1742 OLDX is the address as it was before break_out_memory_refs was called.
1743 In some cases it is useful to look at this to decide what needs to be done.
1745 MODE and WIN are passed so that this macro can use
1746 GO_IF_LEGITIMATE_ADDRESS.
1748 Normally it is always safe for this macro to do nothing. It exists to
1749 recognize opportunities to optimize the output.
1751 But on a few ports with segmented architectures and indexed addressing
1752 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1754 legitimize_address (x, oldx, mode)
1756 rtx oldx ATTRIBUTE_UNUSED;
1757 enum machine_mode mode ATTRIBUTE_UNUSED;
1759 /* Uh-oh. We might have an address for x[n-100000]. This needs
1760 special handling to avoid creating an indexed memory address
1761 with x-100000 as the base. */
1762 if (GET_CODE (x) == PLUS
1763 && symbolic_operand (XEXP (x, 1), VOIDmode))
1765 /* Ugly. We modify things here so that the address offset specified
1766 by the index expression is computed first, then added to x to form
1767 the entire address. */
1769 rtx regx1, regy1, regy2, y;
1771 /* Strip off any CONST. */
1773 if (GET_CODE (y) == CONST)
1776 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1778 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1779 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1780 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1781 regx1 = force_reg (Pmode,
1782 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1783 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1790 mn10300_address_cost_1 (x, unsig)
1794 switch (GET_CODE (x))
1797 switch (REGNO_REG_CLASS (REGNO (x)))
1823 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
1824 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
1829 return mn10300_address_cost (XEXP (x, 0));
1833 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
1836 if (INTVAL (x) == 0)
1838 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1840 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1842 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1852 switch (GET_CODE (XEXP (x, 0)))
1855 return mn10300_address_cost (XEXP (x, 0));
1871 mn10300_address_cost (x)
1875 return mn10300_address_cost_1 (x, &s);
1879 mn10300_rtx_costs (x, code, outer_code, total)
1881 int code, outer_code;
1887 /* Zeros are extremely cheap. */
1888 if (INTVAL (x) == 0 && outer_code == SET)
1890 /* If it fits in 8 bits, then it's still relatively cheap. */
1891 else if (INT_8_BITS (INTVAL (x)))
1893 /* This is the "base" cost, includes constants where either the
1894 upper or lower 16bits are all zeros. */
1895 else if (INT_16_BITS (INTVAL (x))
1896 || (INTVAL (x) & 0xffff) == 0
1897 || (INTVAL (x) & 0xffff0000) == 0)
1906 /* These are more costly than a CONST_INT, but we can relax them,
1907 so they're less costly than a CONST_DOUBLE. */
1912 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
1913 so their cost is very high. */
1917 /* ??? This probably needs more work. */
1929 /* Check whether a constant used to initialize a DImode or DFmode can
1930 use a clr instruction. The code here must be kept in sync with
1934 mn10300_wide_const_load_uses_clr (operands)
1939 if (GET_CODE (operands[0]) != REG
1940 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
1943 switch (GET_CODE (operands[1]))
1948 split_double (operands[1], &low, &high);
1949 val[0] = INTVAL (low);
1950 val[1] = INTVAL (high);
1955 if (GET_MODE (operands[1]) == DFmode)
1959 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
1960 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
1962 else if (GET_MODE (operands[1]) == VOIDmode
1963 || GET_MODE (operands[1]) == DImode)
1965 val[0] = CONST_DOUBLE_LOW (operands[1]);
1966 val[1] = CONST_DOUBLE_HIGH (operands[1]);
1974 return val[0] == 0 || val[1] == 0;