1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
45 #include "target-def.h"
47 /* This is used by GOTaddr2picreg to uniquely identify
49 int mn10300_unspec_int_label_counter;
51 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
52 names are not prefixed by underscores, to tell whether to prefix a
53 label with a plus sign or not, so that the assembler can tell
54 symbol names from register names. */
55 int mn10300_protect_label;
57 /* The size of the callee register save area. Right now we save everything
58 on entry since it costs us nothing in code size. It does cost us from a
59 speed standpoint, so we want to optimize this sooner or later. */
60 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
61 + 4 * regs_ever_live[3] \
62 + 4 * regs_ever_live[6] \
63 + 4 * regs_ever_live[7] \
64 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
65 || regs_ever_live[16] || regs_ever_live[17]))
68 static int mn10300_address_cost_1 (rtx, int *);
69 static int mn10300_address_cost (rtx);
70 static bool mn10300_rtx_costs (rtx, int, int, int *);
71 static void mn10300_file_start (void);
74 /* Initialize the GCC target structure. */
75 #undef TARGET_ASM_ALIGNED_HI_OP
76 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
78 #undef TARGET_RTX_COSTS
79 #define TARGET_RTX_COSTS mn10300_rtx_costs
80 #undef TARGET_ADDRESS_COST
81 #define TARGET_ADDRESS_COST mn10300_address_cost
83 #undef TARGET_ASM_FILE_START
84 #define TARGET_ASM_FILE_START mn10300_file_start
85 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
86 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
88 #undef TARGET_ENCODE_SECTION_INFO
89 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
91 static void mn10300_encode_section_info (tree, rtx, int);
92 struct gcc_target targetm = TARGET_INITIALIZER;
97 default_file_start ();
100 fprintf (asm_out_file, "\t.am33_2\n");
101 else if (TARGET_AM33)
102 fprintf (asm_out_file, "\t.am33\n");
106 /* Print operand X using operand code CODE to assembly language output file
110 print_operand (file, x, code)
119 if (cc_status.mdep.fpCC)
121 switch (code == 'b' ? GET_CODE (x)
122 : reverse_condition_maybe_unordered (GET_CODE (x)))
125 fprintf (file, "ne");
128 fprintf (file, "eq");
131 fprintf (file, "ge");
134 fprintf (file, "gt");
137 fprintf (file, "le");
140 fprintf (file, "lt");
143 fprintf (file, "lge");
146 fprintf (file, "uo");
149 fprintf (file, "lg");
152 fprintf (file, "ue");
155 fprintf (file, "uge");
158 fprintf (file, "ug");
161 fprintf (file, "ule");
164 fprintf (file, "ul");
171 /* These are normal and reversed branches. */
172 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
175 fprintf (file, "ne");
178 fprintf (file, "eq");
181 fprintf (file, "ge");
184 fprintf (file, "gt");
187 fprintf (file, "le");
190 fprintf (file, "lt");
193 fprintf (file, "cc");
196 fprintf (file, "hi");
199 fprintf (file, "ls");
202 fprintf (file, "cs");
209 /* This is used for the operand to a call instruction;
210 if it's a REG, enclose it in parens, else output
211 the operand normally. */
212 if (GET_CODE (x) == REG)
215 print_operand (file, x, 0);
219 print_operand (file, x, 0);
223 switch (GET_CODE (x))
227 output_address (XEXP (x, 0));
232 fprintf (file, "fd%d", REGNO (x) - 18);
240 /* These are the least significant word in a 64bit value. */
242 switch (GET_CODE (x))
246 output_address (XEXP (x, 0));
251 fprintf (file, "%s", reg_names[REGNO (x)]);
255 fprintf (file, "%s", reg_names[subreg_regno (x)]);
263 switch (GET_MODE (x))
266 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
267 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
268 fprintf (file, "0x%lx", val[0]);
271 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
272 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
273 fprintf (file, "0x%lx", val[0]);
277 print_operand_address (file,
278 GEN_INT (CONST_DOUBLE_LOW (x)));
289 split_double (x, &low, &high);
290 fprintf (file, "%ld", (long)INTVAL (low));
299 /* Similarly, but for the most significant word. */
301 switch (GET_CODE (x))
305 x = adjust_address (x, SImode, 4);
306 output_address (XEXP (x, 0));
311 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
315 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
323 switch (GET_MODE (x))
326 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
327 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
328 fprintf (file, "0x%lx", val[1]);
334 print_operand_address (file,
335 GEN_INT (CONST_DOUBLE_HIGH (x)));
346 split_double (x, &low, &high);
347 fprintf (file, "%ld", (long)INTVAL (high));
358 if (GET_CODE (XEXP (x, 0)) == REG)
359 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
361 output_address (XEXP (x, 0));
366 if (INTVAL (x) < -128 || INTVAL (x) > 255)
368 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
372 if (INTVAL (x) < -128 || INTVAL (x) > 255)
374 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
377 /* For shift counts. The hardware ignores the upper bits of
378 any immediate, but the assembler will flag an out of range
379 shift count as an error. So we mask off the high bits
380 of the immediate here. */
382 if (GET_CODE (x) == CONST_INT)
384 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
390 switch (GET_CODE (x))
394 output_address (XEXP (x, 0));
403 fprintf (file, "%s", reg_names[REGNO (x)]);
407 fprintf (file, "%s", reg_names[subreg_regno (x)]);
410 /* This will only be single precision.... */
416 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
417 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
418 fprintf (file, "0x%lx", val);
428 print_operand_address (file, x);
437 /* Output assembly language output for the address ADDR to FILE. */
440 print_operand_address (file, addr)
444 switch (GET_CODE (addr))
447 print_operand_address (file, XEXP (addr, 0));
451 print_operand (file, addr, 0);
456 if (REG_P (XEXP (addr, 0))
457 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
458 base = XEXP (addr, 0), index = XEXP (addr, 1);
459 else if (REG_P (XEXP (addr, 1))
460 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
461 base = XEXP (addr, 1), index = XEXP (addr, 0);
464 print_operand (file, index, 0);
466 print_operand (file, base, 0);;
470 output_addr_const (file, addr);
473 output_addr_const (file, addr);
478 /* Count the number of FP registers that have to be saved. */
487 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
488 if (regs_ever_live[i] && ! call_used_regs[i])
494 /* Print a set of registers in the format required by "movm" and "ret".
495 Register K is saved if bit K of MASK is set. The data and address
496 registers can be stored individually, but the extended registers cannot.
497 We assume that the mask alread takes that into account. For instance,
498 bits 14 to 17 must have the same value. */
501 mn10300_print_reg_list (file, mask)
511 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
512 if ((mask & (1 << i)) != 0)
516 fputs (reg_names [i], file);
520 if ((mask & 0x3c000) != 0)
522 if ((mask & 0x3c000) != 0x3c000)
526 fputs ("exreg1", file);
534 can_use_return_insn ()
536 /* size includes the fixed stack space needed for function calls. */
537 int size = get_frame_size () + current_function_outgoing_args_size;
539 /* And space for the return pointer. */
540 size += current_function_outgoing_args_size ? 4 : 0;
542 return (reload_completed
544 && !regs_ever_live[2]
545 && !regs_ever_live[3]
546 && !regs_ever_live[6]
547 && !regs_ever_live[7]
548 && !regs_ever_live[14]
549 && !regs_ever_live[15]
550 && !regs_ever_live[16]
551 && !regs_ever_live[17]
552 && fp_regs_to_save () == 0
553 && !frame_pointer_needed);
556 /* Returns the set of live, callee-saved registers as a bitmask. The
557 callee-saved extended registers cannot be stored individually, so
558 all of them will be included in the mask if any one of them is used. */
561 mn10300_get_live_callee_saved_regs ()
567 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
568 if (regs_ever_live[i] && ! call_used_regs[i])
570 if ((mask & 0x3c000) != 0)
576 /* Generate an instruction that pushes several registers onto the stack.
577 Register K will be saved if bit K in MASK is set. The function does
578 nothing if MASK is zero.
580 To be compatible with the "movm" instruction, the lowest-numbered
581 register must be stored in the lowest slot. If MASK is the set
582 { R1,...,RN }, where R1...RN are ordered least first, the generated
583 instruction will have the form:
586 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
587 (set (mem:SI (plus:SI (reg:SI 9)
591 (set (mem:SI (plus:SI (reg:SI 9)
596 mn10300_gen_multiple_store (mask)
606 /* Count how many registers need to be saved. */
608 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
609 if ((mask & (1 << i)) != 0)
612 /* We need one PARALLEL element to update the stack pointer and
613 an additional element for each register that is stored. */
614 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
616 /* Create the instruction that updates the stack pointer. */
618 = gen_rtx_SET (SImode,
620 gen_rtx_PLUS (SImode,
622 GEN_INT (-count * 4)));
624 /* Create each store. */
626 for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
627 if ((mask & (1 << i)) != 0)
629 rtx address = gen_rtx_PLUS (SImode,
631 GEN_INT (-pari * 4));
632 XVECEXP(par, 0, pari)
633 = gen_rtx_SET (VOIDmode,
634 gen_rtx_MEM (SImode, address),
635 gen_rtx_REG (SImode, i));
639 par = emit_insn (par);
640 RTX_FRAME_RELATED_P (par) = 1;
649 /* SIZE includes the fixed stack space needed for function calls. */
650 size = get_frame_size () + current_function_outgoing_args_size;
651 size += (current_function_outgoing_args_size ? 4 : 0);
653 /* If we use any of the callee-saved registers, save them now. */
654 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
656 if (TARGET_AM33_2 && fp_regs_to_save ())
658 int num_regs_to_save = fp_regs_to_save (), i;
660 enum { save_sp_merge,
662 save_sp_partial_merge,
664 save_a0_no_merge } strategy;
665 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
669 /* We have several different strategies to save FP registers.
670 We can store them using SP offsets, which is beneficial if
671 there are just a few registers to save, or we can use `a0' in
672 post-increment mode (`a0' is the only call-clobbered address
673 register that is never used to pass information to a
674 function). Furthermore, if we don't need a frame pointer, we
675 can merge the two SP adds into a single one, but this isn't
676 always beneficial; sometimes we can just split the two adds
677 so that we don't exceed a 16-bit constant size. The code
678 below will select which strategy to use, so as to generate
679 smallest code. Ties are broken in favor or shorter sequences
680 (in terms of number of instructions). */
682 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
683 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
684 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
685 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
686 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
687 (((S) >= (L)) ? (SIZE1) * (N) \
688 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
689 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
691 #define SIZE_FMOV_SP_(S,N) \
692 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
693 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
694 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
695 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
697 /* Consider alternative save_sp_merge only if we don't need the
698 frame pointer and size is nonzero. */
699 if (! frame_pointer_needed && size)
701 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
702 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
703 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
704 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
706 if (this_strategy_size < strategy_size)
708 strategy = save_sp_merge;
709 strategy_size = this_strategy_size;
713 /* Consider alternative save_sp_no_merge unconditionally. */
714 /* Insn: add -4 * num_regs_to_save, sp. */
715 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
716 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
717 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
720 /* Insn: add -size, sp. */
721 this_strategy_size += SIZE_ADD_SP (-size);
724 if (this_strategy_size < strategy_size)
726 strategy = save_sp_no_merge;
727 strategy_size = this_strategy_size;
730 /* Consider alternative save_sp_partial_merge only if we don't
731 need a frame pointer and size is reasonably large. */
732 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
734 /* Insn: add -128, sp. */
735 this_strategy_size = SIZE_ADD_SP (-128);
736 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
737 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
741 /* Insn: add 128-size, sp. */
742 this_strategy_size += SIZE_ADD_SP (128 - size);
745 if (this_strategy_size < strategy_size)
747 strategy = save_sp_partial_merge;
748 strategy_size = this_strategy_size;
752 /* Consider alternative save_a0_merge only if we don't need a
753 frame pointer, size is nonzero and the user hasn't
754 changed the calling conventions of a0. */
755 if (! frame_pointer_needed && size
756 && call_used_regs[FIRST_ADDRESS_REGNUM]
757 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
759 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
760 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
761 /* Insn: mov sp, a0. */
762 this_strategy_size++;
765 /* Insn: add size, a0. */
766 this_strategy_size += SIZE_ADD_AX (size);
768 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
769 this_strategy_size += 3 * num_regs_to_save;
771 if (this_strategy_size < strategy_size)
773 strategy = save_a0_merge;
774 strategy_size = this_strategy_size;
778 /* Consider alternative save_a0_no_merge if the user hasn't
779 changed the calling conventions of a0. */
780 if (call_used_regs[FIRST_ADDRESS_REGNUM]
781 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
783 /* Insn: add -4 * num_regs_to_save, sp. */
784 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
785 /* Insn: mov sp, a0. */
786 this_strategy_size++;
787 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
788 this_strategy_size += 3 * num_regs_to_save;
791 /* Insn: add -size, sp. */
792 this_strategy_size += SIZE_ADD_SP (-size);
795 if (this_strategy_size < strategy_size)
797 strategy = save_a0_no_merge;
798 strategy_size = this_strategy_size;
802 /* Emit the initial SP add, common to all strategies. */
805 case save_sp_no_merge:
806 case save_a0_no_merge:
807 emit_insn (gen_addsi3 (stack_pointer_rtx,
809 GEN_INT (-4 * num_regs_to_save)));
813 case save_sp_partial_merge:
814 emit_insn (gen_addsi3 (stack_pointer_rtx,
817 xsize = 128 - 4 * num_regs_to_save;
823 emit_insn (gen_addsi3 (stack_pointer_rtx,
825 GEN_INT (-(size + 4 * num_regs_to_save))));
826 /* We'll have to adjust FP register saves according to the
829 /* Since we've already created the stack frame, don't do it
830 again at the end of the function. */
838 /* Now prepare register a0, if we have decided to use it. */
842 case save_sp_no_merge:
843 case save_sp_partial_merge:
848 case save_a0_no_merge:
849 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
850 emit_insn (gen_movsi (reg, stack_pointer_rtx));
852 emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
853 reg = gen_rtx_POST_INC (SImode, reg);
860 /* Now actually save the FP registers. */
861 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
862 if (regs_ever_live[i] && ! call_used_regs[i])
870 /* If we aren't using `a0', use an SP offset. */
873 addr = gen_rtx_PLUS (SImode,
878 addr = stack_pointer_rtx;
883 insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
884 gen_rtx_REG (SImode, i)));
886 RTX_FRAME_RELATED_P (insn) = 1;
890 /* Now put the frame pointer into the frame pointer register. */
891 if (frame_pointer_needed)
892 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
894 /* Allocate stack for this frame. */
896 emit_insn (gen_addsi3 (stack_pointer_rtx,
899 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
901 rtx insn = get_last_insn ();
902 rtx last = emit_insn (gen_GOTaddr2picreg ());
904 /* Mark these insns as possibly dead. Sometimes, flow2 may
905 delete all uses of the PIC register. In this case, let it
906 delete the initialization too. */
909 insn = NEXT_INSN (insn);
911 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
915 while (insn != last);
924 /* SIZE includes the fixed stack space needed for function calls. */
925 size = get_frame_size () + current_function_outgoing_args_size;
926 size += (current_function_outgoing_args_size ? 4 : 0);
928 if (TARGET_AM33_2 && fp_regs_to_save ())
930 int num_regs_to_save = fp_regs_to_save (), i;
933 /* We have several options to restore FP registers. We could
934 load them from SP offsets, but, if there are enough FP
935 registers to restore, we win if we use a post-increment
938 /* If we have a frame pointer, it's the best option, because we
939 already know it has the value we want. */
940 if (frame_pointer_needed)
941 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
942 /* Otherwise, we may use `a1', since it's call-clobbered and
943 it's never used for return values. But only do so if it's
944 smaller than using SP offsets. */
947 enum { restore_sp_post_adjust,
948 restore_sp_pre_adjust,
949 restore_sp_partial_adjust,
950 restore_a1 } strategy;
951 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
953 /* Consider using sp offsets before adjusting sp. */
954 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
955 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
956 /* If size is too large, we'll have to adjust SP with an
958 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
960 /* Insn: add size + 4 * num_regs_to_save, sp. */
961 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
963 /* If we don't have to restore any non-FP registers,
964 we'll be able to save one byte by using rets. */
965 if (! REG_SAVE_BYTES)
966 this_strategy_size--;
968 if (this_strategy_size < strategy_size)
970 strategy = restore_sp_post_adjust;
971 strategy_size = this_strategy_size;
974 /* Consider using sp offsets after adjusting sp. */
975 /* Insn: add size, sp. */
976 this_strategy_size = SIZE_ADD_SP (size);
977 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
978 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
979 /* We're going to use ret to release the FP registers
980 save area, so, no savings. */
982 if (this_strategy_size < strategy_size)
984 strategy = restore_sp_pre_adjust;
985 strategy_size = this_strategy_size;
988 /* Consider using sp offsets after partially adjusting sp.
989 When size is close to 32Kb, we may be able to adjust SP
990 with an imm16 add instruction while still using fmov
992 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
994 /* Insn: add size + 4 * num_regs_to_save
995 + REG_SAVE_BYTES - 252,sp. */
996 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
997 + REG_SAVE_BYTES - 252);
998 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
999 this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
1000 - 4 * num_regs_to_save,
1002 /* We're going to use ret to release the FP registers
1003 save area, so, no savings. */
1005 if (this_strategy_size < strategy_size)
1007 strategy = restore_sp_partial_adjust;
1008 strategy_size = this_strategy_size;
1012 /* Consider using a1 in post-increment mode, as long as the
1013 user hasn't changed the calling conventions of a1. */
1014 if (call_used_regs[FIRST_ADDRESS_REGNUM+1]
1015 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1017 /* Insn: mov sp,a1. */
1018 this_strategy_size = 1;
1021 /* Insn: add size,a1. */
1022 this_strategy_size += SIZE_ADD_AX (size);
1024 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1025 this_strategy_size += 3 * num_regs_to_save;
1026 /* If size is large enough, we may be able to save a
1028 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1030 /* Insn: mov a1,sp. */
1031 this_strategy_size += 2;
1033 /* If we don't have to restore any non-FP registers,
1034 we'll be able to save one byte by using rets. */
1035 if (! REG_SAVE_BYTES)
1036 this_strategy_size--;
1038 if (this_strategy_size < strategy_size)
1040 strategy = restore_a1;
1041 strategy_size = this_strategy_size;
1047 case restore_sp_post_adjust:
1050 case restore_sp_pre_adjust:
1051 emit_insn (gen_addsi3 (stack_pointer_rtx,
1057 case restore_sp_partial_adjust:
1058 emit_insn (gen_addsi3 (stack_pointer_rtx,
1060 GEN_INT (size + 4 * num_regs_to_save
1061 + REG_SAVE_BYTES - 252)));
1062 size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1066 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1067 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1069 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1077 /* Adjust the selected register, if any, for post-increment. */
1079 reg = gen_rtx_POST_INC (SImode, reg);
1081 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1082 if (regs_ever_live[i] && ! call_used_regs[i])
1090 /* If we aren't using a post-increment register, use an
1092 addr = gen_rtx_PLUS (SImode,
1097 addr = stack_pointer_rtx;
1101 emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
1102 gen_rtx_MEM (SImode, addr)));
1105 /* If we were using the restore_a1 strategy and the number of
1106 bytes to be released won't fit in the `ret' byte, copy `a1'
1107 to `sp', to avoid having to use `add' to adjust it. */
1108 if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1110 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1115 /* Maybe cut back the stack, except for the register save area.
1117 If the frame pointer exists, then use the frame pointer to
1120 If the stack size + register save area is more than 255 bytes,
1121 then the stack must be cut back here since the size + register
1122 save size is too big for a ret/retf instruction.
1124 Else leave it alone, it will be cut back as part of the
1125 ret/retf instruction, or there wasn't any stack to begin with.
1127 Under no circumstances should the register save area be
1128 deallocated here, that would leave a window where an interrupt
1129 could occur and trash the register save area. */
1130 if (frame_pointer_needed)
1132 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1135 else if (size + REG_SAVE_BYTES > 255)
1137 emit_insn (gen_addsi3 (stack_pointer_rtx,
1143 /* Adjust the stack and restore callee-saved registers, if any. */
1144 if (size || regs_ever_live[2] || regs_ever_live[3]
1145 || regs_ever_live[6] || regs_ever_live[7]
1146 || regs_ever_live[14] || regs_ever_live[15]
1147 || regs_ever_live[16] || regs_ever_live[17]
1148 || frame_pointer_needed)
1149 emit_jump_insn (gen_return_internal_regs
1150 (GEN_INT (size + REG_SAVE_BYTES)));
1152 emit_jump_insn (gen_return_internal ());
1155 /* Update the condition code from the insn. */
1158 notice_update_cc (body, insn)
1162 switch (get_attr_cc (insn))
1165 /* Insn does not affect CC at all. */
1169 /* Insn does not change CC, but the 0'th operand has been changed. */
1170 if (cc_status.value1 != 0
1171 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1172 cc_status.value1 = 0;
1176 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1177 V,C are unusable. */
1179 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
1180 cc_status.value1 = recog_data.operand[0];
1184 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1187 cc_status.flags |= CC_NO_CARRY;
1188 cc_status.value1 = recog_data.operand[0];
1192 /* The insn is a compare instruction. */
1194 cc_status.value1 = SET_SRC (body);
1195 if (GET_CODE (cc_status.value1) == COMPARE
1196 && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
1197 cc_status.mdep.fpCC = 1;
1201 /* The insn is a compare instruction. */
1203 cc_status.value1 = SET_SRC (body);
1204 cc_status.flags |= CC_INVERTED;
1208 /* Insn doesn't leave CC in a usable state. */
1217 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1218 This function is for MATCH_PARALLEL and so assumes OP is known to be
1219 parallel. If OP is a multiple store, return a mask indicating which
1220 registers it saves. Return 0 otherwise. */
1223 store_multiple_operation (op, mode)
1225 enum machine_mode mode ATTRIBUTE_UNUSED;
1233 count = XVECLEN (op, 0);
1237 /* Check that first instruction has the form (set (sp) (plus A B)) */
1238 elt = XVECEXP (op, 0, 0);
1239 if (GET_CODE (elt) != SET
1240 || GET_CODE (SET_DEST (elt)) != REG
1241 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1242 || GET_CODE (SET_SRC (elt)) != PLUS)
1245 /* Check that A is the stack pointer and B is the expected stack size.
1246 For OP to match, each subsequent instruction should push a word onto
1247 the stack. We therefore expect the first instruction to create
1248 COUNT-1 stack slots. */
1249 elt = SET_SRC (elt);
1250 if (GET_CODE (XEXP (elt, 0)) != REG
1251 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1252 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1253 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1256 /* Now go through the rest of the vector elements. They must be
1257 ordered so that the first instruction stores the highest-numbered
1258 register to the highest stack slot and that subsequent instructions
1259 store a lower-numbered register to the slot below.
1261 LAST keeps track of the smallest-numbered register stored so far.
1262 MASK is the set of stored registers. */
1263 last = LAST_EXTENDED_REGNUM + 1;
1265 for (i = 1; i < count; i++)
1267 /* Check that element i is a (set (mem M) R) and that R is valid. */
1268 elt = XVECEXP (op, 0, i);
1269 if (GET_CODE (elt) != SET
1270 || GET_CODE (SET_DEST (elt)) != MEM
1271 || GET_CODE (SET_SRC (elt)) != REG
1272 || REGNO (SET_SRC (elt)) >= last)
1275 /* R was OK, so provisionally add it to MASK. We return 0 in any
1276 case if the rest of the instruction has a flaw. */
1277 last = REGNO (SET_SRC (elt));
1278 mask |= (1 << last);
1280 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1281 elt = XEXP (SET_DEST (elt), 0);
1282 if (GET_CODE (elt) != PLUS
1283 || GET_CODE (XEXP (elt, 0)) != REG
1284 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1285 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1286 || INTVAL (XEXP (elt, 1)) != -i * 4)
1290 /* All or none of the callee-saved extended registers must be in the set. */
1291 if ((mask & 0x3c000) != 0
1292 && (mask & 0x3c000) != 0x3c000)
1298 /* Return true if OP is a valid call operand. */
1301 call_address_operand (op, mode)
1303 enum machine_mode mode ATTRIBUTE_UNUSED;
1306 return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG);
1308 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
1311 /* What (if any) secondary registers are needed to move IN with mode
1312 MODE into a register in register class CLASS.
1314 We might be able to simplify this. */
1316 secondary_reload_class (class, mode, in)
1317 enum reg_class class;
1318 enum machine_mode mode;
1321 /* Memory loads less than a full word wide can't have an
1322 address or stack pointer destination. They must use
1323 a data register as an intermediate register. */
1324 if ((GET_CODE (in) == MEM
1325 || (GET_CODE (in) == REG
1326 && REGNO (in) >= FIRST_PSEUDO_REGISTER)
1327 || (GET_CODE (in) == SUBREG
1328 && GET_CODE (SUBREG_REG (in)) == REG
1329 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
1330 && (mode == QImode || mode == HImode)
1331 && (class == ADDRESS_REGS || class == SP_REGS
1332 || class == SP_OR_ADDRESS_REGS))
1335 return DATA_OR_EXTENDED_REGS;
1339 /* We can't directly load sp + const_int into a data register;
1340 we must use an address register as an intermediate. */
1341 if (class != SP_REGS
1342 && class != ADDRESS_REGS
1343 && class != SP_OR_ADDRESS_REGS
1344 && class != SP_OR_EXTENDED_REGS
1345 && class != ADDRESS_OR_EXTENDED_REGS
1346 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
1347 && (in == stack_pointer_rtx
1348 || (GET_CODE (in) == PLUS
1349 && (XEXP (in, 0) == stack_pointer_rtx
1350 || XEXP (in, 1) == stack_pointer_rtx))))
1351 return ADDRESS_REGS;
1353 if (GET_CODE (in) == PLUS
1354 && (XEXP (in, 0) == stack_pointer_rtx
1355 || XEXP (in, 1) == stack_pointer_rtx))
1358 return DATA_OR_EXTENDED_REGS;
1362 if (TARGET_AM33_2 && class == FP_REGS
1363 && GET_CODE (in) == MEM && ! OK_FOR_Q (in))
1366 return DATA_OR_EXTENDED_REGS;
1370 /* Otherwise assume no secondary reloads are needed. */
1375 initial_offset (from, to)
1378 /* The difference between the argument pointer and the frame pointer
1379 is the size of the callee register save area. */
1380 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1382 if (regs_ever_live[2] || regs_ever_live[3]
1383 || regs_ever_live[6] || regs_ever_live[7]
1384 || regs_ever_live[14] || regs_ever_live[15]
1385 || regs_ever_live[16] || regs_ever_live[17]
1386 || fp_regs_to_save ()
1387 || frame_pointer_needed)
1388 return REG_SAVE_BYTES
1389 + 4 * fp_regs_to_save ();
1394 /* The difference between the argument pointer and the stack pointer is
1395 the sum of the size of this function's frame, the callee register save
1396 area, and the fixed stack space needed for function calls (if any). */
1397 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1399 if (regs_ever_live[2] || regs_ever_live[3]
1400 || regs_ever_live[6] || regs_ever_live[7]
1401 || regs_ever_live[14] || regs_ever_live[15]
1402 || regs_ever_live[16] || regs_ever_live[17]
1403 || fp_regs_to_save ()
1404 || frame_pointer_needed)
1405 return (get_frame_size () + REG_SAVE_BYTES
1406 + 4 * fp_regs_to_save ()
1407 + (current_function_outgoing_args_size
1408 ? current_function_outgoing_args_size + 4 : 0));
1410 return (get_frame_size ()
1411 + (current_function_outgoing_args_size
1412 ? current_function_outgoing_args_size + 4 : 0));
1415 /* The difference between the frame pointer and stack pointer is the sum
1416 of the size of this function's frame and the fixed stack space needed
1417 for function calls (if any). */
1418 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1419 return (get_frame_size ()
1420 + (current_function_outgoing_args_size
1421 ? current_function_outgoing_args_size + 4 : 0));
1426 /* Flush the argument registers to the stack for a stdarg function;
1427 return the new argument pointer. */
1429 mn10300_builtin_saveregs ()
1432 tree fntype = TREE_TYPE (current_function_decl);
1433 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
1434 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1435 != void_type_node)))
1436 ? UNITS_PER_WORD : 0);
1437 int set = get_varargs_alias_set ();
1440 offset = plus_constant (current_function_arg_offset_rtx, argadj);
1442 offset = current_function_arg_offset_rtx;
1444 mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
1445 set_mem_alias_set (mem, set);
1446 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1448 mem = gen_rtx_MEM (SImode,
1449 plus_constant (current_function_internal_arg_pointer, 4));
1450 set_mem_alias_set (mem, set);
1451 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1453 return copy_to_reg (expand_binop (Pmode, add_optab,
1454 current_function_internal_arg_pointer,
1455 offset, 0, 0, OPTAB_LIB_WIDEN));
1459 mn10300_va_start (valist, nextarg)
1463 nextarg = expand_builtin_saveregs ();
1464 std_expand_builtin_va_start (valist, nextarg);
1468 mn10300_va_arg (valist, type)
1471 HOST_WIDE_INT align, rsize;
1474 /* Compute the rounded size of the type. */
1475 align = PARM_BOUNDARY / BITS_PER_UNIT;
1476 rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
1478 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
1479 build_int_2 ((rsize > 8 ? 4 : rsize), 0));
1480 TREE_SIDE_EFFECTS (t) = 1;
1482 ptr = build_pointer_type (type);
1484 /* "Large" types are passed by reference. */
1487 pptr = build_pointer_type (ptr);
1488 t = build1 (NOP_EXPR, pptr, t);
1489 TREE_SIDE_EFFECTS (t) = 1;
1491 t = build1 (INDIRECT_REF, ptr, t);
1492 TREE_SIDE_EFFECTS (t) = 1;
1496 t = build1 (NOP_EXPR, ptr, t);
1497 TREE_SIDE_EFFECTS (t) = 1;
1501 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1504 /* Return an RTX to represent where a value with mode MODE will be returned
1505 from a function. If the result is 0, the argument is pushed. */
1508 function_arg (cum, mode, type, named)
1509 CUMULATIVE_ARGS *cum;
1510 enum machine_mode mode;
1512 int named ATTRIBUTE_UNUSED;
1517 /* We only support using 2 data registers as argument registers. */
1520 /* Figure out the size of the object to be passed. */
1521 if (mode == BLKmode)
1522 size = int_size_in_bytes (type);
1524 size = GET_MODE_SIZE (mode);
1526 /* Figure out the alignment of the object to be passed. */
1529 cum->nbytes = (cum->nbytes + 3) & ~3;
1531 /* Don't pass this arg via a register if all the argument registers
1533 if (cum->nbytes > nregs * UNITS_PER_WORD)
1536 /* Don't pass this arg via a register if it would be split between
1537 registers and memory. */
1538 if (type == NULL_TREE
1539 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1542 switch (cum->nbytes / UNITS_PER_WORD)
1545 result = gen_rtx_REG (mode, 0);
1548 result = gen_rtx_REG (mode, 1);
1557 /* Return the number of registers to use for an argument passed partially
1558 in registers and partially in memory. */
1561 function_arg_partial_nregs (cum, mode, type, named)
1562 CUMULATIVE_ARGS *cum;
1563 enum machine_mode mode;
1565 int named ATTRIBUTE_UNUSED;
1569 /* We only support using 2 data registers as argument registers. */
1572 /* Figure out the size of the object to be passed. */
1573 if (mode == BLKmode)
1574 size = int_size_in_bytes (type);
1576 size = GET_MODE_SIZE (mode);
1578 /* Figure out the alignment of the object to be passed. */
1581 cum->nbytes = (cum->nbytes + 3) & ~3;
1583 /* Don't pass this arg via a register if all the argument registers
1585 if (cum->nbytes > nregs * UNITS_PER_WORD)
1588 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1591 /* Don't pass this arg via a register if it would be split between
1592 registers and memory. */
1593 if (type == NULL_TREE
1594 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1597 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1600 /* Output a tst insn. */
1602 output_tst (operand, insn)
1608 /* We can save a byte if we can find a register which has the value
1610 temp = PREV_INSN (insn);
1611 while (optimize && temp)
1615 /* We allow the search to go through call insns. We record
1616 the fact that we've past a CALL_INSN and reject matches which
1617 use call clobbered registers. */
1618 if (GET_CODE (temp) == CODE_LABEL
1619 || GET_CODE (temp) == JUMP_INSN
1620 || GET_CODE (temp) == BARRIER)
1623 if (GET_CODE (temp) == CALL_INSN)
1626 if (GET_CODE (temp) == NOTE)
1628 temp = PREV_INSN (temp);
1632 /* It must be an insn, see if it is a simple set. */
1633 set = single_set (temp);
1636 temp = PREV_INSN (temp);
1640 /* Are we setting a data register to zero (this does not win for
1643 If it's a call clobbered register, have we past a call?
1645 Make sure the register we find isn't the same as ourself;
1646 the mn10300 can't encode that.
1648 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1649 so the code to detect calls here isn't doing anything useful. */
1650 if (REG_P (SET_DEST (set))
1651 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1652 && !reg_set_between_p (SET_DEST (set), temp, insn)
1653 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1654 == REGNO_REG_CLASS (REGNO (operand)))
1655 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1656 && REGNO (SET_DEST (set)) != REGNO (operand)
1658 || !call_used_regs[REGNO (SET_DEST (set))]))
1661 xoperands[0] = operand;
1662 xoperands[1] = SET_DEST (set);
1664 output_asm_insn ("cmp %1,%0", xoperands);
1668 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1669 && REG_P (SET_DEST (set))
1670 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1671 && !reg_set_between_p (SET_DEST (set), temp, insn)
1672 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1673 != REGNO_REG_CLASS (REGNO (operand)))
1674 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1675 && REGNO (SET_DEST (set)) != REGNO (operand)
1677 || !call_used_regs[REGNO (SET_DEST (set))]))
1680 xoperands[0] = operand;
1681 xoperands[1] = SET_DEST (set);
1683 output_asm_insn ("cmp %1,%0", xoperands);
1686 temp = PREV_INSN (temp);
1692 impossible_plus_operand (op, mode)
1694 enum machine_mode mode ATTRIBUTE_UNUSED;
1696 if (GET_CODE (op) != PLUS)
1699 if (XEXP (op, 0) == stack_pointer_rtx
1700 || XEXP (op, 1) == stack_pointer_rtx)
1706 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1707 for the btst insn which may examine memory or a register (the memory
1708 variant only allows an unsigned 8 bit integer). */
1710 const_8bit_operand (op, mode)
1712 enum machine_mode mode ATTRIBUTE_UNUSED;
1714 return (GET_CODE (op) == CONST_INT
1716 && INTVAL (op) < 256);
1719 /* Return true if the operand is the 1.0f constant. */
1721 const_1f_operand (op, mode)
1723 enum machine_mode mode ATTRIBUTE_UNUSED;
1725 return (op == CONST1_RTX (SFmode));
1728 /* Similarly, but when using a zero_extract pattern for a btst where
1729 the source operand might end up in memory. */
1731 mask_ok_for_mem_btst (len, bit)
1735 unsigned int mask = 0;
1744 /* MASK must bit into an 8bit value. */
1745 return (((mask & 0xff) == mask)
1746 || ((mask & 0xff00) == mask)
1747 || ((mask & 0xff0000) == mask)
1748 || ((mask & 0xff000000) == mask));
1751 /* Return 1 if X contains a symbolic expression. We know these
1752 expressions will have one of a few well defined forms, so
1753 we need only check those forms. */
1755 symbolic_operand (op, mode)
1757 enum machine_mode mode ATTRIBUTE_UNUSED;
1759 switch (GET_CODE (op))
1766 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1767 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1768 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1774 /* Try machine dependent ways of modifying an illegitimate address
1775 to be legitimate. If we find one, return the new valid address.
1776 This macro is used in only one place: `memory_address' in explow.c.
1778 OLDX is the address as it was before break_out_memory_refs was called.
1779 In some cases it is useful to look at this to decide what needs to be done.
1781 MODE and WIN are passed so that this macro can use
1782 GO_IF_LEGITIMATE_ADDRESS.
1784 Normally it is always safe for this macro to do nothing. It exists to
1785 recognize opportunities to optimize the output.
1787 But on a few ports with segmented architectures and indexed addressing
1788 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1790 legitimize_address (x, oldx, mode)
1792 rtx oldx ATTRIBUTE_UNUSED;
1793 enum machine_mode mode ATTRIBUTE_UNUSED;
1795 if (flag_pic && ! legitimate_pic_operand_p (x))
1796 x = legitimize_pic_address (oldx, NULL_RTX);
1798 /* Uh-oh. We might have an address for x[n-100000]. This needs
1799 special handling to avoid creating an indexed memory address
1800 with x-100000 as the base. */
1801 if (GET_CODE (x) == PLUS
1802 && symbolic_operand (XEXP (x, 1), VOIDmode))
1804 /* Ugly. We modify things here so that the address offset specified
1805 by the index expression is computed first, then added to x to form
1806 the entire address. */
1808 rtx regx1, regy1, regy2, y;
1810 /* Strip off any CONST. */
1812 if (GET_CODE (y) == CONST)
1815 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1817 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1818 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1819 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1820 regx1 = force_reg (Pmode,
1821 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1822 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1828 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1829 @GOTOFF in `reg'. */
1831 legitimize_pic_address (orig, reg)
1835 if (GET_CODE (orig) == LABEL_REF
1836 || (GET_CODE (orig) == SYMBOL_REF
1837 && (CONSTANT_POOL_ADDRESS_P (orig)
1838 || ! MN10300_GLOBAL_P (orig))))
1841 reg = gen_reg_rtx (Pmode);
1843 emit_insn (gen_symGOTOFF2reg (reg, orig));
1846 else if (GET_CODE (orig) == SYMBOL_REF)
1849 reg = gen_reg_rtx (Pmode);
1851 emit_insn (gen_symGOT2reg (reg, orig));
1857 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1858 isn't protected by a PIC unspec; nonzero otherwise. */
1860 legitimate_pic_operand_p (x)
1863 register const char *fmt;
1866 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1869 if (GET_CODE (x) == UNSPEC
1870 && (XINT (x, 1) == UNSPEC_PIC
1871 || XINT (x, 1) == UNSPEC_GOT
1872 || XINT (x, 1) == UNSPEC_GOTOFF
1873 || XINT (x, 1) == UNSPEC_PLT))
1876 if (GET_CODE (x) == QUEUED)
1877 return legitimate_pic_operand_p (QUEUED_VAR (x));
1879 fmt = GET_RTX_FORMAT (GET_CODE (x));
1880 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1886 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1887 if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
1890 else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
1898 mn10300_address_cost_1 (x, unsig)
1902 switch (GET_CODE (x))
1905 switch (REGNO_REG_CLASS (REGNO (x)))
1931 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
1932 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
1937 return mn10300_address_cost (XEXP (x, 0));
1941 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
1944 if (INTVAL (x) == 0)
1946 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1948 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1950 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1960 switch (GET_CODE (XEXP (x, 0)))
1963 return mn10300_address_cost (XEXP (x, 0));
1979 mn10300_address_cost (x)
1983 return mn10300_address_cost_1 (x, &s);
1987 mn10300_rtx_costs (x, code, outer_code, total)
1989 int code, outer_code;
1995 /* Zeros are extremely cheap. */
1996 if (INTVAL (x) == 0 && outer_code == SET)
1998 /* If it fits in 8 bits, then it's still relatively cheap. */
1999 else if (INT_8_BITS (INTVAL (x)))
2001 /* This is the "base" cost, includes constants where either the
2002 upper or lower 16bits are all zeros. */
2003 else if (INT_16_BITS (INTVAL (x))
2004 || (INTVAL (x) & 0xffff) == 0
2005 || (INTVAL (x) & 0xffff0000) == 0)
2014 /* These are more costly than a CONST_INT, but we can relax them,
2015 so they're less costly than a CONST_DOUBLE. */
2020 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
2021 so their cost is very high. */
2025 /* ??? This probably needs more work. */
2037 /* Check whether a constant used to initialize a DImode or DFmode can
2038 use a clr instruction. The code here must be kept in sync with
2042 mn10300_wide_const_load_uses_clr (operands)
2047 if (GET_CODE (operands[0]) != REG
2048 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
2051 switch (GET_CODE (operands[1]))
2056 split_double (operands[1], &low, &high);
2057 val[0] = INTVAL (low);
2058 val[1] = INTVAL (high);
2063 if (GET_MODE (operands[1]) == DFmode)
2067 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
2068 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
2070 else if (GET_MODE (operands[1]) == VOIDmode
2071 || GET_MODE (operands[1]) == DImode)
2073 val[0] = CONST_DOUBLE_LOW (operands[1]);
2074 val[1] = CONST_DOUBLE_HIGH (operands[1]);
2082 return val[0] == 0 || val[1] == 0;
2084 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2085 may access it using GOTOFF instead of GOT. */
2088 mn10300_encode_section_info (decl, rtl, first)
2095 if (GET_CODE (rtl) != MEM)
2097 symbol = XEXP (rtl, 0);
2098 if (GET_CODE (symbol) != SYMBOL_REF)
2102 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);