gcc/config/mips/sync.md

   1 ;;  Machine Description for MIPS based processor synchronization
   2 ;;  instructions.
   3 ;;  Copyright (C) 2007, 2008
   4 ;;  Free Software Foundation, Inc.
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;; Atomic fetch bitwise operations.
  23 (define_code_iterator fetchop_bit [ior xor and])
  24
  25 ;; Atomic HI and QI operations
  26 (define_code_iterator atomic_hiqi_op [plus minus ior xor and])
  27
  28 ;; Atomic memory operations.
  29
  30 (define_insn "memory_barrier"
  31   [(set (mem:BLK (scratch))
  32         (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))]
  33   "GENERATE_SYNC"
  34   "%|sync%-")
  35
  36 (define_insn "sync_compare_and_swap<mode>"
  37   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
  38         (match_operand:GPR 1 "memory_operand" "+R,R"))
  39    (set (match_dup 1)
  40         (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
  41                               (match_operand:GPR 3 "arith_operand" "I,d")]
  42          UNSPEC_COMPARE_AND_SWAP))]
  43   "GENERATE_LL_SC"
  44 {
  45   if (which_alternative == 0)
  46     return mips_output_sync_loop (MIPS_COMPARE_AND_SWAP ("<d>", "li"));
  47   else
  48     return mips_output_sync_loop (MIPS_COMPARE_AND_SWAP ("<d>", "move"));
  49 }
  50   [(set_attr "length" "32")])
  51
  52 (define_expand "sync_compare_and_swap<mode>"
  53   [(match_operand:SHORT 0 "register_operand")
  54    (match_operand:SHORT 1 "memory_operand")
  55    (match_operand:SHORT 2 "general_operand")
  56    (match_operand:SHORT 3 "general_operand")]
  57   "GENERATE_LL_SC"
  58 {
  59   union mips_gen_fn_ptrs generator;
  60   generator.fn_6 = gen_compare_and_swap_12;
  61   mips_expand_atomic_qihi (generator,
  62                            operands[0], operands[1], operands[2], operands[3]);
  63   DONE;
  64 })
  65
  66 ;; Helper insn for mips_expand_atomic_qihi.
  67 (define_insn "compare_and_swap_12"
  68   [(set (match_operand:SI 0 "register_operand" "=&d,&d")
  69         (match_operand:SI 1 "memory_operand" "+R,R"))
  70    (set (match_dup 1)
  71         (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
  72                              (match_operand:SI 3 "register_operand" "d,d")
  73                              (match_operand:SI 4 "reg_or_0_operand" "dJ,dJ")
  74                              (match_operand:SI 5 "reg_or_0_operand" "d,J")]
  75                             UNSPEC_COMPARE_AND_SWAP_12))]
  76   "GENERATE_LL_SC"
  77 {
  78   if (which_alternative == 0)
  79     return (mips_output_sync_loop
  80             (MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP)));
  81   else
  82     return (mips_output_sync_loop
  83             (MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP)));
  84 }
  85   [(set_attr "length" "40,36")])
  86
  87 (define_insn "sync_add<mode>"
  88   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
  89         (unspec_volatile:GPR
  90           [(plus:GPR (match_dup 0)
  91                      (match_operand:GPR 1 "arith_operand" "I,d"))]
  92           UNSPEC_SYNC_OLD_OP))]
  93   "GENERATE_LL_SC"
  94 {
  95   if (which_alternative == 0)
  96     return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>addiu"));
  97   else
  98     return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>addu"));
  99 }
 100   [(set_attr "length" "28")])
 101
 102 (define_expand "sync_<optab><mode>"
 103   [(set (match_operand:SHORT 0 "memory_operand")
 104         (unspec_volatile:SHORT
 105           [(atomic_hiqi_op:SHORT (match_dup 0)
 106                                  (match_operand:SHORT 1 "general_operand"))]
 107           UNSPEC_SYNC_OLD_OP))]
 108   "GENERATE_LL_SC"
 109 {
 110   union mips_gen_fn_ptrs generator;
 111   generator.fn_4 = gen_sync_<optab>_12;
 112   mips_expand_atomic_qihi (generator,
 113                            NULL, operands[0], operands[1], NULL);
 114   DONE;
 115 })
 116
 117 ;; Helper insn for sync_<optab><mode>
 118 (define_insn "sync_<optab>_12"
 119   [(set (match_operand:SI 0 "memory_operand" "+R")
 120         (unspec_volatile:SI
 121           [(match_operand:SI 1 "register_operand" "d")
 122            (match_operand:SI 2 "register_operand" "d")
 123            (atomic_hiqi_op:SI (match_dup 0)
 124                               (match_operand:SI 3 "register_operand" "dJ"))]
 125           UNSPEC_SYNC_OLD_OP_12))
 126    (clobber (match_scratch:SI 4 "=&d"))]
 127   "GENERATE_LL_SC"
 128 {
 129     return (mips_output_sync_loop
 130             (MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_NOT_NOP)));
 131 }
 132   [(set_attr "length" "40")])
 133
 134 (define_expand "sync_old_<optab><mode>"
 135   [(parallel [
 136      (set (match_operand:SHORT 0 "register_operand")
 137           (match_operand:SHORT 1 "memory_operand"))
 138      (set (match_dup 1)
 139           (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
 140                                     (match_dup 1)
 141                                     (match_operand:SHORT 2 "general_operand"))]
 142             UNSPEC_SYNC_OLD_OP))])]
 143   "GENERATE_LL_SC"
 144 {
 145   union mips_gen_fn_ptrs generator;
 146   generator.fn_5 = gen_sync_old_<optab>_12;
 147   mips_expand_atomic_qihi (generator,
 148                            operands[0], operands[1], operands[2], NULL);
 149   DONE;
 150 })
 151
 152 ;; Helper insn for sync_old_<optab><mode>
 153 (define_insn "sync_old_<optab>_12"
 154   [(set (match_operand:SI 0 "register_operand" "=&d")
 155         (match_operand:SI 1 "memory_operand" "+R"))
 156    (set (match_dup 1)
 157         (unspec_volatile:SI
 158           [(match_operand:SI 2 "register_operand" "d")
 159            (match_operand:SI 3 "register_operand" "d")
 160            (atomic_hiqi_op:SI (match_dup 0)
 161                               (match_operand:SI 4 "register_operand" "dJ"))]
 162           UNSPEC_SYNC_OLD_OP_12))
 163    (clobber (match_scratch:SI 5 "=&d"))]
 164   "GENERATE_LL_SC"
 165 {
 166     return (mips_output_sync_loop
 167             (MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_NOT_NOP,
 168                                   MIPS_SYNC_OLD_OP_12_NOT_NOP_REG)));
 169 }
 170   [(set_attr "length" "40")])
 171
 172 (define_expand "sync_new_<optab><mode>"
 173   [(parallel [
 174      (set (match_operand:SHORT 0 "register_operand")
 175           (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
 176                                     (match_operand:SHORT 1 "memory_operand")
 177                                     (match_operand:SHORT 2 "general_operand"))]
 178             UNSPEC_SYNC_NEW_OP))
 179      (set (match_dup 1)
 180           (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
 181             UNSPEC_SYNC_NEW_OP))])]
 182   "GENERATE_LL_SC"
 183 {
 184   union mips_gen_fn_ptrs generator;
 185   generator.fn_5 = gen_sync_new_<optab>_12;
 186   mips_expand_atomic_qihi (generator,
 187                            operands[0], operands[1], operands[2], NULL);
 188   DONE;
 189 })
 190
 191 ;; Helper insn for sync_new_<optab><mode>
 192 (define_insn "sync_new_<optab>_12"
 193   [(set (match_operand:SI 0 "register_operand" "=&d")
 194         (unspec_volatile:SI
 195           [(match_operand:SI 1 "memory_operand" "+R")
 196            (match_operand:SI 2 "register_operand" "d")
 197            (match_operand:SI 3 "register_operand" "d")
 198            (atomic_hiqi_op:SI (match_dup 0)
 199                               (match_operand:SI 4 "register_operand" "dJ"))]
 200           UNSPEC_SYNC_NEW_OP_12))
 201    (set (match_dup 1)
 202         (unspec_volatile:SI
 203           [(match_dup 1)
 204            (match_dup 2)
 205            (match_dup 3)
 206            (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
 207   "GENERATE_LL_SC"
 208 {
 209     return (mips_output_sync_loop
 210             (MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_NOT_NOP)));
 211 }
 212   [(set_attr "length" "40")])
 213
 214 (define_expand "sync_nand<mode>"
 215   [(set (match_operand:SHORT 0 "memory_operand")
 216         (unspec_volatile:SHORT
 217           [(match_dup 0)
 218            (match_operand:SHORT 1 "general_operand")]
 219           UNSPEC_SYNC_OLD_OP))]
 220   "GENERATE_LL_SC"
 221 {
 222   union mips_gen_fn_ptrs generator;
 223   generator.fn_4 = gen_sync_nand_12;
 224   mips_expand_atomic_qihi (generator,
 225                            NULL, operands[0], operands[1], NULL);
 226   DONE;
 227 })
 228
 229 ;; Helper insn for sync_nand<mode>
 230 (define_insn "sync_nand_12"
 231   [(set (match_operand:SI 0 "memory_operand" "+R")
 232         (unspec_volatile:SI
 233           [(match_operand:SI 1 "register_operand" "d")
 234            (match_operand:SI 2 "register_operand" "d")
 235            (match_dup 0)
 236            (match_operand:SI 3 "register_operand" "dJ")]
 237           UNSPEC_SYNC_OLD_OP_12))
 238    (clobber (match_scratch:SI 4 "=&d"))]
 239   "GENERATE_LL_SC"
 240 {
 241     return (mips_output_sync_loop
 242             (MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_NOT_NOT)));
 243 }
 244   [(set_attr "length" "44")])
 245
 246 (define_expand "sync_old_nand<mode>"
 247   [(parallel [
 248      (set (match_operand:SHORT 0 "register_operand")
 249           (match_operand:SHORT 1 "memory_operand"))
 250      (set (match_dup 1)
 251           (unspec_volatile:SHORT [(match_dup 1)
 252                                   (match_operand:SHORT 2 "general_operand")]
 253             UNSPEC_SYNC_OLD_OP))])]
 254   "GENERATE_LL_SC"
 255 {
 256   union mips_gen_fn_ptrs generator;
 257   generator.fn_5 = gen_sync_old_nand_12;
 258   mips_expand_atomic_qihi (generator,
 259                            operands[0], operands[1], operands[2], NULL);
 260   DONE;
 261 })
 262
 263 ;; Helper insn for sync_old_nand<mode>
 264 (define_insn "sync_old_nand_12"
 265   [(set (match_operand:SI 0 "register_operand" "=&d")
 266         (match_operand:SI 1 "memory_operand" "+R"))
 267    (set (match_dup 1)
 268         (unspec_volatile:SI
 269           [(match_operand:SI 2 "register_operand" "d")
 270            (match_operand:SI 3 "register_operand" "d")
 271            (match_operand:SI 4 "register_operand" "dJ")]
 272           UNSPEC_SYNC_OLD_OP_12))
 273    (clobber (match_scratch:SI 5 "=&d"))]
 274   "GENERATE_LL_SC"
 275 {
 276     return (mips_output_sync_loop
 277             (MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_NOT_NOT,
 278                                   MIPS_SYNC_OLD_OP_12_NOT_NOT_REG)));
 279 }
 280   [(set_attr "length" "44")])
 281
 282 (define_expand "sync_new_nand<mode>"
 283   [(parallel [
 284      (set (match_operand:SHORT 0 "register_operand")
 285           (unspec_volatile:SHORT [(match_operand:SHORT 1 "memory_operand")
 286                                   (match_operand:SHORT 2 "general_operand")]
 287             UNSPEC_SYNC_NEW_OP))
 288      (set (match_dup 1)
 289           (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
 290             UNSPEC_SYNC_NEW_OP))])]
 291   "GENERATE_LL_SC"
 292 {
 293   union mips_gen_fn_ptrs generator;
 294   generator.fn_5 = gen_sync_new_nand_12;
 295   mips_expand_atomic_qihi (generator,
 296                            operands[0], operands[1], operands[2], NULL);
 297   DONE;
 298 })
 299
 300 ;; Helper insn for sync_new_nand<mode>
 301 (define_insn "sync_new_nand_12"
 302   [(set (match_operand:SI 0 "register_operand" "=&d")
 303         (unspec_volatile:SI
 304           [(match_operand:SI 1 "memory_operand" "+R")
 305            (match_operand:SI 2 "register_operand" "d")
 306            (match_operand:SI 3 "register_operand" "d")
 307            (match_operand:SI 4 "register_operand" "dJ")]
 308           UNSPEC_SYNC_NEW_OP_12))
 309    (set (match_dup 1)
 310         (unspec_volatile:SI
 311           [(match_dup 1)
 312            (match_dup 2)
 313            (match_dup 3)
 314            (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
 315   "GENERATE_LL_SC"
 316 {
 317     return (mips_output_sync_loop
 318             (MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_NOT_NOT)));
 319 }
 320   [(set_attr "length" "40")])
 321
 322 (define_insn "sync_sub<mode>"
 323   [(set (match_operand:GPR 0 "memory_operand" "+R")
 324         (unspec_volatile:GPR
 325           [(minus:GPR (match_dup 0)
 326                               (match_operand:GPR 1 "register_operand" "d"))]
 327          UNSPEC_SYNC_OLD_OP))]
 328   "GENERATE_LL_SC"
 329 {
 330   return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>subu"));
 331 }
 332   [(set_attr "length" "28")])
 333
 334 (define_insn "sync_old_add<mode>"
 335   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 336         (match_operand:GPR 1 "memory_operand" "+R,R"))
 337    (set (match_dup 1)
 338         (unspec_volatile:GPR
 339           [(plus:GPR (match_dup 1)
 340                      (match_operand:GPR 2 "arith_operand" "I,d"))]
 341          UNSPEC_SYNC_OLD_OP))]
 342   "GENERATE_LL_SC"
 343 {
 344   if (which_alternative == 0)
 345     return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>addiu"));
 346   else
 347     return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>addu"));
 348 }
 349   [(set_attr "length" "28")])
 350
 351 (define_insn "sync_old_sub<mode>"
 352   [(set (match_operand:GPR 0 "register_operand" "=&d")
 353         (match_operand:GPR 1 "memory_operand" "+R"))
 354    (set (match_dup 1)
 355         (unspec_volatile:GPR
 356           [(minus:GPR (match_dup 1)
 357                       (match_operand:GPR 2 "register_operand" "d"))]
 358          UNSPEC_SYNC_OLD_OP))]
 359   "GENERATE_LL_SC"
 360 {
 361   return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>subu"));
 362 }
 363   [(set_attr "length" "28")])
 364
 365 (define_insn "sync_new_add<mode>"
 366   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 367         (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
 368                   (match_operand:GPR 2 "arith_operand" "I,d")))
 369    (set (match_dup 1)
 370         (unspec_volatile:GPR
 371           [(plus:GPR (match_dup 1) (match_dup 2))]
 372          UNSPEC_SYNC_NEW_OP))]
 373   "GENERATE_LL_SC"
 374 {
 375   if (which_alternative == 0)
 376     return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>addiu"));
 377   else
 378     return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>addu"));
 379 }
 380   [(set_attr "length" "28")])
 381
 382 (define_insn "sync_new_sub<mode>"
 383   [(set (match_operand:GPR 0 "register_operand" "=&d")
 384         (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
 385                    (match_operand:GPR 2 "register_operand" "d")))
 386    (set (match_dup 1)
 387         (unspec_volatile:GPR
 388           [(minus:GPR (match_dup 1) (match_dup 2))]
 389          UNSPEC_SYNC_NEW_OP))]
 390   "GENERATE_LL_SC"
 391 {
 392   return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>subu"));
 393 }
 394   [(set_attr "length" "28")])
 395
 396 (define_insn "sync_<optab><mode>"
 397   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
 398         (unspec_volatile:GPR
 399           [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
 400                               (match_dup 0))]
 401          UNSPEC_SYNC_OLD_OP))]
 402   "GENERATE_LL_SC"
 403 {
 404   if (which_alternative == 0)
 405     return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<immediate_insn>"));
 406   else
 407     return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<insn>"));
 408 }
 409   [(set_attr "length" "28")])
 410
 411 (define_insn "sync_old_<optab><mode>"
 412   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 413         (match_operand:GPR 1 "memory_operand" "+R,R"))
 414    (set (match_dup 1)
 415         (unspec_volatile:GPR
 416           [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
 417                             (match_dup 1))]
 418          UNSPEC_SYNC_OLD_OP))]
 419   "GENERATE_LL_SC"
 420 {
 421   if (which_alternative == 0)
 422     return (mips_output_sync_loop
 423             (MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>")));
 424   else
 425     return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<insn>"));
 426 }
 427   [(set_attr "length" "28")])
 428
 429 (define_insn "sync_new_<optab><mode>"
 430   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 431         (match_operand:GPR 1 "memory_operand" "+R,R"))
 432    (set (match_dup 1)
 433         (unspec_volatile:GPR
 434           [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
 435                             (match_dup 1))]
 436          UNSPEC_SYNC_NEW_OP))]
 437   "GENERATE_LL_SC"
 438 {
 439   if (which_alternative == 0)
 440     return (mips_output_sync_loop
 441             (MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>")));
 442   else
 443     return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<insn>"));
 444 }
 445   [(set_attr "length" "28")])
 446
 447 (define_insn "sync_nand<mode>"
 448   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
 449         (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
 450          UNSPEC_SYNC_OLD_OP))]
 451   "GENERATE_LL_SC"
 452 {
 453   if (which_alternative == 0)
 454     return mips_output_sync_loop (MIPS_SYNC_NAND ("<d>", "andi"));
 455   else
 456     return mips_output_sync_loop (MIPS_SYNC_NAND ("<d>", "and"));
 457 }
 458   [(set_attr "length" "32")])
 459
 460 (define_insn "sync_old_nand<mode>"
 461   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 462         (match_operand:GPR 1 "memory_operand" "+R,R"))
 463    (set (match_dup 1)
 464         (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
 465          UNSPEC_SYNC_OLD_OP))]
 466   "GENERATE_LL_SC"
 467 {
 468   if (which_alternative == 0)
 469     return mips_output_sync_loop (MIPS_SYNC_OLD_NAND ("<d>", "andi"));
 470   else
 471     return mips_output_sync_loop (MIPS_SYNC_OLD_NAND ("<d>", "and"));
 472 }
 473   [(set_attr "length" "32")])
 474
 475 (define_insn "sync_new_nand<mode>"
 476   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 477         (match_operand:GPR 1 "memory_operand" "+R,R"))
 478    (set (match_dup 1)
 479         (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
 480          UNSPEC_SYNC_NEW_OP))]
 481   "GENERATE_LL_SC"
 482 {
 483   if (which_alternative == 0)
 484     return mips_output_sync_loop (MIPS_SYNC_NEW_NAND ("<d>", "andi"));
 485   else
 486     return mips_output_sync_loop (MIPS_SYNC_NEW_NAND ("<d>", "and"));
 487 }
 488   [(set_attr "length" "32")])
 489
 490 (define_insn "sync_lock_test_and_set<mode>"
 491   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 492         (match_operand:GPR 1 "memory_operand" "+R,R"))
 493    (set (match_dup 1)
 494         (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
 495          UNSPEC_SYNC_EXCHANGE))]
 496   "GENERATE_LL_SC"
 497 {
 498   if (which_alternative == 0)
 499     return mips_output_sync_loop (MIPS_SYNC_EXCHANGE ("<d>", "li"));
 500   else
 501     return mips_output_sync_loop (MIPS_SYNC_EXCHANGE ("<d>", "move"));
 502 }
 503   [(set_attr "length" "24")])
 504
 505 (define_expand "sync_lock_test_and_set<mode>"
 506   [(match_operand:SHORT 0 "register_operand")
 507    (match_operand:SHORT 1 "memory_operand")
 508    (match_operand:SHORT 2 "general_operand")]
 509   "GENERATE_LL_SC"
 510 {
 511   union mips_gen_fn_ptrs generator;
 512   generator.fn_5 = gen_test_and_set_12;
 513   mips_expand_atomic_qihi (generator,
 514                            operands[0], operands[1], operands[2], NULL);
 515   DONE;
 516 })
 517
 518 (define_insn "test_and_set_12"
 519   [(set (match_operand:SI 0 "register_operand" "=&d,&d")
 520         (match_operand:SI 1 "memory_operand" "+R,R"))
 521    (set (match_dup 1)
 522         (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
 523                              (match_operand:SI 3 "register_operand" "d,d")
 524                              (match_operand:SI 4 "arith_operand" "d,J")]
 525           UNSPEC_SYNC_EXCHANGE_12))]
 526   "GENERATE_LL_SC"
 527 {
 528   if (which_alternative == 0)
 529     return (mips_output_sync_loop
 530             (MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP)));
 531   else
 532     return (mips_output_sync_loop
 533             (MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP)));
 534 }
 535   [(set_attr "length" "28,24")])