gcc/config/mips/sr71k.md

   1 ;; .........................
   2 ;;
   3 ;; DFA-based pipeline description for Sandcraft SR3 (MIPS64 based)
   4 ;;
   5 ;; The SR3 is describeds as:
   6 ;;     - nine-stage pipeline, insn buffering with out-of-order issue to
   7 ;;       multiple function units, with an average dispatch rate of 2
   8 ;;       insn.s per cycle (max 6 insns: 2 fpu, 4 cpu).
   9 ;;
  10 ;;  The details on this are scant except for a diagram in
  11 ;;  Chap. 6 of Rev. 1.0 SR3 Spec.
  12 ;;
  13 ;;  The model employed below is designed to closely approximate the
  14 ;;  published latencies. Emulation of out-of-order issue and the insn
  15 ;;  buffering is done via a VLIW dispatch style (with a packing of 6 insns);
  16 ;;  the function unit reservations restrictions (define_*_set) are
  17 ;;  contrived to support published timings.
  18 ;;
  19 ;; Reference:
  20 ;;   "SR3 Microporocessor Specification, System development information,"
  21 ;;   Revision 1.0, 13 December 2000.
  22 ;;
  23 ;;
  24 ;; Reservation model is based on:
  25 ;;   1) Figure 6-1, from the 1.0 specicification.
  26 ;;   2) Chapter 19, from the 1.0 specificication.
  27 ;;   3) following questions(Red Hat)/answers(Sandcraft):
  28 ;;     RH> From Section 19.1
  29 ;;     RH>      1) In terms of figure 6-1, are all the instructions in
  30 ;;     RH>         table 19-1 restricted
  31 ;;     RH>         to ALUx? When ALUx is not in use for an instruction in table;;     RH>          19-1 is
  32 ;;     RH>         it fully compatible with all insns that issue to ALUy?
  33 ;;
  34 ;;     Yes, all the instructions in Table 19-1 only go to ALUX, and all the
  35 ;;     instructions that can be issued to ALUY can also be issued to ALUX.
  36 ;;
  37 ;;
  38 ;;     RH> From Section 19.2
  39 ;;     RH>      2) Explain conditional moves execution path (in terms of
  40 ;;     RH>      figure 6-1)
  41 ;;
  42 ;;     Conditional move of integer registers (based on floating point condition
  43 ;;     codes or integer register value) go to ALUX or ALUY.
  44 ;;
  45 ;;     RH>      3) Explain floating point store execution path (in terms of
  46 ;;     RH>      figure 6-1)
  47 ;;
  48 ;;     Floating point stores go to Ld/St and go to MOV in the floating point
  49 ;;     pipeline.
  50 ;;
  51 ;;     Floating point loads go to Ld/St and go to LOAD in the floating point
  52 ;;     pipeline.
  53 ;;
  54 ;;     RH>      4) Explain branch on floating condition (in terms of figure 6-1);;
  55 ;;     Branch on floating condition go to BRU.
  56 ;;
  57 ;;     RH>      5) Is the column for single RECIP instruction latency correct?
  58 ;;     RH>      What about for RSQRT single and double?
  59 ;;
  60 ;;     The latency/repeat for RECIP and RSQRT are correct.
  61 ;;
  62
  63 ;;
  64 ;; Use four automata to isolate long latency operations, and to
  65 ;; reduce the complexity of cpu+fpu, reducing space.
  66 ;;
  67 (define_automaton "sr71_cpu, sr71_cpu1, sr71_cp1, sr71_cp2, sr71_fextra, sr71_imacc")
  68
  69 ;;  feeders for CPU function units and feeders for fpu (CP1 interface)
  70 (define_cpu_unit "sr_iss0,sr_iss1,sr_iss2,sr_iss3,sr_iss4,sr_iss5" "sr71_cpu")
  71
  72 ;; CPU function units
  73 (define_cpu_unit "ipu_bru"       "sr71_cpu1")
  74 (define_cpu_unit "ipu_alux"      "sr71_cpu1")
  75 (define_cpu_unit "ipu_aluy"      "sr71_cpu1")
  76 (define_cpu_unit "ipu_ldst"      "sr71_cpu1")
  77 (define_cpu_unit "ipu_macc_iter" "sr71_imacc")
  78
  79
  80 ;; Floating-point unit (Co-processor interface 1).
  81 (define_cpu_unit "fpu_mov"          "sr71_cp1")
  82 (define_cpu_unit "fpu_load"         "sr71_cp1")
  83 (define_cpu_unit "fpu_fpu"          "sr71_cp2")
  84
  85 ;; fictitous unit to track long float insns with separate automaton
  86 (define_cpu_unit "fpu_iter"         "sr71_fextra")
  87
  88
  89 ;;
  90 ;; Define common execution path (reservation) combinations
  91 ;;
  92
  93 ;;
  94 (define_reservation "cpu_iss"         "sr_iss0|sr_iss1|sr_iss2|sr_iss3")
  95
  96 ;; two cycles are used for instruction using the fpu as it runs
  97 ;; at half the clock speed of the cpu. By adding an extra cycle
  98 ;; to the issue units, the default/minimum "repeat" dispatch delay is
  99 ;; accounted for all insn.s
 100 (define_reservation "cp1_iss"         "(sr_iss4*2)|(sr_iss5*2)")
 101
 102 (define_reservation "serial_dispatch" "sr_iss0+sr_iss1+sr_iss2+sr_iss3+sr_iss4+sr_iss5")
 103
 104 ;; Simulate a 6 insn VLIW dispatch, 1 cycle in dispatch followed by
 105 ;; reservation of function unit.
 106 (define_reservation "ri_insns"         "cpu_iss,(ipu_alux|ipu_aluy)")
 107 (define_reservation "ri_mem"           "cpu_iss,ipu_ldst")
 108 (define_reservation "ri_alux"          "cpu_iss,ipu_alux")
 109 (define_reservation "ri_branch"        "cpu_iss,ipu_bru")
 110
 111 (define_reservation "rf_insn"          "cp1_iss,fpu_fpu")
 112 (define_reservation "rf_ldmem"         "cp1_iss,fpu_load")
 113
 114 ; simultaneous reservation of pseudo-unit keeps cp1 fpu tied
 115 ; up until long cycle insn is finished...
 116 (define_reservation "rf_multi1"        "rf_insn+fpu_iter")
 117
 118 ;;
 119 ;; The ordering of the instruction-execution-path/resource-usage
 120 ;; descriptions (also known as reservation RTL) is roughly ordered
 121 ;; based on the define attribute RTL for the "type" classification.
 122 ;; When modifying, remember that the first test that matches is the
 123 ;; reservation used!
 124 ;;
 125
 126
 127 (define_insn_reservation "ir_sr70_unknown"
 128                                1
 129                           (and (eq_attr "cpu" "sr71000")
 130                                (eq_attr "type" "unknown"))
 131                          "serial_dispatch")
 132
 133
 134 ;; Assume prediction fails.
 135 (define_insn_reservation "ir_sr70_branch"
 136                                6
 137                           (and (eq_attr "cpu" "sr71000")
 138                                (eq_attr "type" "branch,jump,call"))
 139                          "ri_branch")
 140
 141 (define_insn_reservation "ir_sr70_load"
 142                                2
 143                           (and (eq_attr "cpu" "sr71000")
 144                                (and (eq_attr "type" "load")
 145                                     (eq_attr "mode" "!SF,DF,FPSW")))
 146                          "ri_mem")
 147
 148 (define_insn_reservation "ir_sr70_store"
 149                                1
 150                           (and (eq_attr "cpu" "sr71000")
 151                                (and (eq_attr "type" "store")
 152                                     (eq_attr "mode" "!SF,DF,FPSW")))
 153                          "ri_mem")
 154
 155
 156 ;;
 157 ;; float loads/stores flow through both cpu and cp1...
 158 ;;
 159 (define_insn_reservation "ir_sr70_fload"
 160                                9
 161                           (and (eq_attr "cpu" "sr71000")
 162                                (and (eq_attr "type" "load")
 163                                     (eq_attr "mode" "SF,DF")))
 164                          "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
 165
 166 (define_insn_reservation "ir_sr70_fstore"
 167                                1
 168                           (and (eq_attr "cpu" "sr71000")
 169                                (and (eq_attr "type" "store")
 170                                     (eq_attr "mode" "SF,DF")))
 171                          "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
 172
 173
 174 ;; This reservation is for conditional move based on integer
 175 ;; or floating point CC.  This could probably use some refinement
 176 ;; as "move" type attr seems to be overloaded in rtl.
 177 (define_insn_reservation "ir_sr70_move"
 178                                4
 179                           (and (eq_attr "cpu" "sr71000")
 180                                (eq_attr "type" "move"))
 181                          "ri_insns")
 182
 183 ;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
 184 ;; are different. Like float load/store, these insns use multiple
 185 ;; resources simultaneously
 186 (define_insn_reservation "ir_sr70_xfer_from"
 187                                6
 188                           (and (eq_attr "cpu" "sr71000")
 189                                (and (eq_attr "type" "xfer")
 190                                     (eq_attr "mode" "!SF,DF,FPSW")))
 191                          "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
 192
 193 (define_insn_reservation "ir_sr70_xfer_to"
 194                                9
 195                           (and (eq_attr "cpu" "sr71000")
 196                                (and (eq_attr "type" "xfer")
 197                                     (eq_attr "mode" "SF,DF")))
 198                          "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
 199
 200 (define_insn_reservation "ir_sr70_hilo"
 201                                1
 202                           (and (eq_attr "cpu" "sr71000")
 203                                (eq_attr "type" "hilo"))
 204                          "ri_insns")
 205
 206 (define_insn_reservation "ir_sr70_arith"
 207                                1
 208                           (and (eq_attr "cpu" "sr71000")
 209                                (eq_attr "type" "arith,darith,const"))
 210                          "ri_insns")
 211
 212 ;; emulate repeat (dispatch stall) by spending extra cycle(s) in
 213 ;; in iter unit
 214 (define_insn_reservation "ir_sr70_imul_si"
 215                                  4
 216                           (and (eq_attr "cpu" "sr71000")
 217                                (and (eq_attr "type" "imul,imadd")
 218                                     (eq_attr "mode" "SI")))
 219                          "ri_alux,ipu_alux,ipu_macc_iter")
 220
 221 (define_insn_reservation "ir_sr70_imul_di"
 222                                  6
 223                           (and (eq_attr "cpu" "sr71000")
 224                                (and (eq_attr "type" "imul,imadd")
 225                                     (eq_attr "mode" "DI")))
 226                          "ri_alux,ipu_alux,(ipu_macc_iter*3)")
 227
 228 ;; Divide algorithm is early out with best latency of 7 pcycles.
 229 ;; Use worst case for scheduling purposes.
 230 (define_insn_reservation "ir_sr70_idiv_si"
 231                                  41
 232                           (and (eq_attr "cpu" "sr71000")
 233                                (and (eq_attr "type" "idiv")
 234                                     (eq_attr "mode" "SI")))
 235                          "ri_alux,ipu_alux,(ipu_macc_iter*38)")
 236
 237 (define_insn_reservation "ir_sr70_idiv_di"
 238                                  73
 239                           (and (eq_attr "cpu" "sr71000")
 240                                (and (eq_attr "type" "idiv")
 241                                     (eq_attr "mode" "DI")))
 242                          "ri_alux,ipu_alux,(ipu_macc_iter*70)")
 243
 244 (define_insn_reservation "ir_sr70_icmp"
 245                                1
 246                           (and (eq_attr "cpu" "sr71000")
 247                                (eq_attr "type" "icmp"))
 248                          "ri_insns")
 249
 250 ;; extra reservations of fpu_fpu are for repeat latency
 251 (define_insn_reservation "ir_sr70_fadd_sf"
 252                                8
 253                           (and (eq_attr "cpu" "sr71000")
 254                                (and (eq_attr "type" "fadd")
 255                                     (eq_attr "mode" "SF")))
 256                          "rf_insn,fpu_fpu")
 257
 258 (define_insn_reservation "ir_sr70_fadd_df"
 259                                10
 260                           (and (eq_attr "cpu" "sr71000")
 261                                (and (eq_attr "type" "fadd")
 262                                     (eq_attr "mode" "DF")))
 263                          "rf_insn,fpu_fpu")
 264
 265 ;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
 266 ;; with the sub or add.
 267 (define_insn_reservation "ir_sr70_fmul_sf"
 268                                8
 269                           (and (eq_attr "cpu" "sr71000")
 270                                (and (eq_attr "type" "fmul,fmadd")
 271                                     (eq_attr "mode" "SF")))
 272                          "rf_insn,fpu_fpu")
 273
 274 ;; tie up the fpu unit to emulate the balance for the "repeat
 275 ;; rate" of 8 (2 are spent in the iss unit)
 276 (define_insn_reservation "ir_sr70_fmul_df"
 277                                16
 278                           (and (eq_attr "cpu" "sr71000")
 279                                (and (eq_attr "type" "fmul,fmadd")
 280                                     (eq_attr "mode" "DF")))
 281                          "rf_insn,fpu_fpu*6")
 282
 283
 284 ;; RECIP insn uses same type attr as div, and for SR3, has same
 285 ;; timings for double. However, single RECIP has a latency of
 286 ;; 28 -- only way to fix this is to introduce new insn attrs.
 287 ;; cycles spent in iter unit are designed to satisfy balance
 288 ;; of "repeat" latency after insn uses up rf_multi1 reservation
 289 (define_insn_reservation "ir_sr70_fdiv_sf"
 290                                 60
 291                           (and (eq_attr "cpu" "sr71000")
 292                                (and (eq_attr "type" "fdiv")
 293                                     (eq_attr "mode" "SF")))
 294                          "rf_multi1+(fpu_iter*51)")
 295
 296 (define_insn_reservation "ir_sr70_fdiv_df"
 297                                 120
 298                           (and (eq_attr "cpu" "sr71000")
 299                                (and (eq_attr "type" "fdiv")
 300                                     (eq_attr "mode" "DF")))
 301                          "rf_multi1+(fpu_iter*109)")
 302
 303 (define_insn_reservation "ir_sr70_fabs"
 304                                4
 305                           (and (eq_attr "cpu" "sr71000")
 306                                (eq_attr "type" "fabs,fneg"))
 307                          "rf_insn,fpu_fpu")
 308
 309 (define_insn_reservation "ir_sr70_fcmp"
 310                                10
 311                           (and (eq_attr "cpu" "sr71000")
 312                                (eq_attr "type" "fcmp"))
 313                          "rf_insn,fpu_fpu")
 314
 315 ;; "fcvt" type attribute covers a number of diff insns, most have the same
 316 ;; latency descriptions, a few vary. We use the
 317 ;; most common timing (which is also worst case).
 318 (define_insn_reservation "ir_sr70_fcvt"
 319                                12
 320                           (and (eq_attr "cpu" "sr71000")
 321                                (eq_attr "type" "fcvt"))
 322                          "rf_insn,fpu_fpu*4")
 323
 324 (define_insn_reservation "ir_sr70_fsqrt_sf"
 325                                 62
 326                           (and (eq_attr "cpu" "sr71000")
 327                                (and (eq_attr "type" "fsqrt")
 328                                     (eq_attr "mode" "SF")))
 329                          "rf_multi1+(fpu_iter*53)")
 330
 331 (define_insn_reservation "ir_sr70_fsqrt_df"
 332                                 122
 333                           (and (eq_attr "cpu" "sr71000")
 334                                (and (eq_attr "type" "fsqrt")
 335                                     (eq_attr "mode" "DF")))
 336                          "rf_multi1+(fpu_iter*111)")
 337
 338 (define_insn_reservation "ir_sr70_frsqrt_sf"
 339                                 48
 340                           (and (eq_attr "cpu" "sr71000")
 341                                (and (eq_attr "type" "frsqrt")
 342                                     (eq_attr "mode" "SF")))
 343                          "rf_multi1+(fpu_iter*39)")
 344
 345 (define_insn_reservation "ir_sr70_frsqrt_df"
 346                                 240
 347                           (and (eq_attr "cpu" "sr71000")
 348                                (and (eq_attr "type" "frsqrt")
 349                                     (eq_attr "mode" "DF")))
 350                          "rf_multi1+(fpu_iter*229)")
 351
 352 (define_insn_reservation "ir_sr70_multi"
 353                                1
 354                           (and (eq_attr "cpu" "sr71000")
 355                                (eq_attr "type" "multi"))
 356                          "serial_dispatch")
 357
 358 (define_insn_reservation "ir_sr70_nop"
 359                                1
 360                           (and (eq_attr "cpu" "sr71000")
 361                                (eq_attr "type" "nop"))
 362                          "ri_insns")