1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
24 ;; Boston, MA 02111-1307, USA.
26 ;; ??? Currently does not have define_function_unit support for the R8000.
27 ;; Must include new entries for fmadd in addition to existing entries.
30 [(UNSPEC_LOAD_DF_LOW 0)
31 (UNSPEC_LOAD_DF_HIGH 1)
32 (UNSPEC_STORE_DF_HIGH 2)
36 (UNSPEC_EH_RECEIVER 6)
38 (UNSPEC_CONSTTABLE_QI 8)
39 (UNSPEC_CONSTTABLE_HI 9)
40 (UNSPEC_CONSTTABLE_SI 10)
41 (UNSPEC_CONSTTABLE_DI 11)
42 (UNSPEC_CONSTTABLE_SF 12)
43 (UNSPEC_CONSTTABLE_DF 13)
58 (UNSPEC_ADDRESS_FIRST 100)])
60 ;; ....................
64 ;; ....................
66 (define_attr "got" "unset,xgot_high,load"
67 (const_string "unset"))
69 ;; For jal instructions, this attribute is DIRECT when the target address
70 ;; is symbolic and INDIRECT when it is a register.
71 (define_attr "jal" "unset,direct,indirect"
72 (const_string "unset"))
74 ;; This attribute is YES if the instruction is a jal macro (not a
75 ;; real jal instruction).
77 ;; jal is always a macro in SVR4 PIC since it includes an instruction to
78 ;; restore $gp. Direct jals are also macros in NewABI PIC since they
79 ;; load the target address into $25.
80 (define_attr "jal_macro" "no,yes"
81 (cond [(eq_attr "jal" "direct")
82 (symbol_ref "TARGET_ABICALLS != 0")
83 (eq_attr "jal" "indirect")
84 (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")]
87 ;; Classification of each insn.
88 ;; branch conditional branch
89 ;; jump unconditional jump
90 ;; call unconditional call
91 ;; load load instruction(s)
92 ;; store store instruction(s)
93 ;; prefetch memory prefetch (register + offset)
94 ;; prefetchx memory indexed prefetch (register + register)
95 ;; move data movement within same register set
96 ;; condmove conditional moves
97 ;; xfer transfer to/from coprocessor
98 ;; hilo transfer of hi/lo registers
99 ;; arith integer arithmetic instruction
100 ;; darith double precision integer arithmetic instructions
101 ;; const load constant
102 ;; imul integer multiply
103 ;; imadd integer multiply-add
104 ;; idiv integer divide
105 ;; icmp integer compare
106 ;; fadd floating point add/subtract
107 ;; fmul floating point multiply
108 ;; fmadd floating point multiply-add
109 ;; fdiv floating point divide
110 ;; fabs floating point absolute value
111 ;; fneg floating point negation
112 ;; fcmp floating point compare
113 ;; fcvt floating point convert
114 ;; fsqrt floating point square root
115 ;; frsqrt floating point reciprocal square root
116 ;; multi multiword sequence (or user asm statements)
119 "unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
120 (cond [(eq_attr "jal" "!unset") (const_string "call")
121 (eq_attr "got" "load") (const_string "load")]
122 (const_string "unknown")))
124 ;; Main data type used by the insn
125 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
126 (const_string "unknown"))
128 ;; Is this an extended instruction in mips16 mode?
129 (define_attr "extended_mips16" "no,yes"
132 ;; Length of instruction in bytes.
133 (define_attr "length" ""
134 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
135 ;; If a branch is outside this range, we have a choice of two
136 ;; sequences. For PIC, an out-of-range branch like:
141 ;; becomes the equivalent of:
150 ;; where the load address can be up to three instructions long
153 ;; The non-PIC case is similar except that we use a direct
154 ;; jump instead of an la/jr pair. Since the target of this
155 ;; jump is an absolute 28-bit bit address (the other bits
156 ;; coming from the address of the delay slot) this form cannot
157 ;; cross a 256MB boundary. We could provide the option of
158 ;; using la/jr in this case too, but we do not do so at
161 ;; Note that this value does not account for the delay slot
162 ;; instruction, whose length is added separately. If the RTL
163 ;; pattern has no explicit delay slot, mips_adjust_insn_length
164 ;; will add the length of the implicit nop.
165 (eq_attr "type" "branch")
166 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
169 (ne (symbol_ref "flag_pic && ! TARGET_EMBEDDED_PIC")
174 (eq_attr "got" "load")
176 (eq_attr "got" "xgot_high")
179 (eq_attr "type" "const")
180 (symbol_ref "mips_const_insns (operands[1]) * 4")
181 (eq_attr "type" "load")
182 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
183 (eq_attr "type" "store")
184 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
186 ;; In the worst case, a call macro will take 8 instructions:
188 ;; lui $25,%call_hi(FOO)
190 ;; lw $25,%call_lo(FOO)($25)
196 (eq_attr "jal_macro" "yes")
199 (and (eq_attr "extended_mips16" "yes")
200 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
203 (and (eq_attr "type" "idiv")
204 (ne (symbol_ref "TARGET_CHECK_ZERO_DIV") (const_int 0)))
205 (cond [(ne (symbol_ref "TARGET_MIPS16") (const_int 0))
210 ;; Attribute describing the processor. This attribute must match exactly
211 ;; with the processor_type enumeration in mips.h.
213 "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
214 (const (symbol_ref "mips_tune")))
216 ;; The type of hardware hazard associated with this instruction.
217 ;; DELAY means that the next instruction cannot read the result
218 ;; of this one. HILO means that the next two instructions cannot
219 ;; write to HI or LO.
220 (define_attr "hazard" "none,delay,hilo"
221 (cond [(and (eq_attr "type" "load")
222 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
223 (const_string "delay")
225 (and (eq_attr "type" "xfer")
226 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
227 (const_string "delay")
229 (and (eq_attr "type" "fcmp")
230 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
231 (const_string "delay")
233 ;; The r4000 multiplication patterns include an mflo instruction.
234 (and (eq_attr "type" "imul")
235 (ne (symbol_ref "TARGET_MIPS4000") (const_int 0)))
236 (const_string "hilo")
238 (and (eq_attr "type" "hilo")
239 (and (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0))
240 (match_operand 1 "hilo_operand" "")))
241 (const_string "hilo")]
242 (const_string "none")))
244 ;; Is it a single instruction?
245 (define_attr "single_insn" "no,yes"
246 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
248 ;; Can the instruction be put into a delay slot?
249 (define_attr "can_delay" "no,yes"
250 (if_then_else (and (eq_attr "type" "!branch,call,jump")
251 (and (eq_attr "hazard" "none")
252 (eq_attr "single_insn" "yes")))
254 (const_string "no")))
256 ;; Attribute defining whether or not we can use the branch-likely instructions
257 (define_attr "branch_likely" "no,yes"
259 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
261 (const_string "no"))))
263 ;; Describe a user's asm statement.
264 (define_asm_attributes
265 [(set_attr "type" "multi")])
267 ;; .........................
269 ;; Branch, call and jump delay slots
271 ;; .........................
273 (define_delay (and (eq_attr "type" "branch")
274 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
275 [(eq_attr "can_delay" "yes")
277 (and (eq_attr "branch_likely" "yes")
278 (eq_attr "can_delay" "yes"))])
280 (define_delay (eq_attr "type" "jump")
281 [(eq_attr "can_delay" "yes")
285 (define_delay (and (eq_attr "type" "call")
286 (eq_attr "jal_macro" "no"))
287 [(eq_attr "can_delay" "yes")
291 ;; .........................
295 ;; .........................
297 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
298 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
300 ;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
302 (define_function_unit "memory" 1 0
303 (and (eq_attr "type" "load")
304 (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
307 (define_function_unit "memory" 1 0
308 (and (eq_attr "type" "load")
309 (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
312 (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
314 (define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
316 (define_function_unit "imuldiv" 1 0
317 (eq_attr "type" "hilo")
320 (define_function_unit "imuldiv" 1 0
321 (and (eq_attr "type" "imul,imadd")
322 (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
325 ;; On them mips16, we want to stronly discourage a mult from appearing
326 ;; after an mflo, since that requires explicit nop instructions. We
327 ;; do this by pretending that mflo ties up the function unit for long
328 ;; enough that the scheduler will ignore load stalls and the like when
329 ;; selecting instructions to between the two instructions.
331 (define_function_unit "imuldiv" 1 0
332 (and (eq_attr "type" "hilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
335 (define_function_unit "imuldiv" 1 0
336 (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3000,r3900"))
339 (define_function_unit "imuldiv" 1 0
340 (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4000,r4600"))
343 (define_function_unit "imuldiv" 1 0
344 (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4650"))
347 (define_function_unit "imuldiv" 1 0
348 (and (eq_attr "type" "imul,imadd")
349 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
352 (define_function_unit "imuldiv" 1 0
353 (and (eq_attr "type" "imul,imadd")
354 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
357 (define_function_unit "imuldiv" 1 0
358 (and (eq_attr "type" "imul,imadd")
359 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
362 (define_function_unit "imuldiv" 1 0
363 (and (eq_attr "type" "imul,imadd")
364 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
367 (define_function_unit "imuldiv" 1 0
368 (and (eq_attr "type" "imul,imadd")
369 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
372 (define_function_unit "imuldiv" 1 0
373 (and (eq_attr "type" "idiv")
374 (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
377 (define_function_unit "imuldiv" 1 0
378 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
381 (define_function_unit "imuldiv" 1 0
382 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
385 (define_function_unit "imuldiv" 1 0
386 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
389 (define_function_unit "imuldiv" 1 0
390 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
393 (define_function_unit "imuldiv" 1 0
394 (and (eq_attr "type" "idiv")
395 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
398 (define_function_unit "imuldiv" 1 0
399 (and (eq_attr "type" "idiv")
400 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
403 (define_function_unit "imuldiv" 1 0
404 (and (eq_attr "type" "idiv")
405 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
408 (define_function_unit "imuldiv" 1 0
409 (and (eq_attr "type" "idiv")
410 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
413 (define_function_unit "imuldiv" 1 0
414 (and (eq_attr "type" "idiv")
415 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
418 (define_function_unit "imuldiv" 1 0
419 (and (eq_attr "type" "idiv")
420 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
423 ;; The R4300 does *NOT* have a separate Floating Point Unit, instead
424 ;; the FP hardware is part of the normal ALU circuitry. This means FP
425 ;; instructions affect the pipe-line, and no functional unit
426 ;; parallelism can occur on R4300 processors. To force GCC into coding
427 ;; for only a single functional unit, we force the R4300 FP
428 ;; instructions to be processed in the "imuldiv" unit.
430 (define_function_unit "adder" 1 1
431 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
434 (define_function_unit "adder" 1 1
435 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
438 (define_function_unit "adder" 1 1
439 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
442 (define_function_unit "adder" 1 1
443 (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
446 (define_function_unit "adder" 1 1
447 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
450 (define_function_unit "adder" 1 1
451 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
454 (define_function_unit "adder" 1 1
455 (and (eq_attr "type" "fabs,fneg")
456 (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
459 (define_function_unit "adder" 1 1
460 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
463 (define_function_unit "mult" 1 1
464 (and (eq_attr "type" "fmul")
465 (and (eq_attr "mode" "SF")
466 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
469 (define_function_unit "mult" 1 1
470 (and (eq_attr "type" "fmul")
471 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
474 (define_function_unit "mult" 1 1
475 (and (eq_attr "type" "fmul")
476 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
479 (define_function_unit "mult" 1 1
480 (and (eq_attr "type" "fmul")
481 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
484 (define_function_unit "mult" 1 1
485 (and (eq_attr "type" "fmul")
486 (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
489 (define_function_unit "mult" 1 1
490 (and (eq_attr "type" "fmul")
491 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
494 (define_function_unit "mult" 1 1
495 (and (eq_attr "type" "fmul")
496 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
499 (define_function_unit "divide" 1 1
500 (and (eq_attr "type" "fdiv")
501 (and (eq_attr "mode" "SF")
502 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
505 (define_function_unit "divide" 1 1
506 (and (eq_attr "type" "fdiv")
507 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
510 (define_function_unit "divide" 1 1
511 (and (eq_attr "type" "fdiv")
512 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
515 (define_function_unit "divide" 1 1
516 (and (eq_attr "type" "fdiv")
517 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
520 (define_function_unit "divide" 1 1
521 (and (eq_attr "type" "fdiv")
522 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
525 (define_function_unit "divide" 1 1
526 (and (eq_attr "type" "fdiv")
527 (and (eq_attr "mode" "DF")
528 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
531 (define_function_unit "divide" 1 1
532 (and (eq_attr "type" "fdiv")
533 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
536 (define_function_unit "divide" 1 1
537 (and (eq_attr "type" "fdiv")
538 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
541 (define_function_unit "divide" 1 1
542 (and (eq_attr "type" "fdiv")
543 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
546 ;;; ??? Is this number right?
547 (define_function_unit "divide" 1 1
548 (and (eq_attr "type" "fsqrt,frsqrt")
549 (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
552 (define_function_unit "divide" 1 1
553 (and (eq_attr "type" "fsqrt,frsqrt")
554 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
557 (define_function_unit "divide" 1 1
558 (and (eq_attr "type" "fsqrt,frsqrt")
559 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
562 ;;; ??? Is this number right?
563 (define_function_unit "divide" 1 1
564 (and (eq_attr "type" "fsqrt,frsqrt")
565 (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
568 (define_function_unit "divide" 1 1
569 (and (eq_attr "type" "fsqrt,frsqrt")
570 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
573 (define_function_unit "divide" 1 1
574 (and (eq_attr "type" "fsqrt,frsqrt")
575 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
578 ;; R4300 FP instruction classes treated as part of the "imuldiv"
581 (define_function_unit "imuldiv" 1 0
582 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
585 (define_function_unit "imuldiv" 1 0
586 (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300"))
589 (define_function_unit "imuldiv" 1 0
590 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
592 (define_function_unit "imuldiv" 1 0
593 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
596 (define_function_unit "imuldiv" 1 0
597 (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
598 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
600 (define_function_unit "imuldiv" 1 0
601 (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
602 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
605 ;; Include scheduling descriptions.
614 ;; ....................
618 ;; ....................
622 [(trap_if (const_int 1) (const_int 0))]
625 if (ISA_HAS_COND_TRAP)
627 /* The IRIX 6 O32 assembler requires the first break operand. */
628 else if (TARGET_MIPS16 || !TARGET_GAS)
634 (define_expand "conditional_trap"
635 [(trap_if (match_operator 0 "cmp_op"
636 [(match_dup 2) (match_dup 3)])
637 (match_operand 1 "const_int_operand" ""))]
640 if (operands[1] == const0_rtx)
642 mips_gen_conditional_trap (operands);
650 [(trap_if (match_operator 0 "trap_cmp_op"
651 [(match_operand:SI 1 "reg_or_0_operand" "dJ")
652 (match_operand:SI 2 "arith_operand" "dI")])
658 [(trap_if (match_operator 0 "trap_cmp_op"
659 [(match_operand:DI 1 "reg_or_0_operand" "dJ")
660 (match_operand:DI 2 "arith_operand" "dI")])
662 "TARGET_64BIT && ISA_HAS_COND_TRAP"
666 ;; ....................
670 ;; ....................
673 (define_insn "adddf3"
674 [(set (match_operand:DF 0 "register_operand" "=f")
675 (plus:DF (match_operand:DF 1 "register_operand" "f")
676 (match_operand:DF 2 "register_operand" "f")))]
677 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
679 [(set_attr "type" "fadd")
680 (set_attr "mode" "DF")])
682 (define_insn "addsf3"
683 [(set (match_operand:SF 0 "register_operand" "=f")
684 (plus:SF (match_operand:SF 1 "register_operand" "f")
685 (match_operand:SF 2 "register_operand" "f")))]
688 [(set_attr "type" "fadd")
689 (set_attr "mode" "SF")])
691 (define_expand "addsi3"
692 [(set (match_operand:SI 0 "register_operand" "")
693 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
694 (match_operand:SI 2 "arith_operand" "")))]
697 /* If a large stack adjustment was forced into a register, we may be
698 asked to generate rtx such as:
700 (set (reg:SI sp) (plus:SI (reg:SI sp) (reg:SI pseudo)))
702 but no such instruction is available in mips16. Handle it by
703 using a temporary. */
705 && REGNO (operands[0]) == STACK_POINTER_REGNUM
706 && ((GET_CODE (operands[1]) == REG
707 && REGNO (operands[1]) != STACK_POINTER_REGNUM)
708 || GET_CODE (operands[2]) != CONST_INT))
710 rtx tmp = gen_reg_rtx (SImode);
712 emit_move_insn (tmp, operands[1]);
713 emit_insn (gen_addsi3 (tmp, tmp, operands[2]));
714 emit_move_insn (operands[0], tmp);
719 (define_insn "addsi3_internal"
720 [(set (match_operand:SI 0 "register_operand" "=d,d")
721 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
722 (match_operand:SI 2 "arith_operand" "d,Q")))]
727 [(set_attr "type" "arith")
728 (set_attr "mode" "SI")])
730 ;; For the mips16, we need to recognize stack pointer additions
731 ;; explicitly, since we don't have a constraint for $sp. These insns
732 ;; will be generated by the save_restore_insns functions.
737 (match_operand:SI 0 "small_int" "I")))]
740 [(set_attr "type" "arith")
741 (set_attr "mode" "SI")
742 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
747 [(set (match_operand:SI 0 "register_operand" "=d")
749 (match_operand:SI 1 "small_int" "I")))]
752 [(set_attr "type" "arith")
753 (set_attr "mode" "SI")
754 (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
759 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
760 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
761 (match_operand:SI 2 "arith_operand" "Q,O,d")))]
763 && (GET_CODE (operands[1]) != REG
764 || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
765 || M16_REG_P (REGNO (operands[1]))
766 || REGNO (operands[1]) == ARG_POINTER_REGNUM
767 || REGNO (operands[1]) == FRAME_POINTER_REGNUM
768 || REGNO (operands[1]) == STACK_POINTER_REGNUM)
769 && (GET_CODE (operands[2]) != REG
770 || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
771 || M16_REG_P (REGNO (operands[2]))
772 || REGNO (operands[2]) == ARG_POINTER_REGNUM
773 || REGNO (operands[2]) == FRAME_POINTER_REGNUM
774 || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
776 if (REGNO (operands[0]) == REGNO (operands[1]))
777 return "addu\t%0,%2";
779 return "addu\t%0,%1,%2";
781 [(set_attr "type" "arith")
782 (set_attr "mode" "SI")
783 (set_attr_alternative "length"
784 [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
787 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
793 ;; On the mips16, we can sometimes split an add of a constant which is
794 ;; a 4 byte instruction into two adds which are both 2 byte
795 ;; instructions. There are two cases: one where we are adding a
796 ;; constant plus a register to another register, and one where we are
797 ;; simply adding a constant to a register.
800 [(set (match_operand:SI 0 "register_operand" "")
801 (plus:SI (match_dup 0)
802 (match_operand:SI 1 "const_int_operand" "")))]
803 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
804 && GET_CODE (operands[0]) == REG
805 && M16_REG_P (REGNO (operands[0]))
806 && GET_CODE (operands[1]) == CONST_INT
807 && ((INTVAL (operands[1]) > 0x7f
808 && INTVAL (operands[1]) <= 0x7f + 0x7f)
809 || (INTVAL (operands[1]) < - 0x80
810 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
811 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
812 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
814 HOST_WIDE_INT val = INTVAL (operands[1]);
818 operands[1] = GEN_INT (0x7f);
819 operands[2] = GEN_INT (val - 0x7f);
823 operands[1] = GEN_INT (- 0x80);
824 operands[2] = GEN_INT (val + 0x80);
829 [(set (match_operand:SI 0 "register_operand" "")
830 (plus:SI (match_operand:SI 1 "register_operand" "")
831 (match_operand:SI 2 "const_int_operand" "")))]
832 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
833 && GET_CODE (operands[0]) == REG
834 && M16_REG_P (REGNO (operands[0]))
835 && GET_CODE (operands[1]) == REG
836 && M16_REG_P (REGNO (operands[1]))
837 && REGNO (operands[0]) != REGNO (operands[1])
838 && GET_CODE (operands[2]) == CONST_INT
839 && ((INTVAL (operands[2]) > 0x7
840 && INTVAL (operands[2]) <= 0x7 + 0x7f)
841 || (INTVAL (operands[2]) < - 0x8
842 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
843 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
844 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
846 HOST_WIDE_INT val = INTVAL (operands[2]);
850 operands[2] = GEN_INT (0x7);
851 operands[3] = GEN_INT (val - 0x7);
855 operands[2] = GEN_INT (- 0x8);
856 operands[3] = GEN_INT (val + 0x8);
860 (define_expand "adddi3"
861 [(parallel [(set (match_operand:DI 0 "register_operand" "")
862 (plus:DI (match_operand:DI 1 "register_operand" "")
863 (match_operand:DI 2 "arith_operand" "")))
864 (clobber (match_dup 3))])]
865 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
867 /* If a large stack adjustment was forced into a register, we may be
868 asked to generate rtx such as:
870 (set (reg:DI sp) (plus:DI (reg:DI sp) (reg:DI pseudo)))
872 but no such instruction is available in mips16. Handle it by
873 using a temporary. */
875 && REGNO (operands[0]) == STACK_POINTER_REGNUM
876 && ((GET_CODE (operands[1]) == REG
877 && REGNO (operands[1]) != STACK_POINTER_REGNUM)
878 || GET_CODE (operands[2]) != CONST_INT))
880 rtx tmp = gen_reg_rtx (DImode);
882 emit_move_insn (tmp, operands[1]);
883 emit_insn (gen_adddi3 (tmp, tmp, operands[2]));
884 emit_move_insn (operands[0], tmp);
890 emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
895 operands[3] = gen_reg_rtx (SImode);
898 (define_insn "adddi3_internal_1"
899 [(set (match_operand:DI 0 "register_operand" "=d,&d")
900 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
901 (match_operand:DI 2 "register_operand" "d,d")))
902 (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
903 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
905 return (REGNO (operands[0]) == REGNO (operands[1])
906 && REGNO (operands[0]) == REGNO (operands[2]))
907 ? "srl\t%3,%L0,31\;sll\t%M0,%M0,1\;sll\t%L0,%L1,1\;addu\t%M0,%M0,%3"
908 : "addu\t%L0,%L1,%L2\;sltu\t%3,%L0,%L2\;addu\t%M0,%M1,%M2\;addu\t%M0,%M0,%3";
910 [(set_attr "type" "darith")
911 (set_attr "mode" "DI")
912 (set_attr "length" "16")])
915 [(set (match_operand:DI 0 "register_operand" "")
916 (plus:DI (match_operand:DI 1 "register_operand" "")
917 (match_operand:DI 2 "register_operand" "")))
918 (clobber (match_operand:SI 3 "register_operand" ""))]
919 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
920 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
921 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
922 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
923 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
924 && (REGNO (operands[0]) != REGNO (operands[1])
925 || REGNO (operands[0]) != REGNO (operands[2]))"
927 [(set (subreg:SI (match_dup 0) 0)
928 (plus:SI (subreg:SI (match_dup 1) 0)
929 (subreg:SI (match_dup 2) 0)))
932 (ltu:SI (subreg:SI (match_dup 0) 0)
933 (subreg:SI (match_dup 2) 0)))
935 (set (subreg:SI (match_dup 0) 4)
936 (plus:SI (subreg:SI (match_dup 1) 4)
937 (subreg:SI (match_dup 2) 4)))
939 (set (subreg:SI (match_dup 0) 4)
940 (plus:SI (subreg:SI (match_dup 0) 4)
945 [(set (match_operand:DI 0 "register_operand" "")
946 (plus:DI (match_operand:DI 1 "register_operand" "")
947 (match_operand:DI 2 "register_operand" "")))
948 (clobber (match_operand:SI 3 "register_operand" ""))]
949 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
950 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
951 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
952 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
953 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
954 && (REGNO (operands[0]) != REGNO (operands[1])
955 || REGNO (operands[0]) != REGNO (operands[2]))"
957 [(set (subreg:SI (match_dup 0) 4)
958 (plus:SI (subreg:SI (match_dup 1) 4)
959 (subreg:SI (match_dup 2) 4)))
962 (ltu:SI (subreg:SI (match_dup 0) 4)
963 (subreg:SI (match_dup 2) 4)))
965 (set (subreg:SI (match_dup 0) 0)
966 (plus:SI (subreg:SI (match_dup 1) 0)
967 (subreg:SI (match_dup 2) 0)))
969 (set (subreg:SI (match_dup 0) 0)
970 (plus:SI (subreg:SI (match_dup 0) 0)
974 (define_insn "adddi3_internal_2"
975 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
976 (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
977 (match_operand:DI 2 "small_int" "P,J,N")))
978 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
979 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
981 addu\t%L0,%L1,%2\;sltu\t%3,%L0,%2\;addu\t%M0,%M1,%3
982 move\t%L0,%L1\;move\t%M0,%M1
983 subu\t%L0,%L1,%n2\;sltu\t%3,%L0,%2\;subu\t%M0,%M1,1\;addu\t%M0,%M0,%3"
984 [(set_attr "type" "darith")
985 (set_attr "mode" "DI")
986 (set_attr "length" "12,8,16")])
989 [(set (match_operand:DI 0 "register_operand" "")
990 (plus:DI (match_operand:DI 1 "register_operand" "")
991 (match_operand:DI 2 "small_int" "")))
992 (clobber (match_operand:SI 3 "register_operand" ""))]
993 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
994 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
995 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
996 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
997 && INTVAL (operands[2]) > 0"
999 [(set (subreg:SI (match_dup 0) 0)
1000 (plus:SI (subreg:SI (match_dup 1) 0)
1004 (ltu:SI (subreg:SI (match_dup 0) 0)
1007 (set (subreg:SI (match_dup 0) 4)
1008 (plus:SI (subreg:SI (match_dup 1) 4)
1013 [(set (match_operand:DI 0 "register_operand" "")
1014 (plus:DI (match_operand:DI 1 "register_operand" "")
1015 (match_operand:DI 2 "small_int" "")))
1016 (clobber (match_operand:SI 3 "register_operand" ""))]
1017 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
1018 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1019 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1020 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1021 && INTVAL (operands[2]) > 0"
1023 [(set (subreg:SI (match_dup 0) 4)
1024 (plus:SI (subreg:SI (match_dup 1) 4)
1028 (ltu:SI (subreg:SI (match_dup 0) 4)
1031 (set (subreg:SI (match_dup 0) 0)
1032 (plus:SI (subreg:SI (match_dup 1) 0)
1036 (define_insn "adddi3_internal_3"
1037 [(set (match_operand:DI 0 "register_operand" "=d,d")
1038 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")
1039 (match_operand:DI 2 "arith_operand" "d,Q")))]
1040 "TARGET_64BIT && !TARGET_MIPS16"
1044 [(set_attr "type" "darith")
1045 (set_attr "mode" "DI")])
1047 ;; For the mips16, we need to recognize stack pointer additions
1048 ;; explicitly, since we don't have a constraint for $sp. These insns
1049 ;; will be generated by the save_restore_insns functions.
1053 (plus:DI (reg:DI 29)
1054 (match_operand:DI 0 "small_int" "I")))]
1055 "TARGET_MIPS16 && TARGET_64BIT"
1057 [(set_attr "type" "arith")
1058 (set_attr "mode" "DI")
1059 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
1064 [(set (match_operand:DI 0 "register_operand" "=d")
1065 (plus:DI (reg:DI 29)
1066 (match_operand:DI 1 "small_int" "I")))]
1067 "TARGET_MIPS16 && TARGET_64BIT"
1069 [(set_attr "type" "arith")
1070 (set_attr "mode" "DI")
1071 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
1076 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1077 (plus:DI (match_operand:DI 1 "register_operand" "0,d,d")
1078 (match_operand:DI 2 "arith_operand" "Q,O,d")))]
1079 "TARGET_MIPS16 && TARGET_64BIT
1080 && (GET_CODE (operands[1]) != REG
1081 || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
1082 || M16_REG_P (REGNO (operands[1]))
1083 || REGNO (operands[1]) == ARG_POINTER_REGNUM
1084 || REGNO (operands[1]) == FRAME_POINTER_REGNUM
1085 || REGNO (operands[1]) == STACK_POINTER_REGNUM)
1086 && (GET_CODE (operands[2]) != REG
1087 || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
1088 || M16_REG_P (REGNO (operands[2]))
1089 || REGNO (operands[2]) == ARG_POINTER_REGNUM
1090 || REGNO (operands[2]) == FRAME_POINTER_REGNUM
1091 || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
1093 if (REGNO (operands[0]) == REGNO (operands[1]))
1094 return "daddu\t%0,%2";
1096 return "daddu\t%0,%1,%2";
1098 [(set_attr "type" "arith")
1099 (set_attr "mode" "DI")
1100 (set_attr_alternative "length"
1101 [(if_then_else (match_operand:VOID 2 "m16_simm5_1" "")
1104 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
1110 ;; On the mips16, we can sometimes split an add of a constant which is
1111 ;; a 4 byte instruction into two adds which are both 2 byte
1112 ;; instructions. There are two cases: one where we are adding a
1113 ;; constant plus a register to another register, and one where we are
1114 ;; simply adding a constant to a register.
1117 [(set (match_operand:DI 0 "register_operand" "")
1118 (plus:DI (match_dup 0)
1119 (match_operand:DI 1 "const_int_operand" "")))]
1120 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1121 && GET_CODE (operands[0]) == REG
1122 && M16_REG_P (REGNO (operands[0]))
1123 && GET_CODE (operands[1]) == CONST_INT
1124 && ((INTVAL (operands[1]) > 0xf
1125 && INTVAL (operands[1]) <= 0xf + 0xf)
1126 || (INTVAL (operands[1]) < - 0x10
1127 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1128 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1129 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1131 HOST_WIDE_INT val = INTVAL (operands[1]);
1135 operands[1] = GEN_INT (0xf);
1136 operands[2] = GEN_INT (val - 0xf);
1140 operands[1] = GEN_INT (- 0x10);
1141 operands[2] = GEN_INT (val + 0x10);
1146 [(set (match_operand:DI 0 "register_operand" "")
1147 (plus:DI (match_operand:DI 1 "register_operand" "")
1148 (match_operand:DI 2 "const_int_operand" "")))]
1149 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1150 && GET_CODE (operands[0]) == REG
1151 && M16_REG_P (REGNO (operands[0]))
1152 && GET_CODE (operands[1]) == REG
1153 && M16_REG_P (REGNO (operands[1]))
1154 && REGNO (operands[0]) != REGNO (operands[1])
1155 && GET_CODE (operands[2]) == CONST_INT
1156 && ((INTVAL (operands[2]) > 0x7
1157 && INTVAL (operands[2]) <= 0x7 + 0xf)
1158 || (INTVAL (operands[2]) < - 0x8
1159 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1160 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1161 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1163 HOST_WIDE_INT val = INTVAL (operands[2]);
1167 operands[2] = GEN_INT (0x7);
1168 operands[3] = GEN_INT (val - 0x7);
1172 operands[2] = GEN_INT (- 0x8);
1173 operands[3] = GEN_INT (val + 0x8);
1177 (define_insn "addsi3_internal_2"
1178 [(set (match_operand:DI 0 "register_operand" "=d,d")
1179 (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
1180 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1181 "TARGET_64BIT && !TARGET_MIPS16"
1185 [(set_attr "type" "arith")
1186 (set_attr "mode" "SI")])
1189 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1190 (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1191 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1192 "TARGET_MIPS16 && TARGET_64BIT"
1194 if (REGNO (operands[0]) == REGNO (operands[1]))
1195 return "addu\t%0,%2";
1197 return "addu\t%0,%1,%2";
1199 [(set_attr "type" "arith")
1200 (set_attr "mode" "SI")
1201 (set_attr_alternative "length"
1202 [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
1205 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
1211 ;; ....................
1215 ;; ....................
1218 (define_insn "subdf3"
1219 [(set (match_operand:DF 0 "register_operand" "=f")
1220 (minus:DF (match_operand:DF 1 "register_operand" "f")
1221 (match_operand:DF 2 "register_operand" "f")))]
1222 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1224 [(set_attr "type" "fadd")
1225 (set_attr "mode" "DF")])
1227 (define_insn "subsf3"
1228 [(set (match_operand:SF 0 "register_operand" "=f")
1229 (minus:SF (match_operand:SF 1 "register_operand" "f")
1230 (match_operand:SF 2 "register_operand" "f")))]
1233 [(set_attr "type" "fadd")
1234 (set_attr "mode" "SF")])
1236 (define_expand "subsi3"
1237 [(set (match_operand:SI 0 "register_operand" "")
1238 (minus:SI (match_operand:SI 1 "register_operand" "")
1239 (match_operand:SI 2 "register_operand" "")))]
1243 (define_insn "subsi3_internal"
1244 [(set (match_operand:SI 0 "register_operand" "=d")
1245 (minus:SI (match_operand:SI 1 "register_operand" "d")
1246 (match_operand:SI 2 "register_operand" "d")))]
1249 [(set_attr "type" "arith")
1250 (set_attr "mode" "SI")])
1252 (define_expand "subdi3"
1253 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
1254 (minus:DI (match_operand:DI 1 "register_operand" "d")
1255 (match_operand:DI 2 "register_operand" "d")))
1256 (clobber (match_dup 3))])]
1257 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
1261 emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
1266 operands[3] = gen_reg_rtx (SImode);
1269 (define_insn "subdi3_internal"
1270 [(set (match_operand:DI 0 "register_operand" "=d")
1271 (minus:DI (match_operand:DI 1 "register_operand" "d")
1272 (match_operand:DI 2 "register_operand" "d")))
1273 (clobber (match_operand:SI 3 "register_operand" "=d"))]
1274 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
1275 "sltu\t%3,%L1,%L2\;subu\t%L0,%L1,%L2\;subu\t%M0,%M1,%M2\;subu\t%M0,%M0,%3"
1276 [(set_attr "type" "darith")
1277 (set_attr "mode" "DI")
1278 (set_attr "length" "16")])
1281 [(set (match_operand:DI 0 "register_operand" "")
1282 (minus:DI (match_operand:DI 1 "register_operand" "")
1283 (match_operand:DI 2 "register_operand" "")))
1284 (clobber (match_operand:SI 3 "register_operand" ""))]
1285 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
1286 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1287 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1288 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1289 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1292 (ltu:SI (subreg:SI (match_dup 1) 0)
1293 (subreg:SI (match_dup 2) 0)))
1295 (set (subreg:SI (match_dup 0) 0)
1296 (minus:SI (subreg:SI (match_dup 1) 0)
1297 (subreg:SI (match_dup 2) 0)))
1299 (set (subreg:SI (match_dup 0) 4)
1300 (minus:SI (subreg:SI (match_dup 1) 4)
1301 (subreg:SI (match_dup 2) 4)))
1303 (set (subreg:SI (match_dup 0) 4)
1304 (minus:SI (subreg:SI (match_dup 0) 4)
1309 [(set (match_operand:DI 0 "register_operand" "")
1310 (minus:DI (match_operand:DI 1 "register_operand" "")
1311 (match_operand:DI 2 "register_operand" "")))
1312 (clobber (match_operand:SI 3 "register_operand" ""))]
1313 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
1314 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1315 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1316 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1317 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1320 (ltu:SI (subreg:SI (match_dup 1) 4)
1321 (subreg:SI (match_dup 2) 4)))
1323 (set (subreg:SI (match_dup 0) 4)
1324 (minus:SI (subreg:SI (match_dup 1) 4)
1325 (subreg:SI (match_dup 2) 4)))
1327 (set (subreg:SI (match_dup 0) 0)
1328 (minus:SI (subreg:SI (match_dup 1) 0)
1329 (subreg:SI (match_dup 2) 0)))
1331 (set (subreg:SI (match_dup 0) 0)
1332 (minus:SI (subreg:SI (match_dup 0) 0)
1336 (define_insn "subdi3_internal_3"
1337 [(set (match_operand:DI 0 "register_operand" "=d")
1338 (minus:DI (match_operand:DI 1 "register_operand" "d")
1339 (match_operand:DI 2 "register_operand" "d")))]
1342 [(set_attr "type" "darith")
1343 (set_attr "mode" "DI")])
1345 (define_insn "subsi3_internal_2"
1346 [(set (match_operand:DI 0 "register_operand" "=d")
1348 (minus:SI (match_operand:SI 1 "register_operand" "d")
1349 (match_operand:SI 2 "register_operand" "d"))))]
1352 [(set_attr "type" "arith")
1353 (set_attr "mode" "DI")])
1356 ;; ....................
1360 ;; ....................
1363 (define_expand "muldf3"
1364 [(set (match_operand:DF 0 "register_operand" "=f")
1365 (mult:DF (match_operand:DF 1 "register_operand" "f")
1366 (match_operand:DF 2 "register_operand" "f")))]
1367 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1370 (define_insn "muldf3_internal"
1371 [(set (match_operand:DF 0 "register_operand" "=f")
1372 (mult:DF (match_operand:DF 1 "register_operand" "f")
1373 (match_operand:DF 2 "register_operand" "f")))]
1374 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_4300_MUL_FIX"
1376 [(set_attr "type" "fmul")
1377 (set_attr "mode" "DF")])
1379 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1380 ;; operands may corrupt immediately following multiplies. This is a
1381 ;; simple fix to insert NOPs.
1383 (define_insn "muldf3_r4300"
1384 [(set (match_operand:DF 0 "register_operand" "=f")
1385 (mult:DF (match_operand:DF 1 "register_operand" "f")
1386 (match_operand:DF 2 "register_operand" "f")))]
1387 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_4300_MUL_FIX"
1388 "mul.d\t%0,%1,%2\;nop"
1389 [(set_attr "type" "fmul")
1390 (set_attr "mode" "DF")
1391 (set_attr "length" "8")])
1393 (define_expand "mulsf3"
1394 [(set (match_operand:SF 0 "register_operand" "=f")
1395 (mult:SF (match_operand:SF 1 "register_operand" "f")
1396 (match_operand:SF 2 "register_operand" "f")))]
1400 (define_insn "mulsf3_internal"
1401 [(set (match_operand:SF 0 "register_operand" "=f")
1402 (mult:SF (match_operand:SF 1 "register_operand" "f")
1403 (match_operand:SF 2 "register_operand" "f")))]
1404 "TARGET_HARD_FLOAT && !TARGET_4300_MUL_FIX"
1406 [(set_attr "type" "fmul")
1407 (set_attr "mode" "SF")])
1409 ;; See muldf3_r4300.
1411 (define_insn "mulsf3_r4300"
1412 [(set (match_operand:SF 0 "register_operand" "=f")
1413 (mult:SF (match_operand:SF 1 "register_operand" "f")
1414 (match_operand:SF 2 "register_operand" "f")))]
1415 "TARGET_HARD_FLOAT && TARGET_4300_MUL_FIX"
1416 "mul.s\t%0,%1,%2\;nop"
1417 [(set_attr "type" "fmul")
1418 (set_attr "mode" "SF")
1419 (set_attr "length" "8")])
1422 ;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
1423 ;; a multiply is in progress, it may give an incorrect result. Avoid
1424 ;; this by keeping the mflo with the mult on the R4000.
1426 (define_expand "mulsi3"
1427 [(set (match_operand:SI 0 "register_operand" "")
1428 (mult:SI (match_operand:SI 1 "register_operand" "")
1429 (match_operand:SI 2 "register_operand" "")))]
1432 if (GENERATE_MULT3_SI || TARGET_MAD)
1433 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1434 else if (!TARGET_MIPS4000 || TARGET_MIPS16)
1435 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1437 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1441 (define_insn "mulsi3_mult3"
1442 [(set (match_operand:SI 0 "register_operand" "=d,l")
1443 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1444 (match_operand:SI 2 "register_operand" "d,d")))
1445 (clobber (match_scratch:SI 3 "=h,h"))
1446 (clobber (match_scratch:SI 4 "=l,X"))]
1450 if (which_alternative == 1)
1451 return "mult\t%1,%2";
1460 return "mul\t%0,%1,%2";
1461 return "mult\t%0,%1,%2";
1463 [(set_attr "type" "imul")
1464 (set_attr "mode" "SI")])
1466 ;; If a register gets allocated to LO, and we spill to memory, the reload
1467 ;; will include a move from LO to a GPR. Merge it into the multiplication
1468 ;; if it can set the GPR directly.
1471 ;; Operand 1: GPR (1st multiplication operand)
1472 ;; Operand 2: GPR (2nd multiplication operand)
1474 ;; Operand 4: GPR (destination)
1477 [(set (match_operand:SI 0 "register_operand" "")
1478 (mult:SI (match_operand:SI 1 "register_operand" "")
1479 (match_operand:SI 2 "register_operand" "")))
1480 (clobber (match_operand:SI 3 "register_operand" ""))
1481 (clobber (scratch:SI))])
1482 (set (match_operand:SI 4 "register_operand" "")
1485 && true_regnum (operands[0]) == LO_REGNUM
1486 && GP_REG_P (true_regnum (operands[4]))
1487 && peep2_reg_dead_p (2, operands[0])"
1490 (mult:SI (match_dup 1)
1492 (clobber (match_dup 3))
1493 (clobber (match_dup 0))])])
1495 (define_insn "mulsi3_internal"
1496 [(set (match_operand:SI 0 "register_operand" "=l")
1497 (mult:SI (match_operand:SI 1 "register_operand" "d")
1498 (match_operand:SI 2 "register_operand" "d")))
1499 (clobber (match_scratch:SI 3 "=h"))]
1500 "!TARGET_MIPS4000 || TARGET_MIPS16"
1502 [(set_attr "type" "imul")
1503 (set_attr "mode" "SI")])
1505 (define_insn "mulsi3_r4000"
1506 [(set (match_operand:SI 0 "register_operand" "=d")
1507 (mult:SI (match_operand:SI 1 "register_operand" "d")
1508 (match_operand:SI 2 "register_operand" "d")))
1509 (clobber (match_scratch:SI 3 "=h"))
1510 (clobber (match_scratch:SI 4 "=l"))]
1511 "TARGET_MIPS4000 && !TARGET_MIPS16"
1512 "mult\t%1,%2\;mflo\t%0"
1513 [(set_attr "type" "imul")
1514 (set_attr "mode" "SI")
1515 (set_attr "length" "8")])
1517 ;; Multiply-accumulate patterns
1519 ;; For processors that can copy the output to a general register:
1521 ;; The all-d alternative is needed because the combiner will find this
1522 ;; pattern and then register alloc/reload will move registers around to
1523 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1525 ;; The last alternative should be made slightly less desirable, but adding
1526 ;; "?" to the constraint is too strong, and causes values to be loaded into
1527 ;; LO even when that's more costly. For now, using "*d" mostly does the
1529 (define_insn "*mul_acc_si"
1530 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1531 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1532 (match_operand:SI 2 "register_operand" "d,d,d"))
1533 (match_operand:SI 3 "register_operand" "0,l,*d")))
1534 (clobber (match_scratch:SI 4 "=h,h,h"))
1535 (clobber (match_scratch:SI 5 "=X,3,l"))
1536 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1538 || ISA_HAS_MADD_MSUB)
1541 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1542 if (which_alternative == 2)
1544 if (ISA_HAS_MADD_MSUB && which_alternative != 0)
1546 return madd[which_alternative];
1548 [(set_attr "type" "imadd,imadd,multi")
1549 (set_attr "mode" "SI")
1550 (set_attr "length" "4,4,8")])
1552 ;; Split the above insn if we failed to get LO allocated.
1554 [(set (match_operand:SI 0 "register_operand" "")
1555 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1556 (match_operand:SI 2 "register_operand" ""))
1557 (match_operand:SI 3 "register_operand" "")))
1558 (clobber (match_scratch:SI 4 ""))
1559 (clobber (match_scratch:SI 5 ""))
1560 (clobber (match_scratch:SI 6 ""))]
1561 "reload_completed && !TARGET_DEBUG_D_MODE
1562 && GP_REG_P (true_regnum (operands[0]))
1563 && GP_REG_P (true_regnum (operands[3]))"
1564 [(parallel [(set (match_dup 6)
1565 (mult:SI (match_dup 1) (match_dup 2)))
1566 (clobber (match_dup 4))
1567 (clobber (match_dup 5))])
1568 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1571 ;; Splitter to copy result of MADD to a general register
1573 [(set (match_operand:SI 0 "register_operand" "")
1574 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1575 (match_operand:SI 2 "register_operand" ""))
1576 (match_operand:SI 3 "register_operand" "")))
1577 (clobber (match_scratch:SI 4 ""))
1578 (clobber (match_scratch:SI 5 ""))
1579 (clobber (match_scratch:SI 6 ""))]
1580 "reload_completed && !TARGET_DEBUG_D_MODE
1581 && GP_REG_P (true_regnum (operands[0]))
1582 && true_regnum (operands[3]) == LO_REGNUM"
1583 [(parallel [(set (match_dup 3)
1584 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1586 (clobber (match_dup 4))
1587 (clobber (match_dup 5))
1588 (clobber (match_dup 6))])
1589 (set (match_dup 0) (match_dup 3))]
1592 (define_insn "*macc"
1593 [(set (match_operand:SI 0 "register_operand" "=l,d")
1594 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1595 (match_operand:SI 2 "register_operand" "d,d"))
1596 (match_operand:SI 3 "register_operand" "0,l")))
1597 (clobber (match_scratch:SI 4 "=h,h"))
1598 (clobber (match_scratch:SI 5 "=X,3"))]
1601 if (which_alternative == 1)
1602 return "macc\t%0,%1,%2";
1603 else if (TARGET_MIPS5500)
1604 return "madd\t%1,%2";
1606 return "macc\t%.,%1,%2";
1608 [(set_attr "type" "imadd")
1609 (set_attr "mode" "SI")])
1611 ;; Pattern generated by define_peephole2 below
1612 (define_insn "*macc2"
1613 [(set (match_operand:SI 0 "register_operand" "=l")
1614 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1615 (match_operand:SI 2 "register_operand" "d"))
1617 (set (match_operand:SI 3 "register_operand" "=d")
1618 (plus:SI (mult:SI (match_dup 1)
1621 (clobber (match_scratch:SI 4 "=h"))]
1622 "ISA_HAS_MACC && reload_completed"
1624 [(set_attr "type" "imadd")
1625 (set_attr "mode" "SI")])
1627 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1630 ;; Operand 1: GPR (1st multiplication operand)
1631 ;; Operand 2: GPR (2nd multiplication operand)
1633 ;; Operand 4: GPR (destination)
1636 [(set (match_operand:SI 0 "register_operand" "")
1637 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1638 (match_operand:SI 2 "register_operand" ""))
1640 (clobber (match_operand:SI 3 "register_operand" ""))
1641 (clobber (scratch:SI))])
1642 (set (match_operand:SI 4 "register_operand" "")
1645 && true_regnum (operands[0]) == LO_REGNUM
1646 && GP_REG_P (true_regnum (operands[4]))"
1647 [(parallel [(set (match_dup 0)
1648 (plus:SI (mult:SI (match_dup 1)
1652 (plus:SI (mult:SI (match_dup 1)
1655 (clobber (match_dup 3))])]
1658 ;; When we have a three-address multiplication instruction, it should
1659 ;; be faster to do a separate multiply and add, rather than moving
1660 ;; something into LO in order to use a macc instruction.
1662 ;; This peephole needs a scratch register to cater for the case when one
1663 ;; of the multiplication operands is the same as the destination.
1665 ;; Operand 0: GPR (scratch)
1667 ;; Operand 2: GPR (addend)
1668 ;; Operand 3: GPR (destination)
1669 ;; Operand 4: GPR (1st multiplication operand)
1670 ;; Operand 5: GPR (2nd multiplication operand)
1673 [(match_scratch:SI 0 "d")
1674 (set (match_operand:SI 1 "register_operand" "")
1675 (match_operand:SI 2 "register_operand" ""))
1678 [(set (match_operand:SI 3 "register_operand" "")
1679 (plus:SI (mult:SI (match_operand:SI 4 "register_operand" "")
1680 (match_operand:SI 5 "register_operand" ""))
1682 (clobber (match_operand:SI 6 "register_operand" ""))
1683 (clobber (match_dup 1))])]
1684 "ISA_HAS_MACC && GENERATE_MULT3_SI
1685 && true_regnum (operands[1]) == LO_REGNUM
1686 && peep2_reg_dead_p (2, operands[1])
1687 && GP_REG_P (true_regnum (operands[3]))"
1688 [(parallel [(set (match_dup 0)
1689 (mult:SI (match_dup 4)
1691 (clobber (match_dup 6))
1692 (clobber (match_dup 1))])
1694 (plus:SI (match_dup 0)
1698 ;; Same as above, except LO is the initial target of the macc.
1700 ;; Operand 0: GPR (scratch)
1702 ;; Operand 2: GPR (addend)
1703 ;; Operand 3: GPR (1st multiplication operand)
1704 ;; Operand 4: GPR (2nd multiplication operand)
1706 ;; Operand 6: GPR (destination)
1708 [(match_scratch:SI 0 "d")
1709 (set (match_operand:SI 1 "register_operand" "")
1710 (match_operand:SI 2 "register_operand" ""))
1714 (plus:SI (mult:SI (match_operand:SI 3 "register_operand" "")
1715 (match_operand:SI 4 "register_operand" ""))
1717 (clobber (match_operand:SI 5 "register_operand" ""))
1718 (clobber (scratch:SI))])
1720 (set (match_operand:SI 6 "register_operand" "")
1722 "ISA_HAS_MACC && GENERATE_MULT3_SI
1723 && true_regnum (operands[1]) == LO_REGNUM
1724 && peep2_reg_dead_p (3, operands[1])
1725 && GP_REG_P (true_regnum (operands[6]))"
1726 [(parallel [(set (match_dup 0)
1727 (mult:SI (match_dup 3)
1729 (clobber (match_dup 5))
1730 (clobber (match_dup 1))])
1732 (plus:SI (match_dup 0)
1736 (define_insn "*mul_sub_si"
1737 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1738 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1739 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1740 (match_operand:SI 3 "register_operand" "d,d,d"))))
1741 (clobber (match_scratch:SI 4 "=h,h,h"))
1742 (clobber (match_scratch:SI 5 "=X,1,l"))
1743 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1749 [(set_attr "type" "imadd,multi,multi")
1750 (set_attr "mode" "SI")
1751 (set_attr "length" "4,8,8")])
1753 ;; Split the above insn if we failed to get LO allocated.
1755 [(set (match_operand:SI 0 "register_operand" "")
1756 (minus:SI (match_operand:SI 1 "register_operand" "")
1757 (mult:SI (match_operand:SI 2 "register_operand" "")
1758 (match_operand:SI 3 "register_operand" ""))))
1759 (clobber (match_scratch:SI 4 ""))
1760 (clobber (match_scratch:SI 5 ""))
1761 (clobber (match_scratch:SI 6 ""))]
1762 "reload_completed && !TARGET_DEBUG_D_MODE
1763 && GP_REG_P (true_regnum (operands[0]))
1764 && GP_REG_P (true_regnum (operands[1]))"
1765 [(parallel [(set (match_dup 6)
1766 (mult:SI (match_dup 2) (match_dup 3)))
1767 (clobber (match_dup 4))
1768 (clobber (match_dup 5))])
1769 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1772 ;; Splitter to copy result of MSUB to a general register
1774 [(set (match_operand:SI 0 "register_operand" "")
1775 (minus:SI (match_operand:SI 1 "register_operand" "")
1776 (mult:SI (match_operand:SI 2 "register_operand" "")
1777 (match_operand:SI 3 "register_operand" ""))))
1778 (clobber (match_scratch:SI 4 ""))
1779 (clobber (match_scratch:SI 5 ""))
1780 (clobber (match_scratch:SI 6 ""))]
1781 "reload_completed && !TARGET_DEBUG_D_MODE
1782 && GP_REG_P (true_regnum (operands[0]))
1783 && true_regnum (operands[1]) == LO_REGNUM"
1784 [(parallel [(set (match_dup 1)
1785 (minus:SI (match_dup 1)
1786 (mult:SI (match_dup 2) (match_dup 3))))
1787 (clobber (match_dup 4))
1788 (clobber (match_dup 5))
1789 (clobber (match_dup 6))])
1790 (set (match_dup 0) (match_dup 1))]
1793 (define_insn "*muls"
1794 [(set (match_operand:SI 0 "register_operand" "=l,d")
1795 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1796 (match_operand:SI 2 "register_operand" "d,d"))))
1797 (clobber (match_scratch:SI 3 "=h,h"))
1798 (clobber (match_scratch:SI 4 "=X,l"))]
1803 [(set_attr "type" "imul")
1804 (set_attr "mode" "SI")])
1806 (define_insn "*msac"
1807 [(set (match_operand:SI 0 "register_operand" "=l,d")
1808 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1809 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1810 (match_operand:SI 3 "register_operand" "d,d"))))
1811 (clobber (match_scratch:SI 4 "=h,h"))
1812 (clobber (match_scratch:SI 5 "=X,1"))]
1815 if (which_alternative == 1)
1816 return "msac\t%0,%2,%3";
1817 else if (TARGET_MIPS5500)
1818 return "msub\t%2,%3";
1820 return "msac\t$0,%2,%3";
1822 [(set_attr "type" "imadd")
1823 (set_attr "mode" "SI")])
1825 (define_expand "muldi3"
1826 [(set (match_operand:DI 0 "register_operand" "")
1827 (mult:DI (match_operand:DI 1 "register_operand" "")
1828 (match_operand:DI 2 "register_operand" "")))]
1831 if (GENERATE_MULT3_DI || TARGET_MIPS4000)
1832 emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
1834 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1838 (define_insn "muldi3_internal"
1839 [(set (match_operand:DI 0 "register_operand" "=l")
1840 (mult:DI (match_operand:DI 1 "register_operand" "d")
1841 (match_operand:DI 2 "register_operand" "d")))
1842 (clobber (match_scratch:DI 3 "=h"))]
1843 "TARGET_64BIT && !TARGET_MIPS4000"
1845 [(set_attr "type" "imul")
1846 (set_attr "mode" "DI")])
1848 (define_insn "muldi3_internal2"
1849 [(set (match_operand:DI 0 "register_operand" "=d")
1850 (mult:DI (match_operand:DI 1 "register_operand" "d")
1851 (match_operand:DI 2 "register_operand" "d")))
1852 (clobber (match_scratch:DI 3 "=h"))
1853 (clobber (match_scratch:DI 4 "=l"))]
1854 "TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000)"
1856 if (GENERATE_MULT3_DI)
1857 return "dmult\t%0,%1,%2";
1859 return "dmult\t%1,%2\;mflo\t%0";
1861 [(set_attr "type" "imul")
1862 (set_attr "mode" "DI")
1863 (set (attr "length")
1864 (if_then_else (ne (symbol_ref "GENERATE_MULT3_DI") (const_int 0))
1868 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1870 (define_expand "mulsidi3"
1872 [(set (match_operand:DI 0 "register_operand" "")
1874 (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
1875 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))
1876 (clobber (scratch:DI))
1877 (clobber (scratch:DI))
1878 (clobber (scratch:DI))])]
1883 emit_insn (gen_mulsidi3_32bit (operands[0], operands[1], operands[2]));
1888 (define_insn "mulsidi3_32bit"
1889 [(set (match_operand:DI 0 "register_operand" "=x")
1891 (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1892 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1895 [(set_attr "type" "imul")
1896 (set_attr "mode" "SI")])
1898 (define_insn_and_split "*mulsidi3_64bit"
1899 [(set (match_operand:DI 0 "register_operand" "=d")
1900 (mult:DI (match_operator:DI 1 "extend_operator"
1901 [(match_operand:SI 3 "register_operand" "d")])
1902 (match_operator:DI 2 "extend_operator"
1903 [(match_operand:SI 4 "register_operand" "d")])))
1904 (clobber (match_scratch:DI 5 "=l"))
1905 (clobber (match_scratch:DI 6 "=h"))
1906 (clobber (match_scratch:DI 7 "=d"))]
1907 "TARGET_64BIT && GET_CODE (operands[1]) == GET_CODE (operands[2])"
1909 "&& reload_completed"
1913 (mult:SI (match_dup 3)
1917 (mult:DI (match_dup 1)
1921 ;; OP7 <- LO, OP0 <- HI
1922 (set (match_dup 7) (match_dup 5))
1923 (set (match_dup 0) (match_dup 6))
1927 (ashift:DI (match_dup 7)
1930 (lshiftrt:DI (match_dup 7)
1933 ;; Shift OP0 into place.
1935 (ashift:DI (match_dup 0)
1938 ;; OR the two halves together
1940 (ior:DI (match_dup 0)
1943 [(set_attr "type" "imul")
1944 (set_attr "mode" "SI")
1945 (set_attr "length" "24")])
1947 (define_insn "*mulsidi3_64bit_parts"
1948 [(set (match_operand:DI 0 "register_operand" "=l")
1950 (mult:SI (match_operand:SI 2 "register_operand" "d")
1951 (match_operand:SI 3 "register_operand" "d"))))
1952 (set (match_operand:DI 1 "register_operand" "=h")
1955 (match_operator:DI 4 "extend_operator" [(match_dup 2)])
1956 (match_operator:DI 5 "extend_operator" [(match_dup 3)]))
1958 "TARGET_64BIT && GET_CODE (operands[4]) == GET_CODE (operands[5])"
1960 if (GET_CODE (operands[4]) == SIGN_EXTEND)
1961 return "mult\t%2,%3";
1963 return "multu\t%2,%3";
1965 [(set_attr "type" "imul")
1966 (set_attr "mode" "SI")])
1968 (define_expand "umulsidi3"
1970 [(set (match_operand:DI 0 "register_operand" "")
1972 (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
1973 (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
1974 (clobber (scratch:DI))
1975 (clobber (scratch:DI))
1976 (clobber (scratch:DI))])]
1981 emit_insn (gen_umulsidi3_32bit (operands[0], operands[1],
1987 (define_insn "umulsidi3_32bit"
1988 [(set (match_operand:DI 0 "register_operand" "=x")
1990 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1991 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1994 [(set_attr "type" "imul")
1995 (set_attr "mode" "SI")])
1997 ;; Widening multiply with negation.
1998 (define_insn "*muls_di"
1999 [(set (match_operand:DI 0 "register_operand" "=x")
2002 (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2003 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2004 "!TARGET_64BIT && ISA_HAS_MULS"
2006 [(set_attr "type" "imul")
2007 (set_attr "length" "4")
2008 (set_attr "mode" "SI")])
2010 (define_insn "*umuls_di"
2011 [(set (match_operand:DI 0 "register_operand" "=x")
2014 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
2015 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2016 "!TARGET_64BIT && ISA_HAS_MULS"
2018 [(set_attr "type" "imul")
2019 (set_attr "length" "4")
2020 (set_attr "mode" "SI")])
2022 (define_insn "*smsac_di"
2023 [(set (match_operand:DI 0 "register_operand" "=x")
2025 (match_operand:DI 3 "register_operand" "0")
2027 (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2028 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2029 "!TARGET_64BIT && ISA_HAS_MSAC"
2031 if (TARGET_MIPS5500)
2032 return "msub\t%1,%2";
2034 return "msac\t$0,%1,%2";
2036 [(set_attr "type" "imadd")
2037 (set_attr "length" "4")
2038 (set_attr "mode" "SI")])
2040 (define_insn "*umsac_di"
2041 [(set (match_operand:DI 0 "register_operand" "=x")
2043 (match_operand:DI 3 "register_operand" "0")
2045 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
2046 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2047 "!TARGET_64BIT && ISA_HAS_MSAC"
2049 if (TARGET_MIPS5500)
2050 return "msubu\t%1,%2";
2052 return "msacu\t$0,%1,%2";
2054 [(set_attr "type" "imadd")
2055 (set_attr "length" "4")
2056 (set_attr "mode" "SI")])
2058 ;; _highpart patterns
2059 (define_expand "umulsi3_highpart"
2060 [(set (match_operand:SI 0 "register_operand" "")
2063 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2064 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
2069 emit_insn (gen_umulsi3_highpart_mulhi_internal (operands[0], operands[1],
2072 emit_insn (gen_umulsi3_highpart_internal (operands[0], operands[1],
2077 (define_insn "umulsi3_highpart_internal"
2078 [(set (match_operand:SI 0 "register_operand" "=h")
2081 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
2082 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
2084 (clobber (match_scratch:SI 3 "=l"))]
2087 [(set_attr "type" "imul")
2088 (set_attr "mode" "SI")
2089 (set_attr "length" "4")])
2091 (define_insn "umulsi3_highpart_mulhi_internal"
2092 [(set (match_operand:SI 0 "register_operand" "=h,d")
2095 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
2096 (zero_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
2098 (clobber (match_scratch:SI 3 "=l,l"))
2099 (clobber (match_scratch:SI 4 "=X,h"))]
2104 [(set_attr "type" "imul")
2105 (set_attr "mode" "SI")
2106 (set_attr "length" "4")])
2108 (define_insn "umulsi3_highpart_neg_mulhi_internal"
2109 [(set (match_operand:SI 0 "register_operand" "=h,d")
2113 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
2114 (zero_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
2116 (clobber (match_scratch:SI 3 "=l,l"))
2117 (clobber (match_scratch:SI 4 "=X,h"))]
2122 [(set_attr "type" "imul")
2123 (set_attr "mode" "SI")
2124 (set_attr "length" "4")])
2126 (define_expand "smulsi3_highpart"
2127 [(set (match_operand:SI 0 "register_operand" "")
2130 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2131 (sign_extend:DI (match_operand:SI 2 "register_operand" "")))
2136 emit_insn (gen_smulsi3_highpart_mulhi_internal (operands[0], operands[1],
2139 emit_insn (gen_smulsi3_highpart_internal (operands[0], operands[1],
2144 (define_insn "smulsi3_highpart_internal"
2145 [(set (match_operand:SI 0 "register_operand" "=h")
2148 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2149 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
2151 (clobber (match_scratch:SI 3 "=l"))]
2154 [(set_attr "type" "imul")
2155 (set_attr "mode" "SI")
2156 (set_attr "length" "4")])
2158 (define_insn "smulsi3_highpart_mulhi_internal"
2159 [(set (match_operand:SI 0 "register_operand" "=h,d")
2162 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
2163 (sign_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
2165 (clobber (match_scratch:SI 3 "=l,l"))
2166 (clobber (match_scratch:SI 4 "=X,h"))]
2171 [(set_attr "type" "imul")
2172 (set_attr "mode" "SI")
2173 (set_attr "length" "4")])
2175 (define_insn "smulsi3_highpart_neg_mulhi_internal"
2176 [(set (match_operand:SI 0 "register_operand" "=h,d")
2180 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
2181 (sign_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
2183 (clobber (match_scratch:SI 3 "=l,l"))
2184 (clobber (match_scratch:SI 4 "=X,h"))]
2189 [(set_attr "type" "imul")
2190 (set_attr "mode" "SI")])
2192 (define_insn "smuldi3_highpart"
2193 [(set (match_operand:DI 0 "register_operand" "=h")
2197 (sign_extend:TI (match_operand:DI 1 "register_operand" "d"))
2198 (sign_extend:TI (match_operand:DI 2 "register_operand" "d")))
2200 (clobber (match_scratch:DI 3 "=l"))]
2203 [(set_attr "type" "imul")
2204 (set_attr "mode" "DI")])
2206 (define_insn "umuldi3_highpart"
2207 [(set (match_operand:DI 0 "register_operand" "=h")
2211 (zero_extend:TI (match_operand:DI 1 "register_operand" "d"))
2212 (zero_extend:TI (match_operand:DI 2 "register_operand" "d")))
2214 (clobber (match_scratch:DI 3 "=l"))]
2217 [(set_attr "type" "imul")
2218 (set_attr "mode" "DI")])
2221 ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
2222 ;; instruction. The HI/LO registers are used as a 64 bit accumulator.
2224 (define_insn "madsi"
2225 [(set (match_operand:SI 0 "register_operand" "+l")
2226 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2227 (match_operand:SI 2 "register_operand" "d"))
2229 (clobber (match_scratch:SI 3 "=h"))]
2232 [(set_attr "type" "imadd")
2233 (set_attr "mode" "SI")])
2235 (define_insn "*umul_acc_di"
2236 [(set (match_operand:DI 0 "register_operand" "=x")
2238 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
2239 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
2240 (match_operand:DI 3 "register_operand" "0")))]
2241 "(TARGET_MAD || ISA_HAS_MACC)
2245 return "madu\t%1,%2";
2246 else if (TARGET_MIPS5500)
2247 return "maddu\t%1,%2";
2249 return "maccu\t%.,%1,%2";
2251 [(set_attr "type" "imadd")
2252 (set_attr "mode" "SI")])
2255 (define_insn "*smul_acc_di"
2256 [(set (match_operand:DI 0 "register_operand" "=x")
2258 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2259 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
2260 (match_operand:DI 3 "register_operand" "0")))]
2261 "(TARGET_MAD || ISA_HAS_MACC)
2265 return "mad\t%1,%2";
2266 else if (TARGET_MIPS5500)
2267 return "madd\t%1,%2";
2269 return "macc\t%.,%1,%2";
2271 [(set_attr "type" "imadd")
2272 (set_attr "mode" "SI")])
2274 ;; Floating point multiply accumulate instructions.
2277 [(set (match_operand:DF 0 "register_operand" "=f")
2278 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2279 (match_operand:DF 2 "register_operand" "f"))
2280 (match_operand:DF 3 "register_operand" "f")))]
2281 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
2282 "madd.d\t%0,%3,%1,%2"
2283 [(set_attr "type" "fmadd")
2284 (set_attr "mode" "DF")])
2287 [(set (match_operand:SF 0 "register_operand" "=f")
2288 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2289 (match_operand:SF 2 "register_operand" "f"))
2290 (match_operand:SF 3 "register_operand" "f")))]
2291 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
2292 "madd.s\t%0,%3,%1,%2"
2293 [(set_attr "type" "fmadd")
2294 (set_attr "mode" "SF")])
2297 [(set (match_operand:DF 0 "register_operand" "=f")
2298 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2299 (match_operand:DF 2 "register_operand" "f"))
2300 (match_operand:DF 3 "register_operand" "f")))]
2301 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
2302 "msub.d\t%0,%3,%1,%2"
2303 [(set_attr "type" "fmadd")
2304 (set_attr "mode" "DF")])
2307 [(set (match_operand:SF 0 "register_operand" "=f")
2308 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2309 (match_operand:SF 2 "register_operand" "f"))
2310 (match_operand:SF 3 "register_operand" "f")))]
2312 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
2313 "msub.s\t%0,%3,%1,%2"
2314 [(set_attr "type" "fmadd")
2315 (set_attr "mode" "SF")])
2318 [(set (match_operand:DF 0 "register_operand" "=f")
2319 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2320 (match_operand:DF 2 "register_operand" "f"))
2321 (match_operand:DF 3 "register_operand" "f"))))]
2322 "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
2323 "nmadd.d\t%0,%3,%1,%2"
2324 [(set_attr "type" "fmadd")
2325 (set_attr "mode" "DF")])
2328 [(set (match_operand:SF 0 "register_operand" "=f")
2329 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2330 (match_operand:SF 2 "register_operand" "f"))
2331 (match_operand:SF 3 "register_operand" "f"))))]
2332 "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
2333 "nmadd.s\t%0,%3,%1,%2"
2334 [(set_attr "type" "fmadd")
2335 (set_attr "mode" "SF")])
2338 [(set (match_operand:DF 0 "register_operand" "=f")
2339 (minus:DF (match_operand:DF 1 "register_operand" "f")
2340 (mult:DF (match_operand:DF 2 "register_operand" "f")
2341 (match_operand:DF 3 "register_operand" "f"))))]
2342 "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
2343 "nmsub.d\t%0,%1,%2,%3"
2344 [(set_attr "type" "fmadd")
2345 (set_attr "mode" "DF")])
2348 [(set (match_operand:SF 0 "register_operand" "=f")
2349 (minus:SF (match_operand:SF 1 "register_operand" "f")
2350 (mult:SF (match_operand:SF 2 "register_operand" "f")
2351 (match_operand:SF 3 "register_operand" "f"))))]
2352 "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
2353 "nmsub.s\t%0,%1,%2,%3"
2354 [(set_attr "type" "fmadd")
2355 (set_attr "mode" "SF")])
2358 ;; ....................
2360 ;; DIVISION and REMAINDER
2362 ;; ....................
2365 (define_expand "divdf3"
2366 [(set (match_operand:DF 0 "register_operand" "")
2367 (div:DF (match_operand:DF 1 "reg_or_const_float_1_operand" "")
2368 (match_operand:DF 2 "register_operand" "")))]
2369 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2371 if (const_float_1_operand (operands[1], DFmode))
2372 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
2376 ;; This pattern works around the early SB-1 rev2 core "F1" erratum:
2378 ;; If an mfc1 or dmfc1 happens to access the floating point register
2379 ;; file at the same time a long latency operation (div, sqrt, recip,
2380 ;; sqrt) iterates an intermediate result back through the floating
2381 ;; point register file bypass, then instead returning the correct
2382 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2383 ;; result of the long latency operation.
2385 ;; The workaround is to insert an unconditional 'mov' from/to the
2386 ;; long latency op destination register.
2388 (define_insn "*divdf3"
2389 [(set (match_operand:DF 0 "register_operand" "=f")
2390 (div:DF (match_operand:DF 1 "register_operand" "f")
2391 (match_operand:DF 2 "register_operand" "f")))]
2392 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2395 return "div.d\t%0,%1,%2\;mov.d\t%0,%0";
2397 return "div.d\t%0,%1,%2";
2399 [(set_attr "type" "fdiv")
2400 (set_attr "mode" "DF")
2401 (set (attr "length")
2402 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2407 ;; This pattern works around the early SB-1 rev2 core "F2" erratum:
2409 ;; In certain cases, div.s and div.ps may have a rounding error
2410 ;; and/or wrong inexact flag.
2412 ;; Therefore, we only allow div.s if not working around SB-1 rev2
2413 ;; errata, or if working around those errata and a slight loss of
2414 ;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
2415 (define_expand "divsf3"
2416 [(set (match_operand:SF 0 "register_operand" "")
2417 (div:SF (match_operand:SF 1 "reg_or_const_float_1_operand" "")
2418 (match_operand:SF 2 "register_operand" "")))]
2419 "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
2421 if (const_float_1_operand (operands[1], SFmode))
2422 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
2426 ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
2427 ;; "divdf3" comment for details).
2429 ;; This pattern works around the early SB-1 rev2 core "F2" erratum (see
2430 ;; "divsf3" comment for details).
2431 (define_insn "*divsf3"
2432 [(set (match_operand:SF 0 "register_operand" "=f")
2433 (div:SF (match_operand:SF 1 "register_operand" "f")
2434 (match_operand:SF 2 "register_operand" "f")))]
2435 "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
2438 return "div.s\t%0,%1,%2\;mov.s\t%0,%0";
2440 return "div.s\t%0,%1,%2";
2442 [(set_attr "type" "fdiv")
2443 (set_attr "mode" "SF")
2444 (set (attr "length")
2445 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2449 ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
2450 ;; "divdf3" comment for details).
2452 [(set (match_operand:DF 0 "register_operand" "=f")
2453 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2454 (match_operand:DF 2 "register_operand" "f")))]
2455 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
2458 return "recip.d\t%0,%2\;mov.d\t%0,%0";
2460 return "recip.d\t%0,%2";
2462 [(set_attr "type" "fdiv")
2463 (set_attr "mode" "DF")
2464 (set (attr "length")
2465 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2469 ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
2470 ;; "divdf3" comment for details).
2472 [(set (match_operand:SF 0 "register_operand" "=f")
2473 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2474 (match_operand:SF 2 "register_operand" "f")))]
2475 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
2478 return "recip.s\t%0,%2\;mov.s\t%0,%0";
2480 return "recip.s\t%0,%2";
2482 [(set_attr "type" "fdiv")
2483 (set_attr "mode" "SF")
2484 (set (attr "length")
2485 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2489 (define_insn "divmodsi4"
2490 [(set (match_operand:SI 0 "register_operand" "=l")
2491 (div:SI (match_operand:SI 1 "register_operand" "d")
2492 (match_operand:SI 2 "register_operand" "d")))
2493 (set (match_operand:SI 3 "register_operand" "=h")
2494 (mod:SI (match_dup 1)
2497 { return mips_output_division ("div\t$0,%1,%2", operands); }
2498 [(set_attr "type" "idiv")
2499 (set_attr "mode" "SI")])
2501 (define_insn "divmoddi4"
2502 [(set (match_operand:DI 0 "register_operand" "=l")
2503 (div:DI (match_operand:DI 1 "register_operand" "d")
2504 (match_operand:DI 2 "register_operand" "d")))
2505 (set (match_operand:DI 3 "register_operand" "=h")
2506 (mod:DI (match_dup 1)
2509 { return mips_output_division ("ddiv\t$0,%1,%2", operands); }
2510 [(set_attr "type" "idiv")
2511 (set_attr "mode" "DI")])
2513 (define_insn "udivmodsi4"
2514 [(set (match_operand:SI 0 "register_operand" "=l")
2515 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2516 (match_operand:SI 2 "register_operand" "d")))
2517 (set (match_operand:SI 3 "register_operand" "=h")
2518 (umod:SI (match_dup 1)
2521 { return mips_output_division ("divu\t$0,%1,%2", operands); }
2522 [(set_attr "type" "idiv")
2523 (set_attr "mode" "SI")])
2525 (define_insn "udivmoddi4"
2526 [(set (match_operand:DI 0 "register_operand" "=l")
2527 (udiv:DI (match_operand:DI 1 "register_operand" "d")
2528 (match_operand:DI 2 "register_operand" "d")))
2529 (set (match_operand:DI 3 "register_operand" "=h")
2530 (umod:DI (match_dup 1)
2533 { return mips_output_division ("ddivu\t$0,%1,%2", operands); }
2534 [(set_attr "type" "idiv")
2535 (set_attr "mode" "DI")])
2538 ;; ....................
2542 ;; ....................
2544 ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
2545 ;; "divdf3" comment for details).
2546 (define_insn "sqrtdf2"
2547 [(set (match_operand:DF 0 "register_operand" "=f")
2548 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
2549 "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
2552 return "sqrt.d\t%0,%1\;mov.d\t%0,%0";
2554 return "sqrt.d\t%0,%1";
2556 [(set_attr "type" "fsqrt")
2557 (set_attr "mode" "DF")
2558 (set (attr "length")
2559 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2563 ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
2564 ;; "divdf3" comment for details).
2565 (define_insn "sqrtsf2"
2566 [(set (match_operand:SF 0 "register_operand" "=f")
2567 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
2568 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
2571 return "sqrt.s\t%0,%1\;mov.s\t%0,%0";
2573 return "sqrt.s\t%0,%1";
2575 [(set_attr "type" "fsqrt")
2576 (set_attr "mode" "SF")
2577 (set (attr "length")
2578 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2582 ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
2583 ;; "divdf3" comment for details).
2585 [(set (match_operand:DF 0 "register_operand" "=f")
2586 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2587 (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
2588 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
2591 return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
2593 return "rsqrt.d\t%0,%2";
2595 [(set_attr "type" "frsqrt")
2596 (set_attr "mode" "DF")
2597 (set (attr "length")
2598 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2602 ;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
2603 ;; "divdf3" comment for details).
2605 [(set (match_operand:SF 0 "register_operand" "=f")
2606 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2607 (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
2608 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
2611 return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
2613 return "rsqrt.s\t%0,%2";
2615 [(set_attr "type" "frsqrt")
2616 (set_attr "mode" "SF")
2617 (set (attr "length")
2618 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2623 ;; ....................
2627 ;; ....................
2629 ;; Do not use the integer abs macro instruction, since that signals an
2630 ;; exception on -2147483648 (sigh).
2632 (define_insn "abssi2"
2633 [(set (match_operand:SI 0 "register_operand" "=d")
2634 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
2637 operands[2] = const0_rtx;
2639 if (REGNO (operands[0]) == REGNO (operands[1]))
2641 if (GENERATE_BRANCHLIKELY)
2642 return "%(bltzl\t%1,1f\;subu\t%0,%z2,%0\n%~1:%)";
2644 return "bgez\t%1,1f%#\;subu\t%0,%z2,%0\n%~1:";
2647 return "%(bgez\t%1,1f\;move\t%0,%1\;subu\t%0,%z2,%0\n%~1:%)";
2649 [(set_attr "type" "multi")
2650 (set_attr "mode" "SI")
2651 (set_attr "length" "12")])
2653 (define_insn "absdi2"
2654 [(set (match_operand:DI 0 "register_operand" "=d")
2655 (abs:DI (match_operand:DI 1 "register_operand" "d")))]
2656 "TARGET_64BIT && !TARGET_MIPS16"
2658 unsigned int regno1;
2659 operands[2] = const0_rtx;
2661 if (GET_CODE (operands[1]) == REG)
2662 regno1 = REGNO (operands[1]);
2664 regno1 = REGNO (XEXP (operands[1], 0));
2666 if (REGNO (operands[0]) == regno1)
2667 return "%(bltzl\t%1,1f\;dsubu\t%0,%z2,%0\n%~1:%)";
2669 return "%(bgez\t%1,1f\;move\t%0,%1\;dsubu\t%0,%z2,%0\n%~1:%)";
2671 [(set_attr "type" "multi")
2672 (set_attr "mode" "DI")
2673 (set_attr "length" "12")])
2675 (define_insn "absdf2"
2676 [(set (match_operand:DF 0 "register_operand" "=f")
2677 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
2678 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2680 [(set_attr "type" "fabs")
2681 (set_attr "mode" "DF")])
2683 (define_insn "abssf2"
2684 [(set (match_operand:SF 0 "register_operand" "=f")
2685 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
2688 [(set_attr "type" "fabs")
2689 (set_attr "mode" "SF")])
2692 ;; ....................
2694 ;; FIND FIRST BIT INSTRUCTION
2696 ;; ....................
2699 (define_insn "ffssi2"
2700 [(set (match_operand:SI 0 "register_operand" "=&d")
2701 (ffs:SI (match_operand:SI 1 "register_operand" "d")))
2702 (clobber (match_scratch:SI 2 "=&d"))
2703 (clobber (match_scratch:SI 3 "=&d"))]
2706 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
2710 %~1:\tand\t%2,%1,0x0001\;\
2720 %~1:\tand\t%2,%3,0x0001\;\
2726 [(set_attr "type" "multi")
2727 (set_attr "mode" "SI")
2728 (set_attr "length" "28")])
2730 (define_insn "ffsdi2"
2731 [(set (match_operand:DI 0 "register_operand" "=&d")
2732 (ffs:DI (match_operand:DI 1 "register_operand" "d")))
2733 (clobber (match_scratch:DI 2 "=&d"))
2734 (clobber (match_scratch:DI 3 "=&d"))]
2735 "TARGET_64BIT && !TARGET_MIPS16"
2737 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
2741 %~1:\tand\t%2,%1,0x0001\;\
2751 %~1:\tand\t%2,%3,0x0001\;\
2757 [(set_attr "type" "multi")
2758 (set_attr "mode" "DI")
2759 (set_attr "length" "28")])
2762 ;; ...................
2764 ;; Count leading zeroes.
2766 ;; ...................
2769 (define_insn "clzsi2"
2770 [(set (match_operand:SI 0 "register_operand" "=d")
2771 (clz:SI (match_operand:SI 1 "register_operand" "d")))]
2774 [(set_attr "type" "arith")
2775 (set_attr "mode" "SI")])
2777 (define_insn "clzdi2"
2778 [(set (match_operand:DI 0 "register_operand" "=d")
2779 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
2782 [(set_attr "type" "arith")
2783 (set_attr "mode" "DI")])
2786 ;; ....................
2788 ;; NEGATION and ONE'S COMPLEMENT
2790 ;; ....................
2792 (define_insn "negsi2"
2793 [(set (match_operand:SI 0 "register_operand" "=d")
2794 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2798 return "neg\t%0,%1";
2800 return "subu\t%0,%.,%1";
2802 [(set_attr "type" "arith")
2803 (set_attr "mode" "SI")])
2805 (define_expand "negdi2"
2806 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
2807 (neg:DI (match_operand:DI 1 "register_operand" "d")))
2808 (clobber (match_dup 2))])]
2809 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
2813 emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
2817 operands[2] = gen_reg_rtx (SImode);
2820 (define_insn "negdi2_internal"
2821 [(set (match_operand:DI 0 "register_operand" "=d")
2822 (neg:DI (match_operand:DI 1 "register_operand" "d")))
2823 (clobber (match_operand:SI 2 "register_operand" "=d"))]
2824 "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
2825 "subu\t%L0,%.,%L1\;subu\t%M0,%.,%M1\;sltu\t%2,%.,%L0\;subu\t%M0,%M0,%2"
2826 [(set_attr "type" "darith")
2827 (set_attr "mode" "DI")
2828 (set_attr "length" "16")])
2830 (define_insn "negdi2_internal_2"
2831 [(set (match_operand:DI 0 "register_operand" "=d")
2832 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2833 "TARGET_64BIT && !TARGET_MIPS16"
2835 [(set_attr "type" "arith")
2836 (set_attr "mode" "DI")])
2838 (define_insn "negdf2"
2839 [(set (match_operand:DF 0 "register_operand" "=f")
2840 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
2841 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2843 [(set_attr "type" "fneg")
2844 (set_attr "mode" "DF")])
2846 (define_insn "negsf2"
2847 [(set (match_operand:SF 0 "register_operand" "=f")
2848 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
2851 [(set_attr "type" "fneg")
2852 (set_attr "mode" "SF")])
2854 (define_insn "one_cmplsi2"
2855 [(set (match_operand:SI 0 "register_operand" "=d")
2856 (not:SI (match_operand:SI 1 "register_operand" "d")))]
2860 return "not\t%0,%1";
2862 return "nor\t%0,%.,%1";
2864 [(set_attr "type" "arith")
2865 (set_attr "mode" "SI")])
2867 (define_insn "one_cmpldi2"
2868 [(set (match_operand:DI 0 "register_operand" "=d")
2869 (not:DI (match_operand:DI 1 "register_operand" "d")))]
2873 return "not\t%0,%1";
2875 return "nor\t%0,%.,%1";
2877 [(set_attr "type" "darith")
2878 (set_attr "mode" "DI")])
2881 ;; ....................
2885 ;; ....................
2888 ;; Many of these instructions use trivial define_expands, because we
2889 ;; want to use a different set of constraints when TARGET_MIPS16.
2891 (define_expand "andsi3"
2892 [(set (match_operand:SI 0 "register_operand" "=d,d")
2893 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
2894 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
2899 operands[1] = force_reg (SImode, operands[1]);
2900 operands[2] = force_reg (SImode, operands[2]);
2905 [(set (match_operand:SI 0 "register_operand" "=d,d")
2906 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
2907 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
2912 [(set_attr "type" "arith")
2913 (set_attr "mode" "SI")])
2916 [(set (match_operand:SI 0 "register_operand" "=d")
2917 (and:SI (match_operand:SI 1 "register_operand" "%0")
2918 (match_operand:SI 2 "register_operand" "d")))]
2921 [(set_attr "type" "arith")
2922 (set_attr "mode" "SI")])
2924 (define_expand "anddi3"
2925 [(set (match_operand:DI 0 "register_operand" "")
2926 (and:DI (match_operand:DI 1 "register_operand" "")
2927 (match_operand:DI 2 "uns_arith_operand" "")))]
2932 operands[1] = force_reg (DImode, operands[1]);
2933 operands[2] = force_reg (DImode, operands[2]);
2938 [(set (match_operand:DI 0 "register_operand" "=d,d")
2939 (and:DI (match_operand:DI 1 "register_operand" "d,d")
2940 (match_operand:DI 2 "uns_arith_operand" "d,K")))]
2941 "TARGET_64BIT && !TARGET_MIPS16"
2945 [(set_attr "type" "darith")
2946 (set_attr "mode" "DI")])
2949 [(set (match_operand:DI 0 "register_operand" "=d")
2950 (and:DI (match_operand:DI 1 "register_operand" "0")
2951 (match_operand:DI 2 "register_operand" "d")))]
2952 "TARGET_64BIT && TARGET_MIPS16"
2954 [(set_attr "type" "darith")
2955 (set_attr "mode" "DI")])
2957 (define_expand "iorsi3"
2958 [(set (match_operand:SI 0 "register_operand" "=d,d")
2959 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
2960 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
2965 operands[1] = force_reg (SImode, operands[1]);
2966 operands[2] = force_reg (SImode, operands[2]);
2971 [(set (match_operand:SI 0 "register_operand" "=d,d")
2972 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
2973 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
2978 [(set_attr "type" "arith")
2979 (set_attr "mode" "SI")])
2982 [(set (match_operand:SI 0 "register_operand" "=d")
2983 (ior:SI (match_operand:SI 1 "register_operand" "%0")
2984 (match_operand:SI 2 "register_operand" "d")))]
2987 [(set_attr "type" "arith")
2988 (set_attr "mode" "SI")])
2990 (define_expand "iordi3"
2991 [(set (match_operand:DI 0 "register_operand" "")
2992 (ior:DI (match_operand:DI 1 "register_operand" "")
2993 (match_operand:DI 2 "uns_arith_operand" "")))]
2998 operands[1] = force_reg (DImode, operands[1]);
2999 operands[2] = force_reg (DImode, operands[2]);
3004 [(set (match_operand:DI 0 "register_operand" "=d,d")
3005 (ior:DI (match_operand:DI 1 "register_operand" "d,d")
3006 (match_operand:DI 2 "uns_arith_operand" "d,K")))]
3007 "TARGET_64BIT && !TARGET_MIPS16"
3011 [(set_attr "type" "darith")
3012 (set_attr "mode" "DI")])
3015 [(set (match_operand:DI 0 "register_operand" "=d")
3016 (ior:DI (match_operand:DI 1 "register_operand" "0")
3017 (match_operand:DI 2 "register_operand" "d")))]
3018 "TARGET_64BIT && TARGET_MIPS16"
3020 [(set_attr "type" "darith")
3021 (set_attr "mode" "DI")])
3023 (define_expand "xorsi3"
3024 [(set (match_operand:SI 0 "register_operand" "=d,d")
3025 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3026 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3031 [(set (match_operand:SI 0 "register_operand" "=d,d")
3032 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3033 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3038 [(set_attr "type" "arith")
3039 (set_attr "mode" "SI")])
3042 [(set (match_operand:SI 0 "register_operand" "=d,t,t")
3043 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%0,d,d")
3044 (match_operand:SI 2 "uns_arith_operand" "d,K,d")))]
3050 [(set_attr "type" "arith")
3051 (set_attr "mode" "SI")
3052 (set_attr_alternative "length"
3054 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
3059 (define_expand "xordi3"
3060 [(set (match_operand:DI 0 "register_operand" "")
3061 (xor:DI (match_operand:DI 1 "register_operand" "")
3062 (match_operand:DI 2 "uns_arith_operand" "")))]
3067 operands[1] = force_reg (DImode, operands[1]);
3068 operands[2] = force_reg (DImode, operands[2]);
3073 [(set (match_operand:DI 0 "register_operand" "=d,d")
3074 (xor:DI (match_operand:DI 1 "register_operand" "d,d")
3075 (match_operand:DI 2 "uns_arith_operand" "d,K")))]
3076 "TARGET_64BIT && !TARGET_MIPS16"
3080 [(set_attr "type" "darith")
3081 (set_attr "mode" "DI")])
3084 [(set (match_operand:DI 0 "register_operand" "=d,t,t")
3085 (xor:DI (match_operand:DI 1 "register_operand" "%0,d,d")
3086 (match_operand:DI 2 "uns_arith_operand" "d,K,d")))]
3087 "TARGET_64BIT && TARGET_MIPS16"
3092 [(set_attr "type" "arith")
3093 (set_attr "mode" "DI")
3094 (set_attr_alternative "length"
3096 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
3101 (define_insn "*norsi3"
3102 [(set (match_operand:SI 0 "register_operand" "=d")
3103 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
3104 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
3107 [(set_attr "type" "arith")
3108 (set_attr "mode" "SI")])
3110 (define_insn "*nordi3"
3111 [(set (match_operand:DI 0 "register_operand" "=d")
3112 (and:DI (not:DI (match_operand:DI 1 "register_operand" "d"))
3113 (not:DI (match_operand:DI 2 "register_operand" "d"))))]
3114 "TARGET_64BIT && !TARGET_MIPS16"
3116 [(set_attr "type" "darith")
3117 (set_attr "mode" "DI")])
3120 ;; ....................
3124 ;; ....................
3128 (define_insn "truncdfsf2"
3129 [(set (match_operand:SF 0 "register_operand" "=f")
3130 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3131 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3133 [(set_attr "type" "fcvt")
3134 (set_attr "mode" "SF")])
3136 ;; Integer truncation patterns. Truncating SImode values to smaller
3137 ;; modes is a no-op, as it is for most other GCC ports. Truncating
3138 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
3139 ;; need to make sure that the lower 32 bits are properly sign-extended
3140 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
3141 ;; smaller than SImode is equivalent to two separate truncations:
3144 ;; DI ---> HI == DI ---> SI ---> HI
3145 ;; DI ---> QI == DI ---> SI ---> QI
3147 ;; Step A needs a real instruction but step B does not.
3149 (define_insn "truncdisi2"
3150 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
3151 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
3156 [(set_attr "type" "darith,store")
3157 (set_attr "mode" "SI")
3158 (set_attr "extended_mips16" "yes,*")])
3160 (define_insn "truncdihi2"
3161 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
3162 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
3167 [(set_attr "type" "darith,store")
3168 (set_attr "mode" "SI")
3169 (set_attr "extended_mips16" "yes,*")])
3171 (define_insn "truncdiqi2"
3172 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
3173 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
3178 [(set_attr "type" "darith,store")
3179 (set_attr "mode" "SI")
3180 (set_attr "extended_mips16" "yes,*")])
3182 ;; Combiner patterns to optimize shift/truncate combinations.
3185 [(set (match_operand:SI 0 "register_operand" "=d")
3186 (truncate:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3187 (match_operand:DI 2 "small_int" "I"))))]
3188 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
3190 [(set_attr "type" "darith")
3191 (set_attr "mode" "SI")])
3194 [(set (match_operand:SI 0 "register_operand" "=d")
3195 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3197 "TARGET_64BIT && !TARGET_MIPS16"
3199 [(set_attr "type" "darith")
3200 (set_attr "mode" "SI")])
3203 ;; Combiner patterns for truncate/sign_extend combinations. They use
3204 ;; the shift/truncate patterns above.
3206 (define_insn_and_split ""
3207 [(set (match_operand:SI 0 "register_operand" "=d")
3209 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
3210 "TARGET_64BIT && !TARGET_MIPS16"
3212 "&& reload_completed"
3214 (ashift:DI (match_dup 1)
3217 (truncate:SI (ashiftrt:DI (match_dup 2)
3219 { operands[2] = gen_lowpart (DImode, operands[0]); })
3221 (define_insn_and_split ""
3222 [(set (match_operand:SI 0 "register_operand" "=d")
3224 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3225 "TARGET_64BIT && !TARGET_MIPS16"
3227 "&& reload_completed"
3229 (ashift:DI (match_dup 1)
3232 (truncate:SI (ashiftrt:DI (match_dup 2)
3234 { operands[2] = gen_lowpart (DImode, operands[0]); })
3237 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3240 [(set (match_operand:SI 0 "register_operand" "=d")
3241 (zero_extend:SI (truncate:HI
3242 (match_operand:DI 1 "register_operand" "d"))))]
3243 "TARGET_64BIT && !TARGET_MIPS16"
3244 "andi\t%0,%1,0xffff"
3245 [(set_attr "type" "darith")
3246 (set_attr "mode" "SI")])
3249 [(set (match_operand:SI 0 "register_operand" "=d")
3250 (zero_extend:SI (truncate:QI
3251 (match_operand:DI 1 "register_operand" "d"))))]
3252 "TARGET_64BIT && !TARGET_MIPS16"
3254 [(set_attr "type" "darith")
3255 (set_attr "mode" "SI")])
3258 [(set (match_operand:HI 0 "register_operand" "=d")
3259 (zero_extend:HI (truncate:QI
3260 (match_operand:DI 1 "register_operand" "d"))))]
3261 "TARGET_64BIT && !TARGET_MIPS16"
3263 [(set_attr "type" "darith")
3264 (set_attr "mode" "HI")])
3267 ;; ....................
3271 ;; ....................
3274 ;; Those for integer source operand are ordered widest source type first.
3276 (define_insn_and_split "zero_extendsidi2"
3277 [(set (match_operand:DI 0 "register_operand" "=d")
3278 (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))]
3281 "&& reload_completed"
3283 (ashift:DI (match_dup 1) (const_int 32)))
3285 (lshiftrt:DI (match_dup 0) (const_int 32)))]
3286 "operands[1] = gen_lowpart (DImode, operands[1]);"
3287 [(set_attr "type" "arith")
3288 (set_attr "mode" "DI")])
3290 (define_insn "*zero_extendsidi2_mem"
3291 [(set (match_operand:DI 0 "register_operand" "=d")
3292 (zero_extend:DI (match_operand:SI 1 "memory_operand" "W")))]
3295 [(set_attr "type" "load")
3296 (set_attr "mode" "DI")])
3298 (define_expand "zero_extendhisi2"
3299 [(set (match_operand:SI 0 "register_operand" "")
3300 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3303 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3305 rtx op = gen_lowpart (SImode, operands[1]);
3306 rtx temp = force_reg (SImode, GEN_INT (0xffff));
3308 emit_insn (gen_andsi3 (operands[0], op, temp));
3314 [(set (match_operand:SI 0 "register_operand" "=d,d")
3315 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
3320 [(set_attr "type" "arith,load")
3321 (set_attr "mode" "SI")
3322 (set_attr "length" "4,*")])
3325 [(set (match_operand:SI 0 "register_operand" "=d")
3326 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
3329 [(set_attr "type" "load")
3330 (set_attr "mode" "SI")])
3332 (define_expand "zero_extendhidi2"
3333 [(set (match_operand:DI 0 "register_operand" "")
3334 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
3337 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3339 rtx op = gen_lowpart (DImode, operands[1]);
3340 rtx temp = force_reg (DImode, GEN_INT (0xffff));
3342 emit_insn (gen_anddi3 (operands[0], op, temp));
3348 [(set (match_operand:DI 0 "register_operand" "=d,d")
3349 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
3350 "TARGET_64BIT && !TARGET_MIPS16"
3354 [(set_attr "type" "arith,load")
3355 (set_attr "mode" "DI")
3356 (set_attr "length" "4,*")])
3359 [(set (match_operand:DI 0 "register_operand" "=d")
3360 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
3361 "TARGET_64BIT && TARGET_MIPS16"
3363 [(set_attr "type" "load")
3364 (set_attr "mode" "DI")])
3366 (define_expand "zero_extendqihi2"
3367 [(set (match_operand:HI 0 "register_operand" "")
3368 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
3371 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3373 rtx op0 = gen_lowpart (SImode, operands[0]);
3374 rtx op1 = gen_lowpart (SImode, operands[1]);
3375 rtx temp = force_reg (SImode, GEN_INT (0xff));
3377 emit_insn (gen_andsi3 (op0, op1, temp));
3383 [(set (match_operand:HI 0 "register_operand" "=d,d")
3384 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3389 [(set_attr "type" "arith,load")
3390 (set_attr "mode" "HI")
3391 (set_attr "length" "4,*")])
3394 [(set (match_operand:HI 0 "register_operand" "=d")
3395 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3398 [(set_attr "type" "load")
3399 (set_attr "mode" "HI")])
3401 (define_expand "zero_extendqisi2"
3402 [(set (match_operand:SI 0 "register_operand" "")
3403 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
3406 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3408 rtx op = gen_lowpart (SImode, operands[1]);
3409 rtx temp = force_reg (SImode, GEN_INT (0xff));
3411 emit_insn (gen_andsi3 (operands[0], op, temp));
3417 [(set (match_operand:SI 0 "register_operand" "=d,d")
3418 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3423 [(set_attr "type" "arith,load")
3424 (set_attr "mode" "SI")
3425 (set_attr "length" "4,*")])
3428 [(set (match_operand:SI 0 "register_operand" "=d")
3429 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3432 [(set_attr "type" "load")
3433 (set_attr "mode" "SI")])
3435 (define_expand "zero_extendqidi2"
3436 [(set (match_operand:DI 0 "register_operand" "")
3437 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
3440 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3442 rtx op = gen_lowpart (DImode, operands[1]);
3443 rtx temp = force_reg (DImode, GEN_INT (0xff));
3445 emit_insn (gen_anddi3 (operands[0], op, temp));
3451 [(set (match_operand:DI 0 "register_operand" "=d,d")
3452 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3453 "TARGET_64BIT && !TARGET_MIPS16"
3457 [(set_attr "type" "arith,load")
3458 (set_attr "mode" "DI")
3459 (set_attr "length" "4,*")])
3462 [(set (match_operand:DI 0 "register_operand" "=d")
3463 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
3464 "TARGET_64BIT && TARGET_MIPS16"
3466 [(set_attr "type" "load")
3467 (set_attr "mode" "DI")])
3470 ;; ....................
3474 ;; ....................
3477 ;; Those for integer source operand are ordered widest source type first.
3479 (define_insn "extendsidi2"
3480 [(set (match_operand:DI 0 "register_operand" "=d,d")
3481 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
3486 [(set_attr "type" "arith,load")
3487 (set_attr "mode" "DI")
3488 (set_attr "extended_mips16" "yes,*")])
3490 ;; These patterns originally accepted general_operands, however, slightly
3491 ;; better code is generated by only accepting register_operands, and then
3492 ;; letting combine generate the lh and lb insns.
3494 ;; These expanders originally put values in registers first. We split
3495 ;; all non-mem patterns after reload.
3497 (define_expand "extendhidi2"
3498 [(set (match_operand:DI 0 "register_operand" "")
3499 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
3503 (define_insn "*extendhidi2"
3504 [(set (match_operand:DI 0 "register_operand" "=d")
3505 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
3510 [(set (match_operand:DI 0 "register_operand" "")
3511 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
3512 "TARGET_64BIT && reload_completed"
3514 (ashift:DI (match_dup 1) (const_int 48)))
3516 (ashiftrt:DI (match_dup 0) (const_int 48)))]
3517 "operands[1] = gen_lowpart (DImode, operands[1]);")
3519 (define_insn "*extendhidi2_mem"
3520 [(set (match_operand:DI 0 "register_operand" "=d")
3521 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
3524 [(set_attr "type" "load")
3525 (set_attr "mode" "DI")])
3527 (define_expand "extendhisi2"
3528 [(set (match_operand:SI 0 "register_operand" "")
3529 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3532 if (ISA_HAS_SEB_SEH)
3534 emit_insn (gen_extendhisi2_hw (operands[0],
3535 force_reg (HImode, operands[1])));
3540 (define_insn "*extendhisi2"
3541 [(set (match_operand:SI 0 "register_operand" "=d")
3542 (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
3547 [(set (match_operand:SI 0 "register_operand" "")
3548 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
3551 (ashift:SI (match_dup 1) (const_int 16)))
3553 (ashiftrt:SI (match_dup 0) (const_int 16)))]
3554 "operands[1] = gen_lowpart (SImode, operands[1]);")
3556 (define_insn "extendhisi2_mem"
3557 [(set (match_operand:SI 0 "register_operand" "=d")
3558 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
3561 [(set_attr "type" "load")
3562 (set_attr "mode" "SI")])
3564 (define_insn "extendhisi2_hw"
3565 [(set (match_operand:SI 0 "register_operand" "=r")
3566 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
3569 [(set_attr "type" "arith")
3570 (set_attr "mode" "SI")])
3572 (define_expand "extendqihi2"
3573 [(set (match_operand:HI 0 "register_operand" "")
3574 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
3578 (define_insn "*extendqihi2"
3579 [(set (match_operand:HI 0 "register_operand" "=d")
3580 (sign_extend:HI (match_operand:QI 1 "register_operand" "d")))]
3585 [(set (match_operand:HI 0 "register_operand" "")
3586 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
3589 (ashift:SI (match_dup 1) (const_int 24)))
3591 (ashiftrt:SI (match_dup 0) (const_int 24)))]
3592 "operands[0] = gen_lowpart (SImode, operands[0]);
3593 operands[1] = gen_lowpart (SImode, operands[1]);")
3595 (define_insn "*extendqihi2_internal_mem"
3596 [(set (match_operand:HI 0 "register_operand" "=d")
3597 (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3600 [(set_attr "type" "load")
3601 (set_attr "mode" "SI")])
3604 (define_expand "extendqisi2"
3605 [(set (match_operand:SI 0 "register_operand" "")
3606 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
3609 if (ISA_HAS_SEB_SEH)
3611 emit_insn (gen_extendqisi2_hw (operands[0],
3612 force_reg (QImode, operands[1])));
3617 (define_insn "*extendqisi2"
3618 [(set (match_operand:SI 0 "register_operand" "=d")
3619 (sign_extend:SI (match_operand:QI 1 "register_operand" "d")))]
3624 [(set (match_operand:SI 0 "register_operand" "")
3625 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
3628 (ashift:SI (match_dup 1) (const_int 24)))
3630 (ashiftrt:SI (match_dup 0) (const_int 24)))]
3631 "operands[1] = gen_lowpart (SImode, operands[1]);")
3633 (define_insn "*extendqisi2_mem"
3634 [(set (match_operand:SI 0 "register_operand" "=d")
3635 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3638 [(set_attr "type" "load")
3639 (set_attr "mode" "SI")])
3641 (define_insn "extendqisi2_hw"
3642 [(set (match_operand:SI 0 "register_operand" "=r")
3643 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
3646 [(set_attr "type" "arith")
3647 (set_attr "mode" "SI")])
3649 (define_expand "extendqidi2"
3650 [(set (match_operand:DI 0 "register_operand" "")
3651 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
3655 (define_insn "*extendqidi2"
3656 [(set (match_operand:DI 0 "register_operand" "=d")
3657 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
3662 [(set (match_operand:DI 0 "register_operand" "")
3663 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
3664 "TARGET_64BIT && reload_completed"
3666 (ashift:DI (match_dup 1) (const_int 56)))
3668 (ashiftrt:DI (match_dup 0) (const_int 56)))]
3669 "operands[1] = gen_lowpart (DImode, operands[1]);")
3671 (define_insn "*extendqidi2_mem"
3672 [(set (match_operand:DI 0 "register_operand" "=d")
3673 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
3676 [(set_attr "type" "load")
3677 (set_attr "mode" "DI")])
3679 (define_insn "extendsfdf2"
3680 [(set (match_operand:DF 0 "register_operand" "=f")
3681 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3682 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3684 [(set_attr "type" "fcvt")
3685 (set_attr "mode" "DF")])
3688 ;; ....................
3692 ;; ....................
3694 (define_expand "fix_truncdfsi2"
3695 [(set (match_operand:SI 0 "register_operand" "=f")
3696 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3697 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3699 if (!ISA_HAS_TRUNC_W)
3701 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3706 (define_insn "fix_truncdfsi2_insn"
3707 [(set (match_operand:SI 0 "register_operand" "=f")
3708 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3709 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3711 [(set_attr "type" "fcvt")
3712 (set_attr "mode" "DF")
3713 (set_attr "length" "4")])
3715 (define_insn "fix_truncdfsi2_macro"
3716 [(set (match_operand:SI 0 "register_operand" "=f")
3717 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3718 (clobber (match_scratch:DF 2 "=d"))]
3719 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3722 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3724 return "trunc.w.d %0,%1,%2";
3726 [(set_attr "type" "fcvt")
3727 (set_attr "mode" "DF")
3728 (set_attr "length" "36")])
3730 (define_expand "fix_truncsfsi2"
3731 [(set (match_operand:SI 0 "register_operand" "=f")
3732 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3735 if (!ISA_HAS_TRUNC_W)
3737 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3742 (define_insn "fix_truncsfsi2_insn"
3743 [(set (match_operand:SI 0 "register_operand" "=f")
3744 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3745 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3747 [(set_attr "type" "fcvt")
3748 (set_attr "mode" "DF")
3749 (set_attr "length" "4")])
3751 (define_insn "fix_truncsfsi2_macro"
3752 [(set (match_operand:SI 0 "register_operand" "=f")
3753 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3754 (clobber (match_scratch:SF 2 "=d"))]
3755 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3758 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3760 return "trunc.w.s %0,%1,%2";
3762 [(set_attr "type" "fcvt")
3763 (set_attr "mode" "DF")
3764 (set_attr "length" "36")])
3767 (define_insn "fix_truncdfdi2"
3768 [(set (match_operand:DI 0 "register_operand" "=f")
3769 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3770 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3772 [(set_attr "type" "fcvt")
3773 (set_attr "mode" "DF")
3774 (set_attr "length" "4")])
3777 (define_insn "fix_truncsfdi2"
3778 [(set (match_operand:DI 0 "register_operand" "=f")
3779 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3780 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3782 [(set_attr "type" "fcvt")
3783 (set_attr "mode" "SF")
3784 (set_attr "length" "4")])
3787 (define_insn "floatsidf2"
3788 [(set (match_operand:DF 0 "register_operand" "=f")
3789 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3790 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3792 [(set_attr "type" "fcvt")
3793 (set_attr "mode" "DF")
3794 (set_attr "length" "4")])
3797 (define_insn "floatdidf2"
3798 [(set (match_operand:DF 0 "register_operand" "=f")
3799 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3800 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3802 [(set_attr "type" "fcvt")
3803 (set_attr "mode" "DF")
3804 (set_attr "length" "4")])
3807 (define_insn "floatsisf2"
3808 [(set (match_operand:SF 0 "register_operand" "=f")
3809 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3812 [(set_attr "type" "fcvt")
3813 (set_attr "mode" "SF")
3814 (set_attr "length" "4")])
3817 (define_insn "floatdisf2"
3818 [(set (match_operand:SF 0 "register_operand" "=f")
3819 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3820 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3822 [(set_attr "type" "fcvt")
3823 (set_attr "mode" "SF")
3824 (set_attr "length" "4")])
3827 (define_expand "fixuns_truncdfsi2"
3828 [(set (match_operand:SI 0 "register_operand" "")
3829 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
3830 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3832 rtx reg1 = gen_reg_rtx (DFmode);
3833 rtx reg2 = gen_reg_rtx (DFmode);
3834 rtx reg3 = gen_reg_rtx (SImode);
3835 rtx label1 = gen_label_rtx ();
3836 rtx label2 = gen_label_rtx ();
3837 REAL_VALUE_TYPE offset;
3839 real_2expN (&offset, 31);
3841 if (reg1) /* turn off complaints about unreached code */
3843 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3844 do_pending_stack_adjust ();
3846 emit_insn (gen_cmpdf (operands[1], reg1));
3847 emit_jump_insn (gen_bge (label1));
3849 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3850 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3851 gen_rtx_LABEL_REF (VOIDmode, label2)));
3854 emit_label (label1);
3855 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3856 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
3857 (BITMASK_HIGH, SImode)));
3859 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3860 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3862 emit_label (label2);
3864 /* allow REG_NOTES to be set on last insn (labels don't have enough
3865 fields, and can't be used for REG_NOTES anyway). */
3866 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
3872 (define_expand "fixuns_truncdfdi2"
3873 [(set (match_operand:DI 0 "register_operand" "")
3874 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
3875 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3877 rtx reg1 = gen_reg_rtx (DFmode);
3878 rtx reg2 = gen_reg_rtx (DFmode);
3879 rtx reg3 = gen_reg_rtx (DImode);
3880 rtx label1 = gen_label_rtx ();
3881 rtx label2 = gen_label_rtx ();
3882 REAL_VALUE_TYPE offset;
3884 real_2expN (&offset, 63);
3886 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3887 do_pending_stack_adjust ();
3889 emit_insn (gen_cmpdf (operands[1], reg1));
3890 emit_jump_insn (gen_bge (label1));
3892 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3893 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3894 gen_rtx_LABEL_REF (VOIDmode, label2)));
3897 emit_label (label1);
3898 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3899 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
3900 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3902 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3903 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3905 emit_label (label2);
3907 /* allow REG_NOTES to be set on last insn (labels don't have enough
3908 fields, and can't be used for REG_NOTES anyway). */
3909 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
3914 (define_expand "fixuns_truncsfsi2"
3915 [(set (match_operand:SI 0 "register_operand" "")
3916 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
3919 rtx reg1 = gen_reg_rtx (SFmode);
3920 rtx reg2 = gen_reg_rtx (SFmode);
3921 rtx reg3 = gen_reg_rtx (SImode);
3922 rtx label1 = gen_label_rtx ();
3923 rtx label2 = gen_label_rtx ();
3924 REAL_VALUE_TYPE offset;
3926 real_2expN (&offset, 31);
3928 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3929 do_pending_stack_adjust ();
3931 emit_insn (gen_cmpsf (operands[1], reg1));
3932 emit_jump_insn (gen_bge (label1));
3934 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3935 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3936 gen_rtx_LABEL_REF (VOIDmode, label2)));
3939 emit_label (label1);
3940 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3941 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
3942 (BITMASK_HIGH, SImode)));
3944 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3945 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3947 emit_label (label2);
3949 /* allow REG_NOTES to be set on last insn (labels don't have enough
3950 fields, and can't be used for REG_NOTES anyway). */
3951 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
3956 (define_expand "fixuns_truncsfdi2"
3957 [(set (match_operand:DI 0 "register_operand" "")
3958 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
3959 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3961 rtx reg1 = gen_reg_rtx (SFmode);
3962 rtx reg2 = gen_reg_rtx (SFmode);
3963 rtx reg3 = gen_reg_rtx (DImode);
3964 rtx label1 = gen_label_rtx ();
3965 rtx label2 = gen_label_rtx ();
3966 REAL_VALUE_TYPE offset;
3968 real_2expN (&offset, 63);
3970 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3971 do_pending_stack_adjust ();
3973 emit_insn (gen_cmpsf (operands[1], reg1));
3974 emit_jump_insn (gen_bge (label1));
3976 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3977 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3978 gen_rtx_LABEL_REF (VOIDmode, label2)));
3981 emit_label (label1);
3982 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3983 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
3984 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3986 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3987 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3989 emit_label (label2);
3991 /* allow REG_NOTES to be set on last insn (labels don't have enough
3992 fields, and can't be used for REG_NOTES anyway). */
3993 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
3998 ;; ....................
4002 ;; ....................
4004 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
4006 (define_expand "extv"
4007 [(set (match_operand 0 "register_operand" "")
4008 (sign_extract (match_operand:QI 1 "memory_operand" "")
4009 (match_operand 2 "immediate_operand" "")
4010 (match_operand 3 "immediate_operand" "")))]
4013 if (mips_expand_unaligned_load (operands[0], operands[1],
4014 INTVAL (operands[2]),
4015 INTVAL (operands[3])))
4021 (define_expand "extzv"
4022 [(set (match_operand 0 "register_operand" "")
4023 (zero_extract (match_operand:QI 1 "memory_operand" "")
4024 (match_operand 2 "immediate_operand" "")
4025 (match_operand 3 "immediate_operand" "")))]
4028 if (mips_expand_unaligned_load (operands[0], operands[1],
4029 INTVAL (operands[2]),
4030 INTVAL (operands[3])))
4036 (define_expand "insv"
4037 [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
4038 (match_operand 1 "immediate_operand" "")
4039 (match_operand 2 "immediate_operand" ""))
4040 (match_operand 3 "reg_or_0_operand" ""))]
4043 if (mips_expand_unaligned_store (operands[0], operands[3],
4044 INTVAL (operands[1]),
4045 INTVAL (operands[2])))
4051 ;; Unaligned word moves generated by the bit field patterns.
4053 ;; As far as the rtl is concerned, both the left-part and right-part
4054 ;; instructions can access the whole field. However, the real operand
4055 ;; refers to just the first or the last byte (depending on endianness).
4056 ;; We therefore use two memory operands to each instruction, one to
4057 ;; describe the rtl effect and one to use in the assembly output.
4059 (define_insn "mov_lwl"
4060 [(set (match_operand:SI 0 "register_operand" "=d")
4061 (unspec:SI [(match_operand:BLK 1 "memory_operand" "m")
4062 (match_operand:QI 2 "memory_operand" "m")]
4066 [(set_attr "type" "load")
4067 (set_attr "mode" "SI")
4068 (set_attr "hazard" "none")])
4070 (define_insn "mov_lwr"
4071 [(set (match_operand:SI 0 "register_operand" "=d")
4072 (unspec:SI [(match_operand:BLK 1 "memory_operand" "m")
4073 (match_operand:QI 2 "memory_operand" "m")
4074 (match_operand:SI 3 "register_operand" "0")]
4078 [(set_attr "type" "load")
4079 (set_attr "mode" "SI")])
4082 (define_insn "mov_swl"
4083 [(set (match_operand:BLK 0 "memory_operand" "=m")
4084 (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ")
4085 (match_operand:QI 2 "memory_operand" "m")]
4089 [(set_attr "type" "store")
4090 (set_attr "mode" "SI")])
4092 (define_insn "mov_swr"
4093 [(set (match_operand:BLK 0 "memory_operand" "+m")
4094 (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ")
4095 (match_operand:QI 2 "memory_operand" "m")
4100 [(set_attr "type" "store")
4101 (set_attr "mode" "SI")])
4104 (define_insn "mov_ldl"
4105 [(set (match_operand:DI 0 "register_operand" "=d")
4106 (unspec:DI [(match_operand:BLK 1 "memory_operand" "m")
4107 (match_operand:QI 2 "memory_operand" "m")]
4109 "TARGET_64BIT && !TARGET_MIPS16"
4111 [(set_attr "type" "load")
4112 (set_attr "mode" "DI")])
4114 (define_insn "mov_ldr"
4115 [(set (match_operand:DI 0 "register_operand" "=d")
4116 (unspec:DI [(match_operand:BLK 1 "memory_operand" "m")
4117 (match_operand:QI 2 "memory_operand" "m")
4118 (match_operand:DI 3 "register_operand" "0")]
4120 "TARGET_64BIT && !TARGET_MIPS16"
4122 [(set_attr "type" "load")
4123 (set_attr "mode" "DI")])
4126 (define_insn "mov_sdl"
4127 [(set (match_operand:BLK 0 "memory_operand" "=m")
4128 (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ")
4129 (match_operand:QI 2 "memory_operand" "m")]
4131 "TARGET_64BIT && !TARGET_MIPS16"
4133 [(set_attr "type" "store")
4134 (set_attr "mode" "DI")])
4136 (define_insn "mov_sdr"
4137 [(set (match_operand:BLK 0 "memory_operand" "+m")
4138 (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ")
4139 (match_operand:QI 2 "memory_operand" "m")
4142 "TARGET_64BIT && !TARGET_MIPS16"
4144 [(set_attr "type" "store")
4145 (set_attr "mode" "DI")])
4147 ;; Insns to fetch a global symbol from a big GOT.
4149 (define_insn_and_split "*xgot_hisi"
4150 [(set (match_operand:SI 0 "register_operand" "=d")
4151 (high:SI (match_operand:SI 1 "global_got_operand" "")))]
4152 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4154 "&& reload_completed"
4155 [(set (match_dup 0) (high:SI (match_dup 2)))
4156 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4158 operands[2] = mips_gotoff_global (operands[1]);
4159 operands[3] = pic_offset_table_rtx;
4161 [(set_attr "got" "xgot_high")])
4163 (define_insn_and_split "*xgot_losi"
4164 [(set (match_operand:SI 0 "register_operand" "=d")
4165 (lo_sum:SI (match_operand:SI 1 "register_operand" "d")
4166 (match_operand:SI 2 "global_got_operand" "")))]
4167 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4169 "&& reload_completed"
4170 [(set (match_dup 0) (match_dup 3))]
4171 { operands[3] = mips_load_got_global (operands[1], operands[2]); }
4172 [(set_attr "got" "load")])
4174 (define_insn_and_split "*xgot_hidi"
4175 [(set (match_operand:DI 0 "register_operand" "=d")
4176 (high:DI (match_operand:DI 1 "global_got_operand" "")))]
4177 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4179 "&& reload_completed"
4180 [(set (match_dup 0) (high:DI (match_dup 2)))
4181 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4183 operands[2] = mips_gotoff_global (operands[1]);
4184 operands[3] = pic_offset_table_rtx;
4186 [(set_attr "got" "xgot_high")])
4188 (define_insn_and_split "*xgot_lodi"
4189 [(set (match_operand:DI 0 "register_operand" "=d")
4190 (lo_sum:DI (match_operand:DI 1 "register_operand" "d")
4191 (match_operand:DI 2 "global_got_operand" "")))]
4192 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4194 "&& reload_completed"
4195 [(set (match_dup 0) (match_dup 3))]
4196 { operands[3] = mips_load_got_global (operands[1], operands[2]); }
4197 [(set_attr "got" "load")])
4199 ;; Insns to fetch a global symbol from a normal GOT.
4201 (define_insn_and_split "*got_dispsi"
4202 [(set (match_operand:SI 0 "register_operand" "=d")
4203 (match_operand:SI 1 "global_got_operand" ""))]
4204 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
4206 "&& reload_completed"
4207 [(set (match_dup 0) (match_dup 2))]
4208 { operands[2] = mips_load_got_global (pic_offset_table_rtx, operands[1]); }
4209 [(set_attr "got" "load")])
4211 (define_insn_and_split "*got_dispdi"
4212 [(set (match_operand:DI 0 "register_operand" "=d")
4213 (match_operand:DI 1 "global_got_operand" ""))]
4214 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
4216 "&& reload_completed"
4217 [(set (match_dup 0) (match_dup 2))]
4218 { operands[2] = mips_load_got_global (pic_offset_table_rtx, operands[1]); }
4219 [(set_attr "got" "load")])
4221 ;; Insns for loading the high part of a local symbol.
4223 (define_insn_and_split "*got_pagesi"
4224 [(set (match_operand:SI 0 "register_operand" "=d")
4225 (high:SI (match_operand:SI 1 "local_got_operand" "")))]
4226 "TARGET_EXPLICIT_RELOCS"
4228 "&& reload_completed"
4229 [(set (match_dup 0) (match_dup 2))]
4230 { operands[2] = mips_load_got_page (operands[1]); }
4231 [(set_attr "got" "load")])
4233 (define_insn_and_split "*got_pagedi"
4234 [(set (match_operand:DI 0 "register_operand" "=d")
4235 (high:DI (match_operand:DI 1 "local_got_operand" "")))]
4236 "TARGET_EXPLICIT_RELOCS"
4238 "&& reload_completed"
4239 [(set (match_dup 0) (match_dup 2))]
4240 { operands[2] = mips_load_got_page (operands[1]); }
4241 [(set_attr "got" "load")])
4243 ;; Instructions for adding the low 16 bits of an address to a register.
4244 ;; Operand 2 is the address: print_operand works out which relocation
4245 ;; should be applied.
4247 (define_insn "*lowsi"
4248 [(set (match_operand:SI 0 "register_operand" "=d")
4249 (lo_sum:SI (match_operand:SI 1 "register_operand" "d")
4250 (match_operand:SI 2 "immediate_operand" "")))]
4253 [(set_attr "type" "arith")
4254 (set_attr "mode" "SI")])
4256 (define_insn "*lowdi"
4257 [(set (match_operand:DI 0 "register_operand" "=d")
4258 (lo_sum:DI (match_operand:DI 1 "register_operand" "d")
4259 (match_operand:DI 2 "immediate_operand" "")))]
4260 "!TARGET_MIPS16 && TARGET_64BIT"
4262 [(set_attr "type" "arith")
4263 (set_attr "mode" "DI")])
4265 (define_insn "*lowsi_mips16"
4266 [(set (match_operand:SI 0 "register_operand" "=d")
4267 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
4268 (match_operand:SI 2 "immediate_operand" "")))]
4271 [(set_attr "type" "arith")
4272 (set_attr "mode" "SI")
4273 (set_attr "length" "8")])
4275 (define_insn "*lowdi_mips16"
4276 [(set (match_operand:DI 0 "register_operand" "=d")
4277 (lo_sum:DI (match_operand:DI 1 "register_operand" "0")
4278 (match_operand:DI 2 "immediate_operand" "")))]
4279 "TARGET_MIPS16 && TARGET_64BIT"
4281 [(set_attr "type" "arith")
4282 (set_attr "mode" "DI")
4283 (set_attr "length" "8")])
4285 ;; 64-bit integer moves
4287 ;; Unlike most other insns, the move insns can't be split with
4288 ;; different predicates, because register spilling and other parts of
4289 ;; the compiler, have memoized the insn number already.
4291 (define_expand "movdi"
4292 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4293 (match_operand:DI 1 "" ""))]
4296 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4299 /* If we are generating embedded PIC code, and we are referring to a
4300 symbol in the .text section, we must use an offset from the start
4302 if (TARGET_EMBEDDED_PIC
4303 && (GET_CODE (operands[1]) == LABEL_REF
4304 || (GET_CODE (operands[1]) == SYMBOL_REF
4305 && ! SYMBOL_REF_FLAG (operands[1]))))
4309 temp = embedded_pic_offset (operands[1]);
4310 temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
4311 force_reg (DImode, temp));
4312 emit_move_insn (operands[0], force_reg (DImode, temp));
4317 ;; For mips16, we need a special case to handle storing $31 into
4318 ;; memory, since we don't have a constraint to match $31. This
4319 ;; instruction can be generated by save_restore_insns.
4322 [(set (match_operand:DI 0 "stack_operand" "=m")
4324 "TARGET_MIPS16 && TARGET_64BIT"
4326 [(set_attr "type" "store")
4327 (set_attr "mode" "DI")])
4329 (define_insn "movdi_internal"
4330 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*x,*d,*x,*B*C*D,*B*C*D,*d,*m")
4331 (match_operand:DI 1 "general_operand" "d,iF,m,d,J,*x,*d,*d,*m,*B*C*D,*B*C*D"))]
4332 "!TARGET_64BIT && !TARGET_MIPS16
4333 && (register_operand (operands[0], DImode)
4334 || register_operand (operands[1], DImode)
4335 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
4336 || operands[1] == CONST0_RTX (DImode))"
4337 { return mips_output_move (operands[0], operands[1]); }
4338 [(set_attr "type" "move,arith,load,store,hilo,hilo,hilo,xfer,load,xfer,store")
4339 (set_attr "mode" "DI")
4340 (set_attr "length" "8,16,*,*,8,8,8,8,*,8,*")])
4343 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4344 (match_operand:DI 1 "general_operand" "d,d,y,K,N,m,d,*x"))]
4345 "!TARGET_64BIT && TARGET_MIPS16
4346 && (register_operand (operands[0], DImode)
4347 || register_operand (operands[1], DImode))"
4348 { return mips_output_move (operands[0], operands[1]); }
4349 [(set_attr "type" "move,move,move,arith,arith,load,store,hilo")
4350 (set_attr "mode" "DI")
4351 (set_attr "length" "8,8,8,8,12,*,*,8")])
4353 (define_insn "movdi_internal2"
4354 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*d,*x,*B*C*D,*B*C*D,*d,*m")
4355 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J,*x,*d,*d,*m,*B*C*D,*B*C*D"))]
4356 "TARGET_64BIT && !TARGET_MIPS16
4357 && (register_operand (operands[0], DImode)
4358 || register_operand (operands[1], DImode)
4359 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
4360 || operands[1] == CONST0_RTX (DImode))"
4361 { return mips_output_move (operands[0], operands[1]); }
4362 [(set_attr "type" "move,const,const,load,store,move,xfer,load,xfer,store,hilo,hilo,hilo,xfer,load,xfer,store")
4363 (set_attr "mode" "DI")
4364 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,8,*,8,*")])
4366 (define_insn "*movdi_internal2_mips16"
4367 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m,*d")
4368 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d,*x"))]
4369 "TARGET_64BIT && TARGET_MIPS16
4370 && (register_operand (operands[0], DImode)
4371 || register_operand (operands[1], DImode))"
4372 { return mips_output_move (operands[0], operands[1]); }
4373 [(set_attr "type" "move,move,move,arith,arith,const,load,store,hilo")
4374 (set_attr "mode" "DI")
4375 (set_attr_alternative "length"
4379 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
4382 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
4391 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4392 ;; when the original load is a 4 byte instruction but the add and the
4393 ;; load are 2 2 byte instructions.
4396 [(set (match_operand:DI 0 "register_operand" "")
4397 (mem:DI (plus:DI (match_dup 0)
4398 (match_operand:DI 1 "const_int_operand" ""))))]
4399 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4400 && !TARGET_DEBUG_D_MODE
4401 && GET_CODE (operands[0]) == REG
4402 && M16_REG_P (REGNO (operands[0]))
4403 && GET_CODE (operands[1]) == CONST_INT
4404 && ((INTVAL (operands[1]) < 0
4405 && INTVAL (operands[1]) >= -0x10)
4406 || (INTVAL (operands[1]) >= 32 * 8
4407 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4408 || (INTVAL (operands[1]) >= 0
4409 && INTVAL (operands[1]) < 32 * 8
4410 && (INTVAL (operands[1]) & 7) != 0))"
4411 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4412 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4414 HOST_WIDE_INT val = INTVAL (operands[1]);
4417 operands[2] = GEN_INT (0);
4418 else if (val >= 32 * 8)
4422 operands[1] = GEN_INT (0x8 + off);
4423 operands[2] = GEN_INT (val - off - 0x8);
4429 operands[1] = GEN_INT (off);
4430 operands[2] = GEN_INT (val - off);
4434 ;; 32-bit Integer moves
4436 ;; Unlike most other insns, the move insns can't be split with
4437 ;; different predicates, because register spilling and other parts of
4438 ;; the compiler, have memoized the insn number already.
4440 (define_expand "movsi"
4441 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4442 (match_operand:SI 1 "" ""))]
4445 if (mips_legitimize_move (SImode, operands[0], operands[1]))
4448 /* If we are generating embedded PIC code, and we are referring to a
4449 symbol in the .text section, we must use an offset from the start
4451 if (TARGET_EMBEDDED_PIC
4452 && (GET_CODE (operands[1]) == LABEL_REF
4453 || (GET_CODE (operands[1]) == SYMBOL_REF
4454 && ! SYMBOL_REF_FLAG (operands[1]))))
4458 temp = embedded_pic_offset (operands[1]);
4459 temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
4460 force_reg (SImode, temp));
4461 emit_move_insn (operands[0], force_reg (SImode, temp));
4466 ;; We can only store $ra directly into a small sp offset.
4469 [(set (match_operand:SI 0 "stack_operand" "=m")
4473 [(set_attr "type" "store")
4474 (set_attr "mode" "SI")])
4476 ;; The difference between these two is whether or not ints are allowed
4477 ;; in FP registers (off by default, use -mdebugh to enable).
4479 (define_insn "movsi_internal"
4480 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*x,*d,*x,*B*C*D,*B*C*D,*d,*m")
4481 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,J,*x,*d,*d,*m,*B*C*D,*B*C*D"))]
4483 && (register_operand (operands[0], SImode)
4484 || register_operand (operands[1], SImode)
4485 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
4486 { return mips_output_move (operands[0], operands[1]); }
4487 [(set_attr "type" "move,const,const,load,store,move,xfer,load,xfer,store,xfer,xfer,hilo,hilo,hilo,xfer,load,xfer,store")
4488 (set_attr "mode" "SI")
4489 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,4,*,4,*")])
4492 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m,*d")
4493 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d,*x"))]
4495 && (register_operand (operands[0], SImode)
4496 || register_operand (operands[1], SImode))"
4497 { return mips_output_move (operands[0], operands[1]); }
4498 [(set_attr "type" "move,move,move,arith,arith,const,load,store,hilo")
4499 (set_attr "mode" "SI")
4500 (set_attr_alternative "length"
4504 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
4507 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
4515 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4516 ;; when the original load is a 4 byte instruction but the add and the
4517 ;; load are 2 2 byte instructions.
4520 [(set (match_operand:SI 0 "register_operand" "")
4521 (mem:SI (plus:SI (match_dup 0)
4522 (match_operand:SI 1 "const_int_operand" ""))))]
4523 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4524 && GET_CODE (operands[0]) == REG
4525 && M16_REG_P (REGNO (operands[0]))
4526 && GET_CODE (operands[1]) == CONST_INT
4527 && ((INTVAL (operands[1]) < 0
4528 && INTVAL (operands[1]) >= -0x80)
4529 || (INTVAL (operands[1]) >= 32 * 4
4530 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4531 || (INTVAL (operands[1]) >= 0
4532 && INTVAL (operands[1]) < 32 * 4
4533 && (INTVAL (operands[1]) & 3) != 0))"
4534 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4535 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4537 HOST_WIDE_INT val = INTVAL (operands[1]);
4540 operands[2] = GEN_INT (0);
4541 else if (val >= 32 * 4)
4545 operands[1] = GEN_INT (0x7c + off);
4546 operands[2] = GEN_INT (val - off - 0x7c);
4552 operands[1] = GEN_INT (off);
4553 operands[2] = GEN_INT (val - off);
4557 ;; On the mips16, we can split a load of certain constants into a load
4558 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4562 [(set (match_operand:SI 0 "register_operand" "")
4563 (match_operand:SI 1 "const_int_operand" ""))]
4564 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4565 && GET_CODE (operands[0]) == REG
4566 && M16_REG_P (REGNO (operands[0]))
4567 && GET_CODE (operands[1]) == CONST_INT
4568 && INTVAL (operands[1]) >= 0x100
4569 && INTVAL (operands[1]) <= 0xff + 0x7f"
4570 [(set (match_dup 0) (match_dup 1))
4571 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4573 int val = INTVAL (operands[1]);
4575 operands[1] = GEN_INT (0xff);
4576 operands[2] = GEN_INT (val - 0xff);
4579 ;; On the mips16, we can split a load of a negative constant into a
4580 ;; load and a neg. That's what mips_output_move will generate anyhow.
4583 [(set (match_operand:SI 0 "register_operand" "")
4584 (match_operand:SI 1 "const_int_operand" ""))]
4585 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4586 && GET_CODE (operands[0]) == REG
4587 && M16_REG_P (REGNO (operands[0]))
4588 && GET_CODE (operands[1]) == CONST_INT
4589 && INTVAL (operands[1]) < 0
4590 && INTVAL (operands[1]) > - 0x8000"
4591 [(set (match_dup 0) (match_dup 1))
4592 (set (match_dup 0) (neg:SI (match_dup 0)))]
4593 { operands[1] = GEN_INT (- INTVAL (operands[1])); })
4595 ;; This insn handles moving CCmode values. It's really just a
4596 ;; slightly simplified copy of movsi_internal2, with additional cases
4597 ;; to move a condition register to a general register and to move
4598 ;; between the general registers and the floating point registers.
4600 (define_insn "movcc"
4601 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4602 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4603 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4604 { return mips_output_move (operands[0], operands[1]); }
4605 [(set_attr "type" "move,move,load,store,xfer,xfer,move,load,store")
4606 (set_attr "mode" "SI")
4607 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
4609 ;; Reload condition code registers. reload_incc and reload_outcc
4610 ;; both handle moves from arbitrary operands into condition code
4611 ;; registers. reload_incc handles the more common case in which
4612 ;; a source operand is constrained to be in a condition-code
4613 ;; register, but has not been allocated to one.
4615 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4616 ;; constraints do not include 'z'. reload_outcc handles the case
4617 ;; when such an operand is allocated to a condition-code register.
4619 ;; Note that reloads from a condition code register to some
4620 ;; other location can be done using ordinary moves. Moving
4621 ;; into a GPR takes a single movcc, moving elsewhere takes
4622 ;; two. We can leave these cases to the generic reload code.
4623 (define_expand "reload_incc"
4624 [(set (match_operand:CC 0 "fcc_register_operand" "=z")
4625 (match_operand:CC 1 "general_operand" ""))
4626 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4627 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4629 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
4633 (define_expand "reload_outcc"
4634 [(set (match_operand:CC 0 "fcc_register_operand" "=z")
4635 (match_operand:CC 1 "register_operand" ""))
4636 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4637 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4639 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
4643 ;; MIPS4 supports loading and storing a floating point register from
4644 ;; the sum of two general registers. We use two versions for each of
4645 ;; these four instructions: one where the two general registers are
4646 ;; SImode, and one where they are DImode. This is because general
4647 ;; registers will be in SImode when they hold 32 bit values, but,
4648 ;; since the 32 bit values are always sign extended, the [ls][wd]xc1
4649 ;; instructions will still work correctly.
4651 ;; ??? Perhaps it would be better to support these instructions by
4652 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
4653 ;; these instructions can only be used to load and store floating
4654 ;; point registers, that would probably cause trouble in reload.
4657 [(set (match_operand:SF 0 "register_operand" "=f")
4658 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
4659 (match_operand:SI 2 "register_operand" "d"))))]
4660 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
4662 [(set_attr "type" "load")
4663 (set_attr "mode" "SF")
4664 (set_attr "length" "4")])
4667 [(set (match_operand:SF 0 "register_operand" "=f")
4668 (mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d")
4669 (match_operand:DI 2 "register_operand" "d"))))]
4670 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
4672 [(set_attr "type" "load")
4673 (set_attr "mode" "SF")
4674 (set_attr "length" "4")])
4677 [(set (match_operand:DF 0 "register_operand" "=f")
4678 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
4679 (match_operand:SI 2 "register_operand" "d"))))]
4680 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4682 [(set_attr "type" "load")
4683 (set_attr "mode" "DF")
4684 (set_attr "length" "4")])
4687 [(set (match_operand:DF 0 "register_operand" "=f")
4688 (mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d")
4689 (match_operand:DI 2 "register_operand" "d"))))]
4690 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4692 [(set_attr "type" "load")
4693 (set_attr "mode" "DF")
4694 (set_attr "length" "4")])
4697 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
4698 (match_operand:SI 2 "register_operand" "d")))
4699 (match_operand:SF 0 "register_operand" "f"))]
4700 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
4702 [(set_attr "type" "store")
4703 (set_attr "mode" "SF")
4704 (set_attr "length" "4")])
4707 [(set (mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d")
4708 (match_operand:DI 2 "register_operand" "d")))
4709 (match_operand:SF 0 "register_operand" "f"))]
4710 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
4712 [(set_attr "type" "store")
4713 (set_attr "mode" "SF")
4714 (set_attr "length" "4")])
4717 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
4718 (match_operand:SI 2 "register_operand" "d")))
4719 (match_operand:DF 0 "register_operand" "f"))]
4720 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4722 [(set_attr "type" "store")
4723 (set_attr "mode" "DF")
4724 (set_attr "length" "4")])
4727 [(set (mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d")
4728 (match_operand:DI 2 "register_operand" "d")))
4729 (match_operand:DF 0 "register_operand" "f"))]
4730 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4732 [(set_attr "type" "store")
4733 (set_attr "mode" "DF")
4734 (set_attr "length" "4")])
4736 ;; 16-bit Integer moves
4738 ;; Unlike most other insns, the move insns can't be split with
4739 ;; different predicates, because register spilling and other parts of
4740 ;; the compiler, have memoized the insn number already.
4741 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4743 (define_expand "movhi"
4744 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4745 (match_operand:HI 1 "general_operand" ""))]
4748 if ((reload_in_progress | reload_completed) == 0
4749 && !register_operand (operands[0], HImode)
4750 && !register_operand (operands[1], HImode)
4752 || (GET_CODE (operands[1]) != CONST_INT
4753 || INTVAL (operands[1]) != 0)))
4755 rtx temp = force_reg (HImode, operands[1]);
4756 emit_move_insn (operands[0], temp);
4761 (define_insn "movhi_internal"
4762 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x,*d")
4763 (match_operand:HI 1 "general_operand" "d,IK,m,dJ,*f,*d,*f,*d,*x"))]
4765 && (register_operand (operands[0], HImode)
4766 || register_operand (operands[1], HImode)
4767 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
4778 [(set_attr "type" "move,arith,load,store,xfer,xfer,move,hilo,hilo")
4779 (set_attr "mode" "HI")
4780 (set_attr "length" "4,4,*,*,4,4,4,4,4")])
4783 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4784 (match_operand:HI 1 "general_operand" "d,d,y,K,N,m,d,*x"))]
4786 && (register_operand (operands[0], HImode)
4787 || register_operand (operands[1], HImode))"
4797 [(set_attr "type" "move,move,move,arith,arith,load,store,hilo")
4798 (set_attr "mode" "HI")
4799 (set_attr_alternative "length"
4803 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
4806 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
4814 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4815 ;; when the original load is a 4 byte instruction but the add and the
4816 ;; load are 2 2 byte instructions.
4819 [(set (match_operand:HI 0 "register_operand" "")
4820 (mem:HI (plus:SI (match_dup 0)
4821 (match_operand:SI 1 "const_int_operand" ""))))]
4822 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4823 && GET_CODE (operands[0]) == REG
4824 && M16_REG_P (REGNO (operands[0]))
4825 && GET_CODE (operands[1]) == CONST_INT
4826 && ((INTVAL (operands[1]) < 0
4827 && INTVAL (operands[1]) >= -0x80)
4828 || (INTVAL (operands[1]) >= 32 * 2
4829 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4830 || (INTVAL (operands[1]) >= 0
4831 && INTVAL (operands[1]) < 32 * 2
4832 && (INTVAL (operands[1]) & 1) != 0))"
4833 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4834 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4836 HOST_WIDE_INT val = INTVAL (operands[1]);
4839 operands[2] = GEN_INT (0);
4840 else if (val >= 32 * 2)
4844 operands[1] = GEN_INT (0x7e + off);
4845 operands[2] = GEN_INT (val - off - 0x7e);
4851 operands[1] = GEN_INT (off);
4852 operands[2] = GEN_INT (val - off);
4856 ;; 8-bit Integer moves
4858 ;; Unlike most other insns, the move insns can't be split with
4859 ;; different predicates, because register spilling and other parts of
4860 ;; the compiler, have memoized the insn number already.
4861 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4863 (define_expand "movqi"
4864 [(set (match_operand:QI 0 "nonimmediate_operand" "")
4865 (match_operand:QI 1 "general_operand" ""))]
4868 if ((reload_in_progress | reload_completed) == 0
4869 && !register_operand (operands[0], QImode)
4870 && !register_operand (operands[1], QImode)
4872 || (GET_CODE (operands[1]) != CONST_INT
4873 || INTVAL (operands[1]) != 0)))
4875 rtx temp = force_reg (QImode, operands[1]);
4876 emit_move_insn (operands[0], temp);
4881 (define_insn "movqi_internal"
4882 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x,*d")
4883 (match_operand:QI 1 "general_operand" "d,IK,m,dJ,*f,*d,*f,*d,*x"))]
4885 && (register_operand (operands[0], QImode)
4886 || register_operand (operands[1], QImode)
4887 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
4898 [(set_attr "type" "move,arith,load,store,xfer,xfer,move,hilo,hilo")
4899 (set_attr "mode" "QI")
4900 (set_attr "length" "4,4,*,*,4,4,4,4,4")])
4903 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4904 (match_operand:QI 1 "general_operand" "d,d,y,K,N,m,d,*x"))]
4906 && (register_operand (operands[0], QImode)
4907 || register_operand (operands[1], QImode))"
4917 [(set_attr "type" "move,move,move,arith,arith,load,store,hilo")
4918 (set_attr "mode" "QI")
4919 (set_attr "length" "4,4,4,4,8,*,*,4")])
4921 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4922 ;; when the original load is a 4 byte instruction but the add and the
4923 ;; load are 2 2 byte instructions.
4926 [(set (match_operand:QI 0 "register_operand" "")
4927 (mem:QI (plus:SI (match_dup 0)
4928 (match_operand:SI 1 "const_int_operand" ""))))]
4929 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4930 && GET_CODE (operands[0]) == REG
4931 && M16_REG_P (REGNO (operands[0]))
4932 && GET_CODE (operands[1]) == CONST_INT
4933 && ((INTVAL (operands[1]) < 0
4934 && INTVAL (operands[1]) >= -0x80)
4935 || (INTVAL (operands[1]) >= 32
4936 && INTVAL (operands[1]) <= 31 + 0x7f))"
4937 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4938 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4940 HOST_WIDE_INT val = INTVAL (operands[1]);
4943 operands[2] = GEN_INT (0);
4946 operands[1] = GEN_INT (0x7f);
4947 operands[2] = GEN_INT (val - 0x7f);
4951 ;; 32-bit floating point moves
4953 (define_expand "movsf"
4954 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4955 (match_operand:SF 1 "general_operand" ""))]
4958 if ((reload_in_progress | reload_completed) == 0
4959 && !register_operand (operands[0], SFmode)
4960 && !nonmemory_operand (operands[1], SFmode))
4961 operands[1] = force_reg (SFmode, operands[1]);
4964 (define_insn "movsf_internal1"
4965 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
4966 (match_operand:SF 1 "general_operand" "f,G,m,fG,*d,*f,*G*d,*m,*d"))]
4968 && (register_operand (operands[0], SFmode)
4969 || nonmemory_operand (operands[1], SFmode))"
4970 { return mips_output_move (operands[0], operands[1]); }
4971 [(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
4972 (set_attr "mode" "SF")
4973 (set_attr "length" "4,4,*,*,4,4,4,*,*")])
4975 (define_insn "movsf_internal2"
4976 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4977 (match_operand:SF 1 "general_operand" " Gd,m,d"))]
4978 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4979 && (register_operand (operands[0], SFmode)
4980 || nonmemory_operand (operands[1], SFmode))"
4981 { return mips_output_move (operands[0], operands[1]); }
4982 [(set_attr "type" "move,load,store")
4983 (set_attr "mode" "SF")
4984 (set_attr "length" "4,*,*")])
4987 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4988 (match_operand:SF 1 "nonimmediate_operand" "d,d,y,m,d"))]
4990 && (register_operand (operands[0], SFmode)
4991 || register_operand (operands[1], SFmode))"
4992 { return mips_output_move (operands[0], operands[1]); }
4993 [(set_attr "type" "move,move,move,load,store")
4994 (set_attr "mode" "SF")
4995 (set_attr "length" "4,4,4,*,*")])
4998 ;; 64-bit floating point moves
5000 (define_expand "movdf"
5001 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5002 (match_operand:DF 1 "general_operand" ""))]
5005 if ((reload_in_progress | reload_completed) == 0
5006 && !register_operand (operands[0], DFmode)
5007 && !nonmemory_operand (operands[1], DFmode))
5008 operands[1] = force_reg (DFmode, operands[1]);
5011 (define_insn "movdf_internal1a"
5012 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
5013 (match_operand:DF 1 "general_operand" "f,G,m,fG,*d,*f,*d*G,*m,*d"))]
5014 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
5015 && (register_operand (operands[0], DFmode)
5016 || nonmemory_operand (operands[1], DFmode))"
5017 { return mips_output_move (operands[0], operands[1]); }
5018 [(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
5019 (set_attr "mode" "DF")
5020 (set_attr "length" "4,4,*,*,4,4,4,*,*")])
5022 (define_insn "movdf_internal1b"
5023 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
5024 (match_operand:DF 1 "general_operand" "f,G,m,fG,*d,*f,*d*G,*m,*d"))]
5025 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
5026 && (register_operand (operands[0], DFmode)
5027 || nonmemory_operand (operands[1], DFmode))"
5028 { return mips_output_move (operands[0], operands[1]); }
5029 [(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
5030 (set_attr "mode" "DF")
5031 (set_attr "length" "4,8,*,*,8,8,8,*,*")])
5033 (define_insn "movdf_internal2"
5034 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
5035 (match_operand:DF 1 "general_operand" "dG,m,dG,f,d,f"))]
5036 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
5037 && (register_operand (operands[0], DFmode)
5038 || nonmemory_operand (operands[1], DFmode))"
5039 { return mips_output_move (operands[0], operands[1]); }
5040 [(set_attr "type" "move,load,store,xfer,xfer,move")
5041 (set_attr "mode" "DF")
5042 (set_attr "length" "8,*,*,4,4,4")])
5045 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
5046 (match_operand:DF 1 "nonimmediate_operand" "d,d,y,m,d"))]
5048 && (register_operand (operands[0], DFmode)
5049 || register_operand (operands[1], DFmode))"
5050 { return mips_output_move (operands[0], operands[1]); }
5051 [(set_attr "type" "move,move,move,load,store")
5052 (set_attr "mode" "DF")
5053 (set_attr "length" "8,8,8,*,*")])
5056 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5057 (match_operand:DI 1 "general_operand" ""))]
5058 "reload_completed && !TARGET_64BIT
5059 && mips_split_64bit_move_p (operands[0], operands[1])"
5062 mips_split_64bit_move (operands[0], operands[1]);
5067 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5068 (match_operand:DF 1 "general_operand" ""))]
5069 "reload_completed && !TARGET_64BIT
5070 && mips_split_64bit_move_p (operands[0], operands[1])"
5073 mips_split_64bit_move (operands[0], operands[1]);
5077 ;; Patterns for loading or storing part of a paired floating point
5078 ;; register. We need them because odd-numbered floating-point registers
5079 ;; are not fully independent: see mips_split_64bit_move.
5081 ;; Load the low word of operand 0 with operand 1.
5082 (define_insn "load_df_low"
5083 [(set (match_operand:DF 0 "register_operand" "=f,f")
5084 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
5085 UNSPEC_LOAD_DF_LOW))]
5086 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
5088 operands[0] = mips_subword (operands[0], 0);
5089 return mips_output_move (operands[0], operands[1]);
5091 [(set_attr "type" "xfer,load")
5092 (set_attr "mode" "SF")
5093 (set_attr "length" "4")])
5095 ;; Load the high word of operand 0 from operand 1, preserving the value
5097 (define_insn "load_df_high"
5098 [(set (match_operand:DF 0 "register_operand" "=f,f")
5099 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
5100 (match_operand:DF 2 "register_operand" "0,0")]
5101 UNSPEC_LOAD_DF_HIGH))]
5102 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
5104 operands[0] = mips_subword (operands[0], 1);
5105 return mips_output_move (operands[0], operands[1]);
5107 [(set_attr "type" "xfer,load")
5108 (set_attr "mode" "SF")
5109 (set_attr "length" "4")])
5111 ;; Store the high word of operand 1 in operand 0. The corresponding
5112 ;; low-word move is done in the normal way.
5113 (define_insn "store_df_high"
5114 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
5115 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
5116 UNSPEC_STORE_DF_HIGH))]
5117 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
5119 operands[1] = mips_subword (operands[1], 1);
5120 return mips_output_move (operands[0], operands[1]);
5122 [(set_attr "type" "xfer,store")
5123 (set_attr "mode" "SF")
5124 (set_attr "length" "4")])
5126 (define_insn_and_split "loadgp"
5127 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
5128 "TARGET_ABICALLS && TARGET_NEWABI"
5131 [(set (match_dup 1) (match_dup 2))
5132 (set (match_dup 1) (match_dup 3))
5133 (set (match_dup 1) (match_dup 4))]
5135 operands[1] = pic_offset_table_rtx;
5136 operands[2] = gen_rtx_HIGH (Pmode, operands[0]);
5137 operands[3] = gen_rtx_PLUS (Pmode, operands[1],
5138 gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM));
5139 operands[4] = gen_rtx_LO_SUM (Pmode, operands[1], operands[0]);
5141 [(set_attr "length" "12")])
5143 ;; The use of gp is hidden when not using explicit relocations.
5144 ;; This blockage instruction prevents the gp load from being
5145 ;; scheduled after an implicit use of gp. It also prevents
5146 ;; the load from being deleted as dead.
5147 (define_insn "loadgp_blockage"
5148 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
5151 [(set_attr "type" "unknown")
5152 (set_attr "mode" "none")
5153 (set_attr "length" "0")])
5155 ;; Emit a .cprestore directive, which expands to a single store instruction.
5156 ;; Note that we continue to use .cprestore for explicit reloc code so that
5157 ;; jals inside inlines asms will work correctly.
5158 (define_insn "cprestore"
5159 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
5163 [(set_attr "type" "store")
5164 (set_attr "length" "4")])
5166 ;; Block moves, see mips.c for more details.
5167 ;; Argument 0 is the destination
5168 ;; Argument 1 is the source
5169 ;; Argument 2 is the length
5170 ;; Argument 3 is the alignment
5172 (define_expand "movstrsi"
5173 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
5174 (match_operand:BLK 1 "general_operand" ""))
5175 (use (match_operand:SI 2 "" ""))
5176 (use (match_operand:SI 3 "const_int_operand" ""))])]
5177 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5179 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5186 ;; ....................
5190 ;; ....................
5192 ;; Many of these instructions use trivial define_expands, because we
5193 ;; want to use a different set of constraints when TARGET_MIPS16.
5195 (define_expand "ashlsi3"
5196 [(set (match_operand:SI 0 "register_operand" "=d")
5197 (ashift:SI (match_operand:SI 1 "register_operand" "d")
5198 (match_operand:SI 2 "arith_operand" "dI")))]
5201 /* On the mips16, a shift of more than 8 is a four byte instruction,
5202 so, for a shift between 8 and 16, it is just as fast to do two
5203 shifts of 8 or less. If there is a lot of shifting going on, we
5204 may win in CSE. Otherwise combine will put the shifts back
5205 together again. This can be called by function_arg, so we must
5206 be careful not to allocate a new register if we've reached the
5210 && GET_CODE (operands[2]) == CONST_INT
5211 && INTVAL (operands[2]) > 8
5212 && INTVAL (operands[2]) <= 16
5213 && ! reload_in_progress
5214 && ! reload_completed)
5216 rtx temp = gen_reg_rtx (SImode);
5218 emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
5219 emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
5220 GEN_INT (INTVAL (operands[2]) - 8)));
5225 (define_insn "ashlsi3_internal1"
5226 [(set (match_operand:SI 0 "register_operand" "=d")
5227 (ashift:SI (match_operand:SI 1 "register_operand" "d")
5228 (match_operand:SI 2 "arith_operand" "dI")))]
5231 if (GET_CODE (operands[2]) == CONST_INT)
5232 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5234 return "sll\t%0,%1,%2";
5236 [(set_attr "type" "arith")
5237 (set_attr "mode" "SI")])
5239 (define_insn "ashlsi3_internal1_extend"
5240 [(set (match_operand:DI 0 "register_operand" "=d")
5241 (sign_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "d")
5242 (match_operand:SI 2 "arith_operand" "dI"))))]
5243 "TARGET_64BIT && !TARGET_MIPS16"
5245 if (GET_CODE (operands[2]) == CONST_INT)
5246 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5248 return "sll\t%0,%1,%2";
5250 [(set_attr "type" "arith")
5251 (set_attr "mode" "DI")])
5254 (define_insn "ashlsi3_internal2"
5255 [(set (match_operand:SI 0 "register_operand" "=d,d")
5256 (ashift:SI (match_operand:SI 1 "register_operand" "0,d")
5257 (match_operand:SI 2 "arith_operand" "d,I")))]
5260 if (which_alternative == 0)
5261 return "sll\t%0,%2";
5263 if (GET_CODE (operands[2]) == CONST_INT)
5264 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5266 return "sll\t%0,%1,%2";
5268 [(set_attr "type" "arith")
5269 (set_attr "mode" "SI")
5270 (set_attr_alternative "length"
5272 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
5276 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5279 [(set (match_operand:SI 0 "register_operand" "")
5280 (ashift:SI (match_operand:SI 1 "register_operand" "")
5281 (match_operand:SI 2 "const_int_operand" "")))]
5282 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5283 && GET_CODE (operands[2]) == CONST_INT
5284 && INTVAL (operands[2]) > 8
5285 && INTVAL (operands[2]) <= 16"
5286 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
5287 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
5288 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5290 (define_expand "ashldi3"
5291 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5292 (ashift:DI (match_operand:DI 1 "register_operand" "")
5293 (match_operand:SI 2 "arith_operand" "")))
5294 (clobber (match_dup 3))])]
5295 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
5299 /* On the mips16, a shift of more than 8 is a four byte
5300 instruction, so, for a shift between 8 and 16, it is just as
5301 fast to do two shifts of 8 or less. If there is a lot of
5302 shifting going on, we may win in CSE. Otherwise combine will
5303 put the shifts back together again. This can be called by
5304 function_arg, so we must be careful not to allocate a new
5305 register if we've reached the reload pass. */
5308 && GET_CODE (operands[2]) == CONST_INT
5309 && INTVAL (operands[2]) > 8
5310 && INTVAL (operands[2]) <= 16
5311 && ! reload_in_progress
5312 && ! reload_completed)
5314 rtx temp = gen_reg_rtx (DImode);
5316 emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
5317 emit_insn (gen_ashldi3_internal4 (operands[0], temp,
5318 GEN_INT (INTVAL (operands[2]) - 8)));
5322 emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
5327 operands[3] = gen_reg_rtx (SImode);
5331 (define_insn "ashldi3_internal"
5332 [(set (match_operand:DI 0 "register_operand" "=&d")
5333 (ashift:DI (match_operand:DI 1 "register_operand" "d")
5334 (match_operand:SI 2 "register_operand" "d")))
5335 (clobber (match_operand:SI 3 "register_operand" "=d"))]
5336 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
5353 [(set_attr "type" "darith")
5354 (set_attr "mode" "SI")
5355 (set_attr "length" "48")])
5358 (define_insn "ashldi3_internal2"
5359 [(set (match_operand:DI 0 "register_operand" "=d")
5360 (ashift:DI (match_operand:DI 1 "register_operand" "d")
5361 (match_operand:SI 2 "small_int" "IJK")))
5362 (clobber (match_operand:SI 3 "register_operand" "=d"))]
5363 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5364 && (INTVAL (operands[2]) & 32) != 0"
5366 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5367 return "sll\t%M0,%L1,%2\;move\t%L0,%.";
5369 [(set_attr "type" "darith")
5370 (set_attr "mode" "DI")
5371 (set_attr "length" "8")])
5375 [(set (match_operand:DI 0 "register_operand" "")
5376 (ashift:DI (match_operand:DI 1 "register_operand" "")
5377 (match_operand:SI 2 "small_int" "")))
5378 (clobber (match_operand:SI 3 "register_operand" ""))]
5379 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
5380 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5381 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
5382 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
5383 && (INTVAL (operands[2]) & 32) != 0"
5385 [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
5386 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
5388 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
5392 [(set (match_operand:DI 0 "register_operand" "")
5393 (ashift:DI (match_operand:DI 1 "register_operand" "")
5394 (match_operand:SI 2 "small_int" "")))
5395 (clobber (match_operand:SI 3 "register_operand" ""))]
5396 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
5397 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5398 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
5399 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
5400 && (INTVAL (operands[2]) & 32) != 0"
5402 [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
5403 (set (subreg:SI (match_dup 0) 4) (const_int 0))]
5405 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
5408 (define_insn "ashldi3_internal3"
5409 [(set (match_operand:DI 0 "register_operand" "=d")
5410 (ashift:DI (match_operand:DI 1 "register_operand" "d")
5411 (match_operand:SI 2 "small_int" "IJK")))
5412 (clobber (match_operand:SI 3 "register_operand" "=d"))]
5413 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5414 && (INTVAL (operands[2]) & 63) < 32
5415 && (INTVAL (operands[2]) & 63) != 0"
5417 int amount = INTVAL (operands[2]);
5419 operands[2] = GEN_INT (amount & 31);
5420 operands[4] = GEN_INT ((-amount) & 31);
5422 return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
5424 [(set_attr "type" "darith")
5425 (set_attr "mode" "DI")
5426 (set_attr "length" "16")])
5430 [(set (match_operand:DI 0 "register_operand" "")
5431 (ashift:DI (match_operand:DI 1 "register_operand" "")
5432 (match_operand:SI 2 "small_int" "")))
5433 (clobber (match_operand:SI 3 "register_operand" ""))]
5434 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
5435 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5436 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
5437 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
5438 && (INTVAL (operands[2]) & 63) < 32
5439 && (INTVAL (operands[2]) & 63) != 0"
5441 [(set (subreg:SI (match_dup 0) 4)
5442 (ashift:SI (subreg:SI (match_dup 1) 4)
5446 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
5449 (set (subreg:SI (match_dup 0) 4)
5450 (ior:SI (subreg:SI (match_dup 0) 4)
5453 (set (subreg:SI (match_dup 0) 0)
5454 (ashift:SI (subreg:SI (match_dup 1) 0)
5457 int amount = INTVAL (operands[2]);
5458 operands[2] = GEN_INT (amount & 31);
5459 operands[4] = GEN_INT ((-amount) & 31);
5464 [(set (match_operand:DI 0 "register_operand" "")
5465 (ashift:DI (match_operand:DI 1 "register_operand" "")
5466 (match_operand:SI 2 "small_int" "")))
5467 (clobber (match_operand:SI 3 "register_operand" ""))]
5468 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
5469 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5470 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
5471 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
5472 && (INTVAL (operands[2]) & 63) < 32
5473 && (INTVAL (operands[2]) & 63) != 0"
5475 [(set (subreg:SI (match_dup 0) 0)
5476 (ashift:SI (subreg:SI (match_dup 1) 0)
5480 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
5483 (set (subreg:SI (match_dup 0) 0)
5484 (ior:SI (subreg:SI (match_dup 0) 0)
5487 (set (subreg:SI (match_dup 0) 4)
5488 (ashift:SI (subreg:SI (match_dup 1) 4)
5491 int amount = INTVAL (operands[2]);
5492 operands[2] = GEN_INT (amount & 31);
5493 operands[4] = GEN_INT ((-amount) & 31);
5497 (define_insn "ashldi3_internal4"
5498 [(set (match_operand:DI 0 "register_operand" "=d")
5499 (ashift:DI (match_operand:DI 1 "register_operand" "d")
5500 (match_operand:SI 2 "arith_operand" "dI")))]
5501 "TARGET_64BIT && !TARGET_MIPS16"
5503 if (GET_CODE (operands[2]) == CONST_INT)
5504 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5506 return "dsll\t%0,%1,%2";
5508 [(set_attr "type" "arith")
5509 (set_attr "mode" "DI")])
5512 [(set (match_operand:DI 0 "register_operand" "=d,d")
5513 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
5514 (match_operand:SI 2 "arith_operand" "d,I")))]
5515 "TARGET_64BIT && TARGET_MIPS16"
5517 if (which_alternative == 0)
5518 return "dsll\t%0,%2";
5520 if (GET_CODE (operands[2]) == CONST_INT)
5521 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5523 return "dsll\t%0,%1,%2";
5525 [(set_attr "type" "arith")
5526 (set_attr "mode" "DI")
5527 (set_attr_alternative "length"
5529 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
5534 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5537 [(set (match_operand:DI 0 "register_operand" "")
5538 (ashift:DI (match_operand:DI 1 "register_operand" "")
5539 (match_operand:SI 2 "const_int_operand" "")))]
5540 "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
5542 && GET_CODE (operands[2]) == CONST_INT
5543 && INTVAL (operands[2]) > 8
5544 && INTVAL (operands[2]) <= 16"
5545 [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
5546 (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
5547 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5549 (define_expand "ashrsi3"
5550 [(set (match_operand:SI 0 "register_operand" "=d")
5551 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
5552 (match_operand:SI 2 "arith_operand" "dI")))]
5555 /* On the mips16, a shift of more than 8 is a four byte instruction,
5556 so, for a shift between 8 and 16, it is just as fast to do two
5557 shifts of 8 or less. If there is a lot of shifting going on, we
5558 may win in CSE. Otherwise combine will put the shifts back
5562 && GET_CODE (operands[2]) == CONST_INT
5563 && INTVAL (operands[2]) > 8
5564 && INTVAL (operands[2]) <= 16)
5566 rtx temp = gen_reg_rtx (SImode);
5568 emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
5569 emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
5570 GEN_INT (INTVAL (operands[2]) - 8)));
5575 (define_insn "ashrsi3_internal1"
5576 [(set (match_operand:SI 0 "register_operand" "=d")
5577 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
5578 (match_operand:SI 2 "arith_operand" "dI")))]
5581 if (GET_CODE (operands[2]) == CONST_INT)
5582 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5584 return "sra\t%0,%1,%2";
5586 [(set_attr "type" "arith")
5587 (set_attr "mode" "SI")])
5589 (define_insn "ashrsi3_internal2"
5590 [(set (match_operand:SI 0 "register_operand" "=d,d")
5591 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
5592 (match_operand:SI 2 "arith_operand" "d,I")))]
5595 if (which_alternative == 0)
5596 return "sra\t%0,%2";
5598 if (GET_CODE (operands[2]) == CONST_INT)
5599 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5601 return "sra\t%0,%1,%2";
5603 [(set_attr "type" "arith")
5604 (set_attr "mode" "SI")
5605 (set_attr_alternative "length"
5607 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
5612 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5615 [(set (match_operand:SI 0 "register_operand" "")
5616 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
5617 (match_operand:SI 2 "const_int_operand" "")))]
5618 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5619 && GET_CODE (operands[2]) == CONST_INT
5620 && INTVAL (operands[2]) > 8
5621 && INTVAL (operands[2]) <= 16"
5622 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
5623 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
5624 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5626 (define_expand "ashrdi3"
5627 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5628 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5629 (match_operand:SI 2 "arith_operand" "")))
5630 (clobber (match_dup 3))])]
5631 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
5635 /* On the mips16, a shift of more than 8 is a four byte
5636 instruction, so, for a shift between 8 and 16, it is just as
5637 fast to do two shifts of 8 or less. If there is a lot of
5638 shifting going on, we may win in CSE. Otherwise combine will
5639 put the shifts back together again. */
5642 && GET_CODE (operands[2]) == CONST_INT
5643 && INTVAL (operands[2]) > 8
5644 && INTVAL (operands[2]) <= 16)
5646 rtx temp = gen_reg_rtx (DImode);
5648 emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
5649 emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
5650 GEN_INT (INTVAL (operands[2]) - 8)));
5654 emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
5659 operands[3] = gen_reg_rtx (SImode);
5663 (define_insn "ashrdi3_internal"
5664 [(set (match_operand:DI 0 "register_operand" "=&d")
5665 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5666 (match_operand:SI 2 "register_operand" "d")))
5667 (clobber (match_operand:SI 3 "register_operand" "=d"))]
5668 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
5685 [(set_attr "type" "darith")
5686 (set_attr "mode" "DI")
5687 (set_attr "length" "48")])
5690 (define_insn "ashrdi3_internal2"
5691 [(set (match_operand:DI 0 "register_operand" "=d")
5692 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5693 (match_operand:SI 2 "small_int" "IJK")))
5694 (clobber (match_operand:SI 3 "register_operand" "=d"))]
5695 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
5697 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5698 return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31";
5700 [(set_attr "type" "darith")
5701 (set_attr "mode" "DI")
5702 (set_attr "length" "8")])
5706 [(set (match_operand:DI 0 "register_operand" "")
5707 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5708 (match_operand:SI 2 "small_int" "")))
5709 (clobber (match_operand:SI 3 "register_operand" ""))]
5710 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
5711 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
5712 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
5713 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
5714 && (INTVAL (operands[2]) & 32) != 0"
5716 [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
5717 (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))]
5719 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
5723 [(set (match_operand:DI 0 "register_operand" "")
5724 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5725 (match_operand:SI 2 "small_int" "")))
5726 (clobber (match_operand:SI 3 "register_operand" ""))]
5727 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
5728 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
5729 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
5730 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
5731 && (INTVAL (operands[2]) & 32) != 0"
5733 [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
5734 (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
5736 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
5739 (define_insn "ashrdi3_internal3"
5740 [(set (match_operand:DI 0 "register_operand" "=d")
5741 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5742 (match_operand:SI 2 "small_int" "IJK")))
5743 (clobber (match_operand:SI 3 "register_operand" "=d"))]
5744 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5745 && (INTVAL (operands[2]) & 63) < 32
5746 && (INTVAL (operands[2]) & 63) != 0"
5748 int amount = INTVAL (operands[2]);
5750 operands[2] = GEN_INT (amount & 31);
5751 operands[4] = GEN_INT ((-amount) & 31);
5753 return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2";
5755 [(set_attr "type" "darith")
5756 (set_attr "mode" "DI")
5757 (set_attr "length" "16")])
5761 [(set (match_operand:DI 0 "register_operand" "")
5762 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5763 (match_operand:SI 2 "small_int" "")))
5764 (clobber (match_operand:SI 3 "register_operand" ""))]
5765 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
5766 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5767 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
5768 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
5769 && (INTVAL (operands[2]) & 63) < 32
5770 && (INTVAL (operands[2]) & 63) != 0"
5772 [(set (subreg:SI (match_dup 0) 0)
5773 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
5777 (ashift:SI (subreg:SI (match_dup 1) 4)
5780 (set (subreg:SI (match_dup 0) 0)
5781 (ior:SI (subreg:SI (match_dup 0) 0)
5784 (set (subreg:SI (match_dup 0) 4)
5785 (ashiftrt:SI (subreg:SI (match_dup 1) 4)
5788 int amount = INTVAL (operands[2]);
5789 operands[2] = GEN_INT (amount & 31);
5790 operands[4] = GEN_INT ((-amount) & 31);
5795 [(set (match_operand:DI 0 "register_operand" "")
5796 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5797 (match_operand:SI 2 "small_int" "")))
5798 (clobber (match_operand:SI 3 "register_operand" ""))]
5799 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
5800 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
5801 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
5802 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
5803 && (INTVAL (operands[2]) & 63) < 32
5804 && (INTVAL (operands[2]) & 63) != 0"
5806 [(set (subreg:SI (match_dup 0) 4)
5807 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
5811 (ashift:SI (subreg:SI (match_dup 1) 0)
5814 (set (subreg:SI (match_dup 0) 4)
5815 (ior:SI (subreg:SI (match_dup 0) 4)
5818 (set (subreg:SI (match_dup 0) 0)
5819 (ashiftrt:SI (subreg:SI (match_dup 1) 0)
5822 int amount = INTVAL (operands[2]);
5823 operands[2] = GEN_INT (amount & 31);
5824 operands[4] = GEN_INT ((-amount) & 31);
5828 (define_insn "ashrdi3_internal4"
5829 [(set (match_operand:DI 0 "register_operand" "=d")
5830 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5831 (match_operand:SI 2 "arith_operand" "dI")))]
5832 "TARGET_64BIT && !TARGET_MIPS16"
5834 if (GET_CODE (operands[2]) == CONST_INT)
5835 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5837 return "dsra\t%0,%1,%2";
5839 [(set_attr "type" "arith")
5840 (set_attr "mode" "DI")])
5843 [(set (match_operand:DI 0 "register_operand" "=d,d")
5844 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5845 (match_operand:SI 2 "arith_operand" "d,I")))]
5846 "TARGET_64BIT && TARGET_MIPS16"
5848 if (GET_CODE (operands[2]) == CONST_INT)
5849 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5851 return "dsra\t%0,%2";
5853 [(set_attr "type" "arith")
5854 (set_attr "mode" "DI")
5855 (set_attr_alternative "length"
5857 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
5861 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5864 [(set (match_operand:DI 0 "register_operand" "")
5865 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5866 (match_operand:SI 2 "const_int_operand" "")))]
5867 "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
5869 && GET_CODE (operands[2]) == CONST_INT
5870 && INTVAL (operands[2]) > 8
5871 && INTVAL (operands[2]) <= 16"
5872 [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
5873 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
5874 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5876 (define_expand "lshrsi3"
5877 [(set (match_operand:SI 0 "register_operand" "=d")
5878 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
5879 (match_operand:SI 2 "arith_operand" "dI")))]
5882 /* On the mips16, a shift of more than 8 is a four byte instruction,
5883 so, for a shift between 8 and 16, it is just as fast to do two
5884 shifts of 8 or less. If there is a lot of shifting going on, we
5885 may win in CSE. Otherwise combine will put the shifts back
5889 && GET_CODE (operands[2]) == CONST_INT
5890 && INTVAL (operands[2]) > 8
5891 && INTVAL (operands[2]) <= 16)
5893 rtx temp = gen_reg_rtx (SImode);
5895 emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
5896 emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
5897 GEN_INT (INTVAL (operands[2]) - 8)));
5902 (define_insn "lshrsi3_internal1"
5903 [(set (match_operand:SI 0 "register_operand" "=d")
5904 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
5905 (match_operand:SI 2 "arith_operand" "dI")))]
5908 if (GET_CODE (operands[2]) == CONST_INT)
5909 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5911 return "srl\t%0,%1,%2";
5913 [(set_attr "type" "arith")
5914 (set_attr "mode" "SI")])
5916 (define_insn "lshrsi3_internal2"
5917 [(set (match_operand:SI 0 "register_operand" "=d,d")
5918 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
5919 (match_operand:SI 2 "arith_operand" "d,I")))]
5922 if (which_alternative == 0)
5923 return "srl\t%0,%2";
5925 if (GET_CODE (operands[2]) == CONST_INT)
5926 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5928 return "srl\t%0,%1,%2";
5930 [(set_attr "type" "arith")
5931 (set_attr "mode" "SI")
5932 (set_attr_alternative "length"
5934 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
5939 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5942 [(set (match_operand:SI 0 "register_operand" "")
5943 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
5944 (match_operand:SI 2 "const_int_operand" "")))]
5945 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5946 && GET_CODE (operands[2]) == CONST_INT
5947 && INTVAL (operands[2]) > 8
5948 && INTVAL (operands[2]) <= 16"
5949 [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
5950 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5951 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5953 ;; If we load a byte on the mips16 as a bitfield, the resulting
5954 ;; sequence of instructions is too complicated for combine, because it
5955 ;; involves four instructions: a load, a shift, a constant load into a
5956 ;; register, and an and (the key problem here is that the mips16 does
5957 ;; not have and immediate). We recognize a shift of a load in order
5958 ;; to make it simple enough for combine to understand.
5960 ;; The length here is the worst case: the length of the split version
5961 ;; will be more accurate.
5962 (define_insn_and_split ""
5963 [(set (match_operand:SI 0 "register_operand" "=d")
5964 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5965 (match_operand:SI 2 "immediate_operand" "I")))]
5969 [(set (match_dup 0) (match_dup 1))
5970 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5972 [(set_attr "type" "load")
5973 (set_attr "mode" "SI")
5974 (set_attr "length" "16")])
5976 (define_expand "lshrdi3"
5977 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5978 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5979 (match_operand:SI 2 "arith_operand" "")))
5980 (clobber (match_dup 3))])]
5981 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
5985 /* On the mips16, a shift of more than 8 is a four byte
5986 instruction, so, for a shift between 8 and 16, it is just as
5987 fast to do two shifts of 8 or less. If there is a lot of
5988 shifting going on, we may win in CSE. Otherwise combine will
5989 put the shifts back together again. */
5992 && GET_CODE (operands[2]) == CONST_INT
5993 && INTVAL (operands[2]) > 8
5994 && INTVAL (operands[2]) <= 16)
5996 rtx temp = gen_reg_rtx (DImode);
5998 emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
5999 emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
6000 GEN_INT (INTVAL (operands[2]) - 8)));
6004 emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
6009 operands[3] = gen_reg_rtx (SImode);
6013 (define_insn "lshrdi3_internal"
6014 [(set (match_operand:DI 0 "register_operand" "=&d")
6015 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6016 (match_operand:SI 2 "register_operand" "d")))
6017 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6018 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
6035 [(set_attr "type" "darith")
6036 (set_attr "mode" "DI")
6037 (set_attr "length" "48")])
6040 (define_insn "lshrdi3_internal2"
6041 [(set (match_operand:DI 0 "register_operand" "=d")
6042 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6043 (match_operand:SI 2 "small_int" "IJK")))
6044 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6045 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6046 && (INTVAL (operands[2]) & 32) != 0"
6048 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6049 return "srl\t%L0,%M1,%2\;move\t%M0,%.";
6051 [(set_attr "type" "darith")
6052 (set_attr "mode" "DI")
6053 (set_attr "length" "8")])
6057 [(set (match_operand:DI 0 "register_operand" "")
6058 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6059 (match_operand:SI 2 "small_int" "")))
6060 (clobber (match_operand:SI 3 "register_operand" ""))]
6061 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
6062 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6063 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6064 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6065 && (INTVAL (operands[2]) & 32) != 0"
6067 [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
6068 (set (subreg:SI (match_dup 0) 4) (const_int 0))]
6070 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
6074 [(set (match_operand:DI 0 "register_operand" "")
6075 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6076 (match_operand:SI 2 "small_int" "")))
6077 (clobber (match_operand:SI 3 "register_operand" ""))]
6078 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
6079 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6080 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6081 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6082 && (INTVAL (operands[2]) & 32) != 0"
6084 [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
6085 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
6087 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
6090 (define_insn "lshrdi3_internal3"
6091 [(set (match_operand:DI 0 "register_operand" "=d")
6092 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6093 (match_operand:SI 2 "small_int" "IJK")))
6094 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6095 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6096 && (INTVAL (operands[2]) & 63) < 32
6097 && (INTVAL (operands[2]) & 63) != 0"
6099 int amount = INTVAL (operands[2]);
6101 operands[2] = GEN_INT (amount & 31);
6102 operands[4] = GEN_INT ((-amount) & 31);
6104 return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2";
6106 [(set_attr "type" "darith")
6107 (set_attr "mode" "DI")
6108 (set_attr "length" "16")])
6112 [(set (match_operand:DI 0 "register_operand" "")
6113 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6114 (match_operand:SI 2 "small_int" "")))
6115 (clobber (match_operand:SI 3 "register_operand" ""))]
6116 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
6117 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6118 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6119 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6120 && (INTVAL (operands[2]) & 63) < 32
6121 && (INTVAL (operands[2]) & 63) != 0"
6123 [(set (subreg:SI (match_dup 0) 0)
6124 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
6128 (ashift:SI (subreg:SI (match_dup 1) 4)
6131 (set (subreg:SI (match_dup 0) 0)
6132 (ior:SI (subreg:SI (match_dup 0) 0)
6135 (set (subreg:SI (match_dup 0) 4)
6136 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
6139 int amount = INTVAL (operands[2]);
6140 operands[2] = GEN_INT (amount & 31);
6141 operands[4] = GEN_INT ((-amount) & 31);
6146 [(set (match_operand:DI 0 "register_operand" "")
6147 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6148 (match_operand:SI 2 "small_int" "")))
6149 (clobber (match_operand:SI 3 "register_operand" ""))]
6150 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
6151 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6152 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6153 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6154 && (INTVAL (operands[2]) & 63) < 32
6155 && (INTVAL (operands[2]) & 63) != 0"
6157 [(set (subreg:SI (match_dup 0) 4)
6158 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
6162 (ashift:SI (subreg:SI (match_dup 1) 0)
6165 (set (subreg:SI (match_dup 0) 4)
6166 (ior:SI (subreg:SI (match_dup 0) 4)
6169 (set (subreg:SI (match_dup 0) 0)
6170 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
6173 int amount = INTVAL (operands[2]);
6174 operands[2] = GEN_INT (amount & 31);
6175 operands[4] = GEN_INT ((-amount) & 31);
6179 (define_insn "lshrdi3_internal4"
6180 [(set (match_operand:DI 0 "register_operand" "=d")
6181 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6182 (match_operand:SI 2 "arith_operand" "dI")))]
6183 "TARGET_64BIT && !TARGET_MIPS16"
6185 if (GET_CODE (operands[2]) == CONST_INT)
6186 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6188 return "dsrl\t%0,%1,%2";
6190 [(set_attr "type" "arith")
6191 (set_attr "mode" "DI")])
6194 [(set (match_operand:DI 0 "register_operand" "=d,d")
6195 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
6196 (match_operand:SI 2 "arith_operand" "d,I")))]
6197 "TARGET_64BIT && TARGET_MIPS16"
6199 if (GET_CODE (operands[2]) == CONST_INT)
6200 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6202 return "dsrl\t%0,%2";
6204 [(set_attr "type" "arith")
6205 (set_attr "mode" "DI")
6206 (set_attr_alternative "length"
6208 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
6212 (define_insn "rotrsi3"
6213 [(set (match_operand:SI 0 "register_operand" "=d")
6214 (rotatert:SI (match_operand:SI 1 "register_operand" "d")
6215 (match_operand:SI 2 "arith_operand" "dn")))]
6218 if (TARGET_SR71K && GET_CODE (operands[2]) != CONST_INT)
6219 return "rorv\t%0,%1,%2";
6221 if ((GET_CODE (operands[2]) == CONST_INT)
6222 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 32))
6225 return "ror\t%0,%1,%2";
6227 [(set_attr "type" "arith")
6228 (set_attr "mode" "SI")])
6230 (define_insn "rotrdi3"
6231 [(set (match_operand:DI 0 "register_operand" "=d")
6232 (rotatert:DI (match_operand:DI 1 "register_operand" "d")
6233 (match_operand:DI 2 "arith_operand" "dn")))]
6238 if (GET_CODE (operands[2]) != CONST_INT)
6239 return "drorv\t%0,%1,%2";
6241 if (INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) <= 63)
6242 return "dror32\t%0,%1,%2";
6245 if ((GET_CODE (operands[2]) == CONST_INT)
6246 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 64))
6249 return "dror\t%0,%1,%2";
6251 [(set_attr "type" "arith")
6252 (set_attr "mode" "DI")])
6255 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
6258 [(set (match_operand:DI 0 "register_operand" "")
6259 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6260 (match_operand:SI 2 "const_int_operand" "")))]
6261 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
6262 && GET_CODE (operands[2]) == CONST_INT
6263 && INTVAL (operands[2]) > 8
6264 && INTVAL (operands[2]) <= 16"
6265 [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
6266 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
6267 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
6270 ;; ....................
6274 ;; ....................
6276 ;; Flow here is rather complex:
6278 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
6279 ;; arguments into the branch_cmp array, and the type into
6280 ;; branch_type. No RTL is generated.
6282 ;; 2) The appropriate branch define_expand is called, which then
6283 ;; creates the appropriate RTL for the comparison and branch.
6284 ;; Different CC modes are used, based on what type of branch is
6285 ;; done, so that we can constrain things appropriately. There
6286 ;; are assumptions in the rest of GCC that break if we fold the
6287 ;; operands into the branches for integer operations, and use cc0
6288 ;; for floating point, so we use the fp status register instead.
6289 ;; If needed, an appropriate temporary is created to hold the
6290 ;; of the integer compare.
6292 (define_expand "cmpsi"
6294 (compare:CC (match_operand:SI 0 "register_operand" "")
6295 (match_operand:SI 1 "arith_operand" "")))]
6298 branch_cmp[0] = operands[0];
6299 branch_cmp[1] = operands[1];
6300 branch_type = CMP_SI;
6304 (define_expand "tstsi"
6306 (match_operand:SI 0 "register_operand" ""))]
6309 branch_cmp[0] = operands[0];
6310 branch_cmp[1] = const0_rtx;
6311 branch_type = CMP_SI;
6315 (define_expand "cmpdi"
6317 (compare:CC (match_operand:DI 0 "register_operand" "")
6318 (match_operand:DI 1 "arith_operand" "")))]
6321 branch_cmp[0] = operands[0];
6322 branch_cmp[1] = operands[1];
6323 branch_type = CMP_DI;
6327 (define_expand "tstdi"
6329 (match_operand:DI 0 "register_operand" ""))]
6332 branch_cmp[0] = operands[0];
6333 branch_cmp[1] = const0_rtx;
6334 branch_type = CMP_DI;
6338 (define_expand "cmpdf"
6340 (compare:CC (match_operand:DF 0 "register_operand" "")
6341 (match_operand:DF 1 "register_operand" "")))]
6342 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6344 branch_cmp[0] = operands[0];
6345 branch_cmp[1] = operands[1];
6346 branch_type = CMP_DF;
6350 (define_expand "cmpsf"
6352 (compare:CC (match_operand:SF 0 "register_operand" "")
6353 (match_operand:SF 1 "register_operand" "")))]
6356 branch_cmp[0] = operands[0];
6357 branch_cmp[1] = operands[1];
6358 branch_type = CMP_SF;
6363 ;; ....................
6365 ;; CONDITIONAL BRANCHES
6367 ;; ....................
6369 ;; Conditional branches on floating-point equality tests.
6371 (define_insn "branch_fp"
6374 (match_operator:CC 0 "cmp_op"
6375 [(match_operand:CC 2 "register_operand" "z")
6377 (label_ref (match_operand 1 "" ""))
6381 return mips_output_conditional_branch (insn,
6383 /*two_operands_p=*/0,
6386 get_attr_length (insn));
6388 [(set_attr "type" "branch")
6389 (set_attr "mode" "none")])
6391 (define_insn "branch_fp_inverted"
6394 (match_operator:CC 0 "cmp_op"
6395 [(match_operand:CC 2 "register_operand" "z")
6398 (label_ref (match_operand 1 "" ""))))]
6401 return mips_output_conditional_branch (insn,
6403 /*two_operands_p=*/0,
6406 get_attr_length (insn));
6408 [(set_attr "type" "branch")
6409 (set_attr "mode" "none")])
6411 ;; Conditional branches on comparisons with zero.
6413 (define_insn "branch_zero"
6416 (match_operator:SI 0 "cmp_op"
6417 [(match_operand:SI 2 "register_operand" "d")
6419 (label_ref (match_operand 1 "" ""))
6423 return mips_output_conditional_branch (insn,
6425 /*two_operands_p=*/0,
6428 get_attr_length (insn));
6430 [(set_attr "type" "branch")
6431 (set_attr "mode" "none")])
6433 (define_insn "branch_zero_inverted"
6436 (match_operator:SI 0 "cmp_op"
6437 [(match_operand:SI 2 "register_operand" "d")
6440 (label_ref (match_operand 1 "" ""))))]
6443 return mips_output_conditional_branch (insn,
6445 /*two_operands_p=*/0,
6448 get_attr_length (insn));
6450 [(set_attr "type" "branch")
6451 (set_attr "mode" "none")])
6453 (define_insn "branch_zero_di"
6456 (match_operator:DI 0 "cmp_op"
6457 [(match_operand:DI 2 "register_operand" "d")
6459 (label_ref (match_operand 1 "" ""))
6463 return mips_output_conditional_branch (insn,
6465 /*two_operands_p=*/0,
6468 get_attr_length (insn));
6470 [(set_attr "type" "branch")
6471 (set_attr "mode" "none")])
6473 (define_insn "branch_zero_di_inverted"
6476 (match_operator:DI 0 "cmp_op"
6477 [(match_operand:DI 2 "register_operand" "d")
6480 (label_ref (match_operand 1 "" ""))))]
6483 return mips_output_conditional_branch (insn,
6485 /*two_operands_p=*/0,
6488 get_attr_length (insn));
6490 [(set_attr "type" "branch")
6491 (set_attr "mode" "none")])
6493 ;; Conditional branch on equality comparison.
6495 (define_insn "branch_equality"
6498 (match_operator:SI 0 "equality_op"
6499 [(match_operand:SI 2 "register_operand" "d")
6500 (match_operand:SI 3 "register_operand" "d")])
6501 (label_ref (match_operand 1 "" ""))
6505 return mips_output_conditional_branch (insn,
6507 /*two_operands_p=*/1,
6510 get_attr_length (insn));
6512 [(set_attr "type" "branch")
6513 (set_attr "mode" "none")])
6515 (define_insn "branch_equality_di"
6518 (match_operator:DI 0 "equality_op"
6519 [(match_operand:DI 2 "register_operand" "d")
6520 (match_operand:DI 3 "register_operand" "d")])
6521 (label_ref (match_operand 1 "" ""))
6525 return mips_output_conditional_branch (insn,
6527 /*two_operands_p=*/1,
6530 get_attr_length (insn));
6532 [(set_attr "type" "branch")
6533 (set_attr "mode" "none")])
6535 (define_insn "branch_equality_inverted"
6538 (match_operator:SI 0 "equality_op"
6539 [(match_operand:SI 2 "register_operand" "d")
6540 (match_operand:SI 3 "register_operand" "d")])
6542 (label_ref (match_operand 1 "" ""))))]
6545 return mips_output_conditional_branch (insn,
6547 /*two_operands_p=*/1,
6550 get_attr_length (insn));
6552 [(set_attr "type" "branch")
6553 (set_attr "mode" "none")])
6555 (define_insn "branch_equality_di_inverted"
6558 (match_operator:DI 0 "equality_op"
6559 [(match_operand:DI 2 "register_operand" "d")
6560 (match_operand:DI 3 "register_operand" "d")])
6562 (label_ref (match_operand 1 "" ""))))]
6565 return mips_output_conditional_branch (insn,
6567 /*two_operands_p=*/1,
6570 get_attr_length (insn));
6572 [(set_attr "type" "branch")
6573 (set_attr "mode" "none")])
6579 (if_then_else (match_operator:SI 0 "equality_op"
6580 [(match_operand:SI 1 "register_operand" "d,t")
6582 (match_operand 2 "pc_or_label_operand" "")
6583 (match_operand 3 "pc_or_label_operand" "")))]
6586 if (operands[2] != pc_rtx)
6588 if (which_alternative == 0)
6589 return "b%C0z\t%1,%2";
6591 return "bt%C0z\t%2";
6595 if (which_alternative == 0)
6596 return "b%N0z\t%1,%3";
6598 return "bt%N0z\t%3";
6601 [(set_attr "type" "branch")
6602 (set_attr "mode" "none")
6603 (set_attr "length" "8")])
6607 (if_then_else (match_operator:DI 0 "equality_op"
6608 [(match_operand:DI 1 "register_operand" "d,t")
6610 (match_operand 2 "pc_or_label_operand" "")
6611 (match_operand 3 "pc_or_label_operand" "")))]
6614 if (operands[2] != pc_rtx)
6616 if (which_alternative == 0)
6617 return "b%C0z\t%1,%2";
6619 return "bt%C0z\t%2";
6623 if (which_alternative == 0)
6624 return "b%N0z\t%1,%3";
6626 return "bt%N0z\t%3";
6629 [(set_attr "type" "branch")
6630 (set_attr "mode" "none")
6631 (set_attr "length" "8")])
6633 (define_expand "bunordered"
6635 (if_then_else (unordered:CC (cc0)
6637 (label_ref (match_operand 0 "" ""))
6641 gen_conditional_branch (operands, UNORDERED);
6645 (define_expand "bordered"
6647 (if_then_else (ordered:CC (cc0)
6649 (label_ref (match_operand 0 "" ""))
6653 gen_conditional_branch (operands, ORDERED);
6657 (define_expand "bunlt"
6659 (if_then_else (unlt:CC (cc0)
6661 (label_ref (match_operand 0 "" ""))
6665 gen_conditional_branch (operands, UNLT);
6669 (define_expand "bunge"
6671 (if_then_else (unge:CC (cc0)
6673 (label_ref (match_operand 0 "" ""))
6677 gen_conditional_branch (operands, UNGE);
6681 (define_expand "buneq"
6683 (if_then_else (uneq:CC (cc0)
6685 (label_ref (match_operand 0 "" ""))
6689 gen_conditional_branch (operands, UNEQ);
6693 (define_expand "bltgt"
6695 (if_then_else (ltgt:CC (cc0)
6697 (label_ref (match_operand 0 "" ""))
6701 gen_conditional_branch (operands, LTGT);
6705 (define_expand "bunle"
6707 (if_then_else (unle:CC (cc0)
6709 (label_ref (match_operand 0 "" ""))
6713 gen_conditional_branch (operands, UNLE);
6717 (define_expand "bungt"
6719 (if_then_else (ungt:CC (cc0)
6721 (label_ref (match_operand 0 "" ""))
6725 gen_conditional_branch (operands, UNGT);
6729 (define_expand "beq"
6731 (if_then_else (eq:CC (cc0)
6733 (label_ref (match_operand 0 "" ""))
6737 gen_conditional_branch (operands, EQ);
6741 (define_expand "bne"
6743 (if_then_else (ne:CC (cc0)
6745 (label_ref (match_operand 0 "" ""))
6749 gen_conditional_branch (operands, NE);
6753 (define_expand "bgt"
6755 (if_then_else (gt:CC (cc0)
6757 (label_ref (match_operand 0 "" ""))
6761 gen_conditional_branch (operands, GT);
6765 (define_expand "bge"
6767 (if_then_else (ge:CC (cc0)
6769 (label_ref (match_operand 0 "" ""))
6773 gen_conditional_branch (operands, GE);
6777 (define_expand "blt"
6779 (if_then_else (lt:CC (cc0)
6781 (label_ref (match_operand 0 "" ""))
6785 gen_conditional_branch (operands, LT);
6789 (define_expand "ble"
6791 (if_then_else (le:CC (cc0)
6793 (label_ref (match_operand 0 "" ""))
6797 gen_conditional_branch (operands, LE);
6801 (define_expand "bgtu"
6803 (if_then_else (gtu:CC (cc0)
6805 (label_ref (match_operand 0 "" ""))
6809 gen_conditional_branch (operands, GTU);
6813 (define_expand "bgeu"
6815 (if_then_else (geu:CC (cc0)
6817 (label_ref (match_operand 0 "" ""))
6821 gen_conditional_branch (operands, GEU);
6825 (define_expand "bltu"
6827 (if_then_else (ltu:CC (cc0)
6829 (label_ref (match_operand 0 "" ""))
6833 gen_conditional_branch (operands, LTU);
6837 (define_expand "bleu"
6839 (if_then_else (leu:CC (cc0)
6841 (label_ref (match_operand 0 "" ""))
6845 gen_conditional_branch (operands, LEU);
6850 ;; ....................
6852 ;; SETTING A REGISTER FROM A COMPARISON
6854 ;; ....................
6856 (define_expand "seq"
6857 [(set (match_operand:SI 0 "register_operand" "=d")
6858 (eq:SI (match_dup 1)
6862 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
6865 /* set up operands from compare. */
6866 operands[1] = branch_cmp[0];
6867 operands[2] = branch_cmp[1];
6869 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
6871 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
6875 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6876 operands[2] = force_reg (SImode, operands[2]);
6878 /* fall through and generate default code */
6882 (define_insn "seq_si_zero"
6883 [(set (match_operand:SI 0 "register_operand" "=d")
6884 (eq:SI (match_operand:SI 1 "register_operand" "d")
6888 [(set_attr "type" "arith")
6889 (set_attr "mode" "SI")])
6892 [(set (match_operand:SI 0 "register_operand" "=t")
6893 (eq:SI (match_operand:SI 1 "register_operand" "d")
6897 [(set_attr "type" "arith")
6898 (set_attr "mode" "SI")])
6900 (define_insn "seq_di_zero"
6901 [(set (match_operand:DI 0 "register_operand" "=d")
6902 (eq:DI (match_operand:DI 1 "register_operand" "d")
6904 "TARGET_64BIT && !TARGET_MIPS16"
6906 [(set_attr "type" "arith")
6907 (set_attr "mode" "DI")])
6910 [(set (match_operand:DI 0 "register_operand" "=t")
6911 (eq:DI (match_operand:DI 1 "register_operand" "d")
6913 "TARGET_64BIT && TARGET_MIPS16"
6915 [(set_attr "type" "arith")
6916 (set_attr "mode" "DI")])
6918 (define_insn "seq_si"
6919 [(set (match_operand:SI 0 "register_operand" "=d,d")
6920 (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
6921 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
6922 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
6924 xor\t%0,%1,%2\;sltu\t%0,%0,1
6925 xori\t%0,%1,%2\;sltu\t%0,%0,1"
6926 [(set_attr "type" "arith")
6927 (set_attr "mode" "SI")
6928 (set_attr "length" "8")])
6931 [(set (match_operand:SI 0 "register_operand" "")
6932 (eq:SI (match_operand:SI 1 "register_operand" "")
6933 (match_operand:SI 2 "uns_arith_operand" "")))]
6934 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
6935 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
6937 (xor:SI (match_dup 1)
6940 (ltu:SI (match_dup 0)
6944 (define_insn "seq_di"
6945 [(set (match_operand:DI 0 "register_operand" "=d,d")
6946 (eq:DI (match_operand:DI 1 "register_operand" "%d,d")
6947 (match_operand:DI 2 "uns_arith_operand" "d,K")))]
6948 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
6950 xor\t%0,%1,%2\;sltu\t%0,%0,1
6951 xori\t%0,%1,%2\;sltu\t%0,%0,1"
6952 [(set_attr "type" "arith")
6953 (set_attr "mode" "DI")
6954 (set_attr "length" "8")])
6957 [(set (match_operand:DI 0 "register_operand" "")
6958 (eq:DI (match_operand:DI 1 "register_operand" "")
6959 (match_operand:DI 2 "uns_arith_operand" "")))]
6960 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
6962 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
6964 (xor:DI (match_dup 1)
6967 (ltu:DI (match_dup 0)
6971 ;; On the mips16 the default code is better than using sltu.
6973 (define_expand "sne"
6974 [(set (match_operand:SI 0 "register_operand" "=d")
6975 (ne:SI (match_dup 1)
6979 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
6982 /* set up operands from compare. */
6983 operands[1] = branch_cmp[0];
6984 operands[2] = branch_cmp[1];
6986 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
6988 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
6992 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
6993 operands[2] = force_reg (SImode, operands[2]);
6995 /* fall through and generate default code */
6998 (define_insn "sne_si_zero"
6999 [(set (match_operand:SI 0 "register_operand" "=d")
7000 (ne:SI (match_operand:SI 1 "register_operand" "d")
7004 [(set_attr "type" "arith")
7005 (set_attr "mode" "SI")])
7007 (define_insn "sne_di_zero"
7008 [(set (match_operand:DI 0 "register_operand" "=d")
7009 (ne:DI (match_operand:DI 1 "register_operand" "d")
7011 "TARGET_64BIT && !TARGET_MIPS16"
7013 [(set_attr "type" "arith")
7014 (set_attr "mode" "DI")])
7016 (define_insn "sne_si"
7017 [(set (match_operand:SI 0 "register_operand" "=d,d")
7018 (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
7019 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
7020 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7022 xor\t%0,%1,%2\;sltu\t%0,%.,%0
7023 xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
7024 [(set_attr "type" "arith")
7025 (set_attr "mode" "SI")
7026 (set_attr "length" "8")])
7029 [(set (match_operand:SI 0 "register_operand" "")
7030 (ne:SI (match_operand:SI 1 "register_operand" "")
7031 (match_operand:SI 2 "uns_arith_operand" "")))]
7032 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
7033 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
7035 (xor:SI (match_dup 1)
7038 (gtu:SI (match_dup 0)
7042 (define_insn "sne_di"
7043 [(set (match_operand:DI 0 "register_operand" "=d,d")
7044 (ne:DI (match_operand:DI 1 "register_operand" "%d,d")
7045 (match_operand:DI 2 "uns_arith_operand" "d,K")))]
7046 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7048 xor\t%0,%1,%2\;sltu\t%0,%.,%0
7049 xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
7050 [(set_attr "type" "arith")
7051 (set_attr "mode" "DI")
7052 (set_attr "length" "8")])
7055 [(set (match_operand:DI 0 "register_operand" "")
7056 (ne:DI (match_operand:DI 1 "register_operand" "")
7057 (match_operand:DI 2 "uns_arith_operand" "")))]
7058 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
7060 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
7062 (xor:DI (match_dup 1)
7065 (gtu:DI (match_dup 0)
7069 (define_expand "sgt"
7070 [(set (match_operand:SI 0 "register_operand" "=d")
7071 (gt:SI (match_dup 1)
7075 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
7078 /* set up operands from compare. */
7079 operands[1] = branch_cmp[0];
7080 operands[2] = branch_cmp[1];
7082 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
7084 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
7088 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
7089 operands[2] = force_reg (SImode, operands[2]);
7091 /* fall through and generate default code */
7094 (define_insn "sgt_si"
7095 [(set (match_operand:SI 0 "register_operand" "=d")
7096 (gt:SI (match_operand:SI 1 "register_operand" "d")
7097 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
7100 [(set_attr "type" "arith")
7101 (set_attr "mode" "SI")])
7104 [(set (match_operand:SI 0 "register_operand" "=t")
7105 (gt:SI (match_operand:SI 1 "register_operand" "d")
7106 (match_operand:SI 2 "register_operand" "d")))]
7109 [(set_attr "type" "arith")
7110 (set_attr "mode" "SI")])
7112 (define_insn "sgt_di"
7113 [(set (match_operand:DI 0 "register_operand" "=d")
7114 (gt:DI (match_operand:DI 1 "register_operand" "d")
7115 (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
7116 "TARGET_64BIT && !TARGET_MIPS16"
7118 [(set_attr "type" "arith")
7119 (set_attr "mode" "DI")])
7122 [(set (match_operand:DI 0 "register_operand" "=d")
7123 (gt:DI (match_operand:DI 1 "register_operand" "d")
7124 (match_operand:DI 2 "register_operand" "d")))]
7125 "TARGET_64BIT && TARGET_MIPS16"
7127 [(set_attr "type" "arith")
7128 (set_attr "mode" "DI")])
7130 (define_expand "sge"
7131 [(set (match_operand:SI 0 "register_operand" "=d")
7132 (ge:SI (match_dup 1)
7136 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
7139 /* set up operands from compare. */
7140 operands[1] = branch_cmp[0];
7141 operands[2] = branch_cmp[1];
7143 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
7145 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
7149 /* fall through and generate default code */
7152 (define_insn "sge_si"
7153 [(set (match_operand:SI 0 "register_operand" "=d")
7154 (ge:SI (match_operand:SI 1 "register_operand" "d")
7155 (match_operand:SI 2 "arith_operand" "dI")))]
7156 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7157 "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
7158 [(set_attr "type" "arith")
7159 (set_attr "mode" "SI")
7160 (set_attr "length" "8")])
7163 [(set (match_operand:SI 0 "register_operand" "")
7164 (ge:SI (match_operand:SI 1 "register_operand" "")
7165 (match_operand:SI 2 "arith_operand" "")))]
7166 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
7168 (lt:SI (match_dup 1)
7171 (xor:SI (match_dup 0)
7175 (define_insn "sge_di"
7176 [(set (match_operand:DI 0 "register_operand" "=d")
7177 (ge:DI (match_operand:DI 1 "register_operand" "d")
7178 (match_operand:DI 2 "arith_operand" "dI")))]
7179 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7180 "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
7181 [(set_attr "type" "arith")
7182 (set_attr "mode" "DI")
7183 (set_attr "length" "8")])
7186 [(set (match_operand:DI 0 "register_operand" "")
7187 (ge:DI (match_operand:DI 1 "register_operand" "")
7188 (match_operand:DI 2 "arith_operand" "")))]
7189 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
7192 (lt:DI (match_dup 1)
7195 (xor:DI (match_dup 0)
7199 (define_expand "slt"
7200 [(set (match_operand:SI 0 "register_operand" "=d")
7201 (lt:SI (match_dup 1)
7205 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
7208 /* set up operands from compare. */
7209 operands[1] = branch_cmp[0];
7210 operands[2] = branch_cmp[1];
7212 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
7214 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
7218 /* fall through and generate default code */
7221 (define_insn "slt_si"
7222 [(set (match_operand:SI 0 "register_operand" "=d")
7223 (lt:SI (match_operand:SI 1 "register_operand" "d")
7224 (match_operand:SI 2 "arith_operand" "dI")))]
7227 [(set_attr "type" "arith")
7228 (set_attr "mode" "SI")])
7231 [(set (match_operand:SI 0 "register_operand" "=t,t")
7232 (lt:SI (match_operand:SI 1 "register_operand" "d,d")
7233 (match_operand:SI 2 "arith_operand" "d,I")))]
7236 [(set_attr "type" "arith")
7237 (set_attr "mode" "SI")
7238 (set_attr_alternative "length"
7240 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
7244 (define_insn "slt_di"
7245 [(set (match_operand:DI 0 "register_operand" "=d")
7246 (lt:DI (match_operand:DI 1 "register_operand" "d")
7247 (match_operand:DI 2 "arith_operand" "dI")))]
7248 "TARGET_64BIT && !TARGET_MIPS16"
7250 [(set_attr "type" "arith")
7251 (set_attr "mode" "DI")])
7254 [(set (match_operand:DI 0 "register_operand" "=t,t")
7255 (lt:DI (match_operand:DI 1 "register_operand" "d,d")
7256 (match_operand:DI 2 "arith_operand" "d,I")))]
7257 "TARGET_64BIT && TARGET_MIPS16"
7259 [(set_attr "type" "arith")
7260 (set_attr "mode" "DI")
7261 (set_attr_alternative "length"
7263 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
7267 (define_expand "sle"
7268 [(set (match_operand:SI 0 "register_operand" "=d")
7269 (le:SI (match_dup 1)
7273 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
7276 /* set up operands from compare. */
7277 operands[1] = branch_cmp[0];
7278 operands[2] = branch_cmp[1];
7280 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
7282 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
7286 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
7287 operands[2] = force_reg (SImode, operands[2]);
7289 /* fall through and generate default code */
7292 (define_insn "sle_si_const"
7293 [(set (match_operand:SI 0 "register_operand" "=d")
7294 (le:SI (match_operand:SI 1 "register_operand" "d")
7295 (match_operand:SI 2 "small_int" "I")))]
7296 "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
7298 operands[2] = GEN_INT (INTVAL (operands[2])+1);
7299 return "slt\t%0,%1,%2";
7301 [(set_attr "type" "arith")
7302 (set_attr "mode" "SI")])
7305 [(set (match_operand:SI 0 "register_operand" "=t")
7306 (le:SI (match_operand:SI 1 "register_operand" "d")
7307 (match_operand:SI 2 "small_int" "I")))]
7308 "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
7310 operands[2] = GEN_INT (INTVAL (operands[2])+1);
7311 return "slt\t%1,%2";
7313 [(set_attr "type" "arith")
7314 (set_attr "mode" "SI")
7315 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
7319 (define_insn "sle_di_const"
7320 [(set (match_operand:DI 0 "register_operand" "=d")
7321 (le:DI (match_operand:DI 1 "register_operand" "d")
7322 (match_operand:DI 2 "small_int" "I")))]
7323 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
7325 operands[2] = GEN_INT (INTVAL (operands[2])+1);
7326 return "slt\t%0,%1,%2";
7328 [(set_attr "type" "arith")
7329 (set_attr "mode" "DI")])
7332 [(set (match_operand:DI 0 "register_operand" "=t")
7333 (le:DI (match_operand:DI 1 "register_operand" "d")
7334 (match_operand:DI 2 "small_int" "I")))]
7335 "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
7337 operands[2] = GEN_INT (INTVAL (operands[2])+1);
7338 return "slt\t%1,%2";
7340 [(set_attr "type" "arith")
7341 (set_attr "mode" "DI")
7342 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
7346 (define_insn "sle_si_reg"
7347 [(set (match_operand:SI 0 "register_operand" "=d")
7348 (le:SI (match_operand:SI 1 "register_operand" "d")
7349 (match_operand:SI 2 "register_operand" "d")))]
7350 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7351 "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
7352 [(set_attr "type" "arith")
7353 (set_attr "mode" "SI")
7354 (set_attr "length" "8")])
7357 [(set (match_operand:SI 0 "register_operand" "")
7358 (le:SI (match_operand:SI 1 "register_operand" "")
7359 (match_operand:SI 2 "register_operand" "")))]
7360 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
7362 (lt:SI (match_dup 2)
7365 (xor:SI (match_dup 0)
7369 (define_insn "sle_di_reg"
7370 [(set (match_operand:DI 0 "register_operand" "=d")
7371 (le:DI (match_operand:DI 1 "register_operand" "d")
7372 (match_operand:DI 2 "register_operand" "d")))]
7373 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7374 "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
7375 [(set_attr "type" "arith")
7376 (set_attr "mode" "DI")
7377 (set_attr "length" "8")])
7380 [(set (match_operand:DI 0 "register_operand" "")
7381 (le:DI (match_operand:DI 1 "register_operand" "")
7382 (match_operand:DI 2 "register_operand" "")))]
7383 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
7386 (lt:DI (match_dup 2)
7389 (xor:DI (match_dup 0)
7393 (define_expand "sgtu"
7394 [(set (match_operand:SI 0 "register_operand" "=d")
7395 (gtu:SI (match_dup 1)
7399 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
7402 /* set up operands from compare. */
7403 operands[1] = branch_cmp[0];
7404 operands[2] = branch_cmp[1];
7406 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
7408 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
7412 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
7413 operands[2] = force_reg (SImode, operands[2]);
7415 /* fall through and generate default code */
7418 (define_insn "sgtu_si"
7419 [(set (match_operand:SI 0 "register_operand" "=d")
7420 (gtu:SI (match_operand:SI 1 "register_operand" "d")
7421 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
7424 [(set_attr "type" "arith")
7425 (set_attr "mode" "SI")])
7428 [(set (match_operand:SI 0 "register_operand" "=t")
7429 (gtu:SI (match_operand:SI 1 "register_operand" "d")
7430 (match_operand:SI 2 "register_operand" "d")))]
7433 [(set_attr "type" "arith")
7434 (set_attr "mode" "SI")])
7436 (define_insn "sgtu_di"
7437 [(set (match_operand:DI 0 "register_operand" "=d")
7438 (gtu:DI (match_operand:DI 1 "register_operand" "d")
7439 (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
7440 "TARGET_64BIT && !TARGET_MIPS16"
7442 [(set_attr "type" "arith")
7443 (set_attr "mode" "DI")])
7446 [(set (match_operand:DI 0 "register_operand" "=t")
7447 (gtu:DI (match_operand:DI 1 "register_operand" "d")
7448 (match_operand:DI 2 "register_operand" "d")))]
7449 "TARGET_64BIT && TARGET_MIPS16"
7451 [(set_attr "type" "arith")
7452 (set_attr "mode" "DI")])
7454 (define_expand "sgeu"
7455 [(set (match_operand:SI 0 "register_operand" "=d")
7456 (geu:SI (match_dup 1)
7460 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
7463 /* set up operands from compare. */
7464 operands[1] = branch_cmp[0];
7465 operands[2] = branch_cmp[1];
7467 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
7469 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
7473 /* fall through and generate default code */
7476 (define_insn "sgeu_si"
7477 [(set (match_operand:SI 0 "register_operand" "=d")
7478 (geu:SI (match_operand:SI 1 "register_operand" "d")
7479 (match_operand:SI 2 "arith_operand" "dI")))]
7480 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7481 "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
7482 [(set_attr "type" "arith")
7483 (set_attr "mode" "SI")
7484 (set_attr "length" "8")])
7487 [(set (match_operand:SI 0 "register_operand" "")
7488 (geu:SI (match_operand:SI 1 "register_operand" "")
7489 (match_operand:SI 2 "arith_operand" "")))]
7490 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
7492 (ltu:SI (match_dup 1)
7495 (xor:SI (match_dup 0)
7499 (define_insn "sgeu_di"
7500 [(set (match_operand:DI 0 "register_operand" "=d")
7501 (geu:DI (match_operand:DI 1 "register_operand" "d")
7502 (match_operand:DI 2 "arith_operand" "dI")))]
7503 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7504 "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
7505 [(set_attr "type" "arith")
7506 (set_attr "mode" "DI")
7507 (set_attr "length" "8")])
7510 [(set (match_operand:DI 0 "register_operand" "")
7511 (geu:DI (match_operand:DI 1 "register_operand" "")
7512 (match_operand:DI 2 "arith_operand" "")))]
7513 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
7516 (ltu:DI (match_dup 1)
7519 (xor:DI (match_dup 0)
7523 (define_expand "sltu"
7524 [(set (match_operand:SI 0 "register_operand" "=d")
7525 (ltu:SI (match_dup 1)
7529 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
7532 /* set up operands from compare. */
7533 operands[1] = branch_cmp[0];
7534 operands[2] = branch_cmp[1];
7536 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
7538 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
7542 /* fall through and generate default code */
7545 (define_insn "sltu_si"
7546 [(set (match_operand:SI 0 "register_operand" "=d")
7547 (ltu:SI (match_operand:SI 1 "register_operand" "d")
7548 (match_operand:SI 2 "arith_operand" "dI")))]
7551 [(set_attr "type" "arith")
7552 (set_attr "mode" "SI")])
7555 [(set (match_operand:SI 0 "register_operand" "=t,t")
7556 (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
7557 (match_operand:SI 2 "arith_operand" "d,I")))]
7560 [(set_attr "type" "arith")
7561 (set_attr "mode" "SI")
7562 (set_attr_alternative "length"
7564 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
7568 (define_insn "sltu_di"
7569 [(set (match_operand:DI 0 "register_operand" "=d")
7570 (ltu:DI (match_operand:DI 1 "register_operand" "d")
7571 (match_operand:DI 2 "arith_operand" "dI")))]
7572 "TARGET_64BIT && !TARGET_MIPS16"
7574 [(set_attr "type" "arith")
7575 (set_attr "mode" "DI")])
7578 [(set (match_operand:DI 0 "register_operand" "=t,t")
7579 (ltu:DI (match_operand:DI 1 "register_operand" "d,d")
7580 (match_operand:DI 2 "arith_operand" "d,I")))]
7581 "TARGET_64BIT && TARGET_MIPS16"
7583 [(set_attr "type" "arith")
7584 (set_attr "mode" "DI")
7585 (set_attr_alternative "length"
7587 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
7591 (define_expand "sleu"
7592 [(set (match_operand:SI 0 "register_operand" "=d")
7593 (leu:SI (match_dup 1)
7597 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
7600 /* set up operands from compare. */
7601 operands[1] = branch_cmp[0];
7602 operands[2] = branch_cmp[1];
7604 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
7606 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
7610 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
7611 operands[2] = force_reg (SImode, operands[2]);
7613 /* fall through and generate default code */
7616 (define_insn "sleu_si_const"
7617 [(set (match_operand:SI 0 "register_operand" "=d")
7618 (leu:SI (match_operand:SI 1 "register_operand" "d")
7619 (match_operand:SI 2 "small_int" "I")))]
7620 "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
7622 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
7623 return "sltu\t%0,%1,%2";
7625 [(set_attr "type" "arith")
7626 (set_attr "mode" "SI")])
7629 [(set (match_operand:SI 0 "register_operand" "=t")
7630 (leu:SI (match_operand:SI 1 "register_operand" "d")
7631 (match_operand:SI 2 "small_int" "I")))]
7632 "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
7634 operands[2] = GEN_INT (INTVAL (operands[2])+1);
7635 return "sltu\t%1,%2";
7637 [(set_attr "type" "arith")
7638 (set_attr "mode" "SI")
7639 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
7643 (define_insn "sleu_di_const"
7644 [(set (match_operand:DI 0 "register_operand" "=d")
7645 (leu:DI (match_operand:DI 1 "register_operand" "d")
7646 (match_operand:DI 2 "small_int" "I")))]
7647 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
7649 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
7650 return "sltu\t%0,%1,%2";
7652 [(set_attr "type" "arith")
7653 (set_attr "mode" "DI")])
7656 [(set (match_operand:DI 0 "register_operand" "=t")
7657 (leu:DI (match_operand:DI 1 "register_operand" "d")
7658 (match_operand:DI 2 "small_int" "I")))]
7659 "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
7661 operands[2] = GEN_INT (INTVAL (operands[2])+1);
7662 return "sltu\t%1,%2";
7664 [(set_attr "type" "arith")
7665 (set_attr "mode" "DI")
7666 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
7670 (define_insn "sleu_si_reg"
7671 [(set (match_operand:SI 0 "register_operand" "=d")
7672 (leu:SI (match_operand:SI 1 "register_operand" "d")
7673 (match_operand:SI 2 "register_operand" "d")))]
7674 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7675 "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
7676 [(set_attr "type" "arith")
7677 (set_attr "mode" "SI")
7678 (set_attr "length" "8")])
7681 [(set (match_operand:SI 0 "register_operand" "")
7682 (leu:SI (match_operand:SI 1 "register_operand" "")
7683 (match_operand:SI 2 "register_operand" "")))]
7684 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
7686 (ltu:SI (match_dup 2)
7689 (xor:SI (match_dup 0)
7693 (define_insn "sleu_di_reg"
7694 [(set (match_operand:DI 0 "register_operand" "=d")
7695 (leu:DI (match_operand:DI 1 "register_operand" "d")
7696 (match_operand:DI 2 "register_operand" "d")))]
7697 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
7698 "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
7699 [(set_attr "type" "arith")
7700 (set_attr "mode" "DI")
7701 (set_attr "length" "8")])
7704 [(set (match_operand:DI 0 "register_operand" "")
7705 (leu:DI (match_operand:DI 1 "register_operand" "")
7706 (match_operand:DI 2 "register_operand" "")))]
7707 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
7710 (ltu:DI (match_dup 2)
7713 (xor:DI (match_dup 0)
7718 ;; ....................
7720 ;; FLOATING POINT COMPARISONS
7722 ;; ....................
7724 (define_insn "sunordered_df"
7725 [(set (match_operand:CC 0 "register_operand" "=z")
7726 (unordered:CC (match_operand:DF 1 "register_operand" "f")
7727 (match_operand:DF 2 "register_operand" "f")))]
7728 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7730 [(set_attr "type" "fcmp")
7731 (set_attr "mode" "FPSW")])
7733 (define_insn "sunlt_df"
7734 [(set (match_operand:CC 0 "register_operand" "=z")
7735 (unlt:CC (match_operand:DF 1 "register_operand" "f")
7736 (match_operand:DF 2 "register_operand" "f")))]
7737 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7739 [(set_attr "type" "fcmp")
7740 (set_attr "mode" "FPSW")])
7742 (define_insn "suneq_df"
7743 [(set (match_operand:CC 0 "register_operand" "=z")
7744 (uneq:CC (match_operand:DF 1 "register_operand" "f")
7745 (match_operand:DF 2 "register_operand" "f")))]
7746 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7748 [(set_attr "type" "fcmp")
7749 (set_attr "mode" "FPSW")])
7751 (define_insn "sunle_df"
7752 [(set (match_operand:CC 0 "register_operand" "=z")
7753 (unle:CC (match_operand:DF 1 "register_operand" "f")
7754 (match_operand:DF 2 "register_operand" "f")))]
7755 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7757 [(set_attr "type" "fcmp")
7758 (set_attr "mode" "FPSW")])
7760 (define_insn "seq_df"
7761 [(set (match_operand:CC 0 "register_operand" "=z")
7762 (eq:CC (match_operand:DF 1 "register_operand" "f")
7763 (match_operand:DF 2 "register_operand" "f")))]
7764 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7766 [(set_attr "type" "fcmp")
7767 (set_attr "mode" "FPSW")])
7769 (define_insn "slt_df"
7770 [(set (match_operand:CC 0 "register_operand" "=z")
7771 (lt:CC (match_operand:DF 1 "register_operand" "f")
7772 (match_operand:DF 2 "register_operand" "f")))]
7773 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7775 [(set_attr "type" "fcmp")
7776 (set_attr "mode" "FPSW")])
7778 (define_insn "sle_df"
7779 [(set (match_operand:CC 0 "register_operand" "=z")
7780 (le:CC (match_operand:DF 1 "register_operand" "f")
7781 (match_operand:DF 2 "register_operand" "f")))]
7782 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7784 [(set_attr "type" "fcmp")
7785 (set_attr "mode" "FPSW")])
7787 (define_insn "sgt_df"
7788 [(set (match_operand:CC 0 "register_operand" "=z")
7789 (gt:CC (match_operand:DF 1 "register_operand" "f")
7790 (match_operand:DF 2 "register_operand" "f")))]
7791 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7793 [(set_attr "type" "fcmp")
7794 (set_attr "mode" "FPSW")])
7796 (define_insn "sge_df"
7797 [(set (match_operand:CC 0 "register_operand" "=z")
7798 (ge:CC (match_operand:DF 1 "register_operand" "f")
7799 (match_operand:DF 2 "register_operand" "f")))]
7800 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7802 [(set_attr "type" "fcmp")
7803 (set_attr "mode" "FPSW")])
7805 (define_insn "sunordered_sf"
7806 [(set (match_operand:CC 0 "register_operand" "=z")
7807 (unordered:CC (match_operand:SF 1 "register_operand" "f")
7808 (match_operand:SF 2 "register_operand" "f")))]
7811 [(set_attr "type" "fcmp")
7812 (set_attr "mode" "FPSW")])
7814 (define_insn "sunlt_sf"
7815 [(set (match_operand:CC 0 "register_operand" "=z")
7816 (unlt:CC (match_operand:SF 1 "register_operand" "f")
7817 (match_operand:SF 2 "register_operand" "f")))]
7820 [(set_attr "type" "fcmp")
7821 (set_attr "mode" "FPSW")])
7823 (define_insn "suneq_sf"
7824 [(set (match_operand:CC 0 "register_operand" "=z")
7825 (uneq:CC (match_operand:SF 1 "register_operand" "f")
7826 (match_operand:SF 2 "register_operand" "f")))]
7829 [(set_attr "type" "fcmp")
7830 (set_attr "mode" "FPSW")])
7832 (define_insn "sunle_sf"
7833 [(set (match_operand:CC 0 "register_operand" "=z")
7834 (unle:CC (match_operand:SF 1 "register_operand" "f")
7835 (match_operand:SF 2 "register_operand" "f")))]
7838 [(set_attr "type" "fcmp")
7839 (set_attr "mode" "FPSW")])
7841 (define_insn "seq_sf"
7842 [(set (match_operand:CC 0 "register_operand" "=z")
7843 (eq:CC (match_operand:SF 1 "register_operand" "f")
7844 (match_operand:SF 2 "register_operand" "f")))]
7847 [(set_attr "type" "fcmp")
7848 (set_attr "mode" "FPSW")])
7850 (define_insn "slt_sf"
7851 [(set (match_operand:CC 0 "register_operand" "=z")
7852 (lt:CC (match_operand:SF 1 "register_operand" "f")
7853 (match_operand:SF 2 "register_operand" "f")))]
7856 [(set_attr "type" "fcmp")
7857 (set_attr "mode" "FPSW")])
7859 (define_insn "sle_sf"
7860 [(set (match_operand:CC 0 "register_operand" "=z")
7861 (le:CC (match_operand:SF 1 "register_operand" "f")
7862 (match_operand:SF 2 "register_operand" "f")))]
7865 [(set_attr "type" "fcmp")
7866 (set_attr "mode" "FPSW")])
7868 (define_insn "sgt_sf"
7869 [(set (match_operand:CC 0 "register_operand" "=z")
7870 (gt:CC (match_operand:SF 1 "register_operand" "f")
7871 (match_operand:SF 2 "register_operand" "f")))]
7874 [(set_attr "type" "fcmp")
7875 (set_attr "mode" "FPSW")])
7877 (define_insn "sge_sf"
7878 [(set (match_operand:CC 0 "register_operand" "=z")
7879 (ge:CC (match_operand:SF 1 "register_operand" "f")
7880 (match_operand:SF 2 "register_operand" "f")))]
7883 [(set_attr "type" "fcmp")
7884 (set_attr "mode" "FPSW")])
7887 ;; ....................
7889 ;; UNCONDITIONAL BRANCHES
7891 ;; ....................
7893 ;; Unconditional branches.
7897 (label_ref (match_operand 0 "" "")))]
7900 if (flag_pic && ! TARGET_EMBEDDED_PIC)
7902 if (get_attr_length (insn) <= 8)
7903 return "%*b\t%l0%/";
7906 output_asm_insn (mips_output_load_label (), operands);
7907 return "%*jr\t%@%/%]";
7911 return "%*j\t%l0%/";
7913 [(set_attr "type" "jump")
7914 (set_attr "mode" "none")
7915 (set (attr "length")
7916 ;; we can't use `j' when emitting non-embedded PIC, so we emit
7917 ;; branch, if it's in range, or load the address of the branch
7918 ;; target into $at in a PIC-compatible way and then jump to it.
7920 (ior (eq (symbol_ref "flag_pic && ! TARGET_EMBEDDED_PIC")
7922 (lt (abs (minus (match_dup 0)
7923 (plus (pc) (const_int 4))))
7924 (const_int 131072)))
7925 (const_int 4) (const_int 16)))])
7927 ;; We need a different insn for the mips16, because a mips16 branch
7928 ;; does not have a delay slot.
7932 (label_ref (match_operand 0 "" "")))]
7935 [(set_attr "type" "branch")
7936 (set_attr "mode" "none")
7937 (set_attr "length" "8")])
7939 (define_expand "indirect_jump"
7940 [(set (pc) (match_operand 0 "register_operand" "d"))]
7946 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
7947 operands[0] = copy_to_mode_reg (Pmode, dest);
7949 if (!(Pmode == DImode))
7950 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
7952 emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
7957 (define_insn "indirect_jump_internal1"
7958 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
7959 "!(Pmode == DImode)"
7961 [(set_attr "type" "jump")
7962 (set_attr "mode" "none")])
7964 (define_insn "indirect_jump_internal2"
7965 [(set (pc) (match_operand:DI 0 "register_operand" "d"))]
7968 [(set_attr "type" "jump")
7969 (set_attr "mode" "none")])
7971 (define_expand "tablejump"
7973 (match_operand 0 "register_operand" "d"))
7974 (use (label_ref (match_operand 1 "" "")))]
7979 if (GET_MODE (operands[0]) != HImode)
7981 if (!(Pmode == DImode))
7982 emit_insn (gen_tablejump_mips161 (operands[0], operands[1]));
7984 emit_insn (gen_tablejump_mips162 (operands[0], operands[1]));
7988 if (GET_MODE (operands[0]) != ptr_mode)
7992 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
7993 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
7995 if (Pmode == SImode)
7996 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
7998 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
8002 (define_insn "tablejump_internal1"
8004 (match_operand:SI 0 "register_operand" "d"))
8005 (use (label_ref (match_operand 1 "" "")))]
8008 [(set_attr "type" "jump")
8009 (set_attr "mode" "none")])
8011 (define_insn "tablejump_internal2"
8013 (match_operand:DI 0 "register_operand" "d"))
8014 (use (label_ref (match_operand 1 "" "")))]
8017 [(set_attr "type" "jump")
8018 (set_attr "mode" "none")])
8020 (define_expand "tablejump_mips161"
8021 [(set (pc) (plus:SI (sign_extend:SI
8022 (match_operand:HI 0 "register_operand" "d"))
8023 (label_ref:SI (match_operand 1 "" ""))))]
8024 "TARGET_MIPS16 && !(Pmode == DImode)"
8028 t1 = gen_reg_rtx (SImode);
8029 t2 = gen_reg_rtx (SImode);
8030 t3 = gen_reg_rtx (SImode);
8031 emit_insn (gen_extendhisi2 (t1, operands[0]));
8032 emit_move_insn (t2, gen_rtx_LABEL_REF (SImode, operands[1]));
8033 emit_insn (gen_addsi3 (t3, t1, t2));
8034 emit_jump_insn (gen_tablejump_internal1 (t3, operands[1]));
8038 (define_expand "tablejump_mips162"
8039 [(set (pc) (plus:DI (sign_extend:DI
8040 (match_operand:HI 0 "register_operand" "d"))
8041 (label_ref:DI (match_operand 1 "" ""))))]
8042 "TARGET_MIPS16 && Pmode == DImode"
8046 t1 = gen_reg_rtx (DImode);
8047 t2 = gen_reg_rtx (DImode);
8048 t3 = gen_reg_rtx (DImode);
8049 emit_insn (gen_extendhidi2 (t1, operands[0]));
8050 emit_move_insn (t2, gen_rtx_LABEL_REF (DImode, operands[1]));
8051 emit_insn (gen_adddi3 (t3, t1, t2));
8052 emit_jump_insn (gen_tablejump_internal2 (t3, operands[1]));
8056 ;; Implement a switch statement when generating embedded PIC code.
8057 ;; Switches are implemented by `tablejump' when not using -membedded-pic.
8059 (define_expand "casesi"
8061 (minus:SI (match_operand:SI 0 "register_operand" "")
8062 (match_operand:SI 1 "const_int_operand" "")))
8064 (compare:CC (match_dup 5)
8065 (match_operand:SI 2 "arith_operand" "")))
8067 (if_then_else (gtu (cc0)
8069 (label_ref (match_operand 4 "" ""))
8073 (mem:SI (plus:SI (mult:SI (match_dup 5)
8075 (label_ref (match_operand 3 "" "")))))
8076 (clobber (match_scratch:SI 6 ""))
8077 (clobber (reg:SI 31))])]
8078 "TARGET_EMBEDDED_PIC"
8082 /* If the index is too large, go to the default label. */
8083 index = expand_binop (SImode, sub_optab, operands[0],
8084 operands[1], 0, 0, OPTAB_WIDEN);
8085 emit_insn (gen_cmpsi (index, operands[2]));
8086 emit_insn (gen_bgtu (operands[4]));
8088 /* Do the PIC jump. */
8089 if (Pmode != DImode)
8090 emit_jump_insn (gen_casesi_internal (index, operands[3],
8091 gen_reg_rtx (SImode)));
8093 emit_jump_insn (gen_casesi_internal_di (index, operands[3],
8094 gen_reg_rtx (DImode)));
8099 ;; An embedded PIC switch statement looks like this:
8101 ;; sll $reg,$index,2
8103 ;; addu $reg,$reg,$31
8104 ;; lw $reg,$L1-$LS1($reg)
8105 ;; addu $reg,$reg,$31
8112 (define_insn "casesi_internal"
8114 (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
8116 (label_ref (match_operand 1 "" "")))))
8117 (clobber (match_operand:SI 2 "register_operand" "=d"))
8118 (clobber (reg:SI 31))]
8119 "TARGET_EMBEDDED_PIC"
8120 "%(bal\t%S1\;sll\t%2,%0,2\n%~%S1:\;addu\t%2,%2,$31%)\;\
8121 lw\t%2,%1-%S1(%2)\;addu\t%2,%2,$31\;%*j\t%2%/"
8122 [(set_attr "type" "jump")
8123 (set_attr "mode" "none")
8124 (set_attr "length" "24")])
8126 ;; This code assumes that the table index will never be >= 29 bits wide,
8127 ;; which allows the 'sign extend' from SI to DI be a no-op.
8128 (define_insn "casesi_internal_di"
8130 (mem:DI (plus:DI (sign_extend:DI
8131 (mult:SI (match_operand:SI 0 "register_operand" "d")
8133 (label_ref (match_operand 1 "" "")))))
8134 (clobber (match_operand:DI 2 "register_operand" "=d"))
8135 (clobber (reg:DI 31))]
8136 "TARGET_EMBEDDED_PIC"
8137 "%(bal\t%S1\;sll\t%2,%0,3\n%~%S1:\;daddu\t%2,%2,$31%)\;\
8138 ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j\t%2%/"
8139 [(set_attr "type" "jump")
8140 (set_attr "mode" "none")
8141 (set_attr "length" "24")])
8143 ;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
8144 ;; While it is possible to either pull it off the stack (in the
8145 ;; o32 case) or recalculate it given t9 and our target label,
8146 ;; it takes 3 or 4 insns to do so.
8148 (define_expand "builtin_setjmp_setup"
8149 [(use (match_operand 0 "register_operand" ""))]
8154 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
8155 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
8159 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
8160 ;; that older code did recalculate the gp from $25. Continue to jump through
8161 ;; $25 for compatibility (we lose nothing by doing so).
8163 (define_expand "builtin_longjmp"
8164 [(use (match_operand 0 "register_operand" "r"))]
8167 /* The elements of the buffer are, in order: */
8168 int W = GET_MODE_SIZE (Pmode);
8169 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8170 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
8171 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
8172 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
8173 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8174 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
8175 The target is bound to be using $28 as the global pointer
8176 but the current function might not be. */
8177 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
8179 /* This bit is similar to expand_builtin_longjmp except that it
8180 restores $gp as well. */
8181 emit_move_insn (hard_frame_pointer_rtx, fp);
8182 emit_move_insn (pv, lab);
8183 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8184 emit_move_insn (gp, gpv);
8185 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8186 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8187 emit_insn (gen_rtx_USE (VOIDmode, gp));
8188 emit_indirect_jump (pv);
8193 ;; ....................
8195 ;; Function prologue/epilogue
8197 ;; ....................
8200 (define_expand "prologue"
8204 mips_expand_prologue ();
8208 ;; Block any insns from being moved before this point, since the
8209 ;; profiling call to mcount can use various registers that aren't
8210 ;; saved or used to pass arguments.
8212 (define_insn "blockage"
8213 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
8216 [(set_attr "type" "unknown")
8217 (set_attr "mode" "none")
8218 (set_attr "length" "0")])
8220 (define_expand "epilogue"
8224 mips_expand_epilogue (false);
8228 (define_expand "sibcall_epilogue"
8232 mips_expand_epilogue (true);
8236 ;; Trivial return. Make it look like a normal return insn as that
8237 ;; allows jump optimizations to work better.
8239 (define_insn "return"
8241 "mips_can_use_return_insn ()"
8243 [(set_attr "type" "jump")
8244 (set_attr "mode" "none")])
8248 (define_insn "return_internal"
8249 [(use (match_operand 0 "pmode_register_operand" ""))
8253 [(set_attr "type" "jump")
8254 (set_attr "mode" "none")])
8256 ;; When generating embedded PIC code we need to get the address of the
8257 ;; current function. This specialized instruction does just that.
8259 (define_insn "get_fnaddr"
8260 [(set (match_operand 0 "register_operand" "=d")
8261 (unspec [(match_operand 1 "" "")] UNSPEC_GET_FNADDR))
8262 (clobber (reg:SI 31))]
8263 "TARGET_EMBEDDED_PIC
8264 && GET_CODE (operands[1]) == SYMBOL_REF"
8265 "%($LF%= = . + 8\;bal\t$LF%=\;nop;la\t%0,%1-$LF%=%)\;addu\t%0,%0,$31"
8266 [(set_attr "type" "call")
8267 (set_attr "mode" "none")
8268 (set_attr "length" "20")])
8270 ;; This is used in compiling the unwind routines.
8271 (define_expand "eh_return"
8272 [(use (match_operand 0 "general_operand" ""))]
8275 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
8277 if (GET_MODE (operands[0]) != gpr_mode)
8278 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
8280 emit_insn (gen_eh_set_lr_di (operands[0]));
8282 emit_insn (gen_eh_set_lr_si (operands[0]));
8287 ;; Clobber the return address on the stack. We can't expand this
8288 ;; until we know where it will be put in the stack frame.
8290 (define_insn "eh_set_lr_si"
8291 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
8292 (clobber (match_scratch:SI 1 "=&d"))]
8296 (define_insn "eh_set_lr_di"
8297 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
8298 (clobber (match_scratch:DI 1 "=&d"))]
8303 [(unspec [(match_operand 0 "register_operand" "")] UNSPEC_EH_RETURN)
8304 (clobber (match_scratch 1 ""))]
8305 "reload_completed && !TARGET_DEBUG_D_MODE"
8308 mips_set_return_address (operands[0], operands[1]);
8312 (define_insn "exception_receiver"
8314 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
8315 "TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
8317 operands[0] = pic_offset_table_rtx;
8318 operands[1] = mips_gp_save_slot ();
8319 return mips_output_move (operands[0], operands[1]);
8321 [(set_attr "type" "load")
8322 (set_attr "length" "8")])
8325 ;; ....................
8329 ;; ....................
8331 ;; Sibling calls. All these patterns use jump instructions.
8333 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
8334 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
8335 ;; is defined in terms of call_insn_operand, the same is true of the
8338 ;; When we use an indirect jump, we need a register that will be
8339 ;; preserved by the epilogue. Since TARGET_ABICALLS forces us to
8340 ;; use $25 for this purpose -- and $25 is never clobbered by the
8341 ;; epilogue -- we might as well use it for !TARGET_ABICALLS as well.
8343 (define_expand "sibcall"
8344 [(parallel [(call (match_operand 0 "" "")
8345 (match_operand 1 "" ""))
8346 (use (match_operand 2 "" "")) ;; next_arg_reg
8347 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
8350 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
8354 (define_insn "sibcall_internal"
8355 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
8356 (match_operand 1 "" ""))]
8357 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
8361 [(set_attr "type" "call")])
8363 (define_expand "sibcall_value"
8364 [(parallel [(set (match_operand 0 "" "")
8365 (call (match_operand 1 "" "")
8366 (match_operand 2 "" "")))
8367 (use (match_operand 3 "" ""))])] ;; next_arg_reg
8370 mips_expand_call (operands[0], XEXP (operands[1], 0),
8371 operands[2], operands[3], true);
8375 (define_insn "sibcall_value_internal"
8376 [(set (match_operand 0 "register_operand" "=df,df")
8377 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
8378 (match_operand 2 "" "")))]
8379 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
8383 [(set_attr "type" "call")])
8385 (define_insn "sibcall_value_multiple_internal"
8386 [(set (match_operand 0 "register_operand" "=df,df")
8387 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
8388 (match_operand 2 "" "")))
8389 (set (match_operand 3 "register_operand" "=df,df")
8390 (call (mem:SI (match_dup 1))
8392 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
8396 [(set_attr "type" "call")])
8398 (define_expand "call"
8399 [(parallel [(call (match_operand 0 "" "")
8400 (match_operand 1 "" ""))
8401 (use (match_operand 2 "" "")) ;; next_arg_reg
8402 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
8405 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
8409 ;; This instruction directly corresponds to an assembly-language "jal".
8410 ;; There are four cases:
8413 ;; Both symbolic and register destinations are OK. The pattern
8414 ;; always expands to a single mips instruction.
8416 ;; - -mabicalls/-mno-explicit-relocs:
8417 ;; Again, both symbolic and register destinations are OK.
8418 ;; The call is treated as a multi-instruction black box.
8420 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
8421 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
8424 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
8425 ;; Only "jal $25" is allowed. The call is actually two instructions:
8426 ;; "jalr $25" followed by an insn to reload $gp.
8428 ;; In the last case, we can generate the individual instructions with
8429 ;; a define_split. There are several things to be wary of:
8431 ;; - We can't expose the load of $gp before reload. If we did,
8432 ;; it might get removed as dead, but reload can introduce new
8433 ;; uses of $gp by rematerializing constants.
8435 ;; - We shouldn't restore $gp after calls that never return.
8436 ;; It isn't valid to insert instructions between a noreturn
8437 ;; call and the following barrier.
8439 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
8440 ;; instruction preserves $gp and so have no effect on its liveness.
8441 ;; But once we generate the separate insns, it becomes obvious that
8442 ;; $gp is not live on entry to the call.
8444 ;; ??? The operands[2] = insn check is a hack to make the original insn
8445 ;; available to the splitter.
8446 (define_insn_and_split "call_internal"
8447 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
8448 (match_operand 1 "" ""))
8449 (clobber (reg:SI 31))]
8451 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%0%/"; }
8452 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
8455 emit_call_insn (gen_call_split (operands[0], operands[1]));
8456 if (!find_reg_note (operands[2], REG_NORETURN, 0))
8457 emit_move_insn (pic_offset_table_rtx, mips_gp_save_slot ());
8460 [(set_attr "jal" "indirect,direct")
8461 (set_attr "extended_mips16" "no,yes")])
8463 (define_insn "call_split"
8464 [(call (mem:SI (match_operand 0 "call_insn_operand" "c"))
8465 (match_operand 1 "" ""))
8466 (clobber (reg:SI 31))
8467 (clobber (reg:SI 28))]
8468 "TARGET_SPLIT_CALLS"
8470 [(set_attr "type" "call")])
8472 (define_expand "call_value"
8473 [(parallel [(set (match_operand 0 "" "")
8474 (call (match_operand 1 "" "")
8475 (match_operand 2 "" "")))
8476 (use (match_operand 3 "" ""))])] ;; next_arg_reg
8479 mips_expand_call (operands[0], XEXP (operands[1], 0),
8480 operands[2], operands[3], false);
8484 ;; See comment for call_internal.
8485 (define_insn_and_split "call_value_internal"
8486 [(set (match_operand 0 "register_operand" "=df,df")
8487 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
8488 (match_operand 2 "" "")))
8489 (clobber (reg:SI 31))]
8491 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
8492 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
8495 emit_call_insn (gen_call_value_split (operands[0], operands[1],
8497 if (!find_reg_note (operands[3], REG_NORETURN, 0))
8498 emit_move_insn (pic_offset_table_rtx, mips_gp_save_slot ());
8501 [(set_attr "jal" "indirect,direct")
8502 (set_attr "extended_mips16" "no,yes")])
8504 (define_insn "call_value_split"
8505 [(set (match_operand 0 "register_operand" "=df")
8506 (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
8507 (match_operand 2 "" "")))
8508 (clobber (reg:SI 31))
8509 (clobber (reg:SI 28))]
8510 "TARGET_SPLIT_CALLS"
8512 [(set_attr "type" "call")])
8514 ;; See comment for call_internal.
8515 (define_insn_and_split "call_value_multiple_internal"
8516 [(set (match_operand 0 "register_operand" "=df,df")
8517 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
8518 (match_operand 2 "" "")))
8519 (set (match_operand 3 "register_operand" "=df,df")
8520 (call (mem:SI (match_dup 1))
8522 (clobber (reg:SI 31))]
8524 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
8525 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
8528 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
8529 operands[2], operands[3]));
8530 if (!find_reg_note (operands[4], REG_NORETURN, 0))
8531 emit_move_insn (pic_offset_table_rtx, mips_gp_save_slot ());
8534 [(set_attr "jal" "indirect,direct")
8535 (set_attr "extended_mips16" "no,yes")])
8537 (define_insn "call_value_multiple_split"
8538 [(set (match_operand 0 "register_operand" "=df")
8539 (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
8540 (match_operand 2 "" "")))
8541 (set (match_operand 3 "register_operand" "=df")
8542 (call (mem:SI (match_dup 1))
8544 (clobber (reg:SI 31))
8545 (clobber (reg:SI 28))]
8546 "TARGET_SPLIT_CALLS"
8548 [(set_attr "type" "call")])
8550 ;; Call subroutine returning any type.
8552 (define_expand "untyped_call"
8553 [(parallel [(call (match_operand 0 "" "")
8555 (match_operand 1 "" "")
8556 (match_operand 2 "" "")])]
8561 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8563 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8565 rtx set = XVECEXP (operands[2], 0, i);
8566 emit_move_insn (SET_DEST (set), SET_SRC (set));
8569 emit_insn (gen_blockage ());
8574 ;; ....................
8578 ;; ....................
8582 (define_expand "prefetch"
8583 [(prefetch (match_operand 0 "address_operand" "")
8584 (match_operand 1 "const_int_operand" "")
8585 (match_operand 2 "const_int_operand" ""))]
8588 if (symbolic_operand (operands[0], GET_MODE (operands[0])))
8589 operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
8592 (define_insn "prefetch_si_address"
8593 [(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
8594 (match_operand:SI 3 "const_int_operand" "I"))
8595 (match_operand:SI 1 "const_int_operand" "n")
8596 (match_operand:SI 2 "const_int_operand" "n"))]
8597 "ISA_HAS_PREFETCH && Pmode == SImode"
8598 { return mips_emit_prefetch (operands); }
8599 [(set_attr "type" "prefetch")])
8601 (define_insn "prefetch_indexed_si"
8602 [(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
8603 (match_operand:SI 3 "register_operand" "r"))
8604 (match_operand:SI 1 "const_int_operand" "n")
8605 (match_operand:SI 2 "const_int_operand" "n"))]
8606 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == SImode"
8607 { return mips_emit_prefetch (operands); }
8608 [(set_attr "type" "prefetchx")])
8610 (define_insn "prefetch_si"
8611 [(prefetch (match_operand:SI 0 "register_operand" "r")
8612 (match_operand:SI 1 "const_int_operand" "n")
8613 (match_operand:SI 2 "const_int_operand" "n"))]
8614 "ISA_HAS_PREFETCH && Pmode == SImode"
8616 operands[3] = const0_rtx;
8617 return mips_emit_prefetch (operands);
8619 [(set_attr "type" "prefetch")])
8621 (define_insn "prefetch_di_address"
8622 [(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
8623 (match_operand:DI 3 "const_int_operand" "I"))
8624 (match_operand:DI 1 "const_int_operand" "n")
8625 (match_operand:DI 2 "const_int_operand" "n"))]
8626 "ISA_HAS_PREFETCH && Pmode == DImode"
8627 { return mips_emit_prefetch (operands); }
8628 [(set_attr "type" "prefetch")])
8630 (define_insn "prefetch_indexed_di"
8631 [(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
8632 (match_operand:DI 3 "register_operand" "r"))
8633 (match_operand:DI 1 "const_int_operand" "n")
8634 (match_operand:DI 2 "const_int_operand" "n"))]
8635 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == DImode"
8636 { return mips_emit_prefetch (operands); }
8637 [(set_attr "type" "prefetchx")])
8639 (define_insn "prefetch_di"
8640 [(prefetch (match_operand:DI 0 "register_operand" "r")
8641 (match_operand:DI 1 "const_int_operand" "n")
8642 (match_operand:DI 2 "const_int_operand" "n"))]
8643 "ISA_HAS_PREFETCH && Pmode == DImode"
8645 operands[3] = const0_rtx;
8646 return mips_emit_prefetch (operands);
8648 [(set_attr "type" "prefetch")])
8654 [(set_attr "type" "nop")
8655 (set_attr "mode" "none")])
8657 ;; Like nop, but commented out when outside a .set noreorder block.
8658 (define_insn "hazard_nop"
8667 [(set_attr "type" "arith")])
8669 ;; MIPS4 Conditional move instructions.
8672 [(set (match_operand:SI 0 "register_operand" "=d,d")
8674 (match_operator 4 "equality_op"
8675 [(match_operand:SI 1 "register_operand" "d,d")
8677 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
8678 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
8679 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
8683 [(set_attr "type" "condmove")
8684 (set_attr "mode" "SI")])
8687 [(set (match_operand:SI 0 "register_operand" "=d,d")
8689 (match_operator 4 "equality_op"
8690 [(match_operand:DI 1 "register_operand" "d,d")
8692 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
8693 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
8694 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
8698 [(set_attr "type" "condmove")
8699 (set_attr "mode" "SI")])
8702 [(set (match_operand:SI 0 "register_operand" "=d,d")
8704 (match_operator 3 "equality_op" [(match_operand:CC 4
8708 (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
8709 (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
8710 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
8714 [(set_attr "type" "condmove")
8715 (set_attr "mode" "SI")])
8718 [(set (match_operand:DI 0 "register_operand" "=d,d")
8720 (match_operator 4 "equality_op"
8721 [(match_operand:SI 1 "register_operand" "d,d")
8723 (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
8724 (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
8725 "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
8729 [(set_attr "type" "condmove")
8730 (set_attr "mode" "DI")])
8733 [(set (match_operand:DI 0 "register_operand" "=d,d")
8735 (match_operator 4 "equality_op"
8736 [(match_operand:DI 1 "register_operand" "d,d")
8738 (match_operand:DI 2 "reg_or_0_operand" "dJ,0")
8739 (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
8740 "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
8744 [(set_attr "type" "condmove")
8745 (set_attr "mode" "DI")])
8748 [(set (match_operand:DI 0 "register_operand" "=d,d")
8750 (match_operator 3 "equality_op" [(match_operand:CC 4
8754 (match_operand:DI 1 "reg_or_0_operand" "dJ,0")
8755 (match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
8756 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
8760 [(set_attr "type" "condmove")
8761 (set_attr "mode" "DI")])
8764 [(set (match_operand:SF 0 "register_operand" "=f,f")
8766 (match_operator 4 "equality_op"
8767 [(match_operand:SI 1 "register_operand" "d,d")
8769 (match_operand:SF 2 "register_operand" "f,0")
8770 (match_operand:SF 3 "register_operand" "0,f")))]
8771 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
8775 [(set_attr "type" "condmove")
8776 (set_attr "mode" "SF")])
8779 [(set (match_operand:SF 0 "register_operand" "=f,f")
8781 (match_operator 4 "equality_op"
8782 [(match_operand:DI 1 "register_operand" "d,d")
8784 (match_operand:SF 2 "register_operand" "f,0")
8785 (match_operand:SF 3 "register_operand" "0,f")))]
8786 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
8790 [(set_attr "type" "condmove")
8791 (set_attr "mode" "SF")])
8794 [(set (match_operand:SF 0 "register_operand" "=f,f")
8796 (match_operator 3 "equality_op" [(match_operand:CC 4
8800 (match_operand:SF 1 "register_operand" "f,0")
8801 (match_operand:SF 2 "register_operand" "0,f")))]
8802 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
8806 [(set_attr "type" "condmove")
8807 (set_attr "mode" "SF")])
8810 [(set (match_operand:DF 0 "register_operand" "=f,f")
8812 (match_operator 4 "equality_op"
8813 [(match_operand:SI 1 "register_operand" "d,d")
8815 (match_operand:DF 2 "register_operand" "f,0")
8816 (match_operand:DF 3 "register_operand" "0,f")))]
8817 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8821 [(set_attr "type" "condmove")
8822 (set_attr "mode" "DF")])
8825 [(set (match_operand:DF 0 "register_operand" "=f,f")
8827 (match_operator 4 "equality_op"
8828 [(match_operand:DI 1 "register_operand" "d,d")
8830 (match_operand:DF 2 "register_operand" "f,0")
8831 (match_operand:DF 3 "register_operand" "0,f")))]
8832 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8836 [(set_attr "type" "condmove")
8837 (set_attr "mode" "DF")])
8840 [(set (match_operand:DF 0 "register_operand" "=f,f")
8842 (match_operator 3 "equality_op" [(match_operand:CC 4
8846 (match_operand:DF 1 "register_operand" "f,0")
8847 (match_operand:DF 2 "register_operand" "0,f")))]
8848 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8852 [(set_attr "type" "condmove")
8853 (set_attr "mode" "DF")])
8855 ;; These are the main define_expand's used to make conditional moves.
8857 (define_expand "movsicc"
8858 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
8859 (set (match_operand:SI 0 "register_operand" "")
8860 (if_then_else:SI (match_dup 5)
8861 (match_operand:SI 2 "reg_or_0_operand" "")
8862 (match_operand:SI 3 "reg_or_0_operand" "")))]
8863 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
8865 gen_conditional_move (operands);
8869 (define_expand "movdicc"
8870 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
8871 (set (match_operand:DI 0 "register_operand" "")
8872 (if_then_else:DI (match_dup 5)
8873 (match_operand:DI 2 "reg_or_0_operand" "")
8874 (match_operand:DI 3 "reg_or_0_operand" "")))]
8875 "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
8877 gen_conditional_move (operands);
8881 (define_expand "movsfcc"
8882 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
8883 (set (match_operand:SF 0 "register_operand" "")
8884 (if_then_else:SF (match_dup 5)
8885 (match_operand:SF 2 "register_operand" "")
8886 (match_operand:SF 3 "register_operand" "")))]
8887 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
8889 gen_conditional_move (operands);
8893 (define_expand "movdfcc"
8894 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
8895 (set (match_operand:DF 0 "register_operand" "")
8896 (if_then_else:DF (match_dup 5)
8897 (match_operand:DF 2 "register_operand" "")
8898 (match_operand:DF 3 "register_operand" "")))]
8899 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8901 gen_conditional_move (operands);
8906 ;; ....................
8908 ;; mips16 inline constant tables
8910 ;; ....................
8913 (define_insn "consttable_qi"
8914 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")]
8915 UNSPEC_CONSTTABLE_QI)]
8918 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
8921 [(set_attr "type" "unknown")
8922 (set_attr "mode" "QI")
8923 (set_attr "length" "8")])
8925 (define_insn "consttable_hi"
8926 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")]
8927 UNSPEC_CONSTTABLE_HI)]
8930 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
8933 [(set_attr "type" "unknown")
8934 (set_attr "mode" "HI")
8935 (set_attr "length" "8")])
8937 (define_insn "consttable_si"
8938 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")]
8939 UNSPEC_CONSTTABLE_SI)]
8942 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
8945 [(set_attr "type" "unknown")
8946 (set_attr "mode" "SI")
8947 (set_attr "length" "8")])
8949 (define_insn "consttable_di"
8950 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")]
8951 UNSPEC_CONSTTABLE_DI)]
8954 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
8957 [(set_attr "type" "unknown")
8958 (set_attr "mode" "DI")
8959 (set_attr "length" "16")])
8961 (define_insn "consttable_sf"
8962 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")]
8963 UNSPEC_CONSTTABLE_SF)]
8968 if (GET_CODE (operands[0]) != CONST_DOUBLE)
8970 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
8971 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
8974 [(set_attr "type" "unknown")
8975 (set_attr "mode" "SF")
8976 (set_attr "length" "8")])
8978 (define_insn "consttable_df"
8979 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")]
8980 UNSPEC_CONSTTABLE_DF)]
8985 if (GET_CODE (operands[0]) != CONST_DOUBLE)
8987 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
8988 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
8991 [(set_attr "type" "unknown")
8992 (set_attr "mode" "DF")
8993 (set_attr "length" "16")])
8995 (define_insn "align_2"
8996 [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_2)]
8999 [(set_attr "type" "unknown")
9000 (set_attr "mode" "HI")
9001 (set_attr "length" "8")])
9003 (define_insn "align_4"
9004 [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_4)]
9007 [(set_attr "type" "unknown")
9008 (set_attr "mode" "SI")
9009 (set_attr "length" "8")])
9011 (define_insn "align_8"
9012 [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_8)]
9015 [(set_attr "type" "unknown")
9016 (set_attr "mode" "DI")
9017 (set_attr "length" "12")])
9020 ;; ....................
9024 ;; ....................
9027 ;; On the mips16, reload will sometimes decide that a pseudo register
9028 ;; should go into $24, and then later on have to reload that register.
9029 ;; When that happens, we get a load of a general register followed by
9030 ;; a move from the general register to $24 followed by a branch.
9031 ;; These peepholes catch the common case, and fix it to just use the
9032 ;; general register for the branch.
9035 [(set (match_operand:SI 0 "register_operand" "=t")
9036 (match_operand:SI 1 "register_operand" "d"))
9038 (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
9040 (match_operand 3 "pc_or_label_operand" "")
9041 (match_operand 4 "pc_or_label_operand" "")))]
9043 && GET_CODE (operands[0]) == REG
9044 && REGNO (operands[0]) == 24
9045 && dead_or_set_p (insn, operands[0])
9046 && GET_CODE (operands[1]) == REG
9047 && M16_REG_P (REGNO (operands[1]))"
9049 if (operands[3] != pc_rtx)
9050 return "b%C2z\t%1,%3";
9052 return "b%N2z\t%1,%4";
9054 [(set_attr "type" "branch")
9055 (set_attr "mode" "none")
9056 (set_attr "length" "8")])
9059 [(set (match_operand:DI 0 "register_operand" "=t")
9060 (match_operand:DI 1 "register_operand" "d"))
9062 (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
9064 (match_operand 3 "pc_or_label_operand" "")
9065 (match_operand 4 "pc_or_label_operand" "")))]
9066 "TARGET_MIPS16 && TARGET_64BIT
9067 && GET_CODE (operands[0]) == REG
9068 && REGNO (operands[0]) == 24
9069 && dead_or_set_p (insn, operands[0])
9070 && GET_CODE (operands[1]) == REG
9071 && M16_REG_P (REGNO (operands[1]))"
9073 if (operands[3] != pc_rtx)
9074 return "b%C2z\t%1,%3";
9076 return "b%N2z\t%1,%4";
9078 [(set_attr "type" "branch")
9079 (set_attr "mode" "none")
9080 (set_attr "length" "8")])
9082 ;; We can also have the reverse reload: reload will spill $24 into
9083 ;; another register, and then do a branch on that register when it
9084 ;; could have just stuck with $24.
9087 [(set (match_operand:SI 0 "register_operand" "=d")
9088 (match_operand:SI 1 "register_operand" "t"))
9090 (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
9092 (match_operand 3 "pc_or_label_operand" "")
9093 (match_operand 4 "pc_or_label_operand" "")))]
9095 && GET_CODE (operands[1]) == REG
9096 && REGNO (operands[1]) == 24
9097 && GET_CODE (operands[0]) == REG
9098 && M16_REG_P (REGNO (operands[0]))
9099 && dead_or_set_p (insn, operands[0])"
9101 if (operands[3] != pc_rtx)
9102 return "bt%C2z\t%3";
9104 return "bt%N2z\t%4";
9106 [(set_attr "type" "branch")
9107 (set_attr "mode" "none")
9108 (set_attr "length" "8")])
9111 [(set (match_operand:DI 0 "register_operand" "=d")
9112 (match_operand:DI 1 "register_operand" "t"))
9114 (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
9116 (match_operand 3 "pc_or_label_operand" "")
9117 (match_operand 4 "pc_or_label_operand" "")))]
9118 "TARGET_MIPS16 && TARGET_64BIT
9119 && GET_CODE (operands[1]) == REG
9120 && REGNO (operands[1]) == 24
9121 && GET_CODE (operands[0]) == REG
9122 && M16_REG_P (REGNO (operands[0]))
9123 && dead_or_set_p (insn, operands[0])"
9125 if (operands[3] != pc_rtx)
9126 return "bt%C2z\t%3";
9128 return "bt%N2z\t%4";
9130 [(set_attr "type" "branch")
9131 (set_attr "mode" "none")
9132 (set_attr "length" "8")])
9135 [(match_operand 0 "small_data_pattern" "")]
9138 { operands[0] = mips_rewrite_small_data (operands[0]); })