1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 ;; Free Software Foundation, Inc.
6 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
7 ;; Changes by Michael Meissner, meissner@osf.org
8 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 ;; Brendan Eich, brendan@microunity.com.
11 ;; This file is part of GCC.
13 ;; GCC is free software; you can redistribute it and/or modify
14 ;; it under the terms of the GNU General Public License as published by
15 ;; the Free Software Foundation; either version 3, or (at your option)
18 ;; GCC is distributed in the hope that it will be useful,
19 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
20 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 ;; GNU General Public License for more details.
23 ;; You should have received a copy of the GNU General Public License
24 ;; along with GCC; see the file COPYING3. If not see
25 ;; <http://www.gnu.org/licenses/>.
27 (define_enum "processor" [
70 (define_c_enum "unspec" [
71 ;; Unaligned accesses.
77 ;; Floating-point moves.
93 UNSPEC_POTENTIAL_CPRESTORE
98 UNSPEC_SET_GOT_VERSION
99 UNSPEC_UPDATE_GOT_VERSION
101 ;; Symbolic accesses.
106 UNSPEC_UNSHIFTED_HIGH
108 ;; MIPS16 constant pools.
110 UNSPEC_CONSTTABLE_INT
111 UNSPEC_CONSTTABLE_FLOAT
113 ;; Blockage and synchronisation.
120 ;; Cache manipulation.
122 UNSPEC_R10K_CACHE_BARRIER
124 ;; Interrupt handling.
132 ;; Used in a call expression in place of args_size. It's present for PIC
133 ;; indirect calls where it contains args_size and the function symbol.
138 [(TLS_GET_TP_REGNUM 3)
139 (PIC_FUNCTION_ADDR_REGNUM 25)
140 (RETURN_ADDR_REGNUM 31)
141 (CPRESTORE_SLOT_REGNUM 76)
142 (GOT_VERSION_REGNUM 79)
144 ;; PIC long branch sequences are never longer than 100 bytes.
145 (MAX_PIC_BRANCH_LENGTH 100)
149 (include "predicates.md")
150 (include "constraints.md")
152 ;; ....................
156 ;; ....................
158 (define_attr "got" "unset,xgot_high,load"
159 (const_string "unset"))
161 ;; For jal instructions, this attribute is DIRECT when the target address
162 ;; is symbolic and INDIRECT when it is a register.
163 (define_attr "jal" "unset,direct,indirect"
164 (const_string "unset"))
166 ;; This attribute is YES if the instruction is a jal macro (not a
167 ;; real jal instruction).
169 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
170 ;; an instruction to restore $gp. Direct jals are also macros for
171 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
173 (define_attr "jal_macro" "no,yes"
174 (cond [(eq_attr "jal" "direct")
175 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
176 ? JAL_MACRO_YES : JAL_MACRO_NO)")
177 (eq_attr "jal" "indirect")
178 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
179 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
180 (const_string "no")))
182 ;; Classification of moves, extensions and truncations. Most values
183 ;; are as for "type" (see below) but there are also the following
184 ;; move-specific values:
186 ;; constN move an N-constraint integer into a MIPS16 register
187 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
188 ;; to produce a sign-extended DEST, even if SRC is not
189 ;; properly sign-extended
190 ;; ext_ins EXT, DEXT, INS or DINS instruction
191 ;; andi a single ANDI instruction
192 ;; loadpool move a constant into a MIPS16 register by loading it
194 ;; shift_shift a shift left followed by a shift right
195 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
197 ;; This attribute is used to determine the instruction's length and
198 ;; scheduling type. For doubleword moves, the attribute always describes
199 ;; the split instructions; in some cases, it is more appropriate for the
200 ;; scheduling type to be "multi" instead.
201 (define_attr "move_type"
202 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
203 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
204 shift_shift,lui_movf"
205 (const_string "unknown"))
207 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
208 (const_string "unknown"))
210 ;; Main data type used by the insn
211 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
212 (const_string "unknown"))
214 ;; True if the main data type is twice the size of a word.
215 (define_attr "dword_mode" "no,yes"
216 (cond [(and (eq_attr "mode" "DI,DF")
217 (not (match_test "TARGET_64BIT")))
220 (and (eq_attr "mode" "TI,TF")
221 (match_test "TARGET_64BIT"))
222 (const_string "yes")]
223 (const_string "no")))
225 ;; Classification of each insn.
226 ;; branch conditional branch
227 ;; jump unconditional jump
228 ;; call unconditional call
229 ;; load load instruction(s)
230 ;; fpload floating point load
231 ;; fpidxload floating point indexed load
232 ;; store store instruction(s)
233 ;; fpstore floating point store
234 ;; fpidxstore floating point indexed store
235 ;; prefetch memory prefetch (register + offset)
236 ;; prefetchx memory indexed prefetch (register + register)
237 ;; condmove conditional moves
238 ;; mtc transfer to coprocessor
239 ;; mfc transfer from coprocessor
240 ;; mthilo transfer to hi/lo registers
241 ;; mfhilo transfer from hi/lo registers
242 ;; const load constant
243 ;; arith integer arithmetic instructions
244 ;; logical integer logical instructions
245 ;; shift integer shift instructions
246 ;; slt set less than instructions
247 ;; signext sign extend instructions
248 ;; clz the clz and clo instructions
249 ;; pop the pop instruction
250 ;; trap trap if instructions
251 ;; imul integer multiply 2 operands
252 ;; imul3 integer multiply 3 operands
253 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
254 ;; imadd integer multiply-add
255 ;; idiv integer divide 2 operands
256 ;; idiv3 integer divide 3 operands
257 ;; move integer register move ({,D}ADD{,U} with rt = 0)
258 ;; fmove floating point register move
259 ;; fadd floating point add/subtract
260 ;; fmul floating point multiply
261 ;; fmadd floating point multiply-add
262 ;; fdiv floating point divide
263 ;; frdiv floating point reciprocal divide
264 ;; frdiv1 floating point reciprocal divide step 1
265 ;; frdiv2 floating point reciprocal divide step 2
266 ;; fabs floating point absolute value
267 ;; fneg floating point negation
268 ;; fcmp floating point compare
269 ;; fcvt floating point convert
270 ;; fsqrt floating point square root
271 ;; frsqrt floating point reciprocal square root
272 ;; frsqrt1 floating point reciprocal square root step1
273 ;; frsqrt2 floating point reciprocal square root step2
274 ;; multi multiword sequence (or user asm statements)
276 ;; ghost an instruction that produces no real code
278 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
279 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
280 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
281 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
282 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
283 (cond [(eq_attr "jal" "!unset") (const_string "call")
284 (eq_attr "got" "load") (const_string "load")
286 (eq_attr "alu_type" "add,sub") (const_string "arith")
288 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
290 ;; If a doubleword move uses these expensive instructions,
291 ;; it is usually better to schedule them in the same way
292 ;; as the singleword form, rather than as "multi".
293 (eq_attr "move_type" "load") (const_string "load")
294 (eq_attr "move_type" "fpload") (const_string "fpload")
295 (eq_attr "move_type" "store") (const_string "store")
296 (eq_attr "move_type" "fpstore") (const_string "fpstore")
297 (eq_attr "move_type" "mtc") (const_string "mtc")
298 (eq_attr "move_type" "mfc") (const_string "mfc")
299 (eq_attr "move_type" "mthilo") (const_string "mthilo")
300 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
302 ;; These types of move are always single insns.
303 (eq_attr "move_type" "fmove") (const_string "fmove")
304 (eq_attr "move_type" "loadpool") (const_string "load")
305 (eq_attr "move_type" "signext") (const_string "signext")
306 (eq_attr "move_type" "ext_ins") (const_string "arith")
307 (eq_attr "move_type" "arith") (const_string "arith")
308 (eq_attr "move_type" "logical") (const_string "logical")
309 (eq_attr "move_type" "sll0") (const_string "shift")
310 (eq_attr "move_type" "andi") (const_string "logical")
312 ;; These types of move are always split.
313 (eq_attr "move_type" "constN,shift_shift")
314 (const_string "multi")
316 ;; These types of move are split for doubleword modes only.
317 (and (eq_attr "move_type" "move,const")
318 (eq_attr "dword_mode" "yes"))
319 (const_string "multi")
320 (eq_attr "move_type" "move") (const_string "move")
321 (eq_attr "move_type" "const") (const_string "const")]
322 ;; We classify "lui_movf" as "unknown" rather than "multi"
323 ;; because we don't split it. FIXME: we should split instead.
324 (const_string "unknown")))
326 ;; Mode for conversion types (fcvt)
327 ;; I2S integer to float single (SI/DI to SF)
328 ;; I2D integer to float double (SI/DI to DF)
329 ;; S2I float to integer (SF to SI/DI)
330 ;; D2I float to integer (DF to SI/DI)
331 ;; D2S double to float single
332 ;; S2D float single to double
334 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
335 (const_string "unknown"))
337 ;; Is this an extended instruction in mips16 mode?
338 (define_attr "extended_mips16" "no,yes"
339 (if_then_else (ior (eq_attr "move_type" "sll0")
340 (eq_attr "type" "branch")
341 (eq_attr "jal" "direct"))
343 (const_string "no")))
345 ;; Attributes describing a sync loop. These loops have the form:
347 ;; if (RELEASE_BARRIER == YES) sync
349 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
350 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
351 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
352 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
353 ;; $AT |= $TMP1 | $TMP3
354 ;; if (!commit (*MEM = $AT)) goto 1.
355 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
359 ;; where "$" values are temporaries and where the other values are
360 ;; specified by the attributes below. Values are specified as operand
361 ;; numbers and insns are specified as enums. If no operand number is
362 ;; specified, the following values are used instead:
366 ;; - INCLUSIVE_MASK: -1
367 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
368 ;; - EXCLUSIVE_MASK: 0
370 ;; MEM and INSN1_OP2 are required.
372 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
373 ;; but the gen* programs don't yet support that.
374 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
375 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
376 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
377 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
378 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
379 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
380 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
381 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
382 (const_string "move"))
383 (define_attr "sync_insn2" "nop,and,xor,not"
384 (const_string "nop"))
385 (define_attr "sync_release_barrier" "yes,no"
386 (const_string "yes"))
388 ;; Length of instruction in bytes.
389 (define_attr "length" ""
390 (cond [(and (eq_attr "extended_mips16" "yes")
391 (match_test "TARGET_MIPS16"))
394 ;; Direct branch instructions have a range of [-0x20000,0x1fffc],
395 ;; relative to the address of the delay slot. If a branch is
396 ;; outside this range, we have a choice of two sequences.
397 ;; For PIC, an out-of-range branch like:
402 ;; becomes the equivalent of:
411 ;; The non-PIC case is similar except that we use a direct
412 ;; jump instead of an la/jr pair. Since the target of this
413 ;; jump is an absolute 28-bit bit address (the other bits
414 ;; coming from the address of the delay slot) this form cannot
415 ;; cross a 256MB boundary. We could provide the option of
416 ;; using la/jr in this case too, but we do not do so at
419 ;; Note that this value does not account for the delay slot
420 ;; instruction, whose length is added separately. If the RTL
421 ;; pattern has no explicit delay slot, mips_adjust_insn_length
422 ;; will add the length of the implicit nop. The values for
423 ;; forward and backward branches will be different as well.
424 (eq_attr "type" "branch")
425 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 131064))
426 (le (minus (pc) (match_dup 0)) (const_int 131068)))
429 ;; The non-PIC case: branch, first delay slot, and J.
430 (match_test "TARGET_ABSOLUTE_JUMPS")
433 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
434 ;; mips_adjust_insn_length substitutes the correct length.
436 ;; Note that we can't simply use (symbol_ref ...) here
437 ;; because genattrtab needs to know the maximum length
439 (const_int MAX_PIC_BRANCH_LENGTH))
441 ;; "Ghost" instructions occupy no space.
442 (eq_attr "type" "ghost")
445 (eq_attr "got" "load")
446 (if_then_else (match_test "TARGET_MIPS16")
449 (eq_attr "got" "xgot_high")
452 ;; In general, constant-pool loads are extended instructions.
453 (eq_attr "move_type" "loadpool")
456 ;; LUI_MOVFs are decomposed into two separate instructions.
457 (eq_attr "move_type" "lui_movf")
460 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
461 ;; They are extended instructions on MIPS16 targets.
462 (eq_attr "move_type" "shift_shift")
463 (if_then_else (match_test "TARGET_MIPS16")
467 ;; Check for doubleword moves that are decomposed into two
469 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
470 (eq_attr "dword_mode" "yes"))
473 ;; Doubleword CONST{,N} moves are split into two word
475 (and (eq_attr "move_type" "const,constN")
476 (eq_attr "dword_mode" "yes"))
477 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
479 ;; Otherwise, constants, loads and stores are handled by external
481 (eq_attr "move_type" "const,constN")
482 (symbol_ref "mips_const_insns (operands[1]) * 4")
483 (eq_attr "move_type" "load,fpload")
484 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
485 (eq_attr "move_type" "store,fpstore")
486 (cond [(not (match_test "TARGET_FIX_24K"))
487 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")]
488 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4 + 4"))
490 ;; In the worst case, a call macro will take 8 instructions:
492 ;; lui $25,%call_hi(FOO)
494 ;; lw $25,%call_lo(FOO)($25)
500 (eq_attr "jal_macro" "yes")
503 ;; Various VR4120 errata require a nop to be inserted after a macc
504 ;; instruction. The assembler does this for us, so account for
505 ;; the worst-case length here.
506 (and (eq_attr "type" "imadd")
507 (match_test "TARGET_FIX_VR4120"))
510 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
511 ;; the result of the second one is missed. The assembler should work
512 ;; around this by inserting a nop after the first dmult.
513 (and (eq_attr "type" "imul,imul3")
514 (and (eq_attr "mode" "DI")
515 (match_test "TARGET_FIX_VR4120")))
518 (eq_attr "type" "idiv,idiv3")
519 (symbol_ref "mips_idiv_insns () * 4")
521 (not (eq_attr "sync_mem" "none"))
522 (symbol_ref "mips_sync_loop_insns (insn, operands) * 4")
525 ;; Attribute describing the processor.
526 (define_enum_attr "cpu" "processor"
527 (const (symbol_ref "mips_tune")))
529 ;; The type of hardware hazard associated with this instruction.
530 ;; DELAY means that the next instruction cannot read the result
531 ;; of this one. HILO means that the next two instructions cannot
532 ;; write to HI or LO.
533 (define_attr "hazard" "none,delay,hilo"
534 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
535 (match_test "ISA_HAS_LOAD_DELAY"))
536 (const_string "delay")
538 (and (eq_attr "type" "mfc,mtc")
539 (match_test "ISA_HAS_XFER_DELAY"))
540 (const_string "delay")
542 (and (eq_attr "type" "fcmp")
543 (match_test "ISA_HAS_FCMP_DELAY"))
544 (const_string "delay")
546 ;; The r4000 multiplication patterns include an mflo instruction.
547 (and (eq_attr "type" "imul")
548 (match_test "TARGET_FIX_R4000"))
549 (const_string "hilo")
551 (and (eq_attr "type" "mfhilo")
552 (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
553 (const_string "hilo")]
554 (const_string "none")))
556 ;; Is it a single instruction?
557 (define_attr "single_insn" "no,yes"
558 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
559 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
561 ;; Can the instruction be put into a delay slot?
562 (define_attr "can_delay" "no,yes"
563 (if_then_else (and (eq_attr "type" "!branch,call,jump")
564 (and (eq_attr "hazard" "none")
565 (eq_attr "single_insn" "yes")))
567 (const_string "no")))
569 ;; Attribute defining whether or not we can use the branch-likely
571 (define_attr "branch_likely" "no,yes"
572 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
574 (const_string "no")))
576 ;; True if an instruction might assign to hi or lo when reloaded.
577 ;; This is used by the TUNE_MACC_CHAINS code.
578 (define_attr "may_clobber_hilo" "no,yes"
579 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
581 (const_string "no")))
583 ;; Describe a user's asm statement.
584 (define_asm_attributes
585 [(set_attr "type" "multi")
586 (set_attr "can_delay" "no")])
588 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
589 ;; from the same template.
590 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
592 ;; A copy of GPR that can be used when a pattern has two independent
594 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
596 ;; This mode iterator allows :HILO to be used as the mode of the
597 ;; concatenated HI and LO registers.
598 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
600 ;; This mode iterator allows :P to be used for patterns that operate on
601 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
602 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
604 ;; This mode iterator allows :MOVECC to be used anywhere that a
605 ;; conditional-move-type condition is needed.
606 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
607 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
609 ;; 32-bit integer moves for which we provide move patterns.
610 (define_mode_iterator IMOVE32
619 (V4UQQ "TARGET_DSP")])
621 ;; 64-bit modes for which we provide move patterns.
622 (define_mode_iterator MOVE64
624 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
625 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
626 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
627 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
629 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
630 (define_mode_iterator MOVE128 [TI TF])
632 ;; This mode iterator allows the QI and HI extension patterns to be
633 ;; defined from the same template.
634 (define_mode_iterator SHORT [QI HI])
636 ;; Likewise the 64-bit truncate-and-shift patterns.
637 (define_mode_iterator SUBDI [QI HI SI])
639 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
640 ;; floating-point mode is allowed.
641 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
642 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
643 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
645 ;; Like ANYF, but only applies to scalar modes.
646 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
647 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
649 ;; A floating-point mode for which moves involving FPRs may need to be split.
650 (define_mode_iterator SPLITF
651 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
652 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
653 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
654 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
655 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
656 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
657 (TF "TARGET_64BIT && TARGET_FLOAT64")])
659 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
660 ;; 32-bit version and "dsubu" in the 64-bit version.
661 (define_mode_attr d [(SI "") (DI "d")
662 (QQ "") (HQ "") (SQ "") (DQ "d")
663 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
664 (HA "") (SA "") (DA "d")
665 (UHA "") (USA "") (UDA "d")])
667 ;; Same as d but upper-case.
668 (define_mode_attr D [(SI "") (DI "D")
669 (QQ "") (HQ "") (SQ "") (DQ "D")
670 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
671 (HA "") (SA "") (DA "D")
672 (UHA "") (USA "") (UDA "D")])
674 ;; This attribute gives the length suffix for a load or store instruction.
675 ;; The same suffixes work for zero and sign extensions.
676 (define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
677 (define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
679 ;; This attributes gives the mode mask of a SHORT.
680 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
682 ;; Mode attributes for GPR loads.
683 (define_mode_attr load [(SI "lw") (DI "ld")])
684 ;; Instruction names for stores.
685 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
687 ;; Similarly for MIPS IV indexed FPR loads and stores.
688 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
689 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
691 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
692 ;; are different. Some forms of unextended addiu have an 8-bit immediate
693 ;; field but the equivalent daddiu has only a 5-bit field.
694 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
696 ;; This attribute gives the best constraint to use for registers of
698 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
700 ;; This attribute gives the format suffix for floating-point operations.
701 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
703 ;; This attribute gives the upper-case mode name for one unit of a
704 ;; floating-point mode.
705 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
707 ;; This attribute gives the integer mode that has the same size as a
709 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
710 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
711 (HA "HI") (SA "SI") (DA "DI")
712 (UHA "HI") (USA "SI") (UDA "DI")
713 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
714 (V2HQ "SI") (V2HA "SI")])
716 ;; This attribute gives the integer mode that has half the size of
717 ;; the controlling mode.
718 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
719 (V2SI "SI") (V4HI "SI") (V8QI "SI")
722 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
724 ;; In certain cases, div.s and div.ps may have a rounding error
725 ;; and/or wrong inexact flag.
727 ;; Therefore, we only allow div.s if not working around SB-1 rev2
728 ;; errata or if a slight loss of precision is OK.
729 (define_mode_attr divide_condition
730 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
731 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
733 ;; This attribute gives the conditions under which SQRT.fmt instructions
735 (define_mode_attr sqrt_condition
736 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
738 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
739 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
740 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
741 ;; so for safety's sake, we apply this restriction to all targets.
742 (define_mode_attr recip_condition
744 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
745 (V2SF "TARGET_SB1")])
747 ;; This code iterator allows signed and unsigned widening multiplications
748 ;; to use the same template.
749 (define_code_iterator any_extend [sign_extend zero_extend])
751 ;; This code iterator allows the two right shift instructions to be
752 ;; generated from the same template.
753 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
755 ;; This code iterator allows the three shift instructions to be generated
756 ;; from the same template.
757 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
759 ;; This code iterator allows unsigned and signed division to be generated
760 ;; from the same template.
761 (define_code_iterator any_div [div udiv])
763 ;; This code iterator allows unsigned and signed modulus to be generated
764 ;; from the same template.
765 (define_code_iterator any_mod [mod umod])
767 ;; This code iterator allows all native floating-point comparisons to be
768 ;; generated from the same template.
769 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
771 ;; This code iterator is used for comparisons that can be implemented
772 ;; by swapping the operands.
773 (define_code_iterator swapped_fcond [ge gt unge ungt])
775 ;; Equality operators.
776 (define_code_iterator equality_op [eq ne])
778 ;; These code iterators allow the signed and unsigned scc operations to use
779 ;; the same template.
780 (define_code_iterator any_gt [gt gtu])
781 (define_code_iterator any_ge [ge geu])
782 (define_code_iterator any_lt [lt ltu])
783 (define_code_iterator any_le [le leu])
785 (define_code_iterator any_return [return simple_return])
787 ;; <u> expands to an empty string when doing a signed operation and
788 ;; "u" when doing an unsigned operation.
789 (define_code_attr u [(sign_extend "") (zero_extend "u")
797 ;; <U> is like <u> except uppercase.
798 (define_code_attr U [(sign_extend "") (zero_extend "U")])
800 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
801 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
803 ;; <optab> expands to the name of the optab for a particular code.
804 (define_code_attr optab [(ashift "ashl")
813 (simple_return "simple_return")])
815 ;; <insn> expands to the name of the insn that implements a particular code.
816 (define_code_attr insn [(ashift "sll")
825 ;; <immediate_insn> expands to the name of the insn that implements
826 ;; a particular code to operate on immediate values.
827 (define_code_attr immediate_insn [(ior "ori")
831 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
832 (define_code_attr fcond [(unordered "un")
840 ;; Similar, but for swapped conditions.
841 (define_code_attr swapped_fcond [(ge "le")
846 ;; The value of the bit when the branch is taken for branch_bit patterns.
847 ;; Comparison is always against zero so this depends on the operator.
848 (define_code_attr bbv [(eq "0") (ne "1")])
850 ;; This is the inverse value of bbv.
851 (define_code_attr bbinv [(eq "1") (ne "0")])
853 ;; .........................
855 ;; Branch, call and jump delay slots
857 ;; .........................
859 (define_delay (and (eq_attr "type" "branch")
860 (not (match_test "TARGET_MIPS16"))
861 (eq_attr "branch_likely" "yes"))
862 [(eq_attr "can_delay" "yes")
864 (eq_attr "can_delay" "yes")])
866 ;; Branches that don't have likely variants do not annul on false.
867 (define_delay (and (eq_attr "type" "branch")
868 (not (match_test "TARGET_MIPS16"))
869 (eq_attr "branch_likely" "no"))
870 [(eq_attr "can_delay" "yes")
874 (define_delay (eq_attr "type" "jump")
875 [(eq_attr "can_delay" "yes")
879 (define_delay (and (eq_attr "type" "call")
880 (eq_attr "jal_macro" "no"))
881 [(eq_attr "can_delay" "yes")
885 ;; Pipeline descriptions.
887 ;; generic.md provides a fallback for processors without a specific
888 ;; pipeline description. It is derived from the old define_function_unit
889 ;; version and uses the "alu" and "imuldiv" units declared below.
891 ;; Some of the processor-specific files are also derived from old
892 ;; define_function_unit descriptions and simply override the parts of
893 ;; generic.md that don't apply. The other processor-specific files
894 ;; are self-contained.
895 (define_automaton "alu,imuldiv")
897 (define_cpu_unit "alu" "alu")
898 (define_cpu_unit "imuldiv" "imuldiv")
900 ;; Ghost instructions produce no real code and introduce no hazards.
901 ;; They exist purely to express an effect on dataflow.
902 (define_insn_reservation "ghost" 0
903 (eq_attr "type" "ghost")
924 (include "loongson2ef.md")
925 (include "loongson3a.md")
926 (include "octeon.md")
930 (include "generic.md")
933 ;; ....................
937 ;; ....................
941 [(trap_if (const_int 1) (const_int 0))]
944 if (ISA_HAS_COND_TRAP)
946 else if (TARGET_MIPS16)
951 [(set_attr "type" "trap")])
953 (define_expand "ctrap<mode>4"
954 [(trap_if (match_operator 0 "comparison_operator"
955 [(match_operand:GPR 1 "reg_or_0_operand")
956 (match_operand:GPR 2 "arith_operand")])
957 (match_operand 3 "const_0_operand"))]
960 mips_expand_conditional_trap (operands[0]);
964 (define_insn "*conditional_trap<mode>"
965 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
966 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
967 (match_operand:GPR 2 "arith_operand" "dI")])
971 [(set_attr "type" "trap")])
974 ;; ....................
978 ;; ....................
981 (define_insn "add<mode>3"
982 [(set (match_operand:ANYF 0 "register_operand" "=f")
983 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
984 (match_operand:ANYF 2 "register_operand" "f")))]
986 "add.<fmt>\t%0,%1,%2"
987 [(set_attr "type" "fadd")
988 (set_attr "mode" "<UNITMODE>")])
990 (define_expand "add<mode>3"
991 [(set (match_operand:GPR 0 "register_operand")
992 (plus:GPR (match_operand:GPR 1 "register_operand")
993 (match_operand:GPR 2 "arith_operand")))]
996 (define_insn "*add<mode>3"
997 [(set (match_operand:GPR 0 "register_operand" "=d,d")
998 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
999 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1004 [(set_attr "alu_type" "add")
1005 (set_attr "mode" "<MODE>")])
1007 (define_insn "*add<mode>3_mips16"
1008 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1009 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1010 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1018 [(set_attr "alu_type" "add")
1019 (set_attr "mode" "<MODE>")
1020 (set_attr_alternative "length"
1021 [(if_then_else (match_operand 2 "m16_simm8_8")
1024 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1027 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1030 (if_then_else (match_operand 2 "m16_simm4_1")
1035 ;; On the mips16, we can sometimes split an add of a constant which is
1036 ;; a 4 byte instruction into two adds which are both 2 byte
1037 ;; instructions. There are two cases: one where we are adding a
1038 ;; constant plus a register to another register, and one where we are
1039 ;; simply adding a constant to a register.
1042 [(set (match_operand:SI 0 "d_operand")
1043 (plus:SI (match_dup 0)
1044 (match_operand:SI 1 "const_int_operand")))]
1045 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1046 && ((INTVAL (operands[1]) > 0x7f
1047 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1048 || (INTVAL (operands[1]) < - 0x80
1049 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1050 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1051 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1053 HOST_WIDE_INT val = INTVAL (operands[1]);
1057 operands[1] = GEN_INT (0x7f);
1058 operands[2] = GEN_INT (val - 0x7f);
1062 operands[1] = GEN_INT (- 0x80);
1063 operands[2] = GEN_INT (val + 0x80);
1068 [(set (match_operand:SI 0 "d_operand")
1069 (plus:SI (match_operand:SI 1 "d_operand")
1070 (match_operand:SI 2 "const_int_operand")))]
1071 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1072 && REGNO (operands[0]) != REGNO (operands[1])
1073 && ((INTVAL (operands[2]) > 0x7
1074 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1075 || (INTVAL (operands[2]) < - 0x8
1076 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1077 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1078 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1080 HOST_WIDE_INT val = INTVAL (operands[2]);
1084 operands[2] = GEN_INT (0x7);
1085 operands[3] = GEN_INT (val - 0x7);
1089 operands[2] = GEN_INT (- 0x8);
1090 operands[3] = GEN_INT (val + 0x8);
1095 [(set (match_operand:DI 0 "d_operand")
1096 (plus:DI (match_dup 0)
1097 (match_operand:DI 1 "const_int_operand")))]
1098 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1099 && ((INTVAL (operands[1]) > 0xf
1100 && INTVAL (operands[1]) <= 0xf + 0xf)
1101 || (INTVAL (operands[1]) < - 0x10
1102 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1103 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1104 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1106 HOST_WIDE_INT val = INTVAL (operands[1]);
1110 operands[1] = GEN_INT (0xf);
1111 operands[2] = GEN_INT (val - 0xf);
1115 operands[1] = GEN_INT (- 0x10);
1116 operands[2] = GEN_INT (val + 0x10);
1121 [(set (match_operand:DI 0 "d_operand")
1122 (plus:DI (match_operand:DI 1 "d_operand")
1123 (match_operand:DI 2 "const_int_operand")))]
1124 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1125 && REGNO (operands[0]) != REGNO (operands[1])
1126 && ((INTVAL (operands[2]) > 0x7
1127 && INTVAL (operands[2]) <= 0x7 + 0xf)
1128 || (INTVAL (operands[2]) < - 0x8
1129 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1130 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1131 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1133 HOST_WIDE_INT val = INTVAL (operands[2]);
1137 operands[2] = GEN_INT (0x7);
1138 operands[3] = GEN_INT (val - 0x7);
1142 operands[2] = GEN_INT (- 0x8);
1143 operands[3] = GEN_INT (val + 0x8);
1147 (define_insn "*addsi3_extended"
1148 [(set (match_operand:DI 0 "register_operand" "=d,d")
1150 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1151 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1152 "TARGET_64BIT && !TARGET_MIPS16"
1156 [(set_attr "alu_type" "add")
1157 (set_attr "mode" "SI")])
1159 ;; Split this insn so that the addiu splitters can have a crack at it.
1160 ;; Use a conservative length estimate until the split.
1161 (define_insn_and_split "*addsi3_extended_mips16"
1162 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1164 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1165 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1166 "TARGET_64BIT && TARGET_MIPS16"
1168 "&& reload_completed"
1169 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1170 { operands[3] = gen_lowpart (SImode, operands[0]); }
1171 [(set_attr "alu_type" "add")
1172 (set_attr "mode" "SI")
1173 (set_attr "extended_mips16" "yes")])
1175 ;; Combiner patterns for unsigned byte-add.
1177 (define_insn "*baddu_si_eb"
1178 [(set (match_operand:SI 0 "register_operand" "=d")
1181 (plus:SI (match_operand:SI 1 "register_operand" "d")
1182 (match_operand:SI 2 "register_operand" "d")) 3)))]
1183 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1185 [(set_attr "alu_type" "add")])
1187 (define_insn "*baddu_si_el"
1188 [(set (match_operand:SI 0 "register_operand" "=d")
1191 (plus:SI (match_operand:SI 1 "register_operand" "d")
1192 (match_operand:SI 2 "register_operand" "d")) 0)))]
1193 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1195 [(set_attr "alu_type" "add")])
1197 (define_insn "*baddu_di<mode>"
1198 [(set (match_operand:GPR 0 "register_operand" "=d")
1201 (plus:DI (match_operand:DI 1 "register_operand" "d")
1202 (match_operand:DI 2 "register_operand" "d")))))]
1203 "ISA_HAS_BADDU && TARGET_64BIT"
1205 [(set_attr "alu_type" "add")])
1208 ;; ....................
1212 ;; ....................
1215 (define_insn "sub<mode>3"
1216 [(set (match_operand:ANYF 0 "register_operand" "=f")
1217 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1218 (match_operand:ANYF 2 "register_operand" "f")))]
1220 "sub.<fmt>\t%0,%1,%2"
1221 [(set_attr "type" "fadd")
1222 (set_attr "mode" "<UNITMODE>")])
1224 (define_insn "sub<mode>3"
1225 [(set (match_operand:GPR 0 "register_operand" "=d")
1226 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1227 (match_operand:GPR 2 "register_operand" "d")))]
1230 [(set_attr "alu_type" "sub")
1231 (set_attr "mode" "<MODE>")])
1233 (define_insn "*subsi3_extended"
1234 [(set (match_operand:DI 0 "register_operand" "=d")
1236 (minus:SI (match_operand:SI 1 "register_operand" "d")
1237 (match_operand:SI 2 "register_operand" "d"))))]
1240 [(set_attr "alu_type" "sub")
1241 (set_attr "mode" "DI")])
1244 ;; ....................
1248 ;; ....................
1251 (define_expand "mul<mode>3"
1252 [(set (match_operand:SCALARF 0 "register_operand")
1253 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1254 (match_operand:SCALARF 2 "register_operand")))]
1258 (define_insn "*mul<mode>3"
1259 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1260 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1261 (match_operand:SCALARF 2 "register_operand" "f")))]
1262 "!TARGET_4300_MUL_FIX"
1263 "mul.<fmt>\t%0,%1,%2"
1264 [(set_attr "type" "fmul")
1265 (set_attr "mode" "<MODE>")])
1267 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1268 ;; operands may corrupt immediately following multiplies. This is a
1269 ;; simple fix to insert NOPs.
1271 (define_insn "*mul<mode>3_r4300"
1272 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1273 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1274 (match_operand:SCALARF 2 "register_operand" "f")))]
1275 "TARGET_4300_MUL_FIX"
1276 "mul.<fmt>\t%0,%1,%2\;nop"
1277 [(set_attr "type" "fmul")
1278 (set_attr "mode" "<MODE>")
1279 (set_attr "length" "8")])
1281 (define_insn "mulv2sf3"
1282 [(set (match_operand:V2SF 0 "register_operand" "=f")
1283 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1284 (match_operand:V2SF 2 "register_operand" "f")))]
1285 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1287 [(set_attr "type" "fmul")
1288 (set_attr "mode" "SF")])
1290 ;; The original R4000 has a cpu bug. If a double-word or a variable
1291 ;; shift executes while an integer multiplication is in progress, the
1292 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1293 ;; with the mult on the R4000.
1295 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1296 ;; (also valid for MIPS R4000MC processors):
1298 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1299 ;; this errata description.
1300 ;; The following code sequence causes the R4000 to incorrectly
1301 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1302 ;; instruction. If the dsra32 instruction is executed during an
1303 ;; integer multiply, the dsra32 will only shift by the amount in
1304 ;; specified in the instruction rather than the amount plus 32
1306 ;; instruction 1: mult rs,rt integer multiply
1307 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1308 ;; right arithmetic + 32
1309 ;; Workaround: A dsra32 instruction placed after an integer
1310 ;; multiply should not be one of the 11 instructions after the
1311 ;; multiply instruction."
1315 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1316 ;; the following description.
1317 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1318 ;; 64-bit versions) may produce incorrect results under the
1319 ;; following conditions:
1320 ;; 1) An integer multiply is currently executing
1321 ;; 2) These types of shift instructions are executed immediately
1322 ;; following an integer divide instruction.
1324 ;; 1) Make sure no integer multiply is running wihen these
1325 ;; instruction are executed. If this cannot be predicted at
1326 ;; compile time, then insert a "mfhi" to R0 instruction
1327 ;; immediately after the integer multiply instruction. This
1328 ;; will cause the integer multiply to complete before the shift
1330 ;; 2) Separate integer divide and these two classes of shift
1331 ;; instructions by another instruction or a noop."
1333 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1336 (define_expand "mul<mode>3"
1337 [(set (match_operand:GPR 0 "register_operand")
1338 (mult:GPR (match_operand:GPR 1 "register_operand")
1339 (match_operand:GPR 2 "register_operand")))]
1344 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
1345 emit_insn (gen_mul<mode>3_mul3_loongson (operands[0], operands[1],
1347 else if (ISA_HAS_<D>MUL3)
1348 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1349 else if (TARGET_MIPS16)
1351 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
1352 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2]));
1353 emit_move_insn (operands[0], lo);
1355 else if (TARGET_FIX_R4000)
1356 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1359 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1363 (define_insn "mul<mode>3_mul3_loongson"
1364 [(set (match_operand:GPR 0 "register_operand" "=d")
1365 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1366 (match_operand:GPR 2 "register_operand" "d")))]
1367 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A"
1369 if (TARGET_LOONGSON_2EF)
1370 return "<d>multu.g\t%0,%1,%2";
1372 return "gs<d>multu\t%0,%1,%2";
1374 [(set_attr "type" "imul3nc")
1375 (set_attr "mode" "<MODE>")])
1377 (define_insn "mul<mode>3_mul3"
1378 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1379 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1380 (match_operand:GPR 2 "register_operand" "d,d")))
1381 (clobber (match_scratch:GPR 3 "=l,X"))]
1384 if (which_alternative == 1)
1385 return "<d>mult\t%1,%2";
1386 if (<MODE>mode == SImode && TARGET_MIPS3900)
1387 return "mult\t%0,%1,%2";
1388 return "<d>mul\t%0,%1,%2";
1390 [(set_attr "type" "imul3,imul")
1391 (set_attr "mode" "<MODE>")])
1393 ;; If a register gets allocated to LO, and we spill to memory, the reload
1394 ;; will include a move from LO to a GPR. Merge it into the multiplication
1395 ;; if it can set the GPR directly.
1398 ;; Operand 1: GPR (1st multiplication operand)
1399 ;; Operand 2: GPR (2nd multiplication operand)
1400 ;; Operand 3: GPR (destination)
1403 [(set (match_operand:SI 0 "lo_operand")
1404 (mult:SI (match_operand:SI 1 "d_operand")
1405 (match_operand:SI 2 "d_operand")))
1406 (clobber (scratch:SI))])
1407 (set (match_operand:SI 3 "d_operand")
1409 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1412 (mult:SI (match_dup 1)
1414 (clobber (match_dup 0))])])
1416 (define_insn "mul<mode>3_internal"
1417 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
1418 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1419 (match_operand:GPR 2 "register_operand" "d")))]
1422 [(set_attr "type" "imul")
1423 (set_attr "mode" "<MODE>")])
1425 (define_insn "mul<mode>3_r4000"
1426 [(set (match_operand:GPR 0 "register_operand" "=d")
1427 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1428 (match_operand:GPR 2 "register_operand" "d")))
1429 (clobber (match_scratch:GPR 3 "=l"))]
1431 "<d>mult\t%1,%2\;mflo\t%0"
1432 [(set_attr "type" "imul")
1433 (set_attr "mode" "<MODE>")
1434 (set_attr "length" "8")])
1436 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1437 ;; of "mult; mflo". They have the same latency, but the first form gives
1438 ;; us an extra cycle to compute the operands.
1441 ;; Operand 1: GPR (1st multiplication operand)
1442 ;; Operand 2: GPR (2nd multiplication operand)
1443 ;; Operand 3: GPR (destination)
1445 [(set (match_operand:SI 0 "lo_operand")
1446 (mult:SI (match_operand:SI 1 "d_operand")
1447 (match_operand:SI 2 "d_operand")))
1448 (set (match_operand:SI 3 "d_operand")
1450 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1455 (plus:SI (mult:SI (match_dup 1)
1459 (plus:SI (mult:SI (match_dup 1)
1463 ;; Multiply-accumulate patterns
1465 ;; This pattern is first matched by combine, which tries to use the
1466 ;; pattern wherever it can. We don't know until later whether it
1467 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1468 ;; so we need to keep both options open.
1470 ;; The second alternative has a "?" marker because it is generally
1471 ;; one instruction more costly than the first alternative. This "?"
1472 ;; marker is enough to convey the relative costs to the register
1475 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1476 ;; reloads of the other operands, even though operands 4 and 5 need no
1477 ;; copy instructions. Reload therefore thinks that the second alternative
1478 ;; is two reloads more costly than the first. We add "*?*?" to the first
1479 ;; alternative as a counterweight.
1480 (define_insn "*mul_acc_si"
1481 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1482 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1483 (match_operand:SI 2 "register_operand" "d,d"))
1484 (match_operand:SI 3 "register_operand" "0,d")))
1485 (clobber (match_scratch:SI 4 "=X,l"))
1486 (clobber (match_scratch:SI 5 "=X,&d"))]
1487 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1491 [(set_attr "type" "imadd")
1492 (set_attr "mode" "SI")
1493 (set_attr "length" "4,8")])
1495 ;; The same idea applies here. The middle alternative needs one less
1496 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1497 (define_insn "*mul_acc_si_r3900"
1498 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1499 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1500 (match_operand:SI 2 "register_operand" "d,d,d"))
1501 (match_operand:SI 3 "register_operand" "0,l,d")))
1502 (clobber (match_scratch:SI 4 "=X,3,l"))
1503 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1504 "TARGET_MIPS3900 && !TARGET_MIPS16"
1509 [(set_attr "type" "imadd")
1510 (set_attr "mode" "SI")
1511 (set_attr "length" "4,4,8")])
1513 ;; Split *mul_acc_si if both the source and destination accumulator
1516 [(set (match_operand:SI 0 "d_operand")
1517 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1518 (match_operand:SI 2 "d_operand"))
1519 (match_operand:SI 3 "d_operand")))
1520 (clobber (match_operand:SI 4 "lo_operand"))
1521 (clobber (match_operand:SI 5 "d_operand"))]
1523 [(parallel [(set (match_dup 5)
1524 (mult:SI (match_dup 1) (match_dup 2)))
1525 (clobber (match_dup 4))])
1526 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1529 (define_insn "*macc"
1530 [(set (match_operand:SI 0 "register_operand" "=l,d")
1531 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1532 (match_operand:SI 2 "register_operand" "d,d"))
1533 (match_operand:SI 3 "register_operand" "0,l")))
1534 (clobber (match_scratch:SI 4 "=X,3"))]
1537 if (which_alternative == 1)
1538 return "macc\t%0,%1,%2";
1539 else if (TARGET_MIPS5500)
1540 return "madd\t%1,%2";
1542 /* The VR4130 assumes that there is a two-cycle latency between a macc
1543 that "writes" to $0 and an instruction that reads from it. We avoid
1544 this by assigning to $1 instead. */
1545 return "%[macc\t%@,%1,%2%]";
1547 [(set_attr "type" "imadd")
1548 (set_attr "mode" "SI")])
1550 (define_insn "*msac"
1551 [(set (match_operand:SI 0 "register_operand" "=l,d")
1552 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1553 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1554 (match_operand:SI 3 "register_operand" "d,d"))))
1555 (clobber (match_scratch:SI 4 "=X,1"))]
1558 if (which_alternative == 1)
1559 return "msac\t%0,%2,%3";
1560 else if (TARGET_MIPS5500)
1561 return "msub\t%2,%3";
1563 return "msac\t$0,%2,%3";
1565 [(set_attr "type" "imadd")
1566 (set_attr "mode" "SI")])
1568 ;; An msac-like instruction implemented using negation and a macc.
1569 (define_insn_and_split "*msac_using_macc"
1570 [(set (match_operand:SI 0 "register_operand" "=l,d")
1571 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1572 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1573 (match_operand:SI 3 "register_operand" "d,d"))))
1574 (clobber (match_scratch:SI 4 "=X,1"))
1575 (clobber (match_scratch:SI 5 "=d,d"))]
1576 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1578 "&& reload_completed"
1580 (neg:SI (match_dup 3)))
1583 (plus:SI (mult:SI (match_dup 2)
1586 (clobber (match_dup 4))])]
1588 [(set_attr "type" "imadd")
1589 (set_attr "length" "8")])
1591 ;; Patterns generated by the define_peephole2 below.
1593 (define_insn "*macc2"
1594 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1595 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1596 (match_operand:SI 2 "register_operand" "d"))
1598 (set (match_operand:SI 3 "register_operand" "=d")
1599 (plus:SI (mult:SI (match_dup 1)
1602 "ISA_HAS_MACC && reload_completed"
1604 [(set_attr "type" "imadd")
1605 (set_attr "mode" "SI")])
1607 (define_insn "*msac2"
1608 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1609 (minus:SI (match_dup 0)
1610 (mult:SI (match_operand:SI 1 "register_operand" "d")
1611 (match_operand:SI 2 "register_operand" "d"))))
1612 (set (match_operand:SI 3 "register_operand" "=d")
1613 (minus:SI (match_dup 0)
1614 (mult:SI (match_dup 1)
1616 "ISA_HAS_MSAC && reload_completed"
1618 [(set_attr "type" "imadd")
1619 (set_attr "mode" "SI")])
1621 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1625 ;; Operand 1: macc/msac
1626 ;; Operand 2: GPR (destination)
1629 [(set (match_operand:SI 0 "lo_operand")
1630 (match_operand:SI 1 "macc_msac_operand"))
1631 (clobber (scratch:SI))])
1632 (set (match_operand:SI 2 "d_operand")
1635 [(parallel [(set (match_dup 0)
1640 ;; When we have a three-address multiplication instruction, it should
1641 ;; be faster to do a separate multiply and add, rather than moving
1642 ;; something into LO in order to use a macc instruction.
1644 ;; This peephole needs a scratch register to cater for the case when one
1645 ;; of the multiplication operands is the same as the destination.
1647 ;; Operand 0: GPR (scratch)
1649 ;; Operand 2: GPR (addend)
1650 ;; Operand 3: GPR (destination)
1651 ;; Operand 4: macc/msac
1652 ;; Operand 5: new multiplication
1653 ;; Operand 6: new addition/subtraction
1655 [(match_scratch:SI 0 "d")
1656 (set (match_operand:SI 1 "lo_operand")
1657 (match_operand:SI 2 "d_operand"))
1660 [(set (match_operand:SI 3 "d_operand")
1661 (match_operand:SI 4 "macc_msac_operand"))
1662 (clobber (match_dup 1))])]
1663 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1664 [(parallel [(set (match_dup 0)
1666 (clobber (match_dup 1))])
1670 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1671 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1672 operands[2], operands[0]);
1675 ;; Same as above, except LO is the initial target of the macc.
1677 ;; Operand 0: GPR (scratch)
1679 ;; Operand 2: GPR (addend)
1680 ;; Operand 3: macc/msac
1681 ;; Operand 4: GPR (destination)
1682 ;; Operand 5: new multiplication
1683 ;; Operand 6: new addition/subtraction
1685 [(match_scratch:SI 0 "d")
1686 (set (match_operand:SI 1 "lo_operand")
1687 (match_operand:SI 2 "d_operand"))
1691 (match_operand:SI 3 "macc_msac_operand"))
1692 (clobber (scratch:SI))])
1694 (set (match_operand:SI 4 "d_operand")
1696 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1697 [(parallel [(set (match_dup 0)
1699 (clobber (match_dup 1))])
1703 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1704 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1705 operands[2], operands[0]);
1708 ;; See the comment above *mul_add_si for details.
1709 (define_insn "*mul_sub_si"
1710 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1711 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1712 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1713 (match_operand:SI 3 "register_operand" "d,d"))))
1714 (clobber (match_scratch:SI 4 "=X,l"))
1715 (clobber (match_scratch:SI 5 "=X,&d"))]
1716 "GENERATE_MADD_MSUB"
1720 [(set_attr "type" "imadd")
1721 (set_attr "mode" "SI")
1722 (set_attr "length" "4,8")])
1724 ;; Split *mul_sub_si if both the source and destination accumulator
1727 [(set (match_operand:SI 0 "d_operand")
1728 (minus:SI (match_operand:SI 1 "d_operand")
1729 (mult:SI (match_operand:SI 2 "d_operand")
1730 (match_operand:SI 3 "d_operand"))))
1731 (clobber (match_operand:SI 4 "lo_operand"))
1732 (clobber (match_operand:SI 5 "d_operand"))]
1734 [(parallel [(set (match_dup 5)
1735 (mult:SI (match_dup 2) (match_dup 3)))
1736 (clobber (match_dup 4))])
1737 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1740 (define_insn "*muls"
1741 [(set (match_operand:SI 0 "register_operand" "=l,d")
1742 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1743 (match_operand:SI 2 "register_operand" "d,d"))))
1744 (clobber (match_scratch:SI 3 "=X,l"))]
1749 [(set_attr "type" "imul,imul3")
1750 (set_attr "mode" "SI")])
1752 (define_expand "<u>mulsidi3"
1753 [(set (match_operand:DI 0 "register_operand")
1754 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1755 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1756 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
1758 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1759 emit_insn (fn (operands[0], operands[1], operands[2]));
1763 (define_expand "<u>mulsidi3_32bit_mips16"
1764 [(set (match_operand:DI 0 "register_operand")
1765 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1766 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1767 "!TARGET_64BIT && TARGET_MIPS16"
1771 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1772 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1773 emit_move_insn (operands[0], hilo);
1777 ;; As well as being named patterns, these instructions are used by the
1778 ;; __builtin_mips_mult<u>() functions. We must always make those functions
1779 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1780 (define_insn "<u>mulsidi3_32bit"
1781 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
1782 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1783 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1784 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP)"
1786 if (ISA_HAS_DSP_MULT)
1787 return "mult<u>\t%q0,%1,%2";
1789 return "mult<u>\t%1,%2";
1791 [(set_attr "type" "imul")
1792 (set_attr "mode" "SI")])
1794 (define_insn "<u>mulsidi3_32bit_r4000"
1795 [(set (match_operand:DI 0 "register_operand" "=d")
1796 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1797 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1798 (clobber (match_scratch:DI 3 "=x"))]
1799 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP"
1800 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1801 [(set_attr "type" "imul")
1802 (set_attr "mode" "SI")
1803 (set_attr "length" "12")])
1805 (define_insn_and_split "<u>mulsidi3_64bit"
1806 [(set (match_operand:DI 0 "register_operand" "=d")
1807 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1808 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1809 (clobber (match_scratch:TI 3 "=x"))
1810 (clobber (match_scratch:DI 4 "=d"))]
1811 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3 && !TARGET_MIPS16"
1813 "&& reload_completed"
1816 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1817 operands[2], operands[4]));
1820 [(set_attr "type" "imul")
1821 (set_attr "mode" "SI")
1822 (set (attr "length")
1823 (if_then_else (match_test "ISA_HAS_EXT_INS")
1827 (define_expand "<u>mulsidi3_64bit_mips16"
1828 [(set (match_operand:DI 0 "register_operand")
1829 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1830 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1831 "TARGET_64BIT && TARGET_MIPS16"
1833 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1834 operands[2], gen_reg_rtx (DImode)));
1838 (define_expand "<u>mulsidi3_64bit_split"
1839 [(set (match_operand:DI 0 "register_operand")
1840 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1841 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1842 (clobber (match_operand:DI 3 "register_operand"))]
1847 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1848 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1850 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM));
1851 emit_insn (gen_mfhidi_ti (operands[3], hilo));
1853 if (ISA_HAS_EXT_INS)
1854 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32),
1858 /* Zero-extend the low part. */
1859 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32));
1860 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32));
1862 /* Shift the high part into place. */
1863 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32));
1865 /* OR the two halves together. */
1866 mips_emit_binary (IOR, operands[0], operands[0], operands[3]);
1871 (define_insn "<u>mulsidi3_64bit_hilo"
1872 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
1875 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1876 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1878 "TARGET_64BIT && !TARGET_FIX_R4000"
1880 [(set_attr "type" "imul")
1881 (set_attr "mode" "SI")])
1883 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
1884 (define_insn "mulsidi3_64bit_dmul"
1885 [(set (match_operand:DI 0 "register_operand" "=d")
1886 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1887 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1888 (clobber (match_scratch:DI 3 "=l"))]
1889 "TARGET_64BIT && ISA_HAS_DMUL3"
1891 [(set_attr "type" "imul3")
1892 (set_attr "mode" "DI")])
1894 ;; Widening multiply with negation.
1895 (define_insn "*muls<u>_di"
1896 [(set (match_operand:DI 0 "muldiv_target_operand" "=x")
1899 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1900 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1901 "!TARGET_64BIT && ISA_HAS_MULS"
1903 [(set_attr "type" "imul")
1904 (set_attr "mode" "SI")])
1906 ;; As well as being named patterns, these instructions are used by the
1907 ;; __builtin_mips_msub<u>() functions. We must always make those functions
1908 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1910 ;; This leads to a slight inconsistency. We honor any tuning overrides
1911 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
1912 ;; even if !ISA_HAS_DSP_MULT.
1913 (define_insn "<u>msubsidi4"
1914 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
1916 (match_operand:DI 3 "muldiv_target_operand" "0")
1918 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1919 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1920 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
1922 if (ISA_HAS_DSP_MULT)
1923 return "msub<u>\t%q0,%1,%2";
1924 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1925 return "msub<u>\t%1,%2";
1927 return "msac<u>\t$0,%1,%2";
1929 [(set_attr "type" "imadd")
1930 (set_attr "mode" "SI")])
1932 ;; _highpart patterns
1934 (define_expand "<su>mulsi3_highpart"
1935 [(set (match_operand:SI 0 "register_operand")
1938 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1939 (any_extend:DI (match_operand:SI 2 "register_operand")))
1944 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1947 else if (TARGET_MIPS16)
1948 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
1951 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1956 (define_insn_and_split "<su>mulsi3_highpart_internal"
1957 [(set (match_operand:SI 0 "register_operand" "=d")
1960 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1961 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1963 (clobber (match_scratch:SI 3 "=l"))]
1964 "!ISA_HAS_MULHI && !TARGET_MIPS16"
1965 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1966 "&& reload_completed && !TARGET_FIX_R4000"
1969 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
1973 [(set_attr "type" "imul")
1974 (set_attr "mode" "SI")
1975 (set_attr "length" "8")])
1977 (define_expand "<su>mulsi3_highpart_split"
1978 [(set (match_operand:SI 0 "register_operand")
1981 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1982 (any_extend:DI (match_operand:SI 2 "register_operand")))
1990 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1991 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1992 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1996 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1997 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1998 emit_insn (gen_mfhisi_di (operands[0], hilo));
2003 (define_insn "<su>mulsi3_highpart_mulhi_internal"
2004 [(set (match_operand:SI 0 "register_operand" "=d")
2008 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2009 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2011 (clobber (match_scratch:SI 3 "=l"))]
2013 "mulhi<u>\t%0,%1,%2"
2014 [(set_attr "type" "imul3")
2015 (set_attr "mode" "SI")])
2017 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
2018 [(set (match_operand:SI 0 "register_operand" "=d")
2023 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2024 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2026 (clobber (match_scratch:SI 3 "=l"))]
2028 "mulshi<u>\t%0,%1,%2"
2029 [(set_attr "type" "imul3")
2030 (set_attr "mode" "SI")])
2032 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
2033 ;; errata MD(0), which says that dmultu does not always produce the
2035 (define_expand "<su>muldi3_highpart"
2036 [(set (match_operand:DI 0 "register_operand")
2039 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2040 (any_extend:TI (match_operand:DI 2 "register_operand")))
2042 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2045 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2048 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1],
2053 (define_insn_and_split "<su>muldi3_highpart_internal"
2054 [(set (match_operand:DI 0 "register_operand" "=d")
2057 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2058 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2060 (clobber (match_scratch:DI 3 "=l"))]
2063 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2064 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2065 "&& reload_completed && !TARGET_FIX_R4000"
2068 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2072 [(set_attr "type" "imul")
2073 (set_attr "mode" "DI")
2074 (set_attr "length" "8")])
2076 (define_expand "<su>muldi3_highpart_split"
2077 [(set (match_operand:DI 0 "register_operand")
2080 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2081 (any_extend:TI (match_operand:DI 2 "register_operand")))
2087 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2088 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2089 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2093 (define_expand "<u>mulditi3"
2094 [(set (match_operand:TI 0 "register_operand")
2095 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2096 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2097 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2103 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2104 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2105 emit_move_insn (operands[0], hilo);
2107 else if (TARGET_FIX_R4000)
2108 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2110 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2115 (define_insn "<u>mulditi3_internal"
2116 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2117 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2118 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2120 && !TARGET_FIX_R4000
2121 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2123 [(set_attr "type" "imul")
2124 (set_attr "mode" "DI")])
2126 (define_insn "<u>mulditi3_r4000"
2127 [(set (match_operand:TI 0 "register_operand" "=d")
2128 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2129 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2130 (clobber (match_scratch:TI 3 "=x"))]
2133 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2134 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2135 [(set_attr "type" "imul")
2136 (set_attr "mode" "DI")
2137 (set_attr "length" "12")])
2139 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2140 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2142 (define_insn "madsi"
2143 [(set (match_operand:SI 0 "register_operand" "+l")
2144 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2145 (match_operand:SI 2 "register_operand" "d"))
2149 [(set_attr "type" "imadd")
2150 (set_attr "mode" "SI")])
2152 ;; See the comment above <u>msubsidi4 for the relationship between
2153 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2154 (define_insn "<u>maddsidi4"
2155 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2157 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2158 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2159 (match_operand:DI 3 "muldiv_target_operand" "0")))]
2160 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2164 return "mad<u>\t%1,%2";
2165 else if (ISA_HAS_DSP_MULT)
2166 return "madd<u>\t%q0,%1,%2";
2167 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2168 return "madd<u>\t%1,%2";
2170 /* See comment in *macc. */
2171 return "%[macc<u>\t%@,%1,%2%]";
2173 [(set_attr "type" "imadd")
2174 (set_attr "mode" "SI")])
2176 ;; Floating point multiply accumulate instructions.
2178 (define_insn "*madd4<mode>"
2179 [(set (match_operand:ANYF 0 "register_operand" "=f")
2180 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2181 (match_operand:ANYF 2 "register_operand" "f"))
2182 (match_operand:ANYF 3 "register_operand" "f")))]
2183 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2184 "madd.<fmt>\t%0,%3,%1,%2"
2185 [(set_attr "type" "fmadd")
2186 (set_attr "mode" "<UNITMODE>")])
2188 (define_insn "*madd3<mode>"
2189 [(set (match_operand:ANYF 0 "register_operand" "=f")
2190 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2191 (match_operand:ANYF 2 "register_operand" "f"))
2192 (match_operand:ANYF 3 "register_operand" "0")))]
2193 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2194 "madd.<fmt>\t%0,%1,%2"
2195 [(set_attr "type" "fmadd")
2196 (set_attr "mode" "<UNITMODE>")])
2198 (define_insn "*msub4<mode>"
2199 [(set (match_operand:ANYF 0 "register_operand" "=f")
2200 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2201 (match_operand:ANYF 2 "register_operand" "f"))
2202 (match_operand:ANYF 3 "register_operand" "f")))]
2203 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2204 "msub.<fmt>\t%0,%3,%1,%2"
2205 [(set_attr "type" "fmadd")
2206 (set_attr "mode" "<UNITMODE>")])
2208 (define_insn "*msub3<mode>"
2209 [(set (match_operand:ANYF 0 "register_operand" "=f")
2210 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2211 (match_operand:ANYF 2 "register_operand" "f"))
2212 (match_operand:ANYF 3 "register_operand" "0")))]
2213 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2214 "msub.<fmt>\t%0,%1,%2"
2215 [(set_attr "type" "fmadd")
2216 (set_attr "mode" "<UNITMODE>")])
2218 (define_insn "*nmadd4<mode>"
2219 [(set (match_operand:ANYF 0 "register_operand" "=f")
2220 (neg:ANYF (plus:ANYF
2221 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2222 (match_operand:ANYF 2 "register_operand" "f"))
2223 (match_operand:ANYF 3 "register_operand" "f"))))]
2224 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2225 && TARGET_FUSED_MADD
2226 && HONOR_SIGNED_ZEROS (<MODE>mode)
2227 && !HONOR_NANS (<MODE>mode)"
2228 "nmadd.<fmt>\t%0,%3,%1,%2"
2229 [(set_attr "type" "fmadd")
2230 (set_attr "mode" "<UNITMODE>")])
2232 (define_insn "*nmadd3<mode>"
2233 [(set (match_operand:ANYF 0 "register_operand" "=f")
2234 (neg:ANYF (plus:ANYF
2235 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2236 (match_operand:ANYF 2 "register_operand" "f"))
2237 (match_operand:ANYF 3 "register_operand" "0"))))]
2238 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2239 && TARGET_FUSED_MADD
2240 && HONOR_SIGNED_ZEROS (<MODE>mode)
2241 && !HONOR_NANS (<MODE>mode)"
2242 "nmadd.<fmt>\t%0,%1,%2"
2243 [(set_attr "type" "fmadd")
2244 (set_attr "mode" "<UNITMODE>")])
2246 (define_insn "*nmadd4<mode>_fastmath"
2247 [(set (match_operand:ANYF 0 "register_operand" "=f")
2249 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2250 (match_operand:ANYF 2 "register_operand" "f"))
2251 (match_operand:ANYF 3 "register_operand" "f")))]
2252 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2253 && TARGET_FUSED_MADD
2254 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2255 && !HONOR_NANS (<MODE>mode)"
2256 "nmadd.<fmt>\t%0,%3,%1,%2"
2257 [(set_attr "type" "fmadd")
2258 (set_attr "mode" "<UNITMODE>")])
2260 (define_insn "*nmadd3<mode>_fastmath"
2261 [(set (match_operand:ANYF 0 "register_operand" "=f")
2263 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2264 (match_operand:ANYF 2 "register_operand" "f"))
2265 (match_operand:ANYF 3 "register_operand" "0")))]
2266 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2267 && TARGET_FUSED_MADD
2268 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2269 && !HONOR_NANS (<MODE>mode)"
2270 "nmadd.<fmt>\t%0,%1,%2"
2271 [(set_attr "type" "fmadd")
2272 (set_attr "mode" "<UNITMODE>")])
2274 (define_insn "*nmsub4<mode>"
2275 [(set (match_operand:ANYF 0 "register_operand" "=f")
2276 (neg:ANYF (minus:ANYF
2277 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2278 (match_operand:ANYF 3 "register_operand" "f"))
2279 (match_operand:ANYF 1 "register_operand" "f"))))]
2280 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2281 && TARGET_FUSED_MADD
2282 && HONOR_SIGNED_ZEROS (<MODE>mode)
2283 && !HONOR_NANS (<MODE>mode)"
2284 "nmsub.<fmt>\t%0,%1,%2,%3"
2285 [(set_attr "type" "fmadd")
2286 (set_attr "mode" "<UNITMODE>")])
2288 (define_insn "*nmsub3<mode>"
2289 [(set (match_operand:ANYF 0 "register_operand" "=f")
2290 (neg:ANYF (minus:ANYF
2291 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2292 (match_operand:ANYF 3 "register_operand" "f"))
2293 (match_operand:ANYF 1 "register_operand" "0"))))]
2294 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2295 && TARGET_FUSED_MADD
2296 && HONOR_SIGNED_ZEROS (<MODE>mode)
2297 && !HONOR_NANS (<MODE>mode)"
2298 "nmsub.<fmt>\t%0,%1,%2"
2299 [(set_attr "type" "fmadd")
2300 (set_attr "mode" "<UNITMODE>")])
2302 (define_insn "*nmsub4<mode>_fastmath"
2303 [(set (match_operand:ANYF 0 "register_operand" "=f")
2305 (match_operand:ANYF 1 "register_operand" "f")
2306 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2307 (match_operand:ANYF 3 "register_operand" "f"))))]
2308 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2309 && TARGET_FUSED_MADD
2310 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2311 && !HONOR_NANS (<MODE>mode)"
2312 "nmsub.<fmt>\t%0,%1,%2,%3"
2313 [(set_attr "type" "fmadd")
2314 (set_attr "mode" "<UNITMODE>")])
2316 (define_insn "*nmsub3<mode>_fastmath"
2317 [(set (match_operand:ANYF 0 "register_operand" "=f")
2319 (match_operand:ANYF 1 "register_operand" "f")
2320 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2321 (match_operand:ANYF 3 "register_operand" "0"))))]
2322 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2323 && TARGET_FUSED_MADD
2324 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2325 && !HONOR_NANS (<MODE>mode)"
2326 "nmsub.<fmt>\t%0,%1,%2"
2327 [(set_attr "type" "fmadd")
2328 (set_attr "mode" "<UNITMODE>")])
2331 ;; ....................
2333 ;; DIVISION and REMAINDER
2335 ;; ....................
2338 (define_expand "div<mode>3"
2339 [(set (match_operand:ANYF 0 "register_operand")
2340 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2341 (match_operand:ANYF 2 "register_operand")))]
2342 "<divide_condition>"
2344 if (const_1_operand (operands[1], <MODE>mode))
2345 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2346 operands[1] = force_reg (<MODE>mode, operands[1]);
2349 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2351 ;; If an mfc1 or dmfc1 happens to access the floating point register
2352 ;; file at the same time a long latency operation (div, sqrt, recip,
2353 ;; sqrt) iterates an intermediate result back through the floating
2354 ;; point register file bypass, then instead returning the correct
2355 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2356 ;; result of the long latency operation.
2358 ;; The workaround is to insert an unconditional 'mov' from/to the
2359 ;; long latency op destination register.
2361 (define_insn "*div<mode>3"
2362 [(set (match_operand:ANYF 0 "register_operand" "=f")
2363 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2364 (match_operand:ANYF 2 "register_operand" "f")))]
2365 "<divide_condition>"
2368 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2370 return "div.<fmt>\t%0,%1,%2";
2372 [(set_attr "type" "fdiv")
2373 (set_attr "mode" "<UNITMODE>")
2374 (set (attr "length")
2375 (if_then_else (match_test "TARGET_FIX_SB1")
2379 (define_insn "*recip<mode>3"
2380 [(set (match_operand:ANYF 0 "register_operand" "=f")
2381 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2382 (match_operand:ANYF 2 "register_operand" "f")))]
2383 "<recip_condition> && flag_unsafe_math_optimizations"
2386 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2388 return "recip.<fmt>\t%0,%2";
2390 [(set_attr "type" "frdiv")
2391 (set_attr "mode" "<UNITMODE>")
2392 (set (attr "length")
2393 (if_then_else (match_test "TARGET_FIX_SB1")
2397 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2398 ;; with negative operands. We use special libgcc functions instead.
2399 (define_expand "divmod<mode>4"
2400 [(set (match_operand:GPR 0 "register_operand")
2401 (div:GPR (match_operand:GPR 1 "register_operand")
2402 (match_operand:GPR 2 "register_operand")))
2403 (set (match_operand:GPR 3 "register_operand")
2404 (mod:GPR (match_dup 1)
2406 "!TARGET_FIX_VR4120"
2410 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1],
2412 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2415 emit_insn (gen_divmod<mode>4_internal (operands[0], operands[1],
2416 operands[2], operands[3]));
2420 (define_insn_and_split "divmod<mode>4_internal"
2421 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
2422 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2423 (match_operand:GPR 2 "register_operand" "d")))
2424 (set (match_operand:GPR 3 "register_operand" "=d")
2425 (mod:GPR (match_dup 1)
2427 "!TARGET_FIX_VR4120 && !TARGET_MIPS16"
2429 "&& reload_completed"
2432 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2435 [(set_attr "type" "idiv")
2436 (set_attr "mode" "<MODE>")
2437 (set_attr "length" "8")])
2439 (define_expand "udivmod<mode>4"
2440 [(set (match_operand:GPR 0 "register_operand")
2441 (udiv:GPR (match_operand:GPR 1 "register_operand")
2442 (match_operand:GPR 2 "register_operand")))
2443 (set (match_operand:GPR 3 "register_operand")
2444 (umod:GPR (match_dup 1)
2450 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1],
2452 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2455 emit_insn (gen_udivmod<mode>4_internal (operands[0], operands[1],
2456 operands[2], operands[3]));
2460 (define_insn_and_split "udivmod<mode>4_internal"
2461 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
2462 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2463 (match_operand:GPR 2 "register_operand" "d")))
2464 (set (match_operand:GPR 3 "register_operand" "=d")
2465 (umod:GPR (match_dup 1)
2472 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2475 [(set_attr "type" "idiv")
2476 (set_attr "mode" "<MODE>")
2477 (set_attr "length" "8")])
2479 (define_expand "<u>divmod<mode>4_split"
2480 [(set (match_operand:GPR 0 "register_operand")
2481 (any_mod:GPR (match_operand:GPR 1 "register_operand")
2482 (match_operand:GPR 2 "register_operand")))]
2489 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2490 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1],
2492 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo));
2496 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2497 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1],
2499 emit_insn (gen_mfhi<mode>_di (operands[0], hilo));
2504 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2505 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x")
2507 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2508 (match_operand:GPR 2 "register_operand" "d"))]
2511 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2512 [(set_attr "type" "idiv")
2513 (set_attr "mode" "<GPR:MODE>")])
2516 ;; ....................
2520 ;; ....................
2522 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2523 ;; "*div[sd]f3" comment for details).
2525 (define_insn "sqrt<mode>2"
2526 [(set (match_operand:ANYF 0 "register_operand" "=f")
2527 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2531 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2533 return "sqrt.<fmt>\t%0,%1";
2535 [(set_attr "type" "fsqrt")
2536 (set_attr "mode" "<UNITMODE>")
2537 (set (attr "length")
2538 (if_then_else (match_test "TARGET_FIX_SB1")
2542 (define_insn "*rsqrt<mode>a"
2543 [(set (match_operand:ANYF 0 "register_operand" "=f")
2544 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2545 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2546 "<recip_condition> && flag_unsafe_math_optimizations"
2549 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2551 return "rsqrt.<fmt>\t%0,%2";
2553 [(set_attr "type" "frsqrt")
2554 (set_attr "mode" "<UNITMODE>")
2555 (set (attr "length")
2556 (if_then_else (match_test "TARGET_FIX_SB1")
2560 (define_insn "*rsqrt<mode>b"
2561 [(set (match_operand:ANYF 0 "register_operand" "=f")
2562 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2563 (match_operand:ANYF 2 "register_operand" "f"))))]
2564 "<recip_condition> && flag_unsafe_math_optimizations"
2567 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2569 return "rsqrt.<fmt>\t%0,%2";
2571 [(set_attr "type" "frsqrt")
2572 (set_attr "mode" "<UNITMODE>")
2573 (set (attr "length")
2574 (if_then_else (match_test "TARGET_FIX_SB1")
2579 ;; ....................
2583 ;; ....................
2585 ;; Do not use the integer abs macro instruction, since that signals an
2586 ;; exception on -2147483648 (sigh).
2588 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2589 ;; invalid; it does not clear their sign bits. We therefore can't use
2590 ;; abs.fmt if the signs of NaNs matter.
2592 (define_insn "abs<mode>2"
2593 [(set (match_operand:ANYF 0 "register_operand" "=f")
2594 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2595 "!HONOR_NANS (<MODE>mode)"
2597 [(set_attr "type" "fabs")
2598 (set_attr "mode" "<UNITMODE>")])
2601 ;; ...................
2603 ;; Count leading zeroes.
2605 ;; ...................
2608 (define_insn "clz<mode>2"
2609 [(set (match_operand:GPR 0 "register_operand" "=d")
2610 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2613 [(set_attr "type" "clz")
2614 (set_attr "mode" "<MODE>")])
2617 ;; ...................
2619 ;; Count number of set bits.
2621 ;; ...................
2624 (define_insn "popcount<mode>2"
2625 [(set (match_operand:GPR 0 "register_operand" "=d")
2626 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2629 [(set_attr "type" "pop")
2630 (set_attr "mode" "<MODE>")])
2633 ;; ....................
2635 ;; NEGATION and ONE'S COMPLEMENT
2637 ;; ....................
2639 (define_insn "negsi2"
2640 [(set (match_operand:SI 0 "register_operand" "=d")
2641 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2645 return "neg\t%0,%1";
2647 return "subu\t%0,%.,%1";
2649 [(set_attr "alu_type" "sub")
2650 (set_attr "mode" "SI")])
2652 (define_insn "negdi2"
2653 [(set (match_operand:DI 0 "register_operand" "=d")
2654 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2655 "TARGET_64BIT && !TARGET_MIPS16"
2657 [(set_attr "alu_type" "sub")
2658 (set_attr "mode" "DI")])
2660 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2661 ;; invalid; it does not flip their sign bit. We therefore can't use
2662 ;; neg.fmt if the signs of NaNs matter.
2664 (define_insn "neg<mode>2"
2665 [(set (match_operand:ANYF 0 "register_operand" "=f")
2666 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2667 "!HONOR_NANS (<MODE>mode)"
2669 [(set_attr "type" "fneg")
2670 (set_attr "mode" "<UNITMODE>")])
2672 (define_insn "one_cmpl<mode>2"
2673 [(set (match_operand:GPR 0 "register_operand" "=d")
2674 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2678 return "not\t%0,%1";
2680 return "nor\t%0,%.,%1";
2682 [(set_attr "alu_type" "not")
2683 (set_attr "mode" "<MODE>")])
2686 ;; ....................
2690 ;; ....................
2693 ;; Many of these instructions use trivial define_expands, because we
2694 ;; want to use a different set of constraints when TARGET_MIPS16.
2696 (define_expand "and<mode>3"
2697 [(set (match_operand:GPR 0 "register_operand")
2698 (and:GPR (match_operand:GPR 1 "register_operand")
2699 (match_operand:GPR 2 "and_reg_operand")))])
2701 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
2702 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
2703 ;; Note that this variant does not trigger for SI mode because we require
2704 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
2705 ;; sign-extended SImode value.
2707 ;; These are possible combinations for operand 1 and 2. The table
2708 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
2709 ;; 16=MIPS16, x=match, S=split):
2711 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
2717 ;; 0xffff_ffff x S x S x
2722 (define_insn "*and<mode>3"
2723 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d")
2724 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,d,d,d,d")
2725 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,K,Yx,Yw,d")))]
2726 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2730 switch (which_alternative)
2733 operands[1] = gen_lowpart (QImode, operands[1]);
2734 return "lbu\t%0,%1";
2736 operands[1] = gen_lowpart (HImode, operands[1]);
2737 return "lhu\t%0,%1";
2739 operands[1] = gen_lowpart (SImode, operands[1]);
2740 return "lwu\t%0,%1";
2742 return "andi\t%0,%1,%x2";
2744 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
2745 operands[2] = GEN_INT (len);
2746 return "<d>ext\t%0,%1,0,%2";
2750 return "and\t%0,%1,%2";
2755 [(set_attr "move_type" "load,load,load,andi,ext_ins,shift_shift,logical")
2756 (set_attr "mode" "<MODE>")])
2758 (define_insn "*and<mode>3_mips16"
2759 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
2760 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%o,o,W,d,0")
2761 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
2762 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2764 switch (which_alternative)
2767 operands[1] = gen_lowpart (QImode, operands[1]);
2768 return "lbu\t%0,%1";
2770 operands[1] = gen_lowpart (HImode, operands[1]);
2771 return "lhu\t%0,%1";
2773 operands[1] = gen_lowpart (SImode, operands[1]);
2774 return "lwu\t%0,%1";
2778 return "and\t%0,%2";
2783 [(set_attr "move_type" "load,load,load,shift_shift,logical")
2784 (set_attr "mode" "<MODE>")])
2786 (define_expand "ior<mode>3"
2787 [(set (match_operand:GPR 0 "register_operand")
2788 (ior:GPR (match_operand:GPR 1 "register_operand")
2789 (match_operand:GPR 2 "uns_arith_operand")))]
2793 operands[2] = force_reg (<MODE>mode, operands[2]);
2796 (define_insn "*ior<mode>3"
2797 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2798 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2799 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2804 [(set_attr "alu_type" "or")
2805 (set_attr "mode" "<MODE>")])
2807 (define_insn "*ior<mode>3_mips16"
2808 [(set (match_operand:GPR 0 "register_operand" "=d")
2809 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2810 (match_operand:GPR 2 "register_operand" "d")))]
2813 [(set_attr "alu_type" "or")
2814 (set_attr "mode" "<MODE>")])
2816 (define_expand "xor<mode>3"
2817 [(set (match_operand:GPR 0 "register_operand")
2818 (xor:GPR (match_operand:GPR 1 "register_operand")
2819 (match_operand:GPR 2 "uns_arith_operand")))]
2824 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2825 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2826 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2831 [(set_attr "alu_type" "xor")
2832 (set_attr "mode" "<MODE>")])
2835 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2836 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2837 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2843 [(set_attr "alu_type" "xor")
2844 (set_attr "mode" "<MODE>")
2845 (set_attr_alternative "length"
2847 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2852 (define_insn "*nor<mode>3"
2853 [(set (match_operand:GPR 0 "register_operand" "=d")
2854 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2855 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2858 [(set_attr "alu_type" "nor")
2859 (set_attr "mode" "<MODE>")])
2862 ;; ....................
2866 ;; ....................
2870 (define_insn "truncdfsf2"
2871 [(set (match_operand:SF 0 "register_operand" "=f")
2872 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2873 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2875 [(set_attr "type" "fcvt")
2876 (set_attr "cnv_mode" "D2S")
2877 (set_attr "mode" "SF")])
2879 ;; Integer truncation patterns. Truncating SImode values to smaller
2880 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2881 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2882 ;; need to make sure that the lower 32 bits are properly sign-extended
2883 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2884 ;; smaller than SImode is equivalent to two separate truncations:
2887 ;; DI ---> HI == DI ---> SI ---> HI
2888 ;; DI ---> QI == DI ---> SI ---> QI
2890 ;; Step A needs a real instruction but step B does not.
2892 (define_insn "truncdi<mode>2"
2893 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
2894 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
2899 [(set_attr "move_type" "sll0,store")
2900 (set_attr "mode" "SI")])
2902 ;; Combiner patterns to optimize shift/truncate combinations.
2904 (define_insn "*ashr_trunc<mode>"
2905 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2907 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2908 (match_operand:DI 2 "const_arith_operand" ""))))]
2909 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
2911 [(set_attr "type" "shift")
2912 (set_attr "mode" "<MODE>")])
2914 (define_insn "*lshr32_trunc<mode>"
2915 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2917 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2919 "TARGET_64BIT && !TARGET_MIPS16"
2921 [(set_attr "type" "shift")
2922 (set_attr "mode" "<MODE>")])
2924 ;; Logical shift by more than 32 results in proper SI values so truncation is
2925 ;; removed by the middle end. Note that a logical shift by 32 is handled by
2926 ;; the previous pattern.
2927 (define_insn "*<optab>_trunc<mode>_exts"
2928 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2930 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
2931 (match_operand:DI 2 "const_arith_operand" ""))))]
2932 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
2934 [(set_attr "type" "arith")
2935 (set_attr "mode" "<MODE>")])
2938 ;; ....................
2942 ;; ....................
2946 (define_expand "zero_extendsidi2"
2947 [(set (match_operand:DI 0 "register_operand")
2948 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
2951 (define_insn_and_split "*zero_extendsidi2"
2952 [(set (match_operand:DI 0 "register_operand" "=d,d")
2953 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2954 "TARGET_64BIT && !ISA_HAS_EXT_INS"
2958 "&& reload_completed && REG_P (operands[1])"
2960 (ashift:DI (match_dup 1) (const_int 32)))
2962 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2963 { operands[1] = gen_lowpart (DImode, operands[1]); }
2964 [(set_attr "move_type" "shift_shift,load")
2965 (set_attr "mode" "DI")])
2967 (define_insn "*zero_extendsidi2_dext"
2968 [(set (match_operand:DI 0 "register_operand" "=d,d")
2969 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2970 "TARGET_64BIT && ISA_HAS_EXT_INS"
2974 [(set_attr "move_type" "arith,load")
2975 (set_attr "mode" "DI")])
2977 ;; See the comment before the *and<mode>3 pattern why this is generated by
2981 [(set (match_operand:DI 0 "register_operand")
2982 (and:DI (match_operand:DI 1 "register_operand")
2983 (const_int 4294967295)))]
2984 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
2986 (ashift:DI (match_dup 1) (const_int 32)))
2988 (lshiftrt:DI (match_dup 0) (const_int 32)))])
2990 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2991 [(set (match_operand:GPR 0 "register_operand")
2992 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2995 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2996 && !memory_operand (operands[1], <SHORT:MODE>mode))
2998 emit_insn (gen_and<GPR:mode>3 (operands[0],
2999 gen_lowpart (<GPR:MODE>mode, operands[1]),
3000 force_reg (<GPR:MODE>mode,
3001 GEN_INT (<SHORT:mask>))));
3006 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
3007 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3009 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3012 andi\t%0,%1,<SHORT:mask>
3013 l<SHORT:size>u\t%0,%1"
3014 [(set_attr "move_type" "andi,load")
3015 (set_attr "mode" "<GPR:MODE>")])
3017 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
3018 [(set (match_operand:GPR 0 "register_operand" "=d")
3019 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
3021 "ze<SHORT:size>\t%0"
3022 ;; This instruction is effectively a special encoding of ANDI.
3023 [(set_attr "move_type" "andi")
3024 (set_attr "mode" "<GPR:MODE>")])
3026 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
3027 [(set (match_operand:GPR 0 "register_operand" "=d")
3028 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
3030 "l<SHORT:size>u\t%0,%1"
3031 [(set_attr "move_type" "load")
3032 (set_attr "mode" "<GPR:MODE>")])
3034 (define_expand "zero_extendqihi2"
3035 [(set (match_operand:HI 0 "register_operand")
3036 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3039 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
3041 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
3047 (define_insn "*zero_extendqihi2"
3048 [(set (match_operand:HI 0 "register_operand" "=d,d")
3049 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3054 [(set_attr "move_type" "andi,load")
3055 (set_attr "mode" "HI")])
3057 (define_insn "*zero_extendqihi2_mips16"
3058 [(set (match_operand:HI 0 "register_operand" "=d")
3059 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3062 [(set_attr "move_type" "load")
3063 (set_attr "mode" "HI")])
3065 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3067 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
3068 [(set (match_operand:GPR 0 "register_operand" "=d")
3070 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3071 "TARGET_64BIT && !TARGET_MIPS16"
3073 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3074 return "andi\t%0,%1,%x2";
3076 [(set_attr "alu_type" "and")
3077 (set_attr "mode" "<GPR:MODE>")])
3079 (define_insn "*zero_extendhi_truncqi"
3080 [(set (match_operand:HI 0 "register_operand" "=d")
3082 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3083 "TARGET_64BIT && !TARGET_MIPS16"
3085 [(set_attr "alu_type" "and")
3086 (set_attr "mode" "HI")])
3089 ;; ....................
3093 ;; ....................
3096 ;; Those for integer source operand are ordered widest source type first.
3098 ;; When TARGET_64BIT, all SImode integer and accumulator registers
3099 ;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
3100 ;; and truncdisi2). We can therefore get rid of register->register
3101 ;; instructions if we constrain the source to be in the same register as
3104 ;; Only the pre-reload scheduler sees the type of the register alternatives;
3105 ;; we split them into nothing before the post-reload scheduler runs.
3106 ;; These alternatives therefore have type "move" in order to reflect
3107 ;; what happens if the two pre-reload operands cannot be tied, and are
3108 ;; instead allocated two separate GPRs. We don't distinguish between
3109 ;; the GPR and LO cases because we don't usually know during pre-reload
3110 ;; scheduling whether an operand will be LO or not.
3111 (define_insn_and_split "extendsidi2"
3112 [(set (match_operand:DI 0 "register_operand" "=d,l,d")
3113 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
3119 "&& reload_completed && register_operand (operands[1], VOIDmode)"
3122 emit_note (NOTE_INSN_DELETED);
3125 [(set_attr "move_type" "move,move,load")
3126 (set_attr "mode" "DI")])
3128 (define_expand "extend<SHORT:mode><GPR:mode>2"
3129 [(set (match_operand:GPR 0 "register_operand")
3130 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3133 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
3134 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3135 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3139 l<SHORT:size>\t%0,%1"
3140 [(set_attr "move_type" "signext,load")
3141 (set_attr "mode" "<GPR:MODE>")])
3143 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3144 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3146 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3147 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3150 l<SHORT:size>\t%0,%1"
3151 "&& reload_completed && REG_P (operands[1])"
3152 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3153 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3155 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3156 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3157 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3159 [(set_attr "move_type" "shift_shift,load")
3160 (set_attr "mode" "<GPR:MODE>")])
3162 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3163 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3165 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3168 se<SHORT:size>\t%0,%1
3169 l<SHORT:size>\t%0,%1"
3170 [(set_attr "move_type" "signext,load")
3171 (set_attr "mode" "<GPR:MODE>")])
3173 (define_expand "extendqihi2"
3174 [(set (match_operand:HI 0 "register_operand")
3175 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3178 (define_insn "*extendqihi2_mips16e"
3179 [(set (match_operand:HI 0 "register_operand" "=d,d")
3180 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3185 [(set_attr "move_type" "signext,load")
3186 (set_attr "mode" "SI")])
3188 (define_insn_and_split "*extendqihi2"
3189 [(set (match_operand:HI 0 "register_operand" "=d,d")
3191 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3192 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3196 "&& reload_completed && REG_P (operands[1])"
3197 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3198 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3200 operands[0] = gen_lowpart (SImode, operands[0]);
3201 operands[1] = gen_lowpart (SImode, operands[1]);
3202 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3203 - GET_MODE_BITSIZE (QImode));
3205 [(set_attr "move_type" "shift_shift,load")
3206 (set_attr "mode" "SI")])
3208 (define_insn "*extendqihi2_seb"
3209 [(set (match_operand:HI 0 "register_operand" "=d,d")
3211 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3216 [(set_attr "move_type" "signext,load")
3217 (set_attr "mode" "SI")])
3219 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3220 ;; use the shift/truncate patterns.
3222 (define_insn_and_split "*extenddi_truncate<mode>"
3223 [(set (match_operand:DI 0 "register_operand" "=d")
3225 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3226 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3228 "&& reload_completed"
3230 (ashift:DI (match_dup 1)
3233 (ashiftrt:DI (match_dup 2)
3236 operands[2] = gen_lowpart (DImode, operands[0]);
3237 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3239 [(set_attr "move_type" "shift_shift")
3240 (set_attr "mode" "DI")])
3242 (define_insn_and_split "*extendsi_truncate<mode>"
3243 [(set (match_operand:SI 0 "register_operand" "=d")
3245 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3246 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3248 "&& reload_completed"
3250 (ashift:DI (match_dup 1)
3253 (truncate:SI (ashiftrt:DI (match_dup 2)
3256 operands[2] = gen_lowpart (DImode, operands[0]);
3257 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3259 [(set_attr "move_type" "shift_shift")
3260 (set_attr "mode" "SI")])
3262 (define_insn_and_split "*extendhi_truncateqi"
3263 [(set (match_operand:HI 0 "register_operand" "=d")
3265 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3266 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3268 "&& reload_completed"
3270 (ashift:DI (match_dup 1)
3273 (truncate:HI (ashiftrt:DI (match_dup 2)
3276 operands[2] = gen_lowpart (DImode, operands[0]);
3278 [(set_attr "move_type" "shift_shift")
3279 (set_attr "mode" "SI")])
3281 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3282 [(set (match_operand:GPR 0 "register_operand" "=d")
3284 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3285 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3287 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3288 return "exts\t%0,%1,0,%m2";
3290 [(set_attr "type" "arith")
3291 (set_attr "mode" "<GPR:MODE>")])
3293 (define_insn "*extendhi_truncateqi_exts"
3294 [(set (match_operand:HI 0 "register_operand" "=d")
3296 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3297 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3299 [(set_attr "type" "arith")
3300 (set_attr "mode" "SI")])
3302 (define_insn "extendsfdf2"
3303 [(set (match_operand:DF 0 "register_operand" "=f")
3304 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3305 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3307 [(set_attr "type" "fcvt")
3308 (set_attr "cnv_mode" "S2D")
3309 (set_attr "mode" "DF")])
3312 ;; ....................
3316 ;; ....................
3318 (define_expand "fix_truncdfsi2"
3319 [(set (match_operand:SI 0 "register_operand")
3320 (fix:SI (match_operand:DF 1 "register_operand")))]
3321 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3323 if (!ISA_HAS_TRUNC_W)
3325 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3330 (define_insn "fix_truncdfsi2_insn"
3331 [(set (match_operand:SI 0 "register_operand" "=f")
3332 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3333 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3335 [(set_attr "type" "fcvt")
3336 (set_attr "mode" "DF")
3337 (set_attr "cnv_mode" "D2I")])
3339 (define_insn "fix_truncdfsi2_macro"
3340 [(set (match_operand:SI 0 "register_operand" "=f")
3341 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3342 (clobber (match_scratch:DF 2 "=d"))]
3343 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3345 if (mips_nomacro.nesting_level > 0)
3346 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3348 return "trunc.w.d %0,%1,%2";
3350 [(set_attr "type" "fcvt")
3351 (set_attr "mode" "DF")
3352 (set_attr "cnv_mode" "D2I")
3353 (set_attr "length" "36")])
3355 (define_expand "fix_truncsfsi2"
3356 [(set (match_operand:SI 0 "register_operand")
3357 (fix:SI (match_operand:SF 1 "register_operand")))]
3360 if (!ISA_HAS_TRUNC_W)
3362 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3367 (define_insn "fix_truncsfsi2_insn"
3368 [(set (match_operand:SI 0 "register_operand" "=f")
3369 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3370 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3372 [(set_attr "type" "fcvt")
3373 (set_attr "mode" "SF")
3374 (set_attr "cnv_mode" "S2I")])
3376 (define_insn "fix_truncsfsi2_macro"
3377 [(set (match_operand:SI 0 "register_operand" "=f")
3378 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3379 (clobber (match_scratch:SF 2 "=d"))]
3380 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3382 if (mips_nomacro.nesting_level > 0)
3383 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3385 return "trunc.w.s %0,%1,%2";
3387 [(set_attr "type" "fcvt")
3388 (set_attr "mode" "SF")
3389 (set_attr "cnv_mode" "S2I")
3390 (set_attr "length" "36")])
3393 (define_insn "fix_truncdfdi2"
3394 [(set (match_operand:DI 0 "register_operand" "=f")
3395 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3396 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3398 [(set_attr "type" "fcvt")
3399 (set_attr "mode" "DF")
3400 (set_attr "cnv_mode" "D2I")])
3403 (define_insn "fix_truncsfdi2"
3404 [(set (match_operand:DI 0 "register_operand" "=f")
3405 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3406 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3408 [(set_attr "type" "fcvt")
3409 (set_attr "mode" "SF")
3410 (set_attr "cnv_mode" "S2I")])
3413 (define_insn "floatsidf2"
3414 [(set (match_operand:DF 0 "register_operand" "=f")
3415 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3416 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3418 [(set_attr "type" "fcvt")
3419 (set_attr "mode" "DF")
3420 (set_attr "cnv_mode" "I2D")])
3423 (define_insn "floatdidf2"
3424 [(set (match_operand:DF 0 "register_operand" "=f")
3425 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3426 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3428 [(set_attr "type" "fcvt")
3429 (set_attr "mode" "DF")
3430 (set_attr "cnv_mode" "I2D")])
3433 (define_insn "floatsisf2"
3434 [(set (match_operand:SF 0 "register_operand" "=f")
3435 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3438 [(set_attr "type" "fcvt")
3439 (set_attr "mode" "SF")
3440 (set_attr "cnv_mode" "I2S")])
3443 (define_insn "floatdisf2"
3444 [(set (match_operand:SF 0 "register_operand" "=f")
3445 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3446 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3448 [(set_attr "type" "fcvt")
3449 (set_attr "mode" "SF")
3450 (set_attr "cnv_mode" "I2S")])
3453 (define_expand "fixuns_truncdfsi2"
3454 [(set (match_operand:SI 0 "register_operand")
3455 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3456 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3458 rtx reg1 = gen_reg_rtx (DFmode);
3459 rtx reg2 = gen_reg_rtx (DFmode);
3460 rtx reg3 = gen_reg_rtx (SImode);
3461 rtx label1 = gen_label_rtx ();
3462 rtx label2 = gen_label_rtx ();
3464 REAL_VALUE_TYPE offset;
3466 real_2expN (&offset, 31, DFmode);
3468 if (reg1) /* Turn off complaints about unreached code. */
3470 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3471 do_pending_stack_adjust ();
3473 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3474 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3476 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3477 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3478 gen_rtx_LABEL_REF (VOIDmode, label2)));
3481 emit_label (label1);
3482 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3483 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3484 (BITMASK_HIGH, SImode)));
3486 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3487 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3489 emit_label (label2);
3491 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3492 fields, and can't be used for REG_NOTES anyway). */
3493 emit_use (stack_pointer_rtx);
3499 (define_expand "fixuns_truncdfdi2"
3500 [(set (match_operand:DI 0 "register_operand")
3501 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3502 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3504 rtx reg1 = gen_reg_rtx (DFmode);
3505 rtx reg2 = gen_reg_rtx (DFmode);
3506 rtx reg3 = gen_reg_rtx (DImode);
3507 rtx label1 = gen_label_rtx ();
3508 rtx label2 = gen_label_rtx ();
3510 REAL_VALUE_TYPE offset;
3512 real_2expN (&offset, 63, DFmode);
3514 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3515 do_pending_stack_adjust ();
3517 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3518 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3520 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3521 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3522 gen_rtx_LABEL_REF (VOIDmode, label2)));
3525 emit_label (label1);
3526 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3527 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3528 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3530 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3531 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3533 emit_label (label2);
3535 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3536 fields, and can't be used for REG_NOTES anyway). */
3537 emit_use (stack_pointer_rtx);
3542 (define_expand "fixuns_truncsfsi2"
3543 [(set (match_operand:SI 0 "register_operand")
3544 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3547 rtx reg1 = gen_reg_rtx (SFmode);
3548 rtx reg2 = gen_reg_rtx (SFmode);
3549 rtx reg3 = gen_reg_rtx (SImode);
3550 rtx label1 = gen_label_rtx ();
3551 rtx label2 = gen_label_rtx ();
3553 REAL_VALUE_TYPE offset;
3555 real_2expN (&offset, 31, SFmode);
3557 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3558 do_pending_stack_adjust ();
3560 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3561 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3563 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3564 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3565 gen_rtx_LABEL_REF (VOIDmode, label2)));
3568 emit_label (label1);
3569 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3570 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3571 (BITMASK_HIGH, SImode)));
3573 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3574 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3576 emit_label (label2);
3578 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3579 fields, and can't be used for REG_NOTES anyway). */
3580 emit_use (stack_pointer_rtx);
3585 (define_expand "fixuns_truncsfdi2"
3586 [(set (match_operand:DI 0 "register_operand")
3587 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3588 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3590 rtx reg1 = gen_reg_rtx (SFmode);
3591 rtx reg2 = gen_reg_rtx (SFmode);
3592 rtx reg3 = gen_reg_rtx (DImode);
3593 rtx label1 = gen_label_rtx ();
3594 rtx label2 = gen_label_rtx ();
3596 REAL_VALUE_TYPE offset;
3598 real_2expN (&offset, 63, SFmode);
3600 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3601 do_pending_stack_adjust ();
3603 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3604 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3606 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3607 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3608 gen_rtx_LABEL_REF (VOIDmode, label2)));
3611 emit_label (label1);
3612 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3613 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3614 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3616 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3617 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3619 emit_label (label2);
3621 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3622 fields, and can't be used for REG_NOTES anyway). */
3623 emit_use (stack_pointer_rtx);
3628 ;; ....................
3632 ;; ....................
3634 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3636 (define_expand "extv"
3637 [(set (match_operand 0 "register_operand")
3638 (sign_extract (match_operand 1 "nonimmediate_operand")
3639 (match_operand 2 "const_int_operand")
3640 (match_operand 3 "const_int_operand")))]
3643 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3644 INTVAL (operands[2]),
3645 INTVAL (operands[3])))
3647 else if (register_operand (operands[1], GET_MODE (operands[0]))
3648 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3650 if (GET_MODE (operands[0]) == DImode)
3651 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3654 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3662 (define_insn "extv<mode>"
3663 [(set (match_operand:GPR 0 "register_operand" "=d")
3664 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3665 (match_operand 2 "const_int_operand" "")
3666 (match_operand 3 "const_int_operand" "")))]
3667 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3668 "exts\t%0,%1,%3,%m2"
3669 [(set_attr "type" "arith")
3670 (set_attr "mode" "<MODE>")])
3673 (define_expand "extzv"
3674 [(set (match_operand 0 "register_operand")
3675 (zero_extract (match_operand 1 "nonimmediate_operand")
3676 (match_operand 2 "const_int_operand")
3677 (match_operand 3 "const_int_operand")))]
3680 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3681 INTVAL (operands[2]),
3682 INTVAL (operands[3])))
3684 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3685 INTVAL (operands[3])))
3687 if (GET_MODE (operands[0]) == DImode)
3688 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3691 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3699 (define_insn "extzv<mode>"
3700 [(set (match_operand:GPR 0 "register_operand" "=d")
3701 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3702 (match_operand 2 "const_int_operand" "")
3703 (match_operand 3 "const_int_operand" "")))]
3704 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3705 INTVAL (operands[3]))"
3706 "<d>ext\t%0,%1,%3,%2"
3707 [(set_attr "type" "arith")
3708 (set_attr "mode" "<MODE>")])
3710 (define_insn "*extzv_truncsi_exts"
3711 [(set (match_operand:SI 0 "register_operand" "=d")
3713 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3714 (match_operand 2 "const_int_operand" "")
3715 (match_operand 3 "const_int_operand" ""))))]
3716 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3718 [(set_attr "type" "arith")
3719 (set_attr "mode" "SI")])
3722 (define_expand "insv"
3723 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3724 (match_operand 1 "immediate_operand")
3725 (match_operand 2 "immediate_operand"))
3726 (match_operand 3 "reg_or_0_operand"))]
3729 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3730 INTVAL (operands[1]),
3731 INTVAL (operands[2])))
3733 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3734 INTVAL (operands[2])))
3736 if (GET_MODE (operands[0]) == DImode)
3737 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3740 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3748 (define_insn "insv<mode>"
3749 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3750 (match_operand:SI 1 "immediate_operand" "I")
3751 (match_operand:SI 2 "immediate_operand" "I"))
3752 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3753 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3754 INTVAL (operands[2]))"
3755 "<d>ins\t%0,%z3,%2,%1"
3756 [(set_attr "type" "arith")
3757 (set_attr "mode" "<MODE>")])
3759 ;; Combiner pattern for cins (clear and insert bit field). We can
3760 ;; implement mask-and-shift-left operation with this. Note that if
3761 ;; the upper bit of the mask is set in an SImode operation, the mask
3762 ;; itself will be sign-extended. mask_low_and_shift_len will
3763 ;; therefore be greater than our threshold of 32.
3765 (define_insn "*cins<mode>"
3766 [(set (match_operand:GPR 0 "register_operand" "=d")
3768 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3769 (match_operand:GPR 2 "const_int_operand" ""))
3770 (match_operand:GPR 3 "const_int_operand" "")))]
3772 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3775 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3776 return "cins\t%0,%1,%2,%m3";
3778 [(set_attr "type" "shift")
3779 (set_attr "mode" "<MODE>")])
3781 ;; Unaligned word moves generated by the bit field patterns.
3783 ;; As far as the rtl is concerned, both the left-part and right-part
3784 ;; instructions can access the whole field. However, the real operand
3785 ;; refers to just the first or the last byte (depending on endianness).
3786 ;; We therefore use two memory operands to each instruction, one to
3787 ;; describe the rtl effect and one to use in the assembly output.
3789 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3790 ;; This allows us to use the standard length calculations for the "load"
3791 ;; and "store" type attributes.
3793 (define_insn "mov_<load>l"
3794 [(set (match_operand:GPR 0 "register_operand" "=d")
3795 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3796 (match_operand:QI 2 "memory_operand" "m")]
3798 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3800 [(set_attr "move_type" "load")
3801 (set_attr "mode" "<MODE>")])
3803 (define_insn "mov_<load>r"
3804 [(set (match_operand:GPR 0 "register_operand" "=d")
3805 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3806 (match_operand:QI 2 "memory_operand" "m")
3807 (match_operand:GPR 3 "register_operand" "0")]
3808 UNSPEC_LOAD_RIGHT))]
3809 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3811 [(set_attr "move_type" "load")
3812 (set_attr "mode" "<MODE>")])
3814 (define_insn "mov_<store>l"
3815 [(set (match_operand:BLK 0 "memory_operand" "=m")
3816 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3817 (match_operand:QI 2 "memory_operand" "m")]
3818 UNSPEC_STORE_LEFT))]
3819 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3821 [(set_attr "move_type" "store")
3822 (set_attr "mode" "<MODE>")])
3824 (define_insn "mov_<store>r"
3825 [(set (match_operand:BLK 0 "memory_operand" "+m")
3826 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3827 (match_operand:QI 2 "memory_operand" "m")
3829 UNSPEC_STORE_RIGHT))]
3830 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3832 [(set_attr "move_type" "store")
3833 (set_attr "mode" "<MODE>")])
3835 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3836 ;; The required value is:
3838 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3840 ;; which translates to:
3842 ;; lui op0,%highest(op1)
3843 ;; daddiu op0,op0,%higher(op1)
3845 ;; daddiu op0,op0,%hi(op1)
3848 ;; The split is deferred until after flow2 to allow the peephole2 below
3850 (define_insn_and_split "*lea_high64"
3851 [(set (match_operand:DI 0 "register_operand" "=d")
3852 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3853 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3855 "&& epilogue_completed"
3856 [(set (match_dup 0) (high:DI (match_dup 2)))
3857 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3858 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3859 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3860 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3862 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3863 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3865 [(set_attr "length" "20")])
3867 ;; Use a scratch register to reduce the latency of the above pattern
3868 ;; on superscalar machines. The optimized sequence is:
3870 ;; lui op1,%highest(op2)
3872 ;; daddiu op1,op1,%higher(op2)
3874 ;; daddu op1,op1,op0
3876 [(set (match_operand:DI 1 "d_operand")
3877 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3878 (match_scratch:DI 0 "d")]
3879 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3880 [(set (match_dup 1) (high:DI (match_dup 3)))
3881 (set (match_dup 0) (high:DI (match_dup 4)))
3882 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3883 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3884 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3886 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3887 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3890 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3891 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3892 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3893 ;; used once. We can then use the sequence:
3895 ;; lui op0,%highest(op1)
3897 ;; daddiu op0,op0,%higher(op1)
3898 ;; daddiu op2,op2,%lo(op1)
3900 ;; daddu op0,op0,op2
3902 ;; which takes 4 cycles on most superscalar targets.
3903 (define_insn_and_split "*lea64"
3904 [(set (match_operand:DI 0 "register_operand" "=d")
3905 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3906 (clobber (match_scratch:DI 2 "=&d"))]
3907 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3909 "&& reload_completed"
3910 [(set (match_dup 0) (high:DI (match_dup 3)))
3911 (set (match_dup 2) (high:DI (match_dup 4)))
3912 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3913 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3914 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3915 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3917 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3918 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3920 [(set_attr "length" "24")])
3922 ;; Split HIGHs into:
3927 ;; on MIPS16 targets.
3929 [(set (match_operand:P 0 "d_operand")
3930 (high:P (match_operand:P 1 "symbolic_operand_with_high")))]
3931 "TARGET_MIPS16 && reload_completed"
3932 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH))
3933 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))])
3935 (define_insn "*unshifted_high"
3936 [(set (match_operand:P 0 "d_operand" "=d")
3937 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")]
3938 UNSPEC_UNSHIFTED_HIGH))]
3941 [(set_attr "extended_mips16" "yes")])
3943 ;; Insns to fetch a symbol from a big GOT.
3945 (define_insn_and_split "*xgot_hi<mode>"
3946 [(set (match_operand:P 0 "register_operand" "=d")
3947 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3948 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3950 "&& reload_completed"
3951 [(set (match_dup 0) (high:P (match_dup 2)))
3952 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3954 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3955 operands[3] = pic_offset_table_rtx;
3957 [(set_attr "got" "xgot_high")
3958 (set_attr "mode" "<MODE>")])
3960 (define_insn_and_split "*xgot_lo<mode>"
3961 [(set (match_operand:P 0 "register_operand" "=d")
3962 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3963 (match_operand:P 2 "got_disp_operand" "")))]
3964 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3966 "&& reload_completed"
3968 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3969 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3970 [(set_attr "got" "load")
3971 (set_attr "mode" "<MODE>")])
3973 ;; Insns to fetch a symbol from a normal GOT.
3975 (define_insn_and_split "*got_disp<mode>"
3976 [(set (match_operand:P 0 "register_operand" "=d")
3977 (match_operand:P 1 "got_disp_operand" ""))]
3978 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3980 "&& reload_completed"
3981 [(set (match_dup 0) (match_dup 2))]
3982 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3983 [(set_attr "got" "load")
3984 (set_attr "mode" "<MODE>")])
3986 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3988 (define_insn_and_split "*got_page<mode>"
3989 [(set (match_operand:P 0 "register_operand" "=d")
3990 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3991 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3993 "&& reload_completed"
3994 [(set (match_dup 0) (match_dup 2))]
3995 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3996 [(set_attr "got" "load")
3997 (set_attr "mode" "<MODE>")])
3999 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
4000 (define_expand "unspec_got_<mode>"
4001 [(unspec:P [(match_operand:P 0)
4002 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
4004 ;; Lower-level instructions for loading an address from the GOT.
4005 ;; We could use MEMs, but an unspec gives more optimization
4008 (define_insn "load_got<mode>"
4009 [(set (match_operand:P 0 "register_operand" "=d")
4010 (unspec:P [(match_operand:P 1 "register_operand" "d")
4011 (match_operand:P 2 "immediate_operand" "")]
4014 "<load>\t%0,%R2(%1)"
4015 [(set_attr "got" "load")
4016 (set_attr "mode" "<MODE>")])
4018 ;; Instructions for adding the low 16 bits of an address to a register.
4019 ;; Operand 2 is the address: mips_print_operand works out which relocation
4020 ;; should be applied.
4022 (define_insn "*low<mode>"
4023 [(set (match_operand:P 0 "register_operand" "=d")
4024 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4025 (match_operand:P 2 "immediate_operand" "")))]
4027 "<d>addiu\t%0,%1,%R2"
4028 [(set_attr "alu_type" "add")
4029 (set_attr "mode" "<MODE>")])
4031 (define_insn "*low<mode>_mips16"
4032 [(set (match_operand:P 0 "register_operand" "=d")
4033 (lo_sum:P (match_operand:P 1 "register_operand" "0")
4034 (match_operand:P 2 "immediate_operand" "")))]
4037 [(set_attr "alu_type" "add")
4038 (set_attr "mode" "<MODE>")
4039 (set_attr "extended_mips16" "yes")])
4041 ;; Expose MIPS16 uses of the global pointer after reload if the function
4042 ;; is responsible for setting up the register itself.
4044 [(set (match_operand:GPR 0 "d_operand")
4045 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
4046 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
4047 [(set (match_dup 0) (match_dup 1))]
4048 { operands[1] = pic_offset_table_rtx; })
4050 ;; Allow combine to split complex const_int load sequences, using operand 2
4051 ;; to store the intermediate results. See move_operand for details.
4053 [(set (match_operand:GPR 0 "register_operand")
4054 (match_operand:GPR 1 "splittable_const_int_operand"))
4055 (clobber (match_operand:GPR 2 "register_operand"))]
4059 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
4063 ;; Likewise, for symbolic operands.
4065 [(set (match_operand:P 0 "register_operand")
4066 (match_operand:P 1))
4067 (clobber (match_operand:P 2 "register_operand"))]
4068 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
4069 [(set (match_dup 0) (match_dup 3))]
4071 mips_split_symbol (operands[2], operands[1],
4072 MAX_MACHINE_MODE, &operands[3]);
4075 ;; 64-bit integer moves
4077 ;; Unlike most other insns, the move insns can't be split with
4078 ;; different predicates, because register spilling and other parts of
4079 ;; the compiler, have memoized the insn number already.
4081 (define_expand "movdi"
4082 [(set (match_operand:DI 0 "")
4083 (match_operand:DI 1 ""))]
4086 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4090 ;; For mips16, we need a special case to handle storing $31 into
4091 ;; memory, since we don't have a constraint to match $31. This
4092 ;; instruction can be generated by save_restore_insns.
4094 (define_insn "*mov<mode>_ra"
4095 [(set (match_operand:GPR 0 "stack_operand" "=m")
4096 (reg:GPR RETURN_ADDR_REGNUM))]
4099 [(set_attr "move_type" "store")
4100 (set_attr "mode" "<MODE>")])
4102 (define_insn "*movdi_32bit"
4103 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
4104 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
4105 "!TARGET_64BIT && !TARGET_MIPS16
4106 && (register_operand (operands[0], DImode)
4107 || reg_or_0_operand (operands[1], DImode))"
4108 { return mips_output_move (operands[0], operands[1]); }
4109 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
4110 (set_attr "mode" "DI")])
4112 (define_insn "*movdi_32bit_mips16"
4113 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4114 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
4115 "!TARGET_64BIT && TARGET_MIPS16
4116 && (register_operand (operands[0], DImode)
4117 || register_operand (operands[1], DImode))"
4118 { return mips_output_move (operands[0], operands[1]); }
4119 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4120 (set_attr "mode" "DI")])
4122 (define_insn "*movdi_64bit"
4123 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
4124 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4125 "TARGET_64BIT && !TARGET_MIPS16
4126 && (register_operand (operands[0], DImode)
4127 || reg_or_0_operand (operands[1], DImode))"
4128 { return mips_output_move (operands[0], operands[1]); }
4129 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
4130 (set_attr "mode" "DI")])
4132 (define_insn "*movdi_64bit_mips16"
4133 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4134 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4135 "TARGET_64BIT && TARGET_MIPS16
4136 && (register_operand (operands[0], DImode)
4137 || register_operand (operands[1], DImode))"
4138 { return mips_output_move (operands[0], operands[1]); }
4139 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
4140 (set_attr "mode" "DI")])
4142 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4143 ;; when the original load is a 4 byte instruction but the add and the
4144 ;; load are 2 2 byte instructions.
4147 [(set (match_operand:DI 0 "d_operand")
4148 (mem:DI (plus:DI (match_dup 0)
4149 (match_operand:DI 1 "const_int_operand"))))]
4150 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4151 && !TARGET_DEBUG_D_MODE
4152 && ((INTVAL (operands[1]) < 0
4153 && INTVAL (operands[1]) >= -0x10)
4154 || (INTVAL (operands[1]) >= 32 * 8
4155 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4156 || (INTVAL (operands[1]) >= 0
4157 && INTVAL (operands[1]) < 32 * 8
4158 && (INTVAL (operands[1]) & 7) != 0))"
4159 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4160 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4162 HOST_WIDE_INT val = INTVAL (operands[1]);
4165 operands[2] = const0_rtx;
4166 else if (val >= 32 * 8)
4170 operands[1] = GEN_INT (0x8 + off);
4171 operands[2] = GEN_INT (val - off - 0x8);
4177 operands[1] = GEN_INT (off);
4178 operands[2] = GEN_INT (val - off);
4182 ;; 32-bit Integer moves
4184 ;; Unlike most other insns, the move insns can't be split with
4185 ;; different predicates, because register spilling and other parts of
4186 ;; the compiler, have memoized the insn number already.
4188 (define_expand "mov<mode>"
4189 [(set (match_operand:IMOVE32 0 "")
4190 (match_operand:IMOVE32 1 ""))]
4193 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4197 ;; The difference between these two is whether or not ints are allowed
4198 ;; in FP registers (off by default, use -mdebugh to enable).
4200 (define_insn "*mov<mode>_internal"
4201 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4202 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4204 && (register_operand (operands[0], <MODE>mode)
4205 || reg_or_0_operand (operands[1], <MODE>mode))"
4206 { return mips_output_move (operands[0], operands[1]); }
4207 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
4208 (set_attr "mode" "SI")])
4210 (define_insn "*mov<mode>_mips16"
4211 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4212 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4214 && (register_operand (operands[0], <MODE>mode)
4215 || register_operand (operands[1], <MODE>mode))"
4216 { return mips_output_move (operands[0], operands[1]); }
4217 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
4218 (set_attr "mode" "SI")])
4220 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4221 ;; when the original load is a 4 byte instruction but the add and the
4222 ;; load are 2 2 byte instructions.
4225 [(set (match_operand:SI 0 "d_operand")
4226 (mem:SI (plus:SI (match_dup 0)
4227 (match_operand:SI 1 "const_int_operand"))))]
4228 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4229 && ((INTVAL (operands[1]) < 0
4230 && INTVAL (operands[1]) >= -0x80)
4231 || (INTVAL (operands[1]) >= 32 * 4
4232 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4233 || (INTVAL (operands[1]) >= 0
4234 && INTVAL (operands[1]) < 32 * 4
4235 && (INTVAL (operands[1]) & 3) != 0))"
4236 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4237 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4239 HOST_WIDE_INT val = INTVAL (operands[1]);
4242 operands[2] = const0_rtx;
4243 else if (val >= 32 * 4)
4247 operands[1] = GEN_INT (0x7c + off);
4248 operands[2] = GEN_INT (val - off - 0x7c);
4254 operands[1] = GEN_INT (off);
4255 operands[2] = GEN_INT (val - off);
4259 ;; On the mips16, we can split a load of certain constants into a load
4260 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4264 [(set (match_operand:SI 0 "d_operand")
4265 (match_operand:SI 1 "const_int_operand"))]
4266 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4267 && INTVAL (operands[1]) >= 0x100
4268 && INTVAL (operands[1]) <= 0xff + 0x7f"
4269 [(set (match_dup 0) (match_dup 1))
4270 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4272 int val = INTVAL (operands[1]);
4274 operands[1] = GEN_INT (0xff);
4275 operands[2] = GEN_INT (val - 0xff);
4278 ;; This insn handles moving CCmode values. It's really just a
4279 ;; slightly simplified copy of movsi_internal2, with additional cases
4280 ;; to move a condition register to a general register and to move
4281 ;; between the general registers and the floating point registers.
4283 (define_insn "movcc"
4284 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4285 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4286 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4287 { return mips_output_move (operands[0], operands[1]); }
4288 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
4289 (set_attr "mode" "SI")])
4291 ;; Reload condition code registers. reload_incc and reload_outcc
4292 ;; both handle moves from arbitrary operands into condition code
4293 ;; registers. reload_incc handles the more common case in which
4294 ;; a source operand is constrained to be in a condition-code
4295 ;; register, but has not been allocated to one.
4297 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4298 ;; constraints do not include 'z'. reload_outcc handles the case
4299 ;; when such an operand is allocated to a condition-code register.
4301 ;; Note that reloads from a condition code register to some
4302 ;; other location can be done using ordinary moves. Moving
4303 ;; into a GPR takes a single movcc, moving elsewhere takes
4304 ;; two. We can leave these cases to the generic reload code.
4305 (define_expand "reload_incc"
4306 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4307 (match_operand:CC 1 "general_operand" ""))
4308 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4309 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4311 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4315 (define_expand "reload_outcc"
4316 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4317 (match_operand:CC 1 "register_operand" ""))
4318 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4319 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4321 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4325 ;; MIPS4 supports loading and storing a floating point register from
4326 ;; the sum of two general registers. We use two versions for each of
4327 ;; these four instructions: one where the two general registers are
4328 ;; SImode, and one where they are DImode. This is because general
4329 ;; registers will be in SImode when they hold 32-bit values, but,
4330 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4331 ;; instructions will still work correctly.
4333 ;; ??? Perhaps it would be better to support these instructions by
4334 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4335 ;; these instructions can only be used to load and store floating
4336 ;; point registers, that would probably cause trouble in reload.
4338 (define_insn "*<ANYF:loadx>_<P:mode>"
4339 [(set (match_operand:ANYF 0 "register_operand" "=f")
4340 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4341 (match_operand:P 2 "register_operand" "d"))))]
4343 "<ANYF:loadx>\t%0,%1(%2)"
4344 [(set_attr "type" "fpidxload")
4345 (set_attr "mode" "<ANYF:UNITMODE>")])
4347 (define_insn "*<ANYF:storex>_<P:mode>"
4348 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4349 (match_operand:P 2 "register_operand" "d")))
4350 (match_operand:ANYF 0 "register_operand" "f"))]
4352 "<ANYF:storex>\t%0,%1(%2)"
4353 [(set_attr "type" "fpidxstore")
4354 (set_attr "mode" "<ANYF:UNITMODE>")])
4356 ;; Scaled indexed address load.
4357 ;; Per md.texi, we only need to look for a pattern with multiply in the
4358 ;; address expression, not shift.
4360 (define_insn "*lwxs"
4361 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4363 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4365 (match_operand:P 2 "register_operand" "d"))))]
4368 [(set_attr "type" "load")
4369 (set_attr "mode" "SI")])
4371 ;; 16-bit Integer moves
4373 ;; Unlike most other insns, the move insns can't be split with
4374 ;; different predicates, because register spilling and other parts of
4375 ;; the compiler, have memoized the insn number already.
4376 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4378 (define_expand "movhi"
4379 [(set (match_operand:HI 0 "")
4380 (match_operand:HI 1 ""))]
4383 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4387 (define_insn "*movhi_internal"
4388 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4389 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4391 && (register_operand (operands[0], HImode)
4392 || reg_or_0_operand (operands[1], HImode))"
4393 { return mips_output_move (operands[0], operands[1]); }
4394 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4395 (set_attr "mode" "HI")])
4397 (define_insn "*movhi_mips16"
4398 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4399 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4401 && (register_operand (operands[0], HImode)
4402 || register_operand (operands[1], HImode))"
4403 { return mips_output_move (operands[0], operands[1]); }
4404 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4405 (set_attr "mode" "HI")])
4407 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4408 ;; when the original load is a 4 byte instruction but the add and the
4409 ;; load are 2 2 byte instructions.
4412 [(set (match_operand:HI 0 "d_operand")
4413 (mem:HI (plus:SI (match_dup 0)
4414 (match_operand:SI 1 "const_int_operand"))))]
4415 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4416 && ((INTVAL (operands[1]) < 0
4417 && INTVAL (operands[1]) >= -0x80)
4418 || (INTVAL (operands[1]) >= 32 * 2
4419 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4420 || (INTVAL (operands[1]) >= 0
4421 && INTVAL (operands[1]) < 32 * 2
4422 && (INTVAL (operands[1]) & 1) != 0))"
4423 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4424 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4426 HOST_WIDE_INT val = INTVAL (operands[1]);
4429 operands[2] = const0_rtx;
4430 else if (val >= 32 * 2)
4434 operands[1] = GEN_INT (0x7e + off);
4435 operands[2] = GEN_INT (val - off - 0x7e);
4441 operands[1] = GEN_INT (off);
4442 operands[2] = GEN_INT (val - off);
4446 ;; 8-bit Integer moves
4448 ;; Unlike most other insns, the move insns can't be split with
4449 ;; different predicates, because register spilling and other parts of
4450 ;; the compiler, have memoized the insn number already.
4451 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4453 (define_expand "movqi"
4454 [(set (match_operand:QI 0 "")
4455 (match_operand:QI 1 ""))]
4458 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4462 (define_insn "*movqi_internal"
4463 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4464 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4466 && (register_operand (operands[0], QImode)
4467 || reg_or_0_operand (operands[1], QImode))"
4468 { return mips_output_move (operands[0], operands[1]); }
4469 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4470 (set_attr "mode" "QI")])
4472 (define_insn "*movqi_mips16"
4473 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4474 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4476 && (register_operand (operands[0], QImode)
4477 || register_operand (operands[1], QImode))"
4478 { return mips_output_move (operands[0], operands[1]); }
4479 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4480 (set_attr "mode" "QI")])
4482 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4483 ;; when the original load is a 4 byte instruction but the add and the
4484 ;; load are 2 2 byte instructions.
4487 [(set (match_operand:QI 0 "d_operand")
4488 (mem:QI (plus:SI (match_dup 0)
4489 (match_operand:SI 1 "const_int_operand"))))]
4490 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4491 && ((INTVAL (operands[1]) < 0
4492 && INTVAL (operands[1]) >= -0x80)
4493 || (INTVAL (operands[1]) >= 32
4494 && INTVAL (operands[1]) <= 31 + 0x7f))"
4495 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4496 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4498 HOST_WIDE_INT val = INTVAL (operands[1]);
4501 operands[2] = const0_rtx;
4504 operands[1] = GEN_INT (0x7f);
4505 operands[2] = GEN_INT (val - 0x7f);
4509 ;; 32-bit floating point moves
4511 (define_expand "movsf"
4512 [(set (match_operand:SF 0 "")
4513 (match_operand:SF 1 ""))]
4516 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4520 (define_insn "*movsf_hardfloat"
4521 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4522 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4524 && (register_operand (operands[0], SFmode)
4525 || reg_or_0_operand (operands[1], SFmode))"
4526 { return mips_output_move (operands[0], operands[1]); }
4527 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4528 (set_attr "mode" "SF")])
4530 (define_insn "*movsf_softfloat"
4531 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4532 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4533 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4534 && (register_operand (operands[0], SFmode)
4535 || reg_or_0_operand (operands[1], SFmode))"
4536 { return mips_output_move (operands[0], operands[1]); }
4537 [(set_attr "move_type" "move,load,store")
4538 (set_attr "mode" "SF")])
4540 (define_insn "*movsf_mips16"
4541 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4542 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4544 && (register_operand (operands[0], SFmode)
4545 || register_operand (operands[1], SFmode))"
4546 { return mips_output_move (operands[0], operands[1]); }
4547 [(set_attr "move_type" "move,move,move,load,store")
4548 (set_attr "mode" "SF")])
4550 ;; 64-bit floating point moves
4552 (define_expand "movdf"
4553 [(set (match_operand:DF 0 "")
4554 (match_operand:DF 1 ""))]
4557 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4561 (define_insn "*movdf_hardfloat"
4562 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4563 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4564 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4565 && (register_operand (operands[0], DFmode)
4566 || reg_or_0_operand (operands[1], DFmode))"
4567 { return mips_output_move (operands[0], operands[1]); }
4568 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4569 (set_attr "mode" "DF")])
4571 (define_insn "*movdf_softfloat"
4572 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4573 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4574 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4575 && (register_operand (operands[0], DFmode)
4576 || reg_or_0_operand (operands[1], DFmode))"
4577 { return mips_output_move (operands[0], operands[1]); }
4578 [(set_attr "move_type" "move,load,store")
4579 (set_attr "mode" "DF")])
4581 (define_insn "*movdf_mips16"
4582 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4583 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4585 && (register_operand (operands[0], DFmode)
4586 || register_operand (operands[1], DFmode))"
4587 { return mips_output_move (operands[0], operands[1]); }
4588 [(set_attr "move_type" "move,move,move,load,store")
4589 (set_attr "mode" "DF")])
4591 ;; 128-bit integer moves
4593 (define_expand "movti"
4594 [(set (match_operand:TI 0)
4595 (match_operand:TI 1))]
4598 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4602 (define_insn "*movti"
4603 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4604 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4607 && (register_operand (operands[0], TImode)
4608 || reg_or_0_operand (operands[1], TImode))"
4610 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4611 (set_attr "mode" "TI")])
4613 (define_insn "*movti_mips16"
4614 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4615 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4618 && (register_operand (operands[0], TImode)
4619 || register_operand (operands[1], TImode))"
4621 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4622 (set_attr "mode" "TI")])
4624 ;; 128-bit floating point moves
4626 (define_expand "movtf"
4627 [(set (match_operand:TF 0)
4628 (match_operand:TF 1))]
4631 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4635 ;; This pattern handles both hard- and soft-float cases.
4636 (define_insn "*movtf"
4637 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4638 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4641 && (register_operand (operands[0], TFmode)
4642 || reg_or_0_operand (operands[1], TFmode))"
4644 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4645 (set_attr "mode" "TF")])
4647 (define_insn "*movtf_mips16"
4648 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4649 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4652 && (register_operand (operands[0], TFmode)
4653 || register_operand (operands[1], TFmode))"
4655 [(set_attr "move_type" "move,move,move,load,store")
4656 (set_attr "mode" "TF")])
4659 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4660 (match_operand:MOVE64 1 "move_operand"))]
4661 "reload_completed && !TARGET_64BIT
4662 && mips_split_64bit_move_p (operands[0], operands[1])"
4665 mips_split_doubleword_move (operands[0], operands[1]);
4670 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4671 (match_operand:MOVE128 1 "move_operand"))]
4672 "TARGET_64BIT && reload_completed"
4675 mips_split_doubleword_move (operands[0], operands[1]);
4679 ;; When generating mips16 code, split moves of negative constants into
4680 ;; a positive "li" followed by a negation.
4682 [(set (match_operand 0 "d_operand")
4683 (match_operand 1 "const_int_operand"))]
4684 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4688 (neg:SI (match_dup 2)))]
4690 operands[2] = gen_lowpart (SImode, operands[0]);
4691 operands[3] = GEN_INT (-INTVAL (operands[1]));
4694 ;; 64-bit paired-single floating point moves
4696 (define_expand "movv2sf"
4697 [(set (match_operand:V2SF 0)
4698 (match_operand:V2SF 1))]
4699 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4701 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4705 (define_insn "*movv2sf"
4706 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4707 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4709 && TARGET_PAIRED_SINGLE_FLOAT
4710 && (register_operand (operands[0], V2SFmode)
4711 || reg_or_0_operand (operands[1], V2SFmode))"
4712 { return mips_output_move (operands[0], operands[1]); }
4713 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4714 (set_attr "mode" "DF")])
4716 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4717 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4719 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4720 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4721 ;; and the errata related to -mfix-vr4130.
4722 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4723 [(set (match_operand:GPR 0 "register_operand" "=d")
4724 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")]
4727 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4728 [(set_attr "move_type" "mfhilo")
4729 (set_attr "mode" "<GPR:MODE>")])
4731 ;; Set the high part of a HI/LO value, given that the low part has
4732 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4733 ;; why we can't just use (reg:GPR HI_REGNUM).
4734 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4735 [(set (match_operand:HILO 0 "register_operand" "=x")
4736 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4737 (match_operand:GPR 2 "register_operand" "l")]
4741 [(set_attr "move_type" "mthilo")
4742 (set_attr "mode" "SI")])
4744 ;; Emit a doubleword move in which exactly one of the operands is
4745 ;; a floating-point register. We can't just emit two normal moves
4746 ;; because of the constraints imposed by the FPU register model;
4747 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4748 ;; the FPR whole and use special patterns to refer to each word of
4749 ;; the other operand.
4751 (define_expand "move_doubleword_fpr<mode>"
4752 [(set (match_operand:SPLITF 0)
4753 (match_operand:SPLITF 1))]
4756 if (FP_REG_RTX_P (operands[0]))
4758 rtx low = mips_subword (operands[1], 0);
4759 rtx high = mips_subword (operands[1], 1);
4760 emit_insn (gen_load_low<mode> (operands[0], low));
4761 if (TARGET_FLOAT64 && !TARGET_64BIT)
4762 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4764 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4768 rtx low = mips_subword (operands[0], 0);
4769 rtx high = mips_subword (operands[0], 1);
4770 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4771 if (TARGET_FLOAT64 && !TARGET_64BIT)
4772 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4774 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4779 ;; Load the low word of operand 0 with operand 1.
4780 (define_insn "load_low<mode>"
4781 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4782 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4786 operands[0] = mips_subword (operands[0], 0);
4787 return mips_output_move (operands[0], operands[1]);
4789 [(set_attr "move_type" "mtc,fpload")
4790 (set_attr "mode" "<HALFMODE>")])
4792 ;; Load the high word of operand 0 from operand 1, preserving the value
4794 (define_insn "load_high<mode>"
4795 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4796 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4797 (match_operand:SPLITF 2 "register_operand" "0,0")]
4801 operands[0] = mips_subword (operands[0], 1);
4802 return mips_output_move (operands[0], operands[1]);
4804 [(set_attr "move_type" "mtc,fpload")
4805 (set_attr "mode" "<HALFMODE>")])
4807 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4808 ;; high word and 0 to store the low word.
4809 (define_insn "store_word<mode>"
4810 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4811 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4812 (match_operand 2 "const_int_operand")]
4813 UNSPEC_STORE_WORD))]
4816 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4817 return mips_output_move (operands[0], operands[1]);
4819 [(set_attr "move_type" "mfc,fpstore")
4820 (set_attr "mode" "<HALFMODE>")])
4822 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4823 ;; value in the low word.
4824 (define_insn "mthc1<mode>"
4825 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4826 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4827 (match_operand:SPLITF 2 "register_operand" "0")]
4829 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4831 [(set_attr "move_type" "mtc")
4832 (set_attr "mode" "<HALFMODE>")])
4834 ;; Move high word of operand 1 to operand 0 using mfhc1.
4835 (define_insn "mfhc1<mode>"
4836 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4837 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4839 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4841 [(set_attr "move_type" "mfc")
4842 (set_attr "mode" "<HALFMODE>")])
4844 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4845 (define_expand "load_const_gp_<mode>"
4846 [(set (match_operand:P 0 "register_operand" "=d")
4847 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4849 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4850 ;; of _gp from the start of this function. Operand 1 is the incoming
4851 ;; function address.
4852 (define_insn_and_split "loadgp_newabi_<mode>"
4853 [(set (match_operand:P 0 "register_operand" "=&d")
4854 (unspec:P [(match_operand:P 1)
4855 (match_operand:P 2 "register_operand" "d")]
4857 "mips_current_loadgp_style () == LOADGP_NEWABI"
4858 { return mips_must_initialize_gp_p () ? "#" : ""; }
4859 "&& mips_must_initialize_gp_p ()"
4860 [(set (match_dup 0) (match_dup 3))
4861 (set (match_dup 0) (match_dup 4))
4862 (set (match_dup 0) (match_dup 5))]
4864 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4865 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4866 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4868 [(set_attr "type" "ghost")])
4870 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4871 (define_insn_and_split "loadgp_absolute_<mode>"
4872 [(set (match_operand:P 0 "register_operand" "=d")
4873 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4874 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4875 { return mips_must_initialize_gp_p () ? "#" : ""; }
4876 "&& mips_must_initialize_gp_p ()"
4879 mips_emit_move (operands[0], operands[1]);
4882 [(set_attr "type" "ghost")])
4884 ;; This blockage instruction prevents the gp load from being
4885 ;; scheduled after an implicit use of gp. It also prevents
4886 ;; the load from being deleted as dead.
4887 (define_insn "loadgp_blockage"
4888 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4891 [(set_attr "type" "ghost")])
4893 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4894 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4895 (define_insn_and_split "loadgp_rtp_<mode>"
4896 [(set (match_operand:P 0 "register_operand" "=d")
4897 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
4898 (match_operand:P 2 "symbol_ref_operand")]
4900 "mips_current_loadgp_style () == LOADGP_RTP"
4901 { return mips_must_initialize_gp_p () ? "#" : ""; }
4902 "&& mips_must_initialize_gp_p ()"
4903 [(set (match_dup 0) (high:P (match_dup 3)))
4904 (set (match_dup 0) (unspec:P [(match_dup 0)
4905 (match_dup 3)] UNSPEC_LOAD_GOT))
4906 (set (match_dup 0) (unspec:P [(match_dup 0)
4907 (match_dup 4)] UNSPEC_LOAD_GOT))]
4909 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4910 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4912 [(set_attr "type" "ghost")])
4914 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4915 ;; global pointer and operand 1 is the MIPS16 register that holds
4916 ;; the required value.
4917 (define_insn_and_split "copygp_mips16_<mode>"
4918 [(set (match_operand:P 0 "register_operand" "=y")
4919 (unspec:P [(match_operand:P 1 "register_operand" "d")]
4922 { return mips_must_initialize_gp_p () ? "#" : ""; }
4923 "&& mips_must_initialize_gp_p ()"
4924 [(set (match_dup 0) (match_dup 1))]
4926 [(set_attr "type" "ghost")])
4928 ;; A placeholder for where the cprestore instruction should go,
4929 ;; if we decide we need one. Operand 0 and operand 1 are as for
4930 ;; "cprestore". Operand 2 is a register that holds the gp value.
4932 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
4933 ;; otherwise any register that holds the correct value will do.
4934 (define_insn_and_split "potential_cprestore_<mode>"
4935 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
4936 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
4937 (match_operand:P 2 "register_operand" "d,d")]
4938 UNSPEC_POTENTIAL_CPRESTORE))
4939 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))]
4940 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
4941 { return mips_must_initialize_gp_p () ? "#" : ""; }
4942 "mips_must_initialize_gp_p ()"
4945 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
4946 operands[2], operands[3]);
4949 [(set_attr "type" "ghost")])
4951 ;; Emit a .cprestore directive, which normally expands to a single store
4952 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
4953 ;; for the cprestore slot. Operand 1 is the offset of the slot from
4954 ;; the stack pointer. (This is redundant with operand 0, but it makes
4955 ;; things a little simpler.)
4956 (define_insn "cprestore_<mode>"
4957 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
4958 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
4961 "TARGET_CPRESTORE_DIRECTIVE"
4963 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
4964 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
4966 return ".cprestore\t%1";
4968 [(set_attr "type" "store")
4969 (set_attr "length" "4,12")])
4971 (define_insn "use_cprestore_<mode>"
4972 [(set (reg:P CPRESTORE_SLOT_REGNUM)
4973 (match_operand:P 0 "cprestore_load_slot_operand"))]
4976 [(set_attr "type" "ghost")])
4978 ;; Expand in-line code to clear the instruction cache between operand[0] and
4980 (define_expand "clear_cache"
4981 [(match_operand 0 "pmode_register_operand")
4982 (match_operand 1 "pmode_register_operand")]
4988 mips_expand_synci_loop (operands[0], operands[1]);
4989 emit_insn (gen_sync ());
4990 emit_insn (PMODE_INSN (gen_clear_hazard, ()));
4992 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4994 rtx len = gen_reg_rtx (Pmode);
4995 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4996 MIPS_ICACHE_SYNC (operands[0], len);
5002 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
5004 { return mips_output_sync (); })
5006 (define_insn "synci"
5007 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
5012 (define_insn "rdhwr_synci_step_<mode>"
5013 [(set (match_operand:P 0 "register_operand" "=d")
5014 (unspec_volatile [(const_int 1)]
5019 (define_insn "clear_hazard_<mode>"
5020 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
5021 (clobber (reg:P RETURN_ADDR_REGNUM))]
5024 return "%(%<bal\t1f\n"
5026 "1:\t<d>addiu\t$31,$31,12\n"
5030 [(set_attr "length" "20")])
5032 ;; Cache operations for R4000-style caches.
5033 (define_insn "mips_cache"
5034 [(set (mem:BLK (scratch))
5035 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
5036 (match_operand:QI 1 "address_operand" "p")]
5037 UNSPEC_MIPS_CACHE))]
5041 ;; Similar, but with the operands hard-coded to an R10K cache barrier
5042 ;; operation. We keep the pattern distinct so that we can identify
5043 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
5044 ;; the operation is never inserted into a delay slot.
5045 (define_insn "r10k_cache_barrier"
5046 [(set (mem:BLK (scratch))
5047 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
5050 [(set_attr "can_delay" "no")])
5052 ;; Block moves, see mips.c for more details.
5053 ;; Argument 0 is the destination
5054 ;; Argument 1 is the source
5055 ;; Argument 2 is the length
5056 ;; Argument 3 is the alignment
5058 (define_expand "movmemsi"
5059 [(parallel [(set (match_operand:BLK 0 "general_operand")
5060 (match_operand:BLK 1 "general_operand"))
5061 (use (match_operand:SI 2 ""))
5062 (use (match_operand:SI 3 "const_int_operand"))])]
5063 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5065 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5072 ;; ....................
5076 ;; ....................
5078 (define_expand "<optab><mode>3"
5079 [(set (match_operand:GPR 0 "register_operand")
5080 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5081 (match_operand:SI 2 "arith_operand")))]
5084 /* On the mips16, a shift of more than 8 is a four byte instruction,
5085 so, for a shift between 8 and 16, it is just as fast to do two
5086 shifts of 8 or less. If there is a lot of shifting going on, we
5087 may win in CSE. Otherwise combine will put the shifts back
5088 together again. This can be called by mips_function_arg, so we must
5089 be careful not to allocate a new register if we've reached the
5093 && CONST_INT_P (operands[2])
5094 && INTVAL (operands[2]) > 8
5095 && INTVAL (operands[2]) <= 16
5096 && !reload_in_progress
5097 && !reload_completed)
5099 rtx temp = gen_reg_rtx (<MODE>mode);
5101 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5102 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5103 GEN_INT (INTVAL (operands[2]) - 8)));
5108 (define_insn "*<optab><mode>3"
5109 [(set (match_operand:GPR 0 "register_operand" "=d")
5110 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
5111 (match_operand:SI 2 "arith_operand" "dI")))]
5114 if (CONST_INT_P (operands[2]))
5115 operands[2] = GEN_INT (INTVAL (operands[2])
5116 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5118 return "<d><insn>\t%0,%1,%2";
5120 [(set_attr "type" "shift")
5121 (set_attr "mode" "<MODE>")])
5123 (define_insn "*<optab>si3_extend"
5124 [(set (match_operand:DI 0 "register_operand" "=d")
5126 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5127 (match_operand:SI 2 "arith_operand" "dI"))))]
5128 "TARGET_64BIT && !TARGET_MIPS16"
5130 if (CONST_INT_P (operands[2]))
5131 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5133 return "<insn>\t%0,%1,%2";
5135 [(set_attr "type" "shift")
5136 (set_attr "mode" "SI")])
5138 (define_insn "*<optab>si3_mips16"
5139 [(set (match_operand:SI 0 "register_operand" "=d,d")
5140 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
5141 (match_operand:SI 2 "arith_operand" "d,I")))]
5144 if (which_alternative == 0)
5145 return "<insn>\t%0,%2";
5147 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5148 return "<insn>\t%0,%1,%2";
5150 [(set_attr "type" "shift")
5151 (set_attr "mode" "SI")
5152 (set_attr_alternative "length"
5154 (if_then_else (match_operand 2 "m16_uimm3_b")
5158 ;; We need separate DImode MIPS16 patterns because of the irregularity
5160 (define_insn "*ashldi3_mips16"
5161 [(set (match_operand:DI 0 "register_operand" "=d,d")
5162 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
5163 (match_operand:SI 2 "arith_operand" "d,I")))]
5164 "TARGET_64BIT && TARGET_MIPS16"
5166 if (which_alternative == 0)
5167 return "dsll\t%0,%2";
5169 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5170 return "dsll\t%0,%1,%2";
5172 [(set_attr "type" "shift")
5173 (set_attr "mode" "DI")
5174 (set_attr_alternative "length"
5176 (if_then_else (match_operand 2 "m16_uimm3_b")
5180 (define_insn "*ashrdi3_mips16"
5181 [(set (match_operand:DI 0 "register_operand" "=d,d")
5182 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5183 (match_operand:SI 2 "arith_operand" "d,I")))]
5184 "TARGET_64BIT && TARGET_MIPS16"
5186 if (CONST_INT_P (operands[2]))
5187 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5189 return "dsra\t%0,%2";
5191 [(set_attr "type" "shift")
5192 (set_attr "mode" "DI")
5193 (set_attr_alternative "length"
5195 (if_then_else (match_operand 2 "m16_uimm3_b")
5199 (define_insn "*lshrdi3_mips16"
5200 [(set (match_operand:DI 0 "register_operand" "=d,d")
5201 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5202 (match_operand:SI 2 "arith_operand" "d,I")))]
5203 "TARGET_64BIT && TARGET_MIPS16"
5205 if (CONST_INT_P (operands[2]))
5206 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5208 return "dsrl\t%0,%2";
5210 [(set_attr "type" "shift")
5211 (set_attr "mode" "DI")
5212 (set_attr_alternative "length"
5214 (if_then_else (match_operand 2 "m16_uimm3_b")
5218 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5221 [(set (match_operand:GPR 0 "d_operand")
5222 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5223 (match_operand:GPR 2 "const_int_operand")))]
5224 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5225 && INTVAL (operands[2]) > 8
5226 && INTVAL (operands[2]) <= 16"
5227 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5228 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5229 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5231 ;; If we load a byte on the mips16 as a bitfield, the resulting
5232 ;; sequence of instructions is too complicated for combine, because it
5233 ;; involves four instructions: a load, a shift, a constant load into a
5234 ;; register, and an and (the key problem here is that the mips16 does
5235 ;; not have and immediate). We recognize a shift of a load in order
5236 ;; to make it simple enough for combine to understand.
5238 ;; The length here is the worst case: the length of the split version
5239 ;; will be more accurate.
5240 (define_insn_and_split ""
5241 [(set (match_operand:SI 0 "register_operand" "=d")
5242 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5243 (match_operand:SI 2 "immediate_operand" "I")))]
5247 [(set (match_dup 0) (match_dup 1))
5248 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5250 [(set_attr "type" "load")
5251 (set_attr "mode" "SI")
5252 (set_attr "length" "16")])
5254 (define_insn "rotr<mode>3"
5255 [(set (match_operand:GPR 0 "register_operand" "=d")
5256 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5257 (match_operand:SI 2 "arith_operand" "dI")))]
5260 if (CONST_INT_P (operands[2]))
5261 gcc_assert (INTVAL (operands[2]) >= 0
5262 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5264 return "<d>ror\t%0,%1,%2";
5266 [(set_attr "type" "shift")
5267 (set_attr "mode" "<MODE>")])
5270 ;; ....................
5272 ;; CONDITIONAL BRANCHES
5274 ;; ....................
5276 ;; Conditional branches on floating-point equality tests.
5278 (define_insn "*branch_fp"
5281 (match_operator 1 "equality_operator"
5282 [(match_operand:CC 2 "register_operand" "z")
5284 (label_ref (match_operand 0 "" ""))
5288 return mips_output_conditional_branch (insn, operands,
5289 MIPS_BRANCH ("b%F1", "%Z2%0"),
5290 MIPS_BRANCH ("b%W1", "%Z2%0"));
5292 [(set_attr "type" "branch")])
5294 (define_insn "*branch_fp_inverted"
5297 (match_operator 1 "equality_operator"
5298 [(match_operand:CC 2 "register_operand" "z")
5301 (label_ref (match_operand 0 "" ""))))]
5304 return mips_output_conditional_branch (insn, operands,
5305 MIPS_BRANCH ("b%W1", "%Z2%0"),
5306 MIPS_BRANCH ("b%F1", "%Z2%0"));
5308 [(set_attr "type" "branch")])
5310 ;; Conditional branches on ordered comparisons with zero.
5312 (define_insn "*branch_order<mode>"
5315 (match_operator 1 "order_operator"
5316 [(match_operand:GPR 2 "register_operand" "d")
5318 (label_ref (match_operand 0 "" ""))
5321 { return mips_output_order_conditional_branch (insn, operands, false); }
5322 [(set_attr "type" "branch")])
5324 (define_insn "*branch_order<mode>_inverted"
5327 (match_operator 1 "order_operator"
5328 [(match_operand:GPR 2 "register_operand" "d")
5331 (label_ref (match_operand 0 "" ""))))]
5333 { return mips_output_order_conditional_branch (insn, operands, true); }
5334 [(set_attr "type" "branch")])
5336 ;; Conditional branch on equality comparison.
5338 (define_insn "*branch_equality<mode>"
5341 (match_operator 1 "equality_operator"
5342 [(match_operand:GPR 2 "register_operand" "d")
5343 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5344 (label_ref (match_operand 0 "" ""))
5348 return mips_output_conditional_branch (insn, operands,
5349 MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
5350 MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
5352 [(set_attr "type" "branch")])
5354 (define_insn "*branch_equality<mode>_inverted"
5357 (match_operator 1 "equality_operator"
5358 [(match_operand:GPR 2 "register_operand" "d")
5359 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5361 (label_ref (match_operand 0 "" ""))))]
5364 return mips_output_conditional_branch (insn, operands,
5365 MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
5366 MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
5368 [(set_attr "type" "branch")])
5372 (define_insn "*branch_equality<mode>_mips16"
5375 (match_operator 0 "equality_operator"
5376 [(match_operand:GPR 1 "register_operand" "d,t")
5378 (match_operand 2 "pc_or_label_operand" "")
5379 (match_operand 3 "pc_or_label_operand" "")))]
5382 if (operands[2] != pc_rtx)
5384 if (which_alternative == 0)
5385 return "b%C0z\t%1,%2";
5387 return "bt%C0z\t%2";
5391 if (which_alternative == 0)
5392 return "b%N0z\t%1,%3";
5394 return "bt%N0z\t%3";
5397 [(set_attr "type" "branch")])
5399 (define_expand "cbranch<mode>4"
5401 (if_then_else (match_operator 0 "comparison_operator"
5402 [(match_operand:GPR 1 "register_operand")
5403 (match_operand:GPR 2 "nonmemory_operand")])
5404 (label_ref (match_operand 3 ""))
5408 mips_expand_conditional_branch (operands);
5412 (define_expand "cbranch<mode>4"
5414 (if_then_else (match_operator 0 "comparison_operator"
5415 [(match_operand:SCALARF 1 "register_operand")
5416 (match_operand:SCALARF 2 "register_operand")])
5417 (label_ref (match_operand 3 ""))
5421 mips_expand_conditional_branch (operands);
5425 ;; Used to implement built-in functions.
5426 (define_expand "condjump"
5428 (if_then_else (match_operand 0)
5429 (label_ref (match_operand 1))
5432 ;; Branch if bit is set/clear.
5434 (define_insn "*branch_bit<bbv><mode>"
5437 (equality_op (zero_extract:GPR
5438 (match_operand:GPR 1 "register_operand" "d")
5440 (match_operand 2 "const_int_operand" ""))
5442 (label_ref (match_operand 0 ""))
5444 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5447 mips_output_conditional_branch (insn, operands,
5448 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5449 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5451 [(set_attr "type" "branch")
5452 (set_attr "branch_likely" "no")])
5454 (define_insn "*branch_bit<bbv><mode>_inverted"
5457 (equality_op (zero_extract:GPR
5458 (match_operand:GPR 1 "register_operand" "d")
5460 (match_operand 2 "const_int_operand" ""))
5463 (label_ref (match_operand 0 ""))))]
5464 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5467 mips_output_conditional_branch (insn, operands,
5468 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5469 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5471 [(set_attr "type" "branch")
5472 (set_attr "branch_likely" "no")])
5475 ;; ....................
5477 ;; SETTING A REGISTER FROM A COMPARISON
5479 ;; ....................
5481 ;; Destination is always set in SI mode.
5483 (define_expand "cstore<mode>4"
5484 [(set (match_operand:SI 0 "register_operand")
5485 (match_operator:SI 1 "mips_cstore_operator"
5486 [(match_operand:GPR 2 "register_operand")
5487 (match_operand:GPR 3 "nonmemory_operand")]))]
5490 mips_expand_scc (operands);
5494 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5495 [(set (match_operand:GPR2 0 "register_operand" "=d")
5496 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5498 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5500 [(set_attr "type" "slt")
5501 (set_attr "mode" "<GPR:MODE>")])
5503 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5504 [(set (match_operand:GPR2 0 "register_operand" "=t")
5505 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5507 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5509 [(set_attr "type" "slt")
5510 (set_attr "mode" "<GPR:MODE>")])
5512 ;; Generate sltiu unless using seq results in better code.
5513 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5514 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5515 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5516 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5522 [(set_attr "type" "slt")
5523 (set_attr "mode" "<GPR:MODE>")])
5525 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5526 [(set (match_operand:GPR2 0 "register_operand" "=d")
5527 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5529 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5531 [(set_attr "type" "slt")
5532 (set_attr "mode" "<GPR:MODE>")])
5534 ;; Generate sltu unless using sne results in better code.
5535 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5536 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5537 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5538 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5544 [(set_attr "type" "slt")
5545 (set_attr "mode" "<GPR:MODE>")])
5547 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5548 [(set (match_operand:GPR2 0 "register_operand" "=d")
5549 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5550 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5553 [(set_attr "type" "slt")
5554 (set_attr "mode" "<GPR:MODE>")])
5556 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5557 [(set (match_operand:GPR2 0 "register_operand" "=t")
5558 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5559 (match_operand:GPR 2 "register_operand" "d")))]
5562 [(set_attr "type" "slt")
5563 (set_attr "mode" "<GPR:MODE>")])
5565 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5566 [(set (match_operand:GPR2 0 "register_operand" "=d")
5567 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5571 [(set_attr "type" "slt")
5572 (set_attr "mode" "<GPR:MODE>")])
5574 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5575 [(set (match_operand:GPR2 0 "register_operand" "=d")
5576 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5577 (match_operand:GPR 2 "arith_operand" "dI")))]
5580 [(set_attr "type" "slt")
5581 (set_attr "mode" "<GPR:MODE>")])
5583 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5584 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5585 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5586 (match_operand:GPR 2 "arith_operand" "d,I")))]
5589 [(set_attr "type" "slt")
5590 (set_attr "mode" "<GPR:MODE>")
5591 (set_attr_alternative "length"
5593 (if_then_else (match_operand 2 "m16_uimm8_1")
5597 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5598 [(set (match_operand:GPR2 0 "register_operand" "=d")
5599 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5600 (match_operand:GPR 2 "sle_operand" "")))]
5603 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5604 return "slt<u>\t%0,%1,%2";
5606 [(set_attr "type" "slt")
5607 (set_attr "mode" "<GPR:MODE>")])
5609 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5610 [(set (match_operand:GPR2 0 "register_operand" "=t")
5611 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5612 (match_operand:GPR 2 "sle_operand" "")))]
5615 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5616 return "slt<u>\t%1,%2";
5618 [(set_attr "type" "slt")
5619 (set_attr "mode" "<GPR:MODE>")
5620 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5625 ;; ....................
5627 ;; FLOATING POINT COMPARISONS
5629 ;; ....................
5631 (define_insn "s<code>_<mode>"
5632 [(set (match_operand:CC 0 "register_operand" "=z")
5633 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5634 (match_operand:SCALARF 2 "register_operand" "f")))]
5636 "c.<fcond>.<fmt>\t%Z0%1,%2"
5637 [(set_attr "type" "fcmp")
5638 (set_attr "mode" "FPSW")])
5640 (define_insn "s<code>_<mode>"
5641 [(set (match_operand:CC 0 "register_operand" "=z")
5642 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5643 (match_operand:SCALARF 2 "register_operand" "f")))]
5645 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5646 [(set_attr "type" "fcmp")
5647 (set_attr "mode" "FPSW")])
5650 ;; ....................
5652 ;; UNCONDITIONAL BRANCHES
5654 ;; ....................
5656 ;; Unconditional branches.
5658 (define_expand "jump"
5660 (label_ref (match_operand 0)))])
5662 (define_insn "*jump_absolute"
5664 (label_ref (match_operand 0)))]
5665 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
5666 { return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); }
5667 [(set_attr "type" "jump")])
5669 (define_insn "*jump_pic"
5671 (label_ref (match_operand 0)))]
5672 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
5674 if (get_attr_length (insn) <= 8)
5675 return "%*b\t%l0%/";
5678 mips_output_load_label (operands[0]);
5679 return "%*jr\t%@%/%]";
5682 [(set_attr "type" "branch")])
5684 ;; We need a different insn for the mips16, because a mips16 branch
5685 ;; does not have a delay slot.
5687 (define_insn "*jump_mips16"
5689 (label_ref (match_operand 0 "" "")))]
5692 [(set_attr "type" "branch")])
5694 (define_expand "indirect_jump"
5695 [(set (pc) (match_operand 0 "register_operand"))]
5698 operands[0] = force_reg (Pmode, operands[0]);
5699 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0])));
5703 (define_insn "indirect_jump_<mode>"
5704 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5707 [(set_attr "type" "jump")
5708 (set_attr "mode" "none")])
5710 (define_expand "tablejump"
5712 (match_operand 0 "register_operand"))
5713 (use (label_ref (match_operand 1 "")))]
5716 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5717 operands[0] = expand_binop (Pmode, add_optab,
5718 convert_to_mode (Pmode, operands[0], false),
5719 gen_rtx_LABEL_REF (Pmode, operands[1]),
5721 else if (TARGET_GPWORD)
5722 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5723 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5724 else if (TARGET_RTP_PIC)
5726 /* When generating RTP PIC, we use case table entries that are relative
5727 to the start of the function. Add the function's address to the
5729 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5730 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5731 start, 0, 0, OPTAB_WIDEN);
5734 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1])));
5738 (define_insn "tablejump_<mode>"
5740 (match_operand:P 0 "register_operand" "d"))
5741 (use (label_ref (match_operand 1 "" "")))]
5744 [(set_attr "type" "jump")
5745 (set_attr "mode" "none")])
5747 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5748 ;; While it is possible to either pull it off the stack (in the
5749 ;; o32 case) or recalculate it given t9 and our target label,
5750 ;; it takes 3 or 4 insns to do so.
5752 (define_expand "builtin_setjmp_setup"
5753 [(use (match_operand 0 "register_operand"))]
5758 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5759 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5763 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5764 ;; that older code did recalculate the gp from $25. Continue to jump through
5765 ;; $25 for compatibility (we lose nothing by doing so).
5767 (define_expand "builtin_longjmp"
5768 [(use (match_operand 0 "register_operand"))]
5771 /* The elements of the buffer are, in order: */
5772 int W = GET_MODE_SIZE (Pmode);
5773 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5774 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5775 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5776 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5777 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5778 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5779 The target is bound to be using $28 as the global pointer
5780 but the current function might not be. */
5781 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5783 /* This bit is similar to expand_builtin_longjmp except that it
5784 restores $gp as well. */
5785 mips_emit_move (hard_frame_pointer_rtx, fp);
5786 mips_emit_move (pv, lab);
5787 emit_stack_restore (SAVE_NONLOCAL, stack);
5788 mips_emit_move (gp, gpv);
5789 emit_use (hard_frame_pointer_rtx);
5790 emit_use (stack_pointer_rtx);
5792 emit_indirect_jump (pv);
5797 ;; ....................
5799 ;; Function prologue/epilogue
5801 ;; ....................
5804 (define_expand "prologue"
5808 mips_expand_prologue ();
5812 ;; Block any insns from being moved before this point, since the
5813 ;; profiling call to mcount can use various registers that aren't
5814 ;; saved or used to pass arguments.
5816 (define_insn "blockage"
5817 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5820 [(set_attr "type" "ghost")
5821 (set_attr "mode" "none")])
5823 (define_expand "epilogue"
5827 mips_expand_epilogue (false);
5831 (define_expand "sibcall_epilogue"
5835 mips_expand_epilogue (true);
5839 ;; Trivial return. Make it look like a normal return insn as that
5840 ;; allows jump optimizations to work better.
5842 (define_expand "return"
5844 "mips_can_use_return_insn ()"
5845 { mips_expand_before_return (); })
5847 (define_expand "simple_return"
5850 { mips_expand_before_return (); })
5852 (define_insn "*<optab>"
5856 [(set_attr "type" "jump")
5857 (set_attr "mode" "none")])
5861 (define_insn "<optab>_internal"
5863 (use (match_operand 0 "pmode_register_operand" ""))]
5866 [(set_attr "type" "jump")
5867 (set_attr "mode" "none")])
5869 ;; Exception return.
5870 (define_insn "mips_eret"
5872 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
5875 [(set_attr "type" "trap")
5876 (set_attr "mode" "none")])
5878 ;; Debug exception return.
5879 (define_insn "mips_deret"
5881 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
5884 [(set_attr "type" "trap")
5885 (set_attr "mode" "none")])
5887 ;; Disable interrupts.
5888 (define_insn "mips_di"
5889 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
5892 [(set_attr "type" "trap")
5893 (set_attr "mode" "none")])
5895 ;; Execution hazard barrier.
5896 (define_insn "mips_ehb"
5897 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
5900 [(set_attr "type" "trap")
5901 (set_attr "mode" "none")])
5903 ;; Read GPR from previous shadow register set.
5904 (define_insn "mips_rdpgpr"
5905 [(set (match_operand:SI 0 "register_operand" "=d")
5906 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
5910 [(set_attr "type" "move")
5911 (set_attr "mode" "SI")])
5913 ;; Move involving COP0 registers.
5914 (define_insn "cop0_move"
5915 [(set (match_operand:SI 0 "register_operand" "=B,d")
5916 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
5919 { return mips_output_move (operands[0], operands[1]); }
5920 [(set_attr "type" "mtc,mfc")
5921 (set_attr "mode" "SI")])
5923 ;; This is used in compiling the unwind routines.
5924 (define_expand "eh_return"
5925 [(use (match_operand 0 "general_operand"))]
5928 if (GET_MODE (operands[0]) != word_mode)
5929 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5931 emit_insn (gen_eh_set_lr_di (operands[0]));
5933 emit_insn (gen_eh_set_lr_si (operands[0]));
5937 ;; Clobber the return address on the stack. We can't expand this
5938 ;; until we know where it will be put in the stack frame.
5940 (define_insn "eh_set_lr_si"
5941 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5942 (clobber (match_scratch:SI 1 "=&d"))]
5946 (define_insn "eh_set_lr_di"
5947 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5948 (clobber (match_scratch:DI 1 "=&d"))]
5953 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5954 (clobber (match_scratch 1))]
5958 mips_set_return_address (operands[0], operands[1]);
5962 (define_expand "exception_receiver"
5966 /* See the comment above load_call<mode> for details. */
5967 emit_insn (gen_set_got_version ());
5969 /* If we have a call-clobbered $gp, restore it from its save slot. */
5970 if (HAVE_restore_gp_si)
5971 emit_insn (gen_restore_gp_si ());
5972 else if (HAVE_restore_gp_di)
5973 emit_insn (gen_restore_gp_di ());
5977 (define_expand "nonlocal_goto_receiver"
5981 /* See the comment above load_call<mode> for details. */
5982 emit_insn (gen_set_got_version ());
5986 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5987 ;; volatile until all uses of $28 are exposed.
5988 (define_insn_and_split "restore_gp_<mode>"
5990 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP))
5991 (clobber (match_scratch:P 0 "=&d"))]
5992 "TARGET_CALL_CLOBBERED_GP"
5994 "&& epilogue_completed"
5997 mips_restore_gp_from_cprestore_slot (operands[0]);
6000 [(set_attr "type" "ghost")])
6002 ;; Move between $gp and its register save slot.
6003 (define_insn_and_split "move_gp<mode>"
6004 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
6005 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
6008 { return mips_must_initialize_gp_p () ? "#" : ""; }
6009 "mips_must_initialize_gp_p ()"
6012 mips_emit_move (operands[0], operands[1]);
6015 [(set_attr "type" "ghost")])
6018 ;; ....................
6022 ;; ....................
6024 ;; Instructions to load a call address from the GOT. The address might
6025 ;; point to a function or to a lazy binding stub. In the latter case,
6026 ;; the stub will use the dynamic linker to resolve the function, which
6027 ;; in turn will change the GOT entry to point to the function's real
6030 ;; This means that every call, even pure and constant ones, can
6031 ;; potentially modify the GOT entry. And once a stub has been called,
6032 ;; we must not call it again.
6034 ;; We represent this restriction using an imaginary, fixed, call-saved
6035 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
6036 ;; live throughout the function and to change its value after every
6037 ;; potential call site. This stops any rtx value that uses the register
6038 ;; from being computed before an earlier call. To do this, we:
6040 ;; - Ensure that the register is live on entry to the function,
6041 ;; so that it is never thought to be used uninitalized.
6043 ;; - Ensure that the register is live on exit from the function,
6044 ;; so that it is live throughout.
6046 ;; - Make each call (lazily-bound or not) use the current value
6047 ;; of GOT_VERSION_REGNUM, so that updates of the register are
6048 ;; not moved across call boundaries.
6050 ;; - Add "ghost" definitions of the register to the beginning of
6051 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
6052 ;; edges may involve calls that normal paths don't. (E.g. the
6053 ;; unwinding code that handles a non-call exception may change
6054 ;; lazily-bound GOT entries.) We do this by making the
6055 ;; exception_receiver and nonlocal_goto_receiver expanders emit
6056 ;; a set_got_version instruction.
6058 ;; - After each call (lazily-bound or not), use a "ghost"
6059 ;; update_got_version instruction to change the register's value.
6060 ;; This instruction mimics the _possible_ effect of the dynamic
6061 ;; resolver during the call and it remains live even if the call
6062 ;; itself becomes dead.
6064 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
6065 ;; The register is therefore not a valid register_operand
6066 ;; and cannot be moved to or from other registers.
6068 (define_insn "load_call<mode>"
6069 [(set (match_operand:P 0 "register_operand" "=d")
6070 (unspec:P [(match_operand:P 1 "register_operand" "d")
6071 (match_operand:P 2 "immediate_operand" "")
6072 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
6074 "<load>\t%0,%R2(%1)"
6075 [(set_attr "got" "load")
6076 (set_attr "mode" "<MODE>")])
6078 (define_insn "set_got_version"
6079 [(set (reg:SI GOT_VERSION_REGNUM)
6080 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
6083 [(set_attr "type" "ghost")])
6085 (define_insn "update_got_version"
6086 [(set (reg:SI GOT_VERSION_REGNUM)
6087 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
6090 [(set_attr "type" "ghost")])
6092 ;; Sibling calls. All these patterns use jump instructions.
6094 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
6095 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
6096 ;; is defined in terms of call_insn_operand, the same is true of the
6099 ;; When we use an indirect jump, we need a register that will be
6100 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
6101 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
6102 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
6105 (define_expand "sibcall"
6106 [(parallel [(call (match_operand 0 "")
6107 (match_operand 1 ""))
6108 (use (match_operand 2 "")) ;; next_arg_reg
6109 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6112 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
6113 operands[1], operands[2], false);
6117 (define_insn "sibcall_internal"
6118 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
6119 (match_operand 1 "" ""))]
6120 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6121 { return MIPS_CALL ("j", operands, 0, 1); }
6122 [(set_attr "jal" "indirect,direct")
6123 (set_attr "jal_macro" "no")])
6125 (define_expand "sibcall_value"
6126 [(parallel [(set (match_operand 0 "")
6127 (call (match_operand 1 "")
6128 (match_operand 2 "")))
6129 (use (match_operand 3 ""))])] ;; next_arg_reg
6132 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
6133 operands[2], operands[3], false);
6137 (define_insn "sibcall_value_internal"
6138 [(set (match_operand 0 "register_operand" "")
6139 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6140 (match_operand 2 "" "")))]
6141 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6142 { return MIPS_CALL ("j", operands, 1, 2); }
6143 [(set_attr "jal" "indirect,direct")
6144 (set_attr "jal_macro" "no")])
6146 (define_insn "sibcall_value_multiple_internal"
6147 [(set (match_operand 0 "register_operand" "")
6148 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6149 (match_operand 2 "" "")))
6150 (set (match_operand 3 "register_operand" "")
6151 (call (mem:SI (match_dup 1))
6153 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6154 { return MIPS_CALL ("j", operands, 1, 2); }
6155 [(set_attr "jal" "indirect,direct")
6156 (set_attr "jal_macro" "no")])
6158 (define_expand "call"
6159 [(parallel [(call (match_operand 0 "")
6160 (match_operand 1 ""))
6161 (use (match_operand 2 "")) ;; next_arg_reg
6162 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6165 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6166 operands[1], operands[2], false);
6170 ;; This instruction directly corresponds to an assembly-language "jal".
6171 ;; There are four cases:
6174 ;; Both symbolic and register destinations are OK. The pattern
6175 ;; always expands to a single mips instruction.
6177 ;; - -mabicalls/-mno-explicit-relocs:
6178 ;; Again, both symbolic and register destinations are OK.
6179 ;; The call is treated as a multi-instruction black box.
6181 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6182 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6185 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6186 ;; Only "jal $25" is allowed. The call is actually two instructions:
6187 ;; "jalr $25" followed by an insn to reload $gp.
6189 ;; In the last case, we can generate the individual instructions with
6190 ;; a define_split. There are several things to be wary of:
6192 ;; - We can't expose the load of $gp before reload. If we did,
6193 ;; it might get removed as dead, but reload can introduce new
6194 ;; uses of $gp by rematerializing constants.
6196 ;; - We shouldn't restore $gp after calls that never return.
6197 ;; It isn't valid to insert instructions between a noreturn
6198 ;; call and the following barrier.
6200 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6201 ;; instruction preserves $gp and so have no effect on its liveness.
6202 ;; But once we generate the separate insns, it becomes obvious that
6203 ;; $gp is not live on entry to the call.
6205 (define_insn_and_split "call_internal"
6206 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6207 (match_operand 1 "" ""))
6208 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6210 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6211 "reload_completed && TARGET_SPLIT_CALLS"
6214 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6217 [(set_attr "jal" "indirect,direct")])
6219 (define_insn "call_split"
6220 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6221 (match_operand 1 "" ""))
6222 (clobber (reg:SI RETURN_ADDR_REGNUM))
6223 (clobber (reg:SI 28))]
6224 "TARGET_SPLIT_CALLS"
6225 { return MIPS_CALL ("jal", operands, 0, 1); }
6226 [(set_attr "jal" "indirect,direct")
6227 (set_attr "jal_macro" "no")])
6229 ;; A pattern for calls that must be made directly. It is used for
6230 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6231 ;; stub; the linker relies on the call relocation type to detect when
6232 ;; such redirection is needed.
6233 (define_insn_and_split "call_internal_direct"
6234 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6237 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6239 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6240 "reload_completed && TARGET_SPLIT_CALLS"
6243 mips_split_call (curr_insn,
6244 gen_call_direct_split (operands[0], operands[1]));
6247 [(set_attr "jal" "direct")])
6249 (define_insn "call_direct_split"
6250 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6253 (clobber (reg:SI RETURN_ADDR_REGNUM))
6254 (clobber (reg:SI 28))]
6255 "TARGET_SPLIT_CALLS"
6256 { return MIPS_CALL ("jal", operands, 0, -1); }
6257 [(set_attr "jal" "direct")
6258 (set_attr "jal_macro" "no")])
6260 (define_expand "call_value"
6261 [(parallel [(set (match_operand 0 "")
6262 (call (match_operand 1 "")
6263 (match_operand 2 "")))
6264 (use (match_operand 3 ""))])] ;; next_arg_reg
6267 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6268 operands[2], operands[3], false);
6272 ;; See comment for call_internal.
6273 (define_insn_and_split "call_value_internal"
6274 [(set (match_operand 0 "register_operand" "")
6275 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6276 (match_operand 2 "" "")))
6277 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6279 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6280 "reload_completed && TARGET_SPLIT_CALLS"
6283 mips_split_call (curr_insn,
6284 gen_call_value_split (operands[0], operands[1],
6288 [(set_attr "jal" "indirect,direct")])
6290 (define_insn "call_value_split"
6291 [(set (match_operand 0 "register_operand" "")
6292 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6293 (match_operand 2 "" "")))
6294 (clobber (reg:SI RETURN_ADDR_REGNUM))
6295 (clobber (reg:SI 28))]
6296 "TARGET_SPLIT_CALLS"
6297 { return MIPS_CALL ("jal", operands, 1, 2); }
6298 [(set_attr "jal" "indirect,direct")
6299 (set_attr "jal_macro" "no")])
6301 ;; See call_internal_direct.
6302 (define_insn_and_split "call_value_internal_direct"
6303 [(set (match_operand 0 "register_operand")
6304 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6307 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6309 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6310 "reload_completed && TARGET_SPLIT_CALLS"
6313 mips_split_call (curr_insn,
6314 gen_call_value_direct_split (operands[0], operands[1],
6318 [(set_attr "jal" "direct")])
6320 (define_insn "call_value_direct_split"
6321 [(set (match_operand 0 "register_operand")
6322 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6325 (clobber (reg:SI RETURN_ADDR_REGNUM))
6326 (clobber (reg:SI 28))]
6327 "TARGET_SPLIT_CALLS"
6328 { return MIPS_CALL ("jal", operands, 1, -1); }
6329 [(set_attr "jal" "direct")
6330 (set_attr "jal_macro" "no")])
6332 ;; See comment for call_internal.
6333 (define_insn_and_split "call_value_multiple_internal"
6334 [(set (match_operand 0 "register_operand" "")
6335 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6336 (match_operand 2 "" "")))
6337 (set (match_operand 3 "register_operand" "")
6338 (call (mem:SI (match_dup 1))
6340 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6342 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6343 "reload_completed && TARGET_SPLIT_CALLS"
6346 mips_split_call (curr_insn,
6347 gen_call_value_multiple_split (operands[0], operands[1],
6348 operands[2], operands[3]));
6351 [(set_attr "jal" "indirect,direct")])
6353 (define_insn "call_value_multiple_split"
6354 [(set (match_operand 0 "register_operand" "")
6355 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6356 (match_operand 2 "" "")))
6357 (set (match_operand 3 "register_operand" "")
6358 (call (mem:SI (match_dup 1))
6360 (clobber (reg:SI RETURN_ADDR_REGNUM))
6361 (clobber (reg:SI 28))]
6362 "TARGET_SPLIT_CALLS"
6363 { return MIPS_CALL ("jal", operands, 1, 2); }
6364 [(set_attr "jal" "indirect,direct")
6365 (set_attr "jal_macro" "no")])
6367 ;; Call subroutine returning any type.
6369 (define_expand "untyped_call"
6370 [(parallel [(call (match_operand 0 "")
6372 (match_operand 1 "")
6373 (match_operand 2 "")])]
6378 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6380 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6382 rtx set = XVECEXP (operands[2], 0, i);
6383 mips_emit_move (SET_DEST (set), SET_SRC (set));
6386 emit_insn (gen_blockage ());
6391 ;; ....................
6395 ;; ....................
6399 (define_insn "prefetch"
6400 [(prefetch (match_operand:QI 0 "address_operand" "p")
6401 (match_operand 1 "const_int_operand" "n")
6402 (match_operand 2 "const_int_operand" "n"))]
6403 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6405 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
6406 /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching. */
6407 return "ld\t$0,%a0";
6408 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6409 return "pref\t%1,%a0";
6411 [(set_attr "type" "prefetch")])
6413 (define_insn "*prefetch_indexed_<mode>"
6414 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6415 (match_operand:P 1 "register_operand" "d"))
6416 (match_operand 2 "const_int_operand" "n")
6417 (match_operand 3 "const_int_operand" "n"))]
6418 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6420 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6421 return "prefx\t%2,%1(%0)";
6423 [(set_attr "type" "prefetchx")])
6429 [(set_attr "type" "nop")
6430 (set_attr "mode" "none")])
6432 ;; Like nop, but commented out when outside a .set noreorder block.
6433 (define_insn "hazard_nop"
6437 if (mips_noreorder.nesting_level > 0)
6442 [(set_attr "type" "nop")])
6444 ;; MIPS4 Conditional move instructions.
6446 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6447 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6449 (match_operator:MOVECC 4 "equality_operator"
6450 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6452 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6453 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6458 [(set_attr "type" "condmove")
6459 (set_attr "mode" "<GPR:MODE>")])
6461 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6462 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6463 (if_then_else:SCALARF
6464 (match_operator:MOVECC 4 "equality_operator"
6465 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6467 (match_operand:SCALARF 2 "register_operand" "f,0")
6468 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6469 "ISA_HAS_FP_CONDMOVE"
6471 mov%T4.<fmt>\t%0,%2,%1
6472 mov%t4.<fmt>\t%0,%3,%1"
6473 [(set_attr "type" "condmove")
6474 (set_attr "mode" "<SCALARF:MODE>")])
6476 ;; These are the main define_expand's used to make conditional moves.
6478 (define_expand "mov<mode>cc"
6479 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6480 (set (match_operand:GPR 0 "register_operand")
6481 (if_then_else:GPR (match_dup 5)
6482 (match_operand:GPR 2 "reg_or_0_operand")
6483 (match_operand:GPR 3 "reg_or_0_operand")))]
6486 mips_expand_conditional_move (operands);
6490 (define_expand "mov<mode>cc"
6491 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6492 (set (match_operand:SCALARF 0 "register_operand")
6493 (if_then_else:SCALARF (match_dup 5)
6494 (match_operand:SCALARF 2 "register_operand")
6495 (match_operand:SCALARF 3 "register_operand")))]
6496 "ISA_HAS_FP_CONDMOVE"
6498 mips_expand_conditional_move (operands);
6503 ;; ....................
6505 ;; mips16 inline constant tables
6507 ;; ....................
6510 (define_insn "consttable_tls_reloc"
6511 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "")
6512 (match_operand 1 "const_int_operand" "")]
6513 UNSPEC_CONSTTABLE_INT)]
6514 "TARGET_MIPS16_PCREL_LOADS"
6515 { return mips_output_tls_reloc_directive (&operands[0]); }
6516 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6518 (define_insn "consttable_int"
6519 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6520 (match_operand 1 "const_int_operand" "")]
6521 UNSPEC_CONSTTABLE_INT)]
6524 assemble_integer (operands[0], INTVAL (operands[1]),
6525 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6528 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6530 (define_insn "consttable_float"
6531 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6532 UNSPEC_CONSTTABLE_FLOAT)]
6537 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6538 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6539 assemble_real (d, GET_MODE (operands[0]),
6540 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6543 [(set (attr "length")
6544 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6546 (define_insn "align"
6547 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6550 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6553 [(match_operand 0 "small_data_pattern")]
6556 { operands[0] = mips_rewrite_small_data (operands[0]); })
6559 ;; ....................
6561 ;; MIPS16e Save/Restore
6563 ;; ....................
6566 (define_insn "*mips16e_save_restore"
6567 [(match_parallel 0 ""
6568 [(set (match_operand:SI 1 "register_operand")
6569 (plus:SI (match_dup 1)
6570 (match_operand:SI 2 "const_int_operand")))])]
6571 "operands[1] == stack_pointer_rtx
6572 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6573 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6574 [(set_attr "type" "arith")
6575 (set_attr "extended_mips16" "yes")])
6577 ;; Thread-Local Storage
6579 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6580 ;; MIPS architecture defines this register, and no current
6581 ;; implementation provides it; instead, any OS which supports TLS is
6582 ;; expected to trap and emulate this instruction. rdhwr is part of the
6583 ;; MIPS 32r2 specification, but we use it on any architecture because
6584 ;; we expect it to be emulated. Use .set to force the assembler to
6587 ;; We do not use a constraint to force the destination to be $3
6588 ;; because $3 can appear explicitly as a function return value.
6589 ;; If we leave the use of $3 implicit in the constraints until
6590 ;; reload, we may end up making a $3 return value live across
6591 ;; the instruction, leading to a spill failure when reloading it.
6592 (define_insn_and_split "tls_get_tp_<mode>"
6593 [(set (match_operand:P 0 "register_operand" "=d")
6594 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6595 (clobber (reg:P TLS_GET_TP_REGNUM))]
6596 "HAVE_AS_TLS && !TARGET_MIPS16"
6598 "&& reload_completed"
6599 [(set (reg:P TLS_GET_TP_REGNUM)
6600 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6601 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6603 [(set_attr "type" "unknown")
6604 ; Since rdhwr always generates a trap for now, putting it in a delay
6605 ; slot would make the kernel's emulation of it much slower.
6606 (set_attr "can_delay" "no")
6607 (set_attr "mode" "<MODE>")
6608 (set_attr "length" "8")])
6610 (define_insn "*tls_get_tp_<mode>_split"
6611 [(set (reg:P TLS_GET_TP_REGNUM)
6612 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6613 "HAVE_AS_TLS && !TARGET_MIPS16"
6614 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6615 [(set_attr "type" "unknown")
6616 ; See tls_get_tp_<mode>
6617 (set_attr "can_delay" "no")
6618 (set_attr "mode" "<MODE>")])
6620 ;; In MIPS16 mode, the TLS base pointer is accessed by a
6621 ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not
6622 ;; accessible in MIPS16.
6624 ;; This is not represented as a call insn, to avoid the
6625 ;; unnecesarry clobbering of caller-save registers by a
6626 ;; function consisting only of: "rdhwr $3,$29; j $31; nop;"
6628 ;; A $25 clobber is added to cater for a $25 load stub added by the
6629 ;; linker to __mips16_rdhwr when the call is made from non-PIC code.
6631 (define_insn_and_split "tls_get_tp_mips16_<mode>"
6632 [(set (match_operand:P 0 "register_operand" "=d")
6633 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")]
6635 (clobber (reg:P TLS_GET_TP_REGNUM))
6636 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6637 (clobber (reg:P RETURN_ADDR_REGNUM))]
6638 "HAVE_AS_TLS && TARGET_MIPS16"
6640 "&& reload_completed"
6641 [(parallel [(set (reg:P TLS_GET_TP_REGNUM)
6642 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP))
6643 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6644 (clobber (reg:P RETURN_ADDR_REGNUM))])
6645 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6647 [(set_attr "type" "multi")
6648 (set_attr "length" "16")
6649 (set_attr "mode" "<MODE>")])
6651 (define_insn "*tls_get_tp_mips16_call_<mode>"
6652 [(set (reg:P TLS_GET_TP_REGNUM)
6653 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")]
6655 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6656 (clobber (reg:P RETURN_ADDR_REGNUM))]
6657 "HAVE_AS_TLS && TARGET_MIPS16"
6658 { return MIPS_CALL ("jal", operands, 0, -1); }
6659 [(set_attr "type" "call")
6660 (set_attr "length" "12")
6661 (set_attr "mode" "<MODE>")])
6663 ;; Synchronization instructions.
6667 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6669 (include "mips-ps-3d.md")
6671 ; The MIPS DSP Instructions.
6673 (include "mips-dsp.md")
6675 ; The MIPS DSP REV 2 Instructions.
6677 (include "mips-dspr2.md")
6679 ; MIPS fixed-point instructions.
6680 (include "mips-fixed.md")
6682 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6683 (include "loongson.md")
6685 (define_c_enum "unspec" [
6686 UNSPEC_ADDRESS_FIRST