1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GNU CC.
11 ;; GNU CC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GNU CC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GNU CC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
24 ;; Boston, MA 02111-1307, USA.
26 ;; ??? Currently does not have define_function_unit support for the R8000.
27 ;; Must include new entries for fmadd in addition to existing entries.
31 ;; ....................
35 ;; ....................
37 ;; Classification of each insn.
38 ;; branch conditional branch
39 ;; jump unconditional jump
40 ;; call unconditional call
41 ;; load load instruction(s)
42 ;; store store instruction(s)
43 ;; move data movement within same register set
44 ;; xfer transfer to/from coprocessor
45 ;; hilo transfer of hi/lo registers
46 ;; arith integer arithmetic instruction
47 ;; darith double precision integer arithmetic instructions
48 ;; imul integer multiply
49 ;; idiv integer divide
50 ;; icmp integer compare
51 ;; fadd floating point add/subtract
52 ;; fmul floating point multiply
53 ;; fmadd floating point multiply-add
54 ;; fdiv floating point divide
55 ;; fabs floating point absolute value
56 ;; fneg floating point negation
57 ;; fcmp floating point compare
58 ;; fcvt floating point convert
59 ;; fsqrt floating point square root
60 ;; multi multiword sequence (or user asm statements)
64 "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
65 (const_string "unknown"))
67 ;; Main data type used by the insn
68 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
70 ;; Length (in # of bytes). A conditional branch is allowed only to a
71 ;; location within a signed 18-bit offset of the delay slot. If that
72 ;; provides too smal a range, we use the `j' instruction. This
73 ;; instruction takes a 28-bit value, but that value is not an offset.
74 ;; Instead, it's bitwise-ored with the high-order four bits of the
75 ;; instruction in the delay slot, which means it cannot be used to
76 ;; cross a 256MB boundary. We could fall back back on the jr,
77 ;; instruction which allows full access to the entire address space,
78 ;; but we do not do so at present.
80 (define_attr "length" ""
81 (cond [(eq_attr "type" "branch")
82 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
88 ;; Attribute describing the processor. This attribute must match exactly
89 ;; with the processor_type enumeration in mips.h.
91 ;; Attribute describing the processor
92 ;; (define_attr "cpu" "default,r3000,r6000,r4000"
94 ;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
95 ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
96 ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
97 ;; (const_string "default"))))
99 ;; ??? Fix everything that tests this attribute.
101 "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000"
102 (const (symbol_ref "mips_cpu_attr")))
104 ;; Does the instruction have a mandatory delay slot?
105 ;; The 3900, is (mostly) mips1, but does not have a mandatory load delay
107 (define_attr "dslot" "no,yes"
108 (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
109 (and (eq_attr "type" "load")
110 (and (eq (symbol_ref "mips_isa") (const_int 1))
111 (and (eq (symbol_ref "mips16") (const_int 0))
112 (eq_attr "cpu" "!r3900")))))
114 (const_string "no")))
116 ;; Attribute defining whether or not we can use the branch-likely instructions
118 (define_attr "branch_likely" "no,yes"
120 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
122 (const_string "no"))))
125 ;; Describe a user's asm statement.
126 (define_asm_attributes
127 [(set_attr "type" "multi")])
129 ;; whether or not generating calls to position independent functions
130 (define_attr "abicalls" "no,yes"
131 (const (symbol_ref "mips_abicalls_attr")))
135 ;; .........................
137 ;; Delay slots, can't describe load/fcmp/xfer delay slots here
139 ;; .........................
141 (define_delay (and (eq_attr "type" "branch")
142 (eq (symbol_ref "mips16") (const_int 0)))
143 [(and (eq_attr "dslot" "no") (eq_attr "length" "4"))
145 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "4")))])
147 (define_delay (eq_attr "type" "jump")
148 [(and (eq_attr "dslot" "no") (eq_attr "length" "4"))
152 (define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
153 [(and (eq_attr "dslot" "no") (eq_attr "length" "4"))
159 ;; .........................
163 ;; .........................
165 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
166 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
168 ;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
170 (define_function_unit "memory" 1 0
171 (and (eq_attr "type" "load")
172 (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
175 (define_function_unit "memory" 1 0
176 (and (eq_attr "type" "load")
177 (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
180 (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
182 (define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
184 (define_function_unit "imuldiv" 1 0
185 (eq_attr "type" "hilo")
188 (define_function_unit "imuldiv" 1 0
189 (and (eq_attr "type" "imul")
190 (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
193 ;; On them mips16, we want to stronly discourage a mult from appearing
194 ;; after an mflo, since that requires explicit nop instructions. We
195 ;; do this by pretending that mflo ties up the function unit for long
196 ;; enough that the scheduler will ignore load stalls and the like when
197 ;; selecting instructions to between the two instructions.
199 (define_function_unit "imuldiv" 1 0
200 (and (eq_attr "type" "hilo") (ne (symbol_ref "mips16") (const_int 0)))
203 (define_function_unit "imuldiv" 1 0
204 (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000,r3900"))
207 (define_function_unit "imuldiv" 1 0
208 (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600"))
211 (define_function_unit "imuldiv" 1 0
212 (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650"))
215 (define_function_unit "imuldiv" 1 0
216 (and (eq_attr "type" "imul")
217 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
220 (define_function_unit "imuldiv" 1 0
221 (and (eq_attr "type" "imul")
222 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
225 (define_function_unit "imuldiv" 1 0
226 (and (eq_attr "type" "imul")
227 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
230 (define_function_unit "imuldiv" 1 0
231 (and (eq_attr "type" "imul")
232 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
235 (define_function_unit "imuldiv" 1 0
236 (and (eq_attr "type" "imul")
237 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
240 (define_function_unit "imuldiv" 1 0
241 (and (eq_attr "type" "idiv")
242 (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
245 (define_function_unit "imuldiv" 1 0
246 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
249 (define_function_unit "imuldiv" 1 0
250 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
253 (define_function_unit "imuldiv" 1 0
254 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
257 (define_function_unit "imuldiv" 1 0
258 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
261 (define_function_unit "imuldiv" 1 0
262 (and (eq_attr "type" "idiv")
263 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
266 (define_function_unit "imuldiv" 1 0
267 (and (eq_attr "type" "idiv")
268 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
271 (define_function_unit "imuldiv" 1 0
272 (and (eq_attr "type" "idiv")
273 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
276 (define_function_unit "imuldiv" 1 0
277 (and (eq_attr "type" "idiv")
278 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
281 (define_function_unit "imuldiv" 1 0
282 (and (eq_attr "type" "idiv")
283 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
286 (define_function_unit "imuldiv" 1 0
287 (and (eq_attr "type" "idiv")
288 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
291 ;; The R4300 does *NOT* have a separate Floating Point Unit, instead
292 ;; the FP hardware is part of the normal ALU circuitry. This means FP
293 ;; instructions affect the pipe-line, and no functional unit
294 ;; parallelism can occur on R4300 processors. To force GCC into coding
295 ;; for only a single functional unit, we force the R4300 FP
296 ;; instructions to be processed in the "imuldiv" unit.
298 (define_function_unit "adder" 1 1
299 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
302 (define_function_unit "adder" 1 1
303 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
306 (define_function_unit "adder" 1 1
307 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
310 (define_function_unit "adder" 1 1
311 (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
314 (define_function_unit "adder" 1 1
315 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
318 (define_function_unit "adder" 1 1
319 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
322 (define_function_unit "adder" 1 1
323 (and (eq_attr "type" "fabs,fneg")
324 (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
327 (define_function_unit "adder" 1 1
328 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
331 (define_function_unit "mult" 1 1
332 (and (eq_attr "type" "fmul")
333 (and (eq_attr "mode" "SF")
334 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
337 (define_function_unit "mult" 1 1
338 (and (eq_attr "type" "fmul")
339 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
342 (define_function_unit "mult" 1 1
343 (and (eq_attr "type" "fmul")
344 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
347 (define_function_unit "mult" 1 1
348 (and (eq_attr "type" "fmul")
349 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
352 (define_function_unit "mult" 1 1
353 (and (eq_attr "type" "fmul")
354 (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
357 (define_function_unit "mult" 1 1
358 (and (eq_attr "type" "fmul")
359 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
362 (define_function_unit "mult" 1 1
363 (and (eq_attr "type" "fmul")
364 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
367 (define_function_unit "divide" 1 1
368 (and (eq_attr "type" "fdiv")
369 (and (eq_attr "mode" "SF")
370 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
373 (define_function_unit "divide" 1 1
374 (and (eq_attr "type" "fdiv")
375 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
378 (define_function_unit "divide" 1 1
379 (and (eq_attr "type" "fdiv")
380 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
383 (define_function_unit "divide" 1 1
384 (and (eq_attr "type" "fdiv")
385 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
388 (define_function_unit "divide" 1 1
389 (and (eq_attr "type" "fdiv")
390 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
393 (define_function_unit "divide" 1 1
394 (and (eq_attr "type" "fdiv")
395 (and (eq_attr "mode" "DF")
396 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
399 (define_function_unit "divide" 1 1
400 (and (eq_attr "type" "fdiv")
401 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
404 (define_function_unit "divide" 1 1
405 (and (eq_attr "type" "fdiv")
406 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
409 (define_function_unit "divide" 1 1
410 (and (eq_attr "type" "fdiv")
411 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
414 ;;; ??? Is this number right?
415 (define_function_unit "divide" 1 1
416 (and (eq_attr "type" "fsqrt")
417 (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
420 (define_function_unit "divide" 1 1
421 (and (eq_attr "type" "fsqrt")
422 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
425 (define_function_unit "divide" 1 1
426 (and (eq_attr "type" "fsqrt")
427 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
430 ;;; ??? Is this number right?
431 (define_function_unit "divide" 1 1
432 (and (eq_attr "type" "fsqrt")
433 (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
436 (define_function_unit "divide" 1 1
437 (and (eq_attr "type" "fsqrt")
438 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
441 (define_function_unit "divide" 1 1
442 (and (eq_attr "type" "fsqrt")
443 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
446 ;; R4300 FP instruction classes treated as part of the "imuldiv"
449 (define_function_unit "imuldiv" 1 0
450 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
453 (define_function_unit "imuldiv" 1 0
454 (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300"))
457 (define_function_unit "imuldiv" 1 0
458 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
460 (define_function_unit "imuldiv" 1 0
461 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
464 (define_function_unit "imuldiv" 1 0
465 (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
466 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
468 (define_function_unit "imuldiv" 1 0
469 (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
470 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
473 ;; The following functional units do not use the cpu type, and use
474 ;; much less memory in genattrtab.c.
476 ;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
477 ;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
479 ;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
481 ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
482 ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
484 ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
485 ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
487 ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
488 ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
490 ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
491 ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
493 ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
494 ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
496 ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
497 ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
500 ;; ....................
504 ;; ....................
508 [(trap_if (const_int 1) (const_int 0))]
512 if (ISA_HAS_COND_TRAP)
513 return \"teq\\t$0,$0\";
518 (define_expand "conditional_trap"
519 [(trap_if (match_operator 0 "cmp_op"
520 [(match_dup 2) (match_dup 3)])
521 (match_operand 1 "const_int_operand" ""))]
525 mips_gen_conditional_trap (operands);
529 ;; Match a TRAP_IF with 2nd arg of 0. The div_trap_* insns match a
530 ;; 2nd arg of any CONST_INT, so this insn must appear first.
531 ;; gen_div_trap always generates TRAP_IF with 2nd arg of 6 or 7.
534 [(trap_if (match_operator 0 "trap_cmp_op"
535 [(match_operand:SI 1 "reg_or_0_operand" "d")
536 (match_operand:SI 2 "nonmemory_operand" "dI")])
542 ;; ....................
546 ;; ....................
549 (define_insn "adddf3"
550 [(set (match_operand:DF 0 "register_operand" "=f")
551 (plus:DF (match_operand:DF 1 "register_operand" "f")
552 (match_operand:DF 2 "register_operand" "f")))]
553 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
555 [(set_attr "type" "fadd")
556 (set_attr "mode" "DF")])
558 (define_insn "addsf3"
559 [(set (match_operand:SF 0 "register_operand" "=f")
560 (plus:SF (match_operand:SF 1 "register_operand" "f")
561 (match_operand:SF 2 "register_operand" "f")))]
564 [(set_attr "type" "fadd")
565 (set_attr "mode" "SF")])
567 (define_expand "addsi3"
568 [(set (match_operand:SI 0 "register_operand" "=d")
569 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
570 (match_operand:SI 2 "arith_operand" "dI")))]
574 /* The mips16 assembler handles -32768 correctly, and so does gas,
575 but some other MIPS assemblers think that -32768 needs to be
576 loaded into a register before it can be added in. */
579 && GET_CODE (operands[2]) == CONST_INT
580 && INTVAL (operands[2]) == -32768)
581 operands[2] = force_reg (SImode, operands[2]);
584 (define_insn "addsi3_internal"
585 [(set (match_operand:SI 0 "register_operand" "=d")
586 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
587 (match_operand:SI 2 "arith_operand" "dI")))]
590 || GET_CODE (operands[2]) != CONST_INT
591 || INTVAL (operands[2]) != -32768)"
593 [(set_attr "type" "arith")
594 (set_attr "mode" "SI")])
596 ;; For the mips16, we need to recognize stack pointer additions
597 ;; explicitly, since we don't have a constraint for $sp. These insns
598 ;; will be generated by the save_restore_insns functions.
603 (match_operand:SI 0 "small_int" "I")))]
606 [(set_attr "type" "arith")
607 (set_attr "mode" "SI")
608 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
613 [(set (match_operand:SI 0 "register_operand" "=d")
615 (match_operand:SI 1 "small_int" "I")))]
618 [(set_attr "type" "arith")
619 (set_attr "mode" "SI")
620 (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
625 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
626 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
627 (match_operand:SI 2 "arith_operand" "IQ,O,d")))]
629 && (GET_CODE (operands[1]) != REG
630 || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
631 || M16_REG_P (REGNO (operands[1]))
632 || REGNO (operands[1]) == ARG_POINTER_REGNUM
633 || REGNO (operands[1]) == FRAME_POINTER_REGNUM
634 || REGNO (operands[1]) == STACK_POINTER_REGNUM)
635 && (GET_CODE (operands[2]) != REG
636 || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
637 || M16_REG_P (REGNO (operands[2]))
638 || REGNO (operands[2]) == ARG_POINTER_REGNUM
639 || REGNO (operands[2]) == FRAME_POINTER_REGNUM
640 || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
643 if (REGNO (operands[0]) == REGNO (operands[1]))
644 return \"addu\\t%0,%2\";
645 return \"addu\\t%0,%1,%2\";
647 [(set_attr "type" "arith")
648 (set_attr "mode" "SI")
649 (set_attr_alternative "length"
650 [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
653 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
659 ;; On the mips16, we can sometimes split an add of a constant which is
660 ;; a 4 byte instruction into two adds which are both 2 byte
661 ;; instructions. There are two cases: one where we are adding a
662 ;; constant plus a register to another register, and one where we are
663 ;; simply adding a constant to a register.
666 [(set (match_operand:SI 0 "register_operand" "")
667 (plus:SI (match_dup 0)
668 (match_operand:SI 1 "const_int_operand" "")))]
669 "TARGET_MIPS16 && reload_completed
670 && GET_CODE (operands[0]) == REG
671 && M16_REG_P (REGNO (operands[0]))
672 && GET_CODE (operands[1]) == CONST_INT
673 && ((INTVAL (operands[1]) > 0x7f
674 && INTVAL (operands[1]) <= 0x7f + 0x7f)
675 || (INTVAL (operands[1]) < - 0x80
676 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
677 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
678 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
681 HOST_WIDE_INT val = INTVAL (operands[1]);
685 operands[1] = GEN_INT (0x7f);
686 operands[2] = GEN_INT (val - 0x7f);
690 operands[1] = GEN_INT (- 0x80);
691 operands[2] = GEN_INT (val + 0x80);
696 [(set (match_operand:SI 0 "register_operand" "")
697 (plus:SI (match_operand:SI 1 "register_operand" "")
698 (match_operand:SI 2 "const_int_operand" "")))]
699 "TARGET_MIPS16 && reload_completed
700 && GET_CODE (operands[0]) == REG
701 && M16_REG_P (REGNO (operands[0]))
702 && GET_CODE (operands[1]) == REG
703 && M16_REG_P (REGNO (operands[1]))
704 && REGNO (operands[0]) != REGNO (operands[1])
705 && GET_CODE (operands[2]) == CONST_INT
706 && ((INTVAL (operands[2]) > 0x7
707 && INTVAL (operands[2]) <= 0x7 + 0x7f)
708 || (INTVAL (operands[2]) < - 0x8
709 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
710 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
711 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
714 HOST_WIDE_INT val = INTVAL (operands[2]);
718 operands[2] = GEN_INT (0x7);
719 operands[3] = GEN_INT (val - 0x7);
723 operands[2] = GEN_INT (- 0x8);
724 operands[3] = GEN_INT (val + 0x8);
728 (define_expand "adddi3"
729 [(parallel [(set (match_operand:DI 0 "register_operand" "")
730 (plus:DI (match_operand:DI 1 "se_register_operand" "")
731 (match_operand:DI 2 "se_arith_operand" "")))
732 (clobber (match_dup 3))])]
733 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
736 /* The mips16 assembler handles -32768 correctly, and so does gas,
737 but some other MIPS assemblers think that -32768 needs to be
738 loaded into a register before it can be added in. */
741 && GET_CODE (operands[2]) == CONST_INT
742 && INTVAL (operands[2]) == -32768)
743 operands[2] = force_reg (DImode, operands[2]);
747 emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
752 operands[3] = gen_reg_rtx (SImode);
755 (define_insn "adddi3_internal_1"
756 [(set (match_operand:DI 0 "register_operand" "=d,&d")
757 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
758 (match_operand:DI 2 "register_operand" "d,d")))
759 (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
760 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
763 return (REGNO (operands[0]) == REGNO (operands[1])
764 && REGNO (operands[0]) == REGNO (operands[2]))
765 ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
766 : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
768 [(set_attr "type" "darith")
769 (set_attr "mode" "DI")
770 (set_attr "length" "16")])
773 [(set (match_operand:DI 0 "register_operand" "")
774 (plus:DI (match_operand:DI 1 "register_operand" "")
775 (match_operand:DI 2 "register_operand" "")))
776 (clobber (match_operand:SI 3 "register_operand" ""))]
777 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
778 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
779 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
780 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
781 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
782 && (REGNO (operands[0]) != REGNO (operands[1])
783 || REGNO (operands[0]) != REGNO (operands[2]))"
785 [(set (subreg:SI (match_dup 0) 0)
786 (plus:SI (subreg:SI (match_dup 1) 0)
787 (subreg:SI (match_dup 2) 0)))
790 (ltu:SI (subreg:SI (match_dup 0) 0)
791 (subreg:SI (match_dup 2) 0)))
793 (set (subreg:SI (match_dup 0) 4)
794 (plus:SI (subreg:SI (match_dup 1) 4)
795 (subreg:SI (match_dup 2) 4)))
797 (set (subreg:SI (match_dup 0) 4)
798 (plus:SI (subreg:SI (match_dup 0) 4)
803 [(set (match_operand:DI 0 "register_operand" "")
804 (plus:DI (match_operand:DI 1 "register_operand" "")
805 (match_operand:DI 2 "register_operand" "")))
806 (clobber (match_operand:SI 3 "register_operand" ""))]
807 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
808 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
809 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
810 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
811 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
812 && (REGNO (operands[0]) != REGNO (operands[1])
813 || REGNO (operands[0]) != REGNO (operands[2]))"
815 [(set (subreg:SI (match_dup 0) 4)
816 (plus:SI (subreg:SI (match_dup 1) 4)
817 (subreg:SI (match_dup 2) 4)))
820 (ltu:SI (subreg:SI (match_dup 0) 4)
821 (subreg:SI (match_dup 2) 4)))
823 (set (subreg:SI (match_dup 0) 0)
824 (plus:SI (subreg:SI (match_dup 1) 0)
825 (subreg:SI (match_dup 2) 0)))
827 (set (subreg:SI (match_dup 0) 0)
828 (plus:SI (subreg:SI (match_dup 0) 0)
832 (define_insn "adddi3_internal_2"
833 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
834 (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
835 (match_operand:DI 2 "small_int" "P,J,N")))
836 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
837 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
839 || GET_CODE (operands[2]) != CONST_INT
840 || INTVAL (operands[2]) != -32768)"
842 addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
843 move\\t%L0,%L1\;move\\t%M0,%M1
844 subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
845 [(set_attr "type" "darith")
846 (set_attr "mode" "DI")
847 (set_attr "length" "12,8,16")])
850 [(set (match_operand:DI 0 "register_operand" "")
851 (plus:DI (match_operand:DI 1 "register_operand" "")
852 (match_operand:DI 2 "small_int" "")))
853 (clobber (match_operand:SI 3 "register_operand" "=d"))]
854 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
855 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
856 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
857 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
858 && INTVAL (operands[2]) > 0"
860 [(set (subreg:SI (match_dup 0) 0)
861 (plus:SI (subreg:SI (match_dup 1) 0)
865 (ltu:SI (subreg:SI (match_dup 0) 0)
868 (set (subreg:SI (match_dup 0) 4)
869 (plus:SI (subreg:SI (match_dup 1) 4)
874 [(set (match_operand:DI 0 "register_operand" "")
875 (plus:DI (match_operand:DI 1 "register_operand" "")
876 (match_operand:DI 2 "small_int" "")))
877 (clobber (match_operand:SI 3 "register_operand" "=d"))]
878 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
879 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
880 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
881 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
882 && INTVAL (operands[2]) > 0"
884 [(set (subreg:SI (match_dup 0) 4)
885 (plus:SI (subreg:SI (match_dup 1) 4)
889 (ltu:SI (subreg:SI (match_dup 0) 4)
892 (set (subreg:SI (match_dup 0) 0)
893 (plus:SI (subreg:SI (match_dup 1) 0)
897 (define_insn "adddi3_internal_3"
898 [(set (match_operand:DI 0 "register_operand" "=d")
899 (plus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
900 (match_operand:DI 2 "se_arith_operand" "dI")))]
904 || GET_CODE (operands[2]) != CONST_INT
905 || INTVAL (operands[2]) != -32768)"
908 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
909 ? \"dsubu\\t%0,%z1,%n2\"
910 : \"daddu\\t%0,%z1,%2\";
912 [(set_attr "type" "darith")
913 (set_attr "mode" "DI")])
915 ;; For the mips16, we need to recognize stack pointer additions
916 ;; explicitly, since we don't have a constraint for $sp. These insns
917 ;; will be generated by the save_restore_insns functions.
922 (match_operand:DI 0 "small_int" "I")))]
923 "TARGET_MIPS16 && TARGET_64BIT"
925 [(set_attr "type" "arith")
926 (set_attr "mode" "DI")
927 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
932 [(set (match_operand:DI 0 "register_operand" "=d")
934 (match_operand:DI 1 "small_int" "I")))]
935 "TARGET_MIPS16 && TARGET_64BIT"
937 [(set_attr "type" "arith")
938 (set_attr "mode" "DI")
939 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
944 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
945 (plus:DI (match_operand:DI 1 "register_operand" "0,d,d")
946 (match_operand:DI 2 "arith_operand" "IQ,O,d")))]
947 "TARGET_MIPS16 && TARGET_64BIT
948 && (GET_CODE (operands[1]) != REG
949 || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
950 || M16_REG_P (REGNO (operands[1]))
951 || REGNO (operands[1]) == ARG_POINTER_REGNUM
952 || REGNO (operands[1]) == FRAME_POINTER_REGNUM
953 || REGNO (operands[1]) == STACK_POINTER_REGNUM)
954 && (GET_CODE (operands[2]) != REG
955 || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
956 || M16_REG_P (REGNO (operands[2]))
957 || REGNO (operands[2]) == ARG_POINTER_REGNUM
958 || REGNO (operands[2]) == FRAME_POINTER_REGNUM
959 || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
962 if (REGNO (operands[0]) == REGNO (operands[1]))
963 return \"daddu\\t%0,%2\";
964 return \"daddu\\t%0,%1,%2\";
966 [(set_attr "type" "arith")
967 (set_attr "mode" "DI")
968 (set_attr_alternative "length"
969 [(if_then_else (match_operand:VOID 2 "m16_simm5_1" "")
972 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
978 ;; On the mips16, we can sometimes split an add of a constant which is
979 ;; a 4 byte instruction into two adds which are both 2 byte
980 ;; instructions. There are two cases: one where we are adding a
981 ;; constant plus a register to another register, and one where we are
982 ;; simply adding a constant to a register.
985 [(set (match_operand:DI 0 "register_operand" "")
986 (plus:DI (match_dup 0)
987 (match_operand:DI 1 "const_int_operand" "")))]
988 "TARGET_MIPS16 && TARGET_64BIT && reload_completed
989 && GET_CODE (operands[0]) == REG
990 && M16_REG_P (REGNO (operands[0]))
991 && GET_CODE (operands[1]) == CONST_INT
992 && ((INTVAL (operands[1]) > 0xf
993 && INTVAL (operands[1]) <= 0xf + 0xf)
994 || (INTVAL (operands[1]) < - 0x10
995 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
996 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
997 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1000 HOST_WIDE_INT val = INTVAL (operands[1]);
1004 operands[1] = GEN_INT (0xf);
1005 operands[2] = GEN_INT (val - 0xf);
1009 operands[1] = GEN_INT (- 0x10);
1010 operands[2] = GEN_INT (val + 0x10);
1015 [(set (match_operand:DI 0 "register_operand" "")
1016 (plus:DI (match_operand:DI 1 "register_operand" "")
1017 (match_operand:DI 2 "const_int_operand" "")))]
1018 "TARGET_MIPS16 && TARGET_64BIT && reload_completed
1019 && GET_CODE (operands[0]) == REG
1020 && M16_REG_P (REGNO (operands[0]))
1021 && GET_CODE (operands[1]) == REG
1022 && M16_REG_P (REGNO (operands[1]))
1023 && REGNO (operands[0]) != REGNO (operands[1])
1024 && GET_CODE (operands[2]) == CONST_INT
1025 && ((INTVAL (operands[2]) > 0x7
1026 && INTVAL (operands[2]) <= 0x7 + 0xf)
1027 || (INTVAL (operands[2]) < - 0x8
1028 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1029 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1030 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1033 HOST_WIDE_INT val = INTVAL (operands[2]);
1037 operands[2] = GEN_INT (0x7);
1038 operands[3] = GEN_INT (val - 0x7);
1042 operands[2] = GEN_INT (- 0x8);
1043 operands[3] = GEN_INT (val + 0x8);
1047 (define_insn "addsi3_internal_2"
1048 [(set (match_operand:DI 0 "register_operand" "=d")
1049 (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1050 (match_operand:SI 2 "arith_operand" "dI"))))]
1054 || GET_CODE (operands[2]) != CONST_INT
1055 || INTVAL (operands[2]) != -32768)"
1058 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1059 ? \"subu\\t%0,%z1,%n2\"
1060 : \"addu\\t%0,%z1,%2\";
1062 [(set_attr "type" "arith")
1063 (set_attr "mode" "SI")])
1066 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1067 (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1068 (match_operand:SI 2 "arith_operand" "I,O,d"))))]
1069 "TARGET_MIPS16 && TARGET_64BIT"
1072 if (REGNO (operands[0]) == REGNO (operands[1]))
1073 return \"addu\\t%0,%2\";
1074 return \"addu\\t%0,%1,%2\";
1076 [(set_attr "type" "arith")
1077 (set_attr "mode" "SI")
1078 (set_attr_alternative "length"
1079 [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
1082 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
1089 ;; ....................
1093 ;; ....................
1096 (define_insn "subdf3"
1097 [(set (match_operand:DF 0 "register_operand" "=f")
1098 (minus:DF (match_operand:DF 1 "register_operand" "f")
1099 (match_operand:DF 2 "register_operand" "f")))]
1100 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1102 [(set_attr "type" "fadd")
1103 (set_attr "mode" "DF")])
1105 (define_insn "subsf3"
1106 [(set (match_operand:SF 0 "register_operand" "=f")
1107 (minus:SF (match_operand:SF 1 "register_operand" "f")
1108 (match_operand:SF 2 "register_operand" "f")))]
1111 [(set_attr "type" "fadd")
1112 (set_attr "mode" "SF")])
1114 (define_expand "subsi3"
1115 [(set (match_operand:SI 0 "register_operand" "=d")
1116 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1117 (match_operand:SI 2 "arith_operand" "dI")))]
1121 if (GET_CODE (operands[2]) == CONST_INT
1122 && (INTVAL (operands[2]) == -32768
1124 && INTVAL (operands[2]) == -0x4000)))
1125 operands[2] = force_reg (SImode, operands[2]);
1128 (define_insn "subsi3_internal"
1129 [(set (match_operand:SI 0 "register_operand" "=d")
1130 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1131 (match_operand:SI 2 "arith_operand" "dI")))]
1133 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1135 [(set_attr "type" "arith")
1136 (set_attr "mode" "SI")])
1138 ;; For the mips16, we need to recognize stack pointer subtractions
1139 ;; explicitly, since we don't have a constraint for $sp. These insns
1140 ;; will be generated by the save_restore_insns functions.
1144 (minus:SI (reg:SI 29)
1145 (match_operand:SI 0 "small_int" "I")))]
1147 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1149 [(set_attr "type" "arith")
1150 (set_attr "mode" "SI")
1151 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
1156 [(set (match_operand:SI 0 "register_operand" "=d")
1157 (minus:SI (reg:SI 29)
1158 (match_operand:SI 1 "small_int" "I")))]
1160 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1162 [(set_attr "type" "arith")
1163 (set_attr "mode" "SI")
1164 (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_nuimm8_4" "")
1170 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1171 (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1172 (match_operand:SI 2 "arith_operand" "I,O,d")))]
1174 && (GET_CODE (operands[2]) != CONST_INT
1175 || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
1178 if (REGNO (operands[0]) == REGNO (operands[1]))
1179 return \"subu\\t%0,%2\";
1180 return \"subu\\t%0,%1,%2\";
1182 [(set_attr "type" "arith")
1183 (set_attr "mode" "SI")
1184 (set_attr_alternative "length"
1185 [(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
1188 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
1193 ;; On the mips16, we can sometimes split an subtract of a constant
1194 ;; which is a 4 byte instruction into two adds which are both 2 byte
1195 ;; instructions. There are two cases: one where we are setting a
1196 ;; register to a register minus a constant, and one where we are
1197 ;; simply subtracting a constant from a register.
1200 [(set (match_operand:SI 0 "register_operand" "")
1201 (minus:SI (match_dup 0)
1202 (match_operand:SI 1 "const_int_operand" "")))]
1203 "TARGET_MIPS16 && reload_completed
1204 && GET_CODE (operands[0]) == REG
1205 && M16_REG_P (REGNO (operands[0]))
1206 && GET_CODE (operands[1]) == CONST_INT
1207 && ((INTVAL (operands[1]) > 0x80
1208 && INTVAL (operands[1]) <= 0x80 + 0x80)
1209 || (INTVAL (operands[1]) < - 0x7f
1210 && INTVAL (operands[1]) >= - 0x7f - 0x7f))"
1211 [(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 1)))
1212 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1215 HOST_WIDE_INT val = INTVAL (operands[1]);
1219 operands[1] = GEN_INT (0x80);
1220 operands[2] = GEN_INT (val - 0x80);
1224 operands[1] = GEN_INT (- 0x7f);
1225 operands[2] = GEN_INT (val + 0x7f);
1230 [(set (match_operand:SI 0 "register_operand" "")
1231 (minus:SI (match_operand:SI 1 "register_operand" "")
1232 (match_operand:SI 2 "const_int_operand" "")))]
1233 "TARGET_MIPS16 && reload_completed
1234 && GET_CODE (operands[0]) == REG
1235 && M16_REG_P (REGNO (operands[0]))
1236 && GET_CODE (operands[1]) == REG
1237 && M16_REG_P (REGNO (operands[1]))
1238 && REGNO (operands[0]) != REGNO (operands[1])
1239 && GET_CODE (operands[2]) == CONST_INT
1240 && ((INTVAL (operands[2]) > 0x8
1241 && INTVAL (operands[2]) <= 0x8 + 0x80)
1242 || (INTVAL (operands[2]) < - 0x7
1243 && INTVAL (operands[2]) >= - 0x7 - 0x7f))"
1244 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1245 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 3)))]
1248 HOST_WIDE_INT val = INTVAL (operands[2]);
1252 operands[2] = GEN_INT (0x8);
1253 operands[3] = GEN_INT (val - 0x8);
1257 operands[2] = GEN_INT (- 0x7);
1258 operands[3] = GEN_INT (val + 0x7);
1262 (define_expand "subdi3"
1263 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
1264 (minus:DI (match_operand:DI 1 "se_register_operand" "d")
1265 (match_operand:DI 2 "se_register_operand" "d")))
1266 (clobber (match_dup 3))])]
1267 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
1272 emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
1277 operands[3] = gen_reg_rtx (SImode);
1280 (define_insn "subdi3_internal"
1281 [(set (match_operand:DI 0 "register_operand" "=d")
1282 (minus:DI (match_operand:DI 1 "register_operand" "d")
1283 (match_operand:DI 2 "register_operand" "d")))
1284 (clobber (match_operand:SI 3 "register_operand" "=d"))]
1285 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
1286 "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
1287 [(set_attr "type" "darith")
1288 (set_attr "mode" "DI")
1289 (set_attr "length" "16")])
1292 [(set (match_operand:DI 0 "register_operand" "")
1293 (minus:DI (match_operand:DI 1 "register_operand" "")
1294 (match_operand:DI 2 "register_operand" "")))
1295 (clobber (match_operand:SI 3 "register_operand" ""))]
1296 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
1297 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1298 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1299 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1300 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1303 (ltu:SI (subreg:SI (match_dup 1) 0)
1304 (subreg:SI (match_dup 2) 0)))
1306 (set (subreg:SI (match_dup 0) 0)
1307 (minus:SI (subreg:SI (match_dup 1) 0)
1308 (subreg:SI (match_dup 2) 0)))
1310 (set (subreg:SI (match_dup 0) 4)
1311 (minus:SI (subreg:SI (match_dup 1) 4)
1312 (subreg:SI (match_dup 2) 4)))
1314 (set (subreg:SI (match_dup 0) 4)
1315 (minus:SI (subreg:SI (match_dup 0) 4)
1320 [(set (match_operand:DI 0 "register_operand" "")
1321 (minus:DI (match_operand:DI 1 "register_operand" "")
1322 (match_operand:DI 2 "register_operand" "")))
1323 (clobber (match_operand:SI 3 "register_operand" ""))]
1324 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
1325 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1326 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1327 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1328 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1331 (ltu:SI (subreg:SI (match_dup 1) 4)
1332 (subreg:SI (match_dup 2) 4)))
1334 (set (subreg:SI (match_dup 0) 4)
1335 (minus:SI (subreg:SI (match_dup 1) 4)
1336 (subreg:SI (match_dup 2) 4)))
1338 (set (subreg:SI (match_dup 0) 0)
1339 (minus:SI (subreg:SI (match_dup 1) 0)
1340 (subreg:SI (match_dup 2) 0)))
1342 (set (subreg:SI (match_dup 0) 0)
1343 (minus:SI (subreg:SI (match_dup 0) 0)
1347 (define_insn "subdi3_internal_2"
1348 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1349 (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
1350 (match_operand:DI 2 "small_int" "P,J,N")))
1351 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
1352 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1353 && INTVAL (operands[2]) != -32768"
1355 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
1356 move\\t%L0,%L1\;move\\t%M0,%M1
1357 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
1358 [(set_attr "type" "darith")
1359 (set_attr "mode" "DI")
1360 (set_attr "length" "12,8,16")])
1363 [(set (match_operand:DI 0 "register_operand" "")
1364 (minus:DI (match_operand:DI 1 "register_operand" "")
1365 (match_operand:DI 2 "small_int" "")))
1366 (clobber (match_operand:SI 3 "register_operand" ""))]
1367 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
1368 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1369 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1370 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1371 && INTVAL (operands[2]) > 0"
1374 (ltu:SI (subreg:SI (match_dup 1) 0)
1377 (set (subreg:SI (match_dup 0) 0)
1378 (minus:SI (subreg:SI (match_dup 1) 0)
1381 (set (subreg:SI (match_dup 0) 4)
1382 (minus:SI (subreg:SI (match_dup 1) 4)
1387 [(set (match_operand:DI 0 "register_operand" "")
1388 (minus:DI (match_operand:DI 1 "register_operand" "")
1389 (match_operand:DI 2 "small_int" "")))
1390 (clobber (match_operand:SI 3 "register_operand" ""))]
1391 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
1392 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1393 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1394 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1395 && INTVAL (operands[2]) > 0"
1398 (ltu:SI (subreg:SI (match_dup 1) 4)
1401 (set (subreg:SI (match_dup 0) 4)
1402 (minus:SI (subreg:SI (match_dup 1) 4)
1405 (set (subreg:SI (match_dup 0) 0)
1406 (minus:SI (subreg:SI (match_dup 1) 0)
1410 (define_insn "subdi3_internal_3"
1411 [(set (match_operand:DI 0 "register_operand" "=d")
1412 (minus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
1413 (match_operand:DI 2 "se_arith_operand" "dI")))]
1414 "TARGET_64BIT && !TARGET_MIPS16
1415 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1418 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1419 ? \"daddu\\t%0,%z1,%n2\"
1420 : \"dsubu\\t%0,%z1,%2\";
1422 [(set_attr "type" "darith")
1423 (set_attr "mode" "DI")])
1425 ;; For the mips16, we need to recognize stack pointer subtractions
1426 ;; explicitly, since we don't have a constraint for $sp. These insns
1427 ;; will be generated by the save_restore_insns functions.
1431 (minus:DI (reg:DI 29)
1432 (match_operand:DI 0 "small_int" "I")))]
1434 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1436 [(set_attr "type" "arith")
1437 (set_attr "mode" "DI")
1438 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
1443 [(set (match_operand:DI 0 "register_operand" "=d")
1444 (minus:DI (reg:DI 29)
1445 (match_operand:DI 1 "small_int" "I")))]
1447 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1449 [(set_attr "type" "arith")
1450 (set_attr "mode" "DI")
1451 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nuimm5_4" "")
1456 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1457 (minus:DI (match_operand:DI 1 "register_operand" "0,d,d")
1458 (match_operand:DI 2 "arith_operand" "I,O,d")))]
1460 && (GET_CODE (operands[2]) != CONST_INT
1461 || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
1464 if (REGNO (operands[0]) == REGNO (operands[1]))
1465 return \"dsubu\\t%0,%2\";
1466 return \"dsubu\\t%0,%1,%2\";
1468 [(set_attr "type" "arith")
1469 (set_attr "mode" "DI")
1470 (set_attr_alternative "length"
1471 [(if_then_else (match_operand:VOID 2 "m16_nsimm5_1" "")
1474 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
1479 ;; On the mips16, we can sometimes split an add of a constant which is
1480 ;; a 4 byte instruction into two adds which are both 2 byte
1481 ;; instructions. There are two cases: one where we are adding a
1482 ;; constant plus a register to another register, and one where we are
1483 ;; simply adding a constant to a register.
1486 [(set (match_operand:DI 0 "register_operand" "")
1487 (minus:DI (match_dup 0)
1488 (match_operand:DI 1 "const_int_operand" "")))]
1489 "TARGET_MIPS16 && TARGET_64BIT && reload_completed
1490 && GET_CODE (operands[0]) == REG
1491 && M16_REG_P (REGNO (operands[0]))
1492 && GET_CODE (operands[1]) == CONST_INT
1493 && ((INTVAL (operands[1]) > 0x10
1494 && INTVAL (operands[1]) <= 0x10 + 0x10)
1495 || (INTVAL (operands[1]) < - 0xf
1496 && INTVAL (operands[1]) >= - 0xf - 0xf))"
1497 [(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 1)))
1498 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
1501 HOST_WIDE_INT val = INTVAL (operands[1]);
1505 operands[1] = GEN_INT (0xf);
1506 operands[2] = GEN_INT (val - 0xf);
1510 operands[1] = GEN_INT (- 0x10);
1511 operands[2] = GEN_INT (val + 0x10);
1516 [(set (match_operand:DI 0 "register_operand" "")
1517 (minus:DI (match_operand:DI 1 "register_operand" "")
1518 (match_operand:DI 2 "const_int_operand" "")))]
1519 "TARGET_MIPS16 && TARGET_64BIT && reload_completed
1520 && GET_CODE (operands[0]) == REG
1521 && M16_REG_P (REGNO (operands[0]))
1522 && GET_CODE (operands[1]) == REG
1523 && M16_REG_P (REGNO (operands[1]))
1524 && REGNO (operands[0]) != REGNO (operands[1])
1525 && GET_CODE (operands[2]) == CONST_INT
1526 && ((INTVAL (operands[2]) > 0x8
1527 && INTVAL (operands[2]) <= 0x8 + 0x10)
1528 || (INTVAL (operands[2]) < - 0x7
1529 && INTVAL (operands[2]) >= - 0x7 - 0xf))"
1530 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
1531 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
1534 HOST_WIDE_INT val = INTVAL (operands[2]);
1538 operands[2] = GEN_INT (0x8);
1539 operands[3] = GEN_INT (val - 0x8);
1543 operands[2] = GEN_INT (- 0x7);
1544 operands[3] = GEN_INT (val + 0x7);
1548 (define_insn "subsi3_internal_2"
1549 [(set (match_operand:DI 0 "register_operand" "=d")
1550 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1551 (match_operand:SI 2 "arith_operand" "dI"))))]
1552 "TARGET_64BIT && !TARGET_MIPS16
1553 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1556 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1557 ? \"addu\\t%0,%z1,%n2\"
1558 : \"subu\\t%0,%z1,%2\";
1560 [(set_attr "type" "arith")
1561 (set_attr "mode" "DI")])
1564 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1565 (sign_extend:DI (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1566 (match_operand:SI 2 "arith_operand" "I,O,d"))))]
1567 "TARGET_64BIT && TARGET_MIPS16
1568 && (GET_CODE (operands[2]) != CONST_INT
1569 || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
1572 if (REGNO (operands[0]) == REGNO (operands[1]))
1573 return \"subu\\t%0,%2\";
1574 return \"subu\\t%0,%1,%2\";
1576 [(set_attr "type" "arith")
1577 (set_attr "mode" "SI")
1578 (set_attr_alternative "length"
1579 [(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
1582 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
1590 ;; ....................
1594 ;; ....................
1597 ;; Early Vr4300 silicon has a CPU bug where multiplies with certain
1598 ;; operands may corrupt immediately following multiplies. This is a
1599 ;; simple fix to insert NOPs.
1601 (define_expand "muldf3"
1602 [(set (match_operand:DF 0 "register_operand" "=f")
1603 (mult:DF (match_operand:DF 1 "register_operand" "f")
1604 (match_operand:DF 2 "register_operand" "f")))]
1605 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1608 if (mips_cpu != PROCESSOR_R4300)
1609 emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
1611 emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
1615 (define_insn "muldf3_internal"
1616 [(set (match_operand:DF 0 "register_operand" "=f")
1617 (mult:DF (match_operand:DF 1 "register_operand" "f")
1618 (match_operand:DF 2 "register_operand" "f")))]
1619 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300"
1621 [(set_attr "type" "fmul")
1622 (set_attr "mode" "DF")])
1624 (define_insn "muldf3_r4300"
1625 [(set (match_operand:DF 0 "register_operand" "=f")
1626 (mult:DF (match_operand:DF 1 "register_operand" "f")
1627 (match_operand:DF 2 "register_operand" "f")))]
1628 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300"
1631 output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
1632 if (TARGET_4300_MUL_FIX)
1633 output_asm_insn (\"nop\", operands);
1636 [(set_attr "type" "fmul")
1637 (set_attr "mode" "DF")
1638 (set_attr "length" "8")]) ;; mul.d + nop
1640 (define_expand "mulsf3"
1641 [(set (match_operand:SF 0 "register_operand" "=f")
1642 (mult:SF (match_operand:SF 1 "register_operand" "f")
1643 (match_operand:SF 2 "register_operand" "f")))]
1647 if (mips_cpu != PROCESSOR_R4300)
1648 emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
1650 emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
1654 (define_insn "mulsf3_internal"
1655 [(set (match_operand:SF 0 "register_operand" "=f")
1656 (mult:SF (match_operand:SF 1 "register_operand" "f")
1657 (match_operand:SF 2 "register_operand" "f")))]
1658 "TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300"
1660 [(set_attr "type" "fmul")
1661 (set_attr "mode" "SF")])
1663 (define_insn "mulsf3_r4300"
1664 [(set (match_operand:SF 0 "register_operand" "=f")
1665 (mult:SF (match_operand:SF 1 "register_operand" "f")
1666 (match_operand:SF 2 "register_operand" "f")))]
1667 "TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300"
1670 output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
1671 if (TARGET_4300_MUL_FIX)
1672 output_asm_insn (\"nop\", operands);
1675 [(set_attr "type" "fmul")
1676 (set_attr "mode" "SF")
1677 (set_attr "length" "8")]) ;; mul.s + nop
1680 ;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
1681 ;; a multiply is in progress, it may give an incorrect result. Avoid
1682 ;; this by keeping the mflo with the mult on the R4000.
1684 (define_expand "mulsi3"
1685 [(set (match_operand:SI 0 "register_operand" "=l")
1686 (mult:SI (match_operand:SI 1 "register_operand" "d")
1687 (match_operand:SI 2 "register_operand" "d")))
1688 (clobber (match_scratch:SI 3 "=h"))
1689 (clobber (match_scratch:SI 4 "=a"))]
1693 if (HAVE_mulsi3_mult3)
1694 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1695 else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16)
1696 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1698 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1702 (define_insn "mulsi3_mult3"
1703 [(set (match_operand:SI 0 "register_operand" "=d,l")
1704 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1705 (match_operand:SI 2 "register_operand" "d,d")))
1706 (clobber (match_scratch:SI 3 "=h,h"))
1707 (clobber (match_scratch:SI 4 "=l,X"))
1708 (clobber (match_scratch:SI 5 "=a,a"))]
1713 if (which_alternative == 1)
1714 return \"mult\\t%1,%2\";
1716 return \"mul\\t%0,%1,%2\";
1717 return \"mult\\t%0,%1,%2\";
1719 [(set_attr "type" "imul")
1720 (set_attr "mode" "SI")])
1722 (define_insn "mulsi3_internal"
1723 [(set (match_operand:SI 0 "register_operand" "=l")
1724 (mult:SI (match_operand:SI 1 "register_operand" "d")
1725 (match_operand:SI 2 "register_operand" "d")))
1726 (clobber (match_scratch:SI 3 "=h"))
1727 (clobber (match_scratch:SI 4 "=a"))]
1728 "mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16"
1730 [(set_attr "type" "imul")
1731 (set_attr "mode" "SI")])
1733 (define_insn "mulsi3_r4000"
1734 [(set (match_operand:SI 0 "register_operand" "=d")
1735 (mult:SI (match_operand:SI 1 "register_operand" "d")
1736 (match_operand:SI 2 "register_operand" "d")))
1737 (clobber (match_scratch:SI 3 "=h"))
1738 (clobber (match_scratch:SI 4 "=l"))
1739 (clobber (match_scratch:SI 5 "=a"))]
1740 "mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16"
1745 xoperands[0] = operands[0];
1746 xoperands[1] = gen_rtx_REG (SImode, LO_REGNUM);
1748 output_asm_insn (\"mult\\t%1,%2\", operands);
1749 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1752 [(set_attr "type" "imul")
1753 (set_attr "mode" "SI")
1754 (set_attr "length" "12")]) ;; mult + mflo + delay
1756 ;; Multiply-accumulate patterns
1758 ;; For processors that can copy the output to a general register:
1760 ;; The all-d alternative is needed because the combiner will find this
1761 ;; pattern and then register alloc/reload will move registers around to
1762 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1764 ;; The last alternative should be made slightly less desirable, but adding
1765 ;; "?" to the constraint is too strong, and causes values to be loaded into
1766 ;; LO even when that's more costly. For now, using "*d" mostly does the
1768 (define_insn "*mul_acc_si"
1769 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1770 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1771 (match_operand:SI 2 "register_operand" "d,d,d"))
1772 (match_operand:SI 3 "register_operand" "0,l,*d")))
1773 (clobber (match_scratch:SI 4 "=h,h,h"))
1774 (clobber (match_scratch:SI 5 "=X,3,l"))
1775 (clobber (match_scratch:SI 6 "=a,a,a"))
1776 (clobber (match_scratch:SI 7 "=X,X,d"))]
1781 static const char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" };
1782 if (which_alternative == 2)
1784 return madd[which_alternative];
1786 [(set_attr "type" "imul,imul,multi")
1787 (set_attr "mode" "SI")
1788 (set_attr "length" "4,4,8")])
1790 ;; Split the above insn if we failed to get LO allocated.
1792 [(set (match_operand:SI 0 "register_operand" "")
1793 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1794 (match_operand:SI 2 "register_operand" ""))
1795 (match_operand:SI 3 "register_operand" "")))
1796 (clobber (match_scratch:SI 4 ""))
1797 (clobber (match_scratch:SI 5 ""))
1798 (clobber (match_scratch:SI 6 ""))
1799 (clobber (match_scratch:SI 7 ""))]
1800 "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[3]))"
1801 [(parallel [(set (match_dup 7)
1802 (mult:SI (match_dup 1) (match_dup 2)))
1803 (clobber (match_dup 4))
1804 (clobber (match_dup 5))
1805 (clobber (match_dup 6))])
1806 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 3)))]
1810 [(set (match_operand:SI 0 "register_operand" "")
1811 (minus:SI (match_operand:SI 1 "register_operand" "")
1812 (mult:SI (match_operand:SI 2 "register_operand" "")
1813 (match_operand:SI 3 "register_operand" ""))))
1814 (clobber (match_scratch:SI 4 ""))
1815 (clobber (match_scratch:SI 5 ""))
1816 (clobber (match_scratch:SI 6 ""))
1817 (clobber (match_scratch:SI 7 ""))]
1818 "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[1]))"
1819 [(parallel [(set (match_dup 7)
1820 (mult:SI (match_dup 2) (match_dup 3)))
1821 (clobber (match_dup 4))
1822 (clobber (match_dup 5))
1823 (clobber (match_dup 6))])
1824 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))]
1827 (define_expand "muldi3"
1828 [(set (match_operand:DI 0 "register_operand" "=l")
1829 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
1830 (match_operand:DI 2 "register_operand" "d")))
1831 (clobber (match_scratch:DI 3 "=h"))
1832 (clobber (match_scratch:DI 4 "=a"))]
1837 if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)
1838 emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
1840 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1844 ;; Don't accept both operands using se_register_operand, because if
1845 ;; both operands are sign extended we would prefer to use mult in the
1846 ;; mulsidi3 pattern. Commutativity should permit either operand to be
1849 (define_insn "muldi3_internal"
1850 [(set (match_operand:DI 0 "register_operand" "=l")
1851 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
1852 (match_operand:DI 2 "register_operand" "d")))
1853 (clobber (match_scratch:DI 3 "=h"))
1854 (clobber (match_scratch:DI 4 "=a"))]
1855 "TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16"
1857 [(set_attr "type" "imul")
1858 (set_attr "mode" "DI")])
1860 (define_insn "muldi3_internal2"
1861 [(set (match_operand:DI 0 "register_operand" "=d")
1862 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
1863 (match_operand:DI 2 "register_operand" "d")))
1864 (clobber (match_scratch:DI 3 "=h"))
1865 (clobber (match_scratch:DI 4 "=l"))
1866 (clobber (match_scratch:DI 5 "=a"))]
1867 "TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)"
1871 output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
1876 xoperands[0] = operands[0];
1877 xoperands[1] = gen_rtx_REG (DImode, LO_REGNUM);
1879 output_asm_insn (\"dmult\\t%1,%2\", operands);
1880 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1884 [(set_attr "type" "imul")
1885 (set_attr "mode" "DI")
1886 (set (attr "length")
1887 (if_then_else (ne (symbol_ref "GENERATE_MULT3") (const_int 0))
1889 (const_int 12)))]) ;; mult + mflo + delay
1891 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1893 (define_expand "mulsidi3"
1894 [(set (match_operand:DI 0 "register_operand" "=x")
1895 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1896 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1900 rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
1902 emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
1905 emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
1910 (define_expand "umulsidi3"
1911 [(set (match_operand:DI 0 "register_operand" "=x")
1912 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1913 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1917 rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
1919 emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
1922 emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
1927 (define_insn "mulsidi3_internal"
1928 [(set (match_operand:DI 0 "register_operand" "=x")
1929 (mult:DI (match_operator:DI 3 "extend_operator"
1930 [(match_operand:SI 1 "register_operand" "d")])
1931 (match_operator:DI 4 "extend_operator"
1932 [(match_operand:SI 2 "register_operand" "d")])))
1933 (clobber (match_scratch:SI 5 "=a"))]
1934 "!TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
1937 if (GET_CODE (operands[3]) == SIGN_EXTEND)
1938 return \"mult\\t%1,%2\";
1939 return \"multu\\t%1,%2\";
1941 [(set_attr "type" "imul")
1942 (set_attr "mode" "SI")])
1944 (define_insn "mulsidi3_64bit"
1945 [(set (match_operand:DI 0 "register_operand" "=a")
1946 (mult:DI (match_operator:DI 3 "extend_operator"
1947 [(match_operand:SI 1 "register_operand" "d")])
1948 (match_operator:DI 4 "extend_operator"
1949 [(match_operand:SI 2 "register_operand" "d")])))
1950 (clobber (match_scratch:DI 5 "=l"))
1951 (clobber (match_scratch:DI 6 "=h"))]
1952 "TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
1955 if (GET_CODE (operands[3]) == SIGN_EXTEND)
1956 return \"mult\\t%1,%2\";
1957 return \"multu\\t%1,%2\";
1959 [(set_attr "type" "imul")
1960 (set_attr "mode" "SI")])
1962 ;; _highpart patterns
1963 (define_expand "smulsi3_highpart"
1964 [(set (match_operand:SI 0 "register_operand" "=h")
1966 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1967 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
1972 rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
1973 rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
1974 #ifndef NO_MD_PROTOTYPES
1975 rtx (*genfn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
1979 genfn = gen_xmulsi3_highpart_internal;
1980 emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
1985 (define_expand "umulsi3_highpart"
1986 [(set (match_operand:SI 0 "register_operand" "=h")
1988 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1989 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
1994 rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
1995 rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
1996 #ifndef NO_MD_PROTOTYPES
1997 rtx (*genfn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
2001 genfn = gen_xmulsi3_highpart_internal;
2002 emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
2007 (define_insn "xmulsi3_highpart_internal"
2008 [(set (match_operand:SI 0 "register_operand" "=h")
2010 (match_operator:DI 5 "highpart_shift_operator"
2011 [(mult:DI (match_operator:DI 3 "extend_operator"
2012 [(match_operand:SI 1 "register_operand" "d")])
2013 (match_operator:DI 4 "extend_operator"
2014 [(match_operand:SI 2 "register_operand" "d")]))
2016 (clobber (match_scratch:SI 6 "=l"))
2017 (clobber (match_scratch:SI 7 "=a"))]
2018 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
2021 if (GET_CODE (operands[3]) == SIGN_EXTEND)
2022 return \"mult\\t%1,%2\";
2024 return \"multu\\t%1,%2\";
2026 [(set_attr "type" "imul")
2027 (set_attr "mode" "SI")])
2029 (define_insn "smuldi3_highpart"
2030 [(set (match_operand:DI 0 "register_operand" "=h")
2032 (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
2033 (sign_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
2035 (clobber (match_scratch:DI 3 "=l"))
2036 (clobber (match_scratch:DI 4 "=a"))]
2039 [(set_attr "type" "imul")
2040 (set_attr "mode" "DI")])
2042 (define_insn "umuldi3_highpart"
2043 [(set (match_operand:DI 0 "register_operand" "=h")
2045 (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
2046 (zero_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
2048 (clobber (match_scratch:DI 3 "=l"))
2049 (clobber (match_scratch:DI 4 "=a"))]
2052 [(set_attr "type" "imul")
2053 (set_attr "mode" "DI")])
2055 ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
2056 ;; instruction. The HI/LO registers are used as a 64 bit accumulator.
2058 (define_insn "madsi"
2059 [(set (match_operand:SI 0 "register_operand" "+l")
2060 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2061 (match_operand:SI 2 "register_operand" "d"))
2063 (clobber (match_scratch:SI 3 "=h"))
2064 (clobber (match_scratch:SI 4 "=a"))]
2067 [(set_attr "type" "imul")
2068 (set_attr "mode" "SI")])
2070 (define_insn "*mul_acc_di"
2071 [(set (match_operand:DI 0 "register_operand" "+x")
2072 (plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
2073 [(match_operand:SI 1 "register_operand" "d")])
2074 (match_operator:DI 4 "extend_operator"
2075 [(match_operand:SI 2 "register_operand" "d")]))
2077 (clobber (match_scratch:SI 5 "=a"))]
2080 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
2083 if (GET_CODE (operands[3]) == SIGN_EXTEND)
2084 return \"mad\\t%1,%2\";
2086 return \"madu\\t%1,%2\";
2088 [(set_attr "type" "imul")
2089 (set_attr "mode" "SI")])
2091 (define_insn "*mul_acc_64bit_di"
2092 [(set (match_operand:DI 0 "register_operand" "+a")
2093 (plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
2094 [(match_operand:SI 1 "register_operand" "d")])
2095 (match_operator:DI 4 "extend_operator"
2096 [(match_operand:SI 2 "register_operand" "d")]))
2098 (clobber (match_scratch:SI 5 "=h"))
2099 (clobber (match_scratch:SI 6 "=l"))]
2102 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
2105 if (GET_CODE (operands[3]) == SIGN_EXTEND)
2106 return \"mad\\t%1,%2\";
2108 return \"madu\\t%1,%2\";
2110 [(set_attr "type" "imul")
2111 (set_attr "mode" "SI")])
2113 ;; Floating point multiply accumulate instructions.
2116 [(set (match_operand:DF 0 "register_operand" "=f")
2117 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2118 (match_operand:DF 2 "register_operand" "f"))
2119 (match_operand:DF 3 "register_operand" "f")))]
2120 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2121 "madd.d\\t%0,%3,%1,%2"
2122 [(set_attr "type" "fmadd")
2123 (set_attr "mode" "DF")])
2126 [(set (match_operand:SF 0 "register_operand" "=f")
2127 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2128 (match_operand:SF 2 "register_operand" "f"))
2129 (match_operand:SF 3 "register_operand" "f")))]
2130 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
2131 "madd.s\\t%0,%3,%1,%2"
2132 [(set_attr "type" "fmadd")
2133 (set_attr "mode" "SF")])
2136 [(set (match_operand:DF 0 "register_operand" "=f")
2137 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2138 (match_operand:DF 2 "register_operand" "f"))
2139 (match_operand:DF 3 "register_operand" "f")))]
2140 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2141 "msub.d\\t%0,%3,%1,%2"
2142 [(set_attr "type" "fmadd")
2143 (set_attr "mode" "DF")])
2146 [(set (match_operand:SF 0 "register_operand" "=f")
2147 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2148 (match_operand:SF 2 "register_operand" "f"))
2149 (match_operand:SF 3 "register_operand" "f")))]
2151 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
2152 "msub.s\\t%0,%3,%1,%2"
2153 [(set_attr "type" "fmadd")
2154 (set_attr "mode" "SF")])
2157 [(set (match_operand:DF 0 "register_operand" "=f")
2158 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2159 (match_operand:DF 2 "register_operand" "f"))
2160 (match_operand:DF 3 "register_operand" "f"))))]
2161 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2162 "nmadd.d\\t%0,%3,%1,%2"
2163 [(set_attr "type" "fmadd")
2164 (set_attr "mode" "DF")])
2167 [(set (match_operand:SF 0 "register_operand" "=f")
2168 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2169 (match_operand:SF 2 "register_operand" "f"))
2170 (match_operand:SF 3 "register_operand" "f"))))]
2171 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
2172 "nmadd.s\\t%0,%3,%1,%2"
2173 [(set_attr "type" "fmadd")
2174 (set_attr "mode" "SF")])
2177 [(set (match_operand:DF 0 "register_operand" "=f")
2178 (minus:DF (match_operand:DF 1 "register_operand" "f")
2179 (mult:DF (match_operand:DF 2 "register_operand" "f")
2180 (match_operand:DF 3 "register_operand" "f"))))]
2181 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2182 "nmsub.d\\t%0,%1,%2,%3"
2183 [(set_attr "type" "fmadd")
2184 (set_attr "mode" "DF")])
2187 [(set (match_operand:SF 0 "register_operand" "=f")
2188 (minus:SF (match_operand:SF 1 "register_operand" "f")
2189 (mult:SF (match_operand:SF 2 "register_operand" "f")
2190 (match_operand:SF 3 "register_operand" "f"))))]
2191 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
2192 "nmsub.s\\t%0,%1,%2,%3"
2193 [(set_attr "type" "fmadd")
2194 (set_attr "mode" "SF")])
2197 ;; ....................
2199 ;; DIVISION and REMAINDER
2201 ;; ....................
2204 (define_insn "divdf3"
2205 [(set (match_operand:DF 0 "register_operand" "=f")
2206 (div:DF (match_operand:DF 1 "register_operand" "f")
2207 (match_operand:DF 2 "register_operand" "f")))]
2208 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2210 [(set_attr "type" "fdiv")
2211 (set_attr "mode" "DF")])
2213 (define_insn "divsf3"
2214 [(set (match_operand:SF 0 "register_operand" "=f")
2215 (div:SF (match_operand:SF 1 "register_operand" "f")
2216 (match_operand:SF 2 "register_operand" "f")))]
2219 [(set_attr "type" "fdiv")
2220 (set_attr "mode" "SF")])
2223 [(set (match_operand:DF 0 "register_operand" "=f")
2224 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2225 (match_operand:DF 2 "register_operand" "f")))]
2226 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
2228 [(set_attr "type" "fdiv")
2229 (set_attr "mode" "DF")])
2232 [(set (match_operand:SF 0 "register_operand" "=f")
2233 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2234 (match_operand:SF 2 "register_operand" "f")))]
2235 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
2237 [(set_attr "type" "fdiv")
2238 (set_attr "mode" "SF")])
2240 ;; If optimizing, prefer the divmod functions over separate div and
2241 ;; mod functions, since this will allow using one instruction for both
2242 ;; the quotient and remainder. At present, the divmod is not moved out
2243 ;; of loops if it is constant within the loop, so allow -mdebugc to
2244 ;; use the old method of doing things.
2246 ;; 64 is the multiply/divide hi register
2247 ;; 65 is the multiply/divide lo register
2249 ;; ??? We can't accept constants here, because the MIPS assembler will replace
2250 ;; a divide by power of 2 with a shift, and then the remainder is no longer
2253 (define_expand "divmodsi4"
2254 [(set (match_operand:SI 0 "register_operand" "=d")
2255 (div:SI (match_operand:SI 1 "register_operand" "d")
2256 (match_operand:SI 2 "register_operand" "d")))
2257 (set (match_operand:SI 3 "register_operand" "=d")
2258 (mod:SI (match_dup 1)
2260 (clobber (match_scratch:SI 4 "=l"))
2261 (clobber (match_scratch:SI 5 "=h"))
2262 (clobber (match_scratch:SI 6 "=a"))]
2266 emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2],
2268 if (!TARGET_NO_CHECK_ZERO_DIV)
2270 emit_insn (gen_div_trap (operands[2],
2274 if (TARGET_CHECK_RANGE_DIV)
2276 emit_insn (gen_div_trap (operands[2],
2277 copy_to_mode_reg (SImode, GEN_INT (-1)),
2279 emit_insn (gen_div_trap (operands[2],
2280 copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
2287 (define_insn "divmodsi4_internal"
2288 [(set (match_operand:SI 0 "register_operand" "=l")
2289 (div:SI (match_operand:SI 1 "register_operand" "d")
2290 (match_operand:SI 2 "register_operand" "d")))
2291 (set (match_operand:SI 3 "register_operand" "=h")
2292 (mod:SI (match_dup 1)
2294 (clobber (match_scratch:SI 4 "=a"))]
2297 [(set_attr "type" "idiv")
2298 (set_attr "mode" "SI")])
2300 (define_expand "divmoddi4"
2301 [(set (match_operand:DI 0 "register_operand" "=d")
2302 (div:DI (match_operand:DI 1 "se_register_operand" "d")
2303 (match_operand:DI 2 "se_register_operand" "d")))
2304 (set (match_operand:DI 3 "register_operand" "=d")
2305 (mod:DI (match_dup 1)
2307 (clobber (match_scratch:DI 4 "=l"))
2308 (clobber (match_scratch:DI 5 "=h"))
2309 (clobber (match_scratch:DI 6 "=a"))]
2310 "TARGET_64BIT && optimize"
2313 emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2],
2315 if (!TARGET_NO_CHECK_ZERO_DIV)
2317 emit_insn (gen_div_trap (operands[2],
2321 if (TARGET_CHECK_RANGE_DIV)
2323 emit_insn (gen_div_trap (operands[2],
2324 copy_to_mode_reg (DImode, GEN_INT (-1)),
2326 emit_insn (gen_div_trap (operands[2],
2327 copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
2334 (define_insn "divmoddi4_internal"
2335 [(set (match_operand:DI 0 "register_operand" "=l")
2336 (div:DI (match_operand:DI 1 "se_register_operand" "d")
2337 (match_operand:DI 2 "se_register_operand" "d")))
2338 (set (match_operand:DI 3 "register_operand" "=h")
2339 (mod:DI (match_dup 1)
2341 (clobber (match_scratch:DI 4 "=a"))]
2342 "TARGET_64BIT && optimize"
2344 [(set_attr "type" "idiv")
2345 (set_attr "mode" "SI")])
2347 (define_expand "udivmodsi4"
2348 [(set (match_operand:SI 0 "register_operand" "=d")
2349 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2350 (match_operand:SI 2 "register_operand" "d")))
2351 (set (match_operand:SI 3 "register_operand" "=d")
2352 (umod:SI (match_dup 1)
2354 (clobber (match_scratch:SI 4 "=l"))
2355 (clobber (match_scratch:SI 5 "=h"))
2356 (clobber (match_scratch:SI 6 "=a"))]
2360 emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2],
2362 if (!TARGET_NO_CHECK_ZERO_DIV)
2364 emit_insn (gen_div_trap (operands[2],
2372 (define_insn "udivmodsi4_internal"
2373 [(set (match_operand:SI 0 "register_operand" "=l")
2374 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2375 (match_operand:SI 2 "register_operand" "d")))
2376 (set (match_operand:SI 3 "register_operand" "=h")
2377 (umod:SI (match_dup 1)
2379 (clobber (match_scratch:SI 4 "=a"))]
2382 [(set_attr "type" "idiv")
2383 (set_attr "mode" "SI")])
2385 (define_expand "udivmoddi4"
2386 [(set (match_operand:DI 0 "register_operand" "=d")
2387 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
2388 (match_operand:DI 2 "se_register_operand" "d")))
2389 (set (match_operand:DI 3 "register_operand" "=d")
2390 (umod:DI (match_dup 1)
2392 (clobber (match_scratch:DI 4 "=l"))
2393 (clobber (match_scratch:DI 5 "=h"))
2394 (clobber (match_scratch:DI 6 "=a"))]
2395 "TARGET_64BIT && optimize"
2398 emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2],
2400 if (!TARGET_NO_CHECK_ZERO_DIV)
2402 emit_insn (gen_div_trap (operands[2],
2410 (define_insn "udivmoddi4_internal"
2411 [(set (match_operand:DI 0 "register_operand" "=l")
2412 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
2413 (match_operand:DI 2 "se_register_operand" "d")))
2414 (set (match_operand:DI 3 "register_operand" "=h")
2415 (umod:DI (match_dup 1)
2417 (clobber (match_scratch:DI 4 "=a"))]
2418 "TARGET_64BIT && optimize"
2420 [(set_attr "type" "idiv")
2421 (set_attr "mode" "SI")])
2425 (define_expand "div_trap"
2426 [(trap_if (eq (match_operand 0 "register_operand" "d")
2427 (match_operand 1 "true_reg_or_0_operand" "dJ"))
2428 (match_operand 2 "immediate_operand" ""))]
2433 emit_insn (gen_div_trap_mips16 (operands[0],operands[1],operands[2]));
2435 emit_insn (gen_div_trap_normal (operands[0],operands[1],operands[2]));
2439 (define_insn "div_trap_normal"
2440 [(trap_if (eq (match_operand 0 "register_operand" "d,d")
2441 (match_operand 1 "true_reg_or_0_operand" "d,J"))
2442 (match_operand 2 "immediate_operand" ""))]
2447 int have_dep_anti = 0;
2449 /* For divmod if one division is not needed then we don't need an extra
2450 divide by zero trap, which is anti dependent on previous trap */
2451 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
2453 if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
2454 && GET_CODE (XEXP (link, 0)) == INSN
2455 && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
2456 && which_alternative == 1)
2458 if (! have_dep_anti)
2460 if (GENERATE_BRANCHLIKELY)
2462 if (which_alternative == 1)
2463 return \"%(beql\\t%0,$0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
2465 return \"%(beql\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
2469 if (which_alternative == 1)
2470 return \"%(bne\\t%0,$0,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
2472 return \"%(bne\\t%0,%1,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
2477 [(set_attr "type" "unknown")
2478 (set_attr "length" "12")])
2481 ;; The mips16 bne insns is a macro which uses reg 24 as an intermediate.
2483 (define_insn "div_trap_mips16"
2484 [(trap_if (eq (match_operand 0 "register_operand" "d,d")
2485 (match_operand 1 "true_reg_or_0_operand" "d,J"))
2486 (match_operand 2 "immediate_operand" ""))
2487 (clobber (reg:SI 24))]
2492 int have_dep_anti = 0;
2494 /* For divmod if one division is not needed then we don't need an extra
2495 divide by zero trap, which is anti dependent on previous trap */
2496 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
2498 if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
2499 && GET_CODE (XEXP (link, 0)) == INSN
2500 && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
2501 && which_alternative == 1)
2503 if (! have_dep_anti)
2505 /* No branch delay slots on mips16. */
2506 if (which_alternative == 1)
2507 return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
2509 return \"%(bne\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
2513 [(set_attr "type" "unknown")
2514 (set_attr "length" "12")])
2516 (define_expand "divsi3"
2517 [(set (match_operand:SI 0 "register_operand" "=l")
2518 (div:SI (match_operand:SI 1 "register_operand" "d")
2519 (match_operand:SI 2 "register_operand" "d")))
2520 (clobber (match_scratch:SI 3 "=h"))
2521 (clobber (match_scratch:SI 4 "=a"))]
2525 emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2]));
2526 if (!TARGET_NO_CHECK_ZERO_DIV)
2528 emit_insn (gen_div_trap (operands[2],
2532 if (TARGET_CHECK_RANGE_DIV)
2534 emit_insn (gen_div_trap (operands[2],
2535 copy_to_mode_reg (SImode, GEN_INT (-1)),
2537 emit_insn (gen_div_trap (operands[2],
2538 copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
2545 (define_insn "divsi3_internal"
2546 [(set (match_operand:SI 0 "register_operand" "=l")
2547 (div:SI (match_operand:SI 1 "register_operand" "d")
2548 (match_operand:SI 2 "nonmemory_operand" "di")))
2549 (clobber (match_scratch:SI 3 "=h"))
2550 (clobber (match_scratch:SI 4 "=a"))]
2553 [(set_attr "type" "idiv")
2554 (set_attr "mode" "SI")])
2556 (define_expand "divdi3"
2557 [(set (match_operand:DI 0 "register_operand" "=l")
2558 (div:DI (match_operand:DI 1 "se_register_operand" "d")
2559 (match_operand:DI 2 "se_register_operand" "d")))
2560 (clobber (match_scratch:DI 3 "=h"))
2561 (clobber (match_scratch:DI 4 "=a"))]
2562 "TARGET_64BIT && !optimize"
2565 emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2]));
2566 if (!TARGET_NO_CHECK_ZERO_DIV)
2568 emit_insn (gen_div_trap (operands[2],
2572 if (TARGET_CHECK_RANGE_DIV)
2574 emit_insn (gen_div_trap (operands[2],
2575 copy_to_mode_reg (DImode, GEN_INT (-1)),
2577 emit_insn (gen_div_trap (operands[2],
2578 copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
2585 (define_insn "divdi3_internal"
2586 [(set (match_operand:DI 0 "register_operand" "=l")
2587 (div:DI (match_operand:DI 1 "se_register_operand" "d")
2588 (match_operand:DI 2 "se_nonmemory_operand" "di")))
2589 (clobber (match_scratch:SI 3 "=h"))
2590 (clobber (match_scratch:SI 4 "=a"))]
2591 "TARGET_64BIT && !optimize"
2593 [(set_attr "type" "idiv")
2594 (set_attr "mode" "DI")])
2596 (define_expand "modsi3"
2597 [(set (match_operand:SI 0 "register_operand" "=h")
2598 (mod:SI (match_operand:SI 1 "register_operand" "d")
2599 (match_operand:SI 2 "register_operand" "d")))
2600 (clobber (match_scratch:SI 3 "=l"))
2601 (clobber (match_scratch:SI 4 "=a"))]
2605 emit_insn (gen_modsi3_internal (operands[0], operands[1], operands[2]));
2606 if (!TARGET_NO_CHECK_ZERO_DIV)
2608 emit_insn (gen_div_trap (operands[2],
2612 if (TARGET_CHECK_RANGE_DIV)
2614 emit_insn (gen_div_trap (operands[2],
2615 copy_to_mode_reg (SImode, GEN_INT (-1)),
2617 emit_insn (gen_div_trap (operands[2],
2618 copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
2625 (define_insn "modsi3_internal"
2626 [(set (match_operand:SI 0 "register_operand" "=h")
2627 (mod:SI (match_operand:SI 1 "register_operand" "d")
2628 (match_operand:SI 2 "nonmemory_operand" "di")))
2629 (clobber (match_scratch:SI 3 "=l"))
2630 (clobber (match_scratch:SI 4 "=a"))]
2633 [(set_attr "type" "idiv")
2634 (set_attr "mode" "SI")])
2636 (define_expand "moddi3"
2637 [(set (match_operand:DI 0 "register_operand" "=h")
2638 (mod:DI (match_operand:DI 1 "se_register_operand" "d")
2639 (match_operand:DI 2 "se_register_operand" "d")))
2640 (clobber (match_scratch:DI 3 "=l"))
2641 (clobber (match_scratch:DI 4 "=a"))]
2642 "TARGET_64BIT && !optimize"
2645 emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2]));
2646 if (!TARGET_NO_CHECK_ZERO_DIV)
2648 emit_insn (gen_div_trap (operands[2],
2652 if (TARGET_CHECK_RANGE_DIV)
2654 emit_insn (gen_div_trap (operands[2],
2655 copy_to_mode_reg (DImode, GEN_INT (-1)),
2657 emit_insn (gen_div_trap (operands[2],
2658 copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
2665 (define_insn "moddi3_internal"
2666 [(set (match_operand:DI 0 "register_operand" "=h")
2667 (mod:DI (match_operand:DI 1 "se_register_operand" "d")
2668 (match_operand:DI 2 "se_nonmemory_operand" "di")))
2669 (clobber (match_scratch:SI 3 "=l"))
2670 (clobber (match_scratch:SI 4 "=a"))]
2671 "TARGET_64BIT && !optimize"
2673 [(set_attr "type" "idiv")
2674 (set_attr "mode" "DI")])
2676 (define_expand "udivsi3"
2677 [(set (match_operand:SI 0 "register_operand" "=l")
2678 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2679 (match_operand:SI 2 "register_operand" "d")))
2680 (clobber (match_scratch:SI 3 "=h"))
2681 (clobber (match_scratch:SI 4 "=a"))]
2685 emit_insn (gen_udivsi3_internal (operands[0], operands[1], operands[2]));
2686 if (!TARGET_NO_CHECK_ZERO_DIV)
2688 emit_insn (gen_div_trap (operands[2],
2696 (define_insn "udivsi3_internal"
2697 [(set (match_operand:SI 0 "register_operand" "=l")
2698 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2699 (match_operand:SI 2 "nonmemory_operand" "di")))
2700 (clobber (match_scratch:SI 3 "=h"))
2701 (clobber (match_scratch:SI 4 "=a"))]
2704 [(set_attr "type" "idiv")
2705 (set_attr "mode" "SI")])
2707 (define_expand "udivdi3"
2708 [(set (match_operand:DI 0 "register_operand" "=l")
2709 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
2710 (match_operand:DI 2 "se_register_operand" "di")))
2711 (clobber (match_scratch:DI 3 "=h"))
2712 (clobber (match_scratch:DI 4 "=a"))]
2713 "TARGET_64BIT && !optimize"
2716 emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2]));
2717 if (!TARGET_NO_CHECK_ZERO_DIV)
2719 emit_insn (gen_div_trap (operands[2],
2727 (define_insn "udivdi3_internal"
2728 [(set (match_operand:DI 0 "register_operand" "=l")
2729 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
2730 (match_operand:DI 2 "se_nonmemory_operand" "di")))
2731 (clobber (match_scratch:SI 3 "=h"))
2732 (clobber (match_scratch:SI 4 "=a"))]
2733 "TARGET_64BIT && !optimize"
2735 [(set_attr "type" "idiv")
2736 (set_attr "mode" "DI")])
2738 (define_expand "umodsi3"
2739 [(set (match_operand:SI 0 "register_operand" "=h")
2740 (umod:SI (match_operand:SI 1 "register_operand" "d")
2741 (match_operand:SI 2 "register_operand" "d")))
2742 (clobber (match_scratch:SI 3 "=l"))
2743 (clobber (match_scratch:SI 4 "=a"))]
2747 emit_insn (gen_umodsi3_internal (operands[0], operands[1], operands[2]));
2748 if (!TARGET_NO_CHECK_ZERO_DIV)
2750 emit_insn (gen_div_trap (operands[2],
2758 (define_insn "umodsi3_internal"
2759 [(set (match_operand:SI 0 "register_operand" "=h")
2760 (umod:SI (match_operand:SI 1 "register_operand" "d")
2761 (match_operand:SI 2 "nonmemory_operand" "di")))
2762 (clobber (match_scratch:SI 3 "=l"))
2763 (clobber (match_scratch:SI 4 "=a"))]
2766 [(set_attr "type" "idiv")
2767 (set_attr "mode" "SI")])
2769 (define_expand "umoddi3"
2770 [(set (match_operand:DI 0 "register_operand" "=h")
2771 (umod:DI (match_operand:DI 1 "se_register_operand" "d")
2772 (match_operand:DI 2 "se_register_operand" "di")))
2773 (clobber (match_scratch:DI 3 "=l"))
2774 (clobber (match_scratch:DI 4 "=a"))]
2775 "TARGET_64BIT && !optimize"
2778 emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2]));
2779 if (!TARGET_NO_CHECK_ZERO_DIV)
2781 emit_insn (gen_div_trap (operands[2],
2789 (define_insn "umoddi3_internal"
2790 [(set (match_operand:DI 0 "register_operand" "=h")
2791 (umod:DI (match_operand:DI 1 "se_register_operand" "d")
2792 (match_operand:DI 2 "se_nonmemory_operand" "di")))
2793 (clobber (match_scratch:SI 3 "=l"))
2794 (clobber (match_scratch:SI 4 "=a"))]
2795 "TARGET_64BIT && !optimize"
2797 [(set_attr "type" "idiv")
2798 (set_attr "mode" "DI")])
2801 ;; ....................
2805 ;; ....................
2807 (define_insn "sqrtdf2"
2808 [(set (match_operand:DF 0 "register_operand" "=f")
2809 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
2810 "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
2812 [(set_attr "type" "fsqrt")
2813 (set_attr "mode" "DF")])
2815 (define_insn "sqrtsf2"
2816 [(set (match_operand:SF 0 "register_operand" "=f")
2817 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
2818 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
2820 [(set_attr "type" "fsqrt")
2821 (set_attr "mode" "SF")])
2824 [(set (match_operand:DF 0 "register_operand" "=f")
2825 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2826 (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
2827 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
2829 [(set_attr "type" "fsqrt")
2830 (set_attr "mode" "DF")])
2833 [(set (match_operand:SF 0 "register_operand" "=f")
2834 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2835 (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
2836 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
2838 [(set_attr "type" "fsqrt")
2839 (set_attr "mode" "SF")])
2843 ;; ....................
2847 ;; ....................
2849 ;; Do not use the integer abs macro instruction, since that signals an
2850 ;; exception on -2147483648 (sigh).
2852 (define_insn "abssi2"
2853 [(set (match_operand:SI 0 "register_operand" "=d")
2854 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
2858 dslots_jump_total++;
2859 dslots_jump_filled++;
2860 operands[2] = const0_rtx;
2862 if (REGNO (operands[0]) == REGNO (operands[1]))
2864 if (GENERATE_BRANCHLIKELY)
2865 return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
2867 return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n%~1:\";
2870 return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
2872 [(set_attr "type" "multi")
2873 (set_attr "mode" "SI")
2874 (set_attr "length" "12")])
2876 (define_insn "absdi2"
2877 [(set (match_operand:DI 0 "register_operand" "=d")
2878 (abs:DI (match_operand:DI 1 "se_register_operand" "d")))]
2879 "TARGET_64BIT && !TARGET_MIPS16"
2882 unsigned int regno1;
2883 dslots_jump_total++;
2884 dslots_jump_filled++;
2885 operands[2] = const0_rtx;
2887 if (GET_CODE (operands[1]) == REG)
2888 regno1 = REGNO (operands[1]);
2890 regno1 = REGNO (XEXP (operands[1], 0));
2892 if (REGNO (operands[0]) == regno1)
2893 return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n%~1:%)\";
2895 return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n%~1:%)\";
2897 [(set_attr "type" "multi")
2898 (set_attr "mode" "DI")
2899 (set_attr "length" "12")])
2901 (define_insn "absdf2"
2902 [(set (match_operand:DF 0 "register_operand" "=f")
2903 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
2904 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2906 [(set_attr "type" "fabs")
2907 (set_attr "mode" "DF")])
2909 (define_insn "abssf2"
2910 [(set (match_operand:SF 0 "register_operand" "=f")
2911 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
2914 [(set_attr "type" "fabs")
2915 (set_attr "mode" "SF")])
2919 ;; ....................
2921 ;; FIND FIRST BIT INSTRUCTION
2923 ;; ....................
2926 (define_insn "ffssi2"
2927 [(set (match_operand:SI 0 "register_operand" "=&d")
2928 (ffs:SI (match_operand:SI 1 "register_operand" "d")))
2929 (clobber (match_scratch:SI 2 "=&d"))
2930 (clobber (match_scratch:SI 3 "=&d"))]
2934 dslots_jump_total += 2;
2935 dslots_jump_filled += 2;
2936 operands[4] = const0_rtx;
2938 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
2941 \\tbeq\\t%1,%z4,2f\\n\\
2942 %~1:\\tand\\t%2,%1,0x0001\\n\\
2943 \\taddu\\t%0,%0,1\\n\\
2944 \\tbeq\\t%2,%z4,1b\\n\\
2945 \\tsrl\\t%1,%1,1\\n\\
2950 \\tmove\\t%3,%1\\n\\
2951 \\tbeq\\t%3,%z4,2f\\n\\
2952 %~1:\\tand\\t%2,%3,0x0001\\n\\
2953 \\taddu\\t%0,%0,1\\n\\
2954 \\tbeq\\t%2,%z4,1b\\n\\
2955 \\tsrl\\t%3,%3,1\\n\\
2958 [(set_attr "type" "multi")
2959 (set_attr "mode" "SI")
2960 (set_attr "length" "12")])
2962 (define_insn "ffsdi2"
2963 [(set (match_operand:DI 0 "register_operand" "=&d")
2964 (ffs:DI (match_operand:DI 1 "se_register_operand" "d")))
2965 (clobber (match_scratch:DI 2 "=&d"))
2966 (clobber (match_scratch:DI 3 "=&d"))]
2967 "TARGET_64BIT && !TARGET_MIPS16"
2970 dslots_jump_total += 2;
2971 dslots_jump_filled += 2;
2972 operands[4] = const0_rtx;
2974 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
2977 \\tbeq\\t%1,%z4,2f\\n\\
2978 %~1:\\tand\\t%2,%1,0x0001\\n\\
2979 \\tdaddu\\t%0,%0,1\\n\\
2980 \\tbeq\\t%2,%z4,1b\\n\\
2981 \\tdsrl\\t%1,%1,1\\n\\
2986 \\tmove\\t%3,%1\\n\\
2987 \\tbeq\\t%3,%z4,2f\\n\\
2988 %~1:\\tand\\t%2,%3,0x0001\\n\\
2989 \\tdaddu\\t%0,%0,1\\n\\
2990 \\tbeq\\t%2,%z4,1b\\n\\
2991 \\tdsrl\\t%3,%3,1\\n\\
2994 [(set_attr "type" "multi")
2995 (set_attr "mode" "DI")
2996 (set_attr "length" "24")])
3000 ;; ....................
3002 ;; NEGATION and ONE'S COMPLEMENT
3004 ;; ....................
3006 (define_insn "negsi2"
3007 [(set (match_operand:SI 0 "register_operand" "=d")
3008 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
3013 return \"neg\\t%0,%1\";
3014 operands[2] = const0_rtx;
3015 return \"subu\\t%0,%z2,%1\";
3017 [(set_attr "type" "arith")
3018 (set_attr "mode" "SI")])
3020 (define_expand "negdi2"
3021 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
3022 (neg:DI (match_operand:DI 1 "se_register_operand" "d")))
3023 (clobber (match_dup 2))])]
3024 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
3029 emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
3033 operands[2] = gen_reg_rtx (SImode);
3036 (define_insn "negdi2_internal"
3037 [(set (match_operand:DI 0 "register_operand" "=d")
3038 (neg:DI (match_operand:DI 1 "register_operand" "d")))
3039 (clobber (match_operand:SI 2 "register_operand" "=d"))]
3040 "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
3043 operands[3] = const0_rtx;
3044 return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
3046 [(set_attr "type" "darith")
3047 (set_attr "mode" "DI")
3048 (set_attr "length" "16")])
3050 (define_insn "negdi2_internal_2"
3051 [(set (match_operand:DI 0 "register_operand" "=d")
3052 (neg:DI (match_operand:DI 1 "se_register_operand" "d")))]
3053 "TARGET_64BIT && !TARGET_MIPS16"
3056 operands[2] = const0_rtx;
3057 return \"dsubu\\t%0,%z2,%1\";
3059 [(set_attr "type" "arith")
3060 (set_attr "mode" "DI")])
3062 (define_insn "negdf2"
3063 [(set (match_operand:DF 0 "register_operand" "=f")
3064 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
3065 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3067 [(set_attr "type" "fneg")
3068 (set_attr "mode" "DF")])
3070 (define_insn "negsf2"
3071 [(set (match_operand:SF 0 "register_operand" "=f")
3072 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
3075 [(set_attr "type" "fneg")
3076 (set_attr "mode" "SF")])
3078 (define_insn "one_cmplsi2"
3079 [(set (match_operand:SI 0 "register_operand" "=d")
3080 (not:SI (match_operand:SI 1 "register_operand" "d")))]
3085 return \"not\\t%0,%1\";
3086 operands[2] = const0_rtx;
3087 return \"nor\\t%0,%z2,%1\";
3089 [(set_attr "type" "arith")
3090 (set_attr "mode" "SI")])
3092 (define_insn "one_cmpldi2"
3093 [(set (match_operand:DI 0 "register_operand" "=d")
3094 (not:DI (match_operand:DI 1 "se_register_operand" "d")))]
3101 return \"not\\t%0,%1\";
3102 return \"not\\t%M0,%M1\;not\\t%L0,%L1\";
3104 operands[2] = const0_rtx;
3106 return \"nor\\t%0,%z2,%1\";
3107 return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
3109 [(set_attr "type" "darith")
3110 (set_attr "mode" "DI")
3111 (set (attr "length")
3112 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
3117 [(set (match_operand:DI 0 "register_operand" "")
3118 (not:DI (match_operand:DI 1 "register_operand" "")))]
3119 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3120 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3121 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
3123 [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
3124 (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
3129 ;; ....................
3133 ;; ....................
3136 ;; Many of these instructions uses trivial define_expands, because we
3137 ;; want to use a different set of constraints when TARGET_MIPS16.
3139 (define_expand "andsi3"
3140 [(set (match_operand:SI 0 "register_operand" "=d,d")
3141 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3142 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3147 operands[2] = force_reg (SImode, operands[2]);
3151 [(set (match_operand:SI 0 "register_operand" "=d,d")
3152 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3153 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3158 [(set_attr "type" "arith")
3159 (set_attr "mode" "SI")])
3162 [(set (match_operand:SI 0 "register_operand" "=d")
3163 (and:SI (match_operand:SI 1 "register_operand" "%0")
3164 (match_operand:SI 2 "register_operand" "d")))]
3167 [(set_attr "type" "arith")
3168 (set_attr "mode" "SI")])
3170 (define_expand "anddi3"
3171 [(set (match_operand:DI 0 "register_operand" "=d")
3172 (and:DI (match_operand:DI 1 "se_register_operand" "d")
3173 (match_operand:DI 2 "se_register_operand" "d")))]
3174 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3178 operands[2] = force_reg (DImode, operands[2]);
3182 [(set (match_operand:DI 0 "register_operand" "=d")
3183 (and:DI (match_operand:DI 1 "se_register_operand" "d")
3184 (match_operand:DI 2 "se_register_operand" "d")))]
3185 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
3189 return \"and\\t%0,%1,%2\";
3190 return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\";
3192 [(set_attr "type" "darith")
3193 (set_attr "mode" "DI")
3194 (set (attr "length")
3195 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
3200 [(set (match_operand:DI 0 "register_operand" "=d")
3201 (and:DI (match_operand:DI 1 "se_register_operand" "0")
3202 (match_operand:DI 2 "se_register_operand" "d")))]
3203 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
3207 return \"and\\t%0,%2\";
3208 return \"and\\t%M0,%M2\;and\\t%L0,%L2\";
3210 [(set_attr "type" "darith")
3211 (set_attr "mode" "DI")
3212 (set (attr "length")
3213 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
3218 [(set (match_operand:DI 0 "register_operand" "")
3219 (and:DI (match_operand:DI 1 "register_operand" "")
3220 (match_operand:DI 2 "register_operand" "")))]
3221 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3222 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3223 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
3224 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
3226 [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
3227 (set (subreg:SI (match_dup 0) 4) (and:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
3230 (define_insn "anddi3_internal1"
3231 [(set (match_operand:DI 0 "register_operand" "=d,d")
3232 (and:DI (match_operand:DI 1 "se_register_operand" "%d,d")
3233 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
3234 "TARGET_64BIT && !TARGET_MIPS16"
3238 [(set_attr "type" "arith")
3239 (set_attr "mode" "DI")])
3241 (define_expand "iorsi3"
3242 [(set (match_operand:SI 0 "register_operand" "=d,d")
3243 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3244 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3249 operands[2] = force_reg (SImode, operands[2]);
3253 [(set (match_operand:SI 0 "register_operand" "=d,d")
3254 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3255 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3260 [(set_attr "type" "arith")
3261 (set_attr "mode" "SI")])
3264 [(set (match_operand:SI 0 "register_operand" "=d")
3265 (ior:SI (match_operand:SI 1 "register_operand" "%0")
3266 (match_operand:SI 2 "register_operand" "d")))]
3269 [(set_attr "type" "arith")
3270 (set_attr "mode" "SI")])
3272 ;;; ??? There is no iordi3 pattern which accepts 'K' constants when
3275 (define_expand "iordi3"
3276 [(set (match_operand:DI 0 "register_operand" "=d")
3277 (ior:DI (match_operand:DI 1 "se_register_operand" "d")
3278 (match_operand:DI 2 "se_register_operand" "d")))]
3279 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3283 [(set (match_operand:DI 0 "register_operand" "=d")
3284 (ior:DI (match_operand:DI 1 "se_register_operand" "d")
3285 (match_operand:DI 2 "se_register_operand" "d")))]
3286 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
3290 return \"or\\t%0,%1,%2\";
3291 return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\";
3293 [(set_attr "type" "darith")
3294 (set_attr "mode" "DI")
3295 (set (attr "length")
3296 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
3301 [(set (match_operand:DI 0 "register_operand" "=d")
3302 (ior:DI (match_operand:DI 1 "se_register_operand" "0")
3303 (match_operand:DI 2 "se_register_operand" "d")))]
3304 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
3308 return \"or\\t%0,%2\";
3309 return \"or\\t%M0,%M2\;or\\t%L0,%L2\";
3311 [(set_attr "type" "darith")
3312 (set_attr "mode" "DI")
3313 (set (attr "length")
3314 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
3319 [(set (match_operand:DI 0 "register_operand" "")
3320 (ior:DI (match_operand:DI 1 "register_operand" "")
3321 (match_operand:DI 2 "register_operand" "")))]
3322 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3323 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3324 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
3325 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
3327 [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
3328 (set (subreg:SI (match_dup 0) 4) (ior:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
3331 (define_expand "xorsi3"
3332 [(set (match_operand:SI 0 "register_operand" "=d,d")
3333 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3334 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3339 [(set (match_operand:SI 0 "register_operand" "=d,d")
3340 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3341 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3346 [(set_attr "type" "arith")
3347 (set_attr "mode" "SI")])
3350 [(set (match_operand:SI 0 "register_operand" "=d,t,t")
3351 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%0,d,d")
3352 (match_operand:SI 2 "uns_arith_operand" "d,K,d")))]
3358 [(set_attr "type" "arith")
3359 (set_attr "mode" "SI")
3360 (set_attr_alternative "length"
3362 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
3367 ;; ??? If delete the 32-bit long long patterns, then could merge this with
3368 ;; the following xordi3_internal pattern.
3369 (define_expand "xordi3"
3370 [(set (match_operand:DI 0 "register_operand" "=d")
3371 (xor:DI (match_operand:DI 1 "se_register_operand" "d")
3372 (match_operand:DI 2 "se_register_operand" "d")))]
3373 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3377 [(set (match_operand:DI 0 "register_operand" "=d")
3378 (xor:DI (match_operand:DI 1 "se_register_operand" "d")
3379 (match_operand:DI 2 "se_register_operand" "d")))]
3380 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
3384 return \"xor\\t%0,%1,%2\";
3385 return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\";
3387 [(set_attr "type" "darith")
3388 (set_attr "mode" "DI")
3389 (set (attr "length")
3390 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
3395 [(set (match_operand:DI 0 "register_operand" "=d")
3396 (xor:DI (match_operand:DI 1 "se_register_operand" "0")
3397 (match_operand:DI 2 "se_register_operand" "d")))]
3398 "!TARGET_64BIT && TARGET_MIPS16"
3399 "xor\\t%M0,%M2\;xor\\t%L0,%L2"
3400 [(set_attr "type" "darith")
3401 (set_attr "mode" "DI")
3402 (set_attr "length" "8")])
3405 [(set (match_operand:DI 0 "register_operand" "=d,t,t")
3406 (xor:DI (match_operand:DI 1 "se_register_operand" "%0,d,d")
3407 (match_operand:DI 2 "se_uns_arith_operand" "d,K,d")))]
3408 "TARGET_64BIT && TARGET_MIPS16"
3413 [(set_attr "type" "arith")
3414 (set_attr "mode" "DI")
3415 (set_attr_alternative "length"
3417 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
3423 [(set (match_operand:DI 0 "register_operand" "")
3424 (xor:DI (match_operand:DI 1 "register_operand" "")
3425 (match_operand:DI 2 "register_operand" "")))]
3426 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3427 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3428 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
3429 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
3431 [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
3432 (set (subreg:SI (match_dup 0) 4) (xor:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
3435 (define_insn "xordi3_immed"
3436 [(set (match_operand:DI 0 "register_operand" "=d")
3437 (xor:DI (match_operand:DI 1 "se_register_operand" "d")
3438 (match_operand:DI 2 "se_uns_arith_operand" "K")))]
3439 "TARGET_64BIT && !TARGET_MIPS16"
3441 [(set_attr "type" "arith")
3442 (set_attr "mode" "DI")])
3444 (define_insn "*norsi3"
3445 [(set (match_operand:SI 0 "register_operand" "=d")
3446 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
3447 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
3450 [(set_attr "type" "arith")
3451 (set_attr "mode" "SI")])
3453 (define_insn "*nordi3"
3454 [(set (match_operand:DI 0 "register_operand" "=d")
3455 (and:DI (not:DI (match_operand:DI 1 "se_register_operand" "d"))
3456 (not:DI (match_operand:DI 2 "se_register_operand" "d"))))]
3461 return \"nor\\t%0,%z1,%z2\";
3462 return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\";
3464 [(set_attr "type" "darith")
3465 (set_attr "mode" "DI")
3466 (set (attr "length")
3467 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
3472 [(set (match_operand:DI 0 "register_operand" "")
3473 (and:DI (not:DI (match_operand:DI 1 "register_operand" ""))
3474 (not:DI (match_operand:DI 2 "register_operand" ""))))]
3475 "reload_completed && !TARGET_MIPS16 && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3476 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3477 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
3478 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
3480 [(set (subreg:SI (match_dup 0) 0) (and:SI (not:SI (subreg:SI (match_dup 1) 0)) (not:SI (subreg:SI (match_dup 2) 0))))
3481 (set (subreg:SI (match_dup 0) 4) (and:SI (not:SI (subreg:SI (match_dup 1) 4)) (not:SI (subreg:SI (match_dup 2) 4))))]
3485 ;; ....................
3489 ;; ....................
3491 (define_insn "truncdfsf2"
3492 [(set (match_operand:SF 0 "register_operand" "=f")
3493 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3494 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3496 [(set_attr "type" "fcvt")
3497 (set_attr "mode" "SF")])
3499 (define_insn "truncdisi2"
3500 [(set (match_operand:SI 0 "register_operand" "=d")
3501 (truncate:SI (match_operand:DI 1 "se_register_operand" "d")))]
3506 return \"dsll\\t%0,%1,32\;dsra\\t%0,32\";
3507 return \"dsll\\t%0,%1,32\;dsra\\t%0,%0,32\";
3509 [(set_attr "type" "darith")
3510 (set_attr "mode" "SI")
3511 (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
3515 (define_insn "truncdihi2"
3516 [(set (match_operand:HI 0 "register_operand" "=d")
3517 (truncate:HI (match_operand:DI 1 "se_register_operand" "d")))]
3522 return \"dsll\\t%0,%1,48\;dsra\\t%0,48\";
3523 return \"andi\\t%0,%1,0xffff\";
3525 [(set_attr "type" "darith")
3526 (set_attr "mode" "HI")
3527 (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
3530 (define_insn "truncdiqi2"
3531 [(set (match_operand:QI 0 "register_operand" "=d")
3532 (truncate:QI (match_operand:DI 1 "se_register_operand" "d")))]
3537 return \"dsll\\t%0,%1,56\;dsra\\t%0,56\";
3538 return \"andi\\t%0,%1,0x00ff\";
3540 [(set_attr "type" "darith")
3541 (set_attr "mode" "QI")
3542 (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
3546 ;; Combiner patterns to optimize shift/truncate combinations.
3548 [(set (match_operand:SI 0 "register_operand" "=d")
3549 (truncate:SI (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
3550 (match_operand:DI 2 "small_int" "I"))))]
3551 "TARGET_64BIT && !TARGET_MIPS16"
3554 int shift_amt = INTVAL (operands[2]) & 0x3f;
3558 operands[2] = GEN_INT (32 - shift_amt);
3559 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
3563 operands[2] = GEN_INT (shift_amt);
3564 return \"dsra\\t%0,%1,%2\";
3567 [(set_attr "type" "darith")
3568 (set_attr "mode" "SI")
3569 (set_attr "length" "8")])
3572 [(set (match_operand:SI 0 "register_operand" "=d")
3573 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
3574 (match_operand:DI 2 "small_int" "I"))))]
3575 "TARGET_64BIT && !TARGET_MIPS16"
3578 int shift_amt = INTVAL (operands[2]) & 0x3f;
3582 operands[2] = GEN_INT (32 - shift_amt);
3583 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
3585 else if (shift_amt == 32)
3586 return \"dsra\\t%0,%1,32\";
3589 operands[2] = GEN_INT (shift_amt);
3590 return \"dsrl\\t%0,%1,%2\";
3593 [(set_attr "type" "darith")
3594 (set_attr "mode" "SI")
3595 (set_attr "length" "8")])
3598 [(set (match_operand:SI 0 "register_operand" "=d")
3599 (truncate:SI (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
3600 (match_operand:DI 2 "small_int" "I"))))]
3604 int shift_amt = INTVAL (operands[2]) & 0x3f;
3608 operands[2] = GEN_INT (32 + shift_amt);
3610 return \"dsll\\t%0,%1,%2\;dsra\\t%0,32\";
3611 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
3614 return \"move\\t%0,%.\";
3616 [(set_attr "type" "darith")
3617 (set_attr "mode" "SI")
3618 (set_attr "length" "8")])
3620 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3623 [(set (match_operand:SI 0 "register_operand" "=d")
3624 (zero_extend:SI (truncate:HI
3625 (match_operand:DI 1 "se_register_operand" "d"))))]
3626 "TARGET_64BIT && !TARGET_MIPS16"
3627 "andi\\t%0,%1,0xffff"
3628 [(set_attr "type" "darith")
3629 (set_attr "mode" "SI")])
3632 [(set (match_operand:SI 0 "register_operand" "=d")
3633 (zero_extend:SI (truncate:QI
3634 (match_operand:DI 1 "se_register_operand" "d"))))]
3635 "TARGET_64BIT && !TARGET_MIPS16"
3637 [(set_attr "type" "darith")
3638 (set_attr "mode" "SI")])
3641 [(set (match_operand:HI 0 "register_operand" "=d")
3642 (zero_extend:HI (truncate:QI
3643 (match_operand:DI 1 "se_register_operand" "d"))))]
3644 "TARGET_64BIT && !TARGET_MIPS16"
3646 [(set_attr "type" "darith")
3647 (set_attr "mode" "HI")])
3650 ;; ....................
3654 ;; ....................
3657 ;; Those for integer source operand are ordered widest source type first.
3659 (define_expand "zero_extendsidi2"
3660 [(set (match_operand:DI 0 "register_operand" "")
3661 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3665 if ((optimize || TARGET_MIPS16) && GET_CODE (operands[1]) == MEM)
3666 operands[1] = force_not_mem (operands[1]);
3668 if (GET_CODE (operands[1]) != MEM)
3670 rtx op1 = gen_lowpart (DImode, operands[1]);
3671 rtx temp = gen_reg_rtx (DImode);
3672 rtx shift = GEN_INT (32);
3674 emit_insn (gen_ashldi3 (temp, op1, shift));
3675 emit_insn (gen_lshrdi3 (operands[0], temp, shift));
3680 (define_insn "zero_extendsidi2_internal"
3681 [(set (match_operand:DI 0 "register_operand" "=d,d")
3682 (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
3683 "TARGET_64BIT && !TARGET_MIPS16"
3684 "* return mips_move_1word (operands, insn, TRUE);"
3685 [(set_attr "type" "load")
3686 (set_attr "mode" "DI")
3687 (set_attr "length" "4,8")])
3689 (define_expand "zero_extendhisi2"
3690 [(set (match_operand:SI 0 "register_operand" "")
3691 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3695 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3697 rtx op = gen_lowpart (SImode, operands[1]);
3698 rtx temp = force_reg (SImode, GEN_INT (0xffff));
3700 emit_insn (gen_andsi3 (operands[0], op, temp));
3706 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3707 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
3711 if (which_alternative == 0)
3712 return \"andi\\t%0,%1,0xffff\";
3714 return mips_move_1word (operands, insn, TRUE);
3716 [(set_attr "type" "arith,load,load")
3717 (set_attr "mode" "SI")
3718 (set_attr "length" "4,4,8")])
3721 [(set (match_operand:SI 0 "register_operand" "=d,d")
3722 (zero_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
3724 "* return mips_move_1word (operands, insn, TRUE);"
3725 [(set_attr "type" "load,load")
3726 (set_attr "mode" "SI")
3727 (set_attr "length" "4,8")])
3729 (define_expand "zero_extendhidi2"
3730 [(set (match_operand:DI 0 "register_operand" "")
3731 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
3735 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3737 rtx op = gen_lowpart (DImode, operands[1]);
3738 rtx temp = force_reg (DImode, GEN_INT (0xffff));
3740 emit_insn (gen_anddi3 (operands[0], op, temp));
3746 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3747 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
3748 "TARGET_64BIT && !TARGET_MIPS16"
3751 if (which_alternative == 0)
3752 return \"andi\\t%0,%1,0xffff\";
3754 return mips_move_1word (operands, insn, TRUE);
3756 [(set_attr "type" "arith,load,load")
3757 (set_attr "mode" "DI")
3758 (set_attr "length" "4,4,8")])
3761 [(set (match_operand:DI 0 "register_operand" "=d,d")
3762 (zero_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
3763 "TARGET_64BIT && TARGET_MIPS16"
3764 "* return mips_move_1word (operands, insn, TRUE);"
3765 [(set_attr "type" "load,load")
3766 (set_attr "mode" "DI")
3767 (set_attr "length" "4,8")])
3769 (define_expand "zero_extendqihi2"
3770 [(set (match_operand:HI 0 "register_operand" "")
3771 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
3775 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3777 rtx op0 = gen_lowpart (SImode, operands[0]);
3778 rtx op1 = gen_lowpart (SImode, operands[1]);
3779 rtx temp = force_reg (SImode, GEN_INT (0xff));
3781 emit_insn (gen_andsi3 (op0, op1, temp));
3787 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3788 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
3792 if (which_alternative == 0)
3793 return \"andi\\t%0,%1,0x00ff\";
3795 return mips_move_1word (operands, insn, TRUE);
3797 [(set_attr "type" "arith,load,load")
3798 (set_attr "mode" "HI")
3799 (set_attr "length" "4,4,8")])
3802 [(set (match_operand:HI 0 "register_operand" "=d,d")
3803 (zero_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
3805 "* return mips_move_1word (operands, insn, TRUE);"
3806 [(set_attr "type" "load,load")
3807 (set_attr "mode" "HI")
3808 (set_attr "length" "4,8")])
3810 (define_expand "zero_extendqisi2"
3811 [(set (match_operand:SI 0 "register_operand" "")
3812 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
3816 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3818 rtx op = gen_lowpart (SImode, operands[1]);
3819 rtx temp = force_reg (SImode, GEN_INT (0xff));
3821 emit_insn (gen_andsi3 (operands[0], op, temp));
3827 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3828 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
3832 if (which_alternative == 0)
3833 return \"andi\\t%0,%1,0x00ff\";
3835 return mips_move_1word (operands, insn, TRUE);
3837 [(set_attr "type" "arith,load,load")
3838 (set_attr "mode" "SI")
3839 (set_attr "length" "4,4,8")])
3842 [(set (match_operand:SI 0 "register_operand" "=d,d")
3843 (zero_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
3845 "* return mips_move_1word (operands, insn, TRUE);"
3846 [(set_attr "type" "load,load")
3847 (set_attr "mode" "SI")
3848 (set_attr "length" "4,8")])
3850 (define_expand "zero_extendqidi2"
3851 [(set (match_operand:DI 0 "register_operand" "")
3852 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
3856 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3858 rtx op = gen_lowpart (DImode, operands[1]);
3859 rtx temp = force_reg (DImode, GEN_INT (0xff));
3861 emit_insn (gen_anddi3 (operands[0], op, temp));
3867 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3868 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
3869 "TARGET_64BIT && !TARGET_MIPS16"
3872 if (which_alternative == 0)
3873 return \"andi\\t%0,%1,0x00ff\";
3875 return mips_move_1word (operands, insn, TRUE);
3877 [(set_attr "type" "arith,load,load")
3878 (set_attr "mode" "DI")
3879 (set_attr "length" "4,4,8")])
3881 ;; These can be created when a paradoxical subreg operand with an implicit
3882 ;; sign_extend operator is reloaded. Because of the subreg, this is really
3884 ;; ??? It might be possible to eliminate the need for these patterns by adding
3885 ;; more support to reload for implicit sign_extend operators.
3886 (define_insn "*paradoxical_extendhidi2"
3887 [(set (match_operand:DI 0 "register_operand" "=d,d")
3889 (subreg:SI (match_operand:HI 1 "memory_operand" "R,m") 0)))]
3893 return mips_move_1word (operands, insn, TRUE);
3895 [(set_attr "type" "load,load")
3896 (set_attr "mode" "DI")
3897 (set_attr "length" "4,8")])
3900 [(set (match_operand:DI 0 "register_operand" "=d,d")
3901 (zero_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
3902 "TARGET_64BIT && TARGET_MIPS16"
3903 "* return mips_move_1word (operands, insn, TRUE);"
3904 [(set_attr "type" "load,load")
3905 (set_attr "mode" "DI")
3906 (set_attr "length" "4,8")])
3909 ;; ....................
3913 ;; ....................
3916 ;; Those for integer source operand are ordered widest source type first.
3918 ;; In 64 bit mode, 32 bit values in general registers are always
3919 ;; correctly sign extended. That means that if the target is a
3920 ;; general register, we can sign extend from SImode to DImode just by
3923 (define_insn "extendsidi2"
3924 [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d")
3925 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x,R,m")))]
3927 "* return mips_move_1word (operands, insn, FALSE);"
3928 [(set_attr "type" "move,move,move,hilo,load,load")
3929 (set_attr "mode" "DI")
3930 (set_attr "length" "4,4,4,4,4,8")])
3932 ;; These patterns originally accepted general_operands, however, slightly
3933 ;; better code is generated by only accepting register_operands, and then
3934 ;; letting combine generate the lh and lb insns.
3936 (define_expand "extendhidi2"
3937 [(set (match_operand:DI 0 "register_operand" "")
3938 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
3942 if (optimize && GET_CODE (operands[1]) == MEM)
3943 operands[1] = force_not_mem (operands[1]);
3945 if (GET_CODE (operands[1]) != MEM)
3947 rtx op1 = gen_lowpart (DImode, operands[1]);
3948 rtx temp = gen_reg_rtx (DImode);
3949 rtx shift = GEN_INT (48);
3951 emit_insn (gen_ashldi3 (temp, op1, shift));
3952 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
3957 (define_insn "extendhidi2_internal"
3958 [(set (match_operand:DI 0 "register_operand" "=d,d")
3959 (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
3961 "* return mips_move_1word (operands, insn, FALSE);"
3962 [(set_attr "type" "load")
3963 (set_attr "mode" "DI")
3964 (set_attr "length" "4,8")])
3966 (define_expand "extendhisi2"
3967 [(set (match_operand:SI 0 "register_operand" "")
3968 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3972 if (optimize && GET_CODE (operands[1]) == MEM)
3973 operands[1] = force_not_mem (operands[1]);
3975 if (GET_CODE (operands[1]) != MEM)
3977 rtx op1 = gen_lowpart (SImode, operands[1]);
3978 rtx temp = gen_reg_rtx (SImode);
3979 rtx shift = GEN_INT (16);
3981 emit_insn (gen_ashlsi3 (temp, op1, shift));
3982 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
3987 (define_insn "extendhisi2_internal"
3988 [(set (match_operand:SI 0 "register_operand" "=d,d")
3989 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
3991 "* return mips_move_1word (operands, insn, FALSE);"
3992 [(set_attr "type" "load")
3993 (set_attr "mode" "SI")
3994 (set_attr "length" "4,8")])
3996 (define_expand "extendqihi2"
3997 [(set (match_operand:HI 0 "register_operand" "")
3998 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
4002 if (optimize && GET_CODE (operands[1]) == MEM)
4003 operands[1] = force_not_mem (operands[1]);
4005 if (GET_CODE (operands[1]) != MEM)
4007 rtx op0 = gen_lowpart (SImode, operands[0]);
4008 rtx op1 = gen_lowpart (SImode, operands[1]);
4009 rtx temp = gen_reg_rtx (SImode);
4010 rtx shift = GEN_INT (24);
4012 emit_insn (gen_ashlsi3 (temp, op1, shift));
4013 emit_insn (gen_ashrsi3 (op0, temp, shift));
4018 (define_insn "extendqihi2_internal"
4019 [(set (match_operand:HI 0 "register_operand" "=d,d")
4020 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
4022 "* return mips_move_1word (operands, insn, FALSE);"
4023 [(set_attr "type" "load")
4024 (set_attr "mode" "SI")
4025 (set_attr "length" "4,8")])
4028 (define_expand "extendqisi2"
4029 [(set (match_operand:SI 0 "register_operand" "")
4030 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
4034 if (optimize && GET_CODE (operands[1]) == MEM)
4035 operands[1] = force_not_mem (operands[1]);
4037 if (GET_CODE (operands[1]) != MEM)
4039 rtx op1 = gen_lowpart (SImode, operands[1]);
4040 rtx temp = gen_reg_rtx (SImode);
4041 rtx shift = GEN_INT (24);
4043 emit_insn (gen_ashlsi3 (temp, op1, shift));
4044 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
4049 (define_insn "extendqisi2_insn"
4050 [(set (match_operand:SI 0 "register_operand" "=d,d")
4051 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
4053 "* return mips_move_1word (operands, insn, FALSE);"
4054 [(set_attr "type" "load")
4055 (set_attr "mode" "SI")
4056 (set_attr "length" "4,8")])
4058 (define_expand "extendqidi2"
4059 [(set (match_operand:DI 0 "register_operand" "")
4060 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
4064 if (optimize && GET_CODE (operands[1]) == MEM)
4065 operands[1] = force_not_mem (operands[1]);
4067 if (GET_CODE (operands[1]) != MEM)
4069 rtx op1 = gen_lowpart (DImode, operands[1]);
4070 rtx temp = gen_reg_rtx (DImode);
4071 rtx shift = GEN_INT (56);
4073 emit_insn (gen_ashldi3 (temp, op1, shift));
4074 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
4079 (define_insn "extendqidi2_insn"
4080 [(set (match_operand:DI 0 "register_operand" "=d,d")
4081 (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
4083 "* return mips_move_1word (operands, insn, FALSE);"
4084 [(set_attr "type" "load")
4085 (set_attr "mode" "DI")
4086 (set_attr "length" "4,8")])
4089 (define_insn "extendsfdf2"
4090 [(set (match_operand:DF 0 "register_operand" "=f")
4091 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
4092 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4094 [(set_attr "type" "fcvt")
4095 (set_attr "mode" "DF")])
4100 ;; ....................
4104 ;; ....................
4106 ;; The SImode scratch register can not be shared with address regs used for
4107 ;; operand zero, because then the address in the move instruction will be
4108 ;; clobbered. We mark the scratch register as early clobbered to prevent this.
4110 ;; We need the ?X in alternative 1 so that it will be choosen only if the
4111 ;; destination is a floating point register. Otherwise, alternative 1 can
4112 ;; have lower cost than alternative 0 (because there is one less loser), and
4113 ;; can be choosen when it won't work (because integral reloads into FP
4114 ;; registers are not supported).
4116 (define_insn "fix_truncdfsi2"
4117 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
4118 (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
4119 (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
4120 (clobber (match_scratch:DF 3 "=f,?*X,f,f"))]
4121 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4126 if (which_alternative == 1)
4127 return \"trunc.w.d %0,%1,%2\";
4129 output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
4131 xoperands[0] = operands[0];
4132 xoperands[1] = operands[3];
4133 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
4136 [(set_attr "type" "fcvt")
4137 (set_attr "mode" "DF")
4138 (set_attr "length" "44,36,40,44")])
4141 (define_insn "fix_truncsfsi2"
4142 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
4143 (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
4144 (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
4145 (clobber (match_scratch:SF 3 "=f,?*X,f,f"))]
4151 if (which_alternative == 1)
4152 return \"trunc.w.s %0,%1,%2\";
4154 output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
4156 xoperands[0] = operands[0];
4157 xoperands[1] = operands[3];
4158 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
4161 [(set_attr "type" "fcvt")
4162 (set_attr "mode" "SF")
4163 (set_attr "length" "44,36,40,44")])
4166 ;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
4167 ;;; but not in the chapter that describes the FPU. It is not mentioned at all
4168 ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
4170 ;;; Deleting this means that we now need two libgcc2.a libraries. One for
4171 ;;; the 32 bit calling convention and one for the 64 bit calling convention.
4173 ;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
4175 (define_insn "fix_truncdfdi2"
4176 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
4177 (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
4178 (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
4179 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4184 if (which_alternative == 1)
4185 return \"trunc.l.d %0,%1\";
4187 output_asm_insn (\"trunc.l.d %2,%1\", operands);
4189 xoperands[0] = operands[0];
4190 xoperands[1] = operands[2];
4191 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
4194 [(set_attr "type" "fcvt")
4195 (set_attr "mode" "DF")
4196 (set_attr "length" "8,4,8,12")])
4199 ;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
4200 ;;; but not in the chapter that describes the FPU. It is not mentioned at all
4201 ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
4202 (define_insn "fix_truncsfdi2"
4203 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
4204 (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
4205 (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
4206 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4211 if (which_alternative == 1)
4212 return \"trunc.l.s %0,%1\";
4214 output_asm_insn (\"trunc.l.s %2,%1\", operands);
4216 xoperands[0] = operands[0];
4217 xoperands[1] = operands[2];
4218 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
4221 [(set_attr "type" "fcvt")
4222 (set_attr "mode" "SF")
4223 (set_attr "length" "8,4,8,12")])
4226 (define_insn "floatsidf2"
4227 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
4228 (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
4229 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4232 dslots_load_total++;
4233 if (GET_CODE (operands[1]) == MEM)
4234 return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
4236 return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
4238 [(set_attr "type" "fcvt")
4239 (set_attr "mode" "DF")
4240 (set_attr "length" "12,16,12")])
4243 (define_insn "floatdidf2"
4244 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
4245 (float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
4246 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4249 dslots_load_total++;
4250 if (GET_CODE (operands[1]) == MEM)
4251 return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
4253 return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
4255 [(set_attr "type" "fcvt")
4256 (set_attr "mode" "DF")
4257 (set_attr "length" "12,16,12")])
4260 (define_insn "floatsisf2"
4261 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
4262 (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
4266 dslots_load_total++;
4267 if (GET_CODE (operands[1]) == MEM)
4268 return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
4270 return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
4272 [(set_attr "type" "fcvt")
4273 (set_attr "mode" "SF")
4274 (set_attr "length" "12,16,12")])
4277 (define_insn "floatdisf2"
4278 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
4279 (float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
4280 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4283 dslots_load_total++;
4284 if (GET_CODE (operands[1]) == MEM)
4285 return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
4287 return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
4289 [(set_attr "type" "fcvt")
4290 (set_attr "mode" "SF")
4291 (set_attr "length" "12,16,12")])
4294 (define_expand "fixuns_truncdfsi2"
4295 [(set (match_operand:SI 0 "register_operand" "")
4296 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
4297 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4300 rtx reg1 = gen_reg_rtx (DFmode);
4301 rtx reg2 = gen_reg_rtx (DFmode);
4302 rtx reg3 = gen_reg_rtx (SImode);
4303 rtx label1 = gen_label_rtx ();
4304 rtx label2 = gen_label_rtx ();
4305 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
4307 if (reg1) /* turn off complaints about unreached code */
4309 emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
4310 do_pending_stack_adjust ();
4312 emit_insn (gen_cmpdf (operands[1], reg1));
4313 emit_jump_insn (gen_bge (label1));
4315 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
4316 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4317 gen_rtx_LABEL_REF (VOIDmode, label2)));
4320 emit_label (label1);
4321 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4322 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
4324 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
4325 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4327 emit_label (label2);
4329 /* allow REG_NOTES to be set on last insn (labels don't have enough
4330 fields, and can't be used for REG_NOTES anyway). */
4331 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4337 (define_expand "fixuns_truncdfdi2"
4338 [(set (match_operand:DI 0 "register_operand" "")
4339 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
4340 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4343 rtx reg1 = gen_reg_rtx (DFmode);
4344 rtx reg2 = gen_reg_rtx (DFmode);
4345 rtx reg3 = gen_reg_rtx (DImode);
4346 rtx label1 = gen_label_rtx ();
4347 rtx label2 = gen_label_rtx ();
4348 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
4350 if (reg1) /* turn off complaints about unreached code */
4352 emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
4353 do_pending_stack_adjust ();
4355 emit_insn (gen_cmpdf (operands[1], reg1));
4356 emit_jump_insn (gen_bge (label1));
4358 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
4359 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4360 gen_rtx_LABEL_REF (VOIDmode, label2)));
4363 emit_label (label1);
4364 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4365 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
4366 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4368 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
4369 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4371 emit_label (label2);
4373 /* allow REG_NOTES to be set on last insn (labels don't have enough
4374 fields, and can't be used for REG_NOTES anyway). */
4375 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4381 (define_expand "fixuns_truncsfsi2"
4382 [(set (match_operand:SI 0 "register_operand" "")
4383 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
4387 rtx reg1 = gen_reg_rtx (SFmode);
4388 rtx reg2 = gen_reg_rtx (SFmode);
4389 rtx reg3 = gen_reg_rtx (SImode);
4390 rtx label1 = gen_label_rtx ();
4391 rtx label2 = gen_label_rtx ();
4392 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
4394 if (reg1) /* turn off complaints about unreached code */
4396 emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
4397 do_pending_stack_adjust ();
4399 emit_insn (gen_cmpsf (operands[1], reg1));
4400 emit_jump_insn (gen_bge (label1));
4402 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
4403 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4404 gen_rtx_LABEL_REF (VOIDmode, label2)));
4407 emit_label (label1);
4408 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4409 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
4411 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
4412 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4414 emit_label (label2);
4416 /* allow REG_NOTES to be set on last insn (labels don't have enough
4417 fields, and can't be used for REG_NOTES anyway). */
4418 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4424 (define_expand "fixuns_truncsfdi2"
4425 [(set (match_operand:DI 0 "register_operand" "")
4426 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
4427 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4430 rtx reg1 = gen_reg_rtx (SFmode);
4431 rtx reg2 = gen_reg_rtx (SFmode);
4432 rtx reg3 = gen_reg_rtx (DImode);
4433 rtx label1 = gen_label_rtx ();
4434 rtx label2 = gen_label_rtx ();
4435 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
4437 if (reg1) /* turn off complaints about unreached code */
4439 emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
4440 do_pending_stack_adjust ();
4442 emit_insn (gen_cmpsf (operands[1], reg1));
4443 emit_jump_insn (gen_bge (label1));
4445 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
4446 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4447 gen_rtx_LABEL_REF (VOIDmode, label2)));
4450 emit_label (label1);
4451 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4452 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
4453 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4455 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
4456 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4458 emit_label (label2);
4460 /* allow REG_NOTES to be set on last insn (labels don't have enough
4461 fields, and can't be used for REG_NOTES anyway). */
4462 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4469 ;; ....................
4473 ;; ....................
4475 ;; Bit field extract patterns which use lwl/lwr.
4477 ;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
4478 ;; It isn't clear whether this will give better code.
4480 ;; Only specify the mode operand 1, the rest are assumed to be word_mode.
4481 (define_expand "extv"
4482 [(set (match_operand 0 "register_operand" "")
4483 (sign_extract (match_operand:QI 1 "memory_operand" "")
4484 (match_operand 2 "immediate_operand" "")
4485 (match_operand 3 "immediate_operand" "")))]
4489 /* If the field does not start on a byte boundary, then fail. */
4490 if (INTVAL (operands[3]) % 8 != 0)
4493 /* MIPS I and MIPS II can only handle a 32bit field. */
4494 if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
4497 /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
4499 && INTVAL (operands[2]) != 64
4500 && INTVAL (operands[2]) != 32)
4503 /* This can happen for a 64 bit target, when extracting a value from
4504 a 64 bit union member. extract_bit_field doesn't verify that our
4505 source matches the predicate, so we force it to be a MEM here. */
4506 if (GET_CODE (operands[1]) != MEM)
4509 /* Change the mode to BLKmode for aliasing purposes. */
4510 operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
4512 /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value. */
4513 if (INTVAL (operands[2]) == 64)
4514 emit_insn (gen_movdi_uld (operands[0], operands[1]));
4519 operands[0] = gen_lowpart (SImode, operands[0]);
4520 if (operands[0] == NULL_RTX)
4523 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
4528 ;; Only specify the mode operand 1, the rest are assumed to be word_mode.
4529 (define_expand "extzv"
4530 [(set (match_operand 0 "register_operand" "")
4531 (zero_extract (match_operand:QI 1 "memory_operand" "")
4532 (match_operand 2 "immediate_operand" "")
4533 (match_operand 3 "immediate_operand" "")))]
4537 /* If the field does not start on a byte boundary, then fail. */
4538 if (INTVAL (operands[3]) % 8 != 0)
4541 /* MIPS I and MIPS II can only handle a 32bit field. */
4542 if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
4545 /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
4547 && INTVAL (operands[2]) != 64
4548 && INTVAL (operands[2]) != 32)
4551 /* This can happen for a 64 bit target, when extracting a value from
4552 a 64 bit union member. extract_bit_field doesn't verify that our
4553 source matches the predicate, so we force it to be a MEM here. */
4554 if (GET_CODE (operands[1]) != MEM)
4557 /* Change the mode to BLKmode for aliasing purposes. */
4558 operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
4560 /* Otherwise, emit a lwl/lwr pair to load the value. */
4561 if (INTVAL (operands[2]) == 64)
4562 emit_insn (gen_movdi_uld (operands[0], operands[1]));
4567 operands[0] = gen_lowpart (SImode, operands[0]);
4568 if (operands[0] == NULL_RTX)
4571 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
4576 ;; Only specify the mode operands 0, the rest are assumed to be word_mode.
4577 (define_expand "insv"
4578 [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
4579 (match_operand 1 "immediate_operand" "")
4580 (match_operand 2 "immediate_operand" ""))
4581 (match_operand 3 "register_operand" ""))]
4585 /* If the field does not start on a byte boundary, then fail. */
4586 if (INTVAL (operands[2]) % 8 != 0)
4589 /* MIPS I and MIPS II can only handle a 32bit field. */
4590 if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
4593 /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
4595 && INTVAL (operands[1]) != 64
4596 && INTVAL (operands[1]) != 32)
4599 /* This can happen for a 64 bit target, when storing into a 32 bit union
4600 member. store_bit_field doesn't verify that our target matches the
4601 predicate, so we force it to be a MEM here. */
4602 if (GET_CODE (operands[0]) != MEM)
4605 /* Change the mode to BLKmode for aliasing purposes. */
4606 operands[0] = change_address (operands[0], BLKmode, XEXP (operands[0], 0));
4608 /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value. */
4609 if (INTVAL (operands[1]) == 64)
4610 emit_insn (gen_movdi_usd (operands[0], operands[3]));
4615 operands[3] = gen_lowpart (SImode, operands[3]);
4616 if (operands[3] == NULL_RTX)
4619 emit_insn (gen_movsi_usw (operands[0], operands[3]));
4624 ;; unaligned word moves generated by the bit field patterns
4626 (define_insn "movsi_ulw"
4627 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
4628 (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
4632 rtx offset = const0_rtx;
4633 rtx addr = XEXP (operands[1], 0);
4634 rtx mem_addr = eliminate_constant_term (addr, &offset);
4638 mips_count_memory_refs (operands[1], 2);
4640 /* The stack/frame pointers are always aligned, so we can convert
4641 to the faster lw if we are referencing an aligned stack location. */
4643 if ((INTVAL (offset) & 3) == 0
4644 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
4645 ret = \"lw\\t%0,%1\";
4647 ret = \"ulw\\t%0,%1\";
4649 return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
4651 [(set_attr "type" "load,load")
4652 (set_attr "mode" "SI")
4653 (set_attr "length" "8,16")])
4655 (define_insn "movsi_usw"
4656 [(set (match_operand:BLK 0 "memory_operand" "=R,o")
4657 (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
4661 rtx offset = const0_rtx;
4662 rtx addr = XEXP (operands[0], 0);
4663 rtx mem_addr = eliminate_constant_term (addr, &offset);
4666 mips_count_memory_refs (operands[0], 2);
4668 /* The stack/frame pointers are always aligned, so we can convert
4669 to the faster sw if we are referencing an aligned stack location. */
4671 if ((INTVAL (offset) & 3) == 0
4672 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
4673 return \"sw\\t%z1,%0\";
4675 return \"usw\\t%z1,%0\";
4677 [(set_attr "type" "store")
4678 (set_attr "mode" "SI")
4679 (set_attr "length" "8,16")])
4681 ;; Bit field extract patterns which use ldl/ldr.
4683 ;; unaligned double word moves generated by the bit field patterns
4685 (define_insn "movdi_uld"
4686 [(set (match_operand:DI 0 "register_operand" "=&d,&d")
4687 (unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
4691 rtx offset = const0_rtx;
4692 rtx addr = XEXP (operands[1], 0);
4693 rtx mem_addr = eliminate_constant_term (addr, &offset);
4697 mips_count_memory_refs (operands[1], 2);
4699 /* The stack/frame pointers are always aligned, so we can convert
4700 to the faster lw if we are referencing an aligned stack location. */
4702 if ((INTVAL (offset) & 7) == 0
4703 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
4704 ret = \"ld\\t%0,%1\";
4706 ret = \"uld\\t%0,%1\";
4708 return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
4710 [(set_attr "type" "load,load")
4711 (set_attr "mode" "SI")
4712 (set_attr "length" "8,16")])
4714 (define_insn "movdi_usd"
4715 [(set (match_operand:BLK 0 "memory_operand" "=R,o")
4716 (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
4720 rtx offset = const0_rtx;
4721 rtx addr = XEXP (operands[0], 0);
4722 rtx mem_addr = eliminate_constant_term (addr, &offset);
4725 mips_count_memory_refs (operands[0], 2);
4727 /* The stack/frame pointers are always aligned, so we can convert
4728 to the faster sw if we are referencing an aligned stack location. */
4730 if ((INTVAL (offset) & 7) == 0
4731 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
4732 return \"sd\\t%1,%0\";
4734 return \"usd\\t%z1,%0\";
4736 [(set_attr "type" "store")
4737 (set_attr "mode" "SI")
4738 (set_attr "length" "8,16")])
4740 ;; These two patterns support loading addresses with two instructions instead
4741 ;; of using the macro instruction la.
4743 ;; ??? mips_move_1word has support for HIGH, so this pattern may be
4747 [(set (match_operand:SI 0 "register_operand" "=r")
4748 (high:SI (match_operand:SI 1 "immediate_operand" "")))]
4749 "mips_split_addresses && !TARGET_MIPS16"
4750 "lui\\t%0,%%hi(%1) # high"
4751 [(set_attr "type" "move")])
4754 [(set (match_operand:SI 0 "register_operand" "=r")
4755 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
4756 (match_operand:SI 2 "immediate_operand" "")))]
4757 "mips_split_addresses && !TARGET_MIPS16"
4758 "addiu\\t%0,%1,%%lo(%2) # low"
4759 [(set_attr "type" "arith")
4760 (set_attr "mode" "SI")])
4762 ;; 64-bit integer moves
4764 ;; Unlike most other insns, the move insns can't be split with
4765 ;; different predicates, because register spilling and other parts of
4766 ;; the compiler, have memoized the insn number already.
4768 (define_expand "movdi"
4769 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4770 (match_operand:DI 1 "general_operand" ""))]
4774 if (mips_split_addresses && mips_check_split (operands[1], DImode))
4776 enum machine_mode mode = GET_MODE (operands[0]);
4777 rtx tem = ((reload_in_progress | reload_completed)
4778 ? operands[0] : gen_reg_rtx (mode));
4780 emit_insn (gen_rtx_SET (VOIDmode, tem,
4781 gen_rtx_HIGH (mode, operands[1])));
4783 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
4786 /* If we are generating embedded PIC code, and we are referring to a
4787 symbol in the .text section, we must use an offset from the start
4789 if (TARGET_EMBEDDED_PIC
4790 && (GET_CODE (operands[1]) == LABEL_REF
4791 || (GET_CODE (operands[1]) == SYMBOL_REF
4792 && ! SYMBOL_REF_FLAG (operands[1]))))
4796 temp = embedded_pic_offset (operands[1]);
4797 temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_rtx,
4798 force_reg (DImode, temp));
4799 emit_move_insn (operands[0], force_reg (DImode, temp));
4803 /* If operands[1] is a constant address illegal for pic, then we need to
4804 handle it just like LEGITIMIZE_ADDRESS does. */
4805 if (flag_pic && pic_address_needs_scratch (operands[1]))
4807 rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
4808 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
4810 if (! SMALL_INT (temp2))
4811 temp2 = force_reg (DImode, temp2);
4813 emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
4817 /* On the mips16, we can handle a GP relative reference by adding in
4818 $gp. We need to check the name to see whether this is a string
4821 && register_operand (operands[0], DImode)
4822 && GET_CODE (operands[1]) == SYMBOL_REF
4823 && SYMBOL_REF_FLAG (operands[1]))
4825 const char *name = XSTR (operands[1], 0);
4828 || strncmp (name + 1, LOCAL_LABEL_PREFIX,
4829 sizeof LOCAL_LABEL_PREFIX - 1) != 0)
4833 if (reload_in_progress || reload_completed)
4835 /* In movsi we use the constant table here. However, in
4836 this case, we're better off copying $28 into a
4837 register and adding, because the constant table entry
4838 would be 8 bytes. */
4839 base_reg = operands[0];
4840 emit_move_insn (base_reg,
4841 gen_rtx (CONST, DImode,
4842 gen_rtx (REG, DImode,
4843 GP_REG_FIRST + 28)));
4847 base_reg = gen_reg_rtx (Pmode);
4848 emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
4851 emit_move_insn (operands[0],
4852 gen_rtx (PLUS, Pmode, base_reg,
4853 mips16_gp_offset (operands[1])));
4858 if ((reload_in_progress | reload_completed) == 0
4859 && !register_operand (operands[0], DImode)
4860 && !register_operand (operands[1], DImode)
4862 || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
4863 && operands[1] != CONST0_RTX (DImode))))
4865 rtx temp = force_reg (DImode, operands[1]);
4866 emit_move_insn (operands[0], temp);
4871 ;; For mips16, we need a special case to handle storing $31 into
4872 ;; memory, since we don't have a constraint to match $31. This
4873 ;; instruction can be generated by save_restore_insns.
4876 [(set (match_operand:DI 0 "memory_operand" "=R,m")
4878 "TARGET_MIPS16 && TARGET_64BIT"
4881 operands[1] = gen_rtx (REG, DImode, 31);
4882 return mips_move_2words (operands, insn);
4884 [(set_attr "type" "store")
4885 (set_attr "mode" "DI")
4886 (set_attr "length" "4,8")])
4888 (define_insn "movdi_internal"
4889 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x")
4890 (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))]
4891 "!TARGET_64BIT && !TARGET_MIPS16
4892 && (register_operand (operands[0], DImode)
4893 || register_operand (operands[1], DImode)
4894 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
4895 || operands[1] == CONST0_RTX (DImode))"
4896 "* return mips_move_2words (operands, insn); "
4897 [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo,hilo")
4898 (set_attr "mode" "DI")
4899 (set_attr "length" "8,16,8,16,8,16,8,8,8")])
4902 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d")
4903 (match_operand:DI 1 "general_operand" "d,d,y,K,N,R,To,d,d,*x"))]
4904 "!TARGET_64BIT && TARGET_MIPS16
4905 && (register_operand (operands[0], DImode)
4906 || register_operand (operands[1], DImode))"
4907 "* return mips_move_2words (operands, insn);"
4908 [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
4909 (set_attr "mode" "DI")
4910 (set_attr "length" "8,8,8,8,12,8,16,8,16,8")])
4913 [(set (match_operand:DI 0 "register_operand" "")
4914 (match_operand:DI 1 "register_operand" ""))]
4915 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4916 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
4917 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
4919 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
4920 (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
4923 (define_insn "movdi_internal2"
4924 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x,*d,*x,*a")
4925 (match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J"))]
4926 "TARGET_64BIT && !TARGET_MIPS16
4927 && (register_operand (operands[0], DImode)
4928 || se_register_operand (operands[1], DImode)
4929 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
4930 || operands[1] == CONST0_RTX (DImode))"
4931 "* return mips_move_2words (operands, insn); "
4932 [(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo")
4933 (set_attr "mode" "DI")
4934 (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,8")])
4937 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
4938 (match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x"))]
4939 "TARGET_64BIT && TARGET_MIPS16
4940 && (register_operand (operands[0], DImode)
4941 || se_register_operand (operands[1], DImode))"
4942 "* return mips_move_2words (operands, insn);"
4943 [(set_attr "type" "move,move,move,arith,arith,arith,load,load,store,store,hilo")
4944 (set_attr "mode" "DI")
4945 (set_attr_alternative "length"
4949 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
4952 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
4955 (if_then_else (match_operand:VOID 1 "m16_usym5_4" "")
4964 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4965 ;; when the original load is a 4 byte instruction but the add and the
4966 ;; load are 2 2 byte instructions.
4969 [(set (match_operand:DI 0 "register_operand" "")
4970 (mem:DI (plus:DI (match_dup 0)
4971 (match_operand:DI 1 "const_int_operand" ""))))]
4972 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4973 && GET_CODE (operands[0]) == REG
4974 && M16_REG_P (REGNO (operands[0]))
4975 && GET_CODE (operands[1]) == CONST_INT
4976 && ((INTVAL (operands[1]) < 0
4977 && INTVAL (operands[1]) >= -0x10)
4978 || (INTVAL (operands[1]) >= 32 * 8
4979 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4980 || (INTVAL (operands[1]) >= 0
4981 && INTVAL (operands[1]) < 32 * 8
4982 && (INTVAL (operands[1]) & 7) != 0))"
4983 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4984 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4987 HOST_WIDE_INT val = INTVAL (operands[1]);
4990 operands[2] = GEN_INT (0);
4991 else if (val >= 32 * 8)
4995 operands[1] = GEN_INT (0x8 + off);
4996 operands[2] = GEN_INT (val - off - 0x8);
5002 operands[1] = GEN_INT (off);
5003 operands[2] = GEN_INT (val - off);
5007 ;; Handle input reloads in DImode.
5008 ;; This is mainly to handle reloading HILO_REGNUM. Note that we may
5009 ;; see it as the source or the destination, depending upon which way
5010 ;; reload handles the instruction.
5011 ;; Making the second operand TImode is a trick. The compiler may
5012 ;; reuse the same register for operand 0 and operand 2. Using TImode
5013 ;; gives us two registers, so we can always use the one which is not
5016 (define_expand "reload_indi"
5017 [(set (match_operand:DI 0 "register_operand" "=b")
5018 (match_operand:DI 1 "" "b"))
5019 (clobber (match_operand:TI 2 "register_operand" "=&d"))]
5023 rtx scratch = gen_rtx_REG (DImode,
5024 (REGNO (operands[0]) == REGNO (operands[2])
5025 ? REGNO (operands[2]) + 1
5026 : REGNO (operands[2])));
5028 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
5030 if (GET_CODE (operands[1]) == MEM)
5032 rtx memword, offword, hi_word, lo_word;
5033 rtx addr = find_replacement (&XEXP (operands[1], 0));
5034 rtx op1 = change_address (operands[1], VOIDmode, addr);
5036 scratch = gen_rtx_REG (SImode, REGNO (scratch));
5037 memword = change_address (op1, SImode, NULL_RTX);
5038 offword = change_address (adj_offsettable_operand (op1, 4),
5040 if (BYTES_BIG_ENDIAN)
5050 emit_move_insn (scratch, hi_word);
5051 emit_move_insn (gen_rtx_REG (SImode, 64), scratch);
5052 emit_move_insn (scratch, lo_word);
5053 emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
5054 emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
5058 emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
5059 emit_insn (gen_movdi (gen_rtx_REG (DImode, 64), scratch));
5060 emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
5061 emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
5062 emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
5063 emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
5067 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
5069 emit_insn (gen_movdi (scratch, gen_rtx_REG (DImode, 65)));
5070 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
5071 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
5072 emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64)));
5073 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5074 emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
5075 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
5078 /* This handles moves between a float register and HI/LO. */
5079 emit_move_insn (scratch, operands[1]);
5080 emit_move_insn (operands[0], scratch);
5084 ;; Handle output reloads in DImode.
5086 ;; Reloading HILO_REG in MIPS16 mode requires two scratch registers, so we
5087 ;; use a TImode scratch reg.
5089 (define_expand "reload_outdi"
5090 [(set (match_operand:DI 0 "" "=b")
5091 (match_operand:DI 1 "se_register_operand" "b"))
5092 (clobber (match_operand:TI 2 "register_operand" "=&d"))]
5096 rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5098 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
5100 emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
5101 emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
5102 emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
5103 emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
5104 emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
5105 emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
5108 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
5110 if (GET_CODE (operands[0]) == MEM)
5112 rtx scratch, memword, offword, hi_word, lo_word;
5113 rtx addr = find_replacement (&XEXP (operands[0], 0));
5114 rtx op0 = change_address (operands[0], VOIDmode, addr);
5116 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5117 memword = change_address (op0, SImode, NULL_RTX);
5118 offword = change_address (adj_offsettable_operand (op0, 4),
5120 if (BYTES_BIG_ENDIAN)
5130 emit_move_insn (scratch, gen_rtx_REG (SImode, 64));
5131 emit_move_insn (hi_word, scratch);
5132 emit_move_insn (scratch, gen_rtx_REG (SImode, 65));
5133 emit_move_insn (lo_word, scratch);
5134 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
5136 else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0])))
5138 /* Handle the case where operand[0] is not a 'd' register,
5139 and hence we can not directly move from the HILO register
5141 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5142 emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
5143 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
5144 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
5145 emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64)));
5146 emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
5147 emit_insn (gen_iordi3 (scratch, scratch, scratch2));
5148 emit_insn (gen_movdi (operands[0], scratch));
5149 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
5153 emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
5154 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
5155 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
5156 emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
5157 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5158 emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
5159 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
5163 /* This handles moves between a float register and HI/LO. */
5164 emit_move_insn (scratch, operands[1]);
5165 emit_move_insn (operands[0], scratch);
5169 ;; 32-bit Integer moves
5172 [(set (match_operand:SI 0 "register_operand" "")
5173 (match_operand:SI 1 "large_int" ""))]
5174 "!TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
5178 (ior:SI (match_dup 0)
5182 operands[2] = GEN_INT (INTVAL (operands[1]) & BITMASK_UPPER16);
5183 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
5186 ;; Unlike most other insns, the move insns can't be split with
5187 ;; different predicates, because register spilling and other parts of
5188 ;; the compiler, have memoized the insn number already.
5190 (define_expand "movsi"
5191 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5192 (match_operand:SI 1 "general_operand" ""))]
5196 if (mips_split_addresses && mips_check_split (operands[1], SImode))
5198 enum machine_mode mode = GET_MODE (operands[0]);
5199 rtx tem = ((reload_in_progress | reload_completed)
5200 ? operands[0] : gen_reg_rtx (mode));
5202 emit_insn (gen_rtx_SET (VOIDmode, tem,
5203 gen_rtx_HIGH (mode, operands[1])));
5205 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
5208 /* If we are generating embedded PIC code, and we are referring to a
5209 symbol in the .text section, we must use an offset from the start
5211 if (TARGET_EMBEDDED_PIC
5212 && (GET_CODE (operands[1]) == LABEL_REF
5213 || (GET_CODE (operands[1]) == SYMBOL_REF
5214 && ! SYMBOL_REF_FLAG (operands[1]))))
5218 temp = embedded_pic_offset (operands[1]);
5219 temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_rtx,
5220 force_reg (SImode, temp));
5221 emit_move_insn (operands[0], force_reg (SImode, temp));
5225 /* If operands[1] is a constant address invalid for pic, then we need to
5226 handle it just like LEGITIMIZE_ADDRESS does. */
5227 if (flag_pic && pic_address_needs_scratch (operands[1]))
5229 rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
5230 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
5232 if (! SMALL_INT (temp2))
5233 temp2 = force_reg (SImode, temp2);
5235 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, temp2));
5239 /* On the mips16, we can handle a GP relative reference by adding in
5240 $gp. We need to check the name to see whether this is a string
5243 && register_operand (operands[0], SImode)
5244 && GET_CODE (operands[1]) == SYMBOL_REF
5245 && SYMBOL_REF_FLAG (operands[1]))
5247 const char *name = XSTR (operands[1], 0);
5250 || strncmp (name + 1, LOCAL_LABEL_PREFIX,
5251 sizeof LOCAL_LABEL_PREFIX - 1) != 0)
5255 if (reload_in_progress || reload_completed)
5257 /* We need to reload this address. In this case we
5258 aren't going to have a chance to combine loading the
5259 address with the load or store. That means that we
5260 can either generate a 2 byte move followed by a 4
5261 byte addition, or a 2 byte load with a 4 byte entry
5262 in the constant table. Since the entry in the
5263 constant table might be shared, we're better off, on
5264 average, loading the address from the constant table. */
5265 emit_move_insn (operands[0],
5266 force_const_mem (SImode, operands[1]));
5270 base_reg = gen_reg_rtx (Pmode);
5271 emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
5273 emit_move_insn (operands[0],
5274 gen_rtx (PLUS, Pmode, base_reg,
5275 mips16_gp_offset (operands[1])));
5280 if ((reload_in_progress | reload_completed) == 0
5281 && !register_operand (operands[0], SImode)
5282 && !register_operand (operands[1], SImode)
5284 || GET_CODE (operands[1]) != CONST_INT
5285 || INTVAL (operands[1]) != 0))
5287 rtx temp = force_reg (SImode, operands[1]);
5288 emit_move_insn (operands[0], temp);
5293 ;; For mips16, we need a special case to handle storing $31 into
5294 ;; memory, since we don't have a constraint to match $31. This
5295 ;; instruction can be generated by save_restore_insns.
5298 [(set (match_operand:SI 0 "memory_operand" "=R,m")
5303 operands[1] = gen_rtx (REG, SImode, 31);
5304 return mips_move_1word (operands, insn, FALSE);
5306 [(set_attr "type" "store")
5307 (set_attr "mode" "SI")
5308 (set_attr "length" "4,8")])
5310 ;; The difference between these two is whether or not ints are allowed
5311 ;; in FP registers (off by default, use -mdebugh to enable).
5313 (define_insn "movsi_internal1"
5314 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d")
5315 (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a"))]
5316 "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
5317 && (register_operand (operands[0], SImode)
5318 || register_operand (operands[1], SImode)
5319 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
5320 "* return mips_move_1word (operands, insn, FALSE);"
5321 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo")
5322 (set_attr "mode" "SI")
5323 (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4")])
5325 (define_insn "movsi_internal2"
5326 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
5327 (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
5328 "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
5329 && (register_operand (operands[0], SImode)
5330 || register_operand (operands[1], SImode)
5331 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
5332 "* return mips_move_1word (operands, insn, FALSE);"
5333 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo")
5334 (set_attr "mode" "SI")
5335 (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,4,4")])
5337 ;; This is the mips16 movsi instruction. We accept a small integer as
5338 ;; the source if the destination is a GP memory reference. This is
5339 ;; because we want the combine pass to turn adding a GP reference to a
5340 ;; register into a direct GP reference, but the combine pass will pass
5341 ;; in the source as a constant if it finds an equivalent one. If the
5342 ;; instruction is recognized, reload will force the constant back out
5346 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,d,R,m,*d,*d")
5347 (match_operand:SI 1 "move_operand" "d,d,y,S,K,N,s,R,m,d,d,*x,*a"))]
5349 && (register_operand (operands[0], SImode)
5350 || register_operand (operands[1], SImode)
5351 || (GET_CODE (operands[0]) == MEM
5352 && GET_CODE (XEXP (operands[0], 0)) == PLUS
5353 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST
5354 && mips16_gp_offset_p (XEXP (XEXP (operands[0], 0), 1))
5355 && GET_CODE (operands[1]) == CONST_INT
5356 && (SMALL_INT (operands[1])
5357 || SMALL_INT_UNSIGNED (operands[1]))))"
5358 "* return mips_move_1word (operands, insn, FALSE);"
5359 [(set_attr "type" "move,move,move,load,arith,arith,arith,load,load,store,store,hilo,hilo")
5360 (set_attr "mode" "SI")
5361 (set_attr_alternative "length"
5366 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
5369 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
5372 (if_then_else (match_operand:VOID 1 "m16_usym8_4" "")
5382 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
5383 ;; when the original load is a 4 byte instruction but the add and the
5384 ;; load are 2 2 byte instructions.
5387 [(set (match_operand:SI 0 "register_operand" "")
5388 (mem:SI (plus:SI (match_dup 0)
5389 (match_operand:SI 1 "const_int_operand" ""))))]
5390 "TARGET_MIPS16 && reload_completed
5391 && GET_CODE (operands[0]) == REG
5392 && M16_REG_P (REGNO (operands[0]))
5393 && GET_CODE (operands[1]) == CONST_INT
5394 && ((INTVAL (operands[1]) < 0
5395 && INTVAL (operands[1]) >= -0x80)
5396 || (INTVAL (operands[1]) >= 32 * 4
5397 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
5398 || (INTVAL (operands[1]) >= 0
5399 && INTVAL (operands[1]) < 32 * 4
5400 && (INTVAL (operands[1]) & 3) != 0))"
5401 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
5402 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
5405 HOST_WIDE_INT val = INTVAL (operands[1]);
5408 operands[2] = GEN_INT (0);
5409 else if (val >= 32 * 4)
5413 operands[1] = GEN_INT (0x7c + off);
5414 operands[2] = GEN_INT (val - off - 0x7c);
5420 operands[1] = GEN_INT (off);
5421 operands[2] = GEN_INT (val - off);
5425 ;; On the mips16, we can split a load of certain constants into a load
5426 ;; and an add. This turns a 4 byte instruction into 2 2 byte
5430 [(set (match_operand:SI 0 "register_operand" "")
5431 (match_operand:SI 1 "const_int_operand" ""))]
5432 "TARGET_MIPS16 && reload_completed
5433 && GET_CODE (operands[0]) == REG
5434 && M16_REG_P (REGNO (operands[0]))
5435 && GET_CODE (operands[1]) == CONST_INT
5436 && INTVAL (operands[1]) >= 0x100
5437 && INTVAL (operands[1]) <= 0xff + 0x7f"
5438 [(set (match_dup 0) (match_dup 1))
5439 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
5442 int val = INTVAL (operands[1]);
5444 operands[1] = GEN_INT (0xff);
5445 operands[2] = GEN_INT (val - 0xff);
5448 ;; On the mips16, we can split a load of a negative constant into a
5449 ;; load and a neg. That's what mips_move_1word will generate anyhow.
5452 [(set (match_operand:SI 0 "register_operand" "")
5453 (match_operand:SI 1 "const_int_operand" ""))]
5454 "TARGET_MIPS16 && reload_completed
5455 && GET_CODE (operands[0]) == REG
5456 && M16_REG_P (REGNO (operands[0]))
5457 && GET_CODE (operands[1]) == CONST_INT
5458 && INTVAL (operands[1]) < 0
5459 && INTVAL (operands[1]) > - 0x8000"
5460 [(set (match_dup 0) (match_dup 1))
5461 (set (match_dup 0) (neg:SI (match_dup 0)))]
5464 operands[1] = GEN_INT (- INTVAL (operands[1]));
5467 ;; Reload HILO_REGNUM in SI mode. This needs a scratch register in
5468 ;; order to set the sign bit correctly in the HI register.
5470 (define_expand "reload_outsi"
5471 [(set (match_operand:SI 0 "general_operand" "=b")
5472 (match_operand:SI 1 "register_operand" "b"))
5473 (clobber (match_operand:SI 2 "register_operand" "=&d"))]
5474 "TARGET_64BIT || TARGET_MIPS16"
5478 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
5480 emit_insn (gen_movsi (gen_rtx_REG (SImode, 65), operands[1]));
5481 emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
5482 emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
5483 emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
5486 /* Use a mult to reload LO on mips16. ??? This is hideous. */
5488 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
5490 emit_insn (gen_movsi (operands[2], GEN_INT (1)));
5491 /* This is gen_mulsi3_internal, but we need to fill in the
5492 scratch registers. */
5493 emit_insn (gen_rtx (PARALLEL, VOIDmode,
5495 gen_rtx (SET, VOIDmode,
5497 gen_rtx (MULT, SImode,
5500 gen_rtx (CLOBBER, VOIDmode,
5501 gen_rtx (REG, SImode, 64)),
5502 gen_rtx (CLOBBER, VOIDmode,
5503 gen_rtx (REG, SImode, 66)))));
5506 /* FIXME: I don't know how to get a value into the HI register. */
5507 if (GET_CODE (operands[0]) == REG
5508 && (TARGET_MIPS16 ? M16_REG_P (REGNO (operands[0]))
5509 : GP_REG_P (REGNO (operands[0]))))
5511 emit_move_insn (operands[0], operands[1]);
5514 /* This handles moves between a float register and HI/LO. */
5515 emit_move_insn (operands[2], operands[1]);
5516 emit_move_insn (operands[0], operands[2]);
5520 ;; Reload a value into HI or LO. There is no mthi or mtlo on mips16,
5521 ;; so we use a mult. ??? This is hideous, and we ought to figure out
5522 ;; something better.
5524 ;; We use no predicate for operand1, because it may be a PLUS, and there
5525 ;; is no convenient predicate for that.
5527 (define_expand "reload_insi"
5528 [(set (match_operand:SI 0 "register_operand" "=b")
5529 (match_operand:SI 1 "" "b"))
5530 (clobber (match_operand:SI 2 "register_operand" "=&d"))]
5535 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
5537 emit_insn (gen_movsi (operands[2], GEN_INT (1)));
5538 /* This is gen_mulsi3_internal, but we need to fill in the
5539 scratch registers. */
5540 emit_insn (gen_rtx (PARALLEL, VOIDmode,
5542 gen_rtx (SET, VOIDmode,
5544 gen_rtx (MULT, SImode,
5547 gen_rtx (CLOBBER, VOIDmode,
5548 gen_rtx (REG, SImode, 64)),
5549 gen_rtx (CLOBBER, VOIDmode,
5550 gen_rtx (REG, SImode, 66)))));
5554 /* If this is a plus, then this must be an add of the stack pointer against
5555 either a hard register or a pseudo. */
5556 if (TARGET_MIPS16 && GET_CODE (operands[1]) == PLUS)
5560 if (XEXP (operands[1], 0) == stack_pointer_rtx)
5561 plus_op = XEXP (operands[1], 1);
5562 else if (XEXP (operands[1], 1) == stack_pointer_rtx)
5563 plus_op = XEXP (operands[1], 0);
5567 /* We should have a register now. */
5568 if (GET_CODE (plus_op) != REG)
5571 if (REGNO (plus_op) < FIRST_PSEUDO_REGISTER)
5573 /* We have to have at least one temporary register which is not
5574 overlapping plus_op. */
5575 if (! rtx_equal_p (plus_op, operands[0]))
5577 emit_move_insn (operands[0], stack_pointer_rtx);
5578 emit_insn (gen_addsi3 (operands[0], operands[0], plus_op));
5580 else if (! rtx_equal_p (plus_op, operands[2]))
5582 emit_move_insn (operands[2], stack_pointer_rtx);
5583 emit_insn (gen_addsi3 (operands[0], plus_op, operands[2]));
5590 /* We need two registers in this case. */
5591 if (! rtx_equal_p (operands[0], operands[2]))
5593 emit_move_insn (operands[0], stack_pointer_rtx);
5594 emit_move_insn (operands[2], plus_op);
5595 emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
5603 /* FIXME: I don't know how to get a value into the HI register. */
5604 emit_move_insn (operands[0], operands[1]);
5608 ;; This insn handles moving CCmode values. It's really just a
5609 ;; slightly simplified copy of movsi_internal2, with additional cases
5610 ;; to move a condition register to a general register and to move
5611 ;; between the general registers and the floating point registers.
5613 (define_insn "movcc"
5614 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
5615 (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
5616 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
5617 "* return mips_move_1word (operands, insn, FALSE);"
5618 [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
5619 (set_attr "mode" "SI")
5620 (set_attr "length" "8,4,4,8,4,8,4,4,4,4,8,4,8")])
5622 ;; Reload condition code registers. These need scratch registers.
5624 (define_expand "reload_incc"
5625 [(set (match_operand:CC 0 "register_operand" "=z")
5626 (match_operand:CC 1 "general_operand" "z"))
5627 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
5628 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
5634 /* This is called when are copying some value into a condition code
5635 register. Operand 0 is the condition code register. Operand 1
5636 is the source. Operand 2 is a scratch register; we use TFmode
5637 because we actually need two floating point registers. */
5638 if (! ST_REG_P (true_regnum (operands[0]))
5639 || ! FP_REG_P (true_regnum (operands[2])))
5642 /* We need to get the source in SFmode so that the insn is
5644 if (GET_CODE (operands[1]) == MEM)
5645 source = change_address (operands[1], SFmode, NULL_RTX);
5646 else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
5647 source = gen_rtx_REG (SFmode, true_regnum (operands[1]));
5649 source = operands[1];
5651 fp1 = gen_rtx_REG (SFmode, REGNO (operands[2]));
5652 fp2 = gen_rtx_REG (SFmode, REGNO (operands[2]) + 1);
5654 emit_insn (gen_move_insn (fp1, source));
5655 emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0)));
5656 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
5657 gen_rtx_LT (CCmode, fp2, fp1)));
5662 (define_expand "reload_outcc"
5663 [(set (match_operand:CC 0 "general_operand" "=z")
5664 (match_operand:CC 1 "register_operand" "z"))
5665 (clobber (match_operand:CC 2 "register_operand" "=&d"))]
5666 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
5669 /* This is called when we are copying a condition code register out
5670 to save it somewhere. Operand 0 should be the location we are
5671 going to save it to. Operand 1 should be the condition code
5672 register. Operand 2 should be a scratch general purpose register
5673 created for us by reload. The mips_secondary_reload_class
5674 function should have told reload that we don't need a scratch
5675 register if the destination is a general purpose register anyhow. */
5676 if (ST_REG_P (true_regnum (operands[0]))
5677 || GP_REG_P (true_regnum (operands[0]))
5678 || ! ST_REG_P (true_regnum (operands[1]))
5679 || ! GP_REG_P (true_regnum (operands[2])))
5682 /* All we have to do is copy the value from the condition code to
5683 the data register, which movcc can handle, and then store the
5684 value into the real final destination. */
5685 emit_insn (gen_move_insn (operands[2], operands[1]));
5686 emit_insn (gen_move_insn (operands[0], operands[2]));
5691 ;; MIPS4 supports loading and storing a floating point register from
5692 ;; the sum of two general registers. We use two versions for each of
5693 ;; these four instructions: one where the two general registers are
5694 ;; SImode, and one where they are DImode. This is because general
5695 ;; registers will be in SImode when they hold 32 bit values, but,
5696 ;; since the 32 bit values are always sign extended, the [ls][wd]xc1
5697 ;; instructions will still work correctly.
5699 ;; ??? Perhaps it would be better to support these instructions by
5700 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
5701 ;; these instructions can only be used to load and store floating
5702 ;; point registers, that would probably cause trouble in reload.
5705 [(set (match_operand:SF 0 "register_operand" "=f")
5706 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
5707 (match_operand:SI 2 "register_operand" "d"))))]
5708 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
5710 [(set_attr "type" "load")
5711 (set_attr "mode" "SF")])
5714 [(set (match_operand:SF 0 "register_operand" "=f")
5715 (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
5716 (match_operand:DI 2 "se_register_operand" "d"))))]
5717 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
5719 [(set_attr "type" "load")
5720 (set_attr "mode" "SF")])
5723 [(set (match_operand:DF 0 "register_operand" "=f")
5724 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
5725 (match_operand:SI 2 "register_operand" "d"))))]
5726 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5728 [(set_attr "type" "load")
5729 (set_attr "mode" "DF")])
5732 [(set (match_operand:DF 0 "register_operand" "=f")
5733 (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
5734 (match_operand:DI 2 "se_register_operand" "d"))))]
5735 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5737 [(set_attr "type" "load")
5738 (set_attr "mode" "DF")])
5741 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
5742 (match_operand:SI 2 "register_operand" "d")))
5743 (match_operand:SF 0 "register_operand" "f"))]
5744 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
5746 [(set_attr "type" "store")
5747 (set_attr "mode" "SF")])
5750 [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
5751 (match_operand:DI 2 "se_register_operand" "d")))
5752 (match_operand:SF 0 "register_operand" "f"))]
5753 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
5755 [(set_attr "type" "store")
5756 (set_attr "mode" "SF")])
5759 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
5760 (match_operand:SI 2 "register_operand" "d")))
5761 (match_operand:DF 0 "register_operand" "f"))]
5762 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5764 [(set_attr "type" "store")
5765 (set_attr "mode" "DF")])
5768 [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
5769 (match_operand:DI 2 "se_register_operand" "d")))
5770 (match_operand:DF 0 "register_operand" "f"))]
5771 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5773 [(set_attr "type" "store")
5774 (set_attr "mode" "DF")])
5776 ;; 16-bit Integer moves
5778 ;; Unlike most other insns, the move insns can't be split with
5779 ;; different predicates, because register spilling and other parts of
5780 ;; the compiler, have memoized the insn number already.
5781 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
5783 (define_expand "movhi"
5784 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5785 (match_operand:HI 1 "general_operand" ""))]
5789 if ((reload_in_progress | reload_completed) == 0
5790 && !register_operand (operands[0], HImode)
5791 && !register_operand (operands[1], HImode)
5793 || (GET_CODE (operands[1]) != CONST_INT
5794 || INTVAL (operands[1]) != 0)))
5796 rtx temp = force_reg (HImode, operands[1]);
5797 emit_move_insn (operands[0], temp);
5802 ;; The difference between these two is whether or not ints are allowed
5803 ;; in FP registers (off by default, use -mdebugh to enable).
5805 (define_insn "movhi_internal1"
5806 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
5807 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
5808 "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
5809 && (register_operand (operands[0], HImode)
5810 || register_operand (operands[1], HImode)
5811 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
5812 "* return mips_move_1word (operands, insn, TRUE);"
5813 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
5814 (set_attr "mode" "HI")
5815 (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
5817 (define_insn "movhi_internal2"
5818 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
5819 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
5820 "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
5821 && (register_operand (operands[0], HImode)
5822 || register_operand (operands[1], HImode)
5823 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
5824 "* return mips_move_1word (operands, insn, TRUE);"
5825 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
5826 (set_attr "mode" "HI")
5827 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
5830 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
5831 (match_operand:HI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
5833 && (register_operand (operands[0], HImode)
5834 || register_operand (operands[1], HImode))"
5835 "* return mips_move_1word (operands, insn, TRUE);"
5836 [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
5837 (set_attr "mode" "HI")
5838 (set_attr_alternative "length"
5842 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
5845 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
5855 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
5856 ;; when the original load is a 4 byte instruction but the add and the
5857 ;; load are 2 2 byte instructions.
5860 [(set (match_operand:HI 0 "register_operand" "")
5861 (mem:HI (plus:SI (match_dup 0)
5862 (match_operand:SI 1 "const_int_operand" ""))))]
5863 "TARGET_MIPS16 && reload_completed
5864 && GET_CODE (operands[0]) == REG
5865 && M16_REG_P (REGNO (operands[0]))
5866 && GET_CODE (operands[1]) == CONST_INT
5867 && ((INTVAL (operands[1]) < 0
5868 && INTVAL (operands[1]) >= -0x80)
5869 || (INTVAL (operands[1]) >= 32 * 2
5870 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
5871 || (INTVAL (operands[1]) >= 0
5872 && INTVAL (operands[1]) < 32 * 2
5873 && (INTVAL (operands[1]) & 1) != 0))"
5874 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
5875 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
5878 HOST_WIDE_INT val = INTVAL (operands[1]);
5881 operands[2] = GEN_INT (0);
5882 else if (val >= 32 * 2)
5886 operands[1] = GEN_INT (0x7e + off);
5887 operands[2] = GEN_INT (val - off - 0x7e);
5893 operands[1] = GEN_INT (off);
5894 operands[2] = GEN_INT (val - off);
5898 ;; 8-bit Integer moves
5900 ;; Unlike most other insns, the move insns can't be split with
5901 ;; different predicates, because register spilling and other parts of
5902 ;; the compiler, have memoized the insn number already.
5903 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
5905 (define_expand "movqi"
5906 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5907 (match_operand:QI 1 "general_operand" ""))]
5911 if ((reload_in_progress | reload_completed) == 0
5912 && !register_operand (operands[0], QImode)
5913 && !register_operand (operands[1], QImode)
5915 || (GET_CODE (operands[1]) != CONST_INT
5916 || INTVAL (operands[1]) != 0)))
5918 rtx temp = force_reg (QImode, operands[1]);
5919 emit_move_insn (operands[0], temp);
5924 ;; The difference between these two is whether or not ints are allowed
5925 ;; in FP registers (off by default, use -mdebugh to enable).
5927 (define_insn "movqi_internal1"
5928 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
5929 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
5930 "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
5931 && (register_operand (operands[0], QImode)
5932 || register_operand (operands[1], QImode)
5933 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
5934 "* return mips_move_1word (operands, insn, TRUE);"
5935 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
5936 (set_attr "mode" "QI")
5937 (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
5939 (define_insn "movqi_internal2"
5940 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
5941 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
5942 "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
5943 && (register_operand (operands[0], QImode)
5944 || register_operand (operands[1], QImode)
5945 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
5946 "* return mips_move_1word (operands, insn, TRUE);"
5947 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
5948 (set_attr "mode" "QI")
5949 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
5952 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
5953 (match_operand:QI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
5955 && (register_operand (operands[0], QImode)
5956 || register_operand (operands[1], QImode))"
5957 "* return mips_move_1word (operands, insn, TRUE);"
5958 [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
5959 (set_attr "mode" "QI")
5960 (set_attr_alternative "length"
5964 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
5967 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
5977 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
5978 ;; when the original load is a 4 byte instruction but the add and the
5979 ;; load are 2 2 byte instructions.
5982 [(set (match_operand:QI 0 "register_operand" "")
5983 (mem:QI (plus:SI (match_dup 0)
5984 (match_operand:SI 1 "const_int_operand" ""))))]
5985 "TARGET_MIPS16 && reload_completed
5986 && GET_CODE (operands[0]) == REG
5987 && M16_REG_P (REGNO (operands[0]))
5988 && GET_CODE (operands[1]) == CONST_INT
5989 && ((INTVAL (operands[1]) < 0
5990 && INTVAL (operands[1]) >= -0x80)
5991 || (INTVAL (operands[1]) >= 32
5992 && INTVAL (operands[1]) <= 31 + 0x7f))"
5993 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
5994 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
5997 HOST_WIDE_INT val = INTVAL (operands[1]);
6000 operands[2] = GEN_INT (0);
6003 operands[1] = GEN_INT (0x7f);
6004 operands[2] = GEN_INT (val - 0x7f);
6008 ;; 32-bit floating point moves
6010 (define_expand "movsf"
6011 [(set (match_operand:SF 0 "nonimmediate_operand" "")
6012 (match_operand:SF 1 "general_operand" ""))]
6016 if ((reload_in_progress | reload_completed) == 0
6017 && !register_operand (operands[0], SFmode)
6018 && !register_operand (operands[1], SFmode)
6020 || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
6021 && operands[1] != CONST0_RTX (SFmode))))
6023 rtx temp = force_reg (SFmode, operands[1]);
6024 emit_move_insn (operands[0], temp);
6029 (define_insn "movsf_internal1"
6030 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
6031 (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
6033 && (register_operand (operands[0], SFmode)
6034 || register_operand (operands[1], SFmode)
6035 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
6036 || operands[1] == CONST0_RTX (SFmode))"
6037 "* return mips_move_1word (operands, insn, FALSE);"
6038 [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
6039 (set_attr "mode" "SF")
6040 (set_attr "length" "4,4,4,8,4,8,4,4,4,4,8,4,8")])
6043 (define_insn "movsf_internal2"
6044 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
6045 (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))]
6046 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
6047 && (register_operand (operands[0], SFmode)
6048 || register_operand (operands[1], SFmode)
6049 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
6050 || operands[1] == CONST0_RTX (SFmode))"
6051 "* return mips_move_1word (operands, insn, FALSE);"
6052 [(set_attr "type" "move,load,load,store,store")
6053 (set_attr "mode" "SF")
6054 (set_attr "length" "4,4,8,4,8")])
6057 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,d,R,m")
6058 (match_operand:SF 1 "general_operand" "d,d,y,R,Fm,d,d"))]
6060 && (register_operand (operands[0], SFmode)
6061 || register_operand (operands[1], SFmode))"
6062 "* return mips_move_1word (operands, insn, FALSE);"
6063 [(set_attr "type" "move,move,move,load,load,store,store")
6064 (set_attr "mode" "SF")
6065 (set_attr "length" "4,4,4,4,8,4,8")])
6068 ;; 64-bit floating point moves
6070 (define_expand "movdf"
6071 [(set (match_operand:DF 0 "nonimmediate_operand" "")
6072 (match_operand:DF 1 "general_operand" ""))]
6076 if ((reload_in_progress | reload_completed) == 0
6077 && !register_operand (operands[0], DFmode)
6078 && !register_operand (operands[1], DFmode)
6080 || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
6081 && operands[1] != CONST0_RTX (DFmode))))
6083 rtx temp = force_reg (DFmode, operands[1]);
6084 emit_move_insn (operands[0], temp);
6089 (define_insn "movdf_internal1"
6090 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,To,f,*f,*d,*d,*d,*d,*R,*T")
6091 (match_operand:DF 1 "general_operand" "f,R,To,fG,fG,F,*d,*f,*d*G,*R,*T*F,*d,*d"))]
6092 "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
6093 && TARGET_DOUBLE_FLOAT
6094 && (register_operand (operands[0], DFmode)
6095 || register_operand (operands[1], DFmode)
6096 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
6097 || operands[1] == CONST0_RTX (DFmode))"
6098 "* return mips_move_2words (operands, insn); "
6099 [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
6100 (set_attr "mode" "DF")
6101 (set_attr "length" "4,8,16,8,16,16,8,8,8,8,16,8,16")])
6103 (define_insn "movdf_internal1a"
6104 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,To,To,*d,*d,*d,*To,*R,*d")
6105 (match_operand:DF 1 "general_operand" " f,To,f,G,f,G,*F,*To,*R,*d,*d,*d"))]
6106 "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
6107 && TARGET_DOUBLE_FLOAT
6108 && (register_operand (operands[0], DFmode)
6109 || register_operand (operands[1], DFmode)
6110 || (GET_CODE (operands [0]) == MEM
6111 && ((GET_CODE (operands[1]) == CONST_INT
6112 && INTVAL (operands[1]) == 0)
6113 || operands[1] == CONST0_RTX (DFmode))))"
6114 "* return mips_move_2words (operands, insn); "
6115 [(set_attr "type" "move,load,store,store,store,store,load,load,load,store,store,move")
6116 (set_attr "mode" "DF")
6117 (set_attr "length" "4,8,4,4,8,8,8,8,4,8,4,4")])
6119 (define_insn "movdf_internal2"
6120 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,To")
6121 (match_operand:DF 1 "general_operand" "dG,R,ToF,d,d"))]
6122 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
6123 && (register_operand (operands[0], DFmode)
6124 || register_operand (operands[1], DFmode)
6125 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
6126 || operands[1] == CONST0_RTX (DFmode))"
6127 "* return mips_move_2words (operands, insn); "
6128 [(set_attr "type" "move,load,load,store,store")
6129 (set_attr "mode" "DF")
6130 (set_attr "length" "8,8,16,8,16")])
6133 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,d,R,To")
6134 (match_operand:DF 1 "general_operand" "d,d,y,R,ToF,d,d"))]
6136 && (register_operand (operands[0], DFmode)
6137 || register_operand (operands[1], DFmode))"
6138 "* return mips_move_2words (operands, insn);"
6139 [(set_attr "type" "move,move,move,load,load,store,store")
6140 (set_attr "mode" "DF")
6141 (set_attr "length" "8,8,8,8,16,8,16")])
6144 [(set (match_operand:DF 0 "register_operand" "")
6145 (match_operand:DF 1 "register_operand" ""))]
6146 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
6147 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
6148 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
6149 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
6150 (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
6153 ;; Instructions to load the global pointer register.
6154 ;; This is volatile to make sure that the scheduler won't move any symbol_ref
6155 ;; uses in front of it. All symbol_refs implicitly use the gp reg.
6157 (define_insn "loadgp"
6159 (unspec_volatile:DI [(match_operand:DI 0 "address_operand" "")
6160 (match_operand:DI 1 "register_operand" "")] 2))
6161 (clobber (reg:DI 1))]
6163 "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]"
6164 [(set_attr "type" "move")
6165 (set_attr "mode" "DI")
6166 (set_attr "length" "12")])
6168 ;; Block moves, see mips.c for more details.
6169 ;; Argument 0 is the destination
6170 ;; Argument 1 is the source
6171 ;; Argument 2 is the length
6172 ;; Argument 3 is the alignment
6174 (define_expand "movstrsi"
6175 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
6176 (match_operand:BLK 1 "general_operand" ""))
6177 (use (match_operand:SI 2 "arith32_operand" ""))
6178 (use (match_operand:SI 3 "immediate_operand" ""))])]
6182 if (operands[0]) /* avoid unused code messages */
6184 expand_block_move (operands);
6189 ;; Insn generated by block moves
6191 (define_insn "movstrsi_internal"
6192 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
6193 (match_operand:BLK 1 "memory_operand" "o")) ;; source
6194 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6195 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6196 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6197 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6198 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6199 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6200 (use (const_int 0))] ;; normal block move
6202 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
6203 [(set_attr "type" "store")
6204 (set_attr "mode" "none")
6205 (set_attr "length" "80")])
6207 ;; We need mips16 versions, because an offset from the stack pointer
6208 ;; is not offsettable, since the stack pointer can only handle 4 and 8
6212 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
6213 (match_operand:BLK 1 "memory_operand" "o")) ;; source
6214 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6215 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6216 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6217 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6218 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6219 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6220 (use (const_int 0))] ;; normal block move
6222 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
6223 [(set_attr "type" "multi")
6224 (set_attr "mode" "none")
6225 (set_attr "length" "80")])
6227 ;; Split a block move into 2 parts, the first part is everything
6228 ;; except for the last move, and the second part is just the last
6229 ;; store, which is exactly 1 instruction (ie, not a usw), so it can
6230 ;; fill a delay slot. This also prevents a bug in delayed branches
6231 ;; from showing up, which reuses one of the registers in our clobbers.
6234 [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
6235 (mem:BLK (match_operand:SI 1 "register_operand" "")))
6236 (clobber (match_operand:SI 4 "register_operand" ""))
6237 (clobber (match_operand:SI 5 "register_operand" ""))
6238 (clobber (match_operand:SI 6 "register_operand" ""))
6239 (clobber (match_operand:SI 7 "register_operand" ""))
6240 (use (match_operand:SI 2 "small_int" ""))
6241 (use (match_operand:SI 3 "small_int" ""))
6242 (use (const_int 0))]
6244 "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
6246 ;; All but the last move
6247 [(parallel [(set (mem:BLK (match_dup 0))
6248 (mem:BLK (match_dup 1)))
6249 (clobber (match_dup 4))
6250 (clobber (match_dup 5))
6251 (clobber (match_dup 6))
6252 (clobber (match_dup 7))
6255 (use (const_int 1))])
6257 ;; The last store, so it can fill a delay slot
6258 (parallel [(set (mem:BLK (match_dup 0))
6259 (mem:BLK (match_dup 1)))
6260 (clobber (match_dup 4))
6261 (clobber (match_dup 5))
6262 (clobber (match_dup 6))
6263 (clobber (match_dup 7))
6266 (use (const_int 2))])]
6270 (define_insn "movstrsi_internal2"
6271 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
6272 (match_operand:BLK 1 "memory_operand" "o")) ;; source
6273 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6274 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6275 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6276 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6277 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6278 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6279 (use (const_int 1))] ;; all but last store
6281 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
6282 [(set_attr "type" "store")
6283 (set_attr "mode" "none")
6284 (set_attr "length" "80")])
6287 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
6288 (match_operand:BLK 1 "memory_operand" "o")) ;; source
6289 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6290 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6291 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6292 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6293 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6294 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6295 (use (const_int 1))] ;; all but last store
6297 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
6298 [(set_attr "type" "multi")
6299 (set_attr "mode" "none")
6300 (set_attr "length" "80")])
6302 (define_insn "movstrsi_internal3"
6303 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
6304 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
6305 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6306 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6307 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6308 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6309 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6310 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6311 (use (const_int 2))] ;; just last store of block move
6313 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
6314 [(set_attr "type" "store")
6315 (set_attr "mode" "none")])
6318 ;; ....................
6322 ;; ....................
6324 ;; Many of these instructions uses trivial define_expands, because we
6325 ;; want to use a different set of constraints when TARGET_MIPS16.
6327 (define_expand "ashlsi3"
6328 [(set (match_operand:SI 0 "register_operand" "=d")
6329 (ashift:SI (match_operand:SI 1 "register_operand" "d")
6330 (match_operand:SI 2 "arith_operand" "dI")))]
6334 /* On the mips16, a shift of more than 8 is a four byte instruction,
6335 so, for a shift between 8 and 16, it is just as fast to do two
6336 shifts of 8 or less. If there is a lot of shifting going on, we
6337 may win in CSE. Otherwise combine will put the shifts back
6338 together again. This can be called by function_arg, so we must
6339 be careful not to allocate a new register if we've reached the
6343 && GET_CODE (operands[2]) == CONST_INT
6344 && INTVAL (operands[2]) > 8
6345 && INTVAL (operands[2]) <= 16
6346 && ! reload_in_progress
6347 && ! reload_completed)
6349 rtx temp = gen_reg_rtx (SImode);
6351 emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
6352 emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
6353 GEN_INT (INTVAL (operands[2]) - 8)));
6358 (define_insn "ashlsi3_internal1"
6359 [(set (match_operand:SI 0 "register_operand" "=d")
6360 (ashift:SI (match_operand:SI 1 "register_operand" "d")
6361 (match_operand:SI 2 "arith_operand" "dI")))]
6365 if (GET_CODE (operands[2]) == CONST_INT)
6366 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6368 return \"sll\\t%0,%1,%2\";
6370 [(set_attr "type" "arith")
6371 (set_attr "mode" "SI")])
6373 (define_insn "ashlsi3_internal2"
6374 [(set (match_operand:SI 0 "register_operand" "=d,d")
6375 (ashift:SI (match_operand:SI 1 "register_operand" "0,d")
6376 (match_operand:SI 2 "arith_operand" "d,I")))]
6380 if (which_alternative == 0)
6381 return \"sll\\t%0,%2\";
6383 if (GET_CODE (operands[2]) == CONST_INT)
6384 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6386 return \"sll\\t%0,%1,%2\";
6388 [(set_attr "type" "arith")
6389 (set_attr "mode" "SI")
6390 (set_attr_alternative "length"
6392 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
6396 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
6399 [(set (match_operand:SI 0 "register_operand" "")
6400 (ashift:SI (match_operand:SI 1 "register_operand" "")
6401 (match_operand:SI 2 "const_int_operand" "")))]
6404 && GET_CODE (operands[2]) == CONST_INT
6405 && INTVAL (operands[2]) > 8
6406 && INTVAL (operands[2]) <= 16"
6407 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
6408 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
6411 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
6414 (define_expand "ashldi3"
6415 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6416 (ashift:DI (match_operand:DI 1 "se_register_operand" "")
6417 (match_operand:SI 2 "arith_operand" "")))
6418 (clobber (match_dup 3))])]
6419 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
6424 /* On the mips16, a shift of more than 8 is a four byte
6425 instruction, so, for a shift between 8 and 16, it is just as
6426 fast to do two shifts of 8 or less. If there is a lot of
6427 shifting going on, we may win in CSE. Otherwise combine will
6428 put the shifts back together again. This can be called by
6429 function_arg, so we must be careful not to allocate a new
6430 register if we've reached the reload pass. */
6433 && GET_CODE (operands[2]) == CONST_INT
6434 && INTVAL (operands[2]) > 8
6435 && INTVAL (operands[2]) <= 16
6436 && ! reload_in_progress
6437 && ! reload_completed)
6439 rtx temp = gen_reg_rtx (DImode);
6441 emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
6442 emit_insn (gen_ashldi3_internal4 (operands[0], temp,
6443 GEN_INT (INTVAL (operands[2]) - 8)));
6447 emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
6452 operands[3] = gen_reg_rtx (SImode);
6456 (define_insn "ashldi3_internal"
6457 [(set (match_operand:DI 0 "register_operand" "=&d")
6458 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6459 (match_operand:SI 2 "register_operand" "d")))
6460 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6461 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
6464 operands[4] = const0_rtx;
6465 dslots_jump_total += 3;
6466 dslots_jump_filled += 2;
6468 return \"sll\\t%3,%2,26\\n\\
6469 \\tbgez\\t%3,1f\\n\\
6470 \\tsll\\t%M0,%L1,%2\\n\\
6472 \\tmove\\t%L0,%z4%)\\n\\
6475 \\t%(beq\\t%3,%z4,2f\\n\\
6476 \\tsll\\t%M0,%M1,%2%)\\n\\
6478 \\tsubu\\t%3,%z4,%2\\n\\
6479 \\tsrl\\t%3,%L1,%3\\n\\
6480 \\tor\\t%M0,%M0,%3\\n\\
6482 \\tsll\\t%L0,%L1,%2\\n\\
6485 [(set_attr "type" "darith")
6486 (set_attr "mode" "SI")
6487 (set_attr "length" "48")])
6490 (define_insn "ashldi3_internal2"
6491 [(set (match_operand:DI 0 "register_operand" "=d")
6492 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6493 (match_operand:SI 2 "small_int" "IJK")))
6494 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6495 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6496 && (INTVAL (operands[2]) & 32) != 0"
6499 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6500 operands[4] = const0_rtx;
6501 return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
6503 [(set_attr "type" "darith")
6504 (set_attr "mode" "DI")
6505 (set_attr "length" "8")])
6509 [(set (match_operand:DI 0 "register_operand" "")
6510 (ashift:DI (match_operand:DI 1 "register_operand" "")
6511 (match_operand:SI 2 "small_int" "")))
6512 (clobber (match_operand:SI 3 "register_operand" ""))]
6513 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
6514 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6515 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6516 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6517 && (INTVAL (operands[2]) & 32) != 0"
6519 [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
6520 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
6522 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
6526 [(set (match_operand:DI 0 "register_operand" "")
6527 (ashift:DI (match_operand:DI 1 "register_operand" "")
6528 (match_operand:SI 2 "small_int" "")))
6529 (clobber (match_operand:SI 3 "register_operand" ""))]
6530 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
6531 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6532 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6533 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6534 && (INTVAL (operands[2]) & 32) != 0"
6536 [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
6537 (set (subreg:SI (match_dup 0) 4) (const_int 0))]
6539 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
6542 (define_insn "ashldi3_internal3"
6543 [(set (match_operand:DI 0 "register_operand" "=d")
6544 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6545 (match_operand:SI 2 "small_int" "IJK")))
6546 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6547 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6548 && (INTVAL (operands[2]) & 63) < 32
6549 && (INTVAL (operands[2]) & 63) != 0"
6552 int amount = INTVAL (operands[2]);
6554 operands[2] = GEN_INT (amount & 31);
6555 operands[4] = const0_rtx;
6556 operands[5] = GEN_INT ((-amount) & 31);
6558 return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
6560 [(set_attr "type" "darith")
6561 (set_attr "mode" "DI")
6562 (set_attr "length" "16")])
6566 [(set (match_operand:DI 0 "register_operand" "")
6567 (ashift:DI (match_operand:DI 1 "register_operand" "")
6568 (match_operand:SI 2 "small_int" "")))
6569 (clobber (match_operand:SI 3 "register_operand" ""))]
6570 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
6571 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6572 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6573 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6574 && (INTVAL (operands[2]) & 63) < 32
6575 && (INTVAL (operands[2]) & 63) != 0"
6577 [(set (subreg:SI (match_dup 0) 4)
6578 (ashift:SI (subreg:SI (match_dup 1) 4)
6582 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
6585 (set (subreg:SI (match_dup 0) 4)
6586 (ior:SI (subreg:SI (match_dup 0) 4)
6589 (set (subreg:SI (match_dup 0) 0)
6590 (ashift:SI (subreg:SI (match_dup 1) 0)
6594 int amount = INTVAL (operands[2]);
6595 operands[2] = GEN_INT (amount & 31);
6596 operands[4] = GEN_INT ((-amount) & 31);
6601 [(set (match_operand:DI 0 "register_operand" "")
6602 (ashift:DI (match_operand:DI 1 "register_operand" "")
6603 (match_operand:SI 2 "small_int" "")))
6604 (clobber (match_operand:SI 3 "register_operand" ""))]
6605 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
6606 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6607 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6608 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6609 && (INTVAL (operands[2]) & 63) < 32
6610 && (INTVAL (operands[2]) & 63) != 0"
6612 [(set (subreg:SI (match_dup 0) 0)
6613 (ashift:SI (subreg:SI (match_dup 1) 0)
6617 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
6620 (set (subreg:SI (match_dup 0) 0)
6621 (ior:SI (subreg:SI (match_dup 0) 0)
6624 (set (subreg:SI (match_dup 0) 4)
6625 (ashift:SI (subreg:SI (match_dup 1) 4)
6629 int amount = INTVAL (operands[2]);
6630 operands[2] = GEN_INT (amount & 31);
6631 operands[4] = GEN_INT ((-amount) & 31);
6635 (define_insn "ashldi3_internal4"
6636 [(set (match_operand:DI 0 "register_operand" "=d")
6637 (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
6638 (match_operand:SI 2 "arith_operand" "dI")))]
6639 "TARGET_64BIT && !TARGET_MIPS16"
6642 if (GET_CODE (operands[2]) == CONST_INT)
6643 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6645 return \"dsll\\t%0,%1,%2\";
6647 [(set_attr "type" "arith")
6648 (set_attr "mode" "DI")])
6651 [(set (match_operand:DI 0 "register_operand" "=d,d")
6652 (ashift:DI (match_operand:DI 1 "se_register_operand" "0,d")
6653 (match_operand:SI 2 "arith_operand" "d,I")))]
6654 "TARGET_64BIT && TARGET_MIPS16"
6657 if (which_alternative == 0)
6658 return \"dsll\\t%0,%2\";
6660 if (GET_CODE (operands[2]) == CONST_INT)
6661 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6663 return \"dsll\\t%0,%1,%2\";
6665 [(set_attr "type" "arith")
6666 (set_attr "mode" "DI")
6667 (set_attr_alternative "length"
6669 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
6674 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
6677 [(set (match_operand:DI 0 "register_operand" "")
6678 (ashift:DI (match_operand:DI 1 "register_operand" "")
6679 (match_operand:SI 2 "const_int_operand" "")))]
6680 "TARGET_MIPS16 && TARGET_64BIT
6682 && GET_CODE (operands[2]) == CONST_INT
6683 && INTVAL (operands[2]) > 8
6684 && INTVAL (operands[2]) <= 16"
6685 [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
6686 (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
6689 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
6692 (define_expand "ashrsi3"
6693 [(set (match_operand:SI 0 "register_operand" "=d")
6694 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
6695 (match_operand:SI 2 "arith_operand" "dI")))]
6699 /* On the mips16, a shift of more than 8 is a four byte instruction,
6700 so, for a shift between 8 and 16, it is just as fast to do two
6701 shifts of 8 or less. If there is a lot of shifting going on, we
6702 may win in CSE. Otherwise combine will put the shifts back
6706 && GET_CODE (operands[2]) == CONST_INT
6707 && INTVAL (operands[2]) > 8
6708 && INTVAL (operands[2]) <= 16)
6710 rtx temp = gen_reg_rtx (SImode);
6712 emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
6713 emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
6714 GEN_INT (INTVAL (operands[2]) - 8)));
6719 (define_insn "ashrsi3_internal1"
6720 [(set (match_operand:SI 0 "register_operand" "=d")
6721 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
6722 (match_operand:SI 2 "arith_operand" "dI")))]
6726 if (GET_CODE (operands[2]) == CONST_INT)
6727 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6729 return \"sra\\t%0,%1,%2\";
6731 [(set_attr "type" "arith")
6732 (set_attr "mode" "SI")])
6734 (define_insn "ashrsi3_internal2"
6735 [(set (match_operand:SI 0 "register_operand" "=d,d")
6736 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
6737 (match_operand:SI 2 "arith_operand" "d,I")))]
6741 if (which_alternative == 0)
6742 return \"sra\\t%0,%2\";
6744 if (GET_CODE (operands[2]) == CONST_INT)
6745 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6747 return \"sra\\t%0,%1,%2\";
6749 [(set_attr "type" "arith")
6750 (set_attr "mode" "SI")
6751 (set_attr_alternative "length"
6753 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
6758 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
6761 [(set (match_operand:SI 0 "register_operand" "")
6762 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6763 (match_operand:SI 2 "const_int_operand" "")))]
6766 && GET_CODE (operands[2]) == CONST_INT
6767 && INTVAL (operands[2]) > 8
6768 && INTVAL (operands[2]) <= 16"
6769 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
6770 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
6773 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
6776 (define_expand "ashrdi3"
6777 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6778 (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "")
6779 (match_operand:SI 2 "arith_operand" "")))
6780 (clobber (match_dup 3))])]
6781 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
6786 /* On the mips16, a shift of more than 8 is a four byte
6787 instruction, so, for a shift between 8 and 16, it is just as
6788 fast to do two shifts of 8 or less. If there is a lot of
6789 shifting going on, we may win in CSE. Otherwise combine will
6790 put the shifts back together again. */
6793 && GET_CODE (operands[2]) == CONST_INT
6794 && INTVAL (operands[2]) > 8
6795 && INTVAL (operands[2]) <= 16)
6797 rtx temp = gen_reg_rtx (DImode);
6799 emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
6800 emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
6801 GEN_INT (INTVAL (operands[2]) - 8)));
6805 emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
6810 operands[3] = gen_reg_rtx (SImode);
6814 (define_insn "ashrdi3_internal"
6815 [(set (match_operand:DI 0 "register_operand" "=&d")
6816 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6817 (match_operand:SI 2 "register_operand" "d")))
6818 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6819 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
6822 operands[4] = const0_rtx;
6823 dslots_jump_total += 3;
6824 dslots_jump_filled += 2;
6826 return \"sll\\t%3,%2,26\\n\\
6827 \\tbgez\\t%3,1f\\n\\
6828 \\tsra\\t%L0,%M1,%2\\n\\
6830 \\tsra\\t%M0,%M1,31%)\\n\\
6833 \\t%(beq\\t%3,%z4,2f\\n\\
6834 \\tsrl\\t%L0,%L1,%2%)\\n\\
6836 \\tsubu\\t%3,%z4,%2\\n\\
6837 \\tsll\\t%3,%M1,%3\\n\\
6838 \\tor\\t%L0,%L0,%3\\n\\
6840 \\tsra\\t%M0,%M1,%2\\n\\
6843 [(set_attr "type" "darith")
6844 (set_attr "mode" "DI")
6845 (set_attr "length" "48")])
6848 (define_insn "ashrdi3_internal2"
6849 [(set (match_operand:DI 0 "register_operand" "=d")
6850 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6851 (match_operand:SI 2 "small_int" "IJK")))
6852 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6853 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
6856 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6857 return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
6859 [(set_attr "type" "darith")
6860 (set_attr "mode" "DI")
6861 (set_attr "length" "8")])
6865 [(set (match_operand:DI 0 "register_operand" "")
6866 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6867 (match_operand:SI 2 "small_int" "")))
6868 (clobber (match_operand:SI 3 "register_operand" ""))]
6869 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
6870 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6871 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6872 && (INTVAL (operands[2]) & 32) != 0"
6874 [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
6875 (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))]
6877 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
6881 [(set (match_operand:DI 0 "register_operand" "")
6882 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6883 (match_operand:SI 2 "small_int" "")))
6884 (clobber (match_operand:SI 3 "register_operand" ""))]
6885 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
6886 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6887 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6888 && (INTVAL (operands[2]) & 32) != 0"
6890 [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
6891 (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
6893 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
6896 (define_insn "ashrdi3_internal3"
6897 [(set (match_operand:DI 0 "register_operand" "=d")
6898 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6899 (match_operand:SI 2 "small_int" "IJK")))
6900 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6901 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6902 && (INTVAL (operands[2]) & 63) < 32
6903 && (INTVAL (operands[2]) & 63) != 0"
6906 int amount = INTVAL (operands[2]);
6908 operands[2] = GEN_INT (amount & 31);
6909 operands[4] = GEN_INT ((-amount) & 31);
6911 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
6913 [(set_attr "type" "darith")
6914 (set_attr "mode" "DI")
6915 (set_attr "length" "16")])
6919 [(set (match_operand:DI 0 "register_operand" "")
6920 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6921 (match_operand:SI 2 "small_int" "")))
6922 (clobber (match_operand:SI 3 "register_operand" ""))]
6923 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
6924 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6925 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6926 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6927 && (INTVAL (operands[2]) & 63) < 32
6928 && (INTVAL (operands[2]) & 63) != 0"
6930 [(set (subreg:SI (match_dup 0) 0)
6931 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
6935 (ashift:SI (subreg:SI (match_dup 1) 4)
6938 (set (subreg:SI (match_dup 0) 0)
6939 (ior:SI (subreg:SI (match_dup 0) 0)
6942 (set (subreg:SI (match_dup 0) 4)
6943 (ashiftrt:SI (subreg:SI (match_dup 1) 4)
6947 int amount = INTVAL (operands[2]);
6948 operands[2] = GEN_INT (amount & 31);
6949 operands[4] = GEN_INT ((-amount) & 31);
6954 [(set (match_operand:DI 0 "register_operand" "")
6955 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6956 (match_operand:SI 2 "small_int" "")))
6957 (clobber (match_operand:SI 3 "register_operand" ""))]
6958 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
6959 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6960 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6961 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6962 && (INTVAL (operands[2]) & 63) < 32
6963 && (INTVAL (operands[2]) & 63) != 0"
6965 [(set (subreg:SI (match_dup 0) 4)
6966 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
6970 (ashift:SI (subreg:SI (match_dup 1) 0)
6973 (set (subreg:SI (match_dup 0) 4)
6974 (ior:SI (subreg:SI (match_dup 0) 4)
6977 (set (subreg:SI (match_dup 0) 0)
6978 (ashiftrt:SI (subreg:SI (match_dup 1) 0)
6982 int amount = INTVAL (operands[2]);
6983 operands[2] = GEN_INT (amount & 31);
6984 operands[4] = GEN_INT ((-amount) & 31);
6988 (define_insn "ashrdi3_internal4"
6989 [(set (match_operand:DI 0 "register_operand" "=d")
6990 (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
6991 (match_operand:SI 2 "arith_operand" "dI")))]
6992 "TARGET_64BIT && !TARGET_MIPS16"
6995 if (GET_CODE (operands[2]) == CONST_INT)
6996 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6998 return \"dsra\\t%0,%1,%2\";
7000 [(set_attr "type" "arith")
7001 (set_attr "mode" "DI")])
7004 [(set (match_operand:DI 0 "register_operand" "=d,d")
7005 (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
7006 (match_operand:SI 2 "arith_operand" "d,I")))]
7007 "TARGET_64BIT && TARGET_MIPS16"
7010 if (GET_CODE (operands[2]) == CONST_INT)
7011 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7013 return \"dsra\\t%0,%2\";
7015 [(set_attr "type" "arith")
7016 (set_attr "mode" "DI")
7017 (set_attr_alternative "length"
7019 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7023 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
7026 [(set (match_operand:DI 0 "register_operand" "")
7027 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7028 (match_operand:SI 2 "const_int_operand" "")))]
7029 "TARGET_MIPS16 && TARGET_64BIT
7031 && GET_CODE (operands[2]) == CONST_INT
7032 && INTVAL (operands[2]) > 8
7033 && INTVAL (operands[2]) <= 16"
7034 [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
7035 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
7038 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
7041 (define_expand "lshrsi3"
7042 [(set (match_operand:SI 0 "register_operand" "=d")
7043 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
7044 (match_operand:SI 2 "arith_operand" "dI")))]
7048 /* On the mips16, a shift of more than 8 is a four byte instruction,
7049 so, for a shift between 8 and 16, it is just as fast to do two
7050 shifts of 8 or less. If there is a lot of shifting going on, we
7051 may win in CSE. Otherwise combine will put the shifts back
7055 && GET_CODE (operands[2]) == CONST_INT
7056 && INTVAL (operands[2]) > 8
7057 && INTVAL (operands[2]) <= 16)
7059 rtx temp = gen_reg_rtx (SImode);
7061 emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
7062 emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
7063 GEN_INT (INTVAL (operands[2]) - 8)));
7068 (define_insn "lshrsi3_internal1"
7069 [(set (match_operand:SI 0 "register_operand" "=d")
7070 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
7071 (match_operand:SI 2 "arith_operand" "dI")))]
7075 if (GET_CODE (operands[2]) == CONST_INT)
7076 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7078 return \"srl\\t%0,%1,%2\";
7080 [(set_attr "type" "arith")
7081 (set_attr "mode" "SI")])
7083 (define_insn "lshrsi3_internal2"
7084 [(set (match_operand:SI 0 "register_operand" "=d,d")
7085 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
7086 (match_operand:SI 2 "arith_operand" "d,I")))]
7090 if (which_alternative == 0)
7091 return \"srl\\t%0,%2\";
7093 if (GET_CODE (operands[2]) == CONST_INT)
7094 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7096 return \"srl\\t%0,%1,%2\";
7098 [(set_attr "type" "arith")
7099 (set_attr "mode" "SI")
7100 (set_attr_alternative "length"
7102 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7107 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
7110 [(set (match_operand:SI 0 "register_operand" "")
7111 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
7112 (match_operand:SI 2 "const_int_operand" "")))]
7115 && GET_CODE (operands[2]) == CONST_INT
7116 && INTVAL (operands[2]) > 8
7117 && INTVAL (operands[2]) <= 16"
7118 [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
7119 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
7122 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
7125 ;; If we load a byte on the mips16 as a bitfield, the resulting
7126 ;; sequence of instructions is too complicated for combine, because it
7127 ;; involves four instructions: a load, a shift, a constant load into a
7128 ;; register, and an and (the key problem here is that the mips16 does
7129 ;; not have and immediate). We recognize a shift of a load in order
7130 ;; to make it simple enough for combine to understand.
7133 [(set (match_operand:SI 0 "register_operand" "=d,d")
7134 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "R,m")
7135 (match_operand:SI 2 "immediate_operand" "I,I")))]
7137 "lw\\t%0,%1\;srl\\t%0,%2"
7138 [(set_attr "type" "load")
7139 (set_attr "mode" "SI")
7140 (set_attr_alternative "length"
7141 [(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7144 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7149 [(set (match_operand:SI 0 "register_operand" "")
7150 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "")
7151 (match_operand:SI 2 "immediate_operand" "")))]
7153 [(set (match_dup 0) (match_dup 1))
7154 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
7157 (define_expand "lshrdi3"
7158 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7159 (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "")
7160 (match_operand:SI 2 "arith_operand" "")))
7161 (clobber (match_dup 3))])]
7162 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
7167 /* On the mips16, a shift of more than 8 is a four byte
7168 instruction, so, for a shift between 8 and 16, it is just as
7169 fast to do two shifts of 8 or less. If there is a lot of
7170 shifting going on, we may win in CSE. Otherwise combine will
7171 put the shifts back together again. */
7174 && GET_CODE (operands[2]) == CONST_INT
7175 && INTVAL (operands[2]) > 8
7176 && INTVAL (operands[2]) <= 16)
7178 rtx temp = gen_reg_rtx (DImode);
7180 emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
7181 emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
7182 GEN_INT (INTVAL (operands[2]) - 8)));
7186 emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
7191 operands[3] = gen_reg_rtx (SImode);
7195 (define_insn "lshrdi3_internal"
7196 [(set (match_operand:DI 0 "register_operand" "=&d")
7197 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
7198 (match_operand:SI 2 "register_operand" "d")))
7199 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7200 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
7203 operands[4] = const0_rtx;
7204 dslots_jump_total += 3;
7205 dslots_jump_filled += 2;
7207 return \"sll\\t%3,%2,26\\n\\
7208 \\tbgez\\t%3,1f\\n\\
7209 \\tsrl\\t%L0,%M1,%2\\n\\
7211 \\tmove\\t%M0,%z4%)\\n\\
7214 \\t%(beq\\t%3,%z4,2f\\n\\
7215 \\tsrl\\t%L0,%L1,%2%)\\n\\
7217 \\tsubu\\t%3,%z4,%2\\n\\
7218 \\tsll\\t%3,%M1,%3\\n\\
7219 \\tor\\t%L0,%L0,%3\\n\\
7221 \\tsrl\\t%M0,%M1,%2\\n\\
7224 [(set_attr "type" "darith")
7225 (set_attr "mode" "DI")
7226 (set_attr "length" "48")])
7229 (define_insn "lshrdi3_internal2"
7230 [(set (match_operand:DI 0 "register_operand" "=d")
7231 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
7232 (match_operand:SI 2 "small_int" "IJK")))
7233 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7234 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7235 && (INTVAL (operands[2]) & 32) != 0"
7238 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7239 operands[4] = const0_rtx;
7240 return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
7242 [(set_attr "type" "darith")
7243 (set_attr "mode" "DI")
7244 (set_attr "length" "8")])
7248 [(set (match_operand:DI 0 "register_operand" "")
7249 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7250 (match_operand:SI 2 "small_int" "")))
7251 (clobber (match_operand:SI 3 "register_operand" ""))]
7252 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
7253 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7254 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7255 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7256 && (INTVAL (operands[2]) & 32) != 0"
7258 [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
7259 (set (subreg:SI (match_dup 0) 4) (const_int 0))]
7261 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
7265 [(set (match_operand:DI 0 "register_operand" "")
7266 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7267 (match_operand:SI 2 "small_int" "")))
7268 (clobber (match_operand:SI 3 "register_operand" ""))]
7269 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
7270 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7271 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7272 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7273 && (INTVAL (operands[2]) & 32) != 0"
7275 [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
7276 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
7278 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
7281 (define_insn "lshrdi3_internal3"
7282 [(set (match_operand:DI 0 "register_operand" "=d")
7283 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
7284 (match_operand:SI 2 "small_int" "IJK")))
7285 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7286 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7287 && (INTVAL (operands[2]) & 63) < 32
7288 && (INTVAL (operands[2]) & 63) != 0"
7291 int amount = INTVAL (operands[2]);
7293 operands[2] = GEN_INT (amount & 31);
7294 operands[4] = GEN_INT ((-amount) & 31);
7296 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
7298 [(set_attr "type" "darith")
7299 (set_attr "mode" "DI")
7300 (set_attr "length" "16")])
7304 [(set (match_operand:DI 0 "register_operand" "")
7305 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7306 (match_operand:SI 2 "small_int" "")))
7307 (clobber (match_operand:SI 3 "register_operand" ""))]
7308 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
7309 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7310 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7311 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7312 && (INTVAL (operands[2]) & 63) < 32
7313 && (INTVAL (operands[2]) & 63) != 0"
7315 [(set (subreg:SI (match_dup 0) 0)
7316 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
7320 (ashift:SI (subreg:SI (match_dup 1) 4)
7323 (set (subreg:SI (match_dup 0) 0)
7324 (ior:SI (subreg:SI (match_dup 0) 0)
7327 (set (subreg:SI (match_dup 0) 4)
7328 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
7332 int amount = INTVAL (operands[2]);
7333 operands[2] = GEN_INT (amount & 31);
7334 operands[4] = GEN_INT ((-amount) & 31);
7339 [(set (match_operand:DI 0 "register_operand" "")
7340 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7341 (match_operand:SI 2 "small_int" "")))
7342 (clobber (match_operand:SI 3 "register_operand" ""))]
7343 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
7344 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7345 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7346 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7347 && (INTVAL (operands[2]) & 63) < 32
7348 && (INTVAL (operands[2]) & 63) != 0"
7350 [(set (subreg:SI (match_dup 0) 4)
7351 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
7355 (ashift:SI (subreg:SI (match_dup 1) 0)
7358 (set (subreg:SI (match_dup 0) 4)
7359 (ior:SI (subreg:SI (match_dup 0) 4)
7362 (set (subreg:SI (match_dup 0) 0)
7363 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
7367 int amount = INTVAL (operands[2]);
7368 operands[2] = GEN_INT (amount & 31);
7369 operands[4] = GEN_INT ((-amount) & 31);
7373 (define_insn "lshrdi3_internal4"
7374 [(set (match_operand:DI 0 "register_operand" "=d")
7375 (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
7376 (match_operand:SI 2 "arith_operand" "dI")))]
7377 "TARGET_64BIT && !TARGET_MIPS16"
7380 if (GET_CODE (operands[2]) == CONST_INT)
7381 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7383 return \"dsrl\\t%0,%1,%2\";
7385 [(set_attr "type" "arith")
7386 (set_attr "mode" "DI")])
7389 [(set (match_operand:DI 0 "register_operand" "=d,d")
7390 (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
7391 (match_operand:SI 2 "arith_operand" "d,I")))]
7392 "TARGET_64BIT && TARGET_MIPS16"
7395 if (GET_CODE (operands[2]) == CONST_INT)
7396 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7398 return \"dsrl\\t%0,%2\";
7400 [(set_attr "type" "arith")
7401 (set_attr "mode" "DI")
7402 (set_attr_alternative "length"
7404 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7408 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
7411 [(set (match_operand:DI 0 "register_operand" "")
7412 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7413 (match_operand:SI 2 "const_int_operand" "")))]
7416 && GET_CODE (operands[2]) == CONST_INT
7417 && INTVAL (operands[2]) > 8
7418 && INTVAL (operands[2]) <= 16"
7419 [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
7420 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
7423 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
7428 ;; ....................
7432 ;; ....................
7434 ;; Flow here is rather complex:
7436 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
7437 ;; arguments into the branch_cmp array, and the type into
7438 ;; branch_type. No RTL is generated.
7440 ;; 2) The appropriate branch define_expand is called, which then
7441 ;; creates the appropriate RTL for the comparison and branch.
7442 ;; Different CC modes are used, based on what type of branch is
7443 ;; done, so that we can constrain things appropriately. There
7444 ;; are assumptions in the rest of GCC that break if we fold the
7445 ;; operands into the branchs for integer operations, and use cc0
7446 ;; for floating point, so we use the fp status register instead.
7447 ;; If needed, an appropriate temporary is created to hold the
7448 ;; of the integer compare.
7450 (define_expand "cmpsi"
7452 (compare:CC (match_operand:SI 0 "register_operand" "")
7453 (match_operand:SI 1 "arith_operand" "")))]
7457 if (operands[0]) /* avoid unused code message */
7459 branch_cmp[0] = operands[0];
7460 branch_cmp[1] = operands[1];
7461 branch_type = CMP_SI;
7466 (define_expand "tstsi"
7468 (match_operand:SI 0 "register_operand" ""))]
7472 if (operands[0]) /* avoid unused code message */
7474 branch_cmp[0] = operands[0];
7475 branch_cmp[1] = const0_rtx;
7476 branch_type = CMP_SI;
7481 (define_expand "cmpdi"
7483 (compare:CC (match_operand:DI 0 "se_register_operand" "")
7484 (match_operand:DI 1 "se_arith_operand" "")))]
7488 if (operands[0]) /* avoid unused code message */
7490 branch_cmp[0] = operands[0];
7491 branch_cmp[1] = operands[1];
7492 branch_type = CMP_DI;
7497 (define_expand "tstdi"
7499 (match_operand:DI 0 "se_register_operand" ""))]
7503 if (operands[0]) /* avoid unused code message */
7505 branch_cmp[0] = operands[0];
7506 branch_cmp[1] = const0_rtx;
7507 branch_type = CMP_DI;
7512 (define_expand "cmpdf"
7514 (compare:CC (match_operand:DF 0 "register_operand" "")
7515 (match_operand:DF 1 "register_operand" "")))]
7516 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7519 if (operands[0]) /* avoid unused code message */
7521 branch_cmp[0] = operands[0];
7522 branch_cmp[1] = operands[1];
7523 branch_type = CMP_DF;
7528 (define_expand "cmpsf"
7530 (compare:CC (match_operand:SF 0 "register_operand" "")
7531 (match_operand:SF 1 "register_operand" "")))]
7535 if (operands[0]) /* avoid unused code message */
7537 branch_cmp[0] = operands[0];
7538 branch_cmp[1] = operands[1];
7539 branch_type = CMP_SF;
7546 ;; ....................
7548 ;; CONDITIONAL BRANCHES
7550 ;; ....................
7552 ;; Conditional branches on floating-point equality tests.
7554 (define_insn "branch_fp"
7557 (match_operator:CC 0 "cmp_op"
7558 [(match_operand:CC 2 "register_operand" "z")
7560 (label_ref (match_operand 1 "" ""))
7565 return mips_output_conditional_branch (insn,
7567 /*two_operands_p=*/0,
7570 get_attr_length (insn));
7572 [(set_attr "type" "branch")
7573 (set_attr "mode" "none")])
7575 (define_insn "branch_fp_inverted"
7578 (match_operator:CC 0 "cmp_op"
7579 [(match_operand:CC 2 "register_operand" "z")
7582 (label_ref (match_operand 1 "" ""))))]
7586 return mips_output_conditional_branch (insn,
7588 /*two_operands_p=*/0,
7591 get_attr_length (insn));
7593 [(set_attr "type" "branch")
7594 (set_attr "mode" "none")])
7596 ;; Conditional branches on comparisons with zero.
7598 (define_insn "branch_zero"
7601 (match_operator:SI 0 "cmp_op"
7602 [(match_operand:SI 2 "register_operand" "d")
7604 (label_ref (match_operand 1 "" ""))
7609 return mips_output_conditional_branch (insn,
7611 /*two_operands_p=*/0,
7614 get_attr_length (insn));
7616 [(set_attr "type" "branch")
7617 (set_attr "mode" "none")])
7619 (define_insn "branch_zero_inverted"
7622 (match_operator:SI 0 "cmp_op"
7623 [(match_operand:SI 2 "register_operand" "d")
7626 (label_ref (match_operand 1 "" ""))))]
7630 return mips_output_conditional_branch (insn,
7632 /*two_operands_p=*/0,
7635 get_attr_length (insn));
7637 [(set_attr "type" "branch")
7638 (set_attr "mode" "none")])
7640 (define_insn "branch_zero_di"
7643 (match_operator:DI 0 "cmp_op"
7644 [(match_operand:DI 2 "se_register_operand" "d")
7646 (label_ref (match_operand 1 "" ""))
7651 return mips_output_conditional_branch (insn,
7653 /*two_operands_p=*/0,
7656 get_attr_length (insn));
7658 [(set_attr "type" "branch")
7659 (set_attr "mode" "none")])
7661 (define_insn "branch_zero_di_inverted"
7664 (match_operator:DI 0 "cmp_op"
7665 [(match_operand:DI 2 "se_register_operand" "d")
7668 (label_ref (match_operand 1 "" ""))))]
7672 return mips_output_conditional_branch (insn,
7674 /*two_operands_p=*/0,
7677 get_attr_length (insn));
7679 [(set_attr "type" "branch")
7680 (set_attr "mode" "none")])
7682 ;; Conditional branch on equality comparision.
7684 (define_insn "branch_equality"
7687 (match_operator:SI 0 "equality_op"
7688 [(match_operand:SI 2 "register_operand" "d")
7689 (match_operand:SI 3 "register_operand" "d")])
7690 (label_ref (match_operand 1 "" ""))
7695 return mips_output_conditional_branch (insn,
7697 /*two_operands_p=*/1,
7700 get_attr_length (insn));
7702 [(set_attr "type" "branch")
7703 (set_attr "mode" "none")])
7705 (define_insn "branch_equality_di"
7708 (match_operator:DI 0 "equality_op"
7709 [(match_operand:DI 2 "se_register_operand" "d")
7710 (match_operand:DI 3 "se_register_operand" "d")])
7711 (label_ref (match_operand 1 "" ""))
7716 return mips_output_conditional_branch (insn,
7718 /*two_operands_p=*/1,
7721 get_attr_length (insn));
7723 [(set_attr "type" "branch")
7724 (set_attr "mode" "none")])
7726 (define_insn "branch_equality_inverted"
7729 (match_operator:SI 0 "equality_op"
7730 [(match_operand:SI 2 "register_operand" "d")
7731 (match_operand:SI 3 "register_operand" "d")])
7733 (label_ref (match_operand 1 "" ""))))]
7737 return mips_output_conditional_branch (insn,
7739 /*two_operands_p=*/1,
7742 get_attr_length (insn));
7744 [(set_attr "type" "branch")
7745 (set_attr "mode" "none")])
7747 (define_insn "branch_equality_di_inverted"
7750 (match_operator:DI 0 "equality_op"
7751 [(match_operand:DI 2 "se_register_operand" "d")
7752 (match_operand:DI 3 "se_register_operand" "d")])
7754 (label_ref (match_operand 1 "" ""))))]
7758 return mips_output_conditional_branch (insn,
7760 /*two_operands_p=*/1,
7763 get_attr_length (insn));
7765 [(set_attr "type" "branch")
7766 (set_attr "mode" "none")])
7772 (if_then_else (match_operator:SI 0 "equality_op"
7773 [(match_operand:SI 1 "register_operand" "d,t")
7775 (match_operand 2 "pc_or_label_operand" "")
7776 (match_operand 3 "pc_or_label_operand" "")))]
7780 if (operands[2] != pc_rtx)
7782 if (which_alternative == 0)
7783 return \"%*b%C0z\\t%1,%2\";
7785 return \"%*bt%C0z\\t%2\";
7789 if (which_alternative == 0)
7790 return \"%*b%N0z\\t%1,%3\";
7792 return \"%*bt%N0z\\t%3\";
7795 [(set_attr "type" "branch")
7796 (set_attr "mode" "none")
7797 (set_attr "length" "8")])
7801 (if_then_else (match_operator:DI 0 "equality_op"
7802 [(match_operand:DI 1 "se_register_operand" "d,t")
7804 (match_operand 2 "pc_or_label_operand" "")
7805 (match_operand 3 "pc_or_label_operand" "")))]
7809 if (operands[2] != pc_rtx)
7811 if (which_alternative == 0)
7812 return \"%*b%C0z\\t%1,%2\";
7814 return \"%*bt%C0z\\t%2\";
7818 if (which_alternative == 0)
7819 return \"%*b%N0z\\t%1,%3\";
7821 return \"%*bt%N0z\\t%3\";
7824 [(set_attr "type" "branch")
7825 (set_attr "mode" "none")
7826 (set_attr "length" "8")])
7828 (define_expand "beq"
7830 (if_then_else (eq:CC (cc0)
7832 (label_ref (match_operand 0 "" ""))
7837 if (operands[0]) /* avoid unused code warning */
7839 gen_conditional_branch (operands, EQ);
7844 (define_expand "bne"
7846 (if_then_else (ne:CC (cc0)
7848 (label_ref (match_operand 0 "" ""))
7853 if (operands[0]) /* avoid unused code warning */
7855 gen_conditional_branch (operands, NE);
7860 (define_expand "bgt"
7862 (if_then_else (gt:CC (cc0)
7864 (label_ref (match_operand 0 "" ""))
7869 if (operands[0]) /* avoid unused code warning */
7871 gen_conditional_branch (operands, GT);
7876 (define_expand "bge"
7878 (if_then_else (ge:CC (cc0)
7880 (label_ref (match_operand 0 "" ""))
7885 if (operands[0]) /* avoid unused code warning */
7887 gen_conditional_branch (operands, GE);
7892 (define_expand "blt"
7894 (if_then_else (lt:CC (cc0)
7896 (label_ref (match_operand 0 "" ""))
7901 if (operands[0]) /* avoid unused code warning */
7903 gen_conditional_branch (operands, LT);
7908 (define_expand "ble"
7910 (if_then_else (le:CC (cc0)
7912 (label_ref (match_operand 0 "" ""))
7917 if (operands[0]) /* avoid unused code warning */
7919 gen_conditional_branch (operands, LE);
7924 (define_expand "bgtu"
7926 (if_then_else (gtu:CC (cc0)
7928 (label_ref (match_operand 0 "" ""))
7933 if (operands[0]) /* avoid unused code warning */
7935 gen_conditional_branch (operands, GTU);
7940 (define_expand "bgeu"
7942 (if_then_else (geu:CC (cc0)
7944 (label_ref (match_operand 0 "" ""))
7949 if (operands[0]) /* avoid unused code warning */
7951 gen_conditional_branch (operands, GEU);
7957 (define_expand "bltu"
7959 (if_then_else (ltu:CC (cc0)
7961 (label_ref (match_operand 0 "" ""))
7966 if (operands[0]) /* avoid unused code warning */
7968 gen_conditional_branch (operands, LTU);
7973 (define_expand "bleu"
7975 (if_then_else (leu:CC (cc0)
7977 (label_ref (match_operand 0 "" ""))
7982 if (operands[0]) /* avoid unused code warning */
7984 gen_conditional_branch (operands, LEU);
7991 ;; ....................
7993 ;; SETTING A REGISTER FROM A COMPARISON
7995 ;; ....................
7997 (define_expand "seq"
7998 [(set (match_operand:SI 0 "register_operand" "=d")
7999 (eq:SI (match_dup 1)
8004 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8007 /* set up operands from compare. */
8008 operands[1] = branch_cmp[0];
8009 operands[2] = branch_cmp[1];
8011 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8013 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
8017 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8018 operands[2] = force_reg (SImode, operands[2]);
8020 /* fall through and generate default code */
8024 (define_insn "seq_si_zero"
8025 [(set (match_operand:SI 0 "register_operand" "=d")
8026 (eq:SI (match_operand:SI 1 "register_operand" "d")
8030 [(set_attr "type" "arith")
8031 (set_attr "mode" "SI")])
8034 [(set (match_operand:SI 0 "register_operand" "=t")
8035 (eq:SI (match_operand:SI 1 "register_operand" "d")
8039 [(set_attr "type" "arith")
8040 (set_attr "mode" "SI")])
8042 (define_insn "seq_di_zero"
8043 [(set (match_operand:DI 0 "register_operand" "=d")
8044 (eq:DI (match_operand:DI 1 "se_register_operand" "d")
8046 "TARGET_64BIT && !TARGET_MIPS16"
8048 [(set_attr "type" "arith")
8049 (set_attr "mode" "DI")])
8052 [(set (match_operand:DI 0 "register_operand" "=t")
8053 (eq:DI (match_operand:DI 1 "se_register_operand" "d")
8055 "TARGET_64BIT && TARGET_MIPS16"
8057 [(set_attr "type" "arith")
8058 (set_attr "mode" "DI")])
8060 (define_insn "seq_si"
8061 [(set (match_operand:SI 0 "register_operand" "=d,d")
8062 (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
8063 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
8064 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8066 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
8067 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
8068 [(set_attr "type" "arith")
8069 (set_attr "mode" "SI")
8070 (set_attr "length" "8")])
8073 [(set (match_operand:SI 0 "register_operand" "")
8074 (eq:SI (match_operand:SI 1 "register_operand" "")
8075 (match_operand:SI 2 "uns_arith_operand" "")))]
8076 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
8077 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8079 (xor:SI (match_dup 1)
8082 (ltu:SI (match_dup 0)
8086 (define_insn "seq_di"
8087 [(set (match_operand:DI 0 "register_operand" "=d,d")
8088 (eq:DI (match_operand:DI 1 "se_register_operand" "%d,d")
8089 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
8090 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8092 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
8093 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
8094 [(set_attr "type" "arith")
8095 (set_attr "mode" "DI")
8096 (set_attr "length" "8")])
8099 [(set (match_operand:DI 0 "register_operand" "")
8100 (eq:DI (match_operand:DI 1 "se_register_operand" "")
8101 (match_operand:DI 2 "se_uns_arith_operand" "")))]
8102 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8104 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8106 (xor:DI (match_dup 1)
8109 (ltu:DI (match_dup 0)
8113 ;; On the mips16 the default code is better than using sltu.
8115 (define_expand "sne"
8116 [(set (match_operand:SI 0 "register_operand" "=d")
8117 (ne:SI (match_dup 1)
8122 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8125 /* set up operands from compare. */
8126 operands[1] = branch_cmp[0];
8127 operands[2] = branch_cmp[1];
8129 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
8131 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
8135 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8136 operands[2] = force_reg (SImode, operands[2]);
8138 /* fall through and generate default code */
8141 (define_insn "sne_si_zero"
8142 [(set (match_operand:SI 0 "register_operand" "=d")
8143 (ne:SI (match_operand:SI 1 "register_operand" "d")
8147 [(set_attr "type" "arith")
8148 (set_attr "mode" "SI")])
8150 (define_insn "sne_di_zero"
8151 [(set (match_operand:DI 0 "register_operand" "=d")
8152 (ne:DI (match_operand:DI 1 "se_register_operand" "d")
8154 "TARGET_64BIT && !TARGET_MIPS16"
8156 [(set_attr "type" "arith")
8157 (set_attr "mode" "DI")])
8159 (define_insn "sne_si"
8160 [(set (match_operand:SI 0 "register_operand" "=d,d")
8161 (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
8162 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
8163 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8165 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
8166 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
8167 [(set_attr "type" "arith")
8168 (set_attr "mode" "SI")
8169 (set_attr "length" "8")])
8172 [(set (match_operand:SI 0 "register_operand" "")
8173 (ne:SI (match_operand:SI 1 "register_operand" "")
8174 (match_operand:SI 2 "uns_arith_operand" "")))]
8175 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
8176 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8178 (xor:SI (match_dup 1)
8181 (gtu:SI (match_dup 0)
8185 (define_insn "sne_di"
8186 [(set (match_operand:DI 0 "register_operand" "=d,d")
8187 (ne:DI (match_operand:DI 1 "se_register_operand" "%d,d")
8188 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
8189 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8191 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
8192 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
8193 [(set_attr "type" "arith")
8194 (set_attr "mode" "DI")
8195 (set_attr "length" "8")])
8198 [(set (match_operand:DI 0 "register_operand" "")
8199 (ne:DI (match_operand:DI 1 "se_register_operand" "")
8200 (match_operand:DI 2 "se_uns_arith_operand" "")))]
8201 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8203 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8205 (xor:DI (match_dup 1)
8208 (gtu:DI (match_dup 0)
8212 (define_expand "sgt"
8213 [(set (match_operand:SI 0 "register_operand" "=d")
8214 (gt:SI (match_dup 1)
8219 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8222 /* set up operands from compare. */
8223 operands[1] = branch_cmp[0];
8224 operands[2] = branch_cmp[1];
8226 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8228 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
8232 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
8233 operands[2] = force_reg (SImode, operands[2]);
8235 /* fall through and generate default code */
8238 (define_insn "sgt_si"
8239 [(set (match_operand:SI 0 "register_operand" "=d")
8240 (gt:SI (match_operand:SI 1 "register_operand" "d")
8241 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
8244 [(set_attr "type" "arith")
8245 (set_attr "mode" "SI")])
8248 [(set (match_operand:SI 0 "register_operand" "=t")
8249 (gt:SI (match_operand:SI 1 "register_operand" "d")
8250 (match_operand:SI 2 "register_operand" "d")))]
8253 [(set_attr "type" "arith")
8254 (set_attr "mode" "SI")])
8256 (define_insn "sgt_di"
8257 [(set (match_operand:DI 0 "register_operand" "=d")
8258 (gt:DI (match_operand:DI 1 "se_register_operand" "d")
8259 (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
8260 "TARGET_64BIT && !TARGET_MIPS16"
8262 [(set_attr "type" "arith")
8263 (set_attr "mode" "DI")])
8266 [(set (match_operand:DI 0 "register_operand" "=d")
8267 (gt:DI (match_operand:DI 1 "se_register_operand" "d")
8268 (match_operand:DI 2 "se_register_operand" "d")))]
8269 "TARGET_64BIT && TARGET_MIPS16"
8271 [(set_attr "type" "arith")
8272 (set_attr "mode" "DI")])
8274 (define_expand "sge"
8275 [(set (match_operand:SI 0 "register_operand" "=d")
8276 (ge:SI (match_dup 1)
8281 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8284 /* set up operands from compare. */
8285 operands[1] = branch_cmp[0];
8286 operands[2] = branch_cmp[1];
8288 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8290 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
8294 /* fall through and generate default code */
8297 (define_insn "sge_si"
8298 [(set (match_operand:SI 0 "register_operand" "=d")
8299 (ge:SI (match_operand:SI 1 "register_operand" "d")
8300 (match_operand:SI 2 "arith_operand" "dI")))]
8301 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8302 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
8303 [(set_attr "type" "arith")
8304 (set_attr "mode" "SI")
8305 (set_attr "length" "8")])
8308 [(set (match_operand:SI 0 "register_operand" "")
8309 (ge:SI (match_operand:SI 1 "register_operand" "")
8310 (match_operand:SI 2 "arith_operand" "")))]
8311 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
8313 (lt:SI (match_dup 1)
8316 (xor:SI (match_dup 0)
8320 (define_insn "sge_di"
8321 [(set (match_operand:DI 0 "register_operand" "=d")
8322 (ge:DI (match_operand:DI 1 "se_register_operand" "d")
8323 (match_operand:DI 2 "se_arith_operand" "dI")))]
8324 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8325 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
8326 [(set_attr "type" "arith")
8327 (set_attr "mode" "DI")
8328 (set_attr "length" "8")])
8331 [(set (match_operand:DI 0 "register_operand" "")
8332 (ge:DI (match_operand:DI 1 "se_register_operand" "")
8333 (match_operand:DI 2 "se_arith_operand" "")))]
8334 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8337 (lt:DI (match_dup 1)
8340 (xor:DI (match_dup 0)
8344 (define_expand "slt"
8345 [(set (match_operand:SI 0 "register_operand" "=d")
8346 (lt:SI (match_dup 1)
8351 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8354 /* set up operands from compare. */
8355 operands[1] = branch_cmp[0];
8356 operands[2] = branch_cmp[1];
8358 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8360 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
8364 /* fall through and generate default code */
8367 (define_insn "slt_si"
8368 [(set (match_operand:SI 0 "register_operand" "=d")
8369 (lt:SI (match_operand:SI 1 "register_operand" "d")
8370 (match_operand:SI 2 "arith_operand" "dI")))]
8373 [(set_attr "type" "arith")
8374 (set_attr "mode" "SI")])
8377 [(set (match_operand:SI 0 "register_operand" "=t,t")
8378 (lt:SI (match_operand:SI 1 "register_operand" "d,d")
8379 (match_operand:SI 2 "arith_operand" "d,I")))]
8382 [(set_attr "type" "arith")
8383 (set_attr "mode" "SI")
8384 (set_attr_alternative "length"
8386 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
8390 (define_insn "slt_di"
8391 [(set (match_operand:DI 0 "register_operand" "=d")
8392 (lt:DI (match_operand:DI 1 "se_register_operand" "d")
8393 (match_operand:DI 2 "se_arith_operand" "dI")))]
8394 "TARGET_64BIT && !TARGET_MIPS16"
8396 [(set_attr "type" "arith")
8397 (set_attr "mode" "DI")])
8400 [(set (match_operand:DI 0 "register_operand" "=t,t")
8401 (lt:DI (match_operand:DI 1 "se_register_operand" "d,d")
8402 (match_operand:DI 2 "se_arith_operand" "d,I")))]
8403 "TARGET_64BIT && TARGET_MIPS16"
8405 [(set_attr "type" "arith")
8406 (set_attr "mode" "DI")
8407 (set_attr_alternative "length"
8409 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
8413 (define_expand "sle"
8414 [(set (match_operand:SI 0 "register_operand" "=d")
8415 (le:SI (match_dup 1)
8420 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8423 /* set up operands from compare. */
8424 operands[1] = branch_cmp[0];
8425 operands[2] = branch_cmp[1];
8427 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8429 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
8433 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
8434 operands[2] = force_reg (SImode, operands[2]);
8436 /* fall through and generate default code */
8439 (define_insn "sle_si_const"
8440 [(set (match_operand:SI 0 "register_operand" "=d")
8441 (le:SI (match_operand:SI 1 "register_operand" "d")
8442 (match_operand:SI 2 "small_int" "I")))]
8443 "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8446 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8447 return \"slt\\t%0,%1,%2\";
8449 [(set_attr "type" "arith")
8450 (set_attr "mode" "SI")])
8453 [(set (match_operand:SI 0 "register_operand" "=t")
8454 (le:SI (match_operand:SI 1 "register_operand" "d")
8455 (match_operand:SI 2 "small_int" "I")))]
8456 "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8459 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8460 return \"slt\\t%1,%2\";
8462 [(set_attr "type" "arith")
8463 (set_attr "mode" "SI")
8464 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
8468 (define_insn "sle_di_const"
8469 [(set (match_operand:DI 0 "register_operand" "=d")
8470 (le:DI (match_operand:DI 1 "se_register_operand" "d")
8471 (match_operand:DI 2 "small_int" "I")))]
8472 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8475 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8476 return \"slt\\t%0,%1,%2\";
8478 [(set_attr "type" "arith")
8479 (set_attr "mode" "DI")])
8482 [(set (match_operand:DI 0 "register_operand" "=t")
8483 (le:DI (match_operand:DI 1 "se_register_operand" "d")
8484 (match_operand:DI 2 "small_int" "I")))]
8485 "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8488 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8489 return \"slt\\t%1,%2\";
8491 [(set_attr "type" "arith")
8492 (set_attr "mode" "DI")
8493 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
8497 (define_insn "sle_si_reg"
8498 [(set (match_operand:SI 0 "register_operand" "=d")
8499 (le:SI (match_operand:SI 1 "register_operand" "d")
8500 (match_operand:SI 2 "register_operand" "d")))]
8501 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8502 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
8503 [(set_attr "type" "arith")
8504 (set_attr "mode" "SI")
8505 (set_attr "length" "8")])
8508 [(set (match_operand:SI 0 "register_operand" "")
8509 (le:SI (match_operand:SI 1 "register_operand" "")
8510 (match_operand:SI 2 "register_operand" "")))]
8511 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
8513 (lt:SI (match_dup 2)
8516 (xor:SI (match_dup 0)
8520 (define_insn "sle_di_reg"
8521 [(set (match_operand:DI 0 "register_operand" "=d")
8522 (le:DI (match_operand:DI 1 "se_register_operand" "d")
8523 (match_operand:DI 2 "se_register_operand" "d")))]
8524 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8525 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
8526 [(set_attr "type" "arith")
8527 (set_attr "mode" "DI")
8528 (set_attr "length" "8")])
8531 [(set (match_operand:DI 0 "register_operand" "")
8532 (le:DI (match_operand:DI 1 "se_register_operand" "")
8533 (match_operand:DI 2 "se_register_operand" "")))]
8534 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8537 (lt:DI (match_dup 2)
8540 (xor:DI (match_dup 0)
8544 (define_expand "sgtu"
8545 [(set (match_operand:SI 0 "register_operand" "=d")
8546 (gtu:SI (match_dup 1)
8551 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8554 /* set up operands from compare. */
8555 operands[1] = branch_cmp[0];
8556 operands[2] = branch_cmp[1];
8558 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8560 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
8564 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
8565 operands[2] = force_reg (SImode, operands[2]);
8567 /* fall through and generate default code */
8570 (define_insn "sgtu_si"
8571 [(set (match_operand:SI 0 "register_operand" "=d")
8572 (gtu:SI (match_operand:SI 1 "register_operand" "d")
8573 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
8576 [(set_attr "type" "arith")
8577 (set_attr "mode" "SI")])
8580 [(set (match_operand:SI 0 "register_operand" "=t")
8581 (gtu:SI (match_operand:SI 1 "register_operand" "d")
8582 (match_operand:SI 2 "register_operand" "d")))]
8585 [(set_attr "type" "arith")
8586 (set_attr "mode" "SI")])
8588 (define_insn "sgtu_di"
8589 [(set (match_operand:DI 0 "register_operand" "=d")
8590 (gtu:DI (match_operand:DI 1 "se_register_operand" "d")
8591 (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
8594 [(set_attr "type" "arith")
8595 (set_attr "mode" "DI")])
8598 [(set (match_operand:DI 0 "register_operand" "=t")
8599 (gtu:DI (match_operand:DI 1 "se_register_operand" "d")
8600 (match_operand:DI 2 "se_register_operand" "d")))]
8603 [(set_attr "type" "arith")
8604 (set_attr "mode" "DI")])
8606 (define_expand "sgeu"
8607 [(set (match_operand:SI 0 "register_operand" "=d")
8608 (geu:SI (match_dup 1)
8613 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8616 /* set up operands from compare. */
8617 operands[1] = branch_cmp[0];
8618 operands[2] = branch_cmp[1];
8620 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8622 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
8626 /* fall through and generate default code */
8629 (define_insn "sgeu_si"
8630 [(set (match_operand:SI 0 "register_operand" "=d")
8631 (geu:SI (match_operand:SI 1 "register_operand" "d")
8632 (match_operand:SI 2 "arith_operand" "dI")))]
8633 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8634 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
8635 [(set_attr "type" "arith")
8636 (set_attr "mode" "SI")
8637 (set_attr "length" "8")])
8640 [(set (match_operand:SI 0 "register_operand" "")
8641 (geu:SI (match_operand:SI 1 "register_operand" "")
8642 (match_operand:SI 2 "arith_operand" "")))]
8643 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
8645 (ltu:SI (match_dup 1)
8648 (xor:SI (match_dup 0)
8652 (define_insn "sgeu_di"
8653 [(set (match_operand:DI 0 "register_operand" "=d")
8654 (geu:DI (match_operand:DI 1 "se_register_operand" "d")
8655 (match_operand:DI 2 "se_arith_operand" "dI")))]
8656 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8657 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
8658 [(set_attr "type" "arith")
8659 (set_attr "mode" "DI")
8660 (set_attr "length" "8")])
8663 [(set (match_operand:DI 0 "register_operand" "")
8664 (geu:DI (match_operand:DI 1 "se_register_operand" "")
8665 (match_operand:DI 2 "se_arith_operand" "")))]
8666 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8669 (ltu:DI (match_dup 1)
8672 (xor:DI (match_dup 0)
8676 (define_expand "sltu"
8677 [(set (match_operand:SI 0 "register_operand" "=d")
8678 (ltu:SI (match_dup 1)
8683 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8686 /* set up operands from compare. */
8687 operands[1] = branch_cmp[0];
8688 operands[2] = branch_cmp[1];
8690 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8692 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
8696 /* fall through and generate default code */
8699 (define_insn "sltu_si"
8700 [(set (match_operand:SI 0 "register_operand" "=d")
8701 (ltu:SI (match_operand:SI 1 "register_operand" "d")
8702 (match_operand:SI 2 "arith_operand" "dI")))]
8705 [(set_attr "type" "arith")
8706 (set_attr "mode" "SI")])
8709 [(set (match_operand:SI 0 "register_operand" "=t,t")
8710 (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
8711 (match_operand:SI 2 "arith_operand" "d,I")))]
8714 [(set_attr "type" "arith")
8715 (set_attr "mode" "SI")
8716 (set_attr_alternative "length"
8718 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
8722 (define_insn "sltu_di"
8723 [(set (match_operand:DI 0 "register_operand" "=d")
8724 (ltu:DI (match_operand:DI 1 "se_register_operand" "d")
8725 (match_operand:DI 2 "se_arith_operand" "dI")))]
8726 "TARGET_64BIT && !TARGET_MIPS16"
8728 [(set_attr "type" "arith")
8729 (set_attr "mode" "DI")])
8732 [(set (match_operand:DI 0 "register_operand" "=t,t")
8733 (ltu:DI (match_operand:DI 1 "se_register_operand" "d,d")
8734 (match_operand:DI 2 "se_arith_operand" "d,I")))]
8735 "TARGET_64BIT && TARGET_MIPS16"
8737 [(set_attr "type" "arith")
8738 (set_attr "mode" "DI")
8739 (set_attr_alternative "length"
8741 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
8745 (define_expand "sleu"
8746 [(set (match_operand:SI 0 "register_operand" "=d")
8747 (leu:SI (match_dup 1)
8752 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8755 /* set up operands from compare. */
8756 operands[1] = branch_cmp[0];
8757 operands[2] = branch_cmp[1];
8759 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8761 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
8765 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
8766 operands[2] = force_reg (SImode, operands[2]);
8768 /* fall through and generate default code */
8771 (define_insn "sleu_si_const"
8772 [(set (match_operand:SI 0 "register_operand" "=d")
8773 (leu:SI (match_operand:SI 1 "register_operand" "d")
8774 (match_operand:SI 2 "small_int" "I")))]
8775 "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8778 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
8779 return \"sltu\\t%0,%1,%2\";
8781 [(set_attr "type" "arith")
8782 (set_attr "mode" "SI")])
8785 [(set (match_operand:SI 0 "register_operand" "=t")
8786 (leu:SI (match_operand:SI 1 "register_operand" "d")
8787 (match_operand:SI 2 "small_int" "I")))]
8788 "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8791 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8792 return \"sltu\\t%1,%2\";
8794 [(set_attr "type" "arith")
8795 (set_attr "mode" "SI")
8796 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
8800 (define_insn "sleu_di_const"
8801 [(set (match_operand:DI 0 "register_operand" "=d")
8802 (leu:DI (match_operand:DI 1 "se_register_operand" "d")
8803 (match_operand:DI 2 "small_int" "I")))]
8804 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8807 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
8808 return \"sltu\\t%0,%1,%2\";
8810 [(set_attr "type" "arith")
8811 (set_attr "mode" "DI")])
8814 [(set (match_operand:DI 0 "register_operand" "=t")
8815 (leu:DI (match_operand:DI 1 "se_register_operand" "d")
8816 (match_operand:DI 2 "small_int" "I")))]
8817 "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8820 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8821 return \"sltu\\t%1,%2\";
8823 [(set_attr "type" "arith")
8824 (set_attr "mode" "DI")
8825 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
8829 (define_insn "sleu_si_reg"
8830 [(set (match_operand:SI 0 "register_operand" "=d")
8831 (leu:SI (match_operand:SI 1 "register_operand" "d")
8832 (match_operand:SI 2 "register_operand" "d")))]
8833 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8834 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
8835 [(set_attr "type" "arith")
8836 (set_attr "mode" "SI")
8837 (set_attr "length" "8")])
8840 [(set (match_operand:SI 0 "register_operand" "")
8841 (leu:SI (match_operand:SI 1 "register_operand" "")
8842 (match_operand:SI 2 "register_operand" "")))]
8843 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
8845 (ltu:SI (match_dup 2)
8848 (xor:SI (match_dup 0)
8852 (define_insn "sleu_di_reg"
8853 [(set (match_operand:DI 0 "register_operand" "=d")
8854 (leu:DI (match_operand:DI 1 "se_register_operand" "d")
8855 (match_operand:DI 2 "se_register_operand" "d")))]
8856 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8857 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
8858 [(set_attr "type" "arith")
8859 (set_attr "mode" "DI")
8860 (set_attr "length" "8")])
8863 [(set (match_operand:DI 0 "register_operand" "")
8864 (leu:DI (match_operand:DI 1 "se_register_operand" "")
8865 (match_operand:DI 2 "se_register_operand" "")))]
8866 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8869 (ltu:DI (match_dup 2)
8872 (xor:DI (match_dup 0)
8878 ;; ....................
8880 ;; FLOATING POINT COMPARISONS
8882 ;; ....................
8884 (define_insn "seq_df"
8885 [(set (match_operand:CC 0 "register_operand" "=z")
8886 (eq:CC (match_operand:DF 1 "register_operand" "f")
8887 (match_operand:DF 2 "register_operand" "f")))]
8888 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8891 return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
8893 [(set_attr "type" "fcmp")
8894 (set_attr "mode" "FPSW")])
8896 (define_insn "slt_df"
8897 [(set (match_operand:CC 0 "register_operand" "=z")
8898 (lt:CC (match_operand:DF 1 "register_operand" "f")
8899 (match_operand:DF 2 "register_operand" "f")))]
8900 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8903 return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
8905 [(set_attr "type" "fcmp")
8906 (set_attr "mode" "FPSW")])
8908 (define_insn "sle_df"
8909 [(set (match_operand:CC 0 "register_operand" "=z")
8910 (le:CC (match_operand:DF 1 "register_operand" "f")
8911 (match_operand:DF 2 "register_operand" "f")))]
8912 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8915 return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
8917 [(set_attr "type" "fcmp")
8918 (set_attr "mode" "FPSW")])
8920 (define_insn "sgt_df"
8921 [(set (match_operand:CC 0 "register_operand" "=z")
8922 (gt:CC (match_operand:DF 1 "register_operand" "f")
8923 (match_operand:DF 2 "register_operand" "f")))]
8924 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8927 return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
8929 [(set_attr "type" "fcmp")
8930 (set_attr "mode" "FPSW")])
8932 (define_insn "sge_df"
8933 [(set (match_operand:CC 0 "register_operand" "=z")
8934 (ge:CC (match_operand:DF 1 "register_operand" "f")
8935 (match_operand:DF 2 "register_operand" "f")))]
8936 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
8939 return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
8941 [(set_attr "type" "fcmp")
8942 (set_attr "mode" "FPSW")])
8944 (define_insn "seq_sf"
8945 [(set (match_operand:CC 0 "register_operand" "=z")
8946 (eq:CC (match_operand:SF 1 "register_operand" "f")
8947 (match_operand:SF 2 "register_operand" "f")))]
8951 return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
8953 [(set_attr "type" "fcmp")
8954 (set_attr "mode" "FPSW")])
8956 (define_insn "slt_sf"
8957 [(set (match_operand:CC 0 "register_operand" "=z")
8958 (lt:CC (match_operand:SF 1 "register_operand" "f")
8959 (match_operand:SF 2 "register_operand" "f")))]
8963 return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
8965 [(set_attr "type" "fcmp")
8966 (set_attr "mode" "FPSW")])
8968 (define_insn "sle_sf"
8969 [(set (match_operand:CC 0 "register_operand" "=z")
8970 (le:CC (match_operand:SF 1 "register_operand" "f")
8971 (match_operand:SF 2 "register_operand" "f")))]
8975 return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
8977 [(set_attr "type" "fcmp")
8978 (set_attr "mode" "FPSW")])
8980 (define_insn "sgt_sf"
8981 [(set (match_operand:CC 0 "register_operand" "=z")
8982 (gt:CC (match_operand:SF 1 "register_operand" "f")
8983 (match_operand:SF 2 "register_operand" "f")))]
8987 return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
8989 [(set_attr "type" "fcmp")
8990 (set_attr "mode" "FPSW")])
8992 (define_insn "sge_sf"
8993 [(set (match_operand:CC 0 "register_operand" "=z")
8994 (ge:CC (match_operand:SF 1 "register_operand" "f")
8995 (match_operand:SF 2 "register_operand" "f")))]
8999 return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
9001 [(set_attr "type" "fcmp")
9002 (set_attr "mode" "FPSW")])
9006 ;; ....................
9008 ;; UNCONDITIONAL BRANCHES
9010 ;; ....................
9012 ;; Unconditional branches.
9016 (label_ref (match_operand 0 "" "")))]
9020 if (GET_CODE (operands[0]) == REG)
9021 return \"%*j\\t%0\";
9022 /* ??? I don't know why this is necessary. This works around an
9023 assembler problem that appears when a label is defined, then referenced
9024 in a switch table, then used in a `j' instruction. */
9025 else if (mips_abi != ABI_32 && mips_abi != ABI_O64)
9026 return \"%*b\\t%l0\";
9028 return \"%*j\\t%l0\";
9030 [(set_attr "type" "jump")
9031 (set_attr "mode" "none")])
9033 ;; We need a different insn for the mips16, because a mips16 branch
9034 ;; does not have a delay slot.
9038 (label_ref (match_operand 0 "" "")))]
9039 "TARGET_MIPS16 && GET_CODE (operands[0]) != REG"
9041 [(set_attr "type" "branch")
9042 (set_attr "mode" "none")
9043 (set_attr "length" "8")])
9045 (define_expand "indirect_jump"
9046 [(set (pc) (match_operand 0 "register_operand" "d"))]
9052 if (operands[0]) /* eliminate unused code warnings */
9055 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
9056 operands[0] = copy_to_mode_reg (Pmode, dest);
9058 if (!(Pmode == DImode))
9059 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
9061 emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
9067 (define_insn "indirect_jump_internal1"
9068 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
9069 "!(Pmode == DImode)"
9071 [(set_attr "type" "jump")
9072 (set_attr "mode" "none")])
9074 (define_insn "indirect_jump_internal2"
9075 [(set (pc) (match_operand:DI 0 "se_register_operand" "d"))]
9078 [(set_attr "type" "jump")
9079 (set_attr "mode" "none")])
9081 (define_expand "tablejump"
9083 (match_operand 0 "register_operand" "d"))
9084 (use (label_ref (match_operand 1 "" "")))]
9088 if (operands[0]) /* eliminate unused code warnings */
9092 if (GET_MODE (operands[0]) != HImode)
9094 if (!(Pmode == DImode))
9095 emit_insn (gen_tablejump_mips161 (operands[0], operands[1]));
9097 emit_insn (gen_tablejump_mips162 (operands[0], operands[1]));
9101 if (GET_MODE (operands[0]) != Pmode)
9106 if (!(Pmode == DImode))
9107 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
9109 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
9113 if (!(Pmode == DImode))
9114 emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
9116 emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
9123 (define_insn "tablejump_internal1"
9125 (match_operand:SI 0 "register_operand" "d"))
9126 (use (label_ref (match_operand 1 "" "")))]
9127 "!(Pmode == DImode)"
9129 [(set_attr "type" "jump")
9130 (set_attr "mode" "none")])
9132 (define_insn "tablejump_internal2"
9134 (match_operand:DI 0 "se_register_operand" "d"))
9135 (use (label_ref (match_operand 1 "" "")))]
9138 [(set_attr "type" "jump")
9139 (set_attr "mode" "none")])
9141 (define_expand "tablejump_internal3"
9142 [(parallel [(set (pc)
9143 (plus:SI (match_operand:SI 0 "register_operand" "d")
9144 (label_ref:SI (match_operand 1 "" ""))))
9145 (use (label_ref:SI (match_dup 1)))])]
9149 (define_expand "tablejump_mips161"
9150 [(set (pc) (plus:SI (sign_extend:SI
9151 (match_operand:HI 0 "register_operand" "d"))
9152 (label_ref:SI (match_operand 1 "" ""))))]
9153 "TARGET_MIPS16 && !(Pmode == DImode)"
9156 if (operands[0]) /* eliminate unused code warnings. */
9160 t1 = gen_reg_rtx (SImode);
9161 t2 = gen_reg_rtx (SImode);
9162 t3 = gen_reg_rtx (SImode);
9163 emit_insn (gen_extendhisi2 (t1, operands[0]));
9164 emit_move_insn (t2, gen_rtx (LABEL_REF, SImode, operands[1]));
9165 emit_insn (gen_addsi3 (t3, t1, t2));
9166 emit_jump_insn (gen_tablejump_internal1 (t3, operands[1]));
9171 (define_expand "tablejump_mips162"
9172 [(set (pc) (plus:DI (sign_extend:DI
9173 (match_operand:HI 0 "register_operand" "d"))
9174 (label_ref:DI (match_operand 1 "" ""))))]
9175 "TARGET_MIPS16 && Pmode == DImode"
9178 if (operands[0]) /* eliminate unused code warnings. */
9182 t1 = gen_reg_rtx (DImode);
9183 t2 = gen_reg_rtx (DImode);
9184 t3 = gen_reg_rtx (DImode);
9185 emit_insn (gen_extendhidi2 (t1, operands[0]));
9186 emit_move_insn (t2, gen_rtx (LABEL_REF, DImode, operands[1]));
9187 emit_insn (gen_adddi3 (t3, t1, t2));
9188 emit_jump_insn (gen_tablejump_internal2 (t3, operands[1]));
9193 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
9194 ;;; it is not valid. ??? With the USE, the condition tests may not be required
9197 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
9198 ;;; We just use the conservative number here.
9202 (plus:SI (match_operand:SI 0 "register_operand" "d")
9203 (label_ref:SI (match_operand 1 "" ""))))
9204 (use (label_ref:SI (match_dup 1)))]
9205 "!(Pmode == DImode) && next_active_insn (insn) != 0
9206 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
9207 && PREV_INSN (next_active_insn (insn)) == operands[1]"
9210 /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic. */
9211 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
9212 output_asm_insn (\".cpadd\\t%0\", operands);
9213 return \"%*j\\t%0\";
9215 [(set_attr "type" "jump")
9216 (set_attr "mode" "none")
9217 (set_attr "length" "8")])
9219 (define_expand "tablejump_internal4"
9220 [(parallel [(set (pc)
9221 (plus:DI (match_operand:DI 0 "se_register_operand" "d")
9222 (label_ref:DI (match_operand 1 "" ""))))
9223 (use (label_ref:DI (match_dup 1)))])]
9227 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
9228 ;;; it is not valid. ??? With the USE, the condition tests may not be required
9233 (plus:DI (match_operand:DI 0 "se_register_operand" "d")
9234 (label_ref:DI (match_operand 1 "" ""))))
9235 (use (label_ref:DI (match_dup 1)))]
9236 "Pmode == DImode && next_active_insn (insn) != 0
9237 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
9238 && PREV_INSN (next_active_insn (insn)) == operands[1]"
9240 [(set_attr "type" "jump")
9241 (set_attr "mode" "none")])
9243 ;; Implement a switch statement when generating embedded PIC code.
9244 ;; Switches are implemented by `tablejump' when not using -membedded-pic.
9246 (define_expand "casesi"
9248 (minus:SI (match_operand:SI 0 "register_operand" "d")
9249 (match_operand:SI 1 "arith_operand" "dI")))
9251 (compare:CC (match_dup 5)
9252 (match_operand:SI 2 "arith_operand" "")))
9254 (if_then_else (gtu (cc0)
9256 (label_ref (match_operand 4 "" ""))
9260 (mem:SI (plus:SI (mult:SI (match_dup 5)
9262 (label_ref (match_operand 3 "" "")))))
9263 (clobber (match_scratch:SI 6 ""))
9264 (clobber (reg:SI 31))])]
9265 "TARGET_EMBEDDED_PIC"
9270 rtx reg = gen_reg_rtx (SImode);
9272 /* If the index is too large, go to the default label. */
9273 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
9274 emit_insn (gen_cmpsi (reg, operands[2]));
9275 emit_insn (gen_bgtu (operands[4]));
9277 /* Do the PIC jump. */
9278 if (Pmode != DImode)
9279 emit_jump_insn (gen_casesi_internal (reg, operands[3],
9280 gen_reg_rtx (SImode)));
9282 emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
9283 gen_reg_rtx (DImode)));
9289 ;; An embedded PIC switch statement looks like this:
9291 ;; sll $reg,$index,2
9293 ;; addu $reg,$reg,$31
9294 ;; lw $reg,$L1-$LS1($reg)
9295 ;; addu $reg,$reg,$31
9302 (define_insn "casesi_internal"
9304 (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
9306 (label_ref (match_operand 1 "" "")))))
9307 (clobber (match_operand:SI 2 "register_operand" "=d"))
9308 (clobber (reg:SI 31))]
9309 "TARGET_EMBEDDED_PIC"
9310 "%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
9311 lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2"
9312 [(set_attr "type" "jump")
9313 (set_attr "mode" "none")
9314 (set_attr "length" "24")])
9316 (define_insn "casesi_internal_di"
9318 (mem:DI (plus:DI (sign_extend:DI
9319 (mult:SI (match_operand:SI 0 "register_operand" "d")
9321 (label_ref (match_operand 1 "" "")))))
9322 (clobber (match_operand:DI 2 "register_operand" "=d"))
9323 (clobber (reg:DI 31))]
9324 "TARGET_EMBEDDED_PIC"
9325 "%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
9326 ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
9327 [(set_attr "type" "jump")
9328 (set_attr "mode" "none")
9329 (set_attr "length" "24")])
9331 ;; For o32/n32/n64, we save the gp in the jmp_buf as well. While it is
9332 ;; possible to either pull it off the stack (in the o32 case) or recalculate
9333 ;; it given t9 and our target label, it takes 3 or 4 insns to do so, and
9336 (define_expand "builtin_setjmp_setup"
9337 [(unspec [(match_operand 0 "register_operand" "r")] 20)]
9341 if (Pmode == DImode)
9342 emit_insn (gen_builtin_setjmp_setup_64 (operands[0]));
9344 emit_insn (gen_builtin_setjmp_setup_32 (operands[0]));
9348 (define_expand "builtin_setjmp_setup_32"
9349 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
9352 "TARGET_ABICALLS && ! (Pmode == DImode)"
9355 (define_expand "builtin_setjmp_setup_64"
9356 [(set (mem:DI (plus:DI (match_operand:DI 0 "register_operand" "r")
9359 "TARGET_ABICALLS && Pmode == DImode"
9362 ;; For o32/n32/n64, we need to arrange for longjmp to put the
9363 ;; target address in t9 so that we can use it for loading $gp.
9365 (define_expand "builtin_longjmp"
9366 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
9370 /* The elements of the buffer are, in order: */
9371 int W = (Pmode == DImode ? 8 : 4);
9372 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
9373 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
9374 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
9375 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
9376 rtx pv = gen_rtx_REG (Pmode, 25);
9377 rtx gp = gen_rtx_REG (Pmode, 28);
9379 /* This bit is the same as expand_builtin_longjmp. */
9380 emit_move_insn (hard_frame_pointer_rtx, fp);
9381 emit_move_insn (pv, lab);
9382 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
9383 emit_move_insn (gp, gpv);
9384 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
9385 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
9386 emit_insn (gen_rtx_USE (VOIDmode, gp));
9387 emit_indirect_jump (pv);
9392 ;; ....................
9394 ;; Function prologue/epilogue
9396 ;; ....................
9399 (define_expand "prologue"
9404 if (mips_isa >= 0) /* avoid unused code warnings */
9406 mips_expand_prologue ();
9411 ;; Block any insns from being moved before this point, since the
9412 ;; profiling call to mcount can use various registers that aren't
9413 ;; saved or used to pass arguments.
9415 (define_insn "blockage"
9416 [(unspec_volatile [(const_int 0)] 0)]
9419 [(set_attr "type" "unknown")
9420 (set_attr "mode" "none")
9421 (set_attr "length" "0")])
9423 (define_expand "epilogue"
9428 if (mips_isa >= 0) /* avoid unused code warnings */
9430 mips_expand_epilogue ();
9435 ;; Trivial return. Make it look like a normal return insn as that
9436 ;; allows jump optimizations to work better .
9437 (define_insn "return"
9439 "mips_can_use_return_insn ()"
9441 [(set_attr "type" "jump")
9442 (set_attr "mode" "none")])
9446 (define_insn "return_internal"
9447 [(use (match_operand 0 "pmode_register_operand" ""))
9452 return \"%*j\\t%0\";
9454 [(set_attr "type" "jump")
9455 (set_attr "mode" "none")])
9457 ;; When generating embedded PIC code we need to get the address of the
9458 ;; current function. This specialized instruction does just that.
9460 (define_insn "get_fnaddr"
9461 [(set (match_operand 0 "register_operand" "=d")
9462 (unspec [(match_operand 1 "" "")] 1))
9463 (clobber (reg:SI 31))]
9464 "TARGET_EMBEDDED_PIC
9465 && GET_CODE (operands[1]) == SYMBOL_REF"
9466 "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
9467 [(set_attr "type" "call")
9468 (set_attr "mode" "none")
9469 (set_attr "length" "16")])
9473 ;; ....................
9477 ;; ....................
9479 ;; calls.c now passes a third argument, make saber happy
9481 (define_expand "call"
9482 [(parallel [(call (match_operand 0 "memory_operand" "m")
9483 (match_operand 1 "" "i"))
9484 (clobber (reg:SI 31))
9485 (use (match_operand 2 "" "")) ;; next_arg_reg
9486 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
9492 if (operands[0]) /* eliminate unused code warnings */
9494 addr = XEXP (operands[0], 0);
9495 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
9496 || ! call_insn_operand (addr, VOIDmode))
9497 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
9499 /* In order to pass small structures by value in registers
9500 compatibly with the MIPS compiler, we need to shift the value
9501 into the high part of the register. Function_arg has encoded
9502 a PARALLEL rtx, holding a vector of adjustments to be made
9503 as the next_arg_reg variable, so we split up the insns,
9504 and emit them separately. */
9506 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
9508 rtvec adjust = XVEC (operands[2], 0);
9509 int num = GET_NUM_ELEM (adjust);
9512 for (i = 0; i < num; i++)
9513 emit_insn (RTVEC_ELT (adjust, i));
9517 && mips16_hard_float
9519 && (int) GET_MODE (operands[2]) != 0)
9521 if (build_mips16_call_stub (NULL_RTX, operands[0], operands[1],
9522 (int) GET_MODE (operands[2])))
9526 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
9527 gen_rtx_REG (SImode,
9528 GP_REG_FIRST + 31)));
9533 (define_expand "call_internal0"
9534 [(parallel [(call (match_operand 0 "" "")
9535 (match_operand 1 "" ""))
9536 (clobber (match_operand:SI 2 "" ""))])]
9540 ;; We need to recognize reg:SI 31 specially for the mips16, because we
9541 ;; don't have a constraint letter for it.
9544 [(call (mem (match_operand 0 "call_insn_operand" "ei"))
9545 (match_operand 1 "" "i"))
9546 (clobber (match_operand:SI 2 "register_operand" "=y"))]
9547 "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
9548 && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31"
9550 [(set_attr "type" "call")
9551 (set_attr "mode" "none")
9552 (set_attr "length" "8")])
9554 (define_insn "call_internal1"
9555 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
9556 (match_operand 1 "" "i"))
9557 (clobber (match_operand:SI 2 "register_operand" "=d"))]
9558 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
9561 register rtx target = operands[0];
9563 if (GET_CODE (target) == SYMBOL_REF)
9564 return \"%*jal\\t%0\";
9565 else if (GET_CODE (target) == CONST_INT)
9566 return \"%[li\\t%@,%0\\n\\t%*jal\\t%2,%@%]\";
9568 return \"%*jal\\t%2,%0\";
9570 [(set_attr "type" "call")
9571 (set_attr "mode" "none")])
9573 (define_insn "call_internal2"
9574 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
9575 (match_operand 1 "" "i"))
9576 (clobber (match_operand:SI 2 "register_operand" "=d"))]
9577 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
9580 register rtx target = operands[0];
9582 if (GET_CODE (target) == SYMBOL_REF)
9584 if (GET_MODE (target) == SImode)
9585 return \"la\\t%^,%0\\n\\tjal\\t%2,%^\";
9587 return \"dla\\t%^,%0\\n\\tjal\\t%2,%^\";
9589 else if (GET_CODE (target) == CONST_INT)
9590 return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
9591 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
9592 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
9594 return \"jal\\t%2,%0\";
9596 [(set_attr "type" "call")
9597 (set_attr "mode" "none")
9598 (set_attr "length" "8")])
9600 (define_insn "call_internal3a"
9601 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
9602 (match_operand 1 "" "i"))
9603 (clobber (match_operand:SI 2 "register_operand" "=d"))]
9605 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
9607 [(set_attr "type" "call")
9608 (set_attr "mode" "none")])
9610 (define_insn "call_internal3b"
9611 [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
9612 (match_operand 1 "" "i"))
9613 (clobber (match_operand:SI 2 "register_operand" "=d"))]
9615 && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
9617 [(set_attr "type" "call")
9618 (set_attr "mode" "none")
9619 (set_attr "length" "1")])
9621 (define_insn "call_internal3c"
9622 [(call (mem:SI (match_operand:SI 0 "register_operand" "e"))
9623 (match_operand 1 "" "i"))
9624 (clobber (match_operand:SI 2 "register_operand" "=y"))]
9625 "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS
9626 && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31"
9628 [(set_attr "type" "call")
9629 (set_attr "mode" "none")])
9631 (define_insn "call_internal4a"
9632 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
9633 (match_operand 1 "" "i"))
9634 (clobber (match_operand:SI 2 "register_operand" "=d"))]
9635 "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
9638 if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
9639 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
9641 return \"jal\\t%2,%0\";
9643 [(set_attr "type" "call")
9644 (set_attr "mode" "none")
9645 (set_attr "length" "8")])
9647 (define_insn "call_internal4b"
9648 [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
9649 (match_operand 1 "" "i"))
9650 (clobber (match_operand:SI 2 "register_operand" "=d"))]
9651 "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
9654 if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
9655 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
9657 return \"jal\\t%2,%0\";
9659 [(set_attr "type" "call")
9660 (set_attr "mode" "none")
9661 (set_attr "length" "8")])
9663 ;; calls.c now passes a fourth argument, make saber happy
9665 (define_expand "call_value"
9666 [(parallel [(set (match_operand 0 "register_operand" "=df")
9667 (call (match_operand 1 "memory_operand" "m")
9668 (match_operand 2 "" "i")))
9669 (clobber (reg:SI 31))
9670 (use (match_operand 3 "" ""))])] ;; next_arg_reg
9676 if (operands[0]) /* eliminate unused code warning */
9678 addr = XEXP (operands[1], 0);
9679 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
9680 || ! call_insn_operand (addr, VOIDmode))
9681 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
9683 /* In order to pass small structures by value in registers
9684 compatibly with the MIPS compiler, we need to shift the value
9685 into the high part of the register. Function_arg has encoded
9686 a PARALLEL rtx, holding a vector of adjustments to be made
9687 as the next_arg_reg variable, so we split up the insns,
9688 and emit them separately. */
9690 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
9692 rtvec adjust = XVEC (operands[3], 0);
9693 int num = GET_NUM_ELEM (adjust);
9696 for (i = 0; i < num; i++)
9697 emit_insn (RTVEC_ELT (adjust, i));
9701 && mips16_hard_float
9702 && ((operands[3] != 0
9703 && (int) GET_MODE (operands[3]) != 0)
9704 || GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT))
9706 if (build_mips16_call_stub (operands[0], operands[1], operands[2],
9707 (operands[3] == 0 ? 0
9708 : (int) GET_MODE (operands[3]))))
9712 /* Handle Irix6 function calls that have multiple non-contiguous
9714 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
9716 emit_call_insn (gen_call_value_multiple_internal0
9717 (XEXP (XVECEXP (operands[0], 0, 0), 0),
9718 operands[1], operands[2],
9719 XEXP (XVECEXP (operands[0], 0, 1), 0),
9720 gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
9724 /* We have a call returning a DImode structure in an FP reg.
9725 Strip off the now unnecessary PARALLEL. */
9726 if (GET_CODE (operands[0]) == PARALLEL)
9727 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
9729 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
9730 gen_rtx_REG (SImode,
9731 GP_REG_FIRST + 31)));
9737 (define_expand "call_value_internal0"
9738 [(parallel [(set (match_operand 0 "" "")
9739 (call (match_operand 1 "" "")
9740 (match_operand 2 "" "")))
9741 (clobber (match_operand:SI 3 "" ""))])]
9745 ;; Recognize $31 specially on the mips16, because we don't have a
9746 ;; constraint letter for it.
9749 [(set (match_operand 0 "register_operand" "=d")
9750 (call (mem (match_operand 1 "call_insn_operand" "ei"))
9751 (match_operand 2 "" "i")))
9752 (clobber (match_operand:SI 3 "register_operand" "=y"))]
9753 "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
9754 && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
9756 [(set_attr "type" "call")
9757 (set_attr "mode" "none")
9758 (set_attr "length" "8")])
9760 (define_insn "call_value_internal1"
9761 [(set (match_operand 0 "register_operand" "=df")
9762 (call (mem (match_operand 1 "call_insn_operand" "ri"))
9763 (match_operand 2 "" "i")))
9764 (clobber (match_operand:SI 3 "register_operand" "=d"))]
9765 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
9768 register rtx target = operands[1];
9770 if (GET_CODE (target) == SYMBOL_REF)
9771 return \"%*jal\\t%1\";
9772 else if (GET_CODE (target) == CONST_INT)
9773 return \"%[li\\t%@,%1\\n\\t%*jal\\t%3,%@%]\";
9775 return \"%*jal\\t%3,%1\";
9777 [(set_attr "type" "call")
9778 (set_attr "mode" "none")])
9780 (define_insn "call_value_internal2"
9781 [(set (match_operand 0 "register_operand" "=df")
9782 (call (mem (match_operand 1 "call_insn_operand" "ri"))
9783 (match_operand 2 "" "i")))
9784 (clobber (match_operand:SI 3 "register_operand" "=d"))]
9785 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
9788 register rtx target = operands[1];
9790 if (GET_CODE (target) == SYMBOL_REF)
9792 if (GET_MODE (target) == SImode)
9793 return \"la\\t%^,%1\\n\\tjal\\t%3,%^\";
9795 return \"dla\\t%^,%1\\n\\tjal\\t%3,%^\";
9797 else if (GET_CODE (target) == CONST_INT)
9798 return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
9799 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
9800 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
9802 return \"jal\\t%3,%1\";
9804 [(set_attr "type" "call")
9805 (set_attr "mode" "none")
9806 (set_attr "length" "8")])
9808 (define_insn "call_value_internal3a"
9809 [(set (match_operand 0 "register_operand" "=df")
9810 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
9811 (match_operand 2 "" "i")))
9812 (clobber (match_operand:SI 3 "register_operand" "=d"))]
9814 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
9816 [(set_attr "type" "call")
9817 (set_attr "mode" "none")])
9819 (define_insn "call_value_internal3b"
9820 [(set (match_operand 0 "register_operand" "=df")
9821 (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
9822 (match_operand 2 "" "i")))
9823 (clobber (match_operand:SI 3 "register_operand" "=d"))]
9825 && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
9827 [(set_attr "type" "call")
9828 (set_attr "mode" "none")])
9830 (define_insn "call_value_internal3c"
9831 [(set (match_operand 0 "register_operand" "=df")
9832 (call (mem:SI (match_operand:SI 1 "register_operand" "e"))
9833 (match_operand 2 "" "i")))
9834 (clobber (match_operand:SI 3 "register_operand" "=y"))]
9835 "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS
9836 && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
9838 [(set_attr "type" "call")
9839 (set_attr "mode" "none")])
9841 (define_insn "call_value_internal4a"
9842 [(set (match_operand 0 "register_operand" "=df")
9843 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
9844 (match_operand 2 "" "i")))
9845 (clobber (match_operand:SI 3 "register_operand" "=d"))]
9846 "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
9849 if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
9850 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
9852 return \"jal\\t%3,%1\";
9854 [(set_attr "type" "call")
9855 (set_attr "mode" "none")
9856 (set_attr "length" "8")])
9858 (define_insn "call_value_internal4b"
9859 [(set (match_operand 0 "register_operand" "=df")
9860 (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
9861 (match_operand 2 "" "i")))
9862 (clobber (match_operand:SI 3 "register_operand" "=d"))]
9863 "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
9866 if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
9867 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
9869 return \"jal\\t%3,%1\";
9871 [(set_attr "type" "call")
9872 (set_attr "mode" "none")
9873 (set_attr "length" "8")])
9875 (define_expand "call_value_multiple_internal0"
9876 [(parallel [(set (match_operand 0 "" "")
9877 (call (match_operand 1 "" "")
9878 (match_operand 2 "" "")))
9879 (set (match_operand 3 "" "")
9882 (clobber (match_operand:SI 4 "" ""))])]
9886 ;; ??? May eventually need all 6 versions of the call patterns with multiple
9889 (define_insn "call_value_multiple_internal1"
9890 [(set (match_operand 0 "register_operand" "=df")
9891 (call (mem (match_operand 1 "call_insn_operand" "ri"))
9892 (match_operand 2 "" "i")))
9893 (set (match_operand 3 "register_operand" "=df")
9894 (call (mem (match_dup 1))
9896 (clobber (match_operand:SI 4 "register_operand" "=d"))]
9897 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
9900 register rtx target = operands[1];
9902 if (GET_CODE (target) == SYMBOL_REF)
9903 return \"%*jal\\t%1\";
9904 else if (GET_CODE (target) == CONST_INT)
9905 return \"%[li\\t%@,%1\\n\\t%*jal\\t%4,%@%]\";
9907 return \"%*jal\\t%4,%1\";
9909 [(set_attr "type" "call")
9910 (set_attr "mode" "none")])
9912 (define_insn "call_value_multiple_internal2"
9913 [(set (match_operand 0 "register_operand" "=df")
9914 (call (mem (match_operand 1 "call_insn_operand" "ri"))
9915 (match_operand 2 "" "i")))
9916 (set (match_operand 3 "register_operand" "=df")
9917 (call (mem (match_dup 1))
9919 (clobber (match_operand:SI 4 "register_operand" "=d"))]
9920 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
9923 register rtx target = operands[1];
9925 if (GET_CODE (target) == SYMBOL_REF)
9927 if (GET_MODE (target) == SImode)
9928 return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
9930 return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
9932 else if (GET_CODE (target) == CONST_INT)
9933 return \"li\\t%^,%1\\n\\tjal\\t%4,%^\";
9934 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
9935 return \"move\\t%^,%1\\n\\tjal\\t%4,%^\";
9937 return \"jal\\t%4,%1\";
9939 [(set_attr "type" "call")
9940 (set_attr "mode" "none")
9941 (set_attr "length" "8")])
9944 ;; Call subroutine returning any type.
9946 (define_expand "untyped_call"
9947 [(parallel [(call (match_operand 0 "" "")
9949 (match_operand 1 "" "")
9950 (match_operand 2 "" "")])]
9954 if (operands[0]) /* silence statement not reached warnings */
9958 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
9960 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9962 rtx set = XVECEXP (operands[2], 0, i);
9963 emit_move_insn (SET_DEST (set), SET_SRC (set));
9966 emit_insn (gen_blockage ());
9972 ;; ....................
9976 ;; ....................
9983 [(set_attr "type" "nop")
9984 (set_attr "mode" "none")])
9986 ;; The MIPS chip does not seem to require stack probes.
9988 ;; (define_expand "probe"
9989 ;; [(set (match_dup 0)
9994 ;; operands[0] = gen_reg_rtx (SImode);
9995 ;; operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
9996 ;; MEM_VOLATILE_P (operands[1]) = TRUE;
9998 ;; /* fall through and generate default code */
10003 ;; MIPS4 Conditional move instructions.
10006 [(set (match_operand:SI 0 "register_operand" "=d,d")
10008 (match_operator 4 "equality_op"
10009 [(match_operand:SI 1 "register_operand" "d,d")
10011 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
10012 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
10013 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10016 mov%b4\\t%0,%z3,%1"
10017 [(set_attr "type" "move")
10018 (set_attr "mode" "SI")])
10021 [(set (match_operand:SI 0 "register_operand" "=d,d")
10023 (match_operator 4 "equality_op"
10024 [(match_operand:DI 1 "se_register_operand" "d,d")
10026 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
10027 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
10028 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10031 mov%b4\\t%0,%z3,%1"
10032 [(set_attr "type" "move")
10033 (set_attr "mode" "SI")])
10036 [(set (match_operand:SI 0 "register_operand" "=d,d")
10038 (match_operator 3 "equality_op" [(match_operand:CC 4
10042 (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
10043 (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
10044 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10047 mov%t3\\t%0,%z2,%4"
10048 [(set_attr "type" "move")
10049 (set_attr "mode" "SI")])
10052 [(set (match_operand:DI 0 "register_operand" "=d,d")
10054 (match_operator 4 "equality_op"
10055 [(match_operand:SI 1 "register_operand" "d,d")
10057 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
10058 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
10059 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10062 mov%b4\\t%0,%z3,%1"
10063 [(set_attr "type" "move")
10064 (set_attr "mode" "DI")])
10067 [(set (match_operand:DI 0 "register_operand" "=d,d")
10069 (match_operator 4 "equality_op"
10070 [(match_operand:DI 1 "se_register_operand" "d,d")
10072 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
10073 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
10074 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10077 mov%b4\\t%0,%z3,%1"
10078 [(set_attr "type" "move")
10079 (set_attr "mode" "DI")])
10082 [(set (match_operand:DI 0 "register_operand" "=d,d")
10084 (match_operator 3 "equality_op" [(match_operand:CC 4
10088 (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
10089 (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
10090 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10093 mov%t3\\t%0,%z2,%4"
10094 [(set_attr "type" "move")
10095 (set_attr "mode" "DI")])
10098 [(set (match_operand:SF 0 "register_operand" "=f,f")
10100 (match_operator 4 "equality_op"
10101 [(match_operand:SI 1 "register_operand" "d,d")
10103 (match_operand:SF 2 "register_operand" "f,0")
10104 (match_operand:SF 3 "register_operand" "0,f")))]
10105 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10107 mov%B4.s\\t%0,%2,%1
10108 mov%b4.s\\t%0,%3,%1"
10109 [(set_attr "type" "move")
10110 (set_attr "mode" "SF")])
10113 [(set (match_operand:SF 0 "register_operand" "=f,f")
10115 (match_operator 4 "equality_op"
10116 [(match_operand:DI 1 "se_register_operand" "d,d")
10118 (match_operand:SF 2 "register_operand" "f,0")
10119 (match_operand:SF 3 "register_operand" "0,f")))]
10120 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10122 mov%B4.s\\t%0,%2,%1
10123 mov%b4.s\\t%0,%3,%1"
10124 [(set_attr "type" "move")
10125 (set_attr "mode" "SF")])
10128 [(set (match_operand:SF 0 "register_operand" "=f,f")
10130 (match_operator 3 "equality_op" [(match_operand:CC 4
10134 (match_operand:SF 1 "register_operand" "f,0")
10135 (match_operand:SF 2 "register_operand" "0,f")))]
10136 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10138 mov%T3.s\\t%0,%1,%4
10139 mov%t3.s\\t%0,%2,%4"
10140 [(set_attr "type" "move")
10141 (set_attr "mode" "SF")])
10144 [(set (match_operand:DF 0 "register_operand" "=f,f")
10146 (match_operator 4 "equality_op"
10147 [(match_operand:SI 1 "register_operand" "d,d")
10149 (match_operand:DF 2 "register_operand" "f,0")
10150 (match_operand:DF 3 "register_operand" "0,f")))]
10151 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
10153 mov%B4.d\\t%0,%2,%1
10154 mov%b4.d\\t%0,%3,%1"
10155 [(set_attr "type" "move")
10156 (set_attr "mode" "DF")])
10159 [(set (match_operand:DF 0 "register_operand" "=f,f")
10161 (match_operator 4 "equality_op"
10162 [(match_operand:DI 1 "se_register_operand" "d,d")
10164 (match_operand:DF 2 "register_operand" "f,0")
10165 (match_operand:DF 3 "register_operand" "0,f")))]
10166 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
10168 mov%B4.d\\t%0,%2,%1
10169 mov%b4.d\\t%0,%3,%1"
10170 [(set_attr "type" "move")
10171 (set_attr "mode" "DF")])
10174 [(set (match_operand:DF 0 "register_operand" "=f,f")
10176 (match_operator 3 "equality_op" [(match_operand:CC 4
10180 (match_operand:DF 1 "register_operand" "f,0")
10181 (match_operand:DF 2 "register_operand" "0,f")))]
10182 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
10184 mov%T3.d\\t%0,%1,%4
10185 mov%t3.d\\t%0,%2,%4"
10186 [(set_attr "type" "move")
10187 (set_attr "mode" "DF")])
10189 ;; These are the main define_expand's used to make conditional moves.
10191 (define_expand "movsicc"
10192 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
10193 (set (match_operand:SI 0 "register_operand" "")
10194 (if_then_else:SI (match_dup 5)
10195 (match_operand:SI 2 "reg_or_0_operand" "")
10196 (match_operand:SI 3 "reg_or_0_operand" "")))]
10197 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10200 gen_conditional_move (operands);
10204 (define_expand "movdicc"
10205 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
10206 (set (match_operand:DI 0 "register_operand" "")
10207 (if_then_else:DI (match_dup 5)
10208 (match_operand:DI 2 "se_reg_or_0_operand" "")
10209 (match_operand:DI 3 "se_reg_or_0_operand" "")))]
10210 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10213 gen_conditional_move (operands);
10217 (define_expand "movsfcc"
10218 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
10219 (set (match_operand:SF 0 "register_operand" "")
10220 (if_then_else:SF (match_dup 5)
10221 (match_operand:SF 2 "register_operand" "")
10222 (match_operand:SF 3 "register_operand" "")))]
10223 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10226 gen_conditional_move (operands);
10230 (define_expand "movdfcc"
10231 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
10232 (set (match_operand:DF 0 "register_operand" "")
10233 (if_then_else:DF (match_dup 5)
10234 (match_operand:DF 2 "register_operand" "")
10235 (match_operand:DF 3 "register_operand" "")))]
10236 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
10239 gen_conditional_move (operands);
10244 ;; ....................
10246 ;; mips16 inline constant tables
10248 ;; ....................
10251 (define_insn "consttable_qi"
10252 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")] 10)]
10256 assemble_integer (operands[0], 1, 1);
10259 [(set_attr "type" "unknown")
10260 (set_attr "mode" "QI")
10261 (set_attr "length" "8")])
10263 (define_insn "consttable_hi"
10264 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")] 11)]
10268 assemble_integer (operands[0], 2, 1);
10271 [(set_attr "type" "unknown")
10272 (set_attr "mode" "HI")
10273 (set_attr "length" "8")])
10275 (define_insn "consttable_si"
10276 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")] 12)]
10280 assemble_integer (operands[0], 4, 1);
10283 [(set_attr "type" "unknown")
10284 (set_attr "mode" "SI")
10285 (set_attr "length" "8")])
10287 (define_insn "consttable_di"
10288 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")] 13)]
10292 assemble_integer (operands[0], 8, 1);
10295 [(set_attr "type" "unknown")
10296 (set_attr "mode" "DI")
10297 (set_attr "length" "16")])
10299 (define_insn "consttable_sf"
10300 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")] 14)]
10304 union real_extract u;
10306 if (GET_CODE (operands[0]) != CONST_DOUBLE)
10308 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
10309 assemble_real (u.d, SFmode);
10312 [(set_attr "type" "unknown")
10313 (set_attr "mode" "SF")
10314 (set_attr "length" "8")])
10316 (define_insn "consttable_df"
10317 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")] 15)]
10321 union real_extract u;
10323 if (GET_CODE (operands[0]) != CONST_DOUBLE)
10325 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
10326 assemble_real (u.d, DFmode);
10329 [(set_attr "type" "unknown")
10330 (set_attr "mode" "DF")
10331 (set_attr "length" "16")])
10333 (define_insn "align_2"
10334 [(unspec_volatile [(const_int 0)] 16)]
10337 [(set_attr "type" "unknown")
10338 (set_attr "mode" "HI")
10339 (set_attr "length" "8")])
10341 (define_insn "align_4"
10342 [(unspec_volatile [(const_int 0)] 17)]
10345 [(set_attr "type" "unknown")
10346 (set_attr "mode" "SI")
10347 (set_attr "length" "8")])
10349 (define_insn "align_8"
10350 [(unspec_volatile [(const_int 0)] 18)]
10353 [(set_attr "type" "unknown")
10354 (set_attr "mode" "DI")
10355 (set_attr "length" "12")])
10358 ;; ....................
10360 ;; mips16 peepholes
10362 ;; ....................
10365 ;; On the mips16, reload will sometimes decide that a pseudo register
10366 ;; should go into $24, and then later on have to reload that register.
10367 ;; When that happens, we get a load of a general register followed by
10368 ;; a move from the general register to $24 followed by a branch.
10369 ;; These peepholes catch the common case, and fix it to just use the
10370 ;; general register for the branch.
10373 [(set (match_operand:SI 0 "register_operand" "=t")
10374 (match_operand:SI 1 "register_operand" "d"))
10376 (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
10378 (match_operand 3 "pc_or_label_operand" "")
10379 (match_operand 4 "pc_or_label_operand" "")))]
10381 && GET_CODE (operands[0]) == REG
10382 && REGNO (operands[0]) == 24
10383 && dead_or_set_p (insn, operands[0])
10384 && GET_CODE (operands[1]) == REG
10385 && M16_REG_P (REGNO (operands[1]))"
10388 if (operands[3] != pc_rtx)
10389 return \"%*b%C2z\\t%1,%3\";
10391 return \"%*b%N2z\\t%1,%4\";
10393 [(set_attr "type" "branch")
10394 (set_attr "mode" "none")
10395 (set_attr "length" "8")])
10398 [(set (match_operand:DI 0 "register_operand" "=t")
10399 (match_operand:DI 1 "register_operand" "d"))
10401 (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
10403 (match_operand 3 "pc_or_label_operand" "")
10404 (match_operand 4 "pc_or_label_operand" "")))]
10405 "TARGET_MIPS16 && TARGET_64BIT
10406 && GET_CODE (operands[0]) == REG
10407 && REGNO (operands[0]) == 24
10408 && dead_or_set_p (insn, operands[0])
10409 && GET_CODE (operands[1]) == REG
10410 && M16_REG_P (REGNO (operands[1]))"
10413 if (operands[3] != pc_rtx)
10414 return \"%*b%C2z\\t%1,%3\";
10416 return \"%*b%N2z\\t%1,%4\";
10418 [(set_attr "type" "branch")
10419 (set_attr "mode" "none")
10420 (set_attr "length" "8")])
10422 ;; We can also have the reverse reload: reload will spill $24 into
10423 ;; another register, and then do a branch on that register when it
10424 ;; could have just stuck with $24.
10427 [(set (match_operand:SI 0 "register_operand" "=d")
10428 (match_operand:SI 1 "register_operand" "t"))
10430 (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
10432 (match_operand 3 "pc_or_label_operand" "")
10433 (match_operand 4 "pc_or_label_operand" "")))]
10435 && GET_CODE (operands[1]) == REG
10436 && REGNO (operands[1]) == 24
10437 && GET_CODE (operands[0]) == REG
10438 && M16_REG_P (REGNO (operands[0]))
10439 && dead_or_set_p (insn, operands[0])"
10442 if (operands[3] != pc_rtx)
10443 return \"%*bt%C2z\\t%3\";
10445 return \"%*bt%N2z\\t%4\";
10447 [(set_attr "type" "branch")
10448 (set_attr "mode" "none")
10449 (set_attr "length" "8")])
10452 [(set (match_operand:DI 0 "register_operand" "=d")
10453 (match_operand:DI 1 "register_operand" "t"))
10455 (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
10457 (match_operand 3 "pc_or_label_operand" "")
10458 (match_operand 4 "pc_or_label_operand" "")))]
10459 "TARGET_MIPS16 && TARGET_64BIT
10460 && GET_CODE (operands[1]) == REG
10461 && REGNO (operands[1]) == 24
10462 && GET_CODE (operands[0]) == REG
10463 && M16_REG_P (REGNO (operands[0]))
10464 && dead_or_set_p (insn, operands[0])"
10467 if (operands[3] != pc_rtx)
10468 return \"%*bt%C2z\\t%3\";
10470 return \"%*bt%N2z\\t%4\";
10472 [(set_attr "type" "branch")
10473 (set_attr "mode" "none")
10474 (set_attr "length" "8")])
10476 ;; For the rare case where we need to load an address into a register
10477 ;; that can not be recognized by the normal movsi/addsi instructions.
10478 ;; I have no idea how many insns this can actually generate. It should
10479 ;; be rare, so over-estimating as 10 instructions should not have any
10480 ;; real performance impact.
10481 (define_insn "leasi"
10482 [(set (match_operand:SI 0 "register_operand" "=d")
10483 (match_operand:SI 1 "address_operand" "p"))]
10486 [(set_attr "type" "arith")
10487 (set_attr "mode" "SI")
10488 (set_attr "length" "40")])
10490 ;; Similarly for targets where we have 64bit pointers.
10491 (define_insn "leadi"
10492 [(set (match_operand:DI 0 "register_operand" "=d")
10493 (match_operand:DI 1 "address_operand" "p"))]
10496 [(set_attr "type" "arith")
10497 (set_attr "mode" "DI")
10498 (set_attr "length" "40")])