1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
51 (UNSPEC_TLS_GET_TP 30)
54 (UNSPEC_CLEAR_HAZARD 33)
58 (UNSPEC_COMPARE_AND_SWAP 37)
59 (UNSPEC_COMPARE_AND_SWAP_12 38)
60 (UNSPEC_SYNC_OLD_OP 39)
61 (UNSPEC_SYNC_NEW_OP 40)
62 (UNSPEC_SYNC_NEW_OP_12 41)
63 (UNSPEC_SYNC_OLD_OP_12 42)
64 (UNSPEC_SYNC_EXCHANGE 43)
65 (UNSPEC_SYNC_EXCHANGE_12 44)
66 (UNSPEC_MEMORY_BARRIER 45)
67 (UNSPEC_SET_GOT_VERSION 46)
68 (UNSPEC_UPDATE_GOT_VERSION 47)
71 (UNSPEC_ADDRESS_FIRST 100)
74 (GOT_VERSION_REGNUM 79)
76 ;; For MIPS Paired-Singled Floating Point Instructions.
78 (UNSPEC_MOVE_TF_PS 200)
81 ;; MIPS64/MIPS32R2 alnv.ps
84 ;; MIPS-3D instructions
88 (UNSPEC_CVT_PW_PS 205)
89 (UNSPEC_CVT_PS_PW 206)
97 (UNSPEC_SINGLE_CC 213)
100 ;; MIPS DSP ASE Revision 0.98 3/24/2005
108 (UNSPEC_RADDU_W_QB 307)
110 (UNSPEC_PRECRQ_QB_PH 309)
111 (UNSPEC_PRECRQ_PH_W 310)
112 (UNSPEC_PRECRQ_RS_PH_W 311)
113 (UNSPEC_PRECRQU_S_QB_PH 312)
114 (UNSPEC_PRECEQ_W_PHL 313)
115 (UNSPEC_PRECEQ_W_PHR 314)
116 (UNSPEC_PRECEQU_PH_QBL 315)
117 (UNSPEC_PRECEQU_PH_QBR 316)
118 (UNSPEC_PRECEQU_PH_QBLA 317)
119 (UNSPEC_PRECEQU_PH_QBRA 318)
120 (UNSPEC_PRECEU_PH_QBL 319)
121 (UNSPEC_PRECEU_PH_QBR 320)
122 (UNSPEC_PRECEU_PH_QBLA 321)
123 (UNSPEC_PRECEU_PH_QBRA 322)
129 (UNSPEC_MULEU_S_PH_QBL 328)
130 (UNSPEC_MULEU_S_PH_QBR 329)
131 (UNSPEC_MULQ_RS_PH 330)
132 (UNSPEC_MULEQ_S_W_PHL 331)
133 (UNSPEC_MULEQ_S_W_PHR 332)
134 (UNSPEC_DPAU_H_QBL 333)
135 (UNSPEC_DPAU_H_QBR 334)
136 (UNSPEC_DPSU_H_QBL 335)
137 (UNSPEC_DPSU_H_QBR 336)
138 (UNSPEC_DPAQ_S_W_PH 337)
139 (UNSPEC_DPSQ_S_W_PH 338)
140 (UNSPEC_MULSAQ_S_W_PH 339)
141 (UNSPEC_DPAQ_SA_L_W 340)
142 (UNSPEC_DPSQ_SA_L_W 341)
143 (UNSPEC_MAQ_S_W_PHL 342)
144 (UNSPEC_MAQ_S_W_PHR 343)
145 (UNSPEC_MAQ_SA_W_PHL 344)
146 (UNSPEC_MAQ_SA_W_PHR 345)
154 (UNSPEC_CMPGU_EQ_QB 353)
155 (UNSPEC_CMPGU_LT_QB 354)
156 (UNSPEC_CMPGU_LE_QB 355)
158 (UNSPEC_PACKRL_PH 357)
160 (UNSPEC_EXTR_R_W 359)
161 (UNSPEC_EXTR_RS_W 360)
162 (UNSPEC_EXTR_S_H 361)
170 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
171 (UNSPEC_ABSQ_S_QB 400)
173 (UNSPEC_ADDU_S_PH 402)
174 (UNSPEC_ADDUH_QB 403)
175 (UNSPEC_ADDUH_R_QB 404)
178 (UNSPEC_CMPGDU_EQ_QB 407)
179 (UNSPEC_CMPGDU_LT_QB 408)
180 (UNSPEC_CMPGDU_LE_QB 409)
181 (UNSPEC_DPA_W_PH 410)
182 (UNSPEC_DPS_W_PH 411)
188 (UNSPEC_MUL_S_PH 417)
189 (UNSPEC_MULQ_RS_W 418)
190 (UNSPEC_MULQ_S_PH 419)
191 (UNSPEC_MULQ_S_W 420)
192 (UNSPEC_MULSA_W_PH 421)
195 (UNSPEC_PRECR_QB_PH 424)
196 (UNSPEC_PRECR_SRA_PH_W 425)
197 (UNSPEC_PRECR_SRA_R_PH_W 426)
200 (UNSPEC_SHRA_R_QB 429)
203 (UNSPEC_SUBU_S_PH 432)
204 (UNSPEC_SUBUH_QB 433)
205 (UNSPEC_SUBUH_R_QB 434)
206 (UNSPEC_ADDQH_PH 435)
207 (UNSPEC_ADDQH_R_PH 436)
209 (UNSPEC_ADDQH_R_W 438)
210 (UNSPEC_SUBQH_PH 439)
211 (UNSPEC_SUBQH_R_PH 440)
213 (UNSPEC_SUBQH_R_W 442)
214 (UNSPEC_DPAX_W_PH 443)
215 (UNSPEC_DPSX_W_PH 444)
216 (UNSPEC_DPAQX_S_W_PH 445)
217 (UNSPEC_DPAQX_SA_W_PH 446)
218 (UNSPEC_DPSQX_S_W_PH 447)
219 (UNSPEC_DPSQX_SA_W_PH 448)
221 ;; ST Microelectronics Loongson-2E/2F.
222 (UNSPEC_LOONGSON_PAVG 500)
223 (UNSPEC_LOONGSON_PCMPEQ 501)
224 (UNSPEC_LOONGSON_PCMPGT 502)
225 (UNSPEC_LOONGSON_PEXTR 503)
226 (UNSPEC_LOONGSON_PINSR_0 504)
227 (UNSPEC_LOONGSON_PINSR_1 505)
228 (UNSPEC_LOONGSON_PINSR_2 506)
229 (UNSPEC_LOONGSON_PINSR_3 507)
230 (UNSPEC_LOONGSON_PMADD 508)
231 (UNSPEC_LOONGSON_PMOVMSK 509)
232 (UNSPEC_LOONGSON_PMULHU 510)
233 (UNSPEC_LOONGSON_PMULH 511)
234 (UNSPEC_LOONGSON_PMULL 512)
235 (UNSPEC_LOONGSON_PMULU 513)
236 (UNSPEC_LOONGSON_PASUBUB 514)
237 (UNSPEC_LOONGSON_BIADD 515)
238 (UNSPEC_LOONGSON_PSADBH 516)
239 (UNSPEC_LOONGSON_PSHUFH 517)
240 (UNSPEC_LOONGSON_PUNPCKH 518)
241 (UNSPEC_LOONGSON_PUNPCKL 519)
242 (UNSPEC_LOONGSON_PADDD 520)
243 (UNSPEC_LOONGSON_PSUBD 521)
245 ;; Used in loongson2ef.md
246 (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
247 (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
248 (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
249 (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
251 (UNSPEC_MIPS_CACHE 600)
252 (UNSPEC_R10K_CACHE_BARRIER 601)
256 (include "predicates.md")
257 (include "constraints.md")
259 ;; ....................
263 ;; ....................
265 (define_attr "got" "unset,xgot_high,load"
266 (const_string "unset"))
268 ;; For jal instructions, this attribute is DIRECT when the target address
269 ;; is symbolic and INDIRECT when it is a register.
270 (define_attr "jal" "unset,direct,indirect"
271 (const_string "unset"))
273 ;; This attribute is YES if the instruction is a jal macro (not a
274 ;; real jal instruction).
276 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
277 ;; an instruction to restore $gp. Direct jals are also macros for
278 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
279 ;; the target address into a register.
280 (define_attr "jal_macro" "no,yes"
281 (cond [(eq_attr "jal" "direct")
282 (symbol_ref "TARGET_CALL_CLOBBERED_GP
283 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
284 (eq_attr "jal" "indirect")
285 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
286 (const_string "no")))
288 ;; Classification of moves, extensions and truncations. Most values
289 ;; are as for "type" (see below) but there are also the following
290 ;; move-specific values:
292 ;; constN move an N-constraint integer into a MIPS16 register
293 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
294 ;; to produce a sign-extended DEST, even if SRC is not
295 ;; properly sign-extended
296 ;; andi a single ANDI instruction
297 ;; loadpool move a constant into a MIPS16 register by loading it
299 ;; shift_shift a shift left followed by a shift right
300 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
302 ;; This attribute is used to determine the instruction's length and
303 ;; scheduling type. For doubleword moves, the attribute always describes
304 ;; the split instructions; in some cases, it is more appropriate for the
305 ;; scheduling type to be "multi" instead.
306 (define_attr "move_type"
307 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
308 const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
309 (const_string "unknown"))
311 ;; Main data type used by the insn
312 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
313 (const_string "unknown"))
315 ;; True if the main data type is twice the size of a word.
316 (define_attr "dword_mode" "no,yes"
317 (cond [(and (eq_attr "mode" "DI,DF")
318 (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
321 (and (eq_attr "mode" "TI,TF")
322 (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
323 (const_string "yes")]
324 (const_string "no")))
326 ;; Classification of each insn.
327 ;; branch conditional branch
328 ;; jump unconditional jump
329 ;; call unconditional call
330 ;; load load instruction(s)
331 ;; fpload floating point load
332 ;; fpidxload floating point indexed load
333 ;; store store instruction(s)
334 ;; fpstore floating point store
335 ;; fpidxstore floating point indexed store
336 ;; prefetch memory prefetch (register + offset)
337 ;; prefetchx memory indexed prefetch (register + register)
338 ;; condmove conditional moves
339 ;; mtc transfer to coprocessor
340 ;; mfc transfer from coprocessor
341 ;; mthilo transfer to hi/lo registers
342 ;; mfhilo transfer from hi/lo registers
343 ;; const load constant
344 ;; arith integer arithmetic instructions
345 ;; logical integer logical instructions
346 ;; shift integer shift instructions
347 ;; slt set less than instructions
348 ;; signext sign extend instructions
349 ;; clz the clz and clo instructions
350 ;; pop the pop instruction
351 ;; trap trap if instructions
352 ;; imul integer multiply 2 operands
353 ;; imul3 integer multiply 3 operands
354 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
355 ;; imadd integer multiply-add
356 ;; idiv integer divide 2 operands
357 ;; idiv3 integer divide 3 operands
358 ;; move integer register move ({,D}ADD{,U} with rt = 0)
359 ;; fmove floating point register move
360 ;; fadd floating point add/subtract
361 ;; fmul floating point multiply
362 ;; fmadd floating point multiply-add
363 ;; fdiv floating point divide
364 ;; frdiv floating point reciprocal divide
365 ;; frdiv1 floating point reciprocal divide step 1
366 ;; frdiv2 floating point reciprocal divide step 2
367 ;; fabs floating point absolute value
368 ;; fneg floating point negation
369 ;; fcmp floating point compare
370 ;; fcvt floating point convert
371 ;; fsqrt floating point square root
372 ;; frsqrt floating point reciprocal square root
373 ;; frsqrt1 floating point reciprocal square root step1
374 ;; frsqrt2 floating point reciprocal square root step2
375 ;; multi multiword sequence (or user asm statements)
377 ;; ghost an instruction that produces no real code
379 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
380 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
381 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
382 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
383 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
384 (cond [(eq_attr "jal" "!unset") (const_string "call")
385 (eq_attr "got" "load") (const_string "load")
387 ;; If a doubleword move uses these expensive instructions,
388 ;; it is usually better to schedule them in the same way
389 ;; as the singleword form, rather than as "multi".
390 (eq_attr "move_type" "load") (const_string "load")
391 (eq_attr "move_type" "fpload") (const_string "fpload")
392 (eq_attr "move_type" "store") (const_string "store")
393 (eq_attr "move_type" "fpstore") (const_string "fpstore")
394 (eq_attr "move_type" "mtc") (const_string "mtc")
395 (eq_attr "move_type" "mfc") (const_string "mfc")
396 (eq_attr "move_type" "mthilo") (const_string "mthilo")
397 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
399 ;; These types of move are always single insns.
400 (eq_attr "move_type" "fmove") (const_string "fmove")
401 (eq_attr "move_type" "loadpool") (const_string "load")
402 (eq_attr "move_type" "signext") (const_string "signext")
403 (eq_attr "move_type" "sll0") (const_string "shift")
404 (eq_attr "move_type" "andi") (const_string "logical")
406 ;; These types of move are always split.
407 (eq_attr "move_type" "constN,lui_movf,shift_shift")
408 (const_string "multi")
410 ;; These types of move are split for doubleword modes only.
411 (and (eq_attr "move_type" "move,const")
412 (eq_attr "dword_mode" "yes"))
413 (const_string "multi")
414 (eq_attr "move_type" "move") (const_string "move")
415 (eq_attr "move_type" "const") (const_string "const")]
416 (const_string "unknown")))
418 ;; Mode for conversion types (fcvt)
419 ;; I2S integer to float single (SI/DI to SF)
420 ;; I2D integer to float double (SI/DI to DF)
421 ;; S2I float to integer (SF to SI/DI)
422 ;; D2I float to integer (DF to SI/DI)
423 ;; D2S double to float single
424 ;; S2D float single to double
426 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
427 (const_string "unknown"))
429 ;; Is this an extended instruction in mips16 mode?
430 (define_attr "extended_mips16" "no,yes"
431 (if_then_else (ior (eq_attr "move_type" "sll0")
432 (eq_attr "type" "branch")
433 (eq_attr "jal" "direct"))
435 (const_string "no")))
437 ;; Length of instruction in bytes.
438 (define_attr "length" ""
439 (cond [(and (eq_attr "extended_mips16" "yes")
440 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
443 ;; Direct branch instructions have a range of [-0x40000,0x3fffc].
444 ;; If a branch is outside this range, we have a choice of two
445 ;; sequences. For PIC, an out-of-range branch like:
450 ;; becomes the equivalent of:
459 ;; where the load address can be up to three instructions long
462 ;; The non-PIC case is similar except that we use a direct
463 ;; jump instead of an la/jr pair. Since the target of this
464 ;; jump is an absolute 28-bit bit address (the other bits
465 ;; coming from the address of the delay slot) this form cannot
466 ;; cross a 256MB boundary. We could provide the option of
467 ;; using la/jr in this case too, but we do not do so at
470 ;; Note that this value does not account for the delay slot
471 ;; instruction, whose length is added separately. If the RTL
472 ;; pattern has no explicit delay slot, mips_adjust_insn_length
473 ;; will add the length of the implicit nop. The values for
474 ;; forward and backward branches will be different as well.
475 (eq_attr "type" "branch")
476 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
477 (le (minus (pc) (match_dup 1)) (const_int 131068)))
479 (ne (symbol_ref "flag_pic") (const_int 0))
483 ;; "Ghost" instructions occupy no space.
484 (eq_attr "type" "ghost")
487 (eq_attr "got" "load")
488 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
491 (eq_attr "got" "xgot_high")
494 ;; In general, constant-pool loads are extended instructions.
495 (eq_attr "move_type" "loadpool")
498 ;; LUI_MOVFs are decomposed into two separate instructions.
499 (eq_attr "move_type" "lui_movf")
502 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
503 ;; They are extended instructions on MIPS16 targets.
504 (eq_attr "move_type" "shift_shift")
505 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
509 ;; Check for doubleword moves that are decomposed into two
511 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
512 (eq_attr "dword_mode" "yes"))
515 ;; Doubleword CONST{,N} moves are split into two word
517 (and (eq_attr "move_type" "const,constN")
518 (eq_attr "dword_mode" "yes"))
519 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
521 ;; Otherwise, constants, loads and stores are handled by external
523 (eq_attr "move_type" "const,constN")
524 (symbol_ref "mips_const_insns (operands[1]) * 4")
525 (eq_attr "move_type" "load,fpload")
526 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
527 (eq_attr "move_type" "store,fpstore")
528 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
530 ;; In the worst case, a call macro will take 8 instructions:
532 ;; lui $25,%call_hi(FOO)
534 ;; lw $25,%call_lo(FOO)($25)
540 (eq_attr "jal_macro" "yes")
543 ;; Various VR4120 errata require a nop to be inserted after a macc
544 ;; instruction. The assembler does this for us, so account for
545 ;; the worst-case length here.
546 (and (eq_attr "type" "imadd")
547 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
550 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
551 ;; the result of the second one is missed. The assembler should work
552 ;; around this by inserting a nop after the first dmult.
553 (and (eq_attr "type" "imul,imul3")
554 (and (eq_attr "mode" "DI")
555 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
558 (eq_attr "type" "idiv,idiv3")
559 (symbol_ref "mips_idiv_insns () * 4")
562 ;; Attribute describing the processor. This attribute must match exactly
563 ;; with the processor_type enumeration in mips.h.
565 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
566 (const (symbol_ref "mips_tune")))
568 ;; The type of hardware hazard associated with this instruction.
569 ;; DELAY means that the next instruction cannot read the result
570 ;; of this one. HILO means that the next two instructions cannot
571 ;; write to HI or LO.
572 (define_attr "hazard" "none,delay,hilo"
573 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
574 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
575 (const_string "delay")
577 (and (eq_attr "type" "mfc,mtc")
578 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
579 (const_string "delay")
581 (and (eq_attr "type" "fcmp")
582 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
583 (const_string "delay")
585 ;; The r4000 multiplication patterns include an mflo instruction.
586 (and (eq_attr "type" "imul")
587 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
588 (const_string "hilo")
590 (and (eq_attr "type" "mfhilo")
591 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
592 (const_string "hilo")]
593 (const_string "none")))
595 ;; Is it a single instruction?
596 (define_attr "single_insn" "no,yes"
597 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
599 ;; Can the instruction be put into a delay slot?
600 (define_attr "can_delay" "no,yes"
601 (if_then_else (and (eq_attr "type" "!branch,call,jump")
602 (and (eq_attr "hazard" "none")
603 (eq_attr "single_insn" "yes")))
605 (const_string "no")))
607 ;; Attribute defining whether or not we can use the branch-likely
609 (define_attr "branch_likely" "no,yes"
610 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
612 (const_string "no")))
614 ;; True if an instruction might assign to hi or lo when reloaded.
615 ;; This is used by the TUNE_MACC_CHAINS code.
616 (define_attr "may_clobber_hilo" "no,yes"
617 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
619 (const_string "no")))
621 ;; Describe a user's asm statement.
622 (define_asm_attributes
623 [(set_attr "type" "multi")
624 (set_attr "can_delay" "no")])
626 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
627 ;; from the same template.
628 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
630 ;; A copy of GPR that can be used when a pattern has two independent
632 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
634 ;; This mode iterator allows :HILO to be used as the mode of the
635 ;; concatenated HI and LO registers.
636 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
638 ;; This mode iterator allows :P to be used for patterns that operate on
639 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
640 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
642 ;; This mode iterator allows :MOVECC to be used anywhere that a
643 ;; conditional-move-type condition is needed.
644 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
645 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
647 ;; 32-bit integer moves for which we provide move patterns.
648 (define_mode_iterator IMOVE32
657 (V4UQQ "TARGET_DSP")])
659 ;; 64-bit modes for which we provide move patterns.
660 (define_mode_iterator MOVE64
662 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
663 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
664 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
665 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
667 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
668 (define_mode_iterator MOVE128 [TI TF])
670 ;; This mode iterator allows the QI and HI extension patterns to be
671 ;; defined from the same template.
672 (define_mode_iterator SHORT [QI HI])
674 ;; Likewise the 64-bit truncate-and-shift patterns.
675 (define_mode_iterator SUBDI [QI HI SI])
677 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
678 ;; floating-point mode is allowed.
679 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
680 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
681 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
683 ;; Like ANYF, but only applies to scalar modes.
684 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
685 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
687 ;; A floating-point mode for which moves involving FPRs may need to be split.
688 (define_mode_iterator SPLITF
689 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
690 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
691 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
692 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
693 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
694 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
695 (TF "TARGET_64BIT && TARGET_FLOAT64")])
697 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
698 ;; 32-bit version and "dsubu" in the 64-bit version.
699 (define_mode_attr d [(SI "") (DI "d")
700 (QQ "") (HQ "") (SQ "") (DQ "d")
701 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
702 (HA "") (SA "") (DA "d")
703 (UHA "") (USA "") (UDA "d")])
705 ;; Same as d but upper-case.
706 (define_mode_attr D [(SI "") (DI "D")
707 (QQ "") (HQ "") (SQ "") (DQ "D")
708 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
709 (HA "") (SA "") (DA "D")
710 (UHA "") (USA "") (UDA "D")])
712 ;; This attribute gives the length suffix for a sign- or zero-extension
714 (define_mode_attr size [(QI "b") (HI "h")])
716 ;; This attributes gives the mode mask of a SHORT.
717 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
719 ;; Mode attributes for GPR loads and stores.
720 (define_mode_attr load [(SI "lw") (DI "ld")])
721 (define_mode_attr store [(SI "sw") (DI "sd")])
723 ;; Similarly for MIPS IV indexed FPR loads and stores.
724 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
725 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
727 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
728 ;; are different. Some forms of unextended addiu have an 8-bit immediate
729 ;; field but the equivalent daddiu has only a 5-bit field.
730 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
732 ;; This attribute gives the best constraint to use for registers of
734 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
736 ;; This attribute gives the format suffix for floating-point operations.
737 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
739 ;; This attribute gives the upper-case mode name for one unit of a
740 ;; floating-point mode.
741 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
743 ;; This attribute gives the integer mode that has the same size as a
745 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
746 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
747 (HA "HI") (SA "SI") (DA "DI")
748 (UHA "HI") (USA "SI") (UDA "DI")
749 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
750 (V2HQ "SI") (V2HA "SI")])
752 ;; This attribute gives the integer mode that has half the size of
753 ;; the controlling mode.
754 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
755 (V2SI "SI") (V4HI "SI") (V8QI "SI")
758 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
760 ;; In certain cases, div.s and div.ps may have a rounding error
761 ;; and/or wrong inexact flag.
763 ;; Therefore, we only allow div.s if not working around SB-1 rev2
764 ;; errata or if a slight loss of precision is OK.
765 (define_mode_attr divide_condition
766 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
767 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
769 ;; This attribute gives the conditions under which SQRT.fmt instructions
771 (define_mode_attr sqrt_condition
772 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
774 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
775 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
776 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
777 ;; so for safety's sake, we apply this restriction to all targets.
778 (define_mode_attr recip_condition
780 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
781 (V2SF "TARGET_SB1")])
783 ;; This code iterator allows all branch instructions to be generated from
784 ;; a single define_expand template.
785 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
786 eq ne gt ge lt le gtu geu ltu leu])
788 ;; This code iterator allows signed and unsigned widening multiplications
789 ;; to use the same template.
790 (define_code_iterator any_extend [sign_extend zero_extend])
792 ;; This code iterator allows the two right shift instructions to be
793 ;; generated from the same template.
794 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
796 ;; This code iterator allows the three shift instructions to be generated
797 ;; from the same template.
798 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
800 ;; This code iterator allows unsigned and signed division to be generated
801 ;; from the same template.
802 (define_code_iterator any_div [div udiv])
804 ;; This code iterator allows unsigned and signed modulus to be generated
805 ;; from the same template.
806 (define_code_iterator any_mod [mod umod])
808 ;; This code iterator allows all native floating-point comparisons to be
809 ;; generated from the same template.
810 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
812 ;; This code iterator is used for comparisons that can be implemented
813 ;; by swapping the operands.
814 (define_code_iterator swapped_fcond [ge gt unge ungt])
816 ;; Equality operators.
817 (define_code_iterator equality_op [eq ne])
819 ;; These code iterators allow the signed and unsigned scc operations to use
820 ;; the same template.
821 (define_code_iterator any_gt [gt gtu])
822 (define_code_iterator any_ge [ge geu])
823 (define_code_iterator any_lt [lt ltu])
824 (define_code_iterator any_le [le leu])
826 ;; <u> expands to an empty string when doing a signed operation and
827 ;; "u" when doing an unsigned operation.
828 (define_code_attr u [(sign_extend "") (zero_extend "u")
836 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
837 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
839 ;; <optab> expands to the name of the optab for a particular code.
840 (define_code_attr optab [(ashift "ashl")
849 ;; <insn> expands to the name of the insn that implements a particular code.
850 (define_code_attr insn [(ashift "sll")
859 ;; <immediate_insn> expands to the name of the insn that implements
860 ;; a particular code to operate on immediate values.
861 (define_code_attr immediate_insn [(ior "ori")
865 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
866 (define_code_attr fcond [(unordered "un")
874 ;; Similar, but for swapped conditions.
875 (define_code_attr swapped_fcond [(ge "le")
880 ;; The value of the bit when the branch is taken for branch_bit patterns.
881 ;; Comparison is always against zero so this depends on the operator.
882 (define_code_attr bbv [(eq "0") (ne "1")])
884 ;; This is the inverse value of bbv.
885 (define_code_attr bbinv [(eq "1") (ne "0")])
887 ;; .........................
889 ;; Branch, call and jump delay slots
891 ;; .........................
893 (define_delay (and (eq_attr "type" "branch")
894 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
895 (eq_attr "branch_likely" "yes"))
896 [(eq_attr "can_delay" "yes")
898 (eq_attr "can_delay" "yes")])
900 ;; Branches that don't have likely variants do not annul on false.
901 (define_delay (and (eq_attr "type" "branch")
902 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
903 (eq_attr "branch_likely" "no"))
904 [(eq_attr "can_delay" "yes")
908 (define_delay (eq_attr "type" "jump")
909 [(eq_attr "can_delay" "yes")
913 (define_delay (and (eq_attr "type" "call")
914 (eq_attr "jal_macro" "no"))
915 [(eq_attr "can_delay" "yes")
919 ;; Pipeline descriptions.
921 ;; generic.md provides a fallback for processors without a specific
922 ;; pipeline description. It is derived from the old define_function_unit
923 ;; version and uses the "alu" and "imuldiv" units declared below.
925 ;; Some of the processor-specific files are also derived from old
926 ;; define_function_unit descriptions and simply override the parts of
927 ;; generic.md that don't apply. The other processor-specific files
928 ;; are self-contained.
929 (define_automaton "alu,imuldiv")
931 (define_cpu_unit "alu" "alu")
932 (define_cpu_unit "imuldiv" "imuldiv")
934 ;; Ghost instructions produce no real code and introduce no hazards.
935 ;; They exist purely to express an effect on dataflow.
936 (define_insn_reservation "ghost" 0
937 (eq_attr "type" "ghost")
958 (include "loongson2ef.md")
959 (include "octeon.md")
963 (include "generic.md")
966 ;; ....................
970 ;; ....................
974 [(trap_if (const_int 1) (const_int 0))]
977 if (ISA_HAS_COND_TRAP)
979 else if (TARGET_MIPS16)
984 [(set_attr "type" "trap")])
986 (define_expand "conditional_trap"
987 [(trap_if (match_operator 0 "comparison_operator"
988 [(match_dup 2) (match_dup 3)])
989 (match_operand 1 "const_int_operand"))]
992 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
993 && operands[1] == const0_rtx)
995 mips_expand_conditional_trap (GET_CODE (operands[0]));
1001 (define_insn "*conditional_trap<mode>"
1002 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1003 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1004 (match_operand:GPR 2 "arith_operand" "dI")])
1008 [(set_attr "type" "trap")])
1011 ;; ....................
1015 ;; ....................
1018 (define_insn "add<mode>3"
1019 [(set (match_operand:ANYF 0 "register_operand" "=f")
1020 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1021 (match_operand:ANYF 2 "register_operand" "f")))]
1023 "add.<fmt>\t%0,%1,%2"
1024 [(set_attr "type" "fadd")
1025 (set_attr "mode" "<UNITMODE>")])
1027 (define_expand "add<mode>3"
1028 [(set (match_operand:GPR 0 "register_operand")
1029 (plus:GPR (match_operand:GPR 1 "register_operand")
1030 (match_operand:GPR 2 "arith_operand")))]
1033 (define_insn "*add<mode>3"
1034 [(set (match_operand:GPR 0 "register_operand" "=d,d")
1035 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
1036 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1041 [(set_attr "type" "arith")
1042 (set_attr "mode" "<MODE>")])
1044 (define_insn "*add<mode>3_mips16"
1045 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1046 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1047 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1055 [(set_attr "type" "arith")
1056 (set_attr "mode" "<MODE>")
1057 (set_attr_alternative "length"
1058 [(if_then_else (match_operand 2 "m16_simm8_8")
1061 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1064 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1067 (if_then_else (match_operand 2 "m16_simm4_1")
1072 ;; On the mips16, we can sometimes split an add of a constant which is
1073 ;; a 4 byte instruction into two adds which are both 2 byte
1074 ;; instructions. There are two cases: one where we are adding a
1075 ;; constant plus a register to another register, and one where we are
1076 ;; simply adding a constant to a register.
1079 [(set (match_operand:SI 0 "d_operand")
1080 (plus:SI (match_dup 0)
1081 (match_operand:SI 1 "const_int_operand")))]
1082 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1083 && ((INTVAL (operands[1]) > 0x7f
1084 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1085 || (INTVAL (operands[1]) < - 0x80
1086 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1087 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1088 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1090 HOST_WIDE_INT val = INTVAL (operands[1]);
1094 operands[1] = GEN_INT (0x7f);
1095 operands[2] = GEN_INT (val - 0x7f);
1099 operands[1] = GEN_INT (- 0x80);
1100 operands[2] = GEN_INT (val + 0x80);
1105 [(set (match_operand:SI 0 "d_operand")
1106 (plus:SI (match_operand:SI 1 "d_operand")
1107 (match_operand:SI 2 "const_int_operand")))]
1108 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1109 && REGNO (operands[0]) != REGNO (operands[1])
1110 && ((INTVAL (operands[2]) > 0x7
1111 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1112 || (INTVAL (operands[2]) < - 0x8
1113 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1114 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1115 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1117 HOST_WIDE_INT val = INTVAL (operands[2]);
1121 operands[2] = GEN_INT (0x7);
1122 operands[3] = GEN_INT (val - 0x7);
1126 operands[2] = GEN_INT (- 0x8);
1127 operands[3] = GEN_INT (val + 0x8);
1132 [(set (match_operand:DI 0 "d_operand")
1133 (plus:DI (match_dup 0)
1134 (match_operand:DI 1 "const_int_operand")))]
1135 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1136 && ((INTVAL (operands[1]) > 0xf
1137 && INTVAL (operands[1]) <= 0xf + 0xf)
1138 || (INTVAL (operands[1]) < - 0x10
1139 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1140 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1141 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1143 HOST_WIDE_INT val = INTVAL (operands[1]);
1147 operands[1] = GEN_INT (0xf);
1148 operands[2] = GEN_INT (val - 0xf);
1152 operands[1] = GEN_INT (- 0x10);
1153 operands[2] = GEN_INT (val + 0x10);
1158 [(set (match_operand:DI 0 "d_operand")
1159 (plus:DI (match_operand:DI 1 "d_operand")
1160 (match_operand:DI 2 "const_int_operand")))]
1161 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1162 && REGNO (operands[0]) != REGNO (operands[1])
1163 && ((INTVAL (operands[2]) > 0x7
1164 && INTVAL (operands[2]) <= 0x7 + 0xf)
1165 || (INTVAL (operands[2]) < - 0x8
1166 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1167 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1168 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1170 HOST_WIDE_INT val = INTVAL (operands[2]);
1174 operands[2] = GEN_INT (0x7);
1175 operands[3] = GEN_INT (val - 0x7);
1179 operands[2] = GEN_INT (- 0x8);
1180 operands[3] = GEN_INT (val + 0x8);
1184 (define_insn "*addsi3_extended"
1185 [(set (match_operand:DI 0 "register_operand" "=d,d")
1187 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1188 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1189 "TARGET_64BIT && !TARGET_MIPS16"
1193 [(set_attr "type" "arith")
1194 (set_attr "mode" "SI")])
1196 ;; Split this insn so that the addiu splitters can have a crack at it.
1197 ;; Use a conservative length estimate until the split.
1198 (define_insn_and_split "*addsi3_extended_mips16"
1199 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1201 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1202 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1203 "TARGET_64BIT && TARGET_MIPS16"
1205 "&& reload_completed"
1206 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1207 { operands[3] = gen_lowpart (SImode, operands[0]); }
1208 [(set_attr "type" "arith")
1209 (set_attr "mode" "SI")
1210 (set_attr "extended_mips16" "yes")])
1212 ;; Combiner patterns for unsigned byte-add.
1214 (define_insn "*baddu_si_eb"
1215 [(set (match_operand:SI 0 "register_operand" "=d")
1218 (plus:SI (match_operand:SI 1 "register_operand" "d")
1219 (match_operand:SI 2 "register_operand" "d")) 3)))]
1220 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1222 [(set_attr "type" "arith")])
1224 (define_insn "*baddu_si_el"
1225 [(set (match_operand:SI 0 "register_operand" "=d")
1228 (plus:SI (match_operand:SI 1 "register_operand" "d")
1229 (match_operand:SI 2 "register_operand" "d")) 0)))]
1230 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1232 [(set_attr "type" "arith")])
1234 (define_insn "*baddu_di<mode>"
1235 [(set (match_operand:GPR 0 "register_operand" "=d")
1238 (plus:DI (match_operand:DI 1 "register_operand" "d")
1239 (match_operand:DI 2 "register_operand" "d")))))]
1240 "ISA_HAS_BADDU && TARGET_64BIT"
1242 [(set_attr "type" "arith")])
1245 ;; ....................
1249 ;; ....................
1252 (define_insn "sub<mode>3"
1253 [(set (match_operand:ANYF 0 "register_operand" "=f")
1254 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1255 (match_operand:ANYF 2 "register_operand" "f")))]
1257 "sub.<fmt>\t%0,%1,%2"
1258 [(set_attr "type" "fadd")
1259 (set_attr "mode" "<UNITMODE>")])
1261 (define_insn "sub<mode>3"
1262 [(set (match_operand:GPR 0 "register_operand" "=d")
1263 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1264 (match_operand:GPR 2 "register_operand" "d")))]
1267 [(set_attr "type" "arith")
1268 (set_attr "mode" "<MODE>")])
1270 (define_insn "*subsi3_extended"
1271 [(set (match_operand:DI 0 "register_operand" "=d")
1273 (minus:SI (match_operand:SI 1 "register_operand" "d")
1274 (match_operand:SI 2 "register_operand" "d"))))]
1277 [(set_attr "type" "arith")
1278 (set_attr "mode" "DI")])
1281 ;; ....................
1285 ;; ....................
1288 (define_expand "mul<mode>3"
1289 [(set (match_operand:SCALARF 0 "register_operand")
1290 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1291 (match_operand:SCALARF 2 "register_operand")))]
1295 (define_insn "*mul<mode>3"
1296 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1297 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1298 (match_operand:SCALARF 2 "register_operand" "f")))]
1299 "!TARGET_4300_MUL_FIX"
1300 "mul.<fmt>\t%0,%1,%2"
1301 [(set_attr "type" "fmul")
1302 (set_attr "mode" "<MODE>")])
1304 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1305 ;; operands may corrupt immediately following multiplies. This is a
1306 ;; simple fix to insert NOPs.
1308 (define_insn "*mul<mode>3_r4300"
1309 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1310 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1311 (match_operand:SCALARF 2 "register_operand" "f")))]
1312 "TARGET_4300_MUL_FIX"
1313 "mul.<fmt>\t%0,%1,%2\;nop"
1314 [(set_attr "type" "fmul")
1315 (set_attr "mode" "<MODE>")
1316 (set_attr "length" "8")])
1318 (define_insn "mulv2sf3"
1319 [(set (match_operand:V2SF 0 "register_operand" "=f")
1320 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1321 (match_operand:V2SF 2 "register_operand" "f")))]
1322 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1324 [(set_attr "type" "fmul")
1325 (set_attr "mode" "SF")])
1327 ;; The original R4000 has a cpu bug. If a double-word or a variable
1328 ;; shift executes while an integer multiplication is in progress, the
1329 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1330 ;; with the mult on the R4000.
1332 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1333 ;; (also valid for MIPS R4000MC processors):
1335 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1336 ;; this errata description.
1337 ;; The following code sequence causes the R4000 to incorrectly
1338 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1339 ;; instruction. If the dsra32 instruction is executed during an
1340 ;; integer multiply, the dsra32 will only shift by the amount in
1341 ;; specified in the instruction rather than the amount plus 32
1343 ;; instruction 1: mult rs,rt integer multiply
1344 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1345 ;; right arithmetic + 32
1346 ;; Workaround: A dsra32 instruction placed after an integer
1347 ;; multiply should not be one of the 11 instructions after the
1348 ;; multiply instruction."
1352 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1353 ;; the following description.
1354 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1355 ;; 64-bit versions) may produce incorrect results under the
1356 ;; following conditions:
1357 ;; 1) An integer multiply is currently executing
1358 ;; 2) These types of shift instructions are executed immediately
1359 ;; following an integer divide instruction.
1361 ;; 1) Make sure no integer multiply is running wihen these
1362 ;; instruction are executed. If this cannot be predicted at
1363 ;; compile time, then insert a "mfhi" to R0 instruction
1364 ;; immediately after the integer multiply instruction. This
1365 ;; will cause the integer multiply to complete before the shift
1367 ;; 2) Separate integer divide and these two classes of shift
1368 ;; instructions by another instruction or a noop."
1370 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1373 (define_expand "mul<mode>3"
1374 [(set (match_operand:GPR 0 "register_operand")
1375 (mult:GPR (match_operand:GPR 1 "register_operand")
1376 (match_operand:GPR 2 "register_operand")))]
1379 if (TARGET_LOONGSON_2EF)
1380 emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
1382 else if (ISA_HAS_<D>MUL3)
1383 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1384 else if (TARGET_FIX_R4000)
1385 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1388 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1392 (define_insn "mul<mode>3_mul3_ls2ef"
1393 [(set (match_operand:GPR 0 "register_operand" "=d")
1394 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1395 (match_operand:GPR 2 "register_operand" "d")))]
1396 "TARGET_LOONGSON_2EF"
1397 "<d>multu.g\t%0,%1,%2"
1398 [(set_attr "type" "imul3nc")
1399 (set_attr "mode" "<MODE>")])
1401 (define_insn "mul<mode>3_mul3"
1402 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1403 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1404 (match_operand:GPR 2 "register_operand" "d,d")))
1405 (clobber (match_scratch:GPR 3 "=l,X"))]
1408 if (which_alternative == 1)
1409 return "<d>mult\t%1,%2";
1410 if (<MODE>mode == SImode && TARGET_MIPS3900)
1411 return "mult\t%0,%1,%2";
1412 return "<d>mul\t%0,%1,%2";
1414 [(set_attr "type" "imul3,imul")
1415 (set_attr "mode" "<MODE>")])
1417 ;; If a register gets allocated to LO, and we spill to memory, the reload
1418 ;; will include a move from LO to a GPR. Merge it into the multiplication
1419 ;; if it can set the GPR directly.
1422 ;; Operand 1: GPR (1st multiplication operand)
1423 ;; Operand 2: GPR (2nd multiplication operand)
1424 ;; Operand 3: GPR (destination)
1427 [(set (match_operand:SI 0 "lo_operand")
1428 (mult:SI (match_operand:SI 1 "d_operand")
1429 (match_operand:SI 2 "d_operand")))
1430 (clobber (scratch:SI))])
1431 (set (match_operand:SI 3 "d_operand")
1433 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1436 (mult:SI (match_dup 1)
1438 (clobber (match_dup 0))])])
1440 (define_insn "mul<mode>3_internal"
1441 [(set (match_operand:GPR 0 "register_operand" "=l")
1442 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1443 (match_operand:GPR 2 "register_operand" "d")))]
1446 [(set_attr "type" "imul")
1447 (set_attr "mode" "<MODE>")])
1449 (define_insn "mul<mode>3_r4000"
1450 [(set (match_operand:GPR 0 "register_operand" "=d")
1451 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1452 (match_operand:GPR 2 "register_operand" "d")))
1453 (clobber (match_scratch:GPR 3 "=l"))]
1455 "<d>mult\t%1,%2\;mflo\t%0"
1456 [(set_attr "type" "imul")
1457 (set_attr "mode" "<MODE>")
1458 (set_attr "length" "8")])
1460 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1461 ;; of "mult; mflo". They have the same latency, but the first form gives
1462 ;; us an extra cycle to compute the operands.
1465 ;; Operand 1: GPR (1st multiplication operand)
1466 ;; Operand 2: GPR (2nd multiplication operand)
1467 ;; Operand 3: GPR (destination)
1469 [(set (match_operand:SI 0 "lo_operand")
1470 (mult:SI (match_operand:SI 1 "d_operand")
1471 (match_operand:SI 2 "d_operand")))
1472 (set (match_operand:SI 3 "d_operand")
1474 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1479 (plus:SI (mult:SI (match_dup 1)
1483 (plus:SI (mult:SI (match_dup 1)
1487 ;; Multiply-accumulate patterns
1489 ;; This pattern is first matched by combine, which tries to use the
1490 ;; pattern wherever it can. We don't know until later whether it
1491 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1492 ;; so we need to keep both options open.
1494 ;; The second alternative has a "?" marker because it is generally
1495 ;; one instruction more costly than the first alternative. This "?"
1496 ;; marker is enough to convey the relative costs to the register
1499 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1500 ;; reloads of the other operands, even though operands 4 and 5 need no
1501 ;; copy instructions. Reload therefore thinks that the second alternative
1502 ;; is two reloads more costly than the first. We add "*?*?" to the first
1503 ;; alternative as a counterweight.
1504 (define_insn "*mul_acc_si"
1505 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1506 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1507 (match_operand:SI 2 "register_operand" "d,d"))
1508 (match_operand:SI 3 "register_operand" "0,d")))
1509 (clobber (match_scratch:SI 4 "=X,l"))
1510 (clobber (match_scratch:SI 5 "=X,&d"))]
1511 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1515 [(set_attr "type" "imadd")
1516 (set_attr "mode" "SI")
1517 (set_attr "length" "4,8")])
1519 ;; The same idea applies here. The middle alternative needs one less
1520 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1521 (define_insn "*mul_acc_si_r3900"
1522 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1523 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1524 (match_operand:SI 2 "register_operand" "d,d,d"))
1525 (match_operand:SI 3 "register_operand" "0,l,d")))
1526 (clobber (match_scratch:SI 4 "=X,3,l"))
1527 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1528 "TARGET_MIPS3900 && !TARGET_MIPS16"
1533 [(set_attr "type" "imadd")
1534 (set_attr "mode" "SI")
1535 (set_attr "length" "4,4,8")])
1537 ;; Split *mul_acc_si if both the source and destination accumulator
1540 [(set (match_operand:SI 0 "d_operand")
1541 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1542 (match_operand:SI 2 "d_operand"))
1543 (match_operand:SI 3 "d_operand")))
1544 (clobber (match_operand:SI 4 "lo_operand"))
1545 (clobber (match_operand:SI 5 "d_operand"))]
1547 [(parallel [(set (match_dup 5)
1548 (mult:SI (match_dup 1) (match_dup 2)))
1549 (clobber (match_dup 4))])
1550 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1553 (define_insn "*macc"
1554 [(set (match_operand:SI 0 "register_operand" "=l,d")
1555 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1556 (match_operand:SI 2 "register_operand" "d,d"))
1557 (match_operand:SI 3 "register_operand" "0,l")))
1558 (clobber (match_scratch:SI 4 "=X,3"))]
1561 if (which_alternative == 1)
1562 return "macc\t%0,%1,%2";
1563 else if (TARGET_MIPS5500)
1564 return "madd\t%1,%2";
1566 /* The VR4130 assumes that there is a two-cycle latency between a macc
1567 that "writes" to $0 and an instruction that reads from it. We avoid
1568 this by assigning to $1 instead. */
1569 return "%[macc\t%@,%1,%2%]";
1571 [(set_attr "type" "imadd")
1572 (set_attr "mode" "SI")])
1574 (define_insn "*msac"
1575 [(set (match_operand:SI 0 "register_operand" "=l,d")
1576 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1577 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1578 (match_operand:SI 3 "register_operand" "d,d"))))
1579 (clobber (match_scratch:SI 4 "=X,1"))]
1582 if (which_alternative == 1)
1583 return "msac\t%0,%2,%3";
1584 else if (TARGET_MIPS5500)
1585 return "msub\t%2,%3";
1587 return "msac\t$0,%2,%3";
1589 [(set_attr "type" "imadd")
1590 (set_attr "mode" "SI")])
1592 ;; An msac-like instruction implemented using negation and a macc.
1593 (define_insn_and_split "*msac_using_macc"
1594 [(set (match_operand:SI 0 "register_operand" "=l,d")
1595 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1596 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1597 (match_operand:SI 3 "register_operand" "d,d"))))
1598 (clobber (match_scratch:SI 4 "=X,1"))
1599 (clobber (match_scratch:SI 5 "=d,d"))]
1600 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1602 "&& reload_completed"
1604 (neg:SI (match_dup 3)))
1607 (plus:SI (mult:SI (match_dup 2)
1610 (clobber (match_dup 4))])]
1612 [(set_attr "type" "imadd")
1613 (set_attr "length" "8")])
1615 ;; Patterns generated by the define_peephole2 below.
1617 (define_insn "*macc2"
1618 [(set (match_operand:SI 0 "register_operand" "=l")
1619 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1620 (match_operand:SI 2 "register_operand" "d"))
1622 (set (match_operand:SI 3 "register_operand" "=d")
1623 (plus:SI (mult:SI (match_dup 1)
1626 "ISA_HAS_MACC && reload_completed"
1628 [(set_attr "type" "imadd")
1629 (set_attr "mode" "SI")])
1631 (define_insn "*msac2"
1632 [(set (match_operand:SI 0 "register_operand" "=l")
1633 (minus:SI (match_dup 0)
1634 (mult:SI (match_operand:SI 1 "register_operand" "d")
1635 (match_operand:SI 2 "register_operand" "d"))))
1636 (set (match_operand:SI 3 "register_operand" "=d")
1637 (minus:SI (match_dup 0)
1638 (mult:SI (match_dup 1)
1640 "ISA_HAS_MSAC && reload_completed"
1642 [(set_attr "type" "imadd")
1643 (set_attr "mode" "SI")])
1645 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1649 ;; Operand 1: macc/msac
1650 ;; Operand 2: GPR (destination)
1653 [(set (match_operand:SI 0 "lo_operand")
1654 (match_operand:SI 1 "macc_msac_operand"))
1655 (clobber (scratch:SI))])
1656 (set (match_operand:SI 2 "d_operand")
1659 [(parallel [(set (match_dup 0)
1664 ;; When we have a three-address multiplication instruction, it should
1665 ;; be faster to do a separate multiply and add, rather than moving
1666 ;; something into LO in order to use a macc instruction.
1668 ;; This peephole needs a scratch register to cater for the case when one
1669 ;; of the multiplication operands is the same as the destination.
1671 ;; Operand 0: GPR (scratch)
1673 ;; Operand 2: GPR (addend)
1674 ;; Operand 3: GPR (destination)
1675 ;; Operand 4: macc/msac
1676 ;; Operand 5: new multiplication
1677 ;; Operand 6: new addition/subtraction
1679 [(match_scratch:SI 0 "d")
1680 (set (match_operand:SI 1 "lo_operand")
1681 (match_operand:SI 2 "d_operand"))
1684 [(set (match_operand:SI 3 "d_operand")
1685 (match_operand:SI 4 "macc_msac_operand"))
1686 (clobber (match_dup 1))])]
1687 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1688 [(parallel [(set (match_dup 0)
1690 (clobber (match_dup 1))])
1694 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1695 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1696 operands[2], operands[0]);
1699 ;; Same as above, except LO is the initial target of the macc.
1701 ;; Operand 0: GPR (scratch)
1703 ;; Operand 2: GPR (addend)
1704 ;; Operand 3: macc/msac
1705 ;; Operand 4: GPR (destination)
1706 ;; Operand 5: new multiplication
1707 ;; Operand 6: new addition/subtraction
1709 [(match_scratch:SI 0 "d")
1710 (set (match_operand:SI 1 "lo_operand")
1711 (match_operand:SI 2 "d_operand"))
1715 (match_operand:SI 3 "macc_msac_operand"))
1716 (clobber (scratch:SI))])
1718 (set (match_operand:SI 4 "d_operand")
1720 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1721 [(parallel [(set (match_dup 0)
1723 (clobber (match_dup 1))])
1727 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1728 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1729 operands[2], operands[0]);
1732 ;; See the comment above *mul_add_si for details.
1733 (define_insn "*mul_sub_si"
1734 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1735 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1736 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1737 (match_operand:SI 3 "register_operand" "d,d"))))
1738 (clobber (match_scratch:SI 4 "=X,l"))
1739 (clobber (match_scratch:SI 5 "=X,&d"))]
1740 "GENERATE_MADD_MSUB"
1744 [(set_attr "type" "imadd")
1745 (set_attr "mode" "SI")
1746 (set_attr "length" "4,8")])
1748 ;; Split *mul_sub_si if both the source and destination accumulator
1751 [(set (match_operand:SI 0 "d_operand")
1752 (minus:SI (match_operand:SI 1 "d_operand")
1753 (mult:SI (match_operand:SI 2 "d_operand")
1754 (match_operand:SI 3 "d_operand"))))
1755 (clobber (match_operand:SI 4 "lo_operand"))
1756 (clobber (match_operand:SI 5 "d_operand"))]
1758 [(parallel [(set (match_dup 5)
1759 (mult:SI (match_dup 2) (match_dup 3)))
1760 (clobber (match_dup 4))])
1761 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1764 (define_insn "*muls"
1765 [(set (match_operand:SI 0 "register_operand" "=l,d")
1766 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1767 (match_operand:SI 2 "register_operand" "d,d"))))
1768 (clobber (match_scratch:SI 3 "=X,l"))]
1773 [(set_attr "type" "imul,imul3")
1774 (set_attr "mode" "SI")])
1776 (define_expand "<u>mulsidi3"
1777 [(set (match_operand:DI 0 "register_operand")
1778 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1779 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1780 "!TARGET_64BIT || !TARGET_FIX_R4000"
1783 emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
1784 else if (TARGET_FIX_R4000)
1785 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1788 emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
1792 (define_insn "<u>mulsidi3_32bit"
1793 [(set (match_operand:DI 0 "register_operand" "=x")
1794 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1795 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1796 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1798 [(set_attr "type" "imul")
1799 (set_attr "mode" "SI")])
1801 (define_insn "<u>mulsidi3_32bit_r4000"
1802 [(set (match_operand:DI 0 "register_operand" "=d")
1803 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1804 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1805 (clobber (match_scratch:DI 3 "=x"))]
1806 "!TARGET_64BIT && TARGET_FIX_R4000"
1807 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1808 [(set_attr "type" "imul")
1809 (set_attr "mode" "SI")
1810 (set_attr "length" "12")])
1812 (define_insn_and_split "<u>mulsidi3_64bit"
1813 [(set (match_operand:DI 0 "register_operand" "=d")
1814 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1815 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1816 (clobber (match_scratch:TI 3 "=x"))
1817 (clobber (match_scratch:DI 4 "=d"))]
1818 "TARGET_64BIT && !TARGET_FIX_R4000"
1820 "&& reload_completed"
1822 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1823 (any_extend:DI (match_dup 2)))]
1826 ;; OP4 <- LO, OP0 <- HI
1827 (set (match_dup 4) (match_dup 5))
1828 (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1832 (ashift:DI (match_dup 4)
1835 (lshiftrt:DI (match_dup 4)
1838 ;; Shift OP0 into place.
1840 (ashift:DI (match_dup 0)
1843 ;; OR the two halves together
1845 (ior:DI (match_dup 0)
1847 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
1848 [(set_attr "type" "imul")
1849 (set_attr "mode" "SI")
1850 (set_attr "length" "24")])
1852 (define_insn "<u>mulsidi3_64bit_hilo"
1853 [(set (match_operand:TI 0 "register_operand" "=x")
1856 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1857 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1859 "TARGET_64BIT && !TARGET_FIX_R4000"
1861 [(set_attr "type" "imul")
1862 (set_attr "mode" "SI")])
1864 ;; Widening multiply with negation.
1865 (define_insn "*muls<u>_di"
1866 [(set (match_operand:DI 0 "register_operand" "=x")
1869 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1870 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1871 "!TARGET_64BIT && ISA_HAS_MULS"
1873 [(set_attr "type" "imul")
1874 (set_attr "mode" "SI")])
1876 (define_insn "<u>msubsidi4"
1877 [(set (match_operand:DI 0 "register_operand" "=ka")
1879 (match_operand:DI 3 "register_operand" "0")
1881 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1882 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1883 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1886 return "msub<u>\t%q0,%1,%2";
1887 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1888 return "msub<u>\t%1,%2";
1890 return "msac<u>\t$0,%1,%2";
1892 [(set_attr "type" "imadd")
1893 (set_attr "mode" "SI")])
1895 ;; _highpart patterns
1897 (define_expand "<su>mulsi3_highpart"
1898 [(set (match_operand:SI 0 "register_operand")
1901 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1902 (any_extend:DI (match_operand:SI 2 "register_operand")))
1907 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1911 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1916 (define_insn_and_split "<su>mulsi3_highpart_internal"
1917 [(set (match_operand:SI 0 "register_operand" "=d")
1920 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1921 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1923 (clobber (match_scratch:SI 3 "=l"))]
1925 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1926 "&& reload_completed && !TARGET_FIX_R4000"
1933 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1934 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1935 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1939 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1940 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1941 emit_insn (gen_mfhisi_di (operands[0], hilo));
1945 [(set_attr "type" "imul")
1946 (set_attr "mode" "SI")
1947 (set_attr "length" "8")])
1949 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1950 [(set (match_operand:SI 0 "register_operand" "=d")
1954 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1955 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1957 (clobber (match_scratch:SI 3 "=l"))]
1959 "mulhi<u>\t%0,%1,%2"
1960 [(set_attr "type" "imul3")
1961 (set_attr "mode" "SI")])
1963 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1964 [(set (match_operand:SI 0 "register_operand" "=d")
1969 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1970 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1972 (clobber (match_scratch:SI 3 "=l"))]
1974 "mulshi<u>\t%0,%1,%2"
1975 [(set_attr "type" "imul3")
1976 (set_attr "mode" "SI")])
1978 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1979 ;; errata MD(0), which says that dmultu does not always produce the
1981 (define_insn_and_split "<su>muldi3_highpart"
1982 [(set (match_operand:DI 0 "register_operand" "=d")
1985 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1986 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1988 (clobber (match_scratch:DI 3 "=l"))]
1989 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1990 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1991 "&& reload_completed && !TARGET_FIX_R4000"
1996 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1997 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
1998 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2001 [(set_attr "type" "imul")
2002 (set_attr "mode" "DI")
2003 (set_attr "length" "8")])
2005 (define_expand "<u>mulditi3"
2006 [(set (match_operand:TI 0 "register_operand")
2007 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2008 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2009 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2011 if (TARGET_FIX_R4000)
2012 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2014 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2019 (define_insn "<u>mulditi3_internal"
2020 [(set (match_operand:TI 0 "register_operand" "=x")
2021 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2022 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2024 && !TARGET_FIX_R4000
2025 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2027 [(set_attr "type" "imul")
2028 (set_attr "mode" "DI")])
2030 (define_insn "<u>mulditi3_r4000"
2031 [(set (match_operand:TI 0 "register_operand" "=d")
2032 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2033 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2034 (clobber (match_scratch:TI 3 "=x"))]
2037 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2038 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2039 [(set_attr "type" "imul")
2040 (set_attr "mode" "DI")
2041 (set_attr "length" "12")])
2043 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2044 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2046 (define_insn "madsi"
2047 [(set (match_operand:SI 0 "register_operand" "+l")
2048 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2049 (match_operand:SI 2 "register_operand" "d"))
2053 [(set_attr "type" "imadd")
2054 (set_attr "mode" "SI")])
2056 (define_insn "<u>maddsidi4"
2057 [(set (match_operand:DI 0 "register_operand" "=ka")
2059 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2060 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2061 (match_operand:DI 3 "register_operand" "0")))]
2062 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
2066 return "mad<u>\t%1,%2";
2067 else if (ISA_HAS_DSPR2)
2068 return "madd<u>\t%q0,%1,%2";
2069 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2070 return "madd<u>\t%1,%2";
2072 /* See comment in *macc. */
2073 return "%[macc<u>\t%@,%1,%2%]";
2075 [(set_attr "type" "imadd")
2076 (set_attr "mode" "SI")])
2078 ;; Floating point multiply accumulate instructions.
2080 (define_insn "*madd4<mode>"
2081 [(set (match_operand:ANYF 0 "register_operand" "=f")
2082 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2083 (match_operand:ANYF 2 "register_operand" "f"))
2084 (match_operand:ANYF 3 "register_operand" "f")))]
2085 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2086 "madd.<fmt>\t%0,%3,%1,%2"
2087 [(set_attr "type" "fmadd")
2088 (set_attr "mode" "<UNITMODE>")])
2090 (define_insn "*madd3<mode>"
2091 [(set (match_operand:ANYF 0 "register_operand" "=f")
2092 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2093 (match_operand:ANYF 2 "register_operand" "f"))
2094 (match_operand:ANYF 3 "register_operand" "0")))]
2095 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2096 "madd.<fmt>\t%0,%1,%2"
2097 [(set_attr "type" "fmadd")
2098 (set_attr "mode" "<UNITMODE>")])
2100 (define_insn "*msub4<mode>"
2101 [(set (match_operand:ANYF 0 "register_operand" "=f")
2102 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2103 (match_operand:ANYF 2 "register_operand" "f"))
2104 (match_operand:ANYF 3 "register_operand" "f")))]
2105 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2106 "msub.<fmt>\t%0,%3,%1,%2"
2107 [(set_attr "type" "fmadd")
2108 (set_attr "mode" "<UNITMODE>")])
2110 (define_insn "*msub3<mode>"
2111 [(set (match_operand:ANYF 0 "register_operand" "=f")
2112 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2113 (match_operand:ANYF 2 "register_operand" "f"))
2114 (match_operand:ANYF 3 "register_operand" "0")))]
2115 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2116 "msub.<fmt>\t%0,%1,%2"
2117 [(set_attr "type" "fmadd")
2118 (set_attr "mode" "<UNITMODE>")])
2120 (define_insn "*nmadd4<mode>"
2121 [(set (match_operand:ANYF 0 "register_operand" "=f")
2122 (neg:ANYF (plus:ANYF
2123 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2124 (match_operand:ANYF 2 "register_operand" "f"))
2125 (match_operand:ANYF 3 "register_operand" "f"))))]
2126 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2127 && TARGET_FUSED_MADD
2128 && HONOR_SIGNED_ZEROS (<MODE>mode)
2129 && !HONOR_NANS (<MODE>mode)"
2130 "nmadd.<fmt>\t%0,%3,%1,%2"
2131 [(set_attr "type" "fmadd")
2132 (set_attr "mode" "<UNITMODE>")])
2134 (define_insn "*nmadd3<mode>"
2135 [(set (match_operand:ANYF 0 "register_operand" "=f")
2136 (neg:ANYF (plus:ANYF
2137 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2138 (match_operand:ANYF 2 "register_operand" "f"))
2139 (match_operand:ANYF 3 "register_operand" "0"))))]
2140 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2141 && TARGET_FUSED_MADD
2142 && HONOR_SIGNED_ZEROS (<MODE>mode)
2143 && !HONOR_NANS (<MODE>mode)"
2144 "nmadd.<fmt>\t%0,%1,%2"
2145 [(set_attr "type" "fmadd")
2146 (set_attr "mode" "<UNITMODE>")])
2148 (define_insn "*nmadd4<mode>_fastmath"
2149 [(set (match_operand:ANYF 0 "register_operand" "=f")
2151 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2152 (match_operand:ANYF 2 "register_operand" "f"))
2153 (match_operand:ANYF 3 "register_operand" "f")))]
2154 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2155 && TARGET_FUSED_MADD
2156 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2157 && !HONOR_NANS (<MODE>mode)"
2158 "nmadd.<fmt>\t%0,%3,%1,%2"
2159 [(set_attr "type" "fmadd")
2160 (set_attr "mode" "<UNITMODE>")])
2162 (define_insn "*nmadd3<mode>_fastmath"
2163 [(set (match_operand:ANYF 0 "register_operand" "=f")
2165 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2166 (match_operand:ANYF 2 "register_operand" "f"))
2167 (match_operand:ANYF 3 "register_operand" "0")))]
2168 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2169 && TARGET_FUSED_MADD
2170 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2171 && !HONOR_NANS (<MODE>mode)"
2172 "nmadd.<fmt>\t%0,%1,%2"
2173 [(set_attr "type" "fmadd")
2174 (set_attr "mode" "<UNITMODE>")])
2176 (define_insn "*nmsub4<mode>"
2177 [(set (match_operand:ANYF 0 "register_operand" "=f")
2178 (neg:ANYF (minus:ANYF
2179 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2180 (match_operand:ANYF 3 "register_operand" "f"))
2181 (match_operand:ANYF 1 "register_operand" "f"))))]
2182 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2183 && TARGET_FUSED_MADD
2184 && HONOR_SIGNED_ZEROS (<MODE>mode)
2185 && !HONOR_NANS (<MODE>mode)"
2186 "nmsub.<fmt>\t%0,%1,%2,%3"
2187 [(set_attr "type" "fmadd")
2188 (set_attr "mode" "<UNITMODE>")])
2190 (define_insn "*nmsub3<mode>"
2191 [(set (match_operand:ANYF 0 "register_operand" "=f")
2192 (neg:ANYF (minus:ANYF
2193 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2194 (match_operand:ANYF 3 "register_operand" "f"))
2195 (match_operand:ANYF 1 "register_operand" "0"))))]
2196 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2197 && TARGET_FUSED_MADD
2198 && HONOR_SIGNED_ZEROS (<MODE>mode)
2199 && !HONOR_NANS (<MODE>mode)"
2200 "nmsub.<fmt>\t%0,%1,%2"
2201 [(set_attr "type" "fmadd")
2202 (set_attr "mode" "<UNITMODE>")])
2204 (define_insn "*nmsub4<mode>_fastmath"
2205 [(set (match_operand:ANYF 0 "register_operand" "=f")
2207 (match_operand:ANYF 1 "register_operand" "f")
2208 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2209 (match_operand:ANYF 3 "register_operand" "f"))))]
2210 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2211 && TARGET_FUSED_MADD
2212 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2213 && !HONOR_NANS (<MODE>mode)"
2214 "nmsub.<fmt>\t%0,%1,%2,%3"
2215 [(set_attr "type" "fmadd")
2216 (set_attr "mode" "<UNITMODE>")])
2218 (define_insn "*nmsub3<mode>_fastmath"
2219 [(set (match_operand:ANYF 0 "register_operand" "=f")
2221 (match_operand:ANYF 1 "register_operand" "f")
2222 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2223 (match_operand:ANYF 3 "register_operand" "0"))))]
2224 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2225 && TARGET_FUSED_MADD
2226 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2227 && !HONOR_NANS (<MODE>mode)"
2228 "nmsub.<fmt>\t%0,%1,%2"
2229 [(set_attr "type" "fmadd")
2230 (set_attr "mode" "<UNITMODE>")])
2233 ;; ....................
2235 ;; DIVISION and REMAINDER
2237 ;; ....................
2240 (define_expand "div<mode>3"
2241 [(set (match_operand:ANYF 0 "register_operand")
2242 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2243 (match_operand:ANYF 2 "register_operand")))]
2244 "<divide_condition>"
2246 if (const_1_operand (operands[1], <MODE>mode))
2247 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2248 operands[1] = force_reg (<MODE>mode, operands[1]);
2251 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2253 ;; If an mfc1 or dmfc1 happens to access the floating point register
2254 ;; file at the same time a long latency operation (div, sqrt, recip,
2255 ;; sqrt) iterates an intermediate result back through the floating
2256 ;; point register file bypass, then instead returning the correct
2257 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2258 ;; result of the long latency operation.
2260 ;; The workaround is to insert an unconditional 'mov' from/to the
2261 ;; long latency op destination register.
2263 (define_insn "*div<mode>3"
2264 [(set (match_operand:ANYF 0 "register_operand" "=f")
2265 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2266 (match_operand:ANYF 2 "register_operand" "f")))]
2267 "<divide_condition>"
2270 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2272 return "div.<fmt>\t%0,%1,%2";
2274 [(set_attr "type" "fdiv")
2275 (set_attr "mode" "<UNITMODE>")
2276 (set (attr "length")
2277 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2281 (define_insn "*recip<mode>3"
2282 [(set (match_operand:ANYF 0 "register_operand" "=f")
2283 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2284 (match_operand:ANYF 2 "register_operand" "f")))]
2285 "<recip_condition> && flag_unsafe_math_optimizations"
2288 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2290 return "recip.<fmt>\t%0,%2";
2292 [(set_attr "type" "frdiv")
2293 (set_attr "mode" "<UNITMODE>")
2294 (set (attr "length")
2295 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2299 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2300 ;; with negative operands. We use special libgcc functions instead.
2301 (define_insn_and_split "divmod<mode>4"
2302 [(set (match_operand:GPR 0 "register_operand" "=l")
2303 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2304 (match_operand:GPR 2 "register_operand" "d")))
2305 (set (match_operand:GPR 3 "register_operand" "=d")
2306 (mod:GPR (match_dup 1)
2308 "!TARGET_FIX_VR4120"
2310 "&& reload_completed"
2317 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2318 emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2319 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2323 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2324 emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2325 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2329 [(set_attr "type" "idiv")
2330 (set_attr "mode" "<MODE>")
2331 (set_attr "length" "8")])
2333 (define_insn_and_split "udivmod<mode>4"
2334 [(set (match_operand:GPR 0 "register_operand" "=l")
2335 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2336 (match_operand:GPR 2 "register_operand" "d")))
2337 (set (match_operand:GPR 3 "register_operand" "=d")
2338 (umod:GPR (match_dup 1)
2349 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2350 emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2351 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2355 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2356 emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2357 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2361 [(set_attr "type" "idiv")
2362 (set_attr "mode" "<MODE>")
2363 (set_attr "length" "8")])
2365 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2366 [(set (match_operand:HILO 0 "register_operand" "=x")
2368 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2369 (match_operand:GPR 2 "register_operand" "d"))]
2372 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2373 [(set_attr "type" "idiv")
2374 (set_attr "mode" "<GPR:MODE>")])
2377 ;; ....................
2381 ;; ....................
2383 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2384 ;; "*div[sd]f3" comment for details).
2386 (define_insn "sqrt<mode>2"
2387 [(set (match_operand:ANYF 0 "register_operand" "=f")
2388 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2392 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2394 return "sqrt.<fmt>\t%0,%1";
2396 [(set_attr "type" "fsqrt")
2397 (set_attr "mode" "<UNITMODE>")
2398 (set (attr "length")
2399 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2403 (define_insn "*rsqrt<mode>a"
2404 [(set (match_operand:ANYF 0 "register_operand" "=f")
2405 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2406 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2407 "<recip_condition> && flag_unsafe_math_optimizations"
2410 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2412 return "rsqrt.<fmt>\t%0,%2";
2414 [(set_attr "type" "frsqrt")
2415 (set_attr "mode" "<UNITMODE>")
2416 (set (attr "length")
2417 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2421 (define_insn "*rsqrt<mode>b"
2422 [(set (match_operand:ANYF 0 "register_operand" "=f")
2423 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2424 (match_operand:ANYF 2 "register_operand" "f"))))]
2425 "<recip_condition> && flag_unsafe_math_optimizations"
2428 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2430 return "rsqrt.<fmt>\t%0,%2";
2432 [(set_attr "type" "frsqrt")
2433 (set_attr "mode" "<UNITMODE>")
2434 (set (attr "length")
2435 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2440 ;; ....................
2444 ;; ....................
2446 ;; Do not use the integer abs macro instruction, since that signals an
2447 ;; exception on -2147483648 (sigh).
2449 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2450 ;; invalid; it does not clear their sign bits. We therefore can't use
2451 ;; abs.fmt if the signs of NaNs matter.
2453 (define_insn "abs<mode>2"
2454 [(set (match_operand:ANYF 0 "register_operand" "=f")
2455 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2456 "!HONOR_NANS (<MODE>mode)"
2458 [(set_attr "type" "fabs")
2459 (set_attr "mode" "<UNITMODE>")])
2462 ;; ...................
2464 ;; Count leading zeroes.
2466 ;; ...................
2469 (define_insn "clz<mode>2"
2470 [(set (match_operand:GPR 0 "register_operand" "=d")
2471 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2474 [(set_attr "type" "clz")
2475 (set_attr "mode" "<MODE>")])
2478 ;; ...................
2480 ;; Count number of set bits.
2482 ;; ...................
2485 (define_insn "popcount<mode>2"
2486 [(set (match_operand:GPR 0 "register_operand" "=d")
2487 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2490 [(set_attr "type" "pop")
2491 (set_attr "mode" "<MODE>")])
2494 ;; ....................
2496 ;; NEGATION and ONE'S COMPLEMENT
2498 ;; ....................
2500 (define_insn "negsi2"
2501 [(set (match_operand:SI 0 "register_operand" "=d")
2502 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2506 return "neg\t%0,%1";
2508 return "subu\t%0,%.,%1";
2510 [(set_attr "type" "arith")
2511 (set_attr "mode" "SI")])
2513 (define_insn "negdi2"
2514 [(set (match_operand:DI 0 "register_operand" "=d")
2515 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2516 "TARGET_64BIT && !TARGET_MIPS16"
2518 [(set_attr "type" "arith")
2519 (set_attr "mode" "DI")])
2521 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2522 ;; invalid; it does not flip their sign bit. We therefore can't use
2523 ;; neg.fmt if the signs of NaNs matter.
2525 (define_insn "neg<mode>2"
2526 [(set (match_operand:ANYF 0 "register_operand" "=f")
2527 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2528 "!HONOR_NANS (<MODE>mode)"
2530 [(set_attr "type" "fneg")
2531 (set_attr "mode" "<UNITMODE>")])
2533 (define_insn "one_cmpl<mode>2"
2534 [(set (match_operand:GPR 0 "register_operand" "=d")
2535 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2539 return "not\t%0,%1";
2541 return "nor\t%0,%.,%1";
2543 [(set_attr "type" "logical")
2544 (set_attr "mode" "<MODE>")])
2547 ;; ....................
2551 ;; ....................
2554 ;; Many of these instructions use trivial define_expands, because we
2555 ;; want to use a different set of constraints when TARGET_MIPS16.
2557 (define_expand "and<mode>3"
2558 [(set (match_operand:GPR 0 "register_operand")
2559 (and:GPR (match_operand:GPR 1 "register_operand")
2560 (match_operand:GPR 2 "uns_arith_operand")))]
2564 operands[2] = force_reg (<MODE>mode, operands[2]);
2567 (define_insn "*and<mode>3"
2568 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2569 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2570 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2575 [(set_attr "type" "logical")
2576 (set_attr "mode" "<MODE>")])
2578 (define_insn "*and<mode>3_mips16"
2579 [(set (match_operand:GPR 0 "register_operand" "=d")
2580 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2581 (match_operand:GPR 2 "register_operand" "d")))]
2584 [(set_attr "type" "logical")
2585 (set_attr "mode" "<MODE>")])
2587 (define_expand "ior<mode>3"
2588 [(set (match_operand:GPR 0 "register_operand")
2589 (ior:GPR (match_operand:GPR 1 "register_operand")
2590 (match_operand:GPR 2 "uns_arith_operand")))]
2594 operands[2] = force_reg (<MODE>mode, operands[2]);
2597 (define_insn "*ior<mode>3"
2598 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2599 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2600 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2605 [(set_attr "type" "logical")
2606 (set_attr "mode" "<MODE>")])
2608 (define_insn "*ior<mode>3_mips16"
2609 [(set (match_operand:GPR 0 "register_operand" "=d")
2610 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2611 (match_operand:GPR 2 "register_operand" "d")))]
2614 [(set_attr "type" "logical")
2615 (set_attr "mode" "<MODE>")])
2617 (define_expand "xor<mode>3"
2618 [(set (match_operand:GPR 0 "register_operand")
2619 (xor:GPR (match_operand:GPR 1 "register_operand")
2620 (match_operand:GPR 2 "uns_arith_operand")))]
2625 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2626 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2627 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2632 [(set_attr "type" "logical")
2633 (set_attr "mode" "<MODE>")])
2636 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2637 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2638 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2644 [(set_attr "type" "logical,arith,arith")
2645 (set_attr "mode" "<MODE>")
2646 (set_attr_alternative "length"
2648 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2653 (define_insn "*nor<mode>3"
2654 [(set (match_operand:GPR 0 "register_operand" "=d")
2655 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2656 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2659 [(set_attr "type" "logical")
2660 (set_attr "mode" "<MODE>")])
2663 ;; ....................
2667 ;; ....................
2671 (define_insn "truncdfsf2"
2672 [(set (match_operand:SF 0 "register_operand" "=f")
2673 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2674 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2676 [(set_attr "type" "fcvt")
2677 (set_attr "cnv_mode" "D2S")
2678 (set_attr "mode" "SF")])
2680 ;; Integer truncation patterns. Truncating SImode values to smaller
2681 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2682 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2683 ;; need to make sure that the lower 32 bits are properly sign-extended
2684 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2685 ;; smaller than SImode is equivalent to two separate truncations:
2688 ;; DI ---> HI == DI ---> SI ---> HI
2689 ;; DI ---> QI == DI ---> SI ---> QI
2691 ;; Step A needs a real instruction but step B does not.
2693 (define_insn "truncdisi2"
2694 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2695 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2700 [(set_attr "move_type" "sll0,store")
2701 (set_attr "mode" "SI")])
2703 (define_insn "truncdihi2"
2704 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2705 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2710 [(set_attr "move_type" "sll0,store")
2711 (set_attr "mode" "SI")])
2713 (define_insn "truncdiqi2"
2714 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2715 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2720 [(set_attr "move_type" "sll0,store")
2721 (set_attr "mode" "SI")])
2723 ;; Combiner patterns to optimize shift/truncate combinations.
2725 (define_insn "*ashr_trunc<mode>"
2726 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2728 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2729 (match_operand:DI 2 "const_arith_operand" ""))))]
2730 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
2732 [(set_attr "type" "shift")
2733 (set_attr "mode" "<MODE>")])
2735 (define_insn "*lshr32_trunc<mode>"
2736 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2738 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2740 "TARGET_64BIT && !TARGET_MIPS16"
2742 [(set_attr "type" "shift")
2743 (set_attr "mode" "<MODE>")])
2745 ;; Logical shift by 32 or more results in proper SI values so
2746 ;; truncation is removed by the middle end.
2747 (define_insn "*<optab>_trunc<mode>_exts"
2748 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2750 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
2751 (match_operand:DI 2 "const_arith_operand" ""))))]
2752 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
2754 [(set_attr "type" "arith")
2755 (set_attr "mode" "<MODE>")])
2757 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
2758 ;; use the shift/truncate patterns above.
2760 (define_insn_and_split "*extenddi_truncate<mode>"
2761 [(set (match_operand:DI 0 "register_operand" "=d")
2763 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2764 "TARGET_64BIT && !TARGET_MIPS16"
2766 "&& reload_completed"
2768 (ashift:DI (match_dup 1)
2771 (ashiftrt:DI (match_dup 2)
2774 operands[2] = gen_lowpart (DImode, operands[0]);
2775 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2778 (define_insn_and_split "*extendsi_truncate<mode>"
2779 [(set (match_operand:SI 0 "register_operand" "=d")
2781 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2782 "TARGET_64BIT && !TARGET_MIPS16"
2784 "&& reload_completed"
2786 (ashift:DI (match_dup 1)
2789 (truncate:SI (ashiftrt:DI (match_dup 2)
2792 operands[2] = gen_lowpart (DImode, operands[0]);
2793 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2796 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2798 (define_insn "*zero_extend<mode>_trunchi"
2799 [(set (match_operand:GPR 0 "register_operand" "=d")
2801 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2802 "TARGET_64BIT && !TARGET_MIPS16"
2803 "andi\t%0,%1,0xffff"
2804 [(set_attr "type" "logical")
2805 (set_attr "mode" "<MODE>")])
2807 (define_insn "*zero_extend<mode>_truncqi"
2808 [(set (match_operand:GPR 0 "register_operand" "=d")
2810 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2811 "TARGET_64BIT && !TARGET_MIPS16"
2813 [(set_attr "type" "logical")
2814 (set_attr "mode" "<MODE>")])
2817 [(set (match_operand:HI 0 "register_operand" "=d")
2819 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2820 "TARGET_64BIT && !TARGET_MIPS16"
2822 [(set_attr "type" "logical")
2823 (set_attr "mode" "HI")])
2826 ;; ....................
2830 ;; ....................
2834 (define_insn_and_split "zero_extendsidi2"
2835 [(set (match_operand:DI 0 "register_operand" "=d,d")
2836 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2841 "&& reload_completed && REG_P (operands[1])"
2843 (ashift:DI (match_dup 1) (const_int 32)))
2845 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2846 { operands[1] = gen_lowpart (DImode, operands[1]); }
2847 [(set_attr "move_type" "shift_shift,load")
2848 (set_attr "mode" "DI")])
2850 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2851 ;; because of TRULY_NOOP_TRUNCATION.
2853 (define_insn_and_split "*clear_upper32"
2854 [(set (match_operand:DI 0 "register_operand" "=d,d")
2855 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2856 (const_int 4294967295)))]
2859 if (which_alternative == 0)
2862 operands[1] = gen_lowpart (SImode, operands[1]);
2863 return "lwu\t%0,%1";
2865 "&& reload_completed && REG_P (operands[1])"
2867 (ashift:DI (match_dup 1) (const_int 32)))
2869 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2871 [(set_attr "move_type" "shift_shift,load")
2872 (set_attr "mode" "DI")])
2874 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2875 [(set (match_operand:GPR 0 "register_operand")
2876 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2879 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2880 && !memory_operand (operands[1], <SHORT:MODE>mode))
2882 emit_insn (gen_and<GPR:mode>3 (operands[0],
2883 gen_lowpart (<GPR:MODE>mode, operands[1]),
2884 force_reg (<GPR:MODE>mode,
2885 GEN_INT (<SHORT:mask>))));
2890 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2891 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2893 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2896 andi\t%0,%1,<SHORT:mask>
2897 l<SHORT:size>u\t%0,%1"
2898 [(set_attr "move_type" "andi,load")
2899 (set_attr "mode" "<GPR:MODE>")])
2901 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2902 [(set (match_operand:GPR 0 "register_operand" "=d")
2903 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2905 "ze<SHORT:size>\t%0"
2906 ;; This instruction is effectively a special encoding of ANDI.
2907 [(set_attr "move_type" "andi")
2908 (set_attr "mode" "<GPR:MODE>")])
2910 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2911 [(set (match_operand:GPR 0 "register_operand" "=d")
2912 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2914 "l<SHORT:size>u\t%0,%1"
2915 [(set_attr "move_type" "load")
2916 (set_attr "mode" "<GPR:MODE>")])
2918 (define_expand "zero_extendqihi2"
2919 [(set (match_operand:HI 0 "register_operand")
2920 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2923 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2925 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2931 (define_insn "*zero_extendqihi2"
2932 [(set (match_operand:HI 0 "register_operand" "=d,d")
2933 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2938 [(set_attr "move_type" "andi,load")
2939 (set_attr "mode" "HI")])
2941 (define_insn "*zero_extendqihi2_mips16"
2942 [(set (match_operand:HI 0 "register_operand" "=d")
2943 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2946 [(set_attr "move_type" "load")
2947 (set_attr "mode" "HI")])
2950 ;; ....................
2954 ;; ....................
2957 ;; Those for integer source operand are ordered widest source type first.
2959 ;; When TARGET_64BIT, all SImode integer registers should already be in
2960 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2961 ;; therefore get rid of register->register instructions if we constrain
2962 ;; the source to be in the same register as the destination.
2964 ;; The register alternative has type "arith" so that the pre-reload
2965 ;; scheduler will treat it as a move. This reflects what happens if
2966 ;; the register alternative needs a reload.
2967 (define_insn_and_split "extendsidi2"
2968 [(set (match_operand:DI 0 "register_operand" "=d,d")
2969 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2974 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2977 emit_note (NOTE_INSN_DELETED);
2980 [(set_attr "move_type" "move,load")
2981 (set_attr "mode" "DI")])
2983 (define_expand "extend<SHORT:mode><GPR:mode>2"
2984 [(set (match_operand:GPR 0 "register_operand")
2985 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2988 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2989 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2990 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2994 l<SHORT:size>\t%0,%1"
2995 [(set_attr "move_type" "signext,load")
2996 (set_attr "mode" "<GPR:MODE>")])
2998 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2999 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3001 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3002 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3005 l<SHORT:size>\t%0,%1"
3006 "&& reload_completed && REG_P (operands[1])"
3007 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3008 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3010 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3011 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3012 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3014 [(set_attr "move_type" "shift_shift,load")
3015 (set_attr "mode" "<GPR:MODE>")])
3017 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3018 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3020 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3023 se<SHORT:size>\t%0,%1
3024 l<SHORT:size>\t%0,%1"
3025 [(set_attr "move_type" "signext,load")
3026 (set_attr "mode" "<GPR:MODE>")])
3028 (define_expand "extendqihi2"
3029 [(set (match_operand:HI 0 "register_operand")
3030 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3033 (define_insn "*extendqihi2_mips16e"
3034 [(set (match_operand:HI 0 "register_operand" "=d,d")
3035 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3040 [(set_attr "move_type" "signext,load")
3041 (set_attr "mode" "SI")])
3043 (define_insn_and_split "*extendqihi2"
3044 [(set (match_operand:HI 0 "register_operand" "=d,d")
3046 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3047 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3051 "&& reload_completed && REG_P (operands[1])"
3052 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3053 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3055 operands[0] = gen_lowpart (SImode, operands[0]);
3056 operands[1] = gen_lowpart (SImode, operands[1]);
3057 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3058 - GET_MODE_BITSIZE (QImode));
3060 [(set_attr "move_type" "shift_shift,load")
3061 (set_attr "mode" "SI")])
3063 (define_insn "*extendqihi2_seb"
3064 [(set (match_operand:HI 0 "register_operand" "=d,d")
3066 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3071 [(set_attr "move_type" "signext,load")
3072 (set_attr "mode" "SI")])
3074 (define_insn "extendsfdf2"
3075 [(set (match_operand:DF 0 "register_operand" "=f")
3076 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3077 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3079 [(set_attr "type" "fcvt")
3080 (set_attr "cnv_mode" "S2D")
3081 (set_attr "mode" "DF")])
3084 ;; ....................
3088 ;; ....................
3090 (define_expand "fix_truncdfsi2"
3091 [(set (match_operand:SI 0 "register_operand")
3092 (fix:SI (match_operand:DF 1 "register_operand")))]
3093 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3095 if (!ISA_HAS_TRUNC_W)
3097 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3102 (define_insn "fix_truncdfsi2_insn"
3103 [(set (match_operand:SI 0 "register_operand" "=f")
3104 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3105 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3107 [(set_attr "type" "fcvt")
3108 (set_attr "mode" "DF")
3109 (set_attr "cnv_mode" "D2I")])
3111 (define_insn "fix_truncdfsi2_macro"
3112 [(set (match_operand:SI 0 "register_operand" "=f")
3113 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3114 (clobber (match_scratch:DF 2 "=d"))]
3115 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3118 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3120 return "trunc.w.d %0,%1,%2";
3122 [(set_attr "type" "fcvt")
3123 (set_attr "mode" "DF")
3124 (set_attr "cnv_mode" "D2I")
3125 (set_attr "length" "36")])
3127 (define_expand "fix_truncsfsi2"
3128 [(set (match_operand:SI 0 "register_operand")
3129 (fix:SI (match_operand:SF 1 "register_operand")))]
3132 if (!ISA_HAS_TRUNC_W)
3134 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3139 (define_insn "fix_truncsfsi2_insn"
3140 [(set (match_operand:SI 0 "register_operand" "=f")
3141 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3142 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3144 [(set_attr "type" "fcvt")
3145 (set_attr "mode" "SF")
3146 (set_attr "cnv_mode" "S2I")])
3148 (define_insn "fix_truncsfsi2_macro"
3149 [(set (match_operand:SI 0 "register_operand" "=f")
3150 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3151 (clobber (match_scratch:SF 2 "=d"))]
3152 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3155 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3157 return "trunc.w.s %0,%1,%2";
3159 [(set_attr "type" "fcvt")
3160 (set_attr "mode" "SF")
3161 (set_attr "cnv_mode" "S2I")
3162 (set_attr "length" "36")])
3165 (define_insn "fix_truncdfdi2"
3166 [(set (match_operand:DI 0 "register_operand" "=f")
3167 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3168 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3170 [(set_attr "type" "fcvt")
3171 (set_attr "mode" "DF")
3172 (set_attr "cnv_mode" "D2I")])
3175 (define_insn "fix_truncsfdi2"
3176 [(set (match_operand:DI 0 "register_operand" "=f")
3177 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3178 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3180 [(set_attr "type" "fcvt")
3181 (set_attr "mode" "SF")
3182 (set_attr "cnv_mode" "S2I")])
3185 (define_insn "floatsidf2"
3186 [(set (match_operand:DF 0 "register_operand" "=f")
3187 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3188 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3190 [(set_attr "type" "fcvt")
3191 (set_attr "mode" "DF")
3192 (set_attr "cnv_mode" "I2D")])
3195 (define_insn "floatdidf2"
3196 [(set (match_operand:DF 0 "register_operand" "=f")
3197 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3198 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3200 [(set_attr "type" "fcvt")
3201 (set_attr "mode" "DF")
3202 (set_attr "cnv_mode" "I2D")])
3205 (define_insn "floatsisf2"
3206 [(set (match_operand:SF 0 "register_operand" "=f")
3207 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3210 [(set_attr "type" "fcvt")
3211 (set_attr "mode" "SF")
3212 (set_attr "cnv_mode" "I2S")])
3215 (define_insn "floatdisf2"
3216 [(set (match_operand:SF 0 "register_operand" "=f")
3217 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3218 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3220 [(set_attr "type" "fcvt")
3221 (set_attr "mode" "SF")
3222 (set_attr "cnv_mode" "I2S")])
3225 (define_expand "fixuns_truncdfsi2"
3226 [(set (match_operand:SI 0 "register_operand")
3227 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3228 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3230 rtx reg1 = gen_reg_rtx (DFmode);
3231 rtx reg2 = gen_reg_rtx (DFmode);
3232 rtx reg3 = gen_reg_rtx (SImode);
3233 rtx label1 = gen_label_rtx ();
3234 rtx label2 = gen_label_rtx ();
3235 REAL_VALUE_TYPE offset;
3237 real_2expN (&offset, 31, DFmode);
3239 if (reg1) /* Turn off complaints about unreached code. */
3241 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3242 do_pending_stack_adjust ();
3244 emit_insn (gen_cmpdf (operands[1], reg1));
3245 emit_jump_insn (gen_bge (label1));
3247 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3248 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3249 gen_rtx_LABEL_REF (VOIDmode, label2)));
3252 emit_label (label1);
3253 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3254 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3255 (BITMASK_HIGH, SImode)));
3257 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3258 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3260 emit_label (label2);
3262 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3263 fields, and can't be used for REG_NOTES anyway). */
3264 emit_use (stack_pointer_rtx);
3270 (define_expand "fixuns_truncdfdi2"
3271 [(set (match_operand:DI 0 "register_operand")
3272 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3273 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3275 rtx reg1 = gen_reg_rtx (DFmode);
3276 rtx reg2 = gen_reg_rtx (DFmode);
3277 rtx reg3 = gen_reg_rtx (DImode);
3278 rtx label1 = gen_label_rtx ();
3279 rtx label2 = gen_label_rtx ();
3280 REAL_VALUE_TYPE offset;
3282 real_2expN (&offset, 63, DFmode);
3284 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3285 do_pending_stack_adjust ();
3287 emit_insn (gen_cmpdf (operands[1], reg1));
3288 emit_jump_insn (gen_bge (label1));
3290 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3291 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3292 gen_rtx_LABEL_REF (VOIDmode, label2)));
3295 emit_label (label1);
3296 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3297 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3298 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3300 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3301 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3303 emit_label (label2);
3305 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3306 fields, and can't be used for REG_NOTES anyway). */
3307 emit_use (stack_pointer_rtx);
3312 (define_expand "fixuns_truncsfsi2"
3313 [(set (match_operand:SI 0 "register_operand")
3314 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3317 rtx reg1 = gen_reg_rtx (SFmode);
3318 rtx reg2 = gen_reg_rtx (SFmode);
3319 rtx reg3 = gen_reg_rtx (SImode);
3320 rtx label1 = gen_label_rtx ();
3321 rtx label2 = gen_label_rtx ();
3322 REAL_VALUE_TYPE offset;
3324 real_2expN (&offset, 31, SFmode);
3326 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3327 do_pending_stack_adjust ();
3329 emit_insn (gen_cmpsf (operands[1], reg1));
3330 emit_jump_insn (gen_bge (label1));
3332 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3333 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3334 gen_rtx_LABEL_REF (VOIDmode, label2)));
3337 emit_label (label1);
3338 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3339 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3340 (BITMASK_HIGH, SImode)));
3342 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3343 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3345 emit_label (label2);
3347 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3348 fields, and can't be used for REG_NOTES anyway). */
3349 emit_use (stack_pointer_rtx);
3354 (define_expand "fixuns_truncsfdi2"
3355 [(set (match_operand:DI 0 "register_operand")
3356 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3357 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3359 rtx reg1 = gen_reg_rtx (SFmode);
3360 rtx reg2 = gen_reg_rtx (SFmode);
3361 rtx reg3 = gen_reg_rtx (DImode);
3362 rtx label1 = gen_label_rtx ();
3363 rtx label2 = gen_label_rtx ();
3364 REAL_VALUE_TYPE offset;
3366 real_2expN (&offset, 63, SFmode);
3368 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3369 do_pending_stack_adjust ();
3371 emit_insn (gen_cmpsf (operands[1], reg1));
3372 emit_jump_insn (gen_bge (label1));
3374 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3375 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3376 gen_rtx_LABEL_REF (VOIDmode, label2)));
3379 emit_label (label1);
3380 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3381 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3382 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3384 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3385 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3387 emit_label (label2);
3389 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3390 fields, and can't be used for REG_NOTES anyway). */
3391 emit_use (stack_pointer_rtx);
3396 ;; ....................
3400 ;; ....................
3402 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3404 (define_expand "extv"
3405 [(set (match_operand 0 "register_operand")
3406 (sign_extract (match_operand 1 "nonimmediate_operand")
3407 (match_operand 2 "const_int_operand")
3408 (match_operand 3 "const_int_operand")))]
3411 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3412 INTVAL (operands[2]),
3413 INTVAL (operands[3])))
3415 else if (register_operand (operands[1], GET_MODE (operands[0]))
3416 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3418 if (GET_MODE (operands[0]) == DImode)
3419 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3422 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3430 (define_insn "extv<mode>"
3431 [(set (match_operand:GPR 0 "register_operand" "=d")
3432 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3433 (match_operand 2 "const_int_operand" "")
3434 (match_operand 3 "const_int_operand" "")))]
3435 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3436 "exts\t%0,%1,%3,%m2"
3437 [(set_attr "type" "arith")
3438 (set_attr "mode" "<MODE>")])
3441 (define_expand "extzv"
3442 [(set (match_operand 0 "register_operand")
3443 (zero_extract (match_operand 1 "nonimmediate_operand")
3444 (match_operand 2 "const_int_operand")
3445 (match_operand 3 "const_int_operand")))]
3448 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3449 INTVAL (operands[2]),
3450 INTVAL (operands[3])))
3452 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3453 INTVAL (operands[3])))
3455 if (GET_MODE (operands[0]) == DImode)
3456 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3459 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3467 (define_insn "extzv<mode>"
3468 [(set (match_operand:GPR 0 "register_operand" "=d")
3469 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3470 (match_operand 2 "const_int_operand" "")
3471 (match_operand 3 "const_int_operand" "")))]
3472 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3473 INTVAL (operands[3]))"
3474 "<d>ext\t%0,%1,%3,%2"
3475 [(set_attr "type" "arith")
3476 (set_attr "mode" "<MODE>")])
3478 (define_insn "*extzv_trunc<mode>_exts"
3479 [(set (match_operand:GPR 0 "register_operand" "=d")
3481 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3482 (match_operand 2 "const_int_operand" "")
3483 (match_operand 3 "const_int_operand" ""))))]
3484 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3486 [(set_attr "type" "arith")
3487 (set_attr "mode" "<MODE>")])
3490 (define_expand "insv"
3491 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3492 (match_operand 1 "immediate_operand")
3493 (match_operand 2 "immediate_operand"))
3494 (match_operand 3 "reg_or_0_operand"))]
3497 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3498 INTVAL (operands[1]),
3499 INTVAL (operands[2])))
3501 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3502 INTVAL (operands[2])))
3504 if (GET_MODE (operands[0]) == DImode)
3505 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3508 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3516 (define_insn "insv<mode>"
3517 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3518 (match_operand:SI 1 "immediate_operand" "I")
3519 (match_operand:SI 2 "immediate_operand" "I"))
3520 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3521 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3522 INTVAL (operands[2]))"
3523 "<d>ins\t%0,%z3,%2,%1"
3524 [(set_attr "type" "arith")
3525 (set_attr "mode" "<MODE>")])
3527 ;; Combiner pattern for cins (clear and insert bit field). We can
3528 ;; implement mask-and-shift-left operation with this. Note that if
3529 ;; the upper bit of the mask is set in an SImode operation, the mask
3530 ;; itself will be sign-extended. mask_low_and_shift_len will
3531 ;; therefore be greater than our threshold of 32.
3533 (define_insn "*cins<mode>"
3534 [(set (match_operand:GPR 0 "register_operand" "=d")
3536 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3537 (match_operand:GPR 2 "const_int_operand" ""))
3538 (match_operand:GPR 3 "const_int_operand" "")))]
3540 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3543 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3544 return "cins\t%0,%1,%2,%m3";
3546 [(set_attr "type" "shift")
3547 (set_attr "mode" "<MODE>")])
3549 ;; Unaligned word moves generated by the bit field patterns.
3551 ;; As far as the rtl is concerned, both the left-part and right-part
3552 ;; instructions can access the whole field. However, the real operand
3553 ;; refers to just the first or the last byte (depending on endianness).
3554 ;; We therefore use two memory operands to each instruction, one to
3555 ;; describe the rtl effect and one to use in the assembly output.
3557 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3558 ;; This allows us to use the standard length calculations for the "load"
3559 ;; and "store" type attributes.
3561 (define_insn "mov_<load>l"
3562 [(set (match_operand:GPR 0 "register_operand" "=d")
3563 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3564 (match_operand:QI 2 "memory_operand" "m")]
3566 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3568 [(set_attr "move_type" "load")
3569 (set_attr "mode" "<MODE>")])
3571 (define_insn "mov_<load>r"
3572 [(set (match_operand:GPR 0 "register_operand" "=d")
3573 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3574 (match_operand:QI 2 "memory_operand" "m")
3575 (match_operand:GPR 3 "register_operand" "0")]
3576 UNSPEC_LOAD_RIGHT))]
3577 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3579 [(set_attr "move_type" "load")
3580 (set_attr "mode" "<MODE>")])
3582 (define_insn "mov_<store>l"
3583 [(set (match_operand:BLK 0 "memory_operand" "=m")
3584 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3585 (match_operand:QI 2 "memory_operand" "m")]
3586 UNSPEC_STORE_LEFT))]
3587 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3589 [(set_attr "move_type" "store")
3590 (set_attr "mode" "<MODE>")])
3592 (define_insn "mov_<store>r"
3593 [(set (match_operand:BLK 0 "memory_operand" "+m")
3594 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3595 (match_operand:QI 2 "memory_operand" "m")
3597 UNSPEC_STORE_RIGHT))]
3598 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3600 [(set_attr "move_type" "store")
3601 (set_attr "mode" "<MODE>")])
3603 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3604 ;; The required value is:
3606 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3608 ;; which translates to:
3610 ;; lui op0,%highest(op1)
3611 ;; daddiu op0,op0,%higher(op1)
3613 ;; daddiu op0,op0,%hi(op1)
3616 ;; The split is deferred until after flow2 to allow the peephole2 below
3618 (define_insn_and_split "*lea_high64"
3619 [(set (match_operand:DI 0 "register_operand" "=d")
3620 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3621 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3623 "&& epilogue_completed"
3624 [(set (match_dup 0) (high:DI (match_dup 2)))
3625 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3626 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3627 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3628 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3630 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3631 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3633 [(set_attr "length" "20")])
3635 ;; Use a scratch register to reduce the latency of the above pattern
3636 ;; on superscalar machines. The optimized sequence is:
3638 ;; lui op1,%highest(op2)
3640 ;; daddiu op1,op1,%higher(op2)
3642 ;; daddu op1,op1,op0
3644 [(set (match_operand:DI 1 "d_operand")
3645 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3646 (match_scratch:DI 0 "d")]
3647 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3648 [(set (match_dup 1) (high:DI (match_dup 3)))
3649 (set (match_dup 0) (high:DI (match_dup 4)))
3650 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3651 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3652 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3654 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3655 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3658 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3659 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3660 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3661 ;; used once. We can then use the sequence:
3663 ;; lui op0,%highest(op1)
3665 ;; daddiu op0,op0,%higher(op1)
3666 ;; daddiu op2,op2,%lo(op1)
3668 ;; daddu op0,op0,op2
3670 ;; which takes 4 cycles on most superscalar targets.
3671 (define_insn_and_split "*lea64"
3672 [(set (match_operand:DI 0 "register_operand" "=d")
3673 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3674 (clobber (match_scratch:DI 2 "=&d"))]
3675 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3677 "&& reload_completed"
3678 [(set (match_dup 0) (high:DI (match_dup 3)))
3679 (set (match_dup 2) (high:DI (match_dup 4)))
3680 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3681 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3682 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3683 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3685 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3686 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3688 [(set_attr "length" "24")])
3690 ;; Split HIGHs into:
3695 ;; on MIPS16 targets.
3697 [(set (match_operand:SI 0 "d_operand")
3698 (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
3699 "TARGET_MIPS16 && reload_completed"
3700 [(set (match_dup 0) (match_dup 2))
3701 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3703 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3706 ;; Insns to fetch a symbol from a big GOT.
3708 (define_insn_and_split "*xgot_hi<mode>"
3709 [(set (match_operand:P 0 "register_operand" "=d")
3710 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3711 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3713 "&& reload_completed"
3714 [(set (match_dup 0) (high:P (match_dup 2)))
3715 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3717 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3718 operands[3] = pic_offset_table_rtx;
3720 [(set_attr "got" "xgot_high")
3721 (set_attr "mode" "<MODE>")])
3723 (define_insn_and_split "*xgot_lo<mode>"
3724 [(set (match_operand:P 0 "register_operand" "=d")
3725 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3726 (match_operand:P 2 "got_disp_operand" "")))]
3727 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3729 "&& reload_completed"
3731 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3732 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3733 [(set_attr "got" "load")
3734 (set_attr "mode" "<MODE>")])
3736 ;; Insns to fetch a symbol from a normal GOT.
3738 (define_insn_and_split "*got_disp<mode>"
3739 [(set (match_operand:P 0 "register_operand" "=d")
3740 (match_operand:P 1 "got_disp_operand" ""))]
3741 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3743 "&& reload_completed"
3744 [(set (match_dup 0) (match_dup 2))]
3745 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3746 [(set_attr "got" "load")
3747 (set_attr "mode" "<MODE>")])
3749 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3751 (define_insn_and_split "*got_page<mode>"
3752 [(set (match_operand:P 0 "register_operand" "=d")
3753 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3754 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3756 "&& reload_completed"
3757 [(set (match_dup 0) (match_dup 2))]
3758 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3759 [(set_attr "got" "load")
3760 (set_attr "mode" "<MODE>")])
3762 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
3763 (define_expand "unspec_got<mode>"
3764 [(unspec:P [(match_operand:P 0)
3765 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
3767 ;; Lower-level instructions for loading an address from the GOT.
3768 ;; We could use MEMs, but an unspec gives more optimization
3771 (define_insn "load_got<mode>"
3772 [(set (match_operand:P 0 "register_operand" "=d")
3773 (unspec:P [(match_operand:P 1 "register_operand" "d")
3774 (match_operand:P 2 "immediate_operand" "")]
3777 "<load>\t%0,%R2(%1)"
3778 [(set_attr "got" "load")
3779 (set_attr "mode" "<MODE>")])
3781 ;; Instructions for adding the low 16 bits of an address to a register.
3782 ;; Operand 2 is the address: mips_print_operand works out which relocation
3783 ;; should be applied.
3785 (define_insn "*low<mode>"
3786 [(set (match_operand:P 0 "register_operand" "=d")
3787 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3788 (match_operand:P 2 "immediate_operand" "")))]
3790 "<d>addiu\t%0,%1,%R2"
3791 [(set_attr "type" "arith")
3792 (set_attr "mode" "<MODE>")])
3794 (define_insn "*low<mode>_mips16"
3795 [(set (match_operand:P 0 "register_operand" "=d")
3796 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3797 (match_operand:P 2 "immediate_operand" "")))]
3800 [(set_attr "type" "arith")
3801 (set_attr "mode" "<MODE>")
3802 (set_attr "extended_mips16" "yes")])
3804 ;; Expose MIPS16 uses of the global pointer after reload if the function
3805 ;; is responsible for setting up the register itself.
3807 [(set (match_operand:GPR 0 "d_operand")
3808 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
3809 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
3810 [(set (match_dup 0) (match_dup 1))]
3811 { operands[1] = pic_offset_table_rtx; })
3813 ;; Allow combine to split complex const_int load sequences, using operand 2
3814 ;; to store the intermediate results. See move_operand for details.
3816 [(set (match_operand:GPR 0 "register_operand")
3817 (match_operand:GPR 1 "splittable_const_int_operand"))
3818 (clobber (match_operand:GPR 2 "register_operand"))]
3822 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3826 ;; Likewise, for symbolic operands.
3828 [(set (match_operand:P 0 "register_operand")
3829 (match_operand:P 1))
3830 (clobber (match_operand:P 2 "register_operand"))]
3831 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3832 [(set (match_dup 0) (match_dup 3))]
3834 mips_split_symbol (operands[2], operands[1],
3835 MAX_MACHINE_MODE, &operands[3]);
3838 ;; 64-bit integer moves
3840 ;; Unlike most other insns, the move insns can't be split with
3841 ;; different predicates, because register spilling and other parts of
3842 ;; the compiler, have memoized the insn number already.
3844 (define_expand "movdi"
3845 [(set (match_operand:DI 0 "")
3846 (match_operand:DI 1 ""))]
3849 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3853 ;; For mips16, we need a special case to handle storing $31 into
3854 ;; memory, since we don't have a constraint to match $31. This
3855 ;; instruction can be generated by save_restore_insns.
3857 (define_insn "*mov<mode>_ra"
3858 [(set (match_operand:GPR 0 "stack_operand" "=m")
3862 [(set_attr "move_type" "store")
3863 (set_attr "mode" "<MODE>")])
3865 (define_insn "*movdi_32bit"
3866 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
3867 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
3868 "!TARGET_64BIT && !TARGET_MIPS16
3869 && (register_operand (operands[0], DImode)
3870 || reg_or_0_operand (operands[1], DImode))"
3871 { return mips_output_move (operands[0], operands[1]); }
3872 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
3873 (set_attr "mode" "DI")])
3875 (define_insn "*movdi_32bit_mips16"
3876 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3877 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3878 "!TARGET_64BIT && TARGET_MIPS16
3879 && (register_operand (operands[0], DImode)
3880 || register_operand (operands[1], DImode))"
3881 { return mips_output_move (operands[0], operands[1]); }
3882 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
3883 (set_attr "mode" "DI")])
3885 (define_insn "*movdi_64bit"
3886 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3887 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3888 "TARGET_64BIT && !TARGET_MIPS16
3889 && (register_operand (operands[0], DImode)
3890 || reg_or_0_operand (operands[1], DImode))"
3891 { return mips_output_move (operands[0], operands[1]); }
3892 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3893 (set_attr "mode" "DI")])
3895 (define_insn "*movdi_64bit_mips16"
3896 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3897 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3898 "TARGET_64BIT && TARGET_MIPS16
3899 && (register_operand (operands[0], DImode)
3900 || register_operand (operands[1], DImode))"
3901 { return mips_output_move (operands[0], operands[1]); }
3902 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3903 (set_attr "mode" "DI")])
3905 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3906 ;; when the original load is a 4 byte instruction but the add and the
3907 ;; load are 2 2 byte instructions.
3910 [(set (match_operand:DI 0 "d_operand")
3911 (mem:DI (plus:DI (match_dup 0)
3912 (match_operand:DI 1 "const_int_operand"))))]
3913 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3914 && !TARGET_DEBUG_D_MODE
3915 && ((INTVAL (operands[1]) < 0
3916 && INTVAL (operands[1]) >= -0x10)
3917 || (INTVAL (operands[1]) >= 32 * 8
3918 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3919 || (INTVAL (operands[1]) >= 0
3920 && INTVAL (operands[1]) < 32 * 8
3921 && (INTVAL (operands[1]) & 7) != 0))"
3922 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3923 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3925 HOST_WIDE_INT val = INTVAL (operands[1]);
3928 operands[2] = const0_rtx;
3929 else if (val >= 32 * 8)
3933 operands[1] = GEN_INT (0x8 + off);
3934 operands[2] = GEN_INT (val - off - 0x8);
3940 operands[1] = GEN_INT (off);
3941 operands[2] = GEN_INT (val - off);
3945 ;; 32-bit Integer moves
3947 ;; Unlike most other insns, the move insns can't be split with
3948 ;; different predicates, because register spilling and other parts of
3949 ;; the compiler, have memoized the insn number already.
3951 (define_expand "mov<mode>"
3952 [(set (match_operand:IMOVE32 0 "")
3953 (match_operand:IMOVE32 1 ""))]
3956 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
3960 ;; The difference between these two is whether or not ints are allowed
3961 ;; in FP registers (off by default, use -mdebugh to enable).
3963 (define_insn "*mov<mode>_internal"
3964 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3965 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3967 && (register_operand (operands[0], <MODE>mode)
3968 || reg_or_0_operand (operands[1], <MODE>mode))"
3969 { return mips_output_move (operands[0], operands[1]); }
3970 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3971 (set_attr "mode" "SI")])
3973 (define_insn "*mov<mode>_mips16"
3974 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3975 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3977 && (register_operand (operands[0], <MODE>mode)
3978 || register_operand (operands[1], <MODE>mode))"
3979 { return mips_output_move (operands[0], operands[1]); }
3980 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3981 (set_attr "mode" "SI")])
3983 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3984 ;; when the original load is a 4 byte instruction but the add and the
3985 ;; load are 2 2 byte instructions.
3988 [(set (match_operand:SI 0 "d_operand")
3989 (mem:SI (plus:SI (match_dup 0)
3990 (match_operand:SI 1 "const_int_operand"))))]
3991 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3992 && ((INTVAL (operands[1]) < 0
3993 && INTVAL (operands[1]) >= -0x80)
3994 || (INTVAL (operands[1]) >= 32 * 4
3995 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3996 || (INTVAL (operands[1]) >= 0
3997 && INTVAL (operands[1]) < 32 * 4
3998 && (INTVAL (operands[1]) & 3) != 0))"
3999 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4000 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4002 HOST_WIDE_INT val = INTVAL (operands[1]);
4005 operands[2] = const0_rtx;
4006 else if (val >= 32 * 4)
4010 operands[1] = GEN_INT (0x7c + off);
4011 operands[2] = GEN_INT (val - off - 0x7c);
4017 operands[1] = GEN_INT (off);
4018 operands[2] = GEN_INT (val - off);
4022 ;; On the mips16, we can split a load of certain constants into a load
4023 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4027 [(set (match_operand:SI 0 "d_operand")
4028 (match_operand:SI 1 "const_int_operand"))]
4029 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4030 && INTVAL (operands[1]) >= 0x100
4031 && INTVAL (operands[1]) <= 0xff + 0x7f"
4032 [(set (match_dup 0) (match_dup 1))
4033 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4035 int val = INTVAL (operands[1]);
4037 operands[1] = GEN_INT (0xff);
4038 operands[2] = GEN_INT (val - 0xff);
4041 ;; This insn handles moving CCmode values. It's really just a
4042 ;; slightly simplified copy of movsi_internal2, with additional cases
4043 ;; to move a condition register to a general register and to move
4044 ;; between the general registers and the floating point registers.
4046 (define_insn "movcc"
4047 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4048 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4049 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4050 { return mips_output_move (operands[0], operands[1]); }
4051 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
4052 (set_attr "mode" "SI")])
4054 ;; Reload condition code registers. reload_incc and reload_outcc
4055 ;; both handle moves from arbitrary operands into condition code
4056 ;; registers. reload_incc handles the more common case in which
4057 ;; a source operand is constrained to be in a condition-code
4058 ;; register, but has not been allocated to one.
4060 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4061 ;; constraints do not include 'z'. reload_outcc handles the case
4062 ;; when such an operand is allocated to a condition-code register.
4064 ;; Note that reloads from a condition code register to some
4065 ;; other location can be done using ordinary moves. Moving
4066 ;; into a GPR takes a single movcc, moving elsewhere takes
4067 ;; two. We can leave these cases to the generic reload code.
4068 (define_expand "reload_incc"
4069 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4070 (match_operand:CC 1 "general_operand" ""))
4071 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4072 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4074 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4078 (define_expand "reload_outcc"
4079 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4080 (match_operand:CC 1 "register_operand" ""))
4081 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4082 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4084 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4088 ;; MIPS4 supports loading and storing a floating point register from
4089 ;; the sum of two general registers. We use two versions for each of
4090 ;; these four instructions: one where the two general registers are
4091 ;; SImode, and one where they are DImode. This is because general
4092 ;; registers will be in SImode when they hold 32-bit values, but,
4093 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4094 ;; instructions will still work correctly.
4096 ;; ??? Perhaps it would be better to support these instructions by
4097 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
4098 ;; these instructions can only be used to load and store floating
4099 ;; point registers, that would probably cause trouble in reload.
4101 (define_insn "*<ANYF:loadx>_<P:mode>"
4102 [(set (match_operand:ANYF 0 "register_operand" "=f")
4103 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4104 (match_operand:P 2 "register_operand" "d"))))]
4106 "<ANYF:loadx>\t%0,%1(%2)"
4107 [(set_attr "type" "fpidxload")
4108 (set_attr "mode" "<ANYF:UNITMODE>")])
4110 (define_insn "*<ANYF:storex>_<P:mode>"
4111 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4112 (match_operand:P 2 "register_operand" "d")))
4113 (match_operand:ANYF 0 "register_operand" "f"))]
4115 "<ANYF:storex>\t%0,%1(%2)"
4116 [(set_attr "type" "fpidxstore")
4117 (set_attr "mode" "<ANYF:UNITMODE>")])
4119 ;; Scaled indexed address load.
4120 ;; Per md.texi, we only need to look for a pattern with multiply in the
4121 ;; address expression, not shift.
4123 (define_insn "*lwxs"
4124 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4126 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
4128 (match_operand:SI 2 "register_operand" "d"))))]
4131 [(set_attr "type" "load")
4132 (set_attr "mode" "SI")])
4134 ;; 16-bit Integer moves
4136 ;; Unlike most other insns, the move insns can't be split with
4137 ;; different predicates, because register spilling and other parts of
4138 ;; the compiler, have memoized the insn number already.
4139 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4141 (define_expand "movhi"
4142 [(set (match_operand:HI 0 "")
4143 (match_operand:HI 1 ""))]
4146 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4150 (define_insn "*movhi_internal"
4151 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4152 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4154 && (register_operand (operands[0], HImode)
4155 || reg_or_0_operand (operands[1], HImode))"
4156 { return mips_output_move (operands[0], operands[1]); }
4157 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4158 (set_attr "mode" "HI")])
4160 (define_insn "*movhi_mips16"
4161 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4162 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4164 && (register_operand (operands[0], HImode)
4165 || register_operand (operands[1], HImode))"
4166 { return mips_output_move (operands[0], operands[1]); }
4167 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4168 (set_attr "mode" "HI")])
4170 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4171 ;; when the original load is a 4 byte instruction but the add and the
4172 ;; load are 2 2 byte instructions.
4175 [(set (match_operand:HI 0 "d_operand")
4176 (mem:HI (plus:SI (match_dup 0)
4177 (match_operand:SI 1 "const_int_operand"))))]
4178 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4179 && ((INTVAL (operands[1]) < 0
4180 && INTVAL (operands[1]) >= -0x80)
4181 || (INTVAL (operands[1]) >= 32 * 2
4182 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4183 || (INTVAL (operands[1]) >= 0
4184 && INTVAL (operands[1]) < 32 * 2
4185 && (INTVAL (operands[1]) & 1) != 0))"
4186 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4187 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4189 HOST_WIDE_INT val = INTVAL (operands[1]);
4192 operands[2] = const0_rtx;
4193 else if (val >= 32 * 2)
4197 operands[1] = GEN_INT (0x7e + off);
4198 operands[2] = GEN_INT (val - off - 0x7e);
4204 operands[1] = GEN_INT (off);
4205 operands[2] = GEN_INT (val - off);
4209 ;; 8-bit Integer moves
4211 ;; Unlike most other insns, the move insns can't be split with
4212 ;; different predicates, because register spilling and other parts of
4213 ;; the compiler, have memoized the insn number already.
4214 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4216 (define_expand "movqi"
4217 [(set (match_operand:QI 0 "")
4218 (match_operand:QI 1 ""))]
4221 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4225 (define_insn "*movqi_internal"
4226 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4227 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4229 && (register_operand (operands[0], QImode)
4230 || reg_or_0_operand (operands[1], QImode))"
4231 { return mips_output_move (operands[0], operands[1]); }
4232 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4233 (set_attr "mode" "QI")])
4235 (define_insn "*movqi_mips16"
4236 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4237 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4239 && (register_operand (operands[0], QImode)
4240 || register_operand (operands[1], QImode))"
4241 { return mips_output_move (operands[0], operands[1]); }
4242 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4243 (set_attr "mode" "QI")])
4245 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4246 ;; when the original load is a 4 byte instruction but the add and the
4247 ;; load are 2 2 byte instructions.
4250 [(set (match_operand:QI 0 "d_operand")
4251 (mem:QI (plus:SI (match_dup 0)
4252 (match_operand:SI 1 "const_int_operand"))))]
4253 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4254 && ((INTVAL (operands[1]) < 0
4255 && INTVAL (operands[1]) >= -0x80)
4256 || (INTVAL (operands[1]) >= 32
4257 && INTVAL (operands[1]) <= 31 + 0x7f))"
4258 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4259 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4261 HOST_WIDE_INT val = INTVAL (operands[1]);
4264 operands[2] = const0_rtx;
4267 operands[1] = GEN_INT (0x7f);
4268 operands[2] = GEN_INT (val - 0x7f);
4272 ;; 32-bit floating point moves
4274 (define_expand "movsf"
4275 [(set (match_operand:SF 0 "")
4276 (match_operand:SF 1 ""))]
4279 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4283 (define_insn "*movsf_hardfloat"
4284 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4285 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4287 && (register_operand (operands[0], SFmode)
4288 || reg_or_0_operand (operands[1], SFmode))"
4289 { return mips_output_move (operands[0], operands[1]); }
4290 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4291 (set_attr "mode" "SF")])
4293 (define_insn "*movsf_softfloat"
4294 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4295 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4296 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4297 && (register_operand (operands[0], SFmode)
4298 || reg_or_0_operand (operands[1], SFmode))"
4299 { return mips_output_move (operands[0], operands[1]); }
4300 [(set_attr "move_type" "move,load,store")
4301 (set_attr "mode" "SF")])
4303 (define_insn "*movsf_mips16"
4304 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4305 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4307 && (register_operand (operands[0], SFmode)
4308 || register_operand (operands[1], SFmode))"
4309 { return mips_output_move (operands[0], operands[1]); }
4310 [(set_attr "move_type" "move,move,move,load,store")
4311 (set_attr "mode" "SF")])
4313 ;; 64-bit floating point moves
4315 (define_expand "movdf"
4316 [(set (match_operand:DF 0 "")
4317 (match_operand:DF 1 ""))]
4320 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4324 (define_insn "*movdf_hardfloat"
4325 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4326 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4327 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4328 && (register_operand (operands[0], DFmode)
4329 || reg_or_0_operand (operands[1], DFmode))"
4330 { return mips_output_move (operands[0], operands[1]); }
4331 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4332 (set_attr "mode" "DF")])
4334 (define_insn "*movdf_softfloat"
4335 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4336 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4337 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4338 && (register_operand (operands[0], DFmode)
4339 || reg_or_0_operand (operands[1], DFmode))"
4340 { return mips_output_move (operands[0], operands[1]); }
4341 [(set_attr "move_type" "move,load,store")
4342 (set_attr "mode" "DF")])
4344 (define_insn "*movdf_mips16"
4345 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4346 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4348 && (register_operand (operands[0], DFmode)
4349 || register_operand (operands[1], DFmode))"
4350 { return mips_output_move (operands[0], operands[1]); }
4351 [(set_attr "move_type" "move,move,move,load,store")
4352 (set_attr "mode" "DF")])
4354 ;; 128-bit integer moves
4356 (define_expand "movti"
4357 [(set (match_operand:TI 0)
4358 (match_operand:TI 1))]
4361 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4365 (define_insn "*movti"
4366 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4367 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4370 && (register_operand (operands[0], TImode)
4371 || reg_or_0_operand (operands[1], TImode))"
4373 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4374 (set_attr "mode" "TI")])
4376 (define_insn "*movti_mips16"
4377 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4378 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4381 && (register_operand (operands[0], TImode)
4382 || register_operand (operands[1], TImode))"
4384 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4385 (set_attr "mode" "TI")])
4387 ;; 128-bit floating point moves
4389 (define_expand "movtf"
4390 [(set (match_operand:TF 0)
4391 (match_operand:TF 1))]
4394 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4398 ;; This pattern handles both hard- and soft-float cases.
4399 (define_insn "*movtf"
4400 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4401 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4404 && (register_operand (operands[0], TFmode)
4405 || reg_or_0_operand (operands[1], TFmode))"
4407 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4408 (set_attr "mode" "TF")])
4410 (define_insn "*movtf_mips16"
4411 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4412 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4415 && (register_operand (operands[0], TFmode)
4416 || register_operand (operands[1], TFmode))"
4418 [(set_attr "move_type" "move,move,move,load,store")
4419 (set_attr "mode" "TF")])
4422 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4423 (match_operand:MOVE64 1 "move_operand"))]
4424 "reload_completed && !TARGET_64BIT
4425 && mips_split_64bit_move_p (operands[0], operands[1])"
4428 mips_split_doubleword_move (operands[0], operands[1]);
4433 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4434 (match_operand:MOVE128 1 "move_operand"))]
4435 "TARGET_64BIT && reload_completed"
4438 mips_split_doubleword_move (operands[0], operands[1]);
4442 ;; When generating mips16 code, split moves of negative constants into
4443 ;; a positive "li" followed by a negation.
4445 [(set (match_operand 0 "d_operand")
4446 (match_operand 1 "const_int_operand"))]
4447 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4451 (neg:SI (match_dup 2)))]
4453 operands[2] = gen_lowpart (SImode, operands[0]);
4454 operands[3] = GEN_INT (-INTVAL (operands[1]));
4457 ;; 64-bit paired-single floating point moves
4459 (define_expand "movv2sf"
4460 [(set (match_operand:V2SF 0)
4461 (match_operand:V2SF 1))]
4462 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4464 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4468 (define_insn "*movv2sf"
4469 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4470 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4472 && TARGET_PAIRED_SINGLE_FLOAT
4473 && (register_operand (operands[0], V2SFmode)
4474 || reg_or_0_operand (operands[1], V2SFmode))"
4475 { return mips_output_move (operands[0], operands[1]); }
4476 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4477 (set_attr "mode" "DF")])
4479 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4480 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4482 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4483 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4484 ;; and the errata related to -mfix-vr4130.
4485 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4486 [(set (match_operand:GPR 0 "register_operand" "=d")
4487 (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
4490 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4491 [(set_attr "move_type" "mfhilo")
4492 (set_attr "mode" "<GPR:MODE>")])
4494 ;; Set the high part of a HI/LO value, given that the low part has
4495 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4496 ;; why we can't just use (reg:GPR HI_REGNUM).
4497 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4498 [(set (match_operand:HILO 0 "register_operand" "=x")
4499 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4500 (match_operand:GPR 2 "register_operand" "l")]
4504 [(set_attr "move_type" "mthilo")
4505 (set_attr "mode" "SI")])
4507 ;; Emit a doubleword move in which exactly one of the operands is
4508 ;; a floating-point register. We can't just emit two normal moves
4509 ;; because of the constraints imposed by the FPU register model;
4510 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4511 ;; the FPR whole and use special patterns to refer to each word of
4512 ;; the other operand.
4514 (define_expand "move_doubleword_fpr<mode>"
4515 [(set (match_operand:SPLITF 0)
4516 (match_operand:SPLITF 1))]
4519 if (FP_REG_RTX_P (operands[0]))
4521 rtx low = mips_subword (operands[1], 0);
4522 rtx high = mips_subword (operands[1], 1);
4523 emit_insn (gen_load_low<mode> (operands[0], low));
4524 if (TARGET_FLOAT64 && !TARGET_64BIT)
4525 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4527 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4531 rtx low = mips_subword (operands[0], 0);
4532 rtx high = mips_subword (operands[0], 1);
4533 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4534 if (TARGET_FLOAT64 && !TARGET_64BIT)
4535 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4537 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4542 ;; Load the low word of operand 0 with operand 1.
4543 (define_insn "load_low<mode>"
4544 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4545 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4549 operands[0] = mips_subword (operands[0], 0);
4550 return mips_output_move (operands[0], operands[1]);
4552 [(set_attr "move_type" "mtc,fpload")
4553 (set_attr "mode" "<HALFMODE>")])
4555 ;; Load the high word of operand 0 from operand 1, preserving the value
4557 (define_insn "load_high<mode>"
4558 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4559 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4560 (match_operand:SPLITF 2 "register_operand" "0,0")]
4564 operands[0] = mips_subword (operands[0], 1);
4565 return mips_output_move (operands[0], operands[1]);
4567 [(set_attr "move_type" "mtc,fpload")
4568 (set_attr "mode" "<HALFMODE>")])
4570 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4571 ;; high word and 0 to store the low word.
4572 (define_insn "store_word<mode>"
4573 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4574 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4575 (match_operand 2 "const_int_operand")]
4576 UNSPEC_STORE_WORD))]
4579 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4580 return mips_output_move (operands[0], operands[1]);
4582 [(set_attr "move_type" "mfc,fpstore")
4583 (set_attr "mode" "<HALFMODE>")])
4585 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4586 ;; value in the low word.
4587 (define_insn "mthc1<mode>"
4588 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4589 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4590 (match_operand:SPLITF 2 "register_operand" "0")]
4592 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4594 [(set_attr "move_type" "mtc")
4595 (set_attr "mode" "<HALFMODE>")])
4597 ;; Move high word of operand 1 to operand 0 using mfhc1.
4598 (define_insn "mfhc1<mode>"
4599 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4600 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4602 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4604 [(set_attr "move_type" "mfc")
4605 (set_attr "mode" "<HALFMODE>")])
4607 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4608 (define_expand "load_const_gp_<mode>"
4609 [(set (match_operand:P 0 "register_operand" "=d")
4610 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4612 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4613 ;; of _gp from the start of this function. Operand 1 is the incoming
4614 ;; function address.
4615 (define_insn_and_split "loadgp_newabi_<mode>"
4616 [(set (match_operand:P 0 "register_operand" "=d")
4617 (unspec_volatile:P [(match_operand:P 1)
4618 (match_operand:P 2 "register_operand" "d")]
4620 "mips_current_loadgp_style () == LOADGP_NEWABI"
4623 [(set (match_dup 0) (match_dup 3))
4624 (set (match_dup 0) (match_dup 4))
4625 (set (match_dup 0) (match_dup 5))]
4627 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4628 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4629 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4631 [(set_attr "length" "12")])
4633 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4634 (define_insn_and_split "loadgp_absolute_<mode>"
4635 [(set (match_operand:P 0 "register_operand" "=d")
4636 (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4637 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4642 mips_emit_move (operands[0], operands[1]);
4645 [(set_attr "length" "8")])
4647 ;; This blockage instruction prevents the gp load from being
4648 ;; scheduled after an implicit use of gp. It also prevents
4649 ;; the load from being deleted as dead.
4650 (define_insn "loadgp_blockage"
4651 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4654 [(set_attr "type" "ghost")
4655 (set_attr "mode" "none")])
4657 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4658 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4659 (define_insn_and_split "loadgp_rtp_<mode>"
4660 [(set (match_operand:P 0 "register_operand" "=d")
4661 (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
4662 (match_operand:P 2 "symbol_ref_operand")]
4664 "mips_current_loadgp_style () == LOADGP_RTP"
4667 [(set (match_dup 0) (high:P (match_dup 3)))
4668 (set (match_dup 0) (unspec:P [(match_dup 0)
4669 (match_dup 3)] UNSPEC_LOAD_GOT))
4670 (set (match_dup 0) (unspec:P [(match_dup 0)
4671 (match_dup 4)] UNSPEC_LOAD_GOT))]
4673 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4674 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4676 [(set_attr "length" "12")])
4678 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4679 ;; global pointer and operand 1 is the MIPS16 register that holds
4680 ;; the required value.
4681 (define_insn_and_split "copygp_mips16"
4682 [(set (match_operand:SI 0 "register_operand" "=y")
4683 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
4687 "&& reload_completed"
4688 [(set (match_dup 0) (match_dup 1))])
4690 ;; Emit a .cprestore directive, which normally expands to a single store
4691 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4692 ;; code so that jals inside inline asms will work correctly.
4693 (define_insn "cprestore"
4694 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4699 if (set_nomacro && which_alternative == 1)
4700 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4702 return ".cprestore\t%0";
4704 [(set_attr "type" "store")
4705 (set_attr "length" "4,12")])
4707 ;; Expand in-line code to clear the instruction cache between operand[0] and
4709 (define_expand "clear_cache"
4710 [(match_operand 0 "pmode_register_operand")
4711 (match_operand 1 "pmode_register_operand")]
4717 mips_expand_synci_loop (operands[0], operands[1]);
4718 emit_insn (gen_sync ());
4719 emit_insn (Pmode == SImode
4720 ? gen_clear_hazard_si ()
4721 : gen_clear_hazard_di ());
4723 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4725 rtx len = gen_reg_rtx (Pmode);
4726 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4727 MIPS_ICACHE_SYNC (operands[0], len);
4733 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4737 (define_insn "synci"
4738 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4743 (define_insn "rdhwr_synci_step_<mode>"
4744 [(set (match_operand:P 0 "register_operand" "=d")
4745 (unspec_volatile [(const_int 1)]
4750 (define_insn "clear_hazard_<mode>"
4751 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4752 (clobber (reg:P 31))]
4755 return "%(%<bal\t1f\n"
4757 "1:\t<d>addiu\t$31,$31,12\n"
4761 [(set_attr "length" "20")])
4763 ;; Cache operations for R4000-style caches.
4764 (define_insn "mips_cache"
4765 [(set (mem:BLK (scratch))
4766 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
4767 (match_operand:QI 1 "address_operand" "p")]
4768 UNSPEC_MIPS_CACHE))]
4772 ;; Similar, but with the operands hard-coded to an R10K cache barrier
4773 ;; operation. We keep the pattern distinct so that we can identify
4774 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
4775 ;; the operation is never inserted into a delay slot.
4776 (define_insn "r10k_cache_barrier"
4777 [(set (mem:BLK (scratch))
4778 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
4781 [(set_attr "can_delay" "no")])
4783 ;; Block moves, see mips.c for more details.
4784 ;; Argument 0 is the destination
4785 ;; Argument 1 is the source
4786 ;; Argument 2 is the length
4787 ;; Argument 3 is the alignment
4789 (define_expand "movmemsi"
4790 [(parallel [(set (match_operand:BLK 0 "general_operand")
4791 (match_operand:BLK 1 "general_operand"))
4792 (use (match_operand:SI 2 ""))
4793 (use (match_operand:SI 3 "const_int_operand"))])]
4794 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4796 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4803 ;; ....................
4807 ;; ....................
4809 (define_expand "<optab><mode>3"
4810 [(set (match_operand:GPR 0 "register_operand")
4811 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4812 (match_operand:SI 2 "arith_operand")))]
4815 /* On the mips16, a shift of more than 8 is a four byte instruction,
4816 so, for a shift between 8 and 16, it is just as fast to do two
4817 shifts of 8 or less. If there is a lot of shifting going on, we
4818 may win in CSE. Otherwise combine will put the shifts back
4819 together again. This can be called by mips_function_arg, so we must
4820 be careful not to allocate a new register if we've reached the
4824 && GET_CODE (operands[2]) == CONST_INT
4825 && INTVAL (operands[2]) > 8
4826 && INTVAL (operands[2]) <= 16
4827 && !reload_in_progress
4828 && !reload_completed)
4830 rtx temp = gen_reg_rtx (<MODE>mode);
4832 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4833 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4834 GEN_INT (INTVAL (operands[2]) - 8)));
4839 (define_insn "*<optab><mode>3"
4840 [(set (match_operand:GPR 0 "register_operand" "=d")
4841 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4842 (match_operand:SI 2 "arith_operand" "dI")))]
4845 if (GET_CODE (operands[2]) == CONST_INT)
4846 operands[2] = GEN_INT (INTVAL (operands[2])
4847 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4849 return "<d><insn>\t%0,%1,%2";
4851 [(set_attr "type" "shift")
4852 (set_attr "mode" "<MODE>")])
4854 (define_insn "*<optab>si3_extend"
4855 [(set (match_operand:DI 0 "register_operand" "=d")
4857 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4858 (match_operand:SI 2 "arith_operand" "dI"))))]
4859 "TARGET_64BIT && !TARGET_MIPS16"
4861 if (GET_CODE (operands[2]) == CONST_INT)
4862 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4864 return "<insn>\t%0,%1,%2";
4866 [(set_attr "type" "shift")
4867 (set_attr "mode" "SI")])
4869 (define_insn "*<optab>si3_mips16"
4870 [(set (match_operand:SI 0 "register_operand" "=d,d")
4871 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4872 (match_operand:SI 2 "arith_operand" "d,I")))]
4875 if (which_alternative == 0)
4876 return "<insn>\t%0,%2";
4878 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4879 return "<insn>\t%0,%1,%2";
4881 [(set_attr "type" "shift")
4882 (set_attr "mode" "SI")
4883 (set_attr_alternative "length"
4885 (if_then_else (match_operand 2 "m16_uimm3_b")
4889 ;; We need separate DImode MIPS16 patterns because of the irregularity
4891 (define_insn "*ashldi3_mips16"
4892 [(set (match_operand:DI 0 "register_operand" "=d,d")
4893 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4894 (match_operand:SI 2 "arith_operand" "d,I")))]
4895 "TARGET_64BIT && TARGET_MIPS16"
4897 if (which_alternative == 0)
4898 return "dsll\t%0,%2";
4900 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4901 return "dsll\t%0,%1,%2";
4903 [(set_attr "type" "shift")
4904 (set_attr "mode" "DI")
4905 (set_attr_alternative "length"
4907 (if_then_else (match_operand 2 "m16_uimm3_b")
4911 (define_insn "*ashrdi3_mips16"
4912 [(set (match_operand:DI 0 "register_operand" "=d,d")
4913 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4914 (match_operand:SI 2 "arith_operand" "d,I")))]
4915 "TARGET_64BIT && TARGET_MIPS16"
4917 if (GET_CODE (operands[2]) == CONST_INT)
4918 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4920 return "dsra\t%0,%2";
4922 [(set_attr "type" "shift")
4923 (set_attr "mode" "DI")
4924 (set_attr_alternative "length"
4926 (if_then_else (match_operand 2 "m16_uimm3_b")
4930 (define_insn "*lshrdi3_mips16"
4931 [(set (match_operand:DI 0 "register_operand" "=d,d")
4932 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4933 (match_operand:SI 2 "arith_operand" "d,I")))]
4934 "TARGET_64BIT && TARGET_MIPS16"
4936 if (GET_CODE (operands[2]) == CONST_INT)
4937 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4939 return "dsrl\t%0,%2";
4941 [(set_attr "type" "shift")
4942 (set_attr "mode" "DI")
4943 (set_attr_alternative "length"
4945 (if_then_else (match_operand 2 "m16_uimm3_b")
4949 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4952 [(set (match_operand:GPR 0 "d_operand")
4953 (any_shift:GPR (match_operand:GPR 1 "d_operand")
4954 (match_operand:GPR 2 "const_int_operand")))]
4955 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4956 && INTVAL (operands[2]) > 8
4957 && INTVAL (operands[2]) <= 16"
4958 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4959 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4960 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4962 ;; If we load a byte on the mips16 as a bitfield, the resulting
4963 ;; sequence of instructions is too complicated for combine, because it
4964 ;; involves four instructions: a load, a shift, a constant load into a
4965 ;; register, and an and (the key problem here is that the mips16 does
4966 ;; not have and immediate). We recognize a shift of a load in order
4967 ;; to make it simple enough for combine to understand.
4969 ;; The length here is the worst case: the length of the split version
4970 ;; will be more accurate.
4971 (define_insn_and_split ""
4972 [(set (match_operand:SI 0 "register_operand" "=d")
4973 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4974 (match_operand:SI 2 "immediate_operand" "I")))]
4978 [(set (match_dup 0) (match_dup 1))
4979 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4981 [(set_attr "type" "load")
4982 (set_attr "mode" "SI")
4983 (set_attr "length" "16")])
4985 (define_insn "rotr<mode>3"
4986 [(set (match_operand:GPR 0 "register_operand" "=d")
4987 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4988 (match_operand:SI 2 "arith_operand" "dI")))]
4991 if (GET_CODE (operands[2]) == CONST_INT)
4992 gcc_assert (INTVAL (operands[2]) >= 0
4993 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4995 return "<d>ror\t%0,%1,%2";
4997 [(set_attr "type" "shift")
4998 (set_attr "mode" "<MODE>")])
5001 ;; ....................
5005 ;; ....................
5007 ;; Flow here is rather complex:
5009 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
5010 ;; into cmp_operands[] but generates no RTL.
5012 ;; 2) The appropriate branch define_expand is called, which then
5013 ;; creates the appropriate RTL for the comparison and branch.
5014 ;; Different CC modes are used, based on what type of branch is
5015 ;; done, so that we can constrain things appropriately. There
5016 ;; are assumptions in the rest of GCC that break if we fold the
5017 ;; operands into the branches for integer operations, and use cc0
5018 ;; for floating point, so we use the fp status register instead.
5019 ;; If needed, an appropriate temporary is created to hold the
5020 ;; of the integer compare.
5022 (define_expand "cmp<mode>"
5024 (compare:CC (match_operand:GPR 0 "register_operand")
5025 (match_operand:GPR 1 "nonmemory_operand")))]
5028 cmp_operands[0] = operands[0];
5029 cmp_operands[1] = operands[1];
5033 (define_expand "cmp<mode>"
5035 (compare:CC (match_operand:SCALARF 0 "register_operand")
5036 (match_operand:SCALARF 1 "register_operand")))]
5039 cmp_operands[0] = operands[0];
5040 cmp_operands[1] = operands[1];
5045 ;; ....................
5047 ;; CONDITIONAL BRANCHES
5049 ;; ....................
5051 ;; Conditional branches on floating-point equality tests.
5053 (define_insn "*branch_fp"
5056 (match_operator 0 "equality_operator"
5057 [(match_operand:CC 2 "register_operand" "z")
5059 (label_ref (match_operand 1 "" ""))
5063 return mips_output_conditional_branch (insn, operands,
5064 MIPS_BRANCH ("b%F0", "%Z2%1"),
5065 MIPS_BRANCH ("b%W0", "%Z2%1"));
5067 [(set_attr "type" "branch")
5068 (set_attr "mode" "none")])
5070 (define_insn "*branch_fp_inverted"
5073 (match_operator 0 "equality_operator"
5074 [(match_operand:CC 2 "register_operand" "z")
5077 (label_ref (match_operand 1 "" ""))))]
5080 return mips_output_conditional_branch (insn, operands,
5081 MIPS_BRANCH ("b%W0", "%Z2%1"),
5082 MIPS_BRANCH ("b%F0", "%Z2%1"));
5084 [(set_attr "type" "branch")
5085 (set_attr "mode" "none")])
5087 ;; Conditional branches on ordered comparisons with zero.
5089 (define_insn "*branch_order<mode>"
5092 (match_operator 0 "order_operator"
5093 [(match_operand:GPR 2 "register_operand" "d")
5095 (label_ref (match_operand 1 "" ""))
5098 { return mips_output_order_conditional_branch (insn, operands, false); }
5099 [(set_attr "type" "branch")
5100 (set_attr "mode" "none")])
5102 (define_insn "*branch_order<mode>_inverted"
5105 (match_operator 0 "order_operator"
5106 [(match_operand:GPR 2 "register_operand" "d")
5109 (label_ref (match_operand 1 "" ""))))]
5111 { return mips_output_order_conditional_branch (insn, operands, true); }
5112 [(set_attr "type" "branch")
5113 (set_attr "mode" "none")])
5115 ;; Conditional branch on equality comparison.
5117 (define_insn "*branch_equality<mode>"
5120 (match_operator 0 "equality_operator"
5121 [(match_operand:GPR 2 "register_operand" "d")
5122 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5123 (label_ref (match_operand 1 "" ""))
5127 return mips_output_conditional_branch (insn, operands,
5128 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
5129 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
5131 [(set_attr "type" "branch")
5132 (set_attr "mode" "none")])
5134 (define_insn "*branch_equality<mode>_inverted"
5137 (match_operator 0 "equality_operator"
5138 [(match_operand:GPR 2 "register_operand" "d")
5139 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5141 (label_ref (match_operand 1 "" ""))))]
5144 return mips_output_conditional_branch (insn, operands,
5145 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
5146 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
5148 [(set_attr "type" "branch")
5149 (set_attr "mode" "none")])
5153 (define_insn "*branch_equality<mode>_mips16"
5156 (match_operator 0 "equality_operator"
5157 [(match_operand:GPR 1 "register_operand" "d,t")
5159 (match_operand 2 "pc_or_label_operand" "")
5160 (match_operand 3 "pc_or_label_operand" "")))]
5163 if (operands[2] != pc_rtx)
5165 if (which_alternative == 0)
5166 return "b%C0z\t%1,%2";
5168 return "bt%C0z\t%2";
5172 if (which_alternative == 0)
5173 return "b%N0z\t%1,%3";
5175 return "bt%N0z\t%3";
5178 [(set_attr "type" "branch")
5179 (set_attr "mode" "none")])
5181 (define_expand "b<code>"
5183 (if_then_else (any_cond:CC (cc0)
5185 (label_ref (match_operand 0 ""))
5189 mips_expand_conditional_branch (operands, <CODE>);
5193 ;; Used to implement built-in functions.
5194 (define_expand "condjump"
5196 (if_then_else (match_operand 0)
5197 (label_ref (match_operand 1))
5200 ;; Branch if bit is set/clear.
5202 (define_insn "*branch_bit<bbv><mode>"
5205 (equality_op (zero_extract:GPR
5206 (match_operand:GPR 0 "register_operand" "d")
5208 (match_operand 2 "const_int_operand" ""))
5210 (label_ref (match_operand 1 ""))
5212 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5215 mips_output_conditional_branch (insn, operands,
5216 MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"),
5217 MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"));
5219 [(set_attr "type" "branch")
5220 (set_attr "mode" "none")
5221 (set_attr "branch_likely" "no")])
5223 (define_insn "*branch_bit<bbv><mode>_inverted"
5226 (equality_op (zero_extract:GPR
5227 (match_operand:GPR 0 "register_operand" "d")
5229 (match_operand 2 "const_int_operand" ""))
5232 (label_ref (match_operand 1 ""))))]
5233 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5236 mips_output_conditional_branch (insn, operands,
5237 MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"),
5238 MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"));
5240 [(set_attr "type" "branch")
5241 (set_attr "mode" "none")
5242 (set_attr "branch_likely" "no")])
5245 ;; ....................
5247 ;; SETTING A REGISTER FROM A COMPARISON
5249 ;; ....................
5251 ;; Destination is always set in SI mode.
5253 (define_expand "seq"
5254 [(set (match_operand:SI 0 "register_operand")
5255 (eq:SI (match_dup 1)
5258 { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
5260 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5261 [(set (match_operand:GPR2 0 "register_operand" "=d")
5262 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5264 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5266 [(set_attr "type" "slt")
5267 (set_attr "mode" "<GPR:MODE>")])
5269 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5270 [(set (match_operand:GPR2 0 "register_operand" "=t")
5271 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5273 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5275 [(set_attr "type" "slt")
5276 (set_attr "mode" "<GPR:MODE>")])
5278 ;; Generate sltiu unless using seq results in better code.
5279 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5280 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5281 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5282 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5288 [(set_attr "type" "slt")
5289 (set_attr "mode" "<GPR:MODE>")])
5291 ;; "sne" uses sltu instructions in which the first operand is $0.
5292 ;; This isn't possible in mips16 code.
5294 (define_expand "sne"
5295 [(set (match_operand:SI 0 "register_operand")
5296 (ne:SI (match_dup 1)
5299 { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
5301 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5302 [(set (match_operand:GPR2 0 "register_operand" "=d")
5303 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5305 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5307 [(set_attr "type" "slt")
5308 (set_attr "mode" "<GPR:MODE>")])
5310 ;; Generate sltu unless using sne results in better code.
5311 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5312 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5313 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5314 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5320 [(set_attr "type" "slt")
5321 (set_attr "mode" "<GPR:MODE>")])
5323 (define_expand "sgt<u>"
5324 [(set (match_operand:SI 0 "register_operand")
5325 (any_gt:SI (match_dup 1)
5328 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5330 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5331 [(set (match_operand:GPR2 0 "register_operand" "=d")
5332 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5333 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5336 [(set_attr "type" "slt")
5337 (set_attr "mode" "<GPR:MODE>")])
5339 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5340 [(set (match_operand:GPR2 0 "register_operand" "=t")
5341 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5342 (match_operand:GPR 2 "register_operand" "d")))]
5345 [(set_attr "type" "slt")
5346 (set_attr "mode" "<GPR:MODE>")])
5348 (define_expand "sge<u>"
5349 [(set (match_operand:SI 0 "register_operand")
5350 (any_ge:SI (match_dup 1)
5353 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5355 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5356 [(set (match_operand:GPR2 0 "register_operand" "=d")
5357 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5361 [(set_attr "type" "slt")
5362 (set_attr "mode" "<GPR:MODE>")])
5364 (define_expand "slt<u>"
5365 [(set (match_operand:SI 0 "register_operand")
5366 (any_lt:SI (match_dup 1)
5369 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5371 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5372 [(set (match_operand:GPR2 0 "register_operand" "=d")
5373 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5374 (match_operand:GPR 2 "arith_operand" "dI")))]
5377 [(set_attr "type" "slt")
5378 (set_attr "mode" "<GPR:MODE>")])
5380 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5381 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5382 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5383 (match_operand:GPR 2 "arith_operand" "d,I")))]
5386 [(set_attr "type" "slt")
5387 (set_attr "mode" "<GPR:MODE>")
5388 (set_attr_alternative "length"
5390 (if_then_else (match_operand 2 "m16_uimm8_1")
5394 (define_expand "sle<u>"
5395 [(set (match_operand:SI 0 "register_operand")
5396 (any_le:SI (match_dup 1)
5399 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5401 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5402 [(set (match_operand:GPR2 0 "register_operand" "=d")
5403 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5404 (match_operand:GPR 2 "sle_operand" "")))]
5407 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5408 return "slt<u>\t%0,%1,%2";
5410 [(set_attr "type" "slt")
5411 (set_attr "mode" "<GPR:MODE>")])
5413 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5414 [(set (match_operand:GPR2 0 "register_operand" "=t")
5415 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5416 (match_operand:GPR 2 "sle_operand" "")))]
5419 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5420 return "slt<u>\t%1,%2";
5422 [(set_attr "type" "slt")
5423 (set_attr "mode" "<GPR:MODE>")
5424 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5429 ;; ....................
5431 ;; FLOATING POINT COMPARISONS
5433 ;; ....................
5435 (define_insn "s<code>_<mode>"
5436 [(set (match_operand:CC 0 "register_operand" "=z")
5437 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5438 (match_operand:SCALARF 2 "register_operand" "f")))]
5440 "c.<fcond>.<fmt>\t%Z0%1,%2"
5441 [(set_attr "type" "fcmp")
5442 (set_attr "mode" "FPSW")])
5444 (define_insn "s<code>_<mode>"
5445 [(set (match_operand:CC 0 "register_operand" "=z")
5446 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5447 (match_operand:SCALARF 2 "register_operand" "f")))]
5449 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5450 [(set_attr "type" "fcmp")
5451 (set_attr "mode" "FPSW")])
5454 ;; ....................
5456 ;; UNCONDITIONAL BRANCHES
5458 ;; ....................
5460 ;; Unconditional branches.
5464 (label_ref (match_operand 0 "" "")))]
5469 if (get_attr_length (insn) <= 8)
5470 return "%*b\t%l0%/";
5473 output_asm_insn (mips_output_load_label (), operands);
5474 return "%*jr\t%@%/%]";
5478 return "%*j\t%l0%/";
5480 [(set_attr "type" "jump")
5481 (set_attr "mode" "none")
5482 (set (attr "length")
5483 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5484 ;; in range, otherwise load the address of the branch target into
5485 ;; $at and then jump to it.
5487 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5488 (lt (abs (minus (match_dup 0)
5489 (plus (pc) (const_int 4))))
5490 (const_int 131072)))
5491 (const_int 4) (const_int 16)))])
5493 ;; We need a different insn for the mips16, because a mips16 branch
5494 ;; does not have a delay slot.
5498 (label_ref (match_operand 0 "" "")))]
5501 [(set_attr "type" "branch")
5502 (set_attr "mode" "none")])
5504 (define_expand "indirect_jump"
5505 [(set (pc) (match_operand 0 "register_operand"))]
5508 operands[0] = force_reg (Pmode, operands[0]);
5509 if (Pmode == SImode)
5510 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5512 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5516 (define_insn "indirect_jump<mode>"
5517 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5520 [(set_attr "type" "jump")
5521 (set_attr "mode" "none")])
5523 (define_expand "tablejump"
5525 (match_operand 0 "register_operand"))
5526 (use (label_ref (match_operand 1 "")))]
5529 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5530 operands[0] = expand_binop (Pmode, add_optab,
5531 convert_to_mode (Pmode, operands[0], false),
5532 gen_rtx_LABEL_REF (Pmode, operands[1]),
5534 else if (TARGET_GPWORD)
5535 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5536 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5537 else if (TARGET_RTP_PIC)
5539 /* When generating RTP PIC, we use case table entries that are relative
5540 to the start of the function. Add the function's address to the
5542 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5543 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5544 start, 0, 0, OPTAB_WIDEN);
5547 if (Pmode == SImode)
5548 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5550 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5554 (define_insn "tablejump<mode>"
5556 (match_operand:P 0 "register_operand" "d"))
5557 (use (label_ref (match_operand 1 "" "")))]
5560 [(set_attr "type" "jump")
5561 (set_attr "mode" "none")])
5563 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5564 ;; While it is possible to either pull it off the stack (in the
5565 ;; o32 case) or recalculate it given t9 and our target label,
5566 ;; it takes 3 or 4 insns to do so.
5568 (define_expand "builtin_setjmp_setup"
5569 [(use (match_operand 0 "register_operand"))]
5574 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5575 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5579 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5580 ;; that older code did recalculate the gp from $25. Continue to jump through
5581 ;; $25 for compatibility (we lose nothing by doing so).
5583 (define_expand "builtin_longjmp"
5584 [(use (match_operand 0 "register_operand"))]
5587 /* The elements of the buffer are, in order: */
5588 int W = GET_MODE_SIZE (Pmode);
5589 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5590 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5591 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5592 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5593 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5594 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5595 The target is bound to be using $28 as the global pointer
5596 but the current function might not be. */
5597 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5599 /* This bit is similar to expand_builtin_longjmp except that it
5600 restores $gp as well. */
5601 mips_emit_move (hard_frame_pointer_rtx, fp);
5602 mips_emit_move (pv, lab);
5603 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5604 mips_emit_move (gp, gpv);
5605 emit_use (hard_frame_pointer_rtx);
5606 emit_use (stack_pointer_rtx);
5608 emit_indirect_jump (pv);
5613 ;; ....................
5615 ;; Function prologue/epilogue
5617 ;; ....................
5620 (define_expand "prologue"
5624 mips_expand_prologue ();
5628 ;; Block any insns from being moved before this point, since the
5629 ;; profiling call to mcount can use various registers that aren't
5630 ;; saved or used to pass arguments.
5632 (define_insn "blockage"
5633 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5636 [(set_attr "type" "ghost")
5637 (set_attr "mode" "none")])
5639 (define_expand "epilogue"
5643 mips_expand_epilogue (false);
5647 (define_expand "sibcall_epilogue"
5651 mips_expand_epilogue (true);
5655 ;; Trivial return. Make it look like a normal return insn as that
5656 ;; allows jump optimizations to work better.
5658 (define_expand "return"
5660 "mips_can_use_return_insn ()"
5661 { mips_expand_before_return (); })
5663 (define_insn "*return"
5665 "mips_can_use_return_insn ()"
5667 [(set_attr "type" "jump")
5668 (set_attr "mode" "none")])
5672 (define_insn "return_internal"
5674 (use (match_operand 0 "pmode_register_operand" ""))]
5677 [(set_attr "type" "jump")
5678 (set_attr "mode" "none")])
5680 ;; This is used in compiling the unwind routines.
5681 (define_expand "eh_return"
5682 [(use (match_operand 0 "general_operand"))]
5685 if (GET_MODE (operands[0]) != word_mode)
5686 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5688 emit_insn (gen_eh_set_lr_di (operands[0]));
5690 emit_insn (gen_eh_set_lr_si (operands[0]));
5694 ;; Clobber the return address on the stack. We can't expand this
5695 ;; until we know where it will be put in the stack frame.
5697 (define_insn "eh_set_lr_si"
5698 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5699 (clobber (match_scratch:SI 1 "=&d"))]
5703 (define_insn "eh_set_lr_di"
5704 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5705 (clobber (match_scratch:DI 1 "=&d"))]
5710 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5711 (clobber (match_scratch 1))]
5715 mips_set_return_address (operands[0], operands[1]);
5719 (define_expand "exception_receiver"
5723 /* See the comment above load_call<mode> for details. */
5724 emit_insn (gen_set_got_version ());
5726 /* If we have a call-clobbered $gp, restore it from its save slot. */
5727 if (HAVE_restore_gp)
5728 emit_insn (gen_restore_gp ());
5732 (define_expand "nonlocal_goto_receiver"
5736 /* See the comment above load_call<mode> for details. */
5737 emit_insn (gen_set_got_version ());
5741 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5742 ;; volatile until all uses of $28 are exposed.
5743 (define_insn_and_split "restore_gp"
5745 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
5746 (clobber (match_scratch:SI 0 "=&d"))]
5747 "TARGET_CALL_CLOBBERED_GP"
5749 "&& reload_completed"
5752 mips_restore_gp (operands[0]);
5755 [(set_attr "type" "load")
5756 (set_attr "length" "12")])
5759 ;; ....................
5763 ;; ....................
5765 ;; Instructions to load a call address from the GOT. The address might
5766 ;; point to a function or to a lazy binding stub. In the latter case,
5767 ;; the stub will use the dynamic linker to resolve the function, which
5768 ;; in turn will change the GOT entry to point to the function's real
5771 ;; This means that every call, even pure and constant ones, can
5772 ;; potentially modify the GOT entry. And once a stub has been called,
5773 ;; we must not call it again.
5775 ;; We represent this restriction using an imaginary, fixed, call-saved
5776 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5777 ;; live throughout the function and to change its value after every
5778 ;; potential call site. This stops any rtx value that uses the register
5779 ;; from being computed before an earlier call. To do this, we:
5781 ;; - Ensure that the register is live on entry to the function,
5782 ;; so that it is never thought to be used uninitalized.
5784 ;; - Ensure that the register is live on exit from the function,
5785 ;; so that it is live throughout.
5787 ;; - Make each call (lazily-bound or not) use the current value
5788 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5789 ;; not moved across call boundaries.
5791 ;; - Add "ghost" definitions of the register to the beginning of
5792 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5793 ;; edges may involve calls that normal paths don't. (E.g. the
5794 ;; unwinding code that handles a non-call exception may change
5795 ;; lazily-bound GOT entries.) We do this by making the
5796 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5797 ;; a set_got_version instruction.
5799 ;; - After each call (lazily-bound or not), use a "ghost"
5800 ;; update_got_version instruction to change the register's value.
5801 ;; This instruction mimics the _possible_ effect of the dynamic
5802 ;; resolver during the call and it remains live even if the call
5803 ;; itself becomes dead.
5805 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5806 ;; The register is therefore not a valid register_operand
5807 ;; and cannot be moved to or from other registers.
5809 ;; Convenience expander that generates the rhs of a load_call<mode> insn.
5810 (define_expand "unspec_call<mode>"
5811 [(unspec:P [(match_operand:P 0)
5813 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL)])
5815 (define_insn "load_call<mode>"
5816 [(set (match_operand:P 0 "register_operand" "=d")
5817 (unspec:P [(match_operand:P 1 "register_operand" "d")
5818 (match_operand:P 2 "immediate_operand" "")
5819 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5821 "<load>\t%0,%R2(%1)"
5822 [(set_attr "got" "load")
5823 (set_attr "mode" "<MODE>")])
5825 (define_insn "set_got_version"
5826 [(set (reg:SI GOT_VERSION_REGNUM)
5827 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5830 [(set_attr "type" "ghost")])
5832 (define_insn "update_got_version"
5833 [(set (reg:SI GOT_VERSION_REGNUM)
5834 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5837 [(set_attr "type" "ghost")])
5839 ;; Sibling calls. All these patterns use jump instructions.
5841 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5842 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5843 ;; is defined in terms of call_insn_operand, the same is true of the
5846 ;; When we use an indirect jump, we need a register that will be
5847 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5848 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5849 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5852 (define_expand "sibcall"
5853 [(parallel [(call (match_operand 0 "")
5854 (match_operand 1 ""))
5855 (use (match_operand 2 "")) ;; next_arg_reg
5856 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5859 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
5860 operands[1], operands[2], false);
5864 (define_insn "sibcall_internal"
5865 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5866 (match_operand 1 "" ""))]
5867 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5868 { return MIPS_CALL ("j", operands, 0); }
5869 [(set_attr "type" "call")])
5871 (define_expand "sibcall_value"
5872 [(parallel [(set (match_operand 0 "")
5873 (call (match_operand 1 "")
5874 (match_operand 2 "")))
5875 (use (match_operand 3 ""))])] ;; next_arg_reg
5878 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
5879 operands[2], operands[3], false);
5883 (define_insn "sibcall_value_internal"
5884 [(set (match_operand 0 "register_operand" "")
5885 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5886 (match_operand 2 "" "")))]
5887 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5888 { return MIPS_CALL ("j", operands, 1); }
5889 [(set_attr "type" "call")])
5891 (define_insn "sibcall_value_multiple_internal"
5892 [(set (match_operand 0 "register_operand" "")
5893 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5894 (match_operand 2 "" "")))
5895 (set (match_operand 3 "register_operand" "")
5896 (call (mem:SI (match_dup 1))
5898 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5899 { return MIPS_CALL ("j", operands, 1); }
5900 [(set_attr "type" "call")])
5902 (define_expand "call"
5903 [(parallel [(call (match_operand 0 "")
5904 (match_operand 1 ""))
5905 (use (match_operand 2 "")) ;; next_arg_reg
5906 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5909 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
5910 operands[1], operands[2], false);
5914 ;; This instruction directly corresponds to an assembly-language "jal".
5915 ;; There are four cases:
5918 ;; Both symbolic and register destinations are OK. The pattern
5919 ;; always expands to a single mips instruction.
5921 ;; - -mabicalls/-mno-explicit-relocs:
5922 ;; Again, both symbolic and register destinations are OK.
5923 ;; The call is treated as a multi-instruction black box.
5925 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5926 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5929 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5930 ;; Only "jal $25" is allowed. The call is actually two instructions:
5931 ;; "jalr $25" followed by an insn to reload $gp.
5933 ;; In the last case, we can generate the individual instructions with
5934 ;; a define_split. There are several things to be wary of:
5936 ;; - We can't expose the load of $gp before reload. If we did,
5937 ;; it might get removed as dead, but reload can introduce new
5938 ;; uses of $gp by rematerializing constants.
5940 ;; - We shouldn't restore $gp after calls that never return.
5941 ;; It isn't valid to insert instructions between a noreturn
5942 ;; call and the following barrier.
5944 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5945 ;; instruction preserves $gp and so have no effect on its liveness.
5946 ;; But once we generate the separate insns, it becomes obvious that
5947 ;; $gp is not live on entry to the call.
5949 ;; ??? The operands[2] = insn check is a hack to make the original insn
5950 ;; available to the splitter.
5951 (define_insn_and_split "call_internal"
5952 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5953 (match_operand 1 "" ""))
5954 (clobber (reg:SI 31))]
5956 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5957 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5960 mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
5963 [(set_attr "jal" "indirect,direct")])
5965 (define_insn "call_split"
5966 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5967 (match_operand 1 "" ""))
5968 (clobber (reg:SI 31))
5969 (clobber (reg:SI 28))]
5970 "TARGET_SPLIT_CALLS"
5971 { return MIPS_CALL ("jal", operands, 0); }
5972 [(set_attr "type" "call")])
5974 ;; A pattern for calls that must be made directly. It is used for
5975 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5976 ;; stub; the linker relies on the call relocation type to detect when
5977 ;; such redirection is needed.
5978 (define_insn_and_split "call_internal_direct"
5979 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5982 (clobber (reg:SI 31))]
5984 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5985 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5988 mips_split_call (operands[2],
5989 gen_call_direct_split (operands[0], operands[1]));
5992 [(set_attr "type" "call")])
5994 (define_insn "call_direct_split"
5995 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5998 (clobber (reg:SI 31))
5999 (clobber (reg:SI 28))]
6000 "TARGET_SPLIT_CALLS"
6001 { return MIPS_CALL ("jal", operands, 0); }
6002 [(set_attr "type" "call")])
6004 (define_expand "call_value"
6005 [(parallel [(set (match_operand 0 "")
6006 (call (match_operand 1 "")
6007 (match_operand 2 "")))
6008 (use (match_operand 3 ""))])] ;; next_arg_reg
6011 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6012 operands[2], operands[3], false);
6016 ;; See comment for call_internal.
6017 (define_insn_and_split "call_value_internal"
6018 [(set (match_operand 0 "register_operand" "")
6019 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6020 (match_operand 2 "" "")))
6021 (clobber (reg:SI 31))]
6023 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6024 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6027 mips_split_call (operands[3],
6028 gen_call_value_split (operands[0], operands[1],
6032 [(set_attr "jal" "indirect,direct")])
6034 (define_insn "call_value_split"
6035 [(set (match_operand 0 "register_operand" "")
6036 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6037 (match_operand 2 "" "")))
6038 (clobber (reg:SI 31))
6039 (clobber (reg:SI 28))]
6040 "TARGET_SPLIT_CALLS"
6041 { return MIPS_CALL ("jal", operands, 1); }
6042 [(set_attr "type" "call")])
6044 ;; See call_internal_direct.
6045 (define_insn_and_split "call_value_internal_direct"
6046 [(set (match_operand 0 "register_operand")
6047 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6050 (clobber (reg:SI 31))]
6052 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6053 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6056 mips_split_call (operands[3],
6057 gen_call_value_direct_split (operands[0], operands[1],
6061 [(set_attr "type" "call")])
6063 (define_insn "call_value_direct_split"
6064 [(set (match_operand 0 "register_operand")
6065 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6068 (clobber (reg:SI 31))
6069 (clobber (reg:SI 28))]
6070 "TARGET_SPLIT_CALLS"
6071 { return MIPS_CALL ("jal", operands, 1); }
6072 [(set_attr "type" "call")])
6074 ;; See comment for call_internal.
6075 (define_insn_and_split "call_value_multiple_internal"
6076 [(set (match_operand 0 "register_operand" "")
6077 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6078 (match_operand 2 "" "")))
6079 (set (match_operand 3 "register_operand" "")
6080 (call (mem:SI (match_dup 1))
6082 (clobber (reg:SI 31))]
6084 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6085 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
6088 mips_split_call (operands[4],
6089 gen_call_value_multiple_split (operands[0], operands[1],
6090 operands[2], operands[3]));
6093 [(set_attr "jal" "indirect,direct")])
6095 (define_insn "call_value_multiple_split"
6096 [(set (match_operand 0 "register_operand" "")
6097 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6098 (match_operand 2 "" "")))
6099 (set (match_operand 3 "register_operand" "")
6100 (call (mem:SI (match_dup 1))
6102 (clobber (reg:SI 31))
6103 (clobber (reg:SI 28))]
6104 "TARGET_SPLIT_CALLS"
6105 { return MIPS_CALL ("jal", operands, 1); }
6106 [(set_attr "type" "call")])
6108 ;; Call subroutine returning any type.
6110 (define_expand "untyped_call"
6111 [(parallel [(call (match_operand 0 "")
6113 (match_operand 1 "")
6114 (match_operand 2 "")])]
6119 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6121 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6123 rtx set = XVECEXP (operands[2], 0, i);
6124 mips_emit_move (SET_DEST (set), SET_SRC (set));
6127 emit_insn (gen_blockage ());
6132 ;; ....................
6136 ;; ....................
6140 (define_insn "prefetch"
6141 [(prefetch (match_operand:QI 0 "address_operand" "p")
6142 (match_operand 1 "const_int_operand" "n")
6143 (match_operand 2 "const_int_operand" "n"))]
6144 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6146 if (TARGET_LOONGSON_2EF)
6147 /* Loongson 2[ef] use load to $0 to perform prefetching. */
6148 return "ld\t$0,%a0";
6149 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6150 return "pref\t%1,%a0";
6152 [(set_attr "type" "prefetch")])
6154 (define_insn "*prefetch_indexed_<mode>"
6155 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6156 (match_operand:P 1 "register_operand" "d"))
6157 (match_operand 2 "const_int_operand" "n")
6158 (match_operand 3 "const_int_operand" "n"))]
6159 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6161 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6162 return "prefx\t%2,%1(%0)";
6164 [(set_attr "type" "prefetchx")])
6170 [(set_attr "type" "nop")
6171 (set_attr "mode" "none")])
6173 ;; Like nop, but commented out when outside a .set noreorder block.
6174 (define_insn "hazard_nop"
6183 [(set_attr "type" "nop")])
6185 ;; MIPS4 Conditional move instructions.
6187 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6188 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6190 (match_operator:MOVECC 4 "equality_operator"
6191 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6193 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6194 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6199 [(set_attr "type" "condmove")
6200 (set_attr "mode" "<GPR:MODE>")])
6202 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6203 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6204 (if_then_else:SCALARF
6205 (match_operator:MOVECC 4 "equality_operator"
6206 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6208 (match_operand:SCALARF 2 "register_operand" "f,0")
6209 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6210 "ISA_HAS_FP_CONDMOVE"
6212 mov%T4.<fmt>\t%0,%2,%1
6213 mov%t4.<fmt>\t%0,%3,%1"
6214 [(set_attr "type" "condmove")
6215 (set_attr "mode" "<SCALARF:MODE>")])
6217 ;; These are the main define_expand's used to make conditional moves.
6219 (define_expand "mov<mode>cc"
6220 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6221 (set (match_operand:GPR 0 "register_operand")
6222 (if_then_else:GPR (match_dup 5)
6223 (match_operand:GPR 2 "reg_or_0_operand")
6224 (match_operand:GPR 3 "reg_or_0_operand")))]
6227 mips_expand_conditional_move (operands);
6231 (define_expand "mov<mode>cc"
6232 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6233 (set (match_operand:SCALARF 0 "register_operand")
6234 (if_then_else:SCALARF (match_dup 5)
6235 (match_operand:SCALARF 2 "register_operand")
6236 (match_operand:SCALARF 3 "register_operand")))]
6237 "ISA_HAS_FP_CONDMOVE"
6239 mips_expand_conditional_move (operands);
6244 ;; ....................
6246 ;; mips16 inline constant tables
6248 ;; ....................
6251 (define_insn "consttable_int"
6252 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6253 (match_operand 1 "const_int_operand" "")]
6254 UNSPEC_CONSTTABLE_INT)]
6257 assemble_integer (operands[0], INTVAL (operands[1]),
6258 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6261 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6263 (define_insn "consttable_float"
6264 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6265 UNSPEC_CONSTTABLE_FLOAT)]
6270 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6271 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6272 assemble_real (d, GET_MODE (operands[0]),
6273 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6276 [(set (attr "length")
6277 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6279 (define_insn "align"
6280 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6283 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6286 [(match_operand 0 "small_data_pattern")]
6289 { operands[0] = mips_rewrite_small_data (operands[0]); })
6292 ;; ....................
6294 ;; MIPS16e Save/Restore
6296 ;; ....................
6299 (define_insn "*mips16e_save_restore"
6300 [(match_parallel 0 ""
6301 [(set (match_operand:SI 1 "register_operand")
6302 (plus:SI (match_dup 1)
6303 (match_operand:SI 2 "const_int_operand")))])]
6304 "operands[1] == stack_pointer_rtx
6305 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6306 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6307 [(set_attr "type" "arith")
6308 (set_attr "extended_mips16" "yes")])
6310 ;; Thread-Local Storage
6312 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6313 ;; MIPS architecture defines this register, and no current
6314 ;; implementation provides it; instead, any OS which supports TLS is
6315 ;; expected to trap and emulate this instruction. rdhwr is part of the
6316 ;; MIPS 32r2 specification, but we use it on any architecture because
6317 ;; we expect it to be emulated. Use .set to force the assembler to
6320 ;; We do not use a constraint to force the destination to be $3
6321 ;; because $3 can appear explicitly as a function return value.
6322 ;; If we leave the use of $3 implicit in the constraints until
6323 ;; reload, we may end up making a $3 return value live across
6324 ;; the instruction, leading to a spill failure when reloading it.
6325 (define_insn_and_split "tls_get_tp_<mode>"
6326 [(set (match_operand:P 0 "register_operand" "=d")
6327 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6328 (clobber (reg:P TLS_GET_TP_REGNUM))]
6329 "HAVE_AS_TLS && !TARGET_MIPS16"
6331 "&& reload_completed"
6332 [(set (reg:P TLS_GET_TP_REGNUM)
6333 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6334 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6336 [(set_attr "type" "unknown")
6337 ; Since rdhwr always generates a trap for now, putting it in a delay
6338 ; slot would make the kernel's emulation of it much slower.
6339 (set_attr "can_delay" "no")
6340 (set_attr "mode" "<MODE>")
6341 (set_attr "length" "8")])
6343 (define_insn "*tls_get_tp_<mode>_split"
6344 [(set (reg:P TLS_GET_TP_REGNUM)
6345 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6346 "HAVE_AS_TLS && !TARGET_MIPS16"
6347 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6348 [(set_attr "type" "unknown")
6349 ; See tls_get_tp_<mode>
6350 (set_attr "can_delay" "no")
6351 (set_attr "mode" "<MODE>")])
6353 ;; Synchronization instructions.
6357 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6359 (include "mips-ps-3d.md")
6361 ; The MIPS DSP Instructions.
6363 (include "mips-dsp.md")
6365 ; The MIPS DSP REV 2 Instructions.
6367 (include "mips-dspr2.md")
6369 ; MIPS fixed-point instructions.
6370 (include "mips-fixed.md")
6372 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6373 (include "loongson.md")