1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
51 (UNSPEC_TLS_GET_TP 30)
54 (UNSPEC_CLEAR_HAZARD 33)
58 (UNSPEC_COMPARE_AND_SWAP 37)
59 (UNSPEC_COMPARE_AND_SWAP_12 38)
60 (UNSPEC_SYNC_OLD_OP 39)
61 (UNSPEC_SYNC_NEW_OP 40)
62 (UNSPEC_SYNC_NEW_OP_12 41)
63 (UNSPEC_SYNC_OLD_OP_12 42)
64 (UNSPEC_SYNC_EXCHANGE 43)
65 (UNSPEC_SYNC_EXCHANGE_12 44)
66 (UNSPEC_MEMORY_BARRIER 45)
67 (UNSPEC_SET_GOT_VERSION 46)
68 (UNSPEC_UPDATE_GOT_VERSION 47)
71 (UNSPEC_ADDRESS_FIRST 100)
74 (GOT_VERSION_REGNUM 79)
76 ;; For MIPS Paired-Singled Floating Point Instructions.
78 (UNSPEC_MOVE_TF_PS 200)
81 ;; MIPS64/MIPS32R2 alnv.ps
84 ;; MIPS-3D instructions
88 (UNSPEC_CVT_PW_PS 205)
89 (UNSPEC_CVT_PS_PW 206)
97 (UNSPEC_SINGLE_CC 213)
100 ;; MIPS DSP ASE Revision 0.98 3/24/2005
108 (UNSPEC_RADDU_W_QB 307)
110 (UNSPEC_PRECRQ_QB_PH 309)
111 (UNSPEC_PRECRQ_PH_W 310)
112 (UNSPEC_PRECRQ_RS_PH_W 311)
113 (UNSPEC_PRECRQU_S_QB_PH 312)
114 (UNSPEC_PRECEQ_W_PHL 313)
115 (UNSPEC_PRECEQ_W_PHR 314)
116 (UNSPEC_PRECEQU_PH_QBL 315)
117 (UNSPEC_PRECEQU_PH_QBR 316)
118 (UNSPEC_PRECEQU_PH_QBLA 317)
119 (UNSPEC_PRECEQU_PH_QBRA 318)
120 (UNSPEC_PRECEU_PH_QBL 319)
121 (UNSPEC_PRECEU_PH_QBR 320)
122 (UNSPEC_PRECEU_PH_QBLA 321)
123 (UNSPEC_PRECEU_PH_QBRA 322)
129 (UNSPEC_MULEU_S_PH_QBL 328)
130 (UNSPEC_MULEU_S_PH_QBR 329)
131 (UNSPEC_MULQ_RS_PH 330)
132 (UNSPEC_MULEQ_S_W_PHL 331)
133 (UNSPEC_MULEQ_S_W_PHR 332)
134 (UNSPEC_DPAU_H_QBL 333)
135 (UNSPEC_DPAU_H_QBR 334)
136 (UNSPEC_DPSU_H_QBL 335)
137 (UNSPEC_DPSU_H_QBR 336)
138 (UNSPEC_DPAQ_S_W_PH 337)
139 (UNSPEC_DPSQ_S_W_PH 338)
140 (UNSPEC_MULSAQ_S_W_PH 339)
141 (UNSPEC_DPAQ_SA_L_W 340)
142 (UNSPEC_DPSQ_SA_L_W 341)
143 (UNSPEC_MAQ_S_W_PHL 342)
144 (UNSPEC_MAQ_S_W_PHR 343)
145 (UNSPEC_MAQ_SA_W_PHL 344)
146 (UNSPEC_MAQ_SA_W_PHR 345)
154 (UNSPEC_CMPGU_EQ_QB 353)
155 (UNSPEC_CMPGU_LT_QB 354)
156 (UNSPEC_CMPGU_LE_QB 355)
158 (UNSPEC_PACKRL_PH 357)
160 (UNSPEC_EXTR_R_W 359)
161 (UNSPEC_EXTR_RS_W 360)
162 (UNSPEC_EXTR_S_H 361)
170 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
171 (UNSPEC_ABSQ_S_QB 400)
173 (UNSPEC_ADDU_S_PH 402)
174 (UNSPEC_ADDUH_QB 403)
175 (UNSPEC_ADDUH_R_QB 404)
178 (UNSPEC_CMPGDU_EQ_QB 407)
179 (UNSPEC_CMPGDU_LT_QB 408)
180 (UNSPEC_CMPGDU_LE_QB 409)
181 (UNSPEC_DPA_W_PH 410)
182 (UNSPEC_DPS_W_PH 411)
188 (UNSPEC_MUL_S_PH 417)
189 (UNSPEC_MULQ_RS_W 418)
190 (UNSPEC_MULQ_S_PH 419)
191 (UNSPEC_MULQ_S_W 420)
192 (UNSPEC_MULSA_W_PH 421)
195 (UNSPEC_PRECR_QB_PH 424)
196 (UNSPEC_PRECR_SRA_PH_W 425)
197 (UNSPEC_PRECR_SRA_R_PH_W 426)
200 (UNSPEC_SHRA_R_QB 429)
203 (UNSPEC_SUBU_S_PH 432)
204 (UNSPEC_SUBUH_QB 433)
205 (UNSPEC_SUBUH_R_QB 434)
206 (UNSPEC_ADDQH_PH 435)
207 (UNSPEC_ADDQH_R_PH 436)
209 (UNSPEC_ADDQH_R_W 438)
210 (UNSPEC_SUBQH_PH 439)
211 (UNSPEC_SUBQH_R_PH 440)
213 (UNSPEC_SUBQH_R_W 442)
214 (UNSPEC_DPAX_W_PH 443)
215 (UNSPEC_DPSX_W_PH 444)
216 (UNSPEC_DPAQX_S_W_PH 445)
217 (UNSPEC_DPAQX_SA_W_PH 446)
218 (UNSPEC_DPSQX_S_W_PH 447)
219 (UNSPEC_DPSQX_SA_W_PH 448)
221 ;; ST Microelectronics Loongson-2E/2F.
222 (UNSPEC_LOONGSON_PAVG 500)
223 (UNSPEC_LOONGSON_PCMPEQ 501)
224 (UNSPEC_LOONGSON_PCMPGT 502)
225 (UNSPEC_LOONGSON_PEXTR 503)
226 (UNSPEC_LOONGSON_PINSR_0 504)
227 (UNSPEC_LOONGSON_PINSR_1 505)
228 (UNSPEC_LOONGSON_PINSR_2 506)
229 (UNSPEC_LOONGSON_PINSR_3 507)
230 (UNSPEC_LOONGSON_PMADD 508)
231 (UNSPEC_LOONGSON_PMOVMSK 509)
232 (UNSPEC_LOONGSON_PMULHU 510)
233 (UNSPEC_LOONGSON_PMULH 511)
234 (UNSPEC_LOONGSON_PMULL 512)
235 (UNSPEC_LOONGSON_PMULU 513)
236 (UNSPEC_LOONGSON_PASUBUB 514)
237 (UNSPEC_LOONGSON_BIADD 515)
238 (UNSPEC_LOONGSON_PSADBH 516)
239 (UNSPEC_LOONGSON_PSHUFH 517)
240 (UNSPEC_LOONGSON_PUNPCKH 518)
241 (UNSPEC_LOONGSON_PUNPCKL 519)
242 (UNSPEC_LOONGSON_PADDD 520)
243 (UNSPEC_LOONGSON_PSUBD 521)
245 ;; Used in loongson2ef.md
246 (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
247 (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
248 (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
249 (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
251 (UNSPEC_MIPS_CACHE 600)
252 (UNSPEC_R10K_CACHE_BARRIER 601)
256 (include "predicates.md")
257 (include "constraints.md")
259 ;; ....................
263 ;; ....................
265 (define_attr "got" "unset,xgot_high,load"
266 (const_string "unset"))
268 ;; For jal instructions, this attribute is DIRECT when the target address
269 ;; is symbolic and INDIRECT when it is a register.
270 (define_attr "jal" "unset,direct,indirect"
271 (const_string "unset"))
273 ;; This attribute is YES if the instruction is a jal macro (not a
274 ;; real jal instruction).
276 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
277 ;; an instruction to restore $gp. Direct jals are also macros for
278 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
279 ;; the target address into a register.
280 (define_attr "jal_macro" "no,yes"
281 (cond [(eq_attr "jal" "direct")
282 (symbol_ref "TARGET_CALL_CLOBBERED_GP
283 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
284 (eq_attr "jal" "indirect")
285 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
286 (const_string "no")))
288 ;; Classification of moves, extensions and truncations. Most values
289 ;; are as for "type" (see below) but there are also the following
290 ;; move-specific values:
292 ;; constN move an N-constraint integer into a MIPS16 register
293 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
294 ;; to produce a sign-extended DEST, even if SRC is not
295 ;; properly sign-extended
296 ;; andi a single ANDI instruction
297 ;; loadpool move a constant into a MIPS16 register by loading it
299 ;; shift_shift a shift left followed by a shift right
300 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
302 ;; This attribute is used to determine the instruction's length and
303 ;; scheduling type. For doubleword moves, the attribute always describes
304 ;; the split instructions; in some cases, it is more appropriate for the
305 ;; scheduling type to be "multi" instead.
306 (define_attr "move_type"
307 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
308 const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
309 (const_string "unknown"))
311 ;; Main data type used by the insn
312 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
313 (const_string "unknown"))
315 ;; True if the main data type is twice the size of a word.
316 (define_attr "dword_mode" "no,yes"
317 (cond [(and (eq_attr "mode" "DI,DF")
318 (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
321 (and (eq_attr "mode" "TI,TF")
322 (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
323 (const_string "yes")]
324 (const_string "no")))
326 ;; Classification of each insn.
327 ;; branch conditional branch
328 ;; jump unconditional jump
329 ;; call unconditional call
330 ;; load load instruction(s)
331 ;; fpload floating point load
332 ;; fpidxload floating point indexed load
333 ;; store store instruction(s)
334 ;; fpstore floating point store
335 ;; fpidxstore floating point indexed store
336 ;; prefetch memory prefetch (register + offset)
337 ;; prefetchx memory indexed prefetch (register + register)
338 ;; condmove conditional moves
339 ;; mtc transfer to coprocessor
340 ;; mfc transfer from coprocessor
341 ;; mthilo transfer to hi/lo registers
342 ;; mfhilo transfer from hi/lo registers
343 ;; const load constant
344 ;; arith integer arithmetic instructions
345 ;; logical integer logical instructions
346 ;; shift integer shift instructions
347 ;; slt set less than instructions
348 ;; signext sign extend instructions
349 ;; clz the clz and clo instructions
350 ;; pop the pop instruction
351 ;; trap trap if instructions
352 ;; imul integer multiply 2 operands
353 ;; imul3 integer multiply 3 operands
354 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
355 ;; imadd integer multiply-add
356 ;; idiv integer divide 2 operands
357 ;; idiv3 integer divide 3 operands
358 ;; move integer register move ({,D}ADD{,U} with rt = 0)
359 ;; fmove floating point register move
360 ;; fadd floating point add/subtract
361 ;; fmul floating point multiply
362 ;; fmadd floating point multiply-add
363 ;; fdiv floating point divide
364 ;; frdiv floating point reciprocal divide
365 ;; frdiv1 floating point reciprocal divide step 1
366 ;; frdiv2 floating point reciprocal divide step 2
367 ;; fabs floating point absolute value
368 ;; fneg floating point negation
369 ;; fcmp floating point compare
370 ;; fcvt floating point convert
371 ;; fsqrt floating point square root
372 ;; frsqrt floating point reciprocal square root
373 ;; frsqrt1 floating point reciprocal square root step1
374 ;; frsqrt2 floating point reciprocal square root step2
375 ;; multi multiword sequence (or user asm statements)
377 ;; ghost an instruction that produces no real code
379 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
380 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
381 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
382 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
383 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
384 (cond [(eq_attr "jal" "!unset") (const_string "call")
385 (eq_attr "got" "load") (const_string "load")
387 ;; If a doubleword move uses these expensive instructions,
388 ;; it is usually better to schedule them in the same way
389 ;; as the singleword form, rather than as "multi".
390 (eq_attr "move_type" "load") (const_string "load")
391 (eq_attr "move_type" "fpload") (const_string "fpload")
392 (eq_attr "move_type" "store") (const_string "store")
393 (eq_attr "move_type" "fpstore") (const_string "fpstore")
394 (eq_attr "move_type" "mtc") (const_string "mtc")
395 (eq_attr "move_type" "mfc") (const_string "mfc")
396 (eq_attr "move_type" "mthilo") (const_string "mthilo")
397 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
399 ;; These types of move are always single insns.
400 (eq_attr "move_type" "fmove") (const_string "fmove")
401 (eq_attr "move_type" "loadpool") (const_string "load")
402 (eq_attr "move_type" "signext") (const_string "signext")
403 (eq_attr "move_type" "sll0") (const_string "shift")
404 (eq_attr "move_type" "andi") (const_string "logical")
406 ;; These types of move are always split.
407 (eq_attr "move_type" "constN,lui_movf,shift_shift")
408 (const_string "multi")
410 ;; These types of move are split for doubleword modes only.
411 (and (eq_attr "move_type" "move,const")
412 (eq_attr "dword_mode" "yes"))
413 (const_string "multi")
414 (eq_attr "move_type" "move") (const_string "move")
415 (eq_attr "move_type" "const") (const_string "const")]
416 (const_string "unknown")))
418 ;; Mode for conversion types (fcvt)
419 ;; I2S integer to float single (SI/DI to SF)
420 ;; I2D integer to float double (SI/DI to DF)
421 ;; S2I float to integer (SF to SI/DI)
422 ;; D2I float to integer (DF to SI/DI)
423 ;; D2S double to float single
424 ;; S2D float single to double
426 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
427 (const_string "unknown"))
429 ;; Is this an extended instruction in mips16 mode?
430 (define_attr "extended_mips16" "no,yes"
431 (if_then_else (ior (eq_attr "move_type" "sll0")
432 (eq_attr "type" "branch")
433 (eq_attr "jal" "direct"))
435 (const_string "no")))
437 ;; Length of instruction in bytes.
438 (define_attr "length" ""
439 (cond [(and (eq_attr "extended_mips16" "yes")
440 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
443 ;; Direct branch instructions have a range of [-0x40000,0x3fffc].
444 ;; If a branch is outside this range, we have a choice of two
445 ;; sequences. For PIC, an out-of-range branch like:
450 ;; becomes the equivalent of:
459 ;; where the load address can be up to three instructions long
462 ;; The non-PIC case is similar except that we use a direct
463 ;; jump instead of an la/jr pair. Since the target of this
464 ;; jump is an absolute 28-bit bit address (the other bits
465 ;; coming from the address of the delay slot) this form cannot
466 ;; cross a 256MB boundary. We could provide the option of
467 ;; using la/jr in this case too, but we do not do so at
470 ;; Note that this value does not account for the delay slot
471 ;; instruction, whose length is added separately. If the RTL
472 ;; pattern has no explicit delay slot, mips_adjust_insn_length
473 ;; will add the length of the implicit nop. The values for
474 ;; forward and backward branches will be different as well.
475 (eq_attr "type" "branch")
476 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
477 (le (minus (pc) (match_dup 1)) (const_int 131068)))
479 (ne (symbol_ref "flag_pic") (const_int 0))
483 ;; "Ghost" instructions occupy no space.
484 (eq_attr "type" "ghost")
487 (eq_attr "got" "load")
488 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
491 (eq_attr "got" "xgot_high")
494 ;; In general, constant-pool loads are extended instructions.
495 (eq_attr "move_type" "loadpool")
498 ;; LUI_MOVFs are decomposed into two separate instructions.
499 (eq_attr "move_type" "lui_movf")
502 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
503 ;; They are extended instructions on MIPS16 targets.
504 (eq_attr "move_type" "shift_shift")
505 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
509 ;; Check for doubleword moves that are decomposed into two
511 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
512 (eq_attr "dword_mode" "yes"))
515 ;; Doubleword CONST{,N} moves are split into two word
517 (and (eq_attr "move_type" "const,constN")
518 (eq_attr "dword_mode" "yes"))
519 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
521 ;; Otherwise, constants, loads and stores are handled by external
523 (eq_attr "move_type" "const,constN")
524 (symbol_ref "mips_const_insns (operands[1]) * 4")
525 (eq_attr "move_type" "load,fpload")
526 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
527 (eq_attr "move_type" "store,fpstore")
528 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
530 ;; In the worst case, a call macro will take 8 instructions:
532 ;; lui $25,%call_hi(FOO)
534 ;; lw $25,%call_lo(FOO)($25)
540 (eq_attr "jal_macro" "yes")
543 ;; Various VR4120 errata require a nop to be inserted after a macc
544 ;; instruction. The assembler does this for us, so account for
545 ;; the worst-case length here.
546 (and (eq_attr "type" "imadd")
547 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
550 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
551 ;; the result of the second one is missed. The assembler should work
552 ;; around this by inserting a nop after the first dmult.
553 (and (eq_attr "type" "imul,imul3")
554 (and (eq_attr "mode" "DI")
555 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
558 (eq_attr "type" "idiv,idiv3")
559 (symbol_ref "mips_idiv_insns () * 4")
562 ;; Attribute describing the processor. This attribute must match exactly
563 ;; with the processor_type enumeration in mips.h.
565 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
566 (const (symbol_ref "mips_tune")))
568 ;; The type of hardware hazard associated with this instruction.
569 ;; DELAY means that the next instruction cannot read the result
570 ;; of this one. HILO means that the next two instructions cannot
571 ;; write to HI or LO.
572 (define_attr "hazard" "none,delay,hilo"
573 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
574 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
575 (const_string "delay")
577 (and (eq_attr "type" "mfc,mtc")
578 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
579 (const_string "delay")
581 (and (eq_attr "type" "fcmp")
582 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
583 (const_string "delay")
585 ;; The r4000 multiplication patterns include an mflo instruction.
586 (and (eq_attr "type" "imul")
587 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
588 (const_string "hilo")
590 (and (eq_attr "type" "mfhilo")
591 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
592 (const_string "hilo")]
593 (const_string "none")))
595 ;; Is it a single instruction?
596 (define_attr "single_insn" "no,yes"
597 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
599 ;; Can the instruction be put into a delay slot?
600 (define_attr "can_delay" "no,yes"
601 (if_then_else (and (eq_attr "type" "!branch,call,jump")
602 (and (eq_attr "hazard" "none")
603 (eq_attr "single_insn" "yes")))
605 (const_string "no")))
607 ;; Attribute defining whether or not we can use the branch-likely
609 (define_attr "branch_likely" "no,yes"
610 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
612 (const_string "no")))
614 ;; True if an instruction might assign to hi or lo when reloaded.
615 ;; This is used by the TUNE_MACC_CHAINS code.
616 (define_attr "may_clobber_hilo" "no,yes"
617 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
619 (const_string "no")))
621 ;; Describe a user's asm statement.
622 (define_asm_attributes
623 [(set_attr "type" "multi")
624 (set_attr "can_delay" "no")])
626 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
627 ;; from the same template.
628 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
630 ;; A copy of GPR that can be used when a pattern has two independent
632 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
634 ;; This mode iterator allows :HILO to be used as the mode of the
635 ;; concatenated HI and LO registers.
636 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
638 ;; This mode iterator allows :P to be used for patterns that operate on
639 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
640 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
642 ;; This mode iterator allows :MOVECC to be used anywhere that a
643 ;; conditional-move-type condition is needed.
644 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
645 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
647 ;; 64-bit modes for which we provide move patterns.
648 (define_mode_iterator MOVE64
650 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
651 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
652 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
653 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
655 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
656 (define_mode_iterator MOVE128 [TI TF])
658 ;; This mode iterator allows the QI and HI extension patterns to be
659 ;; defined from the same template.
660 (define_mode_iterator SHORT [QI HI])
662 ;; Likewise the 64-bit truncate-and-shift patterns.
663 (define_mode_iterator SUBDI [QI HI SI])
665 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
666 ;; floating-point mode is allowed.
667 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
668 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
669 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
671 ;; Like ANYF, but only applies to scalar modes.
672 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
673 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
675 ;; A floating-point mode for which moves involving FPRs may need to be split.
676 (define_mode_iterator SPLITF
677 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
678 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
679 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
680 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
681 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
682 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
683 (TF "TARGET_64BIT && TARGET_FLOAT64")])
685 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
686 ;; 32-bit version and "dsubu" in the 64-bit version.
687 (define_mode_attr d [(SI "") (DI "d")
688 (QQ "") (HQ "") (SQ "") (DQ "d")
689 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
690 (HA "") (SA "") (DA "d")
691 (UHA "") (USA "") (UDA "d")])
693 ;; Same as d but upper-case.
694 (define_mode_attr D [(SI "") (DI "D")
695 (QQ "") (HQ "") (SQ "") (DQ "D")
696 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
697 (HA "") (SA "") (DA "D")
698 (UHA "") (USA "") (UDA "D")])
700 ;; This attribute gives the length suffix for a sign- or zero-extension
702 (define_mode_attr size [(QI "b") (HI "h")])
704 ;; This attributes gives the mode mask of a SHORT.
705 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
707 ;; Mode attributes for GPR loads and stores.
708 (define_mode_attr load [(SI "lw") (DI "ld")])
709 (define_mode_attr store [(SI "sw") (DI "sd")])
711 ;; Similarly for MIPS IV indexed FPR loads and stores.
712 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
713 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
715 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
716 ;; are different. Some forms of unextended addiu have an 8-bit immediate
717 ;; field but the equivalent daddiu has only a 5-bit field.
718 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
720 ;; This attribute gives the best constraint to use for registers of
722 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
724 ;; This attribute gives the format suffix for floating-point operations.
725 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
727 ;; This attribute gives the upper-case mode name for one unit of a
728 ;; floating-point mode.
729 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
731 ;; This attribute gives the integer mode that has the same size as a
733 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
734 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
735 (HA "HI") (SA "SI") (DA "DI")
736 (UHA "HI") (USA "SI") (UDA "DI")
737 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
738 (V2HQ "SI") (V2HA "SI")])
740 ;; This attribute gives the integer mode that has half the size of
741 ;; the controlling mode.
742 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
743 (V2SI "SI") (V4HI "SI") (V8QI "SI")
746 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
748 ;; In certain cases, div.s and div.ps may have a rounding error
749 ;; and/or wrong inexact flag.
751 ;; Therefore, we only allow div.s if not working around SB-1 rev2
752 ;; errata or if a slight loss of precision is OK.
753 (define_mode_attr divide_condition
754 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
755 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
757 ;; This attribute gives the conditions under which SQRT.fmt instructions
759 (define_mode_attr sqrt_condition
760 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
762 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
763 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
764 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
765 ;; so for safety's sake, we apply this restriction to all targets.
766 (define_mode_attr recip_condition
768 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
769 (V2SF "TARGET_SB1")])
771 ;; This code iterator allows all branch instructions to be generated from
772 ;; a single define_expand template.
773 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
774 eq ne gt ge lt le gtu geu ltu leu])
776 ;; This code iterator allows signed and unsigned widening multiplications
777 ;; to use the same template.
778 (define_code_iterator any_extend [sign_extend zero_extend])
780 ;; This code iterator allows the two right shift instructions to be
781 ;; generated from the same template.
782 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
784 ;; This code iterator allows the three shift instructions to be generated
785 ;; from the same template.
786 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
788 ;; This code iterator allows unsigned and signed division to be generated
789 ;; from the same template.
790 (define_code_iterator any_div [div udiv])
792 ;; This code iterator allows unsigned and signed modulus to be generated
793 ;; from the same template.
794 (define_code_iterator any_mod [mod umod])
796 ;; This code iterator allows all native floating-point comparisons to be
797 ;; generated from the same template.
798 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
800 ;; This code iterator is used for comparisons that can be implemented
801 ;; by swapping the operands.
802 (define_code_iterator swapped_fcond [ge gt unge ungt])
804 ;; Equality operators.
805 (define_code_iterator equality_op [eq ne])
807 ;; These code iterators allow the signed and unsigned scc operations to use
808 ;; the same template.
809 (define_code_iterator any_gt [gt gtu])
810 (define_code_iterator any_ge [ge geu])
811 (define_code_iterator any_lt [lt ltu])
812 (define_code_iterator any_le [le leu])
814 ;; <u> expands to an empty string when doing a signed operation and
815 ;; "u" when doing an unsigned operation.
816 (define_code_attr u [(sign_extend "") (zero_extend "u")
824 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
825 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
827 ;; <optab> expands to the name of the optab for a particular code.
828 (define_code_attr optab [(ashift "ashl")
837 ;; <insn> expands to the name of the insn that implements a particular code.
838 (define_code_attr insn [(ashift "sll")
847 ;; <immediate_insn> expands to the name of the insn that implements
848 ;; a particular code to operate on immediate values.
849 (define_code_attr immediate_insn [(ior "ori")
853 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
854 (define_code_attr fcond [(unordered "un")
862 ;; Similar, but for swapped conditions.
863 (define_code_attr swapped_fcond [(ge "le")
868 ;; The value of the bit when the branch is taken for branch_bit patterns.
869 ;; Comparison is always against zero so this depends on the operator.
870 (define_code_attr bbv [(eq "0") (ne "1")])
872 ;; This is the inverse value of bbv.
873 (define_code_attr bbinv [(eq "1") (ne "0")])
875 ;; .........................
877 ;; Branch, call and jump delay slots
879 ;; .........................
881 (define_delay (and (eq_attr "type" "branch")
882 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
883 (eq_attr "branch_likely" "yes"))
884 [(eq_attr "can_delay" "yes")
886 (eq_attr "can_delay" "yes")])
888 ;; Branches that don't have likely variants do not annul on false.
889 (define_delay (and (eq_attr "type" "branch")
890 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
891 (eq_attr "branch_likely" "no"))
892 [(eq_attr "can_delay" "yes")
896 (define_delay (eq_attr "type" "jump")
897 [(eq_attr "can_delay" "yes")
901 (define_delay (and (eq_attr "type" "call")
902 (eq_attr "jal_macro" "no"))
903 [(eq_attr "can_delay" "yes")
907 ;; Pipeline descriptions.
909 ;; generic.md provides a fallback for processors without a specific
910 ;; pipeline description. It is derived from the old define_function_unit
911 ;; version and uses the "alu" and "imuldiv" units declared below.
913 ;; Some of the processor-specific files are also derived from old
914 ;; define_function_unit descriptions and simply override the parts of
915 ;; generic.md that don't apply. The other processor-specific files
916 ;; are self-contained.
917 (define_automaton "alu,imuldiv")
919 (define_cpu_unit "alu" "alu")
920 (define_cpu_unit "imuldiv" "imuldiv")
922 ;; Ghost instructions produce no real code and introduce no hazards.
923 ;; They exist purely to express an effect on dataflow.
924 (define_insn_reservation "ghost" 0
925 (eq_attr "type" "ghost")
946 (include "loongson2ef.md")
947 (include "octeon.md")
951 (include "generic.md")
954 ;; ....................
958 ;; ....................
962 [(trap_if (const_int 1) (const_int 0))]
965 if (ISA_HAS_COND_TRAP)
967 else if (TARGET_MIPS16)
972 [(set_attr "type" "trap")])
974 (define_expand "conditional_trap"
975 [(trap_if (match_operator 0 "comparison_operator"
976 [(match_dup 2) (match_dup 3)])
977 (match_operand 1 "const_int_operand"))]
980 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
981 && operands[1] == const0_rtx)
983 mips_expand_conditional_trap (GET_CODE (operands[0]));
989 (define_insn "*conditional_trap<mode>"
990 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
991 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
992 (match_operand:GPR 2 "arith_operand" "dI")])
996 [(set_attr "type" "trap")])
999 ;; ....................
1003 ;; ....................
1006 (define_insn "add<mode>3"
1007 [(set (match_operand:ANYF 0 "register_operand" "=f")
1008 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1009 (match_operand:ANYF 2 "register_operand" "f")))]
1011 "add.<fmt>\t%0,%1,%2"
1012 [(set_attr "type" "fadd")
1013 (set_attr "mode" "<UNITMODE>")])
1015 (define_expand "add<mode>3"
1016 [(set (match_operand:GPR 0 "register_operand")
1017 (plus:GPR (match_operand:GPR 1 "register_operand")
1018 (match_operand:GPR 2 "arith_operand")))]
1021 (define_insn "*add<mode>3"
1022 [(set (match_operand:GPR 0 "register_operand" "=d,d")
1023 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
1024 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1029 [(set_attr "type" "arith")
1030 (set_attr "mode" "<MODE>")])
1032 (define_insn "*add<mode>3_mips16"
1033 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1034 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1035 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1043 [(set_attr "type" "arith")
1044 (set_attr "mode" "<MODE>")
1045 (set_attr_alternative "length"
1046 [(if_then_else (match_operand 2 "m16_simm8_8")
1049 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1052 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1055 (if_then_else (match_operand 2 "m16_simm4_1")
1060 ;; On the mips16, we can sometimes split an add of a constant which is
1061 ;; a 4 byte instruction into two adds which are both 2 byte
1062 ;; instructions. There are two cases: one where we are adding a
1063 ;; constant plus a register to another register, and one where we are
1064 ;; simply adding a constant to a register.
1067 [(set (match_operand:SI 0 "d_operand")
1068 (plus:SI (match_dup 0)
1069 (match_operand:SI 1 "const_int_operand")))]
1070 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1071 && ((INTVAL (operands[1]) > 0x7f
1072 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1073 || (INTVAL (operands[1]) < - 0x80
1074 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1075 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1076 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1078 HOST_WIDE_INT val = INTVAL (operands[1]);
1082 operands[1] = GEN_INT (0x7f);
1083 operands[2] = GEN_INT (val - 0x7f);
1087 operands[1] = GEN_INT (- 0x80);
1088 operands[2] = GEN_INT (val + 0x80);
1093 [(set (match_operand:SI 0 "d_operand")
1094 (plus:SI (match_operand:SI 1 "d_operand")
1095 (match_operand:SI 2 "const_int_operand")))]
1096 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1097 && REGNO (operands[0]) != REGNO (operands[1])
1098 && ((INTVAL (operands[2]) > 0x7
1099 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1100 || (INTVAL (operands[2]) < - 0x8
1101 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1102 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1103 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1105 HOST_WIDE_INT val = INTVAL (operands[2]);
1109 operands[2] = GEN_INT (0x7);
1110 operands[3] = GEN_INT (val - 0x7);
1114 operands[2] = GEN_INT (- 0x8);
1115 operands[3] = GEN_INT (val + 0x8);
1120 [(set (match_operand:DI 0 "d_operand")
1121 (plus:DI (match_dup 0)
1122 (match_operand:DI 1 "const_int_operand")))]
1123 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1124 && ((INTVAL (operands[1]) > 0xf
1125 && INTVAL (operands[1]) <= 0xf + 0xf)
1126 || (INTVAL (operands[1]) < - 0x10
1127 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1128 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1129 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1131 HOST_WIDE_INT val = INTVAL (operands[1]);
1135 operands[1] = GEN_INT (0xf);
1136 operands[2] = GEN_INT (val - 0xf);
1140 operands[1] = GEN_INT (- 0x10);
1141 operands[2] = GEN_INT (val + 0x10);
1146 [(set (match_operand:DI 0 "d_operand")
1147 (plus:DI (match_operand:DI 1 "d_operand")
1148 (match_operand:DI 2 "const_int_operand")))]
1149 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1150 && REGNO (operands[0]) != REGNO (operands[1])
1151 && ((INTVAL (operands[2]) > 0x7
1152 && INTVAL (operands[2]) <= 0x7 + 0xf)
1153 || (INTVAL (operands[2]) < - 0x8
1154 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1155 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1156 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1158 HOST_WIDE_INT val = INTVAL (operands[2]);
1162 operands[2] = GEN_INT (0x7);
1163 operands[3] = GEN_INT (val - 0x7);
1167 operands[2] = GEN_INT (- 0x8);
1168 operands[3] = GEN_INT (val + 0x8);
1172 (define_insn "*addsi3_extended"
1173 [(set (match_operand:DI 0 "register_operand" "=d,d")
1175 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1176 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1177 "TARGET_64BIT && !TARGET_MIPS16"
1181 [(set_attr "type" "arith")
1182 (set_attr "mode" "SI")])
1184 ;; Split this insn so that the addiu splitters can have a crack at it.
1185 ;; Use a conservative length estimate until the split.
1186 (define_insn_and_split "*addsi3_extended_mips16"
1187 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1189 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1190 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1191 "TARGET_64BIT && TARGET_MIPS16"
1193 "&& reload_completed"
1194 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1195 { operands[3] = gen_lowpart (SImode, operands[0]); }
1196 [(set_attr "type" "arith")
1197 (set_attr "mode" "SI")
1198 (set_attr "extended_mips16" "yes")])
1200 ;; Combiner patterns for unsigned byte-add.
1202 (define_insn "*baddu_si_eb"
1203 [(set (match_operand:SI 0 "register_operand" "=d")
1206 (plus:SI (match_operand:SI 1 "register_operand" "d")
1207 (match_operand:SI 2 "register_operand" "d")) 3)))]
1208 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1210 [(set_attr "type" "arith")])
1212 (define_insn "*baddu_si_el"
1213 [(set (match_operand:SI 0 "register_operand" "=d")
1216 (plus:SI (match_operand:SI 1 "register_operand" "d")
1217 (match_operand:SI 2 "register_operand" "d")) 0)))]
1218 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1220 [(set_attr "type" "arith")])
1222 (define_insn "*baddu_di<mode>"
1223 [(set (match_operand:GPR 0 "register_operand" "=d")
1226 (plus:DI (match_operand:DI 1 "register_operand" "d")
1227 (match_operand:DI 2 "register_operand" "d")))))]
1228 "ISA_HAS_BADDU && TARGET_64BIT"
1230 [(set_attr "type" "arith")])
1233 ;; ....................
1237 ;; ....................
1240 (define_insn "sub<mode>3"
1241 [(set (match_operand:ANYF 0 "register_operand" "=f")
1242 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1243 (match_operand:ANYF 2 "register_operand" "f")))]
1245 "sub.<fmt>\t%0,%1,%2"
1246 [(set_attr "type" "fadd")
1247 (set_attr "mode" "<UNITMODE>")])
1249 (define_insn "sub<mode>3"
1250 [(set (match_operand:GPR 0 "register_operand" "=d")
1251 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1252 (match_operand:GPR 2 "register_operand" "d")))]
1255 [(set_attr "type" "arith")
1256 (set_attr "mode" "<MODE>")])
1258 (define_insn "*subsi3_extended"
1259 [(set (match_operand:DI 0 "register_operand" "=d")
1261 (minus:SI (match_operand:SI 1 "register_operand" "d")
1262 (match_operand:SI 2 "register_operand" "d"))))]
1265 [(set_attr "type" "arith")
1266 (set_attr "mode" "DI")])
1269 ;; ....................
1273 ;; ....................
1276 (define_expand "mul<mode>3"
1277 [(set (match_operand:SCALARF 0 "register_operand")
1278 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1279 (match_operand:SCALARF 2 "register_operand")))]
1283 (define_insn "*mul<mode>3"
1284 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1285 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1286 (match_operand:SCALARF 2 "register_operand" "f")))]
1287 "!TARGET_4300_MUL_FIX"
1288 "mul.<fmt>\t%0,%1,%2"
1289 [(set_attr "type" "fmul")
1290 (set_attr "mode" "<MODE>")])
1292 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1293 ;; operands may corrupt immediately following multiplies. This is a
1294 ;; simple fix to insert NOPs.
1296 (define_insn "*mul<mode>3_r4300"
1297 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1298 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1299 (match_operand:SCALARF 2 "register_operand" "f")))]
1300 "TARGET_4300_MUL_FIX"
1301 "mul.<fmt>\t%0,%1,%2\;nop"
1302 [(set_attr "type" "fmul")
1303 (set_attr "mode" "<MODE>")
1304 (set_attr "length" "8")])
1306 (define_insn "mulv2sf3"
1307 [(set (match_operand:V2SF 0 "register_operand" "=f")
1308 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1309 (match_operand:V2SF 2 "register_operand" "f")))]
1310 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1312 [(set_attr "type" "fmul")
1313 (set_attr "mode" "SF")])
1315 ;; The original R4000 has a cpu bug. If a double-word or a variable
1316 ;; shift executes while an integer multiplication is in progress, the
1317 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1318 ;; with the mult on the R4000.
1320 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1321 ;; (also valid for MIPS R4000MC processors):
1323 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1324 ;; this errata description.
1325 ;; The following code sequence causes the R4000 to incorrectly
1326 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1327 ;; instruction. If the dsra32 instruction is executed during an
1328 ;; integer multiply, the dsra32 will only shift by the amount in
1329 ;; specified in the instruction rather than the amount plus 32
1331 ;; instruction 1: mult rs,rt integer multiply
1332 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1333 ;; right arithmetic + 32
1334 ;; Workaround: A dsra32 instruction placed after an integer
1335 ;; multiply should not be one of the 11 instructions after the
1336 ;; multiply instruction."
1340 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1341 ;; the following description.
1342 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1343 ;; 64-bit versions) may produce incorrect results under the
1344 ;; following conditions:
1345 ;; 1) An integer multiply is currently executing
1346 ;; 2) These types of shift instructions are executed immediately
1347 ;; following an integer divide instruction.
1349 ;; 1) Make sure no integer multiply is running wihen these
1350 ;; instruction are executed. If this cannot be predicted at
1351 ;; compile time, then insert a "mfhi" to R0 instruction
1352 ;; immediately after the integer multiply instruction. This
1353 ;; will cause the integer multiply to complete before the shift
1355 ;; 2) Separate integer divide and these two classes of shift
1356 ;; instructions by another instruction or a noop."
1358 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1361 (define_expand "mul<mode>3"
1362 [(set (match_operand:GPR 0 "register_operand")
1363 (mult:GPR (match_operand:GPR 1 "register_operand")
1364 (match_operand:GPR 2 "register_operand")))]
1367 if (TARGET_LOONGSON_2EF)
1368 emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
1370 else if (ISA_HAS_<D>MUL3)
1371 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1372 else if (TARGET_FIX_R4000)
1373 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1376 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1380 (define_insn "mul<mode>3_mul3_ls2ef"
1381 [(set (match_operand:GPR 0 "register_operand" "=d")
1382 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1383 (match_operand:GPR 2 "register_operand" "d")))]
1384 "TARGET_LOONGSON_2EF"
1385 "<d>multu.g\t%0,%1,%2"
1386 [(set_attr "type" "imul3nc")
1387 (set_attr "mode" "<MODE>")])
1389 (define_insn "mul<mode>3_mul3"
1390 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1391 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1392 (match_operand:GPR 2 "register_operand" "d,d")))
1393 (clobber (match_scratch:GPR 3 "=l,X"))]
1396 if (which_alternative == 1)
1397 return "<d>mult\t%1,%2";
1398 if (<MODE>mode == SImode && TARGET_MIPS3900)
1399 return "mult\t%0,%1,%2";
1400 return "<d>mul\t%0,%1,%2";
1402 [(set_attr "type" "imul3,imul")
1403 (set_attr "mode" "<MODE>")])
1405 ;; If a register gets allocated to LO, and we spill to memory, the reload
1406 ;; will include a move from LO to a GPR. Merge it into the multiplication
1407 ;; if it can set the GPR directly.
1410 ;; Operand 1: GPR (1st multiplication operand)
1411 ;; Operand 2: GPR (2nd multiplication operand)
1412 ;; Operand 3: GPR (destination)
1415 [(set (match_operand:SI 0 "lo_operand")
1416 (mult:SI (match_operand:SI 1 "d_operand")
1417 (match_operand:SI 2 "d_operand")))
1418 (clobber (scratch:SI))])
1419 (set (match_operand:SI 3 "d_operand")
1421 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1424 (mult:SI (match_dup 1)
1426 (clobber (match_dup 0))])])
1428 (define_insn "mul<mode>3_internal"
1429 [(set (match_operand:GPR 0 "register_operand" "=l")
1430 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1431 (match_operand:GPR 2 "register_operand" "d")))]
1434 [(set_attr "type" "imul")
1435 (set_attr "mode" "<MODE>")])
1437 (define_insn "mul<mode>3_r4000"
1438 [(set (match_operand:GPR 0 "register_operand" "=d")
1439 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1440 (match_operand:GPR 2 "register_operand" "d")))
1441 (clobber (match_scratch:GPR 3 "=l"))]
1443 "<d>mult\t%1,%2\;mflo\t%0"
1444 [(set_attr "type" "imul")
1445 (set_attr "mode" "<MODE>")
1446 (set_attr "length" "8")])
1448 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1449 ;; of "mult; mflo". They have the same latency, but the first form gives
1450 ;; us an extra cycle to compute the operands.
1453 ;; Operand 1: GPR (1st multiplication operand)
1454 ;; Operand 2: GPR (2nd multiplication operand)
1455 ;; Operand 3: GPR (destination)
1457 [(set (match_operand:SI 0 "lo_operand")
1458 (mult:SI (match_operand:SI 1 "d_operand")
1459 (match_operand:SI 2 "d_operand")))
1460 (set (match_operand:SI 3 "d_operand")
1462 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1467 (plus:SI (mult:SI (match_dup 1)
1471 (plus:SI (mult:SI (match_dup 1)
1475 ;; Multiply-accumulate patterns
1477 ;; This pattern is first matched by combine, which tries to use the
1478 ;; pattern wherever it can. We don't know until later whether it
1479 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1480 ;; so we need to keep both options open.
1482 ;; The second alternative has a "?" marker because it is generally
1483 ;; one instruction more costly than the first alternative. This "?"
1484 ;; marker is enough to convey the relative costs to the register
1487 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1488 ;; reloads of the other operands, even though operands 4 and 5 need no
1489 ;; copy instructions. Reload therefore thinks that the second alternative
1490 ;; is two reloads more costly than the first. We add "*?*?" to the first
1491 ;; alternative as a counterweight.
1492 (define_insn "*mul_acc_si"
1493 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1494 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1495 (match_operand:SI 2 "register_operand" "d,d"))
1496 (match_operand:SI 3 "register_operand" "0,d")))
1497 (clobber (match_scratch:SI 4 "=X,l"))
1498 (clobber (match_scratch:SI 5 "=X,&d"))]
1499 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1503 [(set_attr "type" "imadd")
1504 (set_attr "mode" "SI")
1505 (set_attr "length" "4,8")])
1507 ;; The same idea applies here. The middle alternative needs one less
1508 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1509 (define_insn "*mul_acc_si_r3900"
1510 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1511 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1512 (match_operand:SI 2 "register_operand" "d,d,d"))
1513 (match_operand:SI 3 "register_operand" "0,l,d")))
1514 (clobber (match_scratch:SI 4 "=X,3,l"))
1515 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1516 "TARGET_MIPS3900 && !TARGET_MIPS16"
1521 [(set_attr "type" "imadd")
1522 (set_attr "mode" "SI")
1523 (set_attr "length" "4,4,8")])
1525 ;; Split *mul_acc_si if both the source and destination accumulator
1528 [(set (match_operand:SI 0 "d_operand")
1529 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1530 (match_operand:SI 2 "d_operand"))
1531 (match_operand:SI 3 "d_operand")))
1532 (clobber (match_operand:SI 4 "lo_operand"))
1533 (clobber (match_operand:SI 5 "d_operand"))]
1535 [(parallel [(set (match_dup 5)
1536 (mult:SI (match_dup 1) (match_dup 2)))
1537 (clobber (match_dup 4))])
1538 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1541 (define_insn "*macc"
1542 [(set (match_operand:SI 0 "register_operand" "=l,d")
1543 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1544 (match_operand:SI 2 "register_operand" "d,d"))
1545 (match_operand:SI 3 "register_operand" "0,l")))
1546 (clobber (match_scratch:SI 4 "=X,3"))]
1549 if (which_alternative == 1)
1550 return "macc\t%0,%1,%2";
1551 else if (TARGET_MIPS5500)
1552 return "madd\t%1,%2";
1554 /* The VR4130 assumes that there is a two-cycle latency between a macc
1555 that "writes" to $0 and an instruction that reads from it. We avoid
1556 this by assigning to $1 instead. */
1557 return "%[macc\t%@,%1,%2%]";
1559 [(set_attr "type" "imadd")
1560 (set_attr "mode" "SI")])
1562 (define_insn "*msac"
1563 [(set (match_operand:SI 0 "register_operand" "=l,d")
1564 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1565 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1566 (match_operand:SI 3 "register_operand" "d,d"))))
1567 (clobber (match_scratch:SI 4 "=X,1"))]
1570 if (which_alternative == 1)
1571 return "msac\t%0,%2,%3";
1572 else if (TARGET_MIPS5500)
1573 return "msub\t%2,%3";
1575 return "msac\t$0,%2,%3";
1577 [(set_attr "type" "imadd")
1578 (set_attr "mode" "SI")])
1580 ;; An msac-like instruction implemented using negation and a macc.
1581 (define_insn_and_split "*msac_using_macc"
1582 [(set (match_operand:SI 0 "register_operand" "=l,d")
1583 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1584 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1585 (match_operand:SI 3 "register_operand" "d,d"))))
1586 (clobber (match_scratch:SI 4 "=X,1"))
1587 (clobber (match_scratch:SI 5 "=d,d"))]
1588 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1590 "&& reload_completed"
1592 (neg:SI (match_dup 3)))
1595 (plus:SI (mult:SI (match_dup 2)
1598 (clobber (match_dup 4))])]
1600 [(set_attr "type" "imadd")
1601 (set_attr "length" "8")])
1603 ;; Patterns generated by the define_peephole2 below.
1605 (define_insn "*macc2"
1606 [(set (match_operand:SI 0 "register_operand" "=l")
1607 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1608 (match_operand:SI 2 "register_operand" "d"))
1610 (set (match_operand:SI 3 "register_operand" "=d")
1611 (plus:SI (mult:SI (match_dup 1)
1614 "ISA_HAS_MACC && reload_completed"
1616 [(set_attr "type" "imadd")
1617 (set_attr "mode" "SI")])
1619 (define_insn "*msac2"
1620 [(set (match_operand:SI 0 "register_operand" "=l")
1621 (minus:SI (match_dup 0)
1622 (mult:SI (match_operand:SI 1 "register_operand" "d")
1623 (match_operand:SI 2 "register_operand" "d"))))
1624 (set (match_operand:SI 3 "register_operand" "=d")
1625 (minus:SI (match_dup 0)
1626 (mult:SI (match_dup 1)
1628 "ISA_HAS_MSAC && reload_completed"
1630 [(set_attr "type" "imadd")
1631 (set_attr "mode" "SI")])
1633 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1637 ;; Operand 1: macc/msac
1638 ;; Operand 2: GPR (destination)
1641 [(set (match_operand:SI 0 "lo_operand")
1642 (match_operand:SI 1 "macc_msac_operand"))
1643 (clobber (scratch:SI))])
1644 (set (match_operand:SI 2 "d_operand")
1647 [(parallel [(set (match_dup 0)
1652 ;; When we have a three-address multiplication instruction, it should
1653 ;; be faster to do a separate multiply and add, rather than moving
1654 ;; something into LO in order to use a macc instruction.
1656 ;; This peephole needs a scratch register to cater for the case when one
1657 ;; of the multiplication operands is the same as the destination.
1659 ;; Operand 0: GPR (scratch)
1661 ;; Operand 2: GPR (addend)
1662 ;; Operand 3: GPR (destination)
1663 ;; Operand 4: macc/msac
1664 ;; Operand 5: new multiplication
1665 ;; Operand 6: new addition/subtraction
1667 [(match_scratch:SI 0 "d")
1668 (set (match_operand:SI 1 "lo_operand")
1669 (match_operand:SI 2 "d_operand"))
1672 [(set (match_operand:SI 3 "d_operand")
1673 (match_operand:SI 4 "macc_msac_operand"))
1674 (clobber (match_dup 1))])]
1675 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1676 [(parallel [(set (match_dup 0)
1678 (clobber (match_dup 1))])
1682 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1683 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1684 operands[2], operands[0]);
1687 ;; Same as above, except LO is the initial target of the macc.
1689 ;; Operand 0: GPR (scratch)
1691 ;; Operand 2: GPR (addend)
1692 ;; Operand 3: macc/msac
1693 ;; Operand 4: GPR (destination)
1694 ;; Operand 5: new multiplication
1695 ;; Operand 6: new addition/subtraction
1697 [(match_scratch:SI 0 "d")
1698 (set (match_operand:SI 1 "lo_operand")
1699 (match_operand:SI 2 "d_operand"))
1703 (match_operand:SI 3 "macc_msac_operand"))
1704 (clobber (scratch:SI))])
1706 (set (match_operand:SI 4 "d_operand")
1708 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1709 [(parallel [(set (match_dup 0)
1711 (clobber (match_dup 1))])
1715 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1716 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1717 operands[2], operands[0]);
1720 ;; See the comment above *mul_add_si for details.
1721 (define_insn "*mul_sub_si"
1722 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1723 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1724 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1725 (match_operand:SI 3 "register_operand" "d,d"))))
1726 (clobber (match_scratch:SI 4 "=X,l"))
1727 (clobber (match_scratch:SI 5 "=X,&d"))]
1728 "GENERATE_MADD_MSUB"
1732 [(set_attr "type" "imadd")
1733 (set_attr "mode" "SI")
1734 (set_attr "length" "4,8")])
1736 ;; Split *mul_sub_si if both the source and destination accumulator
1739 [(set (match_operand:SI 0 "d_operand")
1740 (minus:SI (match_operand:SI 1 "d_operand")
1741 (mult:SI (match_operand:SI 2 "d_operand")
1742 (match_operand:SI 3 "d_operand"))))
1743 (clobber (match_operand:SI 4 "lo_operand"))
1744 (clobber (match_operand:SI 5 "d_operand"))]
1746 [(parallel [(set (match_dup 5)
1747 (mult:SI (match_dup 2) (match_dup 3)))
1748 (clobber (match_dup 4))])
1749 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1752 (define_insn "*muls"
1753 [(set (match_operand:SI 0 "register_operand" "=l,d")
1754 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1755 (match_operand:SI 2 "register_operand" "d,d"))))
1756 (clobber (match_scratch:SI 3 "=X,l"))]
1761 [(set_attr "type" "imul,imul3")
1762 (set_attr "mode" "SI")])
1764 (define_expand "<u>mulsidi3"
1765 [(set (match_operand:DI 0 "register_operand")
1766 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1767 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1768 "!TARGET_64BIT || !TARGET_FIX_R4000"
1771 emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
1772 else if (TARGET_FIX_R4000)
1773 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1776 emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
1780 (define_insn "<u>mulsidi3_32bit"
1781 [(set (match_operand:DI 0 "register_operand" "=x")
1782 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1783 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1784 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1786 [(set_attr "type" "imul")
1787 (set_attr "mode" "SI")])
1789 (define_insn "<u>mulsidi3_32bit_r4000"
1790 [(set (match_operand:DI 0 "register_operand" "=d")
1791 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1792 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1793 (clobber (match_scratch:DI 3 "=x"))]
1794 "!TARGET_64BIT && TARGET_FIX_R4000"
1795 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1796 [(set_attr "type" "imul")
1797 (set_attr "mode" "SI")
1798 (set_attr "length" "12")])
1800 (define_insn_and_split "<u>mulsidi3_64bit"
1801 [(set (match_operand:DI 0 "register_operand" "=d")
1802 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1803 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1804 (clobber (match_scratch:TI 3 "=x"))
1805 (clobber (match_scratch:DI 4 "=d"))]
1806 "TARGET_64BIT && !TARGET_FIX_R4000"
1808 "&& reload_completed"
1810 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1811 (any_extend:DI (match_dup 2)))]
1814 ;; OP4 <- LO, OP0 <- HI
1815 (set (match_dup 4) (match_dup 5))
1816 (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1820 (ashift:DI (match_dup 4)
1823 (lshiftrt:DI (match_dup 4)
1826 ;; Shift OP0 into place.
1828 (ashift:DI (match_dup 0)
1831 ;; OR the two halves together
1833 (ior:DI (match_dup 0)
1835 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
1836 [(set_attr "type" "imul")
1837 (set_attr "mode" "SI")
1838 (set_attr "length" "24")])
1840 (define_insn "<u>mulsidi3_64bit_hilo"
1841 [(set (match_operand:TI 0 "register_operand" "=x")
1844 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1845 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1847 "TARGET_64BIT && !TARGET_FIX_R4000"
1849 [(set_attr "type" "imul")
1850 (set_attr "mode" "SI")])
1852 ;; Widening multiply with negation.
1853 (define_insn "*muls<u>_di"
1854 [(set (match_operand:DI 0 "register_operand" "=x")
1857 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1858 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1859 "!TARGET_64BIT && ISA_HAS_MULS"
1861 [(set_attr "type" "imul")
1862 (set_attr "mode" "SI")])
1864 (define_insn "<u>msubsidi4"
1865 [(set (match_operand:DI 0 "register_operand" "=ka")
1867 (match_operand:DI 3 "register_operand" "0")
1869 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1870 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1871 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1874 return "msub<u>\t%q0,%1,%2";
1875 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1876 return "msub<u>\t%1,%2";
1878 return "msac<u>\t$0,%1,%2";
1880 [(set_attr "type" "imadd")
1881 (set_attr "mode" "SI")])
1883 ;; _highpart patterns
1885 (define_expand "<su>mulsi3_highpart"
1886 [(set (match_operand:SI 0 "register_operand")
1889 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1890 (any_extend:DI (match_operand:SI 2 "register_operand")))
1895 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1899 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1904 (define_insn_and_split "<su>mulsi3_highpart_internal"
1905 [(set (match_operand:SI 0 "register_operand" "=d")
1908 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1909 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1911 (clobber (match_scratch:SI 3 "=l"))]
1913 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1914 "&& reload_completed && !TARGET_FIX_R4000"
1921 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1922 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1923 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1927 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1928 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1929 emit_insn (gen_mfhisi_di (operands[0], hilo));
1933 [(set_attr "type" "imul")
1934 (set_attr "mode" "SI")
1935 (set_attr "length" "8")])
1937 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1938 [(set (match_operand:SI 0 "register_operand" "=d")
1942 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1943 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1945 (clobber (match_scratch:SI 3 "=l"))]
1947 "mulhi<u>\t%0,%1,%2"
1948 [(set_attr "type" "imul3")
1949 (set_attr "mode" "SI")])
1951 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1952 [(set (match_operand:SI 0 "register_operand" "=d")
1957 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1958 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1960 (clobber (match_scratch:SI 3 "=l"))]
1962 "mulshi<u>\t%0,%1,%2"
1963 [(set_attr "type" "imul3")
1964 (set_attr "mode" "SI")])
1966 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1967 ;; errata MD(0), which says that dmultu does not always produce the
1969 (define_insn_and_split "<su>muldi3_highpart"
1970 [(set (match_operand:DI 0 "register_operand" "=d")
1973 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1974 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1976 (clobber (match_scratch:DI 3 "=l"))]
1977 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1978 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1979 "&& reload_completed && !TARGET_FIX_R4000"
1984 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1985 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
1986 emit_insn (gen_mfhidi_ti (operands[0], hilo));
1989 [(set_attr "type" "imul")
1990 (set_attr "mode" "DI")
1991 (set_attr "length" "8")])
1993 (define_expand "<u>mulditi3"
1994 [(set (match_operand:TI 0 "register_operand")
1995 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
1996 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
1997 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1999 if (TARGET_FIX_R4000)
2000 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2002 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2007 (define_insn "<u>mulditi3_internal"
2008 [(set (match_operand:TI 0 "register_operand" "=x")
2009 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2010 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2012 && !TARGET_FIX_R4000
2013 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2015 [(set_attr "type" "imul")
2016 (set_attr "mode" "DI")])
2018 (define_insn "<u>mulditi3_r4000"
2019 [(set (match_operand:TI 0 "register_operand" "=d")
2020 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2021 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2022 (clobber (match_scratch:TI 3 "=x"))]
2025 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2026 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2027 [(set_attr "type" "imul")
2028 (set_attr "mode" "DI")
2029 (set_attr "length" "12")])
2031 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2032 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2034 (define_insn "madsi"
2035 [(set (match_operand:SI 0 "register_operand" "+l")
2036 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2037 (match_operand:SI 2 "register_operand" "d"))
2041 [(set_attr "type" "imadd")
2042 (set_attr "mode" "SI")])
2044 (define_insn "<u>maddsidi4"
2045 [(set (match_operand:DI 0 "register_operand" "=ka")
2047 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2048 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2049 (match_operand:DI 3 "register_operand" "0")))]
2050 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
2054 return "mad<u>\t%1,%2";
2055 else if (ISA_HAS_DSPR2)
2056 return "madd<u>\t%q0,%1,%2";
2057 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2058 return "madd<u>\t%1,%2";
2060 /* See comment in *macc. */
2061 return "%[macc<u>\t%@,%1,%2%]";
2063 [(set_attr "type" "imadd")
2064 (set_attr "mode" "SI")])
2066 ;; Floating point multiply accumulate instructions.
2068 (define_insn "*madd4<mode>"
2069 [(set (match_operand:ANYF 0 "register_operand" "=f")
2070 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2071 (match_operand:ANYF 2 "register_operand" "f"))
2072 (match_operand:ANYF 3 "register_operand" "f")))]
2073 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2074 "madd.<fmt>\t%0,%3,%1,%2"
2075 [(set_attr "type" "fmadd")
2076 (set_attr "mode" "<UNITMODE>")])
2078 (define_insn "*madd3<mode>"
2079 [(set (match_operand:ANYF 0 "register_operand" "=f")
2080 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2081 (match_operand:ANYF 2 "register_operand" "f"))
2082 (match_operand:ANYF 3 "register_operand" "0")))]
2083 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2084 "madd.<fmt>\t%0,%1,%2"
2085 [(set_attr "type" "fmadd")
2086 (set_attr "mode" "<UNITMODE>")])
2088 (define_insn "*msub4<mode>"
2089 [(set (match_operand:ANYF 0 "register_operand" "=f")
2090 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2091 (match_operand:ANYF 2 "register_operand" "f"))
2092 (match_operand:ANYF 3 "register_operand" "f")))]
2093 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2094 "msub.<fmt>\t%0,%3,%1,%2"
2095 [(set_attr "type" "fmadd")
2096 (set_attr "mode" "<UNITMODE>")])
2098 (define_insn "*msub3<mode>"
2099 [(set (match_operand:ANYF 0 "register_operand" "=f")
2100 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2101 (match_operand:ANYF 2 "register_operand" "f"))
2102 (match_operand:ANYF 3 "register_operand" "0")))]
2103 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2104 "msub.<fmt>\t%0,%1,%2"
2105 [(set_attr "type" "fmadd")
2106 (set_attr "mode" "<UNITMODE>")])
2108 (define_insn "*nmadd4<mode>"
2109 [(set (match_operand:ANYF 0 "register_operand" "=f")
2110 (neg:ANYF (plus:ANYF
2111 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2112 (match_operand:ANYF 2 "register_operand" "f"))
2113 (match_operand:ANYF 3 "register_operand" "f"))))]
2114 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2115 && TARGET_FUSED_MADD
2116 && HONOR_SIGNED_ZEROS (<MODE>mode)
2117 && !HONOR_NANS (<MODE>mode)"
2118 "nmadd.<fmt>\t%0,%3,%1,%2"
2119 [(set_attr "type" "fmadd")
2120 (set_attr "mode" "<UNITMODE>")])
2122 (define_insn "*nmadd3<mode>"
2123 [(set (match_operand:ANYF 0 "register_operand" "=f")
2124 (neg:ANYF (plus:ANYF
2125 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2126 (match_operand:ANYF 2 "register_operand" "f"))
2127 (match_operand:ANYF 3 "register_operand" "0"))))]
2128 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2129 && TARGET_FUSED_MADD
2130 && HONOR_SIGNED_ZEROS (<MODE>mode)
2131 && !HONOR_NANS (<MODE>mode)"
2132 "nmadd.<fmt>\t%0,%1,%2"
2133 [(set_attr "type" "fmadd")
2134 (set_attr "mode" "<UNITMODE>")])
2136 (define_insn "*nmadd4<mode>_fastmath"
2137 [(set (match_operand:ANYF 0 "register_operand" "=f")
2139 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2140 (match_operand:ANYF 2 "register_operand" "f"))
2141 (match_operand:ANYF 3 "register_operand" "f")))]
2142 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2143 && TARGET_FUSED_MADD
2144 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2145 && !HONOR_NANS (<MODE>mode)"
2146 "nmadd.<fmt>\t%0,%3,%1,%2"
2147 [(set_attr "type" "fmadd")
2148 (set_attr "mode" "<UNITMODE>")])
2150 (define_insn "*nmadd3<mode>_fastmath"
2151 [(set (match_operand:ANYF 0 "register_operand" "=f")
2153 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2154 (match_operand:ANYF 2 "register_operand" "f"))
2155 (match_operand:ANYF 3 "register_operand" "0")))]
2156 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2157 && TARGET_FUSED_MADD
2158 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2159 && !HONOR_NANS (<MODE>mode)"
2160 "nmadd.<fmt>\t%0,%1,%2"
2161 [(set_attr "type" "fmadd")
2162 (set_attr "mode" "<UNITMODE>")])
2164 (define_insn "*nmsub4<mode>"
2165 [(set (match_operand:ANYF 0 "register_operand" "=f")
2166 (neg:ANYF (minus:ANYF
2167 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2168 (match_operand:ANYF 3 "register_operand" "f"))
2169 (match_operand:ANYF 1 "register_operand" "f"))))]
2170 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2171 && TARGET_FUSED_MADD
2172 && HONOR_SIGNED_ZEROS (<MODE>mode)
2173 && !HONOR_NANS (<MODE>mode)"
2174 "nmsub.<fmt>\t%0,%1,%2,%3"
2175 [(set_attr "type" "fmadd")
2176 (set_attr "mode" "<UNITMODE>")])
2178 (define_insn "*nmsub3<mode>"
2179 [(set (match_operand:ANYF 0 "register_operand" "=f")
2180 (neg:ANYF (minus:ANYF
2181 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2182 (match_operand:ANYF 3 "register_operand" "f"))
2183 (match_operand:ANYF 1 "register_operand" "0"))))]
2184 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2185 && TARGET_FUSED_MADD
2186 && HONOR_SIGNED_ZEROS (<MODE>mode)
2187 && !HONOR_NANS (<MODE>mode)"
2188 "nmsub.<fmt>\t%0,%1,%2"
2189 [(set_attr "type" "fmadd")
2190 (set_attr "mode" "<UNITMODE>")])
2192 (define_insn "*nmsub4<mode>_fastmath"
2193 [(set (match_operand:ANYF 0 "register_operand" "=f")
2195 (match_operand:ANYF 1 "register_operand" "f")
2196 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2197 (match_operand:ANYF 3 "register_operand" "f"))))]
2198 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2199 && TARGET_FUSED_MADD
2200 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2201 && !HONOR_NANS (<MODE>mode)"
2202 "nmsub.<fmt>\t%0,%1,%2,%3"
2203 [(set_attr "type" "fmadd")
2204 (set_attr "mode" "<UNITMODE>")])
2206 (define_insn "*nmsub3<mode>_fastmath"
2207 [(set (match_operand:ANYF 0 "register_operand" "=f")
2209 (match_operand:ANYF 1 "register_operand" "f")
2210 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2211 (match_operand:ANYF 3 "register_operand" "0"))))]
2212 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2213 && TARGET_FUSED_MADD
2214 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2215 && !HONOR_NANS (<MODE>mode)"
2216 "nmsub.<fmt>\t%0,%1,%2"
2217 [(set_attr "type" "fmadd")
2218 (set_attr "mode" "<UNITMODE>")])
2221 ;; ....................
2223 ;; DIVISION and REMAINDER
2225 ;; ....................
2228 (define_expand "div<mode>3"
2229 [(set (match_operand:ANYF 0 "register_operand")
2230 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2231 (match_operand:ANYF 2 "register_operand")))]
2232 "<divide_condition>"
2234 if (const_1_operand (operands[1], <MODE>mode))
2235 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2236 operands[1] = force_reg (<MODE>mode, operands[1]);
2239 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2241 ;; If an mfc1 or dmfc1 happens to access the floating point register
2242 ;; file at the same time a long latency operation (div, sqrt, recip,
2243 ;; sqrt) iterates an intermediate result back through the floating
2244 ;; point register file bypass, then instead returning the correct
2245 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2246 ;; result of the long latency operation.
2248 ;; The workaround is to insert an unconditional 'mov' from/to the
2249 ;; long latency op destination register.
2251 (define_insn "*div<mode>3"
2252 [(set (match_operand:ANYF 0 "register_operand" "=f")
2253 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2254 (match_operand:ANYF 2 "register_operand" "f")))]
2255 "<divide_condition>"
2258 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2260 return "div.<fmt>\t%0,%1,%2";
2262 [(set_attr "type" "fdiv")
2263 (set_attr "mode" "<UNITMODE>")
2264 (set (attr "length")
2265 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2269 (define_insn "*recip<mode>3"
2270 [(set (match_operand:ANYF 0 "register_operand" "=f")
2271 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2272 (match_operand:ANYF 2 "register_operand" "f")))]
2273 "<recip_condition> && flag_unsafe_math_optimizations"
2276 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2278 return "recip.<fmt>\t%0,%2";
2280 [(set_attr "type" "frdiv")
2281 (set_attr "mode" "<UNITMODE>")
2282 (set (attr "length")
2283 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2287 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2288 ;; with negative operands. We use special libgcc functions instead.
2289 (define_insn_and_split "divmod<mode>4"
2290 [(set (match_operand:GPR 0 "register_operand" "=l")
2291 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2292 (match_operand:GPR 2 "register_operand" "d")))
2293 (set (match_operand:GPR 3 "register_operand" "=d")
2294 (mod:GPR (match_dup 1)
2296 "!TARGET_FIX_VR4120"
2298 "&& reload_completed"
2305 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2306 emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2307 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2311 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2312 emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2313 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2317 [(set_attr "type" "idiv")
2318 (set_attr "mode" "<MODE>")
2319 (set_attr "length" "8")])
2321 (define_insn_and_split "udivmod<mode>4"
2322 [(set (match_operand:GPR 0 "register_operand" "=l")
2323 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2324 (match_operand:GPR 2 "register_operand" "d")))
2325 (set (match_operand:GPR 3 "register_operand" "=d")
2326 (umod:GPR (match_dup 1)
2337 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2338 emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2339 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2343 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2344 emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2345 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2349 [(set_attr "type" "idiv")
2350 (set_attr "mode" "<MODE>")
2351 (set_attr "length" "8")])
2353 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2354 [(set (match_operand:HILO 0 "register_operand" "=x")
2356 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2357 (match_operand:GPR 2 "register_operand" "d"))]
2360 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2361 [(set_attr "type" "idiv")
2362 (set_attr "mode" "<GPR:MODE>")])
2365 ;; ....................
2369 ;; ....................
2371 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2372 ;; "*div[sd]f3" comment for details).
2374 (define_insn "sqrt<mode>2"
2375 [(set (match_operand:ANYF 0 "register_operand" "=f")
2376 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2380 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2382 return "sqrt.<fmt>\t%0,%1";
2384 [(set_attr "type" "fsqrt")
2385 (set_attr "mode" "<UNITMODE>")
2386 (set (attr "length")
2387 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2391 (define_insn "*rsqrt<mode>a"
2392 [(set (match_operand:ANYF 0 "register_operand" "=f")
2393 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2394 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2395 "<recip_condition> && flag_unsafe_math_optimizations"
2398 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2400 return "rsqrt.<fmt>\t%0,%2";
2402 [(set_attr "type" "frsqrt")
2403 (set_attr "mode" "<UNITMODE>")
2404 (set (attr "length")
2405 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2409 (define_insn "*rsqrt<mode>b"
2410 [(set (match_operand:ANYF 0 "register_operand" "=f")
2411 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2412 (match_operand:ANYF 2 "register_operand" "f"))))]
2413 "<recip_condition> && flag_unsafe_math_optimizations"
2416 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2418 return "rsqrt.<fmt>\t%0,%2";
2420 [(set_attr "type" "frsqrt")
2421 (set_attr "mode" "<UNITMODE>")
2422 (set (attr "length")
2423 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2428 ;; ....................
2432 ;; ....................
2434 ;; Do not use the integer abs macro instruction, since that signals an
2435 ;; exception on -2147483648 (sigh).
2437 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2438 ;; invalid; it does not clear their sign bits. We therefore can't use
2439 ;; abs.fmt if the signs of NaNs matter.
2441 (define_insn "abs<mode>2"
2442 [(set (match_operand:ANYF 0 "register_operand" "=f")
2443 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2444 "!HONOR_NANS (<MODE>mode)"
2446 [(set_attr "type" "fabs")
2447 (set_attr "mode" "<UNITMODE>")])
2450 ;; ...................
2452 ;; Count leading zeroes.
2454 ;; ...................
2457 (define_insn "clz<mode>2"
2458 [(set (match_operand:GPR 0 "register_operand" "=d")
2459 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2462 [(set_attr "type" "clz")
2463 (set_attr "mode" "<MODE>")])
2466 ;; ...................
2468 ;; Count number of set bits.
2470 ;; ...................
2473 (define_insn "popcount<mode>2"
2474 [(set (match_operand:GPR 0 "register_operand" "=d")
2475 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2478 [(set_attr "type" "pop")
2479 (set_attr "mode" "<MODE>")])
2482 ;; ....................
2484 ;; NEGATION and ONE'S COMPLEMENT
2486 ;; ....................
2488 (define_insn "negsi2"
2489 [(set (match_operand:SI 0 "register_operand" "=d")
2490 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2494 return "neg\t%0,%1";
2496 return "subu\t%0,%.,%1";
2498 [(set_attr "type" "arith")
2499 (set_attr "mode" "SI")])
2501 (define_insn "negdi2"
2502 [(set (match_operand:DI 0 "register_operand" "=d")
2503 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2504 "TARGET_64BIT && !TARGET_MIPS16"
2506 [(set_attr "type" "arith")
2507 (set_attr "mode" "DI")])
2509 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2510 ;; invalid; it does not flip their sign bit. We therefore can't use
2511 ;; neg.fmt if the signs of NaNs matter.
2513 (define_insn "neg<mode>2"
2514 [(set (match_operand:ANYF 0 "register_operand" "=f")
2515 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2516 "!HONOR_NANS (<MODE>mode)"
2518 [(set_attr "type" "fneg")
2519 (set_attr "mode" "<UNITMODE>")])
2521 (define_insn "one_cmpl<mode>2"
2522 [(set (match_operand:GPR 0 "register_operand" "=d")
2523 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2527 return "not\t%0,%1";
2529 return "nor\t%0,%.,%1";
2531 [(set_attr "type" "logical")
2532 (set_attr "mode" "<MODE>")])
2535 ;; ....................
2539 ;; ....................
2542 ;; Many of these instructions use trivial define_expands, because we
2543 ;; want to use a different set of constraints when TARGET_MIPS16.
2545 (define_expand "and<mode>3"
2546 [(set (match_operand:GPR 0 "register_operand")
2547 (and:GPR (match_operand:GPR 1 "register_operand")
2548 (match_operand:GPR 2 "uns_arith_operand")))]
2552 operands[2] = force_reg (<MODE>mode, operands[2]);
2555 (define_insn "*and<mode>3"
2556 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2557 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2558 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2563 [(set_attr "type" "logical")
2564 (set_attr "mode" "<MODE>")])
2566 (define_insn "*and<mode>3_mips16"
2567 [(set (match_operand:GPR 0 "register_operand" "=d")
2568 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2569 (match_operand:GPR 2 "register_operand" "d")))]
2572 [(set_attr "type" "logical")
2573 (set_attr "mode" "<MODE>")])
2575 (define_expand "ior<mode>3"
2576 [(set (match_operand:GPR 0 "register_operand")
2577 (ior:GPR (match_operand:GPR 1 "register_operand")
2578 (match_operand:GPR 2 "uns_arith_operand")))]
2582 operands[2] = force_reg (<MODE>mode, operands[2]);
2585 (define_insn "*ior<mode>3"
2586 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2587 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2588 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2593 [(set_attr "type" "logical")
2594 (set_attr "mode" "<MODE>")])
2596 (define_insn "*ior<mode>3_mips16"
2597 [(set (match_operand:GPR 0 "register_operand" "=d")
2598 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2599 (match_operand:GPR 2 "register_operand" "d")))]
2602 [(set_attr "type" "logical")
2603 (set_attr "mode" "<MODE>")])
2605 (define_expand "xor<mode>3"
2606 [(set (match_operand:GPR 0 "register_operand")
2607 (xor:GPR (match_operand:GPR 1 "register_operand")
2608 (match_operand:GPR 2 "uns_arith_operand")))]
2613 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2614 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2615 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2620 [(set_attr "type" "logical")
2621 (set_attr "mode" "<MODE>")])
2624 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2625 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2626 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2632 [(set_attr "type" "logical,arith,arith")
2633 (set_attr "mode" "<MODE>")
2634 (set_attr_alternative "length"
2636 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2641 (define_insn "*nor<mode>3"
2642 [(set (match_operand:GPR 0 "register_operand" "=d")
2643 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2644 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2647 [(set_attr "type" "logical")
2648 (set_attr "mode" "<MODE>")])
2651 ;; ....................
2655 ;; ....................
2659 (define_insn "truncdfsf2"
2660 [(set (match_operand:SF 0 "register_operand" "=f")
2661 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2662 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2664 [(set_attr "type" "fcvt")
2665 (set_attr "cnv_mode" "D2S")
2666 (set_attr "mode" "SF")])
2668 ;; Integer truncation patterns. Truncating SImode values to smaller
2669 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2670 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2671 ;; need to make sure that the lower 32 bits are properly sign-extended
2672 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2673 ;; smaller than SImode is equivalent to two separate truncations:
2676 ;; DI ---> HI == DI ---> SI ---> HI
2677 ;; DI ---> QI == DI ---> SI ---> QI
2679 ;; Step A needs a real instruction but step B does not.
2681 (define_insn "truncdisi2"
2682 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2683 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2688 [(set_attr "move_type" "sll0,store")
2689 (set_attr "mode" "SI")])
2691 (define_insn "truncdihi2"
2692 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2693 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2698 [(set_attr "move_type" "sll0,store")
2699 (set_attr "mode" "SI")])
2701 (define_insn "truncdiqi2"
2702 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2703 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2708 [(set_attr "move_type" "sll0,store")
2709 (set_attr "mode" "SI")])
2711 ;; Combiner patterns to optimize shift/truncate combinations.
2713 (define_insn "*ashr_trunc<mode>"
2714 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2716 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2717 (match_operand:DI 2 "const_arith_operand" ""))))]
2718 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
2720 [(set_attr "type" "shift")
2721 (set_attr "mode" "<MODE>")])
2723 (define_insn "*lshr32_trunc<mode>"
2724 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2726 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2728 "TARGET_64BIT && !TARGET_MIPS16"
2730 [(set_attr "type" "shift")
2731 (set_attr "mode" "<MODE>")])
2733 ;; Logical shift by 32 or more results in proper SI values so
2734 ;; truncation is removed by the middle end.
2735 (define_insn "*<optab>_trunc<mode>_exts"
2736 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2738 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
2739 (match_operand:DI 2 "const_arith_operand" ""))))]
2740 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
2742 [(set_attr "type" "arith")
2743 (set_attr "mode" "<MODE>")])
2745 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
2746 ;; use the shift/truncate patterns above.
2748 (define_insn_and_split "*extenddi_truncate<mode>"
2749 [(set (match_operand:DI 0 "register_operand" "=d")
2751 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2752 "TARGET_64BIT && !TARGET_MIPS16"
2754 "&& reload_completed"
2756 (ashift:DI (match_dup 1)
2759 (ashiftrt:DI (match_dup 2)
2762 operands[2] = gen_lowpart (DImode, operands[0]);
2763 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2766 (define_insn_and_split "*extendsi_truncate<mode>"
2767 [(set (match_operand:SI 0 "register_operand" "=d")
2769 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2770 "TARGET_64BIT && !TARGET_MIPS16"
2772 "&& reload_completed"
2774 (ashift:DI (match_dup 1)
2777 (truncate:SI (ashiftrt:DI (match_dup 2)
2780 operands[2] = gen_lowpart (DImode, operands[0]);
2781 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2784 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2786 (define_insn "*zero_extend<mode>_trunchi"
2787 [(set (match_operand:GPR 0 "register_operand" "=d")
2789 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2790 "TARGET_64BIT && !TARGET_MIPS16"
2791 "andi\t%0,%1,0xffff"
2792 [(set_attr "type" "logical")
2793 (set_attr "mode" "<MODE>")])
2795 (define_insn "*zero_extend<mode>_truncqi"
2796 [(set (match_operand:GPR 0 "register_operand" "=d")
2798 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2799 "TARGET_64BIT && !TARGET_MIPS16"
2801 [(set_attr "type" "logical")
2802 (set_attr "mode" "<MODE>")])
2805 [(set (match_operand:HI 0 "register_operand" "=d")
2807 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2808 "TARGET_64BIT && !TARGET_MIPS16"
2810 [(set_attr "type" "logical")
2811 (set_attr "mode" "HI")])
2814 ;; ....................
2818 ;; ....................
2822 (define_insn_and_split "zero_extendsidi2"
2823 [(set (match_operand:DI 0 "register_operand" "=d,d")
2824 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2829 "&& reload_completed && REG_P (operands[1])"
2831 (ashift:DI (match_dup 1) (const_int 32)))
2833 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2834 { operands[1] = gen_lowpart (DImode, operands[1]); }
2835 [(set_attr "move_type" "shift_shift,load")
2836 (set_attr "mode" "DI")])
2838 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2839 ;; because of TRULY_NOOP_TRUNCATION.
2841 (define_insn_and_split "*clear_upper32"
2842 [(set (match_operand:DI 0 "register_operand" "=d,d")
2843 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2844 (const_int 4294967295)))]
2847 if (which_alternative == 0)
2850 operands[1] = gen_lowpart (SImode, operands[1]);
2851 return "lwu\t%0,%1";
2853 "&& reload_completed && REG_P (operands[1])"
2855 (ashift:DI (match_dup 1) (const_int 32)))
2857 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2859 [(set_attr "move_type" "shift_shift,load")
2860 (set_attr "mode" "DI")])
2862 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2863 [(set (match_operand:GPR 0 "register_operand")
2864 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2867 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2868 && !memory_operand (operands[1], <SHORT:MODE>mode))
2870 emit_insn (gen_and<GPR:mode>3 (operands[0],
2871 gen_lowpart (<GPR:MODE>mode, operands[1]),
2872 force_reg (<GPR:MODE>mode,
2873 GEN_INT (<SHORT:mask>))));
2878 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2879 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2881 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2884 andi\t%0,%1,<SHORT:mask>
2885 l<SHORT:size>u\t%0,%1"
2886 [(set_attr "move_type" "andi,load")
2887 (set_attr "mode" "<GPR:MODE>")])
2889 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2890 [(set (match_operand:GPR 0 "register_operand" "=d")
2891 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2893 "ze<SHORT:size>\t%0"
2894 ;; This instruction is effectively a special encoding of ANDI.
2895 [(set_attr "move_type" "andi")
2896 (set_attr "mode" "<GPR:MODE>")])
2898 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2899 [(set (match_operand:GPR 0 "register_operand" "=d")
2900 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2902 "l<SHORT:size>u\t%0,%1"
2903 [(set_attr "move_type" "load")
2904 (set_attr "mode" "<GPR:MODE>")])
2906 (define_expand "zero_extendqihi2"
2907 [(set (match_operand:HI 0 "register_operand")
2908 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2911 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2913 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2919 (define_insn "*zero_extendqihi2"
2920 [(set (match_operand:HI 0 "register_operand" "=d,d")
2921 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2926 [(set_attr "move_type" "andi,load")
2927 (set_attr "mode" "HI")])
2929 (define_insn "*zero_extendqihi2_mips16"
2930 [(set (match_operand:HI 0 "register_operand" "=d")
2931 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2934 [(set_attr "move_type" "load")
2935 (set_attr "mode" "HI")])
2938 ;; ....................
2942 ;; ....................
2945 ;; Those for integer source operand are ordered widest source type first.
2947 ;; When TARGET_64BIT, all SImode integer registers should already be in
2948 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2949 ;; therefore get rid of register->register instructions if we constrain
2950 ;; the source to be in the same register as the destination.
2952 ;; The register alternative has type "arith" so that the pre-reload
2953 ;; scheduler will treat it as a move. This reflects what happens if
2954 ;; the register alternative needs a reload.
2955 (define_insn_and_split "extendsidi2"
2956 [(set (match_operand:DI 0 "register_operand" "=d,d")
2957 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2962 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2965 emit_note (NOTE_INSN_DELETED);
2968 [(set_attr "move_type" "move,load")
2969 (set_attr "mode" "DI")])
2971 (define_expand "extend<SHORT:mode><GPR:mode>2"
2972 [(set (match_operand:GPR 0 "register_operand")
2973 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2976 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2977 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2978 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2982 l<SHORT:size>\t%0,%1"
2983 [(set_attr "move_type" "signext,load")
2984 (set_attr "mode" "<GPR:MODE>")])
2986 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2987 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2989 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2990 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2993 l<SHORT:size>\t%0,%1"
2994 "&& reload_completed && REG_P (operands[1])"
2995 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2996 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2998 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2999 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3000 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3002 [(set_attr "move_type" "shift_shift,load")
3003 (set_attr "mode" "<GPR:MODE>")])
3005 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3006 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3008 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3011 se<SHORT:size>\t%0,%1
3012 l<SHORT:size>\t%0,%1"
3013 [(set_attr "move_type" "signext,load")
3014 (set_attr "mode" "<GPR:MODE>")])
3016 (define_expand "extendqihi2"
3017 [(set (match_operand:HI 0 "register_operand")
3018 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3021 (define_insn "*extendqihi2_mips16e"
3022 [(set (match_operand:HI 0 "register_operand" "=d,d")
3023 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3028 [(set_attr "move_type" "signext,load")
3029 (set_attr "mode" "SI")])
3031 (define_insn_and_split "*extendqihi2"
3032 [(set (match_operand:HI 0 "register_operand" "=d,d")
3034 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3035 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3039 "&& reload_completed && REG_P (operands[1])"
3040 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3041 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3043 operands[0] = gen_lowpart (SImode, operands[0]);
3044 operands[1] = gen_lowpart (SImode, operands[1]);
3045 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3046 - GET_MODE_BITSIZE (QImode));
3048 [(set_attr "move_type" "shift_shift,load")
3049 (set_attr "mode" "SI")])
3051 (define_insn "*extendqihi2_seb"
3052 [(set (match_operand:HI 0 "register_operand" "=d,d")
3054 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3059 [(set_attr "move_type" "signext,load")
3060 (set_attr "mode" "SI")])
3062 (define_insn "extendsfdf2"
3063 [(set (match_operand:DF 0 "register_operand" "=f")
3064 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3065 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3067 [(set_attr "type" "fcvt")
3068 (set_attr "cnv_mode" "S2D")
3069 (set_attr "mode" "DF")])
3072 ;; ....................
3076 ;; ....................
3078 (define_expand "fix_truncdfsi2"
3079 [(set (match_operand:SI 0 "register_operand")
3080 (fix:SI (match_operand:DF 1 "register_operand")))]
3081 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3083 if (!ISA_HAS_TRUNC_W)
3085 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3090 (define_insn "fix_truncdfsi2_insn"
3091 [(set (match_operand:SI 0 "register_operand" "=f")
3092 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3093 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3095 [(set_attr "type" "fcvt")
3096 (set_attr "mode" "DF")
3097 (set_attr "cnv_mode" "D2I")])
3099 (define_insn "fix_truncdfsi2_macro"
3100 [(set (match_operand:SI 0 "register_operand" "=f")
3101 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3102 (clobber (match_scratch:DF 2 "=d"))]
3103 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3106 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3108 return "trunc.w.d %0,%1,%2";
3110 [(set_attr "type" "fcvt")
3111 (set_attr "mode" "DF")
3112 (set_attr "cnv_mode" "D2I")
3113 (set_attr "length" "36")])
3115 (define_expand "fix_truncsfsi2"
3116 [(set (match_operand:SI 0 "register_operand")
3117 (fix:SI (match_operand:SF 1 "register_operand")))]
3120 if (!ISA_HAS_TRUNC_W)
3122 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3127 (define_insn "fix_truncsfsi2_insn"
3128 [(set (match_operand:SI 0 "register_operand" "=f")
3129 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3130 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3132 [(set_attr "type" "fcvt")
3133 (set_attr "mode" "SF")
3134 (set_attr "cnv_mode" "S2I")])
3136 (define_insn "fix_truncsfsi2_macro"
3137 [(set (match_operand:SI 0 "register_operand" "=f")
3138 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3139 (clobber (match_scratch:SF 2 "=d"))]
3140 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3143 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3145 return "trunc.w.s %0,%1,%2";
3147 [(set_attr "type" "fcvt")
3148 (set_attr "mode" "SF")
3149 (set_attr "cnv_mode" "S2I")
3150 (set_attr "length" "36")])
3153 (define_insn "fix_truncdfdi2"
3154 [(set (match_operand:DI 0 "register_operand" "=f")
3155 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3156 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3158 [(set_attr "type" "fcvt")
3159 (set_attr "mode" "DF")
3160 (set_attr "cnv_mode" "D2I")])
3163 (define_insn "fix_truncsfdi2"
3164 [(set (match_operand:DI 0 "register_operand" "=f")
3165 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3166 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3168 [(set_attr "type" "fcvt")
3169 (set_attr "mode" "SF")
3170 (set_attr "cnv_mode" "S2I")])
3173 (define_insn "floatsidf2"
3174 [(set (match_operand:DF 0 "register_operand" "=f")
3175 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3176 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3178 [(set_attr "type" "fcvt")
3179 (set_attr "mode" "DF")
3180 (set_attr "cnv_mode" "I2D")])
3183 (define_insn "floatdidf2"
3184 [(set (match_operand:DF 0 "register_operand" "=f")
3185 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3186 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3188 [(set_attr "type" "fcvt")
3189 (set_attr "mode" "DF")
3190 (set_attr "cnv_mode" "I2D")])
3193 (define_insn "floatsisf2"
3194 [(set (match_operand:SF 0 "register_operand" "=f")
3195 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3198 [(set_attr "type" "fcvt")
3199 (set_attr "mode" "SF")
3200 (set_attr "cnv_mode" "I2S")])
3203 (define_insn "floatdisf2"
3204 [(set (match_operand:SF 0 "register_operand" "=f")
3205 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3206 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3208 [(set_attr "type" "fcvt")
3209 (set_attr "mode" "SF")
3210 (set_attr "cnv_mode" "I2S")])
3213 (define_expand "fixuns_truncdfsi2"
3214 [(set (match_operand:SI 0 "register_operand")
3215 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3216 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3218 rtx reg1 = gen_reg_rtx (DFmode);
3219 rtx reg2 = gen_reg_rtx (DFmode);
3220 rtx reg3 = gen_reg_rtx (SImode);
3221 rtx label1 = gen_label_rtx ();
3222 rtx label2 = gen_label_rtx ();
3223 REAL_VALUE_TYPE offset;
3225 real_2expN (&offset, 31, DFmode);
3227 if (reg1) /* Turn off complaints about unreached code. */
3229 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3230 do_pending_stack_adjust ();
3232 emit_insn (gen_cmpdf (operands[1], reg1));
3233 emit_jump_insn (gen_bge (label1));
3235 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3236 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3237 gen_rtx_LABEL_REF (VOIDmode, label2)));
3240 emit_label (label1);
3241 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3242 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3243 (BITMASK_HIGH, SImode)));
3245 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3246 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3248 emit_label (label2);
3250 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3251 fields, and can't be used for REG_NOTES anyway). */
3252 emit_use (stack_pointer_rtx);
3258 (define_expand "fixuns_truncdfdi2"
3259 [(set (match_operand:DI 0 "register_operand")
3260 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3261 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3263 rtx reg1 = gen_reg_rtx (DFmode);
3264 rtx reg2 = gen_reg_rtx (DFmode);
3265 rtx reg3 = gen_reg_rtx (DImode);
3266 rtx label1 = gen_label_rtx ();
3267 rtx label2 = gen_label_rtx ();
3268 REAL_VALUE_TYPE offset;
3270 real_2expN (&offset, 63, DFmode);
3272 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3273 do_pending_stack_adjust ();
3275 emit_insn (gen_cmpdf (operands[1], reg1));
3276 emit_jump_insn (gen_bge (label1));
3278 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3279 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3280 gen_rtx_LABEL_REF (VOIDmode, label2)));
3283 emit_label (label1);
3284 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3285 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3286 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3288 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3289 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3291 emit_label (label2);
3293 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3294 fields, and can't be used for REG_NOTES anyway). */
3295 emit_use (stack_pointer_rtx);
3300 (define_expand "fixuns_truncsfsi2"
3301 [(set (match_operand:SI 0 "register_operand")
3302 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3305 rtx reg1 = gen_reg_rtx (SFmode);
3306 rtx reg2 = gen_reg_rtx (SFmode);
3307 rtx reg3 = gen_reg_rtx (SImode);
3308 rtx label1 = gen_label_rtx ();
3309 rtx label2 = gen_label_rtx ();
3310 REAL_VALUE_TYPE offset;
3312 real_2expN (&offset, 31, SFmode);
3314 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3315 do_pending_stack_adjust ();
3317 emit_insn (gen_cmpsf (operands[1], reg1));
3318 emit_jump_insn (gen_bge (label1));
3320 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3321 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3322 gen_rtx_LABEL_REF (VOIDmode, label2)));
3325 emit_label (label1);
3326 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3327 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3328 (BITMASK_HIGH, SImode)));
3330 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3331 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3333 emit_label (label2);
3335 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3336 fields, and can't be used for REG_NOTES anyway). */
3337 emit_use (stack_pointer_rtx);
3342 (define_expand "fixuns_truncsfdi2"
3343 [(set (match_operand:DI 0 "register_operand")
3344 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3345 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3347 rtx reg1 = gen_reg_rtx (SFmode);
3348 rtx reg2 = gen_reg_rtx (SFmode);
3349 rtx reg3 = gen_reg_rtx (DImode);
3350 rtx label1 = gen_label_rtx ();
3351 rtx label2 = gen_label_rtx ();
3352 REAL_VALUE_TYPE offset;
3354 real_2expN (&offset, 63, SFmode);
3356 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3357 do_pending_stack_adjust ();
3359 emit_insn (gen_cmpsf (operands[1], reg1));
3360 emit_jump_insn (gen_bge (label1));
3362 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3363 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3364 gen_rtx_LABEL_REF (VOIDmode, label2)));
3367 emit_label (label1);
3368 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3369 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3370 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3372 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3373 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3375 emit_label (label2);
3377 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3378 fields, and can't be used for REG_NOTES anyway). */
3379 emit_use (stack_pointer_rtx);
3384 ;; ....................
3388 ;; ....................
3390 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3392 (define_expand "extv"
3393 [(set (match_operand 0 "register_operand")
3394 (sign_extract (match_operand 1 "nonimmediate_operand")
3395 (match_operand 2 "const_int_operand")
3396 (match_operand 3 "const_int_operand")))]
3399 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3400 INTVAL (operands[2]),
3401 INTVAL (operands[3])))
3403 else if (register_operand (operands[1], GET_MODE (operands[0]))
3404 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3406 if (GET_MODE (operands[0]) == DImode)
3407 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3410 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3418 (define_insn "extv<mode>"
3419 [(set (match_operand:GPR 0 "register_operand" "=d")
3420 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3421 (match_operand 2 "const_int_operand" "")
3422 (match_operand 3 "const_int_operand" "")))]
3423 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3424 "exts\t%0,%1,%3,%m2"
3425 [(set_attr "type" "arith")
3426 (set_attr "mode" "<MODE>")])
3429 (define_expand "extzv"
3430 [(set (match_operand 0 "register_operand")
3431 (zero_extract (match_operand 1 "nonimmediate_operand")
3432 (match_operand 2 "const_int_operand")
3433 (match_operand 3 "const_int_operand")))]
3436 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3437 INTVAL (operands[2]),
3438 INTVAL (operands[3])))
3440 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3441 INTVAL (operands[3])))
3443 if (GET_MODE (operands[0]) == DImode)
3444 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3447 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3455 (define_insn "extzv<mode>"
3456 [(set (match_operand:GPR 0 "register_operand" "=d")
3457 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3458 (match_operand 2 "const_int_operand" "")
3459 (match_operand 3 "const_int_operand" "")))]
3460 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3461 INTVAL (operands[3]))"
3462 "<d>ext\t%0,%1,%3,%2"
3463 [(set_attr "type" "arith")
3464 (set_attr "mode" "<MODE>")])
3466 (define_insn "*extzv_trunc<mode>_exts"
3467 [(set (match_operand:GPR 0 "register_operand" "=d")
3469 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3470 (match_operand 2 "const_int_operand" "")
3471 (match_operand 3 "const_int_operand" ""))))]
3472 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3474 [(set_attr "type" "arith")
3475 (set_attr "mode" "<MODE>")])
3478 (define_expand "insv"
3479 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3480 (match_operand 1 "immediate_operand")
3481 (match_operand 2 "immediate_operand"))
3482 (match_operand 3 "reg_or_0_operand"))]
3485 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3486 INTVAL (operands[1]),
3487 INTVAL (operands[2])))
3489 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3490 INTVAL (operands[2])))
3492 if (GET_MODE (operands[0]) == DImode)
3493 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3496 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3504 (define_insn "insv<mode>"
3505 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3506 (match_operand:SI 1 "immediate_operand" "I")
3507 (match_operand:SI 2 "immediate_operand" "I"))
3508 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3509 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3510 INTVAL (operands[2]))"
3511 "<d>ins\t%0,%z3,%2,%1"
3512 [(set_attr "type" "arith")
3513 (set_attr "mode" "<MODE>")])
3515 ;; Combiner pattern for cins (clear and insert bit field). We can
3516 ;; implement mask-and-shift-left operation with this. Note that if
3517 ;; the upper bit of the mask is set in an SImode operation, the mask
3518 ;; itself will be sign-extended. mask_low_and_shift_len will
3519 ;; therefore be greater than our threshold of 32.
3521 (define_insn "*cins<mode>"
3522 [(set (match_operand:GPR 0 "register_operand" "=d")
3524 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3525 (match_operand:GPR 2 "const_int_operand" ""))
3526 (match_operand:GPR 3 "const_int_operand" "")))]
3528 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3531 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3532 return "cins\t%0,%1,%2,%m3";
3534 [(set_attr "type" "shift")
3535 (set_attr "mode" "<MODE>")])
3537 ;; Unaligned word moves generated by the bit field patterns.
3539 ;; As far as the rtl is concerned, both the left-part and right-part
3540 ;; instructions can access the whole field. However, the real operand
3541 ;; refers to just the first or the last byte (depending on endianness).
3542 ;; We therefore use two memory operands to each instruction, one to
3543 ;; describe the rtl effect and one to use in the assembly output.
3545 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3546 ;; This allows us to use the standard length calculations for the "load"
3547 ;; and "store" type attributes.
3549 (define_insn "mov_<load>l"
3550 [(set (match_operand:GPR 0 "register_operand" "=d")
3551 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3552 (match_operand:QI 2 "memory_operand" "m")]
3554 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3556 [(set_attr "move_type" "load")
3557 (set_attr "mode" "<MODE>")])
3559 (define_insn "mov_<load>r"
3560 [(set (match_operand:GPR 0 "register_operand" "=d")
3561 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3562 (match_operand:QI 2 "memory_operand" "m")
3563 (match_operand:GPR 3 "register_operand" "0")]
3564 UNSPEC_LOAD_RIGHT))]
3565 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3567 [(set_attr "move_type" "load")
3568 (set_attr "mode" "<MODE>")])
3570 (define_insn "mov_<store>l"
3571 [(set (match_operand:BLK 0 "memory_operand" "=m")
3572 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3573 (match_operand:QI 2 "memory_operand" "m")]
3574 UNSPEC_STORE_LEFT))]
3575 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3577 [(set_attr "move_type" "store")
3578 (set_attr "mode" "<MODE>")])
3580 (define_insn "mov_<store>r"
3581 [(set (match_operand:BLK 0 "memory_operand" "+m")
3582 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3583 (match_operand:QI 2 "memory_operand" "m")
3585 UNSPEC_STORE_RIGHT))]
3586 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3588 [(set_attr "move_type" "store")
3589 (set_attr "mode" "<MODE>")])
3591 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3592 ;; The required value is:
3594 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3596 ;; which translates to:
3598 ;; lui op0,%highest(op1)
3599 ;; daddiu op0,op0,%higher(op1)
3601 ;; daddiu op0,op0,%hi(op1)
3604 ;; The split is deferred until after flow2 to allow the peephole2 below
3606 (define_insn_and_split "*lea_high64"
3607 [(set (match_operand:DI 0 "register_operand" "=d")
3608 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3609 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3611 "&& epilogue_completed"
3612 [(set (match_dup 0) (high:DI (match_dup 2)))
3613 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3614 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3615 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3616 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3618 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3619 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3621 [(set_attr "length" "20")])
3623 ;; Use a scratch register to reduce the latency of the above pattern
3624 ;; on superscalar machines. The optimized sequence is:
3626 ;; lui op1,%highest(op2)
3628 ;; daddiu op1,op1,%higher(op2)
3630 ;; daddu op1,op1,op0
3632 [(set (match_operand:DI 1 "d_operand")
3633 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3634 (match_scratch:DI 0 "d")]
3635 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3636 [(set (match_dup 1) (high:DI (match_dup 3)))
3637 (set (match_dup 0) (high:DI (match_dup 4)))
3638 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3639 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3640 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3642 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3643 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3646 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3647 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3648 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3649 ;; used once. We can then use the sequence:
3651 ;; lui op0,%highest(op1)
3653 ;; daddiu op0,op0,%higher(op1)
3654 ;; daddiu op2,op2,%lo(op1)
3656 ;; daddu op0,op0,op2
3658 ;; which takes 4 cycles on most superscalar targets.
3659 (define_insn_and_split "*lea64"
3660 [(set (match_operand:DI 0 "register_operand" "=d")
3661 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3662 (clobber (match_scratch:DI 2 "=&d"))]
3663 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3665 "&& reload_completed"
3666 [(set (match_dup 0) (high:DI (match_dup 3)))
3667 (set (match_dup 2) (high:DI (match_dup 4)))
3668 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3669 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3670 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3671 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3673 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3674 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3676 [(set_attr "length" "24")])
3678 ;; Split HIGHs into:
3683 ;; on MIPS16 targets.
3685 [(set (match_operand:SI 0 "d_operand")
3686 (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
3687 "TARGET_MIPS16 && reload_completed"
3688 [(set (match_dup 0) (match_dup 2))
3689 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3691 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3694 ;; Insns to fetch a symbol from a big GOT.
3696 (define_insn_and_split "*xgot_hi<mode>"
3697 [(set (match_operand:P 0 "register_operand" "=d")
3698 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3699 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3701 "&& reload_completed"
3702 [(set (match_dup 0) (high:P (match_dup 2)))
3703 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3705 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3706 operands[3] = pic_offset_table_rtx;
3708 [(set_attr "got" "xgot_high")
3709 (set_attr "mode" "<MODE>")])
3711 (define_insn_and_split "*xgot_lo<mode>"
3712 [(set (match_operand:P 0 "register_operand" "=d")
3713 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3714 (match_operand:P 2 "got_disp_operand" "")))]
3715 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3717 "&& reload_completed"
3719 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3720 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3721 [(set_attr "got" "load")
3722 (set_attr "mode" "<MODE>")])
3724 ;; Insns to fetch a symbol from a normal GOT.
3726 (define_insn_and_split "*got_disp<mode>"
3727 [(set (match_operand:P 0 "register_operand" "=d")
3728 (match_operand:P 1 "got_disp_operand" ""))]
3729 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3731 "&& reload_completed"
3732 [(set (match_dup 0) (match_dup 2))]
3733 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3734 [(set_attr "got" "load")
3735 (set_attr "mode" "<MODE>")])
3737 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3739 (define_insn_and_split "*got_page<mode>"
3740 [(set (match_operand:P 0 "register_operand" "=d")
3741 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3742 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3744 "&& reload_completed"
3745 [(set (match_dup 0) (match_dup 2))]
3746 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3747 [(set_attr "got" "load")
3748 (set_attr "mode" "<MODE>")])
3750 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
3751 (define_expand "unspec_got<mode>"
3752 [(unspec:P [(match_operand:P 0)
3753 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
3755 ;; Lower-level instructions for loading an address from the GOT.
3756 ;; We could use MEMs, but an unspec gives more optimization
3759 (define_insn "load_got<mode>"
3760 [(set (match_operand:P 0 "register_operand" "=d")
3761 (unspec:P [(match_operand:P 1 "register_operand" "d")
3762 (match_operand:P 2 "immediate_operand" "")]
3765 "<load>\t%0,%R2(%1)"
3766 [(set_attr "got" "load")
3767 (set_attr "mode" "<MODE>")])
3769 ;; Instructions for adding the low 16 bits of an address to a register.
3770 ;; Operand 2 is the address: mips_print_operand works out which relocation
3771 ;; should be applied.
3773 (define_insn "*low<mode>"
3774 [(set (match_operand:P 0 "register_operand" "=d")
3775 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3776 (match_operand:P 2 "immediate_operand" "")))]
3778 "<d>addiu\t%0,%1,%R2"
3779 [(set_attr "type" "arith")
3780 (set_attr "mode" "<MODE>")])
3782 (define_insn "*low<mode>_mips16"
3783 [(set (match_operand:P 0 "register_operand" "=d")
3784 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3785 (match_operand:P 2 "immediate_operand" "")))]
3788 [(set_attr "type" "arith")
3789 (set_attr "mode" "<MODE>")
3790 (set_attr "extended_mips16" "yes")])
3792 ;; Expose MIPS16 uses of the global pointer after reload if the function
3793 ;; is responsible for setting up the register itself.
3795 [(set (match_operand:GPR 0 "d_operand")
3796 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
3797 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
3798 [(set (match_dup 0) (match_dup 1))]
3799 { operands[1] = pic_offset_table_rtx; })
3801 ;; Allow combine to split complex const_int load sequences, using operand 2
3802 ;; to store the intermediate results. See move_operand for details.
3804 [(set (match_operand:GPR 0 "register_operand")
3805 (match_operand:GPR 1 "splittable_const_int_operand"))
3806 (clobber (match_operand:GPR 2 "register_operand"))]
3810 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3814 ;; Likewise, for symbolic operands.
3816 [(set (match_operand:P 0 "register_operand")
3817 (match_operand:P 1))
3818 (clobber (match_operand:P 2 "register_operand"))]
3819 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3820 [(set (match_dup 0) (match_dup 3))]
3822 mips_split_symbol (operands[2], operands[1],
3823 MAX_MACHINE_MODE, &operands[3]);
3826 ;; 64-bit integer moves
3828 ;; Unlike most other insns, the move insns can't be split with
3829 ;; different predicates, because register spilling and other parts of
3830 ;; the compiler, have memoized the insn number already.
3832 (define_expand "movdi"
3833 [(set (match_operand:DI 0 "")
3834 (match_operand:DI 1 ""))]
3837 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3841 ;; For mips16, we need a special case to handle storing $31 into
3842 ;; memory, since we don't have a constraint to match $31. This
3843 ;; instruction can be generated by save_restore_insns.
3845 (define_insn "*mov<mode>_ra"
3846 [(set (match_operand:GPR 0 "stack_operand" "=m")
3850 [(set_attr "move_type" "store")
3851 (set_attr "mode" "<MODE>")])
3853 (define_insn "*movdi_32bit"
3854 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
3855 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
3856 "!TARGET_64BIT && !TARGET_MIPS16
3857 && (register_operand (operands[0], DImode)
3858 || reg_or_0_operand (operands[1], DImode))"
3859 { return mips_output_move (operands[0], operands[1]); }
3860 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
3861 (set_attr "mode" "DI")])
3863 (define_insn "*movdi_32bit_mips16"
3864 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3865 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3866 "!TARGET_64BIT && TARGET_MIPS16
3867 && (register_operand (operands[0], DImode)
3868 || register_operand (operands[1], DImode))"
3869 { return mips_output_move (operands[0], operands[1]); }
3870 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
3871 (set_attr "mode" "DI")])
3873 (define_insn "*movdi_64bit"
3874 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3875 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3876 "TARGET_64BIT && !TARGET_MIPS16
3877 && (register_operand (operands[0], DImode)
3878 || reg_or_0_operand (operands[1], DImode))"
3879 { return mips_output_move (operands[0], operands[1]); }
3880 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3881 (set_attr "mode" "DI")])
3883 (define_insn "*movdi_64bit_mips16"
3884 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3885 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3886 "TARGET_64BIT && TARGET_MIPS16
3887 && (register_operand (operands[0], DImode)
3888 || register_operand (operands[1], DImode))"
3889 { return mips_output_move (operands[0], operands[1]); }
3890 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3891 (set_attr "mode" "DI")])
3893 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3894 ;; when the original load is a 4 byte instruction but the add and the
3895 ;; load are 2 2 byte instructions.
3898 [(set (match_operand:DI 0 "d_operand")
3899 (mem:DI (plus:DI (match_dup 0)
3900 (match_operand:DI 1 "const_int_operand"))))]
3901 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3902 && !TARGET_DEBUG_D_MODE
3903 && ((INTVAL (operands[1]) < 0
3904 && INTVAL (operands[1]) >= -0x10)
3905 || (INTVAL (operands[1]) >= 32 * 8
3906 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3907 || (INTVAL (operands[1]) >= 0
3908 && INTVAL (operands[1]) < 32 * 8
3909 && (INTVAL (operands[1]) & 7) != 0))"
3910 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3911 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3913 HOST_WIDE_INT val = INTVAL (operands[1]);
3916 operands[2] = const0_rtx;
3917 else if (val >= 32 * 8)
3921 operands[1] = GEN_INT (0x8 + off);
3922 operands[2] = GEN_INT (val - off - 0x8);
3928 operands[1] = GEN_INT (off);
3929 operands[2] = GEN_INT (val - off);
3933 ;; 32-bit Integer moves
3935 ;; Unlike most other insns, the move insns can't be split with
3936 ;; different predicates, because register spilling and other parts of
3937 ;; the compiler, have memoized the insn number already.
3939 (define_expand "movsi"
3940 [(set (match_operand:SI 0 "")
3941 (match_operand:SI 1 ""))]
3944 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3948 ;; The difference between these two is whether or not ints are allowed
3949 ;; in FP registers (off by default, use -mdebugh to enable).
3951 (define_insn "*movsi_internal"
3952 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3953 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3955 && (register_operand (operands[0], SImode)
3956 || reg_or_0_operand (operands[1], SImode))"
3957 { return mips_output_move (operands[0], operands[1]); }
3958 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3959 (set_attr "mode" "SI")])
3961 (define_insn "*movsi_mips16"
3962 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3963 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3965 && (register_operand (operands[0], SImode)
3966 || register_operand (operands[1], SImode))"
3967 { return mips_output_move (operands[0], operands[1]); }
3968 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3969 (set_attr "mode" "SI")])
3971 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3972 ;; when the original load is a 4 byte instruction but the add and the
3973 ;; load are 2 2 byte instructions.
3976 [(set (match_operand:SI 0 "d_operand")
3977 (mem:SI (plus:SI (match_dup 0)
3978 (match_operand:SI 1 "const_int_operand"))))]
3979 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3980 && ((INTVAL (operands[1]) < 0
3981 && INTVAL (operands[1]) >= -0x80)
3982 || (INTVAL (operands[1]) >= 32 * 4
3983 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3984 || (INTVAL (operands[1]) >= 0
3985 && INTVAL (operands[1]) < 32 * 4
3986 && (INTVAL (operands[1]) & 3) != 0))"
3987 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3988 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3990 HOST_WIDE_INT val = INTVAL (operands[1]);
3993 operands[2] = const0_rtx;
3994 else if (val >= 32 * 4)
3998 operands[1] = GEN_INT (0x7c + off);
3999 operands[2] = GEN_INT (val - off - 0x7c);
4005 operands[1] = GEN_INT (off);
4006 operands[2] = GEN_INT (val - off);
4010 ;; On the mips16, we can split a load of certain constants into a load
4011 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4015 [(set (match_operand:SI 0 "d_operand")
4016 (match_operand:SI 1 "const_int_operand"))]
4017 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4018 && INTVAL (operands[1]) >= 0x100
4019 && INTVAL (operands[1]) <= 0xff + 0x7f"
4020 [(set (match_dup 0) (match_dup 1))
4021 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4023 int val = INTVAL (operands[1]);
4025 operands[1] = GEN_INT (0xff);
4026 operands[2] = GEN_INT (val - 0xff);
4029 ;; This insn handles moving CCmode values. It's really just a
4030 ;; slightly simplified copy of movsi_internal2, with additional cases
4031 ;; to move a condition register to a general register and to move
4032 ;; between the general registers and the floating point registers.
4034 (define_insn "movcc"
4035 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4036 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4037 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4038 { return mips_output_move (operands[0], operands[1]); }
4039 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
4040 (set_attr "mode" "SI")])
4042 ;; Reload condition code registers. reload_incc and reload_outcc
4043 ;; both handle moves from arbitrary operands into condition code
4044 ;; registers. reload_incc handles the more common case in which
4045 ;; a source operand is constrained to be in a condition-code
4046 ;; register, but has not been allocated to one.
4048 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4049 ;; constraints do not include 'z'. reload_outcc handles the case
4050 ;; when such an operand is allocated to a condition-code register.
4052 ;; Note that reloads from a condition code register to some
4053 ;; other location can be done using ordinary moves. Moving
4054 ;; into a GPR takes a single movcc, moving elsewhere takes
4055 ;; two. We can leave these cases to the generic reload code.
4056 (define_expand "reload_incc"
4057 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4058 (match_operand:CC 1 "general_operand" ""))
4059 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4060 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4062 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4066 (define_expand "reload_outcc"
4067 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4068 (match_operand:CC 1 "register_operand" ""))
4069 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4070 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4072 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4076 ;; MIPS4 supports loading and storing a floating point register from
4077 ;; the sum of two general registers. We use two versions for each of
4078 ;; these four instructions: one where the two general registers are
4079 ;; SImode, and one where they are DImode. This is because general
4080 ;; registers will be in SImode when they hold 32-bit values, but,
4081 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4082 ;; instructions will still work correctly.
4084 ;; ??? Perhaps it would be better to support these instructions by
4085 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
4086 ;; these instructions can only be used to load and store floating
4087 ;; point registers, that would probably cause trouble in reload.
4089 (define_insn "*<ANYF:loadx>_<P:mode>"
4090 [(set (match_operand:ANYF 0 "register_operand" "=f")
4091 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4092 (match_operand:P 2 "register_operand" "d"))))]
4094 "<ANYF:loadx>\t%0,%1(%2)"
4095 [(set_attr "type" "fpidxload")
4096 (set_attr "mode" "<ANYF:UNITMODE>")])
4098 (define_insn "*<ANYF:storex>_<P:mode>"
4099 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4100 (match_operand:P 2 "register_operand" "d")))
4101 (match_operand:ANYF 0 "register_operand" "f"))]
4103 "<ANYF:storex>\t%0,%1(%2)"
4104 [(set_attr "type" "fpidxstore")
4105 (set_attr "mode" "<ANYF:UNITMODE>")])
4107 ;; Scaled indexed address load.
4108 ;; Per md.texi, we only need to look for a pattern with multiply in the
4109 ;; address expression, not shift.
4111 (define_insn "*lwxs"
4112 [(set (match_operand:SI 0 "register_operand" "=d")
4113 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
4115 (match_operand:SI 2 "register_operand" "d"))))]
4118 [(set_attr "type" "load")
4119 (set_attr "mode" "SI")])
4121 ;; 16-bit Integer moves
4123 ;; Unlike most other insns, the move insns can't be split with
4124 ;; different predicates, because register spilling and other parts of
4125 ;; the compiler, have memoized the insn number already.
4126 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4128 (define_expand "movhi"
4129 [(set (match_operand:HI 0 "")
4130 (match_operand:HI 1 ""))]
4133 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4137 (define_insn "*movhi_internal"
4138 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4139 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4141 && (register_operand (operands[0], HImode)
4142 || reg_or_0_operand (operands[1], HImode))"
4143 { return mips_output_move (operands[0], operands[1]); }
4144 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4145 (set_attr "mode" "HI")])
4147 (define_insn "*movhi_mips16"
4148 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4149 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4151 && (register_operand (operands[0], HImode)
4152 || register_operand (operands[1], HImode))"
4153 { return mips_output_move (operands[0], operands[1]); }
4154 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4155 (set_attr "mode" "HI")])
4157 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4158 ;; when the original load is a 4 byte instruction but the add and the
4159 ;; load are 2 2 byte instructions.
4162 [(set (match_operand:HI 0 "d_operand")
4163 (mem:HI (plus:SI (match_dup 0)
4164 (match_operand:SI 1 "const_int_operand"))))]
4165 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4166 && ((INTVAL (operands[1]) < 0
4167 && INTVAL (operands[1]) >= -0x80)
4168 || (INTVAL (operands[1]) >= 32 * 2
4169 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4170 || (INTVAL (operands[1]) >= 0
4171 && INTVAL (operands[1]) < 32 * 2
4172 && (INTVAL (operands[1]) & 1) != 0))"
4173 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4174 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4176 HOST_WIDE_INT val = INTVAL (operands[1]);
4179 operands[2] = const0_rtx;
4180 else if (val >= 32 * 2)
4184 operands[1] = GEN_INT (0x7e + off);
4185 operands[2] = GEN_INT (val - off - 0x7e);
4191 operands[1] = GEN_INT (off);
4192 operands[2] = GEN_INT (val - off);
4196 ;; 8-bit Integer moves
4198 ;; Unlike most other insns, the move insns can't be split with
4199 ;; different predicates, because register spilling and other parts of
4200 ;; the compiler, have memoized the insn number already.
4201 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4203 (define_expand "movqi"
4204 [(set (match_operand:QI 0 "")
4205 (match_operand:QI 1 ""))]
4208 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4212 (define_insn "*movqi_internal"
4213 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4214 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4216 && (register_operand (operands[0], QImode)
4217 || reg_or_0_operand (operands[1], QImode))"
4218 { return mips_output_move (operands[0], operands[1]); }
4219 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4220 (set_attr "mode" "QI")])
4222 (define_insn "*movqi_mips16"
4223 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4224 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4226 && (register_operand (operands[0], QImode)
4227 || register_operand (operands[1], QImode))"
4228 { return mips_output_move (operands[0], operands[1]); }
4229 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4230 (set_attr "mode" "QI")])
4232 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4233 ;; when the original load is a 4 byte instruction but the add and the
4234 ;; load are 2 2 byte instructions.
4237 [(set (match_operand:QI 0 "d_operand")
4238 (mem:QI (plus:SI (match_dup 0)
4239 (match_operand:SI 1 "const_int_operand"))))]
4240 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4241 && ((INTVAL (operands[1]) < 0
4242 && INTVAL (operands[1]) >= -0x80)
4243 || (INTVAL (operands[1]) >= 32
4244 && INTVAL (operands[1]) <= 31 + 0x7f))"
4245 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4246 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4248 HOST_WIDE_INT val = INTVAL (operands[1]);
4251 operands[2] = const0_rtx;
4254 operands[1] = GEN_INT (0x7f);
4255 operands[2] = GEN_INT (val - 0x7f);
4259 ;; 32-bit floating point moves
4261 (define_expand "movsf"
4262 [(set (match_operand:SF 0 "")
4263 (match_operand:SF 1 ""))]
4266 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4270 (define_insn "*movsf_hardfloat"
4271 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4272 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4274 && (register_operand (operands[0], SFmode)
4275 || reg_or_0_operand (operands[1], SFmode))"
4276 { return mips_output_move (operands[0], operands[1]); }
4277 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4278 (set_attr "mode" "SF")])
4280 (define_insn "*movsf_softfloat"
4281 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4282 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4283 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4284 && (register_operand (operands[0], SFmode)
4285 || reg_or_0_operand (operands[1], SFmode))"
4286 { return mips_output_move (operands[0], operands[1]); }
4287 [(set_attr "move_type" "move,load,store")
4288 (set_attr "mode" "SF")])
4290 (define_insn "*movsf_mips16"
4291 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4292 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4294 && (register_operand (operands[0], SFmode)
4295 || register_operand (operands[1], SFmode))"
4296 { return mips_output_move (operands[0], operands[1]); }
4297 [(set_attr "move_type" "move,move,move,load,store")
4298 (set_attr "mode" "SF")])
4300 ;; 64-bit floating point moves
4302 (define_expand "movdf"
4303 [(set (match_operand:DF 0 "")
4304 (match_operand:DF 1 ""))]
4307 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4311 (define_insn "*movdf_hardfloat"
4312 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4313 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4314 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4315 && (register_operand (operands[0], DFmode)
4316 || reg_or_0_operand (operands[1], DFmode))"
4317 { return mips_output_move (operands[0], operands[1]); }
4318 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4319 (set_attr "mode" "DF")])
4321 (define_insn "*movdf_softfloat"
4322 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4323 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4324 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4325 && (register_operand (operands[0], DFmode)
4326 || reg_or_0_operand (operands[1], DFmode))"
4327 { return mips_output_move (operands[0], operands[1]); }
4328 [(set_attr "move_type" "move,load,store")
4329 (set_attr "mode" "DF")])
4331 (define_insn "*movdf_mips16"
4332 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4333 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4335 && (register_operand (operands[0], DFmode)
4336 || register_operand (operands[1], DFmode))"
4337 { return mips_output_move (operands[0], operands[1]); }
4338 [(set_attr "move_type" "move,move,move,load,store")
4339 (set_attr "mode" "DF")])
4341 ;; 128-bit integer moves
4343 (define_expand "movti"
4344 [(set (match_operand:TI 0)
4345 (match_operand:TI 1))]
4348 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4352 (define_insn "*movti"
4353 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4354 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4357 && (register_operand (operands[0], TImode)
4358 || reg_or_0_operand (operands[1], TImode))"
4360 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4361 (set_attr "mode" "TI")])
4363 (define_insn "*movti_mips16"
4364 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4365 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4368 && (register_operand (operands[0], TImode)
4369 || register_operand (operands[1], TImode))"
4371 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4372 (set_attr "mode" "TI")])
4374 ;; 128-bit floating point moves
4376 (define_expand "movtf"
4377 [(set (match_operand:TF 0)
4378 (match_operand:TF 1))]
4381 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4385 ;; This pattern handles both hard- and soft-float cases.
4386 (define_insn "*movtf"
4387 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4388 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4391 && (register_operand (operands[0], TFmode)
4392 || reg_or_0_operand (operands[1], TFmode))"
4394 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4395 (set_attr "mode" "TF")])
4397 (define_insn "*movtf_mips16"
4398 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4399 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4402 && (register_operand (operands[0], TFmode)
4403 || register_operand (operands[1], TFmode))"
4405 [(set_attr "move_type" "move,move,move,load,store")
4406 (set_attr "mode" "TF")])
4409 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4410 (match_operand:MOVE64 1 "move_operand"))]
4411 "reload_completed && !TARGET_64BIT
4412 && mips_split_64bit_move_p (operands[0], operands[1])"
4415 mips_split_doubleword_move (operands[0], operands[1]);
4420 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4421 (match_operand:MOVE128 1 "move_operand"))]
4422 "TARGET_64BIT && reload_completed"
4425 mips_split_doubleword_move (operands[0], operands[1]);
4429 ;; When generating mips16 code, split moves of negative constants into
4430 ;; a positive "li" followed by a negation.
4432 [(set (match_operand 0 "d_operand")
4433 (match_operand 1 "const_int_operand"))]
4434 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4438 (neg:SI (match_dup 2)))]
4440 operands[2] = gen_lowpart (SImode, operands[0]);
4441 operands[3] = GEN_INT (-INTVAL (operands[1]));
4444 ;; 64-bit paired-single floating point moves
4446 (define_expand "movv2sf"
4447 [(set (match_operand:V2SF 0)
4448 (match_operand:V2SF 1))]
4449 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4451 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4455 (define_insn "*movv2sf"
4456 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4457 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4459 && TARGET_PAIRED_SINGLE_FLOAT
4460 && (register_operand (operands[0], V2SFmode)
4461 || reg_or_0_operand (operands[1], V2SFmode))"
4462 { return mips_output_move (operands[0], operands[1]); }
4463 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4464 (set_attr "mode" "DF")])
4466 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4467 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4469 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4470 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4471 ;; and the errata related to -mfix-vr4130.
4472 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4473 [(set (match_operand:GPR 0 "register_operand" "=d")
4474 (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
4477 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4478 [(set_attr "move_type" "mfhilo")
4479 (set_attr "mode" "<GPR:MODE>")])
4481 ;; Set the high part of a HI/LO value, given that the low part has
4482 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4483 ;; why we can't just use (reg:GPR HI_REGNUM).
4484 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4485 [(set (match_operand:HILO 0 "register_operand" "=x")
4486 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4487 (match_operand:GPR 2 "register_operand" "l")]
4491 [(set_attr "move_type" "mthilo")
4492 (set_attr "mode" "SI")])
4494 ;; Emit a doubleword move in which exactly one of the operands is
4495 ;; a floating-point register. We can't just emit two normal moves
4496 ;; because of the constraints imposed by the FPU register model;
4497 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4498 ;; the FPR whole and use special patterns to refer to each word of
4499 ;; the other operand.
4501 (define_expand "move_doubleword_fpr<mode>"
4502 [(set (match_operand:SPLITF 0)
4503 (match_operand:SPLITF 1))]
4506 if (FP_REG_RTX_P (operands[0]))
4508 rtx low = mips_subword (operands[1], 0);
4509 rtx high = mips_subword (operands[1], 1);
4510 emit_insn (gen_load_low<mode> (operands[0], low));
4511 if (ISA_HAS_MXHC1 && reg_or_0_operand (high, <HALFMODE>mode))
4512 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4514 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4518 rtx low = mips_subword (operands[0], 0);
4519 rtx high = mips_subword (operands[0], 1);
4520 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4521 if (ISA_HAS_MXHC1 && register_operand (high, <HALFMODE>mode))
4522 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4524 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4529 ;; Load the low word of operand 0 with operand 1.
4530 (define_insn "load_low<mode>"
4531 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4532 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4536 operands[0] = mips_subword (operands[0], 0);
4537 return mips_output_move (operands[0], operands[1]);
4539 [(set_attr "move_type" "mtc,fpload")
4540 (set_attr "mode" "<HALFMODE>")])
4542 ;; Load the high word of operand 0 from operand 1, preserving the value
4544 (define_insn "load_high<mode>"
4545 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4546 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4547 (match_operand:SPLITF 2 "register_operand" "0,0")]
4551 operands[0] = mips_subword (operands[0], 1);
4552 return mips_output_move (operands[0], operands[1]);
4554 [(set_attr "move_type" "mtc,fpload")
4555 (set_attr "mode" "<HALFMODE>")])
4557 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4558 ;; high word and 0 to store the low word.
4559 (define_insn "store_word<mode>"
4560 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4561 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4562 (match_operand 2 "const_int_operand")]
4563 UNSPEC_STORE_WORD))]
4566 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4567 return mips_output_move (operands[0], operands[1]);
4569 [(set_attr "move_type" "mfc,fpstore")
4570 (set_attr "mode" "<HALFMODE>")])
4572 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4573 ;; value in the low word.
4574 (define_insn "mthc1<mode>"
4575 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4576 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4577 (match_operand:SPLITF 2 "register_operand" "0")]
4579 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4581 [(set_attr "move_type" "mtc")
4582 (set_attr "mode" "<HALFMODE>")])
4584 ;; Move high word of operand 1 to operand 0 using mfhc1.
4585 (define_insn "mfhc1<mode>"
4586 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4587 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4589 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4591 [(set_attr "move_type" "mfc")
4592 (set_attr "mode" "<HALFMODE>")])
4594 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4595 (define_expand "load_const_gp_<mode>"
4596 [(set (match_operand:P 0 "register_operand" "=d")
4597 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4599 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4600 ;; of _gp from the start of this function. Operand 1 is the incoming
4601 ;; function address.
4602 (define_insn_and_split "loadgp_newabi_<mode>"
4603 [(set (match_operand:P 0 "register_operand" "=d")
4604 (unspec_volatile:P [(match_operand:P 1)
4605 (match_operand:P 2 "register_operand" "d")]
4607 "mips_current_loadgp_style () == LOADGP_NEWABI"
4610 [(set (match_dup 0) (match_dup 3))
4611 (set (match_dup 0) (match_dup 4))
4612 (set (match_dup 0) (match_dup 5))]
4614 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4615 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4616 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4618 [(set_attr "length" "12")])
4620 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4621 (define_insn_and_split "loadgp_absolute_<mode>"
4622 [(set (match_operand:P 0 "register_operand" "=d")
4623 (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4624 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4629 mips_emit_move (operands[0], operands[1]);
4632 [(set_attr "length" "8")])
4634 ;; This blockage instruction prevents the gp load from being
4635 ;; scheduled after an implicit use of gp. It also prevents
4636 ;; the load from being deleted as dead.
4637 (define_insn "loadgp_blockage"
4638 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4641 [(set_attr "type" "ghost")
4642 (set_attr "mode" "none")])
4644 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4645 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4646 (define_insn_and_split "loadgp_rtp_<mode>"
4647 [(set (match_operand:P 0 "register_operand" "=d")
4648 (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
4649 (match_operand:P 2 "symbol_ref_operand")]
4651 "mips_current_loadgp_style () == LOADGP_RTP"
4654 [(set (match_dup 0) (high:P (match_dup 3)))
4655 (set (match_dup 0) (unspec:P [(match_dup 0)
4656 (match_dup 3)] UNSPEC_LOAD_GOT))
4657 (set (match_dup 0) (unspec:P [(match_dup 0)
4658 (match_dup 4)] UNSPEC_LOAD_GOT))]
4660 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4661 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4663 [(set_attr "length" "12")])
4665 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4666 ;; global pointer and operand 1 is the MIPS16 register that holds
4667 ;; the required value.
4668 (define_insn_and_split "copygp_mips16"
4669 [(set (match_operand:SI 0 "register_operand" "=y")
4670 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
4674 "&& reload_completed"
4675 [(set (match_dup 0) (match_dup 1))])
4677 ;; Emit a .cprestore directive, which normally expands to a single store
4678 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4679 ;; code so that jals inside inline asms will work correctly.
4680 (define_insn "cprestore"
4681 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4686 if (set_nomacro && which_alternative == 1)
4687 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4689 return ".cprestore\t%0";
4691 [(set_attr "type" "store")
4692 (set_attr "length" "4,12")])
4694 ;; Expand in-line code to clear the instruction cache between operand[0] and
4696 (define_expand "clear_cache"
4697 [(match_operand 0 "pmode_register_operand")
4698 (match_operand 1 "pmode_register_operand")]
4704 mips_expand_synci_loop (operands[0], operands[1]);
4705 emit_insn (gen_sync ());
4706 emit_insn (gen_clear_hazard ());
4708 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4710 rtx len = gen_reg_rtx (Pmode);
4711 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4712 MIPS_ICACHE_SYNC (operands[0], len);
4718 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4722 (define_insn "synci"
4723 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4728 (define_insn "rdhwr"
4729 [(set (match_operand:SI 0 "register_operand" "=d")
4730 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4735 (define_insn "clear_hazard"
4736 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4737 (clobber (reg:SI 31))]
4740 return "%(%<bal\t1f\n"
4742 "1:\taddiu\t$31,$31,12\n"
4746 [(set_attr "length" "20")])
4748 ;; Cache operations for R4000-style caches.
4749 (define_insn "mips_cache"
4750 [(set (mem:BLK (scratch))
4751 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
4752 (match_operand:QI 1 "address_operand" "p")]
4753 UNSPEC_MIPS_CACHE))]
4757 ;; Similar, but with the operands hard-coded to an R10K cache barrier
4758 ;; operation. We keep the pattern distinct so that we can identify
4759 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
4760 ;; the operation is never inserted into a delay slot.
4761 (define_insn "r10k_cache_barrier"
4762 [(set (mem:BLK (scratch))
4763 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
4766 [(set_attr "can_delay" "no")])
4768 ;; Block moves, see mips.c for more details.
4769 ;; Argument 0 is the destination
4770 ;; Argument 1 is the source
4771 ;; Argument 2 is the length
4772 ;; Argument 3 is the alignment
4774 (define_expand "movmemsi"
4775 [(parallel [(set (match_operand:BLK 0 "general_operand")
4776 (match_operand:BLK 1 "general_operand"))
4777 (use (match_operand:SI 2 ""))
4778 (use (match_operand:SI 3 "const_int_operand"))])]
4779 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4781 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4788 ;; ....................
4792 ;; ....................
4794 (define_expand "<optab><mode>3"
4795 [(set (match_operand:GPR 0 "register_operand")
4796 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4797 (match_operand:SI 2 "arith_operand")))]
4800 /* On the mips16, a shift of more than 8 is a four byte instruction,
4801 so, for a shift between 8 and 16, it is just as fast to do two
4802 shifts of 8 or less. If there is a lot of shifting going on, we
4803 may win in CSE. Otherwise combine will put the shifts back
4804 together again. This can be called by mips_function_arg, so we must
4805 be careful not to allocate a new register if we've reached the
4809 && GET_CODE (operands[2]) == CONST_INT
4810 && INTVAL (operands[2]) > 8
4811 && INTVAL (operands[2]) <= 16
4812 && !reload_in_progress
4813 && !reload_completed)
4815 rtx temp = gen_reg_rtx (<MODE>mode);
4817 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4818 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4819 GEN_INT (INTVAL (operands[2]) - 8)));
4824 (define_insn "*<optab><mode>3"
4825 [(set (match_operand:GPR 0 "register_operand" "=d")
4826 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4827 (match_operand:SI 2 "arith_operand" "dI")))]
4830 if (GET_CODE (operands[2]) == CONST_INT)
4831 operands[2] = GEN_INT (INTVAL (operands[2])
4832 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4834 return "<d><insn>\t%0,%1,%2";
4836 [(set_attr "type" "shift")
4837 (set_attr "mode" "<MODE>")])
4839 (define_insn "*<optab>si3_extend"
4840 [(set (match_operand:DI 0 "register_operand" "=d")
4842 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4843 (match_operand:SI 2 "arith_operand" "dI"))))]
4844 "TARGET_64BIT && !TARGET_MIPS16"
4846 if (GET_CODE (operands[2]) == CONST_INT)
4847 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4849 return "<insn>\t%0,%1,%2";
4851 [(set_attr "type" "shift")
4852 (set_attr "mode" "SI")])
4854 (define_insn "*<optab>si3_mips16"
4855 [(set (match_operand:SI 0 "register_operand" "=d,d")
4856 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4857 (match_operand:SI 2 "arith_operand" "d,I")))]
4860 if (which_alternative == 0)
4861 return "<insn>\t%0,%2";
4863 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4864 return "<insn>\t%0,%1,%2";
4866 [(set_attr "type" "shift")
4867 (set_attr "mode" "SI")
4868 (set_attr_alternative "length"
4870 (if_then_else (match_operand 2 "m16_uimm3_b")
4874 ;; We need separate DImode MIPS16 patterns because of the irregularity
4876 (define_insn "*ashldi3_mips16"
4877 [(set (match_operand:DI 0 "register_operand" "=d,d")
4878 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4879 (match_operand:SI 2 "arith_operand" "d,I")))]
4880 "TARGET_64BIT && TARGET_MIPS16"
4882 if (which_alternative == 0)
4883 return "dsll\t%0,%2";
4885 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4886 return "dsll\t%0,%1,%2";
4888 [(set_attr "type" "shift")
4889 (set_attr "mode" "DI")
4890 (set_attr_alternative "length"
4892 (if_then_else (match_operand 2 "m16_uimm3_b")
4896 (define_insn "*ashrdi3_mips16"
4897 [(set (match_operand:DI 0 "register_operand" "=d,d")
4898 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4899 (match_operand:SI 2 "arith_operand" "d,I")))]
4900 "TARGET_64BIT && TARGET_MIPS16"
4902 if (GET_CODE (operands[2]) == CONST_INT)
4903 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4905 return "dsra\t%0,%2";
4907 [(set_attr "type" "shift")
4908 (set_attr "mode" "DI")
4909 (set_attr_alternative "length"
4911 (if_then_else (match_operand 2 "m16_uimm3_b")
4915 (define_insn "*lshrdi3_mips16"
4916 [(set (match_operand:DI 0 "register_operand" "=d,d")
4917 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4918 (match_operand:SI 2 "arith_operand" "d,I")))]
4919 "TARGET_64BIT && TARGET_MIPS16"
4921 if (GET_CODE (operands[2]) == CONST_INT)
4922 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4924 return "dsrl\t%0,%2";
4926 [(set_attr "type" "shift")
4927 (set_attr "mode" "DI")
4928 (set_attr_alternative "length"
4930 (if_then_else (match_operand 2 "m16_uimm3_b")
4934 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4937 [(set (match_operand:GPR 0 "d_operand")
4938 (any_shift:GPR (match_operand:GPR 1 "d_operand")
4939 (match_operand:GPR 2 "const_int_operand")))]
4940 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4941 && INTVAL (operands[2]) > 8
4942 && INTVAL (operands[2]) <= 16"
4943 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4944 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4945 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4947 ;; If we load a byte on the mips16 as a bitfield, the resulting
4948 ;; sequence of instructions is too complicated for combine, because it
4949 ;; involves four instructions: a load, a shift, a constant load into a
4950 ;; register, and an and (the key problem here is that the mips16 does
4951 ;; not have and immediate). We recognize a shift of a load in order
4952 ;; to make it simple enough for combine to understand.
4954 ;; The length here is the worst case: the length of the split version
4955 ;; will be more accurate.
4956 (define_insn_and_split ""
4957 [(set (match_operand:SI 0 "register_operand" "=d")
4958 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4959 (match_operand:SI 2 "immediate_operand" "I")))]
4963 [(set (match_dup 0) (match_dup 1))
4964 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4966 [(set_attr "type" "load")
4967 (set_attr "mode" "SI")
4968 (set_attr "length" "16")])
4970 (define_insn "rotr<mode>3"
4971 [(set (match_operand:GPR 0 "register_operand" "=d")
4972 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4973 (match_operand:SI 2 "arith_operand" "dI")))]
4976 if (GET_CODE (operands[2]) == CONST_INT)
4977 gcc_assert (INTVAL (operands[2]) >= 0
4978 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4980 return "<d>ror\t%0,%1,%2";
4982 [(set_attr "type" "shift")
4983 (set_attr "mode" "<MODE>")])
4986 ;; ....................
4990 ;; ....................
4992 ;; Flow here is rather complex:
4994 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4995 ;; into cmp_operands[] but generates no RTL.
4997 ;; 2) The appropriate branch define_expand is called, which then
4998 ;; creates the appropriate RTL for the comparison and branch.
4999 ;; Different CC modes are used, based on what type of branch is
5000 ;; done, so that we can constrain things appropriately. There
5001 ;; are assumptions in the rest of GCC that break if we fold the
5002 ;; operands into the branches for integer operations, and use cc0
5003 ;; for floating point, so we use the fp status register instead.
5004 ;; If needed, an appropriate temporary is created to hold the
5005 ;; of the integer compare.
5007 (define_expand "cmp<mode>"
5009 (compare:CC (match_operand:GPR 0 "register_operand")
5010 (match_operand:GPR 1 "nonmemory_operand")))]
5013 cmp_operands[0] = operands[0];
5014 cmp_operands[1] = operands[1];
5018 (define_expand "cmp<mode>"
5020 (compare:CC (match_operand:SCALARF 0 "register_operand")
5021 (match_operand:SCALARF 1 "register_operand")))]
5024 cmp_operands[0] = operands[0];
5025 cmp_operands[1] = operands[1];
5030 ;; ....................
5032 ;; CONDITIONAL BRANCHES
5034 ;; ....................
5036 ;; Conditional branches on floating-point equality tests.
5038 (define_insn "*branch_fp"
5041 (match_operator 0 "equality_operator"
5042 [(match_operand:CC 2 "register_operand" "z")
5044 (label_ref (match_operand 1 "" ""))
5048 return mips_output_conditional_branch (insn, operands,
5049 MIPS_BRANCH ("b%F0", "%Z2%1"),
5050 MIPS_BRANCH ("b%W0", "%Z2%1"));
5052 [(set_attr "type" "branch")
5053 (set_attr "mode" "none")])
5055 (define_insn "*branch_fp_inverted"
5058 (match_operator 0 "equality_operator"
5059 [(match_operand:CC 2 "register_operand" "z")
5062 (label_ref (match_operand 1 "" ""))))]
5065 return mips_output_conditional_branch (insn, operands,
5066 MIPS_BRANCH ("b%W0", "%Z2%1"),
5067 MIPS_BRANCH ("b%F0", "%Z2%1"));
5069 [(set_attr "type" "branch")
5070 (set_attr "mode" "none")])
5072 ;; Conditional branches on ordered comparisons with zero.
5074 (define_insn "*branch_order<mode>"
5077 (match_operator 0 "order_operator"
5078 [(match_operand:GPR 2 "register_operand" "d")
5080 (label_ref (match_operand 1 "" ""))
5083 { return mips_output_order_conditional_branch (insn, operands, false); }
5084 [(set_attr "type" "branch")
5085 (set_attr "mode" "none")])
5087 (define_insn "*branch_order<mode>_inverted"
5090 (match_operator 0 "order_operator"
5091 [(match_operand:GPR 2 "register_operand" "d")
5094 (label_ref (match_operand 1 "" ""))))]
5096 { return mips_output_order_conditional_branch (insn, operands, true); }
5097 [(set_attr "type" "branch")
5098 (set_attr "mode" "none")])
5100 ;; Conditional branch on equality comparison.
5102 (define_insn "*branch_equality<mode>"
5105 (match_operator 0 "equality_operator"
5106 [(match_operand:GPR 2 "register_operand" "d")
5107 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5108 (label_ref (match_operand 1 "" ""))
5112 return mips_output_conditional_branch (insn, operands,
5113 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
5114 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
5116 [(set_attr "type" "branch")
5117 (set_attr "mode" "none")])
5119 (define_insn "*branch_equality<mode>_inverted"
5122 (match_operator 0 "equality_operator"
5123 [(match_operand:GPR 2 "register_operand" "d")
5124 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5126 (label_ref (match_operand 1 "" ""))))]
5129 return mips_output_conditional_branch (insn, operands,
5130 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
5131 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
5133 [(set_attr "type" "branch")
5134 (set_attr "mode" "none")])
5138 (define_insn "*branch_equality<mode>_mips16"
5141 (match_operator 0 "equality_operator"
5142 [(match_operand:GPR 1 "register_operand" "d,t")
5144 (match_operand 2 "pc_or_label_operand" "")
5145 (match_operand 3 "pc_or_label_operand" "")))]
5148 if (operands[2] != pc_rtx)
5150 if (which_alternative == 0)
5151 return "b%C0z\t%1,%2";
5153 return "bt%C0z\t%2";
5157 if (which_alternative == 0)
5158 return "b%N0z\t%1,%3";
5160 return "bt%N0z\t%3";
5163 [(set_attr "type" "branch")
5164 (set_attr "mode" "none")])
5166 (define_expand "b<code>"
5168 (if_then_else (any_cond:CC (cc0)
5170 (label_ref (match_operand 0 ""))
5174 mips_expand_conditional_branch (operands, <CODE>);
5178 ;; Used to implement built-in functions.
5179 (define_expand "condjump"
5181 (if_then_else (match_operand 0)
5182 (label_ref (match_operand 1))
5185 ;; Branch if bit is set/clear.
5187 (define_insn "*branch_bit<bbv><mode>"
5190 (equality_op (zero_extract:GPR
5191 (match_operand:GPR 1 "register_operand" "d")
5193 (match_operand 2 "const_int_operand" ""))
5195 (label_ref (match_operand 0 ""))
5197 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5200 mips_output_conditional_branch (insn, operands,
5201 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5202 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5204 [(set_attr "type" "branch")
5205 (set_attr "mode" "none")
5206 (set_attr "branch_likely" "no")])
5208 (define_insn "*branch_bit<bbv><mode>_inverted"
5211 (equality_op (zero_extract:GPR
5212 (match_operand:GPR 1 "register_operand" "d")
5214 (match_operand 2 "const_int_operand" ""))
5217 (label_ref (match_operand 0 ""))))]
5218 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5221 mips_output_conditional_branch (insn, operands,
5222 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5223 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5225 [(set_attr "type" "branch")
5226 (set_attr "mode" "none")
5227 (set_attr "branch_likely" "no")])
5230 ;; ....................
5232 ;; SETTING A REGISTER FROM A COMPARISON
5234 ;; ....................
5236 ;; Destination is always set in SI mode.
5238 (define_expand "seq"
5239 [(set (match_operand:SI 0 "register_operand")
5240 (eq:SI (match_dup 1)
5243 { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
5245 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5246 [(set (match_operand:GPR2 0 "register_operand" "=d")
5247 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5249 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5251 [(set_attr "type" "slt")
5252 (set_attr "mode" "<GPR:MODE>")])
5254 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5255 [(set (match_operand:GPR2 0 "register_operand" "=t")
5256 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5258 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5260 [(set_attr "type" "slt")
5261 (set_attr "mode" "<GPR:MODE>")])
5263 ;; Generate sltiu unless using seq results in better code.
5264 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5265 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5266 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5267 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5273 [(set_attr "type" "slt")
5274 (set_attr "mode" "<GPR:MODE>")])
5276 ;; "sne" uses sltu instructions in which the first operand is $0.
5277 ;; This isn't possible in mips16 code.
5279 (define_expand "sne"
5280 [(set (match_operand:SI 0 "register_operand")
5281 (ne:SI (match_dup 1)
5284 { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
5286 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5287 [(set (match_operand:GPR2 0 "register_operand" "=d")
5288 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5290 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5292 [(set_attr "type" "slt")
5293 (set_attr "mode" "<GPR:MODE>")])
5295 ;; Generate sltu unless using sne results in better code.
5296 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5297 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5298 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5299 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5305 [(set_attr "type" "slt")
5306 (set_attr "mode" "<GPR:MODE>")])
5308 (define_expand "sgt<u>"
5309 [(set (match_operand:SI 0 "register_operand")
5310 (any_gt:SI (match_dup 1)
5313 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5315 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5316 [(set (match_operand:GPR2 0 "register_operand" "=d")
5317 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5318 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5321 [(set_attr "type" "slt")
5322 (set_attr "mode" "<GPR:MODE>")])
5324 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5325 [(set (match_operand:GPR2 0 "register_operand" "=t")
5326 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5327 (match_operand:GPR 2 "register_operand" "d")))]
5330 [(set_attr "type" "slt")
5331 (set_attr "mode" "<GPR:MODE>")])
5333 (define_expand "sge<u>"
5334 [(set (match_operand:SI 0 "register_operand")
5335 (any_ge:SI (match_dup 1)
5338 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5340 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5341 [(set (match_operand:GPR2 0 "register_operand" "=d")
5342 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5346 [(set_attr "type" "slt")
5347 (set_attr "mode" "<GPR:MODE>")])
5349 (define_expand "slt<u>"
5350 [(set (match_operand:SI 0 "register_operand")
5351 (any_lt:SI (match_dup 1)
5354 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5356 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5357 [(set (match_operand:GPR2 0 "register_operand" "=d")
5358 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5359 (match_operand:GPR 2 "arith_operand" "dI")))]
5362 [(set_attr "type" "slt")
5363 (set_attr "mode" "<GPR:MODE>")])
5365 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5366 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5367 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5368 (match_operand:GPR 2 "arith_operand" "d,I")))]
5371 [(set_attr "type" "slt")
5372 (set_attr "mode" "<GPR:MODE>")
5373 (set_attr_alternative "length"
5375 (if_then_else (match_operand 2 "m16_uimm8_1")
5379 (define_expand "sle<u>"
5380 [(set (match_operand:SI 0 "register_operand")
5381 (any_le:SI (match_dup 1)
5384 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5386 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5387 [(set (match_operand:GPR2 0 "register_operand" "=d")
5388 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5389 (match_operand:GPR 2 "sle_operand" "")))]
5392 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5393 return "slt<u>\t%0,%1,%2";
5395 [(set_attr "type" "slt")
5396 (set_attr "mode" "<GPR:MODE>")])
5398 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5399 [(set (match_operand:GPR2 0 "register_operand" "=t")
5400 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5401 (match_operand:GPR 2 "sle_operand" "")))]
5404 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5405 return "slt<u>\t%1,%2";
5407 [(set_attr "type" "slt")
5408 (set_attr "mode" "<GPR:MODE>")
5409 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5414 ;; ....................
5416 ;; FLOATING POINT COMPARISONS
5418 ;; ....................
5420 (define_insn "s<code>_<mode>"
5421 [(set (match_operand:CC 0 "register_operand" "=z")
5422 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5423 (match_operand:SCALARF 2 "register_operand" "f")))]
5425 "c.<fcond>.<fmt>\t%Z0%1,%2"
5426 [(set_attr "type" "fcmp")
5427 (set_attr "mode" "FPSW")])
5429 (define_insn "s<code>_<mode>"
5430 [(set (match_operand:CC 0 "register_operand" "=z")
5431 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5432 (match_operand:SCALARF 2 "register_operand" "f")))]
5434 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5435 [(set_attr "type" "fcmp")
5436 (set_attr "mode" "FPSW")])
5439 ;; ....................
5441 ;; UNCONDITIONAL BRANCHES
5443 ;; ....................
5445 ;; Unconditional branches.
5449 (label_ref (match_operand 0 "" "")))]
5454 if (get_attr_length (insn) <= 8)
5455 return "%*b\t%l0%/";
5458 output_asm_insn (mips_output_load_label (), operands);
5459 return "%*jr\t%@%/%]";
5463 return "%*j\t%l0%/";
5465 [(set_attr "type" "jump")
5466 (set_attr "mode" "none")
5467 (set (attr "length")
5468 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5469 ;; in range, otherwise load the address of the branch target into
5470 ;; $at and then jump to it.
5472 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5473 (lt (abs (minus (match_dup 0)
5474 (plus (pc) (const_int 4))))
5475 (const_int 131072)))
5476 (const_int 4) (const_int 16)))])
5478 ;; We need a different insn for the mips16, because a mips16 branch
5479 ;; does not have a delay slot.
5483 (label_ref (match_operand 0 "" "")))]
5486 [(set_attr "type" "branch")
5487 (set_attr "mode" "none")])
5489 (define_expand "indirect_jump"
5490 [(set (pc) (match_operand 0 "register_operand"))]
5493 operands[0] = force_reg (Pmode, operands[0]);
5494 if (Pmode == SImode)
5495 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5497 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5501 (define_insn "indirect_jump<mode>"
5502 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5505 [(set_attr "type" "jump")
5506 (set_attr "mode" "none")])
5508 (define_expand "tablejump"
5510 (match_operand 0 "register_operand"))
5511 (use (label_ref (match_operand 1 "")))]
5514 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5515 operands[0] = expand_binop (Pmode, add_optab,
5516 convert_to_mode (Pmode, operands[0], false),
5517 gen_rtx_LABEL_REF (Pmode, operands[1]),
5519 else if (TARGET_GPWORD)
5520 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5521 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5522 else if (TARGET_RTP_PIC)
5524 /* When generating RTP PIC, we use case table entries that are relative
5525 to the start of the function. Add the function's address to the
5527 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5528 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5529 start, 0, 0, OPTAB_WIDEN);
5532 if (Pmode == SImode)
5533 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5535 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5539 (define_insn "tablejump<mode>"
5541 (match_operand:P 0 "register_operand" "d"))
5542 (use (label_ref (match_operand 1 "" "")))]
5545 [(set_attr "type" "jump")
5546 (set_attr "mode" "none")])
5548 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5549 ;; While it is possible to either pull it off the stack (in the
5550 ;; o32 case) or recalculate it given t9 and our target label,
5551 ;; it takes 3 or 4 insns to do so.
5553 (define_expand "builtin_setjmp_setup"
5554 [(use (match_operand 0 "register_operand"))]
5559 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5560 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5564 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5565 ;; that older code did recalculate the gp from $25. Continue to jump through
5566 ;; $25 for compatibility (we lose nothing by doing so).
5568 (define_expand "builtin_longjmp"
5569 [(use (match_operand 0 "register_operand"))]
5572 /* The elements of the buffer are, in order: */
5573 int W = GET_MODE_SIZE (Pmode);
5574 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5575 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5576 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5577 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5578 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5579 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5580 The target is bound to be using $28 as the global pointer
5581 but the current function might not be. */
5582 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5584 /* This bit is similar to expand_builtin_longjmp except that it
5585 restores $gp as well. */
5586 mips_emit_move (hard_frame_pointer_rtx, fp);
5587 mips_emit_move (pv, lab);
5588 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5589 mips_emit_move (gp, gpv);
5590 emit_use (hard_frame_pointer_rtx);
5591 emit_use (stack_pointer_rtx);
5593 emit_indirect_jump (pv);
5598 ;; ....................
5600 ;; Function prologue/epilogue
5602 ;; ....................
5605 (define_expand "prologue"
5609 mips_expand_prologue ();
5613 ;; Block any insns from being moved before this point, since the
5614 ;; profiling call to mcount can use various registers that aren't
5615 ;; saved or used to pass arguments.
5617 (define_insn "blockage"
5618 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5621 [(set_attr "type" "ghost")
5622 (set_attr "mode" "none")])
5624 (define_expand "epilogue"
5628 mips_expand_epilogue (false);
5632 (define_expand "sibcall_epilogue"
5636 mips_expand_epilogue (true);
5640 ;; Trivial return. Make it look like a normal return insn as that
5641 ;; allows jump optimizations to work better.
5643 (define_expand "return"
5645 "mips_can_use_return_insn ()"
5646 { mips_expand_before_return (); })
5648 (define_insn "*return"
5650 "mips_can_use_return_insn ()"
5652 [(set_attr "type" "jump")
5653 (set_attr "mode" "none")])
5657 (define_insn "return_internal"
5659 (use (match_operand 0 "pmode_register_operand" ""))]
5662 [(set_attr "type" "jump")
5663 (set_attr "mode" "none")])
5665 ;; This is used in compiling the unwind routines.
5666 (define_expand "eh_return"
5667 [(use (match_operand 0 "general_operand"))]
5670 if (GET_MODE (operands[0]) != word_mode)
5671 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5673 emit_insn (gen_eh_set_lr_di (operands[0]));
5675 emit_insn (gen_eh_set_lr_si (operands[0]));
5679 ;; Clobber the return address on the stack. We can't expand this
5680 ;; until we know where it will be put in the stack frame.
5682 (define_insn "eh_set_lr_si"
5683 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5684 (clobber (match_scratch:SI 1 "=&d"))]
5688 (define_insn "eh_set_lr_di"
5689 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5690 (clobber (match_scratch:DI 1 "=&d"))]
5695 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5696 (clobber (match_scratch 1))]
5700 mips_set_return_address (operands[0], operands[1]);
5704 (define_expand "exception_receiver"
5708 /* See the comment above load_call<mode> for details. */
5709 emit_insn (gen_set_got_version ());
5711 /* If we have a call-clobbered $gp, restore it from its save slot. */
5712 if (HAVE_restore_gp)
5713 emit_insn (gen_restore_gp ());
5717 (define_expand "nonlocal_goto_receiver"
5721 /* See the comment above load_call<mode> for details. */
5722 emit_insn (gen_set_got_version ());
5726 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5727 ;; volatile until all uses of $28 are exposed.
5728 (define_insn_and_split "restore_gp"
5730 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
5731 (clobber (match_scratch:SI 0 "=&d"))]
5732 "TARGET_CALL_CLOBBERED_GP"
5734 "&& reload_completed"
5737 mips_restore_gp (operands[0]);
5740 [(set_attr "type" "load")
5741 (set_attr "length" "12")])
5744 ;; ....................
5748 ;; ....................
5750 ;; Instructions to load a call address from the GOT. The address might
5751 ;; point to a function or to a lazy binding stub. In the latter case,
5752 ;; the stub will use the dynamic linker to resolve the function, which
5753 ;; in turn will change the GOT entry to point to the function's real
5756 ;; This means that every call, even pure and constant ones, can
5757 ;; potentially modify the GOT entry. And once a stub has been called,
5758 ;; we must not call it again.
5760 ;; We represent this restriction using an imaginary, fixed, call-saved
5761 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5762 ;; live throughout the function and to change its value after every
5763 ;; potential call site. This stops any rtx value that uses the register
5764 ;; from being computed before an earlier call. To do this, we:
5766 ;; - Ensure that the register is live on entry to the function,
5767 ;; so that it is never thought to be used uninitalized.
5769 ;; - Ensure that the register is live on exit from the function,
5770 ;; so that it is live throughout.
5772 ;; - Make each call (lazily-bound or not) use the current value
5773 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5774 ;; not moved across call boundaries.
5776 ;; - Add "ghost" definitions of the register to the beginning of
5777 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5778 ;; edges may involve calls that normal paths don't. (E.g. the
5779 ;; unwinding code that handles a non-call exception may change
5780 ;; lazily-bound GOT entries.) We do this by making the
5781 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5782 ;; a set_got_version instruction.
5784 ;; - After each call (lazily-bound or not), use a "ghost"
5785 ;; update_got_version instruction to change the register's value.
5786 ;; This instruction mimics the _possible_ effect of the dynamic
5787 ;; resolver during the call and it remains live even if the call
5788 ;; itself becomes dead.
5790 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5791 ;; The register is therefore not a valid register_operand
5792 ;; and cannot be moved to or from other registers.
5794 ;; Convenience expander that generates the rhs of a load_call<mode> insn.
5795 (define_expand "unspec_call<mode>"
5796 [(unspec:P [(match_operand:P 0)
5798 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL)])
5800 (define_insn "load_call<mode>"
5801 [(set (match_operand:P 0 "register_operand" "=d")
5802 (unspec:P [(match_operand:P 1 "register_operand" "d")
5803 (match_operand:P 2 "immediate_operand" "")
5804 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5806 "<load>\t%0,%R2(%1)"
5807 [(set_attr "got" "load")
5808 (set_attr "mode" "<MODE>")])
5810 (define_insn "set_got_version"
5811 [(set (reg:SI GOT_VERSION_REGNUM)
5812 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5815 [(set_attr "type" "ghost")])
5817 (define_insn "update_got_version"
5818 [(set (reg:SI GOT_VERSION_REGNUM)
5819 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5822 [(set_attr "type" "ghost")])
5824 ;; Sibling calls. All these patterns use jump instructions.
5826 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5827 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5828 ;; is defined in terms of call_insn_operand, the same is true of the
5831 ;; When we use an indirect jump, we need a register that will be
5832 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5833 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5834 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5837 (define_expand "sibcall"
5838 [(parallel [(call (match_operand 0 "")
5839 (match_operand 1 ""))
5840 (use (match_operand 2 "")) ;; next_arg_reg
5841 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5844 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
5845 operands[1], operands[2], false);
5849 (define_insn "sibcall_internal"
5850 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5851 (match_operand 1 "" ""))]
5852 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5853 { return MIPS_CALL ("j", operands, 0); }
5854 [(set_attr "type" "call")])
5856 (define_expand "sibcall_value"
5857 [(parallel [(set (match_operand 0 "")
5858 (call (match_operand 1 "")
5859 (match_operand 2 "")))
5860 (use (match_operand 3 ""))])] ;; next_arg_reg
5863 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
5864 operands[2], operands[3], false);
5868 (define_insn "sibcall_value_internal"
5869 [(set (match_operand 0 "register_operand" "")
5870 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5871 (match_operand 2 "" "")))]
5872 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5873 { return MIPS_CALL ("j", operands, 1); }
5874 [(set_attr "type" "call")])
5876 (define_insn "sibcall_value_multiple_internal"
5877 [(set (match_operand 0 "register_operand" "")
5878 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5879 (match_operand 2 "" "")))
5880 (set (match_operand 3 "register_operand" "")
5881 (call (mem:SI (match_dup 1))
5883 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5884 { return MIPS_CALL ("j", operands, 1); }
5885 [(set_attr "type" "call")])
5887 (define_expand "call"
5888 [(parallel [(call (match_operand 0 "")
5889 (match_operand 1 ""))
5890 (use (match_operand 2 "")) ;; next_arg_reg
5891 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5894 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
5895 operands[1], operands[2], false);
5899 ;; This instruction directly corresponds to an assembly-language "jal".
5900 ;; There are four cases:
5903 ;; Both symbolic and register destinations are OK. The pattern
5904 ;; always expands to a single mips instruction.
5906 ;; - -mabicalls/-mno-explicit-relocs:
5907 ;; Again, both symbolic and register destinations are OK.
5908 ;; The call is treated as a multi-instruction black box.
5910 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5911 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5914 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5915 ;; Only "jal $25" is allowed. The call is actually two instructions:
5916 ;; "jalr $25" followed by an insn to reload $gp.
5918 ;; In the last case, we can generate the individual instructions with
5919 ;; a define_split. There are several things to be wary of:
5921 ;; - We can't expose the load of $gp before reload. If we did,
5922 ;; it might get removed as dead, but reload can introduce new
5923 ;; uses of $gp by rematerializing constants.
5925 ;; - We shouldn't restore $gp after calls that never return.
5926 ;; It isn't valid to insert instructions between a noreturn
5927 ;; call and the following barrier.
5929 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5930 ;; instruction preserves $gp and so have no effect on its liveness.
5931 ;; But once we generate the separate insns, it becomes obvious that
5932 ;; $gp is not live on entry to the call.
5934 ;; ??? The operands[2] = insn check is a hack to make the original insn
5935 ;; available to the splitter.
5936 (define_insn_and_split "call_internal"
5937 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5938 (match_operand 1 "" ""))
5939 (clobber (reg:SI 31))]
5941 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5942 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5945 mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
5948 [(set_attr "jal" "indirect,direct")])
5950 (define_insn "call_split"
5951 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5952 (match_operand 1 "" ""))
5953 (clobber (reg:SI 31))
5954 (clobber (reg:SI 28))]
5955 "TARGET_SPLIT_CALLS"
5956 { return MIPS_CALL ("jal", operands, 0); }
5957 [(set_attr "type" "call")])
5959 ;; A pattern for calls that must be made directly. It is used for
5960 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5961 ;; stub; the linker relies on the call relocation type to detect when
5962 ;; such redirection is needed.
5963 (define_insn_and_split "call_internal_direct"
5964 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5967 (clobber (reg:SI 31))]
5969 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5970 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5973 mips_split_call (operands[2],
5974 gen_call_direct_split (operands[0], operands[1]));
5977 [(set_attr "type" "call")])
5979 (define_insn "call_direct_split"
5980 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5983 (clobber (reg:SI 31))
5984 (clobber (reg:SI 28))]
5985 "TARGET_SPLIT_CALLS"
5986 { return MIPS_CALL ("jal", operands, 0); }
5987 [(set_attr "type" "call")])
5989 (define_expand "call_value"
5990 [(parallel [(set (match_operand 0 "")
5991 (call (match_operand 1 "")
5992 (match_operand 2 "")))
5993 (use (match_operand 3 ""))])] ;; next_arg_reg
5996 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
5997 operands[2], operands[3], false);
6001 ;; See comment for call_internal.
6002 (define_insn_and_split "call_value_internal"
6003 [(set (match_operand 0 "register_operand" "")
6004 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6005 (match_operand 2 "" "")))
6006 (clobber (reg:SI 31))]
6008 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6009 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6012 mips_split_call (operands[3],
6013 gen_call_value_split (operands[0], operands[1],
6017 [(set_attr "jal" "indirect,direct")])
6019 (define_insn "call_value_split"
6020 [(set (match_operand 0 "register_operand" "")
6021 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6022 (match_operand 2 "" "")))
6023 (clobber (reg:SI 31))
6024 (clobber (reg:SI 28))]
6025 "TARGET_SPLIT_CALLS"
6026 { return MIPS_CALL ("jal", operands, 1); }
6027 [(set_attr "type" "call")])
6029 ;; See call_internal_direct.
6030 (define_insn_and_split "call_value_internal_direct"
6031 [(set (match_operand 0 "register_operand")
6032 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6035 (clobber (reg:SI 31))]
6037 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6038 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6041 mips_split_call (operands[3],
6042 gen_call_value_direct_split (operands[0], operands[1],
6046 [(set_attr "type" "call")])
6048 (define_insn "call_value_direct_split"
6049 [(set (match_operand 0 "register_operand")
6050 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6053 (clobber (reg:SI 31))
6054 (clobber (reg:SI 28))]
6055 "TARGET_SPLIT_CALLS"
6056 { return MIPS_CALL ("jal", operands, 1); }
6057 [(set_attr "type" "call")])
6059 ;; See comment for call_internal.
6060 (define_insn_and_split "call_value_multiple_internal"
6061 [(set (match_operand 0 "register_operand" "")
6062 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6063 (match_operand 2 "" "")))
6064 (set (match_operand 3 "register_operand" "")
6065 (call (mem:SI (match_dup 1))
6067 (clobber (reg:SI 31))]
6069 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6070 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
6073 mips_split_call (operands[4],
6074 gen_call_value_multiple_split (operands[0], operands[1],
6075 operands[2], operands[3]));
6078 [(set_attr "jal" "indirect,direct")])
6080 (define_insn "call_value_multiple_split"
6081 [(set (match_operand 0 "register_operand" "")
6082 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6083 (match_operand 2 "" "")))
6084 (set (match_operand 3 "register_operand" "")
6085 (call (mem:SI (match_dup 1))
6087 (clobber (reg:SI 31))
6088 (clobber (reg:SI 28))]
6089 "TARGET_SPLIT_CALLS"
6090 { return MIPS_CALL ("jal", operands, 1); }
6091 [(set_attr "type" "call")])
6093 ;; Call subroutine returning any type.
6095 (define_expand "untyped_call"
6096 [(parallel [(call (match_operand 0 "")
6098 (match_operand 1 "")
6099 (match_operand 2 "")])]
6104 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6106 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6108 rtx set = XVECEXP (operands[2], 0, i);
6109 mips_emit_move (SET_DEST (set), SET_SRC (set));
6112 emit_insn (gen_blockage ());
6117 ;; ....................
6121 ;; ....................
6125 (define_insn "prefetch"
6126 [(prefetch (match_operand:QI 0 "address_operand" "p")
6127 (match_operand 1 "const_int_operand" "n")
6128 (match_operand 2 "const_int_operand" "n"))]
6129 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6131 if (TARGET_LOONGSON_2EF)
6132 /* Loongson 2[ef] use load to $0 to perform prefetching. */
6133 return "ld\t$0,%a0";
6134 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6135 return "pref\t%1,%a0";
6137 [(set_attr "type" "prefetch")])
6139 (define_insn "*prefetch_indexed_<mode>"
6140 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6141 (match_operand:P 1 "register_operand" "d"))
6142 (match_operand 2 "const_int_operand" "n")
6143 (match_operand 3 "const_int_operand" "n"))]
6144 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6146 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6147 return "prefx\t%2,%1(%0)";
6149 [(set_attr "type" "prefetchx")])
6155 [(set_attr "type" "nop")
6156 (set_attr "mode" "none")])
6158 ;; Like nop, but commented out when outside a .set noreorder block.
6159 (define_insn "hazard_nop"
6168 [(set_attr "type" "nop")])
6170 ;; MIPS4 Conditional move instructions.
6172 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6173 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6175 (match_operator:MOVECC 4 "equality_operator"
6176 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6178 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6179 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6184 [(set_attr "type" "condmove")
6185 (set_attr "mode" "<GPR:MODE>")])
6187 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6188 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6189 (if_then_else:SCALARF
6190 (match_operator:MOVECC 4 "equality_operator"
6191 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6193 (match_operand:SCALARF 2 "register_operand" "f,0")
6194 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6195 "ISA_HAS_FP_CONDMOVE"
6197 mov%T4.<fmt>\t%0,%2,%1
6198 mov%t4.<fmt>\t%0,%3,%1"
6199 [(set_attr "type" "condmove")
6200 (set_attr "mode" "<SCALARF:MODE>")])
6202 ;; These are the main define_expand's used to make conditional moves.
6204 (define_expand "mov<mode>cc"
6205 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6206 (set (match_operand:GPR 0 "register_operand")
6207 (if_then_else:GPR (match_dup 5)
6208 (match_operand:GPR 2 "reg_or_0_operand")
6209 (match_operand:GPR 3 "reg_or_0_operand")))]
6212 mips_expand_conditional_move (operands);
6216 (define_expand "mov<mode>cc"
6217 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6218 (set (match_operand:SCALARF 0 "register_operand")
6219 (if_then_else:SCALARF (match_dup 5)
6220 (match_operand:SCALARF 2 "register_operand")
6221 (match_operand:SCALARF 3 "register_operand")))]
6222 "ISA_HAS_FP_CONDMOVE"
6224 mips_expand_conditional_move (operands);
6229 ;; ....................
6231 ;; mips16 inline constant tables
6233 ;; ....................
6236 (define_insn "consttable_int"
6237 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6238 (match_operand 1 "const_int_operand" "")]
6239 UNSPEC_CONSTTABLE_INT)]
6242 assemble_integer (operands[0], INTVAL (operands[1]),
6243 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6246 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6248 (define_insn "consttable_float"
6249 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6250 UNSPEC_CONSTTABLE_FLOAT)]
6255 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6256 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6257 assemble_real (d, GET_MODE (operands[0]),
6258 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6261 [(set (attr "length")
6262 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6264 (define_insn "align"
6265 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6268 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6271 [(match_operand 0 "small_data_pattern")]
6274 { operands[0] = mips_rewrite_small_data (operands[0]); })
6277 ;; ....................
6279 ;; MIPS16e Save/Restore
6281 ;; ....................
6284 (define_insn "*mips16e_save_restore"
6285 [(match_parallel 0 ""
6286 [(set (match_operand:SI 1 "register_operand")
6287 (plus:SI (match_dup 1)
6288 (match_operand:SI 2 "const_int_operand")))])]
6289 "operands[1] == stack_pointer_rtx
6290 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6291 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6292 [(set_attr "type" "arith")
6293 (set_attr "extended_mips16" "yes")])
6295 ;; Thread-Local Storage
6297 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6298 ;; MIPS architecture defines this register, and no current
6299 ;; implementation provides it; instead, any OS which supports TLS is
6300 ;; expected to trap and emulate this instruction. rdhwr is part of the
6301 ;; MIPS 32r2 specification, but we use it on any architecture because
6302 ;; we expect it to be emulated. Use .set to force the assembler to
6305 ;; We do not use a constraint to force the destination to be $3
6306 ;; because $3 can appear explicitly as a function return value.
6307 ;; If we leave the use of $3 implicit in the constraints until
6308 ;; reload, we may end up making a $3 return value live across
6309 ;; the instruction, leading to a spill failure when reloading it.
6310 (define_insn_and_split "tls_get_tp_<mode>"
6311 [(set (match_operand:P 0 "register_operand" "=d")
6312 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6313 (clobber (reg:P TLS_GET_TP_REGNUM))]
6314 "HAVE_AS_TLS && !TARGET_MIPS16"
6316 "&& reload_completed"
6317 [(set (reg:P TLS_GET_TP_REGNUM)
6318 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6319 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6321 [(set_attr "type" "unknown")
6322 ; Since rdhwr always generates a trap for now, putting it in a delay
6323 ; slot would make the kernel's emulation of it much slower.
6324 (set_attr "can_delay" "no")
6325 (set_attr "mode" "<MODE>")
6326 (set_attr "length" "8")])
6328 (define_insn "*tls_get_tp_<mode>_split"
6329 [(set (reg:P TLS_GET_TP_REGNUM)
6330 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6331 "HAVE_AS_TLS && !TARGET_MIPS16"
6332 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6333 [(set_attr "type" "unknown")
6334 ; See tls_get_tp_<mode>
6335 (set_attr "can_delay" "no")
6336 (set_attr "mode" "<MODE>")])
6338 ;; Synchronization instructions.
6342 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6344 (include "mips-ps-3d.md")
6346 ; The MIPS DSP Instructions.
6348 (include "mips-dsp.md")
6350 ; The MIPS DSP REV 2 Instructions.
6352 (include "mips-dspr2.md")
6354 ; MIPS fixed-point instructions.
6355 (include "mips-fixed.md")
6357 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6358 (include "loongson.md")