1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
26 (define_enum "processor" [
67 (define_c_enum "unspec" [
68 ;; Unaligned accesses.
74 ;; Floating-point moves.
90 UNSPEC_POTENTIAL_CPRESTORE
95 UNSPEC_SET_GOT_VERSION
96 UNSPEC_UPDATE_GOT_VERSION
104 ;; MIPS16 constant pools.
106 UNSPEC_CONSTTABLE_INT
107 UNSPEC_CONSTTABLE_FLOAT
109 ;; Blockage and synchronisation.
116 ;; Cache manipulation.
118 UNSPEC_R10K_CACHE_BARRIER
120 ;; Interrupt handling.
128 ;; Used in a call expression in place of args_size. It's present for PIC
129 ;; indirect calls where it contains args_size and the function symbol.
134 [(TLS_GET_TP_REGNUM 3)
135 (RETURN_ADDR_REGNUM 31)
136 (CPRESTORE_SLOT_REGNUM 76)
137 (GOT_VERSION_REGNUM 79)
139 ;; PIC long branch sequences are never longer than 100 bytes.
140 (MAX_PIC_BRANCH_LENGTH 100)
144 (include "predicates.md")
145 (include "constraints.md")
147 ;; ....................
151 ;; ....................
153 (define_attr "got" "unset,xgot_high,load"
154 (const_string "unset"))
156 ;; For jal instructions, this attribute is DIRECT when the target address
157 ;; is symbolic and INDIRECT when it is a register.
158 (define_attr "jal" "unset,direct,indirect"
159 (const_string "unset"))
161 ;; This attribute is YES if the instruction is a jal macro (not a
162 ;; real jal instruction).
164 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
165 ;; an instruction to restore $gp. Direct jals are also macros for
166 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
168 (define_attr "jal_macro" "no,yes"
169 (cond [(eq_attr "jal" "direct")
170 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
171 ? JAL_MACRO_YES : JAL_MACRO_NO)")
172 (eq_attr "jal" "indirect")
173 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
174 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
175 (const_string "no")))
177 ;; Classification of moves, extensions and truncations. Most values
178 ;; are as for "type" (see below) but there are also the following
179 ;; move-specific values:
181 ;; constN move an N-constraint integer into a MIPS16 register
182 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
183 ;; to produce a sign-extended DEST, even if SRC is not
184 ;; properly sign-extended
185 ;; ext_ins EXT, DEXT, INS or DINS instruction
186 ;; andi a single ANDI instruction
187 ;; loadpool move a constant into a MIPS16 register by loading it
189 ;; shift_shift a shift left followed by a shift right
190 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
192 ;; This attribute is used to determine the instruction's length and
193 ;; scheduling type. For doubleword moves, the attribute always describes
194 ;; the split instructions; in some cases, it is more appropriate for the
195 ;; scheduling type to be "multi" instead.
196 (define_attr "move_type"
197 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
198 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
199 shift_shift,lui_movf"
200 (const_string "unknown"))
202 ;; Main data type used by the insn
203 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
204 (const_string "unknown"))
206 ;; True if the main data type is twice the size of a word.
207 (define_attr "dword_mode" "no,yes"
208 (cond [(and (eq_attr "mode" "DI,DF")
209 (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
212 (and (eq_attr "mode" "TI,TF")
213 (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
214 (const_string "yes")]
215 (const_string "no")))
217 ;; Classification of each insn.
218 ;; branch conditional branch
219 ;; jump unconditional jump
220 ;; call unconditional call
221 ;; load load instruction(s)
222 ;; fpload floating point load
223 ;; fpidxload floating point indexed load
224 ;; store store instruction(s)
225 ;; fpstore floating point store
226 ;; fpidxstore floating point indexed store
227 ;; prefetch memory prefetch (register + offset)
228 ;; prefetchx memory indexed prefetch (register + register)
229 ;; condmove conditional moves
230 ;; mtc transfer to coprocessor
231 ;; mfc transfer from coprocessor
232 ;; mthilo transfer to hi/lo registers
233 ;; mfhilo transfer from hi/lo registers
234 ;; const load constant
235 ;; arith integer arithmetic instructions
236 ;; logical integer logical instructions
237 ;; shift integer shift instructions
238 ;; slt set less than instructions
239 ;; signext sign extend instructions
240 ;; clz the clz and clo instructions
241 ;; pop the pop instruction
242 ;; trap trap if instructions
243 ;; imul integer multiply 2 operands
244 ;; imul3 integer multiply 3 operands
245 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
246 ;; imadd integer multiply-add
247 ;; idiv integer divide 2 operands
248 ;; idiv3 integer divide 3 operands
249 ;; move integer register move ({,D}ADD{,U} with rt = 0)
250 ;; fmove floating point register move
251 ;; fadd floating point add/subtract
252 ;; fmul floating point multiply
253 ;; fmadd floating point multiply-add
254 ;; fdiv floating point divide
255 ;; frdiv floating point reciprocal divide
256 ;; frdiv1 floating point reciprocal divide step 1
257 ;; frdiv2 floating point reciprocal divide step 2
258 ;; fabs floating point absolute value
259 ;; fneg floating point negation
260 ;; fcmp floating point compare
261 ;; fcvt floating point convert
262 ;; fsqrt floating point square root
263 ;; frsqrt floating point reciprocal square root
264 ;; frsqrt1 floating point reciprocal square root step1
265 ;; frsqrt2 floating point reciprocal square root step2
266 ;; multi multiword sequence (or user asm statements)
268 ;; ghost an instruction that produces no real code
270 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
271 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
272 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
273 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
274 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
275 (cond [(eq_attr "jal" "!unset") (const_string "call")
276 (eq_attr "got" "load") (const_string "load")
278 ;; If a doubleword move uses these expensive instructions,
279 ;; it is usually better to schedule them in the same way
280 ;; as the singleword form, rather than as "multi".
281 (eq_attr "move_type" "load") (const_string "load")
282 (eq_attr "move_type" "fpload") (const_string "fpload")
283 (eq_attr "move_type" "store") (const_string "store")
284 (eq_attr "move_type" "fpstore") (const_string "fpstore")
285 (eq_attr "move_type" "mtc") (const_string "mtc")
286 (eq_attr "move_type" "mfc") (const_string "mfc")
287 (eq_attr "move_type" "mthilo") (const_string "mthilo")
288 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
290 ;; These types of move are always single insns.
291 (eq_attr "move_type" "fmove") (const_string "fmove")
292 (eq_attr "move_type" "loadpool") (const_string "load")
293 (eq_attr "move_type" "signext") (const_string "signext")
294 (eq_attr "move_type" "ext_ins") (const_string "arith")
295 (eq_attr "move_type" "arith") (const_string "arith")
296 (eq_attr "move_type" "logical") (const_string "logical")
297 (eq_attr "move_type" "sll0") (const_string "shift")
298 (eq_attr "move_type" "andi") (const_string "logical")
300 ;; These types of move are always split.
301 (eq_attr "move_type" "constN,shift_shift")
302 (const_string "multi")
304 ;; These types of move are split for doubleword modes only.
305 (and (eq_attr "move_type" "move,const")
306 (eq_attr "dword_mode" "yes"))
307 (const_string "multi")
308 (eq_attr "move_type" "move") (const_string "move")
309 (eq_attr "move_type" "const") (const_string "const")]
310 ;; We classify "lui_movf" as "unknown" rather than "multi"
311 ;; because we don't split it. FIXME: we should split instead.
312 (const_string "unknown")))
314 ;; Mode for conversion types (fcvt)
315 ;; I2S integer to float single (SI/DI to SF)
316 ;; I2D integer to float double (SI/DI to DF)
317 ;; S2I float to integer (SF to SI/DI)
318 ;; D2I float to integer (DF to SI/DI)
319 ;; D2S double to float single
320 ;; S2D float single to double
322 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
323 (const_string "unknown"))
325 ;; Is this an extended instruction in mips16 mode?
326 (define_attr "extended_mips16" "no,yes"
327 (if_then_else (ior (eq_attr "move_type" "sll0")
328 (eq_attr "type" "branch")
329 (eq_attr "jal" "direct"))
331 (const_string "no")))
333 ;; Attributes describing a sync loop. These loops have the form:
335 ;; if (RELEASE_BARRIER == YES) sync
337 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
338 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
339 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
340 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
341 ;; $AT |= $TMP1 | $TMP3
342 ;; if (!commit (*MEM = $AT)) goto 1.
343 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
347 ;; where "$" values are temporaries and where the other values are
348 ;; specified by the attributes below. Values are specified as operand
349 ;; numbers and insns are specified as enums. If no operand number is
350 ;; specified, the following values are used instead:
354 ;; - INCLUSIVE_MASK: -1
355 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
356 ;; - EXCLUSIVE_MASK: 0
358 ;; MEM and INSN1_OP2 are required.
360 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
361 ;; but the gen* programs don't yet support that.
362 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
363 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
364 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
365 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
366 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
367 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
368 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
369 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
370 (const_string "move"))
371 (define_attr "sync_insn2" "nop,and,xor,not"
372 (const_string "nop"))
373 (define_attr "sync_release_barrier" "yes,no"
374 (const_string "yes"))
376 ;; Length of instruction in bytes.
377 (define_attr "length" ""
378 (cond [(and (eq_attr "extended_mips16" "yes")
379 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
382 ;; Direct branch instructions have a range of [-0x20000,0x1fffc],
383 ;; relative to the address of the delay slot. If a branch is
384 ;; outside this range, we have a choice of two sequences.
385 ;; For PIC, an out-of-range branch like:
390 ;; becomes the equivalent of:
399 ;; The non-PIC case is similar except that we use a direct
400 ;; jump instead of an la/jr pair. Since the target of this
401 ;; jump is an absolute 28-bit bit address (the other bits
402 ;; coming from the address of the delay slot) this form cannot
403 ;; cross a 256MB boundary. We could provide the option of
404 ;; using la/jr in this case too, but we do not do so at
407 ;; Note that this value does not account for the delay slot
408 ;; instruction, whose length is added separately. If the RTL
409 ;; pattern has no explicit delay slot, mips_adjust_insn_length
410 ;; will add the length of the implicit nop. The values for
411 ;; forward and backward branches will be different as well.
412 (eq_attr "type" "branch")
413 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 131064))
414 (le (minus (pc) (match_dup 0)) (const_int 131068)))
417 ;; The non-PIC case: branch, first delay slot, and J.
418 (ne (symbol_ref "TARGET_ABSOLUTE_JUMPS") (const_int 0))
421 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
422 ;; mips_adjust_insn_length substitutes the correct length.
424 ;; Note that we can't simply use (symbol_ref ...) here
425 ;; because genattrtab needs to know the maximum length
427 (const_int MAX_PIC_BRANCH_LENGTH))
429 ;; "Ghost" instructions occupy no space.
430 (eq_attr "type" "ghost")
433 (eq_attr "got" "load")
434 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
437 (eq_attr "got" "xgot_high")
440 ;; In general, constant-pool loads are extended instructions.
441 (eq_attr "move_type" "loadpool")
444 ;; LUI_MOVFs are decomposed into two separate instructions.
445 (eq_attr "move_type" "lui_movf")
448 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
449 ;; They are extended instructions on MIPS16 targets.
450 (eq_attr "move_type" "shift_shift")
451 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
455 ;; Check for doubleword moves that are decomposed into two
457 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
458 (eq_attr "dword_mode" "yes"))
461 ;; Doubleword CONST{,N} moves are split into two word
463 (and (eq_attr "move_type" "const,constN")
464 (eq_attr "dword_mode" "yes"))
465 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
467 ;; Otherwise, constants, loads and stores are handled by external
469 (eq_attr "move_type" "const,constN")
470 (symbol_ref "mips_const_insns (operands[1]) * 4")
471 (eq_attr "move_type" "load,fpload")
472 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
473 (eq_attr "move_type" "store,fpstore")
474 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
476 ;; In the worst case, a call macro will take 8 instructions:
478 ;; lui $25,%call_hi(FOO)
480 ;; lw $25,%call_lo(FOO)($25)
486 (eq_attr "jal_macro" "yes")
489 ;; Various VR4120 errata require a nop to be inserted after a macc
490 ;; instruction. The assembler does this for us, so account for
491 ;; the worst-case length here.
492 (and (eq_attr "type" "imadd")
493 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
496 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
497 ;; the result of the second one is missed. The assembler should work
498 ;; around this by inserting a nop after the first dmult.
499 (and (eq_attr "type" "imul,imul3")
500 (and (eq_attr "mode" "DI")
501 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
504 (eq_attr "type" "idiv,idiv3")
505 (symbol_ref "mips_idiv_insns () * 4")
507 (not (eq_attr "sync_mem" "none"))
508 (symbol_ref "mips_sync_loop_insns (insn, operands) * 4")
511 ;; Attribute describing the processor.
512 (define_enum_attr "cpu" "processor"
513 (const (symbol_ref "mips_tune")))
515 ;; The type of hardware hazard associated with this instruction.
516 ;; DELAY means that the next instruction cannot read the result
517 ;; of this one. HILO means that the next two instructions cannot
518 ;; write to HI or LO.
519 (define_attr "hazard" "none,delay,hilo"
520 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
521 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
522 (const_string "delay")
524 (and (eq_attr "type" "mfc,mtc")
525 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
526 (const_string "delay")
528 (and (eq_attr "type" "fcmp")
529 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
530 (const_string "delay")
532 ;; The r4000 multiplication patterns include an mflo instruction.
533 (and (eq_attr "type" "imul")
534 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
535 (const_string "hilo")
537 (and (eq_attr "type" "mfhilo")
538 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
539 (const_string "hilo")]
540 (const_string "none")))
542 ;; Is it a single instruction?
543 (define_attr "single_insn" "no,yes"
544 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
545 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
547 ;; Can the instruction be put into a delay slot?
548 (define_attr "can_delay" "no,yes"
549 (if_then_else (and (eq_attr "type" "!branch,call,jump")
550 (and (eq_attr "hazard" "none")
551 (eq_attr "single_insn" "yes")))
553 (const_string "no")))
555 ;; Attribute defining whether or not we can use the branch-likely
557 (define_attr "branch_likely" "no,yes"
558 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
560 (const_string "no")))
562 ;; True if an instruction might assign to hi or lo when reloaded.
563 ;; This is used by the TUNE_MACC_CHAINS code.
564 (define_attr "may_clobber_hilo" "no,yes"
565 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
567 (const_string "no")))
569 ;; Describe a user's asm statement.
570 (define_asm_attributes
571 [(set_attr "type" "multi")
572 (set_attr "can_delay" "no")])
574 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
575 ;; from the same template.
576 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
578 ;; A copy of GPR that can be used when a pattern has two independent
580 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
582 ;; This mode iterator allows :HILO to be used as the mode of the
583 ;; concatenated HI and LO registers.
584 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
586 ;; This mode iterator allows :P to be used for patterns that operate on
587 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
588 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
590 ;; This mode iterator allows :MOVECC to be used anywhere that a
591 ;; conditional-move-type condition is needed.
592 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
593 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
595 ;; 32-bit integer moves for which we provide move patterns.
596 (define_mode_iterator IMOVE32
605 (V4UQQ "TARGET_DSP")])
607 ;; 64-bit modes for which we provide move patterns.
608 (define_mode_iterator MOVE64
610 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
611 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
612 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
613 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
615 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
616 (define_mode_iterator MOVE128 [TI TF])
618 ;; This mode iterator allows the QI and HI extension patterns to be
619 ;; defined from the same template.
620 (define_mode_iterator SHORT [QI HI])
622 ;; Likewise the 64-bit truncate-and-shift patterns.
623 (define_mode_iterator SUBDI [QI HI SI])
625 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
626 ;; floating-point mode is allowed.
627 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
628 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
629 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
631 ;; Like ANYF, but only applies to scalar modes.
632 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
633 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
635 ;; A floating-point mode for which moves involving FPRs may need to be split.
636 (define_mode_iterator SPLITF
637 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
638 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
639 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
640 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
641 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
642 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
643 (TF "TARGET_64BIT && TARGET_FLOAT64")])
645 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
646 ;; 32-bit version and "dsubu" in the 64-bit version.
647 (define_mode_attr d [(SI "") (DI "d")
648 (QQ "") (HQ "") (SQ "") (DQ "d")
649 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
650 (HA "") (SA "") (DA "d")
651 (UHA "") (USA "") (UDA "d")])
653 ;; Same as d but upper-case.
654 (define_mode_attr D [(SI "") (DI "D")
655 (QQ "") (HQ "") (SQ "") (DQ "D")
656 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
657 (HA "") (SA "") (DA "D")
658 (UHA "") (USA "") (UDA "D")])
660 ;; This attribute gives the length suffix for a sign- or zero-extension
662 (define_mode_attr size [(QI "b") (HI "h")])
664 ;; This attributes gives the mode mask of a SHORT.
665 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
667 ;; Mode attributes for GPR loads.
668 (define_mode_attr load [(SI "lw") (DI "ld")])
669 ;; Instruction names for stores.
670 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
672 ;; Similarly for MIPS IV indexed FPR loads and stores.
673 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
674 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
676 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
677 ;; are different. Some forms of unextended addiu have an 8-bit immediate
678 ;; field but the equivalent daddiu has only a 5-bit field.
679 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
681 ;; This attribute gives the best constraint to use for registers of
683 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
685 ;; This attribute gives the format suffix for floating-point operations.
686 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
688 ;; This attribute gives the upper-case mode name for one unit of a
689 ;; floating-point mode.
690 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
692 ;; This attribute gives the integer mode that has the same size as a
694 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
695 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
696 (HA "HI") (SA "SI") (DA "DI")
697 (UHA "HI") (USA "SI") (UDA "DI")
698 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
699 (V2HQ "SI") (V2HA "SI")])
701 ;; This attribute gives the integer mode that has half the size of
702 ;; the controlling mode.
703 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
704 (V2SI "SI") (V4HI "SI") (V8QI "SI")
707 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
709 ;; In certain cases, div.s and div.ps may have a rounding error
710 ;; and/or wrong inexact flag.
712 ;; Therefore, we only allow div.s if not working around SB-1 rev2
713 ;; errata or if a slight loss of precision is OK.
714 (define_mode_attr divide_condition
715 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
716 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
718 ;; This attribute gives the conditions under which SQRT.fmt instructions
720 (define_mode_attr sqrt_condition
721 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
723 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
724 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
725 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
726 ;; so for safety's sake, we apply this restriction to all targets.
727 (define_mode_attr recip_condition
729 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
730 (V2SF "TARGET_SB1")])
732 ;; This code iterator allows signed and unsigned widening multiplications
733 ;; to use the same template.
734 (define_code_iterator any_extend [sign_extend zero_extend])
736 ;; This code iterator allows the two right shift instructions to be
737 ;; generated from the same template.
738 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
740 ;; This code iterator allows the three shift instructions to be generated
741 ;; from the same template.
742 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
744 ;; This code iterator allows unsigned and signed division to be generated
745 ;; from the same template.
746 (define_code_iterator any_div [div udiv])
748 ;; This code iterator allows unsigned and signed modulus to be generated
749 ;; from the same template.
750 (define_code_iterator any_mod [mod umod])
752 ;; This code iterator allows all native floating-point comparisons to be
753 ;; generated from the same template.
754 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
756 ;; This code iterator is used for comparisons that can be implemented
757 ;; by swapping the operands.
758 (define_code_iterator swapped_fcond [ge gt unge ungt])
760 ;; Equality operators.
761 (define_code_iterator equality_op [eq ne])
763 ;; These code iterators allow the signed and unsigned scc operations to use
764 ;; the same template.
765 (define_code_iterator any_gt [gt gtu])
766 (define_code_iterator any_ge [ge geu])
767 (define_code_iterator any_lt [lt ltu])
768 (define_code_iterator any_le [le leu])
770 ;; <u> expands to an empty string when doing a signed operation and
771 ;; "u" when doing an unsigned operation.
772 (define_code_attr u [(sign_extend "") (zero_extend "u")
780 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
781 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
783 ;; <optab> expands to the name of the optab for a particular code.
784 (define_code_attr optab [(ashift "ashl")
793 ;; <insn> expands to the name of the insn that implements a particular code.
794 (define_code_attr insn [(ashift "sll")
803 ;; <immediate_insn> expands to the name of the insn that implements
804 ;; a particular code to operate on immediate values.
805 (define_code_attr immediate_insn [(ior "ori")
809 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
810 (define_code_attr fcond [(unordered "un")
818 ;; Similar, but for swapped conditions.
819 (define_code_attr swapped_fcond [(ge "le")
824 ;; The value of the bit when the branch is taken for branch_bit patterns.
825 ;; Comparison is always against zero so this depends on the operator.
826 (define_code_attr bbv [(eq "0") (ne "1")])
828 ;; This is the inverse value of bbv.
829 (define_code_attr bbinv [(eq "1") (ne "0")])
831 ;; .........................
833 ;; Branch, call and jump delay slots
835 ;; .........................
837 (define_delay (and (eq_attr "type" "branch")
838 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
839 (eq_attr "branch_likely" "yes"))
840 [(eq_attr "can_delay" "yes")
842 (eq_attr "can_delay" "yes")])
844 ;; Branches that don't have likely variants do not annul on false.
845 (define_delay (and (eq_attr "type" "branch")
846 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
847 (eq_attr "branch_likely" "no"))
848 [(eq_attr "can_delay" "yes")
852 (define_delay (eq_attr "type" "jump")
853 [(eq_attr "can_delay" "yes")
857 (define_delay (and (eq_attr "type" "call")
858 (eq_attr "jal_macro" "no"))
859 [(eq_attr "can_delay" "yes")
863 ;; Pipeline descriptions.
865 ;; generic.md provides a fallback for processors without a specific
866 ;; pipeline description. It is derived from the old define_function_unit
867 ;; version and uses the "alu" and "imuldiv" units declared below.
869 ;; Some of the processor-specific files are also derived from old
870 ;; define_function_unit descriptions and simply override the parts of
871 ;; generic.md that don't apply. The other processor-specific files
872 ;; are self-contained.
873 (define_automaton "alu,imuldiv")
875 (define_cpu_unit "alu" "alu")
876 (define_cpu_unit "imuldiv" "imuldiv")
878 ;; Ghost instructions produce no real code and introduce no hazards.
879 ;; They exist purely to express an effect on dataflow.
880 (define_insn_reservation "ghost" 0
881 (eq_attr "type" "ghost")
902 (include "loongson2ef.md")
903 (include "octeon.md")
907 (include "generic.md")
910 ;; ....................
914 ;; ....................
918 [(trap_if (const_int 1) (const_int 0))]
921 if (ISA_HAS_COND_TRAP)
923 else if (TARGET_MIPS16)
928 [(set_attr "type" "trap")])
930 (define_expand "ctrap<mode>4"
931 [(trap_if (match_operator 0 "comparison_operator"
932 [(match_operand:GPR 1 "reg_or_0_operand")
933 (match_operand:GPR 2 "arith_operand")])
934 (match_operand 3 "const_0_operand"))]
937 mips_expand_conditional_trap (operands[0]);
941 (define_insn "*conditional_trap<mode>"
942 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
943 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
944 (match_operand:GPR 2 "arith_operand" "dI")])
948 [(set_attr "type" "trap")])
951 ;; ....................
955 ;; ....................
958 (define_insn "add<mode>3"
959 [(set (match_operand:ANYF 0 "register_operand" "=f")
960 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
961 (match_operand:ANYF 2 "register_operand" "f")))]
963 "add.<fmt>\t%0,%1,%2"
964 [(set_attr "type" "fadd")
965 (set_attr "mode" "<UNITMODE>")])
967 (define_expand "add<mode>3"
968 [(set (match_operand:GPR 0 "register_operand")
969 (plus:GPR (match_operand:GPR 1 "register_operand")
970 (match_operand:GPR 2 "arith_operand")))]
973 (define_insn "*add<mode>3"
974 [(set (match_operand:GPR 0 "register_operand" "=d,d")
975 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
976 (match_operand:GPR 2 "arith_operand" "d,Q")))]
981 [(set_attr "type" "arith")
982 (set_attr "mode" "<MODE>")])
984 (define_insn "*add<mode>3_mips16"
985 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
986 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
987 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
995 [(set_attr "type" "arith")
996 (set_attr "mode" "<MODE>")
997 (set_attr_alternative "length"
998 [(if_then_else (match_operand 2 "m16_simm8_8")
1001 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1004 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1007 (if_then_else (match_operand 2 "m16_simm4_1")
1012 ;; On the mips16, we can sometimes split an add of a constant which is
1013 ;; a 4 byte instruction into two adds which are both 2 byte
1014 ;; instructions. There are two cases: one where we are adding a
1015 ;; constant plus a register to another register, and one where we are
1016 ;; simply adding a constant to a register.
1019 [(set (match_operand:SI 0 "d_operand")
1020 (plus:SI (match_dup 0)
1021 (match_operand:SI 1 "const_int_operand")))]
1022 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1023 && ((INTVAL (operands[1]) > 0x7f
1024 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1025 || (INTVAL (operands[1]) < - 0x80
1026 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1027 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1028 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1030 HOST_WIDE_INT val = INTVAL (operands[1]);
1034 operands[1] = GEN_INT (0x7f);
1035 operands[2] = GEN_INT (val - 0x7f);
1039 operands[1] = GEN_INT (- 0x80);
1040 operands[2] = GEN_INT (val + 0x80);
1045 [(set (match_operand:SI 0 "d_operand")
1046 (plus:SI (match_operand:SI 1 "d_operand")
1047 (match_operand:SI 2 "const_int_operand")))]
1048 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1049 && REGNO (operands[0]) != REGNO (operands[1])
1050 && ((INTVAL (operands[2]) > 0x7
1051 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1052 || (INTVAL (operands[2]) < - 0x8
1053 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1054 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1055 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1057 HOST_WIDE_INT val = INTVAL (operands[2]);
1061 operands[2] = GEN_INT (0x7);
1062 operands[3] = GEN_INT (val - 0x7);
1066 operands[2] = GEN_INT (- 0x8);
1067 operands[3] = GEN_INT (val + 0x8);
1072 [(set (match_operand:DI 0 "d_operand")
1073 (plus:DI (match_dup 0)
1074 (match_operand:DI 1 "const_int_operand")))]
1075 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1076 && ((INTVAL (operands[1]) > 0xf
1077 && INTVAL (operands[1]) <= 0xf + 0xf)
1078 || (INTVAL (operands[1]) < - 0x10
1079 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1080 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1081 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1083 HOST_WIDE_INT val = INTVAL (operands[1]);
1087 operands[1] = GEN_INT (0xf);
1088 operands[2] = GEN_INT (val - 0xf);
1092 operands[1] = GEN_INT (- 0x10);
1093 operands[2] = GEN_INT (val + 0x10);
1098 [(set (match_operand:DI 0 "d_operand")
1099 (plus:DI (match_operand:DI 1 "d_operand")
1100 (match_operand:DI 2 "const_int_operand")))]
1101 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1102 && REGNO (operands[0]) != REGNO (operands[1])
1103 && ((INTVAL (operands[2]) > 0x7
1104 && INTVAL (operands[2]) <= 0x7 + 0xf)
1105 || (INTVAL (operands[2]) < - 0x8
1106 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1107 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1108 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1110 HOST_WIDE_INT val = INTVAL (operands[2]);
1114 operands[2] = GEN_INT (0x7);
1115 operands[3] = GEN_INT (val - 0x7);
1119 operands[2] = GEN_INT (- 0x8);
1120 operands[3] = GEN_INT (val + 0x8);
1124 (define_insn "*addsi3_extended"
1125 [(set (match_operand:DI 0 "register_operand" "=d,d")
1127 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1128 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1129 "TARGET_64BIT && !TARGET_MIPS16"
1133 [(set_attr "type" "arith")
1134 (set_attr "mode" "SI")])
1136 ;; Split this insn so that the addiu splitters can have a crack at it.
1137 ;; Use a conservative length estimate until the split.
1138 (define_insn_and_split "*addsi3_extended_mips16"
1139 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1141 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1142 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1143 "TARGET_64BIT && TARGET_MIPS16"
1145 "&& reload_completed"
1146 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1147 { operands[3] = gen_lowpart (SImode, operands[0]); }
1148 [(set_attr "type" "arith")
1149 (set_attr "mode" "SI")
1150 (set_attr "extended_mips16" "yes")])
1152 ;; Combiner patterns for unsigned byte-add.
1154 (define_insn "*baddu_si_eb"
1155 [(set (match_operand:SI 0 "register_operand" "=d")
1158 (plus:SI (match_operand:SI 1 "register_operand" "d")
1159 (match_operand:SI 2 "register_operand" "d")) 3)))]
1160 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1162 [(set_attr "type" "arith")])
1164 (define_insn "*baddu_si_el"
1165 [(set (match_operand:SI 0 "register_operand" "=d")
1168 (plus:SI (match_operand:SI 1 "register_operand" "d")
1169 (match_operand:SI 2 "register_operand" "d")) 0)))]
1170 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1172 [(set_attr "type" "arith")])
1174 (define_insn "*baddu_di<mode>"
1175 [(set (match_operand:GPR 0 "register_operand" "=d")
1178 (plus:DI (match_operand:DI 1 "register_operand" "d")
1179 (match_operand:DI 2 "register_operand" "d")))))]
1180 "ISA_HAS_BADDU && TARGET_64BIT"
1182 [(set_attr "type" "arith")])
1185 ;; ....................
1189 ;; ....................
1192 (define_insn "sub<mode>3"
1193 [(set (match_operand:ANYF 0 "register_operand" "=f")
1194 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1195 (match_operand:ANYF 2 "register_operand" "f")))]
1197 "sub.<fmt>\t%0,%1,%2"
1198 [(set_attr "type" "fadd")
1199 (set_attr "mode" "<UNITMODE>")])
1201 (define_insn "sub<mode>3"
1202 [(set (match_operand:GPR 0 "register_operand" "=d")
1203 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1204 (match_operand:GPR 2 "register_operand" "d")))]
1207 [(set_attr "type" "arith")
1208 (set_attr "mode" "<MODE>")])
1210 (define_insn "*subsi3_extended"
1211 [(set (match_operand:DI 0 "register_operand" "=d")
1213 (minus:SI (match_operand:SI 1 "register_operand" "d")
1214 (match_operand:SI 2 "register_operand" "d"))))]
1217 [(set_attr "type" "arith")
1218 (set_attr "mode" "DI")])
1221 ;; ....................
1225 ;; ....................
1228 (define_expand "mul<mode>3"
1229 [(set (match_operand:SCALARF 0 "register_operand")
1230 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1231 (match_operand:SCALARF 2 "register_operand")))]
1235 (define_insn "*mul<mode>3"
1236 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1237 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1238 (match_operand:SCALARF 2 "register_operand" "f")))]
1239 "!TARGET_4300_MUL_FIX"
1240 "mul.<fmt>\t%0,%1,%2"
1241 [(set_attr "type" "fmul")
1242 (set_attr "mode" "<MODE>")])
1244 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1245 ;; operands may corrupt immediately following multiplies. This is a
1246 ;; simple fix to insert NOPs.
1248 (define_insn "*mul<mode>3_r4300"
1249 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1250 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1251 (match_operand:SCALARF 2 "register_operand" "f")))]
1252 "TARGET_4300_MUL_FIX"
1253 "mul.<fmt>\t%0,%1,%2\;nop"
1254 [(set_attr "type" "fmul")
1255 (set_attr "mode" "<MODE>")
1256 (set_attr "length" "8")])
1258 (define_insn "mulv2sf3"
1259 [(set (match_operand:V2SF 0 "register_operand" "=f")
1260 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1261 (match_operand:V2SF 2 "register_operand" "f")))]
1262 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1264 [(set_attr "type" "fmul")
1265 (set_attr "mode" "SF")])
1267 ;; The original R4000 has a cpu bug. If a double-word or a variable
1268 ;; shift executes while an integer multiplication is in progress, the
1269 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1270 ;; with the mult on the R4000.
1272 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1273 ;; (also valid for MIPS R4000MC processors):
1275 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1276 ;; this errata description.
1277 ;; The following code sequence causes the R4000 to incorrectly
1278 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1279 ;; instruction. If the dsra32 instruction is executed during an
1280 ;; integer multiply, the dsra32 will only shift by the amount in
1281 ;; specified in the instruction rather than the amount plus 32
1283 ;; instruction 1: mult rs,rt integer multiply
1284 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1285 ;; right arithmetic + 32
1286 ;; Workaround: A dsra32 instruction placed after an integer
1287 ;; multiply should not be one of the 11 instructions after the
1288 ;; multiply instruction."
1292 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1293 ;; the following description.
1294 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1295 ;; 64-bit versions) may produce incorrect results under the
1296 ;; following conditions:
1297 ;; 1) An integer multiply is currently executing
1298 ;; 2) These types of shift instructions are executed immediately
1299 ;; following an integer divide instruction.
1301 ;; 1) Make sure no integer multiply is running wihen these
1302 ;; instruction are executed. If this cannot be predicted at
1303 ;; compile time, then insert a "mfhi" to R0 instruction
1304 ;; immediately after the integer multiply instruction. This
1305 ;; will cause the integer multiply to complete before the shift
1307 ;; 2) Separate integer divide and these two classes of shift
1308 ;; instructions by another instruction or a noop."
1310 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1313 (define_expand "mul<mode>3"
1314 [(set (match_operand:GPR 0 "register_operand")
1315 (mult:GPR (match_operand:GPR 1 "register_operand")
1316 (match_operand:GPR 2 "register_operand")))]
1319 if (TARGET_LOONGSON_2EF)
1320 emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
1322 else if (ISA_HAS_<D>MUL3)
1323 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1324 else if (TARGET_FIX_R4000)
1325 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1328 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1332 (define_insn "mul<mode>3_mul3_ls2ef"
1333 [(set (match_operand:GPR 0 "register_operand" "=d")
1334 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1335 (match_operand:GPR 2 "register_operand" "d")))]
1336 "TARGET_LOONGSON_2EF"
1337 "<d>multu.g\t%0,%1,%2"
1338 [(set_attr "type" "imul3nc")
1339 (set_attr "mode" "<MODE>")])
1341 (define_insn "mul<mode>3_mul3"
1342 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1343 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1344 (match_operand:GPR 2 "register_operand" "d,d")))
1345 (clobber (match_scratch:GPR 3 "=l,X"))]
1348 if (which_alternative == 1)
1349 return "<d>mult\t%1,%2";
1350 if (<MODE>mode == SImode && TARGET_MIPS3900)
1351 return "mult\t%0,%1,%2";
1352 return "<d>mul\t%0,%1,%2";
1354 [(set_attr "type" "imul3,imul")
1355 (set_attr "mode" "<MODE>")])
1357 ;; If a register gets allocated to LO, and we spill to memory, the reload
1358 ;; will include a move from LO to a GPR. Merge it into the multiplication
1359 ;; if it can set the GPR directly.
1362 ;; Operand 1: GPR (1st multiplication operand)
1363 ;; Operand 2: GPR (2nd multiplication operand)
1364 ;; Operand 3: GPR (destination)
1367 [(set (match_operand:SI 0 "lo_operand")
1368 (mult:SI (match_operand:SI 1 "d_operand")
1369 (match_operand:SI 2 "d_operand")))
1370 (clobber (scratch:SI))])
1371 (set (match_operand:SI 3 "d_operand")
1373 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1376 (mult:SI (match_dup 1)
1378 (clobber (match_dup 0))])])
1380 (define_insn "mul<mode>3_internal"
1381 [(set (match_operand:GPR 0 "register_operand" "=l")
1382 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1383 (match_operand:GPR 2 "register_operand" "d")))]
1386 [(set_attr "type" "imul")
1387 (set_attr "mode" "<MODE>")])
1389 (define_insn "mul<mode>3_r4000"
1390 [(set (match_operand:GPR 0 "register_operand" "=d")
1391 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1392 (match_operand:GPR 2 "register_operand" "d")))
1393 (clobber (match_scratch:GPR 3 "=l"))]
1395 "<d>mult\t%1,%2\;mflo\t%0"
1396 [(set_attr "type" "imul")
1397 (set_attr "mode" "<MODE>")
1398 (set_attr "length" "8")])
1400 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1401 ;; of "mult; mflo". They have the same latency, but the first form gives
1402 ;; us an extra cycle to compute the operands.
1405 ;; Operand 1: GPR (1st multiplication operand)
1406 ;; Operand 2: GPR (2nd multiplication operand)
1407 ;; Operand 3: GPR (destination)
1409 [(set (match_operand:SI 0 "lo_operand")
1410 (mult:SI (match_operand:SI 1 "d_operand")
1411 (match_operand:SI 2 "d_operand")))
1412 (set (match_operand:SI 3 "d_operand")
1414 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1419 (plus:SI (mult:SI (match_dup 1)
1423 (plus:SI (mult:SI (match_dup 1)
1427 ;; Multiply-accumulate patterns
1429 ;; This pattern is first matched by combine, which tries to use the
1430 ;; pattern wherever it can. We don't know until later whether it
1431 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1432 ;; so we need to keep both options open.
1434 ;; The second alternative has a "?" marker because it is generally
1435 ;; one instruction more costly than the first alternative. This "?"
1436 ;; marker is enough to convey the relative costs to the register
1439 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1440 ;; reloads of the other operands, even though operands 4 and 5 need no
1441 ;; copy instructions. Reload therefore thinks that the second alternative
1442 ;; is two reloads more costly than the first. We add "*?*?" to the first
1443 ;; alternative as a counterweight.
1444 (define_insn "*mul_acc_si"
1445 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1446 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1447 (match_operand:SI 2 "register_operand" "d,d"))
1448 (match_operand:SI 3 "register_operand" "0,d")))
1449 (clobber (match_scratch:SI 4 "=X,l"))
1450 (clobber (match_scratch:SI 5 "=X,&d"))]
1451 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1455 [(set_attr "type" "imadd")
1456 (set_attr "mode" "SI")
1457 (set_attr "length" "4,8")])
1459 ;; The same idea applies here. The middle alternative needs one less
1460 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1461 (define_insn "*mul_acc_si_r3900"
1462 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1463 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1464 (match_operand:SI 2 "register_operand" "d,d,d"))
1465 (match_operand:SI 3 "register_operand" "0,l,d")))
1466 (clobber (match_scratch:SI 4 "=X,3,l"))
1467 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1468 "TARGET_MIPS3900 && !TARGET_MIPS16"
1473 [(set_attr "type" "imadd")
1474 (set_attr "mode" "SI")
1475 (set_attr "length" "4,4,8")])
1477 ;; Split *mul_acc_si if both the source and destination accumulator
1480 [(set (match_operand:SI 0 "d_operand")
1481 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1482 (match_operand:SI 2 "d_operand"))
1483 (match_operand:SI 3 "d_operand")))
1484 (clobber (match_operand:SI 4 "lo_operand"))
1485 (clobber (match_operand:SI 5 "d_operand"))]
1487 [(parallel [(set (match_dup 5)
1488 (mult:SI (match_dup 1) (match_dup 2)))
1489 (clobber (match_dup 4))])
1490 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1493 (define_insn "*macc"
1494 [(set (match_operand:SI 0 "register_operand" "=l,d")
1495 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1496 (match_operand:SI 2 "register_operand" "d,d"))
1497 (match_operand:SI 3 "register_operand" "0,l")))
1498 (clobber (match_scratch:SI 4 "=X,3"))]
1501 if (which_alternative == 1)
1502 return "macc\t%0,%1,%2";
1503 else if (TARGET_MIPS5500)
1504 return "madd\t%1,%2";
1506 /* The VR4130 assumes that there is a two-cycle latency between a macc
1507 that "writes" to $0 and an instruction that reads from it. We avoid
1508 this by assigning to $1 instead. */
1509 return "%[macc\t%@,%1,%2%]";
1511 [(set_attr "type" "imadd")
1512 (set_attr "mode" "SI")])
1514 (define_insn "*msac"
1515 [(set (match_operand:SI 0 "register_operand" "=l,d")
1516 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1517 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1518 (match_operand:SI 3 "register_operand" "d,d"))))
1519 (clobber (match_scratch:SI 4 "=X,1"))]
1522 if (which_alternative == 1)
1523 return "msac\t%0,%2,%3";
1524 else if (TARGET_MIPS5500)
1525 return "msub\t%2,%3";
1527 return "msac\t$0,%2,%3";
1529 [(set_attr "type" "imadd")
1530 (set_attr "mode" "SI")])
1532 ;; An msac-like instruction implemented using negation and a macc.
1533 (define_insn_and_split "*msac_using_macc"
1534 [(set (match_operand:SI 0 "register_operand" "=l,d")
1535 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1536 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1537 (match_operand:SI 3 "register_operand" "d,d"))))
1538 (clobber (match_scratch:SI 4 "=X,1"))
1539 (clobber (match_scratch:SI 5 "=d,d"))]
1540 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1542 "&& reload_completed"
1544 (neg:SI (match_dup 3)))
1547 (plus:SI (mult:SI (match_dup 2)
1550 (clobber (match_dup 4))])]
1552 [(set_attr "type" "imadd")
1553 (set_attr "length" "8")])
1555 ;; Patterns generated by the define_peephole2 below.
1557 (define_insn "*macc2"
1558 [(set (match_operand:SI 0 "register_operand" "=l")
1559 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1560 (match_operand:SI 2 "register_operand" "d"))
1562 (set (match_operand:SI 3 "register_operand" "=d")
1563 (plus:SI (mult:SI (match_dup 1)
1566 "ISA_HAS_MACC && reload_completed"
1568 [(set_attr "type" "imadd")
1569 (set_attr "mode" "SI")])
1571 (define_insn "*msac2"
1572 [(set (match_operand:SI 0 "register_operand" "=l")
1573 (minus:SI (match_dup 0)
1574 (mult:SI (match_operand:SI 1 "register_operand" "d")
1575 (match_operand:SI 2 "register_operand" "d"))))
1576 (set (match_operand:SI 3 "register_operand" "=d")
1577 (minus:SI (match_dup 0)
1578 (mult:SI (match_dup 1)
1580 "ISA_HAS_MSAC && reload_completed"
1582 [(set_attr "type" "imadd")
1583 (set_attr "mode" "SI")])
1585 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1589 ;; Operand 1: macc/msac
1590 ;; Operand 2: GPR (destination)
1593 [(set (match_operand:SI 0 "lo_operand")
1594 (match_operand:SI 1 "macc_msac_operand"))
1595 (clobber (scratch:SI))])
1596 (set (match_operand:SI 2 "d_operand")
1599 [(parallel [(set (match_dup 0)
1604 ;; When we have a three-address multiplication instruction, it should
1605 ;; be faster to do a separate multiply and add, rather than moving
1606 ;; something into LO in order to use a macc instruction.
1608 ;; This peephole needs a scratch register to cater for the case when one
1609 ;; of the multiplication operands is the same as the destination.
1611 ;; Operand 0: GPR (scratch)
1613 ;; Operand 2: GPR (addend)
1614 ;; Operand 3: GPR (destination)
1615 ;; Operand 4: macc/msac
1616 ;; Operand 5: new multiplication
1617 ;; Operand 6: new addition/subtraction
1619 [(match_scratch:SI 0 "d")
1620 (set (match_operand:SI 1 "lo_operand")
1621 (match_operand:SI 2 "d_operand"))
1624 [(set (match_operand:SI 3 "d_operand")
1625 (match_operand:SI 4 "macc_msac_operand"))
1626 (clobber (match_dup 1))])]
1627 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1628 [(parallel [(set (match_dup 0)
1630 (clobber (match_dup 1))])
1634 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1635 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1636 operands[2], operands[0]);
1639 ;; Same as above, except LO is the initial target of the macc.
1641 ;; Operand 0: GPR (scratch)
1643 ;; Operand 2: GPR (addend)
1644 ;; Operand 3: macc/msac
1645 ;; Operand 4: GPR (destination)
1646 ;; Operand 5: new multiplication
1647 ;; Operand 6: new addition/subtraction
1649 [(match_scratch:SI 0 "d")
1650 (set (match_operand:SI 1 "lo_operand")
1651 (match_operand:SI 2 "d_operand"))
1655 (match_operand:SI 3 "macc_msac_operand"))
1656 (clobber (scratch:SI))])
1658 (set (match_operand:SI 4 "d_operand")
1660 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1661 [(parallel [(set (match_dup 0)
1663 (clobber (match_dup 1))])
1667 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1668 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1669 operands[2], operands[0]);
1672 ;; See the comment above *mul_add_si for details.
1673 (define_insn "*mul_sub_si"
1674 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1675 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1676 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1677 (match_operand:SI 3 "register_operand" "d,d"))))
1678 (clobber (match_scratch:SI 4 "=X,l"))
1679 (clobber (match_scratch:SI 5 "=X,&d"))]
1680 "GENERATE_MADD_MSUB"
1684 [(set_attr "type" "imadd")
1685 (set_attr "mode" "SI")
1686 (set_attr "length" "4,8")])
1688 ;; Split *mul_sub_si if both the source and destination accumulator
1691 [(set (match_operand:SI 0 "d_operand")
1692 (minus:SI (match_operand:SI 1 "d_operand")
1693 (mult:SI (match_operand:SI 2 "d_operand")
1694 (match_operand:SI 3 "d_operand"))))
1695 (clobber (match_operand:SI 4 "lo_operand"))
1696 (clobber (match_operand:SI 5 "d_operand"))]
1698 [(parallel [(set (match_dup 5)
1699 (mult:SI (match_dup 2) (match_dup 3)))
1700 (clobber (match_dup 4))])
1701 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1704 (define_insn "*muls"
1705 [(set (match_operand:SI 0 "register_operand" "=l,d")
1706 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1707 (match_operand:SI 2 "register_operand" "d,d"))))
1708 (clobber (match_scratch:SI 3 "=X,l"))]
1713 [(set_attr "type" "imul,imul3")
1714 (set_attr "mode" "SI")])
1716 (define_expand "<u>mulsidi3"
1717 [(set (match_operand:DI 0 "register_operand")
1718 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1719 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1720 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
1722 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1723 emit_insn (fn (operands[0], operands[1], operands[2]));
1727 (define_insn "<u>mulsidi3_32bit"
1728 [(set (match_operand:DI 0 "register_operand" "=x")
1729 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1730 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1731 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1733 [(set_attr "type" "imul")
1734 (set_attr "mode" "SI")])
1736 (define_insn "<u>mulsidi3_32bit_r4000"
1737 [(set (match_operand:DI 0 "register_operand" "=d")
1738 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1739 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1740 (clobber (match_scratch:DI 3 "=x"))]
1741 "!TARGET_64BIT && TARGET_FIX_R4000"
1742 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1743 [(set_attr "type" "imul")
1744 (set_attr "mode" "SI")
1745 (set_attr "length" "12")])
1747 (define_insn "<u>mulsidi3_64bit"
1748 [(set (match_operand:DI 0 "register_operand" "=d")
1749 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1750 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1751 (clobber (match_scratch:TI 3 "=x"))
1752 (clobber (match_scratch:DI 4 "=d"))]
1753 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3"
1755 [(set_attr "type" "imul")
1756 (set_attr "mode" "SI")
1757 (set (attr "length")
1758 (if_then_else (ne (symbol_ref "ISA_HAS_EXT_INS") (const_int 0))
1763 [(set (match_operand:DI 0 "d_operand")
1764 (mult:DI (any_extend:DI (match_operand:SI 1 "d_operand"))
1765 (any_extend:DI (match_operand:SI 2 "d_operand"))))
1766 (clobber (match_operand:TI 3 "hilo_operand"))
1767 (clobber (match_operand:DI 4 "d_operand"))]
1768 "TARGET_64BIT && !TARGET_FIX_R4000 && ISA_HAS_EXT_INS && reload_completed"
1770 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1771 (any_extend:DI (match_dup 2)))]
1774 ;; OP0 <- LO, OP4 <- HI
1775 (set (match_dup 0) (match_dup 5))
1776 (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1778 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 32))
1780 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); })
1783 [(set (match_operand:DI 0 "d_operand")
1784 (mult:DI (any_extend:DI (match_operand:SI 1 "d_operand"))
1785 (any_extend:DI (match_operand:SI 2 "d_operand"))))
1786 (clobber (match_operand:TI 3 "hilo_operand"))
1787 (clobber (match_operand:DI 4 "d_operand"))]
1788 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_EXT_INS && reload_completed"
1790 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1791 (any_extend:DI (match_dup 2)))]
1794 ;; OP0 <- LO, OP4 <- HI
1795 (set (match_dup 0) (match_dup 5))
1796 (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1800 (ashift:DI (match_dup 0)
1803 (lshiftrt:DI (match_dup 0)
1806 ;; Shift OP4 into place.
1808 (ashift:DI (match_dup 4)
1811 ;; OR the two halves together
1813 (ior:DI (match_dup 0)
1815 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); })
1817 (define_insn "<u>mulsidi3_64bit_hilo"
1818 [(set (match_operand:TI 0 "register_operand" "=x")
1821 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1822 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1824 "TARGET_64BIT && !TARGET_FIX_R4000"
1826 [(set_attr "type" "imul")
1827 (set_attr "mode" "SI")])
1829 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
1830 (define_insn "mulsidi3_64bit_dmul"
1831 [(set (match_operand:DI 0 "register_operand" "=d")
1832 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1833 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1834 (clobber (match_scratch:DI 3 "=l"))]
1835 "TARGET_64BIT && ISA_HAS_DMUL3"
1837 [(set_attr "type" "imul3")
1838 (set_attr "mode" "DI")])
1840 ;; Widening multiply with negation.
1841 (define_insn "*muls<u>_di"
1842 [(set (match_operand:DI 0 "register_operand" "=x")
1845 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1846 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1847 "!TARGET_64BIT && ISA_HAS_MULS"
1849 [(set_attr "type" "imul")
1850 (set_attr "mode" "SI")])
1852 (define_insn "<u>msubsidi4"
1853 [(set (match_operand:DI 0 "register_operand" "=ka")
1855 (match_operand:DI 3 "register_operand" "0")
1857 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1858 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1859 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1862 return "msub<u>\t%q0,%1,%2";
1863 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1864 return "msub<u>\t%1,%2";
1866 return "msac<u>\t$0,%1,%2";
1868 [(set_attr "type" "imadd")
1869 (set_attr "mode" "SI")])
1871 ;; _highpart patterns
1873 (define_expand "<su>mulsi3_highpart"
1874 [(set (match_operand:SI 0 "register_operand")
1877 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1878 (any_extend:DI (match_operand:SI 2 "register_operand")))
1883 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1887 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1892 (define_insn_and_split "<su>mulsi3_highpart_internal"
1893 [(set (match_operand:SI 0 "register_operand" "=d")
1896 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1897 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1899 (clobber (match_scratch:SI 3 "=l"))]
1901 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1902 "&& reload_completed && !TARGET_FIX_R4000"
1909 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1910 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1911 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1915 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1916 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1917 emit_insn (gen_mfhisi_di (operands[0], hilo));
1921 [(set_attr "type" "imul")
1922 (set_attr "mode" "SI")
1923 (set_attr "length" "8")])
1925 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1926 [(set (match_operand:SI 0 "register_operand" "=d")
1930 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1931 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1933 (clobber (match_scratch:SI 3 "=l"))]
1935 "mulhi<u>\t%0,%1,%2"
1936 [(set_attr "type" "imul3")
1937 (set_attr "mode" "SI")])
1939 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1940 [(set (match_operand:SI 0 "register_operand" "=d")
1945 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1946 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1948 (clobber (match_scratch:SI 3 "=l"))]
1950 "mulshi<u>\t%0,%1,%2"
1951 [(set_attr "type" "imul3")
1952 (set_attr "mode" "SI")])
1954 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1955 ;; errata MD(0), which says that dmultu does not always produce the
1957 (define_insn_and_split "<su>muldi3_highpart"
1958 [(set (match_operand:DI 0 "register_operand" "=d")
1961 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1962 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1964 (clobber (match_scratch:DI 3 "=l"))]
1965 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1966 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1967 "&& reload_completed && !TARGET_FIX_R4000"
1972 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1973 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
1974 emit_insn (gen_mfhidi_ti (operands[0], hilo));
1977 [(set_attr "type" "imul")
1978 (set_attr "mode" "DI")
1979 (set_attr "length" "8")])
1981 (define_expand "<u>mulditi3"
1982 [(set (match_operand:TI 0 "register_operand")
1983 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
1984 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
1985 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1987 if (TARGET_FIX_R4000)
1988 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
1990 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
1995 (define_insn "<u>mulditi3_internal"
1996 [(set (match_operand:TI 0 "register_operand" "=x")
1997 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1998 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2000 && !TARGET_FIX_R4000
2001 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2003 [(set_attr "type" "imul")
2004 (set_attr "mode" "DI")])
2006 (define_insn "<u>mulditi3_r4000"
2007 [(set (match_operand:TI 0 "register_operand" "=d")
2008 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2009 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2010 (clobber (match_scratch:TI 3 "=x"))]
2013 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2014 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2015 [(set_attr "type" "imul")
2016 (set_attr "mode" "DI")
2017 (set_attr "length" "12")])
2019 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2020 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2022 (define_insn "madsi"
2023 [(set (match_operand:SI 0 "register_operand" "+l")
2024 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2025 (match_operand:SI 2 "register_operand" "d"))
2029 [(set_attr "type" "imadd")
2030 (set_attr "mode" "SI")])
2032 (define_insn "<u>maddsidi4"
2033 [(set (match_operand:DI 0 "register_operand" "=ka")
2035 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2036 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2037 (match_operand:DI 3 "register_operand" "0")))]
2038 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
2042 return "mad<u>\t%1,%2";
2043 else if (ISA_HAS_DSPR2)
2044 return "madd<u>\t%q0,%1,%2";
2045 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2046 return "madd<u>\t%1,%2";
2048 /* See comment in *macc. */
2049 return "%[macc<u>\t%@,%1,%2%]";
2051 [(set_attr "type" "imadd")
2052 (set_attr "mode" "SI")])
2054 ;; Floating point multiply accumulate instructions.
2056 (define_insn "*madd4<mode>"
2057 [(set (match_operand:ANYF 0 "register_operand" "=f")
2058 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2059 (match_operand:ANYF 2 "register_operand" "f"))
2060 (match_operand:ANYF 3 "register_operand" "f")))]
2061 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2062 "madd.<fmt>\t%0,%3,%1,%2"
2063 [(set_attr "type" "fmadd")
2064 (set_attr "mode" "<UNITMODE>")])
2066 (define_insn "*madd3<mode>"
2067 [(set (match_operand:ANYF 0 "register_operand" "=f")
2068 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2069 (match_operand:ANYF 2 "register_operand" "f"))
2070 (match_operand:ANYF 3 "register_operand" "0")))]
2071 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2072 "madd.<fmt>\t%0,%1,%2"
2073 [(set_attr "type" "fmadd")
2074 (set_attr "mode" "<UNITMODE>")])
2076 (define_insn "*msub4<mode>"
2077 [(set (match_operand:ANYF 0 "register_operand" "=f")
2078 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2079 (match_operand:ANYF 2 "register_operand" "f"))
2080 (match_operand:ANYF 3 "register_operand" "f")))]
2081 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2082 "msub.<fmt>\t%0,%3,%1,%2"
2083 [(set_attr "type" "fmadd")
2084 (set_attr "mode" "<UNITMODE>")])
2086 (define_insn "*msub3<mode>"
2087 [(set (match_operand:ANYF 0 "register_operand" "=f")
2088 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2089 (match_operand:ANYF 2 "register_operand" "f"))
2090 (match_operand:ANYF 3 "register_operand" "0")))]
2091 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2092 "msub.<fmt>\t%0,%1,%2"
2093 [(set_attr "type" "fmadd")
2094 (set_attr "mode" "<UNITMODE>")])
2096 (define_insn "*nmadd4<mode>"
2097 [(set (match_operand:ANYF 0 "register_operand" "=f")
2098 (neg:ANYF (plus:ANYF
2099 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2100 (match_operand:ANYF 2 "register_operand" "f"))
2101 (match_operand:ANYF 3 "register_operand" "f"))))]
2102 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2103 && TARGET_FUSED_MADD
2104 && HONOR_SIGNED_ZEROS (<MODE>mode)
2105 && !HONOR_NANS (<MODE>mode)"
2106 "nmadd.<fmt>\t%0,%3,%1,%2"
2107 [(set_attr "type" "fmadd")
2108 (set_attr "mode" "<UNITMODE>")])
2110 (define_insn "*nmadd3<mode>"
2111 [(set (match_operand:ANYF 0 "register_operand" "=f")
2112 (neg:ANYF (plus:ANYF
2113 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2114 (match_operand:ANYF 2 "register_operand" "f"))
2115 (match_operand:ANYF 3 "register_operand" "0"))))]
2116 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2117 && TARGET_FUSED_MADD
2118 && HONOR_SIGNED_ZEROS (<MODE>mode)
2119 && !HONOR_NANS (<MODE>mode)"
2120 "nmadd.<fmt>\t%0,%1,%2"
2121 [(set_attr "type" "fmadd")
2122 (set_attr "mode" "<UNITMODE>")])
2124 (define_insn "*nmadd4<mode>_fastmath"
2125 [(set (match_operand:ANYF 0 "register_operand" "=f")
2127 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2128 (match_operand:ANYF 2 "register_operand" "f"))
2129 (match_operand:ANYF 3 "register_operand" "f")))]
2130 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2131 && TARGET_FUSED_MADD
2132 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2133 && !HONOR_NANS (<MODE>mode)"
2134 "nmadd.<fmt>\t%0,%3,%1,%2"
2135 [(set_attr "type" "fmadd")
2136 (set_attr "mode" "<UNITMODE>")])
2138 (define_insn "*nmadd3<mode>_fastmath"
2139 [(set (match_operand:ANYF 0 "register_operand" "=f")
2141 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2142 (match_operand:ANYF 2 "register_operand" "f"))
2143 (match_operand:ANYF 3 "register_operand" "0")))]
2144 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2145 && TARGET_FUSED_MADD
2146 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2147 && !HONOR_NANS (<MODE>mode)"
2148 "nmadd.<fmt>\t%0,%1,%2"
2149 [(set_attr "type" "fmadd")
2150 (set_attr "mode" "<UNITMODE>")])
2152 (define_insn "*nmsub4<mode>"
2153 [(set (match_operand:ANYF 0 "register_operand" "=f")
2154 (neg:ANYF (minus:ANYF
2155 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2156 (match_operand:ANYF 3 "register_operand" "f"))
2157 (match_operand:ANYF 1 "register_operand" "f"))))]
2158 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2159 && TARGET_FUSED_MADD
2160 && HONOR_SIGNED_ZEROS (<MODE>mode)
2161 && !HONOR_NANS (<MODE>mode)"
2162 "nmsub.<fmt>\t%0,%1,%2,%3"
2163 [(set_attr "type" "fmadd")
2164 (set_attr "mode" "<UNITMODE>")])
2166 (define_insn "*nmsub3<mode>"
2167 [(set (match_operand:ANYF 0 "register_operand" "=f")
2168 (neg:ANYF (minus:ANYF
2169 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2170 (match_operand:ANYF 3 "register_operand" "f"))
2171 (match_operand:ANYF 1 "register_operand" "0"))))]
2172 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2173 && TARGET_FUSED_MADD
2174 && HONOR_SIGNED_ZEROS (<MODE>mode)
2175 && !HONOR_NANS (<MODE>mode)"
2176 "nmsub.<fmt>\t%0,%1,%2"
2177 [(set_attr "type" "fmadd")
2178 (set_attr "mode" "<UNITMODE>")])
2180 (define_insn "*nmsub4<mode>_fastmath"
2181 [(set (match_operand:ANYF 0 "register_operand" "=f")
2183 (match_operand:ANYF 1 "register_operand" "f")
2184 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2185 (match_operand:ANYF 3 "register_operand" "f"))))]
2186 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2187 && TARGET_FUSED_MADD
2188 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2189 && !HONOR_NANS (<MODE>mode)"
2190 "nmsub.<fmt>\t%0,%1,%2,%3"
2191 [(set_attr "type" "fmadd")
2192 (set_attr "mode" "<UNITMODE>")])
2194 (define_insn "*nmsub3<mode>_fastmath"
2195 [(set (match_operand:ANYF 0 "register_operand" "=f")
2197 (match_operand:ANYF 1 "register_operand" "f")
2198 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2199 (match_operand:ANYF 3 "register_operand" "0"))))]
2200 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2201 && TARGET_FUSED_MADD
2202 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2203 && !HONOR_NANS (<MODE>mode)"
2204 "nmsub.<fmt>\t%0,%1,%2"
2205 [(set_attr "type" "fmadd")
2206 (set_attr "mode" "<UNITMODE>")])
2209 ;; ....................
2211 ;; DIVISION and REMAINDER
2213 ;; ....................
2216 (define_expand "div<mode>3"
2217 [(set (match_operand:ANYF 0 "register_operand")
2218 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2219 (match_operand:ANYF 2 "register_operand")))]
2220 "<divide_condition>"
2222 if (const_1_operand (operands[1], <MODE>mode))
2223 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2224 operands[1] = force_reg (<MODE>mode, operands[1]);
2227 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2229 ;; If an mfc1 or dmfc1 happens to access the floating point register
2230 ;; file at the same time a long latency operation (div, sqrt, recip,
2231 ;; sqrt) iterates an intermediate result back through the floating
2232 ;; point register file bypass, then instead returning the correct
2233 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2234 ;; result of the long latency operation.
2236 ;; The workaround is to insert an unconditional 'mov' from/to the
2237 ;; long latency op destination register.
2239 (define_insn "*div<mode>3"
2240 [(set (match_operand:ANYF 0 "register_operand" "=f")
2241 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2242 (match_operand:ANYF 2 "register_operand" "f")))]
2243 "<divide_condition>"
2246 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2248 return "div.<fmt>\t%0,%1,%2";
2250 [(set_attr "type" "fdiv")
2251 (set_attr "mode" "<UNITMODE>")
2252 (set (attr "length")
2253 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2257 (define_insn "*recip<mode>3"
2258 [(set (match_operand:ANYF 0 "register_operand" "=f")
2259 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2260 (match_operand:ANYF 2 "register_operand" "f")))]
2261 "<recip_condition> && flag_unsafe_math_optimizations"
2264 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2266 return "recip.<fmt>\t%0,%2";
2268 [(set_attr "type" "frdiv")
2269 (set_attr "mode" "<UNITMODE>")
2270 (set (attr "length")
2271 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2275 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2276 ;; with negative operands. We use special libgcc functions instead.
2277 (define_insn_and_split "divmod<mode>4"
2278 [(set (match_operand:GPR 0 "register_operand" "=l")
2279 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2280 (match_operand:GPR 2 "register_operand" "d")))
2281 (set (match_operand:GPR 3 "register_operand" "=d")
2282 (mod:GPR (match_dup 1)
2284 "!TARGET_FIX_VR4120"
2286 "&& reload_completed"
2293 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2294 emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2295 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2299 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2300 emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2301 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2305 [(set_attr "type" "idiv")
2306 (set_attr "mode" "<MODE>")
2307 (set_attr "length" "8")])
2309 (define_insn_and_split "udivmod<mode>4"
2310 [(set (match_operand:GPR 0 "register_operand" "=l")
2311 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2312 (match_operand:GPR 2 "register_operand" "d")))
2313 (set (match_operand:GPR 3 "register_operand" "=d")
2314 (umod:GPR (match_dup 1)
2325 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2326 emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2327 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2331 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2332 emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2333 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2337 [(set_attr "type" "idiv")
2338 (set_attr "mode" "<MODE>")
2339 (set_attr "length" "8")])
2341 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2342 [(set (match_operand:HILO 0 "register_operand" "=x")
2344 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2345 (match_operand:GPR 2 "register_operand" "d"))]
2348 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2349 [(set_attr "type" "idiv")
2350 (set_attr "mode" "<GPR:MODE>")])
2353 ;; ....................
2357 ;; ....................
2359 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2360 ;; "*div[sd]f3" comment for details).
2362 (define_insn "sqrt<mode>2"
2363 [(set (match_operand:ANYF 0 "register_operand" "=f")
2364 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2368 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2370 return "sqrt.<fmt>\t%0,%1";
2372 [(set_attr "type" "fsqrt")
2373 (set_attr "mode" "<UNITMODE>")
2374 (set (attr "length")
2375 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2379 (define_insn "*rsqrt<mode>a"
2380 [(set (match_operand:ANYF 0 "register_operand" "=f")
2381 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2382 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2383 "<recip_condition> && flag_unsafe_math_optimizations"
2386 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2388 return "rsqrt.<fmt>\t%0,%2";
2390 [(set_attr "type" "frsqrt")
2391 (set_attr "mode" "<UNITMODE>")
2392 (set (attr "length")
2393 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2397 (define_insn "*rsqrt<mode>b"
2398 [(set (match_operand:ANYF 0 "register_operand" "=f")
2399 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2400 (match_operand:ANYF 2 "register_operand" "f"))))]
2401 "<recip_condition> && flag_unsafe_math_optimizations"
2404 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2406 return "rsqrt.<fmt>\t%0,%2";
2408 [(set_attr "type" "frsqrt")
2409 (set_attr "mode" "<UNITMODE>")
2410 (set (attr "length")
2411 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2416 ;; ....................
2420 ;; ....................
2422 ;; Do not use the integer abs macro instruction, since that signals an
2423 ;; exception on -2147483648 (sigh).
2425 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2426 ;; invalid; it does not clear their sign bits. We therefore can't use
2427 ;; abs.fmt if the signs of NaNs matter.
2429 (define_insn "abs<mode>2"
2430 [(set (match_operand:ANYF 0 "register_operand" "=f")
2431 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2432 "!HONOR_NANS (<MODE>mode)"
2434 [(set_attr "type" "fabs")
2435 (set_attr "mode" "<UNITMODE>")])
2438 ;; ...................
2440 ;; Count leading zeroes.
2442 ;; ...................
2445 (define_insn "clz<mode>2"
2446 [(set (match_operand:GPR 0 "register_operand" "=d")
2447 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2450 [(set_attr "type" "clz")
2451 (set_attr "mode" "<MODE>")])
2454 ;; ...................
2456 ;; Count number of set bits.
2458 ;; ...................
2461 (define_insn "popcount<mode>2"
2462 [(set (match_operand:GPR 0 "register_operand" "=d")
2463 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2466 [(set_attr "type" "pop")
2467 (set_attr "mode" "<MODE>")])
2470 ;; ....................
2472 ;; NEGATION and ONE'S COMPLEMENT
2474 ;; ....................
2476 (define_insn "negsi2"
2477 [(set (match_operand:SI 0 "register_operand" "=d")
2478 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2482 return "neg\t%0,%1";
2484 return "subu\t%0,%.,%1";
2486 [(set_attr "type" "arith")
2487 (set_attr "mode" "SI")])
2489 (define_insn "negdi2"
2490 [(set (match_operand:DI 0 "register_operand" "=d")
2491 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2492 "TARGET_64BIT && !TARGET_MIPS16"
2494 [(set_attr "type" "arith")
2495 (set_attr "mode" "DI")])
2497 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2498 ;; invalid; it does not flip their sign bit. We therefore can't use
2499 ;; neg.fmt if the signs of NaNs matter.
2501 (define_insn "neg<mode>2"
2502 [(set (match_operand:ANYF 0 "register_operand" "=f")
2503 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2504 "!HONOR_NANS (<MODE>mode)"
2506 [(set_attr "type" "fneg")
2507 (set_attr "mode" "<UNITMODE>")])
2509 (define_insn "one_cmpl<mode>2"
2510 [(set (match_operand:GPR 0 "register_operand" "=d")
2511 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2515 return "not\t%0,%1";
2517 return "nor\t%0,%.,%1";
2519 [(set_attr "type" "logical")
2520 (set_attr "mode" "<MODE>")])
2523 ;; ....................
2527 ;; ....................
2530 ;; Many of these instructions use trivial define_expands, because we
2531 ;; want to use a different set of constraints when TARGET_MIPS16.
2533 (define_expand "and<mode>3"
2534 [(set (match_operand:GPR 0 "register_operand")
2535 (and:GPR (match_operand:GPR 1 "register_operand")
2536 (match_operand:GPR 2 "and_reg_operand")))])
2538 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
2539 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
2540 ;; Note that this variant does not trigger for SI mode because we require
2541 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
2542 ;; sign-extended SImode value.
2544 ;; These are possible combinations for operand 1 and 2. The table
2545 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
2546 ;; 16=MIPS16, x=match, S=split):
2548 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
2554 ;; 0xffff_ffff x S x S x
2559 (define_insn "*and<mode>3"
2560 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d")
2561 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,d,d,d,d")
2562 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,K,Yx,Yw,d")))]
2563 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2567 switch (which_alternative)
2570 operands[1] = gen_lowpart (QImode, operands[1]);
2571 return "lbu\t%0,%1";
2573 operands[1] = gen_lowpart (HImode, operands[1]);
2574 return "lhu\t%0,%1";
2576 operands[1] = gen_lowpart (SImode, operands[1]);
2577 return "lwu\t%0,%1";
2579 return "andi\t%0,%1,%x2";
2581 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
2582 operands[2] = GEN_INT (len);
2583 return "<d>ext\t%0,%1,0,%2";
2587 return "and\t%0,%1,%2";
2592 [(set_attr "move_type" "load,load,load,andi,ext_ins,shift_shift,logical")
2593 (set_attr "mode" "<MODE>")])
2595 (define_insn "*and<mode>3_mips16"
2596 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
2597 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%o,o,W,d,0")
2598 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
2599 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2601 switch (which_alternative)
2604 operands[1] = gen_lowpart (QImode, operands[1]);
2605 return "lbu\t%0,%1";
2607 operands[1] = gen_lowpart (HImode, operands[1]);
2608 return "lhu\t%0,%1";
2610 operands[1] = gen_lowpart (SImode, operands[1]);
2611 return "lwu\t%0,%1";
2615 return "and\t%0,%2";
2620 [(set_attr "move_type" "load,load,load,shift_shift,logical")
2621 (set_attr "mode" "<MODE>")])
2623 (define_expand "ior<mode>3"
2624 [(set (match_operand:GPR 0 "register_operand")
2625 (ior:GPR (match_operand:GPR 1 "register_operand")
2626 (match_operand:GPR 2 "uns_arith_operand")))]
2630 operands[2] = force_reg (<MODE>mode, operands[2]);
2633 (define_insn "*ior<mode>3"
2634 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2635 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2636 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2641 [(set_attr "type" "logical")
2642 (set_attr "mode" "<MODE>")])
2644 (define_insn "*ior<mode>3_mips16"
2645 [(set (match_operand:GPR 0 "register_operand" "=d")
2646 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2647 (match_operand:GPR 2 "register_operand" "d")))]
2650 [(set_attr "type" "logical")
2651 (set_attr "mode" "<MODE>")])
2653 (define_expand "xor<mode>3"
2654 [(set (match_operand:GPR 0 "register_operand")
2655 (xor:GPR (match_operand:GPR 1 "register_operand")
2656 (match_operand:GPR 2 "uns_arith_operand")))]
2661 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2662 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2663 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2668 [(set_attr "type" "logical")
2669 (set_attr "mode" "<MODE>")])
2672 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2673 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2674 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2680 [(set_attr "type" "logical,arith,arith")
2681 (set_attr "mode" "<MODE>")
2682 (set_attr_alternative "length"
2684 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2689 (define_insn "*nor<mode>3"
2690 [(set (match_operand:GPR 0 "register_operand" "=d")
2691 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2692 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2695 [(set_attr "type" "logical")
2696 (set_attr "mode" "<MODE>")])
2699 ;; ....................
2703 ;; ....................
2707 (define_insn "truncdfsf2"
2708 [(set (match_operand:SF 0 "register_operand" "=f")
2709 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2710 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2712 [(set_attr "type" "fcvt")
2713 (set_attr "cnv_mode" "D2S")
2714 (set_attr "mode" "SF")])
2716 ;; Integer truncation patterns. Truncating SImode values to smaller
2717 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2718 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2719 ;; need to make sure that the lower 32 bits are properly sign-extended
2720 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2721 ;; smaller than SImode is equivalent to two separate truncations:
2724 ;; DI ---> HI == DI ---> SI ---> HI
2725 ;; DI ---> QI == DI ---> SI ---> QI
2727 ;; Step A needs a real instruction but step B does not.
2729 (define_insn "truncdi<mode>2"
2730 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
2731 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
2736 [(set_attr "move_type" "sll0,store")
2737 (set_attr "mode" "SI")])
2739 ;; Combiner patterns to optimize shift/truncate combinations.
2741 (define_insn "*ashr_trunc<mode>"
2742 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2744 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2745 (match_operand:DI 2 "const_arith_operand" ""))))]
2746 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
2748 [(set_attr "type" "shift")
2749 (set_attr "mode" "<MODE>")])
2751 (define_insn "*lshr32_trunc<mode>"
2752 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2754 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2756 "TARGET_64BIT && !TARGET_MIPS16"
2758 [(set_attr "type" "shift")
2759 (set_attr "mode" "<MODE>")])
2761 ;; Logical shift by more than 32 results in proper SI values so truncation is
2762 ;; removed by the middle end. Note that a logical shift by 32 is handled by
2763 ;; the previous pattern.
2764 (define_insn "*<optab>_trunc<mode>_exts"
2765 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2767 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
2768 (match_operand:DI 2 "const_arith_operand" ""))))]
2769 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
2771 [(set_attr "type" "arith")
2772 (set_attr "mode" "<MODE>")])
2775 ;; ....................
2779 ;; ....................
2783 (define_expand "zero_extendsidi2"
2784 [(set (match_operand:DI 0 "register_operand")
2785 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
2788 (define_insn_and_split "*zero_extendsidi2"
2789 [(set (match_operand:DI 0 "register_operand" "=d,d")
2790 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2791 "TARGET_64BIT && !ISA_HAS_EXT_INS"
2795 "&& reload_completed && REG_P (operands[1])"
2797 (ashift:DI (match_dup 1) (const_int 32)))
2799 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2800 { operands[1] = gen_lowpart (DImode, operands[1]); }
2801 [(set_attr "move_type" "shift_shift,load")
2802 (set_attr "mode" "DI")])
2804 (define_insn "*zero_extendsidi2_dext"
2805 [(set (match_operand:DI 0 "register_operand" "=d,d")
2806 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2807 "TARGET_64BIT && ISA_HAS_EXT_INS"
2811 [(set_attr "move_type" "arith,load")
2812 (set_attr "mode" "DI")])
2814 ;; See the comment before the *and<mode>3 pattern why this is generated by
2818 [(set (match_operand:DI 0 "register_operand")
2819 (and:DI (match_operand:DI 1 "register_operand")
2820 (const_int 4294967295)))]
2821 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
2823 (ashift:DI (match_dup 1) (const_int 32)))
2825 (lshiftrt:DI (match_dup 0) (const_int 32)))])
2827 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2828 [(set (match_operand:GPR 0 "register_operand")
2829 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2832 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2833 && !memory_operand (operands[1], <SHORT:MODE>mode))
2835 emit_insn (gen_and<GPR:mode>3 (operands[0],
2836 gen_lowpart (<GPR:MODE>mode, operands[1]),
2837 force_reg (<GPR:MODE>mode,
2838 GEN_INT (<SHORT:mask>))));
2843 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2844 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2846 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2849 andi\t%0,%1,<SHORT:mask>
2850 l<SHORT:size>u\t%0,%1"
2851 [(set_attr "move_type" "andi,load")
2852 (set_attr "mode" "<GPR:MODE>")])
2854 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2855 [(set (match_operand:GPR 0 "register_operand" "=d")
2856 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2858 "ze<SHORT:size>\t%0"
2859 ;; This instruction is effectively a special encoding of ANDI.
2860 [(set_attr "move_type" "andi")
2861 (set_attr "mode" "<GPR:MODE>")])
2863 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2864 [(set (match_operand:GPR 0 "register_operand" "=d")
2865 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2867 "l<SHORT:size>u\t%0,%1"
2868 [(set_attr "move_type" "load")
2869 (set_attr "mode" "<GPR:MODE>")])
2871 (define_expand "zero_extendqihi2"
2872 [(set (match_operand:HI 0 "register_operand")
2873 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2876 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2878 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2884 (define_insn "*zero_extendqihi2"
2885 [(set (match_operand:HI 0 "register_operand" "=d,d")
2886 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2891 [(set_attr "move_type" "andi,load")
2892 (set_attr "mode" "HI")])
2894 (define_insn "*zero_extendqihi2_mips16"
2895 [(set (match_operand:HI 0 "register_operand" "=d")
2896 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2899 [(set_attr "move_type" "load")
2900 (set_attr "mode" "HI")])
2902 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2904 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
2905 [(set (match_operand:GPR 0 "register_operand" "=d")
2907 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2908 "TARGET_64BIT && !TARGET_MIPS16"
2910 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
2911 return "andi\t%0,%1,%x2";
2913 [(set_attr "type" "logical")
2914 (set_attr "mode" "<GPR:MODE>")])
2916 (define_insn "*zero_extendhi_truncqi"
2917 [(set (match_operand:HI 0 "register_operand" "=d")
2919 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2920 "TARGET_64BIT && !TARGET_MIPS16"
2922 [(set_attr "type" "logical")
2923 (set_attr "mode" "HI")])
2926 ;; ....................
2930 ;; ....................
2933 ;; Those for integer source operand are ordered widest source type first.
2935 ;; When TARGET_64BIT, all SImode integer registers should already be in
2936 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2937 ;; therefore get rid of register->register instructions if we constrain
2938 ;; the source to be in the same register as the destination.
2940 ;; The register alternative has type "arith" so that the pre-reload
2941 ;; scheduler will treat it as a move. This reflects what happens if
2942 ;; the register alternative needs a reload.
2943 (define_insn_and_split "extendsidi2"
2944 [(set (match_operand:DI 0 "register_operand" "=d,d")
2945 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2950 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2953 emit_note (NOTE_INSN_DELETED);
2956 [(set_attr "move_type" "move,load")
2957 (set_attr "mode" "DI")])
2959 (define_expand "extend<SHORT:mode><GPR:mode>2"
2960 [(set (match_operand:GPR 0 "register_operand")
2961 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2964 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2965 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2966 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2970 l<SHORT:size>\t%0,%1"
2971 [(set_attr "move_type" "signext,load")
2972 (set_attr "mode" "<GPR:MODE>")])
2974 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2975 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2977 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2978 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2981 l<SHORT:size>\t%0,%1"
2982 "&& reload_completed && REG_P (operands[1])"
2983 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2984 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2986 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2987 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2988 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2990 [(set_attr "move_type" "shift_shift,load")
2991 (set_attr "mode" "<GPR:MODE>")])
2993 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2994 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2996 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2999 se<SHORT:size>\t%0,%1
3000 l<SHORT:size>\t%0,%1"
3001 [(set_attr "move_type" "signext,load")
3002 (set_attr "mode" "<GPR:MODE>")])
3004 (define_expand "extendqihi2"
3005 [(set (match_operand:HI 0 "register_operand")
3006 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3009 (define_insn "*extendqihi2_mips16e"
3010 [(set (match_operand:HI 0 "register_operand" "=d,d")
3011 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3016 [(set_attr "move_type" "signext,load")
3017 (set_attr "mode" "SI")])
3019 (define_insn_and_split "*extendqihi2"
3020 [(set (match_operand:HI 0 "register_operand" "=d,d")
3022 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3023 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3027 "&& reload_completed && REG_P (operands[1])"
3028 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3029 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3031 operands[0] = gen_lowpart (SImode, operands[0]);
3032 operands[1] = gen_lowpart (SImode, operands[1]);
3033 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3034 - GET_MODE_BITSIZE (QImode));
3036 [(set_attr "move_type" "shift_shift,load")
3037 (set_attr "mode" "SI")])
3039 (define_insn "*extendqihi2_seb"
3040 [(set (match_operand:HI 0 "register_operand" "=d,d")
3042 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3047 [(set_attr "move_type" "signext,load")
3048 (set_attr "mode" "SI")])
3050 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3051 ;; use the shift/truncate patterns.
3053 (define_insn_and_split "*extenddi_truncate<mode>"
3054 [(set (match_operand:DI 0 "register_operand" "=d")
3056 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3057 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3059 "&& reload_completed"
3061 (ashift:DI (match_dup 1)
3064 (ashiftrt:DI (match_dup 2)
3067 operands[2] = gen_lowpart (DImode, operands[0]);
3068 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3070 [(set_attr "move_type" "shift_shift")
3071 (set_attr "mode" "DI")])
3073 (define_insn_and_split "*extendsi_truncate<mode>"
3074 [(set (match_operand:SI 0 "register_operand" "=d")
3076 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3077 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3079 "&& reload_completed"
3081 (ashift:DI (match_dup 1)
3084 (truncate:SI (ashiftrt:DI (match_dup 2)
3087 operands[2] = gen_lowpart (DImode, operands[0]);
3088 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3090 [(set_attr "move_type" "shift_shift")
3091 (set_attr "mode" "SI")])
3093 (define_insn_and_split "*extendhi_truncateqi"
3094 [(set (match_operand:HI 0 "register_operand" "=d")
3096 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3097 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3099 "&& reload_completed"
3101 (ashift:DI (match_dup 1)
3104 (truncate:HI (ashiftrt:DI (match_dup 2)
3107 operands[2] = gen_lowpart (DImode, operands[0]);
3109 [(set_attr "move_type" "shift_shift")
3110 (set_attr "mode" "SI")])
3112 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3113 [(set (match_operand:GPR 0 "register_operand" "=d")
3115 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3116 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3118 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3119 return "exts\t%0,%1,0,%m2";
3121 [(set_attr "type" "arith")
3122 (set_attr "mode" "<GPR:MODE>")])
3124 (define_insn "*extendhi_truncateqi_exts"
3125 [(set (match_operand:HI 0 "register_operand" "=d")
3127 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3128 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3130 [(set_attr "type" "arith")
3131 (set_attr "mode" "SI")])
3133 (define_insn "extendsfdf2"
3134 [(set (match_operand:DF 0 "register_operand" "=f")
3135 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3136 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3138 [(set_attr "type" "fcvt")
3139 (set_attr "cnv_mode" "S2D")
3140 (set_attr "mode" "DF")])
3143 ;; ....................
3147 ;; ....................
3149 (define_expand "fix_truncdfsi2"
3150 [(set (match_operand:SI 0 "register_operand")
3151 (fix:SI (match_operand:DF 1 "register_operand")))]
3152 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3154 if (!ISA_HAS_TRUNC_W)
3156 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3161 (define_insn "fix_truncdfsi2_insn"
3162 [(set (match_operand:SI 0 "register_operand" "=f")
3163 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3164 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3166 [(set_attr "type" "fcvt")
3167 (set_attr "mode" "DF")
3168 (set_attr "cnv_mode" "D2I")])
3170 (define_insn "fix_truncdfsi2_macro"
3171 [(set (match_operand:SI 0 "register_operand" "=f")
3172 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3173 (clobber (match_scratch:DF 2 "=d"))]
3174 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3176 if (mips_nomacro.nesting_level > 0)
3177 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3179 return "trunc.w.d %0,%1,%2";
3181 [(set_attr "type" "fcvt")
3182 (set_attr "mode" "DF")
3183 (set_attr "cnv_mode" "D2I")
3184 (set_attr "length" "36")])
3186 (define_expand "fix_truncsfsi2"
3187 [(set (match_operand:SI 0 "register_operand")
3188 (fix:SI (match_operand:SF 1 "register_operand")))]
3191 if (!ISA_HAS_TRUNC_W)
3193 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3198 (define_insn "fix_truncsfsi2_insn"
3199 [(set (match_operand:SI 0 "register_operand" "=f")
3200 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3201 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3203 [(set_attr "type" "fcvt")
3204 (set_attr "mode" "SF")
3205 (set_attr "cnv_mode" "S2I")])
3207 (define_insn "fix_truncsfsi2_macro"
3208 [(set (match_operand:SI 0 "register_operand" "=f")
3209 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3210 (clobber (match_scratch:SF 2 "=d"))]
3211 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3213 if (mips_nomacro.nesting_level > 0)
3214 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3216 return "trunc.w.s %0,%1,%2";
3218 [(set_attr "type" "fcvt")
3219 (set_attr "mode" "SF")
3220 (set_attr "cnv_mode" "S2I")
3221 (set_attr "length" "36")])
3224 (define_insn "fix_truncdfdi2"
3225 [(set (match_operand:DI 0 "register_operand" "=f")
3226 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3227 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3229 [(set_attr "type" "fcvt")
3230 (set_attr "mode" "DF")
3231 (set_attr "cnv_mode" "D2I")])
3234 (define_insn "fix_truncsfdi2"
3235 [(set (match_operand:DI 0 "register_operand" "=f")
3236 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3237 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3239 [(set_attr "type" "fcvt")
3240 (set_attr "mode" "SF")
3241 (set_attr "cnv_mode" "S2I")])
3244 (define_insn "floatsidf2"
3245 [(set (match_operand:DF 0 "register_operand" "=f")
3246 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3247 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3249 [(set_attr "type" "fcvt")
3250 (set_attr "mode" "DF")
3251 (set_attr "cnv_mode" "I2D")])
3254 (define_insn "floatdidf2"
3255 [(set (match_operand:DF 0 "register_operand" "=f")
3256 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3257 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3259 [(set_attr "type" "fcvt")
3260 (set_attr "mode" "DF")
3261 (set_attr "cnv_mode" "I2D")])
3264 (define_insn "floatsisf2"
3265 [(set (match_operand:SF 0 "register_operand" "=f")
3266 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3269 [(set_attr "type" "fcvt")
3270 (set_attr "mode" "SF")
3271 (set_attr "cnv_mode" "I2S")])
3274 (define_insn "floatdisf2"
3275 [(set (match_operand:SF 0 "register_operand" "=f")
3276 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3277 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3279 [(set_attr "type" "fcvt")
3280 (set_attr "mode" "SF")
3281 (set_attr "cnv_mode" "I2S")])
3284 (define_expand "fixuns_truncdfsi2"
3285 [(set (match_operand:SI 0 "register_operand")
3286 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3287 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3289 rtx reg1 = gen_reg_rtx (DFmode);
3290 rtx reg2 = gen_reg_rtx (DFmode);
3291 rtx reg3 = gen_reg_rtx (SImode);
3292 rtx label1 = gen_label_rtx ();
3293 rtx label2 = gen_label_rtx ();
3295 REAL_VALUE_TYPE offset;
3297 real_2expN (&offset, 31, DFmode);
3299 if (reg1) /* Turn off complaints about unreached code. */
3301 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3302 do_pending_stack_adjust ();
3304 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3305 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3307 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3308 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3309 gen_rtx_LABEL_REF (VOIDmode, label2)));
3312 emit_label (label1);
3313 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3314 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3315 (BITMASK_HIGH, SImode)));
3317 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3318 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3320 emit_label (label2);
3322 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3323 fields, and can't be used for REG_NOTES anyway). */
3324 emit_use (stack_pointer_rtx);
3330 (define_expand "fixuns_truncdfdi2"
3331 [(set (match_operand:DI 0 "register_operand")
3332 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3333 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3335 rtx reg1 = gen_reg_rtx (DFmode);
3336 rtx reg2 = gen_reg_rtx (DFmode);
3337 rtx reg3 = gen_reg_rtx (DImode);
3338 rtx label1 = gen_label_rtx ();
3339 rtx label2 = gen_label_rtx ();
3341 REAL_VALUE_TYPE offset;
3343 real_2expN (&offset, 63, DFmode);
3345 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3346 do_pending_stack_adjust ();
3348 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3349 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3351 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3352 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3353 gen_rtx_LABEL_REF (VOIDmode, label2)));
3356 emit_label (label1);
3357 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3358 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3359 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3361 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3362 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3364 emit_label (label2);
3366 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3367 fields, and can't be used for REG_NOTES anyway). */
3368 emit_use (stack_pointer_rtx);
3373 (define_expand "fixuns_truncsfsi2"
3374 [(set (match_operand:SI 0 "register_operand")
3375 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3378 rtx reg1 = gen_reg_rtx (SFmode);
3379 rtx reg2 = gen_reg_rtx (SFmode);
3380 rtx reg3 = gen_reg_rtx (SImode);
3381 rtx label1 = gen_label_rtx ();
3382 rtx label2 = gen_label_rtx ();
3384 REAL_VALUE_TYPE offset;
3386 real_2expN (&offset, 31, SFmode);
3388 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3389 do_pending_stack_adjust ();
3391 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3392 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3394 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3395 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3396 gen_rtx_LABEL_REF (VOIDmode, label2)));
3399 emit_label (label1);
3400 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3401 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3402 (BITMASK_HIGH, SImode)));
3404 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3405 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3407 emit_label (label2);
3409 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3410 fields, and can't be used for REG_NOTES anyway). */
3411 emit_use (stack_pointer_rtx);
3416 (define_expand "fixuns_truncsfdi2"
3417 [(set (match_operand:DI 0 "register_operand")
3418 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3419 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3421 rtx reg1 = gen_reg_rtx (SFmode);
3422 rtx reg2 = gen_reg_rtx (SFmode);
3423 rtx reg3 = gen_reg_rtx (DImode);
3424 rtx label1 = gen_label_rtx ();
3425 rtx label2 = gen_label_rtx ();
3427 REAL_VALUE_TYPE offset;
3429 real_2expN (&offset, 63, SFmode);
3431 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3432 do_pending_stack_adjust ();
3434 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3435 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3437 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3438 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3439 gen_rtx_LABEL_REF (VOIDmode, label2)));
3442 emit_label (label1);
3443 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3444 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3445 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3447 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3448 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3450 emit_label (label2);
3452 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3453 fields, and can't be used for REG_NOTES anyway). */
3454 emit_use (stack_pointer_rtx);
3459 ;; ....................
3463 ;; ....................
3465 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3467 (define_expand "extv"
3468 [(set (match_operand 0 "register_operand")
3469 (sign_extract (match_operand 1 "nonimmediate_operand")
3470 (match_operand 2 "const_int_operand")
3471 (match_operand 3 "const_int_operand")))]
3474 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3475 INTVAL (operands[2]),
3476 INTVAL (operands[3])))
3478 else if (register_operand (operands[1], GET_MODE (operands[0]))
3479 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3481 if (GET_MODE (operands[0]) == DImode)
3482 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3485 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3493 (define_insn "extv<mode>"
3494 [(set (match_operand:GPR 0 "register_operand" "=d")
3495 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3496 (match_operand 2 "const_int_operand" "")
3497 (match_operand 3 "const_int_operand" "")))]
3498 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3499 "exts\t%0,%1,%3,%m2"
3500 [(set_attr "type" "arith")
3501 (set_attr "mode" "<MODE>")])
3504 (define_expand "extzv"
3505 [(set (match_operand 0 "register_operand")
3506 (zero_extract (match_operand 1 "nonimmediate_operand")
3507 (match_operand 2 "const_int_operand")
3508 (match_operand 3 "const_int_operand")))]
3511 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3512 INTVAL (operands[2]),
3513 INTVAL (operands[3])))
3515 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3516 INTVAL (operands[3])))
3518 if (GET_MODE (operands[0]) == DImode)
3519 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3522 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3530 (define_insn "extzv<mode>"
3531 [(set (match_operand:GPR 0 "register_operand" "=d")
3532 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3533 (match_operand 2 "const_int_operand" "")
3534 (match_operand 3 "const_int_operand" "")))]
3535 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3536 INTVAL (operands[3]))"
3537 "<d>ext\t%0,%1,%3,%2"
3538 [(set_attr "type" "arith")
3539 (set_attr "mode" "<MODE>")])
3541 (define_insn "*extzv_truncsi_exts"
3542 [(set (match_operand:SI 0 "register_operand" "=d")
3544 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3545 (match_operand 2 "const_int_operand" "")
3546 (match_operand 3 "const_int_operand" ""))))]
3547 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3549 [(set_attr "type" "arith")
3550 (set_attr "mode" "SI")])
3553 (define_expand "insv"
3554 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3555 (match_operand 1 "immediate_operand")
3556 (match_operand 2 "immediate_operand"))
3557 (match_operand 3 "reg_or_0_operand"))]
3560 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3561 INTVAL (operands[1]),
3562 INTVAL (operands[2])))
3564 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3565 INTVAL (operands[2])))
3567 if (GET_MODE (operands[0]) == DImode)
3568 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3571 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3579 (define_insn "insv<mode>"
3580 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3581 (match_operand:SI 1 "immediate_operand" "I")
3582 (match_operand:SI 2 "immediate_operand" "I"))
3583 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3584 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3585 INTVAL (operands[2]))"
3586 "<d>ins\t%0,%z3,%2,%1"
3587 [(set_attr "type" "arith")
3588 (set_attr "mode" "<MODE>")])
3590 ;; Combiner pattern for cins (clear and insert bit field). We can
3591 ;; implement mask-and-shift-left operation with this. Note that if
3592 ;; the upper bit of the mask is set in an SImode operation, the mask
3593 ;; itself will be sign-extended. mask_low_and_shift_len will
3594 ;; therefore be greater than our threshold of 32.
3596 (define_insn "*cins<mode>"
3597 [(set (match_operand:GPR 0 "register_operand" "=d")
3599 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3600 (match_operand:GPR 2 "const_int_operand" ""))
3601 (match_operand:GPR 3 "const_int_operand" "")))]
3603 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3606 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3607 return "cins\t%0,%1,%2,%m3";
3609 [(set_attr "type" "shift")
3610 (set_attr "mode" "<MODE>")])
3612 ;; Unaligned word moves generated by the bit field patterns.
3614 ;; As far as the rtl is concerned, both the left-part and right-part
3615 ;; instructions can access the whole field. However, the real operand
3616 ;; refers to just the first or the last byte (depending on endianness).
3617 ;; We therefore use two memory operands to each instruction, one to
3618 ;; describe the rtl effect and one to use in the assembly output.
3620 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3621 ;; This allows us to use the standard length calculations for the "load"
3622 ;; and "store" type attributes.
3624 (define_insn "mov_<load>l"
3625 [(set (match_operand:GPR 0 "register_operand" "=d")
3626 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3627 (match_operand:QI 2 "memory_operand" "m")]
3629 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3631 [(set_attr "move_type" "load")
3632 (set_attr "mode" "<MODE>")])
3634 (define_insn "mov_<load>r"
3635 [(set (match_operand:GPR 0 "register_operand" "=d")
3636 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3637 (match_operand:QI 2 "memory_operand" "m")
3638 (match_operand:GPR 3 "register_operand" "0")]
3639 UNSPEC_LOAD_RIGHT))]
3640 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3642 [(set_attr "move_type" "load")
3643 (set_attr "mode" "<MODE>")])
3645 (define_insn "mov_<store>l"
3646 [(set (match_operand:BLK 0 "memory_operand" "=m")
3647 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3648 (match_operand:QI 2 "memory_operand" "m")]
3649 UNSPEC_STORE_LEFT))]
3650 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3652 [(set_attr "move_type" "store")
3653 (set_attr "mode" "<MODE>")])
3655 (define_insn "mov_<store>r"
3656 [(set (match_operand:BLK 0 "memory_operand" "+m")
3657 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3658 (match_operand:QI 2 "memory_operand" "m")
3660 UNSPEC_STORE_RIGHT))]
3661 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3663 [(set_attr "move_type" "store")
3664 (set_attr "mode" "<MODE>")])
3666 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3667 ;; The required value is:
3669 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3671 ;; which translates to:
3673 ;; lui op0,%highest(op1)
3674 ;; daddiu op0,op0,%higher(op1)
3676 ;; daddiu op0,op0,%hi(op1)
3679 ;; The split is deferred until after flow2 to allow the peephole2 below
3681 (define_insn_and_split "*lea_high64"
3682 [(set (match_operand:DI 0 "register_operand" "=d")
3683 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3684 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3686 "&& epilogue_completed"
3687 [(set (match_dup 0) (high:DI (match_dup 2)))
3688 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3689 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3690 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3691 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3693 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3694 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3696 [(set_attr "length" "20")])
3698 ;; Use a scratch register to reduce the latency of the above pattern
3699 ;; on superscalar machines. The optimized sequence is:
3701 ;; lui op1,%highest(op2)
3703 ;; daddiu op1,op1,%higher(op2)
3705 ;; daddu op1,op1,op0
3707 [(set (match_operand:DI 1 "d_operand")
3708 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3709 (match_scratch:DI 0 "d")]
3710 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3711 [(set (match_dup 1) (high:DI (match_dup 3)))
3712 (set (match_dup 0) (high:DI (match_dup 4)))
3713 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3714 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3715 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3717 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3718 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3721 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3722 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3723 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3724 ;; used once. We can then use the sequence:
3726 ;; lui op0,%highest(op1)
3728 ;; daddiu op0,op0,%higher(op1)
3729 ;; daddiu op2,op2,%lo(op1)
3731 ;; daddu op0,op0,op2
3733 ;; which takes 4 cycles on most superscalar targets.
3734 (define_insn_and_split "*lea64"
3735 [(set (match_operand:DI 0 "register_operand" "=d")
3736 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3737 (clobber (match_scratch:DI 2 "=&d"))]
3738 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3740 "&& reload_completed"
3741 [(set (match_dup 0) (high:DI (match_dup 3)))
3742 (set (match_dup 2) (high:DI (match_dup 4)))
3743 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3744 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3745 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3746 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3748 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3749 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3751 [(set_attr "length" "24")])
3753 ;; Split HIGHs into:
3758 ;; on MIPS16 targets.
3760 [(set (match_operand:SI 0 "d_operand")
3761 (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
3762 "TARGET_MIPS16 && reload_completed"
3763 [(set (match_dup 0) (match_dup 2))
3764 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3766 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3769 ;; Insns to fetch a symbol from a big GOT.
3771 (define_insn_and_split "*xgot_hi<mode>"
3772 [(set (match_operand:P 0 "register_operand" "=d")
3773 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3774 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3776 "&& reload_completed"
3777 [(set (match_dup 0) (high:P (match_dup 2)))
3778 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3780 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3781 operands[3] = pic_offset_table_rtx;
3783 [(set_attr "got" "xgot_high")
3784 (set_attr "mode" "<MODE>")])
3786 (define_insn_and_split "*xgot_lo<mode>"
3787 [(set (match_operand:P 0 "register_operand" "=d")
3788 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3789 (match_operand:P 2 "got_disp_operand" "")))]
3790 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3792 "&& reload_completed"
3794 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3795 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3796 [(set_attr "got" "load")
3797 (set_attr "mode" "<MODE>")])
3799 ;; Insns to fetch a symbol from a normal GOT.
3801 (define_insn_and_split "*got_disp<mode>"
3802 [(set (match_operand:P 0 "register_operand" "=d")
3803 (match_operand:P 1 "got_disp_operand" ""))]
3804 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3806 "&& reload_completed"
3807 [(set (match_dup 0) (match_dup 2))]
3808 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3809 [(set_attr "got" "load")
3810 (set_attr "mode" "<MODE>")])
3812 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3814 (define_insn_and_split "*got_page<mode>"
3815 [(set (match_operand:P 0 "register_operand" "=d")
3816 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3817 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3819 "&& reload_completed"
3820 [(set (match_dup 0) (match_dup 2))]
3821 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3822 [(set_attr "got" "load")
3823 (set_attr "mode" "<MODE>")])
3825 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
3826 (define_expand "unspec_got<mode>"
3827 [(unspec:P [(match_operand:P 0)
3828 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
3830 ;; Lower-level instructions for loading an address from the GOT.
3831 ;; We could use MEMs, but an unspec gives more optimization
3834 (define_insn "load_got<mode>"
3835 [(set (match_operand:P 0 "register_operand" "=d")
3836 (unspec:P [(match_operand:P 1 "register_operand" "d")
3837 (match_operand:P 2 "immediate_operand" "")]
3840 "<load>\t%0,%R2(%1)"
3841 [(set_attr "got" "load")
3842 (set_attr "mode" "<MODE>")])
3844 ;; Instructions for adding the low 16 bits of an address to a register.
3845 ;; Operand 2 is the address: mips_print_operand works out which relocation
3846 ;; should be applied.
3848 (define_insn "*low<mode>"
3849 [(set (match_operand:P 0 "register_operand" "=d")
3850 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3851 (match_operand:P 2 "immediate_operand" "")))]
3853 "<d>addiu\t%0,%1,%R2"
3854 [(set_attr "type" "arith")
3855 (set_attr "mode" "<MODE>")])
3857 (define_insn "*low<mode>_mips16"
3858 [(set (match_operand:P 0 "register_operand" "=d")
3859 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3860 (match_operand:P 2 "immediate_operand" "")))]
3863 [(set_attr "type" "arith")
3864 (set_attr "mode" "<MODE>")
3865 (set_attr "extended_mips16" "yes")])
3867 ;; Expose MIPS16 uses of the global pointer after reload if the function
3868 ;; is responsible for setting up the register itself.
3870 [(set (match_operand:GPR 0 "d_operand")
3871 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
3872 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
3873 [(set (match_dup 0) (match_dup 1))]
3874 { operands[1] = pic_offset_table_rtx; })
3876 ;; Allow combine to split complex const_int load sequences, using operand 2
3877 ;; to store the intermediate results. See move_operand for details.
3879 [(set (match_operand:GPR 0 "register_operand")
3880 (match_operand:GPR 1 "splittable_const_int_operand"))
3881 (clobber (match_operand:GPR 2 "register_operand"))]
3885 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3889 ;; Likewise, for symbolic operands.
3891 [(set (match_operand:P 0 "register_operand")
3892 (match_operand:P 1))
3893 (clobber (match_operand:P 2 "register_operand"))]
3894 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3895 [(set (match_dup 0) (match_dup 3))]
3897 mips_split_symbol (operands[2], operands[1],
3898 MAX_MACHINE_MODE, &operands[3]);
3901 ;; 64-bit integer moves
3903 ;; Unlike most other insns, the move insns can't be split with
3904 ;; different predicates, because register spilling and other parts of
3905 ;; the compiler, have memoized the insn number already.
3907 (define_expand "movdi"
3908 [(set (match_operand:DI 0 "")
3909 (match_operand:DI 1 ""))]
3912 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3916 ;; For mips16, we need a special case to handle storing $31 into
3917 ;; memory, since we don't have a constraint to match $31. This
3918 ;; instruction can be generated by save_restore_insns.
3920 (define_insn "*mov<mode>_ra"
3921 [(set (match_operand:GPR 0 "stack_operand" "=m")
3922 (reg:GPR RETURN_ADDR_REGNUM))]
3925 [(set_attr "move_type" "store")
3926 (set_attr "mode" "<MODE>")])
3928 (define_insn "*movdi_32bit"
3929 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
3930 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
3931 "!TARGET_64BIT && !TARGET_MIPS16
3932 && (register_operand (operands[0], DImode)
3933 || reg_or_0_operand (operands[1], DImode))"
3934 { return mips_output_move (operands[0], operands[1]); }
3935 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
3936 (set_attr "mode" "DI")])
3938 (define_insn "*movdi_32bit_mips16"
3939 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3940 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3941 "!TARGET_64BIT && TARGET_MIPS16
3942 && (register_operand (operands[0], DImode)
3943 || register_operand (operands[1], DImode))"
3944 { return mips_output_move (operands[0], operands[1]); }
3945 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
3946 (set_attr "mode" "DI")])
3948 (define_insn "*movdi_64bit"
3949 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3950 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3951 "TARGET_64BIT && !TARGET_MIPS16
3952 && (register_operand (operands[0], DImode)
3953 || reg_or_0_operand (operands[1], DImode))"
3954 { return mips_output_move (operands[0], operands[1]); }
3955 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3956 (set_attr "mode" "DI")])
3958 (define_insn "*movdi_64bit_mips16"
3959 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3960 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3961 "TARGET_64BIT && TARGET_MIPS16
3962 && (register_operand (operands[0], DImode)
3963 || register_operand (operands[1], DImode))"
3964 { return mips_output_move (operands[0], operands[1]); }
3965 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3966 (set_attr "mode" "DI")])
3968 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3969 ;; when the original load is a 4 byte instruction but the add and the
3970 ;; load are 2 2 byte instructions.
3973 [(set (match_operand:DI 0 "d_operand")
3974 (mem:DI (plus:DI (match_dup 0)
3975 (match_operand:DI 1 "const_int_operand"))))]
3976 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3977 && !TARGET_DEBUG_D_MODE
3978 && ((INTVAL (operands[1]) < 0
3979 && INTVAL (operands[1]) >= -0x10)
3980 || (INTVAL (operands[1]) >= 32 * 8
3981 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3982 || (INTVAL (operands[1]) >= 0
3983 && INTVAL (operands[1]) < 32 * 8
3984 && (INTVAL (operands[1]) & 7) != 0))"
3985 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3986 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3988 HOST_WIDE_INT val = INTVAL (operands[1]);
3991 operands[2] = const0_rtx;
3992 else if (val >= 32 * 8)
3996 operands[1] = GEN_INT (0x8 + off);
3997 operands[2] = GEN_INT (val - off - 0x8);
4003 operands[1] = GEN_INT (off);
4004 operands[2] = GEN_INT (val - off);
4008 ;; 32-bit Integer moves
4010 ;; Unlike most other insns, the move insns can't be split with
4011 ;; different predicates, because register spilling and other parts of
4012 ;; the compiler, have memoized the insn number already.
4014 (define_expand "mov<mode>"
4015 [(set (match_operand:IMOVE32 0 "")
4016 (match_operand:IMOVE32 1 ""))]
4019 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4023 ;; The difference between these two is whether or not ints are allowed
4024 ;; in FP registers (off by default, use -mdebugh to enable).
4026 (define_insn "*mov<mode>_internal"
4027 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4028 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4030 && (register_operand (operands[0], <MODE>mode)
4031 || reg_or_0_operand (operands[1], <MODE>mode))"
4032 { return mips_output_move (operands[0], operands[1]); }
4033 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
4034 (set_attr "mode" "SI")])
4036 (define_insn "*mov<mode>_mips16"
4037 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4038 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4040 && (register_operand (operands[0], <MODE>mode)
4041 || register_operand (operands[1], <MODE>mode))"
4042 { return mips_output_move (operands[0], operands[1]); }
4043 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
4044 (set_attr "mode" "SI")])
4046 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4047 ;; when the original load is a 4 byte instruction but the add and the
4048 ;; load are 2 2 byte instructions.
4051 [(set (match_operand:SI 0 "d_operand")
4052 (mem:SI (plus:SI (match_dup 0)
4053 (match_operand:SI 1 "const_int_operand"))))]
4054 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4055 && ((INTVAL (operands[1]) < 0
4056 && INTVAL (operands[1]) >= -0x80)
4057 || (INTVAL (operands[1]) >= 32 * 4
4058 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4059 || (INTVAL (operands[1]) >= 0
4060 && INTVAL (operands[1]) < 32 * 4
4061 && (INTVAL (operands[1]) & 3) != 0))"
4062 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4063 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4065 HOST_WIDE_INT val = INTVAL (operands[1]);
4068 operands[2] = const0_rtx;
4069 else if (val >= 32 * 4)
4073 operands[1] = GEN_INT (0x7c + off);
4074 operands[2] = GEN_INT (val - off - 0x7c);
4080 operands[1] = GEN_INT (off);
4081 operands[2] = GEN_INT (val - off);
4085 ;; On the mips16, we can split a load of certain constants into a load
4086 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4090 [(set (match_operand:SI 0 "d_operand")
4091 (match_operand:SI 1 "const_int_operand"))]
4092 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4093 && INTVAL (operands[1]) >= 0x100
4094 && INTVAL (operands[1]) <= 0xff + 0x7f"
4095 [(set (match_dup 0) (match_dup 1))
4096 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4098 int val = INTVAL (operands[1]);
4100 operands[1] = GEN_INT (0xff);
4101 operands[2] = GEN_INT (val - 0xff);
4104 ;; This insn handles moving CCmode values. It's really just a
4105 ;; slightly simplified copy of movsi_internal2, with additional cases
4106 ;; to move a condition register to a general register and to move
4107 ;; between the general registers and the floating point registers.
4109 (define_insn "movcc"
4110 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4111 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4112 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4113 { return mips_output_move (operands[0], operands[1]); }
4114 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
4115 (set_attr "mode" "SI")])
4117 ;; Reload condition code registers. reload_incc and reload_outcc
4118 ;; both handle moves from arbitrary operands into condition code
4119 ;; registers. reload_incc handles the more common case in which
4120 ;; a source operand is constrained to be in a condition-code
4121 ;; register, but has not been allocated to one.
4123 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4124 ;; constraints do not include 'z'. reload_outcc handles the case
4125 ;; when such an operand is allocated to a condition-code register.
4127 ;; Note that reloads from a condition code register to some
4128 ;; other location can be done using ordinary moves. Moving
4129 ;; into a GPR takes a single movcc, moving elsewhere takes
4130 ;; two. We can leave these cases to the generic reload code.
4131 (define_expand "reload_incc"
4132 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4133 (match_operand:CC 1 "general_operand" ""))
4134 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4135 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4137 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4141 (define_expand "reload_outcc"
4142 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4143 (match_operand:CC 1 "register_operand" ""))
4144 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4145 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4147 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4151 ;; MIPS4 supports loading and storing a floating point register from
4152 ;; the sum of two general registers. We use two versions for each of
4153 ;; these four instructions: one where the two general registers are
4154 ;; SImode, and one where they are DImode. This is because general
4155 ;; registers will be in SImode when they hold 32-bit values, but,
4156 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4157 ;; instructions will still work correctly.
4159 ;; ??? Perhaps it would be better to support these instructions by
4160 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4161 ;; these instructions can only be used to load and store floating
4162 ;; point registers, that would probably cause trouble in reload.
4164 (define_insn "*<ANYF:loadx>_<P:mode>"
4165 [(set (match_operand:ANYF 0 "register_operand" "=f")
4166 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4167 (match_operand:P 2 "register_operand" "d"))))]
4169 "<ANYF:loadx>\t%0,%1(%2)"
4170 [(set_attr "type" "fpidxload")
4171 (set_attr "mode" "<ANYF:UNITMODE>")])
4173 (define_insn "*<ANYF:storex>_<P:mode>"
4174 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4175 (match_operand:P 2 "register_operand" "d")))
4176 (match_operand:ANYF 0 "register_operand" "f"))]
4178 "<ANYF:storex>\t%0,%1(%2)"
4179 [(set_attr "type" "fpidxstore")
4180 (set_attr "mode" "<ANYF:UNITMODE>")])
4182 ;; Scaled indexed address load.
4183 ;; Per md.texi, we only need to look for a pattern with multiply in the
4184 ;; address expression, not shift.
4186 (define_insn "*lwxs"
4187 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4189 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4191 (match_operand:P 2 "register_operand" "d"))))]
4194 [(set_attr "type" "load")
4195 (set_attr "mode" "SI")])
4197 ;; 16-bit Integer moves
4199 ;; Unlike most other insns, the move insns can't be split with
4200 ;; different predicates, because register spilling and other parts of
4201 ;; the compiler, have memoized the insn number already.
4202 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4204 (define_expand "movhi"
4205 [(set (match_operand:HI 0 "")
4206 (match_operand:HI 1 ""))]
4209 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4213 (define_insn "*movhi_internal"
4214 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4215 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4217 && (register_operand (operands[0], HImode)
4218 || reg_or_0_operand (operands[1], HImode))"
4219 { return mips_output_move (operands[0], operands[1]); }
4220 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4221 (set_attr "mode" "HI")])
4223 (define_insn "*movhi_mips16"
4224 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4225 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4227 && (register_operand (operands[0], HImode)
4228 || register_operand (operands[1], HImode))"
4229 { return mips_output_move (operands[0], operands[1]); }
4230 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4231 (set_attr "mode" "HI")])
4233 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4234 ;; when the original load is a 4 byte instruction but the add and the
4235 ;; load are 2 2 byte instructions.
4238 [(set (match_operand:HI 0 "d_operand")
4239 (mem:HI (plus:SI (match_dup 0)
4240 (match_operand:SI 1 "const_int_operand"))))]
4241 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4242 && ((INTVAL (operands[1]) < 0
4243 && INTVAL (operands[1]) >= -0x80)
4244 || (INTVAL (operands[1]) >= 32 * 2
4245 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4246 || (INTVAL (operands[1]) >= 0
4247 && INTVAL (operands[1]) < 32 * 2
4248 && (INTVAL (operands[1]) & 1) != 0))"
4249 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4250 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4252 HOST_WIDE_INT val = INTVAL (operands[1]);
4255 operands[2] = const0_rtx;
4256 else if (val >= 32 * 2)
4260 operands[1] = GEN_INT (0x7e + off);
4261 operands[2] = GEN_INT (val - off - 0x7e);
4267 operands[1] = GEN_INT (off);
4268 operands[2] = GEN_INT (val - off);
4272 ;; 8-bit Integer moves
4274 ;; Unlike most other insns, the move insns can't be split with
4275 ;; different predicates, because register spilling and other parts of
4276 ;; the compiler, have memoized the insn number already.
4277 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4279 (define_expand "movqi"
4280 [(set (match_operand:QI 0 "")
4281 (match_operand:QI 1 ""))]
4284 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4288 (define_insn "*movqi_internal"
4289 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4290 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4292 && (register_operand (operands[0], QImode)
4293 || reg_or_0_operand (operands[1], QImode))"
4294 { return mips_output_move (operands[0], operands[1]); }
4295 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4296 (set_attr "mode" "QI")])
4298 (define_insn "*movqi_mips16"
4299 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4300 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4302 && (register_operand (operands[0], QImode)
4303 || register_operand (operands[1], QImode))"
4304 { return mips_output_move (operands[0], operands[1]); }
4305 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4306 (set_attr "mode" "QI")])
4308 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4309 ;; when the original load is a 4 byte instruction but the add and the
4310 ;; load are 2 2 byte instructions.
4313 [(set (match_operand:QI 0 "d_operand")
4314 (mem:QI (plus:SI (match_dup 0)
4315 (match_operand:SI 1 "const_int_operand"))))]
4316 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4317 && ((INTVAL (operands[1]) < 0
4318 && INTVAL (operands[1]) >= -0x80)
4319 || (INTVAL (operands[1]) >= 32
4320 && INTVAL (operands[1]) <= 31 + 0x7f))"
4321 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4322 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4324 HOST_WIDE_INT val = INTVAL (operands[1]);
4327 operands[2] = const0_rtx;
4330 operands[1] = GEN_INT (0x7f);
4331 operands[2] = GEN_INT (val - 0x7f);
4335 ;; 32-bit floating point moves
4337 (define_expand "movsf"
4338 [(set (match_operand:SF 0 "")
4339 (match_operand:SF 1 ""))]
4342 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4346 (define_insn "*movsf_hardfloat"
4347 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4348 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4350 && (register_operand (operands[0], SFmode)
4351 || reg_or_0_operand (operands[1], SFmode))"
4352 { return mips_output_move (operands[0], operands[1]); }
4353 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4354 (set_attr "mode" "SF")])
4356 (define_insn "*movsf_softfloat"
4357 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4358 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4359 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4360 && (register_operand (operands[0], SFmode)
4361 || reg_or_0_operand (operands[1], SFmode))"
4362 { return mips_output_move (operands[0], operands[1]); }
4363 [(set_attr "move_type" "move,load,store")
4364 (set_attr "mode" "SF")])
4366 (define_insn "*movsf_mips16"
4367 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4368 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4370 && (register_operand (operands[0], SFmode)
4371 || register_operand (operands[1], SFmode))"
4372 { return mips_output_move (operands[0], operands[1]); }
4373 [(set_attr "move_type" "move,move,move,load,store")
4374 (set_attr "mode" "SF")])
4376 ;; 64-bit floating point moves
4378 (define_expand "movdf"
4379 [(set (match_operand:DF 0 "")
4380 (match_operand:DF 1 ""))]
4383 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4387 (define_insn "*movdf_hardfloat"
4388 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4389 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4390 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4391 && (register_operand (operands[0], DFmode)
4392 || reg_or_0_operand (operands[1], DFmode))"
4393 { return mips_output_move (operands[0], operands[1]); }
4394 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4395 (set_attr "mode" "DF")])
4397 (define_insn "*movdf_softfloat"
4398 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4399 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4400 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4401 && (register_operand (operands[0], DFmode)
4402 || reg_or_0_operand (operands[1], DFmode))"
4403 { return mips_output_move (operands[0], operands[1]); }
4404 [(set_attr "move_type" "move,load,store")
4405 (set_attr "mode" "DF")])
4407 (define_insn "*movdf_mips16"
4408 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4409 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4411 && (register_operand (operands[0], DFmode)
4412 || register_operand (operands[1], DFmode))"
4413 { return mips_output_move (operands[0], operands[1]); }
4414 [(set_attr "move_type" "move,move,move,load,store")
4415 (set_attr "mode" "DF")])
4417 ;; 128-bit integer moves
4419 (define_expand "movti"
4420 [(set (match_operand:TI 0)
4421 (match_operand:TI 1))]
4424 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4428 (define_insn "*movti"
4429 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4430 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4433 && (register_operand (operands[0], TImode)
4434 || reg_or_0_operand (operands[1], TImode))"
4436 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4437 (set_attr "mode" "TI")])
4439 (define_insn "*movti_mips16"
4440 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4441 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4444 && (register_operand (operands[0], TImode)
4445 || register_operand (operands[1], TImode))"
4447 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4448 (set_attr "mode" "TI")])
4450 ;; 128-bit floating point moves
4452 (define_expand "movtf"
4453 [(set (match_operand:TF 0)
4454 (match_operand:TF 1))]
4457 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4461 ;; This pattern handles both hard- and soft-float cases.
4462 (define_insn "*movtf"
4463 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4464 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4467 && (register_operand (operands[0], TFmode)
4468 || reg_or_0_operand (operands[1], TFmode))"
4470 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4471 (set_attr "mode" "TF")])
4473 (define_insn "*movtf_mips16"
4474 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4475 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4478 && (register_operand (operands[0], TFmode)
4479 || register_operand (operands[1], TFmode))"
4481 [(set_attr "move_type" "move,move,move,load,store")
4482 (set_attr "mode" "TF")])
4485 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4486 (match_operand:MOVE64 1 "move_operand"))]
4487 "reload_completed && !TARGET_64BIT
4488 && mips_split_64bit_move_p (operands[0], operands[1])"
4491 mips_split_doubleword_move (operands[0], operands[1]);
4496 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4497 (match_operand:MOVE128 1 "move_operand"))]
4498 "TARGET_64BIT && reload_completed"
4501 mips_split_doubleword_move (operands[0], operands[1]);
4505 ;; When generating mips16 code, split moves of negative constants into
4506 ;; a positive "li" followed by a negation.
4508 [(set (match_operand 0 "d_operand")
4509 (match_operand 1 "const_int_operand"))]
4510 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4514 (neg:SI (match_dup 2)))]
4516 operands[2] = gen_lowpart (SImode, operands[0]);
4517 operands[3] = GEN_INT (-INTVAL (operands[1]));
4520 ;; 64-bit paired-single floating point moves
4522 (define_expand "movv2sf"
4523 [(set (match_operand:V2SF 0)
4524 (match_operand:V2SF 1))]
4525 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4527 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4531 (define_insn "*movv2sf"
4532 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4533 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4535 && TARGET_PAIRED_SINGLE_FLOAT
4536 && (register_operand (operands[0], V2SFmode)
4537 || reg_or_0_operand (operands[1], V2SFmode))"
4538 { return mips_output_move (operands[0], operands[1]); }
4539 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4540 (set_attr "mode" "DF")])
4542 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4543 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4545 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4546 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4547 ;; and the errata related to -mfix-vr4130.
4548 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4549 [(set (match_operand:GPR 0 "register_operand" "=d")
4550 (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
4553 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4554 [(set_attr "move_type" "mfhilo")
4555 (set_attr "mode" "<GPR:MODE>")])
4557 ;; Set the high part of a HI/LO value, given that the low part has
4558 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4559 ;; why we can't just use (reg:GPR HI_REGNUM).
4560 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4561 [(set (match_operand:HILO 0 "register_operand" "=x")
4562 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4563 (match_operand:GPR 2 "register_operand" "l")]
4567 [(set_attr "move_type" "mthilo")
4568 (set_attr "mode" "SI")])
4570 ;; Emit a doubleword move in which exactly one of the operands is
4571 ;; a floating-point register. We can't just emit two normal moves
4572 ;; because of the constraints imposed by the FPU register model;
4573 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4574 ;; the FPR whole and use special patterns to refer to each word of
4575 ;; the other operand.
4577 (define_expand "move_doubleword_fpr<mode>"
4578 [(set (match_operand:SPLITF 0)
4579 (match_operand:SPLITF 1))]
4582 if (FP_REG_RTX_P (operands[0]))
4584 rtx low = mips_subword (operands[1], 0);
4585 rtx high = mips_subword (operands[1], 1);
4586 emit_insn (gen_load_low<mode> (operands[0], low));
4587 if (TARGET_FLOAT64 && !TARGET_64BIT)
4588 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4590 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4594 rtx low = mips_subword (operands[0], 0);
4595 rtx high = mips_subword (operands[0], 1);
4596 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4597 if (TARGET_FLOAT64 && !TARGET_64BIT)
4598 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4600 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4605 ;; Load the low word of operand 0 with operand 1.
4606 (define_insn "load_low<mode>"
4607 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4608 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4612 operands[0] = mips_subword (operands[0], 0);
4613 return mips_output_move (operands[0], operands[1]);
4615 [(set_attr "move_type" "mtc,fpload")
4616 (set_attr "mode" "<HALFMODE>")])
4618 ;; Load the high word of operand 0 from operand 1, preserving the value
4620 (define_insn "load_high<mode>"
4621 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4622 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4623 (match_operand:SPLITF 2 "register_operand" "0,0")]
4627 operands[0] = mips_subword (operands[0], 1);
4628 return mips_output_move (operands[0], operands[1]);
4630 [(set_attr "move_type" "mtc,fpload")
4631 (set_attr "mode" "<HALFMODE>")])
4633 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4634 ;; high word and 0 to store the low word.
4635 (define_insn "store_word<mode>"
4636 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4637 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4638 (match_operand 2 "const_int_operand")]
4639 UNSPEC_STORE_WORD))]
4642 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4643 return mips_output_move (operands[0], operands[1]);
4645 [(set_attr "move_type" "mfc,fpstore")
4646 (set_attr "mode" "<HALFMODE>")])
4648 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4649 ;; value in the low word.
4650 (define_insn "mthc1<mode>"
4651 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4652 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4653 (match_operand:SPLITF 2 "register_operand" "0")]
4655 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4657 [(set_attr "move_type" "mtc")
4658 (set_attr "mode" "<HALFMODE>")])
4660 ;; Move high word of operand 1 to operand 0 using mfhc1.
4661 (define_insn "mfhc1<mode>"
4662 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4663 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4665 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4667 [(set_attr "move_type" "mfc")
4668 (set_attr "mode" "<HALFMODE>")])
4670 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4671 (define_expand "load_const_gp_<mode>"
4672 [(set (match_operand:P 0 "register_operand" "=d")
4673 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4675 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4676 ;; of _gp from the start of this function. Operand 1 is the incoming
4677 ;; function address.
4678 (define_insn_and_split "loadgp_newabi_<mode>"
4679 [(set (match_operand:P 0 "register_operand" "=d")
4680 (unspec:P [(match_operand:P 1)
4681 (match_operand:P 2 "register_operand" "d")]
4683 "mips_current_loadgp_style () == LOADGP_NEWABI"
4684 { return mips_must_initialize_gp_p () ? "#" : ""; }
4685 "&& mips_must_initialize_gp_p ()"
4686 [(set (match_dup 0) (match_dup 3))
4687 (set (match_dup 0) (match_dup 4))
4688 (set (match_dup 0) (match_dup 5))]
4690 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4691 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4692 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4694 [(set_attr "type" "ghost")])
4696 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4697 (define_insn_and_split "loadgp_absolute_<mode>"
4698 [(set (match_operand:P 0 "register_operand" "=d")
4699 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4700 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4701 { return mips_must_initialize_gp_p () ? "#" : ""; }
4702 "&& mips_must_initialize_gp_p ()"
4705 mips_emit_move (operands[0], operands[1]);
4708 [(set_attr "type" "ghost")])
4710 ;; This blockage instruction prevents the gp load from being
4711 ;; scheduled after an implicit use of gp. It also prevents
4712 ;; the load from being deleted as dead.
4713 (define_insn "loadgp_blockage"
4714 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4717 [(set_attr "type" "ghost")])
4719 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4720 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4721 (define_insn_and_split "loadgp_rtp_<mode>"
4722 [(set (match_operand:P 0 "register_operand" "=d")
4723 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
4724 (match_operand:P 2 "symbol_ref_operand")]
4726 "mips_current_loadgp_style () == LOADGP_RTP"
4727 { return mips_must_initialize_gp_p () ? "#" : ""; }
4728 "&& mips_must_initialize_gp_p ()"
4729 [(set (match_dup 0) (high:P (match_dup 3)))
4730 (set (match_dup 0) (unspec:P [(match_dup 0)
4731 (match_dup 3)] UNSPEC_LOAD_GOT))
4732 (set (match_dup 0) (unspec:P [(match_dup 0)
4733 (match_dup 4)] UNSPEC_LOAD_GOT))]
4735 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4736 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4738 [(set_attr "type" "ghost")])
4740 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4741 ;; global pointer and operand 1 is the MIPS16 register that holds
4742 ;; the required value.
4743 (define_insn_and_split "copygp_mips16"
4744 [(set (match_operand:SI 0 "register_operand" "=y")
4745 (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
4748 { return mips_must_initialize_gp_p () ? "#" : ""; }
4749 "&& mips_must_initialize_gp_p ()"
4750 [(set (match_dup 0) (match_dup 1))]
4752 [(set_attr "type" "ghost")])
4754 ;; A placeholder for where the cprestore instruction should go,
4755 ;; if we decide we need one. Operand 0 and operand 1 are as for
4756 ;; "cprestore". Operand 2 is a register that holds the gp value.
4758 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
4759 ;; otherwise any register that holds the correct value will do.
4760 (define_insn_and_split "potential_cprestore"
4761 [(set (match_operand:SI 0 "cprestore_save_slot_operand" "=X,X")
4762 (unspec:SI [(match_operand:SI 1 "const_int_operand" "I,i")
4763 (match_operand:SI 2 "register_operand" "d,d")]
4764 UNSPEC_POTENTIAL_CPRESTORE))
4765 (clobber (match_operand:SI 3 "scratch_operand" "=X,&d"))]
4766 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
4767 { return mips_must_initialize_gp_p () ? "#" : ""; }
4768 "mips_must_initialize_gp_p ()"
4771 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
4772 operands[2], operands[3]);
4775 [(set_attr "type" "ghost")])
4777 ;; Emit a .cprestore directive, which normally expands to a single store
4778 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
4779 ;; for the cprestore slot. Operand 1 is the offset of the slot from
4780 ;; the stack pointer. (This is redundant with operand 0, but it makes
4781 ;; things a little simpler.)
4782 (define_insn "cprestore"
4783 [(set (match_operand:SI 0 "cprestore_save_slot_operand" "=X,X")
4784 (unspec:SI [(match_operand:SI 1 "const_int_operand" "I,i")
4787 "TARGET_CPRESTORE_DIRECTIVE"
4789 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
4790 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
4792 return ".cprestore\t%1";
4794 [(set_attr "type" "store")
4795 (set_attr "length" "4,12")])
4797 (define_insn "use_cprestore"
4798 [(set (reg:SI CPRESTORE_SLOT_REGNUM)
4799 (match_operand:SI 0 "cprestore_load_slot_operand"))]
4802 [(set_attr "type" "ghost")])
4804 ;; Expand in-line code to clear the instruction cache between operand[0] and
4806 (define_expand "clear_cache"
4807 [(match_operand 0 "pmode_register_operand")
4808 (match_operand 1 "pmode_register_operand")]
4814 mips_expand_synci_loop (operands[0], operands[1]);
4815 emit_insn (gen_sync ());
4816 emit_insn (Pmode == SImode
4817 ? gen_clear_hazard_si ()
4818 : gen_clear_hazard_di ());
4820 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4822 rtx len = gen_reg_rtx (Pmode);
4823 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4824 MIPS_ICACHE_SYNC (operands[0], len);
4830 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4832 { return mips_output_sync (); })
4834 (define_insn "synci"
4835 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4840 (define_insn "rdhwr_synci_step_<mode>"
4841 [(set (match_operand:P 0 "register_operand" "=d")
4842 (unspec_volatile [(const_int 1)]
4847 (define_insn "clear_hazard_<mode>"
4848 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4849 (clobber (reg:P RETURN_ADDR_REGNUM))]
4852 return "%(%<bal\t1f\n"
4854 "1:\t<d>addiu\t$31,$31,12\n"
4858 [(set_attr "length" "20")])
4860 ;; Cache operations for R4000-style caches.
4861 (define_insn "mips_cache"
4862 [(set (mem:BLK (scratch))
4863 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
4864 (match_operand:QI 1 "address_operand" "p")]
4865 UNSPEC_MIPS_CACHE))]
4869 ;; Similar, but with the operands hard-coded to an R10K cache barrier
4870 ;; operation. We keep the pattern distinct so that we can identify
4871 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
4872 ;; the operation is never inserted into a delay slot.
4873 (define_insn "r10k_cache_barrier"
4874 [(set (mem:BLK (scratch))
4875 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
4878 [(set_attr "can_delay" "no")])
4880 ;; Block moves, see mips.c for more details.
4881 ;; Argument 0 is the destination
4882 ;; Argument 1 is the source
4883 ;; Argument 2 is the length
4884 ;; Argument 3 is the alignment
4886 (define_expand "movmemsi"
4887 [(parallel [(set (match_operand:BLK 0 "general_operand")
4888 (match_operand:BLK 1 "general_operand"))
4889 (use (match_operand:SI 2 ""))
4890 (use (match_operand:SI 3 "const_int_operand"))])]
4891 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4893 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4900 ;; ....................
4904 ;; ....................
4906 (define_expand "<optab><mode>3"
4907 [(set (match_operand:GPR 0 "register_operand")
4908 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4909 (match_operand:SI 2 "arith_operand")))]
4912 /* On the mips16, a shift of more than 8 is a four byte instruction,
4913 so, for a shift between 8 and 16, it is just as fast to do two
4914 shifts of 8 or less. If there is a lot of shifting going on, we
4915 may win in CSE. Otherwise combine will put the shifts back
4916 together again. This can be called by mips_function_arg, so we must
4917 be careful not to allocate a new register if we've reached the
4921 && CONST_INT_P (operands[2])
4922 && INTVAL (operands[2]) > 8
4923 && INTVAL (operands[2]) <= 16
4924 && !reload_in_progress
4925 && !reload_completed)
4927 rtx temp = gen_reg_rtx (<MODE>mode);
4929 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4930 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4931 GEN_INT (INTVAL (operands[2]) - 8)));
4936 (define_insn "*<optab><mode>3"
4937 [(set (match_operand:GPR 0 "register_operand" "=d")
4938 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4939 (match_operand:SI 2 "arith_operand" "dI")))]
4942 if (CONST_INT_P (operands[2]))
4943 operands[2] = GEN_INT (INTVAL (operands[2])
4944 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4946 return "<d><insn>\t%0,%1,%2";
4948 [(set_attr "type" "shift")
4949 (set_attr "mode" "<MODE>")])
4951 (define_insn "*<optab>si3_extend"
4952 [(set (match_operand:DI 0 "register_operand" "=d")
4954 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4955 (match_operand:SI 2 "arith_operand" "dI"))))]
4956 "TARGET_64BIT && !TARGET_MIPS16"
4958 if (CONST_INT_P (operands[2]))
4959 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4961 return "<insn>\t%0,%1,%2";
4963 [(set_attr "type" "shift")
4964 (set_attr "mode" "SI")])
4966 (define_insn "*<optab>si3_mips16"
4967 [(set (match_operand:SI 0 "register_operand" "=d,d")
4968 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4969 (match_operand:SI 2 "arith_operand" "d,I")))]
4972 if (which_alternative == 0)
4973 return "<insn>\t%0,%2";
4975 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4976 return "<insn>\t%0,%1,%2";
4978 [(set_attr "type" "shift")
4979 (set_attr "mode" "SI")
4980 (set_attr_alternative "length"
4982 (if_then_else (match_operand 2 "m16_uimm3_b")
4986 ;; We need separate DImode MIPS16 patterns because of the irregularity
4988 (define_insn "*ashldi3_mips16"
4989 [(set (match_operand:DI 0 "register_operand" "=d,d")
4990 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4991 (match_operand:SI 2 "arith_operand" "d,I")))]
4992 "TARGET_64BIT && TARGET_MIPS16"
4994 if (which_alternative == 0)
4995 return "dsll\t%0,%2";
4997 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4998 return "dsll\t%0,%1,%2";
5000 [(set_attr "type" "shift")
5001 (set_attr "mode" "DI")
5002 (set_attr_alternative "length"
5004 (if_then_else (match_operand 2 "m16_uimm3_b")
5008 (define_insn "*ashrdi3_mips16"
5009 [(set (match_operand:DI 0 "register_operand" "=d,d")
5010 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5011 (match_operand:SI 2 "arith_operand" "d,I")))]
5012 "TARGET_64BIT && TARGET_MIPS16"
5014 if (CONST_INT_P (operands[2]))
5015 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5017 return "dsra\t%0,%2";
5019 [(set_attr "type" "shift")
5020 (set_attr "mode" "DI")
5021 (set_attr_alternative "length"
5023 (if_then_else (match_operand 2 "m16_uimm3_b")
5027 (define_insn "*lshrdi3_mips16"
5028 [(set (match_operand:DI 0 "register_operand" "=d,d")
5029 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5030 (match_operand:SI 2 "arith_operand" "d,I")))]
5031 "TARGET_64BIT && TARGET_MIPS16"
5033 if (CONST_INT_P (operands[2]))
5034 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5036 return "dsrl\t%0,%2";
5038 [(set_attr "type" "shift")
5039 (set_attr "mode" "DI")
5040 (set_attr_alternative "length"
5042 (if_then_else (match_operand 2 "m16_uimm3_b")
5046 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5049 [(set (match_operand:GPR 0 "d_operand")
5050 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5051 (match_operand:GPR 2 "const_int_operand")))]
5052 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5053 && INTVAL (operands[2]) > 8
5054 && INTVAL (operands[2]) <= 16"
5055 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5056 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5057 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5059 ;; If we load a byte on the mips16 as a bitfield, the resulting
5060 ;; sequence of instructions is too complicated for combine, because it
5061 ;; involves four instructions: a load, a shift, a constant load into a
5062 ;; register, and an and (the key problem here is that the mips16 does
5063 ;; not have and immediate). We recognize a shift of a load in order
5064 ;; to make it simple enough for combine to understand.
5066 ;; The length here is the worst case: the length of the split version
5067 ;; will be more accurate.
5068 (define_insn_and_split ""
5069 [(set (match_operand:SI 0 "register_operand" "=d")
5070 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5071 (match_operand:SI 2 "immediate_operand" "I")))]
5075 [(set (match_dup 0) (match_dup 1))
5076 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5078 [(set_attr "type" "load")
5079 (set_attr "mode" "SI")
5080 (set_attr "length" "16")])
5082 (define_insn "rotr<mode>3"
5083 [(set (match_operand:GPR 0 "register_operand" "=d")
5084 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5085 (match_operand:SI 2 "arith_operand" "dI")))]
5088 if (CONST_INT_P (operands[2]))
5089 gcc_assert (INTVAL (operands[2]) >= 0
5090 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5092 return "<d>ror\t%0,%1,%2";
5094 [(set_attr "type" "shift")
5095 (set_attr "mode" "<MODE>")])
5098 ;; ....................
5100 ;; CONDITIONAL BRANCHES
5102 ;; ....................
5104 ;; Conditional branches on floating-point equality tests.
5106 (define_insn "*branch_fp"
5109 (match_operator 1 "equality_operator"
5110 [(match_operand:CC 2 "register_operand" "z")
5112 (label_ref (match_operand 0 "" ""))
5116 return mips_output_conditional_branch (insn, operands,
5117 MIPS_BRANCH ("b%F1", "%Z2%0"),
5118 MIPS_BRANCH ("b%W1", "%Z2%0"));
5120 [(set_attr "type" "branch")])
5122 (define_insn "*branch_fp_inverted"
5125 (match_operator 1 "equality_operator"
5126 [(match_operand:CC 2 "register_operand" "z")
5129 (label_ref (match_operand 0 "" ""))))]
5132 return mips_output_conditional_branch (insn, operands,
5133 MIPS_BRANCH ("b%W1", "%Z2%0"),
5134 MIPS_BRANCH ("b%F1", "%Z2%0"));
5136 [(set_attr "type" "branch")])
5138 ;; Conditional branches on ordered comparisons with zero.
5140 (define_insn "*branch_order<mode>"
5143 (match_operator 1 "order_operator"
5144 [(match_operand:GPR 2 "register_operand" "d")
5146 (label_ref (match_operand 0 "" ""))
5149 { return mips_output_order_conditional_branch (insn, operands, false); }
5150 [(set_attr "type" "branch")])
5152 (define_insn "*branch_order<mode>_inverted"
5155 (match_operator 1 "order_operator"
5156 [(match_operand:GPR 2 "register_operand" "d")
5159 (label_ref (match_operand 0 "" ""))))]
5161 { return mips_output_order_conditional_branch (insn, operands, true); }
5162 [(set_attr "type" "branch")])
5164 ;; Conditional branch on equality comparison.
5166 (define_insn "*branch_equality<mode>"
5169 (match_operator 1 "equality_operator"
5170 [(match_operand:GPR 2 "register_operand" "d")
5171 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5172 (label_ref (match_operand 0 "" ""))
5176 return mips_output_conditional_branch (insn, operands,
5177 MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
5178 MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
5180 [(set_attr "type" "branch")])
5182 (define_insn "*branch_equality<mode>_inverted"
5185 (match_operator 1 "equality_operator"
5186 [(match_operand:GPR 2 "register_operand" "d")
5187 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5189 (label_ref (match_operand 0 "" ""))))]
5192 return mips_output_conditional_branch (insn, operands,
5193 MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
5194 MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
5196 [(set_attr "type" "branch")])
5200 (define_insn "*branch_equality<mode>_mips16"
5203 (match_operator 0 "equality_operator"
5204 [(match_operand:GPR 1 "register_operand" "d,t")
5206 (match_operand 2 "pc_or_label_operand" "")
5207 (match_operand 3 "pc_or_label_operand" "")))]
5210 if (operands[2] != pc_rtx)
5212 if (which_alternative == 0)
5213 return "b%C0z\t%1,%2";
5215 return "bt%C0z\t%2";
5219 if (which_alternative == 0)
5220 return "b%N0z\t%1,%3";
5222 return "bt%N0z\t%3";
5225 [(set_attr "type" "branch")])
5227 (define_expand "cbranch<mode>4"
5229 (if_then_else (match_operator 0 "comparison_operator"
5230 [(match_operand:GPR 1 "register_operand")
5231 (match_operand:GPR 2 "nonmemory_operand")])
5232 (label_ref (match_operand 3 ""))
5236 mips_expand_conditional_branch (operands);
5240 (define_expand "cbranch<mode>4"
5242 (if_then_else (match_operator 0 "comparison_operator"
5243 [(match_operand:SCALARF 1 "register_operand")
5244 (match_operand:SCALARF 2 "register_operand")])
5245 (label_ref (match_operand 3 ""))
5249 mips_expand_conditional_branch (operands);
5253 ;; Used to implement built-in functions.
5254 (define_expand "condjump"
5256 (if_then_else (match_operand 0)
5257 (label_ref (match_operand 1))
5260 ;; Branch if bit is set/clear.
5262 (define_insn "*branch_bit<bbv><mode>"
5265 (equality_op (zero_extract:GPR
5266 (match_operand:GPR 1 "register_operand" "d")
5268 (match_operand 2 "const_int_operand" ""))
5270 (label_ref (match_operand 0 ""))
5272 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5275 mips_output_conditional_branch (insn, operands,
5276 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5277 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5279 [(set_attr "type" "branch")
5280 (set_attr "branch_likely" "no")])
5282 (define_insn "*branch_bit<bbv><mode>_inverted"
5285 (equality_op (zero_extract:GPR
5286 (match_operand:GPR 1 "register_operand" "d")
5288 (match_operand 2 "const_int_operand" ""))
5291 (label_ref (match_operand 0 ""))))]
5292 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5295 mips_output_conditional_branch (insn, operands,
5296 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5297 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5299 [(set_attr "type" "branch")
5300 (set_attr "branch_likely" "no")])
5303 ;; ....................
5305 ;; SETTING A REGISTER FROM A COMPARISON
5307 ;; ....................
5309 ;; Destination is always set in SI mode.
5311 (define_expand "cstore<mode>4"
5312 [(set (match_operand:SI 0 "register_operand")
5313 (match_operator:SI 1 "mips_cstore_operator"
5314 [(match_operand:GPR 2 "register_operand")
5315 (match_operand:GPR 3 "nonmemory_operand")]))]
5318 mips_expand_scc (operands);
5322 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5323 [(set (match_operand:GPR2 0 "register_operand" "=d")
5324 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5326 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5328 [(set_attr "type" "slt")
5329 (set_attr "mode" "<GPR:MODE>")])
5331 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5332 [(set (match_operand:GPR2 0 "register_operand" "=t")
5333 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5335 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5337 [(set_attr "type" "slt")
5338 (set_attr "mode" "<GPR:MODE>")])
5340 ;; Generate sltiu unless using seq results in better code.
5341 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5342 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5343 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5344 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5350 [(set_attr "type" "slt")
5351 (set_attr "mode" "<GPR:MODE>")])
5353 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5354 [(set (match_operand:GPR2 0 "register_operand" "=d")
5355 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5357 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5359 [(set_attr "type" "slt")
5360 (set_attr "mode" "<GPR:MODE>")])
5362 ;; Generate sltu unless using sne results in better code.
5363 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5364 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5365 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5366 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5372 [(set_attr "type" "slt")
5373 (set_attr "mode" "<GPR:MODE>")])
5375 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5376 [(set (match_operand:GPR2 0 "register_operand" "=d")
5377 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5378 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5381 [(set_attr "type" "slt")
5382 (set_attr "mode" "<GPR:MODE>")])
5384 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5385 [(set (match_operand:GPR2 0 "register_operand" "=t")
5386 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5387 (match_operand:GPR 2 "register_operand" "d")))]
5390 [(set_attr "type" "slt")
5391 (set_attr "mode" "<GPR:MODE>")])
5393 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5394 [(set (match_operand:GPR2 0 "register_operand" "=d")
5395 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5399 [(set_attr "type" "slt")
5400 (set_attr "mode" "<GPR:MODE>")])
5402 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5403 [(set (match_operand:GPR2 0 "register_operand" "=d")
5404 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5405 (match_operand:GPR 2 "arith_operand" "dI")))]
5408 [(set_attr "type" "slt")
5409 (set_attr "mode" "<GPR:MODE>")])
5411 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5412 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5413 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5414 (match_operand:GPR 2 "arith_operand" "d,I")))]
5417 [(set_attr "type" "slt")
5418 (set_attr "mode" "<GPR:MODE>")
5419 (set_attr_alternative "length"
5421 (if_then_else (match_operand 2 "m16_uimm8_1")
5425 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5426 [(set (match_operand:GPR2 0 "register_operand" "=d")
5427 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5428 (match_operand:GPR 2 "sle_operand" "")))]
5431 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5432 return "slt<u>\t%0,%1,%2";
5434 [(set_attr "type" "slt")
5435 (set_attr "mode" "<GPR:MODE>")])
5437 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5438 [(set (match_operand:GPR2 0 "register_operand" "=t")
5439 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5440 (match_operand:GPR 2 "sle_operand" "")))]
5443 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5444 return "slt<u>\t%1,%2";
5446 [(set_attr "type" "slt")
5447 (set_attr "mode" "<GPR:MODE>")
5448 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5453 ;; ....................
5455 ;; FLOATING POINT COMPARISONS
5457 ;; ....................
5459 (define_insn "s<code>_<mode>"
5460 [(set (match_operand:CC 0 "register_operand" "=z")
5461 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5462 (match_operand:SCALARF 2 "register_operand" "f")))]
5464 "c.<fcond>.<fmt>\t%Z0%1,%2"
5465 [(set_attr "type" "fcmp")
5466 (set_attr "mode" "FPSW")])
5468 (define_insn "s<code>_<mode>"
5469 [(set (match_operand:CC 0 "register_operand" "=z")
5470 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5471 (match_operand:SCALARF 2 "register_operand" "f")))]
5473 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5474 [(set_attr "type" "fcmp")
5475 (set_attr "mode" "FPSW")])
5478 ;; ....................
5480 ;; UNCONDITIONAL BRANCHES
5482 ;; ....................
5484 ;; Unconditional branches.
5486 (define_expand "jump"
5488 (label_ref (match_operand 0)))])
5490 (define_insn "*jump_absolute"
5492 (label_ref (match_operand 0)))]
5493 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
5494 { return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); }
5495 [(set_attr "type" "jump")])
5497 (define_insn "*jump_pic"
5499 (label_ref (match_operand 0)))]
5500 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
5502 if (get_attr_length (insn) <= 8)
5503 return "%*b\t%l0%/";
5506 mips_output_load_label (operands[0]);
5507 return "%*jr\t%@%/%]";
5510 [(set_attr "type" "branch")])
5512 ;; We need a different insn for the mips16, because a mips16 branch
5513 ;; does not have a delay slot.
5515 (define_insn "*jump_mips16"
5517 (label_ref (match_operand 0 "" "")))]
5520 [(set_attr "type" "branch")])
5522 (define_expand "indirect_jump"
5523 [(set (pc) (match_operand 0 "register_operand"))]
5526 operands[0] = force_reg (Pmode, operands[0]);
5527 if (Pmode == SImode)
5528 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5530 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5534 (define_insn "indirect_jump<mode>"
5535 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5538 [(set_attr "type" "jump")
5539 (set_attr "mode" "none")])
5541 (define_expand "tablejump"
5543 (match_operand 0 "register_operand"))
5544 (use (label_ref (match_operand 1 "")))]
5547 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5548 operands[0] = expand_binop (Pmode, add_optab,
5549 convert_to_mode (Pmode, operands[0], false),
5550 gen_rtx_LABEL_REF (Pmode, operands[1]),
5552 else if (TARGET_GPWORD)
5553 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5554 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5555 else if (TARGET_RTP_PIC)
5557 /* When generating RTP PIC, we use case table entries that are relative
5558 to the start of the function. Add the function's address to the
5560 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5561 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5562 start, 0, 0, OPTAB_WIDEN);
5565 if (Pmode == SImode)
5566 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5568 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5572 (define_insn "tablejump<mode>"
5574 (match_operand:P 0 "register_operand" "d"))
5575 (use (label_ref (match_operand 1 "" "")))]
5578 [(set_attr "type" "jump")
5579 (set_attr "mode" "none")])
5581 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5582 ;; While it is possible to either pull it off the stack (in the
5583 ;; o32 case) or recalculate it given t9 and our target label,
5584 ;; it takes 3 or 4 insns to do so.
5586 (define_expand "builtin_setjmp_setup"
5587 [(use (match_operand 0 "register_operand"))]
5592 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5593 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5597 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5598 ;; that older code did recalculate the gp from $25. Continue to jump through
5599 ;; $25 for compatibility (we lose nothing by doing so).
5601 (define_expand "builtin_longjmp"
5602 [(use (match_operand 0 "register_operand"))]
5605 /* The elements of the buffer are, in order: */
5606 int W = GET_MODE_SIZE (Pmode);
5607 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5608 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5609 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5610 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5611 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5612 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5613 The target is bound to be using $28 as the global pointer
5614 but the current function might not be. */
5615 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5617 /* This bit is similar to expand_builtin_longjmp except that it
5618 restores $gp as well. */
5619 mips_emit_move (hard_frame_pointer_rtx, fp);
5620 mips_emit_move (pv, lab);
5621 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5622 mips_emit_move (gp, gpv);
5623 emit_use (hard_frame_pointer_rtx);
5624 emit_use (stack_pointer_rtx);
5626 emit_indirect_jump (pv);
5631 ;; ....................
5633 ;; Function prologue/epilogue
5635 ;; ....................
5638 (define_expand "prologue"
5642 mips_expand_prologue ();
5646 ;; Block any insns from being moved before this point, since the
5647 ;; profiling call to mcount can use various registers that aren't
5648 ;; saved or used to pass arguments.
5650 (define_insn "blockage"
5651 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5654 [(set_attr "type" "ghost")
5655 (set_attr "mode" "none")])
5657 (define_expand "epilogue"
5661 mips_expand_epilogue (false);
5665 (define_expand "sibcall_epilogue"
5669 mips_expand_epilogue (true);
5673 ;; Trivial return. Make it look like a normal return insn as that
5674 ;; allows jump optimizations to work better.
5676 (define_expand "return"
5678 "mips_can_use_return_insn ()"
5679 { mips_expand_before_return (); })
5681 (define_insn "*return"
5683 "mips_can_use_return_insn ()"
5685 [(set_attr "type" "jump")
5686 (set_attr "mode" "none")])
5690 (define_insn "return_internal"
5692 (use (match_operand 0 "pmode_register_operand" ""))]
5695 [(set_attr "type" "jump")
5696 (set_attr "mode" "none")])
5698 ;; Exception return.
5699 (define_insn "mips_eret"
5701 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
5704 [(set_attr "type" "trap")
5705 (set_attr "mode" "none")])
5707 ;; Debug exception return.
5708 (define_insn "mips_deret"
5710 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
5713 [(set_attr "type" "trap")
5714 (set_attr "mode" "none")])
5716 ;; Disable interrupts.
5717 (define_insn "mips_di"
5718 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
5721 [(set_attr "type" "trap")
5722 (set_attr "mode" "none")])
5724 ;; Execution hazard barrier.
5725 (define_insn "mips_ehb"
5726 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
5729 [(set_attr "type" "trap")
5730 (set_attr "mode" "none")])
5732 ;; Read GPR from previous shadow register set.
5733 (define_insn "mips_rdpgpr"
5734 [(set (match_operand:SI 0 "register_operand" "=d")
5735 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
5739 [(set_attr "type" "move")
5740 (set_attr "mode" "SI")])
5742 ;; Move involving COP0 registers.
5743 (define_insn "cop0_move"
5744 [(set (match_operand:SI 0 "register_operand" "=B,d")
5745 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
5748 { return mips_output_move (operands[0], operands[1]); }
5749 [(set_attr "type" "mtc,mfc")
5750 (set_attr "mode" "SI")])
5752 ;; This is used in compiling the unwind routines.
5753 (define_expand "eh_return"
5754 [(use (match_operand 0 "general_operand"))]
5757 if (GET_MODE (operands[0]) != word_mode)
5758 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5760 emit_insn (gen_eh_set_lr_di (operands[0]));
5762 emit_insn (gen_eh_set_lr_si (operands[0]));
5766 ;; Clobber the return address on the stack. We can't expand this
5767 ;; until we know where it will be put in the stack frame.
5769 (define_insn "eh_set_lr_si"
5770 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5771 (clobber (match_scratch:SI 1 "=&d"))]
5775 (define_insn "eh_set_lr_di"
5776 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5777 (clobber (match_scratch:DI 1 "=&d"))]
5782 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5783 (clobber (match_scratch 1))]
5787 mips_set_return_address (operands[0], operands[1]);
5791 (define_expand "exception_receiver"
5795 /* See the comment above load_call<mode> for details. */
5796 emit_insn (gen_set_got_version ());
5798 /* If we have a call-clobbered $gp, restore it from its save slot. */
5799 if (HAVE_restore_gp)
5800 emit_insn (gen_restore_gp ());
5804 (define_expand "nonlocal_goto_receiver"
5808 /* See the comment above load_call<mode> for details. */
5809 emit_insn (gen_set_got_version ());
5813 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5814 ;; volatile until all uses of $28 are exposed.
5815 (define_insn_and_split "restore_gp"
5817 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
5818 (clobber (match_scratch:SI 0 "=&d"))]
5819 "TARGET_CALL_CLOBBERED_GP"
5821 "&& epilogue_completed"
5824 mips_restore_gp_from_cprestore_slot (operands[0]);
5827 [(set_attr "type" "ghost")])
5829 ;; Move between $gp and its register save slot.
5830 (define_insn_and_split "move_gp<mode>"
5831 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
5832 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
5835 { return mips_must_initialize_gp_p () ? "#" : ""; }
5836 "mips_must_initialize_gp_p ()"
5839 mips_emit_move (operands[0], operands[1]);
5842 [(set_attr "type" "ghost")])
5845 ;; ....................
5849 ;; ....................
5851 ;; Instructions to load a call address from the GOT. The address might
5852 ;; point to a function or to a lazy binding stub. In the latter case,
5853 ;; the stub will use the dynamic linker to resolve the function, which
5854 ;; in turn will change the GOT entry to point to the function's real
5857 ;; This means that every call, even pure and constant ones, can
5858 ;; potentially modify the GOT entry. And once a stub has been called,
5859 ;; we must not call it again.
5861 ;; We represent this restriction using an imaginary, fixed, call-saved
5862 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5863 ;; live throughout the function and to change its value after every
5864 ;; potential call site. This stops any rtx value that uses the register
5865 ;; from being computed before an earlier call. To do this, we:
5867 ;; - Ensure that the register is live on entry to the function,
5868 ;; so that it is never thought to be used uninitalized.
5870 ;; - Ensure that the register is live on exit from the function,
5871 ;; so that it is live throughout.
5873 ;; - Make each call (lazily-bound or not) use the current value
5874 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5875 ;; not moved across call boundaries.
5877 ;; - Add "ghost" definitions of the register to the beginning of
5878 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5879 ;; edges may involve calls that normal paths don't. (E.g. the
5880 ;; unwinding code that handles a non-call exception may change
5881 ;; lazily-bound GOT entries.) We do this by making the
5882 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5883 ;; a set_got_version instruction.
5885 ;; - After each call (lazily-bound or not), use a "ghost"
5886 ;; update_got_version instruction to change the register's value.
5887 ;; This instruction mimics the _possible_ effect of the dynamic
5888 ;; resolver during the call and it remains live even if the call
5889 ;; itself becomes dead.
5891 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5892 ;; The register is therefore not a valid register_operand
5893 ;; and cannot be moved to or from other registers.
5895 (define_insn "load_call<mode>"
5896 [(set (match_operand:P 0 "register_operand" "=d")
5897 (unspec:P [(match_operand:P 1 "register_operand" "d")
5898 (match_operand:P 2 "immediate_operand" "")
5899 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5901 "<load>\t%0,%R2(%1)"
5902 [(set_attr "got" "load")
5903 (set_attr "mode" "<MODE>")])
5905 (define_insn "set_got_version"
5906 [(set (reg:SI GOT_VERSION_REGNUM)
5907 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5910 [(set_attr "type" "ghost")])
5912 (define_insn "update_got_version"
5913 [(set (reg:SI GOT_VERSION_REGNUM)
5914 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5917 [(set_attr "type" "ghost")])
5919 ;; Sibling calls. All these patterns use jump instructions.
5921 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5922 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5923 ;; is defined in terms of call_insn_operand, the same is true of the
5926 ;; When we use an indirect jump, we need a register that will be
5927 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5928 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5929 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5932 (define_expand "sibcall"
5933 [(parallel [(call (match_operand 0 "")
5934 (match_operand 1 ""))
5935 (use (match_operand 2 "")) ;; next_arg_reg
5936 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5939 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
5940 operands[1], operands[2], false);
5944 (define_insn "sibcall_internal"
5945 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5946 (match_operand 1 "" ""))]
5947 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5948 { return MIPS_CALL ("j", operands, 0, 1); }
5949 [(set_attr "type" "call")])
5951 (define_expand "sibcall_value"
5952 [(parallel [(set (match_operand 0 "")
5953 (call (match_operand 1 "")
5954 (match_operand 2 "")))
5955 (use (match_operand 3 ""))])] ;; next_arg_reg
5958 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
5959 operands[2], operands[3], false);
5963 (define_insn "sibcall_value_internal"
5964 [(set (match_operand 0 "register_operand" "")
5965 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5966 (match_operand 2 "" "")))]
5967 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5968 { return MIPS_CALL ("j", operands, 1, 2); }
5969 [(set_attr "type" "call")])
5971 (define_insn "sibcall_value_multiple_internal"
5972 [(set (match_operand 0 "register_operand" "")
5973 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5974 (match_operand 2 "" "")))
5975 (set (match_operand 3 "register_operand" "")
5976 (call (mem:SI (match_dup 1))
5978 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5979 { return MIPS_CALL ("j", operands, 1, 2); }
5980 [(set_attr "type" "call")])
5982 (define_expand "call"
5983 [(parallel [(call (match_operand 0 "")
5984 (match_operand 1 ""))
5985 (use (match_operand 2 "")) ;; next_arg_reg
5986 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5989 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
5990 operands[1], operands[2], false);
5994 ;; This instruction directly corresponds to an assembly-language "jal".
5995 ;; There are four cases:
5998 ;; Both symbolic and register destinations are OK. The pattern
5999 ;; always expands to a single mips instruction.
6001 ;; - -mabicalls/-mno-explicit-relocs:
6002 ;; Again, both symbolic and register destinations are OK.
6003 ;; The call is treated as a multi-instruction black box.
6005 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6006 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6009 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6010 ;; Only "jal $25" is allowed. The call is actually two instructions:
6011 ;; "jalr $25" followed by an insn to reload $gp.
6013 ;; In the last case, we can generate the individual instructions with
6014 ;; a define_split. There are several things to be wary of:
6016 ;; - We can't expose the load of $gp before reload. If we did,
6017 ;; it might get removed as dead, but reload can introduce new
6018 ;; uses of $gp by rematerializing constants.
6020 ;; - We shouldn't restore $gp after calls that never return.
6021 ;; It isn't valid to insert instructions between a noreturn
6022 ;; call and the following barrier.
6024 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6025 ;; instruction preserves $gp and so have no effect on its liveness.
6026 ;; But once we generate the separate insns, it becomes obvious that
6027 ;; $gp is not live on entry to the call.
6029 ;; ??? The operands[2] = insn check is a hack to make the original insn
6030 ;; available to the splitter.
6031 (define_insn_and_split "call_internal"
6032 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6033 (match_operand 1 "" ""))
6034 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6036 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6037 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
6040 mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
6043 [(set_attr "jal" "indirect,direct")])
6045 (define_insn "call_split"
6046 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
6047 (match_operand 1 "" ""))
6048 (clobber (reg:SI RETURN_ADDR_REGNUM))
6049 (clobber (reg:SI 28))]
6050 "TARGET_SPLIT_CALLS"
6051 { return MIPS_CALL ("jal", operands, 0, 1); }
6052 [(set_attr "type" "call")])
6054 ;; A pattern for calls that must be made directly. It is used for
6055 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6056 ;; stub; the linker relies on the call relocation type to detect when
6057 ;; such redirection is needed.
6058 (define_insn_and_split "call_internal_direct"
6059 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6062 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6064 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6065 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
6068 mips_split_call (operands[2],
6069 gen_call_direct_split (operands[0], operands[1]));
6072 [(set_attr "type" "call")])
6074 (define_insn "call_direct_split"
6075 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6078 (clobber (reg:SI RETURN_ADDR_REGNUM))
6079 (clobber (reg:SI 28))]
6080 "TARGET_SPLIT_CALLS"
6081 { return MIPS_CALL ("jal", operands, 0, -1); }
6082 [(set_attr "type" "call")])
6084 (define_expand "call_value"
6085 [(parallel [(set (match_operand 0 "")
6086 (call (match_operand 1 "")
6087 (match_operand 2 "")))
6088 (use (match_operand 3 ""))])] ;; next_arg_reg
6091 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6092 operands[2], operands[3], false);
6096 ;; See comment for call_internal.
6097 (define_insn_and_split "call_value_internal"
6098 [(set (match_operand 0 "register_operand" "")
6099 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6100 (match_operand 2 "" "")))
6101 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6103 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6104 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6107 mips_split_call (operands[3],
6108 gen_call_value_split (operands[0], operands[1],
6112 [(set_attr "jal" "indirect,direct")])
6114 (define_insn "call_value_split"
6115 [(set (match_operand 0 "register_operand" "")
6116 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6117 (match_operand 2 "" "")))
6118 (clobber (reg:SI RETURN_ADDR_REGNUM))
6119 (clobber (reg:SI 28))]
6120 "TARGET_SPLIT_CALLS"
6121 { return MIPS_CALL ("jal", operands, 1, 2); }
6122 [(set_attr "type" "call")])
6124 ;; See call_internal_direct.
6125 (define_insn_and_split "call_value_internal_direct"
6126 [(set (match_operand 0 "register_operand")
6127 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6130 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6132 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6133 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6136 mips_split_call (operands[3],
6137 gen_call_value_direct_split (operands[0], operands[1],
6141 [(set_attr "type" "call")])
6143 (define_insn "call_value_direct_split"
6144 [(set (match_operand 0 "register_operand")
6145 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6148 (clobber (reg:SI RETURN_ADDR_REGNUM))
6149 (clobber (reg:SI 28))]
6150 "TARGET_SPLIT_CALLS"
6151 { return MIPS_CALL ("jal", operands, 1, -1); }
6152 [(set_attr "type" "call")])
6154 ;; See comment for call_internal.
6155 (define_insn_and_split "call_value_multiple_internal"
6156 [(set (match_operand 0 "register_operand" "")
6157 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6158 (match_operand 2 "" "")))
6159 (set (match_operand 3 "register_operand" "")
6160 (call (mem:SI (match_dup 1))
6162 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6164 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6165 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
6168 mips_split_call (operands[4],
6169 gen_call_value_multiple_split (operands[0], operands[1],
6170 operands[2], operands[3]));
6173 [(set_attr "jal" "indirect,direct")])
6175 (define_insn "call_value_multiple_split"
6176 [(set (match_operand 0 "register_operand" "")
6177 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6178 (match_operand 2 "" "")))
6179 (set (match_operand 3 "register_operand" "")
6180 (call (mem:SI (match_dup 1))
6182 (clobber (reg:SI RETURN_ADDR_REGNUM))
6183 (clobber (reg:SI 28))]
6184 "TARGET_SPLIT_CALLS"
6185 { return MIPS_CALL ("jal", operands, 1, 2); }
6186 [(set_attr "type" "call")])
6188 ;; Call subroutine returning any type.
6190 (define_expand "untyped_call"
6191 [(parallel [(call (match_operand 0 "")
6193 (match_operand 1 "")
6194 (match_operand 2 "")])]
6199 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6201 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6203 rtx set = XVECEXP (operands[2], 0, i);
6204 mips_emit_move (SET_DEST (set), SET_SRC (set));
6207 emit_insn (gen_blockage ());
6212 ;; ....................
6216 ;; ....................
6220 (define_insn "prefetch"
6221 [(prefetch (match_operand:QI 0 "address_operand" "p")
6222 (match_operand 1 "const_int_operand" "n")
6223 (match_operand 2 "const_int_operand" "n"))]
6224 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6226 if (TARGET_LOONGSON_2EF)
6227 /* Loongson 2[ef] use load to $0 to perform prefetching. */
6228 return "ld\t$0,%a0";
6229 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6230 return "pref\t%1,%a0";
6232 [(set_attr "type" "prefetch")])
6234 (define_insn "*prefetch_indexed_<mode>"
6235 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6236 (match_operand:P 1 "register_operand" "d"))
6237 (match_operand 2 "const_int_operand" "n")
6238 (match_operand 3 "const_int_operand" "n"))]
6239 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6241 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6242 return "prefx\t%2,%1(%0)";
6244 [(set_attr "type" "prefetchx")])
6250 [(set_attr "type" "nop")
6251 (set_attr "mode" "none")])
6253 ;; Like nop, but commented out when outside a .set noreorder block.
6254 (define_insn "hazard_nop"
6258 if (mips_noreorder.nesting_level > 0)
6263 [(set_attr "type" "nop")])
6265 ;; MIPS4 Conditional move instructions.
6267 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6268 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6270 (match_operator:MOVECC 4 "equality_operator"
6271 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6273 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6274 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6279 [(set_attr "type" "condmove")
6280 (set_attr "mode" "<GPR:MODE>")])
6282 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6283 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6284 (if_then_else:SCALARF
6285 (match_operator:MOVECC 4 "equality_operator"
6286 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6288 (match_operand:SCALARF 2 "register_operand" "f,0")
6289 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6290 "ISA_HAS_FP_CONDMOVE"
6292 mov%T4.<fmt>\t%0,%2,%1
6293 mov%t4.<fmt>\t%0,%3,%1"
6294 [(set_attr "type" "condmove")
6295 (set_attr "mode" "<SCALARF:MODE>")])
6297 ;; These are the main define_expand's used to make conditional moves.
6299 (define_expand "mov<mode>cc"
6300 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6301 (set (match_operand:GPR 0 "register_operand")
6302 (if_then_else:GPR (match_dup 5)
6303 (match_operand:GPR 2 "reg_or_0_operand")
6304 (match_operand:GPR 3 "reg_or_0_operand")))]
6307 mips_expand_conditional_move (operands);
6311 (define_expand "mov<mode>cc"
6312 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6313 (set (match_operand:SCALARF 0 "register_operand")
6314 (if_then_else:SCALARF (match_dup 5)
6315 (match_operand:SCALARF 2 "register_operand")
6316 (match_operand:SCALARF 3 "register_operand")))]
6317 "ISA_HAS_FP_CONDMOVE"
6319 mips_expand_conditional_move (operands);
6324 ;; ....................
6326 ;; mips16 inline constant tables
6328 ;; ....................
6331 (define_insn "consttable_int"
6332 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6333 (match_operand 1 "const_int_operand" "")]
6334 UNSPEC_CONSTTABLE_INT)]
6337 assemble_integer (operands[0], INTVAL (operands[1]),
6338 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6341 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6343 (define_insn "consttable_float"
6344 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6345 UNSPEC_CONSTTABLE_FLOAT)]
6350 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6351 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6352 assemble_real (d, GET_MODE (operands[0]),
6353 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6356 [(set (attr "length")
6357 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6359 (define_insn "align"
6360 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6363 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6366 [(match_operand 0 "small_data_pattern")]
6369 { operands[0] = mips_rewrite_small_data (operands[0]); })
6372 ;; ....................
6374 ;; MIPS16e Save/Restore
6376 ;; ....................
6379 (define_insn "*mips16e_save_restore"
6380 [(match_parallel 0 ""
6381 [(set (match_operand:SI 1 "register_operand")
6382 (plus:SI (match_dup 1)
6383 (match_operand:SI 2 "const_int_operand")))])]
6384 "operands[1] == stack_pointer_rtx
6385 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6386 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6387 [(set_attr "type" "arith")
6388 (set_attr "extended_mips16" "yes")])
6390 ;; Thread-Local Storage
6392 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6393 ;; MIPS architecture defines this register, and no current
6394 ;; implementation provides it; instead, any OS which supports TLS is
6395 ;; expected to trap and emulate this instruction. rdhwr is part of the
6396 ;; MIPS 32r2 specification, but we use it on any architecture because
6397 ;; we expect it to be emulated. Use .set to force the assembler to
6400 ;; We do not use a constraint to force the destination to be $3
6401 ;; because $3 can appear explicitly as a function return value.
6402 ;; If we leave the use of $3 implicit in the constraints until
6403 ;; reload, we may end up making a $3 return value live across
6404 ;; the instruction, leading to a spill failure when reloading it.
6405 (define_insn_and_split "tls_get_tp_<mode>"
6406 [(set (match_operand:P 0 "register_operand" "=d")
6407 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6408 (clobber (reg:P TLS_GET_TP_REGNUM))]
6409 "HAVE_AS_TLS && !TARGET_MIPS16"
6411 "&& reload_completed"
6412 [(set (reg:P TLS_GET_TP_REGNUM)
6413 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6414 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6416 [(set_attr "type" "unknown")
6417 ; Since rdhwr always generates a trap for now, putting it in a delay
6418 ; slot would make the kernel's emulation of it much slower.
6419 (set_attr "can_delay" "no")
6420 (set_attr "mode" "<MODE>")
6421 (set_attr "length" "8")])
6423 (define_insn "*tls_get_tp_<mode>_split"
6424 [(set (reg:P TLS_GET_TP_REGNUM)
6425 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6426 "HAVE_AS_TLS && !TARGET_MIPS16"
6427 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6428 [(set_attr "type" "unknown")
6429 ; See tls_get_tp_<mode>
6430 (set_attr "can_delay" "no")
6431 (set_attr "mode" "<MODE>")])
6433 ;; Synchronization instructions.
6437 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6439 (include "mips-ps-3d.md")
6441 ; The MIPS DSP Instructions.
6443 (include "mips-dsp.md")
6445 ; The MIPS DSP REV 2 Instructions.
6447 (include "mips-dspr2.md")
6449 ; MIPS fixed-point instructions.
6450 (include "mips-fixed.md")
6452 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6453 (include "loongson.md")
6455 (define_c_enum "unspec" [
6456 UNSPEC_ADDRESS_FIRST