1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_arch; /* which cpu to codegen for */
137 extern enum processor_type mips_tune; /* which cpu to schedule for */
138 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
139 extern int mips_isa; /* architectural level */
140 extern int mips16; /* whether generating mips16 code */
141 extern int mips16_hard_float; /* mips16 without -msoft-float */
142 extern int mips_entry; /* generate entry/exit for mips16 */
143 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
144 extern const char *mips_arch_string; /* for -march=<xxx> */
145 extern const char *mips_tune_string; /* for -mtune=<xxx> */
146 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
147 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
148 extern const char *mips_entry_string; /* for -mentry */
149 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
150 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
151 extern int mips_split_addresses; /* perform high/lo_sum support */
152 extern int dslots_load_total; /* total # load related delay slots */
153 extern int dslots_load_filled; /* # filled load delay slots */
154 extern int dslots_jump_total; /* total # jump related delay slots */
155 extern int dslots_jump_filled; /* # filled jump delay slots */
156 extern int dslots_number_nops; /* # of nops needed by previous insn */
157 extern int num_refs[3]; /* # 1/2/3 word references */
158 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
159 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
160 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
161 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
162 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
163 extern int mips_string_length; /* length of strings for mips16 */
164 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
166 /* Functions to change what output section we are using. */
167 extern void rdata_section PARAMS ((void));
168 extern void sdata_section PARAMS ((void));
169 extern void sbss_section PARAMS ((void));
171 /* Stubs for half-pic support if not OSF/1 reference platform. */
174 #define HALF_PIC_P() 0
175 #define HALF_PIC_NUMBER_PTRS 0
176 #define HALF_PIC_NUMBER_REFS 0
177 #define HALF_PIC_ENCODE(DECL)
178 #define HALF_PIC_DECLARE(NAME)
179 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
180 #define HALF_PIC_ADDRESS_P(X) 0
181 #define HALF_PIC_PTR(X) X
182 #define HALF_PIC_FINISH(STREAM)
185 /* Macros to silence warnings about numbers being signed in traditional
186 C and unsigned in ISO C when compiled on 32-bit hosts. */
188 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
189 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
190 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
193 /* Run-time compilation parameters selecting different hardware subsets. */
195 /* Macros used in the machine description to test the flags. */
197 /* Bits for real switches */
198 #define MASK_INT64 0x00000001 /* ints are 64 bits */
199 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
200 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
201 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
202 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
203 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
204 #define MASK_STATS 0x00000040 /* print statistics to stderr */
205 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
206 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
207 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
208 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
209 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
210 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
211 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
212 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
213 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
214 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
215 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
216 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
217 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
218 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
219 #define MASK_NO_CHECK_ZERO_DIV \
220 0x00200000 /* divide by zero checking */
221 #define MASK_CHECK_RANGE_DIV \
222 0x00400000 /* divide result range checking */
223 #define MASK_UNINIT_CONST_IN_RODATA \
224 0x00800000 /* Store uninitialized
227 /* Debug switches, not documented */
228 #define MASK_DEBUG 0 /* unused */
229 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
230 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
231 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
232 #define MASK_DEBUG_D 0 /* don't do define_split's */
233 #define MASK_DEBUG_E 0 /* function_arg debug */
234 #define MASK_DEBUG_F 0 /* ??? */
235 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
236 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
237 #define MASK_DEBUG_I 0 /* unused */
239 /* Dummy switches used only in specs */
240 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
242 /* r4000 64 bit sizes */
243 #define TARGET_INT64 (target_flags & MASK_INT64)
244 #define TARGET_LONG64 (target_flags & MASK_LONG64)
245 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
246 #define TARGET_64BIT (target_flags & MASK_64BIT)
248 /* Mips vs. GNU linker */
249 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
251 /* Mips vs. GNU assembler */
252 #define TARGET_GAS (target_flags & MASK_GAS)
253 #define TARGET_MIPS_AS (!TARGET_GAS)
256 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
257 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
258 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
259 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
260 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
261 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
262 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
263 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
264 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
265 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
267 /* Reg. Naming in .s ($21 vs. $a0) */
268 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
270 /* Optimize for Sdata/Sbss */
271 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
273 /* print program statistics */
274 #define TARGET_STATS (target_flags & MASK_STATS)
276 /* call memcpy instead of inline code */
277 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
279 /* .abicalls, etc from Pyramid V.4 */
280 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
282 /* OSF pic references to externs */
283 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
285 /* software floating point */
286 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
287 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
289 /* always call through a register */
290 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
292 /* generate embedded PIC code;
294 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
296 /* for embedded systems, optimize for
297 reduced RAM space instead of for
299 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
301 /* always store uninitialized const
302 variables in rodata, requires
303 TARGET_EMBEDDED_DATA. */
304 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
306 /* generate big endian code. */
307 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
309 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
310 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
312 #define TARGET_MAD (target_flags & MASK_MAD)
314 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
316 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
317 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
319 /* This is true if we must enable the assembly language file switching
322 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
324 /* We must disable the function end stabs when doing the file switching trick,
325 because the Lscope stabs end up in the wrong place, making it impossible
326 to debug the resulting code. */
327 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
329 /* Generate mips16 code */
330 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
332 /* Architecture target defines. */
333 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
334 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
335 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
336 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
338 /* Scheduling target defines. */
339 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
340 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
341 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
342 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
343 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
345 /* Macro to define tables used to set the flags.
346 This is a list in braces of pairs in braces,
347 each pair being { "NAME", VALUE }
348 where VALUE is the bits to set or minus the bits to clear.
349 An empty string NAME is used to identify the default VALUE. */
351 #define TARGET_SWITCHES \
354 N_("No default crt0.o") }, \
355 {"int64", MASK_INT64 | MASK_LONG64, \
356 N_("Use 64-bit int type")}, \
357 {"long64", MASK_LONG64, \
358 N_("Use 64-bit long type")}, \
359 {"long32", -(MASK_LONG64 | MASK_INT64), \
360 N_("Use 32-bit long type")}, \
361 {"split-addresses", MASK_SPLIT_ADDR, \
362 N_("Optimize lui/addiu address loads")}, \
363 {"no-split-addresses", -MASK_SPLIT_ADDR, \
364 N_("Don't optimize lui/addiu address loads")}, \
365 {"mips-as", -MASK_GAS, \
366 N_("Use MIPS as")}, \
369 {"rnames", MASK_NAME_REGS, \
370 N_("Use symbolic register names")}, \
371 {"no-rnames", -MASK_NAME_REGS, \
372 N_("Don't use symbolic register names")}, \
373 {"gpOPT", MASK_GPOPT, \
374 N_("Use GP relative sdata/sbss sections")}, \
375 {"gpopt", MASK_GPOPT, \
376 N_("Use GP relative sdata/sbss sections")}, \
377 {"no-gpOPT", -MASK_GPOPT, \
378 N_("Don't use GP relative sdata/sbss sections")}, \
379 {"no-gpopt", -MASK_GPOPT, \
380 N_("Don't use GP relative sdata/sbss sections")}, \
381 {"stats", MASK_STATS, \
382 N_("Output compiler statistics")}, \
383 {"no-stats", -MASK_STATS, \
384 N_("Don't output compiler statistics")}, \
385 {"memcpy", MASK_MEMCPY, \
386 N_("Don't optimize block moves")}, \
387 {"no-memcpy", -MASK_MEMCPY, \
388 N_("Optimize block moves")}, \
389 {"mips-tfile", MASK_MIPS_TFILE, \
390 N_("Use mips-tfile asm postpass")}, \
391 {"no-mips-tfile", -MASK_MIPS_TFILE, \
392 N_("Don't use mips-tfile asm postpass")}, \
393 {"soft-float", MASK_SOFT_FLOAT, \
394 N_("Use software floating point")}, \
395 {"hard-float", -MASK_SOFT_FLOAT, \
396 N_("Use hardware floating point")}, \
397 {"fp64", MASK_FLOAT64, \
398 N_("Use 64-bit FP registers")}, \
399 {"fp32", -MASK_FLOAT64, \
400 N_("Use 32-bit FP registers")}, \
401 {"gp64", MASK_64BIT, \
402 N_("Use 64-bit general registers")}, \
403 {"gp32", -MASK_64BIT, \
404 N_("Use 32-bit general registers")}, \
405 {"abicalls", MASK_ABICALLS, \
406 N_("Use Irix PIC")}, \
407 {"no-abicalls", -MASK_ABICALLS, \
408 N_("Don't use Irix PIC")}, \
409 {"half-pic", MASK_HALF_PIC, \
410 N_("Use OSF PIC")}, \
411 {"no-half-pic", -MASK_HALF_PIC, \
412 N_("Don't use OSF PIC")}, \
413 {"long-calls", MASK_LONG_CALLS, \
414 N_("Use indirect calls")}, \
415 {"no-long-calls", -MASK_LONG_CALLS, \
416 N_("Don't use indirect calls")}, \
417 {"embedded-pic", MASK_EMBEDDED_PIC, \
418 N_("Use embedded PIC")}, \
419 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
420 N_("Don't use embedded PIC")}, \
421 {"embedded-data", MASK_EMBEDDED_DATA, \
422 N_("Use ROM instead of RAM")}, \
423 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
424 N_("Don't use ROM instead of RAM")}, \
425 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
426 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
427 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
428 N_("Don't put uninitialized constants in ROM")}, \
429 {"eb", MASK_BIG_ENDIAN, \
430 N_("Use big-endian byte order")}, \
431 {"el", -MASK_BIG_ENDIAN, \
432 N_("Use little-endian byte order")}, \
433 {"single-float", MASK_SINGLE_FLOAT, \
434 N_("Use single (32-bit) FP only")}, \
435 {"double-float", -MASK_SINGLE_FLOAT, \
436 N_("Don't use single (32-bit) FP only")}, \
438 N_("Use multiply accumulate")}, \
439 {"no-mad", -MASK_MAD, \
440 N_("Don't use multiply accumulate")}, \
441 {"fix4300", MASK_4300_MUL_FIX, \
442 N_("Work around early 4300 hardware bug")}, \
443 {"no-fix4300", -MASK_4300_MUL_FIX, \
444 N_("Don't work around early 4300 hardware bug")}, \
446 N_("Optimize for 3900")}, \
448 N_("Optimize for 4650")}, \
449 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
450 N_("Trap on integer divide by zero")}, \
451 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
452 N_("Don't trap on integer divide by zero")}, \
453 {"check-range-division",MASK_CHECK_RANGE_DIV, \
454 N_("Trap on integer divide overflow")}, \
455 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
456 N_("Don't trap on integer divide overflow")}, \
457 {"debug", MASK_DEBUG, \
459 {"debuga", MASK_DEBUG_A, \
461 {"debugb", MASK_DEBUG_B, \
463 {"debugc", MASK_DEBUG_C, \
465 {"debugd", MASK_DEBUG_D, \
467 {"debuge", MASK_DEBUG_E, \
469 {"debugf", MASK_DEBUG_F, \
471 {"debugg", MASK_DEBUG_G, \
473 {"debugh", MASK_DEBUG_H, \
475 {"debugi", MASK_DEBUG_I, \
477 {"", (TARGET_DEFAULT \
478 | TARGET_CPU_DEFAULT \
479 | TARGET_ENDIAN_DEFAULT), \
483 /* Default target_flags if no switches are specified */
485 #ifndef TARGET_DEFAULT
486 #define TARGET_DEFAULT 0
489 #ifndef TARGET_CPU_DEFAULT
490 #define TARGET_CPU_DEFAULT 0
493 #ifndef TARGET_ENDIAN_DEFAULT
495 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
497 #define TARGET_ENDIAN_DEFAULT 0
501 #ifndef MIPS_ISA_DEFAULT
502 #define MIPS_ISA_DEFAULT 1
507 /* Make this compile time constant for libgcc2 */
509 #define TARGET_64BIT 1
511 #define TARGET_64BIT 0
513 #endif /* IN_LIBGCC2 */
515 #ifndef MULTILIB_ENDIAN_DEFAULT
516 #if TARGET_ENDIAN_DEFAULT == 0
517 #define MULTILIB_ENDIAN_DEFAULT "EL"
519 #define MULTILIB_ENDIAN_DEFAULT "EB"
523 #ifndef MULTILIB_ISA_DEFAULT
524 # if MIPS_ISA_DEFAULT == 1
525 # define MULTILIB_ISA_DEFAULT "mips1"
527 # if MIPS_ISA_DEFAULT == 2
528 # define MULTILIB_ISA_DEFAULT "mips2"
530 # if MIPS_ISA_DEFAULT == 3
531 # define MULTILIB_ISA_DEFAULT "mips3"
533 # if MIPS_ISA_DEFAULT == 4
534 # define MULTILIB_ISA_DEFAULT "mips4"
536 # define MULTILIB_ISA_DEFAULT "mips1"
543 #ifndef MULTILIB_DEFAULTS
544 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
547 /* We must pass -EL to the linker by default for little endian embedded
548 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
549 linker will default to using big-endian output files. The OUTPUT_FORMAT
550 line must be in the linker script, otherwise -EB/-EL will not work. */
553 #if TARGET_ENDIAN_DEFAULT == 0
554 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EL} %{EB}"
556 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EB} %{EL}"
560 /* This macro is similar to `TARGET_SWITCHES' but defines names of
561 command options that have values. Its definition is an
562 initializer with a subgrouping for each command option.
564 Each subgrouping contains a string constant, that defines the
565 fixed part of the option name, and the address of a variable.
566 The variable, type `char *', is set to the variable part of the
567 given option if the fixed part matches. The actual option name
568 is made by appending `-m' to the specified name.
570 Here is an example which defines `-mshort-data-NUMBER'. If the
571 given option is `-mshort-data-512', the variable `m88k_short_data'
572 will be set to the string `"512"'.
574 extern char *m88k_short_data;
575 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
577 #define TARGET_OPTIONS \
579 SUBTARGET_TARGET_OPTIONS \
580 { "cpu=", &mips_cpu_string, \
581 N_("Specify CPU for scheduling purposes")}, \
582 { "tune=", &mips_tune_string, \
583 N_("Specify CPU for scheduling purposes")}, \
584 { "arch=", &mips_arch_string, \
585 N_("Specify CPU for code generation purposes")}, \
586 { "ips", &mips_isa_string, \
587 N_("Specify a Standard MIPS ISA")}, \
588 { "entry", &mips_entry_string, \
589 N_("Use mips16 entry/exit psuedo ops")}, \
590 { "no-mips16", &mips_no_mips16_string, \
591 N_("Don't use MIPS16 instructions")}, \
592 { "explicit-type-size", &mips_explicit_type_size_string, \
596 /* This is meant to be redefined in the host dependent files. */
597 #define SUBTARGET_TARGET_OPTIONS
599 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
601 /* Generate three-operand multiply instructions for both SImode and DImode. */
602 #define GENERATE_MULT3 (TARGET_MIPS3900 \
605 /* Macros to decide whether certain features are available or not,
606 depending on the instruction set architecture level. */
608 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
609 #define HAVE_SQRT_P() (mips_isa != 1)
611 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
612 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
615 /* ISA has branch likely instructions (eg. mips2). */
616 /* Disable branchlikely for tx39 until compare rewrite. They haven't
617 been generated up to this point. */
618 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
619 /* || TARGET_MIPS3900 */)
621 /* ISA has the conditional move instructions introduced in mips4. */
622 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
625 /* ISA has just the integer condition move instructions (movn,movz) */
626 #define ISA_HAS_INT_CONDMOVE 0
630 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
631 branch on CC, and move (both FP and non-FP) on CC. */
632 #define ISA_HAS_8CC (mips_isa == 4 \
636 /* This is a catch all for the other new mips4 instructions: indexed load and
637 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
638 and the FP recip and recip sqrt instructions */
639 #define ISA_HAS_FP4 (mips_isa == 4 \
642 /* ISA has conditional trap instructions. */
643 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
645 /* ISA has nmadd and nmsub instructions. */
646 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
649 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
650 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
651 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
652 target_flags, and -mgp64 sets MASK_64BIT.
654 Setting MASK_64BIT in target_flags will cause gcc to assume that
655 registers are 64 bits wide. int, long and void * will be 32 bit;
656 this may be changed with -mint64 or -mlong64.
658 The gen* programs link code that refers to MASK_64BIT. They don't
659 actually use the information in target_flags; they just refer to
662 /* Switch Recognition by gcc.c. Add -G xx support */
664 #ifdef SWITCH_TAKES_ARG
665 #undef SWITCH_TAKES_ARG
668 #define SWITCH_TAKES_ARG(CHAR) \
669 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
671 /* Sometimes certain combinations of command options do not make sense
672 on a particular target machine. You can define a macro
673 `OVERRIDE_OPTIONS' to take account of this. This macro, if
674 defined, is executed once just after all the command options have
677 On the MIPS, it is used to handle -G. We also use it to set up all
678 of the tables referenced in the other macros. */
680 #define OVERRIDE_OPTIONS override_options ()
682 /* Zero or more C statements that may conditionally modify two
683 variables `fixed_regs' and `call_used_regs' (both of type `char
684 []') after they have been initialized from the two preceding
687 This is necessary in case the fixed or call-clobbered registers
688 depend on target flags.
690 You need not define this macro if it has no work to do.
692 If the usage of an entire class of registers depends on the target
693 flags, you may indicate this to GCC by using this macro to modify
694 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
695 the classes which should not be used by GCC. Also define the macro
696 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
697 letter for a class that shouldn't be used.
699 (However, if this class is not included in `GENERAL_REGS' and all
700 of the insn patterns whose constraints permit this class are
701 controlled by target switches, then GCC will automatically avoid
702 using these registers when the target switches are opposed to
705 #define CONDITIONAL_REGISTER_USAGE \
708 if (!TARGET_HARD_FLOAT) \
712 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
713 fixed_regs[regno] = call_used_regs[regno] = 1; \
714 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
715 fixed_regs[regno] = call_used_regs[regno] = 1; \
717 else if (! ISA_HAS_8CC) \
721 /* We only have a single condition code register. We \
722 implement this by hiding all the condition code registers, \
723 and generating RTL that refers directly to ST_REG_FIRST. */ \
724 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
725 fixed_regs[regno] = call_used_regs[regno] = 1; \
727 /* In mips16 mode, we permit the $t temporary registers to be used \
728 for reload. We prohibit the unused $s registers, since they \
729 are caller saved, and saving them via a mips16 register would \
730 probably waste more time than just reloading the value. */ \
733 fixed_regs[18] = call_used_regs[18] = 1; \
734 fixed_regs[19] = call_used_regs[19] = 1; \
735 fixed_regs[20] = call_used_regs[20] = 1; \
736 fixed_regs[21] = call_used_regs[21] = 1; \
737 fixed_regs[22] = call_used_regs[22] = 1; \
738 fixed_regs[23] = call_used_regs[23] = 1; \
739 fixed_regs[26] = call_used_regs[26] = 1; \
740 fixed_regs[27] = call_used_regs[27] = 1; \
741 fixed_regs[30] = call_used_regs[30] = 1; \
743 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
747 /* This is meant to be redefined in the host dependent files. */
748 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
750 /* Show we can debug even without a frame pointer. */
751 #define CAN_DEBUG_WITHOUT_FP
753 /* Complain about missing specs and predefines that should be defined in each
754 of the target tm files to override the defaults. This is mostly a place-
755 holder until I can get each of the files updated [mm]. */
757 #if defined(OSF_OS) \
758 || defined(DECSTATION) \
759 || defined(SGI_TARGET) \
760 || defined(MIPS_NEWS) \
761 || defined(MIPS_SYSV) \
762 || defined(MIPS_SVR4) \
763 || defined(MIPS_BSD43)
765 #ifndef CPP_PREDEFINES
766 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
770 #error "Define LIB_SPEC in the appropriate tm.h file"
773 #ifndef STARTFILE_SPEC
774 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
778 #error "Define MACHINE_TYPE in the appropriate tm.h file"
782 /* Tell collect what flags to pass to nm. */
784 #define NM_FLAGS "-Bn"
788 /* Names to predefine in the preprocessor for this target machine. */
790 #ifndef CPP_PREDEFINES
791 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
792 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
793 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
796 /* Assembler specs. */
798 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
801 #define MIPS_AS_ASM_SPEC "\
802 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
803 %{pipe: %e-pipe is not supported.} \
804 %{K} %(subtarget_mips_as_asm_spec)"
806 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
807 rather than gas. It may be overridden by subtargets. */
809 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
810 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
813 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
816 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
818 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
819 GAS_ASM_SPEC as the default, depending upon the value of
822 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
825 #define TARGET_ASM_SPEC "\
826 %{mmips-as: %(mips_as_asm_spec)} \
827 %{!mmips-as: %(gas_asm_spec)}"
831 #define TARGET_ASM_SPEC "\
832 %{!mgas: %(mips_as_asm_spec)} \
833 %{mgas: %(gas_asm_spec)}"
837 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
838 to the assembler. It may be overridden by subtargets. */
839 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
840 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
842 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
845 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
846 the assembler. It may be overridden by subtargets. */
847 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
848 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
849 %{g} %{g0} %{g1} %{g2} %{g3} \
850 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
851 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
852 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
853 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
856 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
857 overridden by subtargets. */
859 #ifndef SUBTARGET_ASM_SPEC
860 #define SUBTARGET_ASM_SPEC ""
863 /* ASM_SPEC is the set of arguments to pass to the assembler. */
866 %{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
867 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
868 %(subtarget_asm_optimizing_spec) \
869 %(subtarget_asm_debugging_spec) \
872 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
874 %(subtarget_asm_spec)"
876 /* Specify to run a post-processor, mips-tfile after the assembler
877 has run to stuff the mips debug information into the object file.
878 This is needed because the $#!%^ MIPS assembler provides no way
879 of specifying such information in the assembly file. If we are
880 cross compiling, disable mips-tfile unless the user specifies
883 #ifndef ASM_FINAL_SPEC
884 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
886 #define ASM_FINAL_SPEC "\
887 %{mmips-as: %{!mno-mips-tfile: \
888 \n mips-tfile %{v*: -v} \
890 %{!K: %{save-temps: -I %b.o~}} \
891 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
892 %{.s:%i} %{!.s:%g.s}}}"
896 #define ASM_FINAL_SPEC "\
897 %{!mgas: %{!mno-mips-tfile: \
898 \n mips-tfile %{v*: -v} \
900 %{!K: %{save-temps: -I %b.o~}} \
901 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
902 %{.s:%i} %{!.s:%g.s}}}"
905 #endif /* ASM_FINAL_SPEC */
907 /* Redefinition of libraries used. Mips doesn't support normal
908 UNIX style profiling via calling _mcount. It does offer
909 profiling that samples the PC, so do what we can... */
912 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
915 /* Extra switches sometimes passed to the linker. */
916 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
917 will interpret it as a -b option. */
922 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \
923 %{bestGnum} %{shared} %{non_shared}"
924 #endif /* LINK_SPEC defined */
926 /* Specs for the compiler proper */
928 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
929 overridden by subtargets. */
930 #ifndef SUBTARGET_CC1_SPEC
931 #define SUBTARGET_CC1_SPEC ""
934 /* Deal with historic options. */
936 #define CC1_CPU_SPEC "\
938 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
939 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
940 %{m4650:-march=r4650 -mmad -msingle-float \
941 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
944 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
948 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
949 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
950 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
951 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
952 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
953 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
954 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
955 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
956 %{pic-none: -mno-half-pic} \
957 %{pic-lib: -mhalf-pic} \
958 %{pic-extern: -mhalf-pic} \
959 %{pic-calls: -mhalf-pic} \
961 %(subtarget_cc1_spec) \
965 /* Preprocessor specs. */
967 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
968 be overridden by subtargets. */
970 #ifndef SUBTARGET_CPP_SIZE_SPEC
971 #define SUBTARGET_CPP_SIZE_SPEC "\
972 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
973 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
976 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
977 overridden by subtargets. */
978 #ifndef SUBTARGET_CPP_SPEC
979 #define SUBTARGET_CPP_SPEC ""
982 /* If we're using 64bit longs, then we have to define __LONG_MAX__
983 correctly. Similarly for 64bit ints and __INT_MAX__. */
984 #ifndef LONG_MAX_SPEC
985 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
986 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
988 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
992 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
993 of the source file extension. */
994 #define CPLUSPLUS_CPP_SPEC "\
995 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
998 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1002 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1003 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1004 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1005 %(subtarget_cpp_size_spec) \
1006 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1007 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1008 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1009 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1010 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1011 %{msoft-float:-D__mips_soft_float} \
1012 %{mabi=eabi:-D__mips_eabi} \
1013 %{mips16:%{!mno-mips16:-D__mips16}} \
1014 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1015 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1017 %(subtarget_cpp_spec) "
1020 /* This macro defines names of additional specifications to put in the specs
1021 that can be used in various specifications like CC1_SPEC. Its definition
1022 is an initializer with a subgrouping for each command option.
1024 Each subgrouping contains a string constant, that defines the
1025 specification name, and a string constant that used by the GNU CC driver
1028 Do not define this macro if it does not need to do anything. */
1030 #define EXTRA_SPECS \
1031 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1032 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
1033 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1034 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1035 { "long_max_spec", LONG_MAX_SPEC }, \
1036 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1037 { "gas_asm_spec", GAS_ASM_SPEC }, \
1038 { "target_asm_spec", TARGET_ASM_SPEC }, \
1039 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1040 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1041 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1042 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1043 { "endian_spec", ENDIAN_SPEC }, \
1044 SUBTARGET_EXTRA_SPECS
1046 #ifndef SUBTARGET_EXTRA_SPECS
1047 #define SUBTARGET_EXTRA_SPECS
1050 /* If defined, this macro is an additional prefix to try after
1051 `STANDARD_EXEC_PREFIX'. */
1053 #ifndef MD_EXEC_PREFIX
1054 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1057 #ifndef MD_STARTFILE_PREFIX
1058 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1062 /* Print subsidiary information on the compiler version in use. */
1064 #define MIPS_VERSION "[AL 1.1, MM 40]"
1066 #ifndef MACHINE_TYPE
1067 #define MACHINE_TYPE "BSD Mips"
1070 #ifndef TARGET_VERSION_INTERNAL
1071 #define TARGET_VERSION_INTERNAL(STREAM) \
1072 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1075 #ifndef TARGET_VERSION
1076 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1080 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1081 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1082 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1084 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1085 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1088 /* By default, turn on GDB extensions. */
1089 #define DEFAULT_GDB_EXTENSIONS 1
1091 /* If we are passing smuggling stabs through the MIPS ECOFF object
1092 format, put a comment in front of the .stab<x> operation so
1093 that the MIPS assembler does not choke. The mips-tfile program
1094 will correctly put the stab into the object file. */
1096 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1097 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1098 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1100 /* Local compiler-generated symbols must have a prefix that the assembler
1101 understands. By default, this is $, although some targets (e.g.,
1102 NetBSD-ELF) need to override this. */
1104 #ifndef LOCAL_LABEL_PREFIX
1105 #define LOCAL_LABEL_PREFIX "$"
1108 /* By default on the mips, external symbols do not have an underscore
1109 prepended, but some targets (e.g., NetBSD) require this. */
1111 #ifndef USER_LABEL_PREFIX
1112 #define USER_LABEL_PREFIX ""
1115 /* Forward references to tags are allowed. */
1116 #define SDB_ALLOW_FORWARD_REFERENCES
1118 /* Unknown tags are also allowed. */
1119 #define SDB_ALLOW_UNKNOWN_REFERENCES
1121 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1122 since the length can run past this up to a continuation point. */
1123 #undef DBX_CONTIN_LENGTH
1124 #define DBX_CONTIN_LENGTH 1500
1126 /* How to renumber registers for dbx and gdb. */
1127 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1129 /* The mapping from gcc register number to DWARF 2 CFA column number.
1130 This mapping does not allow for tracking register 0, since SGI's broken
1131 dwarf reader thinks column 0 is used for the frame address, but since
1132 register 0 is fixed this is not a problem. */
1133 #define DWARF_FRAME_REGNUM(REG) \
1134 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1136 /* The DWARF 2 CFA column which tracks the return address. */
1137 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1139 /* Before the prologue, RA lives in r31. */
1140 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1142 /* Describe how we implement __builtin_eh_return. */
1143 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1144 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1146 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1147 The default for this in 64-bit mode is 8, which causes problems with
1148 SFmode register saves. */
1149 #define DWARF_CIE_DATA_ALIGNMENT 4
1151 /* Overrides for the COFF debug format. */
1152 #define PUT_SDB_SCL(a) \
1154 extern FILE *asm_out_text_file; \
1155 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1158 #define PUT_SDB_INT_VAL(a) \
1160 extern FILE *asm_out_text_file; \
1161 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1164 #define PUT_SDB_VAL(a) \
1166 extern FILE *asm_out_text_file; \
1167 fputs ("\t.val\t", asm_out_text_file); \
1168 output_addr_const (asm_out_text_file, (a)); \
1169 fputc (';', asm_out_text_file); \
1172 #define PUT_SDB_DEF(a) \
1174 extern FILE *asm_out_text_file; \
1175 fprintf (asm_out_text_file, "\t%s.def\t", \
1176 (TARGET_GAS) ? "" : "#"); \
1177 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1178 fputc (';', asm_out_text_file); \
1181 #define PUT_SDB_PLAIN_DEF(a) \
1183 extern FILE *asm_out_text_file; \
1184 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1185 (TARGET_GAS) ? "" : "#", (a)); \
1188 #define PUT_SDB_ENDEF \
1190 extern FILE *asm_out_text_file; \
1191 fprintf (asm_out_text_file, "\t.endef\n"); \
1194 #define PUT_SDB_TYPE(a) \
1196 extern FILE *asm_out_text_file; \
1197 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1200 #define PUT_SDB_SIZE(a) \
1202 extern FILE *asm_out_text_file; \
1203 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1206 #define PUT_SDB_DIM(a) \
1208 extern FILE *asm_out_text_file; \
1209 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1212 #ifndef PUT_SDB_START_DIM
1213 #define PUT_SDB_START_DIM \
1215 extern FILE *asm_out_text_file; \
1216 fprintf (asm_out_text_file, "\t.dim\t"); \
1220 #ifndef PUT_SDB_NEXT_DIM
1221 #define PUT_SDB_NEXT_DIM(a) \
1223 extern FILE *asm_out_text_file; \
1224 fprintf (asm_out_text_file, "%d,", a); \
1228 #ifndef PUT_SDB_LAST_DIM
1229 #define PUT_SDB_LAST_DIM(a) \
1231 extern FILE *asm_out_text_file; \
1232 fprintf (asm_out_text_file, "%d;", a); \
1236 #define PUT_SDB_TAG(a) \
1238 extern FILE *asm_out_text_file; \
1239 fprintf (asm_out_text_file, "\t.tag\t"); \
1240 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1241 fputc (';', asm_out_text_file); \
1244 /* For block start and end, we create labels, so that
1245 later we can figure out where the correct offset is.
1246 The normal .ent/.end serve well enough for functions,
1247 so those are just commented out. */
1249 #define PUT_SDB_BLOCK_START(LINE) \
1251 extern FILE *asm_out_text_file; \
1252 fprintf (asm_out_text_file, \
1253 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1254 LOCAL_LABEL_PREFIX, \
1256 (TARGET_GAS) ? "" : "#", \
1257 LOCAL_LABEL_PREFIX, \
1260 sdb_label_count++; \
1263 #define PUT_SDB_BLOCK_END(LINE) \
1265 extern FILE *asm_out_text_file; \
1266 fprintf (asm_out_text_file, \
1267 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1268 LOCAL_LABEL_PREFIX, \
1270 (TARGET_GAS) ? "" : "#", \
1271 LOCAL_LABEL_PREFIX, \
1274 sdb_label_count++; \
1277 #define PUT_SDB_FUNCTION_START(LINE)
1279 #define PUT_SDB_FUNCTION_END(LINE) \
1281 extern FILE *asm_out_text_file; \
1282 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1285 #define PUT_SDB_EPILOGUE_END(NAME)
1287 #define PUT_SDB_SRC_FILE(FILENAME) \
1289 extern FILE *asm_out_text_file; \
1290 output_file_directive (asm_out_text_file, (FILENAME)); \
1293 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1294 sprintf ((BUFFER), ".%dfake", (NUMBER));
1296 /* Correct the offset of automatic variables and arguments. Note that
1297 the MIPS debug format wants all automatic variables and arguments
1298 to be in terms of the virtual frame pointer (stack pointer before
1299 any adjustment in the function), while the MIPS 3.0 linker wants
1300 the frame pointer to be the stack pointer after the initial
1303 #define DEBUGGER_AUTO_OFFSET(X) \
1304 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1305 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1306 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1308 /* Tell collect that the object format is ECOFF */
1309 #ifndef OBJECT_FORMAT_ROSE
1310 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1311 #define EXTENDED_COFF /* ECOFF, not normal coff */
1314 #if 0 /* These definitions normally have no effect because
1315 MIPS systems define USE_COLLECT2, so
1316 assemble_constructor does nothing anyway. */
1318 /* Don't use the default definitions, because we don't have gld.
1319 Also, we don't want stabs when generating ECOFF output.
1320 Instead we depend on collect to handle these. */
1322 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1323 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1327 /* Target machine storage layout */
1329 /* Define in order to support both big and little endian float formats
1330 in the same gcc binary. */
1331 #define REAL_ARITHMETIC
1333 /* Define this if most significant bit is lowest numbered
1334 in instructions that operate on numbered bit-fields.
1336 #define BITS_BIG_ENDIAN 0
1338 /* Define this if most significant byte of a word is the lowest numbered. */
1339 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1341 /* Define this if most significant word of a multiword number is the lowest. */
1342 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1344 /* Define this to set the endianness to use in libgcc2.c, which can
1345 not depend on target_flags. */
1346 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1347 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1349 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1352 /* Number of bits in an addressable storage unit */
1353 #define BITS_PER_UNIT 8
1355 /* Width in bits of a "word", which is the contents of a machine register.
1356 Note that this is not necessarily the width of data type `int';
1357 if using 16-bit ints on a 68000, this would still be 32.
1358 But on a machine with 16-bit registers, this would be 16. */
1359 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1360 #define MAX_BITS_PER_WORD 64
1362 /* Width of a word, in units (bytes). */
1363 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1364 #define MIN_UNITS_PER_WORD 4
1366 /* For MIPS, width of a floating point register. */
1367 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1369 /* A C expression for the size in bits of the type `int' on the
1370 target machine. If you don't define this, the default is one
1372 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1373 #define MAX_INT_TYPE_SIZE 64
1375 /* Tell the preprocessor the maximum size of wchar_t. */
1376 #ifndef MAX_WCHAR_TYPE_SIZE
1377 #ifndef WCHAR_TYPE_SIZE
1378 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1382 /* A C expression for the size in bits of the type `short' on the
1383 target machine. If you don't define this, the default is half a
1384 word. (If this would be less than one storage unit, it is
1385 rounded up to one unit.) */
1386 #define SHORT_TYPE_SIZE 16
1388 /* A C expression for the size in bits of the type `long' on the
1389 target machine. If you don't define this, the default is one
1391 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1392 #define MAX_LONG_TYPE_SIZE 64
1394 /* A C expression for the size in bits of the type `long long' on the
1395 target machine. If you don't define this, the default is two
1397 #define LONG_LONG_TYPE_SIZE 64
1399 /* A C expression for the size in bits of the type `char' on the
1400 target machine. If you don't define this, the default is one
1401 quarter of a word. (If this would be less than one storage unit,
1402 it is rounded up to one unit.) */
1403 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1405 /* A C expression for the size in bits of the type `float' on the
1406 target machine. If you don't define this, the default is one
1408 #define FLOAT_TYPE_SIZE 32
1410 /* A C expression for the size in bits of the type `double' on the
1411 target machine. If you don't define this, the default is two
1413 #define DOUBLE_TYPE_SIZE 64
1415 /* A C expression for the size in bits of the type `long double' on
1416 the target machine. If you don't define this, the default is two
1418 #define LONG_DOUBLE_TYPE_SIZE 64
1420 /* Width in bits of a pointer.
1421 See also the macro `Pmode' defined below. */
1422 #ifndef POINTER_SIZE
1423 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1426 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1427 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1429 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1430 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1432 /* Allocation boundary (in *bits*) for the code of a function. */
1433 #define FUNCTION_BOUNDARY 32
1435 /* Alignment of field after `int : 0' in a structure. */
1436 #define EMPTY_FIELD_BOUNDARY 32
1438 /* Every structure's size must be a multiple of this. */
1439 /* 8 is observed right on a DECstation and on riscos 4.02. */
1440 #define STRUCTURE_SIZE_BOUNDARY 8
1442 /* There is no point aligning anything to a rounder boundary than this. */
1443 #define BIGGEST_ALIGNMENT 64
1445 /* Set this nonzero if move instructions will actually fail to work
1446 when given unaligned data. */
1447 #define STRICT_ALIGNMENT 1
1449 /* Define this if you wish to imitate the way many other C compilers
1450 handle alignment of bitfields and the structures that contain
1453 The behavior is that the type written for a bitfield (`int',
1454 `short', or other integer type) imposes an alignment for the
1455 entire structure, as if the structure really did contain an
1456 ordinary field of that type. In addition, the bitfield is placed
1457 within the structure so that it would fit within such a field,
1458 not crossing a boundary for it.
1460 Thus, on most machines, a bitfield whose type is written as `int'
1461 would not cross a four-byte boundary, and would force four-byte
1462 alignment for the whole structure. (The alignment used may not
1463 be four bytes; it is controlled by the other alignment
1466 If the macro is defined, its definition should be a C expression;
1467 a nonzero value for the expression enables this behavior. */
1469 #define PCC_BITFIELD_TYPE_MATTERS 1
1471 /* If defined, a C expression to compute the alignment given to a
1472 constant that is being placed in memory. CONSTANT is the constant
1473 and ALIGN is the alignment that the object would ordinarily have.
1474 The value of this macro is used instead of that alignment to align
1477 If this macro is not defined, then ALIGN is used.
1479 The typical use of this macro is to increase alignment for string
1480 constants to be word aligned so that `strcpy' calls that copy
1481 constants can be done inline. */
1483 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1484 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1485 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1487 /* If defined, a C expression to compute the alignment for a static
1488 variable. TYPE is the data type, and ALIGN is the alignment that
1489 the object would ordinarily have. The value of this macro is used
1490 instead of that alignment to align the object.
1492 If this macro is not defined, then ALIGN is used.
1494 One use of this macro is to increase alignment of medium-size
1495 data to make it all fit in fewer cache lines. Another is to
1496 cause character arrays to be word-aligned so that `strcpy' calls
1497 that copy constants to character arrays can be done inline. */
1499 #undef DATA_ALIGNMENT
1500 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1501 ((((ALIGN) < BITS_PER_WORD) \
1502 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1503 || TREE_CODE (TYPE) == UNION_TYPE \
1504 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1507 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1509 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1511 /* Define this macro if an argument declared as `char' or `short' in a
1512 prototype should actually be passed as an `int'. In addition to
1513 avoiding errors in certain cases of mismatch, it also makes for
1514 better code on certain machines. */
1516 #define PROMOTE_PROTOTYPES 1
1518 /* Define if operations between registers always perform the operation
1519 on the full register even if a narrower mode is specified. */
1520 #define WORD_REGISTER_OPERATIONS
1522 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1523 will either zero-extend or sign-extend. The value of this macro should
1524 be the code that says which one of the two operations is implicitly
1527 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1528 moves. All other referces are zero extended. */
1529 #define LOAD_EXTEND_OP(MODE) \
1530 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1531 ? SIGN_EXTEND : ZERO_EXTEND)
1533 /* Define this macro if it is advisable to hold scalars in registers
1534 in a wider mode than that declared by the program. In such cases,
1535 the value is constrained to be within the bounds of the declared
1536 type, but kept valid in the wider mode. The signedness of the
1537 extension may differ from that of the type.
1539 We promote any value smaller than SImode up to SImode. We don't
1540 want to promote to DImode when in 64 bit mode, because that would
1541 prevent us from using the faster SImode multiply and divide
1544 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1545 if (GET_MODE_CLASS (MODE) == MODE_INT \
1546 && GET_MODE_SIZE (MODE) < 4) \
1549 /* Define this if function arguments should also be promoted using the above
1552 #define PROMOTE_FUNCTION_ARGS
1554 /* Likewise, if the function return value is promoted. */
1556 #define PROMOTE_FUNCTION_RETURN
1558 /* Standard register usage. */
1560 /* Number of actual hardware registers.
1561 The hardware registers are assigned numbers for the compiler
1562 from 0 to just below FIRST_PSEUDO_REGISTER.
1563 All registers that the compiler knows about must be given numbers,
1564 even those that are not normally considered general registers.
1566 On the Mips, we have 32 integer registers, 32 floating point
1567 registers, 8 condition code registers, and the special registers
1568 hi, lo, hilo, and rap. The 8 condition code registers are only
1569 used if mips_isa >= 4. The hilo register is only used in 64 bit
1570 mode. It represents a 64 bit value stored as two 32 bit values in
1571 the hi and lo registers; this is the result of the mult
1572 instruction. rap is a pointer to the stack where the return
1573 address reg ($31) was stored. This is needed for C++ exception
1576 #define FIRST_PSEUDO_REGISTER 76
1578 /* 1 for registers that have pervasive standard uses
1579 and are not available for the register allocator.
1581 On the MIPS, see conventions, page D-2 */
1583 #define FIXED_REGISTERS \
1585 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1593 /* 1 for registers not available across function calls.
1594 These must include the FIXED_REGISTERS and also any
1595 registers that can be used without being saved.
1596 The latter must include the registers where values are returned
1597 and the register where structure-value addresses are passed.
1598 Aside from that, you can include as many other registers as you like. */
1600 #define CALL_USED_REGISTERS \
1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1603 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1605 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1606 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1610 /* Internal macros to classify a register number as to whether it's a
1611 general purpose register, a floating point register, a
1612 multiply/divide register, or a status register. */
1614 #define GP_REG_FIRST 0
1615 #define GP_REG_LAST 31
1616 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1617 #define GP_DBX_FIRST 0
1619 #define FP_REG_FIRST 32
1620 #define FP_REG_LAST 63
1621 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1622 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1624 #define MD_REG_FIRST 64
1625 #define MD_REG_LAST 66
1626 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1628 #define ST_REG_FIRST 67
1629 #define ST_REG_LAST 74
1630 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1632 #define RAP_REG_NUM 75
1634 #define AT_REGNUM (GP_REG_FIRST + 1)
1635 #define HI_REGNUM (MD_REG_FIRST + 0)
1636 #define LO_REGNUM (MD_REG_FIRST + 1)
1637 #define HILO_REGNUM (MD_REG_FIRST + 2)
1639 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1640 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1641 should be used instead. */
1642 #define FPSW_REGNUM ST_REG_FIRST
1644 #define GP_REG_P(REGNO) \
1645 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1646 #define M16_REG_P(REGNO) \
1647 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1648 #define FP_REG_P(REGNO) \
1649 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1650 #define MD_REG_P(REGNO) \
1651 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1652 #define ST_REG_P(REGNO) \
1653 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1655 /* Return number of consecutive hard regs needed starting at reg REGNO
1656 to hold something of mode MODE.
1657 This is ordinarily the length in words of a value of mode MODE
1658 but can be less for certain modes in special long registers.
1660 On the MIPS, all general registers are one word long. Except on
1661 the R4000 with the FR bit set, the floating point uses register
1662 pairs, with the second register not being allocable. */
1664 #define HARD_REGNO_NREGS(REGNO, MODE) \
1665 (! FP_REG_P (REGNO) \
1666 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1667 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1669 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1670 MODE. In 32 bit mode, require that DImode and DFmode be in even
1671 registers. For DImode, this makes some of the insns easier to
1672 write, since you don't have to worry about a DImode value in
1673 registers 3 & 4, producing a result in 4 & 5.
1675 To make the code simpler HARD_REGNO_MODE_OK now just references an
1676 array built in override_options. Because machmodes.h is not yet
1677 included before this file is processed, the MODE bound can't be
1680 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1682 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1683 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1685 /* Value is 1 if it is a good idea to tie two pseudo registers
1686 when one has mode MODE1 and one has mode MODE2.
1687 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1688 for any hard reg, then this must be 0 for correct output. */
1689 #define MODES_TIEABLE_P(MODE1, MODE2) \
1690 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1691 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1692 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1693 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1695 /* MIPS pc is not overloaded on a register. */
1696 /* #define PC_REGNUM xx */
1698 /* Register to use for pushing function arguments. */
1699 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1701 /* Offset from the stack pointer to the first available location. Use
1702 the default value zero. */
1703 /* #define STACK_POINTER_OFFSET 0 */
1705 /* Base register for access to local variables of the function. We
1706 pretend that the frame pointer is $1, and then eliminate it to
1707 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1708 a fixed register, and will not be used for anything else. */
1709 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1711 /* Temporary scratch register for use by the assembler. */
1712 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1714 /* $30 is not available on the mips16, so we use $17 as the frame
1716 #define HARD_FRAME_POINTER_REGNUM \
1717 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1719 /* Value should be nonzero if functions must have frame pointers.
1720 Zero means the frame pointer need not be set up (and parms
1721 may be accessed via the stack pointer) in functions that seem suitable.
1722 This is computed in `reload', in reload1.c. */
1723 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1725 /* Base register for access to arguments of the function. */
1726 #define ARG_POINTER_REGNUM GP_REG_FIRST
1728 /* Fake register that holds the address on the stack of the
1729 current function's return address. */
1730 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1732 /* Register in which static-chain is passed to a function. */
1733 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1735 /* If the structure value address is passed in a register, then
1736 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1737 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1739 /* If the structure value address is not passed in a register, define
1740 `STRUCT_VALUE' as an expression returning an RTX for the place
1741 where the address is passed. If it returns 0, the address is
1742 passed as an "invisible" first argument. */
1743 #define STRUCT_VALUE 0
1745 /* Mips registers used in prologue/epilogue code when the stack frame
1746 is larger than 32K bytes. These registers must come from the
1747 scratch register set, and not used for passing and returning
1748 arguments and any other information used in the calling sequence
1749 (such as pic). Must start at 12, since t0/t3 are parameter passing
1750 registers in the 64 bit ABI. */
1752 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1753 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1755 /* Define this macro if it is as good or better to call a constant
1756 function address than to call an address kept in a register. */
1757 #define NO_FUNCTION_CSE 1
1759 /* Define this macro if it is as good or better for a function to
1760 call itself with an explicit address than to call an address
1761 kept in a register. */
1762 #define NO_RECURSIVE_FUNCTION_CSE 1
1764 /* The register number of the register used to address a table of
1765 static data addresses in memory. In some cases this register is
1766 defined by a processor's "application binary interface" (ABI).
1767 When this macro is defined, RTL is generated for this register
1768 once, as with the stack pointer and frame pointer registers. If
1769 this macro is not defined, it is up to the machine-dependent
1770 files to allocate such a register (if necessary). */
1771 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1773 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1775 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1776 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1777 isn't always called for static inline functions. */
1778 #define INIT_EXPANDERS \
1780 embedded_pic_fnaddr_rtx = NULL; \
1781 mips16_gp_pseudo_rtx = NULL; \
1784 /* Define the classes of registers for register constraints in the
1785 machine description. Also define ranges of constants.
1787 One of the classes must always be named ALL_REGS and include all hard regs.
1788 If there is more than one class, another class must be named NO_REGS
1789 and contain no registers.
1791 The name GENERAL_REGS must be the name of a class (or an alias for
1792 another name such as ALL_REGS). This is the class of registers
1793 that is allowed by "g" or "r" in a register constraint.
1794 Also, registers outside this class are allocated only when
1795 instructions express preferences for them.
1797 The classes must be numbered in nondecreasing order; that is,
1798 a larger-numbered class must never be contained completely
1799 in a smaller-numbered class.
1801 For any two classes, it is very desirable that there be another
1802 class that represents their union. */
1806 NO_REGS, /* no registers in set */
1807 M16_NA_REGS, /* mips16 regs not used to pass args */
1808 M16_REGS, /* mips16 directly accessible registers */
1809 T_REG, /* mips16 T register ($24) */
1810 M16_T_REGS, /* mips16 registers plus T register */
1811 GR_REGS, /* integer registers */
1812 FP_REGS, /* floating point registers */
1813 HI_REG, /* hi register */
1814 LO_REG, /* lo register */
1815 HILO_REG, /* hilo register pair for 64 bit mode mult */
1816 MD_REGS, /* multiply/divide registers (hi/lo) */
1817 HI_AND_GR_REGS, /* union classes */
1820 ST_REGS, /* status registers (fp status) */
1821 ALL_REGS, /* all registers */
1822 LIM_REG_CLASSES /* max value + 1 */
1825 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1827 #define GENERAL_REGS GR_REGS
1829 /* An initializer containing the names of the register classes as C
1830 string constants. These names are used in writing some of the
1833 #define REG_CLASS_NAMES \
1848 "HILO_AND_GR_REGS", \
1853 /* An initializer containing the contents of the register classes,
1854 as integers which are bit masks. The Nth integer specifies the
1855 contents of class N. The way the integer MASK is interpreted is
1856 that register R is in the class if `MASK & (1 << R)' is 1.
1858 When the machine has more than 32 registers, an integer does not
1859 suffice. Then the integers are replaced by sub-initializers,
1860 braced groupings containing several integers. Each
1861 sub-initializer must be suitable as an initializer for the type
1862 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1864 #define REG_CLASS_CONTENTS \
1866 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1867 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1868 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1869 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1870 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1871 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1872 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1873 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1874 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1875 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1876 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1877 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1878 { 0xffffffff, 0x00000000, 0x00000002 }, \
1879 { 0xffffffff, 0x00000000, 0x00000004 }, \
1880 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1881 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1885 /* A C expression whose value is a register class containing hard
1886 register REGNO. In general there is more that one such class;
1887 choose a class which is "minimal", meaning that no smaller class
1888 also contains the register. */
1890 extern enum reg_class mips_regno_to_class[];
1892 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1894 /* A macro whose definition is the name of the class to which a
1895 valid base register must belong. A base register is one used in
1896 an address which is the register value plus a displacement. */
1898 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1900 /* A macro whose definition is the name of the class to which a
1901 valid index register must belong. An index register is one used
1902 in an address where its value is either multiplied by a scale
1903 factor or added to another register (as well as added to a
1906 #define INDEX_REG_CLASS NO_REGS
1908 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1909 registers explicitly used in the rtl to be used as spill registers
1910 but prevents the compiler from extending the lifetime of these
1913 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1915 /* This macro is used later on in the file. */
1916 #define GR_REG_CLASS_P(CLASS) \
1917 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1918 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1920 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1921 is the default value (allocate the registers in numeric order). We
1922 define it just so that we can override it for the mips16 target in
1923 ORDER_REGS_FOR_LOCAL_ALLOC. */
1925 #define REG_ALLOC_ORDER \
1926 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1927 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1928 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1929 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1930 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1933 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1934 to be rearranged based on a particular function. On the mips16, we
1935 want to allocate $24 (T_REG) before other registers for
1936 instructions for which it is possible. */
1938 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1940 /* REGISTER AND CONSTANT CLASSES */
1942 /* Get reg_class from a letter such as appears in the machine
1945 DEFINED REGISTER CLASSES:
1947 'd' General (aka integer) registers
1948 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1949 'y' General registers (in both mips16 and non mips16 mode)
1950 'e' mips16 non argument registers (M16_NA_REGS)
1951 't' mips16 temporary register ($24)
1952 'f' Floating point registers
1955 'x' Multiply/divide registers
1957 'z' FP Status register
1958 'b' All registers */
1960 extern enum reg_class mips_char_to_class[];
1962 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1964 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1965 string can be used to stand for particular ranges of immediate
1966 operands. This macro defines what the ranges are. C is the
1967 letter, and VALUE is a constant value. Return 1 if VALUE is
1968 in the range specified by C. */
1972 `I' is used for the range of constants an arithmetic insn can
1973 actually contain (16 bits signed integers).
1975 `J' is used for the range which is just zero (ie, $r0).
1977 `K' is used for the range of constants a logical insn can actually
1978 contain (16 bit zero-extended integers).
1980 `L' is used for the range of constants that be loaded with lui
1981 (ie, the bottom 16 bits are zero).
1983 `M' is used for the range of constants that take two words to load
1984 (ie, not matched by `I', `K', and `L').
1986 `N' is used for negative 16 bit constants other than -65536.
1988 `O' is a 15 bit signed integer.
1990 `P' is used for positive 16 bit constants. */
1992 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1993 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1995 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1996 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1997 : (C) == 'J' ? ((VALUE) == 0) \
1998 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1999 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2000 && (((VALUE) & ~2147483647) == 0 \
2001 || ((VALUE) & ~2147483647) == ~2147483647)) \
2002 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2003 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2004 && (((VALUE) & 0x0000ffff) != 0 \
2005 || (((VALUE) & ~2147483647) != 0 \
2006 && ((VALUE) & ~2147483647) != ~2147483647))) \
2007 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2008 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2009 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2012 /* Similar, but for floating constants, and defining letters G and H.
2013 Here VALUE is the CONST_DOUBLE rtx itself. */
2017 'G' : Floating point 0 */
2019 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2021 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2023 /* Letters in the range `Q' through `U' may be defined in a
2024 machine-dependent fashion to stand for arbitrary operand types.
2025 The machine description macro `EXTRA_CONSTRAINT' is passed the
2026 operand as its first argument and the constraint letter as its
2029 `Q' is for mips16 GP relative constants
2030 `R' is for memory references which take 1 word for the instruction.
2031 `S' is for references to extern items which are PIC for OSF/rose.
2032 `T' is for memory addresses that can be used to load two words. */
2034 #define EXTRA_CONSTRAINT(OP,CODE) \
2035 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2036 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2037 && mips16_gp_offset_p (OP)) \
2038 : (GET_CODE (OP) != MEM) ? FALSE \
2039 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2040 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2041 && HALF_PIC_ADDRESS_P (OP)) \
2044 /* Given an rtx X being reloaded into a reg required to be
2045 in class CLASS, return the class of reg to actually use.
2046 In general this is just CLASS; but on some machines
2047 in some cases it is preferable to use a more restrictive class. */
2049 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2050 ((CLASS) != ALL_REGS \
2051 ? (! TARGET_MIPS16 \
2053 : ((CLASS) != GR_REGS \
2056 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2057 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2058 ? (TARGET_SOFT_FLOAT \
2059 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2061 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2062 || GET_MODE (X) == VOIDmode) \
2063 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2066 /* Certain machines have the property that some registers cannot be
2067 copied to some other registers without using memory. Define this
2068 macro on those machines to be a C expression that is non-zero if
2069 objects of mode MODE in registers of CLASS1 can only be copied to
2070 registers of class CLASS2 by storing a register of CLASS1 into
2071 memory and loading that memory location into a register of CLASS2.
2073 Do not define this macro if its value would always be zero. */
2075 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2076 ((!TARGET_DEBUG_H_MODE \
2077 && GET_MODE_CLASS (MODE) == MODE_INT \
2078 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2079 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2080 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2081 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2082 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2084 /* The HI and LO registers can only be reloaded via the general
2085 registers. Condition code registers can only be loaded to the
2086 general registers, and from the floating point registers. */
2088 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2089 mips_secondary_reload_class (CLASS, MODE, X, 1)
2090 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2091 mips_secondary_reload_class (CLASS, MODE, X, 0)
2093 /* Return the maximum number of consecutive registers
2094 needed to represent mode MODE in a register of class CLASS. */
2096 #define CLASS_UNITS(mode, size) \
2097 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2099 #define CLASS_MAX_NREGS(CLASS, MODE) \
2100 ((CLASS) == FP_REGS \
2102 ? CLASS_UNITS (MODE, 8) \
2103 : 2 * CLASS_UNITS (MODE, 8)) \
2104 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2106 /* If defined, gives a class of registers that cannot be used as the
2107 operand of a SUBREG that changes the mode of the object illegally. */
2109 #define CLASS_CANNOT_CHANGE_MODE \
2110 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2112 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2114 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2115 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2117 /* Stack layout; function entry, exit and calling. */
2119 /* Define this if pushing a word on the stack
2120 makes the stack pointer a smaller address. */
2121 #define STACK_GROWS_DOWNWARD
2123 /* Define this if the nominal address of the stack frame
2124 is at the high-address end of the local variables;
2125 that is, each additional local variable allocated
2126 goes at a more negative offset in the frame. */
2127 /* #define FRAME_GROWS_DOWNWARD */
2129 /* Offset within stack frame to start allocating local variables at.
2130 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2131 first local allocated. Otherwise, it is the offset to the BEGINNING
2132 of the first local allocated. */
2133 #define STARTING_FRAME_OFFSET \
2134 (current_function_outgoing_args_size \
2135 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2137 /* Offset from the stack pointer register to an item dynamically
2138 allocated on the stack, e.g., by `alloca'.
2140 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2141 length of the outgoing arguments. The default is correct for most
2142 machines. See `function.c' for details.
2144 The MIPS ABI states that functions which dynamically allocate the
2145 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2146 we are trying to create a second frame pointer to the function, so
2147 allocate some stack space to make it happy.
2149 However, the linker currently complains about linking any code that
2150 dynamically allocates stack space, and there seems to be a bug in
2151 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2154 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2155 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2156 ? 4*UNITS_PER_WORD \
2157 : current_function_outgoing_args_size)
2160 /* The return address for the current frame is in r31 is this is a leaf
2161 function. Otherwise, it is on the stack. It is at a variable offset
2162 from sp/fp/ap, so we define a fake hard register rap which is a
2163 poiner to the return address on the stack. This always gets eliminated
2164 during reload to be either the frame pointer or the stack pointer plus
2167 /* ??? This definition fails for leaf functions. There is currently no
2168 general solution for this problem. */
2170 /* ??? There appears to be no way to get the return address of any previous
2171 frame except by disassembling instructions in the prologue/epilogue.
2172 So currently we support only the current frame. */
2174 #define RETURN_ADDR_RTX(count, frame) \
2176 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2179 /* Structure to be filled in by compute_frame_size with register
2180 save masks, and offsets for the current function. */
2182 struct mips_frame_info
2184 long total_size; /* # bytes that the entire frame takes up */
2185 long var_size; /* # bytes that variables take up */
2186 long args_size; /* # bytes that outgoing arguments take up */
2187 long extra_size; /* # bytes of extra gunk */
2188 int gp_reg_size; /* # bytes needed to store gp regs */
2189 int fp_reg_size; /* # bytes needed to store fp regs */
2190 long mask; /* mask of saved gp registers */
2191 long fmask; /* mask of saved fp registers */
2192 long gp_save_offset; /* offset from vfp to store gp registers */
2193 long fp_save_offset; /* offset from vfp to store fp registers */
2194 long gp_sp_offset; /* offset from new sp to store gp registers */
2195 long fp_sp_offset; /* offset from new sp to store fp registers */
2196 int initialized; /* != 0 if frame size already calculated */
2197 int num_gp; /* number of gp registers saved */
2198 int num_fp; /* number of fp registers saved */
2199 long insns_len; /* length of insns; mips16 only */
2202 extern struct mips_frame_info current_frame_info;
2204 /* If defined, this macro specifies a table of register pairs used to
2205 eliminate unneeded registers that point into the stack frame. If
2206 it is not defined, the only elimination attempted by the compiler
2207 is to replace references to the frame pointer with references to
2210 The definition of this macro is a list of structure
2211 initializations, each of which specifies an original and
2212 replacement register.
2214 On some machines, the position of the argument pointer is not
2215 known until the compilation is completed. In such a case, a
2216 separate hard register must be used for the argument pointer.
2217 This register can be eliminated by replacing it with either the
2218 frame pointer or the argument pointer, depending on whether or not
2219 the frame pointer has been eliminated.
2221 In this case, you might specify:
2222 #define ELIMINABLE_REGS \
2223 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2224 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2225 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2227 Note that the elimination of the argument pointer with the stack
2228 pointer is specified first since that is the preferred elimination.
2230 The eliminations to $17 are only used on the mips16. See the
2231 definition of HARD_FRAME_POINTER_REGNUM. */
2233 #define ELIMINABLE_REGS \
2234 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2235 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2236 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2237 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2238 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2239 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2240 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2241 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2242 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2243 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2245 /* A C expression that returns non-zero if the compiler is allowed to
2246 try to replace register number FROM-REG with register number
2247 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2248 defined, and will usually be the constant 1, since most of the
2249 cases preventing register elimination are things that the compiler
2250 already knows about.
2252 When not in mips16 and mips64, we can always eliminate to the
2253 frame pointer. We can eliminate to the stack pointer unless
2254 a frame pointer is needed. In mips16 mode, we need a frame
2255 pointer for a large frame; otherwise, reload may be unable
2256 to compute the address of a local variable, since there is
2257 no way to add a large constant to the stack pointer
2258 without using a temporary register.
2260 In mips16, for some instructions (eg lwu), we can't eliminate the
2261 frame pointer for the stack pointer. These instructions are
2262 only generated in TARGET_64BIT mode.
2265 #define CAN_ELIMINATE(FROM, TO) \
2266 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2267 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2268 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2269 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2270 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2271 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2272 && (! TARGET_MIPS16 \
2273 || compute_frame_size (get_frame_size ()) < 32768)))))
2275 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2276 specifies the initial difference between the specified pair of
2277 registers. This macro must be defined if `ELIMINABLE_REGS' is
2280 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2281 { compute_frame_size (get_frame_size ()); \
2282 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2283 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2284 (OFFSET) = - current_function_outgoing_args_size; \
2285 else if ((FROM) == FRAME_POINTER_REGNUM) \
2287 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2288 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2289 (OFFSET) = (current_frame_info.total_size \
2290 - current_function_outgoing_args_size \
2291 - ((mips_abi != ABI_32 \
2292 && mips_abi != ABI_O64 \
2293 && mips_abi != ABI_EABI) \
2294 ? current_function_pretend_args_size \
2296 else if ((FROM) == ARG_POINTER_REGNUM) \
2297 (OFFSET) = (current_frame_info.total_size \
2298 - ((mips_abi != ABI_32 \
2299 && mips_abi != ABI_O64 \
2300 && mips_abi != ABI_EABI) \
2301 ? current_function_pretend_args_size \
2303 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2304 so we must add 4 bytes to the offset to get the right value. */ \
2305 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2307 if (leaf_function_p ()) \
2309 else (OFFSET) = current_frame_info.gp_sp_offset \
2310 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2311 * (BYTES_BIG_ENDIAN != 0)); \
2315 /* If we generate an insn to push BYTES bytes,
2316 this says how many the stack pointer really advances by.
2317 On the vax, sp@- in a byte insn really pushes a word. */
2319 /* #define PUSH_ROUNDING(BYTES) 0 */
2321 /* If defined, the maximum amount of space required for outgoing
2322 arguments will be computed and placed into the variable
2323 `current_function_outgoing_args_size'. No space will be pushed
2324 onto the stack for each call; instead, the function prologue
2325 should increase the stack frame size by this amount.
2327 It is not proper to define both `PUSH_ROUNDING' and
2328 `ACCUMULATE_OUTGOING_ARGS'. */
2329 #define ACCUMULATE_OUTGOING_ARGS 1
2331 /* Offset from the argument pointer register to the first argument's
2332 address. On some machines it may depend on the data type of the
2335 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2336 the first argument's address.
2338 On the MIPS, we must skip the first argument position if we are
2339 returning a structure or a union, to account for its address being
2340 passed in $4. However, at the current time, this produces a compiler
2341 that can't bootstrap, so comment it out for now. */
2344 #define FIRST_PARM_OFFSET(FNDECL) \
2346 && TREE_TYPE (FNDECL) != 0 \
2347 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2348 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2349 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2353 #define FIRST_PARM_OFFSET(FNDECL) 0
2356 /* When a parameter is passed in a register, stack space is still
2357 allocated for it. For the MIPS, stack space must be allocated, cf
2358 Asm Lang Prog Guide page 7-8.
2360 BEWARE that some space is also allocated for non existing arguments
2361 in register. In case an argument list is of form GF used registers
2362 are a0 (a2,a3), but we should push over a1... */
2364 #define REG_PARM_STACK_SPACE(FNDECL) \
2365 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2367 /* Define this if it is the responsibility of the caller to
2368 allocate the area reserved for arguments passed in registers.
2369 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2370 of this macro is to determine whether the space is included in
2371 `current_function_outgoing_args_size'. */
2372 #define OUTGOING_REG_PARM_STACK_SPACE
2374 /* Align stack frames on 64 bits (Double Word ). */
2375 #ifndef STACK_BOUNDARY
2376 #define STACK_BOUNDARY 64
2379 /* Make sure 4 words are always allocated on the stack. */
2381 #ifndef STACK_ARGS_ADJUST
2382 #define STACK_ARGS_ADJUST(SIZE) \
2384 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2385 SIZE.constant = 4 * UNITS_PER_WORD; \
2390 /* A C expression that should indicate the number of bytes of its
2391 own arguments that a function pops on returning, or 0
2392 if the function pops no arguments and the caller must therefore
2393 pop them all after the function returns.
2395 FUNDECL is the declaration node of the function (as a tree).
2397 FUNTYPE is a C variable whose value is a tree node that
2398 describes the function in question. Normally it is a node of
2399 type `FUNCTION_TYPE' that describes the data type of the function.
2400 From this it is possible to obtain the data types of the value
2401 and arguments (if known).
2403 When a call to a library function is being considered, FUNTYPE
2404 will contain an identifier node for the library function. Thus,
2405 if you need to distinguish among various library functions, you
2406 can do so by their names. Note that "library function" in this
2407 context means a function used to perform arithmetic, whose name
2408 is known specially in the compiler and was not mentioned in the
2409 C code being compiled.
2411 STACK-SIZE is the number of bytes of arguments passed on the
2412 stack. If a variable number of bytes is passed, it is zero, and
2413 argument popping will always be the responsibility of the
2414 calling function. */
2416 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2419 /* Symbolic macros for the registers used to return integer and floating
2422 #define GP_RETURN (GP_REG_FIRST + 2)
2423 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2425 /* Symbolic macros for the first/last argument registers. */
2427 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2428 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2429 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2430 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2432 #define MAX_ARGS_IN_REGISTERS 4
2434 /* Define how to find the value returned by a library function
2435 assuming the value has mode MODE. Because we define
2436 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2437 PROMOTE_MODE does. */
2439 #define LIBCALL_VALUE(MODE) \
2441 ((GET_MODE_CLASS (MODE) != MODE_INT \
2442 || GET_MODE_SIZE (MODE) >= 4) \
2445 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2446 && (! TARGET_SINGLE_FLOAT \
2447 || GET_MODE_SIZE (MODE) <= 4)) \
2451 /* Define how to find the value returned by a function.
2452 VALTYPE is the data type of the value (as a tree).
2453 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2454 otherwise, FUNC is 0. */
2456 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2459 /* 1 if N is a possible register number for a function value.
2460 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2461 Currently, R2 and F0 are only implemented here (C has no complex type) */
2463 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2465 /* 1 if N is a possible register number for function argument passing.
2466 We have no FP argument registers when soft-float. When FP registers
2467 are 32 bits, we can't directly reference the odd numbered ones. */
2469 #define FUNCTION_ARG_REGNO_P(N) \
2470 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2471 || ((! TARGET_SOFT_FLOAT \
2472 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2473 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2474 && ! fixed_regs[N]))
2476 /* A C expression which can inhibit the returning of certain function
2477 values in registers, based on the type of value. A nonzero value says
2478 to return the function value in memory, just as large structures are
2479 always returned. Here TYPE will be a C expression of type
2480 `tree', representing the data type of the value.
2482 Note that values of mode `BLKmode' must be explicitly
2483 handled by this macro. Also, the option `-fpcc-struct-return'
2484 takes effect regardless of this macro. On most systems, it is
2485 possible to leave the macro undefined; this causes a default
2486 definition to be used, whose value is the constant 1 for BLKmode
2487 values, and 0 otherwise.
2489 GCC normally converts 1 byte structures into chars, 2 byte
2490 structs into shorts, and 4 byte structs into ints, and returns
2491 them this way. Defining the following macro overrides this,
2492 to give us MIPS cc compatibility. */
2494 #define RETURN_IN_MEMORY(TYPE) \
2495 (TYPE_MODE (TYPE) == BLKmode)
2497 /* A code distinguishing the floating point format of the target
2498 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2499 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2501 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2504 /* Define a data type for recording info about an argument list
2505 during the scan of that argument list. This data type should
2506 hold all necessary information about the function itself
2507 and about the args processed so far, enough to enable macros
2508 such as FUNCTION_ARG to determine where the next arg should go.
2510 On the mips16, we need to keep track of which floating point
2511 arguments were passed in general registers, but would have been
2512 passed in the FP regs if this were a 32 bit function, so that we
2513 can move them to the FP regs if we wind up calling a 32 bit
2514 function. We record this information in fp_code, encoded in base
2515 four. A zero digit means no floating point argument, a one digit
2516 means an SFmode argument, and a two digit means a DFmode argument,
2517 and a three digit is not used. The low order digit is the first
2518 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2519 an SFmode argument. ??? A more sophisticated approach will be
2520 needed if MIPS_ABI != ABI_32. */
2522 typedef struct mips_args {
2523 int gp_reg_found; /* whether a gp register was found yet */
2524 unsigned int arg_number; /* argument number */
2525 unsigned int arg_words; /* # total words the arguments take */
2526 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2527 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2528 int fp_code; /* Mode of FP arguments (mips16) */
2529 unsigned int num_adjusts; /* number of adjustments made */
2530 /* Adjustments made to args pass in regs. */
2531 /* ??? The size is doubled to work around a
2532 bug in the code that sets the adjustments
2534 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2537 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2538 for a call to a function whose data type is FNTYPE.
2539 For a library call, FNTYPE is 0.
2543 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2544 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2546 /* Update the data in CUM to advance over an argument
2547 of mode MODE and data type TYPE.
2548 (TYPE is null for libcalls where that information may not be available.) */
2550 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2551 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2553 /* Determine where to put an argument to a function.
2554 Value is zero to push the argument on the stack,
2555 or a hard register in which to store the argument.
2557 MODE is the argument's machine mode.
2558 TYPE is the data type of the argument (as a tree).
2559 This is null for libcalls where that information may
2561 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2562 the preceding args and about the function being called.
2563 NAMED is nonzero if this argument is a named parameter
2564 (otherwise it is an extra parameter matching an ellipsis). */
2566 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2567 function_arg( &CUM, MODE, TYPE, NAMED)
2569 /* For an arg passed partly in registers and partly in memory,
2570 this is the number of registers used.
2571 For args passed entirely in registers or entirely in memory, zero. */
2573 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2574 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2576 /* If defined, a C expression that gives the alignment boundary, in
2577 bits, of an argument with the specified mode and type. If it is
2578 not defined, `PARM_BOUNDARY' is used for all arguments. */
2580 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2582 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2584 : TYPE_ALIGN(TYPE)) \
2585 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2587 : GET_MODE_ALIGNMENT(MODE)))
2590 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2592 #define MUST_SAVE_REGISTER(regno) \
2593 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2594 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2595 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2597 /* ALIGN FRAMES on double word boundaries */
2598 #ifndef MIPS_STACK_ALIGN
2599 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2603 /* Define the `__builtin_va_list' type for the ABI. */
2604 #define BUILD_VA_LIST_TYPE(VALIST) \
2605 (VALIST) = mips_build_va_list ()
2607 /* Implement `va_start' for varargs and stdarg. */
2608 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2609 mips_va_start (stdarg, valist, nextarg)
2611 /* Implement `va_arg'. */
2612 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2613 mips_va_arg (valist, type)
2615 /* Output assembler code to FILE to increment profiler label # LABELNO
2616 for profiling a function entry. */
2618 #define FUNCTION_PROFILER(FILE, LABELNO) \
2620 if (TARGET_MIPS16) \
2621 sorry ("mips16 function profiling"); \
2622 fprintf (FILE, "\t.set\tnoreorder\n"); \
2623 fprintf (FILE, "\t.set\tnoat\n"); \
2624 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2625 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2626 fprintf (FILE, "\tjal\t_mcount\n"); \
2628 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2629 TARGET_64BIT ? "dsubu" : "subu", \
2630 reg_names[STACK_POINTER_REGNUM], \
2631 reg_names[STACK_POINTER_REGNUM], \
2632 Pmode == DImode ? 16 : 8); \
2633 fprintf (FILE, "\t.set\treorder\n"); \
2634 fprintf (FILE, "\t.set\tat\n"); \
2637 /* Define this macro if the code for function profiling should come
2638 before the function prologue. Normally, the profiling code comes
2641 /* #define PROFILE_BEFORE_PROLOGUE */
2643 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2644 the stack pointer does not matter. The value is tested only in
2645 functions that have frame pointers.
2646 No definition is equivalent to always zero. */
2648 #define EXIT_IGNORE_STACK 1
2651 /* A C statement to output, on the stream FILE, assembler code for a
2652 block of data that contains the constant parts of a trampoline.
2653 This code should not include a label--the label is taken care of
2656 #define TRAMPOLINE_TEMPLATE(STREAM) \
2658 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2659 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2660 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2661 if (Pmode == DImode) \
2663 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2664 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2668 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2669 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2671 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2672 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2673 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2674 if (Pmode == DImode) \
2676 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2677 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2681 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2682 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2686 /* A C expression for the size in bytes of the trampoline, as an
2689 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2691 /* Alignment required for trampolines, in bits. */
2693 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2695 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2696 program and data caches. */
2698 #ifndef CACHE_FLUSH_FUNC
2699 #define CACHE_FLUSH_FUNC "_flush_cache"
2702 /* A C statement to initialize the variable parts of a trampoline.
2703 ADDR is an RTX for the address of the trampoline; FNADDR is an
2704 RTX for the address of the nested function; STATIC_CHAIN is an
2705 RTX for the static chain value that should be passed to the
2706 function when it is called. */
2708 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2711 if (Pmode == DImode) \
2713 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2714 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2718 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2719 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2722 /* Flush both caches. We need to flush the data cache in case \
2723 the system has a write-back cache. */ \
2724 /* ??? Should check the return value for errors. */ \
2725 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2726 0, VOIDmode, 3, addr, Pmode, \
2727 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2728 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2731 /* Addressing modes, and classification of registers for them. */
2733 /* #define HAVE_POST_INCREMENT 0 */
2734 /* #define HAVE_POST_DECREMENT 0 */
2736 /* #define HAVE_PRE_DECREMENT 0 */
2737 /* #define HAVE_PRE_INCREMENT 0 */
2739 /* These assume that REGNO is a hard or pseudo reg number.
2740 They give nonzero only if REGNO is a hard reg of the suitable class
2741 or a pseudo reg currently allocated to a suitable hard reg.
2742 These definitions are NOT overridden anywhere. */
2744 #define BASE_REG_P(regno, mode) \
2746 ? (M16_REG_P (regno) \
2747 || (regno) == FRAME_POINTER_REGNUM \
2748 || (regno) == ARG_POINTER_REGNUM \
2749 || ((regno) == STACK_POINTER_REGNUM \
2750 && (GET_MODE_SIZE (mode) == 4 \
2751 || GET_MODE_SIZE (mode) == 8))) \
2754 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2755 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2758 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2759 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2761 #define REGNO_OK_FOR_INDEX_P(regno) 0
2762 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2763 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2765 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2766 and check its validity for a certain class.
2767 We have two alternate definitions for each of them.
2768 The usual definition accepts all pseudo regs; the other rejects them all.
2769 The symbol REG_OK_STRICT causes the latter definition to be used.
2771 Most source files want to accept pseudo regs in the hope that
2772 they will get allocated to the class that the insn wants them to be in.
2773 Some source files that are used after register allocation
2774 need to be strict. */
2776 #ifndef REG_OK_STRICT
2777 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2778 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2780 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2781 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2784 #define REG_OK_FOR_INDEX_P(X) 0
2787 /* Maximum number of registers that can appear in a valid memory address. */
2789 #define MAX_REGS_PER_ADDRESS 1
2791 /* A C compound statement with a conditional `goto LABEL;' executed
2792 if X (an RTX) is a legitimate memory address on the target
2793 machine for a memory operand of mode MODE.
2795 It usually pays to define several simpler macros to serve as
2796 subroutines for this one. Otherwise it may be too complicated
2799 This macro must exist in two variants: a strict variant and a
2800 non-strict one. The strict variant is used in the reload pass.
2801 It must be defined so that any pseudo-register that has not been
2802 allocated a hard register is considered a memory reference. In
2803 contexts where some kind of register is required, a
2804 pseudo-register with no hard register must be rejected.
2806 The non-strict variant is used in other passes. It must be
2807 defined to accept all pseudo-registers in every context where
2808 some kind of register is required.
2810 Compiler source files that want to use the strict variant of
2811 this macro define the macro `REG_OK_STRICT'. You should use an
2812 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2813 in that case and the non-strict variant otherwise.
2815 Typically among the subroutines used to define
2816 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2817 acceptable registers for various purposes (one for base
2818 registers, one for index registers, and so on). Then only these
2819 subroutine macros need have two variants; the higher levels of
2820 macros may be the same whether strict or not.
2822 Normally, constant addresses which are the sum of a `symbol_ref'
2823 and an integer are stored inside a `const' RTX to mark them as
2824 constant. Therefore, there is no need to recognize such sums
2825 specifically as legitimate addresses. Normally you would simply
2826 recognize any `const' as legitimate.
2828 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2829 constant sums that are not marked with `const'. It assumes
2830 that a naked `plus' indicates indexing. If so, then you *must*
2831 reject such naked constant sums as illegitimate addresses, so
2832 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2834 On some machines, whether a symbolic address is legitimate
2835 depends on the section that the address refers to. On these
2836 machines, define the macro `ENCODE_SECTION_INFO' to store the
2837 information into the `symbol_ref', and then check for it here.
2838 When you see a `const', you will have to look inside it to find
2839 the `symbol_ref' in order to determine the section. */
2842 #define GO_PRINTF(x) fprintf(stderr, (x))
2843 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2844 #define GO_DEBUG_RTX(x) debug_rtx(x)
2847 #define GO_PRINTF(x)
2848 #define GO_PRINTF2(x,y)
2849 #define GO_DEBUG_RTX(x)
2852 #ifdef REG_OK_STRICT
2853 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2855 if (mips_legitimate_address_p (MODE, X, 1)) \
2859 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2861 if (mips_legitimate_address_p (MODE, X, 0)) \
2866 /* A C expression that is 1 if the RTX X is a constant which is a
2867 valid address. This is defined to be the same as `CONSTANT_P (X)',
2868 but rejecting CONST_DOUBLE. */
2869 /* When pic, we must reject addresses of the form symbol+large int.
2870 This is because an instruction `sw $4,s+70000' needs to be converted
2871 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2872 assembler would use $at as a temp to load in the large offset. In this
2873 case $at is already in use. We convert such problem addresses to
2874 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2875 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2876 #define CONSTANT_ADDRESS_P(X) \
2877 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2878 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2879 || (GET_CODE (X) == CONST \
2880 && ! (flag_pic && pic_address_needs_scratch (X)) \
2881 && (mips_abi == ABI_32 \
2882 || mips_abi == ABI_O64 \
2883 || mips_abi == ABI_EABI))) \
2884 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2886 /* Define this, so that when PIC, reload won't try to reload invalid
2887 addresses which require two reload registers. */
2889 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2891 /* Nonzero if the constant value X is a legitimate general operand.
2892 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2894 At present, GAS doesn't understand li.[sd], so don't allow it
2895 to be generated at present. Also, the MIPS assembler does not
2896 grok li.d Infinity. */
2898 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2899 Note that the Irix 6 assembler problem may already be fixed.
2900 Note also that the GET_CODE (X) == CONST test catches the mips16
2901 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2902 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2903 ABI_64 to work together, we'll need to fix this. */
2904 #define LEGITIMATE_CONSTANT_P(X) \
2905 ((GET_CODE (X) != CONST_DOUBLE \
2906 || mips_const_double_ok (X, GET_MODE (X))) \
2907 && ! (GET_CODE (X) == CONST \
2909 && (mips_abi == ABI_N32 \
2910 || mips_abi == ABI_64)) \
2911 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2913 /* A C compound statement that attempts to replace X with a valid
2914 memory address for an operand of mode MODE. WIN will be a C
2915 statement label elsewhere in the code; the macro definition may
2918 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2920 to avoid further processing if the address has become legitimate.
2922 X will always be the result of a call to `break_out_memory_refs',
2923 and OLDX will be the operand that was given to that function to
2926 The code generated by this macro should not alter the
2927 substructure of X. If it transforms X into a more legitimate
2928 form, it should assign X (which will always be a C variable) a
2931 It is not necessary for this macro to come up with a legitimate
2932 address. The compiler has standard ways of doing so in all
2933 cases. In fact, it is safe for this macro to do nothing. But
2934 often a machine-dependent strategy can generate better code.
2936 For the MIPS, transform:
2938 memory(X + <large int>)
2942 Y = <large int> & ~0x7fff;
2944 memory (Z + (<large int> & 0x7fff));
2946 This is for CSE to find several similar references, and only use one Z.
2948 When PIC, convert addresses of the form memory (symbol+large int) to
2949 memory (reg+large int). */
2952 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2954 register rtx xinsn = (X); \
2956 if (TARGET_DEBUG_B_MODE) \
2958 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2959 GO_DEBUG_RTX (xinsn); \
2962 if (mips_split_addresses && mips_check_split (X, MODE)) \
2964 /* ??? Is this ever executed? */ \
2965 X = gen_rtx_LO_SUM (Pmode, \
2966 copy_to_mode_reg (Pmode, \
2967 gen_rtx (HIGH, Pmode, X)), \
2972 if (GET_CODE (xinsn) == CONST \
2973 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2974 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2975 || (mips_abi != ABI_32 \
2976 && mips_abi != ABI_O64 \
2977 && mips_abi != ABI_EABI))) \
2979 rtx ptr_reg = gen_reg_rtx (Pmode); \
2980 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2982 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2984 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
2985 if (SMALL_INT (constant)) \
2987 /* Otherwise we fall through so the code below will fix the \
2992 if (GET_CODE (xinsn) == PLUS) \
2994 register rtx xplus0 = XEXP (xinsn, 0); \
2995 register rtx xplus1 = XEXP (xinsn, 1); \
2996 register enum rtx_code code0 = GET_CODE (xplus0); \
2997 register enum rtx_code code1 = GET_CODE (xplus1); \
2999 if (code0 != REG && code1 == REG) \
3001 xplus0 = XEXP (xinsn, 1); \
3002 xplus1 = XEXP (xinsn, 0); \
3003 code0 = GET_CODE (xplus0); \
3004 code1 = GET_CODE (xplus1); \
3007 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3008 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3010 rtx int_reg = gen_reg_rtx (Pmode); \
3011 rtx ptr_reg = gen_reg_rtx (Pmode); \
3013 emit_move_insn (int_reg, \
3014 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3016 emit_insn (gen_rtx_SET (VOIDmode, \
3018 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3020 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3025 if (TARGET_DEBUG_B_MODE) \
3026 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3030 /* A C statement or compound statement with a conditional `goto
3031 LABEL;' executed if memory address X (an RTX) can have different
3032 meanings depending on the machine mode of the memory reference it
3035 Autoincrement and autodecrement addresses typically have
3036 mode-dependent effects because the amount of the increment or
3037 decrement is the size of the operand being addressed. Some
3038 machines have other mode-dependent addresses. Many RISC machines
3039 have no mode-dependent addresses.
3041 You may assume that ADDR is a valid address for the machine. */
3043 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3046 /* Define this macro if references to a symbol must be treated
3047 differently depending on something about the variable or
3048 function named by the symbol (such as what section it is in).
3050 The macro definition, if any, is executed immediately after the
3051 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3052 The value of the rtl will be a `mem' whose address is a
3055 The usual thing for this macro to do is to a flag in the
3056 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3057 name string in the `symbol_ref' (if one bit is not enough
3060 The best way to modify the name string is by adding text to the
3061 beginning, with suitable punctuation to prevent any ambiguity.
3062 Allocate the new name in `saveable_obstack'. You will have to
3063 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3064 and output the name accordingly.
3066 You can also check the information stored in the `symbol_ref' in
3067 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3068 `PRINT_OPERAND_ADDRESS'.
3070 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3073 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3074 symbols which are not in the .text section.
3076 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3077 constants which are put in the .text section. We also record the
3078 total length of all such strings; this total is used to decide
3079 whether we need to split the constant table, and need not be
3082 When not mips16 code nor embedded PIC, if a symbol is in a
3083 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3084 splitting the reference so that gas can generate a gp relative
3087 When TARGET_EMBEDDED_DATA is set, we assume that all const
3088 variables will be stored in ROM, which is too far from %gp to use
3089 %gprel addressing. Note that (1) we include "extern const"
3090 variables in this, which mips_select_section doesn't, and (2) we
3091 can't always tell if they're really const (they might be const C++
3092 objects with non-const constructors), so we err on the side of
3093 caution and won't use %gprel anyway (otherwise we'd have to defer
3094 this decision to the linker/loader). The handling of extern consts
3095 is why the DECL_INITIAL macros differ from mips_select_section.
3097 If you are changing this macro, you should look at
3098 mips_select_section and see if it needs a similar change. */
3100 #ifndef UNIQUE_SECTION_P
3101 #define UNIQUE_SECTION_P(DECL) (0)
3104 #define ENCODE_SECTION_INFO(DECL) \
3107 if (TARGET_MIPS16) \
3109 if (TREE_CODE (DECL) == STRING_CST \
3110 && ! flag_writable_strings \
3111 /* If this string is from a function, and the function will \
3112 go in a gnu linkonce section, then we can't directly \
3113 access the string. This gets an assembler error \
3114 "unsupported PC relative reference to different section".\
3115 If we modify SELECT_SECTION to put it in function_section\
3116 instead of text_section, it still fails because \
3117 DECL_SECTION_NAME isn't set until assemble_start_function.\
3118 If we fix that, it still fails because strings are shared\
3119 among multiple functions, and we have cross section \
3120 references again. We force it to work by putting string \
3121 addresses in the constant pool and indirecting. */ \
3122 && (! current_function_decl \
3123 || ! UNIQUE_SECTION_P (current_function_decl))) \
3125 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3126 mips_string_length += TREE_STRING_LENGTH (DECL); \
3130 if (TARGET_EMBEDDED_DATA \
3131 && (TREE_CODE (DECL) == VAR_DECL \
3132 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3133 && (!DECL_INITIAL (DECL) \
3134 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3136 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3139 else if (TARGET_EMBEDDED_PIC) \
3141 if (TREE_CODE (DECL) == VAR_DECL) \
3142 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3143 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3144 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3145 else if (TREE_CODE (DECL) == STRING_CST \
3146 && ! flag_writable_strings) \
3147 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3149 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3152 else if (TREE_CODE (DECL) == VAR_DECL \
3153 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3154 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3156 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3159 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3162 /* We can not perform GP optimizations on variables which are in \
3163 specific sections, except for .sdata and .sbss which are \
3165 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3166 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3168 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3170 if (size > 0 && size <= mips_section_threshold) \
3171 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3174 else if (HALF_PIC_P ()) \
3176 HALF_PIC_ENCODE (DECL); \
3181 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3182 'the start of the function that this code is output in'. */
3184 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3185 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3186 asm_fprintf ((FILE), "%U%s", \
3187 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3189 asm_fprintf ((FILE), "%U%s", (NAME))
3191 /* The mips16 wants the constant pool to be after the function,
3192 because the PC relative load instructions use unsigned offsets. */
3194 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3196 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3197 mips_string_length = 0;
3200 /* In mips16 mode, put most string constants after the function. */
3201 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3202 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3205 /* Specify the machine mode that this machine uses
3206 for the index in the tablejump instruction.
3207 ??? Using HImode in mips16 mode can cause overflow. However, the
3208 overflow is no more likely than the overflow in a branch
3209 instruction. Large functions can currently break in both ways. */
3210 #define CASE_VECTOR_MODE \
3211 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3213 /* Define as C expression which evaluates to nonzero if the tablejump
3214 instruction expects the table to contain offsets from the address of the
3216 Do not define this if the table should contain absolute addresses. */
3217 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3219 /* Specify the tree operation to be used to convert reals to integers. */
3220 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3222 /* This is the kind of divide that is easiest to do in the general case. */
3223 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3225 /* Define this as 1 if `char' should by default be signed; else as 0. */
3226 #ifndef DEFAULT_SIGNED_CHAR
3227 #define DEFAULT_SIGNED_CHAR 1
3230 /* Max number of bytes we can move from memory to memory
3231 in one reasonably fast instruction. */
3232 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3233 #define MAX_MOVE_MAX 8
3235 /* Define this macro as a C expression which is nonzero if
3236 accessing less than a word of memory (i.e. a `char' or a
3237 `short') is no faster than accessing a word of memory, i.e., if
3238 such access require more than one instruction or if there is no
3239 difference in cost between byte and (aligned) word loads.
3241 On RISC machines, it tends to generate better code to define
3242 this as 1, since it avoids making a QI or HI mode register. */
3243 #define SLOW_BYTE_ACCESS 1
3245 /* We assume that the store-condition-codes instructions store 0 for false
3246 and some other value for true. This is the value stored for true. */
3248 #define STORE_FLAG_VALUE 1
3250 /* Define this if zero-extension is slow (more than one real instruction). */
3251 #define SLOW_ZERO_EXTEND
3253 /* Define this to be nonzero if shift instructions ignore all but the low-order
3255 #define SHIFT_COUNT_TRUNCATED 1
3257 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3258 is done just by pretending it is already truncated. */
3259 /* In 64 bit mode, 32 bit instructions require that register values be properly
3260 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3261 converts a value >32 bits to a value <32 bits. */
3262 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3263 Something needs to be done about this. Perhaps not use any 32 bit
3264 instructions? Perhaps use PROMOTE_MODE? */
3265 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3266 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3268 /* Specify the machine mode that pointers have.
3269 After generation of rtl, the compiler makes no further distinction
3270 between pointers and any other objects of this machine mode.
3272 For MIPS we make pointers are the smaller of longs and gp-registers. */
3275 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3278 /* A function address in a call instruction
3279 is a word address (for indexing purposes)
3280 so give the MEM rtx a words's mode. */
3282 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3284 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3285 memset, instead of the BSD functions bcopy and bzero. */
3287 #if defined(MIPS_SYSV) || defined(OSF_OS)
3288 #define TARGET_MEM_FUNCTIONS
3292 /* A part of a C `switch' statement that describes the relative
3293 costs of constant RTL expressions. It must contain `case'
3294 labels for expression codes `const_int', `const', `symbol_ref',
3295 `label_ref' and `const_double'. Each case must ultimately reach
3296 a `return' statement to return the relative cost of the use of
3297 that kind of constant value in an expression. The cost may
3298 depend on the precise value of the constant, which is available
3299 for examination in X.
3301 CODE is the expression code--redundant, since it can be obtained
3302 with `GET_CODE (X)'. */
3304 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3306 if (! TARGET_MIPS16) \
3308 /* Always return 0, since we don't have different sized \
3309 instructions, hence different costs according to Richard \
3313 if ((OUTER_CODE) == SET) \
3315 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3317 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3318 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3319 return COSTS_N_INSNS (1); \
3321 return COSTS_N_INSNS (2); \
3323 /* A PLUS could be an address. We don't want to force an address \
3324 to use a register, so accept any signed 16 bit value without \
3326 if ((OUTER_CODE) == PLUS \
3327 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3329 /* A number between 1 and 8 inclusive is efficient for a shift. \
3330 Otherwise, we will need an extended instruction. */ \
3331 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3332 || (OUTER_CODE) == LSHIFTRT) \
3334 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3336 return COSTS_N_INSNS (1); \
3338 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3339 if ((OUTER_CODE) == XOR \
3340 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3342 /* We may be able to use slt or sltu for a comparison with a \
3343 signed 16 bit value. (The boundary conditions aren't quite \
3344 right, but this is just a heuristic anyhow.) */ \
3345 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3346 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3347 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3348 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3349 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3351 /* Equality comparisons with 0 are cheap. */ \
3352 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3353 && INTVAL (X) == 0) \
3356 /* Otherwise, work out the cost to load the value into a \
3358 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3359 return COSTS_N_INSNS (1); \
3360 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3361 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3362 return COSTS_N_INSNS (2); \
3364 return COSTS_N_INSNS (3); \
3367 return COSTS_N_INSNS (2); \
3371 rtx offset = const0_rtx; \
3372 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3374 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3376 /* Treat this like a signed 16 bit CONST_INT. */ \
3377 if ((OUTER_CODE) == PLUS) \
3379 else if ((OUTER_CODE) == SET) \
3380 return COSTS_N_INSNS (1); \
3382 return COSTS_N_INSNS (2); \
3385 if (GET_CODE (symref) == LABEL_REF) \
3386 return COSTS_N_INSNS (2); \
3388 if (GET_CODE (symref) != SYMBOL_REF) \
3389 return COSTS_N_INSNS (4); \
3391 /* let's be paranoid.... */ \
3392 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3393 return COSTS_N_INSNS (2); \
3395 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3399 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3401 case CONST_DOUBLE: \
3404 if (TARGET_MIPS16) \
3405 return COSTS_N_INSNS (4); \
3406 split_double (X, &high, &low); \
3407 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3408 || low == CONST0_RTX (GET_MODE (low))) \
3412 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3413 This can be used, for example, to indicate how costly a multiply
3414 instruction is. In writing this macro, you can use the construct
3415 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3417 This macro is optional; do not define it if the default cost
3418 assumptions are adequate for the target machine.
3420 If -mdebugd is used, change the multiply cost to 2, so multiply by
3421 a constant isn't converted to a series of shifts. This helps
3422 strength reduction, and also makes it easier to identify what the
3423 compiler is doing. */
3425 /* ??? Fix this to be right for the R8000. */
3426 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3429 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3430 if (simple_memory_operand (X, GET_MODE (X))) \
3431 return COSTS_N_INSNS (num_words); \
3433 return COSTS_N_INSNS (2*num_words); \
3437 return COSTS_N_INSNS (6); \
3440 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3445 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3446 return COSTS_N_INSNS (2); \
3453 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3454 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3460 enum machine_mode xmode = GET_MODE (X); \
3461 if (xmode == SFmode || xmode == DFmode) \
3462 return COSTS_N_INSNS (1); \
3464 return COSTS_N_INSNS (4); \
3470 enum machine_mode xmode = GET_MODE (X); \
3471 if (xmode == SFmode || xmode == DFmode) \
3475 return COSTS_N_INSNS (2); \
3476 else if (TUNE_MIPS6000) \
3477 return COSTS_N_INSNS (3); \
3479 return COSTS_N_INSNS (6); \
3482 if (xmode == DImode && !TARGET_64BIT) \
3483 return COSTS_N_INSNS (4); \
3489 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3496 enum machine_mode xmode = GET_MODE (X); \
3497 if (xmode == SFmode) \
3502 return COSTS_N_INSNS (4); \
3503 else if (TUNE_MIPS6000) \
3504 return COSTS_N_INSNS (5); \
3506 return COSTS_N_INSNS (7); \
3509 if (xmode == DFmode) \
3514 return COSTS_N_INSNS (5); \
3515 else if (TUNE_MIPS6000) \
3516 return COSTS_N_INSNS (6); \
3518 return COSTS_N_INSNS (8); \
3521 if (TUNE_MIPS3000) \
3522 return COSTS_N_INSNS (12); \
3523 else if (TUNE_MIPS3900) \
3524 return COSTS_N_INSNS (2); \
3525 else if (TUNE_MIPS6000) \
3526 return COSTS_N_INSNS (17); \
3527 else if (TUNE_MIPS5000) \
3528 return COSTS_N_INSNS (5); \
3530 return COSTS_N_INSNS (10); \
3536 enum machine_mode xmode = GET_MODE (X); \
3537 if (xmode == SFmode) \
3541 return COSTS_N_INSNS (12); \
3542 else if (TUNE_MIPS6000) \
3543 return COSTS_N_INSNS (15); \
3545 return COSTS_N_INSNS (23); \
3548 if (xmode == DFmode) \
3552 return COSTS_N_INSNS (19); \
3553 else if (TUNE_MIPS6000) \
3554 return COSTS_N_INSNS (16); \
3556 return COSTS_N_INSNS (36); \
3559 /* fall through */ \
3565 return COSTS_N_INSNS (35); \
3566 else if (TUNE_MIPS6000) \
3567 return COSTS_N_INSNS (38); \
3568 else if (TUNE_MIPS5000) \
3569 return COSTS_N_INSNS (36); \
3571 return COSTS_N_INSNS (69); \
3574 /* A sign extend from SImode to DImode in 64 bit mode is often \
3575 zero instructions, because the result can often be used \
3576 directly by another instruction; we'll call it one. */ \
3577 if (TARGET_64BIT && GET_MODE (X) == DImode \
3578 && GET_MODE (XEXP (X, 0)) == SImode) \
3579 return COSTS_N_INSNS (1); \
3581 return COSTS_N_INSNS (2); \
3584 if (TARGET_64BIT && GET_MODE (X) == DImode \
3585 && GET_MODE (XEXP (X, 0)) == SImode) \
3586 return COSTS_N_INSNS (2); \
3588 return COSTS_N_INSNS (1);
3590 /* An expression giving the cost of an addressing mode that
3591 contains ADDRESS. If not defined, the cost is computed from the
3592 form of the ADDRESS expression and the `CONST_COSTS' values.
3594 For most CISC machines, the default cost is a good approximation
3595 of the true cost of the addressing mode. However, on RISC
3596 machines, all instructions normally have the same length and
3597 execution time. Hence all addresses will have equal costs.
3599 In cases where more than one form of an address is known, the
3600 form with the lowest cost will be used. If multiple forms have
3601 the same, lowest, cost, the one that is the most complex will be
3604 For example, suppose an address that is equal to the sum of a
3605 register and a constant is used twice in the same basic block.
3606 When this macro is not defined, the address will be computed in
3607 a register and memory references will be indirect through that
3608 register. On machines where the cost of the addressing mode
3609 containing the sum is no higher than that of a simple indirect
3610 reference, this will produce an additional instruction and
3611 possibly require an additional register. Proper specification
3612 of this macro eliminates this overhead for such machines.
3614 Similar use of this macro is made in strength reduction of loops.
3616 ADDRESS need not be valid as an address. In such a case, the
3617 cost is not relevant and can be any value; invalid addresses
3618 need not be assigned a different cost.
3620 On machines where an address involving more than one register is
3621 as cheap as an address computation involving only one register,
3622 defining `ADDRESS_COST' to reflect this can cause two registers
3623 to be live over a region of code where only one would have been
3624 if `ADDRESS_COST' were not defined in that manner. This effect
3625 should be considered in the definition of this macro.
3626 Equivalent costs should probably only be given to addresses with
3627 different numbers of registers on machines with lots of registers.
3629 This macro will normally either not be defined or be defined as
3632 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3634 /* A C expression for the cost of moving data from a register in
3635 class FROM to one in class TO. The classes are expressed using
3636 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3637 the default; other values are interpreted relative to that.
3639 It is not required that the cost always equal 2 when FROM is the
3640 same as TO; on some machines it is expensive to move between
3641 registers if they are not general registers.
3643 If reload sees an insn consisting of a single `set' between two
3644 hard registers, and if `REGISTER_MOVE_COST' applied to their
3645 classes returns a value of 2, reload does not check to ensure
3646 that the constraints of the insn are met. Setting a cost of
3647 other than 2 will allow reload to verify that the constraints are
3648 met. You should do this if the `movM' pattern's constraints do
3649 not allow such copying.
3651 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3652 registers the same as for one of moving general registers to
3653 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3654 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3655 isn't clear if it is wise. And it might not work in all cases. We
3656 could solve the DImode LO reg problem by using a multiply, just like
3657 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3658 by using divide instructions. divu puts the remainder in the HI
3659 reg, so doing a divide by -1 will move the value in the HI reg for
3660 all values except -1. We could handle that case by using a signed
3661 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3662 compare/branch to test the input value to see which instruction we
3663 need to use. This gets pretty messy, but it is feasible. */
3665 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3666 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3667 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3668 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3669 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3670 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3671 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3672 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3673 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3674 : (((FROM) == HI_REG || (FROM) == LO_REG \
3675 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3676 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3677 : (((TO) == HI_REG || (TO) == LO_REG \
3678 || (TO) == MD_REGS || (TO) == HILO_REG) \
3679 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3680 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3681 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3684 /* ??? Fix this to be right for the R8000. */
3685 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3686 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3687 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3689 /* Define if copies to/from condition code registers should be avoided.
3691 This is needed for the MIPS because reload_outcc is not complete;
3692 it needs to handle cases where the source is a general or another
3693 condition code register. */
3694 #define AVOID_CCMODE_COPIES
3696 /* A C expression for the cost of a branch instruction. A value of
3697 1 is the default; other values are interpreted relative to that. */
3699 /* ??? Fix this to be right for the R8000. */
3700 #define BRANCH_COST \
3702 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3705 /* A C statement (sans semicolon) to update the integer variable COST
3706 based on the relationship between INSN that is dependent on
3707 DEP_INSN through the dependence LINK. The default is to make no
3708 adjustment to COST. On the MIPS, ignore the cost of anti- and
3709 output-dependencies. */
3711 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3712 if (REG_NOTE_KIND (LINK) != 0) \
3713 (COST) = 0; /* Anti or output dependence. */
3715 /* If defined, modifies the length assigned to instruction INSN as a
3716 function of the context in which it is used. LENGTH is an lvalue
3717 that contains the initially computed length of the insn and should
3718 be updated with the correct length of the insn. */
3719 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3720 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3723 /* Optionally define this if you have added predicates to
3724 `MACHINE.c'. This macro is called within an initializer of an
3725 array of structures. The first field in the structure is the
3726 name of a predicate and the second field is an array of rtl
3727 codes. For each predicate, list all rtl codes that can be in
3728 expressions matched by the predicate. The list should have a
3729 trailing comma. Here is an example of two entries in the list
3730 for a typical RISC machine:
3732 #define PREDICATE_CODES \
3733 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3734 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3736 Defining this macro does not affect the generated code (however,
3737 incorrect definitions that omit an rtl code that may be matched
3738 by the predicate can cause the compiler to malfunction).
3739 Instead, it allows the table built by `genrecog' to be more
3740 compact and efficient, thus speeding up the compiler. The most
3741 important predicates to include in the list specified by this
3742 macro are thoses used in the most insn patterns. */
3744 #define PREDICATE_CODES \
3745 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3746 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3747 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3748 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3749 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3750 {"small_int", { CONST_INT }}, \
3751 {"large_int", { CONST_INT }}, \
3752 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3753 {"const_float_1_operand", { CONST_DOUBLE }}, \
3754 {"simple_memory_operand", { MEM, SUBREG }}, \
3755 {"equality_op", { EQ, NE }}, \
3756 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3758 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3759 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3760 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3761 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3762 SYMBOL_REF, LABEL_REF, SUBREG, \
3764 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3765 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3766 MEM, SIGN_EXTEND }}, \
3767 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3768 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3770 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3772 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3774 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3775 SYMBOL_REF, LABEL_REF, SUBREG, \
3776 REG, SIGN_EXTEND }}, \
3777 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3778 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3779 CONST_DOUBLE, CONST }}, \
3780 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3781 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3783 /* A list of predicates that do special things with modes, and so
3784 should not elicit warnings for VOIDmode match_operand. */
3786 #define SPECIAL_MODE_PREDICATES \
3787 "pc_or_label_operand",
3790 /* If defined, a C statement to be executed just prior to the
3791 output of assembler code for INSN, to modify the extracted
3792 operands so they will be output differently.
3794 Here the argument OPVEC is the vector containing the operands
3795 extracted from INSN, and NOPERANDS is the number of elements of
3796 the vector which contain meaningful data for this insn. The
3797 contents of this vector are what will be used to convert the
3798 insn template into assembler code, so you can change the
3799 assembler output by changing the contents of the vector.
3801 We use it to check if the current insn needs a nop in front of it
3802 because of load delays, and also to update the delay slot
3805 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3806 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3809 /* Control the assembler format that we output. */
3811 /* Output at beginning of assembler file.
3812 If we are optimizing to use the global pointer, create a temporary
3813 file to hold all of the text stuff, and write it out to the end.
3814 This is needed because the MIPS assembler is evidently one pass,
3815 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3816 declaration when the code is processed, it generates a two
3817 instruction sequence. */
3819 #undef ASM_FILE_START
3820 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3822 /* Output to assembler file text saying following lines
3823 may contain character constants, extra white space, comments, etc. */
3825 #define ASM_APP_ON " #APP\n"
3827 /* Output to assembler file text saying following lines
3828 no longer contain unusual constructs. */
3830 #define ASM_APP_OFF " #NO_APP\n"
3832 /* How to refer to registers in assembler output.
3833 This sequence is indexed by compiler's hard-register-number (see above).
3835 In order to support the two different conventions for register names,
3836 we use the name of a table set up in mips.c, which is overwritten
3837 if -mrnames is used. */
3839 #define REGISTER_NAMES \
3841 &mips_reg_names[ 0][0], \
3842 &mips_reg_names[ 1][0], \
3843 &mips_reg_names[ 2][0], \
3844 &mips_reg_names[ 3][0], \
3845 &mips_reg_names[ 4][0], \
3846 &mips_reg_names[ 5][0], \
3847 &mips_reg_names[ 6][0], \
3848 &mips_reg_names[ 7][0], \
3849 &mips_reg_names[ 8][0], \
3850 &mips_reg_names[ 9][0], \
3851 &mips_reg_names[10][0], \
3852 &mips_reg_names[11][0], \
3853 &mips_reg_names[12][0], \
3854 &mips_reg_names[13][0], \
3855 &mips_reg_names[14][0], \
3856 &mips_reg_names[15][0], \
3857 &mips_reg_names[16][0], \
3858 &mips_reg_names[17][0], \
3859 &mips_reg_names[18][0], \
3860 &mips_reg_names[19][0], \
3861 &mips_reg_names[20][0], \
3862 &mips_reg_names[21][0], \
3863 &mips_reg_names[22][0], \
3864 &mips_reg_names[23][0], \
3865 &mips_reg_names[24][0], \
3866 &mips_reg_names[25][0], \
3867 &mips_reg_names[26][0], \
3868 &mips_reg_names[27][0], \
3869 &mips_reg_names[28][0], \
3870 &mips_reg_names[29][0], \
3871 &mips_reg_names[30][0], \
3872 &mips_reg_names[31][0], \
3873 &mips_reg_names[32][0], \
3874 &mips_reg_names[33][0], \
3875 &mips_reg_names[34][0], \
3876 &mips_reg_names[35][0], \
3877 &mips_reg_names[36][0], \
3878 &mips_reg_names[37][0], \
3879 &mips_reg_names[38][0], \
3880 &mips_reg_names[39][0], \
3881 &mips_reg_names[40][0], \
3882 &mips_reg_names[41][0], \
3883 &mips_reg_names[42][0], \
3884 &mips_reg_names[43][0], \
3885 &mips_reg_names[44][0], \
3886 &mips_reg_names[45][0], \
3887 &mips_reg_names[46][0], \
3888 &mips_reg_names[47][0], \
3889 &mips_reg_names[48][0], \
3890 &mips_reg_names[49][0], \
3891 &mips_reg_names[50][0], \
3892 &mips_reg_names[51][0], \
3893 &mips_reg_names[52][0], \
3894 &mips_reg_names[53][0], \
3895 &mips_reg_names[54][0], \
3896 &mips_reg_names[55][0], \
3897 &mips_reg_names[56][0], \
3898 &mips_reg_names[57][0], \
3899 &mips_reg_names[58][0], \
3900 &mips_reg_names[59][0], \
3901 &mips_reg_names[60][0], \
3902 &mips_reg_names[61][0], \
3903 &mips_reg_names[62][0], \
3904 &mips_reg_names[63][0], \
3905 &mips_reg_names[64][0], \
3906 &mips_reg_names[65][0], \
3907 &mips_reg_names[66][0], \
3908 &mips_reg_names[67][0], \
3909 &mips_reg_names[68][0], \
3910 &mips_reg_names[69][0], \
3911 &mips_reg_names[70][0], \
3912 &mips_reg_names[71][0], \
3913 &mips_reg_names[72][0], \
3914 &mips_reg_names[73][0], \
3915 &mips_reg_names[74][0], \
3916 &mips_reg_names[75][0], \
3919 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3920 So define this for it. */
3921 #define DEBUG_REGISTER_NAMES \
3923 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3924 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3925 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3926 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3927 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3928 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3929 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3930 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3931 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3932 "$fcc5","$fcc6","$fcc7","$rap" \
3935 /* If defined, a C initializer for an array of structures
3936 containing a name and a register number. This macro defines
3937 additional names for hard registers, thus allowing the `asm'
3938 option in declarations to refer to registers using alternate
3941 We define both names for the integer registers here. */
3943 #define ADDITIONAL_REGISTER_NAMES \
3945 { "$0", 0 + GP_REG_FIRST }, \
3946 { "$1", 1 + GP_REG_FIRST }, \
3947 { "$2", 2 + GP_REG_FIRST }, \
3948 { "$3", 3 + GP_REG_FIRST }, \
3949 { "$4", 4 + GP_REG_FIRST }, \
3950 { "$5", 5 + GP_REG_FIRST }, \
3951 { "$6", 6 + GP_REG_FIRST }, \
3952 { "$7", 7 + GP_REG_FIRST }, \
3953 { "$8", 8 + GP_REG_FIRST }, \
3954 { "$9", 9 + GP_REG_FIRST }, \
3955 { "$10", 10 + GP_REG_FIRST }, \
3956 { "$11", 11 + GP_REG_FIRST }, \
3957 { "$12", 12 + GP_REG_FIRST }, \
3958 { "$13", 13 + GP_REG_FIRST }, \
3959 { "$14", 14 + GP_REG_FIRST }, \
3960 { "$15", 15 + GP_REG_FIRST }, \
3961 { "$16", 16 + GP_REG_FIRST }, \
3962 { "$17", 17 + GP_REG_FIRST }, \
3963 { "$18", 18 + GP_REG_FIRST }, \
3964 { "$19", 19 + GP_REG_FIRST }, \
3965 { "$20", 20 + GP_REG_FIRST }, \
3966 { "$21", 21 + GP_REG_FIRST }, \
3967 { "$22", 22 + GP_REG_FIRST }, \
3968 { "$23", 23 + GP_REG_FIRST }, \
3969 { "$24", 24 + GP_REG_FIRST }, \
3970 { "$25", 25 + GP_REG_FIRST }, \
3971 { "$26", 26 + GP_REG_FIRST }, \
3972 { "$27", 27 + GP_REG_FIRST }, \
3973 { "$28", 28 + GP_REG_FIRST }, \
3974 { "$29", 29 + GP_REG_FIRST }, \
3975 { "$30", 30 + GP_REG_FIRST }, \
3976 { "$31", 31 + GP_REG_FIRST }, \
3977 { "$sp", 29 + GP_REG_FIRST }, \
3978 { "$fp", 30 + GP_REG_FIRST }, \
3979 { "at", 1 + GP_REG_FIRST }, \
3980 { "v0", 2 + GP_REG_FIRST }, \
3981 { "v1", 3 + GP_REG_FIRST }, \
3982 { "a0", 4 + GP_REG_FIRST }, \
3983 { "a1", 5 + GP_REG_FIRST }, \
3984 { "a2", 6 + GP_REG_FIRST }, \
3985 { "a3", 7 + GP_REG_FIRST }, \
3986 { "t0", 8 + GP_REG_FIRST }, \
3987 { "t1", 9 + GP_REG_FIRST }, \
3988 { "t2", 10 + GP_REG_FIRST }, \
3989 { "t3", 11 + GP_REG_FIRST }, \
3990 { "t4", 12 + GP_REG_FIRST }, \
3991 { "t5", 13 + GP_REG_FIRST }, \
3992 { "t6", 14 + GP_REG_FIRST }, \
3993 { "t7", 15 + GP_REG_FIRST }, \
3994 { "s0", 16 + GP_REG_FIRST }, \
3995 { "s1", 17 + GP_REG_FIRST }, \
3996 { "s2", 18 + GP_REG_FIRST }, \
3997 { "s3", 19 + GP_REG_FIRST }, \
3998 { "s4", 20 + GP_REG_FIRST }, \
3999 { "s5", 21 + GP_REG_FIRST }, \
4000 { "s6", 22 + GP_REG_FIRST }, \
4001 { "s7", 23 + GP_REG_FIRST }, \
4002 { "t8", 24 + GP_REG_FIRST }, \
4003 { "t9", 25 + GP_REG_FIRST }, \
4004 { "k0", 26 + GP_REG_FIRST }, \
4005 { "k1", 27 + GP_REG_FIRST }, \
4006 { "gp", 28 + GP_REG_FIRST }, \
4007 { "sp", 29 + GP_REG_FIRST }, \
4008 { "fp", 30 + GP_REG_FIRST }, \
4009 { "ra", 31 + GP_REG_FIRST }, \
4010 { "$sp", 29 + GP_REG_FIRST }, \
4011 { "$fp", 30 + GP_REG_FIRST } \
4014 /* A C compound statement to output to stdio stream STREAM the
4015 assembler syntax for an instruction operand X. X is an RTL
4018 CODE is a value that can be used to specify one of several ways
4019 of printing the operand. It is used when identical operands
4020 must be printed differently depending on the context. CODE
4021 comes from the `%' specification that was used to request
4022 printing of the operand. If the specification was just `%DIGIT'
4023 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4024 is the ASCII code for LTR.
4026 If X is a register, this macro should print the register's name.
4027 The names can be found in an array `reg_names' whose type is
4028 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4030 When the machine description has a specification `%PUNCT' (a `%'
4031 followed by a punctuation character), this macro is called with
4032 a null pointer for X and the punctuation character for CODE.
4034 See mips.c for the MIPS specific codes. */
4036 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4038 /* A C expression which evaluates to true if CODE is a valid
4039 punctuation character for use in the `PRINT_OPERAND' macro. If
4040 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4041 punctuation characters (except for the standard one, `%') are
4042 used in this way. */
4044 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4046 /* A C compound statement to output to stdio stream STREAM the
4047 assembler syntax for an instruction operand that is a memory
4048 reference whose address is ADDR. ADDR is an RTL expression.
4050 On some machines, the syntax for a symbolic address depends on
4051 the section that the address refers to. On these machines,
4052 define the macro `ENCODE_SECTION_INFO' to store the information
4053 into the `symbol_ref', and then check for it here. */
4055 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4058 /* A C statement, to be executed after all slot-filler instructions
4059 have been output. If necessary, call `dbr_sequence_length' to
4060 determine the number of slots filled in a sequence (zero if not
4061 currently outputting a sequence), to decide how many no-ops to
4062 output, or whatever.
4064 Don't define this macro if it has nothing to do, but it is
4065 helpful in reading assembly output if the extent of the delay
4066 sequence is made explicit (e.g. with white space).
4068 Note that output routines for instructions with delay slots must
4069 be prepared to deal with not being output as part of a sequence
4070 (i.e. when the scheduling pass is not run, or when no slot
4071 fillers could be found.) The variable `final_sequence' is null
4072 when not processing a sequence, otherwise it contains the
4073 `sequence' rtx being output. */
4075 #define DBR_OUTPUT_SEQEND(STREAM) \
4078 if (set_nomacro > 0 && --set_nomacro == 0) \
4079 fputs ("\t.set\tmacro\n", STREAM); \
4081 if (set_noreorder > 0 && --set_noreorder == 0) \
4082 fputs ("\t.set\treorder\n", STREAM); \
4084 dslots_jump_filled++; \
4085 fputs ("\n", STREAM); \
4090 /* How to tell the debugger about changes of source files. Note, the
4091 mips ECOFF format cannot deal with changes of files inside of
4092 functions, which means the output of parser generators like bison
4093 is generally not debuggable without using the -l switch. Lose,
4094 lose, lose. Silicon graphics seems to want all .file's hardwired
4097 #ifndef SET_FILE_NUMBER
4098 #define SET_FILE_NUMBER() ++num_source_filenames
4101 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4102 mips_output_filename (STREAM, NAME)
4104 /* This is defined so that it can be overridden in iris6.h. */
4105 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4108 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4109 output_quoted_string (STREAM, NAME); \
4110 fputs ("\n", STREAM); \
4114 /* This is how to output a note the debugger telling it the line number
4115 to which the following sequence of instructions corresponds.
4116 Silicon graphics puts a label after each .loc. */
4118 #ifndef LABEL_AFTER_LOC
4119 #define LABEL_AFTER_LOC(STREAM)
4122 #undef ASM_OUTPUT_SOURCE_LINE
4123 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4124 mips_output_lineno (STREAM, LINE)
4126 /* The MIPS implementation uses some labels for its own purpose. The
4127 following lists what labels are created, and are all formed by the
4128 pattern $L[a-z].*. The machine independent portion of GCC creates
4129 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4131 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4132 $Lb[0-9]+ Begin blocks for MIPS debug support
4133 $Lc[0-9]+ Label for use in s<xx> operation.
4134 $Le[0-9]+ End blocks for MIPS debug support
4135 $Lp\..+ Half-pic labels. */
4137 /* This is how to output the definition of a user-level label named NAME,
4138 such as the label on a static function or variable NAME.
4140 If we are optimizing the gp, remember that this label has been put
4141 out, so we know not to emit an .extern for it in mips_asm_file_end.
4142 We use one of the common bits in the IDENTIFIER tree node for this,
4143 since those bits seem to be unused, and we don't have any method
4144 of getting the decl nodes from the name. */
4146 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4148 assemble_name (STREAM, NAME); \
4149 fputs (":\n", STREAM); \
4153 /* A C statement (sans semicolon) to output to the stdio stream
4154 STREAM any text necessary for declaring the name NAME of an
4155 initialized variable which is being defined. This macro must
4156 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4157 The argument DECL is the `VAR_DECL' tree node representing the
4160 If this macro is not defined, then the variable name is defined
4161 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4163 #undef ASM_DECLARE_OBJECT_NAME
4164 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4167 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4168 HALF_PIC_DECLARE (NAME); \
4173 /* This is how to output a command to make the user-level label named NAME
4174 defined for reference from other files. */
4176 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4178 fputs ("\t.globl\t", STREAM); \
4179 assemble_name (STREAM, NAME); \
4180 fputs ("\n", STREAM); \
4183 /* This says how to define a global common symbol. */
4185 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4187 /* If the target wants uninitialized const declarations in \
4188 .rdata then don't put them in .comm */ \
4189 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4190 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4191 && (DECL_INITIAL (DECL) == 0 \
4192 || DECL_INITIAL (DECL) == error_mark_node)) \
4194 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4195 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4197 READONLY_DATA_SECTION (); \
4198 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4199 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4203 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4208 /* This says how to define a local common symbol (ie, not visible to
4211 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4212 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4215 /* This says how to output an external. It would be possible not to
4216 output anything and let undefined symbol become external. However
4217 the assembler uses length information on externals to allocate in
4218 data/sdata bss/sbss, thereby saving exec time. */
4220 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4221 mips_output_external(STREAM,DECL,NAME)
4223 /* This says what to print at the end of the assembly file */
4225 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4228 /* This is how to declare a function name. The actual work of
4229 emitting the label is moved to function_prologue, so that we can
4230 get the line number correctly emitted before the .ent directive,
4231 and after any .file directives.
4233 Also, switch files if we are optimizing the global pointer. */
4235 #undef ASM_DECLARE_FUNCTION_NAME
4236 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4238 extern FILE *asm_out_text_file; \
4239 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4241 STREAM = asm_out_text_file; \
4242 /* ??? text_section gets called too soon. If the previous \
4243 function is in a special section and we're not, we have \
4244 to switch back to the text section. We can't call \
4245 text_section again as gcc thinks we're already there. */ \
4246 /* ??? See varasm.c. There are other things that get output \
4247 too early, like alignment (before we've switched STREAM). */ \
4248 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4249 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4252 HALF_PIC_DECLARE (NAME); \
4255 /* This is how to output an internal numbered label where
4256 PREFIX is the class of label and NUM is the number within the class. */
4258 #undef ASM_OUTPUT_INTERNAL_LABEL
4259 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4260 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4262 /* This is how to store into the string LABEL
4263 the symbol_ref name of an internal numbered label where
4264 PREFIX is the class of label and NUM is the number within the class.
4265 This is suitable for output with `assemble_name'. */
4267 #undef ASM_GENERATE_INTERNAL_LABEL
4268 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4269 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4271 /* This is how to output an assembler line defining a `double' constant. */
4273 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4274 mips_output_double (STREAM, VALUE)
4277 /* This is how to output an assembler line defining a `float' constant. */
4279 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4280 mips_output_float (STREAM, VALUE)
4283 /* This is how to output an assembler line defining an `int' constant. */
4285 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4287 fprintf (STREAM, "\t.word\t"); \
4288 output_addr_const (STREAM, (VALUE)); \
4289 fprintf (STREAM, "\n"); \
4292 /* Likewise for 64 bit, `char' and `short' constants.
4294 FIXME: operand_subword can't handle some complex constant expressions
4295 that output_addr_const can (for example it does not call
4296 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4297 rely on that to avoid operand_subword for most of the cases where this
4298 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4299 or the same case with the type of 'i' changed to long long.
4303 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4305 if (TARGET_64BIT || TARGET_GAS) \
4307 fprintf (STREAM, "\t.dword\t"); \
4308 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4309 /* We can't use 'X' for negative numbers, because then we won't \
4310 get the right value for the upper 32 bits. */ \
4311 output_addr_const (STREAM, VALUE); \
4313 /* We must use 'X', because otherwise LONG_MIN will print as \
4314 a number that the Irix 6 assembler won't accept. */ \
4315 print_operand (STREAM, VALUE, 'X'); \
4316 fprintf (STREAM, "\n"); \
4320 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4321 UNITS_PER_WORD, 1); \
4322 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4323 UNITS_PER_WORD, 1); \
4327 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4329 fprintf (STREAM, "\t.half\t"); \
4330 output_addr_const (STREAM, (VALUE)); \
4331 fprintf (STREAM, "\n"); \
4334 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4336 fprintf (STREAM, "\t.byte\t"); \
4337 output_addr_const (STREAM, (VALUE)); \
4338 fprintf (STREAM, "\n"); \
4341 /* This is how to output an assembler line for a numeric constant byte. */
4343 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4344 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4346 /* This is how to output an element of a case-vector that is absolute. */
4348 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4349 fprintf (STREAM, "\t%s\t%sL%d\n", \
4350 Pmode == DImode ? ".dword" : ".word", \
4351 LOCAL_LABEL_PREFIX, \
4354 /* This is how to output an element of a case-vector that is relative.
4355 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4356 TARGET_EMBEDDED_PIC). */
4358 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4360 if (TARGET_MIPS16) \
4361 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4362 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4363 else if (TARGET_EMBEDDED_PIC) \
4364 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4365 Pmode == DImode ? ".dword" : ".word", \
4366 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4367 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4368 fprintf (STREAM, "\t%s\t%sL%d\n", \
4369 Pmode == DImode ? ".gpdword" : ".gpword", \
4370 LOCAL_LABEL_PREFIX, VALUE); \
4372 fprintf (STREAM, "\t%s\t%sL%d\n", \
4373 Pmode == DImode ? ".dword" : ".word", \
4374 LOCAL_LABEL_PREFIX, VALUE); \
4377 /* When generating embedded PIC or mips16 code we want to put the jump
4378 table in the .text section. In all other cases, we want to put the
4379 jump table in the .rdata section. Unfortunately, we can't use
4380 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4381 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4382 section if appropriate. */
4383 #undef ASM_OUTPUT_CASE_LABEL
4384 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4386 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4387 function_section (current_function_decl); \
4388 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4391 /* This is how to output an assembler line
4392 that says to advance the location counter
4393 to a multiple of 2**LOG bytes. */
4395 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4396 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4398 /* This is how to output an assembler line to advance the location
4399 counter by SIZE bytes. */
4401 #undef ASM_OUTPUT_SKIP
4402 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4403 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4405 /* This is how to output a string. */
4406 #undef ASM_OUTPUT_ASCII
4407 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4408 mips_output_ascii (STREAM, STRING, LEN)
4410 /* Handle certain cpp directives used in header files on sysV. */
4411 #define SCCS_DIRECTIVE
4413 /* Output #ident as a in the read-only data section. */
4414 #undef ASM_OUTPUT_IDENT
4415 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4417 const char *p = STRING; \
4418 int size = strlen (p) + 1; \
4420 assemble_string (p, size); \
4423 /* Default to -G 8 */
4424 #ifndef MIPS_DEFAULT_GVALUE
4425 #define MIPS_DEFAULT_GVALUE 8
4428 /* Define the strings to put out for each section in the object file. */
4429 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4430 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4431 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4432 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4433 #undef READONLY_DATA_SECTION
4434 #define READONLY_DATA_SECTION rdata_section
4435 #define SMALL_DATA_SECTION sdata_section
4437 /* What other sections we support other than the normal .data/.text. */
4439 #undef EXTRA_SECTIONS
4440 #define EXTRA_SECTIONS in_sdata, in_rdata
4442 /* Define the additional functions to select our additional sections. */
4444 /* on the MIPS it is not a good idea to put constants in the text
4445 section, since this defeats the sdata/data mechanism. This is
4446 especially true when -O is used. In this case an effort is made to
4447 address with faster (gp) register relative addressing, which can
4448 only get at sdata and sbss items (there is no stext !!) However,
4449 if the constant is too large for sdata, and it's readonly, it
4450 will go into the .rdata section. */
4452 #undef EXTRA_SECTION_FUNCTIONS
4453 #define EXTRA_SECTION_FUNCTIONS \
4457 if (in_section != in_sdata) \
4459 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4460 in_section = in_sdata; \
4467 if (in_section != in_rdata) \
4469 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4470 in_section = in_rdata; \
4474 /* Given a decl node or constant node, choose the section to output it in
4475 and select that section. */
4477 #undef SELECT_RTX_SECTION
4478 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4480 #undef SELECT_SECTION
4481 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4484 /* Store in OUTPUT a string (made with alloca) containing
4485 an assembler-name for a local static variable named NAME.
4486 LABELNO is an integer which is different for each call. */
4488 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4489 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4490 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4492 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4495 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4496 TARGET_64BIT ? "dsubu" : "subu", \
4497 reg_names[STACK_POINTER_REGNUM], \
4498 reg_names[STACK_POINTER_REGNUM], \
4499 TARGET_64BIT ? "sd" : "sw", \
4501 reg_names[STACK_POINTER_REGNUM]); \
4505 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4508 if (! set_noreorder) \
4509 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4511 dslots_load_total++; \
4512 dslots_load_filled++; \
4513 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4514 TARGET_64BIT ? "ld" : "lw", \
4516 reg_names[STACK_POINTER_REGNUM], \
4517 TARGET_64BIT ? "daddu" : "addu", \
4518 reg_names[STACK_POINTER_REGNUM], \
4519 reg_names[STACK_POINTER_REGNUM]); \
4521 if (! set_noreorder) \
4522 fprintf (STREAM, "\t.set\treorder\n"); \
4526 /* How to start an assembler comment.
4527 The leading space is important (the mips native assembler requires it). */
4528 #ifndef ASM_COMMENT_START
4529 #define ASM_COMMENT_START " #"
4533 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4534 and mips-tdump.c to print them out.
4536 These must match the corresponding definitions in gdb/mipsread.c.
4537 Unfortunately, gcc and gdb do not currently share any directories. */
4539 #define CODE_MASK 0x8F300
4540 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4541 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4542 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4545 /* Default definitions for size_t and ptrdiff_t. */
4548 #define NO_BUILTIN_SIZE_TYPE
4549 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4552 #ifndef PTRDIFF_TYPE
4553 #define NO_BUILTIN_PTRDIFF_TYPE
4554 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4557 /* See mips_expand_prologue's use of loadgp for when this should be
4560 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4561 && mips_abi != ABI_32 \
4562 && mips_abi != ABI_O64)
4564 /* In mips16 mode, we need to look through the function to check for
4565 PC relative loads that are out of range. */
4566 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4568 /* We need to use a special set of functions to handle hard floating
4569 point code in mips16 mode. */
4571 #ifndef INIT_SUBTARGET_OPTABS
4572 #define INIT_SUBTARGET_OPTABS
4575 #define INIT_TARGET_OPTABS \
4578 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4579 INIT_SUBTARGET_OPTABS; \
4582 add_optab->handlers[(int) SFmode].libfunc = \
4583 init_one_libfunc ("__mips16_addsf3"); \
4584 sub_optab->handlers[(int) SFmode].libfunc = \
4585 init_one_libfunc ("__mips16_subsf3"); \
4586 smul_optab->handlers[(int) SFmode].libfunc = \
4587 init_one_libfunc ("__mips16_mulsf3"); \
4588 flodiv_optab->handlers[(int) SFmode].libfunc = \
4589 init_one_libfunc ("__mips16_divsf3"); \
4591 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4592 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4593 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4594 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4595 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4596 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4598 floatsisf_libfunc = \
4599 init_one_libfunc ("__mips16_floatsisf"); \
4601 init_one_libfunc ("__mips16_fixsfsi"); \
4603 if (TARGET_DOUBLE_FLOAT) \
4605 add_optab->handlers[(int) DFmode].libfunc = \
4606 init_one_libfunc ("__mips16_adddf3"); \
4607 sub_optab->handlers[(int) DFmode].libfunc = \
4608 init_one_libfunc ("__mips16_subdf3"); \
4609 smul_optab->handlers[(int) DFmode].libfunc = \
4610 init_one_libfunc ("__mips16_muldf3"); \
4611 flodiv_optab->handlers[(int) DFmode].libfunc = \
4612 init_one_libfunc ("__mips16_divdf3"); \
4614 extendsfdf2_libfunc = \
4615 init_one_libfunc ("__mips16_extendsfdf2"); \
4616 truncdfsf2_libfunc = \
4617 init_one_libfunc ("__mips16_truncdfsf2"); \
4620 init_one_libfunc ("__mips16_eqdf2"); \
4622 init_one_libfunc ("__mips16_nedf2"); \
4624 init_one_libfunc ("__mips16_gtdf2"); \
4626 init_one_libfunc ("__mips16_gedf2"); \
4628 init_one_libfunc ("__mips16_ltdf2"); \
4630 init_one_libfunc ("__mips16_ledf2"); \
4632 floatsidf_libfunc = \
4633 init_one_libfunc ("__mips16_floatsidf"); \
4635 init_one_libfunc ("__mips16_fixdfsi"); \
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