1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
83 /* Recast the cpu class to be the cpu attribute. */
84 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
86 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
87 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
88 to work on a 64 bit machine. */
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 /* Information about one recognized processor. Defined here for the
116 benefit of TARGET_CPU_CPP_BUILTINS. */
117 struct mips_cpu_info {
118 /* The 'canonical' name of the processor as far as GCC is concerned.
119 It's typically a manufacturer's prefix followed by a numerical
120 designation. It should be lower case. */
123 /* The internal processor number that most closely matches this
124 entry. Several processors can have the same value, if there's no
125 difference between them from GCC's point of view. */
126 enum processor_type cpu;
128 /* The ISA level that the processor implements. */
132 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
133 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
134 extern const char *current_function_file; /* filename current function is in */
135 extern int num_source_filenames; /* current .file # */
136 extern int inside_function; /* != 0 if inside of a function */
137 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
138 extern int file_in_function_warning; /* warning given about .file in func */
139 extern int sdb_label_count; /* block start/end next label # */
140 extern int sdb_begin_function_line; /* Starting Line of current function */
141 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
142 extern int g_switch_value; /* value of the -G xx switch */
143 extern int g_switch_set; /* whether -G xx was passed. */
144 extern int sym_lineno; /* sgi next label # for each stmt */
145 extern int set_noreorder; /* # of nested .set noreorder's */
146 extern int set_nomacro; /* # of nested .set nomacro's */
147 extern int set_noat; /* # of nested .set noat's */
148 extern int set_volatile; /* # of nested .set volatile's */
149 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
150 extern int mips_dbx_regno[]; /* Map register # to debug register # */
151 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
152 extern enum cmp_type branch_type; /* what type of branch to use */
153 extern enum processor_type mips_arch; /* which cpu to codegen for */
154 extern enum processor_type mips_tune; /* which cpu to schedule for */
155 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
156 extern int mips_isa; /* architectural level */
157 extern int mips16; /* whether generating mips16 code */
158 extern int mips16_hard_float; /* mips16 without -msoft-float */
159 extern int mips_entry; /* generate entry/exit for mips16 */
160 extern const char *mips_arch_string; /* for -march=<xxx> */
161 extern const char *mips_tune_string; /* for -mtune=<xxx> */
162 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
163 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
164 extern const char *mips_entry_string; /* for -mentry */
165 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
166 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
167 extern int dslots_load_total; /* total # load related delay slots */
168 extern int dslots_load_filled; /* # filled load delay slots */
169 extern int dslots_jump_total; /* total # jump related delay slots */
170 extern int dslots_jump_filled; /* # filled jump delay slots */
171 extern int dslots_number_nops; /* # of nops needed by previous insn */
172 extern int num_refs[3]; /* # 1/2/3 word references */
173 extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
174 extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
175 extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
176 extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
177 extern int mips_string_length; /* length of strings for mips16 */
178 extern const struct mips_cpu_info mips_cpu_info_table[];
179 extern const struct mips_cpu_info *mips_arch_info;
180 extern const struct mips_cpu_info *mips_tune_info;
182 /* Functions to change what output section we are using. */
183 extern void sdata_section PARAMS ((void));
184 extern void sbss_section PARAMS ((void));
186 /* Macros to silence warnings about numbers being signed in traditional
187 C and unsigned in ISO C when compiled on 32-bit hosts. */
189 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
190 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
191 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
194 /* Run-time compilation parameters selecting different hardware subsets. */
196 /* Macros used in the machine description to test the flags. */
198 /* Bits for real switches */
199 #define MASK_INT64 0x00000001 /* ints are 64 bits */
200 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
201 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
202 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
203 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
204 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
205 #define MASK_STATS 0x00000040 /* print statistics to stderr */
206 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
207 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
208 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
209 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
210 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
211 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
212 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
213 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
214 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
215 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
216 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
217 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
218 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
219 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
220 #define MASK_NO_CHECK_ZERO_DIV \
221 0x00200000 /* divide by zero checking */
222 #define MASK_CHECK_RANGE_DIV \
223 0x00400000 /* divide result range checking */
224 #define MASK_UNINIT_CONST_IN_RODATA \
225 0x00800000 /* Store uninitialized
227 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
228 multiply-add operations. */
229 #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
231 #define MASK_EXPLICIT_RELOCS 0x04000000 /* Use relocation operators. */
233 /* Debug switches, not documented */
234 #define MASK_DEBUG 0 /* unused */
235 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
236 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
237 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
238 #define MASK_DEBUG_D 0 /* don't do define_split's */
239 #define MASK_DEBUG_E 0 /* function_arg debug */
240 #define MASK_DEBUG_F 0 /* ??? */
241 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
242 #define MASK_DEBUG_I 0 /* unused */
244 /* Dummy switches used only in specs */
245 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
247 /* r4000 64 bit sizes */
248 #define TARGET_INT64 (target_flags & MASK_INT64)
249 #define TARGET_LONG64 (target_flags & MASK_LONG64)
250 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
251 #define TARGET_64BIT (target_flags & MASK_64BIT)
253 /* Mips vs. GNU linker */
254 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
256 /* Mips vs. GNU assembler */
257 #define TARGET_GAS (target_flags & MASK_GAS)
258 #define TARGET_MIPS_AS (!TARGET_GAS)
261 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
262 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
263 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
264 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
265 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
266 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
267 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
268 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
269 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
271 /* Reg. Naming in .s ($21 vs. $a0) */
272 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
274 /* Optimize for Sdata/Sbss */
275 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
277 /* print program statistics */
278 #define TARGET_STATS (target_flags & MASK_STATS)
280 /* call memcpy instead of inline code */
281 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
283 /* .abicalls, etc from Pyramid V.4 */
284 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
286 /* software floating point */
287 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
288 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
290 /* always call through a register */
291 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
293 /* generate embedded PIC code;
295 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
297 /* for embedded systems, optimize for
298 reduced RAM space instead of for
300 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
302 /* always store uninitialized const
303 variables in rodata, requires
304 TARGET_EMBEDDED_DATA. */
305 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
307 /* generate big endian code. */
308 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
310 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
311 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
313 #define TARGET_MAD (target_flags & MASK_MAD)
315 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
317 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
319 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
320 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
322 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
325 /* True if we should use NewABI-style relocation operators for
326 symbolic addresses. This is never true for mips16 code,
327 which has its own conventions. */
329 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
332 /* This is true if we must enable the assembly language file switching
335 #define TARGET_FILE_SWITCHING \
336 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
338 /* True if the call patterns should be split into a jalr followed by
339 an instruction to restore $gp. This is only ever true for SVR4 PIC,
340 in which $gp is call-clobbered. It is only safe to split the load
341 from the call when every use of $gp is explicit. */
343 #define TARGET_SPLIT_CALLS \
344 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
346 /* True if we can optimize sibling calls. For simplicity, we only
347 handle cases in which call_insn_operand will reject invalid
348 sibcall addresses. There are two cases in which this isn't true:
350 - TARGET_MIPS16. call_insn_operand accepts constant addresses
351 but there is no direct jump instruction. It isn't worth
352 using sibling calls in this case anyway; they would usually
353 be longer than normal calls.
355 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
356 accepts global constants, but "jr $25" is the only allowed
359 #define TARGET_SIBCALLS \
360 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
362 /* True if .gpword or .gpdword should be used for switch tables.
363 Not all SGI assemblers support this. */
365 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
368 /* We must disable the function end stabs when doing the file switching trick,
369 because the Lscope stabs end up in the wrong place, making it impossible
370 to debug the resulting code. */
371 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
373 /* Generate mips16 code */
374 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
376 /* Generic ISA defines. */
377 #define ISA_MIPS1 (mips_isa == 1)
378 #define ISA_MIPS2 (mips_isa == 2)
379 #define ISA_MIPS3 (mips_isa == 3)
380 #define ISA_MIPS4 (mips_isa == 4)
381 #define ISA_MIPS32 (mips_isa == 32)
382 #define ISA_MIPS32R2 (mips_isa == 33)
383 #define ISA_MIPS64 (mips_isa == 64)
385 /* Architecture target defines. */
386 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
387 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
388 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
389 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
390 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
391 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
392 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
393 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
394 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
395 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
396 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
398 /* Scheduling target defines. */
399 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
400 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
401 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
402 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
403 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
404 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
405 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
406 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
407 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
409 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
411 /* Define preprocessor macros for the -march and -mtune options.
412 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
413 processor. If INFO's canonical name is "foo", define PREFIX to
414 be "foo", and define an additional macro PREFIX_FOO. */
415 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
420 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
421 for (p = macro; *p != 0; p++) \
424 builtin_define (macro); \
425 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
430 /* Target CPU builtins. */
431 #define TARGET_CPU_CPP_BUILTINS() \
434 builtin_assert ("cpu=mips"); \
435 builtin_define ("__mips__"); \
436 builtin_define ("_mips"); \
438 /* We do this here because __mips is defined below \
439 and so we can't use builtin_define_std. */ \
441 builtin_define ("mips"); \
443 /* Treat _R3000 and _R4000 like register-size defines, \
444 which is how they've historically been used. */ \
447 builtin_define ("__mips64"); \
448 builtin_define_std ("R4000"); \
449 builtin_define ("_R4000"); \
453 builtin_define_std ("R3000"); \
454 builtin_define ("_R3000"); \
456 if (TARGET_FLOAT64) \
457 builtin_define ("__mips_fpr=64"); \
459 builtin_define ("__mips_fpr=32"); \
462 builtin_define ("__mips16"); \
464 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
465 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
469 builtin_define ("__mips=1"); \
470 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
472 else if (ISA_MIPS2) \
474 builtin_define ("__mips=2"); \
475 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
477 else if (ISA_MIPS3) \
479 builtin_define ("__mips=3"); \
480 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
482 else if (ISA_MIPS4) \
484 builtin_define ("__mips=4"); \
485 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
487 else if (ISA_MIPS32) \
489 builtin_define ("__mips=32"); \
490 builtin_define ("__mips_isa_rev=1"); \
491 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
493 else if (ISA_MIPS32R2) \
495 builtin_define ("__mips=32"); \
496 builtin_define ("__mips_isa_rev=2"); \
497 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
499 else if (ISA_MIPS64) \
501 builtin_define ("__mips=64"); \
502 builtin_define ("__mips_isa_rev=1"); \
503 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
506 if (TARGET_HARD_FLOAT) \
507 builtin_define ("__mips_hard_float"); \
508 else if (TARGET_SOFT_FLOAT) \
509 builtin_define ("__mips_soft_float"); \
511 if (TARGET_SINGLE_FLOAT) \
512 builtin_define ("__mips_single_float"); \
514 if (TARGET_BIG_ENDIAN) \
516 builtin_define_std ("MIPSEB"); \
517 builtin_define ("_MIPSEB"); \
521 builtin_define_std ("MIPSEL"); \
522 builtin_define ("_MIPSEL"); \
525 /* Macros dependent on the C dialect. */ \
526 if (preprocessing_asm_p ()) \
528 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
529 builtin_define ("_LANGUAGE_ASSEMBLY"); \
531 else if (c_language == clk_c) \
533 builtin_define_std ("LANGUAGE_C"); \
534 builtin_define ("_LANGUAGE_C"); \
536 else if (c_language == clk_cplusplus) \
538 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
539 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
540 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
544 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
545 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
546 /* Bizzare, but needed at least for Irix. */ \
547 builtin_define_std ("LANGUAGE_C"); \
548 builtin_define ("_LANGUAGE_C"); \
551 if (mips_abi == ABI_EABI) \
552 builtin_define ("__mips_eabi"); \
558 /* Macro to define tables used to set the flags.
559 This is a list in braces of pairs in braces,
560 each pair being { "NAME", VALUE }
561 where VALUE is the bits to set or minus the bits to clear.
562 An empty string NAME is used to identify the default VALUE. */
564 #define TARGET_SWITCHES \
566 SUBTARGET_TARGET_SWITCHES \
567 {"int64", MASK_INT64 | MASK_LONG64, \
568 N_("Use 64-bit int type")}, \
569 {"long64", MASK_LONG64, \
570 N_("Use 64-bit long type")}, \
571 {"long32", -(MASK_LONG64 | MASK_INT64), \
572 N_("Use 32-bit long type")}, \
573 {"split-addresses", MASK_SPLIT_ADDR, \
574 N_("Optimize lui/addiu address loads")}, \
575 {"no-split-addresses", -MASK_SPLIT_ADDR, \
576 N_("Don't optimize lui/addiu address loads")}, \
577 {"mips-as", -MASK_GAS, \
578 N_("Use MIPS as")}, \
581 {"rnames", MASK_NAME_REGS, \
582 N_("Use symbolic register names")}, \
583 {"no-rnames", -MASK_NAME_REGS, \
584 N_("Don't use symbolic register names")}, \
585 {"gpOPT", MASK_GPOPT, \
586 N_("Use GP relative sdata/sbss sections")}, \
587 {"gpopt", MASK_GPOPT, \
588 N_("Use GP relative sdata/sbss sections")}, \
589 {"no-gpOPT", -MASK_GPOPT, \
590 N_("Don't use GP relative sdata/sbss sections")}, \
591 {"no-gpopt", -MASK_GPOPT, \
592 N_("Don't use GP relative sdata/sbss sections")}, \
593 {"stats", MASK_STATS, \
594 N_("Output compiler statistics")}, \
595 {"no-stats", -MASK_STATS, \
596 N_("Don't output compiler statistics")}, \
597 {"memcpy", MASK_MEMCPY, \
598 N_("Don't optimize block moves")}, \
599 {"no-memcpy", -MASK_MEMCPY, \
600 N_("Optimize block moves")}, \
601 {"mips-tfile", MASK_MIPS_TFILE, \
602 N_("Use mips-tfile asm postpass")}, \
603 {"no-mips-tfile", -MASK_MIPS_TFILE, \
604 N_("Don't use mips-tfile asm postpass")}, \
605 {"soft-float", MASK_SOFT_FLOAT, \
606 N_("Use software floating point")}, \
607 {"hard-float", -MASK_SOFT_FLOAT, \
608 N_("Use hardware floating point")}, \
609 {"fp64", MASK_FLOAT64, \
610 N_("Use 64-bit FP registers")}, \
611 {"fp32", -MASK_FLOAT64, \
612 N_("Use 32-bit FP registers")}, \
613 {"gp64", MASK_64BIT, \
614 N_("Use 64-bit general registers")}, \
615 {"gp32", -MASK_64BIT, \
616 N_("Use 32-bit general registers")}, \
617 {"abicalls", MASK_ABICALLS, \
618 N_("Use Irix PIC")}, \
619 {"no-abicalls", -MASK_ABICALLS, \
620 N_("Don't use Irix PIC")}, \
621 {"long-calls", MASK_LONG_CALLS, \
622 N_("Use indirect calls")}, \
623 {"no-long-calls", -MASK_LONG_CALLS, \
624 N_("Don't use indirect calls")}, \
625 {"embedded-pic", MASK_EMBEDDED_PIC, \
626 N_("Use embedded PIC")}, \
627 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
628 N_("Don't use embedded PIC")}, \
629 {"embedded-data", MASK_EMBEDDED_DATA, \
630 N_("Use ROM instead of RAM")}, \
631 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
632 N_("Don't use ROM instead of RAM")}, \
633 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
634 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
635 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
636 N_("Don't put uninitialized constants in ROM")}, \
637 {"eb", MASK_BIG_ENDIAN, \
638 N_("Use big-endian byte order")}, \
639 {"el", -MASK_BIG_ENDIAN, \
640 N_("Use little-endian byte order")}, \
641 {"single-float", MASK_SINGLE_FLOAT, \
642 N_("Use single (32-bit) FP only")}, \
643 {"double-float", -MASK_SINGLE_FLOAT, \
644 N_("Don't use single (32-bit) FP only")}, \
646 N_("Use multiply accumulate")}, \
647 {"no-mad", -MASK_MAD, \
648 N_("Don't use multiply accumulate")}, \
649 {"no-fused-madd", MASK_NO_FUSED_MADD, \
650 N_("Don't generate fused multiply/add instructions")}, \
651 {"fused-madd", -MASK_NO_FUSED_MADD, \
652 N_("Generate fused multiply/add instructions")}, \
653 {"fix4300", MASK_4300_MUL_FIX, \
654 N_("Work around early 4300 hardware bug")}, \
655 {"no-fix4300", -MASK_4300_MUL_FIX, \
656 N_("Don't work around early 4300 hardware bug")}, \
657 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
658 N_("Trap on integer divide by zero")}, \
659 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
660 N_("Don't trap on integer divide by zero")}, \
661 {"check-range-division",MASK_CHECK_RANGE_DIV, \
662 N_("Trap on integer divide overflow")}, \
663 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
664 N_("Don't trap on integer divide overflow")}, \
665 { "branch-likely", MASK_BRANCHLIKELY, \
666 N_("Use Branch Likely instructions, overriding default for arch")}, \
667 { "no-branch-likely", -MASK_BRANCHLIKELY, \
668 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
669 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
670 N_("Use NewABI-style %reloc() assembly operators")}, \
671 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
672 N_("Use assembler macros instead of relocation operators")}, \
673 {"debug", MASK_DEBUG, \
675 {"debuga", MASK_DEBUG_A, \
677 {"debugb", MASK_DEBUG_B, \
679 {"debugc", MASK_DEBUG_C, \
681 {"debugd", MASK_DEBUG_D, \
683 {"debuge", MASK_DEBUG_E, \
685 {"debugf", MASK_DEBUG_F, \
687 {"debugg", MASK_DEBUG_G, \
689 {"debugi", MASK_DEBUG_I, \
691 {"", (TARGET_DEFAULT \
692 | TARGET_CPU_DEFAULT \
693 | TARGET_ENDIAN_DEFAULT), \
697 /* Default target_flags if no switches are specified */
699 #ifndef TARGET_DEFAULT
700 #define TARGET_DEFAULT 0
703 #ifndef TARGET_CPU_DEFAULT
704 #define TARGET_CPU_DEFAULT 0
707 #ifndef TARGET_ENDIAN_DEFAULT
708 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
711 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
712 #ifndef MIPS_ISA_DEFAULT
713 #ifndef MIPS_CPU_STRING_DEFAULT
714 #define MIPS_CPU_STRING_DEFAULT "from-abi"
720 /* Make this compile time constant for libgcc2 */
722 #define TARGET_64BIT 1
724 #define TARGET_64BIT 0
726 #endif /* IN_LIBGCC2 */
728 #ifndef MULTILIB_ENDIAN_DEFAULT
729 #if TARGET_ENDIAN_DEFAULT == 0
730 #define MULTILIB_ENDIAN_DEFAULT "EL"
732 #define MULTILIB_ENDIAN_DEFAULT "EB"
736 #ifndef MULTILIB_ISA_DEFAULT
737 # if MIPS_ISA_DEFAULT == 1
738 # define MULTILIB_ISA_DEFAULT "mips1"
740 # if MIPS_ISA_DEFAULT == 2
741 # define MULTILIB_ISA_DEFAULT "mips2"
743 # if MIPS_ISA_DEFAULT == 3
744 # define MULTILIB_ISA_DEFAULT "mips3"
746 # if MIPS_ISA_DEFAULT == 4
747 # define MULTILIB_ISA_DEFAULT "mips4"
749 # if MIPS_ISA_DEFAULT == 32
750 # define MULTILIB_ISA_DEFAULT "mips32"
752 # if MIPS_ISA_DEFAULT == 33
753 # define MULTILIB_ISA_DEFAULT "mips32r2"
755 # if MIPS_ISA_DEFAULT == 64
756 # define MULTILIB_ISA_DEFAULT "mips64"
758 # define MULTILIB_ISA_DEFAULT "mips1"
768 #ifndef MULTILIB_DEFAULTS
769 #define MULTILIB_DEFAULTS \
770 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
773 /* We must pass -EL to the linker by default for little endian embedded
774 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
775 linker will default to using big-endian output files. The OUTPUT_FORMAT
776 line must be in the linker script, otherwise -EB/-EL will not work. */
779 #if TARGET_ENDIAN_DEFAULT == 0
780 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
782 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
786 #define TARGET_OPTIONS \
788 SUBTARGET_TARGET_OPTIONS \
789 { "tune=", &mips_tune_string, \
790 N_("Specify CPU for scheduling purposes"), 0}, \
791 { "arch=", &mips_arch_string, \
792 N_("Specify CPU for code generation purposes"), 0}, \
793 { "abi=", &mips_abi_string, \
794 N_("Specify an ABI"), 0}, \
795 { "ips", &mips_isa_string, \
796 N_("Specify a Standard MIPS ISA"), 0}, \
797 { "entry", &mips_entry_string, \
798 N_("Use mips16 entry/exit psuedo ops"), 0}, \
799 { "no-mips16", &mips_no_mips16_string, \
800 N_("Don't use MIPS16 instructions"), 0}, \
801 { "no-flush-func", &mips_cache_flush_func, \
802 N_("Don't call any cache flush functions"), 0}, \
803 { "flush-func=", &mips_cache_flush_func, \
804 N_("Specify cache flush function"), 0}, \
807 /* This is meant to be redefined in the host dependent files. */
808 #define SUBTARGET_TARGET_OPTIONS
810 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
814 /* Generate three-operand multiply instructions for SImode. */
815 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
823 /* Generate three-operand multiply instructions for DImode. */
824 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
827 /* Macros to decide whether certain features are available or not,
828 depending on the instruction set architecture level. */
830 #define HAVE_SQRT_P() (!ISA_MIPS1)
832 /* True if the ABI can only work with 64-bit integer registers. We
833 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
834 otherwise floating-point registers must also be 64-bit. */
835 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
836 || mips_abi == ABI_O64 \
837 || mips_abi == ABI_N32)
839 /* Likewise for 32-bit regs. */
840 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
842 /* True if symbols are 64 bits wide. At present, n64 is the only
843 ABI for which this is true. */
844 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
846 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
847 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
851 /* ISA has branch likely instructions (eg. mips2). */
852 /* Disable branchlikely for tx39 until compare rewrite. They haven't
853 been generated up to this point. */
854 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
857 /* ISA has the conditional move instructions introduced in mips4. */
858 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
862 && !TARGET_MIPS5500 \
865 /* ISA has just the integer condition move instructions (movn,movz) */
866 #define ISA_HAS_INT_CONDMOVE 0
868 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
869 branch on CC, and move (both FP and non-FP) on CC. */
870 #define ISA_HAS_8CC (ISA_MIPS4 \
875 /* This is a catch all for the other new mips4 instructions: indexed load and
876 indexed prefetch instructions, the FP madd and msub instructions,
877 and the FP recip and recip sqrt instructions */
878 #define ISA_HAS_FP4 ((ISA_MIPS4 \
882 /* ISA has conditional trap instructions. */
883 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
886 /* ISA has integer multiply-accumulate instructions, madd and msub. */
887 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
892 /* ISA has floating-point nmadd and nmsub instructions. */
893 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
895 && (!TARGET_MIPS5400 || TARGET_MAD) \
898 /* ISA has count leading zeroes/ones instruction (not implemented). */
899 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
904 /* ISA has double-word count leading zeroes/ones instruction (not
906 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
909 /* ISA has three operand multiply instructions that put
910 the high part in an accumulator: mulhi or mulhiu. */
911 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
916 /* ISA has three operand multiply instructions that
917 negates the result and puts the result in an accumulator. */
918 #define ISA_HAS_MULS (TARGET_MIPS5400 \
923 /* ISA has three operand multiply instructions that subtracts the
924 result from a 4th operand and puts the result in an accumulator. */
925 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
929 /* ISA has three operand multiply instructions that the result
930 from a 4th operand and puts the result in an accumulator. */
931 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
937 /* ISA has 32-bit rotate right instruction. */
938 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
945 /* ISA has 64-bit rotate right instruction. */
946 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
948 && (TARGET_MIPS5400 \
953 /* ISA has data prefetch instruction. */
954 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
960 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
961 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
962 also requires TARGET_DOUBLE_FLOAT. */
963 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
965 /* ISA includes the MIPS32r2 seb and seh instructions. */
966 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
970 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
971 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
972 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
973 target_flags, and -mgp64 sets MASK_64BIT.
975 Setting MASK_64BIT in target_flags will cause gcc to assume that
976 registers are 64 bits wide. int, long and void * will be 32 bit;
977 this may be changed with -mint64 or -mlong64.
979 The gen* programs link code that refers to MASK_64BIT. They don't
980 actually use the information in target_flags; they just refer to
983 /* Switch Recognition by gcc.c. Add -G xx support */
985 #undef SWITCH_TAKES_ARG
986 #define SWITCH_TAKES_ARG(CHAR) \
987 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
989 /* Sometimes certain combinations of command options do not make sense
990 on a particular target machine. You can define a macro
991 `OVERRIDE_OPTIONS' to take account of this. This macro, if
992 defined, is executed once just after all the command options have
995 On the MIPS, it is used to handle -G. We also use it to set up all
996 of the tables referenced in the other macros. */
998 #define OVERRIDE_OPTIONS override_options ()
1000 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1002 /* Show we can debug even without a frame pointer. */
1003 #define CAN_DEBUG_WITHOUT_FP
1005 /* Tell collect what flags to pass to nm. */
1007 #define NM_FLAGS "-Bn"
1011 /* Assembler specs. */
1013 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1016 #define MIPS_AS_ASM_SPEC "\
1017 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1018 %{pipe: %e-pipe is not supported} \
1019 %{K} %(subtarget_mips_as_asm_spec)"
1021 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1022 rather than gas. It may be overridden by subtargets. */
1024 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1025 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1028 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1031 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1033 #define SUBTARGET_TARGET_SWITCHES
1035 extern int mips_abi;
1037 #ifndef MIPS_ABI_DEFAULT
1038 #define MIPS_ABI_DEFAULT ABI_32
1041 /* Use the most portable ABI flag for the ASM specs. */
1043 #if MIPS_ABI_DEFAULT == ABI_32
1044 #define MULTILIB_ABI_DEFAULT "mabi=32"
1045 #define ASM_ABI_DEFAULT_SPEC "-32"
1048 #if MIPS_ABI_DEFAULT == ABI_O64
1049 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1050 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1053 #if MIPS_ABI_DEFAULT == ABI_N32
1054 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1055 #define ASM_ABI_DEFAULT_SPEC "-n32"
1058 #if MIPS_ABI_DEFAULT == ABI_64
1059 #define MULTILIB_ABI_DEFAULT "mabi=64"
1060 #define ASM_ABI_DEFAULT_SPEC "-64"
1063 #if MIPS_ABI_DEFAULT == ABI_EABI
1064 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1065 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1068 /* Only ELF targets can switch the ABI. */
1069 #ifndef OBJECT_FORMAT_ELF
1070 #undef ASM_ABI_DEFAULT_SPEC
1071 #define ASM_ABI_DEFAULT_SPEC ""
1074 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1075 GAS_ASM_SPEC as the default, depending upon the value of
1078 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1081 #define TARGET_ASM_SPEC "\
1082 %{mmips-as: %(mips_as_asm_spec)} \
1083 %{!mmips-as: %(gas_asm_spec)}"
1087 #define TARGET_ASM_SPEC "\
1088 %{!mgas: %(mips_as_asm_spec)} \
1089 %{mgas: %(gas_asm_spec)}"
1091 #endif /* not GAS */
1093 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1094 to the assembler. It may be overridden by subtargets. */
1095 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1096 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1098 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1101 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1102 the assembler. It may be overridden by subtargets. */
1103 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1104 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1105 %{g} %{g0} %{g1} %{g2} %{g3} \
1106 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1107 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1108 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1109 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1110 %{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1113 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1114 overridden by subtargets. */
1116 #ifndef SUBTARGET_ASM_SPEC
1117 #define SUBTARGET_ASM_SPEC ""
1120 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1121 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1122 whether we're using GAS. These options can only be used properly
1123 with GAS, and it is better to get an error from a non-GAS assembler
1124 than to silently generate bad code. */
1128 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1129 %{mips32} %{mips32r2} %{mips64} \
1130 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1131 %(subtarget_asm_optimizing_spec) \
1132 %(subtarget_asm_debugging_spec) \
1134 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1135 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1136 %{mgp32} %{mgp64} %{march=*} \
1137 %(target_asm_spec) \
1138 %(subtarget_asm_spec)"
1140 /* Specify to run a post-processor, mips-tfile after the assembler
1141 has run to stuff the mips debug information into the object file.
1142 This is needed because the $#!%^ MIPS assembler provides no way
1143 of specifying such information in the assembly file. If we are
1144 cross compiling, disable mips-tfile unless the user specifies
1147 #ifndef ASM_FINAL_SPEC
1148 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1150 #define ASM_FINAL_SPEC "\
1151 %{mmips-as: %{!mno-mips-tfile: \
1152 \n mips-tfile %{v*: -v} \
1154 %{!K: %{save-temps: -I %b.o~}} \
1155 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1156 %{.s:%i} %{!.s:%g.s}}}"
1160 #define ASM_FINAL_SPEC "\
1161 %{!mgas: %{!mno-mips-tfile: \
1162 \n mips-tfile %{v*: -v} \
1164 %{!K: %{save-temps: -I %b.o~}} \
1165 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1166 %{.s:%i} %{!.s:%g.s}}}"
1169 #endif /* ASM_FINAL_SPEC */
1171 /* Redefinition of libraries used. Mips doesn't support normal
1172 UNIX style profiling via calling _mcount. It does offer
1173 profiling that samples the PC, so do what we can... */
1176 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1179 /* Extra switches sometimes passed to the linker. */
1180 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1181 will interpret it as a -b option. */
1184 #define LINK_SPEC "\
1186 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1187 %{bestGnum} %{shared} %{non_shared}"
1188 #endif /* LINK_SPEC defined */
1191 /* Specs for the compiler proper */
1193 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1194 overridden by subtargets. */
1195 #ifndef SUBTARGET_CC1_SPEC
1196 #define SUBTARGET_CC1_SPEC ""
1199 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1200 /* Note, we will need to adjust the following if we ever find a MIPS variant
1201 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1202 that show up in this case. */
1206 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1207 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1209 %(subtarget_cc1_spec)"
1212 /* Preprocessor specs. */
1214 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1215 overridden by subtargets. */
1216 #ifndef SUBTARGET_CPP_SPEC
1217 #define SUBTARGET_CPP_SPEC ""
1220 #define CPP_SPEC "%(subtarget_cpp_spec)"
1222 /* This macro defines names of additional specifications to put in the specs
1223 that can be used in various specifications like CC1_SPEC. Its definition
1224 is an initializer with a subgrouping for each command option.
1226 Each subgrouping contains a string constant, that defines the
1227 specification name, and a string constant that used by the GNU CC driver
1230 Do not define this macro if it does not need to do anything. */
1232 #define EXTRA_SPECS \
1233 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1234 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1235 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1236 { "gas_asm_spec", GAS_ASM_SPEC }, \
1237 { "target_asm_spec", TARGET_ASM_SPEC }, \
1238 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1239 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1240 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1241 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1242 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1243 { "endian_spec", ENDIAN_SPEC }, \
1244 SUBTARGET_EXTRA_SPECS
1246 #ifndef SUBTARGET_EXTRA_SPECS
1247 #define SUBTARGET_EXTRA_SPECS
1250 /* If defined, this macro is an additional prefix to try after
1251 `STANDARD_EXEC_PREFIX'. */
1253 #ifndef MD_EXEC_PREFIX
1254 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1257 #ifndef MD_STARTFILE_PREFIX
1258 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1262 /* Print subsidiary information on the compiler version in use. */
1264 #define MIPS_VERSION "[AL 1.1, MM 40]"
1266 #ifndef MACHINE_TYPE
1267 #define MACHINE_TYPE "BSD Mips"
1270 #ifndef TARGET_VERSION_INTERNAL
1271 #define TARGET_VERSION_INTERNAL(STREAM) \
1272 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1275 #ifndef TARGET_VERSION
1276 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1280 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1281 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1282 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1284 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1285 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1288 /* By default, turn on GDB extensions. */
1289 #define DEFAULT_GDB_EXTENSIONS 1
1291 /* If we are passing smuggling stabs through the MIPS ECOFF object
1292 format, put a comment in front of the .stab<x> operation so
1293 that the MIPS assembler does not choke. The mips-tfile program
1294 will correctly put the stab into the object file. */
1296 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1297 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1298 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1300 /* Local compiler-generated symbols must have a prefix that the assembler
1301 understands. By default, this is $, although some targets (e.g.,
1302 NetBSD-ELF) need to override this. */
1304 #ifndef LOCAL_LABEL_PREFIX
1305 #define LOCAL_LABEL_PREFIX "$"
1308 /* By default on the mips, external symbols do not have an underscore
1309 prepended, but some targets (e.g., NetBSD) require this. */
1311 #ifndef USER_LABEL_PREFIX
1312 #define USER_LABEL_PREFIX ""
1315 /* Forward references to tags are allowed. */
1316 #define SDB_ALLOW_FORWARD_REFERENCES
1318 /* Unknown tags are also allowed. */
1319 #define SDB_ALLOW_UNKNOWN_REFERENCES
1321 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1322 since the length can run past this up to a continuation point. */
1323 #undef DBX_CONTIN_LENGTH
1324 #define DBX_CONTIN_LENGTH 1500
1326 /* How to renumber registers for dbx and gdb. */
1327 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1329 /* The mapping from gcc register number to DWARF 2 CFA column number.
1330 This mapping does not allow for tracking register 0, since SGI's broken
1331 dwarf reader thinks column 0 is used for the frame address, but since
1332 register 0 is fixed this is not a problem. */
1333 #define DWARF_FRAME_REGNUM(REG) \
1334 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1336 /* The DWARF 2 CFA column which tracks the return address. */
1337 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1339 /* Before the prologue, RA lives in r31. */
1340 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1342 /* Describe how we implement __builtin_eh_return. */
1343 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1344 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1346 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1347 The default for this in 64-bit mode is 8, which causes problems with
1348 SFmode register saves. */
1349 #define DWARF_CIE_DATA_ALIGNMENT 4
1351 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1353 /* Overrides for the COFF debug format. */
1354 #define PUT_SDB_SCL(a) \
1356 extern FILE *asm_out_text_file; \
1357 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1360 #define PUT_SDB_INT_VAL(a) \
1362 extern FILE *asm_out_text_file; \
1363 fprintf (asm_out_text_file, "\t.val\t"); \
1364 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1365 fprintf (asm_out_text_file, ";"); \
1368 #define PUT_SDB_VAL(a) \
1370 extern FILE *asm_out_text_file; \
1371 fputs ("\t.val\t", asm_out_text_file); \
1372 output_addr_const (asm_out_text_file, (a)); \
1373 fputc (';', asm_out_text_file); \
1376 #define PUT_SDB_DEF(a) \
1378 extern FILE *asm_out_text_file; \
1379 fprintf (asm_out_text_file, "\t%s.def\t", \
1380 (TARGET_GAS) ? "" : "#"); \
1381 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1382 fputc (';', asm_out_text_file); \
1385 #define PUT_SDB_PLAIN_DEF(a) \
1387 extern FILE *asm_out_text_file; \
1388 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1389 (TARGET_GAS) ? "" : "#", (a)); \
1392 #define PUT_SDB_ENDEF \
1394 extern FILE *asm_out_text_file; \
1395 fprintf (asm_out_text_file, "\t.endef\n"); \
1398 #define PUT_SDB_TYPE(a) \
1400 extern FILE *asm_out_text_file; \
1401 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1404 #define PUT_SDB_SIZE(a) \
1406 extern FILE *asm_out_text_file; \
1407 fprintf (asm_out_text_file, "\t.size\t"); \
1408 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1409 fprintf (asm_out_text_file, ";"); \
1412 #define PUT_SDB_DIM(a) \
1414 extern FILE *asm_out_text_file; \
1415 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1418 #ifndef PUT_SDB_START_DIM
1419 #define PUT_SDB_START_DIM \
1421 extern FILE *asm_out_text_file; \
1422 fprintf (asm_out_text_file, "\t.dim\t"); \
1426 #ifndef PUT_SDB_NEXT_DIM
1427 #define PUT_SDB_NEXT_DIM(a) \
1429 extern FILE *asm_out_text_file; \
1430 fprintf (asm_out_text_file, "%d,", a); \
1434 #ifndef PUT_SDB_LAST_DIM
1435 #define PUT_SDB_LAST_DIM(a) \
1437 extern FILE *asm_out_text_file; \
1438 fprintf (asm_out_text_file, "%d;", a); \
1442 #define PUT_SDB_TAG(a) \
1444 extern FILE *asm_out_text_file; \
1445 fprintf (asm_out_text_file, "\t.tag\t"); \
1446 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1447 fputc (';', asm_out_text_file); \
1450 /* For block start and end, we create labels, so that
1451 later we can figure out where the correct offset is.
1452 The normal .ent/.end serve well enough for functions,
1453 so those are just commented out. */
1455 #define PUT_SDB_BLOCK_START(LINE) \
1457 extern FILE *asm_out_text_file; \
1458 fprintf (asm_out_text_file, \
1459 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1460 LOCAL_LABEL_PREFIX, \
1462 (TARGET_GAS) ? "" : "#", \
1463 LOCAL_LABEL_PREFIX, \
1466 sdb_label_count++; \
1469 #define PUT_SDB_BLOCK_END(LINE) \
1471 extern FILE *asm_out_text_file; \
1472 fprintf (asm_out_text_file, \
1473 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1474 LOCAL_LABEL_PREFIX, \
1476 (TARGET_GAS) ? "" : "#", \
1477 LOCAL_LABEL_PREFIX, \
1480 sdb_label_count++; \
1483 #define PUT_SDB_FUNCTION_START(LINE)
1485 #define PUT_SDB_FUNCTION_END(LINE) \
1487 extern FILE *asm_out_text_file; \
1488 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1491 #define PUT_SDB_EPILOGUE_END(NAME)
1493 #define PUT_SDB_SRC_FILE(FILENAME) \
1495 extern FILE *asm_out_text_file; \
1496 output_file_directive (asm_out_text_file, (FILENAME));\
1499 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1500 sprintf ((BUFFER), ".%dfake", (NUMBER));
1502 /* Correct the offset of automatic variables and arguments. Note that
1503 the MIPS debug format wants all automatic variables and arguments
1504 to be in terms of the virtual frame pointer (stack pointer before
1505 any adjustment in the function), while the MIPS 3.0 linker wants
1506 the frame pointer to be the stack pointer after the initial
1509 #define DEBUGGER_AUTO_OFFSET(X) \
1510 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1511 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1512 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1514 /* Tell collect that the object format is ECOFF */
1515 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1516 #define EXTENDED_COFF /* ECOFF, not normal coff */
1518 /* Target machine storage layout */
1520 /* Define this if most significant bit is lowest numbered
1521 in instructions that operate on numbered bit-fields.
1523 #define BITS_BIG_ENDIAN 0
1525 /* Define this if most significant byte of a word is the lowest numbered. */
1526 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1528 /* Define this if most significant word of a multiword number is the lowest. */
1529 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1531 /* Define this to set the endianness to use in libgcc2.c, which can
1532 not depend on target_flags. */
1533 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1534 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1536 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1539 #define MAX_BITS_PER_WORD 64
1541 /* Width of a word, in units (bytes). */
1542 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1543 #define MIN_UNITS_PER_WORD 4
1545 /* For MIPS, width of a floating point register. */
1546 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1548 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1549 the next available register. */
1550 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1552 /* The largest size of value that can be held in floating-point
1553 registers and moved with a single instruction. */
1554 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1556 /* The largest size of value that can be held in floating-point
1558 #define UNITS_PER_FPVALUE \
1559 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1561 /* The number of bytes in a double. */
1562 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1564 /* A C expression for the size in bits of the type `int' on the
1565 target machine. If you don't define this, the default is one
1567 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1569 /* Tell the preprocessor the maximum size of wchar_t. */
1570 #ifndef MAX_WCHAR_TYPE_SIZE
1571 #ifndef WCHAR_TYPE_SIZE
1572 #define MAX_WCHAR_TYPE_SIZE 64
1576 /* A C expression for the size in bits of the type `short' on the
1577 target machine. If you don't define this, the default is half a
1578 word. (If this would be less than one storage unit, it is
1579 rounded up to one unit.) */
1580 #define SHORT_TYPE_SIZE 16
1582 /* A C expression for the size in bits of the type `long' on the
1583 target machine. If you don't define this, the default is one
1585 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1586 #define MAX_LONG_TYPE_SIZE 64
1588 /* A C expression for the size in bits of the type `long long' on the
1589 target machine. If you don't define this, the default is two
1591 #define LONG_LONG_TYPE_SIZE 64
1593 /* A C expression for the size in bits of the type `float' on the
1594 target machine. If you don't define this, the default is one
1596 #define FLOAT_TYPE_SIZE 32
1598 /* A C expression for the size in bits of the type `double' on the
1599 target machine. If you don't define this, the default is two
1601 #define DOUBLE_TYPE_SIZE 64
1603 /* A C expression for the size in bits of the type `long double' on
1604 the target machine. If you don't define this, the default is two
1606 #define LONG_DOUBLE_TYPE_SIZE \
1607 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1609 /* long double is not a fixed mode, but the idea is that, if we
1610 support long double, we also want a 128-bit integer type. */
1611 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1614 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1615 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1616 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1618 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1622 /* Width in bits of a pointer. */
1623 #ifndef POINTER_SIZE
1624 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1627 #define POINTERS_EXTEND_UNSIGNED 0
1629 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1630 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1631 || mips_abi == ABI_64 \
1632 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1635 /* Allocation boundary (in *bits*) for the code of a function. */
1636 #define FUNCTION_BOUNDARY 32
1638 /* Alignment of field after `int : 0' in a structure. */
1639 #define EMPTY_FIELD_BOUNDARY 32
1641 /* Every structure's size must be a multiple of this. */
1642 /* 8 is observed right on a DECstation and on riscos 4.02. */
1643 #define STRUCTURE_SIZE_BOUNDARY 8
1645 /* There is no point aligning anything to a rounder boundary than this. */
1646 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1648 /* Set this nonzero if move instructions will actually fail to work
1649 when given unaligned data. */
1650 #define STRICT_ALIGNMENT 1
1652 /* Define this if you wish to imitate the way many other C compilers
1653 handle alignment of bitfields and the structures that contain
1656 The behavior is that the type written for a bit-field (`int',
1657 `short', or other integer type) imposes an alignment for the
1658 entire structure, as if the structure really did contain an
1659 ordinary field of that type. In addition, the bit-field is placed
1660 within the structure so that it would fit within such a field,
1661 not crossing a boundary for it.
1663 Thus, on most machines, a bit-field whose type is written as `int'
1664 would not cross a four-byte boundary, and would force four-byte
1665 alignment for the whole structure. (The alignment used may not
1666 be four bytes; it is controlled by the other alignment
1669 If the macro is defined, its definition should be a C expression;
1670 a nonzero value for the expression enables this behavior. */
1672 #define PCC_BITFIELD_TYPE_MATTERS 1
1674 /* If defined, a C expression to compute the alignment given to a
1675 constant that is being placed in memory. CONSTANT is the constant
1676 and ALIGN is the alignment that the object would ordinarily have.
1677 The value of this macro is used instead of that alignment to align
1680 If this macro is not defined, then ALIGN is used.
1682 The typical use of this macro is to increase alignment for string
1683 constants to be word aligned so that `strcpy' calls that copy
1684 constants can be done inline. */
1686 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1687 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1688 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1690 /* If defined, a C expression to compute the alignment for a static
1691 variable. TYPE is the data type, and ALIGN is the alignment that
1692 the object would ordinarily have. The value of this macro is used
1693 instead of that alignment to align the object.
1695 If this macro is not defined, then ALIGN is used.
1697 One use of this macro is to increase alignment of medium-size
1698 data to make it all fit in fewer cache lines. Another is to
1699 cause character arrays to be word-aligned so that `strcpy' calls
1700 that copy constants to character arrays can be done inline. */
1702 #undef DATA_ALIGNMENT
1703 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1704 ((((ALIGN) < BITS_PER_WORD) \
1705 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1706 || TREE_CODE (TYPE) == UNION_TYPE \
1707 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1710 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1712 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1714 /* Define this macro if an argument declared as `char' or `short' in a
1715 prototype should actually be passed as an `int'. In addition to
1716 avoiding errors in certain cases of mismatch, it also makes for
1717 better code on certain machines. */
1719 #define PROMOTE_PROTOTYPES 1
1721 /* Define if operations between registers always perform the operation
1722 on the full register even if a narrower mode is specified. */
1723 #define WORD_REGISTER_OPERATIONS
1725 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1726 will either zero-extend or sign-extend. The value of this macro should
1727 be the code that says which one of the two operations is implicitly
1730 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1731 moves. All other referces are zero extended. */
1732 #define LOAD_EXTEND_OP(MODE) \
1733 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1734 ? SIGN_EXTEND : ZERO_EXTEND)
1736 /* Define this macro if it is advisable to hold scalars in registers
1737 in a wider mode than that declared by the program. In such cases,
1738 the value is constrained to be within the bounds of the declared
1739 type, but kept valid in the wider mode. The signedness of the
1740 extension may differ from that of the type. */
1742 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1743 if (GET_MODE_CLASS (MODE) == MODE_INT \
1744 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1746 if ((MODE) == SImode) \
1751 /* Define if loading short immediate values into registers sign extends. */
1752 #define SHORT_IMMEDIATES_SIGN_EXTEND
1755 /* Define this if function arguments should also be promoted using the above
1757 #define PROMOTE_FUNCTION_ARGS
1759 /* Likewise, if the function return value is promoted. */
1760 #define PROMOTE_FUNCTION_RETURN
1763 /* Standard register usage. */
1765 /* Number of actual hardware registers.
1766 The hardware registers are assigned numbers for the compiler
1767 from 0 to just below FIRST_PSEUDO_REGISTER.
1768 All registers that the compiler knows about must be given numbers,
1769 even those that are not normally considered general registers.
1771 On the Mips, we have 32 integer registers, 32 floating point
1772 registers, 8 condition code registers, and the special registers
1773 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1774 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1775 processor.) The 8 condition code registers are only used if
1776 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1777 represents a 64 bit value stored as two 32 bit values in the hi and
1778 lo registers; this is the result of the mult instruction. rap is a
1779 pointer to the stack where the return address reg ($31) was stored.
1780 This is needed for C++ exception handling. */
1782 #define FIRST_PSEUDO_REGISTER 176
1784 /* 1 for registers that have pervasive standard uses
1785 and are not available for the register allocator.
1787 On the MIPS, see conventions, page D-2 */
1789 /* Regarding coprocessor registers: without evidence to the contrary,
1790 it's best to assume that each coprocessor register has a unique
1791 use. This can be overridden, in, e.g., override_options() or
1792 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1793 for a particular target. */
1795 #define FIXED_REGISTERS \
1797 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1798 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1799 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1800 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1801 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1802 /* COP0 registers */ \
1803 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1804 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1805 /* COP2 registers */ \
1806 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1807 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1808 /* COP3 registers */ \
1809 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1810 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1814 /* Don't mark $31 as a call-clobbered register. The idea is that
1815 it's really the call instructions themselves which clobber $31.
1816 We don't care what the called function does with it afterwards.
1818 This approach makes it easier to implement sibcalls. Unlike normal
1819 calls, sibcalls don't clobber $31, so the register reaches the
1820 called function in tact. EPILOGUE_USES says that $31 is useful
1821 to the called function. */
1823 #define CALL_USED_REGISTERS \
1825 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1826 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1827 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1828 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1829 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1830 /* COP0 registers */ \
1831 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1832 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1833 /* COP2 registers */ \
1834 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1835 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1836 /* COP3 registers */ \
1837 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1838 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1841 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1842 problem which makes CALL_USED_REGISTERS *always* include
1843 all the FIXED_REGISTERS. Until this problem has been
1844 resolved this macro can be used to overcome this situation.
1845 In particular, block_propagate() requires this list
1846 be acurate, or we can remove registers which should be live.
1847 This macro is used in regs_invalidated_by_call. */
1850 #define CALL_REALLY_USED_REGISTERS \
1851 { /* General registers. */ \
1852 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1853 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1854 /* Floating-point registers. */ \
1855 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1856 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1858 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1859 /* COP0 registers */ \
1860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1862 /* COP2 registers */ \
1863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1865 /* COP3 registers */ \
1866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1870 /* Internal macros to classify a register number as to whether it's a
1871 general purpose register, a floating point register, a
1872 multiply/divide register, or a status register. */
1874 #define GP_REG_FIRST 0
1875 #define GP_REG_LAST 31
1876 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1877 #define GP_DBX_FIRST 0
1879 #define FP_REG_FIRST 32
1880 #define FP_REG_LAST 63
1881 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1882 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1884 #define MD_REG_FIRST 64
1885 #define MD_REG_LAST 66
1886 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1887 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1889 #define ST_REG_FIRST 67
1890 #define ST_REG_LAST 74
1891 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1894 /* FIXME: renumber. */
1895 #define COP0_REG_FIRST 80
1896 #define COP0_REG_LAST 111
1897 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1899 #define COP2_REG_FIRST 112
1900 #define COP2_REG_LAST 143
1901 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1903 #define COP3_REG_FIRST 144
1904 #define COP3_REG_LAST 175
1905 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1906 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1907 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1909 #define AT_REGNUM (GP_REG_FIRST + 1)
1910 #define HI_REGNUM (MD_REG_FIRST + 0)
1911 #define LO_REGNUM (MD_REG_FIRST + 1)
1912 #define HILO_REGNUM (MD_REG_FIRST + 2)
1914 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1915 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1916 should be used instead. */
1917 #define FPSW_REGNUM ST_REG_FIRST
1919 #define GP_REG_P(REGNO) \
1920 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1921 #define M16_REG_P(REGNO) \
1922 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1923 #define FP_REG_P(REGNO) \
1924 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1925 #define MD_REG_P(REGNO) \
1926 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1927 #define ST_REG_P(REGNO) \
1928 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1929 #define COP0_REG_P(REGNO) \
1930 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1931 #define COP2_REG_P(REGNO) \
1932 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1933 #define COP3_REG_P(REGNO) \
1934 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1935 #define ALL_COP_REG_P(REGNO) \
1936 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1938 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1940 /* Return coprocessor number from register number. */
1942 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1943 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1944 : COP3_REG_P (REGNO) ? '3' : '?')
1946 /* Return number of consecutive hard regs needed starting at reg REGNO
1947 to hold something of mode MODE.
1948 This is ordinarily the length in words of a value of mode MODE
1949 but can be less for certain modes in special long registers.
1951 On the MIPS, all general registers are one word long. Except on
1952 the R4000 with the FR bit set, the floating point uses register
1953 pairs, with the second register not being allocable. */
1955 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1957 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1958 MODE. In 32 bit mode, require that DImode and DFmode be in even
1959 registers. For DImode, this makes some of the insns easier to
1960 write, since you don't have to worry about a DImode value in
1961 registers 3 & 4, producing a result in 4 & 5.
1963 To make the code simpler HARD_REGNO_MODE_OK now just references an
1964 array built in override_options. Because machmodes.h is not yet
1965 included before this file is processed, the MODE bound can't be
1968 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1970 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1971 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1973 /* Value is 1 if it is a good idea to tie two pseudo registers
1974 when one has mode MODE1 and one has mode MODE2.
1975 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1976 for any hard reg, then this must be 0 for correct output. */
1977 #define MODES_TIEABLE_P(MODE1, MODE2) \
1978 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1979 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1980 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1981 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1983 /* MIPS pc is not overloaded on a register. */
1984 /* #define PC_REGNUM xx */
1986 /* Register to use for pushing function arguments. */
1987 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1989 /* Offset from the stack pointer to the first available location. Use
1990 the default value zero. */
1991 /* #define STACK_POINTER_OFFSET 0 */
1993 /* Base register for access to local variables of the function. We
1994 pretend that the frame pointer is $1, and then eliminate it to
1995 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1996 a fixed register, and will not be used for anything else. */
1997 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1999 /* Temporary scratch register for use by the assembler. */
2000 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
2002 /* $30 is not available on the mips16, so we use $17 as the frame
2004 #define HARD_FRAME_POINTER_REGNUM \
2005 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
2007 /* Value should be nonzero if functions must have frame pointers.
2008 Zero means the frame pointer need not be set up (and parms
2009 may be accessed via the stack pointer) in functions that seem suitable.
2010 This is computed in `reload', in reload1.c. */
2011 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
2013 /* Base register for access to arguments of the function. */
2014 #define ARG_POINTER_REGNUM GP_REG_FIRST
2016 /* Register in which static-chain is passed to a function. */
2017 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
2019 /* If the structure value address is passed in a register, then
2020 `STRUCT_VALUE_REGNUM' should be the number of that register. */
2021 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
2023 /* If the structure value address is not passed in a register, define
2024 `STRUCT_VALUE' as an expression returning an RTX for the place
2025 where the address is passed. If it returns 0, the address is
2026 passed as an "invisible" first argument. */
2027 #define STRUCT_VALUE 0
2029 /* Mips registers used in prologue/epilogue code when the stack frame
2030 is larger than 32K bytes. These registers must come from the
2031 scratch register set, and not used for passing and returning
2032 arguments and any other information used in the calling sequence
2033 (such as pic). Must start at 12, since t0/t3 are parameter passing
2034 registers in the 64 bit ABI. */
2036 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
2037 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
2039 /* Define this macro if it is as good or better to call a constant
2040 function address than to call an address kept in a register. */
2041 #define NO_FUNCTION_CSE 1
2043 /* Define this macro if it is as good or better for a function to
2044 call itself with an explicit address than to call an address
2045 kept in a register. */
2046 #define NO_RECURSIVE_FUNCTION_CSE 1
2048 /* The register number of the register used to address a table of
2049 static data addresses in memory. In some cases this register is
2050 defined by a processor's "application binary interface" (ABI).
2051 When this macro is defined, RTL is generated for this register
2052 once, as with the stack pointer and frame pointer registers. If
2053 this macro is not defined, it is up to the machine-dependent
2054 files to allocate such a register (if necessary). */
2055 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
2057 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
2059 /* Define the classes of registers for register constraints in the
2060 machine description. Also define ranges of constants.
2062 One of the classes must always be named ALL_REGS and include all hard regs.
2063 If there is more than one class, another class must be named NO_REGS
2064 and contain no registers.
2066 The name GENERAL_REGS must be the name of a class (or an alias for
2067 another name such as ALL_REGS). This is the class of registers
2068 that is allowed by "g" or "r" in a register constraint.
2069 Also, registers outside this class are allocated only when
2070 instructions express preferences for them.
2072 The classes must be numbered in nondecreasing order; that is,
2073 a larger-numbered class must never be contained completely
2074 in a smaller-numbered class.
2076 For any two classes, it is very desirable that there be another
2077 class that represents their union. */
2081 NO_REGS, /* no registers in set */
2082 M16_NA_REGS, /* mips16 regs not used to pass args */
2083 M16_REGS, /* mips16 directly accessible registers */
2084 T_REG, /* mips16 T register ($24) */
2085 M16_T_REGS, /* mips16 registers plus T register */
2086 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2087 LEA_REGS, /* Every GPR except $25 */
2088 GR_REGS, /* integer registers */
2089 FP_REGS, /* floating point registers */
2090 HI_REG, /* hi register */
2091 LO_REG, /* lo register */
2092 HILO_REG, /* hilo register pair for 64 bit mode mult */
2093 MD_REGS, /* multiply/divide registers (hi/lo) */
2094 COP0_REGS, /* generic coprocessor classes */
2097 HI_AND_GR_REGS, /* union classes */
2105 ALL_COP_AND_GR_REGS,
2106 ST_REGS, /* status registers (fp status) */
2107 ALL_REGS, /* all registers */
2108 LIM_REG_CLASSES /* max value + 1 */
2111 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2113 #define GENERAL_REGS GR_REGS
2115 /* An initializer containing the names of the register classes as C
2116 string constants. These names are used in writing some of the
2119 #define REG_CLASS_NAMES \
2126 "PIC_FN_ADDR_REG", \
2134 /* coprocessor registers */ \
2140 "HILO_AND_GR_REGS", \
2142 "COP0_AND_GR_REGS", \
2143 "COP2_AND_GR_REGS", \
2144 "COP3_AND_GR_REGS", \
2146 "ALL_COP_AND_GR_REGS", \
2151 /* An initializer containing the contents of the register classes,
2152 as integers which are bit masks. The Nth integer specifies the
2153 contents of class N. The way the integer MASK is interpreted is
2154 that register R is in the class if `MASK & (1 << R)' is 1.
2156 When the machine has more than 32 registers, an integer does not
2157 suffice. Then the integers are replaced by sub-initializers,
2158 braced groupings containing several integers. Each
2159 sub-initializer must be suitable as an initializer for the type
2160 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2162 #define REG_CLASS_CONTENTS \
2164 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2165 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2166 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2167 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2168 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2169 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
2170 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
2171 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2172 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2173 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2174 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2175 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2176 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2177 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2178 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2179 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2180 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2181 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2182 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2183 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2184 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2185 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2186 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2187 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2188 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2189 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2190 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2194 /* A C expression whose value is a register class containing hard
2195 register REGNO. In general there is more that one such class;
2196 choose a class which is "minimal", meaning that no smaller class
2197 also contains the register. */
2199 extern const enum reg_class mips_regno_to_class[];
2201 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2203 /* A macro whose definition is the name of the class to which a
2204 valid base register must belong. A base register is one used in
2205 an address which is the register value plus a displacement. */
2207 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2209 /* A macro whose definition is the name of the class to which a
2210 valid index register must belong. An index register is one used
2211 in an address where its value is either multiplied by a scale
2212 factor or added to another register (as well as added to a
2215 #define INDEX_REG_CLASS NO_REGS
2217 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2218 registers explicitly used in the rtl to be used as spill registers
2219 but prevents the compiler from extending the lifetime of these
2222 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2224 /* This macro is used later on in the file. */
2225 #define GR_REG_CLASS_P(CLASS) \
2226 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2227 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
2228 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
2230 /* This macro is also used later on in the file. */
2231 #define COP_REG_CLASS_P(CLASS) \
2232 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2234 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2235 is the default value (allocate the registers in numeric order). We
2236 define it just so that we can override it for the mips16 target in
2237 ORDER_REGS_FOR_LOCAL_ALLOC. */
2239 #define REG_ALLOC_ORDER \
2240 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2241 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2242 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2243 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2244 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2245 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2246 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2247 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2248 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2249 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2250 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2253 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2254 to be rearranged based on a particular function. On the mips16, we
2255 want to allocate $24 (T_REG) before other registers for
2256 instructions for which it is possible. */
2258 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2260 /* REGISTER AND CONSTANT CLASSES */
2262 /* Get reg_class from a letter such as appears in the machine
2265 DEFINED REGISTER CLASSES:
2267 'd' General (aka integer) registers
2268 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2269 'y' General registers (in both mips16 and non mips16 mode)
2270 'e' mips16 non argument registers (M16_NA_REGS)
2271 't' mips16 temporary register ($24)
2272 'f' Floating point registers
2275 'x' Multiply/divide registers
2277 'z' FP Status register
2281 'b' All registers */
2283 extern enum reg_class mips_char_to_class[256];
2285 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2287 /* True if VALUE is a signed 16-bit number. */
2289 #define SMALL_OPERAND(VALUE) \
2290 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2292 /* True if VALUE is an unsigned 16-bit number. */
2294 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2295 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2297 /* True if VALUE can be loaded into a register using LUI. */
2299 #define LUI_OPERAND(VALUE) \
2300 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2301 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2303 /* Return a value X with the low 16 bits clear, and such that
2304 VALUE - X is a signed 16-bit value. */
2306 #define CONST_HIGH_PART(VALUE) \
2307 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2309 #define CONST_LOW_PART(VALUE) \
2310 ((VALUE) - CONST_HIGH_PART (VALUE))
2312 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2313 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2314 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2316 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2317 string can be used to stand for particular ranges of immediate
2318 operands. This macro defines what the ranges are. C is the
2319 letter, and VALUE is a constant value. Return 1 if VALUE is
2320 in the range specified by C. */
2324 `I' is used for the range of constants an arithmetic insn can
2325 actually contain (16 bits signed integers).
2327 `J' is used for the range which is just zero (ie, $r0).
2329 `K' is used for the range of constants a logical insn can actually
2330 contain (16 bit zero-extended integers).
2332 `L' is used for the range of constants that be loaded with lui
2333 (ie, the bottom 16 bits are zero).
2335 `M' is used for the range of constants that take two words to load
2336 (ie, not matched by `I', `K', and `L').
2338 `N' is used for negative 16 bit constants other than -65536.
2340 `O' is a 15 bit signed integer.
2342 `P' is used for positive 16 bit constants. */
2344 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2345 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2346 : (C) == 'J' ? ((VALUE) == 0) \
2347 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2348 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2349 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2350 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2351 && !LUI_OPERAND (VALUE)) \
2352 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2353 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2354 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2357 /* Similar, but for floating constants, and defining letters G and H.
2358 Here VALUE is the CONST_DOUBLE rtx itself. */
2362 'G' : Floating point 0 */
2364 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2366 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2368 /* True if OP is a constant that should not be moved into $25.
2369 We need this because many versions of gas treat 'la $25,foo' as
2370 part of a call sequence and allow a global 'foo' to be lazily bound. */
2372 #define DANGEROUS_FOR_LA25_P(OP) \
2374 && !TARGET_EXPLICIT_RELOCS \
2375 && mips_global_pic_constant_p (OP))
2377 /* Letters in the range `Q' through `U' may be defined in a
2378 machine-dependent fashion to stand for arbitrary operand types.
2379 The machine description macro `EXTRA_CONSTRAINT' is passed the
2380 operand as its first argument and the constraint letter as its
2383 `Q' is for signed 16-bit constants.
2384 `R' is for single-instruction memory references. Note that this
2385 constraint has often been used in linux and glibc code.
2386 `S' is for legitimate constant call addresses.
2387 `T' is for constant move_operands that cannot be safely loaded into $25.
2388 `U' is for constant move_operands that can be safely loaded into $25. */
2390 #define EXTRA_CONSTRAINT(OP,CODE) \
2391 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2392 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2393 && mips_fetch_insns (OP) == 1) \
2394 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2395 && call_insn_operand (OP, VOIDmode)) \
2396 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2397 && move_operand (OP, VOIDmode) \
2398 && DANGEROUS_FOR_LA25_P (OP)) \
2399 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2400 && move_operand (OP, VOIDmode) \
2401 && !DANGEROUS_FOR_LA25_P (OP)) \
2404 /* Given an rtx X being reloaded into a reg required to be
2405 in class CLASS, return the class of reg to actually use.
2406 In general this is just CLASS; but on some machines
2407 in some cases it is preferable to use a more restrictive class. */
2409 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2410 ((CLASS) != ALL_REGS \
2411 ? (! TARGET_MIPS16 \
2413 : ((CLASS) != GR_REGS \
2416 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2417 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2418 ? (TARGET_SOFT_FLOAT \
2419 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2421 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2422 || GET_MODE (X) == VOIDmode) \
2423 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2426 /* Certain machines have the property that some registers cannot be
2427 copied to some other registers without using memory. Define this
2428 macro on those machines to be a C expression that is nonzero if
2429 objects of mode MODE in registers of CLASS1 can only be copied to
2430 registers of class CLASS2 by storing a register of CLASS1 into
2431 memory and loading that memory location into a register of CLASS2.
2433 Do not define this macro if its value would always be zero. */
2435 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2436 ((!TARGET_DEBUG_H_MODE \
2437 && GET_MODE_CLASS (MODE) == MODE_INT \
2438 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2439 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2440 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2441 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2442 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2444 /* The HI and LO registers can only be reloaded via the general
2445 registers. Condition code registers can only be loaded to the
2446 general registers, and from the floating point registers. */
2448 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2449 mips_secondary_reload_class (CLASS, MODE, X, 1)
2450 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2451 mips_secondary_reload_class (CLASS, MODE, X, 0)
2453 /* Return the maximum number of consecutive registers
2454 needed to represent mode MODE in a register of class CLASS. */
2456 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2458 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2459 mips_cannot_change_mode_class (FROM, TO, CLASS)
2461 /* Stack layout; function entry, exit and calling. */
2463 /* Define this if pushing a word on the stack
2464 makes the stack pointer a smaller address. */
2465 #define STACK_GROWS_DOWNWARD
2467 /* Define this if the nominal address of the stack frame
2468 is at the high-address end of the local variables;
2469 that is, each additional local variable allocated
2470 goes at a more negative offset in the frame. */
2471 /* #define FRAME_GROWS_DOWNWARD */
2473 /* Offset within stack frame to start allocating local variables at.
2474 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2475 first local allocated. Otherwise, it is the offset to the BEGINNING
2476 of the first local allocated. */
2477 #define STARTING_FRAME_OFFSET \
2478 (current_function_outgoing_args_size \
2479 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2481 /* Offset from the stack pointer register to an item dynamically
2482 allocated on the stack, e.g., by `alloca'.
2484 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2485 length of the outgoing arguments. The default is correct for most
2486 machines. See `function.c' for details.
2488 The MIPS ABI states that functions which dynamically allocate the
2489 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2490 we are trying to create a second frame pointer to the function, so
2491 allocate some stack space to make it happy.
2493 However, the linker currently complains about linking any code that
2494 dynamically allocates stack space, and there seems to be a bug in
2495 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2498 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2499 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2500 ? 4*UNITS_PER_WORD \
2501 : current_function_outgoing_args_size)
2504 /* The return address for the current frame is in r31 if this is a leaf
2505 function. Otherwise, it is on the stack. It is at a variable offset
2506 from sp/fp/ap, so we define a fake hard register rap which is a
2507 poiner to the return address on the stack. This always gets eliminated
2508 during reload to be either the frame pointer or the stack pointer plus
2511 #define RETURN_ADDR_RTX mips_return_addr
2513 /* Since the mips16 ISA mode is encoded in the least-significant bit
2514 of the address, mask it off return addresses for purposes of
2515 finding exception handling regions. */
2517 #define MASK_RETURN_ADDR GEN_INT (-2)
2520 /* Similarly, don't use the least-significant bit to tell pointers to
2521 code from vtable index. */
2523 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2525 /* If defined, this macro specifies a table of register pairs used to
2526 eliminate unneeded registers that point into the stack frame. If
2527 it is not defined, the only elimination attempted by the compiler
2528 is to replace references to the frame pointer with references to
2531 The definition of this macro is a list of structure
2532 initializations, each of which specifies an original and
2533 replacement register.
2535 On some machines, the position of the argument pointer is not
2536 known until the compilation is completed. In such a case, a
2537 separate hard register must be used for the argument pointer.
2538 This register can be eliminated by replacing it with either the
2539 frame pointer or the argument pointer, depending on whether or not
2540 the frame pointer has been eliminated.
2542 In this case, you might specify:
2543 #define ELIMINABLE_REGS \
2544 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2545 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2546 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2548 Note that the elimination of the argument pointer with the stack
2549 pointer is specified first since that is the preferred elimination.
2551 The eliminations to $17 are only used on the mips16. See the
2552 definition of HARD_FRAME_POINTER_REGNUM. */
2554 #define ELIMINABLE_REGS \
2555 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2556 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2557 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2558 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2559 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2560 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2562 /* A C expression that returns nonzero if the compiler is allowed to
2563 try to replace register number FROM-REG with register number
2564 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2565 defined, and will usually be the constant 1, since most of the
2566 cases preventing register elimination are things that the compiler
2567 already knows about.
2569 When not in mips16 and mips64, we can always eliminate to the
2570 frame pointer. We can eliminate to the stack pointer unless
2571 a frame pointer is needed. In mips16 mode, we need a frame
2572 pointer for a large frame; otherwise, reload may be unable
2573 to compute the address of a local variable, since there is
2574 no way to add a large constant to the stack pointer
2575 without using a temporary register.
2577 In mips16, for some instructions (eg lwu), we can't eliminate the
2578 frame pointer for the stack pointer. These instructions are
2579 only generated in TARGET_64BIT mode.
2582 #define CAN_ELIMINATE(FROM, TO) \
2583 (((TO) == HARD_FRAME_POINTER_REGNUM \
2584 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2585 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2586 && (! TARGET_MIPS16 \
2587 || compute_frame_size (get_frame_size ()) < 32768))))
2589 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2590 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2592 /* If we generate an insn to push BYTES bytes,
2593 this says how many the stack pointer really advances by.
2594 On the VAX, sp@- in a byte insn really pushes a word. */
2596 /* #define PUSH_ROUNDING(BYTES) 0 */
2598 /* If defined, the maximum amount of space required for outgoing
2599 arguments will be computed and placed into the variable
2600 `current_function_outgoing_args_size'. No space will be pushed
2601 onto the stack for each call; instead, the function prologue
2602 should increase the stack frame size by this amount.
2604 It is not proper to define both `PUSH_ROUNDING' and
2605 `ACCUMULATE_OUTGOING_ARGS'. */
2606 #define ACCUMULATE_OUTGOING_ARGS 1
2608 /* Offset from the argument pointer register to the first argument's
2609 address. On some machines it may depend on the data type of the
2612 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2613 the first argument's address.
2615 On the MIPS, we must skip the first argument position if we are
2616 returning a structure or a union, to account for its address being
2617 passed in $4. However, at the current time, this produces a compiler
2618 that can't bootstrap, so comment it out for now. */
2621 #define FIRST_PARM_OFFSET(FNDECL) \
2623 && TREE_TYPE (FNDECL) != 0 \
2624 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2625 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2626 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2630 #define FIRST_PARM_OFFSET(FNDECL) 0
2633 /* When a parameter is passed in a register, stack space is still
2634 allocated for it. For the MIPS, stack space must be allocated, cf
2635 Asm Lang Prog Guide page 7-8.
2637 BEWARE that some space is also allocated for non existing arguments
2638 in register. In case an argument list is of form GF used registers
2639 are a0 (a2,a3), but we should push over a1... */
2641 #define REG_PARM_STACK_SPACE(FNDECL) \
2642 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2643 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2646 /* Define this if it is the responsibility of the caller to
2647 allocate the area reserved for arguments passed in registers.
2648 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2649 of this macro is to determine whether the space is included in
2650 `current_function_outgoing_args_size'. */
2651 #define OUTGOING_REG_PARM_STACK_SPACE
2653 #define STACK_BOUNDARY \
2654 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2657 /* Make sure 4 words are always allocated on the stack. */
2659 #ifndef STACK_ARGS_ADJUST
2660 #define STACK_ARGS_ADJUST(SIZE) \
2662 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2663 SIZE.constant = 4 * UNITS_PER_WORD; \
2668 /* A C expression that should indicate the number of bytes of its
2669 own arguments that a function pops on returning, or 0
2670 if the function pops no arguments and the caller must therefore
2671 pop them all after the function returns.
2673 FUNDECL is the declaration node of the function (as a tree).
2675 FUNTYPE is a C variable whose value is a tree node that
2676 describes the function in question. Normally it is a node of
2677 type `FUNCTION_TYPE' that describes the data type of the function.
2678 From this it is possible to obtain the data types of the value
2679 and arguments (if known).
2681 When a call to a library function is being considered, FUNTYPE
2682 will contain an identifier node for the library function. Thus,
2683 if you need to distinguish among various library functions, you
2684 can do so by their names. Note that "library function" in this
2685 context means a function used to perform arithmetic, whose name
2686 is known specially in the compiler and was not mentioned in the
2687 C code being compiled.
2689 STACK-SIZE is the number of bytes of arguments passed on the
2690 stack. If a variable number of bytes is passed, it is zero, and
2691 argument popping will always be the responsibility of the
2692 calling function. */
2694 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2697 /* Symbolic macros for the registers used to return integer and floating
2700 #define GP_RETURN (GP_REG_FIRST + 2)
2701 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2703 #define MAX_ARGS_IN_REGISTERS \
2704 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2706 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2708 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2710 /* Symbolic macros for the first/last argument registers. */
2712 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2713 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2714 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2715 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2717 /* Define how to find the value returned by a library function
2718 assuming the value has mode MODE. Because we define
2719 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2720 PROMOTE_MODE does. */
2722 #define LIBCALL_VALUE(MODE) \
2723 mips_function_value (NULL_TREE, NULL, (MODE))
2725 /* Define how to find the value returned by a function.
2726 VALTYPE is the data type of the value (as a tree).
2727 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2728 otherwise, FUNC is 0. */
2730 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2731 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2733 /* 1 if N is a possible register number for a function value.
2734 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2735 Currently, R2 and F0 are only implemented here (C has no complex type) */
2737 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2738 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2739 && (N) == FP_RETURN + 2))
2741 /* 1 if N is a possible register number for function argument passing.
2742 We have no FP argument registers when soft-float. When FP registers
2743 are 32 bits, we can't directly reference the odd numbered ones. */
2745 #define FUNCTION_ARG_REGNO_P(N) \
2746 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2747 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2748 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2751 /* A C expression which can inhibit the returning of certain function
2752 values in registers, based on the type of value. A nonzero value says
2753 to return the function value in memory, just as large structures are
2754 always returned. Here TYPE will be a C expression of type
2755 `tree', representing the data type of the value.
2757 Note that values of mode `BLKmode' must be explicitly
2758 handled by this macro. Also, the option `-fpcc-struct-return'
2759 takes effect regardless of this macro. On most systems, it is
2760 possible to leave the macro undefined; this causes a default
2761 definition to be used, whose value is the constant 1 for BLKmode
2762 values, and 0 otherwise.
2764 GCC normally converts 1 byte structures into chars, 2 byte
2765 structs into shorts, and 4 byte structs into ints, and returns
2766 them this way. Defining the following macro overrides this,
2767 to give us MIPS cc compatibility. */
2769 #define RETURN_IN_MEMORY(TYPE) \
2770 mips_return_in_memory (TYPE)
2772 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2773 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2776 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2778 /* Define a data type for recording info about an argument list
2779 during the scan of that argument list. This data type should
2780 hold all necessary information about the function itself
2781 and about the args processed so far, enough to enable macros
2782 such as FUNCTION_ARG to determine where the next arg should go.
2784 This structure has to cope with two different argument allocation
2785 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2786 first N words go in registers and the rest go on the stack. If I < N,
2787 the Ith word might go in Ith integer argument register or the
2788 Ith floating-point one. In some cases, it has to go in both (see
2789 function_arg). For these ABIs, we only need to remember the number
2790 of words passed so far.
2792 The EABI instead allocates the integer and floating-point arguments
2793 separately. The first N words of FP arguments go in FP registers,
2794 the rest go on the stack. Likewise, the first N words of the other
2795 arguments go in integer registers, and the rest go on the stack. We
2796 need to maintain three counts: the number of integer registers used,
2797 the number of floating-point registers used, and the number of words
2798 passed on the stack.
2800 We could keep separate information for the two ABIs (a word count for
2801 the standard ABIs, and three separate counts for the EABI). But it
2802 seems simpler to view the standard ABIs as forms of EABI that do not
2803 allocate floating-point registers.
2805 So for the standard ABIs, the first N words are allocated to integer
2806 registers, and function_arg decides on an argument-by-argument basis
2807 whether that argument should really go in an integer register, or in
2808 a floating-point one. */
2810 typedef struct mips_args {
2811 /* Always true for varargs functions. Otherwise true if at least
2812 one argument has been passed in an integer register. */
2815 /* The number of arguments seen so far. */
2816 unsigned int arg_number;
2818 /* For EABI, the number of integer registers used so far. For other
2819 ABIs, the number of words passed in registers (whether integer
2820 or floating-point). */
2821 unsigned int num_gprs;
2823 /* For EABI, the number of floating-point registers used so far. */
2824 unsigned int num_fprs;
2826 /* The number of words passed on the stack. */
2827 unsigned int stack_words;
2829 /* On the mips16, we need to keep track of which floating point
2830 arguments were passed in general registers, but would have been
2831 passed in the FP regs if this were a 32 bit function, so that we
2832 can move them to the FP regs if we wind up calling a 32 bit
2833 function. We record this information in fp_code, encoded in base
2834 four. A zero digit means no floating point argument, a one digit
2835 means an SFmode argument, and a two digit means a DFmode argument,
2836 and a three digit is not used. The low order digit is the first
2837 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2838 an SFmode argument. ??? A more sophisticated approach will be
2839 needed if MIPS_ABI != ABI_32. */
2842 /* True if the function has a prototype. */
2845 /* When a structure does not take up a full register, the argument
2846 should sometimes be shifted left so that it occupies the high part
2847 of the register. These two fields describe an array of ashl
2848 patterns for doing this. See function_arg_advance, which creates
2849 the shift patterns, and function_arg, which returns them when given
2850 a VOIDmode argument. */
2851 unsigned int num_adjusts;
2852 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2855 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2856 for a call to a function whose data type is FNTYPE.
2857 For a library call, FNTYPE is 0.
2861 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2862 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2864 /* Update the data in CUM to advance over an argument
2865 of mode MODE and data type TYPE.
2866 (TYPE is null for libcalls where that information may not be available.) */
2868 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2869 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2871 /* Determine where to put an argument to a function.
2872 Value is zero to push the argument on the stack,
2873 or a hard register in which to store the argument.
2875 MODE is the argument's machine mode.
2876 TYPE is the data type of the argument (as a tree).
2877 This is null for libcalls where that information may
2879 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2880 the preceding args and about the function being called.
2881 NAMED is nonzero if this argument is a named parameter
2882 (otherwise it is an extra parameter matching an ellipsis). */
2884 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2885 function_arg( &CUM, MODE, TYPE, NAMED)
2887 /* For an arg passed partly in registers and partly in memory,
2888 this is the number of registers used.
2889 For args passed entirely in registers or entirely in memory, zero. */
2891 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2892 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2894 /* If defined, a C expression that gives the alignment boundary, in
2895 bits, of an argument with the specified mode and type. If it is
2896 not defined, `PARM_BOUNDARY' is used for all arguments. */
2898 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2900 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2902 : TYPE_ALIGN(TYPE)) \
2903 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2905 : GET_MODE_ALIGNMENT(MODE)))
2907 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2908 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2910 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2911 (! BYTES_BIG_ENDIAN \
2913 : (((MODE) == BLKmode \
2914 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2915 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2916 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2917 && (mips_abi == ABI_32 \
2918 || mips_abi == ABI_O64 \
2919 || mips_abi == ABI_EABI \
2920 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2921 ? downward : upward))
2923 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2924 (mips_abi == ABI_EABI && (NAMED) \
2925 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2927 /* Modified version of the macro in expr.h. */
2928 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2930 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2931 || TREE_ADDRESSABLE (TYPE) \
2932 || ((MODE) == BLKmode \
2933 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2934 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2935 && 0 == (int_size_in_bytes (TYPE) \
2936 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2937 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2938 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2940 /* True if using EABI and varargs can be passed in floating-point
2941 registers. Under these conditions, we need a more complex form
2942 of va_list, which tracks GPR, FPR and stack arguments separately. */
2943 #define EABI_FLOAT_VARARGS_P \
2944 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2947 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2949 #define MUST_SAVE_REGISTER(regno) \
2950 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2951 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2952 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2954 /* Say that the epilogue uses the return address register. Note that
2955 in the case of sibcalls, the values "used by the epilogue" are
2956 considered live at the start of the called function. */
2957 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2959 /* Treat LOC as a byte offset from the stack pointer and round it up
2960 to the next fully-aligned offset. */
2961 #define MIPS_STACK_ALIGN(LOC) \
2962 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2963 ? ((LOC) + 7) & ~7 \
2964 : ((LOC) + 15) & ~15)
2967 /* Define the `__builtin_va_list' type for the ABI. */
2968 #define BUILD_VA_LIST_TYPE(VALIST) \
2969 (VALIST) = mips_build_va_list ()
2971 /* Implement `va_start' for varargs and stdarg. */
2972 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2973 mips_va_start (valist, nextarg)
2975 /* Implement `va_arg'. */
2976 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2977 mips_va_arg (valist, type)
2979 /* Output assembler code to FILE to increment profiler label # LABELNO
2980 for profiling a function entry. */
2982 #define FUNCTION_PROFILER(FILE, LABELNO) \
2984 if (TARGET_MIPS16) \
2985 sorry ("mips16 function profiling"); \
2986 fprintf (FILE, "\t.set\tnoat\n"); \
2987 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2988 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2989 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2992 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2993 TARGET_64BIT ? "dsubu" : "subu", \
2994 reg_names[STACK_POINTER_REGNUM], \
2995 reg_names[STACK_POINTER_REGNUM], \
2996 Pmode == DImode ? 16 : 8); \
2998 fprintf (FILE, "\tjal\t_mcount\n"); \
2999 fprintf (FILE, "\t.set\tat\n"); \
3002 /* Define this macro if the code for function profiling should come
3003 before the function prologue. Normally, the profiling code comes
3006 /* #define PROFILE_BEFORE_PROLOGUE */
3008 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
3009 the stack pointer does not matter. The value is tested only in
3010 functions that have frame pointers.
3011 No definition is equivalent to always zero. */
3013 #define EXIT_IGNORE_STACK 1
3016 /* A C statement to output, on the stream FILE, assembler code for a
3017 block of data that contains the constant parts of a trampoline.
3018 This code should not include a label--the label is taken care of
3021 #define TRAMPOLINE_TEMPLATE(STREAM) \
3023 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
3024 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
3025 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
3026 if (ptr_mode == DImode) \
3028 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
3029 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
3033 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
3034 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
3036 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
3037 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
3038 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
3039 if (ptr_mode == DImode) \
3041 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
3042 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
3046 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
3047 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
3051 /* A C expression for the size in bytes of the trampoline, as an
3054 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
3056 /* Alignment required for trampolines, in bits. */
3058 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
3060 /* INITIALIZE_TRAMPOLINE calls this library function to flush
3061 program and data caches. */
3063 #ifndef CACHE_FLUSH_FUNC
3064 #define CACHE_FLUSH_FUNC "_flush_cache"
3067 /* A C statement to initialize the variable parts of a trampoline.
3068 ADDR is an RTX for the address of the trampoline; FNADDR is an
3069 RTX for the address of the nested function; STATIC_CHAIN is an
3070 RTX for the static chain value that should be passed to the
3071 function when it is called. */
3073 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
3075 rtx func_addr, chain_addr; \
3077 func_addr = plus_constant (ADDR, 32); \
3078 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
3079 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
3080 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
3081 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
3082 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
3084 /* Flush both caches. We need to flush the data cache in case \
3085 the system has a write-back cache. */ \
3086 /* ??? Should check the return value for errors. */ \
3087 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
3088 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
3089 0, VOIDmode, 3, ADDR, Pmode, \
3090 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
3091 GEN_INT (3), TYPE_MODE (integer_type_node)); \
3094 /* Addressing modes, and classification of registers for them. */
3096 /* These assume that REGNO is a hard or pseudo reg number.
3097 They give nonzero only if REGNO is a hard reg of the suitable class
3098 or a pseudo reg currently allocated to a suitable hard reg.
3099 These definitions are NOT overridden anywhere. */
3101 #define BASE_REG_P(regno, mode) \
3103 ? (M16_REG_P (regno) \
3104 || (regno) == FRAME_POINTER_REGNUM \
3105 || (regno) == ARG_POINTER_REGNUM \
3106 || ((regno) == STACK_POINTER_REGNUM \
3107 && (GET_MODE_SIZE (mode) == 4 \
3108 || GET_MODE_SIZE (mode) == 8))) \
3111 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
3112 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3115 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3116 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3118 #define REGNO_OK_FOR_INDEX_P(regno) 0
3119 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3120 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3122 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3123 and check its validity for a certain class.
3124 We have two alternate definitions for each of them.
3125 The usual definition accepts all pseudo regs; the other rejects them all.
3126 The symbol REG_OK_STRICT causes the latter definition to be used.
3128 Most source files want to accept pseudo regs in the hope that
3129 they will get allocated to the class that the insn wants them to be in.
3130 Some source files that are used after register allocation
3131 need to be strict. */
3133 #ifndef REG_OK_STRICT
3134 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3135 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3137 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3138 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3141 #define REG_OK_FOR_INDEX_P(X) 0
3144 /* Maximum number of registers that can appear in a valid memory address. */
3146 #define MAX_REGS_PER_ADDRESS 1
3148 /* A C compound statement with a conditional `goto LABEL;' executed
3149 if X (an RTX) is a legitimate memory address on the target
3150 machine for a memory operand of mode MODE. */
3153 #define GO_PRINTF(x) fprintf(stderr, (x))
3154 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3155 #define GO_DEBUG_RTX(x) debug_rtx(x)
3158 #define GO_PRINTF(x)
3159 #define GO_PRINTF2(x,y)
3160 #define GO_DEBUG_RTX(x)
3163 #ifdef REG_OK_STRICT
3164 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3166 if (mips_legitimate_address_p (MODE, X, 1)) \
3170 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3172 if (mips_legitimate_address_p (MODE, X, 0)) \
3177 /* Check for constness inline but use mips_legitimate_address_p
3178 to check whether a constant really is an address. */
3180 #define CONSTANT_ADDRESS_P(X) \
3181 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
3184 /* Nonzero if the constant value X is a legitimate general operand.
3185 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3187 At present, GAS doesn't understand li.[sd], so don't allow it
3188 to be generated at present. Also, the MIPS assembler does not
3189 grok li.d Infinity. */
3191 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3192 Note that the Irix 6 assembler problem may already be fixed.
3193 Note also that the GET_CODE (X) == CONST test catches the mips16
3194 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3195 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3196 ABI_64 to work together, we'll need to fix this. */
3197 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
3199 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3201 if (mips_legitimize_address (&(X), MODE)) \
3206 /* A C statement or compound statement with a conditional `goto
3207 LABEL;' executed if memory address X (an RTX) can have different
3208 meanings depending on the machine mode of the memory reference it
3211 Autoincrement and autodecrement addresses typically have
3212 mode-dependent effects because the amount of the increment or
3213 decrement is the size of the operand being addressed. Some
3214 machines have other mode-dependent addresses. Many RISC machines
3215 have no mode-dependent addresses.
3217 You may assume that ADDR is a valid address for the machine. */
3219 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3221 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3222 'the start of the function that this code is output in'. */
3224 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3225 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3226 asm_fprintf ((FILE), "%U%s", \
3227 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3229 asm_fprintf ((FILE), "%U%s", (NAME))
3231 /* The mips16 wants the constant pool to be after the function,
3232 because the PC relative load instructions use unsigned offsets. */
3234 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3236 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3237 mips_string_length = 0;
3239 /* Specify the machine mode that this machine uses
3240 for the index in the tablejump instruction.
3241 ??? Using HImode in mips16 mode can cause overflow. However, the
3242 overflow is no more likely than the overflow in a branch
3243 instruction. Large functions can currently break in both ways. */
3244 #define CASE_VECTOR_MODE \
3245 (TARGET_MIPS16 ? HImode : ptr_mode)
3247 /* Define as C expression which evaluates to nonzero if the tablejump
3248 instruction expects the table to contain offsets from the address of the
3250 Do not define this if the table should contain absolute addresses. */
3251 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3253 /* Define this as 1 if `char' should by default be signed; else as 0. */
3254 #ifndef DEFAULT_SIGNED_CHAR
3255 #define DEFAULT_SIGNED_CHAR 1
3258 /* Max number of bytes we can move from memory to memory
3259 in one reasonably fast instruction. */
3260 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3261 #define MAX_MOVE_MAX 8
3263 /* Define this macro as a C expression which is nonzero if
3264 accessing less than a word of memory (i.e. a `char' or a
3265 `short') is no faster than accessing a word of memory, i.e., if
3266 such access require more than one instruction or if there is no
3267 difference in cost between byte and (aligned) word loads.
3269 On RISC machines, it tends to generate better code to define
3270 this as 1, since it avoids making a QI or HI mode register. */
3271 #define SLOW_BYTE_ACCESS 1
3273 /* We assume that the store-condition-codes instructions store 0 for false
3274 and some other value for true. This is the value stored for true. */
3276 #define STORE_FLAG_VALUE 1
3278 /* Define this to be nonzero if shift instructions ignore all but the low-order
3280 #define SHIFT_COUNT_TRUNCATED 1
3282 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3283 is done just by pretending it is already truncated. */
3284 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3285 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3288 /* Specify the machine mode that pointers have.
3289 After generation of rtl, the compiler makes no further distinction
3290 between pointers and any other objects of this machine mode. */
3293 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
3296 /* Give call MEMs SImode since it is the "most permissive" mode
3297 for both 32-bit and 64-bit targets. */
3299 #define FUNCTION_MODE SImode
3302 /* The cost of loading values from the constant pool. It should be
3303 larger than the cost of any constant we want to synthesise in-line. */
3305 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
3307 /* A C expression for the cost of moving data from a register in
3308 class FROM to one in class TO. The classes are expressed using
3309 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3310 the default; other values are interpreted relative to that.
3312 It is not required that the cost always equal 2 when FROM is the
3313 same as TO; on some machines it is expensive to move between
3314 registers if they are not general registers.
3316 If reload sees an insn consisting of a single `set' between two
3317 hard registers, and if `REGISTER_MOVE_COST' applied to their
3318 classes returns a value of 2, reload does not check to ensure
3319 that the constraints of the insn are met. Setting a cost of
3320 other than 2 will allow reload to verify that the constraints are
3321 met. You should do this if the `movM' pattern's constraints do
3322 not allow such copying. */
3324 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3325 mips_register_move_cost (MODE, FROM, TO)
3327 /* ??? Fix this to be right for the R8000. */
3328 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3329 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3330 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3332 /* Define if copies to/from condition code registers should be avoided.
3334 This is needed for the MIPS because reload_outcc is not complete;
3335 it needs to handle cases where the source is a general or another
3336 condition code register. */
3337 #define AVOID_CCMODE_COPIES
3339 /* A C expression for the cost of a branch instruction. A value of
3340 1 is the default; other values are interpreted relative to that. */
3342 /* ??? Fix this to be right for the R8000. */
3343 #define BRANCH_COST \
3345 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3348 /* If defined, modifies the length assigned to instruction INSN as a
3349 function of the context in which it is used. LENGTH is an lvalue
3350 that contains the initially computed length of the insn and should
3351 be updated with the correct length of the insn. */
3352 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3353 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3356 /* Optionally define this if you have added predicates to
3357 `MACHINE.c'. This macro is called within an initializer of an
3358 array of structures. The first field in the structure is the
3359 name of a predicate and the second field is an array of rtl
3360 codes. For each predicate, list all rtl codes that can be in
3361 expressions matched by the predicate. The list should have a
3362 trailing comma. Here is an example of two entries in the list
3363 for a typical RISC machine:
3365 #define PREDICATE_CODES \
3366 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3367 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3369 Defining this macro does not affect the generated code (however,
3370 incorrect definitions that omit an rtl code that may be matched
3371 by the predicate can cause the compiler to malfunction).
3372 Instead, it allows the table built by `genrecog' to be more
3373 compact and efficient, thus speeding up the compiler. The most
3374 important predicates to include in the list specified by this
3375 macro are thoses used in the most insn patterns. */
3377 #define PREDICATE_CODES \
3378 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3379 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3380 {"const_arith_operand", { CONST, CONST_INT }}, \
3381 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3382 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3383 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3384 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3385 {"small_int", { CONST_INT }}, \
3386 {"large_int", { CONST_INT }}, \
3387 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3388 {"const_float_1_operand", { CONST_DOUBLE }}, \
3389 {"simple_memory_operand", { MEM, SUBREG }}, \
3390 {"equality_op", { EQ, NE }}, \
3391 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3393 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3394 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3395 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
3396 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3397 SYMBOL_REF, LABEL_REF, SUBREG, \
3399 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3400 CONST_DOUBLE, CONST }}, \
3401 {"fcc_register_operand", { REG, SUBREG }},
3403 /* A list of predicates that do special things with modes, and so
3404 should not elicit warnings for VOIDmode match_operand. */
3406 #define SPECIAL_MODE_PREDICATES \
3407 "pc_or_label_operand",
3410 /* If defined, a C statement to be executed just prior to the
3411 output of assembler code for INSN, to modify the extracted
3412 operands so they will be output differently.
3414 Here the argument OPVEC is the vector containing the operands
3415 extracted from INSN, and NOPERANDS is the number of elements of
3416 the vector which contain meaningful data for this insn. The
3417 contents of this vector are what will be used to convert the
3418 insn template into assembler code, so you can change the
3419 assembler output by changing the contents of the vector.
3421 We use it to check if the current insn needs a nop in front of it
3422 because of load delays, and also to update the delay slot
3425 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3426 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3429 /* Control the assembler format that we output. */
3431 /* Output at beginning of assembler file.
3432 If we are optimizing to use the global pointer, create a temporary
3433 file to hold all of the text stuff, and write it out to the end.
3434 This is needed because the MIPS assembler is evidently one pass,
3435 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3436 declaration when the code is processed, it generates a two
3437 instruction sequence. */
3439 #undef ASM_FILE_START
3440 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3442 /* Output to assembler file text saying following lines
3443 may contain character constants, extra white space, comments, etc. */
3446 #define ASM_APP_ON " #APP\n"
3449 /* Output to assembler file text saying following lines
3450 no longer contain unusual constructs. */
3453 #define ASM_APP_OFF " #NO_APP\n"
3456 /* How to refer to registers in assembler output.
3457 This sequence is indexed by compiler's hard-register-number (see above).
3459 In order to support the two different conventions for register names,
3460 we use the name of a table set up in mips.c, which is overwritten
3461 if -mrnames is used. */
3463 #define REGISTER_NAMES \
3465 &mips_reg_names[ 0][0], \
3466 &mips_reg_names[ 1][0], \
3467 &mips_reg_names[ 2][0], \
3468 &mips_reg_names[ 3][0], \
3469 &mips_reg_names[ 4][0], \
3470 &mips_reg_names[ 5][0], \
3471 &mips_reg_names[ 6][0], \
3472 &mips_reg_names[ 7][0], \
3473 &mips_reg_names[ 8][0], \
3474 &mips_reg_names[ 9][0], \
3475 &mips_reg_names[10][0], \
3476 &mips_reg_names[11][0], \
3477 &mips_reg_names[12][0], \
3478 &mips_reg_names[13][0], \
3479 &mips_reg_names[14][0], \
3480 &mips_reg_names[15][0], \
3481 &mips_reg_names[16][0], \
3482 &mips_reg_names[17][0], \
3483 &mips_reg_names[18][0], \
3484 &mips_reg_names[19][0], \
3485 &mips_reg_names[20][0], \
3486 &mips_reg_names[21][0], \
3487 &mips_reg_names[22][0], \
3488 &mips_reg_names[23][0], \
3489 &mips_reg_names[24][0], \
3490 &mips_reg_names[25][0], \
3491 &mips_reg_names[26][0], \
3492 &mips_reg_names[27][0], \
3493 &mips_reg_names[28][0], \
3494 &mips_reg_names[29][0], \
3495 &mips_reg_names[30][0], \
3496 &mips_reg_names[31][0], \
3497 &mips_reg_names[32][0], \
3498 &mips_reg_names[33][0], \
3499 &mips_reg_names[34][0], \
3500 &mips_reg_names[35][0], \
3501 &mips_reg_names[36][0], \
3502 &mips_reg_names[37][0], \
3503 &mips_reg_names[38][0], \
3504 &mips_reg_names[39][0], \
3505 &mips_reg_names[40][0], \
3506 &mips_reg_names[41][0], \
3507 &mips_reg_names[42][0], \
3508 &mips_reg_names[43][0], \
3509 &mips_reg_names[44][0], \
3510 &mips_reg_names[45][0], \
3511 &mips_reg_names[46][0], \
3512 &mips_reg_names[47][0], \
3513 &mips_reg_names[48][0], \
3514 &mips_reg_names[49][0], \
3515 &mips_reg_names[50][0], \
3516 &mips_reg_names[51][0], \
3517 &mips_reg_names[52][0], \
3518 &mips_reg_names[53][0], \
3519 &mips_reg_names[54][0], \
3520 &mips_reg_names[55][0], \
3521 &mips_reg_names[56][0], \
3522 &mips_reg_names[57][0], \
3523 &mips_reg_names[58][0], \
3524 &mips_reg_names[59][0], \
3525 &mips_reg_names[60][0], \
3526 &mips_reg_names[61][0], \
3527 &mips_reg_names[62][0], \
3528 &mips_reg_names[63][0], \
3529 &mips_reg_names[64][0], \
3530 &mips_reg_names[65][0], \
3531 &mips_reg_names[66][0], \
3532 &mips_reg_names[67][0], \
3533 &mips_reg_names[68][0], \
3534 &mips_reg_names[69][0], \
3535 &mips_reg_names[70][0], \
3536 &mips_reg_names[71][0], \
3537 &mips_reg_names[72][0], \
3538 &mips_reg_names[73][0], \
3539 &mips_reg_names[74][0], \
3540 &mips_reg_names[75][0], \
3541 &mips_reg_names[76][0], \
3542 &mips_reg_names[77][0], \
3543 &mips_reg_names[78][0], \
3544 &mips_reg_names[79][0], \
3545 &mips_reg_names[80][0], \
3546 &mips_reg_names[81][0], \
3547 &mips_reg_names[82][0], \
3548 &mips_reg_names[83][0], \
3549 &mips_reg_names[84][0], \
3550 &mips_reg_names[85][0], \
3551 &mips_reg_names[86][0], \
3552 &mips_reg_names[87][0], \
3553 &mips_reg_names[88][0], \
3554 &mips_reg_names[89][0], \
3555 &mips_reg_names[90][0], \
3556 &mips_reg_names[91][0], \
3557 &mips_reg_names[92][0], \
3558 &mips_reg_names[93][0], \
3559 &mips_reg_names[94][0], \
3560 &mips_reg_names[95][0], \
3561 &mips_reg_names[96][0], \
3562 &mips_reg_names[97][0], \
3563 &mips_reg_names[98][0], \
3564 &mips_reg_names[99][0], \
3565 &mips_reg_names[100][0], \
3566 &mips_reg_names[101][0], \
3567 &mips_reg_names[102][0], \
3568 &mips_reg_names[103][0], \
3569 &mips_reg_names[104][0], \
3570 &mips_reg_names[105][0], \
3571 &mips_reg_names[106][0], \
3572 &mips_reg_names[107][0], \
3573 &mips_reg_names[108][0], \
3574 &mips_reg_names[109][0], \
3575 &mips_reg_names[110][0], \
3576 &mips_reg_names[111][0], \
3577 &mips_reg_names[112][0], \
3578 &mips_reg_names[113][0], \
3579 &mips_reg_names[114][0], \
3580 &mips_reg_names[115][0], \
3581 &mips_reg_names[116][0], \
3582 &mips_reg_names[117][0], \
3583 &mips_reg_names[118][0], \
3584 &mips_reg_names[119][0], \
3585 &mips_reg_names[120][0], \
3586 &mips_reg_names[121][0], \
3587 &mips_reg_names[122][0], \
3588 &mips_reg_names[123][0], \
3589 &mips_reg_names[124][0], \
3590 &mips_reg_names[125][0], \
3591 &mips_reg_names[126][0], \
3592 &mips_reg_names[127][0], \
3593 &mips_reg_names[128][0], \
3594 &mips_reg_names[129][0], \
3595 &mips_reg_names[130][0], \
3596 &mips_reg_names[131][0], \
3597 &mips_reg_names[132][0], \
3598 &mips_reg_names[133][0], \
3599 &mips_reg_names[134][0], \
3600 &mips_reg_names[135][0], \
3601 &mips_reg_names[136][0], \
3602 &mips_reg_names[137][0], \
3603 &mips_reg_names[138][0], \
3604 &mips_reg_names[139][0], \
3605 &mips_reg_names[140][0], \
3606 &mips_reg_names[141][0], \
3607 &mips_reg_names[142][0], \
3608 &mips_reg_names[143][0], \
3609 &mips_reg_names[144][0], \
3610 &mips_reg_names[145][0], \
3611 &mips_reg_names[146][0], \
3612 &mips_reg_names[147][0], \
3613 &mips_reg_names[148][0], \
3614 &mips_reg_names[149][0], \
3615 &mips_reg_names[150][0], \
3616 &mips_reg_names[151][0], \
3617 &mips_reg_names[152][0], \
3618 &mips_reg_names[153][0], \
3619 &mips_reg_names[154][0], \
3620 &mips_reg_names[155][0], \
3621 &mips_reg_names[156][0], \
3622 &mips_reg_names[157][0], \
3623 &mips_reg_names[158][0], \
3624 &mips_reg_names[159][0], \
3625 &mips_reg_names[160][0], \
3626 &mips_reg_names[161][0], \
3627 &mips_reg_names[162][0], \
3628 &mips_reg_names[163][0], \
3629 &mips_reg_names[164][0], \
3630 &mips_reg_names[165][0], \
3631 &mips_reg_names[166][0], \
3632 &mips_reg_names[167][0], \
3633 &mips_reg_names[168][0], \
3634 &mips_reg_names[169][0], \
3635 &mips_reg_names[170][0], \
3636 &mips_reg_names[171][0], \
3637 &mips_reg_names[172][0], \
3638 &mips_reg_names[173][0], \
3639 &mips_reg_names[174][0], \
3640 &mips_reg_names[175][0] \
3643 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3644 So define this for it. */
3645 #define DEBUG_REGISTER_NAMES \
3647 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3648 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3649 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3650 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3651 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3652 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3653 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3654 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3655 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3656 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3657 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3658 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3659 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3660 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3661 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3662 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3663 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3664 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3665 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3666 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3667 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3668 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3671 /* If defined, a C initializer for an array of structures
3672 containing a name and a register number. This macro defines
3673 additional names for hard registers, thus allowing the `asm'
3674 option in declarations to refer to registers using alternate
3677 We define both names for the integer registers here. */
3679 #define ADDITIONAL_REGISTER_NAMES \
3681 { "$0", 0 + GP_REG_FIRST }, \
3682 { "$1", 1 + GP_REG_FIRST }, \
3683 { "$2", 2 + GP_REG_FIRST }, \
3684 { "$3", 3 + GP_REG_FIRST }, \
3685 { "$4", 4 + GP_REG_FIRST }, \
3686 { "$5", 5 + GP_REG_FIRST }, \
3687 { "$6", 6 + GP_REG_FIRST }, \
3688 { "$7", 7 + GP_REG_FIRST }, \
3689 { "$8", 8 + GP_REG_FIRST }, \
3690 { "$9", 9 + GP_REG_FIRST }, \
3691 { "$10", 10 + GP_REG_FIRST }, \
3692 { "$11", 11 + GP_REG_FIRST }, \
3693 { "$12", 12 + GP_REG_FIRST }, \
3694 { "$13", 13 + GP_REG_FIRST }, \
3695 { "$14", 14 + GP_REG_FIRST }, \
3696 { "$15", 15 + GP_REG_FIRST }, \
3697 { "$16", 16 + GP_REG_FIRST }, \
3698 { "$17", 17 + GP_REG_FIRST }, \
3699 { "$18", 18 + GP_REG_FIRST }, \
3700 { "$19", 19 + GP_REG_FIRST }, \
3701 { "$20", 20 + GP_REG_FIRST }, \
3702 { "$21", 21 + GP_REG_FIRST }, \
3703 { "$22", 22 + GP_REG_FIRST }, \
3704 { "$23", 23 + GP_REG_FIRST }, \
3705 { "$24", 24 + GP_REG_FIRST }, \
3706 { "$25", 25 + GP_REG_FIRST }, \
3707 { "$26", 26 + GP_REG_FIRST }, \
3708 { "$27", 27 + GP_REG_FIRST }, \
3709 { "$28", 28 + GP_REG_FIRST }, \
3710 { "$29", 29 + GP_REG_FIRST }, \
3711 { "$30", 30 + GP_REG_FIRST }, \
3712 { "$31", 31 + GP_REG_FIRST }, \
3713 { "$sp", 29 + GP_REG_FIRST }, \
3714 { "$fp", 30 + GP_REG_FIRST }, \
3715 { "at", 1 + GP_REG_FIRST }, \
3716 { "v0", 2 + GP_REG_FIRST }, \
3717 { "v1", 3 + GP_REG_FIRST }, \
3718 { "a0", 4 + GP_REG_FIRST }, \
3719 { "a1", 5 + GP_REG_FIRST }, \
3720 { "a2", 6 + GP_REG_FIRST }, \
3721 { "a3", 7 + GP_REG_FIRST }, \
3722 { "t0", 8 + GP_REG_FIRST }, \
3723 { "t1", 9 + GP_REG_FIRST }, \
3724 { "t2", 10 + GP_REG_FIRST }, \
3725 { "t3", 11 + GP_REG_FIRST }, \
3726 { "t4", 12 + GP_REG_FIRST }, \
3727 { "t5", 13 + GP_REG_FIRST }, \
3728 { "t6", 14 + GP_REG_FIRST }, \
3729 { "t7", 15 + GP_REG_FIRST }, \
3730 { "s0", 16 + GP_REG_FIRST }, \
3731 { "s1", 17 + GP_REG_FIRST }, \
3732 { "s2", 18 + GP_REG_FIRST }, \
3733 { "s3", 19 + GP_REG_FIRST }, \
3734 { "s4", 20 + GP_REG_FIRST }, \
3735 { "s5", 21 + GP_REG_FIRST }, \
3736 { "s6", 22 + GP_REG_FIRST }, \
3737 { "s7", 23 + GP_REG_FIRST }, \
3738 { "t8", 24 + GP_REG_FIRST }, \
3739 { "t9", 25 + GP_REG_FIRST }, \
3740 { "k0", 26 + GP_REG_FIRST }, \
3741 { "k1", 27 + GP_REG_FIRST }, \
3742 { "gp", 28 + GP_REG_FIRST }, \
3743 { "sp", 29 + GP_REG_FIRST }, \
3744 { "fp", 30 + GP_REG_FIRST }, \
3745 { "ra", 31 + GP_REG_FIRST }, \
3746 { "$sp", 29 + GP_REG_FIRST }, \
3747 { "$fp", 30 + GP_REG_FIRST } \
3748 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3751 /* This is meant to be redefined in the host dependent files. It is a
3752 set of alternative names and regnums for mips coprocessors. */
3754 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3756 /* A C compound statement to output to stdio stream STREAM the
3757 assembler syntax for an instruction operand X. X is an RTL
3760 CODE is a value that can be used to specify one of several ways
3761 of printing the operand. It is used when identical operands
3762 must be printed differently depending on the context. CODE
3763 comes from the `%' specification that was used to request
3764 printing of the operand. If the specification was just `%DIGIT'
3765 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3766 is the ASCII code for LTR.
3768 If X is a register, this macro should print the register's name.
3769 The names can be found in an array `reg_names' whose type is
3770 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3772 When the machine description has a specification `%PUNCT' (a `%'
3773 followed by a punctuation character), this macro is called with
3774 a null pointer for X and the punctuation character for CODE.
3776 See mips.c for the MIPS specific codes. */
3778 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3780 /* A C expression which evaluates to true if CODE is a valid
3781 punctuation character for use in the `PRINT_OPERAND' macro. If
3782 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3783 punctuation characters (except for the standard one, `%') are
3784 used in this way. */
3786 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3788 /* A C compound statement to output to stdio stream STREAM the
3789 assembler syntax for an instruction operand that is a memory
3790 reference whose address is ADDR. ADDR is an RTL expression. */
3792 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3795 /* A C statement, to be executed after all slot-filler instructions
3796 have been output. If necessary, call `dbr_sequence_length' to
3797 determine the number of slots filled in a sequence (zero if not
3798 currently outputting a sequence), to decide how many no-ops to
3799 output, or whatever.
3801 Don't define this macro if it has nothing to do, but it is
3802 helpful in reading assembly output if the extent of the delay
3803 sequence is made explicit (e.g. with white space).
3805 Note that output routines for instructions with delay slots must
3806 be prepared to deal with not being output as part of a sequence
3807 (i.e. when the scheduling pass is not run, or when no slot
3808 fillers could be found.) The variable `final_sequence' is null
3809 when not processing a sequence, otherwise it contains the
3810 `sequence' rtx being output. */
3812 #define DBR_OUTPUT_SEQEND(STREAM) \
3815 if (set_nomacro > 0 && --set_nomacro == 0) \
3816 fputs ("\t.set\tmacro\n", STREAM); \
3818 if (set_noreorder > 0 && --set_noreorder == 0) \
3819 fputs ("\t.set\treorder\n", STREAM); \
3821 dslots_jump_filled++; \
3822 fputs ("\n", STREAM); \
3827 /* How to tell the debugger about changes of source files. Note, the
3828 mips ECOFF format cannot deal with changes of files inside of
3829 functions, which means the output of parser generators like bison
3830 is generally not debuggable without using the -l switch. Lose,
3831 lose, lose. Silicon graphics seems to want all .file's hardwired
3834 #ifndef SET_FILE_NUMBER
3835 #define SET_FILE_NUMBER() ++num_source_filenames
3838 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3839 mips_output_filename (STREAM, NAME)
3841 /* This is defined so that it can be overridden in iris6.h. */
3842 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3845 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3846 output_quoted_string (STREAM, NAME); \
3847 fputs ("\n", STREAM); \
3851 /* This is how to output a note the debugger telling it the line number
3852 to which the following sequence of instructions corresponds.
3853 Silicon graphics puts a label after each .loc. */
3855 #ifndef LABEL_AFTER_LOC
3856 #define LABEL_AFTER_LOC(STREAM)
3859 #ifndef ASM_OUTPUT_SOURCE_LINE
3860 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3861 mips_output_lineno (STREAM, LINE)
3864 /* The MIPS implementation uses some labels for its own purpose. The
3865 following lists what labels are created, and are all formed by the
3866 pattern $L[a-z].*. The machine independent portion of GCC creates
3867 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3869 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3870 $Lb[0-9]+ Begin blocks for MIPS debug support
3871 $Lc[0-9]+ Label for use in s<xx> operation.
3872 $Le[0-9]+ End blocks for MIPS debug support */
3874 /* A C statement (sans semicolon) to output to the stdio stream
3875 STREAM any text necessary for declaring the name NAME of an
3876 initialized variable which is being defined. This macro must
3877 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3878 The argument DECL is the `VAR_DECL' tree node representing the
3881 If this macro is not defined, then the variable name is defined
3882 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3884 #undef ASM_DECLARE_OBJECT_NAME
3885 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3888 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3892 /* Globalizing directive for a label. */
3893 #define GLOBAL_ASM_OP "\t.globl\t"
3895 /* This says how to define a global common symbol. */
3897 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3899 /* If the target wants uninitialized const declarations in \
3900 .rdata then don't put them in .comm */ \
3901 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3902 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3903 && (DECL_INITIAL (DECL) == 0 \
3904 || DECL_INITIAL (DECL) == error_mark_node)) \
3906 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3907 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3909 readonly_data_section (); \
3910 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3911 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3915 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3920 /* This says how to define a local common symbol (ie, not visible to
3923 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3924 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3927 /* This says how to output an external. It would be possible not to
3928 output anything and let undefined symbol become external. However
3929 the assembler uses length information on externals to allocate in
3930 data/sdata bss/sbss, thereby saving exec time. */
3932 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3933 mips_output_external(STREAM,DECL,NAME)
3935 /* This says what to print at the end of the assembly file */
3937 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
3940 /* Play switch file games if we're optimizing the global pointer. */
3943 #define TEXT_SECTION() \
3945 extern FILE *asm_out_text_file; \
3946 if (TARGET_FILE_SWITCHING) \
3947 asm_out_file = asm_out_text_file; \
3948 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
3949 fputc ('\n', asm_out_file); \
3953 /* This is how to declare a function name. The actual work of
3954 emitting the label is moved to function_prologue, so that we can
3955 get the line number correctly emitted before the .ent directive,
3956 and after any .file directives. Define as empty so that the function
3957 is not declared before the .ent directive elsewhere. */
3959 #undef ASM_DECLARE_FUNCTION_NAME
3960 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3962 /* This is how to store into the string LABEL
3963 the symbol_ref name of an internal numbered label where
3964 PREFIX is the class of label and NUM is the number within the class.
3965 This is suitable for output with `assemble_name'. */
3967 #undef ASM_GENERATE_INTERNAL_LABEL
3968 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3969 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3971 /* This is how to output an element of a case-vector that is absolute. */
3973 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3974 fprintf (STREAM, "\t%s\t%sL%d\n", \
3975 ptr_mode == DImode ? ".dword" : ".word", \
3976 LOCAL_LABEL_PREFIX, \
3979 /* This is how to output an element of a case-vector that is relative.
3980 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3981 TARGET_EMBEDDED_PIC). */
3983 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3985 if (TARGET_MIPS16) \
3986 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3987 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3988 else if (TARGET_EMBEDDED_PIC) \
3989 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3990 ptr_mode == DImode ? ".dword" : ".word", \
3991 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3992 else if (TARGET_GPWORD) \
3993 fprintf (STREAM, "\t%s\t%sL%d\n", \
3994 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3995 LOCAL_LABEL_PREFIX, VALUE); \
3997 fprintf (STREAM, "\t%s\t%sL%d\n", \
3998 ptr_mode == DImode ? ".dword" : ".word", \
3999 LOCAL_LABEL_PREFIX, VALUE); \
4002 /* When generating embedded PIC or mips16 code we want to put the jump
4003 table in the .text section. In all other cases, we want to put the
4004 jump table in the .rdata section. Unfortunately, we can't use
4005 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4006 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4007 section if appropriate. */
4008 #undef ASM_OUTPUT_CASE_LABEL
4009 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4011 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4012 function_section (current_function_decl); \
4013 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
4016 /* This is how to output an assembler line
4017 that says to advance the location counter
4018 to a multiple of 2**LOG bytes. */
4020 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4021 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4023 /* This is how to output an assembler line to advance the location
4024 counter by SIZE bytes. */
4026 #undef ASM_OUTPUT_SKIP
4027 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4028 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
4030 /* This is how to output a string. */
4031 #undef ASM_OUTPUT_ASCII
4032 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4033 mips_output_ascii (STREAM, STRING, LEN)
4035 /* Output #ident as a in the read-only data section. */
4036 #undef ASM_OUTPUT_IDENT
4037 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4039 const char *p = STRING; \
4040 int size = strlen (p) + 1; \
4041 readonly_data_section (); \
4042 assemble_string (p, size); \
4045 /* Default to -G 8 */
4046 #ifndef MIPS_DEFAULT_GVALUE
4047 #define MIPS_DEFAULT_GVALUE 8
4050 /* Define the strings to put out for each section in the object file. */
4051 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4052 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4053 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4055 #undef READONLY_DATA_SECTION_ASM_OP
4056 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4058 #define SMALL_DATA_SECTION sdata_section
4060 /* What other sections we support other than the normal .data/.text. */
4062 #undef EXTRA_SECTIONS
4063 #define EXTRA_SECTIONS in_sdata
4065 /* Define the additional functions to select our additional sections. */
4067 /* on the MIPS it is not a good idea to put constants in the text
4068 section, since this defeats the sdata/data mechanism. This is
4069 especially true when -O is used. In this case an effort is made to
4070 address with faster (gp) register relative addressing, which can
4071 only get at sdata and sbss items (there is no stext !!) However,
4072 if the constant is too large for sdata, and it's readonly, it
4073 will go into the .rdata section. */
4075 #undef EXTRA_SECTION_FUNCTIONS
4076 #define EXTRA_SECTION_FUNCTIONS \
4080 if (in_section != in_sdata) \
4082 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4083 in_section = in_sdata; \
4087 /* Given a decl node or constant node, choose the section to output it in
4088 and select that section. */
4090 #undef TARGET_ASM_SELECT_SECTION
4091 #define TARGET_ASM_SELECT_SECTION mips_select_section
4093 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4096 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4097 TARGET_64BIT ? "dsubu" : "subu", \
4098 reg_names[STACK_POINTER_REGNUM], \
4099 reg_names[STACK_POINTER_REGNUM], \
4100 TARGET_64BIT ? "sd" : "sw", \
4102 reg_names[STACK_POINTER_REGNUM]); \
4106 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4109 if (! set_noreorder) \
4110 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4112 dslots_load_total++; \
4113 dslots_load_filled++; \
4114 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4115 TARGET_64BIT ? "ld" : "lw", \
4117 reg_names[STACK_POINTER_REGNUM], \
4118 TARGET_64BIT ? "daddu" : "addu", \
4119 reg_names[STACK_POINTER_REGNUM], \
4120 reg_names[STACK_POINTER_REGNUM]); \
4122 if (! set_noreorder) \
4123 fprintf (STREAM, "\t.set\treorder\n"); \
4127 /* How to start an assembler comment.
4128 The leading space is important (the mips native assembler requires it). */
4129 #ifndef ASM_COMMENT_START
4130 #define ASM_COMMENT_START " #"
4134 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4135 and mips-tdump.c to print them out.
4137 These must match the corresponding definitions in gdb/mipsread.c.
4138 Unfortunately, gcc and gdb do not currently share any directories. */
4140 #define CODE_MASK 0x8F300
4141 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4142 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4143 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4146 /* Default definitions for size_t and ptrdiff_t. We must override the
4147 definitions from ../svr4.h on mips-*-linux-gnu. */
4150 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
4153 #ifndef PTRDIFF_TYPE
4154 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
4157 /* See mips_expand_prologue's use of loadgp for when this should be
4160 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4161 && mips_abi != ABI_32 \
4162 && mips_abi != ABI_O64)
4164 /* In mips16 mode, we need to look through the function to check for
4165 PC relative loads that are out of range. */
4166 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4168 /* We need to use a special set of functions to handle hard floating
4169 point code in mips16 mode. */
4171 #ifndef INIT_SUBTARGET_OPTABS
4172 #define INIT_SUBTARGET_OPTABS
4175 #define INIT_TARGET_OPTABS \
4178 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4179 INIT_SUBTARGET_OPTABS; \
4182 add_optab->handlers[(int) SFmode].libfunc = \
4183 init_one_libfunc ("__mips16_addsf3"); \
4184 sub_optab->handlers[(int) SFmode].libfunc = \
4185 init_one_libfunc ("__mips16_subsf3"); \
4186 smul_optab->handlers[(int) SFmode].libfunc = \
4187 init_one_libfunc ("__mips16_mulsf3"); \
4188 sdiv_optab->handlers[(int) SFmode].libfunc = \
4189 init_one_libfunc ("__mips16_divsf3"); \
4191 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4192 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4193 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4194 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4195 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4196 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4198 floatsisf_libfunc = \
4199 init_one_libfunc ("__mips16_floatsisf"); \
4201 init_one_libfunc ("__mips16_fixsfsi"); \
4203 if (TARGET_DOUBLE_FLOAT) \
4205 add_optab->handlers[(int) DFmode].libfunc = \
4206 init_one_libfunc ("__mips16_adddf3"); \
4207 sub_optab->handlers[(int) DFmode].libfunc = \
4208 init_one_libfunc ("__mips16_subdf3"); \
4209 smul_optab->handlers[(int) DFmode].libfunc = \
4210 init_one_libfunc ("__mips16_muldf3"); \
4211 sdiv_optab->handlers[(int) DFmode].libfunc = \
4212 init_one_libfunc ("__mips16_divdf3"); \
4214 extendsfdf2_libfunc = \
4215 init_one_libfunc ("__mips16_extendsfdf2"); \
4216 truncdfsf2_libfunc = \
4217 init_one_libfunc ("__mips16_truncdfsf2"); \
4220 init_one_libfunc ("__mips16_eqdf2"); \
4222 init_one_libfunc ("__mips16_nedf2"); \
4224 init_one_libfunc ("__mips16_gtdf2"); \
4226 init_one_libfunc ("__mips16_gedf2"); \
4228 init_one_libfunc ("__mips16_ltdf2"); \
4230 init_one_libfunc ("__mips16_ledf2"); \
4232 floatsidf_libfunc = \
4233 init_one_libfunc ("__mips16_floatsidf"); \
4235 init_one_libfunc ("__mips16_fixdfsi"); \
4241 #define DFMODE_NAN \
4242 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4243 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4244 #define SFMODE_NAN \
4245 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4246 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4248 /* Generate calls to memcpy, etc., not bcopy, etc. */
4249 #define TARGET_MEM_FUNCTIONS
4252 /* Since the bits of the _init and _fini function is spread across
4253 many object files, each potentially with its own GP, we must assume
4254 we need to load our GP. We don't preserve $gp or $ra, since each
4255 init/fini chunk is supposed to initialize $gp, and crti/crtn
4256 already take care of preserving $ra and, when appropriate, $gp. */
4257 #if _MIPS_SIM == _MIPS_SIM_ABI32
4258 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4259 asm (SECTION_OP "\n\
4265 jal " USER_LABEL_PREFIX #FUNC "\n\
4266 " TEXT_SECTION_ASM_OP);
4267 #endif /* Switch to #elif when we're no longer limited by K&R C. */
4268 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4269 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4270 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4271 asm (SECTION_OP "\n\
4276 .cpsetup $31, $2, 1b\n\
4277 jal " USER_LABEL_PREFIX #FUNC "\n\
4278 " TEXT_SECTION_ASM_OP);