1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char call_used_regs[];
30 extern int may_call_alloca;
31 extern int target_flags;
33 /* MIPS external variables defined in mips.c. */
37 CMP_SI, /* compare four byte integers */
38 CMP_DI, /* compare eight byte integers */
39 CMP_SF, /* compare single precision floats */
40 CMP_DF, /* compare double precision floats */
41 CMP_MAX /* max comparison type */
44 /* Which processor to schedule for. Since there is no difference between
45 a R2000 and R3000 in terms of the scheduler, we collapse them into
46 just an R3000. The elements of the enumeration must match exactly
47 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
76 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
77 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
78 to work on a 64 bit machine. */
86 /* Whether to emit abicalls code sequences or not. */
88 enum mips_abicalls_type {
93 /* Recast the abicalls class to be the abicalls attribute. */
94 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
96 /* Information about one recognized processor. Defined here for the
97 benefit of TARGET_CPU_CPP_BUILTINS. */
98 struct mips_cpu_info {
99 /* The 'canonical' name of the processor as far as GCC is concerned.
100 It's typically a manufacturer's prefix followed by a numerical
101 designation. It should be lower case. */
104 /* The internal processor number that most closely matches this
105 entry. Several processors can have the same value, if there's no
106 difference between them from GCC's point of view. */
107 enum processor_type cpu;
109 /* The ISA level that the processor implements. */
113 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
114 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
115 extern const char *current_function_file; /* filename current function is in */
116 extern int num_source_filenames; /* current .file # */
117 extern int inside_function; /* != 0 if inside of a function */
118 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
119 extern int file_in_function_warning; /* warning given about .file in func */
120 extern int sdb_label_count; /* block start/end next label # */
121 extern int sdb_begin_function_line; /* Starting Line of current function */
122 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
123 extern int sym_lineno; /* sgi next label # for each stmt */
124 extern int set_noreorder; /* # of nested .set noreorder's */
125 extern int set_nomacro; /* # of nested .set nomacro's */
126 extern int set_noat; /* # of nested .set noat's */
127 extern int set_volatile; /* # of nested .set volatile's */
128 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
129 extern int mips_dbx_regno[]; /* Map register # to debug register # */
130 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
131 extern enum cmp_type branch_type; /* what type of branch to use */
132 extern enum processor_type mips_arch; /* which cpu to codegen for */
133 extern enum processor_type mips_tune; /* which cpu to schedule for */
134 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
135 extern int mips_isa; /* architectural level */
136 extern int mips16; /* whether generating mips16 code */
137 extern int mips16_hard_float; /* mips16 without -msoft-float */
138 extern int mips_entry; /* generate entry/exit for mips16 */
139 extern const char *mips_arch_string; /* for -march=<xxx> */
140 extern const char *mips_tune_string; /* for -mtune=<xxx> */
141 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
142 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
143 extern const char *mips_entry_string; /* for -mentry */
144 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
145 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
146 extern int mips_string_length; /* length of strings for mips16 */
147 extern const struct mips_cpu_info mips_cpu_info_table[];
148 extern const struct mips_cpu_info *mips_arch_info;
149 extern const struct mips_cpu_info *mips_tune_info;
151 /* Macros to silence warnings about numbers being signed in traditional
152 C and unsigned in ISO C when compiled on 32-bit hosts. */
154 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
155 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
156 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
159 /* Run-time compilation parameters selecting different hardware subsets. */
161 /* Macros used in the machine description to test the flags. */
163 /* Bits for real switches */
164 #define MASK_INT64 0x00000001 /* ints are 64 bits */
165 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
166 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
167 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
168 multiply-add operations. */
169 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
170 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
171 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
172 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
173 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
174 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
175 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
176 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
177 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
178 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
179 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
180 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
181 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
182 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
183 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
184 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
185 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
186 #define MASK_NO_CHECK_ZERO_DIV \
187 0x00200000 /* divide by zero checking */
188 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
190 #define MASK_UNINIT_CONST_IN_RODATA \
191 0x00800000 /* Store uninitialized
194 /* Debug switches, not documented */
195 #define MASK_DEBUG 0 /* unused */
196 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
197 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
198 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
199 #define MASK_DEBUG_D 0 /* don't do define_split's */
200 #define MASK_DEBUG_E 0 /* function_arg debug */
201 #define MASK_DEBUG_F 0 /* ??? */
202 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
203 #define MASK_DEBUG_I 0 /* unused */
205 /* Dummy switches used only in specs */
206 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
208 /* r4000 64 bit sizes */
209 #define TARGET_INT64 (target_flags & MASK_INT64)
210 #define TARGET_LONG64 (target_flags & MASK_LONG64)
211 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
212 #define TARGET_64BIT (target_flags & MASK_64BIT)
214 /* Mips vs. GNU linker */
215 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
217 /* Mips vs. GNU assembler */
218 #define TARGET_GAS (target_flags & MASK_GAS)
219 #define TARGET_MIPS_AS (!TARGET_GAS)
222 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
223 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
224 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
225 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
226 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
227 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
228 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
229 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
230 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
232 /* Reg. Naming in .s ($21 vs. $a0) */
233 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
235 /* call memcpy instead of inline code */
236 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
238 /* .abicalls, etc from Pyramid V.4 */
239 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
241 /* software floating point */
242 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
243 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
245 /* always call through a register */
246 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
248 /* generate embedded PIC code;
250 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
252 /* for embedded systems, optimize for
253 reduced RAM space instead of for
255 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
257 /* always store uninitialized const
258 variables in rodata, requires
259 TARGET_EMBEDDED_DATA. */
260 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
262 /* generate big endian code. */
263 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
265 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
266 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
268 #define TARGET_MAD (target_flags & MASK_MAD)
270 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
272 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
274 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
276 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
279 /* True if we should use NewABI-style relocation operators for
280 symbolic addresses. This is never true for mips16 code,
281 which has its own conventions. */
283 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
286 /* True if the call patterns should be split into a jalr followed by
287 an instruction to restore $gp. This is only ever true for SVR4 PIC,
288 in which $gp is call-clobbered. It is only safe to split the load
289 from the call when every use of $gp is explicit. */
291 #define TARGET_SPLIT_CALLS \
292 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
294 /* True if we can optimize sibling calls. For simplicity, we only
295 handle cases in which call_insn_operand will reject invalid
296 sibcall addresses. There are two cases in which this isn't true:
298 - TARGET_MIPS16. call_insn_operand accepts constant addresses
299 but there is no direct jump instruction. It isn't worth
300 using sibling calls in this case anyway; they would usually
301 be longer than normal calls.
303 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
304 accepts global constants, but "jr $25" is the only allowed
307 #define TARGET_SIBCALLS \
308 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
310 /* True if .gpword or .gpdword should be used for switch tables.
311 Not all SGI assemblers support this. */
313 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
315 /* Generate mips16 code */
316 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
318 /* Generic ISA defines. */
319 #define ISA_MIPS1 (mips_isa == 1)
320 #define ISA_MIPS2 (mips_isa == 2)
321 #define ISA_MIPS3 (mips_isa == 3)
322 #define ISA_MIPS4 (mips_isa == 4)
323 #define ISA_MIPS32 (mips_isa == 32)
324 #define ISA_MIPS32R2 (mips_isa == 33)
325 #define ISA_MIPS64 (mips_isa == 64)
327 /* Architecture target defines. */
328 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
329 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
330 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
331 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
332 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
333 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
334 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
335 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
336 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
337 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
338 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
340 /* Scheduling target defines. */
341 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
342 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
343 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
344 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
345 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
346 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
347 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
348 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
349 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
351 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
353 /* Define preprocessor macros for the -march and -mtune options.
354 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
355 processor. If INFO's canonical name is "foo", define PREFIX to
356 be "foo", and define an additional macro PREFIX_FOO. */
357 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
362 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
363 for (p = macro; *p != 0; p++) \
366 builtin_define (macro); \
367 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
372 /* Target CPU builtins. */
373 #define TARGET_CPU_CPP_BUILTINS() \
376 builtin_assert ("cpu=mips"); \
377 builtin_define ("__mips__"); \
378 builtin_define ("_mips"); \
380 /* We do this here because __mips is defined below \
381 and so we can't use builtin_define_std. */ \
383 builtin_define ("mips"); \
385 /* Treat _R3000 and _R4000 like register-size defines, \
386 which is how they've historically been used. */ \
389 builtin_define ("__mips64"); \
390 builtin_define_std ("R4000"); \
391 builtin_define ("_R4000"); \
395 builtin_define_std ("R3000"); \
396 builtin_define ("_R3000"); \
398 if (TARGET_FLOAT64) \
399 builtin_define ("__mips_fpr=64"); \
401 builtin_define ("__mips_fpr=32"); \
404 builtin_define ("__mips16"); \
406 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
407 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
411 builtin_define ("__mips=1"); \
412 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
414 else if (ISA_MIPS2) \
416 builtin_define ("__mips=2"); \
417 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
419 else if (ISA_MIPS3) \
421 builtin_define ("__mips=3"); \
422 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
424 else if (ISA_MIPS4) \
426 builtin_define ("__mips=4"); \
427 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
429 else if (ISA_MIPS32) \
431 builtin_define ("__mips=32"); \
432 builtin_define ("__mips_isa_rev=1"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
435 else if (ISA_MIPS32R2) \
437 builtin_define ("__mips=32"); \
438 builtin_define ("__mips_isa_rev=2"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
441 else if (ISA_MIPS64) \
443 builtin_define ("__mips=64"); \
444 builtin_define ("__mips_isa_rev=1"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
448 if (TARGET_HARD_FLOAT) \
449 builtin_define ("__mips_hard_float"); \
450 else if (TARGET_SOFT_FLOAT) \
451 builtin_define ("__mips_soft_float"); \
453 if (TARGET_SINGLE_FLOAT) \
454 builtin_define ("__mips_single_float"); \
456 if (TARGET_BIG_ENDIAN) \
458 builtin_define_std ("MIPSEB"); \
459 builtin_define ("_MIPSEB"); \
463 builtin_define_std ("MIPSEL"); \
464 builtin_define ("_MIPSEL"); \
467 /* Macros dependent on the C dialect. */ \
468 if (preprocessing_asm_p ()) \
470 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
471 builtin_define ("_LANGUAGE_ASSEMBLY"); \
473 else if (c_dialect_cxx ()) \
475 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
476 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
477 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
481 builtin_define_std ("LANGUAGE_C"); \
482 builtin_define ("_LANGUAGE_C"); \
484 if (c_dialect_objc ()) \
486 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
487 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
488 /* Bizzare, but needed at least for Irix. */ \
489 builtin_define_std ("LANGUAGE_C"); \
490 builtin_define ("_LANGUAGE_C"); \
493 if (mips_abi == ABI_EABI) \
494 builtin_define ("__mips_eabi"); \
500 /* Macro to define tables used to set the flags.
501 This is a list in braces of pairs in braces,
502 each pair being { "NAME", VALUE }
503 where VALUE is the bits to set or minus the bits to clear.
504 An empty string NAME is used to identify the default VALUE. */
506 #define TARGET_SWITCHES \
508 SUBTARGET_TARGET_SWITCHES \
509 {"int64", MASK_INT64 | MASK_LONG64, \
510 N_("Use 64-bit int type")}, \
511 {"long64", MASK_LONG64, \
512 N_("Use 64-bit long type")}, \
513 {"long32", -(MASK_LONG64 | MASK_INT64), \
514 N_("Use 32-bit long type")}, \
515 {"split-addresses", MASK_SPLIT_ADDR, \
516 N_("Optimize lui/addiu address loads")}, \
517 {"no-split-addresses", -MASK_SPLIT_ADDR, \
518 N_("Don't optimize lui/addiu address loads")}, \
519 {"mips-as", -MASK_GAS, \
520 N_("Use MIPS as")}, \
523 {"rnames", MASK_NAME_REGS, \
524 N_("Use symbolic register names")}, \
525 {"no-rnames", -MASK_NAME_REGS, \
526 N_("Don't use symbolic register names")}, \
528 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
530 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
532 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
534 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
536 N_("Output compiler statistics (now ignored)")}, \
538 N_("Don't output compiler statistics")}, \
539 {"memcpy", MASK_MEMCPY, \
540 N_("Don't optimize block moves")}, \
541 {"no-memcpy", -MASK_MEMCPY, \
542 N_("Optimize block moves")}, \
543 {"mips-tfile", MASK_MIPS_TFILE, \
544 N_("Use mips-tfile asm postpass")}, \
545 {"no-mips-tfile", -MASK_MIPS_TFILE, \
546 N_("Don't use mips-tfile asm postpass")}, \
547 {"soft-float", MASK_SOFT_FLOAT, \
548 N_("Use software floating point")}, \
549 {"hard-float", -MASK_SOFT_FLOAT, \
550 N_("Use hardware floating point")}, \
551 {"fp64", MASK_FLOAT64, \
552 N_("Use 64-bit FP registers")}, \
553 {"fp32", -MASK_FLOAT64, \
554 N_("Use 32-bit FP registers")}, \
555 {"gp64", MASK_64BIT, \
556 N_("Use 64-bit general registers")}, \
557 {"gp32", -MASK_64BIT, \
558 N_("Use 32-bit general registers")}, \
559 {"abicalls", MASK_ABICALLS, \
560 N_("Use Irix PIC")}, \
561 {"no-abicalls", -MASK_ABICALLS, \
562 N_("Don't use Irix PIC")}, \
563 {"long-calls", MASK_LONG_CALLS, \
564 N_("Use indirect calls")}, \
565 {"no-long-calls", -MASK_LONG_CALLS, \
566 N_("Don't use indirect calls")}, \
567 {"embedded-pic", MASK_EMBEDDED_PIC, \
568 N_("Use embedded PIC")}, \
569 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
570 N_("Don't use embedded PIC")}, \
571 {"embedded-data", MASK_EMBEDDED_DATA, \
572 N_("Use ROM instead of RAM")}, \
573 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
574 N_("Don't use ROM instead of RAM")}, \
575 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
576 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
577 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
578 N_("Don't put uninitialized constants in ROM")}, \
579 {"eb", MASK_BIG_ENDIAN, \
580 N_("Use big-endian byte order")}, \
581 {"el", -MASK_BIG_ENDIAN, \
582 N_("Use little-endian byte order")}, \
583 {"single-float", MASK_SINGLE_FLOAT, \
584 N_("Use single (32-bit) FP only")}, \
585 {"double-float", -MASK_SINGLE_FLOAT, \
586 N_("Don't use single (32-bit) FP only")}, \
588 N_("Use multiply accumulate")}, \
589 {"no-mad", -MASK_MAD, \
590 N_("Don't use multiply accumulate")}, \
591 {"no-fused-madd", MASK_NO_FUSED_MADD, \
592 N_("Don't generate fused multiply/add instructions")}, \
593 {"fused-madd", -MASK_NO_FUSED_MADD, \
594 N_("Generate fused multiply/add instructions")}, \
595 {"fix4300", MASK_4300_MUL_FIX, \
596 N_("Work around early 4300 hardware bug")}, \
597 {"no-fix4300", -MASK_4300_MUL_FIX, \
598 N_("Don't work around early 4300 hardware bug")}, \
599 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
600 N_("Trap on integer divide by zero")}, \
601 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
602 N_("Don't trap on integer divide by zero")}, \
603 { "branch-likely", MASK_BRANCHLIKELY, \
604 N_("Use Branch Likely instructions, overriding default for arch")}, \
605 { "no-branch-likely", -MASK_BRANCHLIKELY, \
606 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
607 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
608 N_("Use NewABI-style %reloc() assembly operators")}, \
609 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
610 N_("Use assembler macros instead of relocation operators")}, \
611 {"debug", MASK_DEBUG, \
613 {"debuga", MASK_DEBUG_A, \
615 {"debugb", MASK_DEBUG_B, \
617 {"debugc", MASK_DEBUG_C, \
619 {"debugd", MASK_DEBUG_D, \
621 {"debuge", MASK_DEBUG_E, \
623 {"debugf", MASK_DEBUG_F, \
625 {"debugg", MASK_DEBUG_G, \
627 {"debugi", MASK_DEBUG_I, \
629 {"", (TARGET_DEFAULT \
630 | TARGET_CPU_DEFAULT \
631 | TARGET_ENDIAN_DEFAULT), \
635 /* Default target_flags if no switches are specified */
637 #ifndef TARGET_DEFAULT
638 #define TARGET_DEFAULT 0
641 #ifndef TARGET_CPU_DEFAULT
642 #define TARGET_CPU_DEFAULT 0
645 #ifndef TARGET_ENDIAN_DEFAULT
646 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
649 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
650 #ifndef MIPS_ISA_DEFAULT
651 #ifndef MIPS_CPU_STRING_DEFAULT
652 #define MIPS_CPU_STRING_DEFAULT "from-abi"
658 /* Make this compile time constant for libgcc2 */
660 #define TARGET_64BIT 1
662 #define TARGET_64BIT 0
664 #endif /* IN_LIBGCC2 */
666 #ifndef MULTILIB_ENDIAN_DEFAULT
667 #if TARGET_ENDIAN_DEFAULT == 0
668 #define MULTILIB_ENDIAN_DEFAULT "EL"
670 #define MULTILIB_ENDIAN_DEFAULT "EB"
674 #ifndef MULTILIB_ISA_DEFAULT
675 # if MIPS_ISA_DEFAULT == 1
676 # define MULTILIB_ISA_DEFAULT "mips1"
678 # if MIPS_ISA_DEFAULT == 2
679 # define MULTILIB_ISA_DEFAULT "mips2"
681 # if MIPS_ISA_DEFAULT == 3
682 # define MULTILIB_ISA_DEFAULT "mips3"
684 # if MIPS_ISA_DEFAULT == 4
685 # define MULTILIB_ISA_DEFAULT "mips4"
687 # if MIPS_ISA_DEFAULT == 32
688 # define MULTILIB_ISA_DEFAULT "mips32"
690 # if MIPS_ISA_DEFAULT == 33
691 # define MULTILIB_ISA_DEFAULT "mips32r2"
693 # if MIPS_ISA_DEFAULT == 64
694 # define MULTILIB_ISA_DEFAULT "mips64"
696 # define MULTILIB_ISA_DEFAULT "mips1"
706 #ifndef MULTILIB_DEFAULTS
707 #define MULTILIB_DEFAULTS \
708 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
711 /* We must pass -EL to the linker by default for little endian embedded
712 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
713 linker will default to using big-endian output files. The OUTPUT_FORMAT
714 line must be in the linker script, otherwise -EB/-EL will not work. */
717 #if TARGET_ENDIAN_DEFAULT == 0
718 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
720 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
724 #define TARGET_OPTIONS \
726 SUBTARGET_TARGET_OPTIONS \
727 { "tune=", &mips_tune_string, \
728 N_("Specify CPU for scheduling purposes"), 0}, \
729 { "arch=", &mips_arch_string, \
730 N_("Specify CPU for code generation purposes"), 0}, \
731 { "abi=", &mips_abi_string, \
732 N_("Specify an ABI"), 0}, \
733 { "ips", &mips_isa_string, \
734 N_("Specify a Standard MIPS ISA"), 0}, \
735 { "entry", &mips_entry_string, \
736 N_("Use mips16 entry/exit psuedo ops"), 0}, \
737 { "no-mips16", &mips_no_mips16_string, \
738 N_("Don't use MIPS16 instructions"), 0}, \
739 { "no-flush-func", &mips_cache_flush_func, \
740 N_("Don't call any cache flush functions"), 0}, \
741 { "flush-func=", &mips_cache_flush_func, \
742 N_("Specify cache flush function"), 0}, \
745 /* This is meant to be redefined in the host dependent files. */
746 #define SUBTARGET_TARGET_OPTIONS
748 /* Support for a compile-time default CPU, et cetera. The rules are:
749 --with-arch is ignored if -march is specified or a -mips is specified
750 (other than -mips16).
751 --with-tune is ignored if -mtune is specified.
752 --with-abi is ignored if -mabi is specified.
753 --with-float is ignored if -mhard-float or -msoft-float are
755 #define OPTION_DEFAULT_SPECS \
756 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
757 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
758 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
759 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
762 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
766 /* Generate three-operand multiply instructions for SImode. */
767 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
775 /* Generate three-operand multiply instructions for DImode. */
776 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
779 /* Macros to decide whether certain features are available or not,
780 depending on the instruction set architecture level. */
782 #define HAVE_SQRT_P() (!ISA_MIPS1)
784 /* True if the ABI can only work with 64-bit integer registers. We
785 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
786 otherwise floating-point registers must also be 64-bit. */
787 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
788 || mips_abi == ABI_O64 \
789 || mips_abi == ABI_N32)
791 /* Likewise for 32-bit regs. */
792 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
794 /* True if symbols are 64 bits wide. At present, n64 is the only
795 ABI for which this is true. */
796 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
798 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
799 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
803 /* ISA has branch likely instructions (eg. mips2). */
804 /* Disable branchlikely for tx39 until compare rewrite. They haven't
805 been generated up to this point. */
806 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
809 /* ISA has the conditional move instructions introduced in mips4. */
810 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
814 && !TARGET_MIPS5500 \
817 /* ISA has just the integer condition move instructions (movn,movz) */
818 #define ISA_HAS_INT_CONDMOVE 0
820 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
821 branch on CC, and move (both FP and non-FP) on CC. */
822 #define ISA_HAS_8CC (ISA_MIPS4 \
827 /* This is a catch all for the other new mips4 instructions: indexed load and
828 indexed prefetch instructions, the FP madd and msub instructions,
829 and the FP recip and recip sqrt instructions */
830 #define ISA_HAS_FP4 ((ISA_MIPS4 \
834 /* ISA has conditional trap instructions. */
835 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
838 /* ISA has integer multiply-accumulate instructions, madd and msub. */
839 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
844 /* ISA has floating-point nmadd and nmsub instructions. */
845 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
847 && (!TARGET_MIPS5400 || TARGET_MAD) \
850 /* ISA has count leading zeroes/ones instruction (not implemented). */
851 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
856 /* ISA has double-word count leading zeroes/ones instruction (not
858 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
861 /* ISA has three operand multiply instructions that put
862 the high part in an accumulator: mulhi or mulhiu. */
863 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
868 /* ISA has three operand multiply instructions that
869 negates the result and puts the result in an accumulator. */
870 #define ISA_HAS_MULS (TARGET_MIPS5400 \
875 /* ISA has three operand multiply instructions that subtracts the
876 result from a 4th operand and puts the result in an accumulator. */
877 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
881 /* ISA has three operand multiply instructions that the result
882 from a 4th operand and puts the result in an accumulator. */
883 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
889 /* ISA has 32-bit rotate right instruction. */
890 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
897 /* ISA has 64-bit rotate right instruction. */
898 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
900 && (TARGET_MIPS5400 \
905 /* ISA has data prefetch instruction. */
906 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
912 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
913 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
914 also requires TARGET_DOUBLE_FLOAT. */
915 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
917 /* ISA includes the MIPS32r2 seb and seh instructions. */
918 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
922 /* True if the result of a load is not available to the next instruction.
923 A nop will then be needed between instructions like "lw $4,..."
924 and "addiu $4,$4,1". */
925 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
926 && !TARGET_MIPS3900 \
929 /* Likewise mtc1 and mfc1. */
930 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
932 /* Likewise floating-point comparisons. */
933 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
935 /* True if mflo and mfhi can be immediately followed by instructions
936 which write to the HI and LO registers. Most targets require a
937 two-instruction gap. */
938 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
940 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
941 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
942 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
943 target_flags, and -mgp64 sets MASK_64BIT.
945 Setting MASK_64BIT in target_flags will cause gcc to assume that
946 registers are 64 bits wide. int, long and void * will be 32 bit;
947 this may be changed with -mint64 or -mlong64.
949 The gen* programs link code that refers to MASK_64BIT. They don't
950 actually use the information in target_flags; they just refer to
953 /* Switch Recognition by gcc.c. Add -G xx support */
955 #undef SWITCH_TAKES_ARG
956 #define SWITCH_TAKES_ARG(CHAR) \
957 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
959 /* Sometimes certain combinations of command options do not make sense
960 on a particular target machine. You can define a macro
961 `OVERRIDE_OPTIONS' to take account of this. This macro, if
962 defined, is executed once just after all the command options have
965 On the MIPS, it is used to handle -G. We also use it to set up all
966 of the tables referenced in the other macros. */
968 #define OVERRIDE_OPTIONS override_options ()
970 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
972 /* Show we can debug even without a frame pointer. */
973 #define CAN_DEBUG_WITHOUT_FP
975 /* Tell collect what flags to pass to nm. */
977 #define NM_FLAGS "-Bn"
981 /* Assembler specs. */
983 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
986 #define MIPS_AS_ASM_SPEC "\
987 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
988 %{pipe: %e-pipe is not supported} \
989 %{K} %(subtarget_mips_as_asm_spec)"
991 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
992 rather than gas. It may be overridden by subtargets. */
994 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
995 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
998 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1001 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1003 #define SUBTARGET_TARGET_SWITCHES
1005 extern int mips_abi;
1007 #ifndef MIPS_ABI_DEFAULT
1008 #define MIPS_ABI_DEFAULT ABI_32
1011 /* Use the most portable ABI flag for the ASM specs. */
1013 #if MIPS_ABI_DEFAULT == ABI_32
1014 #define MULTILIB_ABI_DEFAULT "mabi=32"
1015 #define ASM_ABI_DEFAULT_SPEC "-32"
1018 #if MIPS_ABI_DEFAULT == ABI_O64
1019 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1020 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1023 #if MIPS_ABI_DEFAULT == ABI_N32
1024 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1025 #define ASM_ABI_DEFAULT_SPEC "-n32"
1028 #if MIPS_ABI_DEFAULT == ABI_64
1029 #define MULTILIB_ABI_DEFAULT "mabi=64"
1030 #define ASM_ABI_DEFAULT_SPEC "-64"
1033 #if MIPS_ABI_DEFAULT == ABI_EABI
1034 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1035 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1038 /* Only ELF targets can switch the ABI. */
1039 #ifndef OBJECT_FORMAT_ELF
1040 #undef ASM_ABI_DEFAULT_SPEC
1041 #define ASM_ABI_DEFAULT_SPEC ""
1044 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1045 GAS_ASM_SPEC as the default, depending upon the value of
1048 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1051 #define TARGET_ASM_SPEC "\
1052 %{mmips-as: %(mips_as_asm_spec)} \
1053 %{!mmips-as: %(gas_asm_spec)}"
1057 #define TARGET_ASM_SPEC "\
1058 %{!mgas: %(mips_as_asm_spec)} \
1059 %{mgas: %(gas_asm_spec)}"
1061 #endif /* not GAS */
1063 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1064 to the assembler. It may be overridden by subtargets. */
1065 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1066 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1068 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1071 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1072 the assembler. It may be overridden by subtargets. */
1073 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1074 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1075 %{g} %{g0} %{g1} %{g2} %{g3} \
1076 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1077 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1078 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1079 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1083 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1084 and stabs debugging info. */
1085 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1087 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1089 #define MDEBUG_ASM_SPEC ""
1090 #endif /* not GAS */
1092 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1093 overridden by subtargets. */
1095 #ifndef SUBTARGET_ASM_SPEC
1096 #define SUBTARGET_ASM_SPEC ""
1099 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1100 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1101 whether we're using GAS. These options can only be used properly
1102 with GAS, and it is better to get an error from a non-GAS assembler
1103 than to silently generate bad code. */
1107 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1108 %{mips32} %{mips32r2} %{mips64} \
1109 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1110 %(subtarget_asm_optimizing_spec) \
1111 %(subtarget_asm_debugging_spec) \
1113 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1114 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1115 %{mgp32} %{mgp64} %{march=*} \
1116 %(target_asm_spec) \
1117 %(subtarget_asm_spec)"
1119 /* Specify to run a post-processor, mips-tfile after the assembler
1120 has run to stuff the mips debug information into the object file.
1121 This is needed because the $#!%^ MIPS assembler provides no way
1122 of specifying such information in the assembly file. If we are
1123 cross compiling, disable mips-tfile unless the user specifies
1126 #ifndef ASM_FINAL_SPEC
1127 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1129 #define ASM_FINAL_SPEC "\
1130 %{mmips-as: %{!mno-mips-tfile: \
1131 \n mips-tfile %{v*: -v} \
1133 %{!K: %{save-temps: -I %b.o~}} \
1134 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1135 %{.s:%i} %{!.s:%g.s}}}"
1139 #define ASM_FINAL_SPEC "\
1140 %{!mgas: %{!mno-mips-tfile: \
1141 \n mips-tfile %{v*: -v} \
1143 %{!K: %{save-temps: -I %b.o~}} \
1144 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1145 %{.s:%i} %{!.s:%g.s}}}"
1148 #endif /* ASM_FINAL_SPEC */
1150 /* Redefinition of libraries used. Mips doesn't support normal
1151 UNIX style profiling via calling _mcount. It does offer
1152 profiling that samples the PC, so do what we can... */
1155 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1158 /* Extra switches sometimes passed to the linker. */
1159 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1160 will interpret it as a -b option. */
1163 #define LINK_SPEC "\
1165 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1166 %{bestGnum} %{shared} %{non_shared}"
1167 #endif /* LINK_SPEC defined */
1170 /* Specs for the compiler proper */
1172 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1173 overridden by subtargets. */
1174 #ifndef SUBTARGET_CC1_SPEC
1175 #define SUBTARGET_CC1_SPEC ""
1178 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1179 /* Note, we will need to adjust the following if we ever find a MIPS variant
1180 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1181 that show up in this case. */
1185 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1186 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1188 %(subtarget_cc1_spec)"
1191 /* Preprocessor specs. */
1193 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1194 overridden by subtargets. */
1195 #ifndef SUBTARGET_CPP_SPEC
1196 #define SUBTARGET_CPP_SPEC ""
1199 #define CPP_SPEC "%(subtarget_cpp_spec)"
1201 /* This macro defines names of additional specifications to put in the specs
1202 that can be used in various specifications like CC1_SPEC. Its definition
1203 is an initializer with a subgrouping for each command option.
1205 Each subgrouping contains a string constant, that defines the
1206 specification name, and a string constant that used by the GNU CC driver
1209 Do not define this macro if it does not need to do anything. */
1211 #define EXTRA_SPECS \
1212 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1213 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1214 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1215 { "gas_asm_spec", GAS_ASM_SPEC }, \
1216 { "target_asm_spec", TARGET_ASM_SPEC }, \
1217 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1218 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1219 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1220 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1221 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1222 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1223 { "endian_spec", ENDIAN_SPEC }, \
1224 SUBTARGET_EXTRA_SPECS
1226 #ifndef SUBTARGET_EXTRA_SPECS
1227 #define SUBTARGET_EXTRA_SPECS
1230 /* If defined, this macro is an additional prefix to try after
1231 `STANDARD_EXEC_PREFIX'. */
1233 #ifndef MD_EXEC_PREFIX
1234 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1237 #ifndef MD_STARTFILE_PREFIX
1238 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1242 /* Print subsidiary information on the compiler version in use. */
1244 #define MIPS_VERSION "[AL 1.1, MM 40]"
1246 #ifndef MACHINE_TYPE
1247 #define MACHINE_TYPE "BSD Mips"
1250 #ifndef TARGET_VERSION_INTERNAL
1251 #define TARGET_VERSION_INTERNAL(STREAM) \
1252 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1255 #ifndef TARGET_VERSION
1256 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1260 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1261 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1262 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1264 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1265 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1268 /* By default, turn on GDB extensions. */
1269 #define DEFAULT_GDB_EXTENSIONS 1
1271 /* If we are passing smuggling stabs through the MIPS ECOFF object
1272 format, put a comment in front of the .stab<x> operation so
1273 that the MIPS assembler does not choke. The mips-tfile program
1274 will correctly put the stab into the object file. */
1276 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1277 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1278 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1280 /* Local compiler-generated symbols must have a prefix that the assembler
1281 understands. By default, this is $, although some targets (e.g.,
1282 NetBSD-ELF) need to override this. */
1284 #ifndef LOCAL_LABEL_PREFIX
1285 #define LOCAL_LABEL_PREFIX "$"
1288 /* By default on the mips, external symbols do not have an underscore
1289 prepended, but some targets (e.g., NetBSD) require this. */
1291 #ifndef USER_LABEL_PREFIX
1292 #define USER_LABEL_PREFIX ""
1295 /* Forward references to tags are allowed. */
1296 #define SDB_ALLOW_FORWARD_REFERENCES
1298 /* Unknown tags are also allowed. */
1299 #define SDB_ALLOW_UNKNOWN_REFERENCES
1301 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1302 since the length can run past this up to a continuation point. */
1303 #undef DBX_CONTIN_LENGTH
1304 #define DBX_CONTIN_LENGTH 1500
1306 /* How to renumber registers for dbx and gdb. */
1307 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1309 /* The mapping from gcc register number to DWARF 2 CFA column number.
1310 This mapping does not allow for tracking register 0, since SGI's broken
1311 dwarf reader thinks column 0 is used for the frame address, but since
1312 register 0 is fixed this is not a problem. */
1313 #define DWARF_FRAME_REGNUM(REG) \
1314 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1316 /* The DWARF 2 CFA column which tracks the return address. */
1317 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1319 /* Before the prologue, RA lives in r31. */
1320 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1322 /* Describe how we implement __builtin_eh_return. */
1323 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1324 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1326 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1327 The default for this in 64-bit mode is 8, which causes problems with
1328 SFmode register saves. */
1329 #define DWARF_CIE_DATA_ALIGNMENT 4
1331 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1333 #define PUT_SDB_DEF(a) \
1335 fprintf (asm_out_file, "\t%s.def\t", \
1336 (TARGET_GAS) ? "" : "#"); \
1337 ASM_OUTPUT_LABELREF (asm_out_file, a); \
1338 fputc (';', asm_out_file); \
1341 #define PUT_SDB_PLAIN_DEF(a) \
1343 fprintf (asm_out_file, "\t%s.def\t.%s;", \
1344 (TARGET_GAS) ? "" : "#", (a)); \
1347 /* For block start and end, we create labels, so that
1348 later we can figure out where the correct offset is.
1349 The normal .ent/.end serve well enough for functions,
1350 so those are just commented out. */
1352 #define PUT_SDB_BLOCK_START(LINE) \
1354 fprintf (asm_out_file, \
1355 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1356 LOCAL_LABEL_PREFIX, \
1358 (TARGET_GAS) ? "" : "#", \
1359 LOCAL_LABEL_PREFIX, \
1362 sdb_label_count++; \
1365 #define PUT_SDB_BLOCK_END(LINE) \
1367 fprintf (asm_out_file, \
1368 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1369 LOCAL_LABEL_PREFIX, \
1371 (TARGET_GAS) ? "" : "#", \
1372 LOCAL_LABEL_PREFIX, \
1375 sdb_label_count++; \
1378 #define PUT_SDB_FUNCTION_START(LINE)
1380 #define PUT_SDB_FUNCTION_END(LINE) \
1382 ASM_OUTPUT_SOURCE_LINE (asm_out_file, LINE + sdb_begin_function_line, 0); \
1385 #define PUT_SDB_EPILOGUE_END(NAME)
1387 /* Correct the offset of automatic variables and arguments. Note that
1388 the MIPS debug format wants all automatic variables and arguments
1389 to be in terms of the virtual frame pointer (stack pointer before
1390 any adjustment in the function), while the MIPS 3.0 linker wants
1391 the frame pointer to be the stack pointer after the initial
1394 #define DEBUGGER_AUTO_OFFSET(X) \
1395 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1396 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1397 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1399 /* Tell collect that the object format is ECOFF */
1400 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1401 #define EXTENDED_COFF /* ECOFF, not normal coff */
1403 /* Target machine storage layout */
1405 /* Define this if most significant bit is lowest numbered
1406 in instructions that operate on numbered bit-fields.
1408 #define BITS_BIG_ENDIAN 0
1410 /* Define this if most significant byte of a word is the lowest numbered. */
1411 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1413 /* Define this if most significant word of a multiword number is the lowest. */
1414 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1416 /* Define this to set the endianness to use in libgcc2.c, which can
1417 not depend on target_flags. */
1418 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1419 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1421 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1424 #define MAX_BITS_PER_WORD 64
1426 /* Width of a word, in units (bytes). */
1427 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1428 #define MIN_UNITS_PER_WORD 4
1430 /* For MIPS, width of a floating point register. */
1431 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1433 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1434 the next available register. */
1435 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1437 /* The largest size of value that can be held in floating-point
1438 registers and moved with a single instruction. */
1439 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1441 /* The largest size of value that can be held in floating-point
1443 #define UNITS_PER_FPVALUE \
1444 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1446 /* The number of bytes in a double. */
1447 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1449 /* A C expression for the size in bits of the type `int' on the
1450 target machine. If you don't define this, the default is one
1452 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1454 /* Tell the preprocessor the maximum size of wchar_t. */
1455 #ifndef MAX_WCHAR_TYPE_SIZE
1456 #ifndef WCHAR_TYPE_SIZE
1457 #define MAX_WCHAR_TYPE_SIZE 64
1461 /* A C expression for the size in bits of the type `short' on the
1462 target machine. If you don't define this, the default is half a
1463 word. (If this would be less than one storage unit, it is
1464 rounded up to one unit.) */
1465 #define SHORT_TYPE_SIZE 16
1467 /* A C expression for the size in bits of the type `long' on the
1468 target machine. If you don't define this, the default is one
1470 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1471 #define MAX_LONG_TYPE_SIZE 64
1473 /* A C expression for the size in bits of the type `long long' on the
1474 target machine. If you don't define this, the default is two
1476 #define LONG_LONG_TYPE_SIZE 64
1478 /* A C expression for the size in bits of the type `float' on the
1479 target machine. If you don't define this, the default is one
1481 #define FLOAT_TYPE_SIZE 32
1483 /* A C expression for the size in bits of the type `double' on the
1484 target machine. If you don't define this, the default is two
1486 #define DOUBLE_TYPE_SIZE 64
1488 /* A C expression for the size in bits of the type `long double' on
1489 the target machine. If you don't define this, the default is two
1491 #define LONG_DOUBLE_TYPE_SIZE \
1492 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1494 /* long double is not a fixed mode, but the idea is that, if we
1495 support long double, we also want a 128-bit integer type. */
1496 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1499 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1500 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1501 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1503 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1507 /* Width in bits of a pointer. */
1508 #ifndef POINTER_SIZE
1509 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1512 #define POINTERS_EXTEND_UNSIGNED 0
1514 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1515 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1516 || mips_abi == ABI_64 \
1517 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1520 /* Allocation boundary (in *bits*) for the code of a function. */
1521 #define FUNCTION_BOUNDARY 32
1523 /* Alignment of field after `int : 0' in a structure. */
1524 #define EMPTY_FIELD_BOUNDARY 32
1526 /* Every structure's size must be a multiple of this. */
1527 /* 8 is observed right on a DECstation and on riscos 4.02. */
1528 #define STRUCTURE_SIZE_BOUNDARY 8
1530 /* There is no point aligning anything to a rounder boundary than this. */
1531 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1533 /* Set this nonzero if move instructions will actually fail to work
1534 when given unaligned data. */
1535 #define STRICT_ALIGNMENT 1
1537 /* Define this if you wish to imitate the way many other C compilers
1538 handle alignment of bitfields and the structures that contain
1541 The behavior is that the type written for a bit-field (`int',
1542 `short', or other integer type) imposes an alignment for the
1543 entire structure, as if the structure really did contain an
1544 ordinary field of that type. In addition, the bit-field is placed
1545 within the structure so that it would fit within such a field,
1546 not crossing a boundary for it.
1548 Thus, on most machines, a bit-field whose type is written as `int'
1549 would not cross a four-byte boundary, and would force four-byte
1550 alignment for the whole structure. (The alignment used may not
1551 be four bytes; it is controlled by the other alignment
1554 If the macro is defined, its definition should be a C expression;
1555 a nonzero value for the expression enables this behavior. */
1557 #define PCC_BITFIELD_TYPE_MATTERS 1
1559 /* If defined, a C expression to compute the alignment given to a
1560 constant that is being placed in memory. CONSTANT is the constant
1561 and ALIGN is the alignment that the object would ordinarily have.
1562 The value of this macro is used instead of that alignment to align
1565 If this macro is not defined, then ALIGN is used.
1567 The typical use of this macro is to increase alignment for string
1568 constants to be word aligned so that `strcpy' calls that copy
1569 constants can be done inline. */
1571 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1572 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1573 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1575 /* If defined, a C expression to compute the alignment for a static
1576 variable. TYPE is the data type, and ALIGN is the alignment that
1577 the object would ordinarily have. The value of this macro is used
1578 instead of that alignment to align the object.
1580 If this macro is not defined, then ALIGN is used.
1582 One use of this macro is to increase alignment of medium-size
1583 data to make it all fit in fewer cache lines. Another is to
1584 cause character arrays to be word-aligned so that `strcpy' calls
1585 that copy constants to character arrays can be done inline. */
1587 #undef DATA_ALIGNMENT
1588 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1589 ((((ALIGN) < BITS_PER_WORD) \
1590 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1591 || TREE_CODE (TYPE) == UNION_TYPE \
1592 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1595 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1597 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1599 /* Define this macro if an argument declared as `char' or `short' in a
1600 prototype should actually be passed as an `int'. In addition to
1601 avoiding errors in certain cases of mismatch, it also makes for
1602 better code on certain machines. */
1604 #define PROMOTE_PROTOTYPES 1
1606 /* Define if operations between registers always perform the operation
1607 on the full register even if a narrower mode is specified. */
1608 #define WORD_REGISTER_OPERATIONS
1610 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1611 will either zero-extend or sign-extend. The value of this macro should
1612 be the code that says which one of the two operations is implicitly
1615 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1616 moves. All other references are zero extended. */
1617 #define LOAD_EXTEND_OP(MODE) \
1618 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1619 ? SIGN_EXTEND : ZERO_EXTEND)
1621 /* Define this macro if it is advisable to hold scalars in registers
1622 in a wider mode than that declared by the program. In such cases,
1623 the value is constrained to be within the bounds of the declared
1624 type, but kept valid in the wider mode. The signedness of the
1625 extension may differ from that of the type. */
1627 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1628 if (GET_MODE_CLASS (MODE) == MODE_INT \
1629 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1631 if ((MODE) == SImode) \
1636 /* Define if loading short immediate values into registers sign extends. */
1637 #define SHORT_IMMEDIATES_SIGN_EXTEND
1640 /* Define this if function arguments should also be promoted using the above
1642 #define PROMOTE_FUNCTION_ARGS
1644 /* Likewise, if the function return value is promoted. */
1645 #define PROMOTE_FUNCTION_RETURN
1648 /* Standard register usage. */
1650 /* Number of actual hardware registers.
1651 The hardware registers are assigned numbers for the compiler
1652 from 0 to just below FIRST_PSEUDO_REGISTER.
1653 All registers that the compiler knows about must be given numbers,
1654 even those that are not normally considered general registers.
1656 On the Mips, we have 32 integer registers, 32 floating point
1657 registers, 8 condition code registers, and the special registers
1658 hi and lo. After that we have 32 COP0 registers, 32 COP2 registers,
1659 and 32 COP3 registers. (COP1 is the floating-point processor.)
1660 The 8 condition code registers are only used if mips_isa >= 4. */
1662 #define FIRST_PSEUDO_REGISTER 176
1664 /* 1 for registers that have pervasive standard uses
1665 and are not available for the register allocator.
1667 On the MIPS, see conventions, page D-2 */
1669 /* Regarding coprocessor registers: without evidence to the contrary,
1670 it's best to assume that each coprocessor register has a unique
1671 use. This can be overridden, in, e.g., override_options() or
1672 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1673 for a particular target. */
1675 #define FIXED_REGISTERS \
1677 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1678 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1679 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1680 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1681 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1682 /* COP0 registers */ \
1683 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1684 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1685 /* COP2 registers */ \
1686 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1687 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1688 /* COP3 registers */ \
1689 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1690 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1694 /* Don't mark $31 as a call-clobbered register. The idea is that
1695 it's really the call instructions themselves which clobber $31.
1696 We don't care what the called function does with it afterwards.
1698 This approach makes it easier to implement sibcalls. Unlike normal
1699 calls, sibcalls don't clobber $31, so the register reaches the
1700 called function in tact. EPILOGUE_USES says that $31 is useful
1701 to the called function. */
1703 #define CALL_USED_REGISTERS \
1705 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1706 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1707 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1708 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1709 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1710 /* COP0 registers */ \
1711 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1712 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1713 /* COP2 registers */ \
1714 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1715 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1716 /* COP3 registers */ \
1717 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1718 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1721 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1722 problem which makes CALL_USED_REGISTERS *always* include
1723 all the FIXED_REGISTERS. Until this problem has been
1724 resolved this macro can be used to overcome this situation.
1725 In particular, block_propagate() requires this list
1726 be accurate, or we can remove registers which should be live.
1727 This macro is used in regs_invalidated_by_call. */
1730 #define CALL_REALLY_USED_REGISTERS \
1731 { /* General registers. */ \
1732 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1733 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1734 /* Floating-point registers. */ \
1735 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1736 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1738 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1739 /* COP0 registers */ \
1740 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1741 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1742 /* COP2 registers */ \
1743 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1744 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1745 /* COP3 registers */ \
1746 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1747 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1750 /* Internal macros to classify a register number as to whether it's a
1751 general purpose register, a floating point register, a
1752 multiply/divide register, or a status register. */
1754 #define GP_REG_FIRST 0
1755 #define GP_REG_LAST 31
1756 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1757 #define GP_DBX_FIRST 0
1759 #define FP_REG_FIRST 32
1760 #define FP_REG_LAST 63
1761 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1762 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1764 #define MD_REG_FIRST 64
1765 #define MD_REG_LAST 65
1766 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1767 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1769 #define ST_REG_FIRST 67
1770 #define ST_REG_LAST 74
1771 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1774 /* FIXME: renumber. */
1775 #define COP0_REG_FIRST 80
1776 #define COP0_REG_LAST 111
1777 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1779 #define COP2_REG_FIRST 112
1780 #define COP2_REG_LAST 143
1781 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1783 #define COP3_REG_FIRST 144
1784 #define COP3_REG_LAST 175
1785 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1786 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1787 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1789 #define AT_REGNUM (GP_REG_FIRST + 1)
1790 #define HI_REGNUM (MD_REG_FIRST + 0)
1791 #define LO_REGNUM (MD_REG_FIRST + 1)
1793 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1794 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1795 should be used instead. */
1796 #define FPSW_REGNUM ST_REG_FIRST
1798 #define GP_REG_P(REGNO) \
1799 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1800 #define M16_REG_P(REGNO) \
1801 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1802 #define FP_REG_P(REGNO) \
1803 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1804 #define MD_REG_P(REGNO) \
1805 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1806 #define ST_REG_P(REGNO) \
1807 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1808 #define COP0_REG_P(REGNO) \
1809 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1810 #define COP2_REG_P(REGNO) \
1811 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1812 #define COP3_REG_P(REGNO) \
1813 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1814 #define ALL_COP_REG_P(REGNO) \
1815 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1817 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1819 /* Return coprocessor number from register number. */
1821 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1822 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1823 : COP3_REG_P (REGNO) ? '3' : '?')
1825 /* Return number of consecutive hard regs needed starting at reg REGNO
1826 to hold something of mode MODE.
1827 This is ordinarily the length in words of a value of mode MODE
1828 but can be less for certain modes in special long registers.
1830 On the MIPS, all general registers are one word long. Except on
1831 the R4000 with the FR bit set, the floating point uses register
1832 pairs, with the second register not being allocable. */
1834 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1836 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1837 MODE. In 32 bit mode, require that DImode and DFmode be in even
1838 registers. For DImode, this makes some of the insns easier to
1839 write, since you don't have to worry about a DImode value in
1840 registers 3 & 4, producing a result in 4 & 5.
1842 To make the code simpler HARD_REGNO_MODE_OK now just references an
1843 array built in override_options. Because machmodes.h is not yet
1844 included before this file is processed, the MODE bound can't be
1847 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1849 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1850 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1852 /* Value is 1 if it is a good idea to tie two pseudo registers
1853 when one has mode MODE1 and one has mode MODE2.
1854 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1855 for any hard reg, then this must be 0 for correct output. */
1856 #define MODES_TIEABLE_P(MODE1, MODE2) \
1857 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1858 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1859 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1860 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1862 /* MIPS pc is not overloaded on a register. */
1863 /* #define PC_REGNUM xx */
1865 /* Register to use for pushing function arguments. */
1866 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1868 /* Offset from the stack pointer to the first available location. Use
1869 the default value zero. */
1870 /* #define STACK_POINTER_OFFSET 0 */
1872 /* Base register for access to local variables of the function. We
1873 pretend that the frame pointer is $1, and then eliminate it to
1874 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1875 a fixed register, and will not be used for anything else. */
1876 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1878 /* Temporary scratch register for use by the assembler. */
1879 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1881 /* $30 is not available on the mips16, so we use $17 as the frame
1883 #define HARD_FRAME_POINTER_REGNUM \
1884 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1886 /* Value should be nonzero if functions must have frame pointers.
1887 Zero means the frame pointer need not be set up (and parms
1888 may be accessed via the stack pointer) in functions that seem suitable.
1889 This is computed in `reload', in reload1.c. */
1890 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1892 /* Base register for access to arguments of the function. */
1893 #define ARG_POINTER_REGNUM GP_REG_FIRST
1895 /* Register in which static-chain is passed to a function. */
1896 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1898 /* If the structure value address is passed in a register, then
1899 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1900 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1902 /* If the structure value address is not passed in a register, define
1903 `STRUCT_VALUE' as an expression returning an RTX for the place
1904 where the address is passed. If it returns 0, the address is
1905 passed as an "invisible" first argument. */
1906 #define STRUCT_VALUE 0
1908 /* Mips registers used in prologue/epilogue code when the stack frame
1909 is larger than 32K bytes. These registers must come from the
1910 scratch register set, and not used for passing and returning
1911 arguments and any other information used in the calling sequence
1912 (such as pic). Must start at 12, since t0/t3 are parameter passing
1913 registers in the 64 bit ABI. */
1915 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1916 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1918 /* Define this macro if it is as good or better to call a constant
1919 function address than to call an address kept in a register. */
1920 #define NO_FUNCTION_CSE 1
1922 /* Define this macro if it is as good or better for a function to
1923 call itself with an explicit address than to call an address
1924 kept in a register. */
1925 #define NO_RECURSIVE_FUNCTION_CSE 1
1927 /* The ABI-defined global pointer. Sometimes we use a different
1928 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1929 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1931 /* We normally use $28 as the global pointer. However, when generating
1932 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1933 register instead. They can then avoid saving and restoring $28
1934 and perhaps avoid using a frame at all.
1936 When a leaf function uses something other than $28, mips_expand_prologue
1937 will modify pic_offset_table_rtx in place. Take the register number
1938 from there after reload. */
1939 #define PIC_OFFSET_TABLE_REGNUM \
1940 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1942 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1944 /* Define the classes of registers for register constraints in the
1945 machine description. Also define ranges of constants.
1947 One of the classes must always be named ALL_REGS and include all hard regs.
1948 If there is more than one class, another class must be named NO_REGS
1949 and contain no registers.
1951 The name GENERAL_REGS must be the name of a class (or an alias for
1952 another name such as ALL_REGS). This is the class of registers
1953 that is allowed by "g" or "r" in a register constraint.
1954 Also, registers outside this class are allocated only when
1955 instructions express preferences for them.
1957 The classes must be numbered in nondecreasing order; that is,
1958 a larger-numbered class must never be contained completely
1959 in a smaller-numbered class.
1961 For any two classes, it is very desirable that there be another
1962 class that represents their union. */
1966 NO_REGS, /* no registers in set */
1967 M16_NA_REGS, /* mips16 regs not used to pass args */
1968 M16_REGS, /* mips16 directly accessible registers */
1969 T_REG, /* mips16 T register ($24) */
1970 M16_T_REGS, /* mips16 registers plus T register */
1971 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1972 LEA_REGS, /* Every GPR except $25 */
1973 GR_REGS, /* integer registers */
1974 FP_REGS, /* floating point registers */
1975 HI_REG, /* hi register */
1976 LO_REG, /* lo register */
1977 MD_REGS, /* multiply/divide registers (hi/lo) */
1978 COP0_REGS, /* generic coprocessor classes */
1981 HI_AND_GR_REGS, /* union classes */
1988 ALL_COP_AND_GR_REGS,
1989 ST_REGS, /* status registers (fp status) */
1990 ALL_REGS, /* all registers */
1991 LIM_REG_CLASSES /* max value + 1 */
1994 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1996 #define GENERAL_REGS GR_REGS
1998 /* An initializer containing the names of the register classes as C
1999 string constants. These names are used in writing some of the
2002 #define REG_CLASS_NAMES \
2009 "PIC_FN_ADDR_REG", \
2016 /* coprocessor registers */ \
2023 "COP0_AND_GR_REGS", \
2024 "COP2_AND_GR_REGS", \
2025 "COP3_AND_GR_REGS", \
2027 "ALL_COP_AND_GR_REGS", \
2032 /* An initializer containing the contents of the register classes,
2033 as integers which are bit masks. The Nth integer specifies the
2034 contents of class N. The way the integer MASK is interpreted is
2035 that register R is in the class if `MASK & (1 << R)' is 1.
2037 When the machine has more than 32 registers, an integer does not
2038 suffice. Then the integers are replaced by sub-initializers,
2039 braced groupings containing several integers. Each
2040 sub-initializer must be suitable as an initializer for the type
2041 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2043 #define REG_CLASS_CONTENTS \
2045 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2046 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2047 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2048 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2049 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2050 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
2051 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
2052 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2053 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2054 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2055 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2056 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2057 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2058 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2059 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2060 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2061 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2062 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2063 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2064 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2065 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2066 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2067 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2068 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2069 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2073 /* A C expression whose value is a register class containing hard
2074 register REGNO. In general there is more that one such class;
2075 choose a class which is "minimal", meaning that no smaller class
2076 also contains the register. */
2078 extern const enum reg_class mips_regno_to_class[];
2080 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2082 /* A macro whose definition is the name of the class to which a
2083 valid base register must belong. A base register is one used in
2084 an address which is the register value plus a displacement. */
2086 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2088 /* A macro whose definition is the name of the class to which a
2089 valid index register must belong. An index register is one used
2090 in an address where its value is either multiplied by a scale
2091 factor or added to another register (as well as added to a
2094 #define INDEX_REG_CLASS NO_REGS
2096 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2097 registers explicitly used in the rtl to be used as spill registers
2098 but prevents the compiler from extending the lifetime of these
2101 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2103 /* This macro is used later on in the file. */
2104 #define GR_REG_CLASS_P(CLASS) \
2105 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2106 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
2107 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
2109 /* This macro is also used later on in the file. */
2110 #define COP_REG_CLASS_P(CLASS) \
2111 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2113 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2114 is the default value (allocate the registers in numeric order). We
2115 define it just so that we can override it for the mips16 target in
2116 ORDER_REGS_FOR_LOCAL_ALLOC. */
2118 #define REG_ALLOC_ORDER \
2119 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2120 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2121 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2122 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2123 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2124 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2125 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2126 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2127 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2128 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2129 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2132 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2133 to be rearranged based on a particular function. On the mips16, we
2134 want to allocate $24 (T_REG) before other registers for
2135 instructions for which it is possible. */
2137 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2139 /* REGISTER AND CONSTANT CLASSES */
2141 /* Get reg_class from a letter such as appears in the machine
2144 DEFINED REGISTER CLASSES:
2146 'd' General (aka integer) registers
2147 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2148 'y' General registers (in both mips16 and non mips16 mode)
2149 'e' mips16 non argument registers (M16_NA_REGS)
2150 't' mips16 temporary register ($24)
2151 'f' Floating point registers
2154 'x' Multiply/divide registers
2155 'z' FP Status register
2159 'b' All registers */
2161 extern enum reg_class mips_char_to_class[256];
2163 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2165 /* True if VALUE is a signed 16-bit number. */
2167 #define SMALL_OPERAND(VALUE) \
2168 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2170 /* True if VALUE is an unsigned 16-bit number. */
2172 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2173 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2175 /* True if VALUE can be loaded into a register using LUI. */
2177 #define LUI_OPERAND(VALUE) \
2178 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2179 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2181 /* Return a value X with the low 16 bits clear, and such that
2182 VALUE - X is a signed 16-bit value. */
2184 #define CONST_HIGH_PART(VALUE) \
2185 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2187 #define CONST_LOW_PART(VALUE) \
2188 ((VALUE) - CONST_HIGH_PART (VALUE))
2190 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2191 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2192 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2194 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2195 string can be used to stand for particular ranges of immediate
2196 operands. This macro defines what the ranges are. C is the
2197 letter, and VALUE is a constant value. Return 1 if VALUE is
2198 in the range specified by C. */
2202 `I' is used for the range of constants an arithmetic insn can
2203 actually contain (16 bits signed integers).
2205 `J' is used for the range which is just zero (ie, $r0).
2207 `K' is used for the range of constants a logical insn can actually
2208 contain (16 bit zero-extended integers).
2210 `L' is used for the range of constants that be loaded with lui
2211 (ie, the bottom 16 bits are zero).
2213 `M' is used for the range of constants that take two words to load
2214 (ie, not matched by `I', `K', and `L').
2216 `N' is used for negative 16 bit constants other than -65536.
2218 `O' is a 15 bit signed integer.
2220 `P' is used for positive 16 bit constants. */
2222 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2223 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2224 : (C) == 'J' ? ((VALUE) == 0) \
2225 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2226 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2227 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2228 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2229 && !LUI_OPERAND (VALUE)) \
2230 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2231 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2232 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2235 /* Similar, but for floating constants, and defining letters G and H.
2236 Here VALUE is the CONST_DOUBLE rtx itself. */
2240 'G' : Floating point 0 */
2242 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2244 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2246 /* True if OP is a constant that should not be moved into $25.
2247 We need this because many versions of gas treat 'la $25,foo' as
2248 part of a call sequence and allow a global 'foo' to be lazily bound. */
2250 #define DANGEROUS_FOR_LA25_P(OP) \
2252 && !TARGET_EXPLICIT_RELOCS \
2253 && mips_global_pic_constant_p (OP))
2255 /* Letters in the range `Q' through `U' may be defined in a
2256 machine-dependent fashion to stand for arbitrary operand types.
2257 The machine description macro `EXTRA_CONSTRAINT' is passed the
2258 operand as its first argument and the constraint letter as its
2261 `Q' is for signed 16-bit constants.
2262 `R' is for single-instruction memory references. Note that this
2263 constraint has often been used in linux and glibc code.
2264 `S' is for legitimate constant call addresses.
2265 `T' is for constant move_operands that cannot be safely loaded into $25.
2266 `U' is for constant move_operands that can be safely loaded into $25. */
2268 #define EXTRA_CONSTRAINT(OP,CODE) \
2269 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2270 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2271 && mips_fetch_insns (OP) == 1) \
2272 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2273 && call_insn_operand (OP, VOIDmode)) \
2274 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2275 && move_operand (OP, VOIDmode) \
2276 && DANGEROUS_FOR_LA25_P (OP)) \
2277 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2278 && move_operand (OP, VOIDmode) \
2279 && !DANGEROUS_FOR_LA25_P (OP)) \
2282 /* Given an rtx X being reloaded into a reg required to be
2283 in class CLASS, return the class of reg to actually use.
2284 In general this is just CLASS; but on some machines
2285 in some cases it is preferable to use a more restrictive class. */
2287 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2288 ((CLASS) != ALL_REGS \
2289 ? (! TARGET_MIPS16 \
2291 : ((CLASS) != GR_REGS \
2294 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2295 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2296 ? (TARGET_SOFT_FLOAT \
2297 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2299 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2300 || GET_MODE (X) == VOIDmode) \
2301 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2304 /* Certain machines have the property that some registers cannot be
2305 copied to some other registers without using memory. Define this
2306 macro on those machines to be a C expression that is nonzero if
2307 objects of mode MODE in registers of CLASS1 can only be copied to
2308 registers of class CLASS2 by storing a register of CLASS1 into
2309 memory and loading that memory location into a register of CLASS2.
2311 Do not define this macro if its value would always be zero. */
2313 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2314 ((!TARGET_DEBUG_H_MODE \
2315 && GET_MODE_CLASS (MODE) == MODE_INT \
2316 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2317 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2318 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2319 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2320 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2322 /* The HI and LO registers can only be reloaded via the general
2323 registers. Condition code registers can only be loaded to the
2324 general registers, and from the floating point registers. */
2326 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2327 mips_secondary_reload_class (CLASS, MODE, X, 1)
2328 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2329 mips_secondary_reload_class (CLASS, MODE, X, 0)
2331 /* Return the maximum number of consecutive registers
2332 needed to represent mode MODE in a register of class CLASS. */
2334 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2336 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2337 mips_cannot_change_mode_class (FROM, TO, CLASS)
2339 /* Stack layout; function entry, exit and calling. */
2341 #define STACK_GROWS_DOWNWARD
2343 /* The offset of the first local variable from the beginning of the frame.
2344 See compute_frame_size for details about the frame layout. */
2345 #define STARTING_FRAME_OFFSET \
2346 (current_function_outgoing_args_size \
2347 + (TARGET_ABICALLS && !TARGET_NEWABI \
2348 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2350 /* Offset from the stack pointer register to an item dynamically
2351 allocated on the stack, e.g., by `alloca'.
2353 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2354 length of the outgoing arguments. The default is correct for most
2355 machines. See `function.c' for details.
2357 The MIPS ABI states that functions which dynamically allocate the
2358 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2359 we are trying to create a second frame pointer to the function, so
2360 allocate some stack space to make it happy.
2362 However, the linker currently complains about linking any code that
2363 dynamically allocates stack space, and there seems to be a bug in
2364 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2367 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2368 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2369 ? 4*UNITS_PER_WORD \
2370 : current_function_outgoing_args_size)
2373 /* The return address for the current frame is in r31 if this is a leaf
2374 function. Otherwise, it is on the stack. It is at a variable offset
2375 from sp/fp/ap, so we define a fake hard register rap which is a
2376 pointer to the return address on the stack. This always gets eliminated
2377 during reload to be either the frame pointer or the stack pointer plus
2380 #define RETURN_ADDR_RTX mips_return_addr
2382 /* Since the mips16 ISA mode is encoded in the least-significant bit
2383 of the address, mask it off return addresses for purposes of
2384 finding exception handling regions. */
2386 #define MASK_RETURN_ADDR GEN_INT (-2)
2389 /* Similarly, don't use the least-significant bit to tell pointers to
2390 code from vtable index. */
2392 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2394 /* If defined, this macro specifies a table of register pairs used to
2395 eliminate unneeded registers that point into the stack frame. If
2396 it is not defined, the only elimination attempted by the compiler
2397 is to replace references to the frame pointer with references to
2400 The definition of this macro is a list of structure
2401 initializations, each of which specifies an original and
2402 replacement register.
2404 On some machines, the position of the argument pointer is not
2405 known until the compilation is completed. In such a case, a
2406 separate hard register must be used for the argument pointer.
2407 This register can be eliminated by replacing it with either the
2408 frame pointer or the argument pointer, depending on whether or not
2409 the frame pointer has been eliminated.
2411 In this case, you might specify:
2412 #define ELIMINABLE_REGS \
2413 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2414 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2415 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2417 Note that the elimination of the argument pointer with the stack
2418 pointer is specified first since that is the preferred elimination.
2420 The eliminations to $17 are only used on the mips16. See the
2421 definition of HARD_FRAME_POINTER_REGNUM. */
2423 #define ELIMINABLE_REGS \
2424 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2425 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2426 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2427 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2428 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2429 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2431 /* A C expression that returns nonzero if the compiler is allowed to
2432 try to replace register number FROM-REG with register number
2433 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2434 defined, and will usually be the constant 1, since most of the
2435 cases preventing register elimination are things that the compiler
2436 already knows about.
2438 When not in mips16 and mips64, we can always eliminate to the
2439 frame pointer. We can eliminate to the stack pointer unless
2440 a frame pointer is needed. In mips16 mode, we need a frame
2441 pointer for a large frame; otherwise, reload may be unable
2442 to compute the address of a local variable, since there is
2443 no way to add a large constant to the stack pointer
2444 without using a temporary register.
2446 In mips16, for some instructions (eg lwu), we can't eliminate the
2447 frame pointer for the stack pointer. These instructions are
2448 only generated in TARGET_64BIT mode.
2451 #define CAN_ELIMINATE(FROM, TO) \
2452 (((TO) == HARD_FRAME_POINTER_REGNUM \
2453 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2454 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2455 && (! TARGET_MIPS16 \
2456 || compute_frame_size (get_frame_size ()) < 32768))))
2458 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2459 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2461 /* If we generate an insn to push BYTES bytes,
2462 this says how many the stack pointer really advances by.
2463 On the VAX, sp@- in a byte insn really pushes a word. */
2465 /* #define PUSH_ROUNDING(BYTES) 0 */
2467 /* If defined, the maximum amount of space required for outgoing
2468 arguments will be computed and placed into the variable
2469 `current_function_outgoing_args_size'. No space will be pushed
2470 onto the stack for each call; instead, the function prologue
2471 should increase the stack frame size by this amount.
2473 It is not proper to define both `PUSH_ROUNDING' and
2474 `ACCUMULATE_OUTGOING_ARGS'. */
2475 #define ACCUMULATE_OUTGOING_ARGS 1
2477 /* Offset from the argument pointer register to the first argument's
2478 address. On some machines it may depend on the data type of the
2481 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2482 the first argument's address.
2484 On the MIPS, we must skip the first argument position if we are
2485 returning a structure or a union, to account for its address being
2486 passed in $4. However, at the current time, this produces a compiler
2487 that can't bootstrap, so comment it out for now. */
2490 #define FIRST_PARM_OFFSET(FNDECL) \
2492 && TREE_TYPE (FNDECL) != 0 \
2493 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2494 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2495 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2499 #define FIRST_PARM_OFFSET(FNDECL) 0
2502 /* When a parameter is passed in a register, stack space is still
2503 allocated for it. For the MIPS, stack space must be allocated, cf
2504 Asm Lang Prog Guide page 7-8.
2506 BEWARE that some space is also allocated for non existing arguments
2507 in register. In case an argument list is of form GF used registers
2508 are a0 (a2,a3), but we should push over a1... */
2510 #define REG_PARM_STACK_SPACE(FNDECL) \
2511 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2512 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2515 /* Define this if it is the responsibility of the caller to
2516 allocate the area reserved for arguments passed in registers.
2517 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2518 of this macro is to determine whether the space is included in
2519 `current_function_outgoing_args_size'. */
2520 #define OUTGOING_REG_PARM_STACK_SPACE
2522 #define STACK_BOUNDARY \
2523 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2527 /* A C expression that should indicate the number of bytes of its
2528 own arguments that a function pops on returning, or 0
2529 if the function pops no arguments and the caller must therefore
2530 pop them all after the function returns.
2532 FUNDECL is the declaration node of the function (as a tree).
2534 FUNTYPE is a C variable whose value is a tree node that
2535 describes the function in question. Normally it is a node of
2536 type `FUNCTION_TYPE' that describes the data type of the function.
2537 From this it is possible to obtain the data types of the value
2538 and arguments (if known).
2540 When a call to a library function is being considered, FUNTYPE
2541 will contain an identifier node for the library function. Thus,
2542 if you need to distinguish among various library functions, you
2543 can do so by their names. Note that "library function" in this
2544 context means a function used to perform arithmetic, whose name
2545 is known specially in the compiler and was not mentioned in the
2546 C code being compiled.
2548 STACK-SIZE is the number of bytes of arguments passed on the
2549 stack. If a variable number of bytes is passed, it is zero, and
2550 argument popping will always be the responsibility of the
2551 calling function. */
2553 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2556 /* Symbolic macros for the registers used to return integer and floating
2559 #define GP_RETURN (GP_REG_FIRST + 2)
2560 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2562 #define MAX_ARGS_IN_REGISTERS \
2563 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2565 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2567 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2569 /* Symbolic macros for the first/last argument registers. */
2571 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2572 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2573 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2574 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2576 /* Define how to find the value returned by a library function
2577 assuming the value has mode MODE. Because we define
2578 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2579 PROMOTE_MODE does. */
2581 #define LIBCALL_VALUE(MODE) \
2582 mips_function_value (NULL_TREE, NULL, (MODE))
2584 /* Define how to find the value returned by a function.
2585 VALTYPE is the data type of the value (as a tree).
2586 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2587 otherwise, FUNC is 0. */
2589 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2590 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2592 /* 1 if N is a possible register number for a function value.
2593 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2594 Currently, R2 and F0 are only implemented here (C has no complex type) */
2596 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2597 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2598 && (N) == FP_RETURN + 2))
2600 /* 1 if N is a possible register number for function argument passing.
2601 We have no FP argument registers when soft-float. When FP registers
2602 are 32 bits, we can't directly reference the odd numbered ones. */
2604 #define FUNCTION_ARG_REGNO_P(N) \
2605 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2606 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2607 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2610 /* A C expression which can inhibit the returning of certain function
2611 values in registers, based on the type of value. A nonzero value says
2612 to return the function value in memory, just as large structures are
2613 always returned. Here TYPE will be a C expression of type
2614 `tree', representing the data type of the value.
2616 Note that values of mode `BLKmode' must be explicitly
2617 handled by this macro. Also, the option `-fpcc-struct-return'
2618 takes effect regardless of this macro. On most systems, it is
2619 possible to leave the macro undefined; this causes a default
2620 definition to be used, whose value is the constant 1 for BLKmode
2621 values, and 0 otherwise.
2623 GCC normally converts 1 byte structures into chars, 2 byte
2624 structs into shorts, and 4 byte structs into ints, and returns
2625 them this way. Defining the following macro overrides this,
2626 to give us MIPS cc compatibility. */
2628 #define RETURN_IN_MEMORY(TYPE) \
2629 mips_return_in_memory (TYPE)
2631 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2632 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2635 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2637 /* Define a data type for recording info about an argument list
2638 during the scan of that argument list. This data type should
2639 hold all necessary information about the function itself
2640 and about the args processed so far, enough to enable macros
2641 such as FUNCTION_ARG to determine where the next arg should go.
2643 This structure has to cope with two different argument allocation
2644 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2645 first N words go in registers and the rest go on the stack. If I < N,
2646 the Ith word might go in Ith integer argument register or the
2647 Ith floating-point one. In some cases, it has to go in both (see
2648 function_arg). For these ABIs, we only need to remember the number
2649 of words passed so far.
2651 The EABI instead allocates the integer and floating-point arguments
2652 separately. The first N words of FP arguments go in FP registers,
2653 the rest go on the stack. Likewise, the first N words of the other
2654 arguments go in integer registers, and the rest go on the stack. We
2655 need to maintain three counts: the number of integer registers used,
2656 the number of floating-point registers used, and the number of words
2657 passed on the stack.
2659 We could keep separate information for the two ABIs (a word count for
2660 the standard ABIs, and three separate counts for the EABI). But it
2661 seems simpler to view the standard ABIs as forms of EABI that do not
2662 allocate floating-point registers.
2664 So for the standard ABIs, the first N words are allocated to integer
2665 registers, and function_arg decides on an argument-by-argument basis
2666 whether that argument should really go in an integer register, or in
2667 a floating-point one. */
2669 typedef struct mips_args {
2670 /* Always true for varargs functions. Otherwise true if at least
2671 one argument has been passed in an integer register. */
2674 /* The number of arguments seen so far. */
2675 unsigned int arg_number;
2677 /* For EABI, the number of integer registers used so far. For other
2678 ABIs, the number of words passed in registers (whether integer
2679 or floating-point). */
2680 unsigned int num_gprs;
2682 /* For EABI, the number of floating-point registers used so far. */
2683 unsigned int num_fprs;
2685 /* The number of words passed on the stack. */
2686 unsigned int stack_words;
2688 /* On the mips16, we need to keep track of which floating point
2689 arguments were passed in general registers, but would have been
2690 passed in the FP regs if this were a 32 bit function, so that we
2691 can move them to the FP regs if we wind up calling a 32 bit
2692 function. We record this information in fp_code, encoded in base
2693 four. A zero digit means no floating point argument, a one digit
2694 means an SFmode argument, and a two digit means a DFmode argument,
2695 and a three digit is not used. The low order digit is the first
2696 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2697 an SFmode argument. ??? A more sophisticated approach will be
2698 needed if MIPS_ABI != ABI_32. */
2701 /* True if the function has a prototype. */
2704 /* When a structure does not take up a full register, the argument
2705 should sometimes be shifted left so that it occupies the high part
2706 of the register. These two fields describe an array of ashl
2707 patterns for doing this. See function_arg_advance, which creates
2708 the shift patterns, and function_arg, which returns them when given
2709 a VOIDmode argument. */
2710 unsigned int num_adjusts;
2711 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2714 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2715 for a call to a function whose data type is FNTYPE.
2716 For a library call, FNTYPE is 0.
2720 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2721 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2723 /* Update the data in CUM to advance over an argument
2724 of mode MODE and data type TYPE.
2725 (TYPE is null for libcalls where that information may not be available.) */
2727 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2728 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2730 /* Determine where to put an argument to a function.
2731 Value is zero to push the argument on the stack,
2732 or a hard register in which to store the argument.
2734 MODE is the argument's machine mode.
2735 TYPE is the data type of the argument (as a tree).
2736 This is null for libcalls where that information may
2738 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2739 the preceding args and about the function being called.
2740 NAMED is nonzero if this argument is a named parameter
2741 (otherwise it is an extra parameter matching an ellipsis). */
2743 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2744 function_arg( &CUM, MODE, TYPE, NAMED)
2746 /* For an arg passed partly in registers and partly in memory,
2747 this is the number of registers used.
2748 For args passed entirely in registers or entirely in memory, zero. */
2750 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2751 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2753 /* If defined, a C expression that gives the alignment boundary, in
2754 bits, of an argument with the specified mode and type. If it is
2755 not defined, `PARM_BOUNDARY' is used for all arguments. */
2757 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2759 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2761 : TYPE_ALIGN(TYPE)) \
2762 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2764 : GET_MODE_ALIGNMENT(MODE)))
2766 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2767 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2769 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2770 (! BYTES_BIG_ENDIAN \
2772 : (((MODE) == BLKmode \
2773 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2774 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2775 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2776 && (mips_abi == ABI_32 \
2777 || mips_abi == ABI_O64 \
2778 || mips_abi == ABI_EABI \
2779 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2780 ? downward : upward))
2782 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2783 (mips_abi == ABI_EABI && (NAMED) \
2784 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2786 /* Modified version of the macro in expr.h. */
2787 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2789 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2790 || TREE_ADDRESSABLE (TYPE) \
2791 || ((MODE) == BLKmode \
2792 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2793 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2794 && 0 == (int_size_in_bytes (TYPE) \
2795 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2796 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2797 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2799 /* True if using EABI and varargs can be passed in floating-point
2800 registers. Under these conditions, we need a more complex form
2801 of va_list, which tracks GPR, FPR and stack arguments separately. */
2802 #define EABI_FLOAT_VARARGS_P \
2803 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2806 /* Say that the epilogue uses the return address register. Note that
2807 in the case of sibcalls, the values "used by the epilogue" are
2808 considered live at the start of the called function. */
2809 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2811 /* Treat LOC as a byte offset from the stack pointer and round it up
2812 to the next fully-aligned offset. */
2813 #define MIPS_STACK_ALIGN(LOC) \
2814 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2815 ? ((LOC) + 7) & ~7 \
2816 : ((LOC) + 15) & ~15)
2819 /* Define the `__builtin_va_list' type for the ABI. */
2820 #define BUILD_VA_LIST_TYPE(VALIST) \
2821 (VALIST) = mips_build_va_list ()
2823 /* Implement `va_start' for varargs and stdarg. */
2824 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2825 mips_va_start (valist, nextarg)
2827 /* Implement `va_arg'. */
2828 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2829 mips_va_arg (valist, type)
2831 /* Output assembler code to FILE to increment profiler label # LABELNO
2832 for profiling a function entry. */
2834 #define FUNCTION_PROFILER(FILE, LABELNO) \
2836 if (TARGET_MIPS16) \
2837 sorry ("mips16 function profiling"); \
2838 fprintf (FILE, "\t.set\tnoat\n"); \
2839 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2840 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2841 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2844 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2845 TARGET_64BIT ? "dsubu" : "subu", \
2846 reg_names[STACK_POINTER_REGNUM], \
2847 reg_names[STACK_POINTER_REGNUM], \
2848 Pmode == DImode ? 16 : 8); \
2850 fprintf (FILE, "\tjal\t_mcount\n"); \
2851 fprintf (FILE, "\t.set\tat\n"); \
2854 /* Define this macro if the code for function profiling should come
2855 before the function prologue. Normally, the profiling code comes
2858 /* #define PROFILE_BEFORE_PROLOGUE */
2860 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2861 the stack pointer does not matter. The value is tested only in
2862 functions that have frame pointers.
2863 No definition is equivalent to always zero. */
2865 #define EXIT_IGNORE_STACK 1
2868 /* A C statement to output, on the stream FILE, assembler code for a
2869 block of data that contains the constant parts of a trampoline.
2870 This code should not include a label--the label is taken care of
2873 #define TRAMPOLINE_TEMPLATE(STREAM) \
2875 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2876 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2877 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2878 if (ptr_mode == DImode) \
2880 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2881 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2885 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2886 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2888 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2889 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2890 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2891 if (ptr_mode == DImode) \
2893 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2894 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2898 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2899 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2903 /* A C expression for the size in bytes of the trampoline, as an
2906 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2908 /* Alignment required for trampolines, in bits. */
2910 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2912 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2913 program and data caches. */
2915 #ifndef CACHE_FLUSH_FUNC
2916 #define CACHE_FLUSH_FUNC "_flush_cache"
2919 /* A C statement to initialize the variable parts of a trampoline.
2920 ADDR is an RTX for the address of the trampoline; FNADDR is an
2921 RTX for the address of the nested function; STATIC_CHAIN is an
2922 RTX for the static chain value that should be passed to the
2923 function when it is called. */
2925 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2927 rtx func_addr, chain_addr; \
2929 func_addr = plus_constant (ADDR, 32); \
2930 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2931 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2932 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2933 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2934 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
2936 /* Flush both caches. We need to flush the data cache in case \
2937 the system has a write-back cache. */ \
2938 /* ??? Should check the return value for errors. */ \
2939 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2940 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2941 0, VOIDmode, 3, ADDR, Pmode, \
2942 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2943 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2946 /* Addressing modes, and classification of registers for them. */
2948 /* These assume that REGNO is a hard or pseudo reg number.
2949 They give nonzero only if REGNO is a hard reg of the suitable class
2950 or a pseudo reg currently allocated to a suitable hard reg.
2951 These definitions are NOT overridden anywhere. */
2953 #define BASE_REG_P(regno, mode) \
2955 ? (M16_REG_P (regno) \
2956 || (regno) == FRAME_POINTER_REGNUM \
2957 || (regno) == ARG_POINTER_REGNUM \
2958 || ((regno) == STACK_POINTER_REGNUM \
2959 && (GET_MODE_SIZE (mode) == 4 \
2960 || GET_MODE_SIZE (mode) == 8))) \
2963 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2964 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2967 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2968 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2970 #define REGNO_OK_FOR_INDEX_P(regno) 0
2971 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2972 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2974 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2975 and check its validity for a certain class.
2976 We have two alternate definitions for each of them.
2977 The usual definition accepts all pseudo regs; the other rejects them all.
2978 The symbol REG_OK_STRICT causes the latter definition to be used.
2980 Most source files want to accept pseudo regs in the hope that
2981 they will get allocated to the class that the insn wants them to be in.
2982 Some source files that are used after register allocation
2983 need to be strict. */
2985 #ifndef REG_OK_STRICT
2986 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2987 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2989 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2990 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2993 #define REG_OK_FOR_INDEX_P(X) 0
2996 /* Maximum number of registers that can appear in a valid memory address. */
2998 #define MAX_REGS_PER_ADDRESS 1
3000 /* A C compound statement with a conditional `goto LABEL;' executed
3001 if X (an RTX) is a legitimate memory address on the target
3002 machine for a memory operand of mode MODE. */
3005 #define GO_PRINTF(x) fprintf(stderr, (x))
3006 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3007 #define GO_DEBUG_RTX(x) debug_rtx(x)
3010 #define GO_PRINTF(x)
3011 #define GO_PRINTF2(x,y)
3012 #define GO_DEBUG_RTX(x)
3015 #ifdef REG_OK_STRICT
3016 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3018 if (mips_legitimate_address_p (MODE, X, 1)) \
3022 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3024 if (mips_legitimate_address_p (MODE, X, 0)) \
3029 /* Check for constness inline but use mips_legitimate_address_p
3030 to check whether a constant really is an address. */
3032 #define CONSTANT_ADDRESS_P(X) \
3033 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
3036 /* Nonzero if the constant value X is a legitimate general operand.
3037 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3039 At present, GAS doesn't understand li.[sd], so don't allow it
3040 to be generated at present. Also, the MIPS assembler does not
3041 grok li.d Infinity. */
3043 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3044 Note that the Irix 6 assembler problem may already be fixed.
3045 Note also that the GET_CODE (X) == CONST test catches the mips16
3046 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3047 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3048 ABI_64 to work together, we'll need to fix this. */
3049 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
3051 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3053 if (mips_legitimize_address (&(X), MODE)) \
3058 /* A C statement or compound statement with a conditional `goto
3059 LABEL;' executed if memory address X (an RTX) can have different
3060 meanings depending on the machine mode of the memory reference it
3063 Autoincrement and autodecrement addresses typically have
3064 mode-dependent effects because the amount of the increment or
3065 decrement is the size of the operand being addressed. Some
3066 machines have other mode-dependent addresses. Many RISC machines
3067 have no mode-dependent addresses.
3069 You may assume that ADDR is a valid address for the machine. */
3071 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3073 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3074 'the start of the function that this code is output in'. */
3076 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3077 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3078 asm_fprintf ((FILE), "%U%s", \
3079 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3081 asm_fprintf ((FILE), "%U%s", (NAME))
3083 /* The mips16 wants the constant pool to be after the function,
3084 because the PC relative load instructions use unsigned offsets. */
3086 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3088 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3089 mips_string_length = 0;
3091 /* Specify the machine mode that this machine uses
3092 for the index in the tablejump instruction.
3093 ??? Using HImode in mips16 mode can cause overflow. However, the
3094 overflow is no more likely than the overflow in a branch
3095 instruction. Large functions can currently break in both ways. */
3096 #define CASE_VECTOR_MODE \
3097 (TARGET_MIPS16 ? HImode : ptr_mode)
3099 /* Define as C expression which evaluates to nonzero if the tablejump
3100 instruction expects the table to contain offsets from the address of the
3102 Do not define this if the table should contain absolute addresses. */
3103 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3105 /* Define this as 1 if `char' should by default be signed; else as 0. */
3106 #ifndef DEFAULT_SIGNED_CHAR
3107 #define DEFAULT_SIGNED_CHAR 1
3110 /* Max number of bytes we can move from memory to memory
3111 in one reasonably fast instruction. */
3112 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3113 #define MAX_MOVE_MAX 8
3115 /* Define this macro as a C expression which is nonzero if
3116 accessing less than a word of memory (i.e. a `char' or a
3117 `short') is no faster than accessing a word of memory, i.e., if
3118 such access require more than one instruction or if there is no
3119 difference in cost between byte and (aligned) word loads.
3121 On RISC machines, it tends to generate better code to define
3122 this as 1, since it avoids making a QI or HI mode register. */
3123 #define SLOW_BYTE_ACCESS 1
3125 /* Define this to be nonzero if shift instructions ignore all but the low-order
3127 #define SHIFT_COUNT_TRUNCATED 1
3129 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3130 is done just by pretending it is already truncated. */
3131 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3132 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3135 /* Specify the machine mode that pointers have.
3136 After generation of rtl, the compiler makes no further distinction
3137 between pointers and any other objects of this machine mode. */
3140 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
3143 /* Give call MEMs SImode since it is the "most permissive" mode
3144 for both 32-bit and 64-bit targets. */
3146 #define FUNCTION_MODE SImode
3149 /* The cost of loading values from the constant pool. It should be
3150 larger than the cost of any constant we want to synthesize in-line. */
3152 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
3154 /* A C expression for the cost of moving data from a register in
3155 class FROM to one in class TO. The classes are expressed using
3156 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3157 the default; other values are interpreted relative to that.
3159 It is not required that the cost always equal 2 when FROM is the
3160 same as TO; on some machines it is expensive to move between
3161 registers if they are not general registers.
3163 If reload sees an insn consisting of a single `set' between two
3164 hard registers, and if `REGISTER_MOVE_COST' applied to their
3165 classes returns a value of 2, reload does not check to ensure
3166 that the constraints of the insn are met. Setting a cost of
3167 other than 2 will allow reload to verify that the constraints are
3168 met. You should do this if the `movM' pattern's constraints do
3169 not allow such copying. */
3171 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3172 mips_register_move_cost (MODE, FROM, TO)
3174 /* ??? Fix this to be right for the R8000. */
3175 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3176 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3177 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3179 /* Define if copies to/from condition code registers should be avoided.
3181 This is needed for the MIPS because reload_outcc is not complete;
3182 it needs to handle cases where the source is a general or another
3183 condition code register. */
3184 #define AVOID_CCMODE_COPIES
3186 /* A C expression for the cost of a branch instruction. A value of
3187 1 is the default; other values are interpreted relative to that. */
3189 /* ??? Fix this to be right for the R8000. */
3190 #define BRANCH_COST \
3192 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3195 /* If defined, modifies the length assigned to instruction INSN as a
3196 function of the context in which it is used. LENGTH is an lvalue
3197 that contains the initially computed length of the insn and should
3198 be updated with the correct length of the insn. */
3199 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3200 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3203 /* Optionally define this if you have added predicates to
3204 `MACHINE.c'. This macro is called within an initializer of an
3205 array of structures. The first field in the structure is the
3206 name of a predicate and the second field is an array of rtl
3207 codes. For each predicate, list all rtl codes that can be in
3208 expressions matched by the predicate. The list should have a
3209 trailing comma. Here is an example of two entries in the list
3210 for a typical RISC machine:
3212 #define PREDICATE_CODES \
3213 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3214 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3216 Defining this macro does not affect the generated code (however,
3217 incorrect definitions that omit an rtl code that may be matched
3218 by the predicate can cause the compiler to malfunction).
3219 Instead, it allows the table built by `genrecog' to be more
3220 compact and efficient, thus speeding up the compiler. The most
3221 important predicates to include in the list specified by this
3222 macro are thoses used in the most insn patterns. */
3224 #define PREDICATE_CODES \
3225 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3226 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3227 {"const_arith_operand", { CONST, CONST_INT }}, \
3228 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3229 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3230 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3231 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3232 {"small_int", { CONST_INT }}, \
3233 {"large_int", { CONST_INT }}, \
3234 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3235 {"const_float_1_operand", { CONST_DOUBLE }}, \
3236 {"simple_memory_operand", { MEM, SUBREG }}, \
3237 {"equality_op", { EQ, NE }}, \
3238 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3240 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3241 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3242 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
3243 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3244 SYMBOL_REF, LABEL_REF, SUBREG, \
3246 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3247 CONST_DOUBLE, CONST }}, \
3248 {"fcc_register_operand", { REG, SUBREG }}, \
3249 {"hilo_operand", { REG }}, \
3250 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
3252 /* A list of predicates that do special things with modes, and so
3253 should not elicit warnings for VOIDmode match_operand. */
3255 #define SPECIAL_MODE_PREDICATES \
3256 "pc_or_label_operand",
3258 /* Control the assembler format that we output. */
3260 /* Output to assembler file text saying following lines
3261 may contain character constants, extra white space, comments, etc. */
3264 #define ASM_APP_ON " #APP\n"
3267 /* Output to assembler file text saying following lines
3268 no longer contain unusual constructs. */
3271 #define ASM_APP_OFF " #NO_APP\n"
3274 /* How to refer to registers in assembler output.
3275 This sequence is indexed by compiler's hard-register-number (see above).
3277 In order to support the two different conventions for register names,
3278 we use the name of a table set up in mips.c, which is overwritten
3279 if -mrnames is used. */
3281 #define REGISTER_NAMES \
3283 &mips_reg_names[ 0][0], \
3284 &mips_reg_names[ 1][0], \
3285 &mips_reg_names[ 2][0], \
3286 &mips_reg_names[ 3][0], \
3287 &mips_reg_names[ 4][0], \
3288 &mips_reg_names[ 5][0], \
3289 &mips_reg_names[ 6][0], \
3290 &mips_reg_names[ 7][0], \
3291 &mips_reg_names[ 8][0], \
3292 &mips_reg_names[ 9][0], \
3293 &mips_reg_names[10][0], \
3294 &mips_reg_names[11][0], \
3295 &mips_reg_names[12][0], \
3296 &mips_reg_names[13][0], \
3297 &mips_reg_names[14][0], \
3298 &mips_reg_names[15][0], \
3299 &mips_reg_names[16][0], \
3300 &mips_reg_names[17][0], \
3301 &mips_reg_names[18][0], \
3302 &mips_reg_names[19][0], \
3303 &mips_reg_names[20][0], \
3304 &mips_reg_names[21][0], \
3305 &mips_reg_names[22][0], \
3306 &mips_reg_names[23][0], \
3307 &mips_reg_names[24][0], \
3308 &mips_reg_names[25][0], \
3309 &mips_reg_names[26][0], \
3310 &mips_reg_names[27][0], \
3311 &mips_reg_names[28][0], \
3312 &mips_reg_names[29][0], \
3313 &mips_reg_names[30][0], \
3314 &mips_reg_names[31][0], \
3315 &mips_reg_names[32][0], \
3316 &mips_reg_names[33][0], \
3317 &mips_reg_names[34][0], \
3318 &mips_reg_names[35][0], \
3319 &mips_reg_names[36][0], \
3320 &mips_reg_names[37][0], \
3321 &mips_reg_names[38][0], \
3322 &mips_reg_names[39][0], \
3323 &mips_reg_names[40][0], \
3324 &mips_reg_names[41][0], \
3325 &mips_reg_names[42][0], \
3326 &mips_reg_names[43][0], \
3327 &mips_reg_names[44][0], \
3328 &mips_reg_names[45][0], \
3329 &mips_reg_names[46][0], \
3330 &mips_reg_names[47][0], \
3331 &mips_reg_names[48][0], \
3332 &mips_reg_names[49][0], \
3333 &mips_reg_names[50][0], \
3334 &mips_reg_names[51][0], \
3335 &mips_reg_names[52][0], \
3336 &mips_reg_names[53][0], \
3337 &mips_reg_names[54][0], \
3338 &mips_reg_names[55][0], \
3339 &mips_reg_names[56][0], \
3340 &mips_reg_names[57][0], \
3341 &mips_reg_names[58][0], \
3342 &mips_reg_names[59][0], \
3343 &mips_reg_names[60][0], \
3344 &mips_reg_names[61][0], \
3345 &mips_reg_names[62][0], \
3346 &mips_reg_names[63][0], \
3347 &mips_reg_names[64][0], \
3348 &mips_reg_names[65][0], \
3349 &mips_reg_names[66][0], \
3350 &mips_reg_names[67][0], \
3351 &mips_reg_names[68][0], \
3352 &mips_reg_names[69][0], \
3353 &mips_reg_names[70][0], \
3354 &mips_reg_names[71][0], \
3355 &mips_reg_names[72][0], \
3356 &mips_reg_names[73][0], \
3357 &mips_reg_names[74][0], \
3358 &mips_reg_names[75][0], \
3359 &mips_reg_names[76][0], \
3360 &mips_reg_names[77][0], \
3361 &mips_reg_names[78][0], \
3362 &mips_reg_names[79][0], \
3363 &mips_reg_names[80][0], \
3364 &mips_reg_names[81][0], \
3365 &mips_reg_names[82][0], \
3366 &mips_reg_names[83][0], \
3367 &mips_reg_names[84][0], \
3368 &mips_reg_names[85][0], \
3369 &mips_reg_names[86][0], \
3370 &mips_reg_names[87][0], \
3371 &mips_reg_names[88][0], \
3372 &mips_reg_names[89][0], \
3373 &mips_reg_names[90][0], \
3374 &mips_reg_names[91][0], \
3375 &mips_reg_names[92][0], \
3376 &mips_reg_names[93][0], \
3377 &mips_reg_names[94][0], \
3378 &mips_reg_names[95][0], \
3379 &mips_reg_names[96][0], \
3380 &mips_reg_names[97][0], \
3381 &mips_reg_names[98][0], \
3382 &mips_reg_names[99][0], \
3383 &mips_reg_names[100][0], \
3384 &mips_reg_names[101][0], \
3385 &mips_reg_names[102][0], \
3386 &mips_reg_names[103][0], \
3387 &mips_reg_names[104][0], \
3388 &mips_reg_names[105][0], \
3389 &mips_reg_names[106][0], \
3390 &mips_reg_names[107][0], \
3391 &mips_reg_names[108][0], \
3392 &mips_reg_names[109][0], \
3393 &mips_reg_names[110][0], \
3394 &mips_reg_names[111][0], \
3395 &mips_reg_names[112][0], \
3396 &mips_reg_names[113][0], \
3397 &mips_reg_names[114][0], \
3398 &mips_reg_names[115][0], \
3399 &mips_reg_names[116][0], \
3400 &mips_reg_names[117][0], \
3401 &mips_reg_names[118][0], \
3402 &mips_reg_names[119][0], \
3403 &mips_reg_names[120][0], \
3404 &mips_reg_names[121][0], \
3405 &mips_reg_names[122][0], \
3406 &mips_reg_names[123][0], \
3407 &mips_reg_names[124][0], \
3408 &mips_reg_names[125][0], \
3409 &mips_reg_names[126][0], \
3410 &mips_reg_names[127][0], \
3411 &mips_reg_names[128][0], \
3412 &mips_reg_names[129][0], \
3413 &mips_reg_names[130][0], \
3414 &mips_reg_names[131][0], \
3415 &mips_reg_names[132][0], \
3416 &mips_reg_names[133][0], \
3417 &mips_reg_names[134][0], \
3418 &mips_reg_names[135][0], \
3419 &mips_reg_names[136][0], \
3420 &mips_reg_names[137][0], \
3421 &mips_reg_names[138][0], \
3422 &mips_reg_names[139][0], \
3423 &mips_reg_names[140][0], \
3424 &mips_reg_names[141][0], \
3425 &mips_reg_names[142][0], \
3426 &mips_reg_names[143][0], \
3427 &mips_reg_names[144][0], \
3428 &mips_reg_names[145][0], \
3429 &mips_reg_names[146][0], \
3430 &mips_reg_names[147][0], \
3431 &mips_reg_names[148][0], \
3432 &mips_reg_names[149][0], \
3433 &mips_reg_names[150][0], \
3434 &mips_reg_names[151][0], \
3435 &mips_reg_names[152][0], \
3436 &mips_reg_names[153][0], \
3437 &mips_reg_names[154][0], \
3438 &mips_reg_names[155][0], \
3439 &mips_reg_names[156][0], \
3440 &mips_reg_names[157][0], \
3441 &mips_reg_names[158][0], \
3442 &mips_reg_names[159][0], \
3443 &mips_reg_names[160][0], \
3444 &mips_reg_names[161][0], \
3445 &mips_reg_names[162][0], \
3446 &mips_reg_names[163][0], \
3447 &mips_reg_names[164][0], \
3448 &mips_reg_names[165][0], \
3449 &mips_reg_names[166][0], \
3450 &mips_reg_names[167][0], \
3451 &mips_reg_names[168][0], \
3452 &mips_reg_names[169][0], \
3453 &mips_reg_names[170][0], \
3454 &mips_reg_names[171][0], \
3455 &mips_reg_names[172][0], \
3456 &mips_reg_names[173][0], \
3457 &mips_reg_names[174][0], \
3458 &mips_reg_names[175][0] \
3461 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3462 So define this for it. */
3463 #define DEBUG_REGISTER_NAMES \
3465 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3466 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3467 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3468 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3469 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3470 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3471 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3472 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3473 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3474 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3475 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3476 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3477 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3478 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3479 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3480 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3481 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3482 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3483 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3484 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3485 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3486 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3489 /* If defined, a C initializer for an array of structures
3490 containing a name and a register number. This macro defines
3491 additional names for hard registers, thus allowing the `asm'
3492 option in declarations to refer to registers using alternate
3495 We define both names for the integer registers here. */
3497 #define ADDITIONAL_REGISTER_NAMES \
3499 { "$0", 0 + GP_REG_FIRST }, \
3500 { "$1", 1 + GP_REG_FIRST }, \
3501 { "$2", 2 + GP_REG_FIRST }, \
3502 { "$3", 3 + GP_REG_FIRST }, \
3503 { "$4", 4 + GP_REG_FIRST }, \
3504 { "$5", 5 + GP_REG_FIRST }, \
3505 { "$6", 6 + GP_REG_FIRST }, \
3506 { "$7", 7 + GP_REG_FIRST }, \
3507 { "$8", 8 + GP_REG_FIRST }, \
3508 { "$9", 9 + GP_REG_FIRST }, \
3509 { "$10", 10 + GP_REG_FIRST }, \
3510 { "$11", 11 + GP_REG_FIRST }, \
3511 { "$12", 12 + GP_REG_FIRST }, \
3512 { "$13", 13 + GP_REG_FIRST }, \
3513 { "$14", 14 + GP_REG_FIRST }, \
3514 { "$15", 15 + GP_REG_FIRST }, \
3515 { "$16", 16 + GP_REG_FIRST }, \
3516 { "$17", 17 + GP_REG_FIRST }, \
3517 { "$18", 18 + GP_REG_FIRST }, \
3518 { "$19", 19 + GP_REG_FIRST }, \
3519 { "$20", 20 + GP_REG_FIRST }, \
3520 { "$21", 21 + GP_REG_FIRST }, \
3521 { "$22", 22 + GP_REG_FIRST }, \
3522 { "$23", 23 + GP_REG_FIRST }, \
3523 { "$24", 24 + GP_REG_FIRST }, \
3524 { "$25", 25 + GP_REG_FIRST }, \
3525 { "$26", 26 + GP_REG_FIRST }, \
3526 { "$27", 27 + GP_REG_FIRST }, \
3527 { "$28", 28 + GP_REG_FIRST }, \
3528 { "$29", 29 + GP_REG_FIRST }, \
3529 { "$30", 30 + GP_REG_FIRST }, \
3530 { "$31", 31 + GP_REG_FIRST }, \
3531 { "$sp", 29 + GP_REG_FIRST }, \
3532 { "$fp", 30 + GP_REG_FIRST }, \
3533 { "at", 1 + GP_REG_FIRST }, \
3534 { "v0", 2 + GP_REG_FIRST }, \
3535 { "v1", 3 + GP_REG_FIRST }, \
3536 { "a0", 4 + GP_REG_FIRST }, \
3537 { "a1", 5 + GP_REG_FIRST }, \
3538 { "a2", 6 + GP_REG_FIRST }, \
3539 { "a3", 7 + GP_REG_FIRST }, \
3540 { "t0", 8 + GP_REG_FIRST }, \
3541 { "t1", 9 + GP_REG_FIRST }, \
3542 { "t2", 10 + GP_REG_FIRST }, \
3543 { "t3", 11 + GP_REG_FIRST }, \
3544 { "t4", 12 + GP_REG_FIRST }, \
3545 { "t5", 13 + GP_REG_FIRST }, \
3546 { "t6", 14 + GP_REG_FIRST }, \
3547 { "t7", 15 + GP_REG_FIRST }, \
3548 { "s0", 16 + GP_REG_FIRST }, \
3549 { "s1", 17 + GP_REG_FIRST }, \
3550 { "s2", 18 + GP_REG_FIRST }, \
3551 { "s3", 19 + GP_REG_FIRST }, \
3552 { "s4", 20 + GP_REG_FIRST }, \
3553 { "s5", 21 + GP_REG_FIRST }, \
3554 { "s6", 22 + GP_REG_FIRST }, \
3555 { "s7", 23 + GP_REG_FIRST }, \
3556 { "t8", 24 + GP_REG_FIRST }, \
3557 { "t9", 25 + GP_REG_FIRST }, \
3558 { "k0", 26 + GP_REG_FIRST }, \
3559 { "k1", 27 + GP_REG_FIRST }, \
3560 { "gp", 28 + GP_REG_FIRST }, \
3561 { "sp", 29 + GP_REG_FIRST }, \
3562 { "fp", 30 + GP_REG_FIRST }, \
3563 { "ra", 31 + GP_REG_FIRST }, \
3564 { "$sp", 29 + GP_REG_FIRST }, \
3565 { "$fp", 30 + GP_REG_FIRST } \
3566 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3569 /* This is meant to be redefined in the host dependent files. It is a
3570 set of alternative names and regnums for mips coprocessors. */
3572 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3574 /* A C compound statement to output to stdio stream STREAM the
3575 assembler syntax for an instruction operand X. X is an RTL
3578 CODE is a value that can be used to specify one of several ways
3579 of printing the operand. It is used when identical operands
3580 must be printed differently depending on the context. CODE
3581 comes from the `%' specification that was used to request
3582 printing of the operand. If the specification was just `%DIGIT'
3583 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3584 is the ASCII code for LTR.
3586 If X is a register, this macro should print the register's name.
3587 The names can be found in an array `reg_names' whose type is
3588 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3590 When the machine description has a specification `%PUNCT' (a `%'
3591 followed by a punctuation character), this macro is called with
3592 a null pointer for X and the punctuation character for CODE.
3594 See mips.c for the MIPS specific codes. */
3596 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3598 /* A C expression which evaluates to true if CODE is a valid
3599 punctuation character for use in the `PRINT_OPERAND' macro. If
3600 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3601 punctuation characters (except for the standard one, `%') are
3602 used in this way. */
3604 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3606 /* A C compound statement to output to stdio stream STREAM the
3607 assembler syntax for an instruction operand that is a memory
3608 reference whose address is ADDR. ADDR is an RTL expression. */
3610 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3613 /* A C statement, to be executed after all slot-filler instructions
3614 have been output. If necessary, call `dbr_sequence_length' to
3615 determine the number of slots filled in a sequence (zero if not
3616 currently outputting a sequence), to decide how many no-ops to
3617 output, or whatever.
3619 Don't define this macro if it has nothing to do, but it is
3620 helpful in reading assembly output if the extent of the delay
3621 sequence is made explicit (e.g. with white space).
3623 Note that output routines for instructions with delay slots must
3624 be prepared to deal with not being output as part of a sequence
3625 (i.e. when the scheduling pass is not run, or when no slot
3626 fillers could be found.) The variable `final_sequence' is null
3627 when not processing a sequence, otherwise it contains the
3628 `sequence' rtx being output. */
3630 #define DBR_OUTPUT_SEQEND(STREAM) \
3633 if (set_nomacro > 0 && --set_nomacro == 0) \
3634 fputs ("\t.set\tmacro\n", STREAM); \
3636 if (set_noreorder > 0 && --set_noreorder == 0) \
3637 fputs ("\t.set\treorder\n", STREAM); \
3639 fputs ("\n", STREAM); \
3644 /* How to tell the debugger about changes of source files. Note, the
3645 mips ECOFF format cannot deal with changes of files inside of
3646 functions, which means the output of parser generators like bison
3647 is generally not debuggable without using the -l switch. Lose,
3648 lose, lose. Silicon graphics seems to want all .file's hardwired
3651 #ifndef SET_FILE_NUMBER
3652 #define SET_FILE_NUMBER() ++num_source_filenames
3655 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3656 mips_output_filename (STREAM, NAME)
3658 /* This is defined so that it can be overridden in iris6.h. */
3659 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3662 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3663 output_quoted_string (STREAM, NAME); \
3664 fputs ("\n", STREAM); \
3668 /* This is how to output a note the debugger telling it the line number
3669 to which the following sequence of instructions corresponds.
3670 Silicon graphics puts a label after each .loc. */
3672 #ifndef LABEL_AFTER_LOC
3673 #define LABEL_AFTER_LOC(STREAM)
3676 #ifndef ASM_OUTPUT_SOURCE_LINE
3677 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3678 mips_output_lineno (STREAM, LINE)
3681 /* The MIPS implementation uses some labels for its own purpose. The
3682 following lists what labels are created, and are all formed by the
3683 pattern $L[a-z].*. The machine independent portion of GCC creates
3684 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3686 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3687 $Lb[0-9]+ Begin blocks for MIPS debug support
3688 $Lc[0-9]+ Label for use in s<xx> operation.
3689 $Le[0-9]+ End blocks for MIPS debug support */
3691 /* A C statement (sans semicolon) to output to the stdio stream
3692 STREAM any text necessary for declaring the name NAME of an
3693 initialized variable which is being defined. This macro must
3694 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3695 The argument DECL is the `VAR_DECL' tree node representing the
3698 If this macro is not defined, then the variable name is defined
3699 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3701 #undef ASM_DECLARE_OBJECT_NAME
3702 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3705 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3709 /* Globalizing directive for a label. */
3710 #define GLOBAL_ASM_OP "\t.globl\t"
3712 /* This says how to define a global common symbol. */
3714 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3716 /* If the target wants uninitialized const declarations in \
3717 .rdata then don't put them in .comm */ \
3718 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3719 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3720 && (DECL_INITIAL (DECL) == 0 \
3721 || DECL_INITIAL (DECL) == error_mark_node)) \
3723 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3724 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3726 readonly_data_section (); \
3727 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3728 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3732 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3737 /* This says how to define a local common symbol (ie, not visible to
3740 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3741 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3744 /* This says how to output an external. It would be possible not to
3745 output anything and let undefined symbol become external. However
3746 the assembler uses length information on externals to allocate in
3747 data/sdata bss/sbss, thereby saving exec time. */
3749 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3750 mips_output_external(STREAM,DECL,NAME)
3753 /* This is how to declare a function name. The actual work of
3754 emitting the label is moved to function_prologue, so that we can
3755 get the line number correctly emitted before the .ent directive,
3756 and after any .file directives. Define as empty so that the function
3757 is not declared before the .ent directive elsewhere. */
3759 #undef ASM_DECLARE_FUNCTION_NAME
3760 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3762 /* This is how to store into the string LABEL
3763 the symbol_ref name of an internal numbered label where
3764 PREFIX is the class of label and NUM is the number within the class.
3765 This is suitable for output with `assemble_name'. */
3767 #undef ASM_GENERATE_INTERNAL_LABEL
3768 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3769 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3771 /* This is how to output an element of a case-vector that is absolute. */
3773 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3774 fprintf (STREAM, "\t%s\t%sL%d\n", \
3775 ptr_mode == DImode ? ".dword" : ".word", \
3776 LOCAL_LABEL_PREFIX, \
3779 /* This is how to output an element of a case-vector that is relative.
3780 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3781 TARGET_EMBEDDED_PIC). */
3783 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3785 if (TARGET_MIPS16) \
3786 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3787 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3788 else if (TARGET_EMBEDDED_PIC) \
3789 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3790 ptr_mode == DImode ? ".dword" : ".word", \
3791 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3792 else if (TARGET_GPWORD) \
3793 fprintf (STREAM, "\t%s\t%sL%d\n", \
3794 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3795 LOCAL_LABEL_PREFIX, VALUE); \
3797 fprintf (STREAM, "\t%s\t%sL%d\n", \
3798 ptr_mode == DImode ? ".dword" : ".word", \
3799 LOCAL_LABEL_PREFIX, VALUE); \
3802 /* When generating embedded PIC or mips16 code we want to put the jump
3803 table in the .text section. In all other cases, we want to put the
3804 jump table in the .rdata section. Unfortunately, we can't use
3805 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3806 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3807 section if appropriate. */
3808 #undef ASM_OUTPUT_CASE_LABEL
3809 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3811 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3812 function_section (current_function_decl); \
3813 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3816 /* This is how to output an assembler line
3817 that says to advance the location counter
3818 to a multiple of 2**LOG bytes. */
3820 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3821 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3823 /* This is how to output an assembler line to advance the location
3824 counter by SIZE bytes. */
3826 #undef ASM_OUTPUT_SKIP
3827 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3828 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3830 /* This is how to output a string. */
3831 #undef ASM_OUTPUT_ASCII
3832 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3833 mips_output_ascii (STREAM, STRING, LEN)
3835 /* Output #ident as a in the read-only data section. */
3836 #undef ASM_OUTPUT_IDENT
3837 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3839 const char *p = STRING; \
3840 int size = strlen (p) + 1; \
3841 readonly_data_section (); \
3842 assemble_string (p, size); \
3845 /* Default to -G 8 */
3846 #ifndef MIPS_DEFAULT_GVALUE
3847 #define MIPS_DEFAULT_GVALUE 8
3850 /* Define the strings to put out for each section in the object file. */
3851 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3852 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3853 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3855 #undef READONLY_DATA_SECTION_ASM_OP
3856 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3858 /* Given a decl node or constant node, choose the section to output it in
3859 and select that section. */
3861 #undef TARGET_ASM_SELECT_SECTION
3862 #define TARGET_ASM_SELECT_SECTION mips_select_section
3864 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3867 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3868 TARGET_64BIT ? "dsubu" : "subu", \
3869 reg_names[STACK_POINTER_REGNUM], \
3870 reg_names[STACK_POINTER_REGNUM], \
3871 TARGET_64BIT ? "sd" : "sw", \
3873 reg_names[STACK_POINTER_REGNUM]); \
3877 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3880 if (! set_noreorder) \
3881 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3883 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3884 TARGET_64BIT ? "ld" : "lw", \
3886 reg_names[STACK_POINTER_REGNUM], \
3887 TARGET_64BIT ? "daddu" : "addu", \
3888 reg_names[STACK_POINTER_REGNUM], \
3889 reg_names[STACK_POINTER_REGNUM]); \
3891 if (! set_noreorder) \
3892 fprintf (STREAM, "\t.set\treorder\n"); \
3896 /* How to start an assembler comment.
3897 The leading space is important (the mips native assembler requires it). */
3898 #ifndef ASM_COMMENT_START
3899 #define ASM_COMMENT_START " #"
3903 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3904 and mips-tdump.c to print them out.
3906 These must match the corresponding definitions in gdb/mipsread.c.
3907 Unfortunately, gcc and gdb do not currently share any directories. */
3909 #define CODE_MASK 0x8F300
3910 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3911 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3912 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3915 /* Default definitions for size_t and ptrdiff_t. We must override the
3916 definitions from ../svr4.h on mips-*-linux-gnu. */
3919 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3922 #ifndef PTRDIFF_TYPE
3923 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3926 /* See mips_expand_prologue's use of loadgp for when this should be
3929 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3930 && mips_abi != ABI_32 \
3931 && mips_abi != ABI_O64)
3933 /* We need to use a special set of functions to handle hard floating
3934 point code in mips16 mode. */
3936 #ifndef INIT_SUBTARGET_OPTABS
3937 #define INIT_SUBTARGET_OPTABS
3940 #define INIT_TARGET_OPTABS \
3943 if (! TARGET_MIPS16 || ! mips16_hard_float) \
3944 INIT_SUBTARGET_OPTABS; \
3947 add_optab->handlers[(int) SFmode].libfunc = \
3948 init_one_libfunc ("__mips16_addsf3"); \
3949 sub_optab->handlers[(int) SFmode].libfunc = \
3950 init_one_libfunc ("__mips16_subsf3"); \
3951 smul_optab->handlers[(int) SFmode].libfunc = \
3952 init_one_libfunc ("__mips16_mulsf3"); \
3953 sdiv_optab->handlers[(int) SFmode].libfunc = \
3954 init_one_libfunc ("__mips16_divsf3"); \
3956 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
3957 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
3958 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
3959 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
3960 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
3961 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
3963 floatsisf_libfunc = \
3964 init_one_libfunc ("__mips16_floatsisf"); \
3966 init_one_libfunc ("__mips16_fixsfsi"); \
3968 if (TARGET_DOUBLE_FLOAT) \
3970 add_optab->handlers[(int) DFmode].libfunc = \
3971 init_one_libfunc ("__mips16_adddf3"); \
3972 sub_optab->handlers[(int) DFmode].libfunc = \
3973 init_one_libfunc ("__mips16_subdf3"); \
3974 smul_optab->handlers[(int) DFmode].libfunc = \
3975 init_one_libfunc ("__mips16_muldf3"); \
3976 sdiv_optab->handlers[(int) DFmode].libfunc = \
3977 init_one_libfunc ("__mips16_divdf3"); \
3979 extendsfdf2_libfunc = \
3980 init_one_libfunc ("__mips16_extendsfdf2"); \
3981 truncdfsf2_libfunc = \
3982 init_one_libfunc ("__mips16_truncdfsf2"); \
3985 init_one_libfunc ("__mips16_eqdf2"); \
3987 init_one_libfunc ("__mips16_nedf2"); \
3989 init_one_libfunc ("__mips16_gtdf2"); \
3991 init_one_libfunc ("__mips16_gedf2"); \
3993 init_one_libfunc ("__mips16_ltdf2"); \
3995 init_one_libfunc ("__mips16_ledf2"); \
3997 floatsidf_libfunc = \
3998 init_one_libfunc ("__mips16_floatsidf"); \
4000 init_one_libfunc ("__mips16_fixdfsi"); \
4006 #define DFMODE_NAN \
4007 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4008 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4009 #define SFMODE_NAN \
4010 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4011 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4013 /* Generate calls to memcpy, etc., not bcopy, etc. */
4014 #define TARGET_MEM_FUNCTIONS
4017 /* Since the bits of the _init and _fini function is spread across
4018 many object files, each potentially with its own GP, we must assume
4019 we need to load our GP. We don't preserve $gp or $ra, since each
4020 init/fini chunk is supposed to initialize $gp, and crti/crtn
4021 already take care of preserving $ra and, when appropriate, $gp. */
4022 #if _MIPS_SIM == _MIPS_SIM_ABI32
4023 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4024 asm (SECTION_OP "\n\
4030 jal " USER_LABEL_PREFIX #FUNC "\n\
4031 " TEXT_SECTION_ASM_OP);
4032 #endif /* Switch to #elif when we're no longer limited by K&R C. */
4033 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4034 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4035 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4036 asm (SECTION_OP "\n\
4041 .cpsetup $31, $2, 1b\n\
4042 jal " USER_LABEL_PREFIX #FUNC "\n\
4043 " TEXT_SECTION_ASM_OP);