1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
137 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
138 extern int mips_isa; /* architectural level */
139 extern int mips16; /* whether generating mips16 code */
140 extern int mips16_hard_float; /* mips16 without -msoft-float */
141 extern int mips_entry; /* generate entry/exit for mips16 */
142 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
143 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
144 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
145 extern const char *mips_entry_string; /* for -mentry */
146 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
147 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
148 extern int mips_split_addresses; /* perform high/lo_sum support */
149 extern int dslots_load_total; /* total # load related delay slots */
150 extern int dslots_load_filled; /* # filled load delay slots */
151 extern int dslots_jump_total; /* total # jump related delay slots */
152 extern int dslots_jump_filled; /* # filled jump delay slots */
153 extern int dslots_number_nops; /* # of nops needed by previous insn */
154 extern int num_refs[3]; /* # 1/2/3 word references */
155 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
156 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
157 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
158 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
159 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
160 extern int mips_string_length; /* length of strings for mips16 */
161 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
163 /* Functions to change what output section we are using. */
164 extern void rdata_section PARAMS ((void));
165 extern void sdata_section PARAMS ((void));
166 extern void sbss_section PARAMS ((void));
168 /* Stubs for half-pic support if not OSF/1 reference platform. */
171 #define HALF_PIC_P() 0
172 #define HALF_PIC_NUMBER_PTRS 0
173 #define HALF_PIC_NUMBER_REFS 0
174 #define HALF_PIC_ENCODE(DECL)
175 #define HALF_PIC_DECLARE(NAME)
176 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
177 #define HALF_PIC_ADDRESS_P(X) 0
178 #define HALF_PIC_PTR(X) X
179 #define HALF_PIC_FINISH(STREAM)
183 /* Run-time compilation parameters selecting different hardware subsets. */
185 /* Macros used in the machine description to test the flags. */
187 /* Bits for real switches */
188 #define MASK_INT64 0x00000001 /* ints are 64 bits */
189 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
190 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
191 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
192 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
193 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
194 #define MASK_STATS 0x00000040 /* print statistics to stderr */
195 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
196 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
197 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
198 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
199 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
200 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
201 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
202 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
203 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
204 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
205 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
206 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
207 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
208 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
209 #define MASK_MIPS16 0x00200000 /* Generate mips16 code */
210 #define MASK_NO_CHECK_ZERO_DIV \
211 0x00400000 /* divide by zero checking */
212 #define MASK_CHECK_RANGE_DIV \
213 0x00800000 /* divide result range checking */
214 #define MASK_UNINIT_CONST_IN_RODATA \
215 0x01000000 /* Store uninitialized
218 /* Debug switches, not documented */
219 #define MASK_DEBUG 0 /* unused */
220 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
221 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
222 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
223 #define MASK_DEBUG_D 0 /* don't do define_split's */
224 #define MASK_DEBUG_E 0 /* function_arg debug */
225 #define MASK_DEBUG_F 0 /* ??? */
226 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
227 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
228 #define MASK_DEBUG_I 0 /* unused */
230 /* Dummy switches used only in specs */
231 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
233 /* r4000 64 bit sizes */
234 #define TARGET_INT64 (target_flags & MASK_INT64)
235 #define TARGET_LONG64 (target_flags & MASK_LONG64)
236 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
237 #define TARGET_64BIT (target_flags & MASK_64BIT)
239 /* Mips vs. GNU linker */
240 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
242 /* generate mips 3900 insns */
243 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
245 /* Mips vs. GNU assembler */
246 #define TARGET_GAS (target_flags & MASK_GAS)
247 #define TARGET_MIPS_AS (!TARGET_GAS)
250 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
251 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
252 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
253 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
254 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
255 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
256 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
257 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
258 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
259 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
261 /* Reg. Naming in .s ($21 vs. $a0) */
262 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
264 /* Optimize for Sdata/Sbss */
265 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
267 /* print program statistics */
268 #define TARGET_STATS (target_flags & MASK_STATS)
270 /* call memcpy instead of inline code */
271 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
273 /* .abicalls, etc from Pyramid V.4 */
274 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
276 /* OSF pic references to externs */
277 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
279 /* software floating point */
280 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
281 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
283 /* always call through a register */
284 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
286 /* generate embedded PIC code;
288 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
290 /* for embedded systems, optimize for
291 reduced RAM space instead of for
293 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
295 /* always store uninitialized const
296 variables in rodata, requires
297 TARGET_EMBEDDED_DATA. */
298 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
300 /* generate big endian code. */
301 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
303 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
304 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
306 #define TARGET_MAD (target_flags & MASK_MAD)
308 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
310 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
311 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
313 /* This is true if we must enable the assembly language file switching
316 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
318 /* We must disable the function end stabs when doing the file switching trick,
319 because the Lscope stabs end up in the wrong place, making it impossible
320 to debug the resulting code. */
321 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
323 /* Generate mips16 code */
324 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
326 /* Macro to define tables used to set the flags.
327 This is a list in braces of pairs in braces,
328 each pair being { "NAME", VALUE }
329 where VALUE is the bits to set or minus the bits to clear.
330 An empty string NAME is used to identify the default VALUE. */
332 #define TARGET_SWITCHES \
335 N_("No default crt0.o") }, \
336 {"int64", MASK_INT64 | MASK_LONG64, \
337 N_("Use 64-bit int type")}, \
338 {"long64", MASK_LONG64, \
339 N_("Use 64-bit long type")}, \
340 {"long32", -(MASK_LONG64 | MASK_INT64), \
341 N_("Use 32-bit long type")}, \
342 {"split-addresses", MASK_SPLIT_ADDR, \
343 N_("Optimize lui/addiu address loads")}, \
344 {"no-split-addresses", -MASK_SPLIT_ADDR, \
345 N_("Don't optimize lui/addiu address loads")}, \
346 {"mips-as", -MASK_GAS, \
347 N_("Use MIPS as")}, \
350 {"rnames", MASK_NAME_REGS, \
351 N_("Use symbolic register names")}, \
352 {"no-rnames", -MASK_NAME_REGS, \
353 N_("Don't use symbolic register names")}, \
354 {"gpOPT", MASK_GPOPT, \
355 N_("Use GP relative sdata/sbss sections")}, \
356 {"gpopt", MASK_GPOPT, \
357 N_("Use GP relative sdata/sbss sections")}, \
358 {"no-gpOPT", -MASK_GPOPT, \
359 N_("Don't use GP relative sdata/sbss sections")}, \
360 {"no-gpopt", -MASK_GPOPT, \
361 N_("Don't use GP relative sdata/sbss sections")}, \
362 {"stats", MASK_STATS, \
363 N_("Output compiler statistics")}, \
364 {"no-stats", -MASK_STATS, \
365 N_("Don't output compiler statistics")}, \
366 {"memcpy", MASK_MEMCPY, \
367 N_("Don't optimize block moves")}, \
368 {"no-memcpy", -MASK_MEMCPY, \
369 N_("Optimize block moves")}, \
370 {"mips-tfile", MASK_MIPS_TFILE, \
371 N_("Use mips-tfile asm postpass")}, \
372 {"no-mips-tfile", -MASK_MIPS_TFILE, \
373 N_("Don't use mips-tfile asm postpass")}, \
374 {"soft-float", MASK_SOFT_FLOAT, \
375 N_("Use software floating point")}, \
376 {"hard-float", -MASK_SOFT_FLOAT, \
377 N_("Use hardware floating point")}, \
378 {"fp64", MASK_FLOAT64, \
379 N_("Use 64-bit FP registers")}, \
380 {"fp32", -MASK_FLOAT64, \
381 N_("Use 32-bit FP registers")}, \
382 {"gp64", MASK_64BIT, \
383 N_("Use 64-bit general registers")}, \
384 {"gp32", -MASK_64BIT, \
385 N_("Use 32-bit general registers")}, \
386 {"abicalls", MASK_ABICALLS, \
387 N_("Use Irix PIC")}, \
388 {"no-abicalls", -MASK_ABICALLS, \
389 N_("Don't use Irix PIC")}, \
390 {"half-pic", MASK_HALF_PIC, \
391 N_("Use OSF PIC")}, \
392 {"no-half-pic", -MASK_HALF_PIC, \
393 N_("Don't use OSF PIC")}, \
394 {"long-calls", MASK_LONG_CALLS, \
395 N_("Use indirect calls")}, \
396 {"no-long-calls", -MASK_LONG_CALLS, \
397 N_("Don't use indirect calls")}, \
398 {"embedded-pic", MASK_EMBEDDED_PIC, \
399 N_("Use embedded PIC")}, \
400 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
401 N_("Don't use embedded PIC")}, \
402 {"embedded-data", MASK_EMBEDDED_DATA, \
403 N_("Use ROM instead of RAM")}, \
404 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
405 N_("Don't use ROM instead of RAM")}, \
406 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
407 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
408 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
409 N_("Don't put uninitialized constants in ROM")}, \
410 {"eb", MASK_BIG_ENDIAN, \
411 N_("Use big-endian byte order")}, \
412 {"el", -MASK_BIG_ENDIAN, \
413 N_("Use little-endian byte order")}, \
414 {"single-float", MASK_SINGLE_FLOAT, \
415 N_("Use single (32-bit) FP only")}, \
416 {"double-float", -MASK_SINGLE_FLOAT, \
417 N_("Don't use single (32-bit) FP only")}, \
419 N_("Use multiply accumulate")}, \
420 {"no-mad", -MASK_MAD, \
421 N_("Don't use multiply accumulate")}, \
422 {"fix4300", MASK_4300_MUL_FIX, \
423 N_("Work around early 4300 hardware bug")}, \
424 {"no-fix4300", -MASK_4300_MUL_FIX, \
425 N_("Don't work around early 4300 hardware bug")}, \
426 {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
427 N_("Optimize for 4650")}, \
428 {"3900", MASK_MIPS3900, \
429 N_("Optimize for 3900")}, \
430 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
431 N_("Trap on integer divide by zero")}, \
432 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
433 N_("Don't trap on integer divide by zero")}, \
434 {"check-range-division",MASK_CHECK_RANGE_DIV, \
435 N_("Trap on integer divide overflow")}, \
436 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
437 N_("Don't trap on integer divide overflow")}, \
438 {"debug", MASK_DEBUG, \
440 {"debuga", MASK_DEBUG_A, \
442 {"debugb", MASK_DEBUG_B, \
444 {"debugc", MASK_DEBUG_C, \
446 {"debugd", MASK_DEBUG_D, \
448 {"debuge", MASK_DEBUG_E, \
450 {"debugf", MASK_DEBUG_F, \
452 {"debugg", MASK_DEBUG_G, \
454 {"debugh", MASK_DEBUG_H, \
456 {"debugi", MASK_DEBUG_I, \
458 {"", (TARGET_DEFAULT \
459 | TARGET_CPU_DEFAULT \
460 | TARGET_ENDIAN_DEFAULT), \
464 /* Default target_flags if no switches are specified */
466 #ifndef TARGET_DEFAULT
467 #define TARGET_DEFAULT 0
470 #ifndef TARGET_CPU_DEFAULT
471 #define TARGET_CPU_DEFAULT 0
474 #ifndef TARGET_ENDIAN_DEFAULT
476 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
478 #define TARGET_ENDIAN_DEFAULT 0
482 #ifndef MIPS_ISA_DEFAULT
483 #define MIPS_ISA_DEFAULT 1
488 /* Make this compile time constant for libgcc2 */
490 #define TARGET_64BIT 1
492 #define TARGET_64BIT 0
494 #endif /* IN_LIBGCC2 */
496 #ifndef MULTILIB_ENDIAN_DEFAULT
497 #if TARGET_ENDIAN_DEFAULT == 0
498 #define MULTILIB_ENDIAN_DEFAULT "EL"
500 #define MULTILIB_ENDIAN_DEFAULT "EB"
504 #ifndef MULTILIB_ISA_DEFAULT
505 #if MIPS_ISA_DEFAULT == 1
506 #define MULTILIB_ISA_DEFAULT "mips1"
507 #elif MIPS_ISA_DEFAULT == 2
508 #define MULTILIB_ISA_DEFAULT "mips2"
509 #elif MIPS_ISA_DEFAULT == 3
510 #define MULTILIB_ISA_DEFAULT "mips3"
511 #elif MIPS_ISA_DEFAULT == 4
512 #define MULTILIB_ISA_DEFAULT "mips4"
514 #define MULTILIB_ISA_DEFAULT "mips1"
518 #ifndef MULTILIB_DEFAULTS
519 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
522 /* We must pass -EL to the linker by default for little endian embedded
523 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
524 linker will default to using big-endian output files. The OUTPUT_FORMAT
525 line must be in the linker script, otherwise -EB/-EL will not work. */
528 #if TARGET_ENDIAN_DEFAULT == 0
529 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EL} %{EB}"
531 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EB} %{EL}"
535 /* This macro is similar to `TARGET_SWITCHES' but defines names of
536 command options that have values. Its definition is an
537 initializer with a subgrouping for each command option.
539 Each subgrouping contains a string constant, that defines the
540 fixed part of the option name, and the address of a variable.
541 The variable, type `char *', is set to the variable part of the
542 given option if the fixed part matches. The actual option name
543 is made by appending `-m' to the specified name.
545 Here is an example which defines `-mshort-data-NUMBER'. If the
546 given option is `-mshort-data-512', the variable `m88k_short_data'
547 will be set to the string `"512"'.
549 extern char *m88k_short_data;
550 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
552 #define TARGET_OPTIONS \
554 SUBTARGET_TARGET_OPTIONS \
555 { "cpu=", &mips_cpu_string, \
556 N_("Specify CPU for scheduling purposes")}, \
557 { "ips", &mips_isa_string, \
558 N_("Specify MIPS ISA")}, \
559 { "entry", &mips_entry_string, \
560 N_("Use mips16 entry/exit psuedo ops")}, \
561 { "no-mips16", &mips_no_mips16_string, \
562 N_("Don't use MIPS16 instructions")}, \
563 { "explicit-type-size", &mips_explicit_type_size_string, \
567 /* This is meant to be redefined in the host dependent files. */
568 #define SUBTARGET_TARGET_OPTIONS
570 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
572 /* Generate three-operand multiply instructions for both SImode and DImode. */
573 #define GENERATE_MULT3 (TARGET_MIPS3900 \
576 /* Macros to decide whether certain features are available or not,
577 depending on the instruction set architecture level. */
579 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
580 #define HAVE_SQRT_P() (mips_isa != 1)
582 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
583 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
586 /* ISA has branch likely instructions (eg. mips2). */
587 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
589 /* ISA has the conditional move instructions introduced in mips4. */
590 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
593 /* ISA has just the integer condition move instructions (movn,movz) */
594 #define ISA_HAS_INT_CONDMOVE 0
598 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
599 branch on CC, and move (both FP and non-FP) on CC. */
600 #define ISA_HAS_8CC (mips_isa == 4 \
604 /* This is a catch all for the other new mips4 instructions: indexed load and
605 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
606 and the FP recip and recip sqrt instructions */
607 #define ISA_HAS_FP4 (mips_isa == 4 \
610 /* ISA has conditional trap instructions. */
611 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
614 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
615 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
616 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
617 target_flags, and -mgp64 sets MASK_64BIT.
619 Setting MASK_64BIT in target_flags will cause gcc to assume that
620 registers are 64 bits wide. int, long and void * will be 32 bit;
621 this may be changed with -mint64 or -mlong64.
623 The gen* programs link code that refers to MASK_64BIT. They don't
624 actually use the information in target_flags; they just refer to
627 /* Switch Recognition by gcc.c. Add -G xx support */
629 #ifdef SWITCH_TAKES_ARG
630 #undef SWITCH_TAKES_ARG
633 #define SWITCH_TAKES_ARG(CHAR) \
634 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
636 /* Sometimes certain combinations of command options do not make sense
637 on a particular target machine. You can define a macro
638 `OVERRIDE_OPTIONS' to take account of this. This macro, if
639 defined, is executed once just after all the command options have
642 On the MIPS, it is used to handle -G. We also use it to set up all
643 of the tables referenced in the other macros. */
645 #define OVERRIDE_OPTIONS override_options ()
647 /* Zero or more C statements that may conditionally modify two
648 variables `fixed_regs' and `call_used_regs' (both of type `char
649 []') after they have been initialized from the two preceding
652 This is necessary in case the fixed or call-clobbered registers
653 depend on target flags.
655 You need not define this macro if it has no work to do.
657 If the usage of an entire class of registers depends on the target
658 flags, you may indicate this to GCC by using this macro to modify
659 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
660 the classes which should not be used by GCC. Also define the macro
661 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
662 letter for a class that shouldn't be used.
664 (However, if this class is not included in `GENERAL_REGS' and all
665 of the insn patterns whose constraints permit this class are
666 controlled by target switches, then GCC will automatically avoid
667 using these registers when the target switches are opposed to
670 #define CONDITIONAL_REGISTER_USAGE \
673 if (!TARGET_HARD_FLOAT) \
677 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
678 fixed_regs[regno] = call_used_regs[regno] = 1; \
679 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
680 fixed_regs[regno] = call_used_regs[regno] = 1; \
682 else if (! ISA_HAS_8CC) \
686 /* We only have a single condition code register. We \
687 implement this by hiding all the condition code registers, \
688 and generating RTL that refers directly to ST_REG_FIRST. */ \
689 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
690 fixed_regs[regno] = call_used_regs[regno] = 1; \
692 /* In mips16 mode, we permit the $t temporary registers to be used \
693 for reload. We prohibit the unused $s registers, since they \
694 are caller saved, and saving them via a mips16 register would \
695 probably waste more time than just reloading the value. */ \
698 fixed_regs[18] = call_used_regs[18] = 1; \
699 fixed_regs[19] = call_used_regs[19] = 1; \
700 fixed_regs[20] = call_used_regs[20] = 1; \
701 fixed_regs[21] = call_used_regs[21] = 1; \
702 fixed_regs[22] = call_used_regs[22] = 1; \
703 fixed_regs[23] = call_used_regs[23] = 1; \
704 fixed_regs[26] = call_used_regs[26] = 1; \
705 fixed_regs[27] = call_used_regs[27] = 1; \
706 fixed_regs[30] = call_used_regs[30] = 1; \
708 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
712 /* This is meant to be redefined in the host dependent files. */
713 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
715 /* Show we can debug even without a frame pointer. */
716 #define CAN_DEBUG_WITHOUT_FP
718 /* Complain about missing specs and predefines that should be defined in each
719 of the target tm files to override the defaults. This is mostly a place-
720 holder until I can get each of the files updated [mm]. */
722 #if defined(OSF_OS) \
723 || defined(DECSTATION) \
724 || defined(SGI_TARGET) \
725 || defined(MIPS_NEWS) \
726 || defined(MIPS_SYSV) \
727 || defined(MIPS_SVR4) \
728 || defined(MIPS_BSD43)
730 #ifndef CPP_PREDEFINES
731 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
735 #error "Define LIB_SPEC in the appropriate tm.h file"
738 #ifndef STARTFILE_SPEC
739 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
743 #error "Define MACHINE_TYPE in the appropriate tm.h file"
747 /* Tell collect what flags to pass to nm. */
749 #define NM_FLAGS "-Bn"
753 /* Names to predefine in the preprocessor for this target machine. */
755 #ifndef CPP_PREDEFINES
756 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
757 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
758 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
761 /* Assembler specs. */
763 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
766 #define MIPS_AS_ASM_SPEC "\
767 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
768 %{pipe: %e-pipe is not supported.} \
769 %{K} %(subtarget_mips_as_asm_spec)"
771 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
772 rather than gas. It may be overridden by subtargets. */
774 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
775 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
778 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
781 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
783 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
784 GAS_ASM_SPEC as the default, depending upon the value of
787 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
790 #define TARGET_ASM_SPEC "\
791 %{mmips-as: %(mips_as_asm_spec)} \
792 %{!mmips-as: %(gas_asm_spec)}"
796 #define TARGET_ASM_SPEC "\
797 %{!mgas: %(mips_as_asm_spec)} \
798 %{mgas: %(gas_asm_spec)}"
802 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
803 to the assembler. It may be overridden by subtargets. */
804 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
805 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
807 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
810 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
811 the assembler. It may be overridden by subtargets. */
812 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
813 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
814 %{g} %{g0} %{g1} %{g2} %{g3} \
815 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
816 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
817 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
818 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
821 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
822 overridden by subtargets. */
824 #ifndef SUBTARGET_ASM_SPEC
825 #define SUBTARGET_ASM_SPEC ""
828 /* ASM_SPEC is the set of arguments to pass to the assembler. */
831 %{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
832 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
833 %(subtarget_asm_optimizing_spec) \
834 %(subtarget_asm_debugging_spec) \
837 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
839 %(subtarget_asm_spec)"
841 /* Specify to run a post-processor, mips-tfile after the assembler
842 has run to stuff the mips debug information into the object file.
843 This is needed because the $#!%^ MIPS assembler provides no way
844 of specifying such information in the assembly file. If we are
845 cross compiling, disable mips-tfile unless the user specifies
848 #ifndef ASM_FINAL_SPEC
849 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
851 #define ASM_FINAL_SPEC "\
852 %{mmips-as: %{!mno-mips-tfile: \
853 \n mips-tfile %{v*: -v} \
855 %{!K: %{save-temps: -I %b.o~}} \
856 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
857 %{.s:%i} %{!.s:%g.s}}}"
861 #define ASM_FINAL_SPEC "\
862 %{!mgas: %{!mno-mips-tfile: \
863 \n mips-tfile %{v*: -v} \
865 %{!K: %{save-temps: -I %b.o~}} \
866 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
867 %{.s:%i} %{!.s:%g.s}}}"
870 #endif /* ASM_FINAL_SPEC */
872 /* Redefinition of libraries used. Mips doesn't support normal
873 UNIX style profiling via calling _mcount. It does offer
874 profiling that samples the PC, so do what we can... */
877 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
880 /* Extra switches sometimes passed to the linker. */
881 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
882 will interpret it as a -b option. */
887 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \
888 %{bestGnum} %{shared} %{non_shared}"
889 #endif /* LINK_SPEC defined */
891 /* Specs for the compiler proper */
893 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
894 overridden by subtargets. */
895 #ifndef SUBTARGET_CC1_SPEC
896 #define SUBTARGET_CC1_SPEC ""
899 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
903 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
904 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
905 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
906 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
907 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
908 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
909 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
910 %{m4650:-mcpu=r4650} \
911 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
912 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
913 %{pic-none: -mno-half-pic} \
914 %{pic-lib: -mhalf-pic} \
915 %{pic-extern: -mhalf-pic} \
916 %{pic-calls: -mhalf-pic} \
918 %(subtarget_cc1_spec) "
921 /* Preprocessor specs. */
923 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
924 be overridden by subtargets. */
926 #ifndef SUBTARGET_CPP_SIZE_SPEC
927 #define SUBTARGET_CPP_SIZE_SPEC "\
928 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
929 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
932 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
933 overridden by subtargets. */
934 #ifndef SUBTARGET_CPP_SPEC
935 #define SUBTARGET_CPP_SPEC ""
938 /* If we're using 64bit longs, then we have to define __LONG_MAX__
939 correctly. Similarly for 64bit ints and __INT_MAX__. */
940 #ifndef LONG_MAX_SPEC
941 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
942 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
944 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
948 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
952 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
953 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
954 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
955 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
956 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
957 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
958 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
959 %(subtarget_cpp_size_spec) \
960 %{mips3:-U__mips -D__mips=3 -D__mips64} \
961 %{mips4:-U__mips -D__mips=4 -D__mips64} \
962 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
963 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
964 %{m4650:%{!msoft-float:-D__mips_single_float}} \
965 %{msoft-float:-D__mips_soft_float} \
966 %{mabi=eabi:-D__mips_eabi} \
967 %{mips16:%{!mno-mips16:-D__mips16}} \
968 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
969 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
971 %(subtarget_cpp_spec) "
974 /* This macro defines names of additional specifications to put in the specs
975 that can be used in various specifications like CC1_SPEC. Its definition
976 is an initializer with a subgrouping for each command option.
978 Each subgrouping contains a string constant, that defines the
979 specification name, and a string constant that used by the GNU CC driver
982 Do not define this macro if it does not need to do anything. */
984 #define EXTRA_SPECS \
985 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
986 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
987 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
988 { "long_max_spec", LONG_MAX_SPEC }, \
989 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
990 { "gas_asm_spec", GAS_ASM_SPEC }, \
991 { "target_asm_spec", TARGET_ASM_SPEC }, \
992 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
993 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
994 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
995 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
996 { "endian_spec", ENDIAN_SPEC }, \
997 SUBTARGET_EXTRA_SPECS
999 #ifndef SUBTARGET_EXTRA_SPECS
1000 #define SUBTARGET_EXTRA_SPECS
1003 /* If defined, this macro is an additional prefix to try after
1004 `STANDARD_EXEC_PREFIX'. */
1006 #ifndef MD_EXEC_PREFIX
1007 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1010 #ifndef MD_STARTFILE_PREFIX
1011 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1015 /* Print subsidiary information on the compiler version in use. */
1017 #define MIPS_VERSION "[AL 1.1, MM 40]"
1019 #ifndef MACHINE_TYPE
1020 #define MACHINE_TYPE "BSD Mips"
1023 #ifndef TARGET_VERSION_INTERNAL
1024 #define TARGET_VERSION_INTERNAL(STREAM) \
1025 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1028 #ifndef TARGET_VERSION
1029 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1033 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1034 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1035 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1037 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1038 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1041 /* By default, turn on GDB extensions. */
1042 #define DEFAULT_GDB_EXTENSIONS 1
1044 /* If we are passing smuggling stabs through the MIPS ECOFF object
1045 format, put a comment in front of the .stab<x> operation so
1046 that the MIPS assembler does not choke. The mips-tfile program
1047 will correctly put the stab into the object file. */
1049 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1050 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1051 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1053 /* Local compiler-generated symbols must have a prefix that the assembler
1054 understands. By default, this is $, although some targets (e.g.,
1055 NetBSD-ELF) need to override this. */
1057 #ifndef LOCAL_LABEL_PREFIX
1058 #define LOCAL_LABEL_PREFIX "$"
1061 /* By default on the mips, external symbols do not have an underscore
1062 prepended, but some targets (e.g., NetBSD) require this. */
1064 #ifndef USER_LABEL_PREFIX
1065 #define USER_LABEL_PREFIX ""
1068 /* Forward references to tags are allowed. */
1069 #define SDB_ALLOW_FORWARD_REFERENCES
1071 /* Unknown tags are also allowed. */
1072 #define SDB_ALLOW_UNKNOWN_REFERENCES
1074 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1075 since the length can run past this up to a continuation point. */
1076 #define DBX_CONTIN_LENGTH 1500
1078 /* How to renumber registers for dbx and gdb. */
1079 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1081 /* The mapping from gcc register number to DWARF 2 CFA column number.
1082 This mapping does not allow for tracking register 0, since SGI's broken
1083 dwarf reader thinks column 0 is used for the frame address, but since
1084 register 0 is fixed this is not a problem. */
1085 #define DWARF_FRAME_REGNUM(REG) \
1086 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1088 /* The DWARF 2 CFA column which tracks the return address. */
1089 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1091 /* Before the prologue, RA lives in r31. */
1092 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1094 /* Overrides for the COFF debug format. */
1095 #define PUT_SDB_SCL(a) \
1097 extern FILE *asm_out_text_file; \
1098 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1101 #define PUT_SDB_INT_VAL(a) \
1103 extern FILE *asm_out_text_file; \
1104 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1107 #define PUT_SDB_VAL(a) \
1109 extern FILE *asm_out_text_file; \
1110 fputs ("\t.val\t", asm_out_text_file); \
1111 output_addr_const (asm_out_text_file, (a)); \
1112 fputc (';', asm_out_text_file); \
1115 #define PUT_SDB_DEF(a) \
1117 extern FILE *asm_out_text_file; \
1118 fprintf (asm_out_text_file, "\t%s.def\t", \
1119 (TARGET_GAS) ? "" : "#"); \
1120 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1121 fputc (';', asm_out_text_file); \
1124 #define PUT_SDB_PLAIN_DEF(a) \
1126 extern FILE *asm_out_text_file; \
1127 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1128 (TARGET_GAS) ? "" : "#", (a)); \
1131 #define PUT_SDB_ENDEF \
1133 extern FILE *asm_out_text_file; \
1134 fprintf (asm_out_text_file, "\t.endef\n"); \
1137 #define PUT_SDB_TYPE(a) \
1139 extern FILE *asm_out_text_file; \
1140 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1143 #define PUT_SDB_SIZE(a) \
1145 extern FILE *asm_out_text_file; \
1146 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1149 #define PUT_SDB_DIM(a) \
1151 extern FILE *asm_out_text_file; \
1152 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1155 #ifndef PUT_SDB_START_DIM
1156 #define PUT_SDB_START_DIM \
1158 extern FILE *asm_out_text_file; \
1159 fprintf (asm_out_text_file, "\t.dim\t"); \
1163 #ifndef PUT_SDB_NEXT_DIM
1164 #define PUT_SDB_NEXT_DIM(a) \
1166 extern FILE *asm_out_text_file; \
1167 fprintf (asm_out_text_file, "%d,", a); \
1171 #ifndef PUT_SDB_LAST_DIM
1172 #define PUT_SDB_LAST_DIM(a) \
1174 extern FILE *asm_out_text_file; \
1175 fprintf (asm_out_text_file, "%d;", a); \
1179 #define PUT_SDB_TAG(a) \
1181 extern FILE *asm_out_text_file; \
1182 fprintf (asm_out_text_file, "\t.tag\t"); \
1183 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1184 fputc (';', asm_out_text_file); \
1187 /* For block start and end, we create labels, so that
1188 later we can figure out where the correct offset is.
1189 The normal .ent/.end serve well enough for functions,
1190 so those are just commented out. */
1192 #define PUT_SDB_BLOCK_START(LINE) \
1194 extern FILE *asm_out_text_file; \
1195 fprintf (asm_out_text_file, \
1196 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1197 LOCAL_LABEL_PREFIX, \
1199 (TARGET_GAS) ? "" : "#", \
1200 LOCAL_LABEL_PREFIX, \
1203 sdb_label_count++; \
1206 #define PUT_SDB_BLOCK_END(LINE) \
1208 extern FILE *asm_out_text_file; \
1209 fprintf (asm_out_text_file, \
1210 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1211 LOCAL_LABEL_PREFIX, \
1213 (TARGET_GAS) ? "" : "#", \
1214 LOCAL_LABEL_PREFIX, \
1217 sdb_label_count++; \
1220 #define PUT_SDB_FUNCTION_START(LINE)
1222 #define PUT_SDB_FUNCTION_END(LINE) \
1224 extern FILE *asm_out_text_file; \
1225 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1228 #define PUT_SDB_EPILOGUE_END(NAME)
1230 #define PUT_SDB_SRC_FILE(FILENAME) \
1232 extern FILE *asm_out_text_file; \
1233 output_file_directive (asm_out_text_file, (FILENAME)); \
1236 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1237 sprintf ((BUFFER), ".%dfake", (NUMBER));
1239 /* Correct the offset of automatic variables and arguments. Note that
1240 the MIPS debug format wants all automatic variables and arguments
1241 to be in terms of the virtual frame pointer (stack pointer before
1242 any adjustment in the function), while the MIPS 3.0 linker wants
1243 the frame pointer to be the stack pointer after the initial
1246 #define DEBUGGER_AUTO_OFFSET(X) \
1247 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1248 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1249 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1251 /* Tell collect that the object format is ECOFF */
1252 #ifndef OBJECT_FORMAT_ROSE
1253 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1254 #define EXTENDED_COFF /* ECOFF, not normal coff */
1257 #if 0 /* These definitions normally have no effect because
1258 MIPS systems define USE_COLLECT2, so
1259 assemble_constructor does nothing anyway. */
1261 /* Don't use the default definitions, because we don't have gld.
1262 Also, we don't want stabs when generating ECOFF output.
1263 Instead we depend on collect to handle these. */
1265 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1266 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1270 /* Target machine storage layout */
1272 /* Define in order to support both big and little endian float formats
1273 in the same gcc binary. */
1274 #define REAL_ARITHMETIC
1276 /* Define this if most significant bit is lowest numbered
1277 in instructions that operate on numbered bit-fields.
1279 #define BITS_BIG_ENDIAN 0
1281 /* Define this if most significant byte of a word is the lowest numbered. */
1282 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1284 /* Define this if most significant word of a multiword number is the lowest. */
1285 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1287 /* Define this to set the endianness to use in libgcc2.c, which can
1288 not depend on target_flags. */
1289 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1290 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1292 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1295 /* Number of bits in an addressable storage unit */
1296 #define BITS_PER_UNIT 8
1298 /* Width in bits of a "word", which is the contents of a machine register.
1299 Note that this is not necessarily the width of data type `int';
1300 if using 16-bit ints on a 68000, this would still be 32.
1301 But on a machine with 16-bit registers, this would be 16. */
1302 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1303 #define MAX_BITS_PER_WORD 64
1305 /* Width of a word, in units (bytes). */
1306 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1307 #define MIN_UNITS_PER_WORD 4
1309 /* For MIPS, width of a floating point register. */
1310 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1312 /* A C expression for the size in bits of the type `int' on the
1313 target machine. If you don't define this, the default is one
1315 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1316 #define MAX_INT_TYPE_SIZE 64
1318 /* Tell the preprocessor the maximum size of wchar_t. */
1319 #ifndef MAX_WCHAR_TYPE_SIZE
1320 #ifndef WCHAR_TYPE_SIZE
1321 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1325 /* A C expression for the size in bits of the type `short' on the
1326 target machine. If you don't define this, the default is half a
1327 word. (If this would be less than one storage unit, it is
1328 rounded up to one unit.) */
1329 #define SHORT_TYPE_SIZE 16
1331 /* A C expression for the size in bits of the type `long' on the
1332 target machine. If you don't define this, the default is one
1334 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1335 #define MAX_LONG_TYPE_SIZE 64
1337 /* A C expression for the size in bits of the type `long long' on the
1338 target machine. If you don't define this, the default is two
1340 #define LONG_LONG_TYPE_SIZE 64
1342 /* A C expression for the size in bits of the type `char' on the
1343 target machine. If you don't define this, the default is one
1344 quarter of a word. (If this would be less than one storage unit,
1345 it is rounded up to one unit.) */
1346 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1348 /* A C expression for the size in bits of the type `float' on the
1349 target machine. If you don't define this, the default is one
1351 #define FLOAT_TYPE_SIZE 32
1353 /* A C expression for the size in bits of the type `double' on the
1354 target machine. If you don't define this, the default is two
1356 #define DOUBLE_TYPE_SIZE 64
1358 /* A C expression for the size in bits of the type `long double' on
1359 the target machine. If you don't define this, the default is two
1361 #define LONG_DOUBLE_TYPE_SIZE 64
1363 /* Width in bits of a pointer.
1364 See also the macro `Pmode' defined below. */
1365 #ifndef POINTER_SIZE
1366 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1369 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1370 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1372 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1373 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1375 /* Allocation boundary (in *bits*) for the code of a function. */
1376 #define FUNCTION_BOUNDARY 32
1378 /* Alignment of field after `int : 0' in a structure. */
1379 #define EMPTY_FIELD_BOUNDARY 32
1381 /* Every structure's size must be a multiple of this. */
1382 /* 8 is observed right on a DECstation and on riscos 4.02. */
1383 #define STRUCTURE_SIZE_BOUNDARY 8
1385 /* There is no point aligning anything to a rounder boundary than this. */
1386 #define BIGGEST_ALIGNMENT 64
1388 /* Set this nonzero if move instructions will actually fail to work
1389 when given unaligned data. */
1390 #define STRICT_ALIGNMENT 1
1392 /* Define this if you wish to imitate the way many other C compilers
1393 handle alignment of bitfields and the structures that contain
1396 The behavior is that the type written for a bitfield (`int',
1397 `short', or other integer type) imposes an alignment for the
1398 entire structure, as if the structure really did contain an
1399 ordinary field of that type. In addition, the bitfield is placed
1400 within the structure so that it would fit within such a field,
1401 not crossing a boundary for it.
1403 Thus, on most machines, a bitfield whose type is written as `int'
1404 would not cross a four-byte boundary, and would force four-byte
1405 alignment for the whole structure. (The alignment used may not
1406 be four bytes; it is controlled by the other alignment
1409 If the macro is defined, its definition should be a C expression;
1410 a nonzero value for the expression enables this behavior. */
1412 #define PCC_BITFIELD_TYPE_MATTERS 1
1414 /* If defined, a C expression to compute the alignment given to a
1415 constant that is being placed in memory. CONSTANT is the constant
1416 and ALIGN is the alignment that the object would ordinarily have.
1417 The value of this macro is used instead of that alignment to align
1420 If this macro is not defined, then ALIGN is used.
1422 The typical use of this macro is to increase alignment for string
1423 constants to be word aligned so that `strcpy' calls that copy
1424 constants can be done inline. */
1426 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1427 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1428 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1430 /* If defined, a C expression to compute the alignment for a static
1431 variable. TYPE is the data type, and ALIGN is the alignment that
1432 the object would ordinarily have. The value of this macro is used
1433 instead of that alignment to align the object.
1435 If this macro is not defined, then ALIGN is used.
1437 One use of this macro is to increase alignment of medium-size
1438 data to make it all fit in fewer cache lines. Another is to
1439 cause character arrays to be word-aligned so that `strcpy' calls
1440 that copy constants to character arrays can be done inline. */
1442 #undef DATA_ALIGNMENT
1443 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1444 ((((ALIGN) < BITS_PER_WORD) \
1445 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1446 || TREE_CODE (TYPE) == UNION_TYPE \
1447 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1450 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1452 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1454 /* Define this macro if an argument declared as `char' or `short' in a
1455 prototype should actually be passed as an `int'. In addition to
1456 avoiding errors in certain cases of mismatch, it also makes for
1457 better code on certain machines. */
1459 #define PROMOTE_PROTOTYPES 1
1461 /* Define if operations between registers always perform the operation
1462 on the full register even if a narrower mode is specified. */
1463 #define WORD_REGISTER_OPERATIONS
1465 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1466 will either zero-extend or sign-extend. The value of this macro should
1467 be the code that says which one of the two operations is implicitly
1470 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1471 moves. All other referces are zero extended. */
1472 #define LOAD_EXTEND_OP(MODE) \
1473 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1474 ? SIGN_EXTEND : ZERO_EXTEND)
1476 /* Define this macro if it is advisable to hold scalars in registers
1477 in a wider mode than that declared by the program. In such cases,
1478 the value is constrained to be within the bounds of the declared
1479 type, but kept valid in the wider mode. The signedness of the
1480 extension may differ from that of the type.
1482 We promote any value smaller than SImode up to SImode. We don't
1483 want to promote to DImode when in 64 bit mode, because that would
1484 prevent us from using the faster SImode multiply and divide
1487 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1488 if (GET_MODE_CLASS (MODE) == MODE_INT \
1489 && GET_MODE_SIZE (MODE) < 4) \
1492 /* Define this if function arguments should also be promoted using the above
1495 #define PROMOTE_FUNCTION_ARGS
1497 /* Likewise, if the function return value is promoted. */
1499 #define PROMOTE_FUNCTION_RETURN
1501 /* Standard register usage. */
1503 /* Number of actual hardware registers.
1504 The hardware registers are assigned numbers for the compiler
1505 from 0 to just below FIRST_PSEUDO_REGISTER.
1506 All registers that the compiler knows about must be given numbers,
1507 even those that are not normally considered general registers.
1509 On the Mips, we have 32 integer registers, 32 floating point
1510 registers, 8 condition code registers, and the special registers
1511 hi, lo, hilo, and rap. The 8 condition code registers are only
1512 used if mips_isa >= 4. The hilo register is only used in 64 bit
1513 mode. It represents a 64 bit value stored as two 32 bit values in
1514 the hi and lo registers; this is the result of the mult
1515 instruction. rap is a pointer to the stack where the return
1516 address reg ($31) was stored. This is needed for C++ exception
1519 #define FIRST_PSEUDO_REGISTER 76
1521 /* 1 for registers that have pervasive standard uses
1522 and are not available for the register allocator.
1524 On the MIPS, see conventions, page D-2 */
1526 #define FIXED_REGISTERS \
1528 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1532 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1536 /* 1 for registers not available across function calls.
1537 These must include the FIXED_REGISTERS and also any
1538 registers that can be used without being saved.
1539 The latter must include the registers where values are returned
1540 and the register where structure-value addresses are passed.
1541 Aside from that, you can include as many other registers as you like. */
1543 #define CALL_USED_REGISTERS \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1546 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1553 /* Internal macros to classify a register number as to whether it's a
1554 general purpose register, a floating point register, a
1555 multiply/divide register, or a status register. */
1557 #define GP_REG_FIRST 0
1558 #define GP_REG_LAST 31
1559 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1560 #define GP_DBX_FIRST 0
1562 #define FP_REG_FIRST 32
1563 #define FP_REG_LAST 63
1564 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1565 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1567 #define MD_REG_FIRST 64
1568 #define MD_REG_LAST 66
1569 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1571 #define ST_REG_FIRST 67
1572 #define ST_REG_LAST 74
1573 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1575 #define RAP_REG_NUM 75
1577 #define AT_REGNUM (GP_REG_FIRST + 1)
1578 #define HI_REGNUM (MD_REG_FIRST + 0)
1579 #define LO_REGNUM (MD_REG_FIRST + 1)
1580 #define HILO_REGNUM (MD_REG_FIRST + 2)
1582 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1583 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1584 should be used instead. */
1585 #define FPSW_REGNUM ST_REG_FIRST
1587 #define GP_REG_P(REGNO) \
1588 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1589 #define M16_REG_P(REGNO) \
1590 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1591 #define FP_REG_P(REGNO) \
1592 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1593 #define MD_REG_P(REGNO) \
1594 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1595 #define ST_REG_P(REGNO) \
1596 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1598 /* Return number of consecutive hard regs needed starting at reg REGNO
1599 to hold something of mode MODE.
1600 This is ordinarily the length in words of a value of mode MODE
1601 but can be less for certain modes in special long registers.
1603 On the MIPS, all general registers are one word long. Except on
1604 the R4000 with the FR bit set, the floating point uses register
1605 pairs, with the second register not being allocable. */
1607 #define HARD_REGNO_NREGS(REGNO, MODE) \
1608 (! FP_REG_P (REGNO) \
1609 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1610 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1612 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1613 MODE. In 32 bit mode, require that DImode and DFmode be in even
1614 registers. For DImode, this makes some of the insns easier to
1615 write, since you don't have to worry about a DImode value in
1616 registers 3 & 4, producing a result in 4 & 5.
1618 To make the code simpler HARD_REGNO_MODE_OK now just references an
1619 array built in override_options. Because machmodes.h is not yet
1620 included before this file is processed, the MODE bound can't be
1623 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1625 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1626 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1628 /* Value is 1 if it is a good idea to tie two pseudo registers
1629 when one has mode MODE1 and one has mode MODE2.
1630 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1631 for any hard reg, then this must be 0 for correct output. */
1632 #define MODES_TIEABLE_P(MODE1, MODE2) \
1633 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1634 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1635 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1636 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1638 /* MIPS pc is not overloaded on a register. */
1639 /* #define PC_REGNUM xx */
1641 /* Register to use for pushing function arguments. */
1642 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1644 /* Offset from the stack pointer to the first available location. Use
1645 the default value zero. */
1646 /* #define STACK_POINTER_OFFSET 0 */
1648 /* Base register for access to local variables of the function. We
1649 pretend that the frame pointer is $1, and then eliminate it to
1650 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1651 a fixed register, and will not be used for anything else. */
1652 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1654 /* Temporary scratch register for use by the assembler. */
1655 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1657 /* $30 is not available on the mips16, so we use $17 as the frame
1659 #define HARD_FRAME_POINTER_REGNUM \
1660 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1662 /* Value should be nonzero if functions must have frame pointers.
1663 Zero means the frame pointer need not be set up (and parms
1664 may be accessed via the stack pointer) in functions that seem suitable.
1665 This is computed in `reload', in reload1.c. */
1666 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1668 /* Base register for access to arguments of the function. */
1669 #define ARG_POINTER_REGNUM GP_REG_FIRST
1671 /* Fake register that holds the address on the stack of the
1672 current function's return address. */
1673 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1675 /* Register in which static-chain is passed to a function. */
1676 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1678 /* If the structure value address is passed in a register, then
1679 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1680 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1682 /* If the structure value address is not passed in a register, define
1683 `STRUCT_VALUE' as an expression returning an RTX for the place
1684 where the address is passed. If it returns 0, the address is
1685 passed as an "invisible" first argument. */
1686 #define STRUCT_VALUE 0
1688 /* Mips registers used in prologue/epilogue code when the stack frame
1689 is larger than 32K bytes. These registers must come from the
1690 scratch register set, and not used for passing and returning
1691 arguments and any other information used in the calling sequence
1692 (such as pic). Must start at 12, since t0/t3 are parameter passing
1693 registers in the 64 bit ABI. */
1695 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1696 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1698 /* Define this macro if it is as good or better to call a constant
1699 function address than to call an address kept in a register. */
1700 #define NO_FUNCTION_CSE 1
1702 /* Define this macro if it is as good or better for a function to
1703 call itself with an explicit address than to call an address
1704 kept in a register. */
1705 #define NO_RECURSIVE_FUNCTION_CSE 1
1707 /* The register number of the register used to address a table of
1708 static data addresses in memory. In some cases this register is
1709 defined by a processor's "application binary interface" (ABI).
1710 When this macro is defined, RTL is generated for this register
1711 once, as with the stack pointer and frame pointer registers. If
1712 this macro is not defined, it is up to the machine-dependent
1713 files to allocate such a register (if necessary). */
1714 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1716 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1718 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1719 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1720 isn't always called for static inline functions. */
1721 #define INIT_EXPANDERS \
1723 embedded_pic_fnaddr_rtx = NULL; \
1724 mips16_gp_pseudo_rtx = NULL; \
1727 /* Define the classes of registers for register constraints in the
1728 machine description. Also define ranges of constants.
1730 One of the classes must always be named ALL_REGS and include all hard regs.
1731 If there is more than one class, another class must be named NO_REGS
1732 and contain no registers.
1734 The name GENERAL_REGS must be the name of a class (or an alias for
1735 another name such as ALL_REGS). This is the class of registers
1736 that is allowed by "g" or "r" in a register constraint.
1737 Also, registers outside this class are allocated only when
1738 instructions express preferences for them.
1740 The classes must be numbered in nondecreasing order; that is,
1741 a larger-numbered class must never be contained completely
1742 in a smaller-numbered class.
1744 For any two classes, it is very desirable that there be another
1745 class that represents their union. */
1749 NO_REGS, /* no registers in set */
1750 M16_NA_REGS, /* mips16 regs not used to pass args */
1751 M16_REGS, /* mips16 directly accessible registers */
1752 T_REG, /* mips16 T register ($24) */
1753 M16_T_REGS, /* mips16 registers plus T register */
1754 GR_REGS, /* integer registers */
1755 FP_REGS, /* floating point registers */
1756 HI_REG, /* hi register */
1757 LO_REG, /* lo register */
1758 HILO_REG, /* hilo register pair for 64 bit mode mult */
1759 MD_REGS, /* multiply/divide registers (hi/lo) */
1760 HI_AND_GR_REGS, /* union classes */
1763 ST_REGS, /* status registers (fp status) */
1764 ALL_REGS, /* all registers */
1765 LIM_REG_CLASSES /* max value + 1 */
1768 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1770 #define GENERAL_REGS GR_REGS
1772 /* An initializer containing the names of the register classes as C
1773 string constants. These names are used in writing some of the
1776 #define REG_CLASS_NAMES \
1791 "HILO_AND_GR_REGS", \
1796 /* An initializer containing the contents of the register classes,
1797 as integers which are bit masks. The Nth integer specifies the
1798 contents of class N. The way the integer MASK is interpreted is
1799 that register R is in the class if `MASK & (1 << R)' is 1.
1801 When the machine has more than 32 registers, an integer does not
1802 suffice. Then the integers are replaced by sub-initializers,
1803 braced groupings containing several integers. Each
1804 sub-initializer must be suitable as an initializer for the type
1805 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1807 #define REG_CLASS_CONTENTS \
1809 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1810 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1811 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1812 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1813 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1814 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1815 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1816 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1817 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1818 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1819 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1820 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1821 { 0xffffffff, 0x00000000, 0x00000002 }, \
1822 { 0xffffffff, 0x00000000, 0x00000004 }, \
1823 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1824 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1828 /* A C expression whose value is a register class containing hard
1829 register REGNO. In general there is more that one such class;
1830 choose a class which is "minimal", meaning that no smaller class
1831 also contains the register. */
1833 extern enum reg_class mips_regno_to_class[];
1835 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1837 /* A macro whose definition is the name of the class to which a
1838 valid base register must belong. A base register is one used in
1839 an address which is the register value plus a displacement. */
1841 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1843 /* A macro whose definition is the name of the class to which a
1844 valid index register must belong. An index register is one used
1845 in an address where its value is either multiplied by a scale
1846 factor or added to another register (as well as added to a
1849 #define INDEX_REG_CLASS NO_REGS
1851 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1852 registers explicitly used in the rtl to be used as spill registers
1853 but prevents the compiler from extending the lifetime of these
1856 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1858 /* This macro is used later on in the file. */
1859 #define GR_REG_CLASS_P(CLASS) \
1860 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1861 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1863 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1864 is the default value (allocate the registers in numeric order). We
1865 define it just so that we can override it for the mips16 target in
1866 ORDER_REGS_FOR_LOCAL_ALLOC. */
1868 #define REG_ALLOC_ORDER \
1869 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1870 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1871 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1872 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1873 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1876 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1877 to be rearranged based on a particular function. On the mips16, we
1878 want to allocate $24 (T_REG) before other registers for
1879 instructions for which it is possible. */
1881 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1883 /* REGISTER AND CONSTANT CLASSES */
1885 /* Get reg_class from a letter such as appears in the machine
1888 DEFINED REGISTER CLASSES:
1890 'd' General (aka integer) registers
1891 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1892 'y' General registers (in both mips16 and non mips16 mode)
1893 'e' mips16 non argument registers (M16_NA_REGS)
1894 't' mips16 temporary register ($24)
1895 'f' Floating point registers
1898 'x' Multiply/divide registers
1900 'z' FP Status register
1901 'b' All registers */
1903 extern enum reg_class mips_char_to_class[];
1905 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1907 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1908 string can be used to stand for particular ranges of immediate
1909 operands. This macro defines what the ranges are. C is the
1910 letter, and VALUE is a constant value. Return 1 if VALUE is
1911 in the range specified by C. */
1915 `I' is used for the range of constants an arithmetic insn can
1916 actually contain (16 bits signed integers).
1918 `J' is used for the range which is just zero (ie, $r0).
1920 `K' is used for the range of constants a logical insn can actually
1921 contain (16 bit zero-extended integers).
1923 `L' is used for the range of constants that be loaded with lui
1924 (ie, the bottom 16 bits are zero).
1926 `M' is used for the range of constants that take two words to load
1927 (ie, not matched by `I', `K', and `L').
1929 `N' is used for negative 16 bit constants other than -65536.
1931 `O' is a 15 bit signed integer.
1933 `P' is used for positive 16 bit constants. */
1935 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1936 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1938 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1939 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1940 : (C) == 'J' ? ((VALUE) == 0) \
1941 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1942 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1943 && (((VALUE) & ~2147483647) == 0 \
1944 || ((VALUE) & ~2147483647) == ~2147483647)) \
1945 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1946 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1947 && (((VALUE) & 0x0000ffff) != 0 \
1948 || (((VALUE) & ~2147483647) != 0 \
1949 && ((VALUE) & ~2147483647) != ~2147483647))) \
1950 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1951 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1952 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1955 /* Similar, but for floating constants, and defining letters G and H.
1956 Here VALUE is the CONST_DOUBLE rtx itself. */
1960 'G' : Floating point 0 */
1962 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1964 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1966 /* Letters in the range `Q' through `U' may be defined in a
1967 machine-dependent fashion to stand for arbitrary operand types.
1968 The machine description macro `EXTRA_CONSTRAINT' is passed the
1969 operand as its first argument and the constraint letter as its
1972 `Q' is for mips16 GP relative constants
1973 `R' is for memory references which take 1 word for the instruction.
1974 `S' is for references to extern items which are PIC for OSF/rose.
1975 `T' is for memory addresses that can be used to load two words. */
1977 #define EXTRA_CONSTRAINT(OP,CODE) \
1978 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1979 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1980 && mips16_gp_offset_p (OP)) \
1981 : (GET_CODE (OP) != MEM) ? FALSE \
1982 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1983 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1984 && HALF_PIC_ADDRESS_P (OP)) \
1987 /* Given an rtx X being reloaded into a reg required to be
1988 in class CLASS, return the class of reg to actually use.
1989 In general this is just CLASS; but on some machines
1990 in some cases it is preferable to use a more restrictive class. */
1992 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1993 ((CLASS) != ALL_REGS \
1994 ? (! TARGET_MIPS16 \
1996 : ((CLASS) != GR_REGS \
1999 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2000 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2001 ? (TARGET_SOFT_FLOAT \
2002 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2004 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2005 || GET_MODE (X) == VOIDmode) \
2006 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2009 /* Certain machines have the property that some registers cannot be
2010 copied to some other registers without using memory. Define this
2011 macro on those machines to be a C expression that is non-zero if
2012 objects of mode MODE in registers of CLASS1 can only be copied to
2013 registers of class CLASS2 by storing a register of CLASS1 into
2014 memory and loading that memory location into a register of CLASS2.
2016 Do not define this macro if its value would always be zero. */
2018 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2019 ((!TARGET_DEBUG_H_MODE \
2020 && GET_MODE_CLASS (MODE) == MODE_INT \
2021 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2022 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2023 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2024 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2025 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2027 /* The HI and LO registers can only be reloaded via the general
2028 registers. Condition code registers can only be loaded to the
2029 general registers, and from the floating point registers. */
2031 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2032 mips_secondary_reload_class (CLASS, MODE, X, 1)
2033 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2034 mips_secondary_reload_class (CLASS, MODE, X, 0)
2036 /* Return the maximum number of consecutive registers
2037 needed to represent mode MODE in a register of class CLASS. */
2039 #define CLASS_UNITS(mode, size) \
2040 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2042 #define CLASS_MAX_NREGS(CLASS, MODE) \
2043 ((CLASS) == FP_REGS \
2045 ? CLASS_UNITS (MODE, 8) \
2046 : 2 * CLASS_UNITS (MODE, 8)) \
2047 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2049 /* If defined, gives a class of registers that cannot be used as the
2050 operand of a SUBREG that changes the mode of the object illegally. */
2052 #define CLASS_CANNOT_CHANGE_MODE \
2053 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2055 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2057 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2058 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2060 /* Stack layout; function entry, exit and calling. */
2062 /* Define this if pushing a word on the stack
2063 makes the stack pointer a smaller address. */
2064 #define STACK_GROWS_DOWNWARD
2066 /* Define this if the nominal address of the stack frame
2067 is at the high-address end of the local variables;
2068 that is, each additional local variable allocated
2069 goes at a more negative offset in the frame. */
2070 /* #define FRAME_GROWS_DOWNWARD */
2072 /* Offset within stack frame to start allocating local variables at.
2073 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2074 first local allocated. Otherwise, it is the offset to the BEGINNING
2075 of the first local allocated. */
2076 #define STARTING_FRAME_OFFSET \
2077 (current_function_outgoing_args_size \
2078 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2080 /* Offset from the stack pointer register to an item dynamically
2081 allocated on the stack, e.g., by `alloca'.
2083 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2084 length of the outgoing arguments. The default is correct for most
2085 machines. See `function.c' for details.
2087 The MIPS ABI states that functions which dynamically allocate the
2088 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2089 we are trying to create a second frame pointer to the function, so
2090 allocate some stack space to make it happy.
2092 However, the linker currently complains about linking any code that
2093 dynamically allocates stack space, and there seems to be a bug in
2094 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2097 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2098 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2099 ? 4*UNITS_PER_WORD \
2100 : current_function_outgoing_args_size)
2103 /* The return address for the current frame is in r31 is this is a leaf
2104 function. Otherwise, it is on the stack. It is at a variable offset
2105 from sp/fp/ap, so we define a fake hard register rap which is a
2106 poiner to the return address on the stack. This always gets eliminated
2107 during reload to be either the frame pointer or the stack pointer plus
2110 /* ??? This definition fails for leaf functions. There is currently no
2111 general solution for this problem. */
2113 /* ??? There appears to be no way to get the return address of any previous
2114 frame except by disassembling instructions in the prologue/epilogue.
2115 So currently we support only the current frame. */
2117 #define RETURN_ADDR_RTX(count, frame) \
2119 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2122 /* Structure to be filled in by compute_frame_size with register
2123 save masks, and offsets for the current function. */
2125 struct mips_frame_info
2127 long total_size; /* # bytes that the entire frame takes up */
2128 long var_size; /* # bytes that variables take up */
2129 long args_size; /* # bytes that outgoing arguments take up */
2130 long extra_size; /* # bytes of extra gunk */
2131 int gp_reg_size; /* # bytes needed to store gp regs */
2132 int fp_reg_size; /* # bytes needed to store fp regs */
2133 long mask; /* mask of saved gp registers */
2134 long fmask; /* mask of saved fp registers */
2135 long gp_save_offset; /* offset from vfp to store gp registers */
2136 long fp_save_offset; /* offset from vfp to store fp registers */
2137 long gp_sp_offset; /* offset from new sp to store gp registers */
2138 long fp_sp_offset; /* offset from new sp to store fp registers */
2139 int initialized; /* != 0 if frame size already calculated */
2140 int num_gp; /* number of gp registers saved */
2141 int num_fp; /* number of fp registers saved */
2142 long insns_len; /* length of insns; mips16 only */
2145 extern struct mips_frame_info current_frame_info;
2147 /* If defined, this macro specifies a table of register pairs used to
2148 eliminate unneeded registers that point into the stack frame. If
2149 it is not defined, the only elimination attempted by the compiler
2150 is to replace references to the frame pointer with references to
2153 The definition of this macro is a list of structure
2154 initializations, each of which specifies an original and
2155 replacement register.
2157 On some machines, the position of the argument pointer is not
2158 known until the compilation is completed. In such a case, a
2159 separate hard register must be used for the argument pointer.
2160 This register can be eliminated by replacing it with either the
2161 frame pointer or the argument pointer, depending on whether or not
2162 the frame pointer has been eliminated.
2164 In this case, you might specify:
2165 #define ELIMINABLE_REGS \
2166 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2167 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2168 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2170 Note that the elimination of the argument pointer with the stack
2171 pointer is specified first since that is the preferred elimination.
2173 The eliminations to $17 are only used on the mips16. See the
2174 definition of HARD_FRAME_POINTER_REGNUM. */
2176 #define ELIMINABLE_REGS \
2177 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2178 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2179 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2180 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2181 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2182 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2183 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2184 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2185 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2186 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2188 /* A C expression that returns non-zero if the compiler is allowed to
2189 try to replace register number FROM-REG with register number
2190 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2191 defined, and will usually be the constant 1, since most of the
2192 cases preventing register elimination are things that the compiler
2193 already knows about.
2195 When not in mips16 and mips64, we can always eliminate to the
2196 frame pointer. We can eliminate to the stack pointer unless
2197 a frame pointer is needed. In mips16 mode, we need a frame
2198 pointer for a large frame; otherwise, reload may be unable
2199 to compute the address of a local variable, since there is
2200 no way to add a large constant to the stack pointer
2201 without using a temporary register.
2203 In mips16, for some instructions (eg lwu), we can't eliminate the
2204 frame pointer for the stack pointer. These instructions are
2205 only generated in TARGET_64BIT mode.
2208 #define CAN_ELIMINATE(FROM, TO) \
2209 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2210 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2211 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2212 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2213 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2214 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2215 && (! TARGET_MIPS16 \
2216 || compute_frame_size (get_frame_size ()) < 32768)))))
2218 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2219 specifies the initial difference between the specified pair of
2220 registers. This macro must be defined if `ELIMINABLE_REGS' is
2223 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2224 { compute_frame_size (get_frame_size ()); \
2225 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2226 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2227 (OFFSET) = - current_function_outgoing_args_size; \
2228 else if ((FROM) == FRAME_POINTER_REGNUM) \
2230 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2231 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2232 (OFFSET) = (current_frame_info.total_size \
2233 - current_function_outgoing_args_size \
2234 - ((mips_abi != ABI_32 \
2235 && mips_abi != ABI_O64 \
2236 && mips_abi != ABI_EABI) \
2237 ? current_function_pretend_args_size \
2239 else if ((FROM) == ARG_POINTER_REGNUM) \
2240 (OFFSET) = (current_frame_info.total_size \
2241 - ((mips_abi != ABI_32 \
2242 && mips_abi != ABI_O64 \
2243 && mips_abi != ABI_EABI) \
2244 ? current_function_pretend_args_size \
2246 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2247 so we must add 4 bytes to the offset to get the right value. */ \
2248 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2250 if (leaf_function_p ()) \
2252 else (OFFSET) = current_frame_info.gp_sp_offset \
2253 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2254 * (BYTES_BIG_ENDIAN != 0)); \
2258 /* If we generate an insn to push BYTES bytes,
2259 this says how many the stack pointer really advances by.
2260 On the vax, sp@- in a byte insn really pushes a word. */
2262 /* #define PUSH_ROUNDING(BYTES) 0 */
2264 /* If defined, the maximum amount of space required for outgoing
2265 arguments will be computed and placed into the variable
2266 `current_function_outgoing_args_size'. No space will be pushed
2267 onto the stack for each call; instead, the function prologue
2268 should increase the stack frame size by this amount.
2270 It is not proper to define both `PUSH_ROUNDING' and
2271 `ACCUMULATE_OUTGOING_ARGS'. */
2272 #define ACCUMULATE_OUTGOING_ARGS 1
2274 /* Offset from the argument pointer register to the first argument's
2275 address. On some machines it may depend on the data type of the
2278 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2279 the first argument's address.
2281 On the MIPS, we must skip the first argument position if we are
2282 returning a structure or a union, to account for its address being
2283 passed in $4. However, at the current time, this produces a compiler
2284 that can't bootstrap, so comment it out for now. */
2287 #define FIRST_PARM_OFFSET(FNDECL) \
2289 && TREE_TYPE (FNDECL) != 0 \
2290 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2291 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2292 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2296 #define FIRST_PARM_OFFSET(FNDECL) 0
2299 /* When a parameter is passed in a register, stack space is still
2300 allocated for it. For the MIPS, stack space must be allocated, cf
2301 Asm Lang Prog Guide page 7-8.
2303 BEWARE that some space is also allocated for non existing arguments
2304 in register. In case an argument list is of form GF used registers
2305 are a0 (a2,a3), but we should push over a1... */
2307 #define REG_PARM_STACK_SPACE(FNDECL) \
2308 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2310 /* Define this if it is the responsibility of the caller to
2311 allocate the area reserved for arguments passed in registers.
2312 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2313 of this macro is to determine whether the space is included in
2314 `current_function_outgoing_args_size'. */
2315 #define OUTGOING_REG_PARM_STACK_SPACE
2317 /* Align stack frames on 64 bits (Double Word ). */
2318 #ifndef STACK_BOUNDARY
2319 #define STACK_BOUNDARY 64
2322 /* Make sure 4 words are always allocated on the stack. */
2324 #ifndef STACK_ARGS_ADJUST
2325 #define STACK_ARGS_ADJUST(SIZE) \
2327 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2328 SIZE.constant = 4 * UNITS_PER_WORD; \
2333 /* A C expression that should indicate the number of bytes of its
2334 own arguments that a function pops on returning, or 0
2335 if the function pops no arguments and the caller must therefore
2336 pop them all after the function returns.
2338 FUNDECL is the declaration node of the function (as a tree).
2340 FUNTYPE is a C variable whose value is a tree node that
2341 describes the function in question. Normally it is a node of
2342 type `FUNCTION_TYPE' that describes the data type of the function.
2343 From this it is possible to obtain the data types of the value
2344 and arguments (if known).
2346 When a call to a library function is being considered, FUNTYPE
2347 will contain an identifier node for the library function. Thus,
2348 if you need to distinguish among various library functions, you
2349 can do so by their names. Note that "library function" in this
2350 context means a function used to perform arithmetic, whose name
2351 is known specially in the compiler and was not mentioned in the
2352 C code being compiled.
2354 STACK-SIZE is the number of bytes of arguments passed on the
2355 stack. If a variable number of bytes is passed, it is zero, and
2356 argument popping will always be the responsibility of the
2357 calling function. */
2359 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2362 /* Symbolic macros for the registers used to return integer and floating
2365 #define GP_RETURN (GP_REG_FIRST + 2)
2366 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2368 /* Symbolic macros for the first/last argument registers. */
2370 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2371 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2372 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2373 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2375 #define MAX_ARGS_IN_REGISTERS 4
2377 /* Define how to find the value returned by a library function
2378 assuming the value has mode MODE. Because we define
2379 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2380 PROMOTE_MODE does. */
2382 #define LIBCALL_VALUE(MODE) \
2384 ((GET_MODE_CLASS (MODE) != MODE_INT \
2385 || GET_MODE_SIZE (MODE) >= 4) \
2388 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2389 && (! TARGET_SINGLE_FLOAT \
2390 || GET_MODE_SIZE (MODE) <= 4)) \
2394 /* Define how to find the value returned by a function.
2395 VALTYPE is the data type of the value (as a tree).
2396 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2397 otherwise, FUNC is 0. */
2399 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2402 /* 1 if N is a possible register number for a function value.
2403 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2404 Currently, R2 and F0 are only implemented here (C has no complex type) */
2406 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2408 /* 1 if N is a possible register number for function argument passing.
2409 We have no FP argument registers when soft-float. When FP registers
2410 are 32 bits, we can't directly reference the odd numbered ones. */
2412 #define FUNCTION_ARG_REGNO_P(N) \
2413 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2414 || ((! TARGET_SOFT_FLOAT \
2415 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2416 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2417 && ! fixed_regs[N]))
2419 /* A C expression which can inhibit the returning of certain function
2420 values in registers, based on the type of value. A nonzero value says
2421 to return the function value in memory, just as large structures are
2422 always returned. Here TYPE will be a C expression of type
2423 `tree', representing the data type of the value.
2425 Note that values of mode `BLKmode' must be explicitly
2426 handled by this macro. Also, the option `-fpcc-struct-return'
2427 takes effect regardless of this macro. On most systems, it is
2428 possible to leave the macro undefined; this causes a default
2429 definition to be used, whose value is the constant 1 for BLKmode
2430 values, and 0 otherwise.
2432 GCC normally converts 1 byte structures into chars, 2 byte
2433 structs into shorts, and 4 byte structs into ints, and returns
2434 them this way. Defining the following macro overrides this,
2435 to give us MIPS cc compatibility. */
2437 #define RETURN_IN_MEMORY(TYPE) \
2438 (TYPE_MODE (TYPE) == BLKmode)
2440 /* A code distinguishing the floating point format of the target
2441 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2442 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2444 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2447 /* Define a data type for recording info about an argument list
2448 during the scan of that argument list. This data type should
2449 hold all necessary information about the function itself
2450 and about the args processed so far, enough to enable macros
2451 such as FUNCTION_ARG to determine where the next arg should go.
2453 On the mips16, we need to keep track of which floating point
2454 arguments were passed in general registers, but would have been
2455 passed in the FP regs if this were a 32 bit function, so that we
2456 can move them to the FP regs if we wind up calling a 32 bit
2457 function. We record this information in fp_code, encoded in base
2458 four. A zero digit means no floating point argument, a one digit
2459 means an SFmode argument, and a two digit means a DFmode argument,
2460 and a three digit is not used. The low order digit is the first
2461 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2462 an SFmode argument. ??? A more sophisticated approach will be
2463 needed if MIPS_ABI != ABI_32. */
2465 typedef struct mips_args {
2466 int gp_reg_found; /* whether a gp register was found yet */
2467 unsigned int arg_number; /* argument number */
2468 unsigned int arg_words; /* # total words the arguments take */
2469 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2470 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2471 int fp_code; /* Mode of FP arguments (mips16) */
2472 unsigned int num_adjusts; /* number of adjustments made */
2473 /* Adjustments made to args pass in regs. */
2474 /* ??? The size is doubled to work around a
2475 bug in the code that sets the adjustments
2477 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2480 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2481 for a call to a function whose data type is FNTYPE.
2482 For a library call, FNTYPE is 0.
2486 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2487 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2489 /* Update the data in CUM to advance over an argument
2490 of mode MODE and data type TYPE.
2491 (TYPE is null for libcalls where that information may not be available.) */
2493 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2494 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2496 /* Determine where to put an argument to a function.
2497 Value is zero to push the argument on the stack,
2498 or a hard register in which to store the argument.
2500 MODE is the argument's machine mode.
2501 TYPE is the data type of the argument (as a tree).
2502 This is null for libcalls where that information may
2504 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2505 the preceding args and about the function being called.
2506 NAMED is nonzero if this argument is a named parameter
2507 (otherwise it is an extra parameter matching an ellipsis). */
2509 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2510 function_arg( &CUM, MODE, TYPE, NAMED)
2512 /* For an arg passed partly in registers and partly in memory,
2513 this is the number of registers used.
2514 For args passed entirely in registers or entirely in memory, zero. */
2516 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2517 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2519 /* If defined, a C expression that gives the alignment boundary, in
2520 bits, of an argument with the specified mode and type. If it is
2521 not defined, `PARM_BOUNDARY' is used for all arguments. */
2523 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2525 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2527 : TYPE_ALIGN(TYPE)) \
2528 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2530 : GET_MODE_ALIGNMENT(MODE)))
2533 /* This macro generates the assembly code for function entry.
2534 FILE is a stdio stream to output the code to.
2535 SIZE is an int: how many units of temporary storage to allocate.
2536 Refer to the array `regs_ever_live' to determine which registers
2537 to save; `regs_ever_live[I]' is nonzero if register number I
2538 is ever used in the function. This macro is responsible for
2539 knowing which registers should not be saved even if used. */
2541 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2543 /* This macro generates the assembly code for function exit,
2544 on machines that need it. If FUNCTION_EPILOGUE is not defined
2545 then individual return instructions are generated for each
2546 return statement. Args are same as for FUNCTION_PROLOGUE. */
2548 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2550 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2552 #define MUST_SAVE_REGISTER(regno) \
2553 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2554 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2555 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2557 /* ALIGN FRAMES on double word boundaries */
2558 #ifndef MIPS_STACK_ALIGN
2559 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2563 /* Define the `__builtin_va_list' type for the ABI. */
2564 #define BUILD_VA_LIST_TYPE(VALIST) \
2565 (VALIST) = mips_build_va_list ()
2567 /* Implement `va_start' for varargs and stdarg. */
2568 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2569 mips_va_start (stdarg, valist, nextarg)
2571 /* Implement `va_arg'. */
2572 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2573 mips_va_arg (valist, type)
2575 /* Output assembler code to FILE to increment profiler label # LABELNO
2576 for profiling a function entry. */
2578 #define FUNCTION_PROFILER(FILE, LABELNO) \
2580 if (TARGET_MIPS16) \
2581 sorry ("mips16 function profiling"); \
2582 fprintf (FILE, "\t.set\tnoreorder\n"); \
2583 fprintf (FILE, "\t.set\tnoat\n"); \
2584 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2585 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2586 fprintf (FILE, "\tjal\t_mcount\n"); \
2588 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2589 TARGET_64BIT ? "dsubu" : "subu", \
2590 reg_names[STACK_POINTER_REGNUM], \
2591 reg_names[STACK_POINTER_REGNUM], \
2592 Pmode == DImode ? 16 : 8); \
2593 fprintf (FILE, "\t.set\treorder\n"); \
2594 fprintf (FILE, "\t.set\tat\n"); \
2597 /* Define this macro if the code for function profiling should come
2598 before the function prologue. Normally, the profiling code comes
2601 /* #define PROFILE_BEFORE_PROLOGUE */
2603 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2604 the stack pointer does not matter. The value is tested only in
2605 functions that have frame pointers.
2606 No definition is equivalent to always zero. */
2608 #define EXIT_IGNORE_STACK 1
2611 /* A C statement to output, on the stream FILE, assembler code for a
2612 block of data that contains the constant parts of a trampoline.
2613 This code should not include a label--the label is taken care of
2616 #define TRAMPOLINE_TEMPLATE(STREAM) \
2618 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2619 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2620 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2621 if (Pmode == DImode) \
2623 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2624 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2628 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2629 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2631 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2632 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2633 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2634 if (Pmode == DImode) \
2636 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2637 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2641 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2642 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2646 /* A C expression for the size in bytes of the trampoline, as an
2649 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2651 /* Alignment required for trampolines, in bits. */
2653 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2655 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2656 program and data caches. */
2658 #ifndef CACHE_FLUSH_FUNC
2659 #define CACHE_FLUSH_FUNC "_flush_cache"
2662 /* A C statement to initialize the variable parts of a trampoline.
2663 ADDR is an RTX for the address of the trampoline; FNADDR is an
2664 RTX for the address of the nested function; STATIC_CHAIN is an
2665 RTX for the static chain value that should be passed to the
2666 function when it is called. */
2668 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2671 if (Pmode == DImode) \
2673 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2674 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2678 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2679 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2682 /* Flush both caches. We need to flush the data cache in case \
2683 the system has a write-back cache. */ \
2684 /* ??? Should check the return value for errors. */ \
2685 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2686 0, VOIDmode, 3, addr, Pmode, \
2687 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2688 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2691 /* Addressing modes, and classification of registers for them. */
2693 /* #define HAVE_POST_INCREMENT 0 */
2694 /* #define HAVE_POST_DECREMENT 0 */
2696 /* #define HAVE_PRE_DECREMENT 0 */
2697 /* #define HAVE_PRE_INCREMENT 0 */
2699 /* These assume that REGNO is a hard or pseudo reg number.
2700 They give nonzero only if REGNO is a hard reg of the suitable class
2701 or a pseudo reg currently allocated to a suitable hard reg.
2702 These definitions are NOT overridden anywhere. */
2704 #define BASE_REG_P(regno, mode) \
2706 ? (M16_REG_P (regno) \
2707 || (regno) == FRAME_POINTER_REGNUM \
2708 || (regno) == ARG_POINTER_REGNUM \
2709 || ((regno) == STACK_POINTER_REGNUM \
2710 && (GET_MODE_SIZE (mode) == 4 \
2711 || GET_MODE_SIZE (mode) == 8))) \
2714 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2715 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2718 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2719 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2721 #define REGNO_OK_FOR_INDEX_P(regno) 0
2722 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2723 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2725 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2726 and check its validity for a certain class.
2727 We have two alternate definitions for each of them.
2728 The usual definition accepts all pseudo regs; the other rejects them all.
2729 The symbol REG_OK_STRICT causes the latter definition to be used.
2731 Most source files want to accept pseudo regs in the hope that
2732 they will get allocated to the class that the insn wants them to be in.
2733 Some source files that are used after register allocation
2734 need to be strict. */
2736 #ifndef REG_OK_STRICT
2737 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2738 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2740 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2741 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2744 #define REG_OK_FOR_INDEX_P(X) 0
2747 /* Maximum number of registers that can appear in a valid memory address. */
2749 #define MAX_REGS_PER_ADDRESS 1
2751 /* A C compound statement with a conditional `goto LABEL;' executed
2752 if X (an RTX) is a legitimate memory address on the target
2753 machine for a memory operand of mode MODE.
2755 It usually pays to define several simpler macros to serve as
2756 subroutines for this one. Otherwise it may be too complicated
2759 This macro must exist in two variants: a strict variant and a
2760 non-strict one. The strict variant is used in the reload pass.
2761 It must be defined so that any pseudo-register that has not been
2762 allocated a hard register is considered a memory reference. In
2763 contexts where some kind of register is required, a
2764 pseudo-register with no hard register must be rejected.
2766 The non-strict variant is used in other passes. It must be
2767 defined to accept all pseudo-registers in every context where
2768 some kind of register is required.
2770 Compiler source files that want to use the strict variant of
2771 this macro define the macro `REG_OK_STRICT'. You should use an
2772 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2773 in that case and the non-strict variant otherwise.
2775 Typically among the subroutines used to define
2776 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2777 acceptable registers for various purposes (one for base
2778 registers, one for index registers, and so on). Then only these
2779 subroutine macros need have two variants; the higher levels of
2780 macros may be the same whether strict or not.
2782 Normally, constant addresses which are the sum of a `symbol_ref'
2783 and an integer are stored inside a `const' RTX to mark them as
2784 constant. Therefore, there is no need to recognize such sums
2785 specifically as legitimate addresses. Normally you would simply
2786 recognize any `const' as legitimate.
2788 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2789 constant sums that are not marked with `const'. It assumes
2790 that a naked `plus' indicates indexing. If so, then you *must*
2791 reject such naked constant sums as illegitimate addresses, so
2792 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2794 On some machines, whether a symbolic address is legitimate
2795 depends on the section that the address refers to. On these
2796 machines, define the macro `ENCODE_SECTION_INFO' to store the
2797 information into the `symbol_ref', and then check for it here.
2798 When you see a `const', you will have to look inside it to find
2799 the `symbol_ref' in order to determine the section. */
2802 #define GO_PRINTF(x) fprintf(stderr, (x))
2803 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2804 #define GO_DEBUG_RTX(x) debug_rtx(x)
2807 #define GO_PRINTF(x)
2808 #define GO_PRINTF2(x,y)
2809 #define GO_DEBUG_RTX(x)
2812 #ifdef REG_OK_STRICT
2813 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2815 if (mips_legitimate_address_p (MODE, X, 1)) \
2819 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2821 if (mips_legitimate_address_p (MODE, X, 0)) \
2826 /* A C expression that is 1 if the RTX X is a constant which is a
2827 valid address. This is defined to be the same as `CONSTANT_P (X)',
2828 but rejecting CONST_DOUBLE. */
2829 /* When pic, we must reject addresses of the form symbol+large int.
2830 This is because an instruction `sw $4,s+70000' needs to be converted
2831 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2832 assembler would use $at as a temp to load in the large offset. In this
2833 case $at is already in use. We convert such problem addresses to
2834 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2835 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2836 #define CONSTANT_ADDRESS_P(X) \
2837 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2838 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2839 || (GET_CODE (X) == CONST \
2840 && ! (flag_pic && pic_address_needs_scratch (X)) \
2841 && (mips_abi == ABI_32 \
2842 || mips_abi == ABI_O64 \
2843 || mips_abi == ABI_EABI))) \
2844 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2846 /* Define this, so that when PIC, reload won't try to reload invalid
2847 addresses which require two reload registers. */
2849 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2851 /* Nonzero if the constant value X is a legitimate general operand.
2852 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2854 At present, GAS doesn't understand li.[sd], so don't allow it
2855 to be generated at present. Also, the MIPS assembler does not
2856 grok li.d Infinity. */
2858 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2859 Note that the Irix 6 assembler problem may already be fixed.
2860 Note also that the GET_CODE (X) == CONST test catches the mips16
2861 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2862 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2863 ABI_64 to work together, we'll need to fix this. */
2864 #define LEGITIMATE_CONSTANT_P(X) \
2865 ((GET_CODE (X) != CONST_DOUBLE \
2866 || mips_const_double_ok (X, GET_MODE (X))) \
2867 && ! (GET_CODE (X) == CONST \
2869 && (mips_abi == ABI_N32 \
2870 || mips_abi == ABI_64)) \
2871 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2873 /* A C compound statement that attempts to replace X with a valid
2874 memory address for an operand of mode MODE. WIN will be a C
2875 statement label elsewhere in the code; the macro definition may
2878 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2880 to avoid further processing if the address has become legitimate.
2882 X will always be the result of a call to `break_out_memory_refs',
2883 and OLDX will be the operand that was given to that function to
2886 The code generated by this macro should not alter the
2887 substructure of X. If it transforms X into a more legitimate
2888 form, it should assign X (which will always be a C variable) a
2891 It is not necessary for this macro to come up with a legitimate
2892 address. The compiler has standard ways of doing so in all
2893 cases. In fact, it is safe for this macro to do nothing. But
2894 often a machine-dependent strategy can generate better code.
2896 For the MIPS, transform:
2898 memory(X + <large int>)
2902 Y = <large int> & ~0x7fff;
2904 memory (Z + (<large int> & 0x7fff));
2906 This is for CSE to find several similar references, and only use one Z.
2908 When PIC, convert addresses of the form memory (symbol+large int) to
2909 memory (reg+large int). */
2912 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2914 register rtx xinsn = (X); \
2916 if (TARGET_DEBUG_B_MODE) \
2918 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2919 GO_DEBUG_RTX (xinsn); \
2922 if (mips_split_addresses && mips_check_split (X, MODE)) \
2924 /* ??? Is this ever executed? */ \
2925 X = gen_rtx_LO_SUM (Pmode, \
2926 copy_to_mode_reg (Pmode, \
2927 gen_rtx (HIGH, Pmode, X)), \
2932 if (GET_CODE (xinsn) == CONST \
2933 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2934 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2935 || (mips_abi != ABI_32 \
2936 && mips_abi != ABI_O64 \
2937 && mips_abi != ABI_EABI))) \
2939 rtx ptr_reg = gen_reg_rtx (Pmode); \
2940 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2942 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2944 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
2945 if (SMALL_INT (constant)) \
2947 /* Otherwise we fall through so the code below will fix the \
2952 if (GET_CODE (xinsn) == PLUS) \
2954 register rtx xplus0 = XEXP (xinsn, 0); \
2955 register rtx xplus1 = XEXP (xinsn, 1); \
2956 register enum rtx_code code0 = GET_CODE (xplus0); \
2957 register enum rtx_code code1 = GET_CODE (xplus1); \
2959 if (code0 != REG && code1 == REG) \
2961 xplus0 = XEXP (xinsn, 1); \
2962 xplus1 = XEXP (xinsn, 0); \
2963 code0 = GET_CODE (xplus0); \
2964 code1 = GET_CODE (xplus1); \
2967 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2968 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2970 rtx int_reg = gen_reg_rtx (Pmode); \
2971 rtx ptr_reg = gen_reg_rtx (Pmode); \
2973 emit_move_insn (int_reg, \
2974 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2976 emit_insn (gen_rtx_SET (VOIDmode, \
2978 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
2980 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
2985 if (TARGET_DEBUG_B_MODE) \
2986 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2990 /* A C statement or compound statement with a conditional `goto
2991 LABEL;' executed if memory address X (an RTX) can have different
2992 meanings depending on the machine mode of the memory reference it
2995 Autoincrement and autodecrement addresses typically have
2996 mode-dependent effects because the amount of the increment or
2997 decrement is the size of the operand being addressed. Some
2998 machines have other mode-dependent addresses. Many RISC machines
2999 have no mode-dependent addresses.
3001 You may assume that ADDR is a valid address for the machine. */
3003 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3006 /* Define this macro if references to a symbol must be treated
3007 differently depending on something about the variable or
3008 function named by the symbol (such as what section it is in).
3010 The macro definition, if any, is executed immediately after the
3011 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3012 The value of the rtl will be a `mem' whose address is a
3015 The usual thing for this macro to do is to a flag in the
3016 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3017 name string in the `symbol_ref' (if one bit is not enough
3020 The best way to modify the name string is by adding text to the
3021 beginning, with suitable punctuation to prevent any ambiguity.
3022 Allocate the new name in `saveable_obstack'. You will have to
3023 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3024 and output the name accordingly.
3026 You can also check the information stored in the `symbol_ref' in
3027 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3028 `PRINT_OPERAND_ADDRESS'.
3030 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3033 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3034 symbols which are not in the .text section.
3036 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3037 constants which are put in the .text section. We also record the
3038 total length of all such strings; this total is used to decide
3039 whether we need to split the constant table, and need not be
3042 When not mips16 code nor embedded PIC, if a symbol is in a
3043 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3044 splitting the reference so that gas can generate a gp relative
3047 When TARGET_EMBEDDED_DATA is set, we assume that all const
3048 variables will be stored in ROM, which is too far from %gp to use
3049 %gprel addressing. Note that (1) we include "extern const"
3050 variables in this, which mips_select_section doesn't, and (2) we
3051 can't always tell if they're really const (they might be const C++
3052 objects with non-const constructors), so we err on the side of
3053 caution and won't use %gprel anyway (otherwise we'd have to defer
3054 this decision to the linker/loader). The handling of extern consts
3055 is why the DECL_INITIAL macros differ from mips_select_section.
3057 If you are changing this macro, you should look at
3058 mips_select_section and see if it needs a similar change. */
3060 #ifndef UNIQUE_SECTION_P
3061 #define UNIQUE_SECTION_P(DECL) (0)
3064 #define ENCODE_SECTION_INFO(DECL) \
3067 if (TARGET_MIPS16) \
3069 if (TREE_CODE (DECL) == STRING_CST \
3070 && ! flag_writable_strings \
3071 /* If this string is from a function, and the function will \
3072 go in a gnu linkonce section, then we can't directly \
3073 access the string. This gets an assembler error \
3074 "unsupported PC relative reference to different section".\
3075 If we modify SELECT_SECTION to put it in function_section\
3076 instead of text_section, it still fails because \
3077 DECL_SECTION_NAME isn't set until assemble_start_function.\
3078 If we fix that, it still fails because strings are shared\
3079 among multiple functions, and we have cross section \
3080 references again. We force it to work by putting string \
3081 addresses in the constant pool and indirecting. */ \
3082 && (! current_function_decl \
3083 || ! UNIQUE_SECTION_P (current_function_decl))) \
3085 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3086 mips_string_length += TREE_STRING_LENGTH (DECL); \
3090 if (TARGET_EMBEDDED_DATA \
3091 && (TREE_CODE (DECL) == VAR_DECL \
3092 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3093 && (!DECL_INITIAL (DECL) \
3094 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3096 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3099 else if (TARGET_EMBEDDED_PIC) \
3101 if (TREE_CODE (DECL) == VAR_DECL) \
3102 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3103 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3104 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3105 else if (TREE_CODE (DECL) == STRING_CST \
3106 && ! flag_writable_strings) \
3107 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3109 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3112 else if (TREE_CODE (DECL) == VAR_DECL \
3113 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3114 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3116 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3119 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3122 /* We can not perform GP optimizations on variables which are in \
3123 specific sections, except for .sdata and .sbss which are \
3125 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3126 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3128 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3130 if (size > 0 && size <= mips_section_threshold) \
3131 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3134 else if (HALF_PIC_P ()) \
3136 HALF_PIC_ENCODE (DECL); \
3141 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3142 'the start of the function that this code is output in'. */
3144 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3145 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3146 asm_fprintf ((FILE), "%U%s", \
3147 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3149 asm_fprintf ((FILE), "%U%s", (NAME))
3151 /* The mips16 wants the constant pool to be after the function,
3152 because the PC relative load instructions use unsigned offsets. */
3154 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3156 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3157 mips_string_length = 0;
3160 /* In mips16 mode, put most string constants after the function. */
3161 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3162 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3165 /* Specify the machine mode that this machine uses
3166 for the index in the tablejump instruction.
3167 ??? Using HImode in mips16 mode can cause overflow. However, the
3168 overflow is no more likely than the overflow in a branch
3169 instruction. Large functions can currently break in both ways. */
3170 #define CASE_VECTOR_MODE \
3171 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3173 /* Define as C expression which evaluates to nonzero if the tablejump
3174 instruction expects the table to contain offsets from the address of the
3176 Do not define this if the table should contain absolute addresses. */
3177 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3179 /* Specify the tree operation to be used to convert reals to integers. */
3180 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3182 /* This is the kind of divide that is easiest to do in the general case. */
3183 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3185 /* Define this as 1 if `char' should by default be signed; else as 0. */
3186 #ifndef DEFAULT_SIGNED_CHAR
3187 #define DEFAULT_SIGNED_CHAR 1
3190 /* Max number of bytes we can move from memory to memory
3191 in one reasonably fast instruction. */
3192 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3193 #define MAX_MOVE_MAX 8
3195 /* Define this macro as a C expression which is nonzero if
3196 accessing less than a word of memory (i.e. a `char' or a
3197 `short') is no faster than accessing a word of memory, i.e., if
3198 such access require more than one instruction or if there is no
3199 difference in cost between byte and (aligned) word loads.
3201 On RISC machines, it tends to generate better code to define
3202 this as 1, since it avoids making a QI or HI mode register. */
3203 #define SLOW_BYTE_ACCESS 1
3205 /* We assume that the store-condition-codes instructions store 0 for false
3206 and some other value for true. This is the value stored for true. */
3208 #define STORE_FLAG_VALUE 1
3210 /* Define this if zero-extension is slow (more than one real instruction). */
3211 #define SLOW_ZERO_EXTEND
3213 /* Define this to be nonzero if shift instructions ignore all but the low-order
3215 #define SHIFT_COUNT_TRUNCATED 1
3217 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3218 is done just by pretending it is already truncated. */
3219 /* In 64 bit mode, 32 bit instructions require that register values be properly
3220 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3221 converts a value >32 bits to a value <32 bits. */
3222 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3223 Something needs to be done about this. Perhaps not use any 32 bit
3224 instructions? Perhaps use PROMOTE_MODE? */
3225 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3226 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3228 /* Specify the machine mode that pointers have.
3229 After generation of rtl, the compiler makes no further distinction
3230 between pointers and any other objects of this machine mode.
3232 For MIPS we make pointers are the smaller of longs and gp-registers. */
3235 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3238 /* A function address in a call instruction
3239 is a word address (for indexing purposes)
3240 so give the MEM rtx a words's mode. */
3242 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3244 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3245 memset, instead of the BSD functions bcopy and bzero. */
3247 #if defined(MIPS_SYSV) || defined(OSF_OS)
3248 #define TARGET_MEM_FUNCTIONS
3252 /* A part of a C `switch' statement that describes the relative
3253 costs of constant RTL expressions. It must contain `case'
3254 labels for expression codes `const_int', `const', `symbol_ref',
3255 `label_ref' and `const_double'. Each case must ultimately reach
3256 a `return' statement to return the relative cost of the use of
3257 that kind of constant value in an expression. The cost may
3258 depend on the precise value of the constant, which is available
3259 for examination in X.
3261 CODE is the expression code--redundant, since it can be obtained
3262 with `GET_CODE (X)'. */
3264 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3266 if (! TARGET_MIPS16) \
3268 /* Always return 0, since we don't have different sized \
3269 instructions, hence different costs according to Richard \
3273 if ((OUTER_CODE) == SET) \
3275 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3277 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3278 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3279 return COSTS_N_INSNS (1); \
3281 return COSTS_N_INSNS (2); \
3283 /* A PLUS could be an address. We don't want to force an address \
3284 to use a register, so accept any signed 16 bit value without \
3286 if ((OUTER_CODE) == PLUS \
3287 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3289 /* A number between 1 and 8 inclusive is efficient for a shift. \
3290 Otherwise, we will need an extended instruction. */ \
3291 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3292 || (OUTER_CODE) == LSHIFTRT) \
3294 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3296 return COSTS_N_INSNS (1); \
3298 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3299 if ((OUTER_CODE) == XOR \
3300 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3302 /* We may be able to use slt or sltu for a comparison with a \
3303 signed 16 bit value. (The boundary conditions aren't quite \
3304 right, but this is just a heuristic anyhow.) */ \
3305 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3306 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3307 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3308 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3309 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3311 /* Equality comparisons with 0 are cheap. */ \
3312 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3313 && INTVAL (X) == 0) \
3316 /* Otherwise, work out the cost to load the value into a \
3318 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3319 return COSTS_N_INSNS (1); \
3320 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3321 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3322 return COSTS_N_INSNS (2); \
3324 return COSTS_N_INSNS (3); \
3327 return COSTS_N_INSNS (2); \
3331 rtx offset = const0_rtx; \
3332 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3334 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3336 /* Treat this like a signed 16 bit CONST_INT. */ \
3337 if ((OUTER_CODE) == PLUS) \
3339 else if ((OUTER_CODE) == SET) \
3340 return COSTS_N_INSNS (1); \
3342 return COSTS_N_INSNS (2); \
3345 if (GET_CODE (symref) == LABEL_REF) \
3346 return COSTS_N_INSNS (2); \
3348 if (GET_CODE (symref) != SYMBOL_REF) \
3349 return COSTS_N_INSNS (4); \
3351 /* let's be paranoid.... */ \
3352 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3353 return COSTS_N_INSNS (2); \
3355 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3359 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3361 case CONST_DOUBLE: \
3364 if (TARGET_MIPS16) \
3365 return COSTS_N_INSNS (4); \
3366 split_double (X, &high, &low); \
3367 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3368 || low == CONST0_RTX (GET_MODE (low))) \
3372 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3373 This can be used, for example, to indicate how costly a multiply
3374 instruction is. In writing this macro, you can use the construct
3375 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3377 This macro is optional; do not define it if the default cost
3378 assumptions are adequate for the target machine.
3380 If -mdebugd is used, change the multiply cost to 2, so multiply by
3381 a constant isn't converted to a series of shifts. This helps
3382 strength reduction, and also makes it easier to identify what the
3383 compiler is doing. */
3385 /* ??? Fix this to be right for the R8000. */
3386 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3389 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3390 if (simple_memory_operand (X, GET_MODE (X))) \
3391 return COSTS_N_INSNS (num_words); \
3393 return COSTS_N_INSNS (2*num_words); \
3397 return COSTS_N_INSNS (6); \
3400 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3405 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3406 return COSTS_N_INSNS (2); \
3413 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3414 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3420 enum machine_mode xmode = GET_MODE (X); \
3421 if (xmode == SFmode || xmode == DFmode) \
3422 return COSTS_N_INSNS (1); \
3424 return COSTS_N_INSNS (4); \
3430 enum machine_mode xmode = GET_MODE (X); \
3431 if (xmode == SFmode || xmode == DFmode) \
3433 if (mips_cpu == PROCESSOR_R3000 \
3434 || mips_cpu == PROCESSOR_R3900) \
3435 return COSTS_N_INSNS (2); \
3436 else if (mips_cpu == PROCESSOR_R6000) \
3437 return COSTS_N_INSNS (3); \
3439 return COSTS_N_INSNS (6); \
3442 if (xmode == DImode && !TARGET_64BIT) \
3443 return COSTS_N_INSNS (4); \
3449 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3456 enum machine_mode xmode = GET_MODE (X); \
3457 if (xmode == SFmode) \
3459 if (mips_cpu == PROCESSOR_R3000 \
3460 || mips_cpu == PROCESSOR_R3900 \
3461 || mips_cpu == PROCESSOR_R5000) \
3462 return COSTS_N_INSNS (4); \
3463 else if (mips_cpu == PROCESSOR_R6000) \
3464 return COSTS_N_INSNS (5); \
3466 return COSTS_N_INSNS (7); \
3469 if (xmode == DFmode) \
3471 if (mips_cpu == PROCESSOR_R3000 \
3472 || mips_cpu == PROCESSOR_R3900 \
3473 || mips_cpu == PROCESSOR_R5000) \
3474 return COSTS_N_INSNS (5); \
3475 else if (mips_cpu == PROCESSOR_R6000) \
3476 return COSTS_N_INSNS (6); \
3478 return COSTS_N_INSNS (8); \
3481 if (mips_cpu == PROCESSOR_R3000) \
3482 return COSTS_N_INSNS (12); \
3483 else if (mips_cpu == PROCESSOR_R3900) \
3484 return COSTS_N_INSNS (2); \
3485 else if (mips_cpu == PROCESSOR_R6000) \
3486 return COSTS_N_INSNS (17); \
3487 else if (mips_cpu == PROCESSOR_R5000) \
3488 return COSTS_N_INSNS (5); \
3490 return COSTS_N_INSNS (10); \
3496 enum machine_mode xmode = GET_MODE (X); \
3497 if (xmode == SFmode) \
3499 if (mips_cpu == PROCESSOR_R3000 \
3500 || mips_cpu == PROCESSOR_R3900) \
3501 return COSTS_N_INSNS (12); \
3502 else if (mips_cpu == PROCESSOR_R6000) \
3503 return COSTS_N_INSNS (15); \
3505 return COSTS_N_INSNS (23); \
3508 if (xmode == DFmode) \
3510 if (mips_cpu == PROCESSOR_R3000 \
3511 || mips_cpu == PROCESSOR_R3900) \
3512 return COSTS_N_INSNS (19); \
3513 else if (mips_cpu == PROCESSOR_R6000) \
3514 return COSTS_N_INSNS (16); \
3516 return COSTS_N_INSNS (36); \
3519 /* fall through */ \
3523 if (mips_cpu == PROCESSOR_R3000 \
3524 || mips_cpu == PROCESSOR_R3900) \
3525 return COSTS_N_INSNS (35); \
3526 else if (mips_cpu == PROCESSOR_R6000) \
3527 return COSTS_N_INSNS (38); \
3528 else if (mips_cpu == PROCESSOR_R5000) \
3529 return COSTS_N_INSNS (36); \
3531 return COSTS_N_INSNS (69); \
3534 /* A sign extend from SImode to DImode in 64 bit mode is often \
3535 zero instructions, because the result can often be used \
3536 directly by another instruction; we'll call it one. */ \
3537 if (TARGET_64BIT && GET_MODE (X) == DImode \
3538 && GET_MODE (XEXP (X, 0)) == SImode) \
3539 return COSTS_N_INSNS (1); \
3541 return COSTS_N_INSNS (2); \
3544 if (TARGET_64BIT && GET_MODE (X) == DImode \
3545 && GET_MODE (XEXP (X, 0)) == SImode) \
3546 return COSTS_N_INSNS (2); \
3548 return COSTS_N_INSNS (1);
3550 /* An expression giving the cost of an addressing mode that
3551 contains ADDRESS. If not defined, the cost is computed from the
3552 form of the ADDRESS expression and the `CONST_COSTS' values.
3554 For most CISC machines, the default cost is a good approximation
3555 of the true cost of the addressing mode. However, on RISC
3556 machines, all instructions normally have the same length and
3557 execution time. Hence all addresses will have equal costs.
3559 In cases where more than one form of an address is known, the
3560 form with the lowest cost will be used. If multiple forms have
3561 the same, lowest, cost, the one that is the most complex will be
3564 For example, suppose an address that is equal to the sum of a
3565 register and a constant is used twice in the same basic block.
3566 When this macro is not defined, the address will be computed in
3567 a register and memory references will be indirect through that
3568 register. On machines where the cost of the addressing mode
3569 containing the sum is no higher than that of a simple indirect
3570 reference, this will produce an additional instruction and
3571 possibly require an additional register. Proper specification
3572 of this macro eliminates this overhead for such machines.
3574 Similar use of this macro is made in strength reduction of loops.
3576 ADDRESS need not be valid as an address. In such a case, the
3577 cost is not relevant and can be any value; invalid addresses
3578 need not be assigned a different cost.
3580 On machines where an address involving more than one register is
3581 as cheap as an address computation involving only one register,
3582 defining `ADDRESS_COST' to reflect this can cause two registers
3583 to be live over a region of code where only one would have been
3584 if `ADDRESS_COST' were not defined in that manner. This effect
3585 should be considered in the definition of this macro.
3586 Equivalent costs should probably only be given to addresses with
3587 different numbers of registers on machines with lots of registers.
3589 This macro will normally either not be defined or be defined as
3592 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3594 /* A C expression for the cost of moving data from a register in
3595 class FROM to one in class TO. The classes are expressed using
3596 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3597 the default; other values are interpreted relative to that.
3599 It is not required that the cost always equal 2 when FROM is the
3600 same as TO; on some machines it is expensive to move between
3601 registers if they are not general registers.
3603 If reload sees an insn consisting of a single `set' between two
3604 hard registers, and if `REGISTER_MOVE_COST' applied to their
3605 classes returns a value of 2, reload does not check to ensure
3606 that the constraints of the insn are met. Setting a cost of
3607 other than 2 will allow reload to verify that the constraints are
3608 met. You should do this if the `movM' pattern's constraints do
3609 not allow such copying.
3611 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3612 registers the same as for one of moving general registers to
3613 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3614 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3615 isn't clear if it is wise. And it might not work in all cases. We
3616 could solve the DImode LO reg problem by using a multiply, just like
3617 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3618 by using divide instructions. divu puts the remainder in the HI
3619 reg, so doing a divide by -1 will move the value in the HI reg for
3620 all values except -1. We could handle that case by using a signed
3621 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3622 compare/branch to test the input value to see which instruction we
3623 need to use. This gets pretty messy, but it is feasible. */
3625 #define REGISTER_MOVE_COST(FROM, TO) \
3626 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3627 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3628 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3629 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3630 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3631 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3632 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3633 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3634 : (((FROM) == HI_REG || (FROM) == LO_REG \
3635 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3636 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3637 : (((TO) == HI_REG || (TO) == LO_REG \
3638 || (TO) == MD_REGS || (TO) == HILO_REG) \
3639 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3640 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3641 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3644 /* ??? Fix this to be right for the R8000. */
3645 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3646 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3647 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3649 /* Define if copies to/from condition code registers should be avoided.
3651 This is needed for the MIPS because reload_outcc is not complete;
3652 it needs to handle cases where the source is a general or another
3653 condition code register. */
3654 #define AVOID_CCMODE_COPIES
3656 /* A C expression for the cost of a branch instruction. A value of
3657 1 is the default; other values are interpreted relative to that. */
3659 /* ??? Fix this to be right for the R8000. */
3660 #define BRANCH_COST \
3662 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3665 /* A C statement (sans semicolon) to update the integer variable COST
3666 based on the relationship between INSN that is dependent on
3667 DEP_INSN through the dependence LINK. The default is to make no
3668 adjustment to COST. On the MIPS, ignore the cost of anti- and
3669 output-dependencies. */
3671 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3672 if (REG_NOTE_KIND (LINK) != 0) \
3673 (COST) = 0; /* Anti or output dependence. */
3675 /* If defined, modifies the length assigned to instruction INSN as a
3676 function of the context in which it is used. LENGTH is an lvalue
3677 that contains the initially computed length of the insn and should
3678 be updated with the correct length of the insn. */
3679 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3680 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3683 /* Optionally define this if you have added predicates to
3684 `MACHINE.c'. This macro is called within an initializer of an
3685 array of structures. The first field in the structure is the
3686 name of a predicate and the second field is an array of rtl
3687 codes. For each predicate, list all rtl codes that can be in
3688 expressions matched by the predicate. The list should have a
3689 trailing comma. Here is an example of two entries in the list
3690 for a typical RISC machine:
3692 #define PREDICATE_CODES \
3693 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3694 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3696 Defining this macro does not affect the generated code (however,
3697 incorrect definitions that omit an rtl code that may be matched
3698 by the predicate can cause the compiler to malfunction).
3699 Instead, it allows the table built by `genrecog' to be more
3700 compact and efficient, thus speeding up the compiler. The most
3701 important predicates to include in the list specified by this
3702 macro are thoses used in the most insn patterns. */
3704 #define PREDICATE_CODES \
3705 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3706 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3707 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3708 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3709 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3710 {"small_int", { CONST_INT }}, \
3711 {"large_int", { CONST_INT }}, \
3712 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3713 {"const_float_1_operand", { CONST_DOUBLE }}, \
3714 {"simple_memory_operand", { MEM, SUBREG }}, \
3715 {"equality_op", { EQ, NE }}, \
3716 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3718 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3719 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3720 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3721 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3722 SYMBOL_REF, LABEL_REF, SUBREG, \
3724 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3725 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3726 MEM, SIGN_EXTEND }}, \
3727 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3728 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3730 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3732 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3734 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3735 SYMBOL_REF, LABEL_REF, SUBREG, \
3736 REG, SIGN_EXTEND }}, \
3737 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3738 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3739 CONST_DOUBLE, CONST }}, \
3740 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3741 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3743 /* A list of predicates that do special things with modes, and so
3744 should not elicit warnings for VOIDmode match_operand. */
3746 #define SPECIAL_MODE_PREDICATES \
3747 "pc_or_label_operand",
3750 /* If defined, a C statement to be executed just prior to the
3751 output of assembler code for INSN, to modify the extracted
3752 operands so they will be output differently.
3754 Here the argument OPVEC is the vector containing the operands
3755 extracted from INSN, and NOPERANDS is the number of elements of
3756 the vector which contain meaningful data for this insn. The
3757 contents of this vector are what will be used to convert the
3758 insn template into assembler code, so you can change the
3759 assembler output by changing the contents of the vector.
3761 We use it to check if the current insn needs a nop in front of it
3762 because of load delays, and also to update the delay slot
3765 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3766 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3769 /* Control the assembler format that we output. */
3771 /* Output at beginning of assembler file.
3772 If we are optimizing to use the global pointer, create a temporary
3773 file to hold all of the text stuff, and write it out to the end.
3774 This is needed because the MIPS assembler is evidently one pass,
3775 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3776 declaration when the code is processed, it generates a two
3777 instruction sequence. */
3779 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3781 /* Output to assembler file text saying following lines
3782 may contain character constants, extra white space, comments, etc. */
3784 #define ASM_APP_ON " #APP\n"
3786 /* Output to assembler file text saying following lines
3787 no longer contain unusual constructs. */
3789 #define ASM_APP_OFF " #NO_APP\n"
3791 /* How to refer to registers in assembler output.
3792 This sequence is indexed by compiler's hard-register-number (see above).
3794 In order to support the two different conventions for register names,
3795 we use the name of a table set up in mips.c, which is overwritten
3796 if -mrnames is used. */
3798 #define REGISTER_NAMES \
3800 &mips_reg_names[ 0][0], \
3801 &mips_reg_names[ 1][0], \
3802 &mips_reg_names[ 2][0], \
3803 &mips_reg_names[ 3][0], \
3804 &mips_reg_names[ 4][0], \
3805 &mips_reg_names[ 5][0], \
3806 &mips_reg_names[ 6][0], \
3807 &mips_reg_names[ 7][0], \
3808 &mips_reg_names[ 8][0], \
3809 &mips_reg_names[ 9][0], \
3810 &mips_reg_names[10][0], \
3811 &mips_reg_names[11][0], \
3812 &mips_reg_names[12][0], \
3813 &mips_reg_names[13][0], \
3814 &mips_reg_names[14][0], \
3815 &mips_reg_names[15][0], \
3816 &mips_reg_names[16][0], \
3817 &mips_reg_names[17][0], \
3818 &mips_reg_names[18][0], \
3819 &mips_reg_names[19][0], \
3820 &mips_reg_names[20][0], \
3821 &mips_reg_names[21][0], \
3822 &mips_reg_names[22][0], \
3823 &mips_reg_names[23][0], \
3824 &mips_reg_names[24][0], \
3825 &mips_reg_names[25][0], \
3826 &mips_reg_names[26][0], \
3827 &mips_reg_names[27][0], \
3828 &mips_reg_names[28][0], \
3829 &mips_reg_names[29][0], \
3830 &mips_reg_names[30][0], \
3831 &mips_reg_names[31][0], \
3832 &mips_reg_names[32][0], \
3833 &mips_reg_names[33][0], \
3834 &mips_reg_names[34][0], \
3835 &mips_reg_names[35][0], \
3836 &mips_reg_names[36][0], \
3837 &mips_reg_names[37][0], \
3838 &mips_reg_names[38][0], \
3839 &mips_reg_names[39][0], \
3840 &mips_reg_names[40][0], \
3841 &mips_reg_names[41][0], \
3842 &mips_reg_names[42][0], \
3843 &mips_reg_names[43][0], \
3844 &mips_reg_names[44][0], \
3845 &mips_reg_names[45][0], \
3846 &mips_reg_names[46][0], \
3847 &mips_reg_names[47][0], \
3848 &mips_reg_names[48][0], \
3849 &mips_reg_names[49][0], \
3850 &mips_reg_names[50][0], \
3851 &mips_reg_names[51][0], \
3852 &mips_reg_names[52][0], \
3853 &mips_reg_names[53][0], \
3854 &mips_reg_names[54][0], \
3855 &mips_reg_names[55][0], \
3856 &mips_reg_names[56][0], \
3857 &mips_reg_names[57][0], \
3858 &mips_reg_names[58][0], \
3859 &mips_reg_names[59][0], \
3860 &mips_reg_names[60][0], \
3861 &mips_reg_names[61][0], \
3862 &mips_reg_names[62][0], \
3863 &mips_reg_names[63][0], \
3864 &mips_reg_names[64][0], \
3865 &mips_reg_names[65][0], \
3866 &mips_reg_names[66][0], \
3867 &mips_reg_names[67][0], \
3868 &mips_reg_names[68][0], \
3869 &mips_reg_names[69][0], \
3870 &mips_reg_names[70][0], \
3871 &mips_reg_names[71][0], \
3872 &mips_reg_names[72][0], \
3873 &mips_reg_names[73][0], \
3874 &mips_reg_names[74][0], \
3875 &mips_reg_names[75][0], \
3878 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3879 So define this for it. */
3880 #define DEBUG_REGISTER_NAMES \
3882 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3883 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3884 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3885 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3886 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3887 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3888 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3889 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3890 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3891 "$fcc5","$fcc6","$fcc7","$rap" \
3894 /* If defined, a C initializer for an array of structures
3895 containing a name and a register number. This macro defines
3896 additional names for hard registers, thus allowing the `asm'
3897 option in declarations to refer to registers using alternate
3900 We define both names for the integer registers here. */
3902 #define ADDITIONAL_REGISTER_NAMES \
3904 { "$0", 0 + GP_REG_FIRST }, \
3905 { "$1", 1 + GP_REG_FIRST }, \
3906 { "$2", 2 + GP_REG_FIRST }, \
3907 { "$3", 3 + GP_REG_FIRST }, \
3908 { "$4", 4 + GP_REG_FIRST }, \
3909 { "$5", 5 + GP_REG_FIRST }, \
3910 { "$6", 6 + GP_REG_FIRST }, \
3911 { "$7", 7 + GP_REG_FIRST }, \
3912 { "$8", 8 + GP_REG_FIRST }, \
3913 { "$9", 9 + GP_REG_FIRST }, \
3914 { "$10", 10 + GP_REG_FIRST }, \
3915 { "$11", 11 + GP_REG_FIRST }, \
3916 { "$12", 12 + GP_REG_FIRST }, \
3917 { "$13", 13 + GP_REG_FIRST }, \
3918 { "$14", 14 + GP_REG_FIRST }, \
3919 { "$15", 15 + GP_REG_FIRST }, \
3920 { "$16", 16 + GP_REG_FIRST }, \
3921 { "$17", 17 + GP_REG_FIRST }, \
3922 { "$18", 18 + GP_REG_FIRST }, \
3923 { "$19", 19 + GP_REG_FIRST }, \
3924 { "$20", 20 + GP_REG_FIRST }, \
3925 { "$21", 21 + GP_REG_FIRST }, \
3926 { "$22", 22 + GP_REG_FIRST }, \
3927 { "$23", 23 + GP_REG_FIRST }, \
3928 { "$24", 24 + GP_REG_FIRST }, \
3929 { "$25", 25 + GP_REG_FIRST }, \
3930 { "$26", 26 + GP_REG_FIRST }, \
3931 { "$27", 27 + GP_REG_FIRST }, \
3932 { "$28", 28 + GP_REG_FIRST }, \
3933 { "$29", 29 + GP_REG_FIRST }, \
3934 { "$30", 30 + GP_REG_FIRST }, \
3935 { "$31", 31 + GP_REG_FIRST }, \
3936 { "$sp", 29 + GP_REG_FIRST }, \
3937 { "$fp", 30 + GP_REG_FIRST }, \
3938 { "at", 1 + GP_REG_FIRST }, \
3939 { "v0", 2 + GP_REG_FIRST }, \
3940 { "v1", 3 + GP_REG_FIRST }, \
3941 { "a0", 4 + GP_REG_FIRST }, \
3942 { "a1", 5 + GP_REG_FIRST }, \
3943 { "a2", 6 + GP_REG_FIRST }, \
3944 { "a3", 7 + GP_REG_FIRST }, \
3945 { "t0", 8 + GP_REG_FIRST }, \
3946 { "t1", 9 + GP_REG_FIRST }, \
3947 { "t2", 10 + GP_REG_FIRST }, \
3948 { "t3", 11 + GP_REG_FIRST }, \
3949 { "t4", 12 + GP_REG_FIRST }, \
3950 { "t5", 13 + GP_REG_FIRST }, \
3951 { "t6", 14 + GP_REG_FIRST }, \
3952 { "t7", 15 + GP_REG_FIRST }, \
3953 { "s0", 16 + GP_REG_FIRST }, \
3954 { "s1", 17 + GP_REG_FIRST }, \
3955 { "s2", 18 + GP_REG_FIRST }, \
3956 { "s3", 19 + GP_REG_FIRST }, \
3957 { "s4", 20 + GP_REG_FIRST }, \
3958 { "s5", 21 + GP_REG_FIRST }, \
3959 { "s6", 22 + GP_REG_FIRST }, \
3960 { "s7", 23 + GP_REG_FIRST }, \
3961 { "t8", 24 + GP_REG_FIRST }, \
3962 { "t9", 25 + GP_REG_FIRST }, \
3963 { "k0", 26 + GP_REG_FIRST }, \
3964 { "k1", 27 + GP_REG_FIRST }, \
3965 { "gp", 28 + GP_REG_FIRST }, \
3966 { "sp", 29 + GP_REG_FIRST }, \
3967 { "fp", 30 + GP_REG_FIRST }, \
3968 { "ra", 31 + GP_REG_FIRST }, \
3969 { "$sp", 29 + GP_REG_FIRST }, \
3970 { "$fp", 30 + GP_REG_FIRST } \
3973 /* Define results of standard character escape sequences. */
3974 #define TARGET_BELL 007
3975 #define TARGET_BS 010
3976 #define TARGET_TAB 011
3977 #define TARGET_NEWLINE 012
3978 #define TARGET_VT 013
3979 #define TARGET_FF 014
3980 #define TARGET_CR 015
3982 /* A C compound statement to output to stdio stream STREAM the
3983 assembler syntax for an instruction operand X. X is an RTL
3986 CODE is a value that can be used to specify one of several ways
3987 of printing the operand. It is used when identical operands
3988 must be printed differently depending on the context. CODE
3989 comes from the `%' specification that was used to request
3990 printing of the operand. If the specification was just `%DIGIT'
3991 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3992 is the ASCII code for LTR.
3994 If X is a register, this macro should print the register's name.
3995 The names can be found in an array `reg_names' whose type is
3996 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3998 When the machine description has a specification `%PUNCT' (a `%'
3999 followed by a punctuation character), this macro is called with
4000 a null pointer for X and the punctuation character for CODE.
4002 See mips.c for the MIPS specific codes. */
4004 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4006 /* A C expression which evaluates to true if CODE is a valid
4007 punctuation character for use in the `PRINT_OPERAND' macro. If
4008 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4009 punctuation characters (except for the standard one, `%') are
4010 used in this way. */
4012 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4014 /* A C compound statement to output to stdio stream STREAM the
4015 assembler syntax for an instruction operand that is a memory
4016 reference whose address is ADDR. ADDR is an RTL expression.
4018 On some machines, the syntax for a symbolic address depends on
4019 the section that the address refers to. On these machines,
4020 define the macro `ENCODE_SECTION_INFO' to store the information
4021 into the `symbol_ref', and then check for it here. */
4023 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4026 /* A C statement, to be executed after all slot-filler instructions
4027 have been output. If necessary, call `dbr_sequence_length' to
4028 determine the number of slots filled in a sequence (zero if not
4029 currently outputting a sequence), to decide how many no-ops to
4030 output, or whatever.
4032 Don't define this macro if it has nothing to do, but it is
4033 helpful in reading assembly output if the extent of the delay
4034 sequence is made explicit (e.g. with white space).
4036 Note that output routines for instructions with delay slots must
4037 be prepared to deal with not being output as part of a sequence
4038 (i.e. when the scheduling pass is not run, or when no slot
4039 fillers could be found.) The variable `final_sequence' is null
4040 when not processing a sequence, otherwise it contains the
4041 `sequence' rtx being output. */
4043 #define DBR_OUTPUT_SEQEND(STREAM) \
4046 if (set_nomacro > 0 && --set_nomacro == 0) \
4047 fputs ("\t.set\tmacro\n", STREAM); \
4049 if (set_noreorder > 0 && --set_noreorder == 0) \
4050 fputs ("\t.set\treorder\n", STREAM); \
4052 dslots_jump_filled++; \
4053 fputs ("\n", STREAM); \
4058 /* How to tell the debugger about changes of source files. Note, the
4059 mips ECOFF format cannot deal with changes of files inside of
4060 functions, which means the output of parser generators like bison
4061 is generally not debuggable without using the -l switch. Lose,
4062 lose, lose. Silicon graphics seems to want all .file's hardwired
4065 #ifndef SET_FILE_NUMBER
4066 #define SET_FILE_NUMBER() ++num_source_filenames
4069 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4070 mips_output_filename (STREAM, NAME)
4072 /* This is defined so that it can be overridden in iris6.h. */
4073 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4076 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4077 output_quoted_string (STREAM, NAME); \
4078 fputs ("\n", STREAM); \
4082 /* This is how to output a note the debugger telling it the line number
4083 to which the following sequence of instructions corresponds.
4084 Silicon graphics puts a label after each .loc. */
4086 #ifndef LABEL_AFTER_LOC
4087 #define LABEL_AFTER_LOC(STREAM)
4090 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4091 mips_output_lineno (STREAM, LINE)
4093 /* The MIPS implementation uses some labels for its own purpose. The
4094 following lists what labels are created, and are all formed by the
4095 pattern $L[a-z].*. The machine independent portion of GCC creates
4096 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4098 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4099 $Lb[0-9]+ Begin blocks for MIPS debug support
4100 $Lc[0-9]+ Label for use in s<xx> operation.
4101 $Le[0-9]+ End blocks for MIPS debug support
4102 $Lp\..+ Half-pic labels. */
4104 /* This is how to output the definition of a user-level label named NAME,
4105 such as the label on a static function or variable NAME.
4107 If we are optimizing the gp, remember that this label has been put
4108 out, so we know not to emit an .extern for it in mips_asm_file_end.
4109 We use one of the common bits in the IDENTIFIER tree node for this,
4110 since those bits seem to be unused, and we don't have any method
4111 of getting the decl nodes from the name. */
4113 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4115 assemble_name (STREAM, NAME); \
4116 fputs (":\n", STREAM); \
4120 /* A C statement (sans semicolon) to output to the stdio stream
4121 STREAM any text necessary for declaring the name NAME of an
4122 initialized variable which is being defined. This macro must
4123 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4124 The argument DECL is the `VAR_DECL' tree node representing the
4127 If this macro is not defined, then the variable name is defined
4128 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4130 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4133 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4134 HALF_PIC_DECLARE (NAME); \
4139 /* This is how to output a command to make the user-level label named NAME
4140 defined for reference from other files. */
4142 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4144 fputs ("\t.globl\t", STREAM); \
4145 assemble_name (STREAM, NAME); \
4146 fputs ("\n", STREAM); \
4149 /* This says how to define a global common symbol. */
4151 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4153 /* If the target wants uninitialized const declarations in \
4154 .rdata then don't put them in .comm */ \
4155 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4156 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4157 && (DECL_INITIAL (DECL) == 0 \
4158 || DECL_INITIAL (DECL) == error_mark_node)) \
4160 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4161 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4163 READONLY_DATA_SECTION (); \
4164 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4165 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4169 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4174 /* This says how to define a local common symbol (ie, not visible to
4177 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4178 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4181 /* This says how to output an external. It would be possible not to
4182 output anything and let undefined symbol become external. However
4183 the assembler uses length information on externals to allocate in
4184 data/sdata bss/sbss, thereby saving exec time. */
4186 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4187 mips_output_external(STREAM,DECL,NAME)
4189 /* This says what to print at the end of the assembly file */
4190 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4193 /* This is how to declare a function name. The actual work of
4194 emitting the label is moved to function_prologue, so that we can
4195 get the line number correctly emitted before the .ent directive,
4196 and after any .file directives.
4198 Also, switch files if we are optimizing the global pointer. */
4200 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4202 extern FILE *asm_out_text_file; \
4203 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4205 STREAM = asm_out_text_file; \
4206 /* ??? text_section gets called too soon. If the previous \
4207 function is in a special section and we're not, we have \
4208 to switch back to the text section. We can't call \
4209 text_section again as gcc thinks we're already there. */ \
4210 /* ??? See varasm.c. There are other things that get output \
4211 too early, like alignment (before we've switched STREAM). */ \
4212 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4213 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4216 HALF_PIC_DECLARE (NAME); \
4219 /* This is how to output an internal numbered label where
4220 PREFIX is the class of label and NUM is the number within the class. */
4222 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4223 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4225 /* This is how to store into the string LABEL
4226 the symbol_ref name of an internal numbered label where
4227 PREFIX is the class of label and NUM is the number within the class.
4228 This is suitable for output with `assemble_name'. */
4230 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4231 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4233 /* This is how to output an assembler line defining a `double' constant. */
4235 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4236 mips_output_double (STREAM, VALUE)
4239 /* This is how to output an assembler line defining a `float' constant. */
4241 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4242 mips_output_float (STREAM, VALUE)
4245 /* This is how to output an assembler line defining an `int' constant. */
4247 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4249 fprintf (STREAM, "\t.word\t"); \
4250 output_addr_const (STREAM, (VALUE)); \
4251 fprintf (STREAM, "\n"); \
4254 /* Likewise for 64 bit, `char' and `short' constants.
4256 FIXME: operand_subword can't handle some complex constant expressions
4257 that output_addr_const can (for example it does not call
4258 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4259 rely on that to avoid operand_subword for most of the cases where this
4260 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4261 or the same case with the type of 'i' changed to long long.
4265 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4267 if (TARGET_64BIT || TARGET_GAS) \
4269 fprintf (STREAM, "\t.dword\t"); \
4270 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4271 /* We can't use 'X' for negative numbers, because then we won't \
4272 get the right value for the upper 32 bits. */ \
4273 output_addr_const (STREAM, VALUE); \
4275 /* We must use 'X', because otherwise LONG_MIN will print as \
4276 a number that the Irix 6 assembler won't accept. */ \
4277 print_operand (STREAM, VALUE, 'X'); \
4278 fprintf (STREAM, "\n"); \
4282 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4283 UNITS_PER_WORD, 1); \
4284 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4285 UNITS_PER_WORD, 1); \
4289 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4291 fprintf (STREAM, "\t.half\t"); \
4292 output_addr_const (STREAM, (VALUE)); \
4293 fprintf (STREAM, "\n"); \
4296 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4298 fprintf (STREAM, "\t.byte\t"); \
4299 output_addr_const (STREAM, (VALUE)); \
4300 fprintf (STREAM, "\n"); \
4303 /* This is how to output an assembler line for a numeric constant byte. */
4305 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4306 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4308 /* This is how to output an element of a case-vector that is absolute. */
4310 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4311 fprintf (STREAM, "\t%s\t%sL%d\n", \
4312 Pmode == DImode ? ".dword" : ".word", \
4313 LOCAL_LABEL_PREFIX, \
4316 /* This is how to output an element of a case-vector that is relative.
4317 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4318 TARGET_EMBEDDED_PIC). */
4320 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4322 if (TARGET_MIPS16) \
4323 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4324 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4325 else if (TARGET_EMBEDDED_PIC) \
4326 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4327 Pmode == DImode ? ".dword" : ".word", \
4328 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4329 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4330 fprintf (STREAM, "\t%s\t%sL%d\n", \
4331 Pmode == DImode ? ".gpdword" : ".gpword", \
4332 LOCAL_LABEL_PREFIX, VALUE); \
4334 fprintf (STREAM, "\t%s\t%sL%d\n", \
4335 Pmode == DImode ? ".dword" : ".word", \
4336 LOCAL_LABEL_PREFIX, VALUE); \
4339 /* When generating embedded PIC or mips16 code we want to put the jump
4340 table in the .text section. In all other cases, we want to put the
4341 jump table in the .rdata section. Unfortunately, we can't use
4342 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4343 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4344 section if appropriate. */
4345 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4347 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4348 function_section (current_function_decl); \
4349 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4352 /* This is how to output an assembler line
4353 that says to advance the location counter
4354 to a multiple of 2**LOG bytes. */
4356 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4357 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4359 /* This is how to output an assembler line to advance the location
4360 counter by SIZE bytes. */
4362 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4363 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4365 /* This is how to output a string. */
4366 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4368 register int i, c, len = (LEN), cur_pos = 17; \
4369 register const unsigned char *string = \
4370 (const unsigned char *)(STRING); \
4371 fprintf ((STREAM), "\t.ascii\t\""); \
4372 for (i = 0; i < len; i++) \
4374 register int c = string[i]; \
4380 putc ('\\', (STREAM)); \
4381 putc (c, (STREAM)); \
4385 case TARGET_NEWLINE: \
4386 fputs ("\\n", (STREAM)); \
4388 && (((c = string[i+1]) >= '\040' && c <= '~') \
4389 || c == TARGET_TAB)) \
4390 cur_pos = 32767; /* break right here */ \
4396 fputs ("\\t", (STREAM)); \
4401 fputs ("\\f", (STREAM)); \
4406 fputs ("\\b", (STREAM)); \
4411 fputs ("\\r", (STREAM)); \
4416 if (c >= ' ' && c < 0177) \
4418 putc (c, (STREAM)); \
4423 fprintf ((STREAM), "\\%03o", c); \
4428 if (cur_pos > 72 && i+1 < len) \
4431 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4434 fprintf ((STREAM), "\"\n"); \
4437 /* Handle certain cpp directives used in header files on sysV. */
4438 #define SCCS_DIRECTIVE
4440 /* Output #ident as a in the read-only data section. */
4441 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4443 const char *p = STRING; \
4444 int size = strlen (p) + 1; \
4446 assemble_string (p, size); \
4449 /* Default to -G 8 */
4450 #ifndef MIPS_DEFAULT_GVALUE
4451 #define MIPS_DEFAULT_GVALUE 8
4454 /* Define the strings to put out for each section in the object file. */
4455 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4456 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4457 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4458 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4459 #define READONLY_DATA_SECTION rdata_section
4460 #define SMALL_DATA_SECTION sdata_section
4462 /* What other sections we support other than the normal .data/.text. */
4464 #define EXTRA_SECTIONS in_sdata, in_rdata
4466 /* Define the additional functions to select our additional sections. */
4468 /* on the MIPS it is not a good idea to put constants in the text
4469 section, since this defeats the sdata/data mechanism. This is
4470 especially true when -O is used. In this case an effort is made to
4471 address with faster (gp) register relative addressing, which can
4472 only get at sdata and sbss items (there is no stext !!) However,
4473 if the constant is too large for sdata, and it's readonly, it
4474 will go into the .rdata section. */
4476 #define EXTRA_SECTION_FUNCTIONS \
4480 if (in_section != in_sdata) \
4482 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4483 in_section = in_sdata; \
4490 if (in_section != in_rdata) \
4492 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4493 in_section = in_rdata; \
4497 /* Given a decl node or constant node, choose the section to output it in
4498 and select that section. */
4500 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4502 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4505 /* Store in OUTPUT a string (made with alloca) containing
4506 an assembler-name for a local static variable named NAME.
4507 LABELNO is an integer which is different for each call. */
4509 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4510 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4511 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4513 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4516 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4517 TARGET_64BIT ? "dsubu" : "subu", \
4518 reg_names[STACK_POINTER_REGNUM], \
4519 reg_names[STACK_POINTER_REGNUM], \
4520 TARGET_64BIT ? "sd" : "sw", \
4522 reg_names[STACK_POINTER_REGNUM]); \
4526 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4529 if (! set_noreorder) \
4530 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4532 dslots_load_total++; \
4533 dslots_load_filled++; \
4534 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4535 TARGET_64BIT ? "ld" : "lw", \
4537 reg_names[STACK_POINTER_REGNUM], \
4538 TARGET_64BIT ? "daddu" : "addu", \
4539 reg_names[STACK_POINTER_REGNUM], \
4540 reg_names[STACK_POINTER_REGNUM]); \
4542 if (! set_noreorder) \
4543 fprintf (STREAM, "\t.set\treorder\n"); \
4547 /* Define the parentheses used to group arithmetic operations
4548 in assembler code. */
4550 #define ASM_OPEN_PAREN "("
4551 #define ASM_CLOSE_PAREN ")"
4553 /* How to start an assembler comment.
4554 The leading space is important (the mips native assembler requires it). */
4555 #ifndef ASM_COMMENT_START
4556 #define ASM_COMMENT_START " #"
4560 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4561 and mips-tdump.c to print them out.
4563 These must match the corresponding definitions in gdb/mipsread.c.
4564 Unfortunately, gcc and gdb do not currently share any directories. */
4566 #define CODE_MASK 0x8F300
4567 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4568 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4569 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4572 /* Default definitions for size_t and ptrdiff_t. */
4575 #define NO_BUILTIN_SIZE_TYPE
4576 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4579 #ifndef PTRDIFF_TYPE
4580 #define NO_BUILTIN_PTRDIFF_TYPE
4581 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4584 /* See mips_expand_prologue's use of loadgp for when this should be
4587 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4588 && mips_abi != ABI_32 \
4589 && mips_abi != ABI_O64)
4591 /* In mips16 mode, we need to look through the function to check for
4592 PC relative loads that are out of range. */
4593 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4595 /* We need to use a special set of functions to handle hard floating
4596 point code in mips16 mode. */
4598 #ifndef INIT_SUBTARGET_OPTABS
4599 #define INIT_SUBTARGET_OPTABS
4602 #define INIT_TARGET_OPTABS \
4605 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4606 INIT_SUBTARGET_OPTABS; \
4609 add_optab->handlers[(int) SFmode].libfunc = \
4610 init_one_libfunc ("__mips16_addsf3"); \
4611 sub_optab->handlers[(int) SFmode].libfunc = \
4612 init_one_libfunc ("__mips16_subsf3"); \
4613 smul_optab->handlers[(int) SFmode].libfunc = \
4614 init_one_libfunc ("__mips16_mulsf3"); \
4615 flodiv_optab->handlers[(int) SFmode].libfunc = \
4616 init_one_libfunc ("__mips16_divsf3"); \
4618 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4619 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4620 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4621 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4622 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4623 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4625 floatsisf_libfunc = \
4626 init_one_libfunc ("__mips16_floatsisf"); \
4628 init_one_libfunc ("__mips16_fixsfsi"); \
4630 if (TARGET_DOUBLE_FLOAT) \
4632 add_optab->handlers[(int) DFmode].libfunc = \
4633 init_one_libfunc ("__mips16_adddf3"); \
4634 sub_optab->handlers[(int) DFmode].libfunc = \
4635 init_one_libfunc ("__mips16_subdf3"); \
4636 smul_optab->handlers[(int) DFmode].libfunc = \
4637 init_one_libfunc ("__mips16_muldf3"); \
4638 flodiv_optab->handlers[(int) DFmode].libfunc = \
4639 init_one_libfunc ("__mips16_divdf3"); \
4641 extendsfdf2_libfunc = \
4642 init_one_libfunc ("__mips16_extendsfdf2"); \
4643 truncdfsf2_libfunc = \
4644 init_one_libfunc ("__mips16_truncdfsf2"); \
4647 init_one_libfunc ("__mips16_eqdf2"); \
4649 init_one_libfunc ("__mips16_nedf2"); \
4651 init_one_libfunc ("__mips16_gtdf2"); \
4653 init_one_libfunc ("__mips16_gedf2"); \
4655 init_one_libfunc ("__mips16_ltdf2"); \
4657 init_one_libfunc ("__mips16_ledf2"); \
4659 floatsidf_libfunc = \
4660 init_one_libfunc ("__mips16_floatsidf"); \
4662 init_one_libfunc ("__mips16_fixdfsi"); \
OSDN Git Service
