1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
137 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
138 extern int mips_isa; /* architectural level */
139 extern int mips16; /* whether generating mips16 code */
140 extern int mips16_hard_float; /* mips16 without -msoft-float */
141 extern int mips_entry; /* generate entry/exit for mips16 */
142 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
143 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
144 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
145 extern const char *mips_entry_string; /* for -mentry */
146 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
147 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
148 extern int mips_split_addresses; /* perform high/lo_sum support */
149 extern int dslots_load_total; /* total # load related delay slots */
150 extern int dslots_load_filled; /* # filled load delay slots */
151 extern int dslots_jump_total; /* total # jump related delay slots */
152 extern int dslots_jump_filled; /* # filled jump delay slots */
153 extern int dslots_number_nops; /* # of nops needed by previous insn */
154 extern int num_refs[3]; /* # 1/2/3 word references */
155 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
156 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
157 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
158 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
159 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
160 extern int mips_string_length; /* length of strings for mips16 */
161 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
163 /* Functions to change what output section we are using. */
164 extern void rdata_section PARAMS ((void));
165 extern void sdata_section PARAMS ((void));
166 extern void sbss_section PARAMS ((void));
168 /* Stubs for half-pic support if not OSF/1 reference platform. */
171 #define HALF_PIC_P() 0
172 #define HALF_PIC_NUMBER_PTRS 0
173 #define HALF_PIC_NUMBER_REFS 0
174 #define HALF_PIC_ENCODE(DECL)
175 #define HALF_PIC_DECLARE(NAME)
176 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
177 #define HALF_PIC_ADDRESS_P(X) 0
178 #define HALF_PIC_PTR(X) X
179 #define HALF_PIC_FINISH(STREAM)
182 /* Macros to silence warnings about numbers being signed in traditional
183 C and unsigned in ISO C when compiled on 32-bit hosts. */
185 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
186 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
187 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
190 /* Run-time compilation parameters selecting different hardware subsets. */
192 /* Macros used in the machine description to test the flags. */
194 /* Bits for real switches */
195 #define MASK_INT64 0x00000001 /* ints are 64 bits */
196 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
197 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
198 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
199 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
200 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
201 #define MASK_STATS 0x00000040 /* print statistics to stderr */
202 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
203 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
204 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
205 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
206 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
207 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
208 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
209 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
210 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
211 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
212 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
213 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
214 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
215 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
216 #define MASK_MIPS16 0x00200000 /* Generate mips16 code */
217 #define MASK_NO_CHECK_ZERO_DIV \
218 0x00400000 /* divide by zero checking */
219 #define MASK_CHECK_RANGE_DIV \
220 0x00800000 /* divide result range checking */
221 #define MASK_UNINIT_CONST_IN_RODATA \
222 0x01000000 /* Store uninitialized
225 /* Debug switches, not documented */
226 #define MASK_DEBUG 0 /* unused */
227 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
228 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
229 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
230 #define MASK_DEBUG_D 0 /* don't do define_split's */
231 #define MASK_DEBUG_E 0 /* function_arg debug */
232 #define MASK_DEBUG_F 0 /* ??? */
233 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
234 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
235 #define MASK_DEBUG_I 0 /* unused */
237 /* Dummy switches used only in specs */
238 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
240 /* r4000 64 bit sizes */
241 #define TARGET_INT64 (target_flags & MASK_INT64)
242 #define TARGET_LONG64 (target_flags & MASK_LONG64)
243 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
244 #define TARGET_64BIT (target_flags & MASK_64BIT)
246 /* Mips vs. GNU linker */
247 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
249 /* generate mips 3900 insns */
250 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
252 /* Mips vs. GNU assembler */
253 #define TARGET_GAS (target_flags & MASK_GAS)
254 #define TARGET_MIPS_AS (!TARGET_GAS)
257 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
258 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
259 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
260 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
261 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
262 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
263 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
264 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
265 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
266 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
268 /* Reg. Naming in .s ($21 vs. $a0) */
269 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
271 /* Optimize for Sdata/Sbss */
272 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
274 /* print program statistics */
275 #define TARGET_STATS (target_flags & MASK_STATS)
277 /* call memcpy instead of inline code */
278 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
280 /* .abicalls, etc from Pyramid V.4 */
281 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
283 /* OSF pic references to externs */
284 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
286 /* software floating point */
287 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
288 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
290 /* always call through a register */
291 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
293 /* generate embedded PIC code;
295 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
297 /* for embedded systems, optimize for
298 reduced RAM space instead of for
300 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
302 /* always store uninitialized const
303 variables in rodata, requires
304 TARGET_EMBEDDED_DATA. */
305 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
307 /* generate big endian code. */
308 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
310 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
311 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
313 #define TARGET_MAD (target_flags & MASK_MAD)
315 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
317 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
318 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
320 /* This is true if we must enable the assembly language file switching
323 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
325 /* We must disable the function end stabs when doing the file switching trick,
326 because the Lscope stabs end up in the wrong place, making it impossible
327 to debug the resulting code. */
328 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
330 /* Generate mips16 code */
331 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
333 /* Macro to define tables used to set the flags.
334 This is a list in braces of pairs in braces,
335 each pair being { "NAME", VALUE }
336 where VALUE is the bits to set or minus the bits to clear.
337 An empty string NAME is used to identify the default VALUE. */
339 #define TARGET_SWITCHES \
342 N_("No default crt0.o") }, \
343 {"int64", MASK_INT64 | MASK_LONG64, \
344 N_("Use 64-bit int type")}, \
345 {"long64", MASK_LONG64, \
346 N_("Use 64-bit long type")}, \
347 {"long32", -(MASK_LONG64 | MASK_INT64), \
348 N_("Use 32-bit long type")}, \
349 {"split-addresses", MASK_SPLIT_ADDR, \
350 N_("Optimize lui/addiu address loads")}, \
351 {"no-split-addresses", -MASK_SPLIT_ADDR, \
352 N_("Don't optimize lui/addiu address loads")}, \
353 {"mips-as", -MASK_GAS, \
354 N_("Use MIPS as")}, \
357 {"rnames", MASK_NAME_REGS, \
358 N_("Use symbolic register names")}, \
359 {"no-rnames", -MASK_NAME_REGS, \
360 N_("Don't use symbolic register names")}, \
361 {"gpOPT", MASK_GPOPT, \
362 N_("Use GP relative sdata/sbss sections")}, \
363 {"gpopt", MASK_GPOPT, \
364 N_("Use GP relative sdata/sbss sections")}, \
365 {"no-gpOPT", -MASK_GPOPT, \
366 N_("Don't use GP relative sdata/sbss sections")}, \
367 {"no-gpopt", -MASK_GPOPT, \
368 N_("Don't use GP relative sdata/sbss sections")}, \
369 {"stats", MASK_STATS, \
370 N_("Output compiler statistics")}, \
371 {"no-stats", -MASK_STATS, \
372 N_("Don't output compiler statistics")}, \
373 {"memcpy", MASK_MEMCPY, \
374 N_("Don't optimize block moves")}, \
375 {"no-memcpy", -MASK_MEMCPY, \
376 N_("Optimize block moves")}, \
377 {"mips-tfile", MASK_MIPS_TFILE, \
378 N_("Use mips-tfile asm postpass")}, \
379 {"no-mips-tfile", -MASK_MIPS_TFILE, \
380 N_("Don't use mips-tfile asm postpass")}, \
381 {"soft-float", MASK_SOFT_FLOAT, \
382 N_("Use software floating point")}, \
383 {"hard-float", -MASK_SOFT_FLOAT, \
384 N_("Use hardware floating point")}, \
385 {"fp64", MASK_FLOAT64, \
386 N_("Use 64-bit FP registers")}, \
387 {"fp32", -MASK_FLOAT64, \
388 N_("Use 32-bit FP registers")}, \
389 {"gp64", MASK_64BIT, \
390 N_("Use 64-bit general registers")}, \
391 {"gp32", -MASK_64BIT, \
392 N_("Use 32-bit general registers")}, \
393 {"abicalls", MASK_ABICALLS, \
394 N_("Use Irix PIC")}, \
395 {"no-abicalls", -MASK_ABICALLS, \
396 N_("Don't use Irix PIC")}, \
397 {"half-pic", MASK_HALF_PIC, \
398 N_("Use OSF PIC")}, \
399 {"no-half-pic", -MASK_HALF_PIC, \
400 N_("Don't use OSF PIC")}, \
401 {"long-calls", MASK_LONG_CALLS, \
402 N_("Use indirect calls")}, \
403 {"no-long-calls", -MASK_LONG_CALLS, \
404 N_("Don't use indirect calls")}, \
405 {"embedded-pic", MASK_EMBEDDED_PIC, \
406 N_("Use embedded PIC")}, \
407 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
408 N_("Don't use embedded PIC")}, \
409 {"embedded-data", MASK_EMBEDDED_DATA, \
410 N_("Use ROM instead of RAM")}, \
411 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
412 N_("Don't use ROM instead of RAM")}, \
413 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
414 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
415 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
416 N_("Don't put uninitialized constants in ROM")}, \
417 {"eb", MASK_BIG_ENDIAN, \
418 N_("Use big-endian byte order")}, \
419 {"el", -MASK_BIG_ENDIAN, \
420 N_("Use little-endian byte order")}, \
421 {"single-float", MASK_SINGLE_FLOAT, \
422 N_("Use single (32-bit) FP only")}, \
423 {"double-float", -MASK_SINGLE_FLOAT, \
424 N_("Don't use single (32-bit) FP only")}, \
426 N_("Use multiply accumulate")}, \
427 {"no-mad", -MASK_MAD, \
428 N_("Don't use multiply accumulate")}, \
429 {"fix4300", MASK_4300_MUL_FIX, \
430 N_("Work around early 4300 hardware bug")}, \
431 {"no-fix4300", -MASK_4300_MUL_FIX, \
432 N_("Don't work around early 4300 hardware bug")}, \
433 {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
434 N_("Optimize for 4650")}, \
435 {"3900", MASK_MIPS3900, \
436 N_("Optimize for 3900")}, \
437 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
438 N_("Trap on integer divide by zero")}, \
439 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
440 N_("Don't trap on integer divide by zero")}, \
441 {"check-range-division",MASK_CHECK_RANGE_DIV, \
442 N_("Trap on integer divide overflow")}, \
443 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
444 N_("Don't trap on integer divide overflow")}, \
445 {"debug", MASK_DEBUG, \
447 {"debuga", MASK_DEBUG_A, \
449 {"debugb", MASK_DEBUG_B, \
451 {"debugc", MASK_DEBUG_C, \
453 {"debugd", MASK_DEBUG_D, \
455 {"debuge", MASK_DEBUG_E, \
457 {"debugf", MASK_DEBUG_F, \
459 {"debugg", MASK_DEBUG_G, \
461 {"debugh", MASK_DEBUG_H, \
463 {"debugi", MASK_DEBUG_I, \
465 {"", (TARGET_DEFAULT \
466 | TARGET_CPU_DEFAULT \
467 | TARGET_ENDIAN_DEFAULT), \
471 /* Default target_flags if no switches are specified */
473 #ifndef TARGET_DEFAULT
474 #define TARGET_DEFAULT 0
477 #ifndef TARGET_CPU_DEFAULT
478 #define TARGET_CPU_DEFAULT 0
481 #ifndef TARGET_ENDIAN_DEFAULT
483 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
485 #define TARGET_ENDIAN_DEFAULT 0
489 #ifndef MIPS_ISA_DEFAULT
490 #define MIPS_ISA_DEFAULT 1
495 /* Make this compile time constant for libgcc2 */
497 #define TARGET_64BIT 1
499 #define TARGET_64BIT 0
501 #endif /* IN_LIBGCC2 */
503 #ifndef MULTILIB_ENDIAN_DEFAULT
504 #if TARGET_ENDIAN_DEFAULT == 0
505 #define MULTILIB_ENDIAN_DEFAULT "EL"
507 #define MULTILIB_ENDIAN_DEFAULT "EB"
511 #ifndef MULTILIB_ISA_DEFAULT
512 # if MIPS_ISA_DEFAULT == 1
513 # define MULTILIB_ISA_DEFAULT "mips1"
515 # if MIPS_ISA_DEFAULT == 2
516 # define MULTILIB_ISA_DEFAULT "mips2"
518 # if MIPS_ISA_DEFAULT == 3
519 # define MULTILIB_ISA_DEFAULT "mips3"
521 # if MIPS_ISA_DEFAULT == 4
522 # define MULTILIB_ISA_DEFAULT "mips4"
524 # define MULTILIB_ISA_DEFAULT "mips1"
531 #ifndef MULTILIB_DEFAULTS
532 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
535 /* We must pass -EL to the linker by default for little endian embedded
536 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
537 linker will default to using big-endian output files. The OUTPUT_FORMAT
538 line must be in the linker script, otherwise -EB/-EL will not work. */
541 #if TARGET_ENDIAN_DEFAULT == 0
542 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EL} %{EB}"
544 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EB} %{EL}"
548 /* This macro is similar to `TARGET_SWITCHES' but defines names of
549 command options that have values. Its definition is an
550 initializer with a subgrouping for each command option.
552 Each subgrouping contains a string constant, that defines the
553 fixed part of the option name, and the address of a variable.
554 The variable, type `char *', is set to the variable part of the
555 given option if the fixed part matches. The actual option name
556 is made by appending `-m' to the specified name.
558 Here is an example which defines `-mshort-data-NUMBER'. If the
559 given option is `-mshort-data-512', the variable `m88k_short_data'
560 will be set to the string `"512"'.
562 extern char *m88k_short_data;
563 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
565 #define TARGET_OPTIONS \
567 SUBTARGET_TARGET_OPTIONS \
568 { "cpu=", &mips_cpu_string, \
569 N_("Specify CPU for scheduling purposes")}, \
570 { "ips", &mips_isa_string, \
571 N_("Specify MIPS ISA")}, \
572 { "entry", &mips_entry_string, \
573 N_("Use mips16 entry/exit psuedo ops")}, \
574 { "no-mips16", &mips_no_mips16_string, \
575 N_("Don't use MIPS16 instructions")}, \
576 { "explicit-type-size", &mips_explicit_type_size_string, \
580 /* This is meant to be redefined in the host dependent files. */
581 #define SUBTARGET_TARGET_OPTIONS
583 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
585 /* Generate three-operand multiply instructions for both SImode and DImode. */
586 #define GENERATE_MULT3 (TARGET_MIPS3900 \
589 /* Macros to decide whether certain features are available or not,
590 depending on the instruction set architecture level. */
592 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
593 #define HAVE_SQRT_P() (mips_isa != 1)
595 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
596 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
599 /* ISA has branch likely instructions (eg. mips2). */
600 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
602 /* ISA has the conditional move instructions introduced in mips4. */
603 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
606 /* ISA has just the integer condition move instructions (movn,movz) */
607 #define ISA_HAS_INT_CONDMOVE 0
611 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
612 branch on CC, and move (both FP and non-FP) on CC. */
613 #define ISA_HAS_8CC (mips_isa == 4 \
617 /* This is a catch all for the other new mips4 instructions: indexed load and
618 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
619 and the FP recip and recip sqrt instructions */
620 #define ISA_HAS_FP4 (mips_isa == 4 \
623 /* ISA has conditional trap instructions. */
624 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
627 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
628 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
629 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
630 target_flags, and -mgp64 sets MASK_64BIT.
632 Setting MASK_64BIT in target_flags will cause gcc to assume that
633 registers are 64 bits wide. int, long and void * will be 32 bit;
634 this may be changed with -mint64 or -mlong64.
636 The gen* programs link code that refers to MASK_64BIT. They don't
637 actually use the information in target_flags; they just refer to
640 /* Switch Recognition by gcc.c. Add -G xx support */
642 #ifdef SWITCH_TAKES_ARG
643 #undef SWITCH_TAKES_ARG
646 #define SWITCH_TAKES_ARG(CHAR) \
647 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
649 /* Sometimes certain combinations of command options do not make sense
650 on a particular target machine. You can define a macro
651 `OVERRIDE_OPTIONS' to take account of this. This macro, if
652 defined, is executed once just after all the command options have
655 On the MIPS, it is used to handle -G. We also use it to set up all
656 of the tables referenced in the other macros. */
658 #define OVERRIDE_OPTIONS override_options ()
660 /* Zero or more C statements that may conditionally modify two
661 variables `fixed_regs' and `call_used_regs' (both of type `char
662 []') after they have been initialized from the two preceding
665 This is necessary in case the fixed or call-clobbered registers
666 depend on target flags.
668 You need not define this macro if it has no work to do.
670 If the usage of an entire class of registers depends on the target
671 flags, you may indicate this to GCC by using this macro to modify
672 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
673 the classes which should not be used by GCC. Also define the macro
674 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
675 letter for a class that shouldn't be used.
677 (However, if this class is not included in `GENERAL_REGS' and all
678 of the insn patterns whose constraints permit this class are
679 controlled by target switches, then GCC will automatically avoid
680 using these registers when the target switches are opposed to
683 #define CONDITIONAL_REGISTER_USAGE \
686 if (!TARGET_HARD_FLOAT) \
690 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
691 fixed_regs[regno] = call_used_regs[regno] = 1; \
692 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
693 fixed_regs[regno] = call_used_regs[regno] = 1; \
695 else if (! ISA_HAS_8CC) \
699 /* We only have a single condition code register. We \
700 implement this by hiding all the condition code registers, \
701 and generating RTL that refers directly to ST_REG_FIRST. */ \
702 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
703 fixed_regs[regno] = call_used_regs[regno] = 1; \
705 /* In mips16 mode, we permit the $t temporary registers to be used \
706 for reload. We prohibit the unused $s registers, since they \
707 are caller saved, and saving them via a mips16 register would \
708 probably waste more time than just reloading the value. */ \
711 fixed_regs[18] = call_used_regs[18] = 1; \
712 fixed_regs[19] = call_used_regs[19] = 1; \
713 fixed_regs[20] = call_used_regs[20] = 1; \
714 fixed_regs[21] = call_used_regs[21] = 1; \
715 fixed_regs[22] = call_used_regs[22] = 1; \
716 fixed_regs[23] = call_used_regs[23] = 1; \
717 fixed_regs[26] = call_used_regs[26] = 1; \
718 fixed_regs[27] = call_used_regs[27] = 1; \
719 fixed_regs[30] = call_used_regs[30] = 1; \
721 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
725 /* This is meant to be redefined in the host dependent files. */
726 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
728 /* Show we can debug even without a frame pointer. */
729 #define CAN_DEBUG_WITHOUT_FP
731 /* Complain about missing specs and predefines that should be defined in each
732 of the target tm files to override the defaults. This is mostly a place-
733 holder until I can get each of the files updated [mm]. */
735 #if defined(OSF_OS) \
736 || defined(DECSTATION) \
737 || defined(SGI_TARGET) \
738 || defined(MIPS_NEWS) \
739 || defined(MIPS_SYSV) \
740 || defined(MIPS_SVR4) \
741 || defined(MIPS_BSD43)
743 #ifndef CPP_PREDEFINES
744 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
748 #error "Define LIB_SPEC in the appropriate tm.h file"
751 #ifndef STARTFILE_SPEC
752 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
756 #error "Define MACHINE_TYPE in the appropriate tm.h file"
760 /* Tell collect what flags to pass to nm. */
762 #define NM_FLAGS "-Bn"
766 /* Names to predefine in the preprocessor for this target machine. */
768 #ifndef CPP_PREDEFINES
769 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
770 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
771 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
774 /* Assembler specs. */
776 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
779 #define MIPS_AS_ASM_SPEC "\
780 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
781 %{pipe: %e-pipe is not supported.} \
782 %{K} %(subtarget_mips_as_asm_spec)"
784 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
785 rather than gas. It may be overridden by subtargets. */
787 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
788 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
791 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
794 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
796 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
797 GAS_ASM_SPEC as the default, depending upon the value of
800 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
803 #define TARGET_ASM_SPEC "\
804 %{mmips-as: %(mips_as_asm_spec)} \
805 %{!mmips-as: %(gas_asm_spec)}"
809 #define TARGET_ASM_SPEC "\
810 %{!mgas: %(mips_as_asm_spec)} \
811 %{mgas: %(gas_asm_spec)}"
815 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
816 to the assembler. It may be overridden by subtargets. */
817 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
818 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
820 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
823 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
824 the assembler. It may be overridden by subtargets. */
825 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
826 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
827 %{g} %{g0} %{g1} %{g2} %{g3} \
828 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
829 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
830 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
831 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
834 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
835 overridden by subtargets. */
837 #ifndef SUBTARGET_ASM_SPEC
838 #define SUBTARGET_ASM_SPEC ""
841 /* ASM_SPEC is the set of arguments to pass to the assembler. */
844 %{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
845 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
846 %(subtarget_asm_optimizing_spec) \
847 %(subtarget_asm_debugging_spec) \
850 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
852 %(subtarget_asm_spec)"
854 /* Specify to run a post-processor, mips-tfile after the assembler
855 has run to stuff the mips debug information into the object file.
856 This is needed because the $#!%^ MIPS assembler provides no way
857 of specifying such information in the assembly file. If we are
858 cross compiling, disable mips-tfile unless the user specifies
861 #ifndef ASM_FINAL_SPEC
862 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
864 #define ASM_FINAL_SPEC "\
865 %{mmips-as: %{!mno-mips-tfile: \
866 \n mips-tfile %{v*: -v} \
868 %{!K: %{save-temps: -I %b.o~}} \
869 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
870 %{.s:%i} %{!.s:%g.s}}}"
874 #define ASM_FINAL_SPEC "\
875 %{!mgas: %{!mno-mips-tfile: \
876 \n mips-tfile %{v*: -v} \
878 %{!K: %{save-temps: -I %b.o~}} \
879 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
880 %{.s:%i} %{!.s:%g.s}}}"
883 #endif /* ASM_FINAL_SPEC */
885 /* Redefinition of libraries used. Mips doesn't support normal
886 UNIX style profiling via calling _mcount. It does offer
887 profiling that samples the PC, so do what we can... */
890 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
893 /* Extra switches sometimes passed to the linker. */
894 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
895 will interpret it as a -b option. */
900 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \
901 %{bestGnum} %{shared} %{non_shared}"
902 #endif /* LINK_SPEC defined */
904 /* Specs for the compiler proper */
906 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
907 overridden by subtargets. */
908 #ifndef SUBTARGET_CC1_SPEC
909 #define SUBTARGET_CC1_SPEC ""
912 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
916 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
917 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
918 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
919 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
920 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
921 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
922 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
923 %{m4650:-mcpu=r4650} \
924 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
925 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
926 %{pic-none: -mno-half-pic} \
927 %{pic-lib: -mhalf-pic} \
928 %{pic-extern: -mhalf-pic} \
929 %{pic-calls: -mhalf-pic} \
931 %(subtarget_cc1_spec) "
934 /* Preprocessor specs. */
936 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
937 be overridden by subtargets. */
939 #ifndef SUBTARGET_CPP_SIZE_SPEC
940 #define SUBTARGET_CPP_SIZE_SPEC "\
941 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
942 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
945 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
946 overridden by subtargets. */
947 #ifndef SUBTARGET_CPP_SPEC
948 #define SUBTARGET_CPP_SPEC ""
951 /* If we're using 64bit longs, then we have to define __LONG_MAX__
952 correctly. Similarly for 64bit ints and __INT_MAX__. */
953 #ifndef LONG_MAX_SPEC
954 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
955 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
957 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
961 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
962 of the source file extension. */
963 #define CPLUSPLUS_CPP_SPEC "\
964 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
967 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
971 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
972 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
973 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
974 %(subtarget_cpp_size_spec) \
975 %{mips3:-U__mips -D__mips=3 -D__mips64} \
976 %{mips4:-U__mips -D__mips=4 -D__mips64} \
977 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
978 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
979 %{m4650:%{!msoft-float:-D__mips_single_float}} \
980 %{msoft-float:-D__mips_soft_float} \
981 %{mabi=eabi:-D__mips_eabi} \
982 %{mips16:%{!mno-mips16:-D__mips16}} \
983 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
984 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
986 %(subtarget_cpp_spec) "
989 /* This macro defines names of additional specifications to put in the specs
990 that can be used in various specifications like CC1_SPEC. Its definition
991 is an initializer with a subgrouping for each command option.
993 Each subgrouping contains a string constant, that defines the
994 specification name, and a string constant that used by the GNU CC driver
997 Do not define this macro if it does not need to do anything. */
999 #define EXTRA_SPECS \
1000 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1001 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1002 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1003 { "long_max_spec", LONG_MAX_SPEC }, \
1004 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1005 { "gas_asm_spec", GAS_ASM_SPEC }, \
1006 { "target_asm_spec", TARGET_ASM_SPEC }, \
1007 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1008 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1009 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1010 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1011 { "endian_spec", ENDIAN_SPEC }, \
1012 SUBTARGET_EXTRA_SPECS
1014 #ifndef SUBTARGET_EXTRA_SPECS
1015 #define SUBTARGET_EXTRA_SPECS
1018 /* If defined, this macro is an additional prefix to try after
1019 `STANDARD_EXEC_PREFIX'. */
1021 #ifndef MD_EXEC_PREFIX
1022 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1025 #ifndef MD_STARTFILE_PREFIX
1026 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1030 /* Print subsidiary information on the compiler version in use. */
1032 #define MIPS_VERSION "[AL 1.1, MM 40]"
1034 #ifndef MACHINE_TYPE
1035 #define MACHINE_TYPE "BSD Mips"
1038 #ifndef TARGET_VERSION_INTERNAL
1039 #define TARGET_VERSION_INTERNAL(STREAM) \
1040 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1043 #ifndef TARGET_VERSION
1044 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1048 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1049 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1050 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1052 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1053 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1056 /* By default, turn on GDB extensions. */
1057 #define DEFAULT_GDB_EXTENSIONS 1
1059 /* If we are passing smuggling stabs through the MIPS ECOFF object
1060 format, put a comment in front of the .stab<x> operation so
1061 that the MIPS assembler does not choke. The mips-tfile program
1062 will correctly put the stab into the object file. */
1064 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1065 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1066 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1068 /* Local compiler-generated symbols must have a prefix that the assembler
1069 understands. By default, this is $, although some targets (e.g.,
1070 NetBSD-ELF) need to override this. */
1072 #ifndef LOCAL_LABEL_PREFIX
1073 #define LOCAL_LABEL_PREFIX "$"
1076 /* By default on the mips, external symbols do not have an underscore
1077 prepended, but some targets (e.g., NetBSD) require this. */
1079 #ifndef USER_LABEL_PREFIX
1080 #define USER_LABEL_PREFIX ""
1083 /* Forward references to tags are allowed. */
1084 #define SDB_ALLOW_FORWARD_REFERENCES
1086 /* Unknown tags are also allowed. */
1087 #define SDB_ALLOW_UNKNOWN_REFERENCES
1089 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1090 since the length can run past this up to a continuation point. */
1091 #undef DBX_CONTIN_LENGTH
1092 #define DBX_CONTIN_LENGTH 1500
1094 /* How to renumber registers for dbx and gdb. */
1095 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1097 /* The mapping from gcc register number to DWARF 2 CFA column number.
1098 This mapping does not allow for tracking register 0, since SGI's broken
1099 dwarf reader thinks column 0 is used for the frame address, but since
1100 register 0 is fixed this is not a problem. */
1101 #define DWARF_FRAME_REGNUM(REG) \
1102 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1104 /* The DWARF 2 CFA column which tracks the return address. */
1105 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1107 /* Before the prologue, RA lives in r31. */
1108 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1110 /* Describe how we implement __builtin_eh_return. */
1111 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1112 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1114 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1115 The default for this in 64-bit mode is 8, which causes problems with
1116 SFmode register saves. */
1117 #define DWARF_CIE_DATA_ALIGNMENT 4
1119 /* Overrides for the COFF debug format. */
1120 #define PUT_SDB_SCL(a) \
1122 extern FILE *asm_out_text_file; \
1123 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1126 #define PUT_SDB_INT_VAL(a) \
1128 extern FILE *asm_out_text_file; \
1129 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1132 #define PUT_SDB_VAL(a) \
1134 extern FILE *asm_out_text_file; \
1135 fputs ("\t.val\t", asm_out_text_file); \
1136 output_addr_const (asm_out_text_file, (a)); \
1137 fputc (';', asm_out_text_file); \
1140 #define PUT_SDB_DEF(a) \
1142 extern FILE *asm_out_text_file; \
1143 fprintf (asm_out_text_file, "\t%s.def\t", \
1144 (TARGET_GAS) ? "" : "#"); \
1145 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1146 fputc (';', asm_out_text_file); \
1149 #define PUT_SDB_PLAIN_DEF(a) \
1151 extern FILE *asm_out_text_file; \
1152 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1153 (TARGET_GAS) ? "" : "#", (a)); \
1156 #define PUT_SDB_ENDEF \
1158 extern FILE *asm_out_text_file; \
1159 fprintf (asm_out_text_file, "\t.endef\n"); \
1162 #define PUT_SDB_TYPE(a) \
1164 extern FILE *asm_out_text_file; \
1165 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1168 #define PUT_SDB_SIZE(a) \
1170 extern FILE *asm_out_text_file; \
1171 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1174 #define PUT_SDB_DIM(a) \
1176 extern FILE *asm_out_text_file; \
1177 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1180 #ifndef PUT_SDB_START_DIM
1181 #define PUT_SDB_START_DIM \
1183 extern FILE *asm_out_text_file; \
1184 fprintf (asm_out_text_file, "\t.dim\t"); \
1188 #ifndef PUT_SDB_NEXT_DIM
1189 #define PUT_SDB_NEXT_DIM(a) \
1191 extern FILE *asm_out_text_file; \
1192 fprintf (asm_out_text_file, "%d,", a); \
1196 #ifndef PUT_SDB_LAST_DIM
1197 #define PUT_SDB_LAST_DIM(a) \
1199 extern FILE *asm_out_text_file; \
1200 fprintf (asm_out_text_file, "%d;", a); \
1204 #define PUT_SDB_TAG(a) \
1206 extern FILE *asm_out_text_file; \
1207 fprintf (asm_out_text_file, "\t.tag\t"); \
1208 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1209 fputc (';', asm_out_text_file); \
1212 /* For block start and end, we create labels, so that
1213 later we can figure out where the correct offset is.
1214 The normal .ent/.end serve well enough for functions,
1215 so those are just commented out. */
1217 #define PUT_SDB_BLOCK_START(LINE) \
1219 extern FILE *asm_out_text_file; \
1220 fprintf (asm_out_text_file, \
1221 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1222 LOCAL_LABEL_PREFIX, \
1224 (TARGET_GAS) ? "" : "#", \
1225 LOCAL_LABEL_PREFIX, \
1228 sdb_label_count++; \
1231 #define PUT_SDB_BLOCK_END(LINE) \
1233 extern FILE *asm_out_text_file; \
1234 fprintf (asm_out_text_file, \
1235 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1236 LOCAL_LABEL_PREFIX, \
1238 (TARGET_GAS) ? "" : "#", \
1239 LOCAL_LABEL_PREFIX, \
1242 sdb_label_count++; \
1245 #define PUT_SDB_FUNCTION_START(LINE)
1247 #define PUT_SDB_FUNCTION_END(LINE) \
1249 extern FILE *asm_out_text_file; \
1250 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1253 #define PUT_SDB_EPILOGUE_END(NAME)
1255 #define PUT_SDB_SRC_FILE(FILENAME) \
1257 extern FILE *asm_out_text_file; \
1258 output_file_directive (asm_out_text_file, (FILENAME)); \
1261 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1262 sprintf ((BUFFER), ".%dfake", (NUMBER));
1264 /* Correct the offset of automatic variables and arguments. Note that
1265 the MIPS debug format wants all automatic variables and arguments
1266 to be in terms of the virtual frame pointer (stack pointer before
1267 any adjustment in the function), while the MIPS 3.0 linker wants
1268 the frame pointer to be the stack pointer after the initial
1271 #define DEBUGGER_AUTO_OFFSET(X) \
1272 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1273 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1274 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1276 /* Tell collect that the object format is ECOFF */
1277 #ifndef OBJECT_FORMAT_ROSE
1278 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1279 #define EXTENDED_COFF /* ECOFF, not normal coff */
1282 #if 0 /* These definitions normally have no effect because
1283 MIPS systems define USE_COLLECT2, so
1284 assemble_constructor does nothing anyway. */
1286 /* Don't use the default definitions, because we don't have gld.
1287 Also, we don't want stabs when generating ECOFF output.
1288 Instead we depend on collect to handle these. */
1290 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1291 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1295 /* Target machine storage layout */
1297 /* Define in order to support both big and little endian float formats
1298 in the same gcc binary. */
1299 #define REAL_ARITHMETIC
1301 /* Define this if most significant bit is lowest numbered
1302 in instructions that operate on numbered bit-fields.
1304 #define BITS_BIG_ENDIAN 0
1306 /* Define this if most significant byte of a word is the lowest numbered. */
1307 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1309 /* Define this if most significant word of a multiword number is the lowest. */
1310 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1312 /* Define this to set the endianness to use in libgcc2.c, which can
1313 not depend on target_flags. */
1314 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1315 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1317 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1320 /* Number of bits in an addressable storage unit */
1321 #define BITS_PER_UNIT 8
1323 /* Width in bits of a "word", which is the contents of a machine register.
1324 Note that this is not necessarily the width of data type `int';
1325 if using 16-bit ints on a 68000, this would still be 32.
1326 But on a machine with 16-bit registers, this would be 16. */
1327 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1328 #define MAX_BITS_PER_WORD 64
1330 /* Width of a word, in units (bytes). */
1331 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1332 #define MIN_UNITS_PER_WORD 4
1334 /* For MIPS, width of a floating point register. */
1335 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1337 /* A C expression for the size in bits of the type `int' on the
1338 target machine. If you don't define this, the default is one
1340 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1341 #define MAX_INT_TYPE_SIZE 64
1343 /* Tell the preprocessor the maximum size of wchar_t. */
1344 #ifndef MAX_WCHAR_TYPE_SIZE
1345 #ifndef WCHAR_TYPE_SIZE
1346 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1350 /* A C expression for the size in bits of the type `short' on the
1351 target machine. If you don't define this, the default is half a
1352 word. (If this would be less than one storage unit, it is
1353 rounded up to one unit.) */
1354 #define SHORT_TYPE_SIZE 16
1356 /* A C expression for the size in bits of the type `long' on the
1357 target machine. If you don't define this, the default is one
1359 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1360 #define MAX_LONG_TYPE_SIZE 64
1362 /* A C expression for the size in bits of the type `long long' on the
1363 target machine. If you don't define this, the default is two
1365 #define LONG_LONG_TYPE_SIZE 64
1367 /* A C expression for the size in bits of the type `char' on the
1368 target machine. If you don't define this, the default is one
1369 quarter of a word. (If this would be less than one storage unit,
1370 it is rounded up to one unit.) */
1371 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1373 /* A C expression for the size in bits of the type `float' on the
1374 target machine. If you don't define this, the default is one
1376 #define FLOAT_TYPE_SIZE 32
1378 /* A C expression for the size in bits of the type `double' on the
1379 target machine. If you don't define this, the default is two
1381 #define DOUBLE_TYPE_SIZE 64
1383 /* A C expression for the size in bits of the type `long double' on
1384 the target machine. If you don't define this, the default is two
1386 #define LONG_DOUBLE_TYPE_SIZE 64
1388 /* Width in bits of a pointer.
1389 See also the macro `Pmode' defined below. */
1390 #ifndef POINTER_SIZE
1391 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1394 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1395 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1397 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1398 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1400 /* Allocation boundary (in *bits*) for the code of a function. */
1401 #define FUNCTION_BOUNDARY 32
1403 /* Alignment of field after `int : 0' in a structure. */
1404 #define EMPTY_FIELD_BOUNDARY 32
1406 /* Every structure's size must be a multiple of this. */
1407 /* 8 is observed right on a DECstation and on riscos 4.02. */
1408 #define STRUCTURE_SIZE_BOUNDARY 8
1410 /* There is no point aligning anything to a rounder boundary than this. */
1411 #define BIGGEST_ALIGNMENT 64
1413 /* Set this nonzero if move instructions will actually fail to work
1414 when given unaligned data. */
1415 #define STRICT_ALIGNMENT 1
1417 /* Define this if you wish to imitate the way many other C compilers
1418 handle alignment of bitfields and the structures that contain
1421 The behavior is that the type written for a bitfield (`int',
1422 `short', or other integer type) imposes an alignment for the
1423 entire structure, as if the structure really did contain an
1424 ordinary field of that type. In addition, the bitfield is placed
1425 within the structure so that it would fit within such a field,
1426 not crossing a boundary for it.
1428 Thus, on most machines, a bitfield whose type is written as `int'
1429 would not cross a four-byte boundary, and would force four-byte
1430 alignment for the whole structure. (The alignment used may not
1431 be four bytes; it is controlled by the other alignment
1434 If the macro is defined, its definition should be a C expression;
1435 a nonzero value for the expression enables this behavior. */
1437 #define PCC_BITFIELD_TYPE_MATTERS 1
1439 /* If defined, a C expression to compute the alignment given to a
1440 constant that is being placed in memory. CONSTANT is the constant
1441 and ALIGN is the alignment that the object would ordinarily have.
1442 The value of this macro is used instead of that alignment to align
1445 If this macro is not defined, then ALIGN is used.
1447 The typical use of this macro is to increase alignment for string
1448 constants to be word aligned so that `strcpy' calls that copy
1449 constants can be done inline. */
1451 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1452 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1453 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1455 /* If defined, a C expression to compute the alignment for a static
1456 variable. TYPE is the data type, and ALIGN is the alignment that
1457 the object would ordinarily have. The value of this macro is used
1458 instead of that alignment to align the object.
1460 If this macro is not defined, then ALIGN is used.
1462 One use of this macro is to increase alignment of medium-size
1463 data to make it all fit in fewer cache lines. Another is to
1464 cause character arrays to be word-aligned so that `strcpy' calls
1465 that copy constants to character arrays can be done inline. */
1467 #undef DATA_ALIGNMENT
1468 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1469 ((((ALIGN) < BITS_PER_WORD) \
1470 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1471 || TREE_CODE (TYPE) == UNION_TYPE \
1472 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1475 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1477 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1479 /* Define this macro if an argument declared as `char' or `short' in a
1480 prototype should actually be passed as an `int'. In addition to
1481 avoiding errors in certain cases of mismatch, it also makes for
1482 better code on certain machines. */
1484 #define PROMOTE_PROTOTYPES 1
1486 /* Define if operations between registers always perform the operation
1487 on the full register even if a narrower mode is specified. */
1488 #define WORD_REGISTER_OPERATIONS
1490 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1491 will either zero-extend or sign-extend. The value of this macro should
1492 be the code that says which one of the two operations is implicitly
1495 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1496 moves. All other referces are zero extended. */
1497 #define LOAD_EXTEND_OP(MODE) \
1498 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1499 ? SIGN_EXTEND : ZERO_EXTEND)
1501 /* Define this macro if it is advisable to hold scalars in registers
1502 in a wider mode than that declared by the program. In such cases,
1503 the value is constrained to be within the bounds of the declared
1504 type, but kept valid in the wider mode. The signedness of the
1505 extension may differ from that of the type.
1507 We promote any value smaller than SImode up to SImode. We don't
1508 want to promote to DImode when in 64 bit mode, because that would
1509 prevent us from using the faster SImode multiply and divide
1512 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1513 if (GET_MODE_CLASS (MODE) == MODE_INT \
1514 && GET_MODE_SIZE (MODE) < 4) \
1517 /* Define this if function arguments should also be promoted using the above
1520 #define PROMOTE_FUNCTION_ARGS
1522 /* Likewise, if the function return value is promoted. */
1524 #define PROMOTE_FUNCTION_RETURN
1526 /* Standard register usage. */
1528 /* Number of actual hardware registers.
1529 The hardware registers are assigned numbers for the compiler
1530 from 0 to just below FIRST_PSEUDO_REGISTER.
1531 All registers that the compiler knows about must be given numbers,
1532 even those that are not normally considered general registers.
1534 On the Mips, we have 32 integer registers, 32 floating point
1535 registers, 8 condition code registers, and the special registers
1536 hi, lo, hilo, and rap. The 8 condition code registers are only
1537 used if mips_isa >= 4. The hilo register is only used in 64 bit
1538 mode. It represents a 64 bit value stored as two 32 bit values in
1539 the hi and lo registers; this is the result of the mult
1540 instruction. rap is a pointer to the stack where the return
1541 address reg ($31) was stored. This is needed for C++ exception
1544 #define FIRST_PSEUDO_REGISTER 76
1546 /* 1 for registers that have pervasive standard uses
1547 and are not available for the register allocator.
1549 On the MIPS, see conventions, page D-2 */
1551 #define FIXED_REGISTERS \
1553 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1554 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1561 /* 1 for registers not available across function calls.
1562 These must include the FIXED_REGISTERS and also any
1563 registers that can be used without being saved.
1564 The latter must include the registers where values are returned
1565 and the register where structure-value addresses are passed.
1566 Aside from that, you can include as many other registers as you like. */
1568 #define CALL_USED_REGISTERS \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1578 /* Internal macros to classify a register number as to whether it's a
1579 general purpose register, a floating point register, a
1580 multiply/divide register, or a status register. */
1582 #define GP_REG_FIRST 0
1583 #define GP_REG_LAST 31
1584 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1585 #define GP_DBX_FIRST 0
1587 #define FP_REG_FIRST 32
1588 #define FP_REG_LAST 63
1589 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1590 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1592 #define MD_REG_FIRST 64
1593 #define MD_REG_LAST 66
1594 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1596 #define ST_REG_FIRST 67
1597 #define ST_REG_LAST 74
1598 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1600 #define RAP_REG_NUM 75
1602 #define AT_REGNUM (GP_REG_FIRST + 1)
1603 #define HI_REGNUM (MD_REG_FIRST + 0)
1604 #define LO_REGNUM (MD_REG_FIRST + 1)
1605 #define HILO_REGNUM (MD_REG_FIRST + 2)
1607 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1608 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1609 should be used instead. */
1610 #define FPSW_REGNUM ST_REG_FIRST
1612 #define GP_REG_P(REGNO) \
1613 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1614 #define M16_REG_P(REGNO) \
1615 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1616 #define FP_REG_P(REGNO) \
1617 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1618 #define MD_REG_P(REGNO) \
1619 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1620 #define ST_REG_P(REGNO) \
1621 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1623 /* Return number of consecutive hard regs needed starting at reg REGNO
1624 to hold something of mode MODE.
1625 This is ordinarily the length in words of a value of mode MODE
1626 but can be less for certain modes in special long registers.
1628 On the MIPS, all general registers are one word long. Except on
1629 the R4000 with the FR bit set, the floating point uses register
1630 pairs, with the second register not being allocable. */
1632 #define HARD_REGNO_NREGS(REGNO, MODE) \
1633 (! FP_REG_P (REGNO) \
1634 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1635 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1637 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1638 MODE. In 32 bit mode, require that DImode and DFmode be in even
1639 registers. For DImode, this makes some of the insns easier to
1640 write, since you don't have to worry about a DImode value in
1641 registers 3 & 4, producing a result in 4 & 5.
1643 To make the code simpler HARD_REGNO_MODE_OK now just references an
1644 array built in override_options. Because machmodes.h is not yet
1645 included before this file is processed, the MODE bound can't be
1648 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1650 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1651 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1653 /* Value is 1 if it is a good idea to tie two pseudo registers
1654 when one has mode MODE1 and one has mode MODE2.
1655 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1656 for any hard reg, then this must be 0 for correct output. */
1657 #define MODES_TIEABLE_P(MODE1, MODE2) \
1658 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1659 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1660 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1661 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1663 /* MIPS pc is not overloaded on a register. */
1664 /* #define PC_REGNUM xx */
1666 /* Register to use for pushing function arguments. */
1667 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1669 /* Offset from the stack pointer to the first available location. Use
1670 the default value zero. */
1671 /* #define STACK_POINTER_OFFSET 0 */
1673 /* Base register for access to local variables of the function. We
1674 pretend that the frame pointer is $1, and then eliminate it to
1675 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1676 a fixed register, and will not be used for anything else. */
1677 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1679 /* Temporary scratch register for use by the assembler. */
1680 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1682 /* $30 is not available on the mips16, so we use $17 as the frame
1684 #define HARD_FRAME_POINTER_REGNUM \
1685 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1687 /* Value should be nonzero if functions must have frame pointers.
1688 Zero means the frame pointer need not be set up (and parms
1689 may be accessed via the stack pointer) in functions that seem suitable.
1690 This is computed in `reload', in reload1.c. */
1691 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1693 /* Base register for access to arguments of the function. */
1694 #define ARG_POINTER_REGNUM GP_REG_FIRST
1696 /* Fake register that holds the address on the stack of the
1697 current function's return address. */
1698 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1700 /* Register in which static-chain is passed to a function. */
1701 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1703 /* If the structure value address is passed in a register, then
1704 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1705 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1707 /* If the structure value address is not passed in a register, define
1708 `STRUCT_VALUE' as an expression returning an RTX for the place
1709 where the address is passed. If it returns 0, the address is
1710 passed as an "invisible" first argument. */
1711 #define STRUCT_VALUE 0
1713 /* Mips registers used in prologue/epilogue code when the stack frame
1714 is larger than 32K bytes. These registers must come from the
1715 scratch register set, and not used for passing and returning
1716 arguments and any other information used in the calling sequence
1717 (such as pic). Must start at 12, since t0/t3 are parameter passing
1718 registers in the 64 bit ABI. */
1720 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1721 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1723 /* Define this macro if it is as good or better to call a constant
1724 function address than to call an address kept in a register. */
1725 #define NO_FUNCTION_CSE 1
1727 /* Define this macro if it is as good or better for a function to
1728 call itself with an explicit address than to call an address
1729 kept in a register. */
1730 #define NO_RECURSIVE_FUNCTION_CSE 1
1732 /* The register number of the register used to address a table of
1733 static data addresses in memory. In some cases this register is
1734 defined by a processor's "application binary interface" (ABI).
1735 When this macro is defined, RTL is generated for this register
1736 once, as with the stack pointer and frame pointer registers. If
1737 this macro is not defined, it is up to the machine-dependent
1738 files to allocate such a register (if necessary). */
1739 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1741 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1743 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1744 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1745 isn't always called for static inline functions. */
1746 #define INIT_EXPANDERS \
1748 embedded_pic_fnaddr_rtx = NULL; \
1749 mips16_gp_pseudo_rtx = NULL; \
1752 /* Define the classes of registers for register constraints in the
1753 machine description. Also define ranges of constants.
1755 One of the classes must always be named ALL_REGS and include all hard regs.
1756 If there is more than one class, another class must be named NO_REGS
1757 and contain no registers.
1759 The name GENERAL_REGS must be the name of a class (or an alias for
1760 another name such as ALL_REGS). This is the class of registers
1761 that is allowed by "g" or "r" in a register constraint.
1762 Also, registers outside this class are allocated only when
1763 instructions express preferences for them.
1765 The classes must be numbered in nondecreasing order; that is,
1766 a larger-numbered class must never be contained completely
1767 in a smaller-numbered class.
1769 For any two classes, it is very desirable that there be another
1770 class that represents their union. */
1774 NO_REGS, /* no registers in set */
1775 M16_NA_REGS, /* mips16 regs not used to pass args */
1776 M16_REGS, /* mips16 directly accessible registers */
1777 T_REG, /* mips16 T register ($24) */
1778 M16_T_REGS, /* mips16 registers plus T register */
1779 GR_REGS, /* integer registers */
1780 FP_REGS, /* floating point registers */
1781 HI_REG, /* hi register */
1782 LO_REG, /* lo register */
1783 HILO_REG, /* hilo register pair for 64 bit mode mult */
1784 MD_REGS, /* multiply/divide registers (hi/lo) */
1785 HI_AND_GR_REGS, /* union classes */
1788 ST_REGS, /* status registers (fp status) */
1789 ALL_REGS, /* all registers */
1790 LIM_REG_CLASSES /* max value + 1 */
1793 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1795 #define GENERAL_REGS GR_REGS
1797 /* An initializer containing the names of the register classes as C
1798 string constants. These names are used in writing some of the
1801 #define REG_CLASS_NAMES \
1816 "HILO_AND_GR_REGS", \
1821 /* An initializer containing the contents of the register classes,
1822 as integers which are bit masks. The Nth integer specifies the
1823 contents of class N. The way the integer MASK is interpreted is
1824 that register R is in the class if `MASK & (1 << R)' is 1.
1826 When the machine has more than 32 registers, an integer does not
1827 suffice. Then the integers are replaced by sub-initializers,
1828 braced groupings containing several integers. Each
1829 sub-initializer must be suitable as an initializer for the type
1830 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1832 #define REG_CLASS_CONTENTS \
1834 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1835 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1836 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1837 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1838 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1839 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1840 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1841 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1842 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1843 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1844 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1845 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1846 { 0xffffffff, 0x00000000, 0x00000002 }, \
1847 { 0xffffffff, 0x00000000, 0x00000004 }, \
1848 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1849 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1853 /* A C expression whose value is a register class containing hard
1854 register REGNO. In general there is more that one such class;
1855 choose a class which is "minimal", meaning that no smaller class
1856 also contains the register. */
1858 extern enum reg_class mips_regno_to_class[];
1860 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1862 /* A macro whose definition is the name of the class to which a
1863 valid base register must belong. A base register is one used in
1864 an address which is the register value plus a displacement. */
1866 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1868 /* A macro whose definition is the name of the class to which a
1869 valid index register must belong. An index register is one used
1870 in an address where its value is either multiplied by a scale
1871 factor or added to another register (as well as added to a
1874 #define INDEX_REG_CLASS NO_REGS
1876 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1877 registers explicitly used in the rtl to be used as spill registers
1878 but prevents the compiler from extending the lifetime of these
1881 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1883 /* This macro is used later on in the file. */
1884 #define GR_REG_CLASS_P(CLASS) \
1885 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1886 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1888 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1889 is the default value (allocate the registers in numeric order). We
1890 define it just so that we can override it for the mips16 target in
1891 ORDER_REGS_FOR_LOCAL_ALLOC. */
1893 #define REG_ALLOC_ORDER \
1894 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1895 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1896 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1897 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1898 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1901 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1902 to be rearranged based on a particular function. On the mips16, we
1903 want to allocate $24 (T_REG) before other registers for
1904 instructions for which it is possible. */
1906 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1908 /* REGISTER AND CONSTANT CLASSES */
1910 /* Get reg_class from a letter such as appears in the machine
1913 DEFINED REGISTER CLASSES:
1915 'd' General (aka integer) registers
1916 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1917 'y' General registers (in both mips16 and non mips16 mode)
1918 'e' mips16 non argument registers (M16_NA_REGS)
1919 't' mips16 temporary register ($24)
1920 'f' Floating point registers
1923 'x' Multiply/divide registers
1925 'z' FP Status register
1926 'b' All registers */
1928 extern enum reg_class mips_char_to_class[];
1930 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1932 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1933 string can be used to stand for particular ranges of immediate
1934 operands. This macro defines what the ranges are. C is the
1935 letter, and VALUE is a constant value. Return 1 if VALUE is
1936 in the range specified by C. */
1940 `I' is used for the range of constants an arithmetic insn can
1941 actually contain (16 bits signed integers).
1943 `J' is used for the range which is just zero (ie, $r0).
1945 `K' is used for the range of constants a logical insn can actually
1946 contain (16 bit zero-extended integers).
1948 `L' is used for the range of constants that be loaded with lui
1949 (ie, the bottom 16 bits are zero).
1951 `M' is used for the range of constants that take two words to load
1952 (ie, not matched by `I', `K', and `L').
1954 `N' is used for negative 16 bit constants other than -65536.
1956 `O' is a 15 bit signed integer.
1958 `P' is used for positive 16 bit constants. */
1960 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1961 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1963 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1964 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1965 : (C) == 'J' ? ((VALUE) == 0) \
1966 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1967 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1968 && (((VALUE) & ~2147483647) == 0 \
1969 || ((VALUE) & ~2147483647) == ~2147483647)) \
1970 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1971 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1972 && (((VALUE) & 0x0000ffff) != 0 \
1973 || (((VALUE) & ~2147483647) != 0 \
1974 && ((VALUE) & ~2147483647) != ~2147483647))) \
1975 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1976 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1977 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1980 /* Similar, but for floating constants, and defining letters G and H.
1981 Here VALUE is the CONST_DOUBLE rtx itself. */
1985 'G' : Floating point 0 */
1987 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1989 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1991 /* Letters in the range `Q' through `U' may be defined in a
1992 machine-dependent fashion to stand for arbitrary operand types.
1993 The machine description macro `EXTRA_CONSTRAINT' is passed the
1994 operand as its first argument and the constraint letter as its
1997 `Q' is for mips16 GP relative constants
1998 `R' is for memory references which take 1 word for the instruction.
1999 `S' is for references to extern items which are PIC for OSF/rose.
2000 `T' is for memory addresses that can be used to load two words. */
2002 #define EXTRA_CONSTRAINT(OP,CODE) \
2003 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2004 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2005 && mips16_gp_offset_p (OP)) \
2006 : (GET_CODE (OP) != MEM) ? FALSE \
2007 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2008 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2009 && HALF_PIC_ADDRESS_P (OP)) \
2012 /* Given an rtx X being reloaded into a reg required to be
2013 in class CLASS, return the class of reg to actually use.
2014 In general this is just CLASS; but on some machines
2015 in some cases it is preferable to use a more restrictive class. */
2017 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2018 ((CLASS) != ALL_REGS \
2019 ? (! TARGET_MIPS16 \
2021 : ((CLASS) != GR_REGS \
2024 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2025 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2026 ? (TARGET_SOFT_FLOAT \
2027 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2029 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2030 || GET_MODE (X) == VOIDmode) \
2031 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2034 /* Certain machines have the property that some registers cannot be
2035 copied to some other registers without using memory. Define this
2036 macro on those machines to be a C expression that is non-zero if
2037 objects of mode MODE in registers of CLASS1 can only be copied to
2038 registers of class CLASS2 by storing a register of CLASS1 into
2039 memory and loading that memory location into a register of CLASS2.
2041 Do not define this macro if its value would always be zero. */
2043 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2044 ((!TARGET_DEBUG_H_MODE \
2045 && GET_MODE_CLASS (MODE) == MODE_INT \
2046 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2047 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2048 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2049 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2050 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2052 /* The HI and LO registers can only be reloaded via the general
2053 registers. Condition code registers can only be loaded to the
2054 general registers, and from the floating point registers. */
2056 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2057 mips_secondary_reload_class (CLASS, MODE, X, 1)
2058 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2059 mips_secondary_reload_class (CLASS, MODE, X, 0)
2061 /* Return the maximum number of consecutive registers
2062 needed to represent mode MODE in a register of class CLASS. */
2064 #define CLASS_UNITS(mode, size) \
2065 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2067 #define CLASS_MAX_NREGS(CLASS, MODE) \
2068 ((CLASS) == FP_REGS \
2070 ? CLASS_UNITS (MODE, 8) \
2071 : 2 * CLASS_UNITS (MODE, 8)) \
2072 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2074 /* If defined, gives a class of registers that cannot be used as the
2075 operand of a SUBREG that changes the mode of the object illegally. */
2077 #define CLASS_CANNOT_CHANGE_MODE \
2078 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2080 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2082 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2083 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2085 /* Stack layout; function entry, exit and calling. */
2087 /* Define this if pushing a word on the stack
2088 makes the stack pointer a smaller address. */
2089 #define STACK_GROWS_DOWNWARD
2091 /* Define this if the nominal address of the stack frame
2092 is at the high-address end of the local variables;
2093 that is, each additional local variable allocated
2094 goes at a more negative offset in the frame. */
2095 /* #define FRAME_GROWS_DOWNWARD */
2097 /* Offset within stack frame to start allocating local variables at.
2098 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2099 first local allocated. Otherwise, it is the offset to the BEGINNING
2100 of the first local allocated. */
2101 #define STARTING_FRAME_OFFSET \
2102 (current_function_outgoing_args_size \
2103 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2105 /* Offset from the stack pointer register to an item dynamically
2106 allocated on the stack, e.g., by `alloca'.
2108 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2109 length of the outgoing arguments. The default is correct for most
2110 machines. See `function.c' for details.
2112 The MIPS ABI states that functions which dynamically allocate the
2113 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2114 we are trying to create a second frame pointer to the function, so
2115 allocate some stack space to make it happy.
2117 However, the linker currently complains about linking any code that
2118 dynamically allocates stack space, and there seems to be a bug in
2119 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2122 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2123 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2124 ? 4*UNITS_PER_WORD \
2125 : current_function_outgoing_args_size)
2128 /* The return address for the current frame is in r31 is this is a leaf
2129 function. Otherwise, it is on the stack. It is at a variable offset
2130 from sp/fp/ap, so we define a fake hard register rap which is a
2131 poiner to the return address on the stack. This always gets eliminated
2132 during reload to be either the frame pointer or the stack pointer plus
2135 /* ??? This definition fails for leaf functions. There is currently no
2136 general solution for this problem. */
2138 /* ??? There appears to be no way to get the return address of any previous
2139 frame except by disassembling instructions in the prologue/epilogue.
2140 So currently we support only the current frame. */
2142 #define RETURN_ADDR_RTX(count, frame) \
2144 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2147 /* Structure to be filled in by compute_frame_size with register
2148 save masks, and offsets for the current function. */
2150 struct mips_frame_info
2152 long total_size; /* # bytes that the entire frame takes up */
2153 long var_size; /* # bytes that variables take up */
2154 long args_size; /* # bytes that outgoing arguments take up */
2155 long extra_size; /* # bytes of extra gunk */
2156 int gp_reg_size; /* # bytes needed to store gp regs */
2157 int fp_reg_size; /* # bytes needed to store fp regs */
2158 long mask; /* mask of saved gp registers */
2159 long fmask; /* mask of saved fp registers */
2160 long gp_save_offset; /* offset from vfp to store gp registers */
2161 long fp_save_offset; /* offset from vfp to store fp registers */
2162 long gp_sp_offset; /* offset from new sp to store gp registers */
2163 long fp_sp_offset; /* offset from new sp to store fp registers */
2164 int initialized; /* != 0 if frame size already calculated */
2165 int num_gp; /* number of gp registers saved */
2166 int num_fp; /* number of fp registers saved */
2167 long insns_len; /* length of insns; mips16 only */
2170 extern struct mips_frame_info current_frame_info;
2172 /* If defined, this macro specifies a table of register pairs used to
2173 eliminate unneeded registers that point into the stack frame. If
2174 it is not defined, the only elimination attempted by the compiler
2175 is to replace references to the frame pointer with references to
2178 The definition of this macro is a list of structure
2179 initializations, each of which specifies an original and
2180 replacement register.
2182 On some machines, the position of the argument pointer is not
2183 known until the compilation is completed. In such a case, a
2184 separate hard register must be used for the argument pointer.
2185 This register can be eliminated by replacing it with either the
2186 frame pointer or the argument pointer, depending on whether or not
2187 the frame pointer has been eliminated.
2189 In this case, you might specify:
2190 #define ELIMINABLE_REGS \
2191 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2192 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2193 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2195 Note that the elimination of the argument pointer with the stack
2196 pointer is specified first since that is the preferred elimination.
2198 The eliminations to $17 are only used on the mips16. See the
2199 definition of HARD_FRAME_POINTER_REGNUM. */
2201 #define ELIMINABLE_REGS \
2202 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2203 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2204 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2205 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2206 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2207 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2208 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2209 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2210 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2211 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2213 /* A C expression that returns non-zero if the compiler is allowed to
2214 try to replace register number FROM-REG with register number
2215 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2216 defined, and will usually be the constant 1, since most of the
2217 cases preventing register elimination are things that the compiler
2218 already knows about.
2220 When not in mips16 and mips64, we can always eliminate to the
2221 frame pointer. We can eliminate to the stack pointer unless
2222 a frame pointer is needed. In mips16 mode, we need a frame
2223 pointer for a large frame; otherwise, reload may be unable
2224 to compute the address of a local variable, since there is
2225 no way to add a large constant to the stack pointer
2226 without using a temporary register.
2228 In mips16, for some instructions (eg lwu), we can't eliminate the
2229 frame pointer for the stack pointer. These instructions are
2230 only generated in TARGET_64BIT mode.
2233 #define CAN_ELIMINATE(FROM, TO) \
2234 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2235 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2236 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2237 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2238 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2239 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2240 && (! TARGET_MIPS16 \
2241 || compute_frame_size (get_frame_size ()) < 32768)))))
2243 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2244 specifies the initial difference between the specified pair of
2245 registers. This macro must be defined if `ELIMINABLE_REGS' is
2248 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2249 { compute_frame_size (get_frame_size ()); \
2250 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2251 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2252 (OFFSET) = - current_function_outgoing_args_size; \
2253 else if ((FROM) == FRAME_POINTER_REGNUM) \
2255 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2256 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2257 (OFFSET) = (current_frame_info.total_size \
2258 - current_function_outgoing_args_size \
2259 - ((mips_abi != ABI_32 \
2260 && mips_abi != ABI_O64 \
2261 && mips_abi != ABI_EABI) \
2262 ? current_function_pretend_args_size \
2264 else if ((FROM) == ARG_POINTER_REGNUM) \
2265 (OFFSET) = (current_frame_info.total_size \
2266 - ((mips_abi != ABI_32 \
2267 && mips_abi != ABI_O64 \
2268 && mips_abi != ABI_EABI) \
2269 ? current_function_pretend_args_size \
2271 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2272 so we must add 4 bytes to the offset to get the right value. */ \
2273 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2275 if (leaf_function_p ()) \
2277 else (OFFSET) = current_frame_info.gp_sp_offset \
2278 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2279 * (BYTES_BIG_ENDIAN != 0)); \
2283 /* If we generate an insn to push BYTES bytes,
2284 this says how many the stack pointer really advances by.
2285 On the vax, sp@- in a byte insn really pushes a word. */
2287 /* #define PUSH_ROUNDING(BYTES) 0 */
2289 /* If defined, the maximum amount of space required for outgoing
2290 arguments will be computed and placed into the variable
2291 `current_function_outgoing_args_size'. No space will be pushed
2292 onto the stack for each call; instead, the function prologue
2293 should increase the stack frame size by this amount.
2295 It is not proper to define both `PUSH_ROUNDING' and
2296 `ACCUMULATE_OUTGOING_ARGS'. */
2297 #define ACCUMULATE_OUTGOING_ARGS 1
2299 /* Offset from the argument pointer register to the first argument's
2300 address. On some machines it may depend on the data type of the
2303 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2304 the first argument's address.
2306 On the MIPS, we must skip the first argument position if we are
2307 returning a structure or a union, to account for its address being
2308 passed in $4. However, at the current time, this produces a compiler
2309 that can't bootstrap, so comment it out for now. */
2312 #define FIRST_PARM_OFFSET(FNDECL) \
2314 && TREE_TYPE (FNDECL) != 0 \
2315 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2316 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2317 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2321 #define FIRST_PARM_OFFSET(FNDECL) 0
2324 /* When a parameter is passed in a register, stack space is still
2325 allocated for it. For the MIPS, stack space must be allocated, cf
2326 Asm Lang Prog Guide page 7-8.
2328 BEWARE that some space is also allocated for non existing arguments
2329 in register. In case an argument list is of form GF used registers
2330 are a0 (a2,a3), but we should push over a1... */
2332 #define REG_PARM_STACK_SPACE(FNDECL) \
2333 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2335 /* Define this if it is the responsibility of the caller to
2336 allocate the area reserved for arguments passed in registers.
2337 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2338 of this macro is to determine whether the space is included in
2339 `current_function_outgoing_args_size'. */
2340 #define OUTGOING_REG_PARM_STACK_SPACE
2342 /* Align stack frames on 64 bits (Double Word ). */
2343 #ifndef STACK_BOUNDARY
2344 #define STACK_BOUNDARY 64
2347 /* Make sure 4 words are always allocated on the stack. */
2349 #ifndef STACK_ARGS_ADJUST
2350 #define STACK_ARGS_ADJUST(SIZE) \
2352 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2353 SIZE.constant = 4 * UNITS_PER_WORD; \
2358 /* A C expression that should indicate the number of bytes of its
2359 own arguments that a function pops on returning, or 0
2360 if the function pops no arguments and the caller must therefore
2361 pop them all after the function returns.
2363 FUNDECL is the declaration node of the function (as a tree).
2365 FUNTYPE is a C variable whose value is a tree node that
2366 describes the function in question. Normally it is a node of
2367 type `FUNCTION_TYPE' that describes the data type of the function.
2368 From this it is possible to obtain the data types of the value
2369 and arguments (if known).
2371 When a call to a library function is being considered, FUNTYPE
2372 will contain an identifier node for the library function. Thus,
2373 if you need to distinguish among various library functions, you
2374 can do so by their names. Note that "library function" in this
2375 context means a function used to perform arithmetic, whose name
2376 is known specially in the compiler and was not mentioned in the
2377 C code being compiled.
2379 STACK-SIZE is the number of bytes of arguments passed on the
2380 stack. If a variable number of bytes is passed, it is zero, and
2381 argument popping will always be the responsibility of the
2382 calling function. */
2384 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2387 /* Symbolic macros for the registers used to return integer and floating
2390 #define GP_RETURN (GP_REG_FIRST + 2)
2391 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2393 /* Symbolic macros for the first/last argument registers. */
2395 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2396 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2397 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2398 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2400 #define MAX_ARGS_IN_REGISTERS 4
2402 /* Define how to find the value returned by a library function
2403 assuming the value has mode MODE. Because we define
2404 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2405 PROMOTE_MODE does. */
2407 #define LIBCALL_VALUE(MODE) \
2409 ((GET_MODE_CLASS (MODE) != MODE_INT \
2410 || GET_MODE_SIZE (MODE) >= 4) \
2413 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2414 && (! TARGET_SINGLE_FLOAT \
2415 || GET_MODE_SIZE (MODE) <= 4)) \
2419 /* Define how to find the value returned by a function.
2420 VALTYPE is the data type of the value (as a tree).
2421 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2422 otherwise, FUNC is 0. */
2424 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2427 /* 1 if N is a possible register number for a function value.
2428 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2429 Currently, R2 and F0 are only implemented here (C has no complex type) */
2431 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2433 /* 1 if N is a possible register number for function argument passing.
2434 We have no FP argument registers when soft-float. When FP registers
2435 are 32 bits, we can't directly reference the odd numbered ones. */
2437 #define FUNCTION_ARG_REGNO_P(N) \
2438 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2439 || ((! TARGET_SOFT_FLOAT \
2440 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2441 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2442 && ! fixed_regs[N]))
2444 /* A C expression which can inhibit the returning of certain function
2445 values in registers, based on the type of value. A nonzero value says
2446 to return the function value in memory, just as large structures are
2447 always returned. Here TYPE will be a C expression of type
2448 `tree', representing the data type of the value.
2450 Note that values of mode `BLKmode' must be explicitly
2451 handled by this macro. Also, the option `-fpcc-struct-return'
2452 takes effect regardless of this macro. On most systems, it is
2453 possible to leave the macro undefined; this causes a default
2454 definition to be used, whose value is the constant 1 for BLKmode
2455 values, and 0 otherwise.
2457 GCC normally converts 1 byte structures into chars, 2 byte
2458 structs into shorts, and 4 byte structs into ints, and returns
2459 them this way. Defining the following macro overrides this,
2460 to give us MIPS cc compatibility. */
2462 #define RETURN_IN_MEMORY(TYPE) \
2463 (TYPE_MODE (TYPE) == BLKmode)
2465 /* A code distinguishing the floating point format of the target
2466 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2467 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2469 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2472 /* Define a data type for recording info about an argument list
2473 during the scan of that argument list. This data type should
2474 hold all necessary information about the function itself
2475 and about the args processed so far, enough to enable macros
2476 such as FUNCTION_ARG to determine where the next arg should go.
2478 On the mips16, we need to keep track of which floating point
2479 arguments were passed in general registers, but would have been
2480 passed in the FP regs if this were a 32 bit function, so that we
2481 can move them to the FP regs if we wind up calling a 32 bit
2482 function. We record this information in fp_code, encoded in base
2483 four. A zero digit means no floating point argument, a one digit
2484 means an SFmode argument, and a two digit means a DFmode argument,
2485 and a three digit is not used. The low order digit is the first
2486 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2487 an SFmode argument. ??? A more sophisticated approach will be
2488 needed if MIPS_ABI != ABI_32. */
2490 typedef struct mips_args {
2491 int gp_reg_found; /* whether a gp register was found yet */
2492 unsigned int arg_number; /* argument number */
2493 unsigned int arg_words; /* # total words the arguments take */
2494 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2495 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2496 int fp_code; /* Mode of FP arguments (mips16) */
2497 unsigned int num_adjusts; /* number of adjustments made */
2498 /* Adjustments made to args pass in regs. */
2499 /* ??? The size is doubled to work around a
2500 bug in the code that sets the adjustments
2502 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2505 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2506 for a call to a function whose data type is FNTYPE.
2507 For a library call, FNTYPE is 0.
2511 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2512 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2514 /* Update the data in CUM to advance over an argument
2515 of mode MODE and data type TYPE.
2516 (TYPE is null for libcalls where that information may not be available.) */
2518 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2519 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2521 /* Determine where to put an argument to a function.
2522 Value is zero to push the argument on the stack,
2523 or a hard register in which to store the argument.
2525 MODE is the argument's machine mode.
2526 TYPE is the data type of the argument (as a tree).
2527 This is null for libcalls where that information may
2529 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2530 the preceding args and about the function being called.
2531 NAMED is nonzero if this argument is a named parameter
2532 (otherwise it is an extra parameter matching an ellipsis). */
2534 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2535 function_arg( &CUM, MODE, TYPE, NAMED)
2537 /* For an arg passed partly in registers and partly in memory,
2538 this is the number of registers used.
2539 For args passed entirely in registers or entirely in memory, zero. */
2541 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2542 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2544 /* If defined, a C expression that gives the alignment boundary, in
2545 bits, of an argument with the specified mode and type. If it is
2546 not defined, `PARM_BOUNDARY' is used for all arguments. */
2548 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2550 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2552 : TYPE_ALIGN(TYPE)) \
2553 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2555 : GET_MODE_ALIGNMENT(MODE)))
2558 /* This macro generates the assembly code for function entry.
2559 FILE is a stdio stream to output the code to.
2560 SIZE is an int: how many units of temporary storage to allocate.
2561 Refer to the array `regs_ever_live' to determine which registers
2562 to save; `regs_ever_live[I]' is nonzero if register number I
2563 is ever used in the function. This macro is responsible for
2564 knowing which registers should not be saved even if used. */
2566 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2568 /* This macro generates the assembly code for function exit,
2569 on machines that need it. If FUNCTION_EPILOGUE is not defined
2570 then individual return instructions are generated for each
2571 return statement. Args are same as for FUNCTION_PROLOGUE. */
2573 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2575 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2577 #define MUST_SAVE_REGISTER(regno) \
2578 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2579 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2580 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2582 /* ALIGN FRAMES on double word boundaries */
2583 #ifndef MIPS_STACK_ALIGN
2584 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2588 /* Define the `__builtin_va_list' type for the ABI. */
2589 #define BUILD_VA_LIST_TYPE(VALIST) \
2590 (VALIST) = mips_build_va_list ()
2592 /* Implement `va_start' for varargs and stdarg. */
2593 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2594 mips_va_start (stdarg, valist, nextarg)
2596 /* Implement `va_arg'. */
2597 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2598 mips_va_arg (valist, type)
2600 /* Output assembler code to FILE to increment profiler label # LABELNO
2601 for profiling a function entry. */
2603 #define FUNCTION_PROFILER(FILE, LABELNO) \
2605 if (TARGET_MIPS16) \
2606 sorry ("mips16 function profiling"); \
2607 fprintf (FILE, "\t.set\tnoreorder\n"); \
2608 fprintf (FILE, "\t.set\tnoat\n"); \
2609 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2610 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2611 fprintf (FILE, "\tjal\t_mcount\n"); \
2613 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2614 TARGET_64BIT ? "dsubu" : "subu", \
2615 reg_names[STACK_POINTER_REGNUM], \
2616 reg_names[STACK_POINTER_REGNUM], \
2617 Pmode == DImode ? 16 : 8); \
2618 fprintf (FILE, "\t.set\treorder\n"); \
2619 fprintf (FILE, "\t.set\tat\n"); \
2622 /* Define this macro if the code for function profiling should come
2623 before the function prologue. Normally, the profiling code comes
2626 /* #define PROFILE_BEFORE_PROLOGUE */
2628 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2629 the stack pointer does not matter. The value is tested only in
2630 functions that have frame pointers.
2631 No definition is equivalent to always zero. */
2633 #define EXIT_IGNORE_STACK 1
2636 /* A C statement to output, on the stream FILE, assembler code for a
2637 block of data that contains the constant parts of a trampoline.
2638 This code should not include a label--the label is taken care of
2641 #define TRAMPOLINE_TEMPLATE(STREAM) \
2643 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2644 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2645 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2646 if (Pmode == DImode) \
2648 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2649 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2653 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2654 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2656 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2657 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2658 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2659 if (Pmode == DImode) \
2661 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2662 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2666 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2667 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2671 /* A C expression for the size in bytes of the trampoline, as an
2674 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2676 /* Alignment required for trampolines, in bits. */
2678 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2680 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2681 program and data caches. */
2683 #ifndef CACHE_FLUSH_FUNC
2684 #define CACHE_FLUSH_FUNC "_flush_cache"
2687 /* A C statement to initialize the variable parts of a trampoline.
2688 ADDR is an RTX for the address of the trampoline; FNADDR is an
2689 RTX for the address of the nested function; STATIC_CHAIN is an
2690 RTX for the static chain value that should be passed to the
2691 function when it is called. */
2693 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2696 if (Pmode == DImode) \
2698 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2699 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2703 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2704 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2707 /* Flush both caches. We need to flush the data cache in case \
2708 the system has a write-back cache. */ \
2709 /* ??? Should check the return value for errors. */ \
2710 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2711 0, VOIDmode, 3, addr, Pmode, \
2712 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2713 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2716 /* Addressing modes, and classification of registers for them. */
2718 /* #define HAVE_POST_INCREMENT 0 */
2719 /* #define HAVE_POST_DECREMENT 0 */
2721 /* #define HAVE_PRE_DECREMENT 0 */
2722 /* #define HAVE_PRE_INCREMENT 0 */
2724 /* These assume that REGNO is a hard or pseudo reg number.
2725 They give nonzero only if REGNO is a hard reg of the suitable class
2726 or a pseudo reg currently allocated to a suitable hard reg.
2727 These definitions are NOT overridden anywhere. */
2729 #define BASE_REG_P(regno, mode) \
2731 ? (M16_REG_P (regno) \
2732 || (regno) == FRAME_POINTER_REGNUM \
2733 || (regno) == ARG_POINTER_REGNUM \
2734 || ((regno) == STACK_POINTER_REGNUM \
2735 && (GET_MODE_SIZE (mode) == 4 \
2736 || GET_MODE_SIZE (mode) == 8))) \
2739 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2740 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2743 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2744 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2746 #define REGNO_OK_FOR_INDEX_P(regno) 0
2747 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2748 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2750 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2751 and check its validity for a certain class.
2752 We have two alternate definitions for each of them.
2753 The usual definition accepts all pseudo regs; the other rejects them all.
2754 The symbol REG_OK_STRICT causes the latter definition to be used.
2756 Most source files want to accept pseudo regs in the hope that
2757 they will get allocated to the class that the insn wants them to be in.
2758 Some source files that are used after register allocation
2759 need to be strict. */
2761 #ifndef REG_OK_STRICT
2762 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2763 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2765 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2766 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2769 #define REG_OK_FOR_INDEX_P(X) 0
2772 /* Maximum number of registers that can appear in a valid memory address. */
2774 #define MAX_REGS_PER_ADDRESS 1
2776 /* A C compound statement with a conditional `goto LABEL;' executed
2777 if X (an RTX) is a legitimate memory address on the target
2778 machine for a memory operand of mode MODE.
2780 It usually pays to define several simpler macros to serve as
2781 subroutines for this one. Otherwise it may be too complicated
2784 This macro must exist in two variants: a strict variant and a
2785 non-strict one. The strict variant is used in the reload pass.
2786 It must be defined so that any pseudo-register that has not been
2787 allocated a hard register is considered a memory reference. In
2788 contexts where some kind of register is required, a
2789 pseudo-register with no hard register must be rejected.
2791 The non-strict variant is used in other passes. It must be
2792 defined to accept all pseudo-registers in every context where
2793 some kind of register is required.
2795 Compiler source files that want to use the strict variant of
2796 this macro define the macro `REG_OK_STRICT'. You should use an
2797 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2798 in that case and the non-strict variant otherwise.
2800 Typically among the subroutines used to define
2801 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2802 acceptable registers for various purposes (one for base
2803 registers, one for index registers, and so on). Then only these
2804 subroutine macros need have two variants; the higher levels of
2805 macros may be the same whether strict or not.
2807 Normally, constant addresses which are the sum of a `symbol_ref'
2808 and an integer are stored inside a `const' RTX to mark them as
2809 constant. Therefore, there is no need to recognize such sums
2810 specifically as legitimate addresses. Normally you would simply
2811 recognize any `const' as legitimate.
2813 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2814 constant sums that are not marked with `const'. It assumes
2815 that a naked `plus' indicates indexing. If so, then you *must*
2816 reject such naked constant sums as illegitimate addresses, so
2817 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2819 On some machines, whether a symbolic address is legitimate
2820 depends on the section that the address refers to. On these
2821 machines, define the macro `ENCODE_SECTION_INFO' to store the
2822 information into the `symbol_ref', and then check for it here.
2823 When you see a `const', you will have to look inside it to find
2824 the `symbol_ref' in order to determine the section. */
2827 #define GO_PRINTF(x) fprintf(stderr, (x))
2828 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2829 #define GO_DEBUG_RTX(x) debug_rtx(x)
2832 #define GO_PRINTF(x)
2833 #define GO_PRINTF2(x,y)
2834 #define GO_DEBUG_RTX(x)
2837 #ifdef REG_OK_STRICT
2838 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2840 if (mips_legitimate_address_p (MODE, X, 1)) \
2844 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2846 if (mips_legitimate_address_p (MODE, X, 0)) \
2851 /* A C expression that is 1 if the RTX X is a constant which is a
2852 valid address. This is defined to be the same as `CONSTANT_P (X)',
2853 but rejecting CONST_DOUBLE. */
2854 /* When pic, we must reject addresses of the form symbol+large int.
2855 This is because an instruction `sw $4,s+70000' needs to be converted
2856 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2857 assembler would use $at as a temp to load in the large offset. In this
2858 case $at is already in use. We convert such problem addresses to
2859 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2860 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2861 #define CONSTANT_ADDRESS_P(X) \
2862 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2863 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2864 || (GET_CODE (X) == CONST \
2865 && ! (flag_pic && pic_address_needs_scratch (X)) \
2866 && (mips_abi == ABI_32 \
2867 || mips_abi == ABI_O64 \
2868 || mips_abi == ABI_EABI))) \
2869 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2871 /* Define this, so that when PIC, reload won't try to reload invalid
2872 addresses which require two reload registers. */
2874 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2876 /* Nonzero if the constant value X is a legitimate general operand.
2877 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2879 At present, GAS doesn't understand li.[sd], so don't allow it
2880 to be generated at present. Also, the MIPS assembler does not
2881 grok li.d Infinity. */
2883 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2884 Note that the Irix 6 assembler problem may already be fixed.
2885 Note also that the GET_CODE (X) == CONST test catches the mips16
2886 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2887 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2888 ABI_64 to work together, we'll need to fix this. */
2889 #define LEGITIMATE_CONSTANT_P(X) \
2890 ((GET_CODE (X) != CONST_DOUBLE \
2891 || mips_const_double_ok (X, GET_MODE (X))) \
2892 && ! (GET_CODE (X) == CONST \
2894 && (mips_abi == ABI_N32 \
2895 || mips_abi == ABI_64)) \
2896 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2898 /* A C compound statement that attempts to replace X with a valid
2899 memory address for an operand of mode MODE. WIN will be a C
2900 statement label elsewhere in the code; the macro definition may
2903 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2905 to avoid further processing if the address has become legitimate.
2907 X will always be the result of a call to `break_out_memory_refs',
2908 and OLDX will be the operand that was given to that function to
2911 The code generated by this macro should not alter the
2912 substructure of X. If it transforms X into a more legitimate
2913 form, it should assign X (which will always be a C variable) a
2916 It is not necessary for this macro to come up with a legitimate
2917 address. The compiler has standard ways of doing so in all
2918 cases. In fact, it is safe for this macro to do nothing. But
2919 often a machine-dependent strategy can generate better code.
2921 For the MIPS, transform:
2923 memory(X + <large int>)
2927 Y = <large int> & ~0x7fff;
2929 memory (Z + (<large int> & 0x7fff));
2931 This is for CSE to find several similar references, and only use one Z.
2933 When PIC, convert addresses of the form memory (symbol+large int) to
2934 memory (reg+large int). */
2937 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2939 register rtx xinsn = (X); \
2941 if (TARGET_DEBUG_B_MODE) \
2943 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2944 GO_DEBUG_RTX (xinsn); \
2947 if (mips_split_addresses && mips_check_split (X, MODE)) \
2949 /* ??? Is this ever executed? */ \
2950 X = gen_rtx_LO_SUM (Pmode, \
2951 copy_to_mode_reg (Pmode, \
2952 gen_rtx (HIGH, Pmode, X)), \
2957 if (GET_CODE (xinsn) == CONST \
2958 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2959 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2960 || (mips_abi != ABI_32 \
2961 && mips_abi != ABI_O64 \
2962 && mips_abi != ABI_EABI))) \
2964 rtx ptr_reg = gen_reg_rtx (Pmode); \
2965 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2967 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2969 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
2970 if (SMALL_INT (constant)) \
2972 /* Otherwise we fall through so the code below will fix the \
2977 if (GET_CODE (xinsn) == PLUS) \
2979 register rtx xplus0 = XEXP (xinsn, 0); \
2980 register rtx xplus1 = XEXP (xinsn, 1); \
2981 register enum rtx_code code0 = GET_CODE (xplus0); \
2982 register enum rtx_code code1 = GET_CODE (xplus1); \
2984 if (code0 != REG && code1 == REG) \
2986 xplus0 = XEXP (xinsn, 1); \
2987 xplus1 = XEXP (xinsn, 0); \
2988 code0 = GET_CODE (xplus0); \
2989 code1 = GET_CODE (xplus1); \
2992 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2993 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2995 rtx int_reg = gen_reg_rtx (Pmode); \
2996 rtx ptr_reg = gen_reg_rtx (Pmode); \
2998 emit_move_insn (int_reg, \
2999 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3001 emit_insn (gen_rtx_SET (VOIDmode, \
3003 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3005 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3010 if (TARGET_DEBUG_B_MODE) \
3011 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3015 /* A C statement or compound statement with a conditional `goto
3016 LABEL;' executed if memory address X (an RTX) can have different
3017 meanings depending on the machine mode of the memory reference it
3020 Autoincrement and autodecrement addresses typically have
3021 mode-dependent effects because the amount of the increment or
3022 decrement is the size of the operand being addressed. Some
3023 machines have other mode-dependent addresses. Many RISC machines
3024 have no mode-dependent addresses.
3026 You may assume that ADDR is a valid address for the machine. */
3028 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3031 /* Define this macro if references to a symbol must be treated
3032 differently depending on something about the variable or
3033 function named by the symbol (such as what section it is in).
3035 The macro definition, if any, is executed immediately after the
3036 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3037 The value of the rtl will be a `mem' whose address is a
3040 The usual thing for this macro to do is to a flag in the
3041 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3042 name string in the `symbol_ref' (if one bit is not enough
3045 The best way to modify the name string is by adding text to the
3046 beginning, with suitable punctuation to prevent any ambiguity.
3047 Allocate the new name in `saveable_obstack'. You will have to
3048 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3049 and output the name accordingly.
3051 You can also check the information stored in the `symbol_ref' in
3052 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3053 `PRINT_OPERAND_ADDRESS'.
3055 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3058 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3059 symbols which are not in the .text section.
3061 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3062 constants which are put in the .text section. We also record the
3063 total length of all such strings; this total is used to decide
3064 whether we need to split the constant table, and need not be
3067 When not mips16 code nor embedded PIC, if a symbol is in a
3068 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3069 splitting the reference so that gas can generate a gp relative
3072 When TARGET_EMBEDDED_DATA is set, we assume that all const
3073 variables will be stored in ROM, which is too far from %gp to use
3074 %gprel addressing. Note that (1) we include "extern const"
3075 variables in this, which mips_select_section doesn't, and (2) we
3076 can't always tell if they're really const (they might be const C++
3077 objects with non-const constructors), so we err on the side of
3078 caution and won't use %gprel anyway (otherwise we'd have to defer
3079 this decision to the linker/loader). The handling of extern consts
3080 is why the DECL_INITIAL macros differ from mips_select_section.
3082 If you are changing this macro, you should look at
3083 mips_select_section and see if it needs a similar change. */
3085 #ifndef UNIQUE_SECTION_P
3086 #define UNIQUE_SECTION_P(DECL) (0)
3089 #define ENCODE_SECTION_INFO(DECL) \
3092 if (TARGET_MIPS16) \
3094 if (TREE_CODE (DECL) == STRING_CST \
3095 && ! flag_writable_strings \
3096 /* If this string is from a function, and the function will \
3097 go in a gnu linkonce section, then we can't directly \
3098 access the string. This gets an assembler error \
3099 "unsupported PC relative reference to different section".\
3100 If we modify SELECT_SECTION to put it in function_section\
3101 instead of text_section, it still fails because \
3102 DECL_SECTION_NAME isn't set until assemble_start_function.\
3103 If we fix that, it still fails because strings are shared\
3104 among multiple functions, and we have cross section \
3105 references again. We force it to work by putting string \
3106 addresses in the constant pool and indirecting. */ \
3107 && (! current_function_decl \
3108 || ! UNIQUE_SECTION_P (current_function_decl))) \
3110 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3111 mips_string_length += TREE_STRING_LENGTH (DECL); \
3115 if (TARGET_EMBEDDED_DATA \
3116 && (TREE_CODE (DECL) == VAR_DECL \
3117 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3118 && (!DECL_INITIAL (DECL) \
3119 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3121 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3124 else if (TARGET_EMBEDDED_PIC) \
3126 if (TREE_CODE (DECL) == VAR_DECL) \
3127 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3128 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3129 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3130 else if (TREE_CODE (DECL) == STRING_CST \
3131 && ! flag_writable_strings) \
3132 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3134 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3137 else if (TREE_CODE (DECL) == VAR_DECL \
3138 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3139 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3141 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3144 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3147 /* We can not perform GP optimizations on variables which are in \
3148 specific sections, except for .sdata and .sbss which are \
3150 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3151 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3153 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3155 if (size > 0 && size <= mips_section_threshold) \
3156 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3159 else if (HALF_PIC_P ()) \
3161 HALF_PIC_ENCODE (DECL); \
3166 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3167 'the start of the function that this code is output in'. */
3169 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3170 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3171 asm_fprintf ((FILE), "%U%s", \
3172 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3174 asm_fprintf ((FILE), "%U%s", (NAME))
3176 /* The mips16 wants the constant pool to be after the function,
3177 because the PC relative load instructions use unsigned offsets. */
3179 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3181 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3182 mips_string_length = 0;
3185 /* In mips16 mode, put most string constants after the function. */
3186 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3187 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3190 /* Specify the machine mode that this machine uses
3191 for the index in the tablejump instruction.
3192 ??? Using HImode in mips16 mode can cause overflow. However, the
3193 overflow is no more likely than the overflow in a branch
3194 instruction. Large functions can currently break in both ways. */
3195 #define CASE_VECTOR_MODE \
3196 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3198 /* Define as C expression which evaluates to nonzero if the tablejump
3199 instruction expects the table to contain offsets from the address of the
3201 Do not define this if the table should contain absolute addresses. */
3202 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3204 /* Specify the tree operation to be used to convert reals to integers. */
3205 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3207 /* This is the kind of divide that is easiest to do in the general case. */
3208 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3210 /* Define this as 1 if `char' should by default be signed; else as 0. */
3211 #ifndef DEFAULT_SIGNED_CHAR
3212 #define DEFAULT_SIGNED_CHAR 1
3215 /* Max number of bytes we can move from memory to memory
3216 in one reasonably fast instruction. */
3217 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3218 #define MAX_MOVE_MAX 8
3220 /* Define this macro as a C expression which is nonzero if
3221 accessing less than a word of memory (i.e. a `char' or a
3222 `short') is no faster than accessing a word of memory, i.e., if
3223 such access require more than one instruction or if there is no
3224 difference in cost between byte and (aligned) word loads.
3226 On RISC machines, it tends to generate better code to define
3227 this as 1, since it avoids making a QI or HI mode register. */
3228 #define SLOW_BYTE_ACCESS 1
3230 /* We assume that the store-condition-codes instructions store 0 for false
3231 and some other value for true. This is the value stored for true. */
3233 #define STORE_FLAG_VALUE 1
3235 /* Define this if zero-extension is slow (more than one real instruction). */
3236 #define SLOW_ZERO_EXTEND
3238 /* Define this to be nonzero if shift instructions ignore all but the low-order
3240 #define SHIFT_COUNT_TRUNCATED 1
3242 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3243 is done just by pretending it is already truncated. */
3244 /* In 64 bit mode, 32 bit instructions require that register values be properly
3245 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3246 converts a value >32 bits to a value <32 bits. */
3247 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3248 Something needs to be done about this. Perhaps not use any 32 bit
3249 instructions? Perhaps use PROMOTE_MODE? */
3250 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3251 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3253 /* Specify the machine mode that pointers have.
3254 After generation of rtl, the compiler makes no further distinction
3255 between pointers and any other objects of this machine mode.
3257 For MIPS we make pointers are the smaller of longs and gp-registers. */
3260 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3263 /* A function address in a call instruction
3264 is a word address (for indexing purposes)
3265 so give the MEM rtx a words's mode. */
3267 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3269 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3270 memset, instead of the BSD functions bcopy and bzero. */
3272 #if defined(MIPS_SYSV) || defined(OSF_OS)
3273 #define TARGET_MEM_FUNCTIONS
3277 /* A part of a C `switch' statement that describes the relative
3278 costs of constant RTL expressions. It must contain `case'
3279 labels for expression codes `const_int', `const', `symbol_ref',
3280 `label_ref' and `const_double'. Each case must ultimately reach
3281 a `return' statement to return the relative cost of the use of
3282 that kind of constant value in an expression. The cost may
3283 depend on the precise value of the constant, which is available
3284 for examination in X.
3286 CODE is the expression code--redundant, since it can be obtained
3287 with `GET_CODE (X)'. */
3289 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3291 if (! TARGET_MIPS16) \
3293 /* Always return 0, since we don't have different sized \
3294 instructions, hence different costs according to Richard \
3298 if ((OUTER_CODE) == SET) \
3300 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3302 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3303 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3304 return COSTS_N_INSNS (1); \
3306 return COSTS_N_INSNS (2); \
3308 /* A PLUS could be an address. We don't want to force an address \
3309 to use a register, so accept any signed 16 bit value without \
3311 if ((OUTER_CODE) == PLUS \
3312 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3314 /* A number between 1 and 8 inclusive is efficient for a shift. \
3315 Otherwise, we will need an extended instruction. */ \
3316 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3317 || (OUTER_CODE) == LSHIFTRT) \
3319 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3321 return COSTS_N_INSNS (1); \
3323 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3324 if ((OUTER_CODE) == XOR \
3325 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3327 /* We may be able to use slt or sltu for a comparison with a \
3328 signed 16 bit value. (The boundary conditions aren't quite \
3329 right, but this is just a heuristic anyhow.) */ \
3330 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3331 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3332 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3333 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3334 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3336 /* Equality comparisons with 0 are cheap. */ \
3337 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3338 && INTVAL (X) == 0) \
3341 /* Otherwise, work out the cost to load the value into a \
3343 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3344 return COSTS_N_INSNS (1); \
3345 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3346 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3347 return COSTS_N_INSNS (2); \
3349 return COSTS_N_INSNS (3); \
3352 return COSTS_N_INSNS (2); \
3356 rtx offset = const0_rtx; \
3357 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3359 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3361 /* Treat this like a signed 16 bit CONST_INT. */ \
3362 if ((OUTER_CODE) == PLUS) \
3364 else if ((OUTER_CODE) == SET) \
3365 return COSTS_N_INSNS (1); \
3367 return COSTS_N_INSNS (2); \
3370 if (GET_CODE (symref) == LABEL_REF) \
3371 return COSTS_N_INSNS (2); \
3373 if (GET_CODE (symref) != SYMBOL_REF) \
3374 return COSTS_N_INSNS (4); \
3376 /* let's be paranoid.... */ \
3377 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3378 return COSTS_N_INSNS (2); \
3380 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3384 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3386 case CONST_DOUBLE: \
3389 if (TARGET_MIPS16) \
3390 return COSTS_N_INSNS (4); \
3391 split_double (X, &high, &low); \
3392 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3393 || low == CONST0_RTX (GET_MODE (low))) \
3397 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3398 This can be used, for example, to indicate how costly a multiply
3399 instruction is. In writing this macro, you can use the construct
3400 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3402 This macro is optional; do not define it if the default cost
3403 assumptions are adequate for the target machine.
3405 If -mdebugd is used, change the multiply cost to 2, so multiply by
3406 a constant isn't converted to a series of shifts. This helps
3407 strength reduction, and also makes it easier to identify what the
3408 compiler is doing. */
3410 /* ??? Fix this to be right for the R8000. */
3411 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3414 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3415 if (simple_memory_operand (X, GET_MODE (X))) \
3416 return COSTS_N_INSNS (num_words); \
3418 return COSTS_N_INSNS (2*num_words); \
3422 return COSTS_N_INSNS (6); \
3425 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3430 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3431 return COSTS_N_INSNS (2); \
3438 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3439 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3445 enum machine_mode xmode = GET_MODE (X); \
3446 if (xmode == SFmode || xmode == DFmode) \
3447 return COSTS_N_INSNS (1); \
3449 return COSTS_N_INSNS (4); \
3455 enum machine_mode xmode = GET_MODE (X); \
3456 if (xmode == SFmode || xmode == DFmode) \
3458 if (mips_cpu == PROCESSOR_R3000 \
3459 || mips_cpu == PROCESSOR_R3900) \
3460 return COSTS_N_INSNS (2); \
3461 else if (mips_cpu == PROCESSOR_R6000) \
3462 return COSTS_N_INSNS (3); \
3464 return COSTS_N_INSNS (6); \
3467 if (xmode == DImode && !TARGET_64BIT) \
3468 return COSTS_N_INSNS (4); \
3474 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3481 enum machine_mode xmode = GET_MODE (X); \
3482 if (xmode == SFmode) \
3484 if (mips_cpu == PROCESSOR_R3000 \
3485 || mips_cpu == PROCESSOR_R3900 \
3486 || mips_cpu == PROCESSOR_R5000) \
3487 return COSTS_N_INSNS (4); \
3488 else if (mips_cpu == PROCESSOR_R6000) \
3489 return COSTS_N_INSNS (5); \
3491 return COSTS_N_INSNS (7); \
3494 if (xmode == DFmode) \
3496 if (mips_cpu == PROCESSOR_R3000 \
3497 || mips_cpu == PROCESSOR_R3900 \
3498 || mips_cpu == PROCESSOR_R5000) \
3499 return COSTS_N_INSNS (5); \
3500 else if (mips_cpu == PROCESSOR_R6000) \
3501 return COSTS_N_INSNS (6); \
3503 return COSTS_N_INSNS (8); \
3506 if (mips_cpu == PROCESSOR_R3000) \
3507 return COSTS_N_INSNS (12); \
3508 else if (mips_cpu == PROCESSOR_R3900) \
3509 return COSTS_N_INSNS (2); \
3510 else if (mips_cpu == PROCESSOR_R6000) \
3511 return COSTS_N_INSNS (17); \
3512 else if (mips_cpu == PROCESSOR_R5000) \
3513 return COSTS_N_INSNS (5); \
3515 return COSTS_N_INSNS (10); \
3521 enum machine_mode xmode = GET_MODE (X); \
3522 if (xmode == SFmode) \
3524 if (mips_cpu == PROCESSOR_R3000 \
3525 || mips_cpu == PROCESSOR_R3900) \
3526 return COSTS_N_INSNS (12); \
3527 else if (mips_cpu == PROCESSOR_R6000) \
3528 return COSTS_N_INSNS (15); \
3530 return COSTS_N_INSNS (23); \
3533 if (xmode == DFmode) \
3535 if (mips_cpu == PROCESSOR_R3000 \
3536 || mips_cpu == PROCESSOR_R3900) \
3537 return COSTS_N_INSNS (19); \
3538 else if (mips_cpu == PROCESSOR_R6000) \
3539 return COSTS_N_INSNS (16); \
3541 return COSTS_N_INSNS (36); \
3544 /* fall through */ \
3548 if (mips_cpu == PROCESSOR_R3000 \
3549 || mips_cpu == PROCESSOR_R3900) \
3550 return COSTS_N_INSNS (35); \
3551 else if (mips_cpu == PROCESSOR_R6000) \
3552 return COSTS_N_INSNS (38); \
3553 else if (mips_cpu == PROCESSOR_R5000) \
3554 return COSTS_N_INSNS (36); \
3556 return COSTS_N_INSNS (69); \
3559 /* A sign extend from SImode to DImode in 64 bit mode is often \
3560 zero instructions, because the result can often be used \
3561 directly by another instruction; we'll call it one. */ \
3562 if (TARGET_64BIT && GET_MODE (X) == DImode \
3563 && GET_MODE (XEXP (X, 0)) == SImode) \
3564 return COSTS_N_INSNS (1); \
3566 return COSTS_N_INSNS (2); \
3569 if (TARGET_64BIT && GET_MODE (X) == DImode \
3570 && GET_MODE (XEXP (X, 0)) == SImode) \
3571 return COSTS_N_INSNS (2); \
3573 return COSTS_N_INSNS (1);
3575 /* An expression giving the cost of an addressing mode that
3576 contains ADDRESS. If not defined, the cost is computed from the
3577 form of the ADDRESS expression and the `CONST_COSTS' values.
3579 For most CISC machines, the default cost is a good approximation
3580 of the true cost of the addressing mode. However, on RISC
3581 machines, all instructions normally have the same length and
3582 execution time. Hence all addresses will have equal costs.
3584 In cases where more than one form of an address is known, the
3585 form with the lowest cost will be used. If multiple forms have
3586 the same, lowest, cost, the one that is the most complex will be
3589 For example, suppose an address that is equal to the sum of a
3590 register and a constant is used twice in the same basic block.
3591 When this macro is not defined, the address will be computed in
3592 a register and memory references will be indirect through that
3593 register. On machines where the cost of the addressing mode
3594 containing the sum is no higher than that of a simple indirect
3595 reference, this will produce an additional instruction and
3596 possibly require an additional register. Proper specification
3597 of this macro eliminates this overhead for such machines.
3599 Similar use of this macro is made in strength reduction of loops.
3601 ADDRESS need not be valid as an address. In such a case, the
3602 cost is not relevant and can be any value; invalid addresses
3603 need not be assigned a different cost.
3605 On machines where an address involving more than one register is
3606 as cheap as an address computation involving only one register,
3607 defining `ADDRESS_COST' to reflect this can cause two registers
3608 to be live over a region of code where only one would have been
3609 if `ADDRESS_COST' were not defined in that manner. This effect
3610 should be considered in the definition of this macro.
3611 Equivalent costs should probably only be given to addresses with
3612 different numbers of registers on machines with lots of registers.
3614 This macro will normally either not be defined or be defined as
3617 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3619 /* A C expression for the cost of moving data from a register in
3620 class FROM to one in class TO. The classes are expressed using
3621 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3622 the default; other values are interpreted relative to that.
3624 It is not required that the cost always equal 2 when FROM is the
3625 same as TO; on some machines it is expensive to move between
3626 registers if they are not general registers.
3628 If reload sees an insn consisting of a single `set' between two
3629 hard registers, and if `REGISTER_MOVE_COST' applied to their
3630 classes returns a value of 2, reload does not check to ensure
3631 that the constraints of the insn are met. Setting a cost of
3632 other than 2 will allow reload to verify that the constraints are
3633 met. You should do this if the `movM' pattern's constraints do
3634 not allow such copying.
3636 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3637 registers the same as for one of moving general registers to
3638 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3639 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3640 isn't clear if it is wise. And it might not work in all cases. We
3641 could solve the DImode LO reg problem by using a multiply, just like
3642 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3643 by using divide instructions. divu puts the remainder in the HI
3644 reg, so doing a divide by -1 will move the value in the HI reg for
3645 all values except -1. We could handle that case by using a signed
3646 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3647 compare/branch to test the input value to see which instruction we
3648 need to use. This gets pretty messy, but it is feasible. */
3650 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3651 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3652 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3653 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3654 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3655 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3656 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3657 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3658 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3659 : (((FROM) == HI_REG || (FROM) == LO_REG \
3660 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3661 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3662 : (((TO) == HI_REG || (TO) == LO_REG \
3663 || (TO) == MD_REGS || (TO) == HILO_REG) \
3664 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3665 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3666 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3669 /* ??? Fix this to be right for the R8000. */
3670 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3671 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3672 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3674 /* Define if copies to/from condition code registers should be avoided.
3676 This is needed for the MIPS because reload_outcc is not complete;
3677 it needs to handle cases where the source is a general or another
3678 condition code register. */
3679 #define AVOID_CCMODE_COPIES
3681 /* A C expression for the cost of a branch instruction. A value of
3682 1 is the default; other values are interpreted relative to that. */
3684 /* ??? Fix this to be right for the R8000. */
3685 #define BRANCH_COST \
3687 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3690 /* A C statement (sans semicolon) to update the integer variable COST
3691 based on the relationship between INSN that is dependent on
3692 DEP_INSN through the dependence LINK. The default is to make no
3693 adjustment to COST. On the MIPS, ignore the cost of anti- and
3694 output-dependencies. */
3696 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3697 if (REG_NOTE_KIND (LINK) != 0) \
3698 (COST) = 0; /* Anti or output dependence. */
3700 /* If defined, modifies the length assigned to instruction INSN as a
3701 function of the context in which it is used. LENGTH is an lvalue
3702 that contains the initially computed length of the insn and should
3703 be updated with the correct length of the insn. */
3704 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3705 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3708 /* Optionally define this if you have added predicates to
3709 `MACHINE.c'. This macro is called within an initializer of an
3710 array of structures. The first field in the structure is the
3711 name of a predicate and the second field is an array of rtl
3712 codes. For each predicate, list all rtl codes that can be in
3713 expressions matched by the predicate. The list should have a
3714 trailing comma. Here is an example of two entries in the list
3715 for a typical RISC machine:
3717 #define PREDICATE_CODES \
3718 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3719 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3721 Defining this macro does not affect the generated code (however,
3722 incorrect definitions that omit an rtl code that may be matched
3723 by the predicate can cause the compiler to malfunction).
3724 Instead, it allows the table built by `genrecog' to be more
3725 compact and efficient, thus speeding up the compiler. The most
3726 important predicates to include in the list specified by this
3727 macro are thoses used in the most insn patterns. */
3729 #define PREDICATE_CODES \
3730 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3731 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3732 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3733 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3734 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3735 {"small_int", { CONST_INT }}, \
3736 {"large_int", { CONST_INT }}, \
3737 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3738 {"const_float_1_operand", { CONST_DOUBLE }}, \
3739 {"simple_memory_operand", { MEM, SUBREG }}, \
3740 {"equality_op", { EQ, NE }}, \
3741 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3743 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3744 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3745 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3746 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3747 SYMBOL_REF, LABEL_REF, SUBREG, \
3749 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3750 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3751 MEM, SIGN_EXTEND }}, \
3752 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3753 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3755 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3757 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3759 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3760 SYMBOL_REF, LABEL_REF, SUBREG, \
3761 REG, SIGN_EXTEND }}, \
3762 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3763 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3764 CONST_DOUBLE, CONST }}, \
3765 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3766 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3768 /* A list of predicates that do special things with modes, and so
3769 should not elicit warnings for VOIDmode match_operand. */
3771 #define SPECIAL_MODE_PREDICATES \
3772 "pc_or_label_operand",
3775 /* If defined, a C statement to be executed just prior to the
3776 output of assembler code for INSN, to modify the extracted
3777 operands so they will be output differently.
3779 Here the argument OPVEC is the vector containing the operands
3780 extracted from INSN, and NOPERANDS is the number of elements of
3781 the vector which contain meaningful data for this insn. The
3782 contents of this vector are what will be used to convert the
3783 insn template into assembler code, so you can change the
3784 assembler output by changing the contents of the vector.
3786 We use it to check if the current insn needs a nop in front of it
3787 because of load delays, and also to update the delay slot
3790 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3791 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3794 /* Control the assembler format that we output. */
3796 /* Output at beginning of assembler file.
3797 If we are optimizing to use the global pointer, create a temporary
3798 file to hold all of the text stuff, and write it out to the end.
3799 This is needed because the MIPS assembler is evidently one pass,
3800 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3801 declaration when the code is processed, it generates a two
3802 instruction sequence. */
3804 #undef ASM_FILE_START
3805 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3807 /* Output to assembler file text saying following lines
3808 may contain character constants, extra white space, comments, etc. */
3810 #define ASM_APP_ON " #APP\n"
3812 /* Output to assembler file text saying following lines
3813 no longer contain unusual constructs. */
3815 #define ASM_APP_OFF " #NO_APP\n"
3817 /* How to refer to registers in assembler output.
3818 This sequence is indexed by compiler's hard-register-number (see above).
3820 In order to support the two different conventions for register names,
3821 we use the name of a table set up in mips.c, which is overwritten
3822 if -mrnames is used. */
3824 #define REGISTER_NAMES \
3826 &mips_reg_names[ 0][0], \
3827 &mips_reg_names[ 1][0], \
3828 &mips_reg_names[ 2][0], \
3829 &mips_reg_names[ 3][0], \
3830 &mips_reg_names[ 4][0], \
3831 &mips_reg_names[ 5][0], \
3832 &mips_reg_names[ 6][0], \
3833 &mips_reg_names[ 7][0], \
3834 &mips_reg_names[ 8][0], \
3835 &mips_reg_names[ 9][0], \
3836 &mips_reg_names[10][0], \
3837 &mips_reg_names[11][0], \
3838 &mips_reg_names[12][0], \
3839 &mips_reg_names[13][0], \
3840 &mips_reg_names[14][0], \
3841 &mips_reg_names[15][0], \
3842 &mips_reg_names[16][0], \
3843 &mips_reg_names[17][0], \
3844 &mips_reg_names[18][0], \
3845 &mips_reg_names[19][0], \
3846 &mips_reg_names[20][0], \
3847 &mips_reg_names[21][0], \
3848 &mips_reg_names[22][0], \
3849 &mips_reg_names[23][0], \
3850 &mips_reg_names[24][0], \
3851 &mips_reg_names[25][0], \
3852 &mips_reg_names[26][0], \
3853 &mips_reg_names[27][0], \
3854 &mips_reg_names[28][0], \
3855 &mips_reg_names[29][0], \
3856 &mips_reg_names[30][0], \
3857 &mips_reg_names[31][0], \
3858 &mips_reg_names[32][0], \
3859 &mips_reg_names[33][0], \
3860 &mips_reg_names[34][0], \
3861 &mips_reg_names[35][0], \
3862 &mips_reg_names[36][0], \
3863 &mips_reg_names[37][0], \
3864 &mips_reg_names[38][0], \
3865 &mips_reg_names[39][0], \
3866 &mips_reg_names[40][0], \
3867 &mips_reg_names[41][0], \
3868 &mips_reg_names[42][0], \
3869 &mips_reg_names[43][0], \
3870 &mips_reg_names[44][0], \
3871 &mips_reg_names[45][0], \
3872 &mips_reg_names[46][0], \
3873 &mips_reg_names[47][0], \
3874 &mips_reg_names[48][0], \
3875 &mips_reg_names[49][0], \
3876 &mips_reg_names[50][0], \
3877 &mips_reg_names[51][0], \
3878 &mips_reg_names[52][0], \
3879 &mips_reg_names[53][0], \
3880 &mips_reg_names[54][0], \
3881 &mips_reg_names[55][0], \
3882 &mips_reg_names[56][0], \
3883 &mips_reg_names[57][0], \
3884 &mips_reg_names[58][0], \
3885 &mips_reg_names[59][0], \
3886 &mips_reg_names[60][0], \
3887 &mips_reg_names[61][0], \
3888 &mips_reg_names[62][0], \
3889 &mips_reg_names[63][0], \
3890 &mips_reg_names[64][0], \
3891 &mips_reg_names[65][0], \
3892 &mips_reg_names[66][0], \
3893 &mips_reg_names[67][0], \
3894 &mips_reg_names[68][0], \
3895 &mips_reg_names[69][0], \
3896 &mips_reg_names[70][0], \
3897 &mips_reg_names[71][0], \
3898 &mips_reg_names[72][0], \
3899 &mips_reg_names[73][0], \
3900 &mips_reg_names[74][0], \
3901 &mips_reg_names[75][0], \
3904 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3905 So define this for it. */
3906 #define DEBUG_REGISTER_NAMES \
3908 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3909 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3910 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3911 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3912 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3913 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3914 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3915 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3916 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3917 "$fcc5","$fcc6","$fcc7","$rap" \
3920 /* If defined, a C initializer for an array of structures
3921 containing a name and a register number. This macro defines
3922 additional names for hard registers, thus allowing the `asm'
3923 option in declarations to refer to registers using alternate
3926 We define both names for the integer registers here. */
3928 #define ADDITIONAL_REGISTER_NAMES \
3930 { "$0", 0 + GP_REG_FIRST }, \
3931 { "$1", 1 + GP_REG_FIRST }, \
3932 { "$2", 2 + GP_REG_FIRST }, \
3933 { "$3", 3 + GP_REG_FIRST }, \
3934 { "$4", 4 + GP_REG_FIRST }, \
3935 { "$5", 5 + GP_REG_FIRST }, \
3936 { "$6", 6 + GP_REG_FIRST }, \
3937 { "$7", 7 + GP_REG_FIRST }, \
3938 { "$8", 8 + GP_REG_FIRST }, \
3939 { "$9", 9 + GP_REG_FIRST }, \
3940 { "$10", 10 + GP_REG_FIRST }, \
3941 { "$11", 11 + GP_REG_FIRST }, \
3942 { "$12", 12 + GP_REG_FIRST }, \
3943 { "$13", 13 + GP_REG_FIRST }, \
3944 { "$14", 14 + GP_REG_FIRST }, \
3945 { "$15", 15 + GP_REG_FIRST }, \
3946 { "$16", 16 + GP_REG_FIRST }, \
3947 { "$17", 17 + GP_REG_FIRST }, \
3948 { "$18", 18 + GP_REG_FIRST }, \
3949 { "$19", 19 + GP_REG_FIRST }, \
3950 { "$20", 20 + GP_REG_FIRST }, \
3951 { "$21", 21 + GP_REG_FIRST }, \
3952 { "$22", 22 + GP_REG_FIRST }, \
3953 { "$23", 23 + GP_REG_FIRST }, \
3954 { "$24", 24 + GP_REG_FIRST }, \
3955 { "$25", 25 + GP_REG_FIRST }, \
3956 { "$26", 26 + GP_REG_FIRST }, \
3957 { "$27", 27 + GP_REG_FIRST }, \
3958 { "$28", 28 + GP_REG_FIRST }, \
3959 { "$29", 29 + GP_REG_FIRST }, \
3960 { "$30", 30 + GP_REG_FIRST }, \
3961 { "$31", 31 + GP_REG_FIRST }, \
3962 { "$sp", 29 + GP_REG_FIRST }, \
3963 { "$fp", 30 + GP_REG_FIRST }, \
3964 { "at", 1 + GP_REG_FIRST }, \
3965 { "v0", 2 + GP_REG_FIRST }, \
3966 { "v1", 3 + GP_REG_FIRST }, \
3967 { "a0", 4 + GP_REG_FIRST }, \
3968 { "a1", 5 + GP_REG_FIRST }, \
3969 { "a2", 6 + GP_REG_FIRST }, \
3970 { "a3", 7 + GP_REG_FIRST }, \
3971 { "t0", 8 + GP_REG_FIRST }, \
3972 { "t1", 9 + GP_REG_FIRST }, \
3973 { "t2", 10 + GP_REG_FIRST }, \
3974 { "t3", 11 + GP_REG_FIRST }, \
3975 { "t4", 12 + GP_REG_FIRST }, \
3976 { "t5", 13 + GP_REG_FIRST }, \
3977 { "t6", 14 + GP_REG_FIRST }, \
3978 { "t7", 15 + GP_REG_FIRST }, \
3979 { "s0", 16 + GP_REG_FIRST }, \
3980 { "s1", 17 + GP_REG_FIRST }, \
3981 { "s2", 18 + GP_REG_FIRST }, \
3982 { "s3", 19 + GP_REG_FIRST }, \
3983 { "s4", 20 + GP_REG_FIRST }, \
3984 { "s5", 21 + GP_REG_FIRST }, \
3985 { "s6", 22 + GP_REG_FIRST }, \
3986 { "s7", 23 + GP_REG_FIRST }, \
3987 { "t8", 24 + GP_REG_FIRST }, \
3988 { "t9", 25 + GP_REG_FIRST }, \
3989 { "k0", 26 + GP_REG_FIRST }, \
3990 { "k1", 27 + GP_REG_FIRST }, \
3991 { "gp", 28 + GP_REG_FIRST }, \
3992 { "sp", 29 + GP_REG_FIRST }, \
3993 { "fp", 30 + GP_REG_FIRST }, \
3994 { "ra", 31 + GP_REG_FIRST }, \
3995 { "$sp", 29 + GP_REG_FIRST }, \
3996 { "$fp", 30 + GP_REG_FIRST } \
3999 /* A C compound statement to output to stdio stream STREAM the
4000 assembler syntax for an instruction operand X. X is an RTL
4003 CODE is a value that can be used to specify one of several ways
4004 of printing the operand. It is used when identical operands
4005 must be printed differently depending on the context. CODE
4006 comes from the `%' specification that was used to request
4007 printing of the operand. If the specification was just `%DIGIT'
4008 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4009 is the ASCII code for LTR.
4011 If X is a register, this macro should print the register's name.
4012 The names can be found in an array `reg_names' whose type is
4013 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4015 When the machine description has a specification `%PUNCT' (a `%'
4016 followed by a punctuation character), this macro is called with
4017 a null pointer for X and the punctuation character for CODE.
4019 See mips.c for the MIPS specific codes. */
4021 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4023 /* A C expression which evaluates to true if CODE is a valid
4024 punctuation character for use in the `PRINT_OPERAND' macro. If
4025 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4026 punctuation characters (except for the standard one, `%') are
4027 used in this way. */
4029 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4031 /* A C compound statement to output to stdio stream STREAM the
4032 assembler syntax for an instruction operand that is a memory
4033 reference whose address is ADDR. ADDR is an RTL expression.
4035 On some machines, the syntax for a symbolic address depends on
4036 the section that the address refers to. On these machines,
4037 define the macro `ENCODE_SECTION_INFO' to store the information
4038 into the `symbol_ref', and then check for it here. */
4040 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4043 /* A C statement, to be executed after all slot-filler instructions
4044 have been output. If necessary, call `dbr_sequence_length' to
4045 determine the number of slots filled in a sequence (zero if not
4046 currently outputting a sequence), to decide how many no-ops to
4047 output, or whatever.
4049 Don't define this macro if it has nothing to do, but it is
4050 helpful in reading assembly output if the extent of the delay
4051 sequence is made explicit (e.g. with white space).
4053 Note that output routines for instructions with delay slots must
4054 be prepared to deal with not being output as part of a sequence
4055 (i.e. when the scheduling pass is not run, or when no slot
4056 fillers could be found.) The variable `final_sequence' is null
4057 when not processing a sequence, otherwise it contains the
4058 `sequence' rtx being output. */
4060 #define DBR_OUTPUT_SEQEND(STREAM) \
4063 if (set_nomacro > 0 && --set_nomacro == 0) \
4064 fputs ("\t.set\tmacro\n", STREAM); \
4066 if (set_noreorder > 0 && --set_noreorder == 0) \
4067 fputs ("\t.set\treorder\n", STREAM); \
4069 dslots_jump_filled++; \
4070 fputs ("\n", STREAM); \
4075 /* How to tell the debugger about changes of source files. Note, the
4076 mips ECOFF format cannot deal with changes of files inside of
4077 functions, which means the output of parser generators like bison
4078 is generally not debuggable without using the -l switch. Lose,
4079 lose, lose. Silicon graphics seems to want all .file's hardwired
4082 #ifndef SET_FILE_NUMBER
4083 #define SET_FILE_NUMBER() ++num_source_filenames
4086 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4087 mips_output_filename (STREAM, NAME)
4089 /* This is defined so that it can be overridden in iris6.h. */
4090 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4093 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4094 output_quoted_string (STREAM, NAME); \
4095 fputs ("\n", STREAM); \
4099 /* This is how to output a note the debugger telling it the line number
4100 to which the following sequence of instructions corresponds.
4101 Silicon graphics puts a label after each .loc. */
4103 #ifndef LABEL_AFTER_LOC
4104 #define LABEL_AFTER_LOC(STREAM)
4107 #undef ASM_OUTPUT_SOURCE_LINE
4108 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4109 mips_output_lineno (STREAM, LINE)
4111 /* The MIPS implementation uses some labels for its own purpose. The
4112 following lists what labels are created, and are all formed by the
4113 pattern $L[a-z].*. The machine independent portion of GCC creates
4114 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4116 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4117 $Lb[0-9]+ Begin blocks for MIPS debug support
4118 $Lc[0-9]+ Label for use in s<xx> operation.
4119 $Le[0-9]+ End blocks for MIPS debug support
4120 $Lp\..+ Half-pic labels. */
4122 /* This is how to output the definition of a user-level label named NAME,
4123 such as the label on a static function or variable NAME.
4125 If we are optimizing the gp, remember that this label has been put
4126 out, so we know not to emit an .extern for it in mips_asm_file_end.
4127 We use one of the common bits in the IDENTIFIER tree node for this,
4128 since those bits seem to be unused, and we don't have any method
4129 of getting the decl nodes from the name. */
4131 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4133 assemble_name (STREAM, NAME); \
4134 fputs (":\n", STREAM); \
4138 /* A C statement (sans semicolon) to output to the stdio stream
4139 STREAM any text necessary for declaring the name NAME of an
4140 initialized variable which is being defined. This macro must
4141 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4142 The argument DECL is the `VAR_DECL' tree node representing the
4145 If this macro is not defined, then the variable name is defined
4146 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4148 #undef ASM_DECLARE_OBJECT_NAME
4149 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4152 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4153 HALF_PIC_DECLARE (NAME); \
4158 /* This is how to output a command to make the user-level label named NAME
4159 defined for reference from other files. */
4161 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4163 fputs ("\t.globl\t", STREAM); \
4164 assemble_name (STREAM, NAME); \
4165 fputs ("\n", STREAM); \
4168 /* This says how to define a global common symbol. */
4170 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4172 /* If the target wants uninitialized const declarations in \
4173 .rdata then don't put them in .comm */ \
4174 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4175 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4176 && (DECL_INITIAL (DECL) == 0 \
4177 || DECL_INITIAL (DECL) == error_mark_node)) \
4179 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4180 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4182 READONLY_DATA_SECTION (); \
4183 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4184 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4188 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4193 /* This says how to define a local common symbol (ie, not visible to
4196 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4197 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4200 /* This says how to output an external. It would be possible not to
4201 output anything and let undefined symbol become external. However
4202 the assembler uses length information on externals to allocate in
4203 data/sdata bss/sbss, thereby saving exec time. */
4205 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4206 mips_output_external(STREAM,DECL,NAME)
4208 /* This says what to print at the end of the assembly file */
4210 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4213 /* This is how to declare a function name. The actual work of
4214 emitting the label is moved to function_prologue, so that we can
4215 get the line number correctly emitted before the .ent directive,
4216 and after any .file directives.
4218 Also, switch files if we are optimizing the global pointer. */
4220 #undef ASM_DECLARE_FUNCTION_NAME
4221 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4223 extern FILE *asm_out_text_file; \
4224 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4226 STREAM = asm_out_text_file; \
4227 /* ??? text_section gets called too soon. If the previous \
4228 function is in a special section and we're not, we have \
4229 to switch back to the text section. We can't call \
4230 text_section again as gcc thinks we're already there. */ \
4231 /* ??? See varasm.c. There are other things that get output \
4232 too early, like alignment (before we've switched STREAM). */ \
4233 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4234 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4237 HALF_PIC_DECLARE (NAME); \
4240 /* This is how to output an internal numbered label where
4241 PREFIX is the class of label and NUM is the number within the class. */
4243 #undef ASM_OUTPUT_INTERNAL_LABEL
4244 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4245 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4247 /* This is how to store into the string LABEL
4248 the symbol_ref name of an internal numbered label where
4249 PREFIX is the class of label and NUM is the number within the class.
4250 This is suitable for output with `assemble_name'. */
4252 #undef ASM_GENERATE_INTERNAL_LABEL
4253 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4254 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4256 /* This is how to output an assembler line defining a `double' constant. */
4258 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4259 mips_output_double (STREAM, VALUE)
4262 /* This is how to output an assembler line defining a `float' constant. */
4264 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4265 mips_output_float (STREAM, VALUE)
4268 /* This is how to output an assembler line defining an `int' constant. */
4270 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4272 fprintf (STREAM, "\t.word\t"); \
4273 output_addr_const (STREAM, (VALUE)); \
4274 fprintf (STREAM, "\n"); \
4277 /* Likewise for 64 bit, `char' and `short' constants.
4279 FIXME: operand_subword can't handle some complex constant expressions
4280 that output_addr_const can (for example it does not call
4281 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4282 rely on that to avoid operand_subword for most of the cases where this
4283 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4284 or the same case with the type of 'i' changed to long long.
4288 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4290 if (TARGET_64BIT || TARGET_GAS) \
4292 fprintf (STREAM, "\t.dword\t"); \
4293 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4294 /* We can't use 'X' for negative numbers, because then we won't \
4295 get the right value for the upper 32 bits. */ \
4296 output_addr_const (STREAM, VALUE); \
4298 /* We must use 'X', because otherwise LONG_MIN will print as \
4299 a number that the Irix 6 assembler won't accept. */ \
4300 print_operand (STREAM, VALUE, 'X'); \
4301 fprintf (STREAM, "\n"); \
4305 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4306 UNITS_PER_WORD, 1); \
4307 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4308 UNITS_PER_WORD, 1); \
4312 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4314 fprintf (STREAM, "\t.half\t"); \
4315 output_addr_const (STREAM, (VALUE)); \
4316 fprintf (STREAM, "\n"); \
4319 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4321 fprintf (STREAM, "\t.byte\t"); \
4322 output_addr_const (STREAM, (VALUE)); \
4323 fprintf (STREAM, "\n"); \
4326 /* This is how to output an assembler line for a numeric constant byte. */
4328 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4329 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4331 /* This is how to output an element of a case-vector that is absolute. */
4333 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4334 fprintf (STREAM, "\t%s\t%sL%d\n", \
4335 Pmode == DImode ? ".dword" : ".word", \
4336 LOCAL_LABEL_PREFIX, \
4339 /* This is how to output an element of a case-vector that is relative.
4340 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4341 TARGET_EMBEDDED_PIC). */
4343 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4345 if (TARGET_MIPS16) \
4346 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4347 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4348 else if (TARGET_EMBEDDED_PIC) \
4349 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4350 Pmode == DImode ? ".dword" : ".word", \
4351 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4352 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4353 fprintf (STREAM, "\t%s\t%sL%d\n", \
4354 Pmode == DImode ? ".gpdword" : ".gpword", \
4355 LOCAL_LABEL_PREFIX, VALUE); \
4357 fprintf (STREAM, "\t%s\t%sL%d\n", \
4358 Pmode == DImode ? ".dword" : ".word", \
4359 LOCAL_LABEL_PREFIX, VALUE); \
4362 /* When generating embedded PIC or mips16 code we want to put the jump
4363 table in the .text section. In all other cases, we want to put the
4364 jump table in the .rdata section. Unfortunately, we can't use
4365 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4366 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4367 section if appropriate. */
4368 #undef ASM_OUTPUT_CASE_LABEL
4369 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4371 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4372 function_section (current_function_decl); \
4373 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4376 /* This is how to output an assembler line
4377 that says to advance the location counter
4378 to a multiple of 2**LOG bytes. */
4380 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4381 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4383 /* This is how to output an assembler line to advance the location
4384 counter by SIZE bytes. */
4386 #undef ASM_OUTPUT_SKIP
4387 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4388 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4390 /* This is how to output a string. */
4391 #undef ASM_OUTPUT_ASCII
4392 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4393 mips_output_ascii (STREAM, STRING, LEN)
4395 /* Handle certain cpp directives used in header files on sysV. */
4396 #define SCCS_DIRECTIVE
4398 /* Output #ident as a in the read-only data section. */
4399 #undef ASM_OUTPUT_IDENT
4400 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4402 const char *p = STRING; \
4403 int size = strlen (p) + 1; \
4405 assemble_string (p, size); \
4408 /* Default to -G 8 */
4409 #ifndef MIPS_DEFAULT_GVALUE
4410 #define MIPS_DEFAULT_GVALUE 8
4413 /* Define the strings to put out for each section in the object file. */
4414 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4415 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4416 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4417 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4418 #undef READONLY_DATA_SECTION
4419 #define READONLY_DATA_SECTION rdata_section
4420 #define SMALL_DATA_SECTION sdata_section
4422 /* What other sections we support other than the normal .data/.text. */
4424 #undef EXTRA_SECTIONS
4425 #define EXTRA_SECTIONS in_sdata, in_rdata
4427 /* Define the additional functions to select our additional sections. */
4429 /* on the MIPS it is not a good idea to put constants in the text
4430 section, since this defeats the sdata/data mechanism. This is
4431 especially true when -O is used. In this case an effort is made to
4432 address with faster (gp) register relative addressing, which can
4433 only get at sdata and sbss items (there is no stext !!) However,
4434 if the constant is too large for sdata, and it's readonly, it
4435 will go into the .rdata section. */
4437 #undef EXTRA_SECTION_FUNCTIONS
4438 #define EXTRA_SECTION_FUNCTIONS \
4442 if (in_section != in_sdata) \
4444 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4445 in_section = in_sdata; \
4452 if (in_section != in_rdata) \
4454 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4455 in_section = in_rdata; \
4459 /* Given a decl node or constant node, choose the section to output it in
4460 and select that section. */
4462 #undef SELECT_RTX_SECTION
4463 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4465 #undef SELECT_SECTION
4466 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4469 /* Store in OUTPUT a string (made with alloca) containing
4470 an assembler-name for a local static variable named NAME.
4471 LABELNO is an integer which is different for each call. */
4473 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4474 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4475 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4477 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4480 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4481 TARGET_64BIT ? "dsubu" : "subu", \
4482 reg_names[STACK_POINTER_REGNUM], \
4483 reg_names[STACK_POINTER_REGNUM], \
4484 TARGET_64BIT ? "sd" : "sw", \
4486 reg_names[STACK_POINTER_REGNUM]); \
4490 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4493 if (! set_noreorder) \
4494 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4496 dslots_load_total++; \
4497 dslots_load_filled++; \
4498 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4499 TARGET_64BIT ? "ld" : "lw", \
4501 reg_names[STACK_POINTER_REGNUM], \
4502 TARGET_64BIT ? "daddu" : "addu", \
4503 reg_names[STACK_POINTER_REGNUM], \
4504 reg_names[STACK_POINTER_REGNUM]); \
4506 if (! set_noreorder) \
4507 fprintf (STREAM, "\t.set\treorder\n"); \
4511 /* Define the parentheses used to group arithmetic operations
4512 in assembler code. */
4514 #define ASM_OPEN_PAREN "("
4515 #define ASM_CLOSE_PAREN ")"
4517 /* How to start an assembler comment.
4518 The leading space is important (the mips native assembler requires it). */
4519 #ifndef ASM_COMMENT_START
4520 #define ASM_COMMENT_START " #"
4524 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4525 and mips-tdump.c to print them out.
4527 These must match the corresponding definitions in gdb/mipsread.c.
4528 Unfortunately, gcc and gdb do not currently share any directories. */
4530 #define CODE_MASK 0x8F300
4531 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4532 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4533 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4536 /* Default definitions for size_t and ptrdiff_t. */
4539 #define NO_BUILTIN_SIZE_TYPE
4540 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4543 #ifndef PTRDIFF_TYPE
4544 #define NO_BUILTIN_PTRDIFF_TYPE
4545 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4548 /* See mips_expand_prologue's use of loadgp for when this should be
4551 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4552 && mips_abi != ABI_32 \
4553 && mips_abi != ABI_O64)
4555 /* In mips16 mode, we need to look through the function to check for
4556 PC relative loads that are out of range. */
4557 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4559 /* We need to use a special set of functions to handle hard floating
4560 point code in mips16 mode. */
4562 #ifndef INIT_SUBTARGET_OPTABS
4563 #define INIT_SUBTARGET_OPTABS
4566 #define INIT_TARGET_OPTABS \
4569 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4570 INIT_SUBTARGET_OPTABS; \
4573 add_optab->handlers[(int) SFmode].libfunc = \
4574 init_one_libfunc ("__mips16_addsf3"); \
4575 sub_optab->handlers[(int) SFmode].libfunc = \
4576 init_one_libfunc ("__mips16_subsf3"); \
4577 smul_optab->handlers[(int) SFmode].libfunc = \
4578 init_one_libfunc ("__mips16_mulsf3"); \
4579 flodiv_optab->handlers[(int) SFmode].libfunc = \
4580 init_one_libfunc ("__mips16_divsf3"); \
4582 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4583 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4584 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4585 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4586 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4587 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4589 floatsisf_libfunc = \
4590 init_one_libfunc ("__mips16_floatsisf"); \
4592 init_one_libfunc ("__mips16_fixsfsi"); \
4594 if (TARGET_DOUBLE_FLOAT) \
4596 add_optab->handlers[(int) DFmode].libfunc = \
4597 init_one_libfunc ("__mips16_adddf3"); \
4598 sub_optab->handlers[(int) DFmode].libfunc = \
4599 init_one_libfunc ("__mips16_subdf3"); \
4600 smul_optab->handlers[(int) DFmode].libfunc = \
4601 init_one_libfunc ("__mips16_muldf3"); \
4602 flodiv_optab->handlers[(int) DFmode].libfunc = \
4603 init_one_libfunc ("__mips16_divdf3"); \
4605 extendsfdf2_libfunc = \
4606 init_one_libfunc ("__mips16_extendsfdf2"); \
4607 truncdfsf2_libfunc = \
4608 init_one_libfunc ("__mips16_truncdfsf2"); \
4611 init_one_libfunc ("__mips16_eqdf2"); \
4613 init_one_libfunc ("__mips16_nedf2"); \
4615 init_one_libfunc ("__mips16_gtdf2"); \
4617 init_one_libfunc ("__mips16_gedf2"); \
4619 init_one_libfunc ("__mips16_ltdf2"); \
4621 init_one_libfunc ("__mips16_ledf2"); \
4623 floatsidf_libfunc = \
4624 init_one_libfunc ("__mips16_floatsidf"); \
4626 init_one_libfunc ("__mips16_fixdfsi"); \
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