1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char call_used_regs[];
30 extern int may_call_alloca;
31 extern char **save_argv;
32 extern int target_flags;
34 /* MIPS external variables defined in mips.c. */
38 CMP_SI, /* compare four byte integers */
39 CMP_DI, /* compare eight byte integers */
40 CMP_SF, /* compare single precision floats */
41 CMP_DF, /* compare double precision floats */
42 CMP_MAX /* max comparison type */
45 /* Which processor to schedule for. Since there is no difference between
46 a R2000 and R3000 in terms of the scheduler, we collapse them into
47 just an R3000. The elements of the enumeration must match exactly
48 the cpu attribute in the mips.md machine description. */
74 /* Recast the cpu class to be the cpu attribute. */
75 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
77 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
78 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
79 to work on a 64 bit machine. */
87 /* Whether to emit abicalls code sequences or not. */
89 enum mips_abicalls_type {
94 /* Recast the abicalls class to be the abicalls attribute. */
95 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
97 /* Which type of block move to do (whether or not the last store is
98 split out so it can fill a branch delay slot). */
100 enum block_move_type {
101 BLOCK_MOVE_NORMAL, /* generate complete block move */
102 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
103 BLOCK_MOVE_LAST /* generate just the last store */
106 /* Information about one recognized processor. Defined here for the
107 benefit of TARGET_CPU_CPP_BUILTINS. */
108 struct mips_cpu_info {
109 /* The 'canonical' name of the processor as far as GCC is concerned.
110 It's typically a manufacturer's prefix followed by a numerical
111 designation. It should be lower case. */
114 /* The internal processor number that most closely matches this
115 entry. Several processors can have the same value, if there's no
116 difference between them from GCC's point of view. */
117 enum processor_type cpu;
119 /* The ISA level that the processor implements. */
123 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
124 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
125 extern const char *current_function_file; /* filename current function is in */
126 extern int num_source_filenames; /* current .file # */
127 extern int inside_function; /* != 0 if inside of a function */
128 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
129 extern int file_in_function_warning; /* warning given about .file in func */
130 extern int sdb_label_count; /* block start/end next label # */
131 extern int sdb_begin_function_line; /* Starting Line of current function */
132 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
133 extern int sym_lineno; /* sgi next label # for each stmt */
134 extern int set_noreorder; /* # of nested .set noreorder's */
135 extern int set_nomacro; /* # of nested .set nomacro's */
136 extern int set_noat; /* # of nested .set noat's */
137 extern int set_volatile; /* # of nested .set volatile's */
138 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
139 extern int mips_dbx_regno[]; /* Map register # to debug register # */
140 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
141 extern enum cmp_type branch_type; /* what type of branch to use */
142 extern enum processor_type mips_arch; /* which cpu to codegen for */
143 extern enum processor_type mips_tune; /* which cpu to schedule for */
144 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
145 extern int mips_isa; /* architectural level */
146 extern int mips16; /* whether generating mips16 code */
147 extern int mips16_hard_float; /* mips16 without -msoft-float */
148 extern int mips_entry; /* generate entry/exit for mips16 */
149 extern const char *mips_arch_string; /* for -march=<xxx> */
150 extern const char *mips_tune_string; /* for -mtune=<xxx> */
151 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
152 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
153 extern const char *mips_entry_string; /* for -mentry */
154 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
155 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
156 extern int mips_string_length; /* length of strings for mips16 */
157 extern const struct mips_cpu_info mips_cpu_info_table[];
158 extern const struct mips_cpu_info *mips_arch_info;
159 extern const struct mips_cpu_info *mips_tune_info;
161 /* Functions to change what output section we are using. */
162 extern void sdata_section PARAMS ((void));
163 extern void sbss_section PARAMS ((void));
165 /* Macros to silence warnings about numbers being signed in traditional
166 C and unsigned in ISO C when compiled on 32-bit hosts. */
168 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
169 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
170 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
173 /* Run-time compilation parameters selecting different hardware subsets. */
175 /* Macros used in the machine description to test the flags. */
177 /* Bits for real switches */
178 #define MASK_INT64 0x00000001 /* ints are 64 bits */
179 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
180 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
181 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
182 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
183 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
184 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
185 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
186 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
187 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
188 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
189 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
190 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
191 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
192 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
193 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
194 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
195 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
196 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
197 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
198 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
199 #define MASK_NO_CHECK_ZERO_DIV \
200 0x00200000 /* divide by zero checking */
201 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
203 #define MASK_UNINIT_CONST_IN_RODATA \
204 0x00800000 /* Store uninitialized
206 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
207 multiply-add operations. */
209 /* Debug switches, not documented */
210 #define MASK_DEBUG 0 /* unused */
211 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
212 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
213 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
214 #define MASK_DEBUG_D 0 /* don't do define_split's */
215 #define MASK_DEBUG_E 0 /* function_arg debug */
216 #define MASK_DEBUG_F 0 /* ??? */
217 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
218 #define MASK_DEBUG_I 0 /* unused */
220 /* Dummy switches used only in specs */
221 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
223 /* r4000 64 bit sizes */
224 #define TARGET_INT64 (target_flags & MASK_INT64)
225 #define TARGET_LONG64 (target_flags & MASK_LONG64)
226 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
227 #define TARGET_64BIT (target_flags & MASK_64BIT)
229 /* Mips vs. GNU linker */
230 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
232 /* Mips vs. GNU assembler */
233 #define TARGET_GAS (target_flags & MASK_GAS)
234 #define TARGET_MIPS_AS (!TARGET_GAS)
237 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
238 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
239 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
240 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
241 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
242 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
243 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
244 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
245 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
247 /* Reg. Naming in .s ($21 vs. $a0) */
248 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
250 /* Optimize for Sdata/Sbss */
251 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
253 /* call memcpy instead of inline code */
254 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
256 /* .abicalls, etc from Pyramid V.4 */
257 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
259 /* software floating point */
260 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
261 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
263 /* always call through a register */
264 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
266 /* generate embedded PIC code;
268 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
270 /* for embedded systems, optimize for
271 reduced RAM space instead of for
273 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
275 /* always store uninitialized const
276 variables in rodata, requires
277 TARGET_EMBEDDED_DATA. */
278 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
280 /* generate big endian code. */
281 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
283 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
284 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
286 #define TARGET_MAD (target_flags & MASK_MAD)
288 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
290 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
292 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
294 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
297 /* True if we should use NewABI-style relocation operators for
298 symbolic addresses. This is never true for mips16 code,
299 which has its own conventions. */
301 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
304 /* True if the call patterns should be split into a jalr followed by
305 an instruction to restore $gp. This is only ever true for SVR4 PIC,
306 in which $gp is call-clobbered. It is only safe to split the load
307 from the call when every use of $gp is explicit. */
309 #define TARGET_SPLIT_CALLS \
310 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
312 /* True if we can optimize sibling calls. For simplicity, we only
313 handle cases in which call_insn_operand will reject invalid
314 sibcall addresses. There are two cases in which this isn't true:
316 - TARGET_MIPS16. call_insn_operand accepts constant addresses
317 but there is no direct jump instruction. It isn't worth
318 using sibling calls in this case anyway; they would usually
319 be longer than normal calls.
321 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
322 accepts global constants, but "jr $25" is the only allowed
325 #define TARGET_SIBCALLS \
326 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
328 /* True if .gpword or .gpdword should be used for switch tables.
329 Not all SGI assemblers support this. */
331 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
333 /* Generate mips16 code */
334 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
336 /* Generic ISA defines. */
337 #define ISA_MIPS1 (mips_isa == 1)
338 #define ISA_MIPS2 (mips_isa == 2)
339 #define ISA_MIPS3 (mips_isa == 3)
340 #define ISA_MIPS4 (mips_isa == 4)
341 #define ISA_MIPS32 (mips_isa == 32)
342 #define ISA_MIPS32R2 (mips_isa == 33)
343 #define ISA_MIPS64 (mips_isa == 64)
345 /* Architecture target defines. */
346 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
347 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
348 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
349 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
350 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
351 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
352 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
353 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
354 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
355 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
356 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
358 /* Scheduling target defines. */
359 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
360 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
361 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
362 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
363 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
364 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
365 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
366 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
367 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
369 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
371 /* Define preprocessor macros for the -march and -mtune options.
372 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
373 processor. If INFO's canonical name is "foo", define PREFIX to
374 be "foo", and define an additional macro PREFIX_FOO. */
375 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
380 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
381 for (p = macro; *p != 0; p++) \
384 builtin_define (macro); \
385 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
390 /* Target CPU builtins. */
391 #define TARGET_CPU_CPP_BUILTINS() \
394 builtin_assert ("cpu=mips"); \
395 builtin_define ("__mips__"); \
396 builtin_define ("_mips"); \
398 /* We do this here because __mips is defined below \
399 and so we can't use builtin_define_std. */ \
401 builtin_define ("mips"); \
403 /* Treat _R3000 and _R4000 like register-size defines, \
404 which is how they've historically been used. */ \
407 builtin_define ("__mips64"); \
408 builtin_define_std ("R4000"); \
409 builtin_define ("_R4000"); \
413 builtin_define_std ("R3000"); \
414 builtin_define ("_R3000"); \
416 if (TARGET_FLOAT64) \
417 builtin_define ("__mips_fpr=64"); \
419 builtin_define ("__mips_fpr=32"); \
422 builtin_define ("__mips16"); \
424 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
425 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
429 builtin_define ("__mips=1"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
432 else if (ISA_MIPS2) \
434 builtin_define ("__mips=2"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
437 else if (ISA_MIPS3) \
439 builtin_define ("__mips=3"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
442 else if (ISA_MIPS4) \
444 builtin_define ("__mips=4"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
447 else if (ISA_MIPS32) \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=1"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
453 else if (ISA_MIPS32R2) \
455 builtin_define ("__mips=32"); \
456 builtin_define ("__mips_isa_rev=2"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
459 else if (ISA_MIPS64) \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=1"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
466 if (TARGET_HARD_FLOAT) \
467 builtin_define ("__mips_hard_float"); \
468 else if (TARGET_SOFT_FLOAT) \
469 builtin_define ("__mips_soft_float"); \
471 if (TARGET_SINGLE_FLOAT) \
472 builtin_define ("__mips_single_float"); \
474 if (TARGET_BIG_ENDIAN) \
476 builtin_define_std ("MIPSEB"); \
477 builtin_define ("_MIPSEB"); \
481 builtin_define_std ("MIPSEL"); \
482 builtin_define ("_MIPSEL"); \
485 /* Macros dependent on the C dialect. */ \
486 if (preprocessing_asm_p ()) \
488 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
489 builtin_define ("_LANGUAGE_ASSEMBLY"); \
491 else if (c_language == clk_c) \
493 builtin_define_std ("LANGUAGE_C"); \
494 builtin_define ("_LANGUAGE_C"); \
496 else if (c_language == clk_cplusplus) \
498 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
499 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
500 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
504 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
505 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
506 /* Bizzare, but needed at least for Irix. */ \
507 builtin_define_std ("LANGUAGE_C"); \
508 builtin_define ("_LANGUAGE_C"); \
511 if (mips_abi == ABI_EABI) \
512 builtin_define ("__mips_eabi"); \
518 /* Macro to define tables used to set the flags.
519 This is a list in braces of pairs in braces,
520 each pair being { "NAME", VALUE }
521 where VALUE is the bits to set or minus the bits to clear.
522 An empty string NAME is used to identify the default VALUE. */
524 #define TARGET_SWITCHES \
526 SUBTARGET_TARGET_SWITCHES \
527 {"int64", MASK_INT64 | MASK_LONG64, \
528 N_("Use 64-bit int type")}, \
529 {"long64", MASK_LONG64, \
530 N_("Use 64-bit long type")}, \
531 {"long32", -(MASK_LONG64 | MASK_INT64), \
532 N_("Use 32-bit long type")}, \
533 {"split-addresses", MASK_SPLIT_ADDR, \
534 N_("Optimize lui/addiu address loads")}, \
535 {"no-split-addresses", -MASK_SPLIT_ADDR, \
536 N_("Don't optimize lui/addiu address loads")}, \
537 {"mips-as", -MASK_GAS, \
538 N_("Use MIPS as")}, \
541 {"rnames", MASK_NAME_REGS, \
542 N_("Use symbolic register names")}, \
543 {"no-rnames", -MASK_NAME_REGS, \
544 N_("Don't use symbolic register names")}, \
545 {"gpOPT", MASK_GPOPT, \
546 N_("Use GP relative sdata/sbss sections")}, \
547 {"gpopt", MASK_GPOPT, \
548 N_("Use GP relative sdata/sbss sections")}, \
549 {"no-gpOPT", -MASK_GPOPT, \
550 N_("Don't use GP relative sdata/sbss sections")}, \
551 {"no-gpopt", -MASK_GPOPT, \
552 N_("Don't use GP relative sdata/sbss sections")}, \
554 N_("Output compiler statistics (now ignored)")}, \
556 N_("Don't output compiler statistics")}, \
557 {"memcpy", MASK_MEMCPY, \
558 N_("Don't optimize block moves")}, \
559 {"no-memcpy", -MASK_MEMCPY, \
560 N_("Optimize block moves")}, \
561 {"mips-tfile", MASK_MIPS_TFILE, \
562 N_("Use mips-tfile asm postpass")}, \
563 {"no-mips-tfile", -MASK_MIPS_TFILE, \
564 N_("Don't use mips-tfile asm postpass")}, \
565 {"soft-float", MASK_SOFT_FLOAT, \
566 N_("Use software floating point")}, \
567 {"hard-float", -MASK_SOFT_FLOAT, \
568 N_("Use hardware floating point")}, \
569 {"fp64", MASK_FLOAT64, \
570 N_("Use 64-bit FP registers")}, \
571 {"fp32", -MASK_FLOAT64, \
572 N_("Use 32-bit FP registers")}, \
573 {"gp64", MASK_64BIT, \
574 N_("Use 64-bit general registers")}, \
575 {"gp32", -MASK_64BIT, \
576 N_("Use 32-bit general registers")}, \
577 {"abicalls", MASK_ABICALLS, \
578 N_("Use Irix PIC")}, \
579 {"no-abicalls", -MASK_ABICALLS, \
580 N_("Don't use Irix PIC")}, \
581 {"long-calls", MASK_LONG_CALLS, \
582 N_("Use indirect calls")}, \
583 {"no-long-calls", -MASK_LONG_CALLS, \
584 N_("Don't use indirect calls")}, \
585 {"embedded-pic", MASK_EMBEDDED_PIC, \
586 N_("Use embedded PIC")}, \
587 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
588 N_("Don't use embedded PIC")}, \
589 {"embedded-data", MASK_EMBEDDED_DATA, \
590 N_("Use ROM instead of RAM")}, \
591 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
592 N_("Don't use ROM instead of RAM")}, \
593 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
594 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
595 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
596 N_("Don't put uninitialized constants in ROM")}, \
597 {"eb", MASK_BIG_ENDIAN, \
598 N_("Use big-endian byte order")}, \
599 {"el", -MASK_BIG_ENDIAN, \
600 N_("Use little-endian byte order")}, \
601 {"single-float", MASK_SINGLE_FLOAT, \
602 N_("Use single (32-bit) FP only")}, \
603 {"double-float", -MASK_SINGLE_FLOAT, \
604 N_("Don't use single (32-bit) FP only")}, \
606 N_("Use multiply accumulate")}, \
607 {"no-mad", -MASK_MAD, \
608 N_("Don't use multiply accumulate")}, \
609 {"no-fused-madd", MASK_NO_FUSED_MADD, \
610 N_("Don't generate fused multiply/add instructions")}, \
611 {"fused-madd", -MASK_NO_FUSED_MADD, \
612 N_("Generate fused multiply/add instructions")}, \
613 {"fix4300", MASK_4300_MUL_FIX, \
614 N_("Work around early 4300 hardware bug")}, \
615 {"no-fix4300", -MASK_4300_MUL_FIX, \
616 N_("Don't work around early 4300 hardware bug")}, \
617 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
618 N_("Trap on integer divide by zero")}, \
619 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
620 N_("Don't trap on integer divide by zero")}, \
621 { "branch-likely", MASK_BRANCHLIKELY, \
622 N_("Use Branch Likely instructions, overriding default for arch")}, \
623 { "no-branch-likely", -MASK_BRANCHLIKELY, \
624 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
625 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
626 N_("Use NewABI-style %reloc() assembly operators")}, \
627 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
628 N_("Use assembler macros instead of relocation operators")}, \
629 {"debug", MASK_DEBUG, \
631 {"debuga", MASK_DEBUG_A, \
633 {"debugb", MASK_DEBUG_B, \
635 {"debugc", MASK_DEBUG_C, \
637 {"debugd", MASK_DEBUG_D, \
639 {"debuge", MASK_DEBUG_E, \
641 {"debugf", MASK_DEBUG_F, \
643 {"debugg", MASK_DEBUG_G, \
645 {"debugi", MASK_DEBUG_I, \
647 {"", (TARGET_DEFAULT \
648 | TARGET_CPU_DEFAULT \
649 | TARGET_ENDIAN_DEFAULT), \
653 /* Default target_flags if no switches are specified */
655 #ifndef TARGET_DEFAULT
656 #define TARGET_DEFAULT 0
659 #ifndef TARGET_CPU_DEFAULT
660 #define TARGET_CPU_DEFAULT 0
663 #ifndef TARGET_ENDIAN_DEFAULT
664 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
667 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
668 #ifndef MIPS_ISA_DEFAULT
669 #ifndef MIPS_CPU_STRING_DEFAULT
670 #define MIPS_CPU_STRING_DEFAULT "from-abi"
676 /* Make this compile time constant for libgcc2 */
678 #define TARGET_64BIT 1
680 #define TARGET_64BIT 0
682 #endif /* IN_LIBGCC2 */
684 #ifndef MULTILIB_ENDIAN_DEFAULT
685 #if TARGET_ENDIAN_DEFAULT == 0
686 #define MULTILIB_ENDIAN_DEFAULT "EL"
688 #define MULTILIB_ENDIAN_DEFAULT "EB"
692 #ifndef MULTILIB_ISA_DEFAULT
693 # if MIPS_ISA_DEFAULT == 1
694 # define MULTILIB_ISA_DEFAULT "mips1"
696 # if MIPS_ISA_DEFAULT == 2
697 # define MULTILIB_ISA_DEFAULT "mips2"
699 # if MIPS_ISA_DEFAULT == 3
700 # define MULTILIB_ISA_DEFAULT "mips3"
702 # if MIPS_ISA_DEFAULT == 4
703 # define MULTILIB_ISA_DEFAULT "mips4"
705 # if MIPS_ISA_DEFAULT == 32
706 # define MULTILIB_ISA_DEFAULT "mips32"
708 # if MIPS_ISA_DEFAULT == 33
709 # define MULTILIB_ISA_DEFAULT "mips32r2"
711 # if MIPS_ISA_DEFAULT == 64
712 # define MULTILIB_ISA_DEFAULT "mips64"
714 # define MULTILIB_ISA_DEFAULT "mips1"
724 #ifndef MULTILIB_DEFAULTS
725 #define MULTILIB_DEFAULTS \
726 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
729 /* We must pass -EL to the linker by default for little endian embedded
730 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
731 linker will default to using big-endian output files. The OUTPUT_FORMAT
732 line must be in the linker script, otherwise -EB/-EL will not work. */
735 #if TARGET_ENDIAN_DEFAULT == 0
736 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
738 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
742 #define TARGET_OPTIONS \
744 SUBTARGET_TARGET_OPTIONS \
745 { "tune=", &mips_tune_string, \
746 N_("Specify CPU for scheduling purposes"), 0}, \
747 { "arch=", &mips_arch_string, \
748 N_("Specify CPU for code generation purposes"), 0}, \
749 { "abi=", &mips_abi_string, \
750 N_("Specify an ABI"), 0}, \
751 { "ips", &mips_isa_string, \
752 N_("Specify a Standard MIPS ISA"), 0}, \
753 { "entry", &mips_entry_string, \
754 N_("Use mips16 entry/exit psuedo ops"), 0}, \
755 { "no-mips16", &mips_no_mips16_string, \
756 N_("Don't use MIPS16 instructions"), 0}, \
757 { "no-flush-func", &mips_cache_flush_func, \
758 N_("Don't call any cache flush functions"), 0}, \
759 { "flush-func=", &mips_cache_flush_func, \
760 N_("Specify cache flush function"), 0}, \
763 /* This is meant to be redefined in the host dependent files. */
764 #define SUBTARGET_TARGET_OPTIONS
766 /* Support for a compile-time default CPU, et cetera. The rules are:
767 --with-arch is ignored if -march is specified or a -mips is specified
768 (other than -mips16).
769 --with-tune is ignored if -mtune is specified.
770 --with-abi is ignored if -mabi is specified.
771 --with-float is ignored if -mhard-float or -msoft-float are
773 #define OPTION_DEFAULT_SPECS \
774 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
775 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
776 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
777 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
780 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
784 /* Generate three-operand multiply instructions for SImode. */
785 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
793 /* Generate three-operand multiply instructions for DImode. */
794 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
797 /* Macros to decide whether certain features are available or not,
798 depending on the instruction set architecture level. */
800 #define HAVE_SQRT_P() (!ISA_MIPS1)
802 /* True if the ABI can only work with 64-bit integer registers. We
803 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
804 otherwise floating-point registers must also be 64-bit. */
805 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
806 || mips_abi == ABI_O64 \
807 || mips_abi == ABI_N32)
809 /* Likewise for 32-bit regs. */
810 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
812 /* True if symbols are 64 bits wide. At present, n64 is the only
813 ABI for which this is true. */
814 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
816 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
817 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
821 /* ISA has branch likely instructions (eg. mips2). */
822 /* Disable branchlikely for tx39 until compare rewrite. They haven't
823 been generated up to this point. */
824 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
827 /* ISA has the conditional move instructions introduced in mips4. */
828 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
832 && !TARGET_MIPS5500 \
835 /* ISA has just the integer condition move instructions (movn,movz) */
836 #define ISA_HAS_INT_CONDMOVE 0
838 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
839 branch on CC, and move (both FP and non-FP) on CC. */
840 #define ISA_HAS_8CC (ISA_MIPS4 \
845 /* This is a catch all for the other new mips4 instructions: indexed load and
846 indexed prefetch instructions, the FP madd and msub instructions,
847 and the FP recip and recip sqrt instructions */
848 #define ISA_HAS_FP4 ((ISA_MIPS4 \
852 /* ISA has conditional trap instructions. */
853 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
856 /* ISA has integer multiply-accumulate instructions, madd and msub. */
857 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
862 /* ISA has floating-point nmadd and nmsub instructions. */
863 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
865 && (!TARGET_MIPS5400 || TARGET_MAD) \
868 /* ISA has count leading zeroes/ones instruction (not implemented). */
869 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
874 /* ISA has double-word count leading zeroes/ones instruction (not
876 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
879 /* ISA has three operand multiply instructions that put
880 the high part in an accumulator: mulhi or mulhiu. */
881 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
886 /* ISA has three operand multiply instructions that
887 negates the result and puts the result in an accumulator. */
888 #define ISA_HAS_MULS (TARGET_MIPS5400 \
893 /* ISA has three operand multiply instructions that subtracts the
894 result from a 4th operand and puts the result in an accumulator. */
895 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
899 /* ISA has three operand multiply instructions that the result
900 from a 4th operand and puts the result in an accumulator. */
901 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
907 /* ISA has 32-bit rotate right instruction. */
908 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
915 /* ISA has 64-bit rotate right instruction. */
916 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
918 && (TARGET_MIPS5400 \
923 /* ISA has data prefetch instruction. */
924 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
930 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
931 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
932 also requires TARGET_DOUBLE_FLOAT. */
933 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
935 /* ISA includes the MIPS32r2 seb and seh instructions. */
936 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
940 /* True if the result of a load is not available to the next instruction.
941 A nop will then be needed between instructions like "lw $4,..."
942 and "addiu $4,$4,1". */
943 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
944 && !TARGET_MIPS3900 \
947 /* Likewise mtc1 and mfc1. */
948 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
950 /* Likewise floating-point comparisons. */
951 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
953 /* True if mflo and mfhi can be immediately followed by instructions
954 which write to the HI and LO registers. Most targets require a
955 two-instruction gap. */
956 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
958 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
959 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
960 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
961 target_flags, and -mgp64 sets MASK_64BIT.
963 Setting MASK_64BIT in target_flags will cause gcc to assume that
964 registers are 64 bits wide. int, long and void * will be 32 bit;
965 this may be changed with -mint64 or -mlong64.
967 The gen* programs link code that refers to MASK_64BIT. They don't
968 actually use the information in target_flags; they just refer to
971 /* Switch Recognition by gcc.c. Add -G xx support */
973 #undef SWITCH_TAKES_ARG
974 #define SWITCH_TAKES_ARG(CHAR) \
975 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
977 /* Sometimes certain combinations of command options do not make sense
978 on a particular target machine. You can define a macro
979 `OVERRIDE_OPTIONS' to take account of this. This macro, if
980 defined, is executed once just after all the command options have
983 On the MIPS, it is used to handle -G. We also use it to set up all
984 of the tables referenced in the other macros. */
986 #define OVERRIDE_OPTIONS override_options ()
988 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
990 /* Show we can debug even without a frame pointer. */
991 #define CAN_DEBUG_WITHOUT_FP
993 /* Tell collect what flags to pass to nm. */
995 #define NM_FLAGS "-Bn"
999 /* Assembler specs. */
1001 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1004 #define MIPS_AS_ASM_SPEC "\
1005 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1006 %{pipe: %e-pipe is not supported} \
1007 %{K} %(subtarget_mips_as_asm_spec)"
1009 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1010 rather than gas. It may be overridden by subtargets. */
1012 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1013 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1016 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1019 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1021 #define SUBTARGET_TARGET_SWITCHES
1023 extern int mips_abi;
1025 #ifndef MIPS_ABI_DEFAULT
1026 #define MIPS_ABI_DEFAULT ABI_32
1029 /* Use the most portable ABI flag for the ASM specs. */
1031 #if MIPS_ABI_DEFAULT == ABI_32
1032 #define MULTILIB_ABI_DEFAULT "mabi=32"
1033 #define ASM_ABI_DEFAULT_SPEC "-32"
1036 #if MIPS_ABI_DEFAULT == ABI_O64
1037 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1038 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1041 #if MIPS_ABI_DEFAULT == ABI_N32
1042 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1043 #define ASM_ABI_DEFAULT_SPEC "-n32"
1046 #if MIPS_ABI_DEFAULT == ABI_64
1047 #define MULTILIB_ABI_DEFAULT "mabi=64"
1048 #define ASM_ABI_DEFAULT_SPEC "-64"
1051 #if MIPS_ABI_DEFAULT == ABI_EABI
1052 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1053 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1056 /* Only ELF targets can switch the ABI. */
1057 #ifndef OBJECT_FORMAT_ELF
1058 #undef ASM_ABI_DEFAULT_SPEC
1059 #define ASM_ABI_DEFAULT_SPEC ""
1062 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1063 GAS_ASM_SPEC as the default, depending upon the value of
1066 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1069 #define TARGET_ASM_SPEC "\
1070 %{mmips-as: %(mips_as_asm_spec)} \
1071 %{!mmips-as: %(gas_asm_spec)}"
1075 #define TARGET_ASM_SPEC "\
1076 %{!mgas: %(mips_as_asm_spec)} \
1077 %{mgas: %(gas_asm_spec)}"
1079 #endif /* not GAS */
1081 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1082 to the assembler. It may be overridden by subtargets. */
1083 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1084 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1086 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1089 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1090 the assembler. It may be overridden by subtargets. */
1091 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1092 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1093 %{g} %{g0} %{g1} %{g2} %{g3} \
1094 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1095 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1096 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1097 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1101 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1102 and stabs debugging info. */
1103 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1105 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1107 #define MDEBUG_ASM_SPEC ""
1108 #endif /* not GAS */
1110 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1111 overridden by subtargets. */
1113 #ifndef SUBTARGET_ASM_SPEC
1114 #define SUBTARGET_ASM_SPEC ""
1117 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1118 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1119 whether we're using GAS. These options can only be used properly
1120 with GAS, and it is better to get an error from a non-GAS assembler
1121 than to silently generate bad code. */
1125 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1126 %{mips32} %{mips32r2} %{mips64} \
1127 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1128 %(subtarget_asm_optimizing_spec) \
1129 %(subtarget_asm_debugging_spec) \
1131 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1132 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1133 %{mgp32} %{mgp64} %{march=*} \
1134 %(target_asm_spec) \
1135 %(subtarget_asm_spec)"
1137 /* Specify to run a post-processor, mips-tfile after the assembler
1138 has run to stuff the mips debug information into the object file.
1139 This is needed because the $#!%^ MIPS assembler provides no way
1140 of specifying such information in the assembly file. If we are
1141 cross compiling, disable mips-tfile unless the user specifies
1144 #ifndef ASM_FINAL_SPEC
1145 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1147 #define ASM_FINAL_SPEC "\
1148 %{mmips-as: %{!mno-mips-tfile: \
1149 \n mips-tfile %{v*: -v} \
1151 %{!K: %{save-temps: -I %b.o~}} \
1152 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1153 %{.s:%i} %{!.s:%g.s}}}"
1157 #define ASM_FINAL_SPEC "\
1158 %{!mgas: %{!mno-mips-tfile: \
1159 \n mips-tfile %{v*: -v} \
1161 %{!K: %{save-temps: -I %b.o~}} \
1162 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1163 %{.s:%i} %{!.s:%g.s}}}"
1166 #endif /* ASM_FINAL_SPEC */
1168 /* Redefinition of libraries used. Mips doesn't support normal
1169 UNIX style profiling via calling _mcount. It does offer
1170 profiling that samples the PC, so do what we can... */
1173 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1176 /* Extra switches sometimes passed to the linker. */
1177 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1178 will interpret it as a -b option. */
1181 #define LINK_SPEC "\
1183 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1184 %{bestGnum} %{shared} %{non_shared}"
1185 #endif /* LINK_SPEC defined */
1188 /* Specs for the compiler proper */
1190 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1191 overridden by subtargets. */
1192 #ifndef SUBTARGET_CC1_SPEC
1193 #define SUBTARGET_CC1_SPEC ""
1196 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1197 /* Note, we will need to adjust the following if we ever find a MIPS variant
1198 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1199 that show up in this case. */
1203 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1204 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1206 %(subtarget_cc1_spec)"
1209 /* Preprocessor specs. */
1211 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1212 overridden by subtargets. */
1213 #ifndef SUBTARGET_CPP_SPEC
1214 #define SUBTARGET_CPP_SPEC ""
1217 #define CPP_SPEC "%(subtarget_cpp_spec)"
1219 /* This macro defines names of additional specifications to put in the specs
1220 that can be used in various specifications like CC1_SPEC. Its definition
1221 is an initializer with a subgrouping for each command option.
1223 Each subgrouping contains a string constant, that defines the
1224 specification name, and a string constant that used by the GNU CC driver
1227 Do not define this macro if it does not need to do anything. */
1229 #define EXTRA_SPECS \
1230 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1231 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1232 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1233 { "gas_asm_spec", GAS_ASM_SPEC }, \
1234 { "target_asm_spec", TARGET_ASM_SPEC }, \
1235 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1236 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1237 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1238 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1239 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1240 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1241 { "endian_spec", ENDIAN_SPEC }, \
1242 SUBTARGET_EXTRA_SPECS
1244 #ifndef SUBTARGET_EXTRA_SPECS
1245 #define SUBTARGET_EXTRA_SPECS
1248 /* If defined, this macro is an additional prefix to try after
1249 `STANDARD_EXEC_PREFIX'. */
1251 #ifndef MD_EXEC_PREFIX
1252 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1255 #ifndef MD_STARTFILE_PREFIX
1256 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1260 /* Print subsidiary information on the compiler version in use. */
1262 #define MIPS_VERSION "[AL 1.1, MM 40]"
1264 #ifndef MACHINE_TYPE
1265 #define MACHINE_TYPE "BSD Mips"
1268 #ifndef TARGET_VERSION_INTERNAL
1269 #define TARGET_VERSION_INTERNAL(STREAM) \
1270 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1273 #ifndef TARGET_VERSION
1274 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1278 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1279 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1280 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1282 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1283 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1286 /* By default, turn on GDB extensions. */
1287 #define DEFAULT_GDB_EXTENSIONS 1
1289 /* If we are passing smuggling stabs through the MIPS ECOFF object
1290 format, put a comment in front of the .stab<x> operation so
1291 that the MIPS assembler does not choke. The mips-tfile program
1292 will correctly put the stab into the object file. */
1294 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1295 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1296 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1298 /* Local compiler-generated symbols must have a prefix that the assembler
1299 understands. By default, this is $, although some targets (e.g.,
1300 NetBSD-ELF) need to override this. */
1302 #ifndef LOCAL_LABEL_PREFIX
1303 #define LOCAL_LABEL_PREFIX "$"
1306 /* By default on the mips, external symbols do not have an underscore
1307 prepended, but some targets (e.g., NetBSD) require this. */
1309 #ifndef USER_LABEL_PREFIX
1310 #define USER_LABEL_PREFIX ""
1313 /* Forward references to tags are allowed. */
1314 #define SDB_ALLOW_FORWARD_REFERENCES
1316 /* Unknown tags are also allowed. */
1317 #define SDB_ALLOW_UNKNOWN_REFERENCES
1319 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1320 since the length can run past this up to a continuation point. */
1321 #undef DBX_CONTIN_LENGTH
1322 #define DBX_CONTIN_LENGTH 1500
1324 /* How to renumber registers for dbx and gdb. */
1325 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1327 /* The mapping from gcc register number to DWARF 2 CFA column number.
1328 This mapping does not allow for tracking register 0, since SGI's broken
1329 dwarf reader thinks column 0 is used for the frame address, but since
1330 register 0 is fixed this is not a problem. */
1331 #define DWARF_FRAME_REGNUM(REG) \
1332 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1334 /* The DWARF 2 CFA column which tracks the return address. */
1335 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1337 /* Before the prologue, RA lives in r31. */
1338 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1340 /* Describe how we implement __builtin_eh_return. */
1341 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1342 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1344 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1345 The default for this in 64-bit mode is 8, which causes problems with
1346 SFmode register saves. */
1347 #define DWARF_CIE_DATA_ALIGNMENT 4
1349 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1351 #define PUT_SDB_DEF(a) \
1353 fprintf (asm_out_file, "\t%s.def\t", \
1354 (TARGET_GAS) ? "" : "#"); \
1355 ASM_OUTPUT_LABELREF (asm_out_file, a); \
1356 fputc (';', asm_out_file); \
1359 #define PUT_SDB_PLAIN_DEF(a) \
1361 fprintf (asm_out_file, "\t%s.def\t.%s;", \
1362 (TARGET_GAS) ? "" : "#", (a)); \
1365 /* For block start and end, we create labels, so that
1366 later we can figure out where the correct offset is.
1367 The normal .ent/.end serve well enough for functions,
1368 so those are just commented out. */
1370 #define PUT_SDB_BLOCK_START(LINE) \
1372 fprintf (asm_out_file, \
1373 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1374 LOCAL_LABEL_PREFIX, \
1376 (TARGET_GAS) ? "" : "#", \
1377 LOCAL_LABEL_PREFIX, \
1380 sdb_label_count++; \
1383 #define PUT_SDB_BLOCK_END(LINE) \
1385 fprintf (asm_out_file, \
1386 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1387 LOCAL_LABEL_PREFIX, \
1389 (TARGET_GAS) ? "" : "#", \
1390 LOCAL_LABEL_PREFIX, \
1393 sdb_label_count++; \
1396 #define PUT_SDB_FUNCTION_START(LINE)
1398 #define PUT_SDB_FUNCTION_END(LINE) \
1400 ASM_OUTPUT_SOURCE_LINE (asm_out_file, LINE + sdb_begin_function_line); \
1403 #define PUT_SDB_EPILOGUE_END(NAME)
1405 /* Correct the offset of automatic variables and arguments. Note that
1406 the MIPS debug format wants all automatic variables and arguments
1407 to be in terms of the virtual frame pointer (stack pointer before
1408 any adjustment in the function), while the MIPS 3.0 linker wants
1409 the frame pointer to be the stack pointer after the initial
1412 #define DEBUGGER_AUTO_OFFSET(X) \
1413 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1414 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1415 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1417 /* Tell collect that the object format is ECOFF */
1418 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1419 #define EXTENDED_COFF /* ECOFF, not normal coff */
1421 /* Target machine storage layout */
1423 /* Define this if most significant bit is lowest numbered
1424 in instructions that operate on numbered bit-fields.
1426 #define BITS_BIG_ENDIAN 0
1428 /* Define this if most significant byte of a word is the lowest numbered. */
1429 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1431 /* Define this if most significant word of a multiword number is the lowest. */
1432 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1434 /* Define this to set the endianness to use in libgcc2.c, which can
1435 not depend on target_flags. */
1436 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1437 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1439 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1442 #define MAX_BITS_PER_WORD 64
1444 /* Width of a word, in units (bytes). */
1445 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1446 #define MIN_UNITS_PER_WORD 4
1448 /* For MIPS, width of a floating point register. */
1449 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1451 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1452 the next available register. */
1453 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1455 /* The largest size of value that can be held in floating-point
1456 registers and moved with a single instruction. */
1457 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1459 /* The largest size of value that can be held in floating-point
1461 #define UNITS_PER_FPVALUE \
1462 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1464 /* The number of bytes in a double. */
1465 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1467 /* A C expression for the size in bits of the type `int' on the
1468 target machine. If you don't define this, the default is one
1470 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1472 /* Tell the preprocessor the maximum size of wchar_t. */
1473 #ifndef MAX_WCHAR_TYPE_SIZE
1474 #ifndef WCHAR_TYPE_SIZE
1475 #define MAX_WCHAR_TYPE_SIZE 64
1479 /* A C expression for the size in bits of the type `short' on the
1480 target machine. If you don't define this, the default is half a
1481 word. (If this would be less than one storage unit, it is
1482 rounded up to one unit.) */
1483 #define SHORT_TYPE_SIZE 16
1485 /* A C expression for the size in bits of the type `long' on the
1486 target machine. If you don't define this, the default is one
1488 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1489 #define MAX_LONG_TYPE_SIZE 64
1491 /* A C expression for the size in bits of the type `long long' on the
1492 target machine. If you don't define this, the default is two
1494 #define LONG_LONG_TYPE_SIZE 64
1496 /* A C expression for the size in bits of the type `float' on the
1497 target machine. If you don't define this, the default is one
1499 #define FLOAT_TYPE_SIZE 32
1501 /* A C expression for the size in bits of the type `double' on the
1502 target machine. If you don't define this, the default is two
1504 #define DOUBLE_TYPE_SIZE 64
1506 /* A C expression for the size in bits of the type `long double' on
1507 the target machine. If you don't define this, the default is two
1509 #define LONG_DOUBLE_TYPE_SIZE \
1510 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1512 /* long double is not a fixed mode, but the idea is that, if we
1513 support long double, we also want a 128-bit integer type. */
1514 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1517 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1518 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1519 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1521 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1525 /* Width in bits of a pointer. */
1526 #ifndef POINTER_SIZE
1527 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1530 #define POINTERS_EXTEND_UNSIGNED 0
1532 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1533 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1534 || mips_abi == ABI_64 \
1535 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1538 /* Allocation boundary (in *bits*) for the code of a function. */
1539 #define FUNCTION_BOUNDARY 32
1541 /* Alignment of field after `int : 0' in a structure. */
1542 #define EMPTY_FIELD_BOUNDARY 32
1544 /* Every structure's size must be a multiple of this. */
1545 /* 8 is observed right on a DECstation and on riscos 4.02. */
1546 #define STRUCTURE_SIZE_BOUNDARY 8
1548 /* There is no point aligning anything to a rounder boundary than this. */
1549 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1551 /* Set this nonzero if move instructions will actually fail to work
1552 when given unaligned data. */
1553 #define STRICT_ALIGNMENT 1
1555 /* Define this if you wish to imitate the way many other C compilers
1556 handle alignment of bitfields and the structures that contain
1559 The behavior is that the type written for a bit-field (`int',
1560 `short', or other integer type) imposes an alignment for the
1561 entire structure, as if the structure really did contain an
1562 ordinary field of that type. In addition, the bit-field is placed
1563 within the structure so that it would fit within such a field,
1564 not crossing a boundary for it.
1566 Thus, on most machines, a bit-field whose type is written as `int'
1567 would not cross a four-byte boundary, and would force four-byte
1568 alignment for the whole structure. (The alignment used may not
1569 be four bytes; it is controlled by the other alignment
1572 If the macro is defined, its definition should be a C expression;
1573 a nonzero value for the expression enables this behavior. */
1575 #define PCC_BITFIELD_TYPE_MATTERS 1
1577 /* If defined, a C expression to compute the alignment given to a
1578 constant that is being placed in memory. CONSTANT is the constant
1579 and ALIGN is the alignment that the object would ordinarily have.
1580 The value of this macro is used instead of that alignment to align
1583 If this macro is not defined, then ALIGN is used.
1585 The typical use of this macro is to increase alignment for string
1586 constants to be word aligned so that `strcpy' calls that copy
1587 constants can be done inline. */
1589 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1590 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1591 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1593 /* If defined, a C expression to compute the alignment for a static
1594 variable. TYPE is the data type, and ALIGN is the alignment that
1595 the object would ordinarily have. The value of this macro is used
1596 instead of that alignment to align the object.
1598 If this macro is not defined, then ALIGN is used.
1600 One use of this macro is to increase alignment of medium-size
1601 data to make it all fit in fewer cache lines. Another is to
1602 cause character arrays to be word-aligned so that `strcpy' calls
1603 that copy constants to character arrays can be done inline. */
1605 #undef DATA_ALIGNMENT
1606 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1607 ((((ALIGN) < BITS_PER_WORD) \
1608 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1609 || TREE_CODE (TYPE) == UNION_TYPE \
1610 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1613 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1615 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1617 /* Define this macro if an argument declared as `char' or `short' in a
1618 prototype should actually be passed as an `int'. In addition to
1619 avoiding errors in certain cases of mismatch, it also makes for
1620 better code on certain machines. */
1622 #define PROMOTE_PROTOTYPES 1
1624 /* Define if operations between registers always perform the operation
1625 on the full register even if a narrower mode is specified. */
1626 #define WORD_REGISTER_OPERATIONS
1628 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1629 will either zero-extend or sign-extend. The value of this macro should
1630 be the code that says which one of the two operations is implicitly
1633 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1634 moves. All other referces are zero extended. */
1635 #define LOAD_EXTEND_OP(MODE) \
1636 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1637 ? SIGN_EXTEND : ZERO_EXTEND)
1639 /* Define this macro if it is advisable to hold scalars in registers
1640 in a wider mode than that declared by the program. In such cases,
1641 the value is constrained to be within the bounds of the declared
1642 type, but kept valid in the wider mode. The signedness of the
1643 extension may differ from that of the type. */
1645 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1646 if (GET_MODE_CLASS (MODE) == MODE_INT \
1647 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1649 if ((MODE) == SImode) \
1654 /* Define if loading short immediate values into registers sign extends. */
1655 #define SHORT_IMMEDIATES_SIGN_EXTEND
1658 /* Define this if function arguments should also be promoted using the above
1660 #define PROMOTE_FUNCTION_ARGS
1662 /* Likewise, if the function return value is promoted. */
1663 #define PROMOTE_FUNCTION_RETURN
1666 /* Standard register usage. */
1668 /* Number of actual hardware registers.
1669 The hardware registers are assigned numbers for the compiler
1670 from 0 to just below FIRST_PSEUDO_REGISTER.
1671 All registers that the compiler knows about must be given numbers,
1672 even those that are not normally considered general registers.
1674 On the Mips, we have 32 integer registers, 32 floating point
1675 registers, 8 condition code registers, and the special registers
1676 hi and lo. After that we have 32 COP0 registers, 32 COP2 registers,
1677 and 32 COP3 registers. (COP1 is the floating-point processor.)
1678 The 8 condition code registers are only used if mips_isa >= 4. */
1680 #define FIRST_PSEUDO_REGISTER 176
1682 /* 1 for registers that have pervasive standard uses
1683 and are not available for the register allocator.
1685 On the MIPS, see conventions, page D-2 */
1687 /* Regarding coprocessor registers: without evidence to the contrary,
1688 it's best to assume that each coprocessor register has a unique
1689 use. This can be overridden, in, e.g., override_options() or
1690 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1691 for a particular target. */
1693 #define FIXED_REGISTERS \
1695 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1696 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1697 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1698 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1699 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1700 /* COP0 registers */ \
1701 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1702 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1703 /* COP2 registers */ \
1704 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1705 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1706 /* COP3 registers */ \
1707 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1708 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1712 /* Don't mark $31 as a call-clobbered register. The idea is that
1713 it's really the call instructions themselves which clobber $31.
1714 We don't care what the called function does with it afterwards.
1716 This approach makes it easier to implement sibcalls. Unlike normal
1717 calls, sibcalls don't clobber $31, so the register reaches the
1718 called function in tact. EPILOGUE_USES says that $31 is useful
1719 to the called function. */
1721 #define CALL_USED_REGISTERS \
1723 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1724 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1725 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1726 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1727 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1728 /* COP0 registers */ \
1729 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1730 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1731 /* COP2 registers */ \
1732 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1733 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1734 /* COP3 registers */ \
1735 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1736 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1739 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1740 problem which makes CALL_USED_REGISTERS *always* include
1741 all the FIXED_REGISTERS. Until this problem has been
1742 resolved this macro can be used to overcome this situation.
1743 In particular, block_propagate() requires this list
1744 be acurate, or we can remove registers which should be live.
1745 This macro is used in regs_invalidated_by_call. */
1748 #define CALL_REALLY_USED_REGISTERS \
1749 { /* General registers. */ \
1750 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1751 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1752 /* Floating-point registers. */ \
1753 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1754 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1756 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1757 /* COP0 registers */ \
1758 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1759 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1760 /* COP2 registers */ \
1761 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1762 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1763 /* COP3 registers */ \
1764 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1765 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1768 /* Internal macros to classify a register number as to whether it's a
1769 general purpose register, a floating point register, a
1770 multiply/divide register, or a status register. */
1772 #define GP_REG_FIRST 0
1773 #define GP_REG_LAST 31
1774 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1775 #define GP_DBX_FIRST 0
1777 #define FP_REG_FIRST 32
1778 #define FP_REG_LAST 63
1779 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1780 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1782 #define MD_REG_FIRST 64
1783 #define MD_REG_LAST 65
1784 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1785 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1787 #define ST_REG_FIRST 67
1788 #define ST_REG_LAST 74
1789 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1792 /* FIXME: renumber. */
1793 #define COP0_REG_FIRST 80
1794 #define COP0_REG_LAST 111
1795 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1797 #define COP2_REG_FIRST 112
1798 #define COP2_REG_LAST 143
1799 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1801 #define COP3_REG_FIRST 144
1802 #define COP3_REG_LAST 175
1803 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1804 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1805 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1807 #define AT_REGNUM (GP_REG_FIRST + 1)
1808 #define HI_REGNUM (MD_REG_FIRST + 0)
1809 #define LO_REGNUM (MD_REG_FIRST + 1)
1811 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1812 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1813 should be used instead. */
1814 #define FPSW_REGNUM ST_REG_FIRST
1816 #define GP_REG_P(REGNO) \
1817 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1818 #define M16_REG_P(REGNO) \
1819 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1820 #define FP_REG_P(REGNO) \
1821 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1822 #define MD_REG_P(REGNO) \
1823 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1824 #define ST_REG_P(REGNO) \
1825 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1826 #define COP0_REG_P(REGNO) \
1827 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1828 #define COP2_REG_P(REGNO) \
1829 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1830 #define COP3_REG_P(REGNO) \
1831 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1832 #define ALL_COP_REG_P(REGNO) \
1833 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1835 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1837 /* Return coprocessor number from register number. */
1839 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1840 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1841 : COP3_REG_P (REGNO) ? '3' : '?')
1843 /* Return number of consecutive hard regs needed starting at reg REGNO
1844 to hold something of mode MODE.
1845 This is ordinarily the length in words of a value of mode MODE
1846 but can be less for certain modes in special long registers.
1848 On the MIPS, all general registers are one word long. Except on
1849 the R4000 with the FR bit set, the floating point uses register
1850 pairs, with the second register not being allocable. */
1852 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1854 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1855 MODE. In 32 bit mode, require that DImode and DFmode be in even
1856 registers. For DImode, this makes some of the insns easier to
1857 write, since you don't have to worry about a DImode value in
1858 registers 3 & 4, producing a result in 4 & 5.
1860 To make the code simpler HARD_REGNO_MODE_OK now just references an
1861 array built in override_options. Because machmodes.h is not yet
1862 included before this file is processed, the MODE bound can't be
1865 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1867 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1868 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1870 /* Value is 1 if it is a good idea to tie two pseudo registers
1871 when one has mode MODE1 and one has mode MODE2.
1872 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1873 for any hard reg, then this must be 0 for correct output. */
1874 #define MODES_TIEABLE_P(MODE1, MODE2) \
1875 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1876 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1877 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1878 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1880 /* MIPS pc is not overloaded on a register. */
1881 /* #define PC_REGNUM xx */
1883 /* Register to use for pushing function arguments. */
1884 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1886 /* Offset from the stack pointer to the first available location. Use
1887 the default value zero. */
1888 /* #define STACK_POINTER_OFFSET 0 */
1890 /* Base register for access to local variables of the function. We
1891 pretend that the frame pointer is $1, and then eliminate it to
1892 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1893 a fixed register, and will not be used for anything else. */
1894 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1896 /* Temporary scratch register for use by the assembler. */
1897 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1899 /* $30 is not available on the mips16, so we use $17 as the frame
1901 #define HARD_FRAME_POINTER_REGNUM \
1902 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1904 /* Value should be nonzero if functions must have frame pointers.
1905 Zero means the frame pointer need not be set up (and parms
1906 may be accessed via the stack pointer) in functions that seem suitable.
1907 This is computed in `reload', in reload1.c. */
1908 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1910 /* Base register for access to arguments of the function. */
1911 #define ARG_POINTER_REGNUM GP_REG_FIRST
1913 /* Register in which static-chain is passed to a function. */
1914 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1916 /* If the structure value address is passed in a register, then
1917 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1918 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1920 /* If the structure value address is not passed in a register, define
1921 `STRUCT_VALUE' as an expression returning an RTX for the place
1922 where the address is passed. If it returns 0, the address is
1923 passed as an "invisible" first argument. */
1924 #define STRUCT_VALUE 0
1926 /* Mips registers used in prologue/epilogue code when the stack frame
1927 is larger than 32K bytes. These registers must come from the
1928 scratch register set, and not used for passing and returning
1929 arguments and any other information used in the calling sequence
1930 (such as pic). Must start at 12, since t0/t3 are parameter passing
1931 registers in the 64 bit ABI. */
1933 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1934 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1936 /* Define this macro if it is as good or better to call a constant
1937 function address than to call an address kept in a register. */
1938 #define NO_FUNCTION_CSE 1
1940 /* Define this macro if it is as good or better for a function to
1941 call itself with an explicit address than to call an address
1942 kept in a register. */
1943 #define NO_RECURSIVE_FUNCTION_CSE 1
1945 /* The ABI-defined global pointer. Sometimes we use a different
1946 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1947 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1949 /* We normally use $28 as the global pointer. However, when generating
1950 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1951 register instead. They can then avoid saving and restoring $28
1952 and perhaps avoid using a frame at all.
1954 When a leaf function uses something other than $28, mips_expand_prologue
1955 will modify pic_offset_table_rtx in place. Take the register number
1956 from there after reload. */
1957 #define PIC_OFFSET_TABLE_REGNUM \
1958 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1960 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1962 /* Define the classes of registers for register constraints in the
1963 machine description. Also define ranges of constants.
1965 One of the classes must always be named ALL_REGS and include all hard regs.
1966 If there is more than one class, another class must be named NO_REGS
1967 and contain no registers.
1969 The name GENERAL_REGS must be the name of a class (or an alias for
1970 another name such as ALL_REGS). This is the class of registers
1971 that is allowed by "g" or "r" in a register constraint.
1972 Also, registers outside this class are allocated only when
1973 instructions express preferences for them.
1975 The classes must be numbered in nondecreasing order; that is,
1976 a larger-numbered class must never be contained completely
1977 in a smaller-numbered class.
1979 For any two classes, it is very desirable that there be another
1980 class that represents their union. */
1984 NO_REGS, /* no registers in set */
1985 M16_NA_REGS, /* mips16 regs not used to pass args */
1986 M16_REGS, /* mips16 directly accessible registers */
1987 T_REG, /* mips16 T register ($24) */
1988 M16_T_REGS, /* mips16 registers plus T register */
1989 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1990 LEA_REGS, /* Every GPR except $25 */
1991 GR_REGS, /* integer registers */
1992 FP_REGS, /* floating point registers */
1993 HI_REG, /* hi register */
1994 LO_REG, /* lo register */
1995 MD_REGS, /* multiply/divide registers (hi/lo) */
1996 COP0_REGS, /* generic coprocessor classes */
1999 HI_AND_GR_REGS, /* union classes */
2006 ALL_COP_AND_GR_REGS,
2007 ST_REGS, /* status registers (fp status) */
2008 ALL_REGS, /* all registers */
2009 LIM_REG_CLASSES /* max value + 1 */
2012 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2014 #define GENERAL_REGS GR_REGS
2016 /* An initializer containing the names of the register classes as C
2017 string constants. These names are used in writing some of the
2020 #define REG_CLASS_NAMES \
2027 "PIC_FN_ADDR_REG", \
2034 /* coprocessor registers */ \
2041 "COP0_AND_GR_REGS", \
2042 "COP2_AND_GR_REGS", \
2043 "COP3_AND_GR_REGS", \
2045 "ALL_COP_AND_GR_REGS", \
2050 /* An initializer containing the contents of the register classes,
2051 as integers which are bit masks. The Nth integer specifies the
2052 contents of class N. The way the integer MASK is interpreted is
2053 that register R is in the class if `MASK & (1 << R)' is 1.
2055 When the machine has more than 32 registers, an integer does not
2056 suffice. Then the integers are replaced by sub-initializers,
2057 braced groupings containing several integers. Each
2058 sub-initializer must be suitable as an initializer for the type
2059 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2061 #define REG_CLASS_CONTENTS \
2063 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2064 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2065 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2066 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2067 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2068 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
2069 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
2070 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2071 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2072 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2073 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2074 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2075 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2076 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2077 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2078 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2079 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2080 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2081 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2082 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2083 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2084 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2085 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2086 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2087 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2091 /* A C expression whose value is a register class containing hard
2092 register REGNO. In general there is more that one such class;
2093 choose a class which is "minimal", meaning that no smaller class
2094 also contains the register. */
2096 extern const enum reg_class mips_regno_to_class[];
2098 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2100 /* A macro whose definition is the name of the class to which a
2101 valid base register must belong. A base register is one used in
2102 an address which is the register value plus a displacement. */
2104 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2106 /* A macro whose definition is the name of the class to which a
2107 valid index register must belong. An index register is one used
2108 in an address where its value is either multiplied by a scale
2109 factor or added to another register (as well as added to a
2112 #define INDEX_REG_CLASS NO_REGS
2114 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2115 registers explicitly used in the rtl to be used as spill registers
2116 but prevents the compiler from extending the lifetime of these
2119 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2121 /* This macro is used later on in the file. */
2122 #define GR_REG_CLASS_P(CLASS) \
2123 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2124 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
2125 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
2127 /* This macro is also used later on in the file. */
2128 #define COP_REG_CLASS_P(CLASS) \
2129 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2131 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2132 is the default value (allocate the registers in numeric order). We
2133 define it just so that we can override it for the mips16 target in
2134 ORDER_REGS_FOR_LOCAL_ALLOC. */
2136 #define REG_ALLOC_ORDER \
2137 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2138 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2139 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2140 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2141 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2142 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2143 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2144 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2145 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2146 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2147 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2150 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2151 to be rearranged based on a particular function. On the mips16, we
2152 want to allocate $24 (T_REG) before other registers for
2153 instructions for which it is possible. */
2155 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2157 /* REGISTER AND CONSTANT CLASSES */
2159 /* Get reg_class from a letter such as appears in the machine
2162 DEFINED REGISTER CLASSES:
2164 'd' General (aka integer) registers
2165 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2166 'y' General registers (in both mips16 and non mips16 mode)
2167 'e' mips16 non argument registers (M16_NA_REGS)
2168 't' mips16 temporary register ($24)
2169 'f' Floating point registers
2172 'x' Multiply/divide registers
2173 'z' FP Status register
2177 'b' All registers */
2179 extern enum reg_class mips_char_to_class[256];
2181 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2183 /* True if VALUE is a signed 16-bit number. */
2185 #define SMALL_OPERAND(VALUE) \
2186 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2188 /* True if VALUE is an unsigned 16-bit number. */
2190 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2191 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2193 /* True if VALUE can be loaded into a register using LUI. */
2195 #define LUI_OPERAND(VALUE) \
2196 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2197 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2199 /* Return a value X with the low 16 bits clear, and such that
2200 VALUE - X is a signed 16-bit value. */
2202 #define CONST_HIGH_PART(VALUE) \
2203 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2205 #define CONST_LOW_PART(VALUE) \
2206 ((VALUE) - CONST_HIGH_PART (VALUE))
2208 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2209 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2210 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2212 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2213 string can be used to stand for particular ranges of immediate
2214 operands. This macro defines what the ranges are. C is the
2215 letter, and VALUE is a constant value. Return 1 if VALUE is
2216 in the range specified by C. */
2220 `I' is used for the range of constants an arithmetic insn can
2221 actually contain (16 bits signed integers).
2223 `J' is used for the range which is just zero (ie, $r0).
2225 `K' is used for the range of constants a logical insn can actually
2226 contain (16 bit zero-extended integers).
2228 `L' is used for the range of constants that be loaded with lui
2229 (ie, the bottom 16 bits are zero).
2231 `M' is used for the range of constants that take two words to load
2232 (ie, not matched by `I', `K', and `L').
2234 `N' is used for negative 16 bit constants other than -65536.
2236 `O' is a 15 bit signed integer.
2238 `P' is used for positive 16 bit constants. */
2240 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2241 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2242 : (C) == 'J' ? ((VALUE) == 0) \
2243 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2244 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2245 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2246 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2247 && !LUI_OPERAND (VALUE)) \
2248 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2249 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2250 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2253 /* Similar, but for floating constants, and defining letters G and H.
2254 Here VALUE is the CONST_DOUBLE rtx itself. */
2258 'G' : Floating point 0 */
2260 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2262 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2264 /* True if OP is a constant that should not be moved into $25.
2265 We need this because many versions of gas treat 'la $25,foo' as
2266 part of a call sequence and allow a global 'foo' to be lazily bound. */
2268 #define DANGEROUS_FOR_LA25_P(OP) \
2270 && !TARGET_EXPLICIT_RELOCS \
2271 && mips_global_pic_constant_p (OP))
2273 /* Letters in the range `Q' through `U' may be defined in a
2274 machine-dependent fashion to stand for arbitrary operand types.
2275 The machine description macro `EXTRA_CONSTRAINT' is passed the
2276 operand as its first argument and the constraint letter as its
2279 `Q' is for signed 16-bit constants.
2280 `R' is for single-instruction memory references. Note that this
2281 constraint has often been used in linux and glibc code.
2282 `S' is for legitimate constant call addresses.
2283 `T' is for constant move_operands that cannot be safely loaded into $25.
2284 `U' is for constant move_operands that can be safely loaded into $25. */
2286 #define EXTRA_CONSTRAINT(OP,CODE) \
2287 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2288 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2289 && mips_fetch_insns (OP) == 1) \
2290 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2291 && call_insn_operand (OP, VOIDmode)) \
2292 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2293 && move_operand (OP, VOIDmode) \
2294 && DANGEROUS_FOR_LA25_P (OP)) \
2295 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2296 && move_operand (OP, VOIDmode) \
2297 && !DANGEROUS_FOR_LA25_P (OP)) \
2300 /* Given an rtx X being reloaded into a reg required to be
2301 in class CLASS, return the class of reg to actually use.
2302 In general this is just CLASS; but on some machines
2303 in some cases it is preferable to use a more restrictive class. */
2305 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2306 ((CLASS) != ALL_REGS \
2307 ? (! TARGET_MIPS16 \
2309 : ((CLASS) != GR_REGS \
2312 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2313 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2314 ? (TARGET_SOFT_FLOAT \
2315 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2317 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2318 || GET_MODE (X) == VOIDmode) \
2319 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2322 /* Certain machines have the property that some registers cannot be
2323 copied to some other registers without using memory. Define this
2324 macro on those machines to be a C expression that is nonzero if
2325 objects of mode MODE in registers of CLASS1 can only be copied to
2326 registers of class CLASS2 by storing a register of CLASS1 into
2327 memory and loading that memory location into a register of CLASS2.
2329 Do not define this macro if its value would always be zero. */
2331 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2332 ((!TARGET_DEBUG_H_MODE \
2333 && GET_MODE_CLASS (MODE) == MODE_INT \
2334 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2335 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2336 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2337 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2338 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2340 /* The HI and LO registers can only be reloaded via the general
2341 registers. Condition code registers can only be loaded to the
2342 general registers, and from the floating point registers. */
2344 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2345 mips_secondary_reload_class (CLASS, MODE, X, 1)
2346 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2347 mips_secondary_reload_class (CLASS, MODE, X, 0)
2349 /* Return the maximum number of consecutive registers
2350 needed to represent mode MODE in a register of class CLASS. */
2352 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2354 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2355 mips_cannot_change_mode_class (FROM, TO, CLASS)
2357 /* Stack layout; function entry, exit and calling. */
2359 #define STACK_GROWS_DOWNWARD
2361 /* The offset of the first local variable from the beginning of the frame.
2362 See compute_frame_size for details about the frame layout. */
2363 #define STARTING_FRAME_OFFSET \
2364 (current_function_outgoing_args_size \
2365 + (TARGET_ABICALLS && !TARGET_NEWABI \
2366 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2368 /* Offset from the stack pointer register to an item dynamically
2369 allocated on the stack, e.g., by `alloca'.
2371 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2372 length of the outgoing arguments. The default is correct for most
2373 machines. See `function.c' for details.
2375 The MIPS ABI states that functions which dynamically allocate the
2376 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2377 we are trying to create a second frame pointer to the function, so
2378 allocate some stack space to make it happy.
2380 However, the linker currently complains about linking any code that
2381 dynamically allocates stack space, and there seems to be a bug in
2382 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2385 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2386 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2387 ? 4*UNITS_PER_WORD \
2388 : current_function_outgoing_args_size)
2391 /* The return address for the current frame is in r31 if this is a leaf
2392 function. Otherwise, it is on the stack. It is at a variable offset
2393 from sp/fp/ap, so we define a fake hard register rap which is a
2394 poiner to the return address on the stack. This always gets eliminated
2395 during reload to be either the frame pointer or the stack pointer plus
2398 #define RETURN_ADDR_RTX mips_return_addr
2400 /* Since the mips16 ISA mode is encoded in the least-significant bit
2401 of the address, mask it off return addresses for purposes of
2402 finding exception handling regions. */
2404 #define MASK_RETURN_ADDR GEN_INT (-2)
2407 /* Similarly, don't use the least-significant bit to tell pointers to
2408 code from vtable index. */
2410 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2412 /* If defined, this macro specifies a table of register pairs used to
2413 eliminate unneeded registers that point into the stack frame. If
2414 it is not defined, the only elimination attempted by the compiler
2415 is to replace references to the frame pointer with references to
2418 The definition of this macro is a list of structure
2419 initializations, each of which specifies an original and
2420 replacement register.
2422 On some machines, the position of the argument pointer is not
2423 known until the compilation is completed. In such a case, a
2424 separate hard register must be used for the argument pointer.
2425 This register can be eliminated by replacing it with either the
2426 frame pointer or the argument pointer, depending on whether or not
2427 the frame pointer has been eliminated.
2429 In this case, you might specify:
2430 #define ELIMINABLE_REGS \
2431 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2432 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2433 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2435 Note that the elimination of the argument pointer with the stack
2436 pointer is specified first since that is the preferred elimination.
2438 The eliminations to $17 are only used on the mips16. See the
2439 definition of HARD_FRAME_POINTER_REGNUM. */
2441 #define ELIMINABLE_REGS \
2442 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2443 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2444 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2445 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2446 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2447 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2449 /* A C expression that returns nonzero if the compiler is allowed to
2450 try to replace register number FROM-REG with register number
2451 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2452 defined, and will usually be the constant 1, since most of the
2453 cases preventing register elimination are things that the compiler
2454 already knows about.
2456 When not in mips16 and mips64, we can always eliminate to the
2457 frame pointer. We can eliminate to the stack pointer unless
2458 a frame pointer is needed. In mips16 mode, we need a frame
2459 pointer for a large frame; otherwise, reload may be unable
2460 to compute the address of a local variable, since there is
2461 no way to add a large constant to the stack pointer
2462 without using a temporary register.
2464 In mips16, for some instructions (eg lwu), we can't eliminate the
2465 frame pointer for the stack pointer. These instructions are
2466 only generated in TARGET_64BIT mode.
2469 #define CAN_ELIMINATE(FROM, TO) \
2470 (((TO) == HARD_FRAME_POINTER_REGNUM \
2471 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2472 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2473 && (! TARGET_MIPS16 \
2474 || compute_frame_size (get_frame_size ()) < 32768))))
2476 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2477 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2479 /* If we generate an insn to push BYTES bytes,
2480 this says how many the stack pointer really advances by.
2481 On the VAX, sp@- in a byte insn really pushes a word. */
2483 /* #define PUSH_ROUNDING(BYTES) 0 */
2485 /* If defined, the maximum amount of space required for outgoing
2486 arguments will be computed and placed into the variable
2487 `current_function_outgoing_args_size'. No space will be pushed
2488 onto the stack for each call; instead, the function prologue
2489 should increase the stack frame size by this amount.
2491 It is not proper to define both `PUSH_ROUNDING' and
2492 `ACCUMULATE_OUTGOING_ARGS'. */
2493 #define ACCUMULATE_OUTGOING_ARGS 1
2495 /* Offset from the argument pointer register to the first argument's
2496 address. On some machines it may depend on the data type of the
2499 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2500 the first argument's address.
2502 On the MIPS, we must skip the first argument position if we are
2503 returning a structure or a union, to account for its address being
2504 passed in $4. However, at the current time, this produces a compiler
2505 that can't bootstrap, so comment it out for now. */
2508 #define FIRST_PARM_OFFSET(FNDECL) \
2510 && TREE_TYPE (FNDECL) != 0 \
2511 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2512 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2513 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2517 #define FIRST_PARM_OFFSET(FNDECL) 0
2520 /* When a parameter is passed in a register, stack space is still
2521 allocated for it. For the MIPS, stack space must be allocated, cf
2522 Asm Lang Prog Guide page 7-8.
2524 BEWARE that some space is also allocated for non existing arguments
2525 in register. In case an argument list is of form GF used registers
2526 are a0 (a2,a3), but we should push over a1... */
2528 #define REG_PARM_STACK_SPACE(FNDECL) \
2529 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2530 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2533 /* Define this if it is the responsibility of the caller to
2534 allocate the area reserved for arguments passed in registers.
2535 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2536 of this macro is to determine whether the space is included in
2537 `current_function_outgoing_args_size'. */
2538 #define OUTGOING_REG_PARM_STACK_SPACE
2540 #define STACK_BOUNDARY \
2541 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2544 /* Make sure 4 words are always allocated on the stack. */
2546 #ifndef STACK_ARGS_ADJUST
2547 #define STACK_ARGS_ADJUST(SIZE) \
2549 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2550 SIZE.constant = 4 * UNITS_PER_WORD; \
2555 /* A C expression that should indicate the number of bytes of its
2556 own arguments that a function pops on returning, or 0
2557 if the function pops no arguments and the caller must therefore
2558 pop them all after the function returns.
2560 FUNDECL is the declaration node of the function (as a tree).
2562 FUNTYPE is a C variable whose value is a tree node that
2563 describes the function in question. Normally it is a node of
2564 type `FUNCTION_TYPE' that describes the data type of the function.
2565 From this it is possible to obtain the data types of the value
2566 and arguments (if known).
2568 When a call to a library function is being considered, FUNTYPE
2569 will contain an identifier node for the library function. Thus,
2570 if you need to distinguish among various library functions, you
2571 can do so by their names. Note that "library function" in this
2572 context means a function used to perform arithmetic, whose name
2573 is known specially in the compiler and was not mentioned in the
2574 C code being compiled.
2576 STACK-SIZE is the number of bytes of arguments passed on the
2577 stack. If a variable number of bytes is passed, it is zero, and
2578 argument popping will always be the responsibility of the
2579 calling function. */
2581 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2584 /* Symbolic macros for the registers used to return integer and floating
2587 #define GP_RETURN (GP_REG_FIRST + 2)
2588 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2590 #define MAX_ARGS_IN_REGISTERS \
2591 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2593 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2595 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2597 /* Symbolic macros for the first/last argument registers. */
2599 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2600 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2601 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2602 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2604 /* Define how to find the value returned by a library function
2605 assuming the value has mode MODE. Because we define
2606 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2607 PROMOTE_MODE does. */
2609 #define LIBCALL_VALUE(MODE) \
2610 mips_function_value (NULL_TREE, NULL, (MODE))
2612 /* Define how to find the value returned by a function.
2613 VALTYPE is the data type of the value (as a tree).
2614 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2615 otherwise, FUNC is 0. */
2617 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2618 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2620 /* 1 if N is a possible register number for a function value.
2621 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2622 Currently, R2 and F0 are only implemented here (C has no complex type) */
2624 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2625 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2626 && (N) == FP_RETURN + 2))
2628 /* 1 if N is a possible register number for function argument passing.
2629 We have no FP argument registers when soft-float. When FP registers
2630 are 32 bits, we can't directly reference the odd numbered ones. */
2632 #define FUNCTION_ARG_REGNO_P(N) \
2633 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2634 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2635 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2638 /* A C expression which can inhibit the returning of certain function
2639 values in registers, based on the type of value. A nonzero value says
2640 to return the function value in memory, just as large structures are
2641 always returned. Here TYPE will be a C expression of type
2642 `tree', representing the data type of the value.
2644 Note that values of mode `BLKmode' must be explicitly
2645 handled by this macro. Also, the option `-fpcc-struct-return'
2646 takes effect regardless of this macro. On most systems, it is
2647 possible to leave the macro undefined; this causes a default
2648 definition to be used, whose value is the constant 1 for BLKmode
2649 values, and 0 otherwise.
2651 GCC normally converts 1 byte structures into chars, 2 byte
2652 structs into shorts, and 4 byte structs into ints, and returns
2653 them this way. Defining the following macro overrides this,
2654 to give us MIPS cc compatibility. */
2656 #define RETURN_IN_MEMORY(TYPE) \
2657 mips_return_in_memory (TYPE)
2659 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2660 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2663 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2665 /* Define a data type for recording info about an argument list
2666 during the scan of that argument list. This data type should
2667 hold all necessary information about the function itself
2668 and about the args processed so far, enough to enable macros
2669 such as FUNCTION_ARG to determine where the next arg should go.
2671 This structure has to cope with two different argument allocation
2672 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2673 first N words go in registers and the rest go on the stack. If I < N,
2674 the Ith word might go in Ith integer argument register or the
2675 Ith floating-point one. In some cases, it has to go in both (see
2676 function_arg). For these ABIs, we only need to remember the number
2677 of words passed so far.
2679 The EABI instead allocates the integer and floating-point arguments
2680 separately. The first N words of FP arguments go in FP registers,
2681 the rest go on the stack. Likewise, the first N words of the other
2682 arguments go in integer registers, and the rest go on the stack. We
2683 need to maintain three counts: the number of integer registers used,
2684 the number of floating-point registers used, and the number of words
2685 passed on the stack.
2687 We could keep separate information for the two ABIs (a word count for
2688 the standard ABIs, and three separate counts for the EABI). But it
2689 seems simpler to view the standard ABIs as forms of EABI that do not
2690 allocate floating-point registers.
2692 So for the standard ABIs, the first N words are allocated to integer
2693 registers, and function_arg decides on an argument-by-argument basis
2694 whether that argument should really go in an integer register, or in
2695 a floating-point one. */
2697 typedef struct mips_args {
2698 /* Always true for varargs functions. Otherwise true if at least
2699 one argument has been passed in an integer register. */
2702 /* The number of arguments seen so far. */
2703 unsigned int arg_number;
2705 /* For EABI, the number of integer registers used so far. For other
2706 ABIs, the number of words passed in registers (whether integer
2707 or floating-point). */
2708 unsigned int num_gprs;
2710 /* For EABI, the number of floating-point registers used so far. */
2711 unsigned int num_fprs;
2713 /* The number of words passed on the stack. */
2714 unsigned int stack_words;
2716 /* On the mips16, we need to keep track of which floating point
2717 arguments were passed in general registers, but would have been
2718 passed in the FP regs if this were a 32 bit function, so that we
2719 can move them to the FP regs if we wind up calling a 32 bit
2720 function. We record this information in fp_code, encoded in base
2721 four. A zero digit means no floating point argument, a one digit
2722 means an SFmode argument, and a two digit means a DFmode argument,
2723 and a three digit is not used. The low order digit is the first
2724 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2725 an SFmode argument. ??? A more sophisticated approach will be
2726 needed if MIPS_ABI != ABI_32. */
2729 /* True if the function has a prototype. */
2732 /* When a structure does not take up a full register, the argument
2733 should sometimes be shifted left so that it occupies the high part
2734 of the register. These two fields describe an array of ashl
2735 patterns for doing this. See function_arg_advance, which creates
2736 the shift patterns, and function_arg, which returns them when given
2737 a VOIDmode argument. */
2738 unsigned int num_adjusts;
2739 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2742 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2743 for a call to a function whose data type is FNTYPE.
2744 For a library call, FNTYPE is 0.
2748 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2749 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2751 /* Update the data in CUM to advance over an argument
2752 of mode MODE and data type TYPE.
2753 (TYPE is null for libcalls where that information may not be available.) */
2755 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2756 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2758 /* Determine where to put an argument to a function.
2759 Value is zero to push the argument on the stack,
2760 or a hard register in which to store the argument.
2762 MODE is the argument's machine mode.
2763 TYPE is the data type of the argument (as a tree).
2764 This is null for libcalls where that information may
2766 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2767 the preceding args and about the function being called.
2768 NAMED is nonzero if this argument is a named parameter
2769 (otherwise it is an extra parameter matching an ellipsis). */
2771 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2772 function_arg( &CUM, MODE, TYPE, NAMED)
2774 /* For an arg passed partly in registers and partly in memory,
2775 this is the number of registers used.
2776 For args passed entirely in registers or entirely in memory, zero. */
2778 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2779 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2781 /* If defined, a C expression that gives the alignment boundary, in
2782 bits, of an argument with the specified mode and type. If it is
2783 not defined, `PARM_BOUNDARY' is used for all arguments. */
2785 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2787 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2789 : TYPE_ALIGN(TYPE)) \
2790 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2792 : GET_MODE_ALIGNMENT(MODE)))
2794 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2795 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2797 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2798 (! BYTES_BIG_ENDIAN \
2800 : (((MODE) == BLKmode \
2801 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2802 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2803 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2804 && (mips_abi == ABI_32 \
2805 || mips_abi == ABI_O64 \
2806 || mips_abi == ABI_EABI \
2807 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2808 ? downward : upward))
2810 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2811 (mips_abi == ABI_EABI && (NAMED) \
2812 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2814 /* Modified version of the macro in expr.h. */
2815 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2817 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2818 || TREE_ADDRESSABLE (TYPE) \
2819 || ((MODE) == BLKmode \
2820 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2821 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2822 && 0 == (int_size_in_bytes (TYPE) \
2823 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2824 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2825 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2827 /* True if using EABI and varargs can be passed in floating-point
2828 registers. Under these conditions, we need a more complex form
2829 of va_list, which tracks GPR, FPR and stack arguments separately. */
2830 #define EABI_FLOAT_VARARGS_P \
2831 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2834 /* Say that the epilogue uses the return address register. Note that
2835 in the case of sibcalls, the values "used by the epilogue" are
2836 considered live at the start of the called function. */
2837 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2839 /* Treat LOC as a byte offset from the stack pointer and round it up
2840 to the next fully-aligned offset. */
2841 #define MIPS_STACK_ALIGN(LOC) \
2842 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2843 ? ((LOC) + 7) & ~7 \
2844 : ((LOC) + 15) & ~15)
2847 /* Define the `__builtin_va_list' type for the ABI. */
2848 #define BUILD_VA_LIST_TYPE(VALIST) \
2849 (VALIST) = mips_build_va_list ()
2851 /* Implement `va_start' for varargs and stdarg. */
2852 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2853 mips_va_start (valist, nextarg)
2855 /* Implement `va_arg'. */
2856 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2857 mips_va_arg (valist, type)
2859 /* Output assembler code to FILE to increment profiler label # LABELNO
2860 for profiling a function entry. */
2862 #define FUNCTION_PROFILER(FILE, LABELNO) \
2864 if (TARGET_MIPS16) \
2865 sorry ("mips16 function profiling"); \
2866 fprintf (FILE, "\t.set\tnoat\n"); \
2867 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2868 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2869 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2872 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2873 TARGET_64BIT ? "dsubu" : "subu", \
2874 reg_names[STACK_POINTER_REGNUM], \
2875 reg_names[STACK_POINTER_REGNUM], \
2876 Pmode == DImode ? 16 : 8); \
2878 fprintf (FILE, "\tjal\t_mcount\n"); \
2879 fprintf (FILE, "\t.set\tat\n"); \
2882 /* Define this macro if the code for function profiling should come
2883 before the function prologue. Normally, the profiling code comes
2886 /* #define PROFILE_BEFORE_PROLOGUE */
2888 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2889 the stack pointer does not matter. The value is tested only in
2890 functions that have frame pointers.
2891 No definition is equivalent to always zero. */
2893 #define EXIT_IGNORE_STACK 1
2896 /* A C statement to output, on the stream FILE, assembler code for a
2897 block of data that contains the constant parts of a trampoline.
2898 This code should not include a label--the label is taken care of
2901 #define TRAMPOLINE_TEMPLATE(STREAM) \
2903 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2904 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2905 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2906 if (ptr_mode == DImode) \
2908 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2909 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2913 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2914 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2916 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2917 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2918 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2919 if (ptr_mode == DImode) \
2921 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2922 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2926 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2927 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2931 /* A C expression for the size in bytes of the trampoline, as an
2934 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2936 /* Alignment required for trampolines, in bits. */
2938 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2940 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2941 program and data caches. */
2943 #ifndef CACHE_FLUSH_FUNC
2944 #define CACHE_FLUSH_FUNC "_flush_cache"
2947 /* A C statement to initialize the variable parts of a trampoline.
2948 ADDR is an RTX for the address of the trampoline; FNADDR is an
2949 RTX for the address of the nested function; STATIC_CHAIN is an
2950 RTX for the static chain value that should be passed to the
2951 function when it is called. */
2953 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2955 rtx func_addr, chain_addr; \
2957 func_addr = plus_constant (ADDR, 32); \
2958 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2959 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2960 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2961 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2962 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
2964 /* Flush both caches. We need to flush the data cache in case \
2965 the system has a write-back cache. */ \
2966 /* ??? Should check the return value for errors. */ \
2967 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2968 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2969 0, VOIDmode, 3, ADDR, Pmode, \
2970 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2971 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2974 /* Addressing modes, and classification of registers for them. */
2976 /* These assume that REGNO is a hard or pseudo reg number.
2977 They give nonzero only if REGNO is a hard reg of the suitable class
2978 or a pseudo reg currently allocated to a suitable hard reg.
2979 These definitions are NOT overridden anywhere. */
2981 #define BASE_REG_P(regno, mode) \
2983 ? (M16_REG_P (regno) \
2984 || (regno) == FRAME_POINTER_REGNUM \
2985 || (regno) == ARG_POINTER_REGNUM \
2986 || ((regno) == STACK_POINTER_REGNUM \
2987 && (GET_MODE_SIZE (mode) == 4 \
2988 || GET_MODE_SIZE (mode) == 8))) \
2991 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2992 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2995 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2996 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2998 #define REGNO_OK_FOR_INDEX_P(regno) 0
2999 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3000 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3002 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3003 and check its validity for a certain class.
3004 We have two alternate definitions for each of them.
3005 The usual definition accepts all pseudo regs; the other rejects them all.
3006 The symbol REG_OK_STRICT causes the latter definition to be used.
3008 Most source files want to accept pseudo regs in the hope that
3009 they will get allocated to the class that the insn wants them to be in.
3010 Some source files that are used after register allocation
3011 need to be strict. */
3013 #ifndef REG_OK_STRICT
3014 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3015 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3017 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3018 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3021 #define REG_OK_FOR_INDEX_P(X) 0
3024 /* Maximum number of registers that can appear in a valid memory address. */
3026 #define MAX_REGS_PER_ADDRESS 1
3028 /* A C compound statement with a conditional `goto LABEL;' executed
3029 if X (an RTX) is a legitimate memory address on the target
3030 machine for a memory operand of mode MODE. */
3033 #define GO_PRINTF(x) fprintf(stderr, (x))
3034 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3035 #define GO_DEBUG_RTX(x) debug_rtx(x)
3038 #define GO_PRINTF(x)
3039 #define GO_PRINTF2(x,y)
3040 #define GO_DEBUG_RTX(x)
3043 #ifdef REG_OK_STRICT
3044 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3046 if (mips_legitimate_address_p (MODE, X, 1)) \
3050 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3052 if (mips_legitimate_address_p (MODE, X, 0)) \
3057 /* Check for constness inline but use mips_legitimate_address_p
3058 to check whether a constant really is an address. */
3060 #define CONSTANT_ADDRESS_P(X) \
3061 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
3064 /* Nonzero if the constant value X is a legitimate general operand.
3065 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3067 At present, GAS doesn't understand li.[sd], so don't allow it
3068 to be generated at present. Also, the MIPS assembler does not
3069 grok li.d Infinity. */
3071 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3072 Note that the Irix 6 assembler problem may already be fixed.
3073 Note also that the GET_CODE (X) == CONST test catches the mips16
3074 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3075 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3076 ABI_64 to work together, we'll need to fix this. */
3077 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
3079 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3081 if (mips_legitimize_address (&(X), MODE)) \
3086 /* A C statement or compound statement with a conditional `goto
3087 LABEL;' executed if memory address X (an RTX) can have different
3088 meanings depending on the machine mode of the memory reference it
3091 Autoincrement and autodecrement addresses typically have
3092 mode-dependent effects because the amount of the increment or
3093 decrement is the size of the operand being addressed. Some
3094 machines have other mode-dependent addresses. Many RISC machines
3095 have no mode-dependent addresses.
3097 You may assume that ADDR is a valid address for the machine. */
3099 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3101 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3102 'the start of the function that this code is output in'. */
3104 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3105 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3106 asm_fprintf ((FILE), "%U%s", \
3107 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3109 asm_fprintf ((FILE), "%U%s", (NAME))
3111 /* The mips16 wants the constant pool to be after the function,
3112 because the PC relative load instructions use unsigned offsets. */
3114 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3116 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3117 mips_string_length = 0;
3119 /* Specify the machine mode that this machine uses
3120 for the index in the tablejump instruction.
3121 ??? Using HImode in mips16 mode can cause overflow. However, the
3122 overflow is no more likely than the overflow in a branch
3123 instruction. Large functions can currently break in both ways. */
3124 #define CASE_VECTOR_MODE \
3125 (TARGET_MIPS16 ? HImode : ptr_mode)
3127 /* Define as C expression which evaluates to nonzero if the tablejump
3128 instruction expects the table to contain offsets from the address of the
3130 Do not define this if the table should contain absolute addresses. */
3131 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3133 /* Define this as 1 if `char' should by default be signed; else as 0. */
3134 #ifndef DEFAULT_SIGNED_CHAR
3135 #define DEFAULT_SIGNED_CHAR 1
3138 /* Max number of bytes we can move from memory to memory
3139 in one reasonably fast instruction. */
3140 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3141 #define MAX_MOVE_MAX 8
3143 /* Define this macro as a C expression which is nonzero if
3144 accessing less than a word of memory (i.e. a `char' or a
3145 `short') is no faster than accessing a word of memory, i.e., if
3146 such access require more than one instruction or if there is no
3147 difference in cost between byte and (aligned) word loads.
3149 On RISC machines, it tends to generate better code to define
3150 this as 1, since it avoids making a QI or HI mode register. */
3151 #define SLOW_BYTE_ACCESS 1
3153 /* Define this to be nonzero if shift instructions ignore all but the low-order
3155 #define SHIFT_COUNT_TRUNCATED 1
3157 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3158 is done just by pretending it is already truncated. */
3159 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3160 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3163 /* Specify the machine mode that pointers have.
3164 After generation of rtl, the compiler makes no further distinction
3165 between pointers and any other objects of this machine mode. */
3168 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
3171 /* Give call MEMs SImode since it is the "most permissive" mode
3172 for both 32-bit and 64-bit targets. */
3174 #define FUNCTION_MODE SImode
3177 /* The cost of loading values from the constant pool. It should be
3178 larger than the cost of any constant we want to synthesise in-line. */
3180 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
3182 /* A C expression for the cost of moving data from a register in
3183 class FROM to one in class TO. The classes are expressed using
3184 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3185 the default; other values are interpreted relative to that.
3187 It is not required that the cost always equal 2 when FROM is the
3188 same as TO; on some machines it is expensive to move between
3189 registers if they are not general registers.
3191 If reload sees an insn consisting of a single `set' between two
3192 hard registers, and if `REGISTER_MOVE_COST' applied to their
3193 classes returns a value of 2, reload does not check to ensure
3194 that the constraints of the insn are met. Setting a cost of
3195 other than 2 will allow reload to verify that the constraints are
3196 met. You should do this if the `movM' pattern's constraints do
3197 not allow such copying. */
3199 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3200 mips_register_move_cost (MODE, FROM, TO)
3202 /* ??? Fix this to be right for the R8000. */
3203 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3204 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3205 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3207 /* Define if copies to/from condition code registers should be avoided.
3209 This is needed for the MIPS because reload_outcc is not complete;
3210 it needs to handle cases where the source is a general or another
3211 condition code register. */
3212 #define AVOID_CCMODE_COPIES
3214 /* A C expression for the cost of a branch instruction. A value of
3215 1 is the default; other values are interpreted relative to that. */
3217 /* ??? Fix this to be right for the R8000. */
3218 #define BRANCH_COST \
3220 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3223 /* If defined, modifies the length assigned to instruction INSN as a
3224 function of the context in which it is used. LENGTH is an lvalue
3225 that contains the initially computed length of the insn and should
3226 be updated with the correct length of the insn. */
3227 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3228 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3231 /* Optionally define this if you have added predicates to
3232 `MACHINE.c'. This macro is called within an initializer of an
3233 array of structures. The first field in the structure is the
3234 name of a predicate and the second field is an array of rtl
3235 codes. For each predicate, list all rtl codes that can be in
3236 expressions matched by the predicate. The list should have a
3237 trailing comma. Here is an example of two entries in the list
3238 for a typical RISC machine:
3240 #define PREDICATE_CODES \
3241 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3242 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3244 Defining this macro does not affect the generated code (however,
3245 incorrect definitions that omit an rtl code that may be matched
3246 by the predicate can cause the compiler to malfunction).
3247 Instead, it allows the table built by `genrecog' to be more
3248 compact and efficient, thus speeding up the compiler. The most
3249 important predicates to include in the list specified by this
3250 macro are thoses used in the most insn patterns. */
3252 #define PREDICATE_CODES \
3253 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3254 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3255 {"const_arith_operand", { CONST, CONST_INT }}, \
3256 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3257 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3258 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3259 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3260 {"small_int", { CONST_INT }}, \
3261 {"large_int", { CONST_INT }}, \
3262 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3263 {"const_float_1_operand", { CONST_DOUBLE }}, \
3264 {"simple_memory_operand", { MEM, SUBREG }}, \
3265 {"equality_op", { EQ, NE }}, \
3266 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3268 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3269 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3270 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
3271 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3272 SYMBOL_REF, LABEL_REF, SUBREG, \
3274 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3275 CONST_DOUBLE, CONST }}, \
3276 {"fcc_register_operand", { REG, SUBREG }}, \
3277 {"hilo_operand", { REG }}, \
3278 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
3280 /* A list of predicates that do special things with modes, and so
3281 should not elicit warnings for VOIDmode match_operand. */
3283 #define SPECIAL_MODE_PREDICATES \
3284 "pc_or_label_operand",
3286 /* Control the assembler format that we output. */
3288 /* Output at beginning of assembler file.
3289 If we are optimizing to use the global pointer, create a temporary
3290 file to hold all of the text stuff, and write it out to the end.
3291 This is needed because the MIPS assembler is evidently one pass,
3292 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3293 declaration when the code is processed, it generates a two
3294 instruction sequence. */
3296 #undef ASM_FILE_START
3297 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3299 /* Output to assembler file text saying following lines
3300 may contain character constants, extra white space, comments, etc. */
3303 #define ASM_APP_ON " #APP\n"
3306 /* Output to assembler file text saying following lines
3307 no longer contain unusual constructs. */
3310 #define ASM_APP_OFF " #NO_APP\n"
3313 /* How to refer to registers in assembler output.
3314 This sequence is indexed by compiler's hard-register-number (see above).
3316 In order to support the two different conventions for register names,
3317 we use the name of a table set up in mips.c, which is overwritten
3318 if -mrnames is used. */
3320 #define REGISTER_NAMES \
3322 &mips_reg_names[ 0][0], \
3323 &mips_reg_names[ 1][0], \
3324 &mips_reg_names[ 2][0], \
3325 &mips_reg_names[ 3][0], \
3326 &mips_reg_names[ 4][0], \
3327 &mips_reg_names[ 5][0], \
3328 &mips_reg_names[ 6][0], \
3329 &mips_reg_names[ 7][0], \
3330 &mips_reg_names[ 8][0], \
3331 &mips_reg_names[ 9][0], \
3332 &mips_reg_names[10][0], \
3333 &mips_reg_names[11][0], \
3334 &mips_reg_names[12][0], \
3335 &mips_reg_names[13][0], \
3336 &mips_reg_names[14][0], \
3337 &mips_reg_names[15][0], \
3338 &mips_reg_names[16][0], \
3339 &mips_reg_names[17][0], \
3340 &mips_reg_names[18][0], \
3341 &mips_reg_names[19][0], \
3342 &mips_reg_names[20][0], \
3343 &mips_reg_names[21][0], \
3344 &mips_reg_names[22][0], \
3345 &mips_reg_names[23][0], \
3346 &mips_reg_names[24][0], \
3347 &mips_reg_names[25][0], \
3348 &mips_reg_names[26][0], \
3349 &mips_reg_names[27][0], \
3350 &mips_reg_names[28][0], \
3351 &mips_reg_names[29][0], \
3352 &mips_reg_names[30][0], \
3353 &mips_reg_names[31][0], \
3354 &mips_reg_names[32][0], \
3355 &mips_reg_names[33][0], \
3356 &mips_reg_names[34][0], \
3357 &mips_reg_names[35][0], \
3358 &mips_reg_names[36][0], \
3359 &mips_reg_names[37][0], \
3360 &mips_reg_names[38][0], \
3361 &mips_reg_names[39][0], \
3362 &mips_reg_names[40][0], \
3363 &mips_reg_names[41][0], \
3364 &mips_reg_names[42][0], \
3365 &mips_reg_names[43][0], \
3366 &mips_reg_names[44][0], \
3367 &mips_reg_names[45][0], \
3368 &mips_reg_names[46][0], \
3369 &mips_reg_names[47][0], \
3370 &mips_reg_names[48][0], \
3371 &mips_reg_names[49][0], \
3372 &mips_reg_names[50][0], \
3373 &mips_reg_names[51][0], \
3374 &mips_reg_names[52][0], \
3375 &mips_reg_names[53][0], \
3376 &mips_reg_names[54][0], \
3377 &mips_reg_names[55][0], \
3378 &mips_reg_names[56][0], \
3379 &mips_reg_names[57][0], \
3380 &mips_reg_names[58][0], \
3381 &mips_reg_names[59][0], \
3382 &mips_reg_names[60][0], \
3383 &mips_reg_names[61][0], \
3384 &mips_reg_names[62][0], \
3385 &mips_reg_names[63][0], \
3386 &mips_reg_names[64][0], \
3387 &mips_reg_names[65][0], \
3388 &mips_reg_names[66][0], \
3389 &mips_reg_names[67][0], \
3390 &mips_reg_names[68][0], \
3391 &mips_reg_names[69][0], \
3392 &mips_reg_names[70][0], \
3393 &mips_reg_names[71][0], \
3394 &mips_reg_names[72][0], \
3395 &mips_reg_names[73][0], \
3396 &mips_reg_names[74][0], \
3397 &mips_reg_names[75][0], \
3398 &mips_reg_names[76][0], \
3399 &mips_reg_names[77][0], \
3400 &mips_reg_names[78][0], \
3401 &mips_reg_names[79][0], \
3402 &mips_reg_names[80][0], \
3403 &mips_reg_names[81][0], \
3404 &mips_reg_names[82][0], \
3405 &mips_reg_names[83][0], \
3406 &mips_reg_names[84][0], \
3407 &mips_reg_names[85][0], \
3408 &mips_reg_names[86][0], \
3409 &mips_reg_names[87][0], \
3410 &mips_reg_names[88][0], \
3411 &mips_reg_names[89][0], \
3412 &mips_reg_names[90][0], \
3413 &mips_reg_names[91][0], \
3414 &mips_reg_names[92][0], \
3415 &mips_reg_names[93][0], \
3416 &mips_reg_names[94][0], \
3417 &mips_reg_names[95][0], \
3418 &mips_reg_names[96][0], \
3419 &mips_reg_names[97][0], \
3420 &mips_reg_names[98][0], \
3421 &mips_reg_names[99][0], \
3422 &mips_reg_names[100][0], \
3423 &mips_reg_names[101][0], \
3424 &mips_reg_names[102][0], \
3425 &mips_reg_names[103][0], \
3426 &mips_reg_names[104][0], \
3427 &mips_reg_names[105][0], \
3428 &mips_reg_names[106][0], \
3429 &mips_reg_names[107][0], \
3430 &mips_reg_names[108][0], \
3431 &mips_reg_names[109][0], \
3432 &mips_reg_names[110][0], \
3433 &mips_reg_names[111][0], \
3434 &mips_reg_names[112][0], \
3435 &mips_reg_names[113][0], \
3436 &mips_reg_names[114][0], \
3437 &mips_reg_names[115][0], \
3438 &mips_reg_names[116][0], \
3439 &mips_reg_names[117][0], \
3440 &mips_reg_names[118][0], \
3441 &mips_reg_names[119][0], \
3442 &mips_reg_names[120][0], \
3443 &mips_reg_names[121][0], \
3444 &mips_reg_names[122][0], \
3445 &mips_reg_names[123][0], \
3446 &mips_reg_names[124][0], \
3447 &mips_reg_names[125][0], \
3448 &mips_reg_names[126][0], \
3449 &mips_reg_names[127][0], \
3450 &mips_reg_names[128][0], \
3451 &mips_reg_names[129][0], \
3452 &mips_reg_names[130][0], \
3453 &mips_reg_names[131][0], \
3454 &mips_reg_names[132][0], \
3455 &mips_reg_names[133][0], \
3456 &mips_reg_names[134][0], \
3457 &mips_reg_names[135][0], \
3458 &mips_reg_names[136][0], \
3459 &mips_reg_names[137][0], \
3460 &mips_reg_names[138][0], \
3461 &mips_reg_names[139][0], \
3462 &mips_reg_names[140][0], \
3463 &mips_reg_names[141][0], \
3464 &mips_reg_names[142][0], \
3465 &mips_reg_names[143][0], \
3466 &mips_reg_names[144][0], \
3467 &mips_reg_names[145][0], \
3468 &mips_reg_names[146][0], \
3469 &mips_reg_names[147][0], \
3470 &mips_reg_names[148][0], \
3471 &mips_reg_names[149][0], \
3472 &mips_reg_names[150][0], \
3473 &mips_reg_names[151][0], \
3474 &mips_reg_names[152][0], \
3475 &mips_reg_names[153][0], \
3476 &mips_reg_names[154][0], \
3477 &mips_reg_names[155][0], \
3478 &mips_reg_names[156][0], \
3479 &mips_reg_names[157][0], \
3480 &mips_reg_names[158][0], \
3481 &mips_reg_names[159][0], \
3482 &mips_reg_names[160][0], \
3483 &mips_reg_names[161][0], \
3484 &mips_reg_names[162][0], \
3485 &mips_reg_names[163][0], \
3486 &mips_reg_names[164][0], \
3487 &mips_reg_names[165][0], \
3488 &mips_reg_names[166][0], \
3489 &mips_reg_names[167][0], \
3490 &mips_reg_names[168][0], \
3491 &mips_reg_names[169][0], \
3492 &mips_reg_names[170][0], \
3493 &mips_reg_names[171][0], \
3494 &mips_reg_names[172][0], \
3495 &mips_reg_names[173][0], \
3496 &mips_reg_names[174][0], \
3497 &mips_reg_names[175][0] \
3500 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3501 So define this for it. */
3502 #define DEBUG_REGISTER_NAMES \
3504 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3505 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3506 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3507 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3508 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3509 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3510 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3511 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3512 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3513 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3514 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3515 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3516 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3517 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3518 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3519 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3520 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3521 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3522 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3523 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3524 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3525 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3528 /* If defined, a C initializer for an array of structures
3529 containing a name and a register number. This macro defines
3530 additional names for hard registers, thus allowing the `asm'
3531 option in declarations to refer to registers using alternate
3534 We define both names for the integer registers here. */
3536 #define ADDITIONAL_REGISTER_NAMES \
3538 { "$0", 0 + GP_REG_FIRST }, \
3539 { "$1", 1 + GP_REG_FIRST }, \
3540 { "$2", 2 + GP_REG_FIRST }, \
3541 { "$3", 3 + GP_REG_FIRST }, \
3542 { "$4", 4 + GP_REG_FIRST }, \
3543 { "$5", 5 + GP_REG_FIRST }, \
3544 { "$6", 6 + GP_REG_FIRST }, \
3545 { "$7", 7 + GP_REG_FIRST }, \
3546 { "$8", 8 + GP_REG_FIRST }, \
3547 { "$9", 9 + GP_REG_FIRST }, \
3548 { "$10", 10 + GP_REG_FIRST }, \
3549 { "$11", 11 + GP_REG_FIRST }, \
3550 { "$12", 12 + GP_REG_FIRST }, \
3551 { "$13", 13 + GP_REG_FIRST }, \
3552 { "$14", 14 + GP_REG_FIRST }, \
3553 { "$15", 15 + GP_REG_FIRST }, \
3554 { "$16", 16 + GP_REG_FIRST }, \
3555 { "$17", 17 + GP_REG_FIRST }, \
3556 { "$18", 18 + GP_REG_FIRST }, \
3557 { "$19", 19 + GP_REG_FIRST }, \
3558 { "$20", 20 + GP_REG_FIRST }, \
3559 { "$21", 21 + GP_REG_FIRST }, \
3560 { "$22", 22 + GP_REG_FIRST }, \
3561 { "$23", 23 + GP_REG_FIRST }, \
3562 { "$24", 24 + GP_REG_FIRST }, \
3563 { "$25", 25 + GP_REG_FIRST }, \
3564 { "$26", 26 + GP_REG_FIRST }, \
3565 { "$27", 27 + GP_REG_FIRST }, \
3566 { "$28", 28 + GP_REG_FIRST }, \
3567 { "$29", 29 + GP_REG_FIRST }, \
3568 { "$30", 30 + GP_REG_FIRST }, \
3569 { "$31", 31 + GP_REG_FIRST }, \
3570 { "$sp", 29 + GP_REG_FIRST }, \
3571 { "$fp", 30 + GP_REG_FIRST }, \
3572 { "at", 1 + GP_REG_FIRST }, \
3573 { "v0", 2 + GP_REG_FIRST }, \
3574 { "v1", 3 + GP_REG_FIRST }, \
3575 { "a0", 4 + GP_REG_FIRST }, \
3576 { "a1", 5 + GP_REG_FIRST }, \
3577 { "a2", 6 + GP_REG_FIRST }, \
3578 { "a3", 7 + GP_REG_FIRST }, \
3579 { "t0", 8 + GP_REG_FIRST }, \
3580 { "t1", 9 + GP_REG_FIRST }, \
3581 { "t2", 10 + GP_REG_FIRST }, \
3582 { "t3", 11 + GP_REG_FIRST }, \
3583 { "t4", 12 + GP_REG_FIRST }, \
3584 { "t5", 13 + GP_REG_FIRST }, \
3585 { "t6", 14 + GP_REG_FIRST }, \
3586 { "t7", 15 + GP_REG_FIRST }, \
3587 { "s0", 16 + GP_REG_FIRST }, \
3588 { "s1", 17 + GP_REG_FIRST }, \
3589 { "s2", 18 + GP_REG_FIRST }, \
3590 { "s3", 19 + GP_REG_FIRST }, \
3591 { "s4", 20 + GP_REG_FIRST }, \
3592 { "s5", 21 + GP_REG_FIRST }, \
3593 { "s6", 22 + GP_REG_FIRST }, \
3594 { "s7", 23 + GP_REG_FIRST }, \
3595 { "t8", 24 + GP_REG_FIRST }, \
3596 { "t9", 25 + GP_REG_FIRST }, \
3597 { "k0", 26 + GP_REG_FIRST }, \
3598 { "k1", 27 + GP_REG_FIRST }, \
3599 { "gp", 28 + GP_REG_FIRST }, \
3600 { "sp", 29 + GP_REG_FIRST }, \
3601 { "fp", 30 + GP_REG_FIRST }, \
3602 { "ra", 31 + GP_REG_FIRST }, \
3603 { "$sp", 29 + GP_REG_FIRST }, \
3604 { "$fp", 30 + GP_REG_FIRST } \
3605 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3608 /* This is meant to be redefined in the host dependent files. It is a
3609 set of alternative names and regnums for mips coprocessors. */
3611 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3613 /* A C compound statement to output to stdio stream STREAM the
3614 assembler syntax for an instruction operand X. X is an RTL
3617 CODE is a value that can be used to specify one of several ways
3618 of printing the operand. It is used when identical operands
3619 must be printed differently depending on the context. CODE
3620 comes from the `%' specification that was used to request
3621 printing of the operand. If the specification was just `%DIGIT'
3622 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3623 is the ASCII code for LTR.
3625 If X is a register, this macro should print the register's name.
3626 The names can be found in an array `reg_names' whose type is
3627 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3629 When the machine description has a specification `%PUNCT' (a `%'
3630 followed by a punctuation character), this macro is called with
3631 a null pointer for X and the punctuation character for CODE.
3633 See mips.c for the MIPS specific codes. */
3635 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3637 /* A C expression which evaluates to true if CODE is a valid
3638 punctuation character for use in the `PRINT_OPERAND' macro. If
3639 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3640 punctuation characters (except for the standard one, `%') are
3641 used in this way. */
3643 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3645 /* A C compound statement to output to stdio stream STREAM the
3646 assembler syntax for an instruction operand that is a memory
3647 reference whose address is ADDR. ADDR is an RTL expression. */
3649 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3652 /* A C statement, to be executed after all slot-filler instructions
3653 have been output. If necessary, call `dbr_sequence_length' to
3654 determine the number of slots filled in a sequence (zero if not
3655 currently outputting a sequence), to decide how many no-ops to
3656 output, or whatever.
3658 Don't define this macro if it has nothing to do, but it is
3659 helpful in reading assembly output if the extent of the delay
3660 sequence is made explicit (e.g. with white space).
3662 Note that output routines for instructions with delay slots must
3663 be prepared to deal with not being output as part of a sequence
3664 (i.e. when the scheduling pass is not run, or when no slot
3665 fillers could be found.) The variable `final_sequence' is null
3666 when not processing a sequence, otherwise it contains the
3667 `sequence' rtx being output. */
3669 #define DBR_OUTPUT_SEQEND(STREAM) \
3672 if (set_nomacro > 0 && --set_nomacro == 0) \
3673 fputs ("\t.set\tmacro\n", STREAM); \
3675 if (set_noreorder > 0 && --set_noreorder == 0) \
3676 fputs ("\t.set\treorder\n", STREAM); \
3678 fputs ("\n", STREAM); \
3683 /* How to tell the debugger about changes of source files. Note, the
3684 mips ECOFF format cannot deal with changes of files inside of
3685 functions, which means the output of parser generators like bison
3686 is generally not debuggable without using the -l switch. Lose,
3687 lose, lose. Silicon graphics seems to want all .file's hardwired
3690 #ifndef SET_FILE_NUMBER
3691 #define SET_FILE_NUMBER() ++num_source_filenames
3694 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3695 mips_output_filename (STREAM, NAME)
3697 /* This is defined so that it can be overridden in iris6.h. */
3698 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3701 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3702 output_quoted_string (STREAM, NAME); \
3703 fputs ("\n", STREAM); \
3707 /* This is how to output a note the debugger telling it the line number
3708 to which the following sequence of instructions corresponds.
3709 Silicon graphics puts a label after each .loc. */
3711 #ifndef LABEL_AFTER_LOC
3712 #define LABEL_AFTER_LOC(STREAM)
3715 #ifndef ASM_OUTPUT_SOURCE_LINE
3716 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3717 mips_output_lineno (STREAM, LINE)
3720 /* The MIPS implementation uses some labels for its own purpose. The
3721 following lists what labels are created, and are all formed by the
3722 pattern $L[a-z].*. The machine independent portion of GCC creates
3723 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3725 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3726 $Lb[0-9]+ Begin blocks for MIPS debug support
3727 $Lc[0-9]+ Label for use in s<xx> operation.
3728 $Le[0-9]+ End blocks for MIPS debug support */
3730 /* A C statement (sans semicolon) to output to the stdio stream
3731 STREAM any text necessary for declaring the name NAME of an
3732 initialized variable which is being defined. This macro must
3733 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3734 The argument DECL is the `VAR_DECL' tree node representing the
3737 If this macro is not defined, then the variable name is defined
3738 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3740 #undef ASM_DECLARE_OBJECT_NAME
3741 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3744 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3748 /* Globalizing directive for a label. */
3749 #define GLOBAL_ASM_OP "\t.globl\t"
3751 /* This says how to define a global common symbol. */
3753 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3755 /* If the target wants uninitialized const declarations in \
3756 .rdata then don't put them in .comm */ \
3757 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3758 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3759 && (DECL_INITIAL (DECL) == 0 \
3760 || DECL_INITIAL (DECL) == error_mark_node)) \
3762 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3763 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3765 readonly_data_section (); \
3766 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3767 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3771 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3776 /* This says how to define a local common symbol (ie, not visible to
3779 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3780 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3783 /* This says how to output an external. It would be possible not to
3784 output anything and let undefined symbol become external. However
3785 the assembler uses length information on externals to allocate in
3786 data/sdata bss/sbss, thereby saving exec time. */
3788 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3789 mips_output_external(STREAM,DECL,NAME)
3792 /* This is how to declare a function name. The actual work of
3793 emitting the label is moved to function_prologue, so that we can
3794 get the line number correctly emitted before the .ent directive,
3795 and after any .file directives. Define as empty so that the function
3796 is not declared before the .ent directive elsewhere. */
3798 #undef ASM_DECLARE_FUNCTION_NAME
3799 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3801 /* This is how to store into the string LABEL
3802 the symbol_ref name of an internal numbered label where
3803 PREFIX is the class of label and NUM is the number within the class.
3804 This is suitable for output with `assemble_name'. */
3806 #undef ASM_GENERATE_INTERNAL_LABEL
3807 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3808 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3810 /* This is how to output an element of a case-vector that is absolute. */
3812 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3813 fprintf (STREAM, "\t%s\t%sL%d\n", \
3814 ptr_mode == DImode ? ".dword" : ".word", \
3815 LOCAL_LABEL_PREFIX, \
3818 /* This is how to output an element of a case-vector that is relative.
3819 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3820 TARGET_EMBEDDED_PIC). */
3822 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3824 if (TARGET_MIPS16) \
3825 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3826 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3827 else if (TARGET_EMBEDDED_PIC) \
3828 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3829 ptr_mode == DImode ? ".dword" : ".word", \
3830 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3831 else if (TARGET_GPWORD) \
3832 fprintf (STREAM, "\t%s\t%sL%d\n", \
3833 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3834 LOCAL_LABEL_PREFIX, VALUE); \
3836 fprintf (STREAM, "\t%s\t%sL%d\n", \
3837 ptr_mode == DImode ? ".dword" : ".word", \
3838 LOCAL_LABEL_PREFIX, VALUE); \
3841 /* When generating embedded PIC or mips16 code we want to put the jump
3842 table in the .text section. In all other cases, we want to put the
3843 jump table in the .rdata section. Unfortunately, we can't use
3844 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3845 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3846 section if appropriate. */
3847 #undef ASM_OUTPUT_CASE_LABEL
3848 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3850 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3851 function_section (current_function_decl); \
3852 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3855 /* This is how to output an assembler line
3856 that says to advance the location counter
3857 to a multiple of 2**LOG bytes. */
3859 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3860 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3862 /* This is how to output an assembler line to advance the location
3863 counter by SIZE bytes. */
3865 #undef ASM_OUTPUT_SKIP
3866 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3867 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3869 /* This is how to output a string. */
3870 #undef ASM_OUTPUT_ASCII
3871 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3872 mips_output_ascii (STREAM, STRING, LEN)
3874 /* Output #ident as a in the read-only data section. */
3875 #undef ASM_OUTPUT_IDENT
3876 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3878 const char *p = STRING; \
3879 int size = strlen (p) + 1; \
3880 readonly_data_section (); \
3881 assemble_string (p, size); \
3884 /* Default to -G 8 */
3885 #ifndef MIPS_DEFAULT_GVALUE
3886 #define MIPS_DEFAULT_GVALUE 8
3889 /* Define the strings to put out for each section in the object file. */
3890 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3891 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3892 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3894 #undef READONLY_DATA_SECTION_ASM_OP
3895 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3897 #define SMALL_DATA_SECTION sdata_section
3899 /* What other sections we support other than the normal .data/.text. */
3901 #undef EXTRA_SECTIONS
3902 #define EXTRA_SECTIONS in_sdata
3904 /* Define the additional functions to select our additional sections. */
3906 /* on the MIPS it is not a good idea to put constants in the text
3907 section, since this defeats the sdata/data mechanism. This is
3908 especially true when -O is used. In this case an effort is made to
3909 address with faster (gp) register relative addressing, which can
3910 only get at sdata and sbss items (there is no stext !!) However,
3911 if the constant is too large for sdata, and it's readonly, it
3912 will go into the .rdata section. */
3914 #undef EXTRA_SECTION_FUNCTIONS
3915 #define EXTRA_SECTION_FUNCTIONS \
3919 if (in_section != in_sdata) \
3921 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3922 in_section = in_sdata; \
3926 /* Given a decl node or constant node, choose the section to output it in
3927 and select that section. */
3929 #undef TARGET_ASM_SELECT_SECTION
3930 #define TARGET_ASM_SELECT_SECTION mips_select_section
3932 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3935 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3936 TARGET_64BIT ? "dsubu" : "subu", \
3937 reg_names[STACK_POINTER_REGNUM], \
3938 reg_names[STACK_POINTER_REGNUM], \
3939 TARGET_64BIT ? "sd" : "sw", \
3941 reg_names[STACK_POINTER_REGNUM]); \
3945 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3948 if (! set_noreorder) \
3949 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3951 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3952 TARGET_64BIT ? "ld" : "lw", \
3954 reg_names[STACK_POINTER_REGNUM], \
3955 TARGET_64BIT ? "daddu" : "addu", \
3956 reg_names[STACK_POINTER_REGNUM], \
3957 reg_names[STACK_POINTER_REGNUM]); \
3959 if (! set_noreorder) \
3960 fprintf (STREAM, "\t.set\treorder\n"); \
3964 /* How to start an assembler comment.
3965 The leading space is important (the mips native assembler requires it). */
3966 #ifndef ASM_COMMENT_START
3967 #define ASM_COMMENT_START " #"
3971 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3972 and mips-tdump.c to print them out.
3974 These must match the corresponding definitions in gdb/mipsread.c.
3975 Unfortunately, gcc and gdb do not currently share any directories. */
3977 #define CODE_MASK 0x8F300
3978 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3979 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3980 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3983 /* Default definitions for size_t and ptrdiff_t. We must override the
3984 definitions from ../svr4.h on mips-*-linux-gnu. */
3987 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3990 #ifndef PTRDIFF_TYPE
3991 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3994 /* See mips_expand_prologue's use of loadgp for when this should be
3997 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3998 && mips_abi != ABI_32 \
3999 && mips_abi != ABI_O64)
4001 /* We need to use a special set of functions to handle hard floating
4002 point code in mips16 mode. */
4004 #ifndef INIT_SUBTARGET_OPTABS
4005 #define INIT_SUBTARGET_OPTABS
4008 #define INIT_TARGET_OPTABS \
4011 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4012 INIT_SUBTARGET_OPTABS; \
4015 add_optab->handlers[(int) SFmode].libfunc = \
4016 init_one_libfunc ("__mips16_addsf3"); \
4017 sub_optab->handlers[(int) SFmode].libfunc = \
4018 init_one_libfunc ("__mips16_subsf3"); \
4019 smul_optab->handlers[(int) SFmode].libfunc = \
4020 init_one_libfunc ("__mips16_mulsf3"); \
4021 sdiv_optab->handlers[(int) SFmode].libfunc = \
4022 init_one_libfunc ("__mips16_divsf3"); \
4024 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4025 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4026 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4027 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4028 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4029 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4031 floatsisf_libfunc = \
4032 init_one_libfunc ("__mips16_floatsisf"); \
4034 init_one_libfunc ("__mips16_fixsfsi"); \
4036 if (TARGET_DOUBLE_FLOAT) \
4038 add_optab->handlers[(int) DFmode].libfunc = \
4039 init_one_libfunc ("__mips16_adddf3"); \
4040 sub_optab->handlers[(int) DFmode].libfunc = \
4041 init_one_libfunc ("__mips16_subdf3"); \
4042 smul_optab->handlers[(int) DFmode].libfunc = \
4043 init_one_libfunc ("__mips16_muldf3"); \
4044 sdiv_optab->handlers[(int) DFmode].libfunc = \
4045 init_one_libfunc ("__mips16_divdf3"); \
4047 extendsfdf2_libfunc = \
4048 init_one_libfunc ("__mips16_extendsfdf2"); \
4049 truncdfsf2_libfunc = \
4050 init_one_libfunc ("__mips16_truncdfsf2"); \
4053 init_one_libfunc ("__mips16_eqdf2"); \
4055 init_one_libfunc ("__mips16_nedf2"); \
4057 init_one_libfunc ("__mips16_gtdf2"); \
4059 init_one_libfunc ("__mips16_gedf2"); \
4061 init_one_libfunc ("__mips16_ltdf2"); \
4063 init_one_libfunc ("__mips16_ledf2"); \
4065 floatsidf_libfunc = \
4066 init_one_libfunc ("__mips16_floatsidf"); \
4068 init_one_libfunc ("__mips16_fixdfsi"); \
4074 #define DFMODE_NAN \
4075 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4076 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4077 #define SFMODE_NAN \
4078 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4079 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4081 /* Generate calls to memcpy, etc., not bcopy, etc. */
4082 #define TARGET_MEM_FUNCTIONS
4085 /* Since the bits of the _init and _fini function is spread across
4086 many object files, each potentially with its own GP, we must assume
4087 we need to load our GP. We don't preserve $gp or $ra, since each
4088 init/fini chunk is supposed to initialize $gp, and crti/crtn
4089 already take care of preserving $ra and, when appropriate, $gp. */
4090 #if _MIPS_SIM == _MIPS_SIM_ABI32
4091 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4092 asm (SECTION_OP "\n\
4098 jal " USER_LABEL_PREFIX #FUNC "\n\
4099 " TEXT_SECTION_ASM_OP);
4100 #endif /* Switch to #elif when we're no longer limited by K&R C. */
4101 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4102 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4103 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4104 asm (SECTION_OP "\n\
4109 .cpsetup $31, $2, 1b\n\
4110 jal " USER_LABEL_PREFIX #FUNC "\n\
4111 " TEXT_SECTION_ASM_OP);