1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
83 /* Recast the cpu class to be the cpu attribute. */
84 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
86 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
87 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
88 to work on a 64 bit machine. */
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 /* Information about one recognized processor. Defined here for the
116 benefit of TARGET_CPU_CPP_BUILTINS. */
117 struct mips_cpu_info {
118 /* The 'canonical' name of the processor as far as GCC is concerned.
119 It's typically a manufacturer's prefix followed by a numerical
120 designation. It should be lower case. */
123 /* The internal processor number that most closely matches this
124 entry. Several processors can have the same value, if there's no
125 difference between them from GCC's point of view. */
126 enum processor_type cpu;
128 /* The ISA level that the processor implements. */
132 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
133 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
134 extern const char *current_function_file; /* filename current function is in */
135 extern int num_source_filenames; /* current .file # */
136 extern int inside_function; /* != 0 if inside of a function */
137 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
138 extern int file_in_function_warning; /* warning given about .file in func */
139 extern int sdb_label_count; /* block start/end next label # */
140 extern int sdb_begin_function_line; /* Starting Line of current function */
141 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
142 extern int g_switch_value; /* value of the -G xx switch */
143 extern int g_switch_set; /* whether -G xx was passed. */
144 extern int sym_lineno; /* sgi next label # for each stmt */
145 extern int set_noreorder; /* # of nested .set noreorder's */
146 extern int set_nomacro; /* # of nested .set nomacro's */
147 extern int set_noat; /* # of nested .set noat's */
148 extern int set_volatile; /* # of nested .set volatile's */
149 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
150 extern int mips_dbx_regno[]; /* Map register # to debug register # */
151 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
152 extern enum cmp_type branch_type; /* what type of branch to use */
153 extern enum processor_type mips_arch; /* which cpu to codegen for */
154 extern enum processor_type mips_tune; /* which cpu to schedule for */
155 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
156 extern int mips_isa; /* architectural level */
157 extern int mips16; /* whether generating mips16 code */
158 extern int mips16_hard_float; /* mips16 without -msoft-float */
159 extern int mips_entry; /* generate entry/exit for mips16 */
160 extern const char *mips_arch_string; /* for -march=<xxx> */
161 extern const char *mips_tune_string; /* for -mtune=<xxx> */
162 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
163 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
164 extern const char *mips_entry_string; /* for -mentry */
165 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
166 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
167 extern int dslots_load_total; /* total # load related delay slots */
168 extern int dslots_load_filled; /* # filled load delay slots */
169 extern int dslots_jump_total; /* total # jump related delay slots */
170 extern int dslots_jump_filled; /* # filled jump delay slots */
171 extern int dslots_number_nops; /* # of nops needed by previous insn */
172 extern int num_refs[3]; /* # 1/2/3 word references */
173 extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
174 extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
175 extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
176 extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
177 extern int mips_string_length; /* length of strings for mips16 */
178 extern const struct mips_cpu_info mips_cpu_info_table[];
179 extern const struct mips_cpu_info *mips_arch_info;
180 extern const struct mips_cpu_info *mips_tune_info;
182 /* Functions to change what output section we are using. */
183 extern void sdata_section PARAMS ((void));
184 extern void sbss_section PARAMS ((void));
186 /* Macros to silence warnings about numbers being signed in traditional
187 C and unsigned in ISO C when compiled on 32-bit hosts. */
189 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
190 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
191 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
194 /* Run-time compilation parameters selecting different hardware subsets. */
196 /* Macros used in the machine description to test the flags. */
198 /* Bits for real switches */
199 #define MASK_INT64 0x00000001 /* ints are 64 bits */
200 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
201 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
202 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
203 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
204 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
205 #define MASK_STATS 0x00000040 /* print statistics to stderr */
206 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
207 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
208 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
209 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
210 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
211 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
212 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
213 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
214 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
215 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
216 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
217 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
218 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
219 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
220 #define MASK_NO_CHECK_ZERO_DIV \
221 0x00200000 /* divide by zero checking */
222 #define MASK_CHECK_RANGE_DIV \
223 0x00400000 /* divide result range checking */
224 #define MASK_UNINIT_CONST_IN_RODATA \
225 0x00800000 /* Store uninitialized
227 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
228 multiply-add operations. */
229 #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
231 #define MASK_EXPLICIT_RELOCS 0x04000000 /* Use relocation operators. */
233 /* Debug switches, not documented */
234 #define MASK_DEBUG 0 /* unused */
235 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
236 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
237 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
238 #define MASK_DEBUG_D 0 /* don't do define_split's */
239 #define MASK_DEBUG_E 0 /* function_arg debug */
240 #define MASK_DEBUG_F 0 /* ??? */
241 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
242 #define MASK_DEBUG_I 0 /* unused */
244 /* Dummy switches used only in specs */
245 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
247 /* r4000 64 bit sizes */
248 #define TARGET_INT64 (target_flags & MASK_INT64)
249 #define TARGET_LONG64 (target_flags & MASK_LONG64)
250 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
251 #define TARGET_64BIT (target_flags & MASK_64BIT)
253 /* Mips vs. GNU linker */
254 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
256 /* Mips vs. GNU assembler */
257 #define TARGET_GAS (target_flags & MASK_GAS)
258 #define TARGET_MIPS_AS (!TARGET_GAS)
261 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
262 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
263 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
264 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
265 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
266 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
267 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
268 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
269 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
271 /* Reg. Naming in .s ($21 vs. $a0) */
272 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
274 /* Optimize for Sdata/Sbss */
275 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
277 /* print program statistics */
278 #define TARGET_STATS (target_flags & MASK_STATS)
280 /* call memcpy instead of inline code */
281 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
283 /* .abicalls, etc from Pyramid V.4 */
284 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
286 /* software floating point */
287 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
288 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
290 /* always call through a register */
291 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
293 /* generate embedded PIC code;
295 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
297 /* for embedded systems, optimize for
298 reduced RAM space instead of for
300 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
302 /* always store uninitialized const
303 variables in rodata, requires
304 TARGET_EMBEDDED_DATA. */
305 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
307 /* generate big endian code. */
308 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
310 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
311 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
313 #define TARGET_MAD (target_flags & MASK_MAD)
315 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
317 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
319 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
320 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
322 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
325 /* True if we should use NewABI-style relocation operators for
326 symbolic addresses. This is never true for mips16 code,
327 which has its own conventions. */
329 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
332 /* This is true if we must enable the assembly language file switching
335 #define TARGET_FILE_SWITCHING \
336 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
338 /* True if the call patterns should be split into a jalr followed by
339 an instruction to restore $gp. This is only ever true for SVR4 PIC,
340 in which $gp is call-clobbered. It is only safe to split the load
341 from the call when every use of $gp is explicit. */
343 #define TARGET_SPLIT_CALLS \
344 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
346 /* True if we can optimize sibling calls. For simplicity, we only
347 handle cases in which call_insn_operand will reject invalid
348 sibcall addresses. There are two cases in which this isn't true:
350 - TARGET_MIPS16. call_insn_operand accepts constant addresses
351 but there is no direct jump instruction. It isn't worth
352 using sibling calls in this case anyway; they would usually
353 be longer than normal calls.
355 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
356 accepts global constants, but "jr $25" is the only allowed
359 #define TARGET_SIBCALLS \
360 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
362 /* True if .gpword or .gpdword should be used for switch tables.
363 Not all SGI assemblers support this. */
365 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
368 /* We must disable the function end stabs when doing the file switching trick,
369 because the Lscope stabs end up in the wrong place, making it impossible
370 to debug the resulting code. */
371 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
373 /* Generate mips16 code */
374 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
376 /* Generic ISA defines. */
377 #define ISA_MIPS1 (mips_isa == 1)
378 #define ISA_MIPS2 (mips_isa == 2)
379 #define ISA_MIPS3 (mips_isa == 3)
380 #define ISA_MIPS4 (mips_isa == 4)
381 #define ISA_MIPS32 (mips_isa == 32)
382 #define ISA_MIPS32R2 (mips_isa == 33)
383 #define ISA_MIPS64 (mips_isa == 64)
385 /* Architecture target defines. */
386 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
387 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
388 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
389 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
390 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
391 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
392 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
393 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
394 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
395 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
396 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
398 /* Scheduling target defines. */
399 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
400 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
401 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
402 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
403 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
404 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
405 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
406 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
407 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
409 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
411 /* Define preprocessor macros for the -march and -mtune options.
412 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
413 processor. If INFO's canonical name is "foo", define PREFIX to
414 be "foo", and define an additional macro PREFIX_FOO. */
415 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
420 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
421 for (p = macro; *p != 0; p++) \
424 builtin_define (macro); \
425 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
430 /* Target CPU builtins. */
431 #define TARGET_CPU_CPP_BUILTINS() \
434 builtin_assert ("cpu=mips"); \
435 builtin_define ("__mips__"); \
436 builtin_define ("_mips"); \
438 /* We do this here because __mips is defined below \
439 and so we can't use builtin_define_std. */ \
441 builtin_define ("mips"); \
443 /* Treat _R3000 and _R4000 like register-size defines, \
444 which is how they've historically been used. */ \
447 builtin_define ("__mips64"); \
448 builtin_define_std ("R4000"); \
449 builtin_define ("_R4000"); \
453 builtin_define_std ("R3000"); \
454 builtin_define ("_R3000"); \
456 if (TARGET_FLOAT64) \
457 builtin_define ("__mips_fpr=64"); \
459 builtin_define ("__mips_fpr=32"); \
462 builtin_define ("__mips16"); \
464 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
465 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
469 builtin_define ("__mips=1"); \
470 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
472 else if (ISA_MIPS2) \
474 builtin_define ("__mips=2"); \
475 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
477 else if (ISA_MIPS3) \
479 builtin_define ("__mips=3"); \
480 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
482 else if (ISA_MIPS4) \
484 builtin_define ("__mips=4"); \
485 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
487 else if (ISA_MIPS32) \
489 builtin_define ("__mips=32"); \
490 builtin_define ("__mips_isa_rev=1"); \
491 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
493 else if (ISA_MIPS32R2) \
495 builtin_define ("__mips=32"); \
496 builtin_define ("__mips_isa_rev=2"); \
497 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
499 else if (ISA_MIPS64) \
501 builtin_define ("__mips=64"); \
502 builtin_define ("__mips_isa_rev=1"); \
503 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
506 if (TARGET_HARD_FLOAT) \
507 builtin_define ("__mips_hard_float"); \
508 else if (TARGET_SOFT_FLOAT) \
509 builtin_define ("__mips_soft_float"); \
511 if (TARGET_SINGLE_FLOAT) \
512 builtin_define ("__mips_single_float"); \
514 if (TARGET_BIG_ENDIAN) \
516 builtin_define_std ("MIPSEB"); \
517 builtin_define ("_MIPSEB"); \
521 builtin_define_std ("MIPSEL"); \
522 builtin_define ("_MIPSEL"); \
525 /* Macros dependent on the C dialect. */ \
526 if (preprocessing_asm_p ()) \
528 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
529 builtin_define ("_LANGUAGE_ASSEMBLY"); \
531 else if (c_language == clk_c) \
533 builtin_define_std ("LANGUAGE_C"); \
534 builtin_define ("_LANGUAGE_C"); \
536 else if (c_language == clk_cplusplus) \
538 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
539 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
540 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
544 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
545 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
546 /* Bizzare, but needed at least for Irix. */ \
547 builtin_define_std ("LANGUAGE_C"); \
548 builtin_define ("_LANGUAGE_C"); \
551 if (mips_abi == ABI_EABI) \
552 builtin_define ("__mips_eabi"); \
558 /* Macro to define tables used to set the flags.
559 This is a list in braces of pairs in braces,
560 each pair being { "NAME", VALUE }
561 where VALUE is the bits to set or minus the bits to clear.
562 An empty string NAME is used to identify the default VALUE. */
564 #define TARGET_SWITCHES \
566 SUBTARGET_TARGET_SWITCHES \
567 {"int64", MASK_INT64 | MASK_LONG64, \
568 N_("Use 64-bit int type")}, \
569 {"long64", MASK_LONG64, \
570 N_("Use 64-bit long type")}, \
571 {"long32", -(MASK_LONG64 | MASK_INT64), \
572 N_("Use 32-bit long type")}, \
573 {"split-addresses", MASK_SPLIT_ADDR, \
574 N_("Optimize lui/addiu address loads")}, \
575 {"no-split-addresses", -MASK_SPLIT_ADDR, \
576 N_("Don't optimize lui/addiu address loads")}, \
577 {"mips-as", -MASK_GAS, \
578 N_("Use MIPS as")}, \
581 {"rnames", MASK_NAME_REGS, \
582 N_("Use symbolic register names")}, \
583 {"no-rnames", -MASK_NAME_REGS, \
584 N_("Don't use symbolic register names")}, \
585 {"gpOPT", MASK_GPOPT, \
586 N_("Use GP relative sdata/sbss sections")}, \
587 {"gpopt", MASK_GPOPT, \
588 N_("Use GP relative sdata/sbss sections")}, \
589 {"no-gpOPT", -MASK_GPOPT, \
590 N_("Don't use GP relative sdata/sbss sections")}, \
591 {"no-gpopt", -MASK_GPOPT, \
592 N_("Don't use GP relative sdata/sbss sections")}, \
593 {"stats", MASK_STATS, \
594 N_("Output compiler statistics")}, \
595 {"no-stats", -MASK_STATS, \
596 N_("Don't output compiler statistics")}, \
597 {"memcpy", MASK_MEMCPY, \
598 N_("Don't optimize block moves")}, \
599 {"no-memcpy", -MASK_MEMCPY, \
600 N_("Optimize block moves")}, \
601 {"mips-tfile", MASK_MIPS_TFILE, \
602 N_("Use mips-tfile asm postpass")}, \
603 {"no-mips-tfile", -MASK_MIPS_TFILE, \
604 N_("Don't use mips-tfile asm postpass")}, \
605 {"soft-float", MASK_SOFT_FLOAT, \
606 N_("Use software floating point")}, \
607 {"hard-float", -MASK_SOFT_FLOAT, \
608 N_("Use hardware floating point")}, \
609 {"fp64", MASK_FLOAT64, \
610 N_("Use 64-bit FP registers")}, \
611 {"fp32", -MASK_FLOAT64, \
612 N_("Use 32-bit FP registers")}, \
613 {"gp64", MASK_64BIT, \
614 N_("Use 64-bit general registers")}, \
615 {"gp32", -MASK_64BIT, \
616 N_("Use 32-bit general registers")}, \
617 {"abicalls", MASK_ABICALLS, \
618 N_("Use Irix PIC")}, \
619 {"no-abicalls", -MASK_ABICALLS, \
620 N_("Don't use Irix PIC")}, \
621 {"long-calls", MASK_LONG_CALLS, \
622 N_("Use indirect calls")}, \
623 {"no-long-calls", -MASK_LONG_CALLS, \
624 N_("Don't use indirect calls")}, \
625 {"embedded-pic", MASK_EMBEDDED_PIC, \
626 N_("Use embedded PIC")}, \
627 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
628 N_("Don't use embedded PIC")}, \
629 {"embedded-data", MASK_EMBEDDED_DATA, \
630 N_("Use ROM instead of RAM")}, \
631 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
632 N_("Don't use ROM instead of RAM")}, \
633 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
634 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
635 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
636 N_("Don't put uninitialized constants in ROM")}, \
637 {"eb", MASK_BIG_ENDIAN, \
638 N_("Use big-endian byte order")}, \
639 {"el", -MASK_BIG_ENDIAN, \
640 N_("Use little-endian byte order")}, \
641 {"single-float", MASK_SINGLE_FLOAT, \
642 N_("Use single (32-bit) FP only")}, \
643 {"double-float", -MASK_SINGLE_FLOAT, \
644 N_("Don't use single (32-bit) FP only")}, \
646 N_("Use multiply accumulate")}, \
647 {"no-mad", -MASK_MAD, \
648 N_("Don't use multiply accumulate")}, \
649 {"no-fused-madd", MASK_NO_FUSED_MADD, \
650 N_("Don't generate fused multiply/add instructions")}, \
651 {"fused-madd", -MASK_NO_FUSED_MADD, \
652 N_("Generate fused multiply/add instructions")}, \
653 {"fix4300", MASK_4300_MUL_FIX, \
654 N_("Work around early 4300 hardware bug")}, \
655 {"no-fix4300", -MASK_4300_MUL_FIX, \
656 N_("Don't work around early 4300 hardware bug")}, \
657 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
658 N_("Trap on integer divide by zero")}, \
659 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
660 N_("Don't trap on integer divide by zero")}, \
661 {"check-range-division",MASK_CHECK_RANGE_DIV, \
662 N_("Trap on integer divide overflow")}, \
663 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
664 N_("Don't trap on integer divide overflow")}, \
665 { "branch-likely", MASK_BRANCHLIKELY, \
666 N_("Use Branch Likely instructions, overriding default for arch")}, \
667 { "no-branch-likely", -MASK_BRANCHLIKELY, \
668 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
669 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
670 N_("Use NewABI-style %reloc() assembly operators")}, \
671 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
672 N_("Use assembler macros instead of relocation operators")}, \
673 {"debug", MASK_DEBUG, \
675 {"debuga", MASK_DEBUG_A, \
677 {"debugb", MASK_DEBUG_B, \
679 {"debugc", MASK_DEBUG_C, \
681 {"debugd", MASK_DEBUG_D, \
683 {"debuge", MASK_DEBUG_E, \
685 {"debugf", MASK_DEBUG_F, \
687 {"debugg", MASK_DEBUG_G, \
689 {"debugi", MASK_DEBUG_I, \
691 {"", (TARGET_DEFAULT \
692 | TARGET_CPU_DEFAULT \
693 | TARGET_ENDIAN_DEFAULT), \
697 /* Default target_flags if no switches are specified */
699 #ifndef TARGET_DEFAULT
700 #define TARGET_DEFAULT 0
703 #ifndef TARGET_CPU_DEFAULT
704 #define TARGET_CPU_DEFAULT 0
707 #ifndef TARGET_ENDIAN_DEFAULT
708 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
711 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
712 #ifndef MIPS_ISA_DEFAULT
713 #ifndef MIPS_CPU_STRING_DEFAULT
714 #define MIPS_CPU_STRING_DEFAULT "from-abi"
720 /* Make this compile time constant for libgcc2 */
722 #define TARGET_64BIT 1
724 #define TARGET_64BIT 0
726 #endif /* IN_LIBGCC2 */
728 #ifndef MULTILIB_ENDIAN_DEFAULT
729 #if TARGET_ENDIAN_DEFAULT == 0
730 #define MULTILIB_ENDIAN_DEFAULT "EL"
732 #define MULTILIB_ENDIAN_DEFAULT "EB"
736 #ifndef MULTILIB_ISA_DEFAULT
737 # if MIPS_ISA_DEFAULT == 1
738 # define MULTILIB_ISA_DEFAULT "mips1"
740 # if MIPS_ISA_DEFAULT == 2
741 # define MULTILIB_ISA_DEFAULT "mips2"
743 # if MIPS_ISA_DEFAULT == 3
744 # define MULTILIB_ISA_DEFAULT "mips3"
746 # if MIPS_ISA_DEFAULT == 4
747 # define MULTILIB_ISA_DEFAULT "mips4"
749 # if MIPS_ISA_DEFAULT == 32
750 # define MULTILIB_ISA_DEFAULT "mips32"
752 # if MIPS_ISA_DEFAULT == 33
753 # define MULTILIB_ISA_DEFAULT "mips32r2"
755 # if MIPS_ISA_DEFAULT == 64
756 # define MULTILIB_ISA_DEFAULT "mips64"
758 # define MULTILIB_ISA_DEFAULT "mips1"
768 #ifndef MULTILIB_DEFAULTS
769 #define MULTILIB_DEFAULTS \
770 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
773 /* We must pass -EL to the linker by default for little endian embedded
774 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
775 linker will default to using big-endian output files. The OUTPUT_FORMAT
776 line must be in the linker script, otherwise -EB/-EL will not work. */
779 #if TARGET_ENDIAN_DEFAULT == 0
780 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
782 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
786 #define TARGET_OPTIONS \
788 SUBTARGET_TARGET_OPTIONS \
789 { "tune=", &mips_tune_string, \
790 N_("Specify CPU for scheduling purposes"), 0}, \
791 { "arch=", &mips_arch_string, \
792 N_("Specify CPU for code generation purposes"), 0}, \
793 { "abi=", &mips_abi_string, \
794 N_("Specify an ABI"), 0}, \
795 { "ips", &mips_isa_string, \
796 N_("Specify a Standard MIPS ISA"), 0}, \
797 { "entry", &mips_entry_string, \
798 N_("Use mips16 entry/exit psuedo ops"), 0}, \
799 { "no-mips16", &mips_no_mips16_string, \
800 N_("Don't use MIPS16 instructions"), 0}, \
801 { "no-flush-func", &mips_cache_flush_func, \
802 N_("Don't call any cache flush functions"), 0}, \
803 { "flush-func=", &mips_cache_flush_func, \
804 N_("Specify cache flush function"), 0}, \
807 /* This is meant to be redefined in the host dependent files. */
808 #define SUBTARGET_TARGET_OPTIONS
810 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
814 /* Generate three-operand multiply instructions for SImode. */
815 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
823 /* Generate three-operand multiply instructions for DImode. */
824 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
827 /* Macros to decide whether certain features are available or not,
828 depending on the instruction set architecture level. */
830 #define HAVE_SQRT_P() (!ISA_MIPS1)
832 /* True if the ABI can only work with 64-bit integer registers. We
833 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
834 otherwise floating-point registers must also be 64-bit. */
835 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
836 || mips_abi == ABI_O64 \
837 || mips_abi == ABI_N32)
839 /* Likewise for 32-bit regs. */
840 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
842 /* True if symbols are 64 bits wide. At present, n64 is the only
843 ABI for which this is true. */
844 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
846 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
847 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
851 /* ISA has branch likely instructions (eg. mips2). */
852 /* Disable branchlikely for tx39 until compare rewrite. They haven't
853 been generated up to this point. */
854 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
857 /* ISA has the conditional move instructions introduced in mips4. */
858 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
862 && !TARGET_MIPS5500 \
865 /* ISA has just the integer condition move instructions (movn,movz) */
866 #define ISA_HAS_INT_CONDMOVE 0
868 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
869 branch on CC, and move (both FP and non-FP) on CC. */
870 #define ISA_HAS_8CC (ISA_MIPS4 \
875 /* This is a catch all for the other new mips4 instructions: indexed load and
876 indexed prefetch instructions, the FP madd and msub instructions,
877 and the FP recip and recip sqrt instructions */
878 #define ISA_HAS_FP4 ((ISA_MIPS4 \
882 /* ISA has conditional trap instructions. */
883 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
886 /* ISA has integer multiply-accumulate instructions, madd and msub. */
887 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
892 /* ISA has floating-point nmadd and nmsub instructions. */
893 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
895 && (!TARGET_MIPS5400 || TARGET_MAD) \
898 /* ISA has count leading zeroes/ones instruction (not implemented). */
899 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
904 /* ISA has double-word count leading zeroes/ones instruction (not
906 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
909 /* ISA has three operand multiply instructions that put
910 the high part in an accumulator: mulhi or mulhiu. */
911 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
916 /* ISA has three operand multiply instructions that
917 negates the result and puts the result in an accumulator. */
918 #define ISA_HAS_MULS (TARGET_MIPS5400 \
923 /* ISA has three operand multiply instructions that subtracts the
924 result from a 4th operand and puts the result in an accumulator. */
925 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
929 /* ISA has three operand multiply instructions that the result
930 from a 4th operand and puts the result in an accumulator. */
931 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
937 /* ISA has 32-bit rotate right instruction. */
938 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
945 /* ISA has 64-bit rotate right instruction. */
946 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
948 && (TARGET_MIPS5400 \
953 /* ISA has data prefetch instruction. */
954 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
960 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
961 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
962 also requires TARGET_DOUBLE_FLOAT. */
963 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
965 /* ISA includes the MIPS32r2 seb and seh instructions. */
966 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
970 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
971 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
972 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
973 target_flags, and -mgp64 sets MASK_64BIT.
975 Setting MASK_64BIT in target_flags will cause gcc to assume that
976 registers are 64 bits wide. int, long and void * will be 32 bit;
977 this may be changed with -mint64 or -mlong64.
979 The gen* programs link code that refers to MASK_64BIT. They don't
980 actually use the information in target_flags; they just refer to
983 /* Switch Recognition by gcc.c. Add -G xx support */
985 #undef SWITCH_TAKES_ARG
986 #define SWITCH_TAKES_ARG(CHAR) \
987 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
989 /* Sometimes certain combinations of command options do not make sense
990 on a particular target machine. You can define a macro
991 `OVERRIDE_OPTIONS' to take account of this. This macro, if
992 defined, is executed once just after all the command options have
995 On the MIPS, it is used to handle -G. We also use it to set up all
996 of the tables referenced in the other macros. */
998 #define OVERRIDE_OPTIONS override_options ()
1000 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1002 /* Show we can debug even without a frame pointer. */
1003 #define CAN_DEBUG_WITHOUT_FP
1005 /* Tell collect what flags to pass to nm. */
1007 #define NM_FLAGS "-Bn"
1011 /* Assembler specs. */
1013 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1016 #define MIPS_AS_ASM_SPEC "\
1017 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1018 %{pipe: %e-pipe is not supported} \
1019 %{K} %(subtarget_mips_as_asm_spec)"
1021 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1022 rather than gas. It may be overridden by subtargets. */
1024 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1025 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1028 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1031 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1033 #define SUBTARGET_TARGET_SWITCHES
1035 extern int mips_abi;
1037 #ifndef MIPS_ABI_DEFAULT
1038 #define MIPS_ABI_DEFAULT ABI_32
1041 /* Use the most portable ABI flag for the ASM specs. */
1043 #if MIPS_ABI_DEFAULT == ABI_32
1044 #define MULTILIB_ABI_DEFAULT "mabi=32"
1045 #define ASM_ABI_DEFAULT_SPEC "-32"
1048 #if MIPS_ABI_DEFAULT == ABI_O64
1049 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1050 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1053 #if MIPS_ABI_DEFAULT == ABI_N32
1054 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1055 #define ASM_ABI_DEFAULT_SPEC "-n32"
1058 #if MIPS_ABI_DEFAULT == ABI_64
1059 #define MULTILIB_ABI_DEFAULT "mabi=64"
1060 #define ASM_ABI_DEFAULT_SPEC "-64"
1063 #if MIPS_ABI_DEFAULT == ABI_EABI
1064 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1065 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1068 /* Only ELF targets can switch the ABI. */
1069 #ifndef OBJECT_FORMAT_ELF
1070 #undef ASM_ABI_DEFAULT_SPEC
1071 #define ASM_ABI_DEFAULT_SPEC ""
1074 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1075 GAS_ASM_SPEC as the default, depending upon the value of
1078 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1081 #define TARGET_ASM_SPEC "\
1082 %{mmips-as: %(mips_as_asm_spec)} \
1083 %{!mmips-as: %(gas_asm_spec)}"
1087 #define TARGET_ASM_SPEC "\
1088 %{!mgas: %(mips_as_asm_spec)} \
1089 %{mgas: %(gas_asm_spec)}"
1091 #endif /* not GAS */
1093 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1094 to the assembler. It may be overridden by subtargets. */
1095 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1096 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1098 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1101 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1102 the assembler. It may be overridden by subtargets. */
1103 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1104 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1105 %{g} %{g0} %{g1} %{g2} %{g3} \
1106 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1107 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1108 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1109 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1110 %{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1113 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1114 overridden by subtargets. */
1116 #ifndef SUBTARGET_ASM_SPEC
1117 #define SUBTARGET_ASM_SPEC ""
1120 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1121 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1122 whether we're using GAS. These options can only be used properly
1123 with GAS, and it is better to get an error from a non-GAS assembler
1124 than to silently generate bad code. */
1128 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1129 %{mips32} %{mips32r2} %{mips64} \
1130 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1131 %(subtarget_asm_optimizing_spec) \
1132 %(subtarget_asm_debugging_spec) \
1134 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1135 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1136 %{mgp32} %{mgp64} %{march=*} \
1137 %(target_asm_spec) \
1138 %(subtarget_asm_spec)"
1140 /* Specify to run a post-processor, mips-tfile after the assembler
1141 has run to stuff the mips debug information into the object file.
1142 This is needed because the $#!%^ MIPS assembler provides no way
1143 of specifying such information in the assembly file. If we are
1144 cross compiling, disable mips-tfile unless the user specifies
1147 #ifndef ASM_FINAL_SPEC
1148 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1150 #define ASM_FINAL_SPEC "\
1151 %{mmips-as: %{!mno-mips-tfile: \
1152 \n mips-tfile %{v*: -v} \
1154 %{!K: %{save-temps: -I %b.o~}} \
1155 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1156 %{.s:%i} %{!.s:%g.s}}}"
1160 #define ASM_FINAL_SPEC "\
1161 %{!mgas: %{!mno-mips-tfile: \
1162 \n mips-tfile %{v*: -v} \
1164 %{!K: %{save-temps: -I %b.o~}} \
1165 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1166 %{.s:%i} %{!.s:%g.s}}}"
1169 #endif /* ASM_FINAL_SPEC */
1171 /* Redefinition of libraries used. Mips doesn't support normal
1172 UNIX style profiling via calling _mcount. It does offer
1173 profiling that samples the PC, so do what we can... */
1176 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1179 /* Extra switches sometimes passed to the linker. */
1180 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1181 will interpret it as a -b option. */
1184 #define LINK_SPEC "\
1186 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1187 %{bestGnum} %{shared} %{non_shared}"
1188 #endif /* LINK_SPEC defined */
1191 /* Specs for the compiler proper */
1193 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1194 overridden by subtargets. */
1195 #ifndef SUBTARGET_CC1_SPEC
1196 #define SUBTARGET_CC1_SPEC ""
1199 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1200 /* Note, we will need to adjust the following if we ever find a MIPS variant
1201 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1202 that show up in this case. */
1206 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1207 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1209 %(subtarget_cc1_spec)"
1212 /* Preprocessor specs. */
1214 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1215 overridden by subtargets. */
1216 #ifndef SUBTARGET_CPP_SPEC
1217 #define SUBTARGET_CPP_SPEC ""
1220 #define CPP_SPEC "%(subtarget_cpp_spec)"
1222 /* This macro defines names of additional specifications to put in the specs
1223 that can be used in various specifications like CC1_SPEC. Its definition
1224 is an initializer with a subgrouping for each command option.
1226 Each subgrouping contains a string constant, that defines the
1227 specification name, and a string constant that used by the GNU CC driver
1230 Do not define this macro if it does not need to do anything. */
1232 #define EXTRA_SPECS \
1233 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1234 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1235 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1236 { "gas_asm_spec", GAS_ASM_SPEC }, \
1237 { "target_asm_spec", TARGET_ASM_SPEC }, \
1238 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1239 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1240 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1241 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1242 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1243 { "endian_spec", ENDIAN_SPEC }, \
1244 SUBTARGET_EXTRA_SPECS
1246 #ifndef SUBTARGET_EXTRA_SPECS
1247 #define SUBTARGET_EXTRA_SPECS
1250 /* If defined, this macro is an additional prefix to try after
1251 `STANDARD_EXEC_PREFIX'. */
1253 #ifndef MD_EXEC_PREFIX
1254 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1257 #ifndef MD_STARTFILE_PREFIX
1258 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1262 /* Print subsidiary information on the compiler version in use. */
1264 #define MIPS_VERSION "[AL 1.1, MM 40]"
1266 #ifndef MACHINE_TYPE
1267 #define MACHINE_TYPE "BSD Mips"
1270 #ifndef TARGET_VERSION_INTERNAL
1271 #define TARGET_VERSION_INTERNAL(STREAM) \
1272 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1275 #ifndef TARGET_VERSION
1276 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1280 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1281 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1282 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1284 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1285 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1288 /* By default, turn on GDB extensions. */
1289 #define DEFAULT_GDB_EXTENSIONS 1
1291 /* If we are passing smuggling stabs through the MIPS ECOFF object
1292 format, put a comment in front of the .stab<x> operation so
1293 that the MIPS assembler does not choke. The mips-tfile program
1294 will correctly put the stab into the object file. */
1296 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1297 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1298 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1300 /* Local compiler-generated symbols must have a prefix that the assembler
1301 understands. By default, this is $, although some targets (e.g.,
1302 NetBSD-ELF) need to override this. */
1304 #ifndef LOCAL_LABEL_PREFIX
1305 #define LOCAL_LABEL_PREFIX "$"
1308 /* By default on the mips, external symbols do not have an underscore
1309 prepended, but some targets (e.g., NetBSD) require this. */
1311 #ifndef USER_LABEL_PREFIX
1312 #define USER_LABEL_PREFIX ""
1315 /* Forward references to tags are allowed. */
1316 #define SDB_ALLOW_FORWARD_REFERENCES
1318 /* Unknown tags are also allowed. */
1319 #define SDB_ALLOW_UNKNOWN_REFERENCES
1321 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1322 since the length can run past this up to a continuation point. */
1323 #undef DBX_CONTIN_LENGTH
1324 #define DBX_CONTIN_LENGTH 1500
1326 /* How to renumber registers for dbx and gdb. */
1327 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1329 /* The mapping from gcc register number to DWARF 2 CFA column number.
1330 This mapping does not allow for tracking register 0, since SGI's broken
1331 dwarf reader thinks column 0 is used for the frame address, but since
1332 register 0 is fixed this is not a problem. */
1333 #define DWARF_FRAME_REGNUM(REG) \
1334 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1336 /* The DWARF 2 CFA column which tracks the return address. */
1337 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1339 /* Before the prologue, RA lives in r31. */
1340 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1342 /* Describe how we implement __builtin_eh_return. */
1343 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1344 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1346 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1347 The default for this in 64-bit mode is 8, which causes problems with
1348 SFmode register saves. */
1349 #define DWARF_CIE_DATA_ALIGNMENT 4
1351 #define ASM_SIMPLIFY_DWARF_ADDR mips_simplify_dwarf_addr
1353 /* Overrides for the COFF debug format. */
1354 #define PUT_SDB_SCL(a) \
1356 extern FILE *asm_out_text_file; \
1357 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1360 #define PUT_SDB_INT_VAL(a) \
1362 extern FILE *asm_out_text_file; \
1363 fprintf (asm_out_text_file, "\t.val\t"); \
1364 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1365 fprintf (asm_out_text_file, ";"); \
1368 #define PUT_SDB_VAL(a) \
1370 extern FILE *asm_out_text_file; \
1371 fputs ("\t.val\t", asm_out_text_file); \
1372 output_addr_const (asm_out_text_file, (a)); \
1373 fputc (';', asm_out_text_file); \
1376 #define PUT_SDB_DEF(a) \
1378 extern FILE *asm_out_text_file; \
1379 fprintf (asm_out_text_file, "\t%s.def\t", \
1380 (TARGET_GAS) ? "" : "#"); \
1381 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1382 fputc (';', asm_out_text_file); \
1385 #define PUT_SDB_PLAIN_DEF(a) \
1387 extern FILE *asm_out_text_file; \
1388 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1389 (TARGET_GAS) ? "" : "#", (a)); \
1392 #define PUT_SDB_ENDEF \
1394 extern FILE *asm_out_text_file; \
1395 fprintf (asm_out_text_file, "\t.endef\n"); \
1398 #define PUT_SDB_TYPE(a) \
1400 extern FILE *asm_out_text_file; \
1401 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1404 #define PUT_SDB_SIZE(a) \
1406 extern FILE *asm_out_text_file; \
1407 fprintf (asm_out_text_file, "\t.size\t"); \
1408 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1409 fprintf (asm_out_text_file, ";"); \
1412 #define PUT_SDB_DIM(a) \
1414 extern FILE *asm_out_text_file; \
1415 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1418 #ifndef PUT_SDB_START_DIM
1419 #define PUT_SDB_START_DIM \
1421 extern FILE *asm_out_text_file; \
1422 fprintf (asm_out_text_file, "\t.dim\t"); \
1426 #ifndef PUT_SDB_NEXT_DIM
1427 #define PUT_SDB_NEXT_DIM(a) \
1429 extern FILE *asm_out_text_file; \
1430 fprintf (asm_out_text_file, "%d,", a); \
1434 #ifndef PUT_SDB_LAST_DIM
1435 #define PUT_SDB_LAST_DIM(a) \
1437 extern FILE *asm_out_text_file; \
1438 fprintf (asm_out_text_file, "%d;", a); \
1442 #define PUT_SDB_TAG(a) \
1444 extern FILE *asm_out_text_file; \
1445 fprintf (asm_out_text_file, "\t.tag\t"); \
1446 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1447 fputc (';', asm_out_text_file); \
1450 /* For block start and end, we create labels, so that
1451 later we can figure out where the correct offset is.
1452 The normal .ent/.end serve well enough for functions,
1453 so those are just commented out. */
1455 #define PUT_SDB_BLOCK_START(LINE) \
1457 extern FILE *asm_out_text_file; \
1458 fprintf (asm_out_text_file, \
1459 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1460 LOCAL_LABEL_PREFIX, \
1462 (TARGET_GAS) ? "" : "#", \
1463 LOCAL_LABEL_PREFIX, \
1466 sdb_label_count++; \
1469 #define PUT_SDB_BLOCK_END(LINE) \
1471 extern FILE *asm_out_text_file; \
1472 fprintf (asm_out_text_file, \
1473 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1474 LOCAL_LABEL_PREFIX, \
1476 (TARGET_GAS) ? "" : "#", \
1477 LOCAL_LABEL_PREFIX, \
1480 sdb_label_count++; \
1483 #define PUT_SDB_FUNCTION_START(LINE)
1485 #define PUT_SDB_FUNCTION_END(LINE) \
1487 extern FILE *asm_out_text_file; \
1488 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1491 #define PUT_SDB_EPILOGUE_END(NAME)
1493 #define PUT_SDB_SRC_FILE(FILENAME) \
1495 extern FILE *asm_out_text_file; \
1496 output_file_directive (asm_out_text_file, (FILENAME));\
1499 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1500 sprintf ((BUFFER), ".%dfake", (NUMBER));
1502 /* Correct the offset of automatic variables and arguments. Note that
1503 the MIPS debug format wants all automatic variables and arguments
1504 to be in terms of the virtual frame pointer (stack pointer before
1505 any adjustment in the function), while the MIPS 3.0 linker wants
1506 the frame pointer to be the stack pointer after the initial
1509 #define DEBUGGER_AUTO_OFFSET(X) \
1510 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1511 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1512 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1514 /* Tell collect that the object format is ECOFF */
1515 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1516 #define EXTENDED_COFF /* ECOFF, not normal coff */
1518 /* Target machine storage layout */
1520 /* Define this if most significant bit is lowest numbered
1521 in instructions that operate on numbered bit-fields.
1523 #define BITS_BIG_ENDIAN 0
1525 /* Define this if most significant byte of a word is the lowest numbered. */
1526 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1528 /* Define this if most significant word of a multiword number is the lowest. */
1529 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1531 /* Define this to set the endianness to use in libgcc2.c, which can
1532 not depend on target_flags. */
1533 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1534 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1536 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1539 #define MAX_BITS_PER_WORD 64
1541 /* Width of a word, in units (bytes). */
1542 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1543 #define MIN_UNITS_PER_WORD 4
1545 /* For MIPS, width of a floating point register. */
1546 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1548 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1549 the next available register. */
1550 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1552 /* The largest size of value that can be held in floating-point
1553 registers and moved with a single instruction. */
1554 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1556 /* The largest size of value that can be held in floating-point
1558 #define UNITS_PER_FPVALUE \
1559 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1561 /* The number of bytes in a double. */
1562 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1564 /* A C expression for the size in bits of the type `int' on the
1565 target machine. If you don't define this, the default is one
1567 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1569 /* Tell the preprocessor the maximum size of wchar_t. */
1570 #ifndef MAX_WCHAR_TYPE_SIZE
1571 #ifndef WCHAR_TYPE_SIZE
1572 #define MAX_WCHAR_TYPE_SIZE 64
1576 /* A C expression for the size in bits of the type `short' on the
1577 target machine. If you don't define this, the default is half a
1578 word. (If this would be less than one storage unit, it is
1579 rounded up to one unit.) */
1580 #define SHORT_TYPE_SIZE 16
1582 /* A C expression for the size in bits of the type `long' on the
1583 target machine. If you don't define this, the default is one
1585 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1586 #define MAX_LONG_TYPE_SIZE 64
1588 /* A C expression for the size in bits of the type `long long' on the
1589 target machine. If you don't define this, the default is two
1591 #define LONG_LONG_TYPE_SIZE 64
1593 /* A C expression for the size in bits of the type `float' on the
1594 target machine. If you don't define this, the default is one
1596 #define FLOAT_TYPE_SIZE 32
1598 /* A C expression for the size in bits of the type `double' on the
1599 target machine. If you don't define this, the default is two
1601 #define DOUBLE_TYPE_SIZE 64
1603 /* A C expression for the size in bits of the type `long double' on
1604 the target machine. If you don't define this, the default is two
1606 #define LONG_DOUBLE_TYPE_SIZE \
1607 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1609 /* long double is not a fixed mode, but the idea is that, if we
1610 support long double, we also want a 128-bit integer type. */
1611 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1614 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1615 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1616 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1618 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1622 /* Width in bits of a pointer. */
1623 #ifndef POINTER_SIZE
1624 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1627 #define POINTERS_EXTEND_UNSIGNED 0
1629 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1630 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1631 || mips_abi == ABI_64 \
1632 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1635 /* Allocation boundary (in *bits*) for the code of a function. */
1636 #define FUNCTION_BOUNDARY 32
1638 /* Alignment of field after `int : 0' in a structure. */
1639 #define EMPTY_FIELD_BOUNDARY 32
1641 /* Every structure's size must be a multiple of this. */
1642 /* 8 is observed right on a DECstation and on riscos 4.02. */
1643 #define STRUCTURE_SIZE_BOUNDARY 8
1645 /* There is no point aligning anything to a rounder boundary than this. */
1646 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1648 /* Set this nonzero if move instructions will actually fail to work
1649 when given unaligned data. */
1650 #define STRICT_ALIGNMENT 1
1652 /* Define this if you wish to imitate the way many other C compilers
1653 handle alignment of bitfields and the structures that contain
1656 The behavior is that the type written for a bit-field (`int',
1657 `short', or other integer type) imposes an alignment for the
1658 entire structure, as if the structure really did contain an
1659 ordinary field of that type. In addition, the bit-field is placed
1660 within the structure so that it would fit within such a field,
1661 not crossing a boundary for it.
1663 Thus, on most machines, a bit-field whose type is written as `int'
1664 would not cross a four-byte boundary, and would force four-byte
1665 alignment for the whole structure. (The alignment used may not
1666 be four bytes; it is controlled by the other alignment
1669 If the macro is defined, its definition should be a C expression;
1670 a nonzero value for the expression enables this behavior. */
1672 #define PCC_BITFIELD_TYPE_MATTERS 1
1674 /* If defined, a C expression to compute the alignment given to a
1675 constant that is being placed in memory. CONSTANT is the constant
1676 and ALIGN is the alignment that the object would ordinarily have.
1677 The value of this macro is used instead of that alignment to align
1680 If this macro is not defined, then ALIGN is used.
1682 The typical use of this macro is to increase alignment for string
1683 constants to be word aligned so that `strcpy' calls that copy
1684 constants can be done inline. */
1686 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1687 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1688 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1690 /* If defined, a C expression to compute the alignment for a static
1691 variable. TYPE is the data type, and ALIGN is the alignment that
1692 the object would ordinarily have. The value of this macro is used
1693 instead of that alignment to align the object.
1695 If this macro is not defined, then ALIGN is used.
1697 One use of this macro is to increase alignment of medium-size
1698 data to make it all fit in fewer cache lines. Another is to
1699 cause character arrays to be word-aligned so that `strcpy' calls
1700 that copy constants to character arrays can be done inline. */
1702 #undef DATA_ALIGNMENT
1703 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1704 ((((ALIGN) < BITS_PER_WORD) \
1705 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1706 || TREE_CODE (TYPE) == UNION_TYPE \
1707 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1710 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1712 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1714 /* Define this macro if an argument declared as `char' or `short' in a
1715 prototype should actually be passed as an `int'. In addition to
1716 avoiding errors in certain cases of mismatch, it also makes for
1717 better code on certain machines. */
1719 #define PROMOTE_PROTOTYPES 1
1721 /* Define if operations between registers always perform the operation
1722 on the full register even if a narrower mode is specified. */
1723 #define WORD_REGISTER_OPERATIONS
1725 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1726 will either zero-extend or sign-extend. The value of this macro should
1727 be the code that says which one of the two operations is implicitly
1730 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1731 moves. All other referces are zero extended. */
1732 #define LOAD_EXTEND_OP(MODE) \
1733 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1734 ? SIGN_EXTEND : ZERO_EXTEND)
1736 /* Define this macro if it is advisable to hold scalars in registers
1737 in a wider mode than that declared by the program. In such cases,
1738 the value is constrained to be within the bounds of the declared
1739 type, but kept valid in the wider mode. The signedness of the
1740 extension may differ from that of the type. */
1742 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1743 if (GET_MODE_CLASS (MODE) == MODE_INT \
1744 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1746 if ((MODE) == SImode) \
1751 /* Define if loading short immediate values into registers sign extends. */
1752 #define SHORT_IMMEDIATES_SIGN_EXTEND
1755 /* Define this if function arguments should also be promoted using the above
1757 #define PROMOTE_FUNCTION_ARGS
1759 /* Likewise, if the function return value is promoted. */
1760 #define PROMOTE_FUNCTION_RETURN
1763 /* Standard register usage. */
1765 /* Number of actual hardware registers.
1766 The hardware registers are assigned numbers for the compiler
1767 from 0 to just below FIRST_PSEUDO_REGISTER.
1768 All registers that the compiler knows about must be given numbers,
1769 even those that are not normally considered general registers.
1771 On the Mips, we have 32 integer registers, 32 floating point
1772 registers, 8 condition code registers, and the special registers
1773 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1774 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1775 processor.) The 8 condition code registers are only used if
1776 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1777 represents a 64 bit value stored as two 32 bit values in the hi and
1778 lo registers; this is the result of the mult instruction. rap is a
1779 pointer to the stack where the return address reg ($31) was stored.
1780 This is needed for C++ exception handling. */
1782 #define FIRST_PSEUDO_REGISTER 176
1784 /* 1 for registers that have pervasive standard uses
1785 and are not available for the register allocator.
1787 On the MIPS, see conventions, page D-2 */
1789 /* Regarding coprocessor registers: without evidence to the contrary,
1790 it's best to assume that each coprocessor register has a unique
1791 use. This can be overridden, in, e.g., override_options() or
1792 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1793 for a particular target. */
1795 #define FIXED_REGISTERS \
1797 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1798 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1799 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1800 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1801 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1802 /* COP0 registers */ \
1803 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1804 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1805 /* COP2 registers */ \
1806 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1807 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1808 /* COP3 registers */ \
1809 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1810 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1814 /* Don't mark $31 as a call-clobbered register. The idea is that
1815 it's really the call instructions themselves which clobber $31.
1816 We don't care what the called function does with it afterwards.
1818 This approach makes it easier to implement sibcalls. Unlike normal
1819 calls, sibcalls don't clobber $31, so the register reaches the
1820 called function in tact. EPILOGUE_USES says that $31 is useful
1821 to the called function. */
1823 #define CALL_USED_REGISTERS \
1825 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1826 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1827 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1828 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1829 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1830 /* COP0 registers */ \
1831 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1832 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1833 /* COP2 registers */ \
1834 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1835 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1836 /* COP3 registers */ \
1837 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1838 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1841 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1842 problem which makes CALL_USED_REGISTERS *always* include
1843 all the FIXED_REGISTERS. Until this problem has been
1844 resolved this macro can be used to overcome this situation.
1845 In particular, block_propagate() requires this list
1846 be acurate, or we can remove registers which should be live.
1847 This macro is used in regs_invalidated_by_call. */
1850 #define CALL_REALLY_USED_REGISTERS \
1851 { /* General registers. */ \
1852 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1853 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1854 /* Floating-point registers. */ \
1855 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1856 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1858 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1859 /* COP0 registers */ \
1860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1862 /* COP2 registers */ \
1863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1865 /* COP3 registers */ \
1866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1870 /* Internal macros to classify a register number as to whether it's a
1871 general purpose register, a floating point register, a
1872 multiply/divide register, or a status register. */
1874 #define GP_REG_FIRST 0
1875 #define GP_REG_LAST 31
1876 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1877 #define GP_DBX_FIRST 0
1879 #define FP_REG_FIRST 32
1880 #define FP_REG_LAST 63
1881 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1882 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1884 #define MD_REG_FIRST 64
1885 #define MD_REG_LAST 66
1886 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1887 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1889 #define ST_REG_FIRST 67
1890 #define ST_REG_LAST 74
1891 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1894 /* FIXME: renumber. */
1895 #define COP0_REG_FIRST 80
1896 #define COP0_REG_LAST 111
1897 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1899 #define COP2_REG_FIRST 112
1900 #define COP2_REG_LAST 143
1901 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1903 #define COP3_REG_FIRST 144
1904 #define COP3_REG_LAST 175
1905 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1906 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1907 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1909 #define AT_REGNUM (GP_REG_FIRST + 1)
1910 #define HI_REGNUM (MD_REG_FIRST + 0)
1911 #define LO_REGNUM (MD_REG_FIRST + 1)
1912 #define HILO_REGNUM (MD_REG_FIRST + 2)
1914 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1915 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1916 should be used instead. */
1917 #define FPSW_REGNUM ST_REG_FIRST
1919 #define GP_REG_P(REGNO) \
1920 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1921 #define M16_REG_P(REGNO) \
1922 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1923 #define FP_REG_P(REGNO) \
1924 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1925 #define MD_REG_P(REGNO) \
1926 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1927 #define ST_REG_P(REGNO) \
1928 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1929 #define COP0_REG_P(REGNO) \
1930 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1931 #define COP2_REG_P(REGNO) \
1932 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1933 #define COP3_REG_P(REGNO) \
1934 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1935 #define ALL_COP_REG_P(REGNO) \
1936 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1938 /* Return coprocessor number from register number. */
1940 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1941 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1942 : COP3_REG_P (REGNO) ? '3' : '?')
1944 /* Return number of consecutive hard regs needed starting at reg REGNO
1945 to hold something of mode MODE.
1946 This is ordinarily the length in words of a value of mode MODE
1947 but can be less for certain modes in special long registers.
1949 On the MIPS, all general registers are one word long. Except on
1950 the R4000 with the FR bit set, the floating point uses register
1951 pairs, with the second register not being allocable. */
1953 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1955 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1956 MODE. In 32 bit mode, require that DImode and DFmode be in even
1957 registers. For DImode, this makes some of the insns easier to
1958 write, since you don't have to worry about a DImode value in
1959 registers 3 & 4, producing a result in 4 & 5.
1961 To make the code simpler HARD_REGNO_MODE_OK now just references an
1962 array built in override_options. Because machmodes.h is not yet
1963 included before this file is processed, the MODE bound can't be
1966 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1968 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1969 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1971 /* Value is 1 if it is a good idea to tie two pseudo registers
1972 when one has mode MODE1 and one has mode MODE2.
1973 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1974 for any hard reg, then this must be 0 for correct output. */
1975 #define MODES_TIEABLE_P(MODE1, MODE2) \
1976 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1977 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1978 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1979 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1981 /* MIPS pc is not overloaded on a register. */
1982 /* #define PC_REGNUM xx */
1984 /* Register to use for pushing function arguments. */
1985 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1987 /* Offset from the stack pointer to the first available location. Use
1988 the default value zero. */
1989 /* #define STACK_POINTER_OFFSET 0 */
1991 /* Base register for access to local variables of the function. We
1992 pretend that the frame pointer is $1, and then eliminate it to
1993 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1994 a fixed register, and will not be used for anything else. */
1995 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1997 /* Temporary scratch register for use by the assembler. */
1998 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
2000 /* $30 is not available on the mips16, so we use $17 as the frame
2002 #define HARD_FRAME_POINTER_REGNUM \
2003 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
2005 /* Value should be nonzero if functions must have frame pointers.
2006 Zero means the frame pointer need not be set up (and parms
2007 may be accessed via the stack pointer) in functions that seem suitable.
2008 This is computed in `reload', in reload1.c. */
2009 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
2011 /* Base register for access to arguments of the function. */
2012 #define ARG_POINTER_REGNUM GP_REG_FIRST
2014 /* Register in which static-chain is passed to a function. */
2015 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
2017 /* If the structure value address is passed in a register, then
2018 `STRUCT_VALUE_REGNUM' should be the number of that register. */
2019 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
2021 /* If the structure value address is not passed in a register, define
2022 `STRUCT_VALUE' as an expression returning an RTX for the place
2023 where the address is passed. If it returns 0, the address is
2024 passed as an "invisible" first argument. */
2025 #define STRUCT_VALUE 0
2027 /* Mips registers used in prologue/epilogue code when the stack frame
2028 is larger than 32K bytes. These registers must come from the
2029 scratch register set, and not used for passing and returning
2030 arguments and any other information used in the calling sequence
2031 (such as pic). Must start at 12, since t0/t3 are parameter passing
2032 registers in the 64 bit ABI. */
2034 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
2035 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
2037 /* Define this macro if it is as good or better to call a constant
2038 function address than to call an address kept in a register. */
2039 #define NO_FUNCTION_CSE 1
2041 /* Define this macro if it is as good or better for a function to
2042 call itself with an explicit address than to call an address
2043 kept in a register. */
2044 #define NO_RECURSIVE_FUNCTION_CSE 1
2046 /* The register number of the register used to address a table of
2047 static data addresses in memory. In some cases this register is
2048 defined by a processor's "application binary interface" (ABI).
2049 When this macro is defined, RTL is generated for this register
2050 once, as with the stack pointer and frame pointer registers. If
2051 this macro is not defined, it is up to the machine-dependent
2052 files to allocate such a register (if necessary). */
2053 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
2055 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
2057 /* Define the classes of registers for register constraints in the
2058 machine description. Also define ranges of constants.
2060 One of the classes must always be named ALL_REGS and include all hard regs.
2061 If there is more than one class, another class must be named NO_REGS
2062 and contain no registers.
2064 The name GENERAL_REGS must be the name of a class (or an alias for
2065 another name such as ALL_REGS). This is the class of registers
2066 that is allowed by "g" or "r" in a register constraint.
2067 Also, registers outside this class are allocated only when
2068 instructions express preferences for them.
2070 The classes must be numbered in nondecreasing order; that is,
2071 a larger-numbered class must never be contained completely
2072 in a smaller-numbered class.
2074 For any two classes, it is very desirable that there be another
2075 class that represents their union. */
2079 NO_REGS, /* no registers in set */
2080 M16_NA_REGS, /* mips16 regs not used to pass args */
2081 M16_REGS, /* mips16 directly accessible registers */
2082 T_REG, /* mips16 T register ($24) */
2083 M16_T_REGS, /* mips16 registers plus T register */
2084 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2085 LEA_REGS, /* Every GPR except $25 */
2086 GR_REGS, /* integer registers */
2087 FP_REGS, /* floating point registers */
2088 HI_REG, /* hi register */
2089 LO_REG, /* lo register */
2090 HILO_REG, /* hilo register pair for 64 bit mode mult */
2091 MD_REGS, /* multiply/divide registers (hi/lo) */
2092 COP0_REGS, /* generic coprocessor classes */
2095 HI_AND_GR_REGS, /* union classes */
2103 ALL_COP_AND_GR_REGS,
2104 ST_REGS, /* status registers (fp status) */
2105 ALL_REGS, /* all registers */
2106 LIM_REG_CLASSES /* max value + 1 */
2109 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2111 #define GENERAL_REGS GR_REGS
2113 /* An initializer containing the names of the register classes as C
2114 string constants. These names are used in writing some of the
2117 #define REG_CLASS_NAMES \
2124 "PIC_FN_ADDR_REG", \
2132 /* coprocessor registers */ \
2138 "HILO_AND_GR_REGS", \
2140 "COP0_AND_GR_REGS", \
2141 "COP2_AND_GR_REGS", \
2142 "COP3_AND_GR_REGS", \
2144 "ALL_COP_AND_GR_REGS", \
2149 /* An initializer containing the contents of the register classes,
2150 as integers which are bit masks. The Nth integer specifies the
2151 contents of class N. The way the integer MASK is interpreted is
2152 that register R is in the class if `MASK & (1 << R)' is 1.
2154 When the machine has more than 32 registers, an integer does not
2155 suffice. Then the integers are replaced by sub-initializers,
2156 braced groupings containing several integers. Each
2157 sub-initializer must be suitable as an initializer for the type
2158 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2160 #define REG_CLASS_CONTENTS \
2162 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2163 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2164 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2165 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2166 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2167 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
2168 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
2169 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2170 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2171 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2172 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2173 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2174 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2175 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2176 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2177 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2178 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2179 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2180 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2181 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2182 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2183 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2184 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2185 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2186 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2187 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2188 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2192 /* A C expression whose value is a register class containing hard
2193 register REGNO. In general there is more that one such class;
2194 choose a class which is "minimal", meaning that no smaller class
2195 also contains the register. */
2197 extern const enum reg_class mips_regno_to_class[];
2199 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2201 /* A macro whose definition is the name of the class to which a
2202 valid base register must belong. A base register is one used in
2203 an address which is the register value plus a displacement. */
2205 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2207 /* A macro whose definition is the name of the class to which a
2208 valid index register must belong. An index register is one used
2209 in an address where its value is either multiplied by a scale
2210 factor or added to another register (as well as added to a
2213 #define INDEX_REG_CLASS NO_REGS
2215 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2216 registers explicitly used in the rtl to be used as spill registers
2217 but prevents the compiler from extending the lifetime of these
2220 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2222 /* This macro is used later on in the file. */
2223 #define GR_REG_CLASS_P(CLASS) \
2224 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2225 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
2226 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
2228 /* This macro is also used later on in the file. */
2229 #define COP_REG_CLASS_P(CLASS) \
2230 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2232 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2233 is the default value (allocate the registers in numeric order). We
2234 define it just so that we can override it for the mips16 target in
2235 ORDER_REGS_FOR_LOCAL_ALLOC. */
2237 #define REG_ALLOC_ORDER \
2238 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2239 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2240 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2241 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2242 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2243 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2244 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2245 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2246 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2247 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2248 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2251 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2252 to be rearranged based on a particular function. On the mips16, we
2253 want to allocate $24 (T_REG) before other registers for
2254 instructions for which it is possible. */
2256 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2258 /* REGISTER AND CONSTANT CLASSES */
2260 /* Get reg_class from a letter such as appears in the machine
2263 DEFINED REGISTER CLASSES:
2265 'd' General (aka integer) registers
2266 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2267 'y' General registers (in both mips16 and non mips16 mode)
2268 'e' mips16 non argument registers (M16_NA_REGS)
2269 't' mips16 temporary register ($24)
2270 'f' Floating point registers
2273 'x' Multiply/divide registers
2275 'z' FP Status register
2279 'b' All registers */
2281 extern enum reg_class mips_char_to_class[256];
2283 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2285 /* True if VALUE is a signed 16-bit number. */
2287 #define SMALL_OPERAND(VALUE) \
2288 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2290 /* True if VALUE is an unsigned 16-bit number. */
2292 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2293 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2295 /* True if VALUE can be loaded into a register using LUI. */
2297 #define LUI_OPERAND(VALUE) \
2298 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2299 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2301 /* Return a value X with the low 16 bits clear, and such that
2302 VALUE - X is a signed 16-bit value. */
2304 #define CONST_HIGH_PART(VALUE) \
2305 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2307 #define CONST_LOW_PART(VALUE) \
2308 ((VALUE) - CONST_HIGH_PART (VALUE))
2310 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2311 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2312 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2314 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2315 string can be used to stand for particular ranges of immediate
2316 operands. This macro defines what the ranges are. C is the
2317 letter, and VALUE is a constant value. Return 1 if VALUE is
2318 in the range specified by C. */
2322 `I' is used for the range of constants an arithmetic insn can
2323 actually contain (16 bits signed integers).
2325 `J' is used for the range which is just zero (ie, $r0).
2327 `K' is used for the range of constants a logical insn can actually
2328 contain (16 bit zero-extended integers).
2330 `L' is used for the range of constants that be loaded with lui
2331 (ie, the bottom 16 bits are zero).
2333 `M' is used for the range of constants that take two words to load
2334 (ie, not matched by `I', `K', and `L').
2336 `N' is used for negative 16 bit constants other than -65536.
2338 `O' is a 15 bit signed integer.
2340 `P' is used for positive 16 bit constants. */
2342 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2343 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2344 : (C) == 'J' ? ((VALUE) == 0) \
2345 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2346 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2347 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2348 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2349 && !LUI_OPERAND (VALUE)) \
2350 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2351 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2352 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2355 /* Similar, but for floating constants, and defining letters G and H.
2356 Here VALUE is the CONST_DOUBLE rtx itself. */
2360 'G' : Floating point 0 */
2362 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2364 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2366 /* True if OP is a constant that should not be moved into $25.
2367 We need this because many versions of gas treat 'la $25,foo' as
2368 part of a call sequence and allow a global 'foo' to be lazily bound. */
2370 #define DANGEROUS_FOR_LA25_P(OP) \
2372 && !TARGET_EXPLICIT_RELOCS \
2373 && mips_global_pic_constant_p (OP))
2375 /* Letters in the range `Q' through `U' may be defined in a
2376 machine-dependent fashion to stand for arbitrary operand types.
2377 The machine description macro `EXTRA_CONSTRAINT' is passed the
2378 operand as its first argument and the constraint letter as its
2381 `Q' is for signed 16-bit constants.
2382 `R' is for single-instruction memory references. Note that this
2383 constraint has often been used in linux and glibc code.
2384 `S' is for legitimate constant call addresses.
2385 `T' is for constant move_operands that cannot be safely loaded into $25.
2386 `U' is for constant move_operands that can be safely loaded into $25. */
2388 #define EXTRA_CONSTRAINT(OP,CODE) \
2389 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2390 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2391 && mips_fetch_insns (OP) == 1) \
2392 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2393 && call_insn_operand (OP, VOIDmode)) \
2394 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2395 && move_operand (OP, VOIDmode) \
2396 && DANGEROUS_FOR_LA25_P (OP)) \
2397 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2398 && move_operand (OP, VOIDmode) \
2399 && !DANGEROUS_FOR_LA25_P (OP)) \
2402 /* Given an rtx X being reloaded into a reg required to be
2403 in class CLASS, return the class of reg to actually use.
2404 In general this is just CLASS; but on some machines
2405 in some cases it is preferable to use a more restrictive class. */
2407 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2408 ((CLASS) != ALL_REGS \
2409 ? (! TARGET_MIPS16 \
2411 : ((CLASS) != GR_REGS \
2414 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2415 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2416 ? (TARGET_SOFT_FLOAT \
2417 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2419 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2420 || GET_MODE (X) == VOIDmode) \
2421 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2424 /* Certain machines have the property that some registers cannot be
2425 copied to some other registers without using memory. Define this
2426 macro on those machines to be a C expression that is nonzero if
2427 objects of mode MODE in registers of CLASS1 can only be copied to
2428 registers of class CLASS2 by storing a register of CLASS1 into
2429 memory and loading that memory location into a register of CLASS2.
2431 Do not define this macro if its value would always be zero. */
2433 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2434 ((!TARGET_DEBUG_H_MODE \
2435 && GET_MODE_CLASS (MODE) == MODE_INT \
2436 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2437 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2438 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2439 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2440 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2442 /* The HI and LO registers can only be reloaded via the general
2443 registers. Condition code registers can only be loaded to the
2444 general registers, and from the floating point registers. */
2446 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2447 mips_secondary_reload_class (CLASS, MODE, X, 1)
2448 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2449 mips_secondary_reload_class (CLASS, MODE, X, 0)
2451 /* Return the maximum number of consecutive registers
2452 needed to represent mode MODE in a register of class CLASS. */
2454 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2456 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2457 mips_cannot_change_mode_class (FROM, TO, CLASS)
2459 /* Stack layout; function entry, exit and calling. */
2461 /* Define this if pushing a word on the stack
2462 makes the stack pointer a smaller address. */
2463 #define STACK_GROWS_DOWNWARD
2465 /* Define this if the nominal address of the stack frame
2466 is at the high-address end of the local variables;
2467 that is, each additional local variable allocated
2468 goes at a more negative offset in the frame. */
2469 /* #define FRAME_GROWS_DOWNWARD */
2471 /* Offset within stack frame to start allocating local variables at.
2472 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2473 first local allocated. Otherwise, it is the offset to the BEGINNING
2474 of the first local allocated. */
2475 #define STARTING_FRAME_OFFSET \
2476 (current_function_outgoing_args_size \
2477 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2479 /* Offset from the stack pointer register to an item dynamically
2480 allocated on the stack, e.g., by `alloca'.
2482 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2483 length of the outgoing arguments. The default is correct for most
2484 machines. See `function.c' for details.
2486 The MIPS ABI states that functions which dynamically allocate the
2487 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2488 we are trying to create a second frame pointer to the function, so
2489 allocate some stack space to make it happy.
2491 However, the linker currently complains about linking any code that
2492 dynamically allocates stack space, and there seems to be a bug in
2493 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2496 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2497 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2498 ? 4*UNITS_PER_WORD \
2499 : current_function_outgoing_args_size)
2502 /* The return address for the current frame is in r31 if this is a leaf
2503 function. Otherwise, it is on the stack. It is at a variable offset
2504 from sp/fp/ap, so we define a fake hard register rap which is a
2505 poiner to the return address on the stack. This always gets eliminated
2506 during reload to be either the frame pointer or the stack pointer plus
2509 #define RETURN_ADDR_RTX mips_return_addr
2511 /* Since the mips16 ISA mode is encoded in the least-significant bit
2512 of the address, mask it off return addresses for purposes of
2513 finding exception handling regions. */
2515 #define MASK_RETURN_ADDR GEN_INT (-2)
2518 /* Similarly, don't use the least-significant bit to tell pointers to
2519 code from vtable index. */
2521 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2523 /* If defined, this macro specifies a table of register pairs used to
2524 eliminate unneeded registers that point into the stack frame. If
2525 it is not defined, the only elimination attempted by the compiler
2526 is to replace references to the frame pointer with references to
2529 The definition of this macro is a list of structure
2530 initializations, each of which specifies an original and
2531 replacement register.
2533 On some machines, the position of the argument pointer is not
2534 known until the compilation is completed. In such a case, a
2535 separate hard register must be used for the argument pointer.
2536 This register can be eliminated by replacing it with either the
2537 frame pointer or the argument pointer, depending on whether or not
2538 the frame pointer has been eliminated.
2540 In this case, you might specify:
2541 #define ELIMINABLE_REGS \
2542 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2543 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2544 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2546 Note that the elimination of the argument pointer with the stack
2547 pointer is specified first since that is the preferred elimination.
2549 The eliminations to $17 are only used on the mips16. See the
2550 definition of HARD_FRAME_POINTER_REGNUM. */
2552 #define ELIMINABLE_REGS \
2553 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2554 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2555 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2556 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2557 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2558 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2560 /* A C expression that returns nonzero if the compiler is allowed to
2561 try to replace register number FROM-REG with register number
2562 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2563 defined, and will usually be the constant 1, since most of the
2564 cases preventing register elimination are things that the compiler
2565 already knows about.
2567 When not in mips16 and mips64, we can always eliminate to the
2568 frame pointer. We can eliminate to the stack pointer unless
2569 a frame pointer is needed. In mips16 mode, we need a frame
2570 pointer for a large frame; otherwise, reload may be unable
2571 to compute the address of a local variable, since there is
2572 no way to add a large constant to the stack pointer
2573 without using a temporary register.
2575 In mips16, for some instructions (eg lwu), we can't eliminate the
2576 frame pointer for the stack pointer. These instructions are
2577 only generated in TARGET_64BIT mode.
2580 #define CAN_ELIMINATE(FROM, TO) \
2581 (((TO) == HARD_FRAME_POINTER_REGNUM \
2582 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2583 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2584 && (! TARGET_MIPS16 \
2585 || compute_frame_size (get_frame_size ()) < 32768))))
2587 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2588 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2590 /* If we generate an insn to push BYTES bytes,
2591 this says how many the stack pointer really advances by.
2592 On the VAX, sp@- in a byte insn really pushes a word. */
2594 /* #define PUSH_ROUNDING(BYTES) 0 */
2596 /* If defined, the maximum amount of space required for outgoing
2597 arguments will be computed and placed into the variable
2598 `current_function_outgoing_args_size'. No space will be pushed
2599 onto the stack for each call; instead, the function prologue
2600 should increase the stack frame size by this amount.
2602 It is not proper to define both `PUSH_ROUNDING' and
2603 `ACCUMULATE_OUTGOING_ARGS'. */
2604 #define ACCUMULATE_OUTGOING_ARGS 1
2606 /* Offset from the argument pointer register to the first argument's
2607 address. On some machines it may depend on the data type of the
2610 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2611 the first argument's address.
2613 On the MIPS, we must skip the first argument position if we are
2614 returning a structure or a union, to account for its address being
2615 passed in $4. However, at the current time, this produces a compiler
2616 that can't bootstrap, so comment it out for now. */
2619 #define FIRST_PARM_OFFSET(FNDECL) \
2621 && TREE_TYPE (FNDECL) != 0 \
2622 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2623 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2624 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2628 #define FIRST_PARM_OFFSET(FNDECL) 0
2631 /* When a parameter is passed in a register, stack space is still
2632 allocated for it. For the MIPS, stack space must be allocated, cf
2633 Asm Lang Prog Guide page 7-8.
2635 BEWARE that some space is also allocated for non existing arguments
2636 in register. In case an argument list is of form GF used registers
2637 are a0 (a2,a3), but we should push over a1... */
2639 #define REG_PARM_STACK_SPACE(FNDECL) \
2640 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2641 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2644 /* Define this if it is the responsibility of the caller to
2645 allocate the area reserved for arguments passed in registers.
2646 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2647 of this macro is to determine whether the space is included in
2648 `current_function_outgoing_args_size'. */
2649 #define OUTGOING_REG_PARM_STACK_SPACE
2651 #define STACK_BOUNDARY \
2652 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2655 /* Make sure 4 words are always allocated on the stack. */
2657 #ifndef STACK_ARGS_ADJUST
2658 #define STACK_ARGS_ADJUST(SIZE) \
2660 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2661 SIZE.constant = 4 * UNITS_PER_WORD; \
2666 /* A C expression that should indicate the number of bytes of its
2667 own arguments that a function pops on returning, or 0
2668 if the function pops no arguments and the caller must therefore
2669 pop them all after the function returns.
2671 FUNDECL is the declaration node of the function (as a tree).
2673 FUNTYPE is a C variable whose value is a tree node that
2674 describes the function in question. Normally it is a node of
2675 type `FUNCTION_TYPE' that describes the data type of the function.
2676 From this it is possible to obtain the data types of the value
2677 and arguments (if known).
2679 When a call to a library function is being considered, FUNTYPE
2680 will contain an identifier node for the library function. Thus,
2681 if you need to distinguish among various library functions, you
2682 can do so by their names. Note that "library function" in this
2683 context means a function used to perform arithmetic, whose name
2684 is known specially in the compiler and was not mentioned in the
2685 C code being compiled.
2687 STACK-SIZE is the number of bytes of arguments passed on the
2688 stack. If a variable number of bytes is passed, it is zero, and
2689 argument popping will always be the responsibility of the
2690 calling function. */
2692 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2695 /* Symbolic macros for the registers used to return integer and floating
2698 #define GP_RETURN (GP_REG_FIRST + 2)
2699 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2701 #define MAX_ARGS_IN_REGISTERS \
2702 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2704 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2706 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2708 /* Symbolic macros for the first/last argument registers. */
2710 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2711 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2712 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2713 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2715 /* Define how to find the value returned by a library function
2716 assuming the value has mode MODE. Because we define
2717 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2718 PROMOTE_MODE does. */
2720 #define LIBCALL_VALUE(MODE) \
2721 mips_function_value (NULL_TREE, NULL, (MODE))
2723 /* Define how to find the value returned by a function.
2724 VALTYPE is the data type of the value (as a tree).
2725 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2726 otherwise, FUNC is 0. */
2728 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2729 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2731 /* 1 if N is a possible register number for a function value.
2732 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2733 Currently, R2 and F0 are only implemented here (C has no complex type) */
2735 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2736 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2737 && (N) == FP_RETURN + 2))
2739 /* 1 if N is a possible register number for function argument passing.
2740 We have no FP argument registers when soft-float. When FP registers
2741 are 32 bits, we can't directly reference the odd numbered ones. */
2743 #define FUNCTION_ARG_REGNO_P(N) \
2744 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2745 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2746 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2749 /* A C expression which can inhibit the returning of certain function
2750 values in registers, based on the type of value. A nonzero value says
2751 to return the function value in memory, just as large structures are
2752 always returned. Here TYPE will be a C expression of type
2753 `tree', representing the data type of the value.
2755 Note that values of mode `BLKmode' must be explicitly
2756 handled by this macro. Also, the option `-fpcc-struct-return'
2757 takes effect regardless of this macro. On most systems, it is
2758 possible to leave the macro undefined; this causes a default
2759 definition to be used, whose value is the constant 1 for BLKmode
2760 values, and 0 otherwise.
2762 GCC normally converts 1 byte structures into chars, 2 byte
2763 structs into shorts, and 4 byte structs into ints, and returns
2764 them this way. Defining the following macro overrides this,
2765 to give us MIPS cc compatibility. */
2767 #define RETURN_IN_MEMORY(TYPE) \
2768 mips_return_in_memory (TYPE)
2770 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2771 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2774 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2776 /* Define a data type for recording info about an argument list
2777 during the scan of that argument list. This data type should
2778 hold all necessary information about the function itself
2779 and about the args processed so far, enough to enable macros
2780 such as FUNCTION_ARG to determine where the next arg should go.
2782 This structure has to cope with two different argument allocation
2783 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2784 first N words go in registers and the rest go on the stack. If I < N,
2785 the Ith word might go in Ith integer argument register or the
2786 Ith floating-point one. In some cases, it has to go in both (see
2787 function_arg). For these ABIs, we only need to remember the number
2788 of words passed so far.
2790 The EABI instead allocates the integer and floating-point arguments
2791 separately. The first N words of FP arguments go in FP registers,
2792 the rest go on the stack. Likewise, the first N words of the other
2793 arguments go in integer registers, and the rest go on the stack. We
2794 need to maintain three counts: the number of integer registers used,
2795 the number of floating-point registers used, and the number of words
2796 passed on the stack.
2798 We could keep separate information for the two ABIs (a word count for
2799 the standard ABIs, and three separate counts for the EABI). But it
2800 seems simpler to view the standard ABIs as forms of EABI that do not
2801 allocate floating-point registers.
2803 So for the standard ABIs, the first N words are allocated to integer
2804 registers, and function_arg decides on an argument-by-argument basis
2805 whether that argument should really go in an integer register, or in
2806 a floating-point one. */
2808 typedef struct mips_args {
2809 /* Always true for varargs functions. Otherwise true if at least
2810 one argument has been passed in an integer register. */
2813 /* The number of arguments seen so far. */
2814 unsigned int arg_number;
2816 /* For EABI, the number of integer registers used so far. For other
2817 ABIs, the number of words passed in registers (whether integer
2818 or floating-point). */
2819 unsigned int num_gprs;
2821 /* For EABI, the number of floating-point registers used so far. */
2822 unsigned int num_fprs;
2824 /* The number of words passed on the stack. */
2825 unsigned int stack_words;
2827 /* On the mips16, we need to keep track of which floating point
2828 arguments were passed in general registers, but would have been
2829 passed in the FP regs if this were a 32 bit function, so that we
2830 can move them to the FP regs if we wind up calling a 32 bit
2831 function. We record this information in fp_code, encoded in base
2832 four. A zero digit means no floating point argument, a one digit
2833 means an SFmode argument, and a two digit means a DFmode argument,
2834 and a three digit is not used. The low order digit is the first
2835 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2836 an SFmode argument. ??? A more sophisticated approach will be
2837 needed if MIPS_ABI != ABI_32. */
2840 /* True if the function has a prototype. */
2843 /* When a structure does not take up a full register, the argument
2844 should sometimes be shifted left so that it occupies the high part
2845 of the register. These two fields describe an array of ashl
2846 patterns for doing this. See function_arg_advance, which creates
2847 the shift patterns, and function_arg, which returns them when given
2848 a VOIDmode argument. */
2849 unsigned int num_adjusts;
2850 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2853 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2854 for a call to a function whose data type is FNTYPE.
2855 For a library call, FNTYPE is 0.
2859 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2860 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2862 /* Update the data in CUM to advance over an argument
2863 of mode MODE and data type TYPE.
2864 (TYPE is null for libcalls where that information may not be available.) */
2866 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2867 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2869 /* Determine where to put an argument to a function.
2870 Value is zero to push the argument on the stack,
2871 or a hard register in which to store the argument.
2873 MODE is the argument's machine mode.
2874 TYPE is the data type of the argument (as a tree).
2875 This is null for libcalls where that information may
2877 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2878 the preceding args and about the function being called.
2879 NAMED is nonzero if this argument is a named parameter
2880 (otherwise it is an extra parameter matching an ellipsis). */
2882 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2883 function_arg( &CUM, MODE, TYPE, NAMED)
2885 /* For an arg passed partly in registers and partly in memory,
2886 this is the number of registers used.
2887 For args passed entirely in registers or entirely in memory, zero. */
2889 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2890 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2892 /* If defined, a C expression that gives the alignment boundary, in
2893 bits, of an argument with the specified mode and type. If it is
2894 not defined, `PARM_BOUNDARY' is used for all arguments. */
2896 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2898 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2900 : TYPE_ALIGN(TYPE)) \
2901 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2903 : GET_MODE_ALIGNMENT(MODE)))
2905 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2906 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2908 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2909 (! BYTES_BIG_ENDIAN \
2911 : (((MODE) == BLKmode \
2912 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2913 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2914 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2915 && (mips_abi == ABI_32 \
2916 || mips_abi == ABI_O64 \
2917 || mips_abi == ABI_EABI \
2918 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2919 ? downward : upward))
2921 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2922 (mips_abi == ABI_EABI && (NAMED) \
2923 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2925 /* Modified version of the macro in expr.h. */
2926 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2928 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2929 || TREE_ADDRESSABLE (TYPE) \
2930 || ((MODE) == BLKmode \
2931 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2932 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2933 && 0 == (int_size_in_bytes (TYPE) \
2934 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2935 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2936 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2938 /* True if using EABI and varargs can be passed in floating-point
2939 registers. Under these conditions, we need a more complex form
2940 of va_list, which tracks GPR, FPR and stack arguments separately. */
2941 #define EABI_FLOAT_VARARGS_P \
2942 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2945 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2947 #define MUST_SAVE_REGISTER(regno) \
2948 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2949 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2950 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2952 /* Say that the epilogue uses the return address register. Note that
2953 in the case of sibcalls, the values "used by the epilogue" are
2954 considered live at the start of the called function. */
2955 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2957 /* Treat LOC as a byte offset from the stack pointer and round it up
2958 to the next fully-aligned offset. */
2959 #define MIPS_STACK_ALIGN(LOC) \
2960 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2961 ? ((LOC) + 7) & ~7 \
2962 : ((LOC) + 15) & ~15)
2965 /* Define the `__builtin_va_list' type for the ABI. */
2966 #define BUILD_VA_LIST_TYPE(VALIST) \
2967 (VALIST) = mips_build_va_list ()
2969 /* Implement `va_start' for varargs and stdarg. */
2970 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2971 mips_va_start (valist, nextarg)
2973 /* Implement `va_arg'. */
2974 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2975 mips_va_arg (valist, type)
2977 /* Output assembler code to FILE to increment profiler label # LABELNO
2978 for profiling a function entry. */
2980 #define FUNCTION_PROFILER(FILE, LABELNO) \
2982 if (TARGET_MIPS16) \
2983 sorry ("mips16 function profiling"); \
2984 fprintf (FILE, "\t.set\tnoat\n"); \
2985 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2986 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2987 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2990 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2991 TARGET_64BIT ? "dsubu" : "subu", \
2992 reg_names[STACK_POINTER_REGNUM], \
2993 reg_names[STACK_POINTER_REGNUM], \
2994 Pmode == DImode ? 16 : 8); \
2996 fprintf (FILE, "\tjal\t_mcount\n"); \
2997 fprintf (FILE, "\t.set\tat\n"); \
3000 /* Define this macro if the code for function profiling should come
3001 before the function prologue. Normally, the profiling code comes
3004 /* #define PROFILE_BEFORE_PROLOGUE */
3006 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
3007 the stack pointer does not matter. The value is tested only in
3008 functions that have frame pointers.
3009 No definition is equivalent to always zero. */
3011 #define EXIT_IGNORE_STACK 1
3014 /* A C statement to output, on the stream FILE, assembler code for a
3015 block of data that contains the constant parts of a trampoline.
3016 This code should not include a label--the label is taken care of
3019 #define TRAMPOLINE_TEMPLATE(STREAM) \
3021 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
3022 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
3023 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
3024 if (ptr_mode == DImode) \
3026 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
3027 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
3031 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
3032 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
3034 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
3035 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
3036 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
3037 if (ptr_mode == DImode) \
3039 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
3040 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
3044 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
3045 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
3049 /* A C expression for the size in bytes of the trampoline, as an
3052 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
3054 /* Alignment required for trampolines, in bits. */
3056 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
3058 /* INITIALIZE_TRAMPOLINE calls this library function to flush
3059 program and data caches. */
3061 #ifndef CACHE_FLUSH_FUNC
3062 #define CACHE_FLUSH_FUNC "_flush_cache"
3065 /* A C statement to initialize the variable parts of a trampoline.
3066 ADDR is an RTX for the address of the trampoline; FNADDR is an
3067 RTX for the address of the nested function; STATIC_CHAIN is an
3068 RTX for the static chain value that should be passed to the
3069 function when it is called. */
3071 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
3073 rtx func_addr, chain_addr; \
3075 func_addr = plus_constant (ADDR, 32); \
3076 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
3077 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
3078 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
3079 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
3080 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
3082 /* Flush both caches. We need to flush the data cache in case \
3083 the system has a write-back cache. */ \
3084 /* ??? Should check the return value for errors. */ \
3085 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
3086 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
3087 0, VOIDmode, 3, ADDR, Pmode, \
3088 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
3089 GEN_INT (3), TYPE_MODE (integer_type_node)); \
3092 /* Addressing modes, and classification of registers for them. */
3094 /* These assume that REGNO is a hard or pseudo reg number.
3095 They give nonzero only if REGNO is a hard reg of the suitable class
3096 or a pseudo reg currently allocated to a suitable hard reg.
3097 These definitions are NOT overridden anywhere. */
3099 #define BASE_REG_P(regno, mode) \
3101 ? (M16_REG_P (regno) \
3102 || (regno) == FRAME_POINTER_REGNUM \
3103 || (regno) == ARG_POINTER_REGNUM \
3104 || ((regno) == STACK_POINTER_REGNUM \
3105 && (GET_MODE_SIZE (mode) == 4 \
3106 || GET_MODE_SIZE (mode) == 8))) \
3109 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
3110 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3113 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3114 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3116 #define REGNO_OK_FOR_INDEX_P(regno) 0
3117 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3118 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3120 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3121 and check its validity for a certain class.
3122 We have two alternate definitions for each of them.
3123 The usual definition accepts all pseudo regs; the other rejects them all.
3124 The symbol REG_OK_STRICT causes the latter definition to be used.
3126 Most source files want to accept pseudo regs in the hope that
3127 they will get allocated to the class that the insn wants them to be in.
3128 Some source files that are used after register allocation
3129 need to be strict. */
3131 #ifndef REG_OK_STRICT
3132 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3133 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3135 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3136 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3139 #define REG_OK_FOR_INDEX_P(X) 0
3142 /* Maximum number of registers that can appear in a valid memory address. */
3144 #define MAX_REGS_PER_ADDRESS 1
3146 /* A C compound statement with a conditional `goto LABEL;' executed
3147 if X (an RTX) is a legitimate memory address on the target
3148 machine for a memory operand of mode MODE. */
3151 #define GO_PRINTF(x) fprintf(stderr, (x))
3152 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3153 #define GO_DEBUG_RTX(x) debug_rtx(x)
3156 #define GO_PRINTF(x)
3157 #define GO_PRINTF2(x,y)
3158 #define GO_DEBUG_RTX(x)
3161 #ifdef REG_OK_STRICT
3162 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3164 if (mips_legitimate_address_p (MODE, X, 1)) \
3168 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3170 if (mips_legitimate_address_p (MODE, X, 0)) \
3175 /* Check for constness inline but use mips_legitimate_address_p
3176 to check whether a constant really is an address. */
3178 #define CONSTANT_ADDRESS_P(X) \
3179 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
3182 /* Nonzero if the constant value X is a legitimate general operand.
3183 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3185 At present, GAS doesn't understand li.[sd], so don't allow it
3186 to be generated at present. Also, the MIPS assembler does not
3187 grok li.d Infinity. */
3189 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3190 Note that the Irix 6 assembler problem may already be fixed.
3191 Note also that the GET_CODE (X) == CONST test catches the mips16
3192 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3193 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3194 ABI_64 to work together, we'll need to fix this. */
3195 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
3197 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3199 if (mips_legitimize_address (&(X), MODE)) \
3204 /* A C statement or compound statement with a conditional `goto
3205 LABEL;' executed if memory address X (an RTX) can have different
3206 meanings depending on the machine mode of the memory reference it
3209 Autoincrement and autodecrement addresses typically have
3210 mode-dependent effects because the amount of the increment or
3211 decrement is the size of the operand being addressed. Some
3212 machines have other mode-dependent addresses. Many RISC machines
3213 have no mode-dependent addresses.
3215 You may assume that ADDR is a valid address for the machine. */
3217 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3219 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3220 'the start of the function that this code is output in'. */
3222 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3223 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3224 asm_fprintf ((FILE), "%U%s", \
3225 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3227 asm_fprintf ((FILE), "%U%s", (NAME))
3229 /* The mips16 wants the constant pool to be after the function,
3230 because the PC relative load instructions use unsigned offsets. */
3232 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3234 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3235 mips_string_length = 0;
3237 /* Specify the machine mode that this machine uses
3238 for the index in the tablejump instruction.
3239 ??? Using HImode in mips16 mode can cause overflow. However, the
3240 overflow is no more likely than the overflow in a branch
3241 instruction. Large functions can currently break in both ways. */
3242 #define CASE_VECTOR_MODE \
3243 (TARGET_MIPS16 ? HImode : ptr_mode)
3245 /* Define as C expression which evaluates to nonzero if the tablejump
3246 instruction expects the table to contain offsets from the address of the
3248 Do not define this if the table should contain absolute addresses. */
3249 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3251 /* Define this as 1 if `char' should by default be signed; else as 0. */
3252 #ifndef DEFAULT_SIGNED_CHAR
3253 #define DEFAULT_SIGNED_CHAR 1
3256 /* Max number of bytes we can move from memory to memory
3257 in one reasonably fast instruction. */
3258 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3259 #define MAX_MOVE_MAX 8
3261 /* Define this macro as a C expression which is nonzero if
3262 accessing less than a word of memory (i.e. a `char' or a
3263 `short') is no faster than accessing a word of memory, i.e., if
3264 such access require more than one instruction or if there is no
3265 difference in cost between byte and (aligned) word loads.
3267 On RISC machines, it tends to generate better code to define
3268 this as 1, since it avoids making a QI or HI mode register. */
3269 #define SLOW_BYTE_ACCESS 1
3271 /* We assume that the store-condition-codes instructions store 0 for false
3272 and some other value for true. This is the value stored for true. */
3274 #define STORE_FLAG_VALUE 1
3276 /* Define this to be nonzero if shift instructions ignore all but the low-order
3278 #define SHIFT_COUNT_TRUNCATED 1
3280 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3281 is done just by pretending it is already truncated. */
3282 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3283 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3286 /* Specify the machine mode that pointers have.
3287 After generation of rtl, the compiler makes no further distinction
3288 between pointers and any other objects of this machine mode. */
3291 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
3294 /* Give call MEMs SImode since it is the "most permissive" mode
3295 for both 32-bit and 64-bit targets. */
3297 #define FUNCTION_MODE SImode
3300 /* The cost of loading values from the constant pool. It should be
3301 larger than the cost of any constant we want to synthesise in-line. */
3303 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
3305 /* A C expression for the cost of moving data from a register in
3306 class FROM to one in class TO. The classes are expressed using
3307 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3308 the default; other values are interpreted relative to that.
3310 It is not required that the cost always equal 2 when FROM is the
3311 same as TO; on some machines it is expensive to move between
3312 registers if they are not general registers.
3314 If reload sees an insn consisting of a single `set' between two
3315 hard registers, and if `REGISTER_MOVE_COST' applied to their
3316 classes returns a value of 2, reload does not check to ensure
3317 that the constraints of the insn are met. Setting a cost of
3318 other than 2 will allow reload to verify that the constraints are
3319 met. You should do this if the `movM' pattern's constraints do
3320 not allow such copying. */
3322 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3323 mips_register_move_cost (MODE, FROM, TO)
3325 /* ??? Fix this to be right for the R8000. */
3326 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3327 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3328 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3330 /* Define if copies to/from condition code registers should be avoided.
3332 This is needed for the MIPS because reload_outcc is not complete;
3333 it needs to handle cases where the source is a general or another
3334 condition code register. */
3335 #define AVOID_CCMODE_COPIES
3337 /* A C expression for the cost of a branch instruction. A value of
3338 1 is the default; other values are interpreted relative to that. */
3340 /* ??? Fix this to be right for the R8000. */
3341 #define BRANCH_COST \
3343 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3346 /* If defined, modifies the length assigned to instruction INSN as a
3347 function of the context in which it is used. LENGTH is an lvalue
3348 that contains the initially computed length of the insn and should
3349 be updated with the correct length of the insn. */
3350 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3351 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3354 /* Optionally define this if you have added predicates to
3355 `MACHINE.c'. This macro is called within an initializer of an
3356 array of structures. The first field in the structure is the
3357 name of a predicate and the second field is an array of rtl
3358 codes. For each predicate, list all rtl codes that can be in
3359 expressions matched by the predicate. The list should have a
3360 trailing comma. Here is an example of two entries in the list
3361 for a typical RISC machine:
3363 #define PREDICATE_CODES \
3364 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3365 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3367 Defining this macro does not affect the generated code (however,
3368 incorrect definitions that omit an rtl code that may be matched
3369 by the predicate can cause the compiler to malfunction).
3370 Instead, it allows the table built by `genrecog' to be more
3371 compact and efficient, thus speeding up the compiler. The most
3372 important predicates to include in the list specified by this
3373 macro are thoses used in the most insn patterns. */
3375 #define PREDICATE_CODES \
3376 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3377 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3378 {"const_arith_operand", { CONST, CONST_INT }}, \
3379 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3380 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3381 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3382 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3383 {"small_int", { CONST_INT }}, \
3384 {"large_int", { CONST_INT }}, \
3385 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3386 {"const_float_1_operand", { CONST_DOUBLE }}, \
3387 {"simple_memory_operand", { MEM, SUBREG }}, \
3388 {"equality_op", { EQ, NE }}, \
3389 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3391 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3392 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3393 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
3394 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3395 SYMBOL_REF, LABEL_REF, SUBREG, \
3397 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3398 CONST_DOUBLE, CONST }}, \
3399 {"fcc_register_operand", { REG, SUBREG }},
3401 /* A list of predicates that do special things with modes, and so
3402 should not elicit warnings for VOIDmode match_operand. */
3404 #define SPECIAL_MODE_PREDICATES \
3405 "pc_or_label_operand",
3408 /* If defined, a C statement to be executed just prior to the
3409 output of assembler code for INSN, to modify the extracted
3410 operands so they will be output differently.
3412 Here the argument OPVEC is the vector containing the operands
3413 extracted from INSN, and NOPERANDS is the number of elements of
3414 the vector which contain meaningful data for this insn. The
3415 contents of this vector are what will be used to convert the
3416 insn template into assembler code, so you can change the
3417 assembler output by changing the contents of the vector.
3419 We use it to check if the current insn needs a nop in front of it
3420 because of load delays, and also to update the delay slot
3423 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3424 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3427 /* Control the assembler format that we output. */
3429 /* Output at beginning of assembler file.
3430 If we are optimizing to use the global pointer, create a temporary
3431 file to hold all of the text stuff, and write it out to the end.
3432 This is needed because the MIPS assembler is evidently one pass,
3433 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3434 declaration when the code is processed, it generates a two
3435 instruction sequence. */
3437 #undef ASM_FILE_START
3438 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3440 /* Output to assembler file text saying following lines
3441 may contain character constants, extra white space, comments, etc. */
3444 #define ASM_APP_ON " #APP\n"
3447 /* Output to assembler file text saying following lines
3448 no longer contain unusual constructs. */
3451 #define ASM_APP_OFF " #NO_APP\n"
3454 /* How to refer to registers in assembler output.
3455 This sequence is indexed by compiler's hard-register-number (see above).
3457 In order to support the two different conventions for register names,
3458 we use the name of a table set up in mips.c, which is overwritten
3459 if -mrnames is used. */
3461 #define REGISTER_NAMES \
3463 &mips_reg_names[ 0][0], \
3464 &mips_reg_names[ 1][0], \
3465 &mips_reg_names[ 2][0], \
3466 &mips_reg_names[ 3][0], \
3467 &mips_reg_names[ 4][0], \
3468 &mips_reg_names[ 5][0], \
3469 &mips_reg_names[ 6][0], \
3470 &mips_reg_names[ 7][0], \
3471 &mips_reg_names[ 8][0], \
3472 &mips_reg_names[ 9][0], \
3473 &mips_reg_names[10][0], \
3474 &mips_reg_names[11][0], \
3475 &mips_reg_names[12][0], \
3476 &mips_reg_names[13][0], \
3477 &mips_reg_names[14][0], \
3478 &mips_reg_names[15][0], \
3479 &mips_reg_names[16][0], \
3480 &mips_reg_names[17][0], \
3481 &mips_reg_names[18][0], \
3482 &mips_reg_names[19][0], \
3483 &mips_reg_names[20][0], \
3484 &mips_reg_names[21][0], \
3485 &mips_reg_names[22][0], \
3486 &mips_reg_names[23][0], \
3487 &mips_reg_names[24][0], \
3488 &mips_reg_names[25][0], \
3489 &mips_reg_names[26][0], \
3490 &mips_reg_names[27][0], \
3491 &mips_reg_names[28][0], \
3492 &mips_reg_names[29][0], \
3493 &mips_reg_names[30][0], \
3494 &mips_reg_names[31][0], \
3495 &mips_reg_names[32][0], \
3496 &mips_reg_names[33][0], \
3497 &mips_reg_names[34][0], \
3498 &mips_reg_names[35][0], \
3499 &mips_reg_names[36][0], \
3500 &mips_reg_names[37][0], \
3501 &mips_reg_names[38][0], \
3502 &mips_reg_names[39][0], \
3503 &mips_reg_names[40][0], \
3504 &mips_reg_names[41][0], \
3505 &mips_reg_names[42][0], \
3506 &mips_reg_names[43][0], \
3507 &mips_reg_names[44][0], \
3508 &mips_reg_names[45][0], \
3509 &mips_reg_names[46][0], \
3510 &mips_reg_names[47][0], \
3511 &mips_reg_names[48][0], \
3512 &mips_reg_names[49][0], \
3513 &mips_reg_names[50][0], \
3514 &mips_reg_names[51][0], \
3515 &mips_reg_names[52][0], \
3516 &mips_reg_names[53][0], \
3517 &mips_reg_names[54][0], \
3518 &mips_reg_names[55][0], \
3519 &mips_reg_names[56][0], \
3520 &mips_reg_names[57][0], \
3521 &mips_reg_names[58][0], \
3522 &mips_reg_names[59][0], \
3523 &mips_reg_names[60][0], \
3524 &mips_reg_names[61][0], \
3525 &mips_reg_names[62][0], \
3526 &mips_reg_names[63][0], \
3527 &mips_reg_names[64][0], \
3528 &mips_reg_names[65][0], \
3529 &mips_reg_names[66][0], \
3530 &mips_reg_names[67][0], \
3531 &mips_reg_names[68][0], \
3532 &mips_reg_names[69][0], \
3533 &mips_reg_names[70][0], \
3534 &mips_reg_names[71][0], \
3535 &mips_reg_names[72][0], \
3536 &mips_reg_names[73][0], \
3537 &mips_reg_names[74][0], \
3538 &mips_reg_names[75][0], \
3539 &mips_reg_names[76][0], \
3540 &mips_reg_names[77][0], \
3541 &mips_reg_names[78][0], \
3542 &mips_reg_names[79][0], \
3543 &mips_reg_names[80][0], \
3544 &mips_reg_names[81][0], \
3545 &mips_reg_names[82][0], \
3546 &mips_reg_names[83][0], \
3547 &mips_reg_names[84][0], \
3548 &mips_reg_names[85][0], \
3549 &mips_reg_names[86][0], \
3550 &mips_reg_names[87][0], \
3551 &mips_reg_names[88][0], \
3552 &mips_reg_names[89][0], \
3553 &mips_reg_names[90][0], \
3554 &mips_reg_names[91][0], \
3555 &mips_reg_names[92][0], \
3556 &mips_reg_names[93][0], \
3557 &mips_reg_names[94][0], \
3558 &mips_reg_names[95][0], \
3559 &mips_reg_names[96][0], \
3560 &mips_reg_names[97][0], \
3561 &mips_reg_names[98][0], \
3562 &mips_reg_names[99][0], \
3563 &mips_reg_names[100][0], \
3564 &mips_reg_names[101][0], \
3565 &mips_reg_names[102][0], \
3566 &mips_reg_names[103][0], \
3567 &mips_reg_names[104][0], \
3568 &mips_reg_names[105][0], \
3569 &mips_reg_names[106][0], \
3570 &mips_reg_names[107][0], \
3571 &mips_reg_names[108][0], \
3572 &mips_reg_names[109][0], \
3573 &mips_reg_names[110][0], \
3574 &mips_reg_names[111][0], \
3575 &mips_reg_names[112][0], \
3576 &mips_reg_names[113][0], \
3577 &mips_reg_names[114][0], \
3578 &mips_reg_names[115][0], \
3579 &mips_reg_names[116][0], \
3580 &mips_reg_names[117][0], \
3581 &mips_reg_names[118][0], \
3582 &mips_reg_names[119][0], \
3583 &mips_reg_names[120][0], \
3584 &mips_reg_names[121][0], \
3585 &mips_reg_names[122][0], \
3586 &mips_reg_names[123][0], \
3587 &mips_reg_names[124][0], \
3588 &mips_reg_names[125][0], \
3589 &mips_reg_names[126][0], \
3590 &mips_reg_names[127][0], \
3591 &mips_reg_names[128][0], \
3592 &mips_reg_names[129][0], \
3593 &mips_reg_names[130][0], \
3594 &mips_reg_names[131][0], \
3595 &mips_reg_names[132][0], \
3596 &mips_reg_names[133][0], \
3597 &mips_reg_names[134][0], \
3598 &mips_reg_names[135][0], \
3599 &mips_reg_names[136][0], \
3600 &mips_reg_names[137][0], \
3601 &mips_reg_names[138][0], \
3602 &mips_reg_names[139][0], \
3603 &mips_reg_names[140][0], \
3604 &mips_reg_names[141][0], \
3605 &mips_reg_names[142][0], \
3606 &mips_reg_names[143][0], \
3607 &mips_reg_names[144][0], \
3608 &mips_reg_names[145][0], \
3609 &mips_reg_names[146][0], \
3610 &mips_reg_names[147][0], \
3611 &mips_reg_names[148][0], \
3612 &mips_reg_names[149][0], \
3613 &mips_reg_names[150][0], \
3614 &mips_reg_names[151][0], \
3615 &mips_reg_names[152][0], \
3616 &mips_reg_names[153][0], \
3617 &mips_reg_names[154][0], \
3618 &mips_reg_names[155][0], \
3619 &mips_reg_names[156][0], \
3620 &mips_reg_names[157][0], \
3621 &mips_reg_names[158][0], \
3622 &mips_reg_names[159][0], \
3623 &mips_reg_names[160][0], \
3624 &mips_reg_names[161][0], \
3625 &mips_reg_names[162][0], \
3626 &mips_reg_names[163][0], \
3627 &mips_reg_names[164][0], \
3628 &mips_reg_names[165][0], \
3629 &mips_reg_names[166][0], \
3630 &mips_reg_names[167][0], \
3631 &mips_reg_names[168][0], \
3632 &mips_reg_names[169][0], \
3633 &mips_reg_names[170][0], \
3634 &mips_reg_names[171][0], \
3635 &mips_reg_names[172][0], \
3636 &mips_reg_names[173][0], \
3637 &mips_reg_names[174][0], \
3638 &mips_reg_names[175][0] \
3641 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3642 So define this for it. */
3643 #define DEBUG_REGISTER_NAMES \
3645 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3646 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3647 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3648 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3649 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3650 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3651 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3652 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3653 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3654 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3655 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3656 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3657 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3658 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3659 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3660 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3661 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3662 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3663 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3664 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3665 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3666 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3669 /* If defined, a C initializer for an array of structures
3670 containing a name and a register number. This macro defines
3671 additional names for hard registers, thus allowing the `asm'
3672 option in declarations to refer to registers using alternate
3675 We define both names for the integer registers here. */
3677 #define ADDITIONAL_REGISTER_NAMES \
3679 { "$0", 0 + GP_REG_FIRST }, \
3680 { "$1", 1 + GP_REG_FIRST }, \
3681 { "$2", 2 + GP_REG_FIRST }, \
3682 { "$3", 3 + GP_REG_FIRST }, \
3683 { "$4", 4 + GP_REG_FIRST }, \
3684 { "$5", 5 + GP_REG_FIRST }, \
3685 { "$6", 6 + GP_REG_FIRST }, \
3686 { "$7", 7 + GP_REG_FIRST }, \
3687 { "$8", 8 + GP_REG_FIRST }, \
3688 { "$9", 9 + GP_REG_FIRST }, \
3689 { "$10", 10 + GP_REG_FIRST }, \
3690 { "$11", 11 + GP_REG_FIRST }, \
3691 { "$12", 12 + GP_REG_FIRST }, \
3692 { "$13", 13 + GP_REG_FIRST }, \
3693 { "$14", 14 + GP_REG_FIRST }, \
3694 { "$15", 15 + GP_REG_FIRST }, \
3695 { "$16", 16 + GP_REG_FIRST }, \
3696 { "$17", 17 + GP_REG_FIRST }, \
3697 { "$18", 18 + GP_REG_FIRST }, \
3698 { "$19", 19 + GP_REG_FIRST }, \
3699 { "$20", 20 + GP_REG_FIRST }, \
3700 { "$21", 21 + GP_REG_FIRST }, \
3701 { "$22", 22 + GP_REG_FIRST }, \
3702 { "$23", 23 + GP_REG_FIRST }, \
3703 { "$24", 24 + GP_REG_FIRST }, \
3704 { "$25", 25 + GP_REG_FIRST }, \
3705 { "$26", 26 + GP_REG_FIRST }, \
3706 { "$27", 27 + GP_REG_FIRST }, \
3707 { "$28", 28 + GP_REG_FIRST }, \
3708 { "$29", 29 + GP_REG_FIRST }, \
3709 { "$30", 30 + GP_REG_FIRST }, \
3710 { "$31", 31 + GP_REG_FIRST }, \
3711 { "$sp", 29 + GP_REG_FIRST }, \
3712 { "$fp", 30 + GP_REG_FIRST }, \
3713 { "at", 1 + GP_REG_FIRST }, \
3714 { "v0", 2 + GP_REG_FIRST }, \
3715 { "v1", 3 + GP_REG_FIRST }, \
3716 { "a0", 4 + GP_REG_FIRST }, \
3717 { "a1", 5 + GP_REG_FIRST }, \
3718 { "a2", 6 + GP_REG_FIRST }, \
3719 { "a3", 7 + GP_REG_FIRST }, \
3720 { "t0", 8 + GP_REG_FIRST }, \
3721 { "t1", 9 + GP_REG_FIRST }, \
3722 { "t2", 10 + GP_REG_FIRST }, \
3723 { "t3", 11 + GP_REG_FIRST }, \
3724 { "t4", 12 + GP_REG_FIRST }, \
3725 { "t5", 13 + GP_REG_FIRST }, \
3726 { "t6", 14 + GP_REG_FIRST }, \
3727 { "t7", 15 + GP_REG_FIRST }, \
3728 { "s0", 16 + GP_REG_FIRST }, \
3729 { "s1", 17 + GP_REG_FIRST }, \
3730 { "s2", 18 + GP_REG_FIRST }, \
3731 { "s3", 19 + GP_REG_FIRST }, \
3732 { "s4", 20 + GP_REG_FIRST }, \
3733 { "s5", 21 + GP_REG_FIRST }, \
3734 { "s6", 22 + GP_REG_FIRST }, \
3735 { "s7", 23 + GP_REG_FIRST }, \
3736 { "t8", 24 + GP_REG_FIRST }, \
3737 { "t9", 25 + GP_REG_FIRST }, \
3738 { "k0", 26 + GP_REG_FIRST }, \
3739 { "k1", 27 + GP_REG_FIRST }, \
3740 { "gp", 28 + GP_REG_FIRST }, \
3741 { "sp", 29 + GP_REG_FIRST }, \
3742 { "fp", 30 + GP_REG_FIRST }, \
3743 { "ra", 31 + GP_REG_FIRST }, \
3744 { "$sp", 29 + GP_REG_FIRST }, \
3745 { "$fp", 30 + GP_REG_FIRST } \
3746 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3749 /* This is meant to be redefined in the host dependent files. It is a
3750 set of alternative names and regnums for mips coprocessors. */
3752 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3754 /* A C compound statement to output to stdio stream STREAM the
3755 assembler syntax for an instruction operand X. X is an RTL
3758 CODE is a value that can be used to specify one of several ways
3759 of printing the operand. It is used when identical operands
3760 must be printed differently depending on the context. CODE
3761 comes from the `%' specification that was used to request
3762 printing of the operand. If the specification was just `%DIGIT'
3763 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3764 is the ASCII code for LTR.
3766 If X is a register, this macro should print the register's name.
3767 The names can be found in an array `reg_names' whose type is
3768 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3770 When the machine description has a specification `%PUNCT' (a `%'
3771 followed by a punctuation character), this macro is called with
3772 a null pointer for X and the punctuation character for CODE.
3774 See mips.c for the MIPS specific codes. */
3776 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3778 /* A C expression which evaluates to true if CODE is a valid
3779 punctuation character for use in the `PRINT_OPERAND' macro. If
3780 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3781 punctuation characters (except for the standard one, `%') are
3782 used in this way. */
3784 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3786 /* A C compound statement to output to stdio stream STREAM the
3787 assembler syntax for an instruction operand that is a memory
3788 reference whose address is ADDR. ADDR is an RTL expression. */
3790 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3793 /* A C statement, to be executed after all slot-filler instructions
3794 have been output. If necessary, call `dbr_sequence_length' to
3795 determine the number of slots filled in a sequence (zero if not
3796 currently outputting a sequence), to decide how many no-ops to
3797 output, or whatever.
3799 Don't define this macro if it has nothing to do, but it is
3800 helpful in reading assembly output if the extent of the delay
3801 sequence is made explicit (e.g. with white space).
3803 Note that output routines for instructions with delay slots must
3804 be prepared to deal with not being output as part of a sequence
3805 (i.e. when the scheduling pass is not run, or when no slot
3806 fillers could be found.) The variable `final_sequence' is null
3807 when not processing a sequence, otherwise it contains the
3808 `sequence' rtx being output. */
3810 #define DBR_OUTPUT_SEQEND(STREAM) \
3813 if (set_nomacro > 0 && --set_nomacro == 0) \
3814 fputs ("\t.set\tmacro\n", STREAM); \
3816 if (set_noreorder > 0 && --set_noreorder == 0) \
3817 fputs ("\t.set\treorder\n", STREAM); \
3819 dslots_jump_filled++; \
3820 fputs ("\n", STREAM); \
3825 /* How to tell the debugger about changes of source files. Note, the
3826 mips ECOFF format cannot deal with changes of files inside of
3827 functions, which means the output of parser generators like bison
3828 is generally not debuggable without using the -l switch. Lose,
3829 lose, lose. Silicon graphics seems to want all .file's hardwired
3832 #ifndef SET_FILE_NUMBER
3833 #define SET_FILE_NUMBER() ++num_source_filenames
3836 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3837 mips_output_filename (STREAM, NAME)
3839 /* This is defined so that it can be overridden in iris6.h. */
3840 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3843 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3844 output_quoted_string (STREAM, NAME); \
3845 fputs ("\n", STREAM); \
3849 /* This is how to output a note the debugger telling it the line number
3850 to which the following sequence of instructions corresponds.
3851 Silicon graphics puts a label after each .loc. */
3853 #ifndef LABEL_AFTER_LOC
3854 #define LABEL_AFTER_LOC(STREAM)
3857 #ifndef ASM_OUTPUT_SOURCE_LINE
3858 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3859 mips_output_lineno (STREAM, LINE)
3862 /* The MIPS implementation uses some labels for its own purpose. The
3863 following lists what labels are created, and are all formed by the
3864 pattern $L[a-z].*. The machine independent portion of GCC creates
3865 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3867 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3868 $Lb[0-9]+ Begin blocks for MIPS debug support
3869 $Lc[0-9]+ Label for use in s<xx> operation.
3870 $Le[0-9]+ End blocks for MIPS debug support */
3872 /* A C statement (sans semicolon) to output to the stdio stream
3873 STREAM any text necessary for declaring the name NAME of an
3874 initialized variable which is being defined. This macro must
3875 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3876 The argument DECL is the `VAR_DECL' tree node representing the
3879 If this macro is not defined, then the variable name is defined
3880 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3882 #undef ASM_DECLARE_OBJECT_NAME
3883 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3886 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3890 /* Globalizing directive for a label. */
3891 #define GLOBAL_ASM_OP "\t.globl\t"
3893 /* This says how to define a global common symbol. */
3895 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3897 /* If the target wants uninitialized const declarations in \
3898 .rdata then don't put them in .comm */ \
3899 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3900 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3901 && (DECL_INITIAL (DECL) == 0 \
3902 || DECL_INITIAL (DECL) == error_mark_node)) \
3904 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3905 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3907 readonly_data_section (); \
3908 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3909 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3913 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3918 /* This says how to define a local common symbol (ie, not visible to
3921 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3922 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
3925 /* This says how to output an external. It would be possible not to
3926 output anything and let undefined symbol become external. However
3927 the assembler uses length information on externals to allocate in
3928 data/sdata bss/sbss, thereby saving exec time. */
3930 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3931 mips_output_external(STREAM,DECL,NAME)
3933 /* This says what to print at the end of the assembly file */
3935 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
3938 /* Play switch file games if we're optimizing the global pointer. */
3941 #define TEXT_SECTION() \
3943 extern FILE *asm_out_text_file; \
3944 if (TARGET_FILE_SWITCHING) \
3945 asm_out_file = asm_out_text_file; \
3946 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
3947 fputc ('\n', asm_out_file); \
3951 /* This is how to declare a function name. The actual work of
3952 emitting the label is moved to function_prologue, so that we can
3953 get the line number correctly emitted before the .ent directive,
3954 and after any .file directives. Define as empty so that the function
3955 is not declared before the .ent directive elsewhere. */
3957 #undef ASM_DECLARE_FUNCTION_NAME
3958 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3960 /* This is how to store into the string LABEL
3961 the symbol_ref name of an internal numbered label where
3962 PREFIX is the class of label and NUM is the number within the class.
3963 This is suitable for output with `assemble_name'. */
3965 #undef ASM_GENERATE_INTERNAL_LABEL
3966 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3967 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3969 /* This is how to output an element of a case-vector that is absolute. */
3971 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3972 fprintf (STREAM, "\t%s\t%sL%d\n", \
3973 ptr_mode == DImode ? ".dword" : ".word", \
3974 LOCAL_LABEL_PREFIX, \
3977 /* This is how to output an element of a case-vector that is relative.
3978 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3979 TARGET_EMBEDDED_PIC). */
3981 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3983 if (TARGET_MIPS16) \
3984 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3985 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3986 else if (TARGET_EMBEDDED_PIC) \
3987 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3988 ptr_mode == DImode ? ".dword" : ".word", \
3989 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3990 else if (TARGET_GPWORD) \
3991 fprintf (STREAM, "\t%s\t%sL%d\n", \
3992 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3993 LOCAL_LABEL_PREFIX, VALUE); \
3995 fprintf (STREAM, "\t%s\t%sL%d\n", \
3996 ptr_mode == DImode ? ".dword" : ".word", \
3997 LOCAL_LABEL_PREFIX, VALUE); \
4000 /* When generating embedded PIC or mips16 code we want to put the jump
4001 table in the .text section. In all other cases, we want to put the
4002 jump table in the .rdata section. Unfortunately, we can't use
4003 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4004 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4005 section if appropriate. */
4006 #undef ASM_OUTPUT_CASE_LABEL
4007 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4009 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4010 function_section (current_function_decl); \
4011 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
4014 /* This is how to output an assembler line
4015 that says to advance the location counter
4016 to a multiple of 2**LOG bytes. */
4018 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4019 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4021 /* This is how to output an assembler line to advance the location
4022 counter by SIZE bytes. */
4024 #undef ASM_OUTPUT_SKIP
4025 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4026 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4028 /* This is how to output a string. */
4029 #undef ASM_OUTPUT_ASCII
4030 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4031 mips_output_ascii (STREAM, STRING, LEN)
4033 /* Output #ident as a in the read-only data section. */
4034 #undef ASM_OUTPUT_IDENT
4035 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4037 const char *p = STRING; \
4038 int size = strlen (p) + 1; \
4039 readonly_data_section (); \
4040 assemble_string (p, size); \
4043 /* Default to -G 8 */
4044 #ifndef MIPS_DEFAULT_GVALUE
4045 #define MIPS_DEFAULT_GVALUE 8
4048 /* Define the strings to put out for each section in the object file. */
4049 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4050 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4051 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4053 #undef READONLY_DATA_SECTION_ASM_OP
4054 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4056 #define SMALL_DATA_SECTION sdata_section
4058 /* What other sections we support other than the normal .data/.text. */
4060 #undef EXTRA_SECTIONS
4061 #define EXTRA_SECTIONS in_sdata
4063 /* Define the additional functions to select our additional sections. */
4065 /* on the MIPS it is not a good idea to put constants in the text
4066 section, since this defeats the sdata/data mechanism. This is
4067 especially true when -O is used. In this case an effort is made to
4068 address with faster (gp) register relative addressing, which can
4069 only get at sdata and sbss items (there is no stext !!) However,
4070 if the constant is too large for sdata, and it's readonly, it
4071 will go into the .rdata section. */
4073 #undef EXTRA_SECTION_FUNCTIONS
4074 #define EXTRA_SECTION_FUNCTIONS \
4078 if (in_section != in_sdata) \
4080 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4081 in_section = in_sdata; \
4085 /* Given a decl node or constant node, choose the section to output it in
4086 and select that section. */
4088 #undef TARGET_ASM_SELECT_SECTION
4089 #define TARGET_ASM_SELECT_SECTION mips_select_section
4091 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4094 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4095 TARGET_64BIT ? "dsubu" : "subu", \
4096 reg_names[STACK_POINTER_REGNUM], \
4097 reg_names[STACK_POINTER_REGNUM], \
4098 TARGET_64BIT ? "sd" : "sw", \
4100 reg_names[STACK_POINTER_REGNUM]); \
4104 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4107 if (! set_noreorder) \
4108 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4110 dslots_load_total++; \
4111 dslots_load_filled++; \
4112 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4113 TARGET_64BIT ? "ld" : "lw", \
4115 reg_names[STACK_POINTER_REGNUM], \
4116 TARGET_64BIT ? "daddu" : "addu", \
4117 reg_names[STACK_POINTER_REGNUM], \
4118 reg_names[STACK_POINTER_REGNUM]); \
4120 if (! set_noreorder) \
4121 fprintf (STREAM, "\t.set\treorder\n"); \
4125 /* How to start an assembler comment.
4126 The leading space is important (the mips native assembler requires it). */
4127 #ifndef ASM_COMMENT_START
4128 #define ASM_COMMENT_START " #"
4132 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4133 and mips-tdump.c to print them out.
4135 These must match the corresponding definitions in gdb/mipsread.c.
4136 Unfortunately, gcc and gdb do not currently share any directories. */
4138 #define CODE_MASK 0x8F300
4139 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4140 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4141 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4144 /* Default definitions for size_t and ptrdiff_t. We must override the
4145 definitions from ../svr4.h on mips-*-linux-gnu. */
4148 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
4151 #ifndef PTRDIFF_TYPE
4152 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
4155 /* See mips_expand_prologue's use of loadgp for when this should be
4158 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4159 && mips_abi != ABI_32 \
4160 && mips_abi != ABI_O64)
4162 /* In mips16 mode, we need to look through the function to check for
4163 PC relative loads that are out of range. */
4164 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4166 /* We need to use a special set of functions to handle hard floating
4167 point code in mips16 mode. */
4169 #ifndef INIT_SUBTARGET_OPTABS
4170 #define INIT_SUBTARGET_OPTABS
4173 #define INIT_TARGET_OPTABS \
4176 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4177 INIT_SUBTARGET_OPTABS; \
4180 add_optab->handlers[(int) SFmode].libfunc = \
4181 init_one_libfunc ("__mips16_addsf3"); \
4182 sub_optab->handlers[(int) SFmode].libfunc = \
4183 init_one_libfunc ("__mips16_subsf3"); \
4184 smul_optab->handlers[(int) SFmode].libfunc = \
4185 init_one_libfunc ("__mips16_mulsf3"); \
4186 sdiv_optab->handlers[(int) SFmode].libfunc = \
4187 init_one_libfunc ("__mips16_divsf3"); \
4189 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4190 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4191 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4192 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4193 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4194 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4196 floatsisf_libfunc = \
4197 init_one_libfunc ("__mips16_floatsisf"); \
4199 init_one_libfunc ("__mips16_fixsfsi"); \
4201 if (TARGET_DOUBLE_FLOAT) \
4203 add_optab->handlers[(int) DFmode].libfunc = \
4204 init_one_libfunc ("__mips16_adddf3"); \
4205 sub_optab->handlers[(int) DFmode].libfunc = \
4206 init_one_libfunc ("__mips16_subdf3"); \
4207 smul_optab->handlers[(int) DFmode].libfunc = \
4208 init_one_libfunc ("__mips16_muldf3"); \
4209 sdiv_optab->handlers[(int) DFmode].libfunc = \
4210 init_one_libfunc ("__mips16_divdf3"); \
4212 extendsfdf2_libfunc = \
4213 init_one_libfunc ("__mips16_extendsfdf2"); \
4214 truncdfsf2_libfunc = \
4215 init_one_libfunc ("__mips16_truncdfsf2"); \
4218 init_one_libfunc ("__mips16_eqdf2"); \
4220 init_one_libfunc ("__mips16_nedf2"); \
4222 init_one_libfunc ("__mips16_gtdf2"); \
4224 init_one_libfunc ("__mips16_gedf2"); \
4226 init_one_libfunc ("__mips16_ltdf2"); \
4228 init_one_libfunc ("__mips16_ledf2"); \
4230 floatsidf_libfunc = \
4231 init_one_libfunc ("__mips16_floatsidf"); \
4233 init_one_libfunc ("__mips16_fixdfsi"); \
4239 #define DFMODE_NAN \
4240 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4241 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4242 #define SFMODE_NAN \
4243 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4244 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4246 /* Generate calls to memcpy, etc., not bcopy, etc. */
4247 #define TARGET_MEM_FUNCTIONS
4250 /* Since the bits of the _init and _fini function is spread across
4251 many object files, each potentially with its own GP, we must assume
4252 we need to load our GP. We don't preserve $gp or $ra, since each
4253 init/fini chunk is supposed to initialize $gp, and crti/crtn
4254 already take care of preserving $ra and, when appropriate, $gp. */
4255 #if _MIPS_SIM == _MIPS_SIM_ABI32
4256 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4257 asm (SECTION_OP "\n\
4263 jal " USER_LABEL_PREFIX #FUNC "\n\
4264 " TEXT_SECTION_ASM_OP);
4265 #endif /* Switch to #elif when we're no longer limited by K&R C. */
4266 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4267 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4268 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4269 asm (SECTION_OP "\n\
4274 .cpsetup $31, $2, 1b\n\
4275 jal " USER_LABEL_PREFIX #FUNC "\n\
4276 " TEXT_SECTION_ASM_OP);