1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
76 /* Recast the cpu class to be the cpu attribute. */
77 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
79 /* Which ABI to use. These are constants because abi64.h must check their
80 value at preprocessing time.
82 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
83 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
90 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
91 which is not the same as the above EABI (defined by Cygnus,
92 Greenhills, and Toshiba?). MEABI is not yet complete or published,
93 but at this point it looks like N32 as far as calling conventions go,
94 but allows for either 32 or 64 bit registers.
96 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
97 EABI the legacy EABI. In the end we may end up calling both ABI's
98 EABI but give them different version numbers, but for now I'm going
99 with different names. */
103 #ifndef MIPS_ABI_DEFAULT
104 /* We define this away so that there is no extra runtime cost if the target
105 doesn't support multiple ABIs. */
106 #define mips_abi ABI_32
111 /* Whether to emit abicalls code sequences or not. */
113 enum mips_abicalls_type {
118 /* Recast the abicalls class to be the abicalls attribute. */
119 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
121 /* Which type of block move to do (whether or not the last store is
122 split out so it can fill a branch delay slot). */
124 enum block_move_type {
125 BLOCK_MOVE_NORMAL, /* generate complete block move */
126 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
127 BLOCK_MOVE_LAST /* generate just the last store */
130 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
131 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
132 extern const char *current_function_file; /* filename current function is in */
133 extern int num_source_filenames; /* current .file # */
134 extern int inside_function; /* != 0 if inside of a function */
135 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
136 extern int file_in_function_warning; /* warning given about .file in func */
137 extern int sdb_label_count; /* block start/end next label # */
138 extern int sdb_begin_function_line; /* Starting Line of current function */
139 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
140 extern int g_switch_value; /* value of the -G xx switch */
141 extern int g_switch_set; /* whether -G xx was passed. */
142 extern int sym_lineno; /* sgi next label # for each stmt */
143 extern int set_noreorder; /* # of nested .set noreorder's */
144 extern int set_nomacro; /* # of nested .set nomacro's */
145 extern int set_noat; /* # of nested .set noat's */
146 extern int set_volatile; /* # of nested .set volatile's */
147 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
148 extern int mips_dbx_regno[]; /* Map register # to debug register # */
149 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
150 extern enum cmp_type branch_type; /* what type of branch to use */
151 extern enum processor_type mips_arch; /* which cpu to codegen for */
152 extern enum processor_type mips_tune; /* which cpu to schedule for */
153 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
154 extern int mips_isa; /* architectural level */
155 extern int mips16; /* whether generating mips16 code */
156 extern int mips16_hard_float; /* mips16 without -msoft-float */
157 extern int mips_entry; /* generate entry/exit for mips16 */
158 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
159 extern const char *mips_arch_string; /* for -march=<xxx> */
160 extern const char *mips_tune_string; /* for -mtune=<xxx> */
161 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
162 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
163 extern const char *mips_entry_string; /* for -mentry */
164 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
165 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
166 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
167 extern int mips_split_addresses; /* perform high/lo_sum support */
168 extern int dslots_load_total; /* total # load related delay slots */
169 extern int dslots_load_filled; /* # filled load delay slots */
170 extern int dslots_jump_total; /* total # jump related delay slots */
171 extern int dslots_jump_filled; /* # filled jump delay slots */
172 extern int dslots_number_nops; /* # of nops needed by previous insn */
173 extern int num_refs[3]; /* # 1/2/3 word references */
174 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
175 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
176 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
177 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
178 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
179 extern int mips_string_length; /* length of strings for mips16 */
180 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
182 /* Functions to change what output section we are using. */
183 extern void rdata_section PARAMS ((void));
184 extern void sdata_section PARAMS ((void));
185 extern void sbss_section PARAMS ((void));
187 /* Stubs for half-pic support if not OSF/1 reference platform. */
190 #define HALF_PIC_P() 0
191 #define HALF_PIC_NUMBER_PTRS 0
192 #define HALF_PIC_NUMBER_REFS 0
193 #define HALF_PIC_ENCODE(DECL)
194 #define HALF_PIC_DECLARE(NAME)
195 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
196 #define HALF_PIC_ADDRESS_P(X) 0
197 #define HALF_PIC_PTR(X) X
198 #define HALF_PIC_FINISH(STREAM)
201 /* Macros to silence warnings about numbers being signed in traditional
202 C and unsigned in ISO C when compiled on 32-bit hosts. */
204 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
205 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
206 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
209 /* Run-time compilation parameters selecting different hardware subsets. */
211 /* Macros used in the machine description to test the flags. */
213 /* Bits for real switches */
214 #define MASK_INT64 0x00000001 /* ints are 64 bits */
215 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
216 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
217 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
218 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
219 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
220 #define MASK_STATS 0x00000040 /* print statistics to stderr */
221 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
222 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
223 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
224 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
225 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
226 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
227 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
228 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
229 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
230 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
231 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
232 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
233 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
234 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
235 #define MASK_NO_CHECK_ZERO_DIV \
236 0x00200000 /* divide by zero checking */
237 #define MASK_CHECK_RANGE_DIV \
238 0x00400000 /* divide result range checking */
239 #define MASK_UNINIT_CONST_IN_RODATA \
240 0x00800000 /* Store uninitialized
242 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
243 multiply-add operations. */
245 /* Debug switches, not documented */
246 #define MASK_DEBUG 0 /* unused */
247 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
248 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
249 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
250 #define MASK_DEBUG_D 0 /* don't do define_split's */
251 #define MASK_DEBUG_E 0 /* function_arg debug */
252 #define MASK_DEBUG_F 0 /* ??? */
253 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
254 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
255 #define MASK_DEBUG_I 0 /* unused */
257 /* Dummy switches used only in specs */
258 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
260 /* r4000 64 bit sizes */
261 #define TARGET_INT64 (target_flags & MASK_INT64)
262 #define TARGET_LONG64 (target_flags & MASK_LONG64)
263 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
264 #define TARGET_64BIT (target_flags & MASK_64BIT)
266 /* Mips vs. GNU linker */
267 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
269 /* Mips vs. GNU assembler */
270 #define TARGET_GAS (target_flags & MASK_GAS)
271 #define TARGET_MIPS_AS (!TARGET_GAS)
274 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
275 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
276 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
277 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
278 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
279 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
280 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
281 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
282 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
283 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
285 /* Reg. Naming in .s ($21 vs. $a0) */
286 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
288 /* Optimize for Sdata/Sbss */
289 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
291 /* print program statistics */
292 #define TARGET_STATS (target_flags & MASK_STATS)
294 /* call memcpy instead of inline code */
295 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
297 /* .abicalls, etc from Pyramid V.4 */
298 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
300 /* OSF pic references to externs */
301 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
303 /* software floating point */
304 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
305 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
307 /* always call through a register */
308 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
310 /* generate embedded PIC code;
312 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
314 /* for embedded systems, optimize for
315 reduced RAM space instead of for
317 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
319 /* always store uninitialized const
320 variables in rodata, requires
321 TARGET_EMBEDDED_DATA. */
322 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
324 /* generate big endian code. */
325 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
327 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
328 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
330 #define TARGET_MAD (target_flags & MASK_MAD)
332 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
334 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
336 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
337 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
339 /* This is true if we must enable the assembly language file switching
342 #define TARGET_FILE_SWITCHING \
343 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
345 /* We must disable the function end stabs when doing the file switching trick,
346 because the Lscope stabs end up in the wrong place, making it impossible
347 to debug the resulting code. */
348 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
350 /* Generate mips16 code */
351 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
353 /* Architecture target defines. */
354 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
355 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
356 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
357 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
358 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
359 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
361 /* Scheduling target defines. */
362 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
363 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
364 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
365 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
366 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
368 /* Macro to define tables used to set the flags.
369 This is a list in braces of pairs in braces,
370 each pair being { "NAME", VALUE }
371 where VALUE is the bits to set or minus the bits to clear.
372 An empty string NAME is used to identify the default VALUE. */
374 #define TARGET_SWITCHES \
377 N_("No default crt0.o") }, \
378 {"int64", MASK_INT64 | MASK_LONG64, \
379 N_("Use 64-bit int type")}, \
380 {"long64", MASK_LONG64, \
381 N_("Use 64-bit long type")}, \
382 {"long32", -(MASK_LONG64 | MASK_INT64), \
383 N_("Use 32-bit long type")}, \
384 {"split-addresses", MASK_SPLIT_ADDR, \
385 N_("Optimize lui/addiu address loads")}, \
386 {"no-split-addresses", -MASK_SPLIT_ADDR, \
387 N_("Don't optimize lui/addiu address loads")}, \
388 {"mips-as", -MASK_GAS, \
389 N_("Use MIPS as")}, \
392 {"rnames", MASK_NAME_REGS, \
393 N_("Use symbolic register names")}, \
394 {"no-rnames", -MASK_NAME_REGS, \
395 N_("Don't use symbolic register names")}, \
396 {"gpOPT", MASK_GPOPT, \
397 N_("Use GP relative sdata/sbss sections")}, \
398 {"gpopt", MASK_GPOPT, \
399 N_("Use GP relative sdata/sbss sections")}, \
400 {"no-gpOPT", -MASK_GPOPT, \
401 N_("Don't use GP relative sdata/sbss sections")}, \
402 {"no-gpopt", -MASK_GPOPT, \
403 N_("Don't use GP relative sdata/sbss sections")}, \
404 {"stats", MASK_STATS, \
405 N_("Output compiler statistics")}, \
406 {"no-stats", -MASK_STATS, \
407 N_("Don't output compiler statistics")}, \
408 {"memcpy", MASK_MEMCPY, \
409 N_("Don't optimize block moves")}, \
410 {"no-memcpy", -MASK_MEMCPY, \
411 N_("Optimize block moves")}, \
412 {"mips-tfile", MASK_MIPS_TFILE, \
413 N_("Use mips-tfile asm postpass")}, \
414 {"no-mips-tfile", -MASK_MIPS_TFILE, \
415 N_("Don't use mips-tfile asm postpass")}, \
416 {"soft-float", MASK_SOFT_FLOAT, \
417 N_("Use software floating point")}, \
418 {"hard-float", -MASK_SOFT_FLOAT, \
419 N_("Use hardware floating point")}, \
420 {"fp64", MASK_FLOAT64, \
421 N_("Use 64-bit FP registers")}, \
422 {"fp32", -MASK_FLOAT64, \
423 N_("Use 32-bit FP registers")}, \
424 {"gp64", MASK_64BIT, \
425 N_("Use 64-bit general registers")}, \
426 {"gp32", -MASK_64BIT, \
427 N_("Use 32-bit general registers")}, \
428 {"abicalls", MASK_ABICALLS, \
429 N_("Use Irix PIC")}, \
430 {"no-abicalls", -MASK_ABICALLS, \
431 N_("Don't use Irix PIC")}, \
432 {"half-pic", MASK_HALF_PIC, \
433 N_("Use OSF PIC")}, \
434 {"no-half-pic", -MASK_HALF_PIC, \
435 N_("Don't use OSF PIC")}, \
436 {"long-calls", MASK_LONG_CALLS, \
437 N_("Use indirect calls")}, \
438 {"no-long-calls", -MASK_LONG_CALLS, \
439 N_("Don't use indirect calls")}, \
440 {"embedded-pic", MASK_EMBEDDED_PIC, \
441 N_("Use embedded PIC")}, \
442 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
443 N_("Don't use embedded PIC")}, \
444 {"embedded-data", MASK_EMBEDDED_DATA, \
445 N_("Use ROM instead of RAM")}, \
446 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
447 N_("Don't use ROM instead of RAM")}, \
448 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
449 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
450 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
451 N_("Don't put uninitialized constants in ROM")}, \
452 {"eb", MASK_BIG_ENDIAN, \
453 N_("Use big-endian byte order")}, \
454 {"el", -MASK_BIG_ENDIAN, \
455 N_("Use little-endian byte order")}, \
456 {"single-float", MASK_SINGLE_FLOAT, \
457 N_("Use single (32-bit) FP only")}, \
458 {"double-float", -MASK_SINGLE_FLOAT, \
459 N_("Don't use single (32-bit) FP only")}, \
461 N_("Use multiply accumulate")}, \
462 {"no-mad", -MASK_MAD, \
463 N_("Don't use multiply accumulate")}, \
464 {"no-fused-madd", MASK_NO_FUSED_MADD, \
465 N_("Don't generate fused multiply/add instructions")}, \
466 {"fused-madd", -MASK_NO_FUSED_MADD, \
467 N_("Generate fused multiply/add instructions")}, \
468 {"fix4300", MASK_4300_MUL_FIX, \
469 N_("Work around early 4300 hardware bug")}, \
470 {"no-fix4300", -MASK_4300_MUL_FIX, \
471 N_("Don't work around early 4300 hardware bug")}, \
473 N_("Optimize for 3900")}, \
475 N_("Optimize for 4650")}, \
476 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
477 N_("Trap on integer divide by zero")}, \
478 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
479 N_("Don't trap on integer divide by zero")}, \
480 {"check-range-division",MASK_CHECK_RANGE_DIV, \
481 N_("Trap on integer divide overflow")}, \
482 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
483 N_("Don't trap on integer divide overflow")}, \
484 {"debug", MASK_DEBUG, \
486 {"debuga", MASK_DEBUG_A, \
488 {"debugb", MASK_DEBUG_B, \
490 {"debugc", MASK_DEBUG_C, \
492 {"debugd", MASK_DEBUG_D, \
494 {"debuge", MASK_DEBUG_E, \
496 {"debugf", MASK_DEBUG_F, \
498 {"debugg", MASK_DEBUG_G, \
500 {"debugh", MASK_DEBUG_H, \
502 {"debugi", MASK_DEBUG_I, \
504 {"", (TARGET_DEFAULT \
505 | TARGET_CPU_DEFAULT \
506 | TARGET_ENDIAN_DEFAULT), \
510 /* Default target_flags if no switches are specified */
512 #ifndef TARGET_DEFAULT
513 #define TARGET_DEFAULT 0
516 #ifndef TARGET_CPU_DEFAULT
517 #define TARGET_CPU_DEFAULT 0
520 #ifndef TARGET_ENDIAN_DEFAULT
522 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
524 #define TARGET_ENDIAN_DEFAULT 0
528 #ifndef MIPS_ISA_DEFAULT
529 #define MIPS_ISA_DEFAULT 1
534 /* Make this compile time constant for libgcc2 */
536 #define TARGET_64BIT 1
538 #define TARGET_64BIT 0
540 #endif /* IN_LIBGCC2 */
542 #ifndef MULTILIB_ENDIAN_DEFAULT
543 #if TARGET_ENDIAN_DEFAULT == 0
544 #define MULTILIB_ENDIAN_DEFAULT "EL"
546 #define MULTILIB_ENDIAN_DEFAULT "EB"
550 #ifndef MULTILIB_ISA_DEFAULT
551 # if MIPS_ISA_DEFAULT == 1
552 # define MULTILIB_ISA_DEFAULT "mips1"
554 # if MIPS_ISA_DEFAULT == 2
555 # define MULTILIB_ISA_DEFAULT "mips2"
557 # if MIPS_ISA_DEFAULT == 3
558 # define MULTILIB_ISA_DEFAULT "mips3"
560 # if MIPS_ISA_DEFAULT == 4
561 # define MULTILIB_ISA_DEFAULT "mips4"
563 # if MIPS_ISA_DEFAULT == 32
564 # define MULTILIB_ISA_DEFAULT "mips32"
566 # if MIPS_ISA_DEFAULT == 64
567 # define MULTILIB_ISA_DEFAULT "mips64"
569 # define MULTILIB_ISA_DEFAULT "mips1"
578 #ifndef MULTILIB_DEFAULTS
579 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
582 /* We must pass -EL to the linker by default for little endian embedded
583 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
584 linker will default to using big-endian output files. The OUTPUT_FORMAT
585 line must be in the linker script, otherwise -EB/-EL will not work. */
588 #if TARGET_ENDIAN_DEFAULT == 0
589 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EL} %{EB}"
591 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EB} %{EL}"
595 /* This macro is similar to `TARGET_SWITCHES' but defines names of
596 command options that have values. Its definition is an
597 initializer with a subgrouping for each command option.
599 Each subgrouping contains a string constant, that defines the
600 fixed part of the option name, and the address of a variable.
601 The variable, type `char *', is set to the variable part of the
602 given option if the fixed part matches. The actual option name
603 is made by appending `-m' to the specified name.
605 Here is an example which defines `-mshort-data-NUMBER'. If the
606 given option is `-mshort-data-512', the variable `m88k_short_data'
607 will be set to the string `"512"'.
609 extern char *m88k_short_data;
610 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
612 #define TARGET_OPTIONS \
614 SUBTARGET_TARGET_OPTIONS \
615 { "cpu=", &mips_cpu_string, \
616 N_("Specify CPU for scheduling purposes")}, \
617 { "tune=", &mips_tune_string, \
618 N_("Specify CPU for scheduling purposes")}, \
619 { "arch=", &mips_arch_string, \
620 N_("Specify CPU for code generation purposes")}, \
621 { "ips", &mips_isa_string, \
622 N_("Specify a Standard MIPS ISA")}, \
623 { "entry", &mips_entry_string, \
624 N_("Use mips16 entry/exit psuedo ops")}, \
625 { "no-mips16", &mips_no_mips16_string, \
626 N_("Don't use MIPS16 instructions")}, \
627 { "explicit-type-size", &mips_explicit_type_size_string, \
629 { "no-flush-func", &mips_cache_flush_func, \
630 N_("Don't call any cache flush functions")}, \
631 { "flush-func=", &mips_cache_flush_func, \
632 N_("Specify cache flush function")}, \
635 /* This is meant to be redefined in the host dependent files. */
636 #define SUBTARGET_TARGET_OPTIONS
638 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
640 /* Generate three-operand multiply instructions for SImode. */
641 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
646 /* Generate three-operand multiply instructions for DImode. */
647 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
650 /* Macros to decide whether certain features are available or not,
651 depending on the instruction set architecture level. */
653 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
654 #define HAVE_SQRT_P() (mips_isa != 1)
656 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
657 #define ISA_HAS_64BIT_REGS (mips_isa == 3 \
661 /* ISA has branch likely instructions (eg. mips2). */
662 /* Disable branchlikely for tx39 until compare rewrite. They haven't
663 been generated up to this point. */
664 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
665 /* || TARGET_MIPS3900 */)
667 /* ISA has the conditional move instructions introduced in mips4. */
668 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
672 /* ISA has just the integer condition move instructions (movn,movz) */
673 #define ISA_HAS_INT_CONDMOVE 0
677 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
678 branch on CC, and move (both FP and non-FP) on CC. */
679 #define ISA_HAS_8CC (mips_isa == 4 \
684 /* This is a catch all for the other new mips4 instructions: indexed load and
685 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
686 and the FP recip and recip sqrt instructions */
687 #define ISA_HAS_FP4 (mips_isa == 4 \
690 /* ISA has conditional trap instructions. */
691 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
693 /* ISA has multiply-accumulate instructions, madd and msub. */
694 #define ISA_HAS_MADD_MSUB (mips_isa == 32 \
698 /* ISA has nmadd and nmsub instructions. */
699 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
702 /* ISA has count leading zeroes/ones instruction (not implemented). */
703 #define ISA_HAS_CLZ_CLO (mips_isa == 32 \
707 /* ISA has double-word count leading zeroes/ones instruction (not
709 #define ISA_HAS_DCLZ_DCLO (mips_isa == 64)
712 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
713 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
714 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
715 target_flags, and -mgp64 sets MASK_64BIT.
717 Setting MASK_64BIT in target_flags will cause gcc to assume that
718 registers are 64 bits wide. int, long and void * will be 32 bit;
719 this may be changed with -mint64 or -mlong64.
721 The gen* programs link code that refers to MASK_64BIT. They don't
722 actually use the information in target_flags; they just refer to
725 /* Switch Recognition by gcc.c. Add -G xx support */
727 #undef SWITCH_TAKES_ARG
728 #define SWITCH_TAKES_ARG(CHAR) \
729 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
731 /* Sometimes certain combinations of command options do not make sense
732 on a particular target machine. You can define a macro
733 `OVERRIDE_OPTIONS' to take account of this. This macro, if
734 defined, is executed once just after all the command options have
737 On the MIPS, it is used to handle -G. We also use it to set up all
738 of the tables referenced in the other macros. */
740 #define OVERRIDE_OPTIONS override_options ()
742 /* Zero or more C statements that may conditionally modify two
743 variables `fixed_regs' and `call_used_regs' (both of type `char
744 []') after they have been initialized from the two preceding
747 This is necessary in case the fixed or call-clobbered registers
748 depend on target flags.
750 You need not define this macro if it has no work to do.
752 If the usage of an entire class of registers depends on the target
753 flags, you may indicate this to GCC by using this macro to modify
754 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
755 the classes which should not be used by GCC. Also define the macro
756 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
757 letter for a class that shouldn't be used.
759 (However, if this class is not included in `GENERAL_REGS' and all
760 of the insn patterns whose constraints permit this class are
761 controlled by target switches, then GCC will automatically avoid
762 using these registers when the target switches are opposed to
765 #define CONDITIONAL_REGISTER_USAGE \
768 if (!TARGET_HARD_FLOAT) \
772 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
773 fixed_regs[regno] = call_used_regs[regno] = 1; \
774 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
775 fixed_regs[regno] = call_used_regs[regno] = 1; \
777 else if (! ISA_HAS_8CC) \
781 /* We only have a single condition code register. We \
782 implement this by hiding all the condition code registers, \
783 and generating RTL that refers directly to ST_REG_FIRST. */ \
784 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
785 fixed_regs[regno] = call_used_regs[regno] = 1; \
787 /* In mips16 mode, we permit the $t temporary registers to be used \
788 for reload. We prohibit the unused $s registers, since they \
789 are caller saved, and saving them via a mips16 register would \
790 probably waste more time than just reloading the value. */ \
793 fixed_regs[18] = call_used_regs[18] = 1; \
794 fixed_regs[19] = call_used_regs[19] = 1; \
795 fixed_regs[20] = call_used_regs[20] = 1; \
796 fixed_regs[21] = call_used_regs[21] = 1; \
797 fixed_regs[22] = call_used_regs[22] = 1; \
798 fixed_regs[23] = call_used_regs[23] = 1; \
799 fixed_regs[26] = call_used_regs[26] = 1; \
800 fixed_regs[27] = call_used_regs[27] = 1; \
801 fixed_regs[30] = call_used_regs[30] = 1; \
803 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
807 /* This is meant to be redefined in the host dependent files. */
808 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
810 /* Show we can debug even without a frame pointer. */
811 #define CAN_DEBUG_WITHOUT_FP
813 /* Complain about missing specs and predefines that should be defined in each
814 of the target tm files to override the defaults. This is mostly a place-
815 holder until I can get each of the files updated [mm]. */
817 #if defined(OSF_OS) \
818 || defined(DECSTATION) \
819 || defined(SGI_TARGET) \
820 || defined(MIPS_NEWS) \
821 || defined(MIPS_SYSV) \
822 || defined(MIPS_SVR4) \
823 || defined(MIPS_BSD43)
825 #ifndef CPP_PREDEFINES
826 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
830 #error "Define LIB_SPEC in the appropriate tm.h file"
833 #ifndef STARTFILE_SPEC
834 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
838 #error "Define MACHINE_TYPE in the appropriate tm.h file"
842 /* Tell collect what flags to pass to nm. */
844 #define NM_FLAGS "-Bn"
848 /* Names to predefine in the preprocessor for this target machine. */
850 #ifndef CPP_PREDEFINES
851 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
852 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
853 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
856 /* Assembler specs. */
858 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
861 #define MIPS_AS_ASM_SPEC "\
862 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
863 %{pipe: %e-pipe is not supported.} \
864 %{K} %(subtarget_mips_as_asm_spec)"
866 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
867 rather than gas. It may be overridden by subtargets. */
869 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
870 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
873 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
876 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips2}}"
878 #ifndef MIPS_ABI_DEFAULT
879 #define ABI_GAS_ASM_SPEC "\
881 %{!mabi=*:%{mips1|mips2|mips32:-mabi=32} %{!mips1:%{!mips2:%{!mips32:-mabi=64}}}}"
884 #if MIPS_ABI_DEFAULT == ABI_32
885 #define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=32}"
888 #if MIPS_ABI_DEFAULT == ABI_N32
889 #define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=n32}"
892 #if MIPS_ABI_DEFAULT == ABI_64
893 #define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=64}"
896 #if MIPS_ABI_DEFAULT == ABI_EABI
897 #define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=eabi}"
900 #if MIPS_ABI_DEFAULT == ABI_O64
901 #define ABI_GAS_ASM_SPEC "\
903 %{!mabi=*:%{mips1|mips2|mips32:-mabi=32} %{!mips1:%{!mips2:%{!mips32:-mabi=o64}}}}"
906 #if MIPS_ABI_DEFAULT == ABI_MEABI
907 #define ABI_GAS_ASM_SPEC "\
909 %{!mabi=*:-mabi=meabi }"
912 #error "Unhandled MIPS_ABI_DEFAULT"
922 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
923 GAS_ASM_SPEC as the default, depending upon the value of
926 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
929 #define TARGET_ASM_SPEC "\
930 %{mmips-as: %(mips_as_asm_spec)} \
931 %{!mmips-as: %(gas_asm_spec)}"
935 #define TARGET_ASM_SPEC "\
936 %{!mgas: %(mips_as_asm_spec)} \
937 %{mgas: %(gas_asm_spec)}"
941 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
942 to the assembler. It may be overridden by subtargets. */
943 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
944 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
946 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
949 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
950 the assembler. It may be overridden by subtargets. */
951 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
952 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
953 %{g} %{g0} %{g1} %{g2} %{g3} \
954 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
955 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
956 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
957 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
960 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
961 overridden by subtargets. */
963 #ifndef SUBTARGET_ASM_SPEC
964 #define SUBTARGET_ASM_SPEC ""
967 /* ASM_SPEC is the set of arguments to pass to the assembler. */
971 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
972 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
973 %(subtarget_asm_optimizing_spec) \
974 %(subtarget_asm_debugging_spec) \
976 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
978 %(subtarget_asm_spec)"
980 /* Specify to run a post-processor, mips-tfile after the assembler
981 has run to stuff the mips debug information into the object file.
982 This is needed because the $#!%^ MIPS assembler provides no way
983 of specifying such information in the assembly file. If we are
984 cross compiling, disable mips-tfile unless the user specifies
987 #ifndef ASM_FINAL_SPEC
988 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
990 #define ASM_FINAL_SPEC "\
991 %{mmips-as: %{!mno-mips-tfile: \
992 \n mips-tfile %{v*: -v} \
994 %{!K: %{save-temps: -I %b.o~}} \
995 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
996 %{.s:%i} %{!.s:%g.s}}}"
1000 #define ASM_FINAL_SPEC "\
1001 %{!mgas: %{!mno-mips-tfile: \
1002 \n mips-tfile %{v*: -v} \
1004 %{!K: %{save-temps: -I %b.o~}} \
1005 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1006 %{.s:%i} %{!.s:%g.s}}}"
1009 #endif /* ASM_FINAL_SPEC */
1011 /* Redefinition of libraries used. Mips doesn't support normal
1012 UNIX style profiling via calling _mcount. It does offer
1013 profiling that samples the PC, so do what we can... */
1016 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1019 /* Extra switches sometimes passed to the linker. */
1020 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1021 will interpret it as a -b option. */
1024 #define LINK_SPEC "\
1026 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
1027 %{bestGnum} %{shared} %{non_shared}"
1028 #endif /* LINK_SPEC defined */
1031 /* Specs for the compiler proper */
1033 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1034 overridden by subtargets. */
1035 #ifndef SUBTARGET_CC1_SPEC
1036 #define SUBTARGET_CC1_SPEC ""
1039 /* Deal with historic options. */
1040 #ifndef CC1_CPU_SPEC
1041 #define CC1_CPU_SPEC "\
1043 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
1044 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
1045 %{m4650:-march=r4650 -mmad -msingle-float \
1046 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
1049 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1050 /* Note, we will need to adjust the following if we ever find a MIPS variant
1051 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1052 that show up in this case. */
1056 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1057 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
1058 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1059 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1060 %{mips32:-mfp32 -mgp32} \
1061 %{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1062 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
1063 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
1064 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
1065 %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
1066 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1067 %{pic-none: -mno-half-pic} \
1068 %{pic-lib: -mhalf-pic} \
1069 %{pic-extern: -mhalf-pic} \
1070 %{pic-calls: -mhalf-pic} \
1072 %(subtarget_cc1_spec) \
1076 /* Preprocessor specs. */
1078 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
1079 be overridden by subtargets. */
1081 #ifndef SUBTARGET_CPP_SIZE_SPEC
1082 #define SUBTARGET_CPP_SIZE_SPEC "\
1083 %{mlong64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}} \
1084 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
1087 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1088 overridden by subtargets. */
1089 #ifndef SUBTARGET_CPP_SPEC
1090 #define SUBTARGET_CPP_SPEC ""
1093 /* If we're using 64bit longs, then we have to define __LONG_MAX__
1094 correctly. Similarly for 64bit ints and __INT_MAX__. */
1095 #ifndef LONG_MAX_SPEC
1096 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
1097 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
1099 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
1103 /* Define appropriate macros for fpr register size. */
1104 #ifndef CPP_FPR_SPEC
1105 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
1106 #define CPP_FPR_SPEC "-D__mips_fpr=64"
1108 #define CPP_FPR_SPEC "-D__mips_fpr=32"
1112 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
1113 of the source file extension. */
1114 #undef CPLUSPLUS_CPP_SPEC
1115 #define CPLUSPLUS_CPP_SPEC "\
1116 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
1119 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1123 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1124 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1125 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1126 %(subtarget_cpp_size_spec) \
1127 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1128 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1129 %{mips32:-U__mips -D__mips=32} \
1130 %{mips64:-U__mips -D__mips=64 -D__mips64} \
1131 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1132 %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
1133 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1134 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1135 %{msoft-float:-D__mips_soft_float} \
1136 %{mabi=eabi:-D__mips_eabi} \
1137 %{mips16:%{!mno-mips16:-D__mips16}} \
1138 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1139 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1141 %(subtarget_cpp_spec) "
1144 /* This macro defines names of additional specifications to put in the specs
1145 that can be used in various specifications like CC1_SPEC. Its definition
1146 is an initializer with a subgrouping for each command option.
1148 Each subgrouping contains a string constant, that defines the
1149 specification name, and a string constant that used by the GNU CC driver
1152 Do not define this macro if it does not need to do anything. */
1154 #define EXTRA_SPECS \
1155 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1156 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
1157 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1158 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1159 { "long_max_spec", LONG_MAX_SPEC }, \
1160 { "cpp_fpr_spec", CPP_FPR_SPEC }, \
1161 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1162 { "gas_asm_spec", GAS_ASM_SPEC }, \
1163 { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \
1164 { "target_asm_spec", TARGET_ASM_SPEC }, \
1165 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1166 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1167 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1168 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1169 { "endian_spec", ENDIAN_SPEC }, \
1170 SUBTARGET_EXTRA_SPECS
1172 #ifndef SUBTARGET_EXTRA_SPECS
1173 #define SUBTARGET_EXTRA_SPECS
1176 /* If defined, this macro is an additional prefix to try after
1177 `STANDARD_EXEC_PREFIX'. */
1179 #ifndef MD_EXEC_PREFIX
1180 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1183 #ifndef MD_STARTFILE_PREFIX
1184 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1188 /* Print subsidiary information on the compiler version in use. */
1190 #define MIPS_VERSION "[AL 1.1, MM 40]"
1192 #ifndef MACHINE_TYPE
1193 #define MACHINE_TYPE "BSD Mips"
1196 #ifndef TARGET_VERSION_INTERNAL
1197 #define TARGET_VERSION_INTERNAL(STREAM) \
1198 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1201 #ifndef TARGET_VERSION
1202 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1206 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1207 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1208 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1210 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1211 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1214 /* By default, turn on GDB extensions. */
1215 #define DEFAULT_GDB_EXTENSIONS 1
1217 /* If we are passing smuggling stabs through the MIPS ECOFF object
1218 format, put a comment in front of the .stab<x> operation so
1219 that the MIPS assembler does not choke. The mips-tfile program
1220 will correctly put the stab into the object file. */
1222 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1223 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1224 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1226 /* Local compiler-generated symbols must have a prefix that the assembler
1227 understands. By default, this is $, although some targets (e.g.,
1228 NetBSD-ELF) need to override this. */
1230 #ifndef LOCAL_LABEL_PREFIX
1231 #define LOCAL_LABEL_PREFIX "$"
1234 /* By default on the mips, external symbols do not have an underscore
1235 prepended, but some targets (e.g., NetBSD) require this. */
1237 #ifndef USER_LABEL_PREFIX
1238 #define USER_LABEL_PREFIX ""
1241 /* Forward references to tags are allowed. */
1242 #define SDB_ALLOW_FORWARD_REFERENCES
1244 /* Unknown tags are also allowed. */
1245 #define SDB_ALLOW_UNKNOWN_REFERENCES
1247 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1248 since the length can run past this up to a continuation point. */
1249 #undef DBX_CONTIN_LENGTH
1250 #define DBX_CONTIN_LENGTH 1500
1252 /* How to renumber registers for dbx and gdb. */
1253 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1255 /* The mapping from gcc register number to DWARF 2 CFA column number.
1256 This mapping does not allow for tracking register 0, since SGI's broken
1257 dwarf reader thinks column 0 is used for the frame address, but since
1258 register 0 is fixed this is not a problem. */
1259 #define DWARF_FRAME_REGNUM(REG) \
1260 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1262 /* The DWARF 2 CFA column which tracks the return address. */
1263 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1265 /* Before the prologue, RA lives in r31. */
1266 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1268 /* Describe how we implement __builtin_eh_return. */
1269 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1270 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1272 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1273 The default for this in 64-bit mode is 8, which causes problems with
1274 SFmode register saves. */
1275 #define DWARF_CIE_DATA_ALIGNMENT 4
1277 /* Overrides for the COFF debug format. */
1278 #define PUT_SDB_SCL(a) \
1280 extern FILE *asm_out_text_file; \
1281 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1284 #define PUT_SDB_INT_VAL(a) \
1286 extern FILE *asm_out_text_file; \
1287 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1290 #define PUT_SDB_VAL(a) \
1292 extern FILE *asm_out_text_file; \
1293 fputs ("\t.val\t", asm_out_text_file); \
1294 output_addr_const (asm_out_text_file, (a)); \
1295 fputc (';', asm_out_text_file); \
1298 #define PUT_SDB_DEF(a) \
1300 extern FILE *asm_out_text_file; \
1301 fprintf (asm_out_text_file, "\t%s.def\t", \
1302 (TARGET_GAS) ? "" : "#"); \
1303 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1304 fputc (';', asm_out_text_file); \
1307 #define PUT_SDB_PLAIN_DEF(a) \
1309 extern FILE *asm_out_text_file; \
1310 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1311 (TARGET_GAS) ? "" : "#", (a)); \
1314 #define PUT_SDB_ENDEF \
1316 extern FILE *asm_out_text_file; \
1317 fprintf (asm_out_text_file, "\t.endef\n"); \
1320 #define PUT_SDB_TYPE(a) \
1322 extern FILE *asm_out_text_file; \
1323 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1326 #define PUT_SDB_SIZE(a) \
1328 extern FILE *asm_out_text_file; \
1329 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1332 #define PUT_SDB_DIM(a) \
1334 extern FILE *asm_out_text_file; \
1335 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1338 #ifndef PUT_SDB_START_DIM
1339 #define PUT_SDB_START_DIM \
1341 extern FILE *asm_out_text_file; \
1342 fprintf (asm_out_text_file, "\t.dim\t"); \
1346 #ifndef PUT_SDB_NEXT_DIM
1347 #define PUT_SDB_NEXT_DIM(a) \
1349 extern FILE *asm_out_text_file; \
1350 fprintf (asm_out_text_file, "%d,", a); \
1354 #ifndef PUT_SDB_LAST_DIM
1355 #define PUT_SDB_LAST_DIM(a) \
1357 extern FILE *asm_out_text_file; \
1358 fprintf (asm_out_text_file, "%d;", a); \
1362 #define PUT_SDB_TAG(a) \
1364 extern FILE *asm_out_text_file; \
1365 fprintf (asm_out_text_file, "\t.tag\t"); \
1366 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1367 fputc (';', asm_out_text_file); \
1370 /* For block start and end, we create labels, so that
1371 later we can figure out where the correct offset is.
1372 The normal .ent/.end serve well enough for functions,
1373 so those are just commented out. */
1375 #define PUT_SDB_BLOCK_START(LINE) \
1377 extern FILE *asm_out_text_file; \
1378 fprintf (asm_out_text_file, \
1379 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1380 LOCAL_LABEL_PREFIX, \
1382 (TARGET_GAS) ? "" : "#", \
1383 LOCAL_LABEL_PREFIX, \
1386 sdb_label_count++; \
1389 #define PUT_SDB_BLOCK_END(LINE) \
1391 extern FILE *asm_out_text_file; \
1392 fprintf (asm_out_text_file, \
1393 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1394 LOCAL_LABEL_PREFIX, \
1396 (TARGET_GAS) ? "" : "#", \
1397 LOCAL_LABEL_PREFIX, \
1400 sdb_label_count++; \
1403 #define PUT_SDB_FUNCTION_START(LINE)
1405 #define PUT_SDB_FUNCTION_END(LINE) \
1407 extern FILE *asm_out_text_file; \
1408 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1411 #define PUT_SDB_EPILOGUE_END(NAME)
1413 #define PUT_SDB_SRC_FILE(FILENAME) \
1415 extern FILE *asm_out_text_file; \
1416 output_file_directive (asm_out_text_file, (FILENAME)); \
1419 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1420 sprintf ((BUFFER), ".%dfake", (NUMBER));
1422 /* Correct the offset of automatic variables and arguments. Note that
1423 the MIPS debug format wants all automatic variables and arguments
1424 to be in terms of the virtual frame pointer (stack pointer before
1425 any adjustment in the function), while the MIPS 3.0 linker wants
1426 the frame pointer to be the stack pointer after the initial
1429 #define DEBUGGER_AUTO_OFFSET(X) \
1430 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1431 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1432 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1434 /* Tell collect that the object format is ECOFF */
1435 #ifndef OBJECT_FORMAT_ROSE
1436 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1437 #define EXTENDED_COFF /* ECOFF, not normal coff */
1440 /* Target machine storage layout */
1442 /* Define in order to support both big and little endian float formats
1443 in the same gcc binary. */
1444 #define REAL_ARITHMETIC
1446 /* Define this if most significant bit is lowest numbered
1447 in instructions that operate on numbered bit-fields.
1449 #define BITS_BIG_ENDIAN 0
1451 /* Define this if most significant byte of a word is the lowest numbered. */
1452 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1454 /* Define this if most significant word of a multiword number is the lowest. */
1455 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1457 /* Define this to set the endianness to use in libgcc2.c, which can
1458 not depend on target_flags. */
1459 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1460 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1462 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1465 /* Number of bits in an addressable storage unit */
1466 #define BITS_PER_UNIT 8
1468 /* Width in bits of a "word", which is the contents of a machine register.
1469 Note that this is not necessarily the width of data type `int';
1470 if using 16-bit ints on a 68000, this would still be 32.
1471 But on a machine with 16-bit registers, this would be 16. */
1472 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1473 #define MAX_BITS_PER_WORD 64
1475 /* Width of a word, in units (bytes). */
1476 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1477 #define MIN_UNITS_PER_WORD 4
1479 /* For MIPS, width of a floating point register. */
1480 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1482 /* A C expression for the size in bits of the type `int' on the
1483 target machine. If you don't define this, the default is one
1485 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1486 #define MAX_INT_TYPE_SIZE 64
1488 /* Tell the preprocessor the maximum size of wchar_t. */
1489 #ifndef MAX_WCHAR_TYPE_SIZE
1490 #ifndef WCHAR_TYPE_SIZE
1491 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1495 /* A C expression for the size in bits of the type `short' on the
1496 target machine. If you don't define this, the default is half a
1497 word. (If this would be less than one storage unit, it is
1498 rounded up to one unit.) */
1499 #define SHORT_TYPE_SIZE 16
1501 /* A C expression for the size in bits of the type `long' on the
1502 target machine. If you don't define this, the default is one
1504 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1505 #define MAX_LONG_TYPE_SIZE 64
1507 /* A C expression for the size in bits of the type `long long' on the
1508 target machine. If you don't define this, the default is two
1510 #define LONG_LONG_TYPE_SIZE 64
1512 /* A C expression for the size in bits of the type `char' on the
1513 target machine. If you don't define this, the default is one
1514 quarter of a word. (If this would be less than one storage unit,
1515 it is rounded up to one unit.) */
1516 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1518 /* A C expression for the size in bits of the type `float' on the
1519 target machine. If you don't define this, the default is one
1521 #define FLOAT_TYPE_SIZE 32
1523 /* A C expression for the size in bits of the type `double' on the
1524 target machine. If you don't define this, the default is two
1526 #define DOUBLE_TYPE_SIZE 64
1528 /* A C expression for the size in bits of the type `long double' on
1529 the target machine. If you don't define this, the default is two
1531 #define LONG_DOUBLE_TYPE_SIZE 64
1533 /* Width in bits of a pointer.
1534 See also the macro `Pmode' defined below. */
1535 #ifndef POINTER_SIZE
1536 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1539 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1540 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1542 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1543 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1545 /* Allocation boundary (in *bits*) for the code of a function. */
1546 #define FUNCTION_BOUNDARY 32
1548 /* Alignment of field after `int : 0' in a structure. */
1549 #define EMPTY_FIELD_BOUNDARY 32
1551 /* Every structure's size must be a multiple of this. */
1552 /* 8 is observed right on a DECstation and on riscos 4.02. */
1553 #define STRUCTURE_SIZE_BOUNDARY 8
1555 /* There is no point aligning anything to a rounder boundary than this. */
1556 #define BIGGEST_ALIGNMENT 64
1558 /* Set this nonzero if move instructions will actually fail to work
1559 when given unaligned data. */
1560 #define STRICT_ALIGNMENT 1
1562 /* Define this if you wish to imitate the way many other C compilers
1563 handle alignment of bitfields and the structures that contain
1566 The behavior is that the type written for a bitfield (`int',
1567 `short', or other integer type) imposes an alignment for the
1568 entire structure, as if the structure really did contain an
1569 ordinary field of that type. In addition, the bitfield is placed
1570 within the structure so that it would fit within such a field,
1571 not crossing a boundary for it.
1573 Thus, on most machines, a bitfield whose type is written as `int'
1574 would not cross a four-byte boundary, and would force four-byte
1575 alignment for the whole structure. (The alignment used may not
1576 be four bytes; it is controlled by the other alignment
1579 If the macro is defined, its definition should be a C expression;
1580 a nonzero value for the expression enables this behavior. */
1582 #define PCC_BITFIELD_TYPE_MATTERS 1
1584 /* If defined, a C expression to compute the alignment given to a
1585 constant that is being placed in memory. CONSTANT is the constant
1586 and ALIGN is the alignment that the object would ordinarily have.
1587 The value of this macro is used instead of that alignment to align
1590 If this macro is not defined, then ALIGN is used.
1592 The typical use of this macro is to increase alignment for string
1593 constants to be word aligned so that `strcpy' calls that copy
1594 constants can be done inline. */
1596 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1597 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1598 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1600 /* If defined, a C expression to compute the alignment for a static
1601 variable. TYPE is the data type, and ALIGN is the alignment that
1602 the object would ordinarily have. The value of this macro is used
1603 instead of that alignment to align the object.
1605 If this macro is not defined, then ALIGN is used.
1607 One use of this macro is to increase alignment of medium-size
1608 data to make it all fit in fewer cache lines. Another is to
1609 cause character arrays to be word-aligned so that `strcpy' calls
1610 that copy constants to character arrays can be done inline. */
1612 #undef DATA_ALIGNMENT
1613 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1614 ((((ALIGN) < BITS_PER_WORD) \
1615 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1616 || TREE_CODE (TYPE) == UNION_TYPE \
1617 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1620 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1622 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1623 || mips_abi == ABI_MEABI \
1624 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1626 /* Define this macro if an argument declared as `char' or `short' in a
1627 prototype should actually be passed as an `int'. In addition to
1628 avoiding errors in certain cases of mismatch, it also makes for
1629 better code on certain machines. */
1631 #define PROMOTE_PROTOTYPES 1
1633 /* Define if operations between registers always perform the operation
1634 on the full register even if a narrower mode is specified. */
1635 #define WORD_REGISTER_OPERATIONS
1637 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1638 will either zero-extend or sign-extend. The value of this macro should
1639 be the code that says which one of the two operations is implicitly
1642 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1643 moves. All other referces are zero extended. */
1644 #define LOAD_EXTEND_OP(MODE) \
1645 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1646 ? SIGN_EXTEND : ZERO_EXTEND)
1648 /* Define this macro if it is advisable to hold scalars in registers
1649 in a wider mode than that declared by the program. In such cases,
1650 the value is constrained to be within the bounds of the declared
1651 type, but kept valid in the wider mode. The signedness of the
1652 extension may differ from that of the type.
1654 We promote any value smaller than SImode up to SImode. We don't
1655 want to promote to DImode when in 64 bit mode, because that would
1656 prevent us from using the faster SImode multiply and divide
1659 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1660 if (GET_MODE_CLASS (MODE) == MODE_INT \
1661 && GET_MODE_SIZE (MODE) < 4) \
1664 /* Define this if function arguments should also be promoted using the above
1667 #define PROMOTE_FUNCTION_ARGS
1669 /* Likewise, if the function return value is promoted. */
1671 #define PROMOTE_FUNCTION_RETURN
1673 /* Standard register usage. */
1675 /* Number of actual hardware registers.
1676 The hardware registers are assigned numbers for the compiler
1677 from 0 to just below FIRST_PSEUDO_REGISTER.
1678 All registers that the compiler knows about must be given numbers,
1679 even those that are not normally considered general registers.
1681 On the Mips, we have 32 integer registers, 32 floating point
1682 registers, 8 condition code registers, and the special registers
1683 hi, lo, hilo, and rap. The 8 condition code registers are only
1684 used if mips_isa >= 4. The hilo register is only used in 64 bit
1685 mode. It represents a 64 bit value stored as two 32 bit values in
1686 the hi and lo registers; this is the result of the mult
1687 instruction. rap is a pointer to the stack where the return
1688 address reg ($31) was stored. This is needed for C++ exception
1691 #define FIRST_PSEUDO_REGISTER 76
1693 /* 1 for registers that have pervasive standard uses
1694 and are not available for the register allocator.
1696 On the MIPS, see conventions, page D-2 */
1698 #define FIXED_REGISTERS \
1700 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1701 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1702 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1703 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1704 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1708 /* 1 for registers not available across function calls.
1709 These must include the FIXED_REGISTERS and also any
1710 registers that can be used without being saved.
1711 The latter must include the registers where values are returned
1712 and the register where structure-value addresses are passed.
1713 Aside from that, you can include as many other registers as you like. */
1715 #define CALL_USED_REGISTERS \
1717 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1718 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1719 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1720 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1721 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1725 /* Internal macros to classify a register number as to whether it's a
1726 general purpose register, a floating point register, a
1727 multiply/divide register, or a status register. */
1729 #define GP_REG_FIRST 0
1730 #define GP_REG_LAST 31
1731 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1732 #define GP_DBX_FIRST 0
1734 #define FP_REG_FIRST 32
1735 #define FP_REG_LAST 63
1736 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1737 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1739 #define MD_REG_FIRST 64
1740 #define MD_REG_LAST 66
1741 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1743 #define ST_REG_FIRST 67
1744 #define ST_REG_LAST 74
1745 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1747 #define RAP_REG_NUM 75
1749 #define AT_REGNUM (GP_REG_FIRST + 1)
1750 #define HI_REGNUM (MD_REG_FIRST + 0)
1751 #define LO_REGNUM (MD_REG_FIRST + 1)
1752 #define HILO_REGNUM (MD_REG_FIRST + 2)
1754 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1755 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1756 should be used instead. */
1757 #define FPSW_REGNUM ST_REG_FIRST
1759 #define GP_REG_P(REGNO) \
1760 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1761 #define M16_REG_P(REGNO) \
1762 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1763 #define FP_REG_P(REGNO) \
1764 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1765 #define MD_REG_P(REGNO) \
1766 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1767 #define ST_REG_P(REGNO) \
1768 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1770 /* Return number of consecutive hard regs needed starting at reg REGNO
1771 to hold something of mode MODE.
1772 This is ordinarily the length in words of a value of mode MODE
1773 but can be less for certain modes in special long registers.
1775 On the MIPS, all general registers are one word long. Except on
1776 the R4000 with the FR bit set, the floating point uses register
1777 pairs, with the second register not being allocable. */
1779 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1781 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1782 MODE. In 32 bit mode, require that DImode and DFmode be in even
1783 registers. For DImode, this makes some of the insns easier to
1784 write, since you don't have to worry about a DImode value in
1785 registers 3 & 4, producing a result in 4 & 5.
1787 To make the code simpler HARD_REGNO_MODE_OK now just references an
1788 array built in override_options. Because machmodes.h is not yet
1789 included before this file is processed, the MODE bound can't be
1792 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1794 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1795 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1797 /* Value is 1 if it is a good idea to tie two pseudo registers
1798 when one has mode MODE1 and one has mode MODE2.
1799 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1800 for any hard reg, then this must be 0 for correct output. */
1801 #define MODES_TIEABLE_P(MODE1, MODE2) \
1802 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1803 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1804 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1805 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1807 /* MIPS pc is not overloaded on a register. */
1808 /* #define PC_REGNUM xx */
1810 /* Register to use for pushing function arguments. */
1811 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1813 /* Offset from the stack pointer to the first available location. Use
1814 the default value zero. */
1815 /* #define STACK_POINTER_OFFSET 0 */
1817 /* Base register for access to local variables of the function. We
1818 pretend that the frame pointer is $1, and then eliminate it to
1819 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1820 a fixed register, and will not be used for anything else. */
1821 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1823 /* Temporary scratch register for use by the assembler. */
1824 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1826 /* $30 is not available on the mips16, so we use $17 as the frame
1828 #define HARD_FRAME_POINTER_REGNUM \
1829 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1831 /* Value should be nonzero if functions must have frame pointers.
1832 Zero means the frame pointer need not be set up (and parms
1833 may be accessed via the stack pointer) in functions that seem suitable.
1834 This is computed in `reload', in reload1.c. */
1835 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1837 /* Base register for access to arguments of the function. */
1838 #define ARG_POINTER_REGNUM GP_REG_FIRST
1840 /* Fake register that holds the address on the stack of the
1841 current function's return address. */
1842 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1844 /* Register in which static-chain is passed to a function. */
1845 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1847 /* If the structure value address is passed in a register, then
1848 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1849 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1851 /* If the structure value address is not passed in a register, define
1852 `STRUCT_VALUE' as an expression returning an RTX for the place
1853 where the address is passed. If it returns 0, the address is
1854 passed as an "invisible" first argument. */
1855 #define STRUCT_VALUE 0
1857 /* Mips registers used in prologue/epilogue code when the stack frame
1858 is larger than 32K bytes. These registers must come from the
1859 scratch register set, and not used for passing and returning
1860 arguments and any other information used in the calling sequence
1861 (such as pic). Must start at 12, since t0/t3 are parameter passing
1862 registers in the 64 bit ABI. */
1864 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1865 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1867 /* Define this macro if it is as good or better to call a constant
1868 function address than to call an address kept in a register. */
1869 #define NO_FUNCTION_CSE 1
1871 /* Define this macro if it is as good or better for a function to
1872 call itself with an explicit address than to call an address
1873 kept in a register. */
1874 #define NO_RECURSIVE_FUNCTION_CSE 1
1876 /* The register number of the register used to address a table of
1877 static data addresses in memory. In some cases this register is
1878 defined by a processor's "application binary interface" (ABI).
1879 When this macro is defined, RTL is generated for this register
1880 once, as with the stack pointer and frame pointer registers. If
1881 this macro is not defined, it is up to the machine-dependent
1882 files to allocate such a register (if necessary). */
1883 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1885 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1887 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1888 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1889 isn't always called for static inline functions. */
1890 #define INIT_EXPANDERS \
1892 embedded_pic_fnaddr_rtx = NULL; \
1893 mips16_gp_pseudo_rtx = NULL; \
1896 /* Define the classes of registers for register constraints in the
1897 machine description. Also define ranges of constants.
1899 One of the classes must always be named ALL_REGS and include all hard regs.
1900 If there is more than one class, another class must be named NO_REGS
1901 and contain no registers.
1903 The name GENERAL_REGS must be the name of a class (or an alias for
1904 another name such as ALL_REGS). This is the class of registers
1905 that is allowed by "g" or "r" in a register constraint.
1906 Also, registers outside this class are allocated only when
1907 instructions express preferences for them.
1909 The classes must be numbered in nondecreasing order; that is,
1910 a larger-numbered class must never be contained completely
1911 in a smaller-numbered class.
1913 For any two classes, it is very desirable that there be another
1914 class that represents their union. */
1918 NO_REGS, /* no registers in set */
1919 M16_NA_REGS, /* mips16 regs not used to pass args */
1920 M16_REGS, /* mips16 directly accessible registers */
1921 T_REG, /* mips16 T register ($24) */
1922 M16_T_REGS, /* mips16 registers plus T register */
1923 GR_REGS, /* integer registers */
1924 FP_REGS, /* floating point registers */
1925 HI_REG, /* hi register */
1926 LO_REG, /* lo register */
1927 HILO_REG, /* hilo register pair for 64 bit mode mult */
1928 MD_REGS, /* multiply/divide registers (hi/lo) */
1929 HI_AND_GR_REGS, /* union classes */
1932 ST_REGS, /* status registers (fp status) */
1933 ALL_REGS, /* all registers */
1934 LIM_REG_CLASSES /* max value + 1 */
1937 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1939 #define GENERAL_REGS GR_REGS
1941 /* An initializer containing the names of the register classes as C
1942 string constants. These names are used in writing some of the
1945 #define REG_CLASS_NAMES \
1960 "HILO_AND_GR_REGS", \
1965 /* An initializer containing the contents of the register classes,
1966 as integers which are bit masks. The Nth integer specifies the
1967 contents of class N. The way the integer MASK is interpreted is
1968 that register R is in the class if `MASK & (1 << R)' is 1.
1970 When the machine has more than 32 registers, an integer does not
1971 suffice. Then the integers are replaced by sub-initializers,
1972 braced groupings containing several integers. Each
1973 sub-initializer must be suitable as an initializer for the type
1974 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1976 #define REG_CLASS_CONTENTS \
1978 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1979 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1980 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1981 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1982 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1983 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1984 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1985 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1986 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1987 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1988 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1989 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1990 { 0xffffffff, 0x00000000, 0x00000002 }, \
1991 { 0xffffffff, 0x00000000, 0x00000004 }, \
1992 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1993 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1997 /* A C expression whose value is a register class containing hard
1998 register REGNO. In general there is more that one such class;
1999 choose a class which is "minimal", meaning that no smaller class
2000 also contains the register. */
2002 extern const enum reg_class mips_regno_to_class[];
2004 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2006 /* A macro whose definition is the name of the class to which a
2007 valid base register must belong. A base register is one used in
2008 an address which is the register value plus a displacement. */
2010 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2012 /* A macro whose definition is the name of the class to which a
2013 valid index register must belong. An index register is one used
2014 in an address where its value is either multiplied by a scale
2015 factor or added to another register (as well as added to a
2018 #define INDEX_REG_CLASS NO_REGS
2020 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2021 registers explicitly used in the rtl to be used as spill registers
2022 but prevents the compiler from extending the lifetime of these
2025 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2027 /* This macro is used later on in the file. */
2028 #define GR_REG_CLASS_P(CLASS) \
2029 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2030 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2032 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2033 is the default value (allocate the registers in numeric order). We
2034 define it just so that we can override it for the mips16 target in
2035 ORDER_REGS_FOR_LOCAL_ALLOC. */
2037 #define REG_ALLOC_ORDER \
2038 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2039 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2040 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2041 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2042 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
2045 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2046 to be rearranged based on a particular function. On the mips16, we
2047 want to allocate $24 (T_REG) before other registers for
2048 instructions for which it is possible. */
2050 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2052 /* REGISTER AND CONSTANT CLASSES */
2054 /* Get reg_class from a letter such as appears in the machine
2057 DEFINED REGISTER CLASSES:
2059 'd' General (aka integer) registers
2060 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2061 'y' General registers (in both mips16 and non mips16 mode)
2062 'e' mips16 non argument registers (M16_NA_REGS)
2063 't' mips16 temporary register ($24)
2064 'f' Floating point registers
2067 'x' Multiply/divide registers
2069 'z' FP Status register
2070 'b' All registers */
2072 extern enum reg_class mips_char_to_class[];
2074 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2076 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2077 string can be used to stand for particular ranges of immediate
2078 operands. This macro defines what the ranges are. C is the
2079 letter, and VALUE is a constant value. Return 1 if VALUE is
2080 in the range specified by C. */
2084 `I' is used for the range of constants an arithmetic insn can
2085 actually contain (16 bits signed integers).
2087 `J' is used for the range which is just zero (ie, $r0).
2089 `K' is used for the range of constants a logical insn can actually
2090 contain (16 bit zero-extended integers).
2092 `L' is used for the range of constants that be loaded with lui
2093 (ie, the bottom 16 bits are zero).
2095 `M' is used for the range of constants that take two words to load
2096 (ie, not matched by `I', `K', and `L').
2098 `N' is used for negative 16 bit constants other than -65536.
2100 `O' is a 15 bit signed integer.
2102 `P' is used for positive 16 bit constants. */
2104 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2105 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2107 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2108 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2109 : (C) == 'J' ? ((VALUE) == 0) \
2110 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2111 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2112 && (((VALUE) & ~2147483647) == 0 \
2113 || ((VALUE) & ~2147483647) == ~2147483647)) \
2114 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2115 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2116 && (((VALUE) & 0x0000ffff) != 0 \
2117 || (((VALUE) & ~2147483647) != 0 \
2118 && ((VALUE) & ~2147483647) != ~2147483647))) \
2119 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2120 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2121 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2124 /* Similar, but for floating constants, and defining letters G and H.
2125 Here VALUE is the CONST_DOUBLE rtx itself. */
2129 'G' : Floating point 0 */
2131 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2133 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2135 /* Letters in the range `Q' through `U' may be defined in a
2136 machine-dependent fashion to stand for arbitrary operand types.
2137 The machine description macro `EXTRA_CONSTRAINT' is passed the
2138 operand as its first argument and the constraint letter as its
2141 `Q' is for mips16 GP relative constants
2142 `R' is for memory references which take 1 word for the instruction.
2143 `S' is for references to extern items which are PIC for OSF/rose.
2144 `T' is for memory addresses that can be used to load two words. */
2146 #define EXTRA_CONSTRAINT(OP,CODE) \
2147 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2148 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2149 && mips16_gp_offset_p (OP)) \
2150 : (GET_CODE (OP) != MEM) ? FALSE \
2151 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2152 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2153 && HALF_PIC_ADDRESS_P (OP)) \
2156 /* Given an rtx X being reloaded into a reg required to be
2157 in class CLASS, return the class of reg to actually use.
2158 In general this is just CLASS; but on some machines
2159 in some cases it is preferable to use a more restrictive class. */
2161 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2162 ((CLASS) != ALL_REGS \
2163 ? (! TARGET_MIPS16 \
2165 : ((CLASS) != GR_REGS \
2168 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2169 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2170 ? (TARGET_SOFT_FLOAT \
2171 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2173 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2174 || GET_MODE (X) == VOIDmode) \
2175 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2178 /* Certain machines have the property that some registers cannot be
2179 copied to some other registers without using memory. Define this
2180 macro on those machines to be a C expression that is non-zero if
2181 objects of mode MODE in registers of CLASS1 can only be copied to
2182 registers of class CLASS2 by storing a register of CLASS1 into
2183 memory and loading that memory location into a register of CLASS2.
2185 Do not define this macro if its value would always be zero. */
2187 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2188 ((!TARGET_DEBUG_H_MODE \
2189 && GET_MODE_CLASS (MODE) == MODE_INT \
2190 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2191 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2192 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2193 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2194 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2196 /* The HI and LO registers can only be reloaded via the general
2197 registers. Condition code registers can only be loaded to the
2198 general registers, and from the floating point registers. */
2200 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2201 mips_secondary_reload_class (CLASS, MODE, X, 1)
2202 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2203 mips_secondary_reload_class (CLASS, MODE, X, 0)
2205 /* Return the maximum number of consecutive registers
2206 needed to represent mode MODE in a register of class CLASS. */
2208 #define CLASS_UNITS(mode, size) \
2209 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2211 #define CLASS_MAX_NREGS(CLASS, MODE) \
2212 ((CLASS) == FP_REGS \
2214 ? CLASS_UNITS (MODE, 8) \
2215 : 2 * CLASS_UNITS (MODE, 8)) \
2216 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2218 /* If defined, gives a class of registers that cannot be used as the
2219 operand of a SUBREG that changes the mode of the object illegally. */
2221 #define CLASS_CANNOT_CHANGE_MODE \
2222 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2224 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2226 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2227 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2229 /* Stack layout; function entry, exit and calling. */
2231 /* Define this if pushing a word on the stack
2232 makes the stack pointer a smaller address. */
2233 #define STACK_GROWS_DOWNWARD
2235 /* Define this if the nominal address of the stack frame
2236 is at the high-address end of the local variables;
2237 that is, each additional local variable allocated
2238 goes at a more negative offset in the frame. */
2239 /* #define FRAME_GROWS_DOWNWARD */
2241 /* Offset within stack frame to start allocating local variables at.
2242 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2243 first local allocated. Otherwise, it is the offset to the BEGINNING
2244 of the first local allocated. */
2245 #define STARTING_FRAME_OFFSET \
2246 (current_function_outgoing_args_size \
2247 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2249 /* Offset from the stack pointer register to an item dynamically
2250 allocated on the stack, e.g., by `alloca'.
2252 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2253 length of the outgoing arguments. The default is correct for most
2254 machines. See `function.c' for details.
2256 The MIPS ABI states that functions which dynamically allocate the
2257 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2258 we are trying to create a second frame pointer to the function, so
2259 allocate some stack space to make it happy.
2261 However, the linker currently complains about linking any code that
2262 dynamically allocates stack space, and there seems to be a bug in
2263 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2266 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2267 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2268 ? 4*UNITS_PER_WORD \
2269 : current_function_outgoing_args_size)
2272 /* The return address for the current frame is in r31 is this is a leaf
2273 function. Otherwise, it is on the stack. It is at a variable offset
2274 from sp/fp/ap, so we define a fake hard register rap which is a
2275 poiner to the return address on the stack. This always gets eliminated
2276 during reload to be either the frame pointer or the stack pointer plus
2279 /* ??? This definition fails for leaf functions. There is currently no
2280 general solution for this problem. */
2282 /* ??? There appears to be no way to get the return address of any previous
2283 frame except by disassembling instructions in the prologue/epilogue.
2284 So currently we support only the current frame. */
2286 #define RETURN_ADDR_RTX(count, frame) \
2288 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2291 /* Structure to be filled in by compute_frame_size with register
2292 save masks, and offsets for the current function. */
2294 struct mips_frame_info
2296 long total_size; /* # bytes that the entire frame takes up */
2297 long var_size; /* # bytes that variables take up */
2298 long args_size; /* # bytes that outgoing arguments take up */
2299 long extra_size; /* # bytes of extra gunk */
2300 int gp_reg_size; /* # bytes needed to store gp regs */
2301 int fp_reg_size; /* # bytes needed to store fp regs */
2302 long mask; /* mask of saved gp registers */
2303 long fmask; /* mask of saved fp registers */
2304 long gp_save_offset; /* offset from vfp to store gp registers */
2305 long fp_save_offset; /* offset from vfp to store fp registers */
2306 long gp_sp_offset; /* offset from new sp to store gp registers */
2307 long fp_sp_offset; /* offset from new sp to store fp registers */
2308 int initialized; /* != 0 if frame size already calculated */
2309 int num_gp; /* number of gp registers saved */
2310 int num_fp; /* number of fp registers saved */
2311 long insns_len; /* length of insns; mips16 only */
2314 extern struct mips_frame_info current_frame_info;
2316 /* If defined, this macro specifies a table of register pairs used to
2317 eliminate unneeded registers that point into the stack frame. If
2318 it is not defined, the only elimination attempted by the compiler
2319 is to replace references to the frame pointer with references to
2322 The definition of this macro is a list of structure
2323 initializations, each of which specifies an original and
2324 replacement register.
2326 On some machines, the position of the argument pointer is not
2327 known until the compilation is completed. In such a case, a
2328 separate hard register must be used for the argument pointer.
2329 This register can be eliminated by replacing it with either the
2330 frame pointer or the argument pointer, depending on whether or not
2331 the frame pointer has been eliminated.
2333 In this case, you might specify:
2334 #define ELIMINABLE_REGS \
2335 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2336 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2337 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2339 Note that the elimination of the argument pointer with the stack
2340 pointer is specified first since that is the preferred elimination.
2342 The eliminations to $17 are only used on the mips16. See the
2343 definition of HARD_FRAME_POINTER_REGNUM. */
2345 #define ELIMINABLE_REGS \
2346 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2347 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2348 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2349 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2350 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2351 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2352 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2353 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2354 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2355 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2357 /* A C expression that returns non-zero if the compiler is allowed to
2358 try to replace register number FROM-REG with register number
2359 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2360 defined, and will usually be the constant 1, since most of the
2361 cases preventing register elimination are things that the compiler
2362 already knows about.
2364 When not in mips16 and mips64, we can always eliminate to the
2365 frame pointer. We can eliminate to the stack pointer unless
2366 a frame pointer is needed. In mips16 mode, we need a frame
2367 pointer for a large frame; otherwise, reload may be unable
2368 to compute the address of a local variable, since there is
2369 no way to add a large constant to the stack pointer
2370 without using a temporary register.
2372 In mips16, for some instructions (eg lwu), we can't eliminate the
2373 frame pointer for the stack pointer. These instructions are
2374 only generated in TARGET_64BIT mode.
2377 #define CAN_ELIMINATE(FROM, TO) \
2378 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2379 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2380 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2381 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2382 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2383 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2384 && (! TARGET_MIPS16 \
2385 || compute_frame_size (get_frame_size ()) < 32768)))))
2387 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2388 specifies the initial difference between the specified pair of
2389 registers. This macro must be defined if `ELIMINABLE_REGS' is
2392 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2393 { compute_frame_size (get_frame_size ()); \
2394 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2395 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2396 (OFFSET) = - current_function_outgoing_args_size; \
2397 else if ((FROM) == FRAME_POINTER_REGNUM) \
2399 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2400 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2401 (OFFSET) = (current_frame_info.total_size \
2402 - current_function_outgoing_args_size \
2403 - ((mips_abi != ABI_32 \
2404 && mips_abi != ABI_O64 \
2405 && mips_abi != ABI_EABI) \
2406 ? current_function_pretend_args_size \
2408 else if ((FROM) == ARG_POINTER_REGNUM) \
2409 (OFFSET) = (current_frame_info.total_size \
2410 - ((mips_abi != ABI_32 \
2411 && mips_abi != ABI_O64 \
2412 && mips_abi != ABI_EABI) \
2413 ? current_function_pretend_args_size \
2415 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2416 so we must add 4 bytes to the offset to get the right value. */ \
2417 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2419 if (leaf_function_p ()) \
2421 else (OFFSET) = current_frame_info.gp_sp_offset \
2422 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2423 * (BYTES_BIG_ENDIAN != 0)); \
2429 /* If we generate an insn to push BYTES bytes,
2430 this says how many the stack pointer really advances by.
2431 On the VAX, sp@- in a byte insn really pushes a word. */
2433 /* #define PUSH_ROUNDING(BYTES) 0 */
2435 /* If defined, the maximum amount of space required for outgoing
2436 arguments will be computed and placed into the variable
2437 `current_function_outgoing_args_size'. No space will be pushed
2438 onto the stack for each call; instead, the function prologue
2439 should increase the stack frame size by this amount.
2441 It is not proper to define both `PUSH_ROUNDING' and
2442 `ACCUMULATE_OUTGOING_ARGS'. */
2443 #define ACCUMULATE_OUTGOING_ARGS 1
2445 /* Offset from the argument pointer register to the first argument's
2446 address. On some machines it may depend on the data type of the
2449 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2450 the first argument's address.
2452 On the MIPS, we must skip the first argument position if we are
2453 returning a structure or a union, to account for its address being
2454 passed in $4. However, at the current time, this produces a compiler
2455 that can't bootstrap, so comment it out for now. */
2458 #define FIRST_PARM_OFFSET(FNDECL) \
2460 && TREE_TYPE (FNDECL) != 0 \
2461 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2462 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2463 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2467 #define FIRST_PARM_OFFSET(FNDECL) 0
2470 /* When a parameter is passed in a register, stack space is still
2471 allocated for it. For the MIPS, stack space must be allocated, cf
2472 Asm Lang Prog Guide page 7-8.
2474 BEWARE that some space is also allocated for non existing arguments
2475 in register. In case an argument list is of form GF used registers
2476 are a0 (a2,a3), but we should push over a1... */
2478 #define REG_PARM_STACK_SPACE(FNDECL) \
2479 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2481 /* Define this if it is the responsibility of the caller to
2482 allocate the area reserved for arguments passed in registers.
2483 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2484 of this macro is to determine whether the space is included in
2485 `current_function_outgoing_args_size'. */
2486 #define OUTGOING_REG_PARM_STACK_SPACE
2488 /* Align stack frames on 64 bits (Double Word ). */
2489 #ifndef STACK_BOUNDARY
2490 #define STACK_BOUNDARY 64
2493 /* Make sure 4 words are always allocated on the stack. */
2495 #ifndef STACK_ARGS_ADJUST
2496 #define STACK_ARGS_ADJUST(SIZE) \
2498 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2499 SIZE.constant = 4 * UNITS_PER_WORD; \
2504 /* A C expression that should indicate the number of bytes of its
2505 own arguments that a function pops on returning, or 0
2506 if the function pops no arguments and the caller must therefore
2507 pop them all after the function returns.
2509 FUNDECL is the declaration node of the function (as a tree).
2511 FUNTYPE is a C variable whose value is a tree node that
2512 describes the function in question. Normally it is a node of
2513 type `FUNCTION_TYPE' that describes the data type of the function.
2514 From this it is possible to obtain the data types of the value
2515 and arguments (if known).
2517 When a call to a library function is being considered, FUNTYPE
2518 will contain an identifier node for the library function. Thus,
2519 if you need to distinguish among various library functions, you
2520 can do so by their names. Note that "library function" in this
2521 context means a function used to perform arithmetic, whose name
2522 is known specially in the compiler and was not mentioned in the
2523 C code being compiled.
2525 STACK-SIZE is the number of bytes of arguments passed on the
2526 stack. If a variable number of bytes is passed, it is zero, and
2527 argument popping will always be the responsibility of the
2528 calling function. */
2530 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2533 /* Symbolic macros for the registers used to return integer and floating
2536 #define GP_RETURN (GP_REG_FIRST + 2)
2537 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2539 /* Symbolic macros for the first/last argument registers. */
2541 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2542 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2543 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2544 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2546 #define MAX_ARGS_IN_REGISTERS 4
2548 /* Define how to find the value returned by a library function
2549 assuming the value has mode MODE. Because we define
2550 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2551 PROMOTE_MODE does. */
2553 #define LIBCALL_VALUE(MODE) \
2555 ((GET_MODE_CLASS (MODE) != MODE_INT \
2556 || GET_MODE_SIZE (MODE) >= 4) \
2559 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2560 && (! TARGET_SINGLE_FLOAT \
2561 || GET_MODE_SIZE (MODE) <= 4)) \
2565 /* Define how to find the value returned by a function.
2566 VALTYPE is the data type of the value (as a tree).
2567 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2568 otherwise, FUNC is 0. */
2570 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2573 /* 1 if N is a possible register number for a function value.
2574 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2575 Currently, R2 and F0 are only implemented here (C has no complex type) */
2577 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2579 /* 1 if N is a possible register number for function argument passing.
2580 We have no FP argument registers when soft-float. When FP registers
2581 are 32 bits, we can't directly reference the odd numbered ones. */
2583 #define FUNCTION_ARG_REGNO_P(N) \
2584 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2585 || ((! TARGET_SOFT_FLOAT \
2586 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2587 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2588 && ! fixed_regs[N]))
2590 /* A C expression which can inhibit the returning of certain function
2591 values in registers, based on the type of value. A nonzero value says
2592 to return the function value in memory, just as large structures are
2593 always returned. Here TYPE will be a C expression of type
2594 `tree', representing the data type of the value.
2596 Note that values of mode `BLKmode' must be explicitly
2597 handled by this macro. Also, the option `-fpcc-struct-return'
2598 takes effect regardless of this macro. On most systems, it is
2599 possible to leave the macro undefined; this causes a default
2600 definition to be used, whose value is the constant 1 for BLKmode
2601 values, and 0 otherwise.
2603 GCC normally converts 1 byte structures into chars, 2 byte
2604 structs into shorts, and 4 byte structs into ints, and returns
2605 them this way. Defining the following macro overrides this,
2606 to give us MIPS cc compatibility. */
2608 #define RETURN_IN_MEMORY(TYPE) \
2609 (TYPE_MODE (TYPE) == BLKmode)
2611 /* A code distinguishing the floating point format of the target
2612 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2613 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2615 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2618 /* Define a data type for recording info about an argument list
2619 during the scan of that argument list. This data type should
2620 hold all necessary information about the function itself
2621 and about the args processed so far, enough to enable macros
2622 such as FUNCTION_ARG to determine where the next arg should go.
2624 On the mips16, we need to keep track of which floating point
2625 arguments were passed in general registers, but would have been
2626 passed in the FP regs if this were a 32 bit function, so that we
2627 can move them to the FP regs if we wind up calling a 32 bit
2628 function. We record this information in fp_code, encoded in base
2629 four. A zero digit means no floating point argument, a one digit
2630 means an SFmode argument, and a two digit means a DFmode argument,
2631 and a three digit is not used. The low order digit is the first
2632 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2633 an SFmode argument. ??? A more sophisticated approach will be
2634 needed if MIPS_ABI != ABI_32. */
2636 typedef struct mips_args {
2637 int gp_reg_found; /* whether a gp register was found yet */
2638 unsigned int arg_number; /* argument number */
2639 unsigned int arg_words; /* # total words the arguments take */
2640 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2641 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2642 int fp_code; /* Mode of FP arguments (mips16) */
2643 unsigned int num_adjusts; /* number of adjustments made */
2644 /* Adjustments made to args pass in regs. */
2645 /* ??? The size is doubled to work around a
2646 bug in the code that sets the adjustments
2648 int prototype; /* True if the function has a prototype. */
2649 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2652 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2653 for a call to a function whose data type is FNTYPE.
2654 For a library call, FNTYPE is 0.
2658 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2659 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2661 /* Update the data in CUM to advance over an argument
2662 of mode MODE and data type TYPE.
2663 (TYPE is null for libcalls where that information may not be available.) */
2665 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2666 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2668 /* Determine where to put an argument to a function.
2669 Value is zero to push the argument on the stack,
2670 or a hard register in which to store the argument.
2672 MODE is the argument's machine mode.
2673 TYPE is the data type of the argument (as a tree).
2674 This is null for libcalls where that information may
2676 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2677 the preceding args and about the function being called.
2678 NAMED is nonzero if this argument is a named parameter
2679 (otherwise it is an extra parameter matching an ellipsis). */
2681 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2682 function_arg( &CUM, MODE, TYPE, NAMED)
2684 /* For an arg passed partly in registers and partly in memory,
2685 this is the number of registers used.
2686 For args passed entirely in registers or entirely in memory, zero. */
2688 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2689 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2691 /* If defined, a C expression that gives the alignment boundary, in
2692 bits, of an argument with the specified mode and type. If it is
2693 not defined, `PARM_BOUNDARY' is used for all arguments. */
2695 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2697 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2699 : TYPE_ALIGN(TYPE)) \
2700 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2702 : GET_MODE_ALIGNMENT(MODE)))
2705 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2707 #define MUST_SAVE_REGISTER(regno) \
2708 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2709 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2710 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2712 /* ALIGN FRAMES on double word boundaries */
2713 #ifndef MIPS_STACK_ALIGN
2714 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2718 /* Define the `__builtin_va_list' type for the ABI. */
2719 #define BUILD_VA_LIST_TYPE(VALIST) \
2720 (VALIST) = mips_build_va_list ()
2722 /* Implement `va_start' for varargs and stdarg. */
2723 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2724 mips_va_start (stdarg, valist, nextarg)
2726 /* Implement `va_arg'. */
2727 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2728 mips_va_arg (valist, type)
2730 /* Output assembler code to FILE to increment profiler label # LABELNO
2731 for profiling a function entry. */
2733 #define FUNCTION_PROFILER(FILE, LABELNO) \
2735 if (TARGET_MIPS16) \
2736 sorry ("mips16 function profiling"); \
2737 fprintf (FILE, "\t.set\tnoreorder\n"); \
2738 fprintf (FILE, "\t.set\tnoat\n"); \
2739 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2740 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2741 fprintf (FILE, "\tjal\t_mcount\n"); \
2743 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2744 TARGET_64BIT ? "dsubu" : "subu", \
2745 reg_names[STACK_POINTER_REGNUM], \
2746 reg_names[STACK_POINTER_REGNUM], \
2747 Pmode == DImode ? 16 : 8); \
2748 fprintf (FILE, "\t.set\treorder\n"); \
2749 fprintf (FILE, "\t.set\tat\n"); \
2752 /* Define this macro if the code for function profiling should come
2753 before the function prologue. Normally, the profiling code comes
2756 /* #define PROFILE_BEFORE_PROLOGUE */
2758 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2759 the stack pointer does not matter. The value is tested only in
2760 functions that have frame pointers.
2761 No definition is equivalent to always zero. */
2763 #define EXIT_IGNORE_STACK 1
2766 /* A C statement to output, on the stream FILE, assembler code for a
2767 block of data that contains the constant parts of a trampoline.
2768 This code should not include a label--the label is taken care of
2771 #define TRAMPOLINE_TEMPLATE(STREAM) \
2773 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2774 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2775 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2776 if (Pmode == DImode) \
2778 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2779 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2783 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2784 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2786 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2787 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2788 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2789 if (Pmode == DImode) \
2791 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2792 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2796 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2797 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2801 /* A C expression for the size in bytes of the trampoline, as an
2804 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2806 /* Alignment required for trampolines, in bits. */
2808 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2810 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2811 program and data caches. */
2813 #ifndef CACHE_FLUSH_FUNC
2814 #define CACHE_FLUSH_FUNC "_flush_cache"
2817 /* A C statement to initialize the variable parts of a trampoline.
2818 ADDR is an RTX for the address of the trampoline; FNADDR is an
2819 RTX for the address of the nested function; STATIC_CHAIN is an
2820 RTX for the static chain value that should be passed to the
2821 function when it is called. */
2823 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2826 if (Pmode == DImode) \
2828 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2829 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2833 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2834 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2837 /* Flush both caches. We need to flush the data cache in case \
2838 the system has a write-back cache. */ \
2839 /* ??? Should check the return value for errors. */ \
2840 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2841 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2842 0, VOIDmode, 3, addr, Pmode, \
2843 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2844 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2847 /* Addressing modes, and classification of registers for them. */
2849 /* #define HAVE_POST_INCREMENT 0 */
2850 /* #define HAVE_POST_DECREMENT 0 */
2852 /* #define HAVE_PRE_DECREMENT 0 */
2853 /* #define HAVE_PRE_INCREMENT 0 */
2855 /* These assume that REGNO is a hard or pseudo reg number.
2856 They give nonzero only if REGNO is a hard reg of the suitable class
2857 or a pseudo reg currently allocated to a suitable hard reg.
2858 These definitions are NOT overridden anywhere. */
2860 #define BASE_REG_P(regno, mode) \
2862 ? (M16_REG_P (regno) \
2863 || (regno) == FRAME_POINTER_REGNUM \
2864 || (regno) == ARG_POINTER_REGNUM \
2865 || ((regno) == STACK_POINTER_REGNUM \
2866 && (GET_MODE_SIZE (mode) == 4 \
2867 || GET_MODE_SIZE (mode) == 8))) \
2870 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2871 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2874 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2875 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2877 #define REGNO_OK_FOR_INDEX_P(regno) 0
2878 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2879 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2881 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2882 and check its validity for a certain class.
2883 We have two alternate definitions for each of them.
2884 The usual definition accepts all pseudo regs; the other rejects them all.
2885 The symbol REG_OK_STRICT causes the latter definition to be used.
2887 Most source files want to accept pseudo regs in the hope that
2888 they will get allocated to the class that the insn wants them to be in.
2889 Some source files that are used after register allocation
2890 need to be strict. */
2892 #ifndef REG_OK_STRICT
2893 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2894 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2896 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2897 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2900 #define REG_OK_FOR_INDEX_P(X) 0
2903 /* Maximum number of registers that can appear in a valid memory address. */
2905 #define MAX_REGS_PER_ADDRESS 1
2907 /* A C compound statement with a conditional `goto LABEL;' executed
2908 if X (an RTX) is a legitimate memory address on the target
2909 machine for a memory operand of mode MODE.
2911 It usually pays to define several simpler macros to serve as
2912 subroutines for this one. Otherwise it may be too complicated
2915 This macro must exist in two variants: a strict variant and a
2916 non-strict one. The strict variant is used in the reload pass.
2917 It must be defined so that any pseudo-register that has not been
2918 allocated a hard register is considered a memory reference. In
2919 contexts where some kind of register is required, a
2920 pseudo-register with no hard register must be rejected.
2922 The non-strict variant is used in other passes. It must be
2923 defined to accept all pseudo-registers in every context where
2924 some kind of register is required.
2926 Compiler source files that want to use the strict variant of
2927 this macro define the macro `REG_OK_STRICT'. You should use an
2928 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2929 in that case and the non-strict variant otherwise.
2931 Typically among the subroutines used to define
2932 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2933 acceptable registers for various purposes (one for base
2934 registers, one for index registers, and so on). Then only these
2935 subroutine macros need have two variants; the higher levels of
2936 macros may be the same whether strict or not.
2938 Normally, constant addresses which are the sum of a `symbol_ref'
2939 and an integer are stored inside a `const' RTX to mark them as
2940 constant. Therefore, there is no need to recognize such sums
2941 specifically as legitimate addresses. Normally you would simply
2942 recognize any `const' as legitimate.
2944 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2945 constant sums that are not marked with `const'. It assumes
2946 that a naked `plus' indicates indexing. If so, then you *must*
2947 reject such naked constant sums as illegitimate addresses, so
2948 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2950 On some machines, whether a symbolic address is legitimate
2951 depends on the section that the address refers to. On these
2952 machines, define the macro `ENCODE_SECTION_INFO' to store the
2953 information into the `symbol_ref', and then check for it here.
2954 When you see a `const', you will have to look inside it to find
2955 the `symbol_ref' in order to determine the section. */
2958 #define GO_PRINTF(x) fprintf(stderr, (x))
2959 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2960 #define GO_DEBUG_RTX(x) debug_rtx(x)
2963 #define GO_PRINTF(x)
2964 #define GO_PRINTF2(x,y)
2965 #define GO_DEBUG_RTX(x)
2968 #ifdef REG_OK_STRICT
2969 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2971 if (mips_legitimate_address_p (MODE, X, 1)) \
2975 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2977 if (mips_legitimate_address_p (MODE, X, 0)) \
2982 /* A C expression that is 1 if the RTX X is a constant which is a
2983 valid address. This is defined to be the same as `CONSTANT_P (X)',
2984 but rejecting CONST_DOUBLE. */
2985 /* When pic, we must reject addresses of the form symbol+large int.
2986 This is because an instruction `sw $4,s+70000' needs to be converted
2987 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2988 assembler would use $at as a temp to load in the large offset. In this
2989 case $at is already in use. We convert such problem addresses to
2990 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2991 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2992 #define CONSTANT_ADDRESS_P(X) \
2993 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2994 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2995 || (GET_CODE (X) == CONST \
2996 && ! (flag_pic && pic_address_needs_scratch (X)) \
2997 && (mips_abi == ABI_32 \
2998 || mips_abi == ABI_O64 \
2999 || mips_abi == ABI_EABI))) \
3000 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
3002 /* Define this, so that when PIC, reload won't try to reload invalid
3003 addresses which require two reload registers. */
3005 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3007 /* Nonzero if the constant value X is a legitimate general operand.
3008 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3010 At present, GAS doesn't understand li.[sd], so don't allow it
3011 to be generated at present. Also, the MIPS assembler does not
3012 grok li.d Infinity. */
3014 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3015 Note that the Irix 6 assembler problem may already be fixed.
3016 Note also that the GET_CODE (X) == CONST test catches the mips16
3017 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3018 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3019 ABI_64 to work together, we'll need to fix this. */
3020 #define LEGITIMATE_CONSTANT_P(X) \
3021 ((GET_CODE (X) != CONST_DOUBLE \
3022 || mips_const_double_ok (X, GET_MODE (X))) \
3023 && ! (GET_CODE (X) == CONST \
3025 && (mips_abi == ABI_N32 \
3026 || mips_abi == ABI_64)) \
3027 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3029 /* A C compound statement that attempts to replace X with a valid
3030 memory address for an operand of mode MODE. WIN will be a C
3031 statement label elsewhere in the code; the macro definition may
3034 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3036 to avoid further processing if the address has become legitimate.
3038 X will always be the result of a call to `break_out_memory_refs',
3039 and OLDX will be the operand that was given to that function to
3042 The code generated by this macro should not alter the
3043 substructure of X. If it transforms X into a more legitimate
3044 form, it should assign X (which will always be a C variable) a
3047 It is not necessary for this macro to come up with a legitimate
3048 address. The compiler has standard ways of doing so in all
3049 cases. In fact, it is safe for this macro to do nothing. But
3050 often a machine-dependent strategy can generate better code.
3052 For the MIPS, transform:
3054 memory(X + <large int>)
3058 Y = <large int> & ~0x7fff;
3060 memory (Z + (<large int> & 0x7fff));
3062 This is for CSE to find several similar references, and only use one Z.
3064 When PIC, convert addresses of the form memory (symbol+large int) to
3065 memory (reg+large int). */
3068 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3070 register rtx xinsn = (X); \
3072 if (TARGET_DEBUG_B_MODE) \
3074 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3075 GO_DEBUG_RTX (xinsn); \
3078 if (mips_split_addresses && mips_check_split (X, MODE)) \
3080 /* ??? Is this ever executed? */ \
3081 X = gen_rtx_LO_SUM (Pmode, \
3082 copy_to_mode_reg (Pmode, \
3083 gen_rtx (HIGH, Pmode, X)), \
3088 if (GET_CODE (xinsn) == CONST \
3089 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3090 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3091 || (mips_abi != ABI_32 \
3092 && mips_abi != ABI_O64 \
3093 && mips_abi != ABI_EABI))) \
3095 rtx ptr_reg = gen_reg_rtx (Pmode); \
3096 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3098 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3100 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3101 if (SMALL_INT (constant)) \
3103 /* Otherwise we fall through so the code below will fix the \
3108 if (GET_CODE (xinsn) == PLUS) \
3110 register rtx xplus0 = XEXP (xinsn, 0); \
3111 register rtx xplus1 = XEXP (xinsn, 1); \
3112 register enum rtx_code code0 = GET_CODE (xplus0); \
3113 register enum rtx_code code1 = GET_CODE (xplus1); \
3115 if (code0 != REG && code1 == REG) \
3117 xplus0 = XEXP (xinsn, 1); \
3118 xplus1 = XEXP (xinsn, 0); \
3119 code0 = GET_CODE (xplus0); \
3120 code1 = GET_CODE (xplus1); \
3123 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3124 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3126 rtx int_reg = gen_reg_rtx (Pmode); \
3127 rtx ptr_reg = gen_reg_rtx (Pmode); \
3129 emit_move_insn (int_reg, \
3130 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3132 emit_insn (gen_rtx_SET (VOIDmode, \
3134 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3136 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3141 if (TARGET_DEBUG_B_MODE) \
3142 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3146 /* A C statement or compound statement with a conditional `goto
3147 LABEL;' executed if memory address X (an RTX) can have different
3148 meanings depending on the machine mode of the memory reference it
3151 Autoincrement and autodecrement addresses typically have
3152 mode-dependent effects because the amount of the increment or
3153 decrement is the size of the operand being addressed. Some
3154 machines have other mode-dependent addresses. Many RISC machines
3155 have no mode-dependent addresses.
3157 You may assume that ADDR is a valid address for the machine. */
3159 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3162 /* Define this macro if references to a symbol must be treated
3163 differently depending on something about the variable or
3164 function named by the symbol (such as what section it is in).
3166 The macro definition, if any, is executed immediately after the
3167 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3168 The value of the rtl will be a `mem' whose address is a
3171 The usual thing for this macro to do is to a flag in the
3172 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3173 name string in the `symbol_ref' (if one bit is not enough
3176 The best way to modify the name string is by adding text to the
3177 beginning, with suitable punctuation to prevent any ambiguity.
3178 Allocate the new name in `saveable_obstack'. You will have to
3179 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3180 and output the name accordingly.
3182 You can also check the information stored in the `symbol_ref' in
3183 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3184 `PRINT_OPERAND_ADDRESS'.
3186 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3189 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3190 symbols which are not in the .text section.
3192 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3193 constants which are put in the .text section. We also record the
3194 total length of all such strings; this total is used to decide
3195 whether we need to split the constant table, and need not be
3198 When not mips16 code nor embedded PIC, if a symbol is in a
3199 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3200 splitting the reference so that gas can generate a gp relative
3203 When TARGET_EMBEDDED_DATA is set, we assume that all const
3204 variables will be stored in ROM, which is too far from %gp to use
3205 %gprel addressing. Note that (1) we include "extern const"
3206 variables in this, which mips_select_section doesn't, and (2) we
3207 can't always tell if they're really const (they might be const C++
3208 objects with non-const constructors), so we err on the side of
3209 caution and won't use %gprel anyway (otherwise we'd have to defer
3210 this decision to the linker/loader). The handling of extern consts
3211 is why the DECL_INITIAL macros differ from mips_select_section.
3213 If you are changing this macro, you should look at
3214 mips_select_section and see if it needs a similar change. */
3216 #define ENCODE_SECTION_INFO(DECL) \
3219 if (TARGET_MIPS16) \
3221 if (TREE_CODE (DECL) == STRING_CST \
3222 && ! flag_writable_strings \
3223 /* If this string is from a function, and the function will \
3224 go in a gnu linkonce section, then we can't directly \
3225 access the string. This gets an assembler error \
3226 "unsupported PC relative reference to different section".\
3227 If we modify SELECT_SECTION to put it in function_section\
3228 instead of text_section, it still fails because \
3229 DECL_SECTION_NAME isn't set until assemble_start_function.\
3230 If we fix that, it still fails because strings are shared\
3231 among multiple functions, and we have cross section \
3232 references again. We force it to work by putting string \
3233 addresses in the constant pool and indirecting. */ \
3234 && (! current_function_decl \
3235 || ! DECL_ONE_ONLY (current_function_decl))) \
3237 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3238 mips_string_length += TREE_STRING_LENGTH (DECL); \
3242 if (TARGET_EMBEDDED_DATA \
3243 && (TREE_CODE (DECL) == VAR_DECL \
3244 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3245 && (!DECL_INITIAL (DECL) \
3246 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3248 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3251 else if (TARGET_EMBEDDED_PIC) \
3253 if (TREE_CODE (DECL) == VAR_DECL) \
3254 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3255 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3256 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3257 else if (TREE_CODE (DECL) == STRING_CST \
3258 && ! flag_writable_strings) \
3259 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3261 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3264 else if (TREE_CODE (DECL) == VAR_DECL \
3265 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3266 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3268 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3271 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3274 /* We can not perform GP optimizations on variables which are in \
3275 specific sections, except for .sdata and .sbss which are \
3277 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3278 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3280 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3282 if (size > 0 && size <= mips_section_threshold) \
3283 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3286 else if (HALF_PIC_P ()) \
3288 HALF_PIC_ENCODE (DECL); \
3293 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3294 'the start of the function that this code is output in'. */
3296 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3297 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3298 asm_fprintf ((FILE), "%U%s", \
3299 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3301 asm_fprintf ((FILE), "%U%s", (NAME))
3303 /* The mips16 wants the constant pool to be after the function,
3304 because the PC relative load instructions use unsigned offsets. */
3306 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3308 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3309 mips_string_length = 0;
3312 /* In mips16 mode, put most string constants after the function. */
3313 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3314 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3317 /* Specify the machine mode that this machine uses
3318 for the index in the tablejump instruction.
3319 ??? Using HImode in mips16 mode can cause overflow. However, the
3320 overflow is no more likely than the overflow in a branch
3321 instruction. Large functions can currently break in both ways. */
3322 #define CASE_VECTOR_MODE \
3323 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3325 /* Define as C expression which evaluates to nonzero if the tablejump
3326 instruction expects the table to contain offsets from the address of the
3328 Do not define this if the table should contain absolute addresses. */
3329 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3331 /* Specify the tree operation to be used to convert reals to integers. */
3332 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3334 /* This is the kind of divide that is easiest to do in the general case. */
3335 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3337 /* Define this as 1 if `char' should by default be signed; else as 0. */
3338 #ifndef DEFAULT_SIGNED_CHAR
3339 #define DEFAULT_SIGNED_CHAR 1
3342 /* Max number of bytes we can move from memory to memory
3343 in one reasonably fast instruction. */
3344 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3345 #define MAX_MOVE_MAX 8
3347 /* Define this macro as a C expression which is nonzero if
3348 accessing less than a word of memory (i.e. a `char' or a
3349 `short') is no faster than accessing a word of memory, i.e., if
3350 such access require more than one instruction or if there is no
3351 difference in cost between byte and (aligned) word loads.
3353 On RISC machines, it tends to generate better code to define
3354 this as 1, since it avoids making a QI or HI mode register. */
3355 #define SLOW_BYTE_ACCESS 1
3357 /* We assume that the store-condition-codes instructions store 0 for false
3358 and some other value for true. This is the value stored for true. */
3360 #define STORE_FLAG_VALUE 1
3362 /* Define this if zero-extension is slow (more than one real instruction). */
3363 #define SLOW_ZERO_EXTEND
3365 /* Define this to be nonzero if shift instructions ignore all but the low-order
3367 #define SHIFT_COUNT_TRUNCATED 1
3369 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3370 is done just by pretending it is already truncated. */
3371 /* In 64 bit mode, 32 bit instructions require that register values be properly
3372 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3373 converts a value >32 bits to a value <32 bits. */
3374 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3375 Something needs to be done about this. Perhaps not use any 32 bit
3376 instructions? Perhaps use PROMOTE_MODE? */
3377 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3378 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3380 /* Specify the machine mode that pointers have.
3381 After generation of rtl, the compiler makes no further distinction
3382 between pointers and any other objects of this machine mode.
3384 For MIPS we make pointers are the smaller of longs and gp-registers. */
3387 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3390 /* A function address in a call instruction
3391 is a word address (for indexing purposes)
3392 so give the MEM rtx a words's mode. */
3394 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3396 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3397 memset, instead of the BSD functions bcopy and bzero. */
3399 #if defined(MIPS_SYSV) || defined(OSF_OS)
3400 #define TARGET_MEM_FUNCTIONS
3404 /* A part of a C `switch' statement that describes the relative
3405 costs of constant RTL expressions. It must contain `case'
3406 labels for expression codes `const_int', `const', `symbol_ref',
3407 `label_ref' and `const_double'. Each case must ultimately reach
3408 a `return' statement to return the relative cost of the use of
3409 that kind of constant value in an expression. The cost may
3410 depend on the precise value of the constant, which is available
3411 for examination in X.
3413 CODE is the expression code--redundant, since it can be obtained
3414 with `GET_CODE (X)'. */
3416 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3418 if (! TARGET_MIPS16) \
3420 /* Always return 0, since we don't have different sized \
3421 instructions, hence different costs according to Richard \
3425 if ((OUTER_CODE) == SET) \
3427 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3429 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3430 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3431 return COSTS_N_INSNS (1); \
3433 return COSTS_N_INSNS (2); \
3435 /* A PLUS could be an address. We don't want to force an address \
3436 to use a register, so accept any signed 16 bit value without \
3438 if ((OUTER_CODE) == PLUS \
3439 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3441 /* A number between 1 and 8 inclusive is efficient for a shift. \
3442 Otherwise, we will need an extended instruction. */ \
3443 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3444 || (OUTER_CODE) == LSHIFTRT) \
3446 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3448 return COSTS_N_INSNS (1); \
3450 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3451 if ((OUTER_CODE) == XOR \
3452 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3454 /* We may be able to use slt or sltu for a comparison with a \
3455 signed 16 bit value. (The boundary conditions aren't quite \
3456 right, but this is just a heuristic anyhow.) */ \
3457 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3458 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3459 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3460 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3461 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3463 /* Equality comparisons with 0 are cheap. */ \
3464 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3465 && INTVAL (X) == 0) \
3468 /* Otherwise, work out the cost to load the value into a \
3470 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3471 return COSTS_N_INSNS (1); \
3472 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3473 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3474 return COSTS_N_INSNS (2); \
3476 return COSTS_N_INSNS (3); \
3479 return COSTS_N_INSNS (2); \
3483 rtx offset = const0_rtx; \
3484 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3486 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3488 /* Treat this like a signed 16 bit CONST_INT. */ \
3489 if ((OUTER_CODE) == PLUS) \
3491 else if ((OUTER_CODE) == SET) \
3492 return COSTS_N_INSNS (1); \
3494 return COSTS_N_INSNS (2); \
3497 if (GET_CODE (symref) == LABEL_REF) \
3498 return COSTS_N_INSNS (2); \
3500 if (GET_CODE (symref) != SYMBOL_REF) \
3501 return COSTS_N_INSNS (4); \
3503 /* let's be paranoid.... */ \
3504 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3505 return COSTS_N_INSNS (2); \
3507 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3511 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3513 case CONST_DOUBLE: \
3516 if (TARGET_MIPS16) \
3517 return COSTS_N_INSNS (4); \
3518 split_double (X, &high, &low); \
3519 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3520 || low == CONST0_RTX (GET_MODE (low))) \
3524 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3525 This can be used, for example, to indicate how costly a multiply
3526 instruction is. In writing this macro, you can use the construct
3527 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3529 This macro is optional; do not define it if the default cost
3530 assumptions are adequate for the target machine.
3532 If -mdebugd is used, change the multiply cost to 2, so multiply by
3533 a constant isn't converted to a series of shifts. This helps
3534 strength reduction, and also makes it easier to identify what the
3535 compiler is doing. */
3537 /* ??? Fix this to be right for the R8000. */
3538 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3541 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3542 if (simple_memory_operand (X, GET_MODE (X))) \
3543 return COSTS_N_INSNS (num_words); \
3545 return COSTS_N_INSNS (2*num_words); \
3549 return COSTS_N_INSNS (6); \
3552 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3557 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3558 return COSTS_N_INSNS (2); \
3565 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3566 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3572 enum machine_mode xmode = GET_MODE (X); \
3573 if (xmode == SFmode || xmode == DFmode) \
3574 return COSTS_N_INSNS (1); \
3576 return COSTS_N_INSNS (4); \
3582 enum machine_mode xmode = GET_MODE (X); \
3583 if (xmode == SFmode || xmode == DFmode) \
3587 return COSTS_N_INSNS (2); \
3588 else if (TUNE_MIPS6000) \
3589 return COSTS_N_INSNS (3); \
3591 return COSTS_N_INSNS (6); \
3594 if (xmode == DImode && !TARGET_64BIT) \
3595 return COSTS_N_INSNS (4); \
3601 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3608 enum machine_mode xmode = GET_MODE (X); \
3609 if (xmode == SFmode) \
3614 return COSTS_N_INSNS (4); \
3615 else if (TUNE_MIPS6000) \
3616 return COSTS_N_INSNS (5); \
3618 return COSTS_N_INSNS (7); \
3621 if (xmode == DFmode) \
3626 return COSTS_N_INSNS (5); \
3627 else if (TUNE_MIPS6000) \
3628 return COSTS_N_INSNS (6); \
3630 return COSTS_N_INSNS (8); \
3633 if (TUNE_MIPS3000) \
3634 return COSTS_N_INSNS (12); \
3635 else if (TUNE_MIPS3900) \
3636 return COSTS_N_INSNS (2); \
3637 else if (TUNE_MIPS6000) \
3638 return COSTS_N_INSNS (17); \
3639 else if (TUNE_MIPS5000) \
3640 return COSTS_N_INSNS (5); \
3642 return COSTS_N_INSNS (10); \
3648 enum machine_mode xmode = GET_MODE (X); \
3649 if (xmode == SFmode) \
3653 return COSTS_N_INSNS (12); \
3654 else if (TUNE_MIPS6000) \
3655 return COSTS_N_INSNS (15); \
3657 return COSTS_N_INSNS (23); \
3660 if (xmode == DFmode) \
3664 return COSTS_N_INSNS (19); \
3665 else if (TUNE_MIPS6000) \
3666 return COSTS_N_INSNS (16); \
3668 return COSTS_N_INSNS (36); \
3671 /* fall through */ \
3677 return COSTS_N_INSNS (35); \
3678 else if (TUNE_MIPS6000) \
3679 return COSTS_N_INSNS (38); \
3680 else if (TUNE_MIPS5000) \
3681 return COSTS_N_INSNS (36); \
3683 return COSTS_N_INSNS (69); \
3686 /* A sign extend from SImode to DImode in 64 bit mode is often \
3687 zero instructions, because the result can often be used \
3688 directly by another instruction; we'll call it one. */ \
3689 if (TARGET_64BIT && GET_MODE (X) == DImode \
3690 && GET_MODE (XEXP (X, 0)) == SImode) \
3691 return COSTS_N_INSNS (1); \
3693 return COSTS_N_INSNS (2); \
3696 if (TARGET_64BIT && GET_MODE (X) == DImode \
3697 && GET_MODE (XEXP (X, 0)) == SImode) \
3698 return COSTS_N_INSNS (2); \
3700 return COSTS_N_INSNS (1);
3702 /* An expression giving the cost of an addressing mode that
3703 contains ADDRESS. If not defined, the cost is computed from the
3704 form of the ADDRESS expression and the `CONST_COSTS' values.
3706 For most CISC machines, the default cost is a good approximation
3707 of the true cost of the addressing mode. However, on RISC
3708 machines, all instructions normally have the same length and
3709 execution time. Hence all addresses will have equal costs.
3711 In cases where more than one form of an address is known, the
3712 form with the lowest cost will be used. If multiple forms have
3713 the same, lowest, cost, the one that is the most complex will be
3716 For example, suppose an address that is equal to the sum of a
3717 register and a constant is used twice in the same basic block.
3718 When this macro is not defined, the address will be computed in
3719 a register and memory references will be indirect through that
3720 register. On machines where the cost of the addressing mode
3721 containing the sum is no higher than that of a simple indirect
3722 reference, this will produce an additional instruction and
3723 possibly require an additional register. Proper specification
3724 of this macro eliminates this overhead for such machines.
3726 Similar use of this macro is made in strength reduction of loops.
3728 ADDRESS need not be valid as an address. In such a case, the
3729 cost is not relevant and can be any value; invalid addresses
3730 need not be assigned a different cost.
3732 On machines where an address involving more than one register is
3733 as cheap as an address computation involving only one register,
3734 defining `ADDRESS_COST' to reflect this can cause two registers
3735 to be live over a region of code where only one would have been
3736 if `ADDRESS_COST' were not defined in that manner. This effect
3737 should be considered in the definition of this macro.
3738 Equivalent costs should probably only be given to addresses with
3739 different numbers of registers on machines with lots of registers.
3741 This macro will normally either not be defined or be defined as
3744 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3746 /* A C expression for the cost of moving data from a register in
3747 class FROM to one in class TO. The classes are expressed using
3748 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3749 the default; other values are interpreted relative to that.
3751 It is not required that the cost always equal 2 when FROM is the
3752 same as TO; on some machines it is expensive to move between
3753 registers if they are not general registers.
3755 If reload sees an insn consisting of a single `set' between two
3756 hard registers, and if `REGISTER_MOVE_COST' applied to their
3757 classes returns a value of 2, reload does not check to ensure
3758 that the constraints of the insn are met. Setting a cost of
3759 other than 2 will allow reload to verify that the constraints are
3760 met. You should do this if the `movM' pattern's constraints do
3761 not allow such copying.
3763 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3764 registers the same as for one of moving general registers to
3765 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3766 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3767 isn't clear if it is wise. And it might not work in all cases. We
3768 could solve the DImode LO reg problem by using a multiply, just like
3769 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3770 by using divide instructions. divu puts the remainder in the HI
3771 reg, so doing a divide by -1 will move the value in the HI reg for
3772 all values except -1. We could handle that case by using a signed
3773 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3774 compare/branch to test the input value to see which instruction we
3775 need to use. This gets pretty messy, but it is feasible. */
3777 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3778 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3779 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3780 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3781 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3782 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3783 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3784 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3785 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3786 : (((FROM) == HI_REG || (FROM) == LO_REG \
3787 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3788 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3789 : (((TO) == HI_REG || (TO) == LO_REG \
3790 || (TO) == MD_REGS || (TO) == HILO_REG) \
3791 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3792 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3793 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3796 /* ??? Fix this to be right for the R8000. */
3797 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3798 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3799 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3801 /* Define if copies to/from condition code registers should be avoided.
3803 This is needed for the MIPS because reload_outcc is not complete;
3804 it needs to handle cases where the source is a general or another
3805 condition code register. */
3806 #define AVOID_CCMODE_COPIES
3808 /* A C expression for the cost of a branch instruction. A value of
3809 1 is the default; other values are interpreted relative to that. */
3811 /* ??? Fix this to be right for the R8000. */
3812 #define BRANCH_COST \
3814 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3817 /* If defined, modifies the length assigned to instruction INSN as a
3818 function of the context in which it is used. LENGTH is an lvalue
3819 that contains the initially computed length of the insn and should
3820 be updated with the correct length of the insn. */
3821 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3822 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3825 /* Optionally define this if you have added predicates to
3826 `MACHINE.c'. This macro is called within an initializer of an
3827 array of structures. The first field in the structure is the
3828 name of a predicate and the second field is an array of rtl
3829 codes. For each predicate, list all rtl codes that can be in
3830 expressions matched by the predicate. The list should have a
3831 trailing comma. Here is an example of two entries in the list
3832 for a typical RISC machine:
3834 #define PREDICATE_CODES \
3835 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3836 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3838 Defining this macro does not affect the generated code (however,
3839 incorrect definitions that omit an rtl code that may be matched
3840 by the predicate can cause the compiler to malfunction).
3841 Instead, it allows the table built by `genrecog' to be more
3842 compact and efficient, thus speeding up the compiler. The most
3843 important predicates to include in the list specified by this
3844 macro are thoses used in the most insn patterns. */
3846 #define PREDICATE_CODES \
3847 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3848 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3849 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3850 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3851 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3852 {"small_int", { CONST_INT }}, \
3853 {"large_int", { CONST_INT }}, \
3854 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3855 {"const_float_1_operand", { CONST_DOUBLE }}, \
3856 {"simple_memory_operand", { MEM, SUBREG }}, \
3857 {"equality_op", { EQ, NE }}, \
3858 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3860 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3861 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3862 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3863 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3864 SYMBOL_REF, LABEL_REF, SUBREG, \
3866 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3867 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3868 MEM, SIGN_EXTEND }}, \
3869 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3870 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3872 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3874 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3876 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3877 SYMBOL_REF, LABEL_REF, SUBREG, \
3878 REG, SIGN_EXTEND }}, \
3879 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3880 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3881 CONST_DOUBLE, CONST }}, \
3882 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3883 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3885 /* A list of predicates that do special things with modes, and so
3886 should not elicit warnings for VOIDmode match_operand. */
3888 #define SPECIAL_MODE_PREDICATES \
3889 "pc_or_label_operand",
3892 /* If defined, a C statement to be executed just prior to the
3893 output of assembler code for INSN, to modify the extracted
3894 operands so they will be output differently.
3896 Here the argument OPVEC is the vector containing the operands
3897 extracted from INSN, and NOPERANDS is the number of elements of
3898 the vector which contain meaningful data for this insn. The
3899 contents of this vector are what will be used to convert the
3900 insn template into assembler code, so you can change the
3901 assembler output by changing the contents of the vector.
3903 We use it to check if the current insn needs a nop in front of it
3904 because of load delays, and also to update the delay slot
3907 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3908 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3911 /* Control the assembler format that we output. */
3913 /* Output at beginning of assembler file.
3914 If we are optimizing to use the global pointer, create a temporary
3915 file to hold all of the text stuff, and write it out to the end.
3916 This is needed because the MIPS assembler is evidently one pass,
3917 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3918 declaration when the code is processed, it generates a two
3919 instruction sequence. */
3921 #undef ASM_FILE_START
3922 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3924 /* Output to assembler file text saying following lines
3925 may contain character constants, extra white space, comments, etc. */
3928 #define ASM_APP_ON " #APP\n"
3931 /* Output to assembler file text saying following lines
3932 no longer contain unusual constructs. */
3935 #define ASM_APP_OFF " #NO_APP\n"
3938 /* How to refer to registers in assembler output.
3939 This sequence is indexed by compiler's hard-register-number (see above).
3941 In order to support the two different conventions for register names,
3942 we use the name of a table set up in mips.c, which is overwritten
3943 if -mrnames is used. */
3945 #define REGISTER_NAMES \
3947 &mips_reg_names[ 0][0], \
3948 &mips_reg_names[ 1][0], \
3949 &mips_reg_names[ 2][0], \
3950 &mips_reg_names[ 3][0], \
3951 &mips_reg_names[ 4][0], \
3952 &mips_reg_names[ 5][0], \
3953 &mips_reg_names[ 6][0], \
3954 &mips_reg_names[ 7][0], \
3955 &mips_reg_names[ 8][0], \
3956 &mips_reg_names[ 9][0], \
3957 &mips_reg_names[10][0], \
3958 &mips_reg_names[11][0], \
3959 &mips_reg_names[12][0], \
3960 &mips_reg_names[13][0], \
3961 &mips_reg_names[14][0], \
3962 &mips_reg_names[15][0], \
3963 &mips_reg_names[16][0], \
3964 &mips_reg_names[17][0], \
3965 &mips_reg_names[18][0], \
3966 &mips_reg_names[19][0], \
3967 &mips_reg_names[20][0], \
3968 &mips_reg_names[21][0], \
3969 &mips_reg_names[22][0], \
3970 &mips_reg_names[23][0], \
3971 &mips_reg_names[24][0], \
3972 &mips_reg_names[25][0], \
3973 &mips_reg_names[26][0], \
3974 &mips_reg_names[27][0], \
3975 &mips_reg_names[28][0], \
3976 &mips_reg_names[29][0], \
3977 &mips_reg_names[30][0], \
3978 &mips_reg_names[31][0], \
3979 &mips_reg_names[32][0], \
3980 &mips_reg_names[33][0], \
3981 &mips_reg_names[34][0], \
3982 &mips_reg_names[35][0], \
3983 &mips_reg_names[36][0], \
3984 &mips_reg_names[37][0], \
3985 &mips_reg_names[38][0], \
3986 &mips_reg_names[39][0], \
3987 &mips_reg_names[40][0], \
3988 &mips_reg_names[41][0], \
3989 &mips_reg_names[42][0], \
3990 &mips_reg_names[43][0], \
3991 &mips_reg_names[44][0], \
3992 &mips_reg_names[45][0], \
3993 &mips_reg_names[46][0], \
3994 &mips_reg_names[47][0], \
3995 &mips_reg_names[48][0], \
3996 &mips_reg_names[49][0], \
3997 &mips_reg_names[50][0], \
3998 &mips_reg_names[51][0], \
3999 &mips_reg_names[52][0], \
4000 &mips_reg_names[53][0], \
4001 &mips_reg_names[54][0], \
4002 &mips_reg_names[55][0], \
4003 &mips_reg_names[56][0], \
4004 &mips_reg_names[57][0], \
4005 &mips_reg_names[58][0], \
4006 &mips_reg_names[59][0], \
4007 &mips_reg_names[60][0], \
4008 &mips_reg_names[61][0], \
4009 &mips_reg_names[62][0], \
4010 &mips_reg_names[63][0], \
4011 &mips_reg_names[64][0], \
4012 &mips_reg_names[65][0], \
4013 &mips_reg_names[66][0], \
4014 &mips_reg_names[67][0], \
4015 &mips_reg_names[68][0], \
4016 &mips_reg_names[69][0], \
4017 &mips_reg_names[70][0], \
4018 &mips_reg_names[71][0], \
4019 &mips_reg_names[72][0], \
4020 &mips_reg_names[73][0], \
4021 &mips_reg_names[74][0], \
4022 &mips_reg_names[75][0], \
4025 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4026 So define this for it. */
4027 #define DEBUG_REGISTER_NAMES \
4029 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4030 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4031 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4032 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4033 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4034 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4035 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4036 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4037 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4038 "$fcc5","$fcc6","$fcc7","$rap" \
4041 /* If defined, a C initializer for an array of structures
4042 containing a name and a register number. This macro defines
4043 additional names for hard registers, thus allowing the `asm'
4044 option in declarations to refer to registers using alternate
4047 We define both names for the integer registers here. */
4049 #define ADDITIONAL_REGISTER_NAMES \
4051 { "$0", 0 + GP_REG_FIRST }, \
4052 { "$1", 1 + GP_REG_FIRST }, \
4053 { "$2", 2 + GP_REG_FIRST }, \
4054 { "$3", 3 + GP_REG_FIRST }, \
4055 { "$4", 4 + GP_REG_FIRST }, \
4056 { "$5", 5 + GP_REG_FIRST }, \
4057 { "$6", 6 + GP_REG_FIRST }, \
4058 { "$7", 7 + GP_REG_FIRST }, \
4059 { "$8", 8 + GP_REG_FIRST }, \
4060 { "$9", 9 + GP_REG_FIRST }, \
4061 { "$10", 10 + GP_REG_FIRST }, \
4062 { "$11", 11 + GP_REG_FIRST }, \
4063 { "$12", 12 + GP_REG_FIRST }, \
4064 { "$13", 13 + GP_REG_FIRST }, \
4065 { "$14", 14 + GP_REG_FIRST }, \
4066 { "$15", 15 + GP_REG_FIRST }, \
4067 { "$16", 16 + GP_REG_FIRST }, \
4068 { "$17", 17 + GP_REG_FIRST }, \
4069 { "$18", 18 + GP_REG_FIRST }, \
4070 { "$19", 19 + GP_REG_FIRST }, \
4071 { "$20", 20 + GP_REG_FIRST }, \
4072 { "$21", 21 + GP_REG_FIRST }, \
4073 { "$22", 22 + GP_REG_FIRST }, \
4074 { "$23", 23 + GP_REG_FIRST }, \
4075 { "$24", 24 + GP_REG_FIRST }, \
4076 { "$25", 25 + GP_REG_FIRST }, \
4077 { "$26", 26 + GP_REG_FIRST }, \
4078 { "$27", 27 + GP_REG_FIRST }, \
4079 { "$28", 28 + GP_REG_FIRST }, \
4080 { "$29", 29 + GP_REG_FIRST }, \
4081 { "$30", 30 + GP_REG_FIRST }, \
4082 { "$31", 31 + GP_REG_FIRST }, \
4083 { "$sp", 29 + GP_REG_FIRST }, \
4084 { "$fp", 30 + GP_REG_FIRST }, \
4085 { "at", 1 + GP_REG_FIRST }, \
4086 { "v0", 2 + GP_REG_FIRST }, \
4087 { "v1", 3 + GP_REG_FIRST }, \
4088 { "a0", 4 + GP_REG_FIRST }, \
4089 { "a1", 5 + GP_REG_FIRST }, \
4090 { "a2", 6 + GP_REG_FIRST }, \
4091 { "a3", 7 + GP_REG_FIRST }, \
4092 { "t0", 8 + GP_REG_FIRST }, \
4093 { "t1", 9 + GP_REG_FIRST }, \
4094 { "t2", 10 + GP_REG_FIRST }, \
4095 { "t3", 11 + GP_REG_FIRST }, \
4096 { "t4", 12 + GP_REG_FIRST }, \
4097 { "t5", 13 + GP_REG_FIRST }, \
4098 { "t6", 14 + GP_REG_FIRST }, \
4099 { "t7", 15 + GP_REG_FIRST }, \
4100 { "s0", 16 + GP_REG_FIRST }, \
4101 { "s1", 17 + GP_REG_FIRST }, \
4102 { "s2", 18 + GP_REG_FIRST }, \
4103 { "s3", 19 + GP_REG_FIRST }, \
4104 { "s4", 20 + GP_REG_FIRST }, \
4105 { "s5", 21 + GP_REG_FIRST }, \
4106 { "s6", 22 + GP_REG_FIRST }, \
4107 { "s7", 23 + GP_REG_FIRST }, \
4108 { "t8", 24 + GP_REG_FIRST }, \
4109 { "t9", 25 + GP_REG_FIRST }, \
4110 { "k0", 26 + GP_REG_FIRST }, \
4111 { "k1", 27 + GP_REG_FIRST }, \
4112 { "gp", 28 + GP_REG_FIRST }, \
4113 { "sp", 29 + GP_REG_FIRST }, \
4114 { "fp", 30 + GP_REG_FIRST }, \
4115 { "ra", 31 + GP_REG_FIRST }, \
4116 { "$sp", 29 + GP_REG_FIRST }, \
4117 { "$fp", 30 + GP_REG_FIRST } \
4120 /* A C compound statement to output to stdio stream STREAM the
4121 assembler syntax for an instruction operand X. X is an RTL
4124 CODE is a value that can be used to specify one of several ways
4125 of printing the operand. It is used when identical operands
4126 must be printed differently depending on the context. CODE
4127 comes from the `%' specification that was used to request
4128 printing of the operand. If the specification was just `%DIGIT'
4129 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4130 is the ASCII code for LTR.
4132 If X is a register, this macro should print the register's name.
4133 The names can be found in an array `reg_names' whose type is
4134 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4136 When the machine description has a specification `%PUNCT' (a `%'
4137 followed by a punctuation character), this macro is called with
4138 a null pointer for X and the punctuation character for CODE.
4140 See mips.c for the MIPS specific codes. */
4142 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4144 /* A C expression which evaluates to true if CODE is a valid
4145 punctuation character for use in the `PRINT_OPERAND' macro. If
4146 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4147 punctuation characters (except for the standard one, `%') are
4148 used in this way. */
4150 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4152 /* A C compound statement to output to stdio stream STREAM the
4153 assembler syntax for an instruction operand that is a memory
4154 reference whose address is ADDR. ADDR is an RTL expression.
4156 On some machines, the syntax for a symbolic address depends on
4157 the section that the address refers to. On these machines,
4158 define the macro `ENCODE_SECTION_INFO' to store the information
4159 into the `symbol_ref', and then check for it here. */
4161 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4164 /* A C statement, to be executed after all slot-filler instructions
4165 have been output. If necessary, call `dbr_sequence_length' to
4166 determine the number of slots filled in a sequence (zero if not
4167 currently outputting a sequence), to decide how many no-ops to
4168 output, or whatever.
4170 Don't define this macro if it has nothing to do, but it is
4171 helpful in reading assembly output if the extent of the delay
4172 sequence is made explicit (e.g. with white space).
4174 Note that output routines for instructions with delay slots must
4175 be prepared to deal with not being output as part of a sequence
4176 (i.e. when the scheduling pass is not run, or when no slot
4177 fillers could be found.) The variable `final_sequence' is null
4178 when not processing a sequence, otherwise it contains the
4179 `sequence' rtx being output. */
4181 #define DBR_OUTPUT_SEQEND(STREAM) \
4184 if (set_nomacro > 0 && --set_nomacro == 0) \
4185 fputs ("\t.set\tmacro\n", STREAM); \
4187 if (set_noreorder > 0 && --set_noreorder == 0) \
4188 fputs ("\t.set\treorder\n", STREAM); \
4190 dslots_jump_filled++; \
4191 fputs ("\n", STREAM); \
4196 /* How to tell the debugger about changes of source files. Note, the
4197 mips ECOFF format cannot deal with changes of files inside of
4198 functions, which means the output of parser generators like bison
4199 is generally not debuggable without using the -l switch. Lose,
4200 lose, lose. Silicon graphics seems to want all .file's hardwired
4203 #ifndef SET_FILE_NUMBER
4204 #define SET_FILE_NUMBER() ++num_source_filenames
4207 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4208 mips_output_filename (STREAM, NAME)
4210 /* This is defined so that it can be overridden in iris6.h. */
4211 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4214 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4215 output_quoted_string (STREAM, NAME); \
4216 fputs ("\n", STREAM); \
4220 /* This is how to output a note the debugger telling it the line number
4221 to which the following sequence of instructions corresponds.
4222 Silicon graphics puts a label after each .loc. */
4224 #ifndef LABEL_AFTER_LOC
4225 #define LABEL_AFTER_LOC(STREAM)
4228 #ifndef ASM_OUTPUT_SOURCE_LINE
4229 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4230 mips_output_lineno (STREAM, LINE)
4233 /* The MIPS implementation uses some labels for its own purpose. The
4234 following lists what labels are created, and are all formed by the
4235 pattern $L[a-z].*. The machine independent portion of GCC creates
4236 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4238 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4239 $Lb[0-9]+ Begin blocks for MIPS debug support
4240 $Lc[0-9]+ Label for use in s<xx> operation.
4241 $Le[0-9]+ End blocks for MIPS debug support
4242 $Lp\..+ Half-pic labels. */
4244 /* This is how to output the definition of a user-level label named NAME,
4245 such as the label on a static function or variable NAME.
4247 If we are optimizing the gp, remember that this label has been put
4248 out, so we know not to emit an .extern for it in mips_asm_file_end.
4249 We use one of the common bits in the IDENTIFIER tree node for this,
4250 since those bits seem to be unused, and we don't have any method
4251 of getting the decl nodes from the name. */
4253 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4255 assemble_name (STREAM, NAME); \
4256 fputs (":\n", STREAM); \
4260 /* A C statement (sans semicolon) to output to the stdio stream
4261 STREAM any text necessary for declaring the name NAME of an
4262 initialized variable which is being defined. This macro must
4263 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4264 The argument DECL is the `VAR_DECL' tree node representing the
4267 If this macro is not defined, then the variable name is defined
4268 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4270 #undef ASM_DECLARE_OBJECT_NAME
4271 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4274 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4275 HALF_PIC_DECLARE (NAME); \
4280 /* This is how to output a command to make the user-level label named NAME
4281 defined for reference from other files. */
4283 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4285 fputs ("\t.globl\t", STREAM); \
4286 assemble_name (STREAM, NAME); \
4287 fputs ("\n", STREAM); \
4290 /* This says how to define a global common symbol. */
4292 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4294 /* If the target wants uninitialized const declarations in \
4295 .rdata then don't put them in .comm */ \
4296 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4297 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4298 && (DECL_INITIAL (DECL) == 0 \
4299 || DECL_INITIAL (DECL) == error_mark_node)) \
4301 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4302 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4304 READONLY_DATA_SECTION (); \
4305 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4306 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4310 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4315 /* This says how to define a local common symbol (ie, not visible to
4318 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4319 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4322 /* This says how to output an external. It would be possible not to
4323 output anything and let undefined symbol become external. However
4324 the assembler uses length information on externals to allocate in
4325 data/sdata bss/sbss, thereby saving exec time. */
4327 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4328 mips_output_external(STREAM,DECL,NAME)
4330 /* This says what to print at the end of the assembly file */
4332 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4335 /* Play switch file games if we're optimizing the global pointer. */
4338 #define TEXT_SECTION() \
4340 extern FILE *asm_out_text_file; \
4341 if (TARGET_FILE_SWITCHING) \
4342 asm_out_file = asm_out_text_file; \
4343 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4344 fputc ('\n', asm_out_file); \
4348 /* This is how to declare a function name. The actual work of
4349 emitting the label is moved to function_prologue, so that we can
4350 get the line number correctly emitted before the .ent directive,
4351 and after any .file directives. */
4353 #undef ASM_DECLARE_FUNCTION_NAME
4354 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4355 HALF_PIC_DECLARE (NAME)
4357 /* This is how to output an internal numbered label where
4358 PREFIX is the class of label and NUM is the number within the class. */
4360 #undef ASM_OUTPUT_INTERNAL_LABEL
4361 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4362 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4364 /* This is how to store into the string LABEL
4365 the symbol_ref name of an internal numbered label where
4366 PREFIX is the class of label and NUM is the number within the class.
4367 This is suitable for output with `assemble_name'. */
4369 #undef ASM_GENERATE_INTERNAL_LABEL
4370 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4371 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4373 /* This is how to output an assembler line defining a `double' constant. */
4375 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4376 mips_output_double (STREAM, VALUE)
4379 /* This is how to output an assembler line defining a `float' constant. */
4381 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4382 mips_output_float (STREAM, VALUE)
4385 /* This is how to output an assembler line defining an `int' constant. */
4387 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4389 fprintf (STREAM, "\t.word\t"); \
4390 output_addr_const (STREAM, (VALUE)); \
4391 fprintf (STREAM, "\n"); \
4394 /* Likewise for 64 bit, `char' and `short' constants.
4396 FIXME: operand_subword can't handle some complex constant expressions
4397 that output_addr_const can (for example it does not call
4398 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4399 rely on that to avoid operand_subword for most of the cases where this
4400 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4401 or the same case with the type of 'i' changed to long long.
4405 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4407 if (TARGET_64BIT || TARGET_GAS) \
4409 fprintf (STREAM, "\t.dword\t"); \
4410 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4411 /* We can't use 'X' for negative numbers, because then we won't \
4412 get the right value for the upper 32 bits. */ \
4413 output_addr_const (STREAM, VALUE); \
4415 /* We must use 'X', because otherwise LONG_MIN will print as \
4416 a number that the Irix 6 assembler won't accept. */ \
4417 print_operand (STREAM, VALUE, 'X'); \
4418 fprintf (STREAM, "\n"); \
4422 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4423 UNITS_PER_WORD, BITS_PER_WORD, 1); \
4424 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4425 UNITS_PER_WORD, BITS_PER_WORD, 1); \
4429 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4431 fprintf (STREAM, "\t.half\t"); \
4432 output_addr_const (STREAM, (VALUE)); \
4433 fprintf (STREAM, "\n"); \
4436 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4438 fprintf (STREAM, "\t.byte\t"); \
4439 output_addr_const (STREAM, (VALUE)); \
4440 fprintf (STREAM, "\n"); \
4443 /* This is how to output an assembler line for a numeric constant byte. */
4445 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4446 fprintf (STREAM, "\t.byte\t0x%x\n", (int)(VALUE))
4448 /* This is how to output an element of a case-vector that is absolute. */
4450 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4451 fprintf (STREAM, "\t%s\t%sL%d\n", \
4452 Pmode == DImode ? ".dword" : ".word", \
4453 LOCAL_LABEL_PREFIX, \
4456 /* This is how to output an element of a case-vector that is relative.
4457 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4458 TARGET_EMBEDDED_PIC). */
4460 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4462 if (TARGET_MIPS16) \
4463 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4464 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4465 else if (TARGET_EMBEDDED_PIC) \
4466 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4467 Pmode == DImode ? ".dword" : ".word", \
4468 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4469 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4470 fprintf (STREAM, "\t%s\t%sL%d\n", \
4471 Pmode == DImode ? ".gpdword" : ".gpword", \
4472 LOCAL_LABEL_PREFIX, VALUE); \
4474 fprintf (STREAM, "\t%s\t%sL%d\n", \
4475 Pmode == DImode ? ".dword" : ".word", \
4476 LOCAL_LABEL_PREFIX, VALUE); \
4479 /* When generating embedded PIC or mips16 code we want to put the jump
4480 table in the .text section. In all other cases, we want to put the
4481 jump table in the .rdata section. Unfortunately, we can't use
4482 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4483 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4484 section if appropriate. */
4485 #undef ASM_OUTPUT_CASE_LABEL
4486 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4488 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4489 function_section (current_function_decl); \
4490 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4493 /* This is how to output an assembler line
4494 that says to advance the location counter
4495 to a multiple of 2**LOG bytes. */
4497 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4498 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4500 /* This is how to output an assembler line to advance the location
4501 counter by SIZE bytes. */
4503 #undef ASM_OUTPUT_SKIP
4504 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4505 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4507 /* This is how to output a string. */
4508 #undef ASM_OUTPUT_ASCII
4509 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4510 mips_output_ascii (STREAM, STRING, LEN)
4512 /* Handle certain cpp directives used in header files on sysV. */
4513 #define SCCS_DIRECTIVE
4515 /* Output #ident as a in the read-only data section. */
4516 #undef ASM_OUTPUT_IDENT
4517 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4519 const char *p = STRING; \
4520 int size = strlen (p) + 1; \
4522 assemble_string (p, size); \
4525 /* Default to -G 8 */
4526 #ifndef MIPS_DEFAULT_GVALUE
4527 #define MIPS_DEFAULT_GVALUE 8
4530 /* Define the strings to put out for each section in the object file. */
4531 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4532 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4533 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4534 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4535 #undef READONLY_DATA_SECTION
4536 #define READONLY_DATA_SECTION rdata_section
4537 #define SMALL_DATA_SECTION sdata_section
4539 /* What other sections we support other than the normal .data/.text. */
4541 #undef EXTRA_SECTIONS
4542 #define EXTRA_SECTIONS in_sdata, in_rdata
4544 /* Define the additional functions to select our additional sections. */
4546 /* on the MIPS it is not a good idea to put constants in the text
4547 section, since this defeats the sdata/data mechanism. This is
4548 especially true when -O is used. In this case an effort is made to
4549 address with faster (gp) register relative addressing, which can
4550 only get at sdata and sbss items (there is no stext !!) However,
4551 if the constant is too large for sdata, and it's readonly, it
4552 will go into the .rdata section. */
4554 #undef EXTRA_SECTION_FUNCTIONS
4555 #define EXTRA_SECTION_FUNCTIONS \
4559 if (in_section != in_sdata) \
4561 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4562 in_section = in_sdata; \
4569 if (in_section != in_rdata) \
4571 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4572 in_section = in_rdata; \
4576 /* Given a decl node or constant node, choose the section to output it in
4577 and select that section. */
4579 #undef SELECT_RTX_SECTION
4580 #define SELECT_RTX_SECTION(MODE, RTX, ALIGN) \
4581 mips_select_rtx_section (MODE, RTX)
4583 #undef SELECT_SECTION
4584 #define SELECT_SECTION(DECL, RELOC, ALIGN) \
4585 mips_select_section (DECL, RELOC)
4588 /* Store in OUTPUT a string (made with alloca) containing
4589 an assembler-name for a local static variable named NAME.
4590 LABELNO is an integer which is different for each call. */
4592 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4593 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4594 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4596 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4599 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4600 TARGET_64BIT ? "dsubu" : "subu", \
4601 reg_names[STACK_POINTER_REGNUM], \
4602 reg_names[STACK_POINTER_REGNUM], \
4603 TARGET_64BIT ? "sd" : "sw", \
4605 reg_names[STACK_POINTER_REGNUM]); \
4609 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4612 if (! set_noreorder) \
4613 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4615 dslots_load_total++; \
4616 dslots_load_filled++; \
4617 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4618 TARGET_64BIT ? "ld" : "lw", \
4620 reg_names[STACK_POINTER_REGNUM], \
4621 TARGET_64BIT ? "daddu" : "addu", \
4622 reg_names[STACK_POINTER_REGNUM], \
4623 reg_names[STACK_POINTER_REGNUM]); \
4625 if (! set_noreorder) \
4626 fprintf (STREAM, "\t.set\treorder\n"); \
4630 /* How to start an assembler comment.
4631 The leading space is important (the mips native assembler requires it). */
4632 #ifndef ASM_COMMENT_START
4633 #define ASM_COMMENT_START " #"
4637 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4638 and mips-tdump.c to print them out.
4640 These must match the corresponding definitions in gdb/mipsread.c.
4641 Unfortunately, gcc and gdb do not currently share any directories. */
4643 #define CODE_MASK 0x8F300
4644 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4645 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4646 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4649 /* Default definitions for size_t and ptrdiff_t. */
4652 #define NO_BUILTIN_SIZE_TYPE
4653 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4656 #ifndef PTRDIFF_TYPE
4657 #define NO_BUILTIN_PTRDIFF_TYPE
4658 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4661 /* See mips_expand_prologue's use of loadgp for when this should be
4664 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4665 && mips_abi != ABI_32 \
4666 && mips_abi != ABI_O64)
4668 /* In mips16 mode, we need to look through the function to check for
4669 PC relative loads that are out of range. */
4670 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4672 /* We need to use a special set of functions to handle hard floating
4673 point code in mips16 mode. */
4675 #ifndef INIT_SUBTARGET_OPTABS
4676 #define INIT_SUBTARGET_OPTABS
4679 #define INIT_TARGET_OPTABS \
4682 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4683 INIT_SUBTARGET_OPTABS; \
4686 add_optab->handlers[(int) SFmode].libfunc = \
4687 init_one_libfunc ("__mips16_addsf3"); \
4688 sub_optab->handlers[(int) SFmode].libfunc = \
4689 init_one_libfunc ("__mips16_subsf3"); \
4690 smul_optab->handlers[(int) SFmode].libfunc = \
4691 init_one_libfunc ("__mips16_mulsf3"); \
4692 sdiv_optab->handlers[(int) SFmode].libfunc = \
4693 init_one_libfunc ("__mips16_divsf3"); \
4695 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4696 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4697 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4698 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4699 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4700 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4702 floatsisf_libfunc = \
4703 init_one_libfunc ("__mips16_floatsisf"); \
4705 init_one_libfunc ("__mips16_fixsfsi"); \
4707 if (TARGET_DOUBLE_FLOAT) \
4709 add_optab->handlers[(int) DFmode].libfunc = \
4710 init_one_libfunc ("__mips16_adddf3"); \
4711 sub_optab->handlers[(int) DFmode].libfunc = \
4712 init_one_libfunc ("__mips16_subdf3"); \
4713 smul_optab->handlers[(int) DFmode].libfunc = \
4714 init_one_libfunc ("__mips16_muldf3"); \
4715 sdiv_optab->handlers[(int) DFmode].libfunc = \
4716 init_one_libfunc ("__mips16_divdf3"); \
4718 extendsfdf2_libfunc = \
4719 init_one_libfunc ("__mips16_extendsfdf2"); \
4720 truncdfsf2_libfunc = \
4721 init_one_libfunc ("__mips16_truncdfsf2"); \
4724 init_one_libfunc ("__mips16_eqdf2"); \
4726 init_one_libfunc ("__mips16_nedf2"); \
4728 init_one_libfunc ("__mips16_gtdf2"); \
4730 init_one_libfunc ("__mips16_gedf2"); \
4732 init_one_libfunc ("__mips16_ltdf2"); \
4734 init_one_libfunc ("__mips16_ledf2"); \
4736 floatsidf_libfunc = \
4737 init_one_libfunc ("__mips16_floatsidf"); \
4739 init_one_libfunc ("__mips16_fixdfsi"); \
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