1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 /* MIPS external variables defined in mips.c. */
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
73 /* Costs of various operations on the different architectures. */
75 struct mips_rtx_cost_data
77 unsigned short fp_add;
78 unsigned short fp_mult_sf;
79 unsigned short fp_mult_df;
80 unsigned short fp_div_sf;
81 unsigned short fp_div_df;
82 unsigned short int_mult_si;
83 unsigned short int_mult_di;
84 unsigned short int_div_si;
85 unsigned short int_div_di;
86 unsigned short branch_cost;
87 unsigned short memory_latency;
90 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
91 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
92 to work on a 64-bit machine. */
100 /* Masks that affect tuning.
102 PTF_AVOID_BRANCHLIKELY
103 Set if it is usually not profitable to use branch-likely instructions
104 for this target, typically because the branches are always predicted
105 taken and so incur a large overhead when not taken. */
106 #define PTF_AVOID_BRANCHLIKELY 0x1
108 /* Information about one recognized processor. Defined here for the
109 benefit of TARGET_CPU_CPP_BUILTINS. */
110 struct mips_cpu_info {
111 /* The 'canonical' name of the processor as far as GCC is concerned.
112 It's typically a manufacturer's prefix followed by a numerical
113 designation. It should be lowercase. */
116 /* The internal processor number that most closely matches this
117 entry. Several processors can have the same value, if there's no
118 difference between them from GCC's point of view. */
119 enum processor_type cpu;
121 /* The ISA level that the processor implements. */
124 /* A mask of PTF_* values. */
125 unsigned int tune_flags;
128 /* Enumerates the setting of the -mcode-readable option. */
129 enum mips_code_readable_setting {
135 /* Macros to silence warnings about numbers being signed in traditional
136 C and unsigned in ISO C when compiled on 32-bit hosts. */
138 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
139 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
140 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
143 /* Run-time compilation parameters selecting different hardware subsets. */
145 /* True if we are generating position-independent VxWorks RTP code. */
146 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
148 /* True if the call patterns should be split into a jalr followed by
149 an instruction to restore $gp. It is only safe to split the load
150 from the call when every use of $gp is explicit. */
152 #define TARGET_SPLIT_CALLS \
153 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
155 /* True if we're generating a form of -mabicalls in which we can use
156 operators like %hi and %lo to refer to locally-binding symbols.
157 We can only do this for -mno-shared, and only then if we can use
158 relocation operations instead of assembly macros. It isn't really
159 worth using absolute sequences for 64-bit symbols because GOT
160 accesses are so much shorter. */
162 #define TARGET_ABSOLUTE_ABICALLS \
165 && TARGET_EXPLICIT_RELOCS \
166 && !ABI_HAS_64BIT_SYMBOLS)
168 /* True if we can optimize sibling calls. For simplicity, we only
169 handle cases in which call_insn_operand will reject invalid
170 sibcall addresses. There are two cases in which this isn't true:
172 - TARGET_MIPS16. call_insn_operand accepts constant addresses
173 but there is no direct jump instruction. It isn't worth
174 using sibling calls in this case anyway; they would usually
175 be longer than normal calls.
177 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
178 accepts global constants, but all sibcalls must be indirect. */
179 #define TARGET_SIBCALLS \
180 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
182 /* True if we need to use a global offset table to access some symbols. */
183 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
185 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
186 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
188 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
189 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
191 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
192 This is true for both the PIC and non-PIC VxWorks RTP modes. */
193 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
195 /* True if .gpword or .gpdword should be used for switch tables.
197 Although GAS does understand .gpdword, the SGI linker mishandles
198 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
199 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
200 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
202 /* Generate mips16 code */
203 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
204 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
205 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
206 /* Generate mips16e register save/restore sequences. */
207 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
209 /* True if we're generating a form of MIPS16 code in which general
210 text loads are allowed. */
211 #define TARGET_MIPS16_TEXT_LOADS \
212 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
214 /* True if we're generating a form of MIPS16 code in which PC-relative
215 loads are allowed. */
216 #define TARGET_MIPS16_PCREL_LOADS \
217 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
219 /* Generic ISA defines. */
220 #define ISA_MIPS1 (mips_isa == 1)
221 #define ISA_MIPS2 (mips_isa == 2)
222 #define ISA_MIPS3 (mips_isa == 3)
223 #define ISA_MIPS4 (mips_isa == 4)
224 #define ISA_MIPS32 (mips_isa == 32)
225 #define ISA_MIPS32R2 (mips_isa == 33)
226 #define ISA_MIPS64 (mips_isa == 64)
228 /* Architecture target defines. */
229 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
230 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
231 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
232 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
233 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
234 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
235 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
236 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
237 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
238 || mips_arch == PROCESSOR_SB1A)
239 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
241 /* Scheduling target defines. */
242 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
243 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
244 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
245 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
246 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
247 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
248 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
249 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
250 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
251 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
252 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
253 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
254 || mips_tune == PROCESSOR_SB1A)
255 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
256 || mips_tune == PROCESSOR_24KF2_1 \
257 || mips_tune == PROCESSOR_24KF1_1)
258 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
259 || mips_tune == PROCESSOR_74KF2_1 \
260 || mips_tune == PROCESSOR_74KF1_1 \
261 || mips_tune == PROCESSOR_74KF3_2)
262 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
264 /* True if the pre-reload scheduler should try to create chains of
265 multiply-add or multiply-subtract instructions. For example,
273 t1 will have a higher priority than t2 and t3 will have a higher
274 priority than t4. However, before reload, there is no dependence
275 between t1 and t3, and they can often have similar priorities.
276 The scheduler will then tend to prefer:
283 which stops us from making full use of macc/madd-style instructions.
284 This sort of situation occurs frequently in Fourier transforms and
287 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
288 queue so that chained multiply-add and multiply-subtract instructions
289 appear ahead of any other instruction that is likely to clobber lo.
290 In the example above, if t2 and t3 become ready at the same time,
291 the code ensures that t2 is scheduled first.
293 Multiply-accumulate instructions are a bigger win for some targets
294 than others, so this macro is defined on an opt-in basis. */
295 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
300 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
301 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
303 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
304 directly accessible, while the command-line options select
305 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
307 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
308 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
310 /* IRIX specific stuff. */
311 #define TARGET_IRIX 0
312 #define TARGET_IRIX6 0
314 /* Define preprocessor macros for the -march and -mtune options.
315 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
316 processor. If INFO's canonical name is "foo", define PREFIX to
317 be "foo", and define an additional macro PREFIX_FOO. */
318 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
323 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
324 for (p = macro; *p != 0; p++) \
327 builtin_define (macro); \
328 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
333 /* Target CPU builtins. */
334 #define TARGET_CPU_CPP_BUILTINS() \
337 /* Everyone but IRIX defines this to mips. */ \
339 builtin_assert ("machine=mips"); \
341 builtin_assert ("cpu=mips"); \
342 builtin_define ("__mips__"); \
343 builtin_define ("_mips"); \
345 /* We do this here because __mips is defined below and so we \
346 can't use builtin_define_std. We don't ever want to define \
347 "mips" for VxWorks because some of the VxWorks headers \
348 construct include filenames from a root directory macro, \
349 an architecture macro and a filename, where the architecture \
350 macro expands to 'mips'. If we define 'mips' to 1, the \
351 architecture macro expands to 1 as well. */ \
352 if (!flag_iso && !TARGET_VXWORKS) \
353 builtin_define ("mips"); \
356 builtin_define ("__mips64"); \
360 /* Treat _R3000 and _R4000 like register-size \
361 defines, which is how they've historically \
365 builtin_define_std ("R4000"); \
366 builtin_define ("_R4000"); \
370 builtin_define_std ("R3000"); \
371 builtin_define ("_R3000"); \
374 if (TARGET_FLOAT64) \
375 builtin_define ("__mips_fpr=64"); \
377 builtin_define ("__mips_fpr=32"); \
380 builtin_define ("__mips16"); \
383 builtin_define ("__mips3d"); \
385 if (TARGET_SMARTMIPS) \
386 builtin_define ("__mips_smartmips"); \
390 builtin_define ("__mips_dsp"); \
393 builtin_define ("__mips_dspr2"); \
394 builtin_define ("__mips_dsp_rev=2"); \
397 builtin_define ("__mips_dsp_rev=1"); \
400 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
401 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
405 builtin_define ("__mips=1"); \
406 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
408 else if (ISA_MIPS2) \
410 builtin_define ("__mips=2"); \
411 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
413 else if (ISA_MIPS3) \
415 builtin_define ("__mips=3"); \
416 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
418 else if (ISA_MIPS4) \
420 builtin_define ("__mips=4"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
423 else if (ISA_MIPS32) \
425 builtin_define ("__mips=32"); \
426 builtin_define ("__mips_isa_rev=1"); \
427 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
429 else if (ISA_MIPS32R2) \
431 builtin_define ("__mips=32"); \
432 builtin_define ("__mips_isa_rev=2"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
435 else if (ISA_MIPS64) \
437 builtin_define ("__mips=64"); \
438 builtin_define ("__mips_isa_rev=1"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
445 builtin_define ("_ABIO32=1"); \
446 builtin_define ("_MIPS_SIM=_ABIO32"); \
450 builtin_define ("_ABIN32=2"); \
451 builtin_define ("_MIPS_SIM=_ABIN32"); \
455 builtin_define ("_ABI64=3"); \
456 builtin_define ("_MIPS_SIM=_ABI64"); \
460 builtin_define ("_ABIO64=4"); \
461 builtin_define ("_MIPS_SIM=_ABIO64"); \
465 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
466 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
467 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
468 builtin_define_with_int_value ("_MIPS_FPSET", \
469 32 / MAX_FPRS_PER_FMT); \
471 /* These defines reflect the ABI in use, not whether the \
472 FPU is directly accessible. */ \
473 if (TARGET_HARD_FLOAT_ABI) \
474 builtin_define ("__mips_hard_float"); \
476 builtin_define ("__mips_soft_float"); \
478 if (TARGET_SINGLE_FLOAT) \
479 builtin_define ("__mips_single_float"); \
481 if (TARGET_PAIRED_SINGLE_FLOAT) \
482 builtin_define ("__mips_paired_single_float"); \
484 if (TARGET_BIG_ENDIAN) \
486 builtin_define_std ("MIPSEB"); \
487 builtin_define ("_MIPSEB"); \
491 builtin_define_std ("MIPSEL"); \
492 builtin_define ("_MIPSEL"); \
495 /* Macros dependent on the C dialect. */ \
496 if (preprocessing_asm_p ()) \
498 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
499 builtin_define ("_LANGUAGE_ASSEMBLY"); \
501 else if (c_dialect_cxx ()) \
503 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
504 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
505 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
509 builtin_define_std ("LANGUAGE_C"); \
510 builtin_define ("_LANGUAGE_C"); \
512 if (c_dialect_objc ()) \
514 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
515 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
516 /* Bizarre, but needed at least for Irix. */ \
517 builtin_define_std ("LANGUAGE_C"); \
518 builtin_define ("_LANGUAGE_C"); \
521 if (mips_abi == ABI_EABI) \
522 builtin_define ("__mips_eabi"); \
526 /* Default target_flags if no switches are specified */
528 #ifndef TARGET_DEFAULT
529 #define TARGET_DEFAULT 0
532 #ifndef TARGET_CPU_DEFAULT
533 #define TARGET_CPU_DEFAULT 0
536 #ifndef TARGET_ENDIAN_DEFAULT
537 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
540 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
541 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
544 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
545 #ifndef MIPS_ISA_DEFAULT
546 #ifndef MIPS_CPU_STRING_DEFAULT
547 #define MIPS_CPU_STRING_DEFAULT "from-abi"
553 /* Make this compile time constant for libgcc2 */
555 #define TARGET_64BIT 1
557 #define TARGET_64BIT 0
559 #endif /* IN_LIBGCC2 */
561 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
562 when compiled with hardware floating point. This is because MIPS16
563 code cannot save and restore the floating-point registers, which is
564 important if in a mixed MIPS16/non-MIPS16 environment. */
567 #if __mips_hard_float
568 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
570 #endif /* IN_LIBGCC2 */
572 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
574 #ifndef MULTILIB_ENDIAN_DEFAULT
575 #if TARGET_ENDIAN_DEFAULT == 0
576 #define MULTILIB_ENDIAN_DEFAULT "EL"
578 #define MULTILIB_ENDIAN_DEFAULT "EB"
582 #ifndef MULTILIB_ISA_DEFAULT
583 # if MIPS_ISA_DEFAULT == 1
584 # define MULTILIB_ISA_DEFAULT "mips1"
586 # if MIPS_ISA_DEFAULT == 2
587 # define MULTILIB_ISA_DEFAULT "mips2"
589 # if MIPS_ISA_DEFAULT == 3
590 # define MULTILIB_ISA_DEFAULT "mips3"
592 # if MIPS_ISA_DEFAULT == 4
593 # define MULTILIB_ISA_DEFAULT "mips4"
595 # if MIPS_ISA_DEFAULT == 32
596 # define MULTILIB_ISA_DEFAULT "mips32"
598 # if MIPS_ISA_DEFAULT == 33
599 # define MULTILIB_ISA_DEFAULT "mips32r2"
601 # if MIPS_ISA_DEFAULT == 64
602 # define MULTILIB_ISA_DEFAULT "mips64"
604 # define MULTILIB_ISA_DEFAULT "mips1"
614 #ifndef MULTILIB_DEFAULTS
615 #define MULTILIB_DEFAULTS \
616 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
619 /* We must pass -EL to the linker by default for little endian embedded
620 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
621 linker will default to using big-endian output files. The OUTPUT_FORMAT
622 line must be in the linker script, otherwise -EB/-EL will not work. */
625 #if TARGET_ENDIAN_DEFAULT == 0
626 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
628 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
632 /* A spec condition that matches all non-mips16 -mips arguments. */
634 #define MIPS_ISA_LEVEL_OPTION_SPEC \
635 "mips1|mips2|mips3|mips4|mips32*|mips64*"
637 /* A spec condition that matches all non-mips16 architecture arguments. */
639 #define MIPS_ARCH_OPTION_SPEC \
640 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
642 /* A spec that infers a -mips argument from an -march argument,
643 or injects the default if no architecture is specified. */
645 #define MIPS_ISA_LEVEL_SPEC \
646 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
647 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
648 %{march=mips2|march=r6000:-mips2} \
649 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
650 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
651 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
652 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
653 |march=34k*|march=74k*: -mips32r2} \
654 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
655 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
657 /* A spec that infers a -mhard-float or -msoft-float setting from an
658 -march argument. Note that soft-float and hard-float code are not
661 #define MIPS_ARCH_FLOAT_SPEC \
662 "%{mhard-float|msoft-float|march=mips*:; \
663 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
664 |march=34kc|march=74kc|march=5kc: -msoft-float; \
665 march=*: -mhard-float}"
667 /* A spec condition that matches 32-bit options. It only works if
668 MIPS_ISA_LEVEL_SPEC has been applied. */
670 #define MIPS_32BIT_OPTION_SPEC \
671 "mips1|mips2|mips32*|mgp32"
673 /* Support for a compile-time default CPU, et cetera. The rules are:
674 --with-arch is ignored if -march is specified or a -mips is specified
675 (other than -mips16).
676 --with-tune is ignored if -mtune is specified.
677 --with-abi is ignored if -mabi is specified.
678 --with-float is ignored if -mhard-float or -msoft-float are
680 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
682 #define OPTION_DEFAULT_SPECS \
683 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
684 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
685 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
686 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
687 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
688 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }
691 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
692 && ISA_HAS_COND_TRAP)
694 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
696 /* True if the ABI can only work with 64-bit integer registers. We
697 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
698 otherwise floating-point registers must also be 64-bit. */
699 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
701 /* Likewise for 32-bit regs. */
702 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
704 /* True if symbols are 64 bits wide. At present, n64 is the only
705 ABI for which this is true. */
706 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
708 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
709 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
713 /* ISA has branch likely instructions (e.g. mips2). */
714 /* Disable branchlikely for tx39 until compare rewrite. They haven't
715 been generated up to this point. */
716 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
718 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
719 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
730 /* ISA has the conditional move instructions introduced in mips4. */
731 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
735 && !TARGET_MIPS5500 \
738 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
739 branch on CC, and move (both FP and non-FP) on CC. */
740 #define ISA_HAS_8CC (ISA_MIPS4 \
745 /* This is a catch all for other mips4 instructions: indexed load, the
746 FP madd and msub instructions, and the FP recip and recip sqrt
748 #define ISA_HAS_FP4 ((ISA_MIPS4 \
749 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
753 /* ISA has conditional trap instructions. */
754 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
757 /* ISA has integer multiply-accumulate instructions, madd and msub. */
758 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
763 /* Integer multiply-accumulate instructions should be generated. */
764 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
766 /* ISA has floating-point nmadd and nmsub instructions. */
767 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
769 && (!TARGET_MIPS5400 || TARGET_MAD) \
772 /* ISA has count leading zeroes/ones instruction (not implemented). */
773 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
778 /* ISA has three operand multiply instructions that put
779 the high part in an accumulator: mulhi or mulhiu. */
780 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
785 /* ISA has three operand multiply instructions that
786 negates the result and puts the result in an accumulator. */
787 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
792 /* ISA has three operand multiply instructions that subtracts the
793 result from a 4th operand and puts the result in an accumulator. */
794 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
799 /* ISA has three operand multiply instructions that the result
800 from a 4th operand and puts the result in an accumulator. */
801 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
808 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
809 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
810 || TARGET_MIPS4130) \
813 /* ISA has the "ror" (rotate right) instructions. */
814 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
818 || TARGET_SMARTMIPS) \
821 /* ISA has data prefetch instructions. This controls use of 'pref'. */
822 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
828 /* ISA has data indexed prefetch instructions. This controls use of
829 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
830 (prefx is a cop1x instruction, so can only be used if FP is
832 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
837 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
838 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
839 also requires TARGET_DOUBLE_FLOAT. */
840 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
842 /* ISA includes the MIPS32r2 seb and seh instructions. */
843 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
846 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
847 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
850 /* ISA has instructions for accessing top part of 64-bit fp regs. */
851 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
853 /* ISA has lwxs instruction (load w/scaled index address. */
854 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
856 /* The DSP ASE is available. */
857 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
859 /* Revision 2 of the DSP ASE is available. */
860 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
862 /* True if the result of a load is not available to the next instruction.
863 A nop will then be needed between instructions like "lw $4,..."
864 and "addiu $4,$4,1". */
865 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
866 && !TARGET_MIPS3900 \
869 /* Likewise mtc1 and mfc1. */
870 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
872 /* Likewise floating-point comparisons. */
873 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
875 /* True if mflo and mfhi can be immediately followed by instructions
876 which write to the HI and LO registers.
878 According to MIPS specifications, MIPS ISAs I, II, and III need
879 (at least) two instructions between the reads of HI/LO and
880 instructions which write them, and later ISAs do not. Contradicting
881 the MIPS specifications, some MIPS IV processor user manuals (e.g.
882 the UM for the NEC Vr5000) document needing the instructions between
883 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
884 MIPS64 and later ISAs to have the interlocks, plus any specific
885 earlier-ISA CPUs for which CPU documentation declares that the
886 instructions are really interlocked. */
887 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
892 /* ISA includes synci, jr.hb and jalr.hb. */
893 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
895 /* ISA includes sync. */
896 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
897 #define GENERATE_SYNC \
898 (target_flags_explicit & MASK_LLSC \
899 ? TARGET_LLSC && !TARGET_MIPS16 \
902 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
903 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
905 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
906 #define GENERATE_LL_SC \
907 (target_flags_explicit & MASK_LLSC \
908 ? TARGET_LLSC && !TARGET_MIPS16 \
911 /* Add -G xx support. */
913 #undef SWITCH_TAKES_ARG
914 #define SWITCH_TAKES_ARG(CHAR) \
915 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
917 #define OVERRIDE_OPTIONS override_options ()
919 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
921 /* Show we can debug even without a frame pointer. */
922 #define CAN_DEBUG_WITHOUT_FP
924 /* Tell collect what flags to pass to nm. */
926 #define NM_FLAGS "-Bn"
930 #ifndef MIPS_ABI_DEFAULT
931 #define MIPS_ABI_DEFAULT ABI_32
934 /* Use the most portable ABI flag for the ASM specs. */
936 #if MIPS_ABI_DEFAULT == ABI_32
937 #define MULTILIB_ABI_DEFAULT "mabi=32"
940 #if MIPS_ABI_DEFAULT == ABI_O64
941 #define MULTILIB_ABI_DEFAULT "mabi=o64"
944 #if MIPS_ABI_DEFAULT == ABI_N32
945 #define MULTILIB_ABI_DEFAULT "mabi=n32"
948 #if MIPS_ABI_DEFAULT == ABI_64
949 #define MULTILIB_ABI_DEFAULT "mabi=64"
952 #if MIPS_ABI_DEFAULT == ABI_EABI
953 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
956 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
957 to the assembler. It may be overridden by subtargets. */
958 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
959 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
961 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
964 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
965 the assembler. It may be overridden by subtargets.
967 Beginning with gas 2.13, -mdebug must be passed to correctly handle
968 COFF debugging info. */
970 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
971 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
972 %{g} %{g0} %{g1} %{g2} %{g3} \
973 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
974 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
975 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
976 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
977 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
980 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
981 overridden by subtargets. */
983 #ifndef SUBTARGET_ASM_SPEC
984 #define SUBTARGET_ASM_SPEC ""
989 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
990 %{mips32} %{mips32r2} %{mips64} \
991 %{mips16} %{mno-mips16:-no-mips16} \
992 %{mips3d} %{mno-mips3d:-no-mips3d} \
993 %{mdmx} %{mno-mdmx:-no-mdmx} \
995 %{mdspr2} %{mno-dspr2} \
996 %{msmartmips} %{mno-smartmips} \
998 %{mfix-vr4120} %{mfix-vr4130} \
999 %(subtarget_asm_optimizing_spec) \
1000 %(subtarget_asm_debugging_spec) \
1001 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1002 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1004 %{mshared} %{mno-shared} \
1005 %{msym32} %{mno-sym32} \
1007 %(subtarget_asm_spec)"
1009 /* Extra switches sometimes passed to the linker. */
1010 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1011 will interpret it as a -b option. */
1014 #define LINK_SPEC "\
1016 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1017 %{bestGnum} %{shared} %{non_shared}"
1018 #endif /* LINK_SPEC defined */
1021 /* Specs for the compiler proper */
1023 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1024 overridden by subtargets. */
1025 #ifndef SUBTARGET_CC1_SPEC
1026 #define SUBTARGET_CC1_SPEC ""
1029 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1033 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1034 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1036 %(subtarget_cc1_spec)"
1038 /* Preprocessor specs. */
1040 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1041 overridden by subtargets. */
1042 #ifndef SUBTARGET_CPP_SPEC
1043 #define SUBTARGET_CPP_SPEC ""
1046 #define CPP_SPEC "%(subtarget_cpp_spec)"
1048 /* This macro defines names of additional specifications to put in the specs
1049 that can be used in various specifications like CC1_SPEC. Its definition
1050 is an initializer with a subgrouping for each command option.
1052 Each subgrouping contains a string constant, that defines the
1053 specification name, and a string constant that used by the GCC driver
1056 Do not define this macro if it does not need to do anything. */
1058 #define EXTRA_SPECS \
1059 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1060 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1061 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1062 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1063 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1064 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1065 { "endian_spec", ENDIAN_SPEC }, \
1066 SUBTARGET_EXTRA_SPECS
1068 #ifndef SUBTARGET_EXTRA_SPECS
1069 #define SUBTARGET_EXTRA_SPECS
1072 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1073 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1074 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1076 #ifndef PREFERRED_DEBUGGING_TYPE
1077 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1080 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1082 /* By default, turn on GDB extensions. */
1083 #define DEFAULT_GDB_EXTENSIONS 1
1085 /* Local compiler-generated symbols must have a prefix that the assembler
1086 understands. By default, this is $, although some targets (e.g.,
1087 NetBSD-ELF) need to override this. */
1089 #ifndef LOCAL_LABEL_PREFIX
1090 #define LOCAL_LABEL_PREFIX "$"
1093 /* By default on the mips, external symbols do not have an underscore
1094 prepended, but some targets (e.g., NetBSD) require this. */
1096 #ifndef USER_LABEL_PREFIX
1097 #define USER_LABEL_PREFIX ""
1100 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1101 since the length can run past this up to a continuation point. */
1102 #undef DBX_CONTIN_LENGTH
1103 #define DBX_CONTIN_LENGTH 1500
1105 /* How to renumber registers for dbx and gdb. */
1106 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1108 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1109 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1111 /* The DWARF 2 CFA column which tracks the return address. */
1112 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1114 /* Before the prologue, RA lives in r31. */
1115 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1117 /* Describe how we implement __builtin_eh_return. */
1118 #define EH_RETURN_DATA_REGNO(N) \
1119 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1121 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1123 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1124 The default for this in 64-bit mode is 8, which causes problems with
1125 SFmode register saves. */
1126 #define DWARF_CIE_DATA_ALIGNMENT -4
1128 /* Correct the offset of automatic variables and arguments. Note that
1129 the MIPS debug format wants all automatic variables and arguments
1130 to be in terms of the virtual frame pointer (stack pointer before
1131 any adjustment in the function), while the MIPS 3.0 linker wants
1132 the frame pointer to be the stack pointer after the initial
1135 #define DEBUGGER_AUTO_OFFSET(X) \
1136 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1137 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1138 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1140 /* Target machine storage layout */
1142 #define BITS_BIG_ENDIAN 0
1143 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1144 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1146 /* Define this to set the endianness to use in libgcc2.c, which can
1147 not depend on target_flags. */
1148 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1149 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1151 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1154 #define MAX_BITS_PER_WORD 64
1156 /* Width of a word, in units (bytes). */
1157 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1159 #define MIN_UNITS_PER_WORD 4
1162 /* For MIPS, width of a floating point register. */
1163 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1165 /* The number of consecutive floating-point registers needed to store the
1166 largest format supported by the FPU. */
1167 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1169 /* The number of consecutive floating-point registers needed to store the
1170 smallest format supported by the FPU. */
1171 #define MIN_FPRS_PER_FMT \
1172 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1174 /* The largest size of value that can be held in floating-point
1175 registers and moved with a single instruction. */
1176 #define UNITS_PER_HWFPVALUE \
1177 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1179 /* The largest size of value that can be held in floating-point
1181 #define UNITS_PER_FPVALUE \
1182 (TARGET_SOFT_FLOAT_ABI ? 0 \
1183 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1184 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1186 /* The number of bytes in a double. */
1187 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1189 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1191 /* Set the sizes of the core types. */
1192 #define SHORT_TYPE_SIZE 16
1193 #define INT_TYPE_SIZE 32
1194 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1195 #define LONG_LONG_TYPE_SIZE 64
1197 #define FLOAT_TYPE_SIZE 32
1198 #define DOUBLE_TYPE_SIZE 64
1199 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1201 /* Define the sizes of fixed-point types. */
1202 #define SHORT_FRACT_TYPE_SIZE 8
1203 #define FRACT_TYPE_SIZE 16
1204 #define LONG_FRACT_TYPE_SIZE 32
1205 #define LONG_LONG_FRACT_TYPE_SIZE 64
1207 #define SHORT_ACCUM_TYPE_SIZE 16
1208 #define ACCUM_TYPE_SIZE 32
1209 #define LONG_ACCUM_TYPE_SIZE 64
1210 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1211 doesn't support 128-bit integers for MIPS32 currently. */
1212 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1214 /* long double is not a fixed mode, but the idea is that, if we
1215 support long double, we also want a 128-bit integer type. */
1216 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1219 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1220 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1221 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1223 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1227 /* Width in bits of a pointer. */
1228 #ifndef POINTER_SIZE
1229 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1232 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1233 #define PARM_BOUNDARY BITS_PER_WORD
1235 /* Allocation boundary (in *bits*) for the code of a function. */
1236 #define FUNCTION_BOUNDARY 32
1238 /* Alignment of field after `int : 0' in a structure. */
1239 #define EMPTY_FIELD_BOUNDARY 32
1241 /* Every structure's size must be a multiple of this. */
1242 /* 8 is observed right on a DECstation and on riscos 4.02. */
1243 #define STRUCTURE_SIZE_BOUNDARY 8
1245 /* There is no point aligning anything to a rounder boundary than this. */
1246 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1248 /* All accesses must be aligned. */
1249 #define STRICT_ALIGNMENT 1
1251 /* Define this if you wish to imitate the way many other C compilers
1252 handle alignment of bitfields and the structures that contain
1255 The behavior is that the type written for a bit-field (`int',
1256 `short', or other integer type) imposes an alignment for the
1257 entire structure, as if the structure really did contain an
1258 ordinary field of that type. In addition, the bit-field is placed
1259 within the structure so that it would fit within such a field,
1260 not crossing a boundary for it.
1262 Thus, on most machines, a bit-field whose type is written as `int'
1263 would not cross a four-byte boundary, and would force four-byte
1264 alignment for the whole structure. (The alignment used may not
1265 be four bytes; it is controlled by the other alignment
1268 If the macro is defined, its definition should be a C expression;
1269 a nonzero value for the expression enables this behavior. */
1271 #define PCC_BITFIELD_TYPE_MATTERS 1
1273 /* If defined, a C expression to compute the alignment given to a
1274 constant that is being placed in memory. CONSTANT is the constant
1275 and ALIGN is the alignment that the object would ordinarily have.
1276 The value of this macro is used instead of that alignment to align
1279 If this macro is not defined, then ALIGN is used.
1281 The typical use of this macro is to increase alignment for string
1282 constants to be word aligned so that `strcpy' calls that copy
1283 constants can be done inline. */
1285 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1286 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1287 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1289 /* If defined, a C expression to compute the alignment for a static
1290 variable. TYPE is the data type, and ALIGN is the alignment that
1291 the object would ordinarily have. The value of this macro is used
1292 instead of that alignment to align the object.
1294 If this macro is not defined, then ALIGN is used.
1296 One use of this macro is to increase alignment of medium-size
1297 data to make it all fit in fewer cache lines. Another is to
1298 cause character arrays to be word-aligned so that `strcpy' calls
1299 that copy constants to character arrays can be done inline. */
1301 #undef DATA_ALIGNMENT
1302 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1303 ((((ALIGN) < BITS_PER_WORD) \
1304 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1305 || TREE_CODE (TYPE) == UNION_TYPE \
1306 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1308 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1309 character arrays to be word-aligned so that `strcpy' calls that copy
1310 constants to character arrays can be done inline, and 'strcmp' can be
1311 optimised to use word loads. */
1312 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1313 DATA_ALIGNMENT (TYPE, ALIGN)
1315 #define PAD_VARARGS_DOWN \
1316 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1318 /* Define if operations between registers always perform the operation
1319 on the full register even if a narrower mode is specified. */
1320 #define WORD_REGISTER_OPERATIONS
1322 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1323 moves. All other references are zero extended. */
1324 #define LOAD_EXTEND_OP(MODE) \
1325 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1326 ? SIGN_EXTEND : ZERO_EXTEND)
1328 /* Define this macro if it is advisable to hold scalars in registers
1329 in a wider mode than that declared by the program. In such cases,
1330 the value is constrained to be within the bounds of the declared
1331 type, but kept valid in the wider mode. The signedness of the
1332 extension may differ from that of the type. */
1334 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1335 if (GET_MODE_CLASS (MODE) == MODE_INT \
1336 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1338 if ((MODE) == SImode) \
1343 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1344 Extensions of pointers to word_mode must be signed. */
1345 #define POINTERS_EXTEND_UNSIGNED false
1347 /* Define if loading short immediate values into registers sign extends. */
1348 #define SHORT_IMMEDIATES_SIGN_EXTEND
1350 /* The [d]clz instructions have the natural values at 0. */
1352 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1353 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1355 /* Standard register usage. */
1357 /* Number of hardware registers. We have:
1359 - 32 integer registers
1360 - 32 floating point registers
1361 - 8 condition code registers
1362 - 2 accumulator registers (hi and lo)
1363 - 32 registers each for coprocessors 0, 2 and 3
1365 - ARG_POINTER_REGNUM
1366 - FRAME_POINTER_REGNUM
1367 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1368 - 3 dummy entries that were used at various times in the past.
1369 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1370 - 6 DSP control registers */
1372 #define FIRST_PSEUDO_REGISTER 188
1374 /* By default, fix the kernel registers ($26 and $27), the global
1375 pointer ($28) and the stack pointer ($29). This can change
1376 depending on the command-line options.
1378 Regarding coprocessor registers: without evidence to the contrary,
1379 it's best to assume that each coprocessor register has a unique
1380 use. This can be overridden, in, e.g., override_options() or
1381 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1382 for a particular target. */
1384 #define FIXED_REGISTERS \
1386 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1387 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1388 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1389 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1390 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1391 /* COP0 registers */ \
1392 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1393 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1394 /* COP2 registers */ \
1395 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1396 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1397 /* COP3 registers */ \
1398 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1399 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1400 /* 6 DSP accumulator registers & 6 control registers */ \
1401 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1405 /* Set up this array for o32 by default.
1407 Note that we don't mark $31 as a call-clobbered register. The idea is
1408 that it's really the call instructions themselves which clobber $31.
1409 We don't care what the called function does with it afterwards.
1411 This approach makes it easier to implement sibcalls. Unlike normal
1412 calls, sibcalls don't clobber $31, so the register reaches the
1413 called function in tact. EPILOGUE_USES says that $31 is useful
1414 to the called function. */
1416 #define CALL_USED_REGISTERS \
1418 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1419 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1420 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1421 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1422 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1423 /* COP0 registers */ \
1424 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1425 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1426 /* COP2 registers */ \
1427 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1428 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1429 /* COP3 registers */ \
1430 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1431 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1432 /* 6 DSP accumulator registers & 6 control registers */ \
1433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1437 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1439 #define CALL_REALLY_USED_REGISTERS \
1440 { /* General registers. */ \
1441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1442 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1443 /* Floating-point registers. */ \
1444 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1445 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1447 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1448 /* COP0 registers */ \
1449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1450 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1451 /* COP2 registers */ \
1452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1454 /* COP3 registers */ \
1455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1457 /* 6 DSP accumulator registers & 6 control registers */ \
1458 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1461 /* Internal macros to classify a register number as to whether it's a
1462 general purpose register, a floating point register, a
1463 multiply/divide register, or a status register. */
1465 #define GP_REG_FIRST 0
1466 #define GP_REG_LAST 31
1467 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1468 #define GP_DBX_FIRST 0
1470 #define FP_REG_FIRST 32
1471 #define FP_REG_LAST 63
1472 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1473 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1475 #define MD_REG_FIRST 64
1476 #define MD_REG_LAST 65
1477 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1478 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1480 /* The DWARF 2 CFA column which tracks the return address from a
1481 signal handler context. This means that to maintain backwards
1482 compatibility, no hard register can be assigned this column if it
1483 would need to be handled by the DWARF unwinder. */
1484 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1486 #define ST_REG_FIRST 67
1487 #define ST_REG_LAST 74
1488 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1491 /* FIXME: renumber. */
1492 #define COP0_REG_FIRST 80
1493 #define COP0_REG_LAST 111
1494 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1496 #define COP2_REG_FIRST 112
1497 #define COP2_REG_LAST 143
1498 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1500 #define COP3_REG_FIRST 144
1501 #define COP3_REG_LAST 175
1502 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1503 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1504 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1506 #define DSP_ACC_REG_FIRST 176
1507 #define DSP_ACC_REG_LAST 181
1508 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1510 #define AT_REGNUM (GP_REG_FIRST + 1)
1511 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1512 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1514 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1515 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1516 should be used instead. */
1517 #define FPSW_REGNUM ST_REG_FIRST
1519 #define GP_REG_P(REGNO) \
1520 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1521 #define M16_REG_P(REGNO) \
1522 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1523 #define FP_REG_P(REGNO) \
1524 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1525 #define MD_REG_P(REGNO) \
1526 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1527 #define ST_REG_P(REGNO) \
1528 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1529 #define COP0_REG_P(REGNO) \
1530 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1531 #define COP2_REG_P(REGNO) \
1532 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1533 #define COP3_REG_P(REGNO) \
1534 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1535 #define ALL_COP_REG_P(REGNO) \
1536 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1537 /* Test if REGNO is one of the 6 new DSP accumulators. */
1538 #define DSP_ACC_REG_P(REGNO) \
1539 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1540 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1541 #define ACC_REG_P(REGNO) \
1542 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1544 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1546 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1547 to initialize the mips16 gp pseudo register. */
1548 #define CONST_GP_P(X) \
1549 (GET_CODE (X) == CONST \
1550 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1551 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1553 /* Return coprocessor number from register number. */
1555 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1556 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1557 : COP3_REG_P (REGNO) ? '3' : '?')
1560 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1562 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1563 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1565 /* Value is 1 if it is a good idea to tie two pseudo registers
1566 when one has mode MODE1 and one has mode MODE2.
1567 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1568 for any hard reg, then this must be 0 for correct output. */
1569 #define MODES_TIEABLE_P(MODE1, MODE2) \
1570 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1571 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1572 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1573 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1575 /* Register to use for pushing function arguments. */
1576 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1578 /* These two registers don't really exist: they get eliminated to either
1579 the stack or hard frame pointer. */
1580 #define ARG_POINTER_REGNUM 77
1581 #define FRAME_POINTER_REGNUM 78
1583 /* $30 is not available on the mips16, so we use $17 as the frame
1585 #define HARD_FRAME_POINTER_REGNUM \
1586 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1588 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1590 /* Register in which static-chain is passed to a function. */
1591 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1593 /* Registers used as temporaries in prologue/epilogue code. If we're
1594 generating mips16 code, these registers must come from the core set
1595 of 8. The prologue register mustn't conflict with any incoming
1596 arguments, the static chain pointer, or the frame pointer. The
1597 epilogue temporary mustn't conflict with the return registers, the
1598 frame pointer, the EH stack adjustment, or the EH data registers. */
1600 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1601 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1603 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1604 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1606 /* Define this macro if it is as good or better to call a constant
1607 function address than to call an address kept in a register. */
1608 #define NO_FUNCTION_CSE 1
1610 /* The ABI-defined global pointer. Sometimes we use a different
1611 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1612 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1614 /* We normally use $28 as the global pointer. However, when generating
1615 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1616 register instead. They can then avoid saving and restoring $28
1617 and perhaps avoid using a frame at all.
1619 When a leaf function uses something other than $28, mips_expand_prologue
1620 will modify pic_offset_table_rtx in place. Take the register number
1621 from there after reload. */
1622 #define PIC_OFFSET_TABLE_REGNUM \
1623 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1625 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1627 /* Define the classes of registers for register constraints in the
1628 machine description. Also define ranges of constants.
1630 One of the classes must always be named ALL_REGS and include all hard regs.
1631 If there is more than one class, another class must be named NO_REGS
1632 and contain no registers.
1634 The name GENERAL_REGS must be the name of a class (or an alias for
1635 another name such as ALL_REGS). This is the class of registers
1636 that is allowed by "g" or "r" in a register constraint.
1637 Also, registers outside this class are allocated only when
1638 instructions express preferences for them.
1640 The classes must be numbered in nondecreasing order; that is,
1641 a larger-numbered class must never be contained completely
1642 in a smaller-numbered class.
1644 For any two classes, it is very desirable that there be another
1645 class that represents their union. */
1649 NO_REGS, /* no registers in set */
1650 M16_NA_REGS, /* mips16 regs not used to pass args */
1651 M16_REGS, /* mips16 directly accessible registers */
1652 T_REG, /* mips16 T register ($24) */
1653 M16_T_REGS, /* mips16 registers plus T register */
1654 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1655 V1_REG, /* Register $v1 ($3) used for TLS access. */
1656 LEA_REGS, /* Every GPR except $25 */
1657 GR_REGS, /* integer registers */
1658 FP_REGS, /* floating point registers */
1659 MD0_REG, /* first multiply/divide register */
1660 MD1_REG, /* second multiply/divide register */
1661 MD_REGS, /* multiply/divide registers (hi/lo) */
1662 COP0_REGS, /* generic coprocessor classes */
1665 HI_AND_GR_REGS, /* union classes */
1672 ALL_COP_AND_GR_REGS,
1673 ST_REGS, /* status registers (fp status) */
1674 DSP_ACC_REGS, /* DSP accumulator registers */
1675 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1676 ALL_REGS, /* all registers */
1677 LIM_REG_CLASSES /* max value + 1 */
1680 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1682 #define GENERAL_REGS GR_REGS
1684 /* An initializer containing the names of the register classes as C
1685 string constants. These names are used in writing some of the
1688 #define REG_CLASS_NAMES \
1695 "PIC_FN_ADDR_REG", \
1703 /* coprocessor registers */ \
1710 "COP0_AND_GR_REGS", \
1711 "COP2_AND_GR_REGS", \
1712 "COP3_AND_GR_REGS", \
1714 "ALL_COP_AND_GR_REGS", \
1721 /* An initializer containing the contents of the register classes,
1722 as integers which are bit masks. The Nth integer specifies the
1723 contents of class N. The way the integer MASK is interpreted is
1724 that register R is in the class if `MASK & (1 << R)' is 1.
1726 When the machine has more than 32 registers, an integer does not
1727 suffice. Then the integers are replaced by sub-initializers,
1728 braced groupings containing several integers. Each
1729 sub-initializer must be suitable as an initializer for the type
1730 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1732 #define REG_CLASS_CONTENTS \
1734 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1735 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1736 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1737 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1738 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1739 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1740 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1741 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1742 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1743 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1744 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1745 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1746 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1747 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1748 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1749 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1750 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1751 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1752 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1753 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1754 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1755 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1756 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1757 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1758 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1759 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1760 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1761 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1765 /* A C expression whose value is a register class containing hard
1766 register REGNO. In general there is more that one such class;
1767 choose a class which is "minimal", meaning that no smaller class
1768 also contains the register. */
1770 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1772 /* A macro whose definition is the name of the class to which a
1773 valid base register must belong. A base register is one used in
1774 an address which is the register value plus a displacement. */
1776 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1778 /* A macro whose definition is the name of the class to which a
1779 valid index register must belong. An index register is one used
1780 in an address where its value is either multiplied by a scale
1781 factor or added to another register (as well as added to a
1784 #define INDEX_REG_CLASS NO_REGS
1786 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1787 registers explicitly used in the rtl to be used as spill registers
1788 but prevents the compiler from extending the lifetime of these
1791 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1793 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1794 is the default value (allocate the registers in numeric order). We
1795 define it just so that we can override it for the mips16 target in
1796 ORDER_REGS_FOR_LOCAL_ALLOC. */
1798 #define REG_ALLOC_ORDER \
1799 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1800 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1801 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1802 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1803 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1804 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1805 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1806 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1807 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1808 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1809 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1810 176,177,178,179,180,181,182,183,184,185,186,187 \
1813 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1814 to be rearranged based on a particular function. On the mips16, we
1815 want to allocate $24 (T_REG) before other registers for
1816 instructions for which it is possible. */
1818 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1820 /* True if VALUE is an unsigned 6-bit number. */
1822 #define UIMM6_OPERAND(VALUE) \
1823 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1825 /* True if VALUE is a signed 10-bit number. */
1827 #define IMM10_OPERAND(VALUE) \
1828 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1830 /* True if VALUE is a signed 16-bit number. */
1832 #define SMALL_OPERAND(VALUE) \
1833 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1835 /* True if VALUE is an unsigned 16-bit number. */
1837 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1838 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1840 /* True if VALUE can be loaded into a register using LUI. */
1842 #define LUI_OPERAND(VALUE) \
1843 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1844 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1846 /* Return a value X with the low 16 bits clear, and such that
1847 VALUE - X is a signed 16-bit value. */
1849 #define CONST_HIGH_PART(VALUE) \
1850 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1852 #define CONST_LOW_PART(VALUE) \
1853 ((VALUE) - CONST_HIGH_PART (VALUE))
1855 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1856 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1857 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1859 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1860 mips_preferred_reload_class (X, CLASS)
1862 /* The HI and LO registers can only be reloaded via the general
1863 registers. Condition code registers can only be loaded to the
1864 general registers, and from the floating point registers. */
1866 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1867 mips_secondary_reload_class (CLASS, MODE, X, 1)
1868 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1869 mips_secondary_reload_class (CLASS, MODE, X, 0)
1871 /* Return the maximum number of consecutive registers
1872 needed to represent mode MODE in a register of class CLASS. */
1874 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1876 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1877 mips_cannot_change_mode_class (FROM, TO, CLASS)
1879 /* Stack layout; function entry, exit and calling. */
1881 #define STACK_GROWS_DOWNWARD
1883 /* The offset of the first local variable from the beginning of the frame.
1884 See compute_frame_size for details about the frame layout. */
1886 #define STARTING_FRAME_OFFSET \
1887 (current_function_outgoing_args_size \
1888 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1890 #define RETURN_ADDR_RTX mips_return_addr
1892 /* Since the mips16 ISA mode is encoded in the least-significant bit
1893 of the address, mask it off return addresses for purposes of
1894 finding exception handling regions. */
1896 #define MASK_RETURN_ADDR GEN_INT (-2)
1899 /* Similarly, don't use the least-significant bit to tell pointers to
1900 code from vtable index. */
1902 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1904 /* The eliminations to $17 are only used for mips16 code. See the
1905 definition of HARD_FRAME_POINTER_REGNUM. */
1907 #define ELIMINABLE_REGS \
1908 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1909 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1910 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1911 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1912 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1913 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1915 /* Make sure that we're not trying to eliminate to the wrong hard frame
1917 #define CAN_ELIMINATE(FROM, TO) \
1918 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
1920 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1921 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1923 /* Allocate stack space for arguments at the beginning of each function. */
1924 #define ACCUMULATE_OUTGOING_ARGS 1
1926 /* The argument pointer always points to the first argument. */
1927 #define FIRST_PARM_OFFSET(FNDECL) 0
1929 /* o32 and o64 reserve stack space for all argument registers. */
1930 #define REG_PARM_STACK_SPACE(FNDECL) \
1932 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1935 /* Define this if it is the responsibility of the caller to
1936 allocate the area reserved for arguments passed in registers.
1937 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1938 of this macro is to determine whether the space is included in
1939 `current_function_outgoing_args_size'. */
1940 #define OUTGOING_REG_PARM_STACK_SPACE 1
1942 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1944 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1946 /* Symbolic macros for the registers used to return integer and floating
1949 #define GP_RETURN (GP_REG_FIRST + 2)
1950 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1952 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1954 /* Symbolic macros for the first/last argument registers. */
1956 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1957 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1958 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1959 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1961 #define LIBCALL_VALUE(MODE) \
1962 mips_function_value (NULL_TREE, NULL, (MODE))
1964 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1965 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1967 /* 1 if N is a possible register number for a function value.
1968 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1969 Currently, R2 and F0 are only implemented here (C has no complex type) */
1971 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1972 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1973 && (N) == FP_RETURN + 2))
1975 /* 1 if N is a possible register number for function argument passing.
1976 We have no FP argument registers when soft-float. When FP registers
1977 are 32 bits, we can't directly reference the odd numbered ones. */
1979 #define FUNCTION_ARG_REGNO_P(N) \
1980 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1981 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1984 /* This structure has to cope with two different argument allocation
1985 schemes. Most MIPS ABIs view the arguments as a structure, of which
1986 the first N words go in registers and the rest go on the stack. If I
1987 < N, the Ith word might go in Ith integer argument register or in a
1988 floating-point register. For these ABIs, we only need to remember
1989 the offset of the current argument into the structure.
1991 The EABI instead allocates the integer and floating-point arguments
1992 separately. The first N words of FP arguments go in FP registers,
1993 the rest go on the stack. Likewise, the first N words of the other
1994 arguments go in integer registers, and the rest go on the stack. We
1995 need to maintain three counts: the number of integer registers used,
1996 the number of floating-point registers used, and the number of words
1997 passed on the stack.
1999 We could keep separate information for the two ABIs (a word count for
2000 the standard ABIs, and three separate counts for the EABI). But it
2001 seems simpler to view the standard ABIs as forms of EABI that do not
2002 allocate floating-point registers.
2004 So for the standard ABIs, the first N words are allocated to integer
2005 registers, and function_arg decides on an argument-by-argument basis
2006 whether that argument should really go in an integer register, or in
2007 a floating-point one. */
2009 typedef struct mips_args {
2010 /* Always true for varargs functions. Otherwise true if at least
2011 one argument has been passed in an integer register. */
2014 /* The number of arguments seen so far. */
2015 unsigned int arg_number;
2017 /* The number of integer registers used so far. For all ABIs except
2018 EABI, this is the number of words that have been added to the
2019 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2020 unsigned int num_gprs;
2022 /* For EABI, the number of floating-point registers used so far. */
2023 unsigned int num_fprs;
2025 /* The number of words passed on the stack. */
2026 unsigned int stack_words;
2028 /* On the mips16, we need to keep track of which floating point
2029 arguments were passed in general registers, but would have been
2030 passed in the FP regs if this were a 32-bit function, so that we
2031 can move them to the FP regs if we wind up calling a 32-bit
2032 function. We record this information in fp_code, encoded in base
2033 four. A zero digit means no floating point argument, a one digit
2034 means an SFmode argument, and a two digit means a DFmode argument,
2035 and a three digit is not used. The low order digit is the first
2036 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2037 an SFmode argument. ??? A more sophisticated approach will be
2038 needed if MIPS_ABI != ABI_32. */
2041 /* True if the function has a prototype. */
2045 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2046 for a call to a function whose data type is FNTYPE.
2047 For a library call, FNTYPE is 0. */
2049 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2050 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2052 /* Update the data in CUM to advance over an argument
2053 of mode MODE and data type TYPE.
2054 (TYPE is null for libcalls where that information may not be available.) */
2056 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2057 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2059 /* Determine where to put an argument to a function.
2060 Value is zero to push the argument on the stack,
2061 or a hard register in which to store the argument.
2063 MODE is the argument's machine mode.
2064 TYPE is the data type of the argument (as a tree).
2065 This is null for libcalls where that information may
2067 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2068 the preceding args and about the function being called.
2069 NAMED is nonzero if this argument is a named parameter
2070 (otherwise it is an extra parameter matching an ellipsis). */
2072 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2073 function_arg( &CUM, MODE, TYPE, NAMED)
2075 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2077 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2078 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2080 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2081 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2083 /* True if using EABI and varargs can be passed in floating-point
2084 registers. Under these conditions, we need a more complex form
2085 of va_list, which tracks GPR, FPR and stack arguments separately. */
2086 #define EABI_FLOAT_VARARGS_P \
2087 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2090 /* Say that the epilogue uses the return address register. Note that
2091 in the case of sibcalls, the values "used by the epilogue" are
2092 considered live at the start of the called function. */
2093 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2095 /* Treat LOC as a byte offset from the stack pointer and round it up
2096 to the next fully-aligned offset. */
2097 #define MIPS_STACK_ALIGN(LOC) \
2098 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2101 /* Implement `va_start' for varargs and stdarg. */
2102 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2103 mips_va_start (valist, nextarg)
2105 /* Output assembler code to FILE to increment profiler label # LABELNO
2106 for profiling a function entry. */
2108 #define FUNCTION_PROFILER(FILE, LABELNO) \
2110 if (TARGET_MIPS16) \
2111 sorry ("mips16 function profiling"); \
2112 fprintf (FILE, "\t.set\tnoat\n"); \
2113 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2114 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2115 if (!TARGET_NEWABI) \
2118 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2119 TARGET_64BIT ? "dsubu" : "subu", \
2120 reg_names[STACK_POINTER_REGNUM], \
2121 reg_names[STACK_POINTER_REGNUM], \
2122 Pmode == DImode ? 16 : 8); \
2124 fprintf (FILE, "\tjal\t_mcount\n"); \
2125 fprintf (FILE, "\t.set\tat\n"); \
2128 /* The profiler preserves all interesting registers, including $31. */
2129 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2131 /* No mips port has ever used the profiler counter word, so don't emit it
2132 or the label for it. */
2134 #define NO_PROFILE_COUNTERS 1
2136 /* Define this macro if the code for function profiling should come
2137 before the function prologue. Normally, the profiling code comes
2140 /* #define PROFILE_BEFORE_PROLOGUE */
2142 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2143 the stack pointer does not matter. The value is tested only in
2144 functions that have frame pointers.
2145 No definition is equivalent to always zero. */
2147 #define EXIT_IGNORE_STACK 1
2150 /* A C statement to output, on the stream FILE, assembler code for a
2151 block of data that contains the constant parts of a trampoline.
2152 This code should not include a label--the label is taken care of
2155 #define TRAMPOLINE_TEMPLATE(STREAM) \
2157 if (ptr_mode == DImode) \
2158 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2160 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2161 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2162 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2163 if (ptr_mode == DImode) \
2165 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2166 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2167 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2171 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2172 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2173 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2175 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2176 if (ptr_mode == DImode) \
2178 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2179 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2180 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2184 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2185 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2186 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2190 /* A C expression for the size in bytes of the trampoline, as an
2193 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2195 /* Alignment required for trampolines, in bits. */
2197 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2199 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2200 program and data caches. */
2202 #ifndef CACHE_FLUSH_FUNC
2203 #define CACHE_FLUSH_FUNC "_flush_cache"
2206 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2207 /* Flush both caches. We need to flush the data cache in case \
2208 the system has a write-back cache. */ \
2209 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2210 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2211 GEN_INT (3), TYPE_MODE (integer_type_node))
2213 /* A C statement to initialize the variable parts of a trampoline.
2214 ADDR is an RTX for the address of the trampoline; FNADDR is an
2215 RTX for the address of the nested function; STATIC_CHAIN is an
2216 RTX for the static chain value that should be passed to the
2217 function when it is called. */
2219 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2221 rtx func_addr, chain_addr, end_addr; \
2223 func_addr = plus_constant (ADDR, 32); \
2224 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2225 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2226 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2227 end_addr = gen_reg_rtx (Pmode); \
2228 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2229 GEN_INT (TRAMPOLINE_SIZE))); \
2230 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2233 /* Addressing modes, and classification of registers for them. */
2235 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2236 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2237 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2239 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2240 and check its validity for a certain class.
2241 We have two alternate definitions for each of them.
2242 The usual definition accepts all pseudo regs; the other rejects them all.
2243 The symbol REG_OK_STRICT causes the latter definition to be used.
2245 Most source files want to accept pseudo regs in the hope that
2246 they will get allocated to the class that the insn wants them to be in.
2247 Some source files that are used after register allocation
2248 need to be strict. */
2250 #ifndef REG_OK_STRICT
2251 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2252 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2254 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2255 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2258 #define REG_OK_FOR_INDEX_P(X) 0
2261 /* Maximum number of registers that can appear in a valid memory address. */
2263 #define MAX_REGS_PER_ADDRESS 1
2265 #ifdef REG_OK_STRICT
2266 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2268 if (mips_legitimate_address_p (MODE, X, 1)) \
2272 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2274 if (mips_legitimate_address_p (MODE, X, 0)) \
2279 /* Check for constness inline but use mips_legitimate_address_p
2280 to check whether a constant really is an address. */
2282 #define CONSTANT_ADDRESS_P(X) \
2283 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2285 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2287 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2289 if (mips_legitimize_address (&(X), MODE)) \
2294 /* A C statement or compound statement with a conditional `goto
2295 LABEL;' executed if memory address X (an RTX) can have different
2296 meanings depending on the machine mode of the memory reference it
2299 Autoincrement and autodecrement addresses typically have
2300 mode-dependent effects because the amount of the increment or
2301 decrement is the size of the operand being addressed. Some
2302 machines have other mode-dependent addresses. Many RISC machines
2303 have no mode-dependent addresses.
2305 You may assume that ADDR is a valid address for the machine. */
2307 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2309 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2310 'the start of the function that this code is output in'. */
2312 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2313 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2314 asm_fprintf ((FILE), "%U%s", \
2315 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2317 asm_fprintf ((FILE), "%U%s", (NAME))
2319 /* Flag to mark a function decl symbol that requires a long call. */
2320 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2321 #define SYMBOL_REF_LONG_CALL_P(X) \
2322 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2324 /* True if we're generating a form of MIPS16 code in which jump tables
2325 are stored in the text section and encoded as 16-bit PC-relative
2326 offsets. This is only possible when general text loads are allowed,
2327 since the table access itself will be an "lh" instruction. */
2328 /* ??? 16-bit offsets can overflow in large functions. */
2329 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2331 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2333 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2335 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2337 /* Define this as 1 if `char' should by default be signed; else as 0. */
2338 #ifndef DEFAULT_SIGNED_CHAR
2339 #define DEFAULT_SIGNED_CHAR 1
2342 /* Max number of bytes we can move from memory to memory
2343 in one reasonably fast instruction. */
2344 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2345 #define MAX_MOVE_MAX 8
2347 /* Define this macro as a C expression which is nonzero if
2348 accessing less than a word of memory (i.e. a `char' or a
2349 `short') is no faster than accessing a word of memory, i.e., if
2350 such access require more than one instruction or if there is no
2351 difference in cost between byte and (aligned) word loads.
2353 On RISC machines, it tends to generate better code to define
2354 this as 1, since it avoids making a QI or HI mode register.
2356 But, generating word accesses for -mips16 is generally bad as shifts
2357 (often extended) would be needed for byte accesses. */
2358 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2360 /* Define this to be nonzero if shift instructions ignore all but the low-order
2362 #define SHIFT_COUNT_TRUNCATED 1
2364 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2365 is done just by pretending it is already truncated. */
2366 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2367 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2370 /* Specify the machine mode that pointers have.
2371 After generation of rtl, the compiler makes no further distinction
2372 between pointers and any other objects of this machine mode. */
2375 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2378 /* Give call MEMs SImode since it is the "most permissive" mode
2379 for both 32-bit and 64-bit targets. */
2381 #define FUNCTION_MODE SImode
2384 /* A C expression for the cost of moving data from a register in
2385 class FROM to one in class TO. The classes are expressed using
2386 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2387 the default; other values are interpreted relative to that.
2389 It is not required that the cost always equal 2 when FROM is the
2390 same as TO; on some machines it is expensive to move between
2391 registers if they are not general registers.
2393 If reload sees an insn consisting of a single `set' between two
2394 hard registers, and if `REGISTER_MOVE_COST' applied to their
2395 classes returns a value of 2, reload does not check to ensure
2396 that the constraints of the insn are met. Setting a cost of
2397 other than 2 will allow reload to verify that the constraints are
2398 met. You should do this if the `movM' pattern's constraints do
2399 not allow such copying. */
2401 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2402 mips_register_move_cost (MODE, FROM, TO)
2404 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2405 (mips_cost->memory_latency \
2406 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2408 /* Define if copies to/from condition code registers should be avoided.
2410 This is needed for the MIPS because reload_outcc is not complete;
2411 it needs to handle cases where the source is a general or another
2412 condition code register. */
2413 #define AVOID_CCMODE_COPIES
2415 /* A C expression for the cost of a branch instruction. A value of
2416 1 is the default; other values are interpreted relative to that. */
2418 #define BRANCH_COST mips_branch_cost
2419 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2421 /* If defined, modifies the length assigned to instruction INSN as a
2422 function of the context in which it is used. LENGTH is an lvalue
2423 that contains the initially computed length of the insn and should
2424 be updated with the correct length of the insn. */
2425 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2426 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2428 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2429 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2431 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2432 "%*" OPCODE "%?\t" OPERANDS "%/"
2434 /* Return the asm template for a call. INSN is the instruction's mnemonic
2435 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2438 When generating GOT code without explicit relocation operators,
2439 all calls should use assembly macros. Otherwise, all indirect
2440 calls should use "jr" or "jalr"; we will arrange to restore $gp
2441 afterwards if necessary. Finally, we can only generate direct
2442 calls for -mabicalls by temporarily switching to non-PIC mode. */
2443 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2444 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2445 ? "%*" INSN "\t%" #OPNO "%/" \
2446 : REG_P (OPERANDS[OPNO]) \
2447 ? "%*" INSN "r\t%" #OPNO "%/" \
2449 ? (".option\tpic0\n\t" \
2450 "%*" INSN "\t%" #OPNO "%/\n\t" \
2452 : "%*" INSN "\t%" #OPNO "%/")
2454 /* Control the assembler format that we output. */
2456 /* Output to assembler file text saying following lines
2457 may contain character constants, extra white space, comments, etc. */
2460 #define ASM_APP_ON " #APP\n"
2463 /* Output to assembler file text saying following lines
2464 no longer contain unusual constructs. */
2467 #define ASM_APP_OFF " #NO_APP\n"
2470 #define REGISTER_NAMES \
2471 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2472 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2473 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2474 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2475 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2476 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2477 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2478 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2479 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2480 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2481 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2482 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2483 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2484 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2485 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2486 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2487 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2488 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2489 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2490 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2491 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2492 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2493 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2494 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2496 /* List the "software" names for each register. Also list the numerical
2497 names for $fp and $sp. */
2499 #define ADDITIONAL_REGISTER_NAMES \
2501 { "$29", 29 + GP_REG_FIRST }, \
2502 { "$30", 30 + GP_REG_FIRST }, \
2503 { "at", 1 + GP_REG_FIRST }, \
2504 { "v0", 2 + GP_REG_FIRST }, \
2505 { "v1", 3 + GP_REG_FIRST }, \
2506 { "a0", 4 + GP_REG_FIRST }, \
2507 { "a1", 5 + GP_REG_FIRST }, \
2508 { "a2", 6 + GP_REG_FIRST }, \
2509 { "a3", 7 + GP_REG_FIRST }, \
2510 { "t0", 8 + GP_REG_FIRST }, \
2511 { "t1", 9 + GP_REG_FIRST }, \
2512 { "t2", 10 + GP_REG_FIRST }, \
2513 { "t3", 11 + GP_REG_FIRST }, \
2514 { "t4", 12 + GP_REG_FIRST }, \
2515 { "t5", 13 + GP_REG_FIRST }, \
2516 { "t6", 14 + GP_REG_FIRST }, \
2517 { "t7", 15 + GP_REG_FIRST }, \
2518 { "s0", 16 + GP_REG_FIRST }, \
2519 { "s1", 17 + GP_REG_FIRST }, \
2520 { "s2", 18 + GP_REG_FIRST }, \
2521 { "s3", 19 + GP_REG_FIRST }, \
2522 { "s4", 20 + GP_REG_FIRST }, \
2523 { "s5", 21 + GP_REG_FIRST }, \
2524 { "s6", 22 + GP_REG_FIRST }, \
2525 { "s7", 23 + GP_REG_FIRST }, \
2526 { "t8", 24 + GP_REG_FIRST }, \
2527 { "t9", 25 + GP_REG_FIRST }, \
2528 { "k0", 26 + GP_REG_FIRST }, \
2529 { "k1", 27 + GP_REG_FIRST }, \
2530 { "gp", 28 + GP_REG_FIRST }, \
2531 { "sp", 29 + GP_REG_FIRST }, \
2532 { "fp", 30 + GP_REG_FIRST }, \
2533 { "ra", 31 + GP_REG_FIRST }, \
2534 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2537 /* This is meant to be redefined in the host dependent files. It is a
2538 set of alternative names and regnums for mips coprocessors. */
2540 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2542 /* A C compound statement to output to stdio stream STREAM the
2543 assembler syntax for an instruction operand X. X is an RTL
2546 CODE is a value that can be used to specify one of several ways
2547 of printing the operand. It is used when identical operands
2548 must be printed differently depending on the context. CODE
2549 comes from the `%' specification that was used to request
2550 printing of the operand. If the specification was just `%DIGIT'
2551 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2552 is the ASCII code for LTR.
2554 If X is a register, this macro should print the register's name.
2555 The names can be found in an array `reg_names' whose type is
2556 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2558 When the machine description has a specification `%PUNCT' (a `%'
2559 followed by a punctuation character), this macro is called with
2560 a null pointer for X and the punctuation character for CODE.
2562 See mips.c for the MIPS specific codes. */
2564 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2566 /* A C expression which evaluates to true if CODE is a valid
2567 punctuation character for use in the `PRINT_OPERAND' macro. If
2568 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2569 punctuation characters (except for the standard one, `%') are
2570 used in this way. */
2572 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2574 /* A C compound statement to output to stdio stream STREAM the
2575 assembler syntax for an instruction operand that is a memory
2576 reference whose address is ADDR. ADDR is an RTL expression. */
2578 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2581 /* A C statement, to be executed after all slot-filler instructions
2582 have been output. If necessary, call `dbr_sequence_length' to
2583 determine the number of slots filled in a sequence (zero if not
2584 currently outputting a sequence), to decide how many no-ops to
2585 output, or whatever.
2587 Don't define this macro if it has nothing to do, but it is
2588 helpful in reading assembly output if the extent of the delay
2589 sequence is made explicit (e.g. with white space).
2591 Note that output routines for instructions with delay slots must
2592 be prepared to deal with not being output as part of a sequence
2593 (i.e. when the scheduling pass is not run, or when no slot
2594 fillers could be found.) The variable `final_sequence' is null
2595 when not processing a sequence, otherwise it contains the
2596 `sequence' rtx being output. */
2598 #define DBR_OUTPUT_SEQEND(STREAM) \
2601 if (set_nomacro > 0 && --set_nomacro == 0) \
2602 fputs ("\t.set\tmacro\n", STREAM); \
2604 if (set_noreorder > 0 && --set_noreorder == 0) \
2605 fputs ("\t.set\treorder\n", STREAM); \
2607 fputs ("\n", STREAM); \
2612 /* How to tell the debugger about changes of source files. */
2613 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2614 mips_output_filename (STREAM, NAME)
2616 /* mips-tfile does not understand .stabd directives. */
2617 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2618 dbxout_begin_stabn_sline (LINE); \
2619 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2622 /* Use .loc directives for SDB line numbers. */
2623 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2624 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2626 /* The MIPS implementation uses some labels for its own purpose. The
2627 following lists what labels are created, and are all formed by the
2628 pattern $L[a-z].*. The machine independent portion of GCC creates
2629 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2631 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2632 $Lb[0-9]+ Begin blocks for MIPS debug support
2633 $Lc[0-9]+ Label for use in s<xx> operation.
2634 $Le[0-9]+ End blocks for MIPS debug support */
2636 #undef ASM_DECLARE_OBJECT_NAME
2637 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2638 mips_declare_object (STREAM, NAME, "", ":\n")
2640 /* Globalizing directive for a label. */
2641 #define GLOBAL_ASM_OP "\t.globl\t"
2643 /* This says how to define a global common symbol. */
2645 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2647 /* This says how to define a local common symbol (i.e., not visible to
2650 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2651 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2652 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2655 /* This says how to output an external. It would be possible not to
2656 output anything and let undefined symbol become external. However
2657 the assembler uses length information on externals to allocate in
2658 data/sdata bss/sbss, thereby saving exec time. */
2660 #undef ASM_OUTPUT_EXTERNAL
2661 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2662 mips_output_external(STREAM,DECL,NAME)
2664 /* This is how to declare a function name. The actual work of
2665 emitting the label is moved to function_prologue, so that we can
2666 get the line number correctly emitted before the .ent directive,
2667 and after any .file directives. Define as empty so that the function
2668 is not declared before the .ent directive elsewhere. */
2670 #undef ASM_DECLARE_FUNCTION_NAME
2671 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2673 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2674 #define FUNCTION_NAME_ALREADY_DECLARED 0
2677 /* This is how to store into the string LABEL
2678 the symbol_ref name of an internal numbered label where
2679 PREFIX is the class of label and NUM is the number within the class.
2680 This is suitable for output with `assemble_name'. */
2682 #undef ASM_GENERATE_INTERNAL_LABEL
2683 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2684 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2686 /* This is how to output an element of a case-vector that is absolute. */
2688 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2689 fprintf (STREAM, "\t%s\t%sL%d\n", \
2690 ptr_mode == DImode ? ".dword" : ".word", \
2691 LOCAL_LABEL_PREFIX, \
2694 /* This is how to output an element of a case-vector. We can make the
2695 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2698 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2700 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2701 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2702 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2703 else if (TARGET_GPWORD) \
2704 fprintf (STREAM, "\t%s\t%sL%d\n", \
2705 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2706 LOCAL_LABEL_PREFIX, VALUE); \
2707 else if (TARGET_RTP_PIC) \
2709 /* Make the entry relative to the start of the function. */ \
2710 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2711 fprintf (STREAM, "\t%s\t%sL%d-", \
2712 Pmode == DImode ? ".dword" : ".word", \
2713 LOCAL_LABEL_PREFIX, VALUE); \
2714 assemble_name (STREAM, XSTR (fnsym, 0)); \
2715 fprintf (STREAM, "\n"); \
2718 fprintf (STREAM, "\t%s\t%sL%d\n", \
2719 ptr_mode == DImode ? ".dword" : ".word", \
2720 LOCAL_LABEL_PREFIX, VALUE); \
2723 /* This is how to output an assembler line
2724 that says to advance the location counter
2725 to a multiple of 2**LOG bytes. */
2727 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2728 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2730 /* This is how to output an assembler line to advance the location
2731 counter by SIZE bytes. */
2733 #undef ASM_OUTPUT_SKIP
2734 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2735 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2737 /* This is how to output a string. */
2738 #undef ASM_OUTPUT_ASCII
2739 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2740 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2742 /* Output #ident as a in the read-only data section. */
2743 #undef ASM_OUTPUT_IDENT
2744 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2746 const char *p = STRING; \
2747 int size = strlen (p) + 1; \
2748 switch_to_section (readonly_data_section); \
2749 assemble_string (p, size); \
2752 /* Default to -G 8 */
2753 #ifndef MIPS_DEFAULT_GVALUE
2754 #define MIPS_DEFAULT_GVALUE 8
2757 /* Define the strings to put out for each section in the object file. */
2758 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2759 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2761 #undef READONLY_DATA_SECTION_ASM_OP
2762 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2764 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2767 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2768 TARGET_64BIT ? "daddiu" : "addiu", \
2769 reg_names[STACK_POINTER_REGNUM], \
2770 reg_names[STACK_POINTER_REGNUM], \
2771 TARGET_64BIT ? "sd" : "sw", \
2773 reg_names[STACK_POINTER_REGNUM]); \
2777 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2780 if (! set_noreorder) \
2781 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2783 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2784 TARGET_64BIT ? "ld" : "lw", \
2786 reg_names[STACK_POINTER_REGNUM], \
2787 TARGET_64BIT ? "daddu" : "addu", \
2788 reg_names[STACK_POINTER_REGNUM], \
2789 reg_names[STACK_POINTER_REGNUM]); \
2791 if (! set_noreorder) \
2792 fprintf (STREAM, "\t.set\treorder\n"); \
2796 /* How to start an assembler comment.
2797 The leading space is important (the mips native assembler requires it). */
2798 #ifndef ASM_COMMENT_START
2799 #define ASM_COMMENT_START " #"
2802 /* Default definitions for size_t and ptrdiff_t. We must override the
2803 definitions from ../svr4.h on mips-*-linux-gnu. */
2806 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2809 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2811 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2812 values were determined experimentally by benchmarking with CSiBE.
2813 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2814 for o32 where we have to restore $gp afterwards as well as make an
2815 indirect call), but in practice, bumping this up higher for
2816 TARGET_ABICALLS doesn't make much difference to code size. */
2818 #define MIPS_CALL_RATIO 8
2820 /* Define MOVE_RATIO to encourage use of movmemsi when enabled,
2821 since it should always generate code at least as good as
2822 move_by_pieces(). But when inline movmemsi pattern is disabled
2823 (i.e., with -mips16 or -mmemcpy), instead use a value approximating
2824 the length of a memcpy call sequence, so that move_by_pieces will
2825 generate inline code if it is shorter than a function call.
2826 Since move_by_pieces_ninsns() counts memory-to-memory moves, but
2827 we'll have to generate a load/store pair for each, halve the value of
2828 MIPS_CALL_RATIO to take that into account.
2829 The default value for MOVE_RATIO when HAVE_movmemsi is true is 2.
2830 There is no point to setting it to less than this to try to disable
2831 move_by_pieces entirely, because that also disables some desirable
2832 tree-level optimizations, specifically related to optimizing a
2833 one-byte string copy into a simple move byte operation. */
2835 #define MOVE_RATIO \
2836 ((TARGET_MIPS16 || TARGET_MEMCPY) ? MIPS_CALL_RATIO / 2 : 2)
2838 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2839 of the length of a memset call, but use the default otherwise. */
2841 #define CLEAR_RATIO \
2842 (optimize_size ? MIPS_CALL_RATIO : 15)
2844 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2845 optimizing for size adjust the ratio to account for the overhead of
2846 loading the constant and replicating it across the word. */
2849 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2851 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2852 in that case each word takes 3 insns (lui, ori, sw), or more in
2853 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2854 and let the move_by_pieces code copy the string from read-only
2855 memory. In the future, this could be tuned further for multi-issue
2856 CPUs that can issue stores down one pipe and arithmetic instructions
2857 down another; in that case, the lui/ori/sw combination would be a
2858 win for long enough strings. */
2860 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2863 /* Since the bits of the _init and _fini function is spread across
2864 many object files, each potentially with its own GP, we must assume
2865 we need to load our GP. We don't preserve $gp or $ra, since each
2866 init/fini chunk is supposed to initialize $gp, and crti/crtn
2867 already take care of preserving $ra and, when appropriate, $gp. */
2868 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2869 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2870 asm (SECTION_OP "\n\
2876 jal " USER_LABEL_PREFIX #FUNC "\n\
2877 " TEXT_SECTION_ASM_OP);
2878 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2879 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2880 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2881 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2882 asm (SECTION_OP "\n\
2887 .cpsetup $31, $2, 1b\n\
2888 jal " USER_LABEL_PREFIX #FUNC "\n\
2889 " TEXT_SECTION_ASM_OP);
2894 #define HAVE_AS_TLS 0
2897 /* Return an asm string that atomically:
2899 - Compares memory reference %1 to register %2 and, if they are
2900 equal, changes %1 to %3.
2902 - Sets register %0 to the old value of memory reference %1.
2904 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
2905 and OP is the instruction that should be used to load %3 into a
2907 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
2909 "1:\tll" SUFFIX "\t%0,%1\n" \
2910 "\tbne\t%0,%z2,2f\n" \
2911 "\t" OP "\t%@,%3\n" \
2912 "\tsc" SUFFIX "\t%@,%1\n" \
2913 "\tbeq\t%@,%.,1b\n" \
2917 /* Return an asm string that atomically:
2919 - Sets memory reference %0 to %0 INSN %1.
2921 SUFFIX is the suffix that should be added to "ll" and "sc"
2923 #define MIPS_SYNC_OP(SUFFIX, INSN) \
2925 "1:\tll" SUFFIX "\t%@,%0\n" \
2926 "\t" INSN "\t%@,%@,%1\n" \
2927 "\tsc" SUFFIX "\t%@,%0\n" \
2928 "\tbeq\t%@,%.,1b\n" \
2932 /* Return an asm string that atomically:
2934 - Sets memory reference %1 to %1 INSN %2.
2936 - Sets register %0 to the old value of memory reference %1.
2938 SUFFIX is the suffix that should be added to "ll" and "sc"
2940 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
2942 "1:\tll" SUFFIX "\t%0,%1\n" \
2943 "\t" INSN "\t%@,%0,%2\n" \
2944 "\tsc" SUFFIX "\t%@,%1\n" \
2945 "\tbeq\t%@,%.,1b\n" \
2949 /* Return an asm string that atomically:
2951 - Sets memory reference %1 to %1 INSN %2.
2953 - Sets register %0 to the new value of memory reference %1.
2955 SUFFIX is the suffix that should be added to "ll" and "sc"
2957 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
2959 "1:\tll" SUFFIX "\t%0,%1\n" \
2960 "\t" INSN "\t%@,%0,%2\n" \
2961 "\tsc" SUFFIX "\t%@,%1\n" \
2962 "\tbeq\t%@,%.,1b\n" \
2963 "\t" INSN "\t%0,%0,%2\n" \
2966 /* Return an asm string that atomically:
2968 - Sets memory reference %0 to ~%0 AND %1.
2970 SUFFIX is the suffix that should be added to "ll" and "sc"
2971 instructions. INSN is the and instruction needed to and a register
2973 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
2975 "1:\tll" SUFFIX "\t%@,%0\n" \
2976 "\tnor\t%@,%@,%.\n" \
2977 "\t" INSN "\t%@,%@,%1\n" \
2978 "\tsc" SUFFIX "\t%@,%0\n" \
2979 "\tbeq\t%@,%.,1b\n" \
2983 /* Return an asm string that atomically:
2985 - Sets memory reference %1 to ~%1 AND %2.
2987 - Sets register %0 to the old value of memory reference %1.
2989 SUFFIX is the suffix that should be added to "ll" and "sc"
2990 instructions. INSN is the and instruction needed to and a register
2992 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
2994 "1:\tll" SUFFIX "\t%0,%1\n" \
2995 "\tnor\t%@,%0,%.\n" \
2996 "\t" INSN "\t%@,%@,%2\n" \
2997 "\tsc" SUFFIX "\t%@,%1\n" \
2998 "\tbeq\t%@,%.,1b\n" \
3002 /* Return an asm string that atomically:
3004 - Sets memory reference %1 to ~%1 AND %2.
3006 - Sets register %0 to the new value of memory reference %1.
3008 SUFFIX is the suffix that should be added to "ll" and "sc"
3009 instructions. INSN is the and instruction needed to and a register
3011 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3013 "1:\tll" SUFFIX "\t%0,%1\n" \
3014 "\tnor\t%0,%0,%.\n" \
3015 "\t" INSN "\t%@,%0,%2\n" \
3016 "\tsc" SUFFIX "\t%@,%1\n" \
3017 "\tbeq\t%@,%.,1b\n" \
3018 "\t" INSN "\t%0,%0,%2\n" \
3021 /* Return an asm string that atomically:
3023 - Sets memory reference %1 to %2.
3025 - Sets register %0 to the old value of memory reference %1.
3027 SUFFIX is the suffix that should be added to "ll" and "sc"
3028 instructions. OP is the and instruction that should be used to
3029 load %2 into a register. */
3030 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3032 "1:\tll" SUFFIX "\t%0,%1\n" \
3033 "\t" OP "\t%@,%2\n" \
3034 "\tsc" SUFFIX "\t%@,%1\n" \
3035 "\tbeq\t%@,%.,1b\n" \
3039 #ifndef USED_FOR_TARGET
3040 extern const enum reg_class mips_regno_to_class[];
3041 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3042 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
3043 extern const char *current_function_file; /* filename current function is in */
3044 extern int num_source_filenames; /* current .file # */
3045 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
3046 extern int sym_lineno; /* sgi next label # for each stmt */
3047 extern int set_noreorder; /* # of nested .set noreorder's */
3048 extern int set_nomacro; /* # of nested .set nomacro's */
3049 extern int set_noat; /* # of nested .set noat's */
3050 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
3051 extern int mips_dbx_regno[];
3052 extern int mips_dwarf_regno[];
3053 extern bool mips_split_p[];
3054 extern GTY(()) rtx cmp_operands[2];
3055 extern enum processor_type mips_arch; /* which cpu to codegen for */
3056 extern enum processor_type mips_tune; /* which cpu to schedule for */
3057 extern int mips_isa; /* architectural level */
3058 extern int mips_abi; /* which ABI to use */
3059 extern const struct mips_cpu_info mips_cpu_info_table[];
3060 extern const struct mips_cpu_info *mips_arch_info;
3061 extern const struct mips_cpu_info *mips_tune_info;
3062 extern const struct mips_rtx_cost_data *mips_cost;
3063 extern enum mips_code_readable_setting mips_code_readable;
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