1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
82 /* Recast the cpu class to be the cpu attribute. */
83 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
85 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
86 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
87 to work on a 64 bit machine. */
94 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
95 which is not the same as the above EABI (defined by Cygnus,
96 Greenhills, and Toshiba?). MEABI is not yet complete or published,
97 but at this point it looks like N32 as far as calling conventions go,
98 but allows for either 32 or 64 bit registers.
100 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
101 EABI the legacy EABI. In the end we may end up calling both ABI's
102 EABI but give them different version numbers, but for now I'm going
103 with different names. */
106 /* Whether to emit abicalls code sequences or not. */
108 enum mips_abicalls_type {
113 /* Recast the abicalls class to be the abicalls attribute. */
114 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
116 /* Which type of block move to do (whether or not the last store is
117 split out so it can fill a branch delay slot). */
119 enum block_move_type {
120 BLOCK_MOVE_NORMAL, /* generate complete block move */
121 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
122 BLOCK_MOVE_LAST /* generate just the last store */
125 /* Information about one recognized processor. Defined here for the
126 benefit of TARGET_CPU_CPP_BUILTINS. */
127 struct mips_cpu_info {
128 /* The 'canonical' name of the processor as far as GCC is concerned.
129 It's typically a manufacturer's prefix followed by a numerical
130 designation. It should be lower case. */
133 /* The internal processor number that most closely matches this
134 entry. Several processors can have the same value, if there's no
135 difference between them from GCC's point of view. */
136 enum processor_type cpu;
138 /* The ISA level that the processor implements. */
142 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
143 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
144 extern const char *current_function_file; /* filename current function is in */
145 extern int num_source_filenames; /* current .file # */
146 extern int inside_function; /* != 0 if inside of a function */
147 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
148 extern int file_in_function_warning; /* warning given about .file in func */
149 extern int sdb_label_count; /* block start/end next label # */
150 extern int sdb_begin_function_line; /* Starting Line of current function */
151 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
152 extern int g_switch_value; /* value of the -G xx switch */
153 extern int g_switch_set; /* whether -G xx was passed. */
154 extern int sym_lineno; /* sgi next label # for each stmt */
155 extern int set_noreorder; /* # of nested .set noreorder's */
156 extern int set_nomacro; /* # of nested .set nomacro's */
157 extern int set_noat; /* # of nested .set noat's */
158 extern int set_volatile; /* # of nested .set volatile's */
159 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
160 extern int mips_dbx_regno[]; /* Map register # to debug register # */
161 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
162 extern enum cmp_type branch_type; /* what type of branch to use */
163 extern enum processor_type mips_arch; /* which cpu to codegen for */
164 extern enum processor_type mips_tune; /* which cpu to schedule for */
165 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
166 extern int mips_isa; /* architectural level */
167 extern int mips16; /* whether generating mips16 code */
168 extern int mips16_hard_float; /* mips16 without -msoft-float */
169 extern int mips_entry; /* generate entry/exit for mips16 */
170 extern const char *mips_arch_string; /* for -march=<xxx> */
171 extern const char *mips_tune_string; /* for -mtune=<xxx> */
172 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
173 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
174 extern const char *mips_entry_string; /* for -mentry */
175 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
176 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
177 extern int mips_split_addresses; /* perform high/lo_sum support */
178 extern int dslots_load_total; /* total # load related delay slots */
179 extern int dslots_load_filled; /* # filled load delay slots */
180 extern int dslots_jump_total; /* total # jump related delay slots */
181 extern int dslots_jump_filled; /* # filled jump delay slots */
182 extern int dslots_number_nops; /* # of nops needed by previous insn */
183 extern int num_refs[3]; /* # 1/2/3 word references */
184 extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
185 extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
186 extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
187 extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
188 extern int mips_string_length; /* length of strings for mips16 */
189 extern const struct mips_cpu_info mips_cpu_info_table[];
190 extern const struct mips_cpu_info *mips_arch_info;
191 extern const struct mips_cpu_info *mips_tune_info;
193 /* Functions to change what output section we are using. */
194 extern void sdata_section PARAMS ((void));
195 extern void sbss_section PARAMS ((void));
197 /* Macros to silence warnings about numbers being signed in traditional
198 C and unsigned in ISO C when compiled on 32-bit hosts. */
200 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
201 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
202 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
205 /* Run-time compilation parameters selecting different hardware subsets. */
207 /* Macros used in the machine description to test the flags. */
209 /* Bits for real switches */
210 #define MASK_INT64 0x00000001 /* ints are 64 bits */
211 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
212 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
213 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
214 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
215 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
216 #define MASK_STATS 0x00000040 /* print statistics to stderr */
217 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
218 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
219 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
220 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
221 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
222 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
223 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
224 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
225 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
226 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
227 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
228 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
229 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
230 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
231 #define MASK_NO_CHECK_ZERO_DIV \
232 0x00200000 /* divide by zero checking */
233 #define MASK_CHECK_RANGE_DIV \
234 0x00400000 /* divide result range checking */
235 #define MASK_UNINIT_CONST_IN_RODATA \
236 0x00800000 /* Store uninitialized
238 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
239 multiply-add operations. */
240 #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
243 /* Debug switches, not documented */
244 #define MASK_DEBUG 0 /* unused */
245 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
246 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
247 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
248 #define MASK_DEBUG_D 0 /* don't do define_split's */
249 #define MASK_DEBUG_E 0 /* function_arg debug */
250 #define MASK_DEBUG_F 0 /* ??? */
251 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
252 #define MASK_DEBUG_I 0 /* unused */
254 /* Dummy switches used only in specs */
255 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
257 /* r4000 64 bit sizes */
258 #define TARGET_INT64 (target_flags & MASK_INT64)
259 #define TARGET_LONG64 (target_flags & MASK_LONG64)
260 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
261 #define TARGET_64BIT (target_flags & MASK_64BIT)
263 /* Mips vs. GNU linker */
264 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
266 /* Mips vs. GNU assembler */
267 #define TARGET_GAS (target_flags & MASK_GAS)
268 #define TARGET_MIPS_AS (!TARGET_GAS)
271 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
272 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
273 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
274 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
275 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
276 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
277 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
278 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
279 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
281 /* Reg. Naming in .s ($21 vs. $a0) */
282 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
284 /* Optimize for Sdata/Sbss */
285 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
287 /* print program statistics */
288 #define TARGET_STATS (target_flags & MASK_STATS)
290 /* call memcpy instead of inline code */
291 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
293 /* .abicalls, etc from Pyramid V.4 */
294 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
296 /* software floating point */
297 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
298 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
300 /* always call through a register */
301 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
303 /* generate embedded PIC code;
305 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
307 /* for embedded systems, optimize for
308 reduced RAM space instead of for
310 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
312 /* always store uninitialized const
313 variables in rodata, requires
314 TARGET_EMBEDDED_DATA. */
315 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
317 /* generate big endian code. */
318 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
320 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
321 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
323 #define TARGET_MAD (target_flags & MASK_MAD)
325 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
327 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
329 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
330 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
332 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
334 /* This is true if we must enable the assembly language file switching
337 #define TARGET_FILE_SWITCHING \
338 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
340 /* We must disable the function end stabs when doing the file switching trick,
341 because the Lscope stabs end up in the wrong place, making it impossible
342 to debug the resulting code. */
343 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
345 /* Generate mips16 code */
346 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
348 /* Generic ISA defines. */
349 #define ISA_MIPS1 (mips_isa == 1)
350 #define ISA_MIPS2 (mips_isa == 2)
351 #define ISA_MIPS3 (mips_isa == 3)
352 #define ISA_MIPS4 (mips_isa == 4)
353 #define ISA_MIPS32 (mips_isa == 32)
354 #define ISA_MIPS64 (mips_isa == 64)
356 /* Architecture target defines. */
357 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
358 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
359 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
360 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
361 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
362 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
363 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
364 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
365 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
366 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
367 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
369 /* Scheduling target defines. */
370 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
371 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
372 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
373 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
374 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
375 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
376 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
377 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
378 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
380 /* Define preprocessor macros for the -march and -mtune options.
381 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
382 processor. If INFO's canonical name is "foo", define PREFIX to
383 be "foo", and define an additional macro PREFIX_FOO. */
384 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
389 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
390 for (p = macro; *p != 0; p++) \
393 builtin_define (macro); \
394 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
399 /* Target CPU builtins. */
400 #define TARGET_CPU_CPP_BUILTINS() \
403 builtin_assert ("cpu=mips"); \
404 builtin_define ("__mips__"); \
405 builtin_define ("_mips"); \
407 /* We do this here because __mips is defined below \
408 and so we can't use builtin_define_std. */ \
410 builtin_define ("mips"); \
412 /* Treat _R3000 and _R4000 like register-size defines, \
413 which is how they've historically been used. */ \
416 builtin_define ("__mips64"); \
417 builtin_define_std ("R4000"); \
418 builtin_define ("_R4000"); \
422 builtin_define_std ("R3000"); \
423 builtin_define ("_R3000"); \
425 if (TARGET_FLOAT64) \
426 builtin_define ("__mips_fpr=64"); \
428 builtin_define ("__mips_fpr=32"); \
431 builtin_define ("__mips16"); \
433 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
434 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
438 builtin_define ("__mips=1"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
441 else if (ISA_MIPS2) \
443 builtin_define ("__mips=2"); \
444 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
446 else if (ISA_MIPS3) \
448 builtin_define ("__mips=3"); \
449 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
451 else if (ISA_MIPS4) \
453 builtin_define ("__mips=4"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
456 else if (ISA_MIPS32) \
458 builtin_define ("__mips=32"); \
459 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
461 else if (ISA_MIPS64) \
463 builtin_define ("__mips=64"); \
464 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
467 if (TARGET_HARD_FLOAT) \
468 builtin_define ("__mips_hard_float"); \
469 else if (TARGET_SOFT_FLOAT) \
470 builtin_define ("__mips_soft_float"); \
472 if (TARGET_SINGLE_FLOAT) \
473 builtin_define ("__mips_single_float"); \
475 if (TARGET_BIG_ENDIAN) \
477 builtin_define_std ("MIPSEB"); \
478 builtin_define ("_MIPSEB"); \
482 builtin_define_std ("MIPSEL"); \
483 builtin_define ("_MIPSEL"); \
486 /* Macros dependent on the C dialect. */ \
487 if (preprocessing_asm_p ()) \
489 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
490 builtin_define ("_LANGUAGE_ASSEMBLY"); \
492 else if (c_language == clk_c) \
494 builtin_define_std ("LANGUAGE_C"); \
495 builtin_define ("_LANGUAGE_C"); \
497 else if (c_language == clk_cplusplus) \
499 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
500 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
501 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
505 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
506 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
507 /* Bizzare, but needed at least for Irix. */ \
508 builtin_define_std ("LANGUAGE_C"); \
509 builtin_define ("_LANGUAGE_C"); \
512 if (mips_abi == ABI_EABI) \
513 builtin_define ("__mips_eabi"); \
519 /* Macro to define tables used to set the flags.
520 This is a list in braces of pairs in braces,
521 each pair being { "NAME", VALUE }
522 where VALUE is the bits to set or minus the bits to clear.
523 An empty string NAME is used to identify the default VALUE. */
525 #define TARGET_SWITCHES \
528 N_("No default crt0.o") }, \
529 {"int64", MASK_INT64 | MASK_LONG64, \
530 N_("Use 64-bit int type")}, \
531 {"long64", MASK_LONG64, \
532 N_("Use 64-bit long type")}, \
533 {"long32", -(MASK_LONG64 | MASK_INT64), \
534 N_("Use 32-bit long type")}, \
535 {"split-addresses", MASK_SPLIT_ADDR, \
536 N_("Optimize lui/addiu address loads")}, \
537 {"no-split-addresses", -MASK_SPLIT_ADDR, \
538 N_("Don't optimize lui/addiu address loads")}, \
539 {"mips-as", -MASK_GAS, \
540 N_("Use MIPS as")}, \
543 {"rnames", MASK_NAME_REGS, \
544 N_("Use symbolic register names")}, \
545 {"no-rnames", -MASK_NAME_REGS, \
546 N_("Don't use symbolic register names")}, \
547 {"gpOPT", MASK_GPOPT, \
548 N_("Use GP relative sdata/sbss sections")}, \
549 {"gpopt", MASK_GPOPT, \
550 N_("Use GP relative sdata/sbss sections")}, \
551 {"no-gpOPT", -MASK_GPOPT, \
552 N_("Don't use GP relative sdata/sbss sections")}, \
553 {"no-gpopt", -MASK_GPOPT, \
554 N_("Don't use GP relative sdata/sbss sections")}, \
555 {"stats", MASK_STATS, \
556 N_("Output compiler statistics")}, \
557 {"no-stats", -MASK_STATS, \
558 N_("Don't output compiler statistics")}, \
559 {"memcpy", MASK_MEMCPY, \
560 N_("Don't optimize block moves")}, \
561 {"no-memcpy", -MASK_MEMCPY, \
562 N_("Optimize block moves")}, \
563 {"mips-tfile", MASK_MIPS_TFILE, \
564 N_("Use mips-tfile asm postpass")}, \
565 {"no-mips-tfile", -MASK_MIPS_TFILE, \
566 N_("Don't use mips-tfile asm postpass")}, \
567 {"soft-float", MASK_SOFT_FLOAT, \
568 N_("Use software floating point")}, \
569 {"hard-float", -MASK_SOFT_FLOAT, \
570 N_("Use hardware floating point")}, \
571 {"fp64", MASK_FLOAT64, \
572 N_("Use 64-bit FP registers")}, \
573 {"fp32", -MASK_FLOAT64, \
574 N_("Use 32-bit FP registers")}, \
575 {"gp64", MASK_64BIT, \
576 N_("Use 64-bit general registers")}, \
577 {"gp32", -MASK_64BIT, \
578 N_("Use 32-bit general registers")}, \
579 {"abicalls", MASK_ABICALLS, \
580 N_("Use Irix PIC")}, \
581 {"no-abicalls", -MASK_ABICALLS, \
582 N_("Don't use Irix PIC")}, \
583 {"long-calls", MASK_LONG_CALLS, \
584 N_("Use indirect calls")}, \
585 {"no-long-calls", -MASK_LONG_CALLS, \
586 N_("Don't use indirect calls")}, \
587 {"embedded-pic", MASK_EMBEDDED_PIC, \
588 N_("Use embedded PIC")}, \
589 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
590 N_("Don't use embedded PIC")}, \
591 {"embedded-data", MASK_EMBEDDED_DATA, \
592 N_("Use ROM instead of RAM")}, \
593 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
594 N_("Don't use ROM instead of RAM")}, \
595 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
596 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
597 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
598 N_("Don't put uninitialized constants in ROM")}, \
599 {"eb", MASK_BIG_ENDIAN, \
600 N_("Use big-endian byte order")}, \
601 {"el", -MASK_BIG_ENDIAN, \
602 N_("Use little-endian byte order")}, \
603 {"single-float", MASK_SINGLE_FLOAT, \
604 N_("Use single (32-bit) FP only")}, \
605 {"double-float", -MASK_SINGLE_FLOAT, \
606 N_("Don't use single (32-bit) FP only")}, \
608 N_("Use multiply accumulate")}, \
609 {"no-mad", -MASK_MAD, \
610 N_("Don't use multiply accumulate")}, \
611 {"no-fused-madd", MASK_NO_FUSED_MADD, \
612 N_("Don't generate fused multiply/add instructions")}, \
613 {"fused-madd", -MASK_NO_FUSED_MADD, \
614 N_("Generate fused multiply/add instructions")}, \
615 {"fix4300", MASK_4300_MUL_FIX, \
616 N_("Work around early 4300 hardware bug")}, \
617 {"no-fix4300", -MASK_4300_MUL_FIX, \
618 N_("Don't work around early 4300 hardware bug")}, \
619 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
620 N_("Trap on integer divide by zero")}, \
621 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
622 N_("Don't trap on integer divide by zero")}, \
623 {"check-range-division",MASK_CHECK_RANGE_DIV, \
624 N_("Trap on integer divide overflow")}, \
625 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
626 N_("Don't trap on integer divide overflow")}, \
627 { "branch-likely", MASK_BRANCHLIKELY, \
628 N_("Use Branch Likely instructions, overriding default for arch")}, \
629 { "no-branch-likely", -MASK_BRANCHLIKELY, \
630 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
631 {"debug", MASK_DEBUG, \
633 {"debuga", MASK_DEBUG_A, \
635 {"debugb", MASK_DEBUG_B, \
637 {"debugc", MASK_DEBUG_C, \
639 {"debugd", MASK_DEBUG_D, \
641 {"debuge", MASK_DEBUG_E, \
643 {"debugf", MASK_DEBUG_F, \
645 {"debugg", MASK_DEBUG_G, \
647 {"debugi", MASK_DEBUG_I, \
649 {"", (TARGET_DEFAULT \
650 | TARGET_CPU_DEFAULT \
651 | TARGET_ENDIAN_DEFAULT), \
655 /* Default target_flags if no switches are specified */
657 #ifndef TARGET_DEFAULT
658 #define TARGET_DEFAULT 0
661 #ifndef TARGET_CPU_DEFAULT
662 #define TARGET_CPU_DEFAULT 0
665 #ifndef TARGET_ENDIAN_DEFAULT
666 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
669 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
670 #ifndef MIPS_ISA_DEFAULT
671 #ifndef MIPS_CPU_STRING_DEFAULT
672 #define MIPS_CPU_STRING_DEFAULT "from-abi"
678 /* Make this compile time constant for libgcc2 */
680 #define TARGET_64BIT 1
682 #define TARGET_64BIT 0
684 #endif /* IN_LIBGCC2 */
686 #ifndef MULTILIB_ENDIAN_DEFAULT
687 #if TARGET_ENDIAN_DEFAULT == 0
688 #define MULTILIB_ENDIAN_DEFAULT "EL"
690 #define MULTILIB_ENDIAN_DEFAULT "EB"
694 #ifndef MULTILIB_ISA_DEFAULT
695 # if MIPS_ISA_DEFAULT == 1
696 # define MULTILIB_ISA_DEFAULT "mips1"
698 # if MIPS_ISA_DEFAULT == 2
699 # define MULTILIB_ISA_DEFAULT "mips2"
701 # if MIPS_ISA_DEFAULT == 3
702 # define MULTILIB_ISA_DEFAULT "mips3"
704 # if MIPS_ISA_DEFAULT == 4
705 # define MULTILIB_ISA_DEFAULT "mips4"
707 # if MIPS_ISA_DEFAULT == 32
708 # define MULTILIB_ISA_DEFAULT "mips32"
710 # if MIPS_ISA_DEFAULT == 64
711 # define MULTILIB_ISA_DEFAULT "mips64"
713 # define MULTILIB_ISA_DEFAULT "mips1"
722 #ifndef MULTILIB_DEFAULTS
723 #define MULTILIB_DEFAULTS \
724 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
727 /* We must pass -EL to the linker by default for little endian embedded
728 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
729 linker will default to using big-endian output files. The OUTPUT_FORMAT
730 line must be in the linker script, otherwise -EB/-EL will not work. */
733 #if TARGET_ENDIAN_DEFAULT == 0
734 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
736 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
740 #define TARGET_OPTIONS \
742 SUBTARGET_TARGET_OPTIONS \
743 { "tune=", &mips_tune_string, \
744 N_("Specify CPU for scheduling purposes")}, \
745 { "arch=", &mips_arch_string, \
746 N_("Specify CPU for code generation purposes")}, \
747 { "abi=", &mips_abi_string, \
748 N_("Specify an ABI")}, \
749 { "ips", &mips_isa_string, \
750 N_("Specify a Standard MIPS ISA")}, \
751 { "entry", &mips_entry_string, \
752 N_("Use mips16 entry/exit psuedo ops")}, \
753 { "no-mips16", &mips_no_mips16_string, \
754 N_("Don't use MIPS16 instructions")}, \
755 { "no-flush-func", &mips_cache_flush_func, \
756 N_("Don't call any cache flush functions")}, \
757 { "flush-func=", &mips_cache_flush_func, \
758 N_("Specify cache flush function")}, \
761 /* This is meant to be redefined in the host dependent files. */
762 #define SUBTARGET_TARGET_OPTIONS
764 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
768 /* Generate three-operand multiply instructions for SImode. */
769 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
776 /* Generate three-operand multiply instructions for DImode. */
777 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
780 /* Macros to decide whether certain features are available or not,
781 depending on the instruction set architecture level. */
783 #define HAVE_SQRT_P() (!ISA_MIPS1)
785 /* True if the ABI can only work with 64-bit integer registers. We
786 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
787 otherwise floating-point registers must also be 64-bit. */
788 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
789 || mips_abi == ABI_O64 \
790 || mips_abi == ABI_N32)
792 /* Likewise for 32-bit regs. */
793 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
795 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
796 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
800 /* ISA has branch likely instructions (eg. mips2). */
801 /* Disable branchlikely for tx39 until compare rewrite. They haven't
802 been generated up to this point. */
803 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
806 /* ISA has the conditional move instructions introduced in mips4. */
807 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
810 && !TARGET_MIPS5500 \
813 /* ISA has just the integer condition move instructions (movn,movz) */
814 #define ISA_HAS_INT_CONDMOVE 0
816 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
817 branch on CC, and move (both FP and non-FP) on CC. */
818 #define ISA_HAS_8CC (ISA_MIPS4 \
822 /* This is a catch all for the other new mips4 instructions: indexed load and
823 indexed prefetch instructions, the FP madd and msub instructions,
824 and the FP recip and recip sqrt instructions */
825 #define ISA_HAS_FP4 ((ISA_MIPS4 \
829 /* ISA has conditional trap instructions. */
830 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
833 /* ISA has integer multiply-accumulate instructions, madd and msub. */
834 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
838 /* ISA has floating-point nmadd and nmsub instructions. */
839 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
841 && (!TARGET_MIPS5400 || TARGET_MAD) \
844 /* ISA has count leading zeroes/ones instruction (not implemented). */
845 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
849 /* ISA has double-word count leading zeroes/ones instruction (not
851 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
854 /* ISA has three operand multiply instructions that put
855 the high part in an accumulator: mulhi or mulhiu. */
856 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
861 /* ISA has three operand multiply instructions that
862 negates the result and puts the result in an accumulator. */
863 #define ISA_HAS_MULS (TARGET_MIPS5400 \
868 /* ISA has three operand multiply instructions that subtracts the
869 result from a 4th operand and puts the result in an accumulator. */
870 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
874 /* ISA has three operand multiply instructions that the result
875 from a 4th operand and puts the result in an accumulator. */
876 #define ISA_HAS_MACC (TARGET_MIPS5400 \
881 /* ISA has 32-bit rotate right instruction. */
882 #define ISA_HAS_ROTR_SI (TARGET_MIPS5400 \
887 /* ISA has 32-bit rotate right instruction. */
888 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
889 && (TARGET_MIPS5400 \
895 /* ISA has data prefetch instruction. */
896 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
901 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
902 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
903 also requires TARGET_DOUBLE_FLOAT. */
904 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
906 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
907 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
908 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
909 target_flags, and -mgp64 sets MASK_64BIT.
911 Setting MASK_64BIT in target_flags will cause gcc to assume that
912 registers are 64 bits wide. int, long and void * will be 32 bit;
913 this may be changed with -mint64 or -mlong64.
915 The gen* programs link code that refers to MASK_64BIT. They don't
916 actually use the information in target_flags; they just refer to
919 /* Switch Recognition by gcc.c. Add -G xx support */
921 #undef SWITCH_TAKES_ARG
922 #define SWITCH_TAKES_ARG(CHAR) \
923 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
925 /* Sometimes certain combinations of command options do not make sense
926 on a particular target machine. You can define a macro
927 `OVERRIDE_OPTIONS' to take account of this. This macro, if
928 defined, is executed once just after all the command options have
931 On the MIPS, it is used to handle -G. We also use it to set up all
932 of the tables referenced in the other macros. */
934 #define OVERRIDE_OPTIONS override_options ()
936 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
938 /* Show we can debug even without a frame pointer. */
939 #define CAN_DEBUG_WITHOUT_FP
941 /* Tell collect what flags to pass to nm. */
943 #define NM_FLAGS "-Bn"
947 /* Assembler specs. */
949 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
952 #define MIPS_AS_ASM_SPEC "\
953 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
954 %{pipe: %e-pipe is not supported} \
955 %{K} %(subtarget_mips_as_asm_spec)"
957 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
958 rather than gas. It may be overridden by subtargets. */
960 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
961 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
964 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
967 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
972 #ifndef MIPS_ABI_DEFAULT
973 #define MIPS_ABI_DEFAULT ABI_32
976 /* Use the most portable ABI flag for the ASM specs. */
978 #if MIPS_ABI_DEFAULT == ABI_32
979 #define MULTILIB_ABI_DEFAULT "mabi=32"
980 #define ASM_ABI_DEFAULT_SPEC "-32"
983 #if MIPS_ABI_DEFAULT == ABI_O64
984 #define MULTILIB_ABI_DEFAULT "mabi=o64"
985 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
988 #if MIPS_ABI_DEFAULT == ABI_N32
989 #define MULTILIB_ABI_DEFAULT "mabi=n32"
990 #define ASM_ABI_DEFAULT_SPEC "-n32"
993 #if MIPS_ABI_DEFAULT == ABI_64
994 #define MULTILIB_ABI_DEFAULT "mabi=64"
995 #define ASM_ABI_DEFAULT_SPEC "-64"
998 #if MIPS_ABI_DEFAULT == ABI_EABI
999 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1000 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1003 #if MIPS_ABI_DEFAULT == ABI_MEABI
1004 /* Most GAS don't know about MEABI. */
1005 #define MULTILIB_ABI_DEFAULT "mabi=meabi"
1006 #define ASM_ABI_DEFAULT_SPEC ""
1009 /* Only ELF targets can switch the ABI. */
1010 #ifndef OBJECT_FORMAT_ELF
1011 #undef ASM_ABI_DEFAULT_SPEC
1012 #define ASM_ABI_DEFAULT_SPEC ""
1015 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1016 GAS_ASM_SPEC as the default, depending upon the value of
1019 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1022 #define TARGET_ASM_SPEC "\
1023 %{mmips-as: %(mips_as_asm_spec)} \
1024 %{!mmips-as: %(gas_asm_spec)}"
1028 #define TARGET_ASM_SPEC "\
1029 %{!mgas: %(mips_as_asm_spec)} \
1030 %{mgas: %(gas_asm_spec)}"
1032 #endif /* not GAS */
1034 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1035 to the assembler. It may be overridden by subtargets. */
1036 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1037 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1039 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1042 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1043 the assembler. It may be overridden by subtargets. */
1044 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1045 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1046 %{g} %{g0} %{g1} %{g2} %{g3} \
1047 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1048 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1049 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1050 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1051 %{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1054 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1055 overridden by subtargets. */
1057 #ifndef SUBTARGET_ASM_SPEC
1058 #define SUBTARGET_ASM_SPEC ""
1061 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1062 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1063 whether we're using GAS. These options can only be used properly
1064 with GAS, and it is better to get an error from a non-GAS assembler
1065 than to silently generate bad code. */
1069 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
1070 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1071 %(subtarget_asm_optimizing_spec) \
1072 %(subtarget_asm_debugging_spec) \
1074 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1075 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1076 %{mgp32} %{mgp64} %{march=*} \
1077 %(target_asm_spec) \
1078 %(subtarget_asm_spec)"
1080 /* Specify to run a post-processor, mips-tfile after the assembler
1081 has run to stuff the mips debug information into the object file.
1082 This is needed because the $#!%^ MIPS assembler provides no way
1083 of specifying such information in the assembly file. If we are
1084 cross compiling, disable mips-tfile unless the user specifies
1087 #ifndef ASM_FINAL_SPEC
1088 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1090 #define ASM_FINAL_SPEC "\
1091 %{mmips-as: %{!mno-mips-tfile: \
1092 \n mips-tfile %{v*: -v} \
1094 %{!K: %{save-temps: -I %b.o~}} \
1095 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1096 %{.s:%i} %{!.s:%g.s}}}"
1100 #define ASM_FINAL_SPEC "\
1101 %{!mgas: %{!mno-mips-tfile: \
1102 \n mips-tfile %{v*: -v} \
1104 %{!K: %{save-temps: -I %b.o~}} \
1105 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1106 %{.s:%i} %{!.s:%g.s}}}"
1109 #endif /* ASM_FINAL_SPEC */
1111 /* Redefinition of libraries used. Mips doesn't support normal
1112 UNIX style profiling via calling _mcount. It does offer
1113 profiling that samples the PC, so do what we can... */
1116 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1119 /* Extra switches sometimes passed to the linker. */
1120 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1121 will interpret it as a -b option. */
1124 #define LINK_SPEC "\
1126 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
1127 %{bestGnum} %{shared} %{non_shared}"
1128 #endif /* LINK_SPEC defined */
1131 /* Specs for the compiler proper */
1133 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1134 overridden by subtargets. */
1135 #ifndef SUBTARGET_CC1_SPEC
1136 #define SUBTARGET_CC1_SPEC ""
1139 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1140 /* Note, we will need to adjust the following if we ever find a MIPS variant
1141 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1142 that show up in this case. */
1146 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1147 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1149 %(subtarget_cc1_spec)"
1152 /* Preprocessor specs. */
1154 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1155 overridden by subtargets. */
1156 #ifndef SUBTARGET_CPP_SPEC
1157 #define SUBTARGET_CPP_SPEC ""
1160 #define CPP_SPEC "%(subtarget_cpp_spec)"
1162 /* This macro defines names of additional specifications to put in the specs
1163 that can be used in various specifications like CC1_SPEC. Its definition
1164 is an initializer with a subgrouping for each command option.
1166 Each subgrouping contains a string constant, that defines the
1167 specification name, and a string constant that used by the GNU CC driver
1170 Do not define this macro if it does not need to do anything. */
1172 #define EXTRA_SPECS \
1173 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1174 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1175 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1176 { "gas_asm_spec", GAS_ASM_SPEC }, \
1177 { "target_asm_spec", TARGET_ASM_SPEC }, \
1178 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1179 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1180 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1181 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1182 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1183 { "endian_spec", ENDIAN_SPEC }, \
1184 SUBTARGET_EXTRA_SPECS
1186 #ifndef SUBTARGET_EXTRA_SPECS
1187 #define SUBTARGET_EXTRA_SPECS
1190 /* If defined, this macro is an additional prefix to try after
1191 `STANDARD_EXEC_PREFIX'. */
1193 #ifndef MD_EXEC_PREFIX
1194 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1197 #ifndef MD_STARTFILE_PREFIX
1198 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1202 /* Print subsidiary information on the compiler version in use. */
1204 #define MIPS_VERSION "[AL 1.1, MM 40]"
1206 #ifndef MACHINE_TYPE
1207 #define MACHINE_TYPE "BSD Mips"
1210 #ifndef TARGET_VERSION_INTERNAL
1211 #define TARGET_VERSION_INTERNAL(STREAM) \
1212 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1215 #ifndef TARGET_VERSION
1216 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1220 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1221 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1222 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1224 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1225 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1228 /* By default, turn on GDB extensions. */
1229 #define DEFAULT_GDB_EXTENSIONS 1
1231 /* If we are passing smuggling stabs through the MIPS ECOFF object
1232 format, put a comment in front of the .stab<x> operation so
1233 that the MIPS assembler does not choke. The mips-tfile program
1234 will correctly put the stab into the object file. */
1236 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1237 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1238 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1240 /* Local compiler-generated symbols must have a prefix that the assembler
1241 understands. By default, this is $, although some targets (e.g.,
1242 NetBSD-ELF) need to override this. */
1244 #ifndef LOCAL_LABEL_PREFIX
1245 #define LOCAL_LABEL_PREFIX "$"
1248 /* By default on the mips, external symbols do not have an underscore
1249 prepended, but some targets (e.g., NetBSD) require this. */
1251 #ifndef USER_LABEL_PREFIX
1252 #define USER_LABEL_PREFIX ""
1255 /* Forward references to tags are allowed. */
1256 #define SDB_ALLOW_FORWARD_REFERENCES
1258 /* Unknown tags are also allowed. */
1259 #define SDB_ALLOW_UNKNOWN_REFERENCES
1261 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1262 since the length can run past this up to a continuation point. */
1263 #undef DBX_CONTIN_LENGTH
1264 #define DBX_CONTIN_LENGTH 1500
1266 /* How to renumber registers for dbx and gdb. */
1267 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1269 /* The mapping from gcc register number to DWARF 2 CFA column number.
1270 This mapping does not allow for tracking register 0, since SGI's broken
1271 dwarf reader thinks column 0 is used for the frame address, but since
1272 register 0 is fixed this is not a problem. */
1273 #define DWARF_FRAME_REGNUM(REG) \
1274 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1276 /* The DWARF 2 CFA column which tracks the return address. */
1277 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1279 /* Before the prologue, RA lives in r31. */
1280 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1282 /* Describe how we implement __builtin_eh_return. */
1283 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1284 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1286 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1287 The default for this in 64-bit mode is 8, which causes problems with
1288 SFmode register saves. */
1289 #define DWARF_CIE_DATA_ALIGNMENT 4
1291 /* Overrides for the COFF debug format. */
1292 #define PUT_SDB_SCL(a) \
1294 extern FILE *asm_out_text_file; \
1295 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1298 #define PUT_SDB_INT_VAL(a) \
1300 extern FILE *asm_out_text_file; \
1301 fprintf (asm_out_text_file, "\t.val\t"); \
1302 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1303 fprintf (asm_out_text_file, ";"); \
1306 #define PUT_SDB_VAL(a) \
1308 extern FILE *asm_out_text_file; \
1309 fputs ("\t.val\t", asm_out_text_file); \
1310 output_addr_const (asm_out_text_file, (a)); \
1311 fputc (';', asm_out_text_file); \
1314 #define PUT_SDB_DEF(a) \
1316 extern FILE *asm_out_text_file; \
1317 fprintf (asm_out_text_file, "\t%s.def\t", \
1318 (TARGET_GAS) ? "" : "#"); \
1319 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1320 fputc (';', asm_out_text_file); \
1323 #define PUT_SDB_PLAIN_DEF(a) \
1325 extern FILE *asm_out_text_file; \
1326 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1327 (TARGET_GAS) ? "" : "#", (a)); \
1330 #define PUT_SDB_ENDEF \
1332 extern FILE *asm_out_text_file; \
1333 fprintf (asm_out_text_file, "\t.endef\n"); \
1336 #define PUT_SDB_TYPE(a) \
1338 extern FILE *asm_out_text_file; \
1339 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1342 #define PUT_SDB_SIZE(a) \
1344 extern FILE *asm_out_text_file; \
1345 fprintf (asm_out_text_file, "\t.size\t"); \
1346 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1347 fprintf (asm_out_text_file, ";"); \
1350 #define PUT_SDB_DIM(a) \
1352 extern FILE *asm_out_text_file; \
1353 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1356 #ifndef PUT_SDB_START_DIM
1357 #define PUT_SDB_START_DIM \
1359 extern FILE *asm_out_text_file; \
1360 fprintf (asm_out_text_file, "\t.dim\t"); \
1364 #ifndef PUT_SDB_NEXT_DIM
1365 #define PUT_SDB_NEXT_DIM(a) \
1367 extern FILE *asm_out_text_file; \
1368 fprintf (asm_out_text_file, "%d,", a); \
1372 #ifndef PUT_SDB_LAST_DIM
1373 #define PUT_SDB_LAST_DIM(a) \
1375 extern FILE *asm_out_text_file; \
1376 fprintf (asm_out_text_file, "%d;", a); \
1380 #define PUT_SDB_TAG(a) \
1382 extern FILE *asm_out_text_file; \
1383 fprintf (asm_out_text_file, "\t.tag\t"); \
1384 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1385 fputc (';', asm_out_text_file); \
1388 /* For block start and end, we create labels, so that
1389 later we can figure out where the correct offset is.
1390 The normal .ent/.end serve well enough for functions,
1391 so those are just commented out. */
1393 #define PUT_SDB_BLOCK_START(LINE) \
1395 extern FILE *asm_out_text_file; \
1396 fprintf (asm_out_text_file, \
1397 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1398 LOCAL_LABEL_PREFIX, \
1400 (TARGET_GAS) ? "" : "#", \
1401 LOCAL_LABEL_PREFIX, \
1404 sdb_label_count++; \
1407 #define PUT_SDB_BLOCK_END(LINE) \
1409 extern FILE *asm_out_text_file; \
1410 fprintf (asm_out_text_file, \
1411 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1412 LOCAL_LABEL_PREFIX, \
1414 (TARGET_GAS) ? "" : "#", \
1415 LOCAL_LABEL_PREFIX, \
1418 sdb_label_count++; \
1421 #define PUT_SDB_FUNCTION_START(LINE)
1423 #define PUT_SDB_FUNCTION_END(LINE) \
1425 extern FILE *asm_out_text_file; \
1426 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1429 #define PUT_SDB_EPILOGUE_END(NAME)
1431 #define PUT_SDB_SRC_FILE(FILENAME) \
1433 extern FILE *asm_out_text_file; \
1434 output_file_directive (asm_out_text_file, (FILENAME));\
1437 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1438 sprintf ((BUFFER), ".%dfake", (NUMBER));
1440 /* Correct the offset of automatic variables and arguments. Note that
1441 the MIPS debug format wants all automatic variables and arguments
1442 to be in terms of the virtual frame pointer (stack pointer before
1443 any adjustment in the function), while the MIPS 3.0 linker wants
1444 the frame pointer to be the stack pointer after the initial
1447 #define DEBUGGER_AUTO_OFFSET(X) \
1448 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1449 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1450 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1452 /* Tell collect that the object format is ECOFF */
1453 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1454 #define EXTENDED_COFF /* ECOFF, not normal coff */
1456 /* Target machine storage layout */
1458 /* Define this if most significant bit is lowest numbered
1459 in instructions that operate on numbered bit-fields.
1461 #define BITS_BIG_ENDIAN 0
1463 /* Define this if most significant byte of a word is the lowest numbered. */
1464 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1466 /* Define this if most significant word of a multiword number is the lowest. */
1467 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1469 /* Define this to set the endianness to use in libgcc2.c, which can
1470 not depend on target_flags. */
1471 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1472 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1474 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1477 #define MAX_BITS_PER_WORD 64
1479 /* Width of a word, in units (bytes). */
1480 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1481 #define MIN_UNITS_PER_WORD 4
1483 /* For MIPS, width of a floating point register. */
1484 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1486 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1487 the next available register. */
1488 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1490 /* The largest size of value that can be held in floating-point registers. */
1491 #define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1493 /* The number of bytes in a double. */
1494 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1496 /* A C expression for the size in bits of the type `int' on the
1497 target machine. If you don't define this, the default is one
1499 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1501 /* Tell the preprocessor the maximum size of wchar_t. */
1502 #ifndef MAX_WCHAR_TYPE_SIZE
1503 #ifndef WCHAR_TYPE_SIZE
1504 #define MAX_WCHAR_TYPE_SIZE 64
1508 /* A C expression for the size in bits of the type `short' on the
1509 target machine. If you don't define this, the default is half a
1510 word. (If this would be less than one storage unit, it is
1511 rounded up to one unit.) */
1512 #define SHORT_TYPE_SIZE 16
1514 /* A C expression for the size in bits of the type `long' on the
1515 target machine. If you don't define this, the default is one
1517 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1518 #define MAX_LONG_TYPE_SIZE 64
1520 /* A C expression for the size in bits of the type `long long' on the
1521 target machine. If you don't define this, the default is two
1523 #define LONG_LONG_TYPE_SIZE 64
1525 /* A C expression for the size in bits of the type `float' on the
1526 target machine. If you don't define this, the default is one
1528 #define FLOAT_TYPE_SIZE 32
1530 /* A C expression for the size in bits of the type `double' on the
1531 target machine. If you don't define this, the default is two
1533 #define DOUBLE_TYPE_SIZE 64
1535 /* A C expression for the size in bits of the type `long double' on
1536 the target machine. If you don't define this, the default is two
1538 #define LONG_DOUBLE_TYPE_SIZE 64
1540 /* Width in bits of a pointer.
1541 See also the macro `Pmode' defined below. */
1542 #ifndef POINTER_SIZE
1543 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1546 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1547 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1549 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1550 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1551 || mips_abi == ABI_64 \
1552 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1554 /* Allocation boundary (in *bits*) for the code of a function. */
1555 #define FUNCTION_BOUNDARY 32
1557 /* Alignment of field after `int : 0' in a structure. */
1558 #define EMPTY_FIELD_BOUNDARY 32
1560 /* Every structure's size must be a multiple of this. */
1561 /* 8 is observed right on a DECstation and on riscos 4.02. */
1562 #define STRUCTURE_SIZE_BOUNDARY 8
1564 /* There is no point aligning anything to a rounder boundary than this. */
1565 #define BIGGEST_ALIGNMENT 64
1567 /* Set this nonzero if move instructions will actually fail to work
1568 when given unaligned data. */
1569 #define STRICT_ALIGNMENT 1
1571 /* Define this if you wish to imitate the way many other C compilers
1572 handle alignment of bitfields and the structures that contain
1575 The behavior is that the type written for a bit-field (`int',
1576 `short', or other integer type) imposes an alignment for the
1577 entire structure, as if the structure really did contain an
1578 ordinary field of that type. In addition, the bit-field is placed
1579 within the structure so that it would fit within such a field,
1580 not crossing a boundary for it.
1582 Thus, on most machines, a bit-field whose type is written as `int'
1583 would not cross a four-byte boundary, and would force four-byte
1584 alignment for the whole structure. (The alignment used may not
1585 be four bytes; it is controlled by the other alignment
1588 If the macro is defined, its definition should be a C expression;
1589 a nonzero value for the expression enables this behavior. */
1591 #define PCC_BITFIELD_TYPE_MATTERS 1
1593 /* If defined, a C expression to compute the alignment given to a
1594 constant that is being placed in memory. CONSTANT is the constant
1595 and ALIGN is the alignment that the object would ordinarily have.
1596 The value of this macro is used instead of that alignment to align
1599 If this macro is not defined, then ALIGN is used.
1601 The typical use of this macro is to increase alignment for string
1602 constants to be word aligned so that `strcpy' calls that copy
1603 constants can be done inline. */
1605 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1606 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1607 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1609 /* If defined, a C expression to compute the alignment for a static
1610 variable. TYPE is the data type, and ALIGN is the alignment that
1611 the object would ordinarily have. The value of this macro is used
1612 instead of that alignment to align the object.
1614 If this macro is not defined, then ALIGN is used.
1616 One use of this macro is to increase alignment of medium-size
1617 data to make it all fit in fewer cache lines. Another is to
1618 cause character arrays to be word-aligned so that `strcpy' calls
1619 that copy constants to character arrays can be done inline. */
1621 #undef DATA_ALIGNMENT
1622 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1623 ((((ALIGN) < BITS_PER_WORD) \
1624 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1625 || TREE_CODE (TYPE) == UNION_TYPE \
1626 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1629 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1631 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1632 || mips_abi == ABI_MEABI \
1633 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1635 /* Define this macro if an argument declared as `char' or `short' in a
1636 prototype should actually be passed as an `int'. In addition to
1637 avoiding errors in certain cases of mismatch, it also makes for
1638 better code on certain machines. */
1640 #define PROMOTE_PROTOTYPES 1
1642 /* Define if operations between registers always perform the operation
1643 on the full register even if a narrower mode is specified. */
1644 #define WORD_REGISTER_OPERATIONS
1646 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1647 will either zero-extend or sign-extend. The value of this macro should
1648 be the code that says which one of the two operations is implicitly
1651 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1652 moves. All other referces are zero extended. */
1653 #define LOAD_EXTEND_OP(MODE) \
1654 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1655 ? SIGN_EXTEND : ZERO_EXTEND)
1657 /* Define this macro if it is advisable to hold scalars in registers
1658 in a wider mode than that declared by the program. In such cases,
1659 the value is constrained to be within the bounds of the declared
1660 type, but kept valid in the wider mode. The signedness of the
1661 extension may differ from that of the type.
1663 We promote any value smaller than SImode up to SImode. We don't
1664 want to promote to DImode when in 64 bit mode, because that would
1665 prevent us from using the faster SImode multiply and divide
1668 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1669 if (GET_MODE_CLASS (MODE) == MODE_INT \
1670 && GET_MODE_SIZE (MODE) < 4) \
1673 /* Define this if function arguments should also be promoted using the above
1676 #define PROMOTE_FUNCTION_ARGS
1678 /* Likewise, if the function return value is promoted. */
1680 #define PROMOTE_FUNCTION_RETURN
1682 /* Standard register usage. */
1684 /* Number of actual hardware registers.
1685 The hardware registers are assigned numbers for the compiler
1686 from 0 to just below FIRST_PSEUDO_REGISTER.
1687 All registers that the compiler knows about must be given numbers,
1688 even those that are not normally considered general registers.
1690 On the Mips, we have 32 integer registers, 32 floating point
1691 registers, 8 condition code registers, and the special registers
1692 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1693 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1694 processor.) The 8 condition code registers are only used if
1695 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1696 represents a 64 bit value stored as two 32 bit values in the hi and
1697 lo registers; this is the result of the mult instruction. rap is a
1698 pointer to the stack where the return address reg ($31) was stored.
1699 This is needed for C++ exception handling. */
1701 #define FIRST_PSEUDO_REGISTER 176
1703 /* 1 for registers that have pervasive standard uses
1704 and are not available for the register allocator.
1706 On the MIPS, see conventions, page D-2 */
1708 /* Regarding coprocessor registers: without evidence to the contrary,
1709 it's best to assume that each coprocessor register has a unique
1710 use. This can be overridden, in, e.g., override_options() or
1711 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1712 for a particular target. */
1714 #define FIXED_REGISTERS \
1716 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1717 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1718 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1719 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1720 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
1721 /* COP0 registers */ \
1722 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1723 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1724 /* COP2 registers */ \
1725 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1726 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1727 /* COP3 registers */ \
1728 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1729 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1733 /* 1 for registers not available across function calls.
1734 These must include the FIXED_REGISTERS and also any
1735 registers that can be used without being saved.
1736 The latter must include the registers where values are returned
1737 and the register where structure-value addresses are passed.
1738 Aside from that, you can include as many other registers as you like. */
1740 #define CALL_USED_REGISTERS \
1742 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1743 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1744 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1745 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1746 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1747 /* COP0 registers */ \
1748 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1749 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1750 /* COP2 registers */ \
1751 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1752 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1753 /* COP3 registers */ \
1754 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1755 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1758 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1759 problem which makes CALL_USED_REGISTERS *always* include
1760 all the FIXED_REGISTERS. Until this problem has been
1761 resolved this macro can be used to overcome this situation.
1762 In particular, block_propagate() requires this list
1763 be acurate, or we can remove registers which should be live.
1764 This macro is used in regs_invalidated_by_call. */
1767 #define CALL_REALLY_USED_REGISTERS \
1768 { /* General registers. */ \
1769 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1770 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1771 /* Floating-point registers. */ \
1772 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1773 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1775 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1776 /* COP0 registers */ \
1777 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1778 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1779 /* COP2 registers */ \
1780 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1781 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1782 /* COP3 registers */ \
1783 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1784 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1787 /* Internal macros to classify a register number as to whether it's a
1788 general purpose register, a floating point register, a
1789 multiply/divide register, or a status register. */
1791 #define GP_REG_FIRST 0
1792 #define GP_REG_LAST 31
1793 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1794 #define GP_DBX_FIRST 0
1796 #define FP_REG_FIRST 32
1797 #define FP_REG_LAST 63
1798 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1799 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1801 #define MD_REG_FIRST 64
1802 #define MD_REG_LAST 66
1803 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1805 #define ST_REG_FIRST 67
1806 #define ST_REG_LAST 74
1807 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1809 #define RAP_REG_NUM 75
1811 #define COP0_REG_FIRST 80
1812 #define COP0_REG_LAST 111
1813 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1815 #define COP2_REG_FIRST 112
1816 #define COP2_REG_LAST 143
1817 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1819 #define COP3_REG_FIRST 144
1820 #define COP3_REG_LAST 175
1821 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1822 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1823 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1825 #define AT_REGNUM (GP_REG_FIRST + 1)
1826 #define HI_REGNUM (MD_REG_FIRST + 0)
1827 #define LO_REGNUM (MD_REG_FIRST + 1)
1828 #define HILO_REGNUM (MD_REG_FIRST + 2)
1830 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1831 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1832 should be used instead. */
1833 #define FPSW_REGNUM ST_REG_FIRST
1835 #define GP_REG_P(REGNO) \
1836 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1837 #define M16_REG_P(REGNO) \
1838 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1839 #define FP_REG_P(REGNO) \
1840 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1841 #define MD_REG_P(REGNO) \
1842 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1843 #define ST_REG_P(REGNO) \
1844 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1845 #define COP0_REG_P(REGNO) \
1846 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1847 #define COP2_REG_P(REGNO) \
1848 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1849 #define COP3_REG_P(REGNO) \
1850 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1851 #define ALL_COP_REG_P(REGNO) \
1852 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1854 /* Return coprocessor number from register number. */
1856 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1857 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1858 : COP3_REG_P (REGNO) ? '3' : '?')
1860 /* Return number of consecutive hard regs needed starting at reg REGNO
1861 to hold something of mode MODE.
1862 This is ordinarily the length in words of a value of mode MODE
1863 but can be less for certain modes in special long registers.
1865 On the MIPS, all general registers are one word long. Except on
1866 the R4000 with the FR bit set, the floating point uses register
1867 pairs, with the second register not being allocable. */
1869 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1871 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1872 MODE. In 32 bit mode, require that DImode and DFmode be in even
1873 registers. For DImode, this makes some of the insns easier to
1874 write, since you don't have to worry about a DImode value in
1875 registers 3 & 4, producing a result in 4 & 5.
1877 To make the code simpler HARD_REGNO_MODE_OK now just references an
1878 array built in override_options. Because machmodes.h is not yet
1879 included before this file is processed, the MODE bound can't be
1882 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1884 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1885 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1887 /* Value is 1 if it is a good idea to tie two pseudo registers
1888 when one has mode MODE1 and one has mode MODE2.
1889 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1890 for any hard reg, then this must be 0 for correct output. */
1891 #define MODES_TIEABLE_P(MODE1, MODE2) \
1892 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1893 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1894 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1895 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1897 /* MIPS pc is not overloaded on a register. */
1898 /* #define PC_REGNUM xx */
1900 /* Register to use for pushing function arguments. */
1901 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1903 /* Offset from the stack pointer to the first available location. Use
1904 the default value zero. */
1905 /* #define STACK_POINTER_OFFSET 0 */
1907 /* Base register for access to local variables of the function. We
1908 pretend that the frame pointer is $1, and then eliminate it to
1909 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1910 a fixed register, and will not be used for anything else. */
1911 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1913 /* Temporary scratch register for use by the assembler. */
1914 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1916 /* $30 is not available on the mips16, so we use $17 as the frame
1918 #define HARD_FRAME_POINTER_REGNUM \
1919 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1921 /* Value should be nonzero if functions must have frame pointers.
1922 Zero means the frame pointer need not be set up (and parms
1923 may be accessed via the stack pointer) in functions that seem suitable.
1924 This is computed in `reload', in reload1.c. */
1925 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1927 /* Base register for access to arguments of the function. */
1928 #define ARG_POINTER_REGNUM GP_REG_FIRST
1930 /* Fake register that holds the address on the stack of the
1931 current function's return address. */
1932 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1934 /* Register in which static-chain is passed to a function. */
1935 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1937 /* If the structure value address is passed in a register, then
1938 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1939 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1941 /* If the structure value address is not passed in a register, define
1942 `STRUCT_VALUE' as an expression returning an RTX for the place
1943 where the address is passed. If it returns 0, the address is
1944 passed as an "invisible" first argument. */
1945 #define STRUCT_VALUE 0
1947 /* Mips registers used in prologue/epilogue code when the stack frame
1948 is larger than 32K bytes. These registers must come from the
1949 scratch register set, and not used for passing and returning
1950 arguments and any other information used in the calling sequence
1951 (such as pic). Must start at 12, since t0/t3 are parameter passing
1952 registers in the 64 bit ABI. */
1954 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1955 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1957 /* Define this macro if it is as good or better to call a constant
1958 function address than to call an address kept in a register. */
1959 #define NO_FUNCTION_CSE 1
1961 /* Define this macro if it is as good or better for a function to
1962 call itself with an explicit address than to call an address
1963 kept in a register. */
1964 #define NO_RECURSIVE_FUNCTION_CSE 1
1966 /* The register number of the register used to address a table of
1967 static data addresses in memory. In some cases this register is
1968 defined by a processor's "application binary interface" (ABI).
1969 When this macro is defined, RTL is generated for this register
1970 once, as with the stack pointer and frame pointer registers. If
1971 this macro is not defined, it is up to the machine-dependent
1972 files to allocate such a register (if necessary). */
1973 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1975 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1977 /* Define the classes of registers for register constraints in the
1978 machine description. Also define ranges of constants.
1980 One of the classes must always be named ALL_REGS and include all hard regs.
1981 If there is more than one class, another class must be named NO_REGS
1982 and contain no registers.
1984 The name GENERAL_REGS must be the name of a class (or an alias for
1985 another name such as ALL_REGS). This is the class of registers
1986 that is allowed by "g" or "r" in a register constraint.
1987 Also, registers outside this class are allocated only when
1988 instructions express preferences for them.
1990 The classes must be numbered in nondecreasing order; that is,
1991 a larger-numbered class must never be contained completely
1992 in a smaller-numbered class.
1994 For any two classes, it is very desirable that there be another
1995 class that represents their union. */
1999 NO_REGS, /* no registers in set */
2000 M16_NA_REGS, /* mips16 regs not used to pass args */
2001 M16_REGS, /* mips16 directly accessible registers */
2002 T_REG, /* mips16 T register ($24) */
2003 M16_T_REGS, /* mips16 registers plus T register */
2004 GR_REGS, /* integer registers */
2005 FP_REGS, /* floating point registers */
2006 HI_REG, /* hi register */
2007 LO_REG, /* lo register */
2008 HILO_REG, /* hilo register pair for 64 bit mode mult */
2009 MD_REGS, /* multiply/divide registers (hi/lo) */
2010 COP0_REGS, /* generic coprocessor classes */
2013 HI_AND_GR_REGS, /* union classes */
2021 ALL_COP_AND_GR_REGS,
2022 ST_REGS, /* status registers (fp status) */
2023 ALL_REGS, /* all registers */
2024 LIM_REG_CLASSES /* max value + 1 */
2027 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2029 #define GENERAL_REGS GR_REGS
2031 /* An initializer containing the names of the register classes as C
2032 string constants. These names are used in writing some of the
2035 #define REG_CLASS_NAMES \
2048 /* coprocessor registers */ \
2054 "HILO_AND_GR_REGS", \
2056 "COP0_AND_GR_REGS", \
2057 "COP2_AND_GR_REGS", \
2058 "COP3_AND_GR_REGS", \
2060 "ALL_COP_AND_GR_REGS", \
2065 /* An initializer containing the contents of the register classes,
2066 as integers which are bit masks. The Nth integer specifies the
2067 contents of class N. The way the integer MASK is interpreted is
2068 that register R is in the class if `MASK & (1 << R)' is 1.
2070 When the machine has more than 32 registers, an integer does not
2071 suffice. Then the integers are replaced by sub-initializers,
2072 braced groupings containing several integers. Each
2073 sub-initializer must be suitable as an initializer for the type
2074 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2076 #define REG_CLASS_CONTENTS \
2078 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2079 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2080 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2081 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2082 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2083 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2084 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2085 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2086 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2087 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2088 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2089 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2090 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2091 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2092 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2093 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2094 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2095 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2096 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2097 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2098 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2099 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2100 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2101 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2102 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2106 /* A C expression whose value is a register class containing hard
2107 register REGNO. In general there is more that one such class;
2108 choose a class which is "minimal", meaning that no smaller class
2109 also contains the register. */
2111 extern const enum reg_class mips_regno_to_class[];
2113 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2115 /* A macro whose definition is the name of the class to which a
2116 valid base register must belong. A base register is one used in
2117 an address which is the register value plus a displacement. */
2119 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2121 /* A macro whose definition is the name of the class to which a
2122 valid index register must belong. An index register is one used
2123 in an address where its value is either multiplied by a scale
2124 factor or added to another register (as well as added to a
2127 #define INDEX_REG_CLASS NO_REGS
2129 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2130 registers explicitly used in the rtl to be used as spill registers
2131 but prevents the compiler from extending the lifetime of these
2134 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2136 /* This macro is used later on in the file. */
2137 #define GR_REG_CLASS_P(CLASS) \
2138 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2139 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2141 /* This macro is also used later on in the file. */
2142 #define COP_REG_CLASS_P(CLASS) \
2143 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2145 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2146 is the default value (allocate the registers in numeric order). We
2147 define it just so that we can override it for the mips16 target in
2148 ORDER_REGS_FOR_LOCAL_ALLOC. */
2150 #define REG_ALLOC_ORDER \
2151 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2152 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2153 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2154 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2155 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2156 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2157 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2158 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2159 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2160 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2161 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2164 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2165 to be rearranged based on a particular function. On the mips16, we
2166 want to allocate $24 (T_REG) before other registers for
2167 instructions for which it is possible. */
2169 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2171 /* REGISTER AND CONSTANT CLASSES */
2173 /* Get reg_class from a letter such as appears in the machine
2176 DEFINED REGISTER CLASSES:
2178 'd' General (aka integer) registers
2179 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2180 'y' General registers (in both mips16 and non mips16 mode)
2181 'e' mips16 non argument registers (M16_NA_REGS)
2182 't' mips16 temporary register ($24)
2183 'f' Floating point registers
2186 'x' Multiply/divide registers
2188 'z' FP Status register
2192 'b' All registers */
2194 extern enum reg_class mips_char_to_class[256];
2196 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2198 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2199 string can be used to stand for particular ranges of immediate
2200 operands. This macro defines what the ranges are. C is the
2201 letter, and VALUE is a constant value. Return 1 if VALUE is
2202 in the range specified by C. */
2206 `I' is used for the range of constants an arithmetic insn can
2207 actually contain (16 bits signed integers).
2209 `J' is used for the range which is just zero (ie, $r0).
2211 `K' is used for the range of constants a logical insn can actually
2212 contain (16 bit zero-extended integers).
2214 `L' is used for the range of constants that be loaded with lui
2215 (ie, the bottom 16 bits are zero).
2217 `M' is used for the range of constants that take two words to load
2218 (ie, not matched by `I', `K', and `L').
2220 `N' is used for negative 16 bit constants other than -65536.
2222 `O' is a 15 bit signed integer.
2224 `P' is used for positive 16 bit constants. */
2226 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2227 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2229 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2230 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2231 : (C) == 'J' ? ((VALUE) == 0) \
2232 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2233 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2234 && (((VALUE) & ~2147483647) == 0 \
2235 || ((VALUE) & ~2147483647) == ~2147483647)) \
2236 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2237 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2238 && (((VALUE) & 0x0000ffff) != 0 \
2239 || (((VALUE) & ~2147483647) != 0 \
2240 && ((VALUE) & ~2147483647) != ~2147483647))) \
2241 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2242 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2243 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2246 /* Similar, but for floating constants, and defining letters G and H.
2247 Here VALUE is the CONST_DOUBLE rtx itself. */
2251 'G' : Floating point 0 */
2253 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2255 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2257 /* Letters in the range `Q' through `U' may be defined in a
2258 machine-dependent fashion to stand for arbitrary operand types.
2259 The machine description macro `EXTRA_CONSTRAINT' is passed the
2260 operand as its first argument and the constraint letter as its
2263 `Q' is for mips16 GP relative constants
2264 `R' is for memory references which take 1 word for the instruction.
2265 `T' is for memory addresses that can be used to load two words. */
2267 #define EXTRA_CONSTRAINT(OP,CODE) \
2268 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2269 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2270 && mips16_gp_offset_p (OP)) \
2271 : (GET_CODE (OP) != MEM) ? FALSE \
2272 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2275 /* Given an rtx X being reloaded into a reg required to be
2276 in class CLASS, return the class of reg to actually use.
2277 In general this is just CLASS; but on some machines
2278 in some cases it is preferable to use a more restrictive class. */
2280 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2281 ((CLASS) != ALL_REGS \
2282 ? (! TARGET_MIPS16 \
2284 : ((CLASS) != GR_REGS \
2287 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2288 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2289 ? (TARGET_SOFT_FLOAT \
2290 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2292 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2293 || GET_MODE (X) == VOIDmode) \
2294 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2297 /* Certain machines have the property that some registers cannot be
2298 copied to some other registers without using memory. Define this
2299 macro on those machines to be a C expression that is nonzero if
2300 objects of mode MODE in registers of CLASS1 can only be copied to
2301 registers of class CLASS2 by storing a register of CLASS1 into
2302 memory and loading that memory location into a register of CLASS2.
2304 Do not define this macro if its value would always be zero. */
2306 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2307 ((!TARGET_DEBUG_H_MODE \
2308 && GET_MODE_CLASS (MODE) == MODE_INT \
2309 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2310 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2311 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2312 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2313 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2315 /* The HI and LO registers can only be reloaded via the general
2316 registers. Condition code registers can only be loaded to the
2317 general registers, and from the floating point registers. */
2319 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2320 mips_secondary_reload_class (CLASS, MODE, X, 1)
2321 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2322 mips_secondary_reload_class (CLASS, MODE, X, 0)
2324 /* Return the maximum number of consecutive registers
2325 needed to represent mode MODE in a register of class CLASS. */
2327 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2329 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \
2330 mips_cannot_change_mode_class (FROM, TO)
2332 /* Stack layout; function entry, exit and calling. */
2334 /* Define this if pushing a word on the stack
2335 makes the stack pointer a smaller address. */
2336 #define STACK_GROWS_DOWNWARD
2338 /* Define this if the nominal address of the stack frame
2339 is at the high-address end of the local variables;
2340 that is, each additional local variable allocated
2341 goes at a more negative offset in the frame. */
2342 /* #define FRAME_GROWS_DOWNWARD */
2344 /* Offset within stack frame to start allocating local variables at.
2345 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2346 first local allocated. Otherwise, it is the offset to the BEGINNING
2347 of the first local allocated. */
2348 #define STARTING_FRAME_OFFSET \
2349 (current_function_outgoing_args_size \
2350 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2352 /* Offset from the stack pointer register to an item dynamically
2353 allocated on the stack, e.g., by `alloca'.
2355 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2356 length of the outgoing arguments. The default is correct for most
2357 machines. See `function.c' for details.
2359 The MIPS ABI states that functions which dynamically allocate the
2360 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2361 we are trying to create a second frame pointer to the function, so
2362 allocate some stack space to make it happy.
2364 However, the linker currently complains about linking any code that
2365 dynamically allocates stack space, and there seems to be a bug in
2366 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2369 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2370 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2371 ? 4*UNITS_PER_WORD \
2372 : current_function_outgoing_args_size)
2375 /* The return address for the current frame is in r31 if this is a leaf
2376 function. Otherwise, it is on the stack. It is at a variable offset
2377 from sp/fp/ap, so we define a fake hard register rap which is a
2378 poiner to the return address on the stack. This always gets eliminated
2379 during reload to be either the frame pointer or the stack pointer plus
2382 /* ??? This definition fails for leaf functions. There is currently no
2383 general solution for this problem. */
2385 /* ??? There appears to be no way to get the return address of any previous
2386 frame except by disassembling instructions in the prologue/epilogue.
2387 So currently we support only the current frame. */
2389 #define RETURN_ADDR_RTX(count, frame) \
2391 ? (leaf_function_p () \
2392 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
2393 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
2394 RETURN_ADDRESS_POINTER_REGNUM))) \
2397 /* Since the mips16 ISA mode is encoded in the least-significant bit
2398 of the address, mask it off return addresses for purposes of
2399 finding exception handling regions. */
2401 #define MASK_RETURN_ADDR GEN_INT (-2)
2403 /* Similarly, don't use the least-significant bit to tell pointers to
2404 code from vtable index. */
2406 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2408 /* If defined, this macro specifies a table of register pairs used to
2409 eliminate unneeded registers that point into the stack frame. If
2410 it is not defined, the only elimination attempted by the compiler
2411 is to replace references to the frame pointer with references to
2414 The definition of this macro is a list of structure
2415 initializations, each of which specifies an original and
2416 replacement register.
2418 On some machines, the position of the argument pointer is not
2419 known until the compilation is completed. In such a case, a
2420 separate hard register must be used for the argument pointer.
2421 This register can be eliminated by replacing it with either the
2422 frame pointer or the argument pointer, depending on whether or not
2423 the frame pointer has been eliminated.
2425 In this case, you might specify:
2426 #define ELIMINABLE_REGS \
2427 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2428 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2429 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2431 Note that the elimination of the argument pointer with the stack
2432 pointer is specified first since that is the preferred elimination.
2434 The eliminations to $17 are only used on the mips16. See the
2435 definition of HARD_FRAME_POINTER_REGNUM. */
2437 #define ELIMINABLE_REGS \
2438 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2439 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2440 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2441 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2442 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2443 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2444 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2445 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2446 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2448 /* A C expression that returns nonzero if the compiler is allowed to
2449 try to replace register number FROM-REG with register number
2450 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2451 defined, and will usually be the constant 1, since most of the
2452 cases preventing register elimination are things that the compiler
2453 already knows about.
2455 When not in mips16 and mips64, we can always eliminate to the
2456 frame pointer. We can eliminate to the stack pointer unless
2457 a frame pointer is needed. In mips16 mode, we need a frame
2458 pointer for a large frame; otherwise, reload may be unable
2459 to compute the address of a local variable, since there is
2460 no way to add a large constant to the stack pointer
2461 without using a temporary register.
2463 In mips16, for some instructions (eg lwu), we can't eliminate the
2464 frame pointer for the stack pointer. These instructions are
2465 only generated in TARGET_64BIT mode.
2468 #define CAN_ELIMINATE(FROM, TO) \
2469 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
2470 && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
2471 || (TO) == HARD_FRAME_POINTER_REGNUM)) \
2472 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2473 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2474 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2475 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2476 && (! TARGET_MIPS16 \
2477 || compute_frame_size (get_frame_size ()) < 32768)))))
2479 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2480 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2482 /* If we generate an insn to push BYTES bytes,
2483 this says how many the stack pointer really advances by.
2484 On the VAX, sp@- in a byte insn really pushes a word. */
2486 /* #define PUSH_ROUNDING(BYTES) 0 */
2488 /* If defined, the maximum amount of space required for outgoing
2489 arguments will be computed and placed into the variable
2490 `current_function_outgoing_args_size'. No space will be pushed
2491 onto the stack for each call; instead, the function prologue
2492 should increase the stack frame size by this amount.
2494 It is not proper to define both `PUSH_ROUNDING' and
2495 `ACCUMULATE_OUTGOING_ARGS'. */
2496 #define ACCUMULATE_OUTGOING_ARGS 1
2498 /* Offset from the argument pointer register to the first argument's
2499 address. On some machines it may depend on the data type of the
2502 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2503 the first argument's address.
2505 On the MIPS, we must skip the first argument position if we are
2506 returning a structure or a union, to account for its address being
2507 passed in $4. However, at the current time, this produces a compiler
2508 that can't bootstrap, so comment it out for now. */
2511 #define FIRST_PARM_OFFSET(FNDECL) \
2513 && TREE_TYPE (FNDECL) != 0 \
2514 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2515 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2516 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2520 #define FIRST_PARM_OFFSET(FNDECL) 0
2523 /* When a parameter is passed in a register, stack space is still
2524 allocated for it. For the MIPS, stack space must be allocated, cf
2525 Asm Lang Prog Guide page 7-8.
2527 BEWARE that some space is also allocated for non existing arguments
2528 in register. In case an argument list is of form GF used registers
2529 are a0 (a2,a3), but we should push over a1... */
2531 #define REG_PARM_STACK_SPACE(FNDECL) \
2532 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2533 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2536 /* Define this if it is the responsibility of the caller to
2537 allocate the area reserved for arguments passed in registers.
2538 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2539 of this macro is to determine whether the space is included in
2540 `current_function_outgoing_args_size'. */
2541 #define OUTGOING_REG_PARM_STACK_SPACE
2543 #define STACK_BOUNDARY \
2544 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2547 /* Make sure 4 words are always allocated on the stack. */
2549 #ifndef STACK_ARGS_ADJUST
2550 #define STACK_ARGS_ADJUST(SIZE) \
2552 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2553 SIZE.constant = 4 * UNITS_PER_WORD; \
2558 /* A C expression that should indicate the number of bytes of its
2559 own arguments that a function pops on returning, or 0
2560 if the function pops no arguments and the caller must therefore
2561 pop them all after the function returns.
2563 FUNDECL is the declaration node of the function (as a tree).
2565 FUNTYPE is a C variable whose value is a tree node that
2566 describes the function in question. Normally it is a node of
2567 type `FUNCTION_TYPE' that describes the data type of the function.
2568 From this it is possible to obtain the data types of the value
2569 and arguments (if known).
2571 When a call to a library function is being considered, FUNTYPE
2572 will contain an identifier node for the library function. Thus,
2573 if you need to distinguish among various library functions, you
2574 can do so by their names. Note that "library function" in this
2575 context means a function used to perform arithmetic, whose name
2576 is known specially in the compiler and was not mentioned in the
2577 C code being compiled.
2579 STACK-SIZE is the number of bytes of arguments passed on the
2580 stack. If a variable number of bytes is passed, it is zero, and
2581 argument popping will always be the responsibility of the
2582 calling function. */
2584 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2587 /* Symbolic macros for the registers used to return integer and floating
2590 #define GP_RETURN (GP_REG_FIRST + 2)
2591 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2593 #define MAX_ARGS_IN_REGISTERS \
2594 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2596 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2598 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2600 /* Symbolic macros for the first/last argument registers. */
2602 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2603 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2604 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2605 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2607 /* Define how to find the value returned by a library function
2608 assuming the value has mode MODE. Because we define
2609 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2610 PROMOTE_MODE does. */
2612 #define LIBCALL_VALUE(MODE) \
2613 mips_function_value (NULL_TREE, NULL, (MODE))
2615 /* Define how to find the value returned by a function.
2616 VALTYPE is the data type of the value (as a tree).
2617 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2618 otherwise, FUNC is 0. */
2620 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2621 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2623 /* 1 if N is a possible register number for a function value.
2624 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2625 Currently, R2 and F0 are only implemented here (C has no complex type) */
2627 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2629 /* 1 if N is a possible register number for function argument passing.
2630 We have no FP argument registers when soft-float. When FP registers
2631 are 32 bits, we can't directly reference the odd numbered ones. */
2633 #define FUNCTION_ARG_REGNO_P(N) \
2634 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2635 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2636 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2639 /* A C expression which can inhibit the returning of certain function
2640 values in registers, based on the type of value. A nonzero value says
2641 to return the function value in memory, just as large structures are
2642 always returned. Here TYPE will be a C expression of type
2643 `tree', representing the data type of the value.
2645 Note that values of mode `BLKmode' must be explicitly
2646 handled by this macro. Also, the option `-fpcc-struct-return'
2647 takes effect regardless of this macro. On most systems, it is
2648 possible to leave the macro undefined; this causes a default
2649 definition to be used, whose value is the constant 1 for BLKmode
2650 values, and 0 otherwise.
2652 GCC normally converts 1 byte structures into chars, 2 byte
2653 structs into shorts, and 4 byte structs into ints, and returns
2654 them this way. Defining the following macro overrides this,
2655 to give us MIPS cc compatibility. */
2657 #define RETURN_IN_MEMORY(TYPE) \
2658 mips_return_in_memory (TYPE)
2660 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2661 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2664 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2666 /* Define a data type for recording info about an argument list
2667 during the scan of that argument list. This data type should
2668 hold all necessary information about the function itself
2669 and about the args processed so far, enough to enable macros
2670 such as FUNCTION_ARG to determine where the next arg should go.
2672 This structure has to cope with two different argument allocation
2673 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2674 first N words go in registers and the rest go on the stack. If I < N,
2675 the Ith word might go in Ith integer argument register or the
2676 Ith floating-point one. In some cases, it has to go in both (see
2677 function_arg). For these ABIs, we only need to remember the number
2678 of words passed so far.
2680 The EABI instead allocates the integer and floating-point arguments
2681 separately. The first N words of FP arguments go in FP registers,
2682 the rest go on the stack. Likewise, the first N words of the other
2683 arguments go in integer registers, and the rest go on the stack. We
2684 need to maintain three counts: the number of integer registers used,
2685 the number of floating-point registers used, and the number of words
2686 passed on the stack.
2688 We could keep separate information for the two ABIs (a word count for
2689 the standard ABIs, and three separate counts for the EABI). But it
2690 seems simpler to view the standard ABIs as forms of EABI that do not
2691 allocate floating-point registers.
2693 So for the standard ABIs, the first N words are allocated to integer
2694 registers, and function_arg decides on an argument-by-argument basis
2695 whether that argument should really go in an integer register, or in
2696 a floating-point one. */
2698 typedef struct mips_args {
2699 /* Always true for varargs functions. Otherwise true if at least
2700 one argument has been passed in an integer register. */
2703 /* The number of arguments seen so far. */
2704 unsigned int arg_number;
2706 /* For EABI, the number of integer registers used so far. For other
2707 ABIs, the number of words passed in registers (whether integer
2708 or floating-point). */
2709 unsigned int num_gprs;
2711 /* For EABI, the number of floating-point registers used so far. */
2712 unsigned int num_fprs;
2714 /* The number of words passed on the stack. */
2715 unsigned int stack_words;
2717 /* On the mips16, we need to keep track of which floating point
2718 arguments were passed in general registers, but would have been
2719 passed in the FP regs if this were a 32 bit function, so that we
2720 can move them to the FP regs if we wind up calling a 32 bit
2721 function. We record this information in fp_code, encoded in base
2722 four. A zero digit means no floating point argument, a one digit
2723 means an SFmode argument, and a two digit means a DFmode argument,
2724 and a three digit is not used. The low order digit is the first
2725 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2726 an SFmode argument. ??? A more sophisticated approach will be
2727 needed if MIPS_ABI != ABI_32. */
2730 /* True if the function has a prototype. */
2733 /* When a structure does not take up a full register, the argument
2734 should sometimes be shifted left so that it occupies the high part
2735 of the register. These two fields describe an array of ashl
2736 patterns for doing this. See function_arg_advance, which creates
2737 the shift patterns, and function_arg, which returns them when given
2738 a VOIDmode argument. */
2739 unsigned int num_adjusts;
2740 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2743 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2744 for a call to a function whose data type is FNTYPE.
2745 For a library call, FNTYPE is 0.
2749 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2750 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2752 /* Update the data in CUM to advance over an argument
2753 of mode MODE and data type TYPE.
2754 (TYPE is null for libcalls where that information may not be available.) */
2756 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2757 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2759 /* Determine where to put an argument to a function.
2760 Value is zero to push the argument on the stack,
2761 or a hard register in which to store the argument.
2763 MODE is the argument's machine mode.
2764 TYPE is the data type of the argument (as a tree).
2765 This is null for libcalls where that information may
2767 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2768 the preceding args and about the function being called.
2769 NAMED is nonzero if this argument is a named parameter
2770 (otherwise it is an extra parameter matching an ellipsis). */
2772 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2773 function_arg( &CUM, MODE, TYPE, NAMED)
2775 /* For an arg passed partly in registers and partly in memory,
2776 this is the number of registers used.
2777 For args passed entirely in registers or entirely in memory, zero. */
2779 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2780 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2782 /* If defined, a C expression that gives the alignment boundary, in
2783 bits, of an argument with the specified mode and type. If it is
2784 not defined, `PARM_BOUNDARY' is used for all arguments. */
2786 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2788 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2790 : TYPE_ALIGN(TYPE)) \
2791 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2793 : GET_MODE_ALIGNMENT(MODE)))
2795 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2796 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2798 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2799 (! BYTES_BIG_ENDIAN \
2801 : (((MODE) == BLKmode \
2802 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2803 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2804 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2805 && (mips_abi == ABI_32 \
2806 || mips_abi == ABI_O64 \
2807 || mips_abi == ABI_EABI \
2808 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2809 ? downward : upward))
2811 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2812 (mips_abi == ABI_EABI && (NAMED) \
2813 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2815 /* Modified version of the macro in expr.h. */
2816 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2818 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2819 || TREE_ADDRESSABLE (TYPE) \
2820 || ((MODE) == BLKmode \
2821 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2822 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2823 && 0 == (int_size_in_bytes (TYPE) \
2824 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2825 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2826 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2828 /* True if using EABI and varargs can be passed in floating-point
2829 registers. Under these conditions, we need a more complex form
2830 of va_list, which tracks GPR, FPR and stack arguments separately. */
2831 #define EABI_FLOAT_VARARGS_P \
2832 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2835 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2837 #define MUST_SAVE_REGISTER(regno) \
2838 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2839 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2840 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2842 /* Treat LOC as a byte offset from the stack pointer and round it up
2843 to the next fully-aligned offset. */
2844 #define MIPS_STACK_ALIGN(LOC) \
2845 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2846 ? ((LOC) + 7) & ~7 \
2847 : ((LOC) + 15) & ~15)
2850 /* Define the `__builtin_va_list' type for the ABI. */
2851 #define BUILD_VA_LIST_TYPE(VALIST) \
2852 (VALIST) = mips_build_va_list ()
2854 /* Implement `va_start' for varargs and stdarg. */
2855 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2856 mips_va_start (valist, nextarg)
2858 /* Implement `va_arg'. */
2859 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2860 mips_va_arg (valist, type)
2862 /* Output assembler code to FILE to increment profiler label # LABELNO
2863 for profiling a function entry. */
2865 #define FUNCTION_PROFILER(FILE, LABELNO) \
2867 if (TARGET_MIPS16) \
2868 sorry ("mips16 function profiling"); \
2869 fprintf (FILE, "\t.set\tnoat\n"); \
2870 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2871 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2873 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2874 TARGET_64BIT ? "dsubu" : "subu", \
2875 reg_names[STACK_POINTER_REGNUM], \
2876 reg_names[STACK_POINTER_REGNUM], \
2877 Pmode == DImode ? 16 : 8); \
2878 fprintf (FILE, "\tjal\t_mcount\n"); \
2879 fprintf (FILE, "\t.set\tat\n"); \
2882 /* Define this macro if the code for function profiling should come
2883 before the function prologue. Normally, the profiling code comes
2886 /* #define PROFILE_BEFORE_PROLOGUE */
2888 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2889 the stack pointer does not matter. The value is tested only in
2890 functions that have frame pointers.
2891 No definition is equivalent to always zero. */
2893 #define EXIT_IGNORE_STACK 1
2896 /* A C statement to output, on the stream FILE, assembler code for a
2897 block of data that contains the constant parts of a trampoline.
2898 This code should not include a label--the label is taken care of
2901 #define TRAMPOLINE_TEMPLATE(STREAM) \
2903 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2904 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2905 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2906 if (Pmode == DImode) \
2908 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2909 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2913 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2914 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2916 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2917 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2918 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2919 if (Pmode == DImode) \
2921 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2922 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2926 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2927 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2931 /* A C expression for the size in bytes of the trampoline, as an
2934 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2936 /* Alignment required for trampolines, in bits. */
2938 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2940 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2941 program and data caches. */
2943 #ifndef CACHE_FLUSH_FUNC
2944 #define CACHE_FLUSH_FUNC "_flush_cache"
2947 /* A C statement to initialize the variable parts of a trampoline.
2948 ADDR is an RTX for the address of the trampoline; FNADDR is an
2949 RTX for the address of the nested function; STATIC_CHAIN is an
2950 RTX for the static chain value that should be passed to the
2951 function when it is called. */
2953 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2956 if (Pmode == DImode) \
2958 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2959 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2963 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2964 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2967 /* Flush both caches. We need to flush the data cache in case \
2968 the system has a write-back cache. */ \
2969 /* ??? Should check the return value for errors. */ \
2970 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2971 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2972 0, VOIDmode, 3, addr, Pmode, \
2973 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2974 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2977 /* Addressing modes, and classification of registers for them. */
2979 /* These assume that REGNO is a hard or pseudo reg number.
2980 They give nonzero only if REGNO is a hard reg of the suitable class
2981 or a pseudo reg currently allocated to a suitable hard reg.
2982 These definitions are NOT overridden anywhere. */
2984 #define BASE_REG_P(regno, mode) \
2986 ? (M16_REG_P (regno) \
2987 || (regno) == FRAME_POINTER_REGNUM \
2988 || (regno) == ARG_POINTER_REGNUM \
2989 || ((regno) == STACK_POINTER_REGNUM \
2990 && (GET_MODE_SIZE (mode) == 4 \
2991 || GET_MODE_SIZE (mode) == 8))) \
2994 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2995 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2998 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2999 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3001 #define REGNO_OK_FOR_INDEX_P(regno) 0
3002 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3003 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3005 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3006 and check its validity for a certain class.
3007 We have two alternate definitions for each of them.
3008 The usual definition accepts all pseudo regs; the other rejects them all.
3009 The symbol REG_OK_STRICT causes the latter definition to be used.
3011 Most source files want to accept pseudo regs in the hope that
3012 they will get allocated to the class that the insn wants them to be in.
3013 Some source files that are used after register allocation
3014 need to be strict. */
3016 #ifndef REG_OK_STRICT
3017 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3018 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3020 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3021 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3024 #define REG_OK_FOR_INDEX_P(X) 0
3027 /* Maximum number of registers that can appear in a valid memory address. */
3029 #define MAX_REGS_PER_ADDRESS 1
3031 /* A C compound statement with a conditional `goto LABEL;' executed
3032 if X (an RTX) is a legitimate memory address on the target
3033 machine for a memory operand of mode MODE. */
3036 #define GO_PRINTF(x) fprintf(stderr, (x))
3037 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3038 #define GO_DEBUG_RTX(x) debug_rtx(x)
3041 #define GO_PRINTF(x)
3042 #define GO_PRINTF2(x,y)
3043 #define GO_DEBUG_RTX(x)
3046 #ifdef REG_OK_STRICT
3047 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3049 if (mips_legitimate_address_p (MODE, X, 1)) \
3053 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3055 if (mips_legitimate_address_p (MODE, X, 0)) \
3060 /* A C expression that is 1 if the RTX X is a constant which is a
3061 valid address. This is defined to be the same as `CONSTANT_P (X)',
3062 but rejecting CONST_DOUBLE. */
3063 /* When pic, we must reject addresses of the form symbol+large int.
3064 This is because an instruction `sw $4,s+70000' needs to be converted
3065 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3066 assembler would use $at as a temp to load in the large offset. In this
3067 case $at is already in use. We convert such problem addresses to
3068 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3069 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them
3070 when !TARGET_GAS. */
3071 /* We should be rejecting everything but const addresses. */
3072 #define CONSTANT_ADDRESS_P(X) \
3073 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3074 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3075 || (GET_CODE (X) == CONST \
3076 && ! (flag_pic && pic_address_needs_scratch (X)) \
3078 && (mips_abi != ABI_N32 \
3079 && mips_abi != ABI_64)))
3082 /* Define this, so that when PIC, reload won't try to reload invalid
3083 addresses which require two reload registers. */
3085 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3087 /* Nonzero if the constant value X is a legitimate general operand.
3088 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3090 At present, GAS doesn't understand li.[sd], so don't allow it
3091 to be generated at present. Also, the MIPS assembler does not
3092 grok li.d Infinity. */
3094 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3095 Note that the Irix 6 assembler problem may already be fixed.
3096 Note also that the GET_CODE (X) == CONST test catches the mips16
3097 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3098 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3099 ABI_64 to work together, we'll need to fix this. */
3100 #define LEGITIMATE_CONSTANT_P(X) \
3101 ((GET_CODE (X) != CONST_DOUBLE \
3102 || mips_const_double_ok (X, GET_MODE (X))) \
3103 && ! (GET_CODE (X) == CONST \
3105 && (mips_abi == ABI_N32 \
3106 || mips_abi == ABI_64)) \
3107 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3109 /* A C compound statement that attempts to replace X with a valid
3110 memory address for an operand of mode MODE. WIN will be a C
3111 statement label elsewhere in the code; the macro definition may
3114 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3116 to avoid further processing if the address has become legitimate.
3118 X will always be the result of a call to `break_out_memory_refs',
3119 and OLDX will be the operand that was given to that function to
3122 The code generated by this macro should not alter the
3123 substructure of X. If it transforms X into a more legitimate
3124 form, it should assign X (which will always be a C variable) a
3127 It is not necessary for this macro to come up with a legitimate
3128 address. The compiler has standard ways of doing so in all
3129 cases. In fact, it is safe for this macro to do nothing. But
3130 often a machine-dependent strategy can generate better code.
3132 For the MIPS, transform:
3134 memory(X + <large int>)
3138 Y = <large int> & ~0x7fff;
3140 memory (Z + (<large int> & 0x7fff));
3142 This is for CSE to find several similar references, and only use one Z.
3144 When PIC, convert addresses of the form memory (symbol+large int) to
3145 memory (reg+large int). */
3148 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3150 register rtx xinsn = (X); \
3152 if (TARGET_DEBUG_B_MODE) \
3154 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3155 GO_DEBUG_RTX (xinsn); \
3158 if (mips_split_addresses && mips_check_split (X, MODE)) \
3160 /* ??? Is this ever executed? */ \
3161 X = gen_rtx_LO_SUM (Pmode, \
3162 copy_to_mode_reg (Pmode, \
3163 gen_rtx (HIGH, Pmode, X)), \
3168 if (GET_CODE (xinsn) == CONST \
3169 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3170 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3172 && (mips_abi == ABI_N32 \
3173 || mips_abi == ABI_64)))) \
3175 rtx ptr_reg = gen_reg_rtx (Pmode); \
3176 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3178 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3180 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3181 if (SMALL_INT (constant)) \
3183 /* Otherwise we fall through so the code below will fix the \
3188 if (GET_CODE (xinsn) == PLUS) \
3190 register rtx xplus0 = XEXP (xinsn, 0); \
3191 register rtx xplus1 = XEXP (xinsn, 1); \
3192 register enum rtx_code code0 = GET_CODE (xplus0); \
3193 register enum rtx_code code1 = GET_CODE (xplus1); \
3195 if (code0 != REG && code1 == REG) \
3197 xplus0 = XEXP (xinsn, 1); \
3198 xplus1 = XEXP (xinsn, 0); \
3199 code0 = GET_CODE (xplus0); \
3200 code1 = GET_CODE (xplus1); \
3203 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3204 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3206 rtx int_reg = gen_reg_rtx (Pmode); \
3207 rtx ptr_reg = gen_reg_rtx (Pmode); \
3209 emit_move_insn (int_reg, \
3210 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3212 emit_insn (gen_rtx_SET (VOIDmode, \
3214 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3216 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3221 if (TARGET_DEBUG_B_MODE) \
3222 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3226 /* A C statement or compound statement with a conditional `goto
3227 LABEL;' executed if memory address X (an RTX) can have different
3228 meanings depending on the machine mode of the memory reference it
3231 Autoincrement and autodecrement addresses typically have
3232 mode-dependent effects because the amount of the increment or
3233 decrement is the size of the operand being addressed. Some
3234 machines have other mode-dependent addresses. Many RISC machines
3235 have no mode-dependent addresses.
3237 You may assume that ADDR is a valid address for the machine. */
3239 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3241 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3242 'the start of the function that this code is output in'. */
3244 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3245 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3246 asm_fprintf ((FILE), "%U%s", \
3247 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3249 asm_fprintf ((FILE), "%U%s", (NAME))
3251 /* The mips16 wants the constant pool to be after the function,
3252 because the PC relative load instructions use unsigned offsets. */
3254 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3256 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3257 mips_string_length = 0;
3260 /* In mips16 mode, put most string constants after the function. */
3261 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3262 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3265 /* Specify the machine mode that this machine uses
3266 for the index in the tablejump instruction.
3267 ??? Using HImode in mips16 mode can cause overflow. However, the
3268 overflow is no more likely than the overflow in a branch
3269 instruction. Large functions can currently break in both ways. */
3270 #define CASE_VECTOR_MODE \
3271 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3273 /* Define as C expression which evaluates to nonzero if the tablejump
3274 instruction expects the table to contain offsets from the address of the
3276 Do not define this if the table should contain absolute addresses. */
3277 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3279 /* Define this as 1 if `char' should by default be signed; else as 0. */
3280 #ifndef DEFAULT_SIGNED_CHAR
3281 #define DEFAULT_SIGNED_CHAR 1
3284 /* Max number of bytes we can move from memory to memory
3285 in one reasonably fast instruction. */
3286 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3287 #define MAX_MOVE_MAX 8
3289 /* Define this macro as a C expression which is nonzero if
3290 accessing less than a word of memory (i.e. a `char' or a
3291 `short') is no faster than accessing a word of memory, i.e., if
3292 such access require more than one instruction or if there is no
3293 difference in cost between byte and (aligned) word loads.
3295 On RISC machines, it tends to generate better code to define
3296 this as 1, since it avoids making a QI or HI mode register. */
3297 #define SLOW_BYTE_ACCESS 1
3299 /* We assume that the store-condition-codes instructions store 0 for false
3300 and some other value for true. This is the value stored for true. */
3302 #define STORE_FLAG_VALUE 1
3304 /* Define this to be nonzero if shift instructions ignore all but the low-order
3306 #define SHIFT_COUNT_TRUNCATED 1
3308 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3309 is done just by pretending it is already truncated. */
3310 /* In 64 bit mode, 32 bit instructions require that register values be properly
3311 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3312 converts a value >32 bits to a value <32 bits. */
3313 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3314 Something needs to be done about this. Perhaps not use any 32 bit
3315 instructions? Perhaps use PROMOTE_MODE? */
3316 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3317 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3319 /* Specify the machine mode that pointers have.
3320 After generation of rtl, the compiler makes no further distinction
3321 between pointers and any other objects of this machine mode.
3323 For MIPS we make pointers are the smaller of longs and gp-registers. */
3326 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3329 /* A function address in a call instruction
3330 is a word address (for indexing purposes)
3331 so give the MEM rtx a words's mode. */
3333 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3336 /* A part of a C `switch' statement that describes the relative
3337 costs of constant RTL expressions. It must contain `case'
3338 labels for expression codes `const_int', `const', `symbol_ref',
3339 `label_ref' and `const_double'. Each case must ultimately reach
3340 a `return' statement to return the relative cost of the use of
3341 that kind of constant value in an expression. The cost may
3342 depend on the precise value of the constant, which is available
3343 for examination in X.
3345 CODE is the expression code--redundant, since it can be obtained
3346 with `GET_CODE (X)'. */
3348 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3350 if (! TARGET_MIPS16) \
3352 /* Always return 0, since we don't have different sized \
3353 instructions, hence different costs according to Richard \
3357 if ((OUTER_CODE) == SET) \
3359 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3361 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3362 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3363 return COSTS_N_INSNS (1); \
3365 return COSTS_N_INSNS (2); \
3367 /* A PLUS could be an address. We don't want to force an address \
3368 to use a register, so accept any signed 16 bit value without \
3370 if ((OUTER_CODE) == PLUS \
3371 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3373 /* A number between 1 and 8 inclusive is efficient for a shift. \
3374 Otherwise, we will need an extended instruction. */ \
3375 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3376 || (OUTER_CODE) == LSHIFTRT) \
3378 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3380 return COSTS_N_INSNS (1); \
3382 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3383 if ((OUTER_CODE) == XOR \
3384 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3386 /* We may be able to use slt or sltu for a comparison with a \
3387 signed 16 bit value. (The boundary conditions aren't quite \
3388 right, but this is just a heuristic anyhow.) */ \
3389 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3390 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3391 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3392 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3393 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3395 /* Equality comparisons with 0 are cheap. */ \
3396 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3397 && INTVAL (X) == 0) \
3400 /* Otherwise, work out the cost to load the value into a \
3402 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3403 return COSTS_N_INSNS (1); \
3404 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3405 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3406 return COSTS_N_INSNS (2); \
3408 return COSTS_N_INSNS (3); \
3411 return COSTS_N_INSNS (2); \
3415 rtx offset = const0_rtx; \
3416 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3418 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3420 /* Treat this like a signed 16 bit CONST_INT. */ \
3421 if ((OUTER_CODE) == PLUS) \
3423 else if ((OUTER_CODE) == SET) \
3424 return COSTS_N_INSNS (1); \
3426 return COSTS_N_INSNS (2); \
3429 if (GET_CODE (symref) == LABEL_REF) \
3430 return COSTS_N_INSNS (2); \
3432 if (GET_CODE (symref) != SYMBOL_REF) \
3433 return COSTS_N_INSNS (4); \
3435 /* let's be paranoid.... */ \
3436 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3437 return COSTS_N_INSNS (2); \
3439 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3443 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3445 case CONST_DOUBLE: \
3448 if (TARGET_MIPS16) \
3449 return COSTS_N_INSNS (4); \
3450 split_double (X, &high, &low); \
3451 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3452 || low == CONST0_RTX (GET_MODE (low))) \
3456 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3457 This can be used, for example, to indicate how costly a multiply
3458 instruction is. In writing this macro, you can use the construct
3459 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3461 This macro is optional; do not define it if the default cost
3462 assumptions are adequate for the target machine.
3464 If -mdebugd is used, change the multiply cost to 2, so multiply by
3465 a constant isn't converted to a series of shifts. This helps
3466 strength reduction, and also makes it easier to identify what the
3467 compiler is doing. */
3469 /* ??? Fix this to be right for the R8000. */
3470 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3473 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3474 if (simple_memory_operand (X, GET_MODE (X))) \
3475 return COSTS_N_INSNS (num_words); \
3477 return COSTS_N_INSNS (2*num_words); \
3481 return COSTS_N_INSNS (6); \
3484 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3489 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3490 return COSTS_N_INSNS (2); \
3497 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3498 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3504 enum machine_mode xmode = GET_MODE (X); \
3505 if (xmode == SFmode || xmode == DFmode) \
3506 return COSTS_N_INSNS (1); \
3508 return COSTS_N_INSNS (4); \
3514 enum machine_mode xmode = GET_MODE (X); \
3515 if (xmode == SFmode || xmode == DFmode) \
3519 return COSTS_N_INSNS (2); \
3520 else if (TUNE_MIPS6000) \
3521 return COSTS_N_INSNS (3); \
3523 return COSTS_N_INSNS (6); \
3526 if (xmode == DImode && !TARGET_64BIT) \
3527 return COSTS_N_INSNS (4); \
3533 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3540 enum machine_mode xmode = GET_MODE (X); \
3541 if (xmode == SFmode) \
3546 return COSTS_N_INSNS (4); \
3547 else if (TUNE_MIPS6000 \
3550 return COSTS_N_INSNS (5); \
3552 return COSTS_N_INSNS (7); \
3555 if (xmode == DFmode) \
3560 return COSTS_N_INSNS (5); \
3561 else if (TUNE_MIPS6000 \
3564 return COSTS_N_INSNS (6); \
3566 return COSTS_N_INSNS (8); \
3569 if (TUNE_MIPS3000) \
3570 return COSTS_N_INSNS (12); \
3571 else if (TUNE_MIPS3900) \
3572 return COSTS_N_INSNS (2); \
3573 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3574 return COSTS_N_INSNS ((xmode == DImode) ? 4 : 3); \
3575 else if (TUNE_MIPS6000) \
3576 return COSTS_N_INSNS (17); \
3577 else if (TUNE_MIPS5000) \
3578 return COSTS_N_INSNS (5); \
3580 return COSTS_N_INSNS (10); \
3586 enum machine_mode xmode = GET_MODE (X); \
3587 if (xmode == SFmode) \
3591 return COSTS_N_INSNS (12); \
3592 else if (TUNE_MIPS6000) \
3593 return COSTS_N_INSNS (15); \
3594 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3595 return COSTS_N_INSNS (30); \
3597 return COSTS_N_INSNS (23); \
3600 if (xmode == DFmode) \
3604 return COSTS_N_INSNS (19); \
3605 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3606 return COSTS_N_INSNS (59); \
3607 else if (TUNE_MIPS6000) \
3608 return COSTS_N_INSNS (16); \
3610 return COSTS_N_INSNS (36); \
3613 /* fall through */ \
3619 return COSTS_N_INSNS (35); \
3620 else if (TUNE_MIPS6000) \
3621 return COSTS_N_INSNS (38); \
3622 else if (TUNE_MIPS5000) \
3623 return COSTS_N_INSNS (36); \
3624 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3625 return COSTS_N_INSNS ((GET_MODE (X) == SImode) ? 42 : 74); \
3627 return COSTS_N_INSNS (69); \
3630 /* A sign extend from SImode to DImode in 64 bit mode is often \
3631 zero instructions, because the result can often be used \
3632 directly by another instruction; we'll call it one. */ \
3633 if (TARGET_64BIT && GET_MODE (X) == DImode \
3634 && GET_MODE (XEXP (X, 0)) == SImode) \
3635 return COSTS_N_INSNS (1); \
3637 return COSTS_N_INSNS (2); \
3640 if (TARGET_64BIT && GET_MODE (X) == DImode \
3641 && GET_MODE (XEXP (X, 0)) == SImode) \
3642 return COSTS_N_INSNS (2); \
3644 return COSTS_N_INSNS (1);
3646 /* An expression giving the cost of an addressing mode that
3647 contains ADDRESS. If not defined, the cost is computed from the
3648 form of the ADDRESS expression and the `CONST_COSTS' values.
3650 For most CISC machines, the default cost is a good approximation
3651 of the true cost of the addressing mode. However, on RISC
3652 machines, all instructions normally have the same length and
3653 execution time. Hence all addresses will have equal costs.
3655 In cases where more than one form of an address is known, the
3656 form with the lowest cost will be used. If multiple forms have
3657 the same, lowest, cost, the one that is the most complex will be
3660 For example, suppose an address that is equal to the sum of a
3661 register and a constant is used twice in the same basic block.
3662 When this macro is not defined, the address will be computed in
3663 a register and memory references will be indirect through that
3664 register. On machines where the cost of the addressing mode
3665 containing the sum is no higher than that of a simple indirect
3666 reference, this will produce an additional instruction and
3667 possibly require an additional register. Proper specification
3668 of this macro eliminates this overhead for such machines.
3670 Similar use of this macro is made in strength reduction of loops.
3672 ADDRESS need not be valid as an address. In such a case, the
3673 cost is not relevant and can be any value; invalid addresses
3674 need not be assigned a different cost.
3676 On machines where an address involving more than one register is
3677 as cheap as an address computation involving only one register,
3678 defining `ADDRESS_COST' to reflect this can cause two registers
3679 to be live over a region of code where only one would have been
3680 if `ADDRESS_COST' were not defined in that manner. This effect
3681 should be considered in the definition of this macro.
3682 Equivalent costs should probably only be given to addresses with
3683 different numbers of registers on machines with lots of registers.
3685 This macro will normally either not be defined or be defined as
3688 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3690 /* A C expression for the cost of moving data from a register in
3691 class FROM to one in class TO. The classes are expressed using
3692 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3693 the default; other values are interpreted relative to that.
3695 It is not required that the cost always equal 2 when FROM is the
3696 same as TO; on some machines it is expensive to move between
3697 registers if they are not general registers.
3699 If reload sees an insn consisting of a single `set' between two
3700 hard registers, and if `REGISTER_MOVE_COST' applied to their
3701 classes returns a value of 2, reload does not check to ensure
3702 that the constraints of the insn are met. Setting a cost of
3703 other than 2 will allow reload to verify that the constraints are
3704 met. You should do this if the `movM' pattern's constraints do
3705 not allow such copying. */
3707 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3708 mips_register_move_cost (MODE, FROM, TO)
3710 /* ??? Fix this to be right for the R8000. */
3711 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3712 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3713 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3715 /* Define if copies to/from condition code registers should be avoided.
3717 This is needed for the MIPS because reload_outcc is not complete;
3718 it needs to handle cases where the source is a general or another
3719 condition code register. */
3720 #define AVOID_CCMODE_COPIES
3722 /* A C expression for the cost of a branch instruction. A value of
3723 1 is the default; other values are interpreted relative to that. */
3725 /* ??? Fix this to be right for the R8000. */
3726 #define BRANCH_COST \
3728 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3731 /* If defined, modifies the length assigned to instruction INSN as a
3732 function of the context in which it is used. LENGTH is an lvalue
3733 that contains the initially computed length of the insn and should
3734 be updated with the correct length of the insn. */
3735 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3736 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3739 /* Optionally define this if you have added predicates to
3740 `MACHINE.c'. This macro is called within an initializer of an
3741 array of structures. The first field in the structure is the
3742 name of a predicate and the second field is an array of rtl
3743 codes. For each predicate, list all rtl codes that can be in
3744 expressions matched by the predicate. The list should have a
3745 trailing comma. Here is an example of two entries in the list
3746 for a typical RISC machine:
3748 #define PREDICATE_CODES \
3749 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3750 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3752 Defining this macro does not affect the generated code (however,
3753 incorrect definitions that omit an rtl code that may be matched
3754 by the predicate can cause the compiler to malfunction).
3755 Instead, it allows the table built by `genrecog' to be more
3756 compact and efficient, thus speeding up the compiler. The most
3757 important predicates to include in the list specified by this
3758 macro are thoses used in the most insn patterns. */
3760 #define PREDICATE_CODES \
3761 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3762 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3763 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3764 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3765 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3766 {"small_int", { CONST_INT }}, \
3767 {"large_int", { CONST_INT }}, \
3768 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3769 {"const_float_1_operand", { CONST_DOUBLE }}, \
3770 {"simple_memory_operand", { MEM, SUBREG }}, \
3771 {"equality_op", { EQ, NE }}, \
3772 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3774 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3775 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3776 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3777 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3778 SYMBOL_REF, LABEL_REF, SUBREG, \
3780 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3781 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3782 MEM, SIGN_EXTEND }}, \
3783 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3784 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3786 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3788 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3790 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3791 SYMBOL_REF, LABEL_REF, SUBREG, \
3792 REG, SIGN_EXTEND }}, \
3793 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3794 CONST_DOUBLE, CONST }}, \
3795 {"fcc_register_operand", { REG, SUBREG }}, \
3796 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3797 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3799 /* A list of predicates that do special things with modes, and so
3800 should not elicit warnings for VOIDmode match_operand. */
3802 #define SPECIAL_MODE_PREDICATES \
3803 "pc_or_label_operand",
3806 /* If defined, a C statement to be executed just prior to the
3807 output of assembler code for INSN, to modify the extracted
3808 operands so they will be output differently.
3810 Here the argument OPVEC is the vector containing the operands
3811 extracted from INSN, and NOPERANDS is the number of elements of
3812 the vector which contain meaningful data for this insn. The
3813 contents of this vector are what will be used to convert the
3814 insn template into assembler code, so you can change the
3815 assembler output by changing the contents of the vector.
3817 We use it to check if the current insn needs a nop in front of it
3818 because of load delays, and also to update the delay slot
3821 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3822 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3825 /* Control the assembler format that we output. */
3827 /* Output at beginning of assembler file.
3828 If we are optimizing to use the global pointer, create a temporary
3829 file to hold all of the text stuff, and write it out to the end.
3830 This is needed because the MIPS assembler is evidently one pass,
3831 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3832 declaration when the code is processed, it generates a two
3833 instruction sequence. */
3835 #undef ASM_FILE_START
3836 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3838 /* Output to assembler file text saying following lines
3839 may contain character constants, extra white space, comments, etc. */
3842 #define ASM_APP_ON " #APP\n"
3845 /* Output to assembler file text saying following lines
3846 no longer contain unusual constructs. */
3849 #define ASM_APP_OFF " #NO_APP\n"
3852 /* How to refer to registers in assembler output.
3853 This sequence is indexed by compiler's hard-register-number (see above).
3855 In order to support the two different conventions for register names,
3856 we use the name of a table set up in mips.c, which is overwritten
3857 if -mrnames is used. */
3859 #define REGISTER_NAMES \
3861 &mips_reg_names[ 0][0], \
3862 &mips_reg_names[ 1][0], \
3863 &mips_reg_names[ 2][0], \
3864 &mips_reg_names[ 3][0], \
3865 &mips_reg_names[ 4][0], \
3866 &mips_reg_names[ 5][0], \
3867 &mips_reg_names[ 6][0], \
3868 &mips_reg_names[ 7][0], \
3869 &mips_reg_names[ 8][0], \
3870 &mips_reg_names[ 9][0], \
3871 &mips_reg_names[10][0], \
3872 &mips_reg_names[11][0], \
3873 &mips_reg_names[12][0], \
3874 &mips_reg_names[13][0], \
3875 &mips_reg_names[14][0], \
3876 &mips_reg_names[15][0], \
3877 &mips_reg_names[16][0], \
3878 &mips_reg_names[17][0], \
3879 &mips_reg_names[18][0], \
3880 &mips_reg_names[19][0], \
3881 &mips_reg_names[20][0], \
3882 &mips_reg_names[21][0], \
3883 &mips_reg_names[22][0], \
3884 &mips_reg_names[23][0], \
3885 &mips_reg_names[24][0], \
3886 &mips_reg_names[25][0], \
3887 &mips_reg_names[26][0], \
3888 &mips_reg_names[27][0], \
3889 &mips_reg_names[28][0], \
3890 &mips_reg_names[29][0], \
3891 &mips_reg_names[30][0], \
3892 &mips_reg_names[31][0], \
3893 &mips_reg_names[32][0], \
3894 &mips_reg_names[33][0], \
3895 &mips_reg_names[34][0], \
3896 &mips_reg_names[35][0], \
3897 &mips_reg_names[36][0], \
3898 &mips_reg_names[37][0], \
3899 &mips_reg_names[38][0], \
3900 &mips_reg_names[39][0], \
3901 &mips_reg_names[40][0], \
3902 &mips_reg_names[41][0], \
3903 &mips_reg_names[42][0], \
3904 &mips_reg_names[43][0], \
3905 &mips_reg_names[44][0], \
3906 &mips_reg_names[45][0], \
3907 &mips_reg_names[46][0], \
3908 &mips_reg_names[47][0], \
3909 &mips_reg_names[48][0], \
3910 &mips_reg_names[49][0], \
3911 &mips_reg_names[50][0], \
3912 &mips_reg_names[51][0], \
3913 &mips_reg_names[52][0], \
3914 &mips_reg_names[53][0], \
3915 &mips_reg_names[54][0], \
3916 &mips_reg_names[55][0], \
3917 &mips_reg_names[56][0], \
3918 &mips_reg_names[57][0], \
3919 &mips_reg_names[58][0], \
3920 &mips_reg_names[59][0], \
3921 &mips_reg_names[60][0], \
3922 &mips_reg_names[61][0], \
3923 &mips_reg_names[62][0], \
3924 &mips_reg_names[63][0], \
3925 &mips_reg_names[64][0], \
3926 &mips_reg_names[65][0], \
3927 &mips_reg_names[66][0], \
3928 &mips_reg_names[67][0], \
3929 &mips_reg_names[68][0], \
3930 &mips_reg_names[69][0], \
3931 &mips_reg_names[70][0], \
3932 &mips_reg_names[71][0], \
3933 &mips_reg_names[72][0], \
3934 &mips_reg_names[73][0], \
3935 &mips_reg_names[74][0], \
3936 &mips_reg_names[75][0], \
3937 &mips_reg_names[76][0], \
3938 &mips_reg_names[77][0], \
3939 &mips_reg_names[78][0], \
3940 &mips_reg_names[79][0], \
3941 &mips_reg_names[80][0], \
3942 &mips_reg_names[81][0], \
3943 &mips_reg_names[82][0], \
3944 &mips_reg_names[83][0], \
3945 &mips_reg_names[84][0], \
3946 &mips_reg_names[85][0], \
3947 &mips_reg_names[86][0], \
3948 &mips_reg_names[87][0], \
3949 &mips_reg_names[88][0], \
3950 &mips_reg_names[89][0], \
3951 &mips_reg_names[90][0], \
3952 &mips_reg_names[91][0], \
3953 &mips_reg_names[92][0], \
3954 &mips_reg_names[93][0], \
3955 &mips_reg_names[94][0], \
3956 &mips_reg_names[95][0], \
3957 &mips_reg_names[96][0], \
3958 &mips_reg_names[97][0], \
3959 &mips_reg_names[98][0], \
3960 &mips_reg_names[99][0], \
3961 &mips_reg_names[100][0], \
3962 &mips_reg_names[101][0], \
3963 &mips_reg_names[102][0], \
3964 &mips_reg_names[103][0], \
3965 &mips_reg_names[104][0], \
3966 &mips_reg_names[105][0], \
3967 &mips_reg_names[106][0], \
3968 &mips_reg_names[107][0], \
3969 &mips_reg_names[108][0], \
3970 &mips_reg_names[109][0], \
3971 &mips_reg_names[110][0], \
3972 &mips_reg_names[111][0], \
3973 &mips_reg_names[112][0], \
3974 &mips_reg_names[113][0], \
3975 &mips_reg_names[114][0], \
3976 &mips_reg_names[115][0], \
3977 &mips_reg_names[116][0], \
3978 &mips_reg_names[117][0], \
3979 &mips_reg_names[118][0], \
3980 &mips_reg_names[119][0], \
3981 &mips_reg_names[120][0], \
3982 &mips_reg_names[121][0], \
3983 &mips_reg_names[122][0], \
3984 &mips_reg_names[123][0], \
3985 &mips_reg_names[124][0], \
3986 &mips_reg_names[125][0], \
3987 &mips_reg_names[126][0], \
3988 &mips_reg_names[127][0], \
3989 &mips_reg_names[128][0], \
3990 &mips_reg_names[129][0], \
3991 &mips_reg_names[130][0], \
3992 &mips_reg_names[131][0], \
3993 &mips_reg_names[132][0], \
3994 &mips_reg_names[133][0], \
3995 &mips_reg_names[134][0], \
3996 &mips_reg_names[135][0], \
3997 &mips_reg_names[136][0], \
3998 &mips_reg_names[137][0], \
3999 &mips_reg_names[138][0], \
4000 &mips_reg_names[139][0], \
4001 &mips_reg_names[140][0], \
4002 &mips_reg_names[141][0], \
4003 &mips_reg_names[142][0], \
4004 &mips_reg_names[143][0], \
4005 &mips_reg_names[144][0], \
4006 &mips_reg_names[145][0], \
4007 &mips_reg_names[146][0], \
4008 &mips_reg_names[147][0], \
4009 &mips_reg_names[148][0], \
4010 &mips_reg_names[149][0], \
4011 &mips_reg_names[150][0], \
4012 &mips_reg_names[151][0], \
4013 &mips_reg_names[152][0], \
4014 &mips_reg_names[153][0], \
4015 &mips_reg_names[154][0], \
4016 &mips_reg_names[155][0], \
4017 &mips_reg_names[156][0], \
4018 &mips_reg_names[157][0], \
4019 &mips_reg_names[158][0], \
4020 &mips_reg_names[159][0], \
4021 &mips_reg_names[160][0], \
4022 &mips_reg_names[161][0], \
4023 &mips_reg_names[162][0], \
4024 &mips_reg_names[163][0], \
4025 &mips_reg_names[164][0], \
4026 &mips_reg_names[165][0], \
4027 &mips_reg_names[166][0], \
4028 &mips_reg_names[167][0], \
4029 &mips_reg_names[168][0], \
4030 &mips_reg_names[169][0], \
4031 &mips_reg_names[170][0], \
4032 &mips_reg_names[171][0], \
4033 &mips_reg_names[172][0], \
4034 &mips_reg_names[173][0], \
4035 &mips_reg_names[174][0], \
4036 &mips_reg_names[175][0] \
4039 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4040 So define this for it. */
4041 #define DEBUG_REGISTER_NAMES \
4043 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4044 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4045 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4046 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4047 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4048 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4049 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4050 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4051 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4052 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
4053 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
4054 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
4055 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
4056 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
4057 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
4058 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
4059 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
4060 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
4061 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
4062 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
4063 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
4064 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
4067 /* If defined, a C initializer for an array of structures
4068 containing a name and a register number. This macro defines
4069 additional names for hard registers, thus allowing the `asm'
4070 option in declarations to refer to registers using alternate
4073 We define both names for the integer registers here. */
4075 #define ADDITIONAL_REGISTER_NAMES \
4077 { "$0", 0 + GP_REG_FIRST }, \
4078 { "$1", 1 + GP_REG_FIRST }, \
4079 { "$2", 2 + GP_REG_FIRST }, \
4080 { "$3", 3 + GP_REG_FIRST }, \
4081 { "$4", 4 + GP_REG_FIRST }, \
4082 { "$5", 5 + GP_REG_FIRST }, \
4083 { "$6", 6 + GP_REG_FIRST }, \
4084 { "$7", 7 + GP_REG_FIRST }, \
4085 { "$8", 8 + GP_REG_FIRST }, \
4086 { "$9", 9 + GP_REG_FIRST }, \
4087 { "$10", 10 + GP_REG_FIRST }, \
4088 { "$11", 11 + GP_REG_FIRST }, \
4089 { "$12", 12 + GP_REG_FIRST }, \
4090 { "$13", 13 + GP_REG_FIRST }, \
4091 { "$14", 14 + GP_REG_FIRST }, \
4092 { "$15", 15 + GP_REG_FIRST }, \
4093 { "$16", 16 + GP_REG_FIRST }, \
4094 { "$17", 17 + GP_REG_FIRST }, \
4095 { "$18", 18 + GP_REG_FIRST }, \
4096 { "$19", 19 + GP_REG_FIRST }, \
4097 { "$20", 20 + GP_REG_FIRST }, \
4098 { "$21", 21 + GP_REG_FIRST }, \
4099 { "$22", 22 + GP_REG_FIRST }, \
4100 { "$23", 23 + GP_REG_FIRST }, \
4101 { "$24", 24 + GP_REG_FIRST }, \
4102 { "$25", 25 + GP_REG_FIRST }, \
4103 { "$26", 26 + GP_REG_FIRST }, \
4104 { "$27", 27 + GP_REG_FIRST }, \
4105 { "$28", 28 + GP_REG_FIRST }, \
4106 { "$29", 29 + GP_REG_FIRST }, \
4107 { "$30", 30 + GP_REG_FIRST }, \
4108 { "$31", 31 + GP_REG_FIRST }, \
4109 { "$sp", 29 + GP_REG_FIRST }, \
4110 { "$fp", 30 + GP_REG_FIRST }, \
4111 { "at", 1 + GP_REG_FIRST }, \
4112 { "v0", 2 + GP_REG_FIRST }, \
4113 { "v1", 3 + GP_REG_FIRST }, \
4114 { "a0", 4 + GP_REG_FIRST }, \
4115 { "a1", 5 + GP_REG_FIRST }, \
4116 { "a2", 6 + GP_REG_FIRST }, \
4117 { "a3", 7 + GP_REG_FIRST }, \
4118 { "t0", 8 + GP_REG_FIRST }, \
4119 { "t1", 9 + GP_REG_FIRST }, \
4120 { "t2", 10 + GP_REG_FIRST }, \
4121 { "t3", 11 + GP_REG_FIRST }, \
4122 { "t4", 12 + GP_REG_FIRST }, \
4123 { "t5", 13 + GP_REG_FIRST }, \
4124 { "t6", 14 + GP_REG_FIRST }, \
4125 { "t7", 15 + GP_REG_FIRST }, \
4126 { "s0", 16 + GP_REG_FIRST }, \
4127 { "s1", 17 + GP_REG_FIRST }, \
4128 { "s2", 18 + GP_REG_FIRST }, \
4129 { "s3", 19 + GP_REG_FIRST }, \
4130 { "s4", 20 + GP_REG_FIRST }, \
4131 { "s5", 21 + GP_REG_FIRST }, \
4132 { "s6", 22 + GP_REG_FIRST }, \
4133 { "s7", 23 + GP_REG_FIRST }, \
4134 { "t8", 24 + GP_REG_FIRST }, \
4135 { "t9", 25 + GP_REG_FIRST }, \
4136 { "k0", 26 + GP_REG_FIRST }, \
4137 { "k1", 27 + GP_REG_FIRST }, \
4138 { "gp", 28 + GP_REG_FIRST }, \
4139 { "sp", 29 + GP_REG_FIRST }, \
4140 { "fp", 30 + GP_REG_FIRST }, \
4141 { "ra", 31 + GP_REG_FIRST }, \
4142 { "$sp", 29 + GP_REG_FIRST }, \
4143 { "$fp", 30 + GP_REG_FIRST } \
4144 ALL_COP_ADDITIONAL_REGISTER_NAMES \
4147 /* This is meant to be redefined in the host dependent files. It is a
4148 set of alternative names and regnums for mips coprocessors. */
4150 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
4152 /* A C compound statement to output to stdio stream STREAM the
4153 assembler syntax for an instruction operand X. X is an RTL
4156 CODE is a value that can be used to specify one of several ways
4157 of printing the operand. It is used when identical operands
4158 must be printed differently depending on the context. CODE
4159 comes from the `%' specification that was used to request
4160 printing of the operand. If the specification was just `%DIGIT'
4161 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4162 is the ASCII code for LTR.
4164 If X is a register, this macro should print the register's name.
4165 The names can be found in an array `reg_names' whose type is
4166 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4168 When the machine description has a specification `%PUNCT' (a `%'
4169 followed by a punctuation character), this macro is called with
4170 a null pointer for X and the punctuation character for CODE.
4172 See mips.c for the MIPS specific codes. */
4174 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4176 /* A C expression which evaluates to true if CODE is a valid
4177 punctuation character for use in the `PRINT_OPERAND' macro. If
4178 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4179 punctuation characters (except for the standard one, `%') are
4180 used in this way. */
4182 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4184 /* A C compound statement to output to stdio stream STREAM the
4185 assembler syntax for an instruction operand that is a memory
4186 reference whose address is ADDR. ADDR is an RTL expression. */
4188 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4191 /* A C statement, to be executed after all slot-filler instructions
4192 have been output. If necessary, call `dbr_sequence_length' to
4193 determine the number of slots filled in a sequence (zero if not
4194 currently outputting a sequence), to decide how many no-ops to
4195 output, or whatever.
4197 Don't define this macro if it has nothing to do, but it is
4198 helpful in reading assembly output if the extent of the delay
4199 sequence is made explicit (e.g. with white space).
4201 Note that output routines for instructions with delay slots must
4202 be prepared to deal with not being output as part of a sequence
4203 (i.e. when the scheduling pass is not run, or when no slot
4204 fillers could be found.) The variable `final_sequence' is null
4205 when not processing a sequence, otherwise it contains the
4206 `sequence' rtx being output. */
4208 #define DBR_OUTPUT_SEQEND(STREAM) \
4211 if (set_nomacro > 0 && --set_nomacro == 0) \
4212 fputs ("\t.set\tmacro\n", STREAM); \
4214 if (set_noreorder > 0 && --set_noreorder == 0) \
4215 fputs ("\t.set\treorder\n", STREAM); \
4217 dslots_jump_filled++; \
4218 fputs ("\n", STREAM); \
4223 /* How to tell the debugger about changes of source files. Note, the
4224 mips ECOFF format cannot deal with changes of files inside of
4225 functions, which means the output of parser generators like bison
4226 is generally not debuggable without using the -l switch. Lose,
4227 lose, lose. Silicon graphics seems to want all .file's hardwired
4230 #ifndef SET_FILE_NUMBER
4231 #define SET_FILE_NUMBER() ++num_source_filenames
4234 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4235 mips_output_filename (STREAM, NAME)
4237 /* This is defined so that it can be overridden in iris6.h. */
4238 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4241 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4242 output_quoted_string (STREAM, NAME); \
4243 fputs ("\n", STREAM); \
4247 /* This is how to output a note the debugger telling it the line number
4248 to which the following sequence of instructions corresponds.
4249 Silicon graphics puts a label after each .loc. */
4251 #ifndef LABEL_AFTER_LOC
4252 #define LABEL_AFTER_LOC(STREAM)
4255 #ifndef ASM_OUTPUT_SOURCE_LINE
4256 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4257 mips_output_lineno (STREAM, LINE)
4260 /* The MIPS implementation uses some labels for its own purpose. The
4261 following lists what labels are created, and are all formed by the
4262 pattern $L[a-z].*. The machine independent portion of GCC creates
4263 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4265 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4266 $Lb[0-9]+ Begin blocks for MIPS debug support
4267 $Lc[0-9]+ Label for use in s<xx> operation.
4268 $Le[0-9]+ End blocks for MIPS debug support */
4270 /* A C statement (sans semicolon) to output to the stdio stream
4271 STREAM any text necessary for declaring the name NAME of an
4272 initialized variable which is being defined. This macro must
4273 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4274 The argument DECL is the `VAR_DECL' tree node representing the
4277 If this macro is not defined, then the variable name is defined
4278 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4280 #undef ASM_DECLARE_OBJECT_NAME
4281 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4284 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4288 /* Globalizing directive for a label. */
4289 #define GLOBAL_ASM_OP "\t.globl\t"
4291 /* This says how to define a global common symbol. */
4293 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4295 /* If the target wants uninitialized const declarations in \
4296 .rdata then don't put them in .comm */ \
4297 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4298 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4299 && (DECL_INITIAL (DECL) == 0 \
4300 || DECL_INITIAL (DECL) == error_mark_node)) \
4302 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4303 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
4305 readonly_data_section (); \
4306 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4307 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4311 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4316 /* This says how to define a local common symbol (ie, not visible to
4319 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4320 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4323 /* This says how to output an external. It would be possible not to
4324 output anything and let undefined symbol become external. However
4325 the assembler uses length information on externals to allocate in
4326 data/sdata bss/sbss, thereby saving exec time. */
4328 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4329 mips_output_external(STREAM,DECL,NAME)
4331 /* This says what to print at the end of the assembly file */
4333 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4336 /* Play switch file games if we're optimizing the global pointer. */
4339 #define TEXT_SECTION() \
4341 extern FILE *asm_out_text_file; \
4342 if (TARGET_FILE_SWITCHING) \
4343 asm_out_file = asm_out_text_file; \
4344 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4345 fputc ('\n', asm_out_file); \
4349 /* This is how to declare a function name. The actual work of
4350 emitting the label is moved to function_prologue, so that we can
4351 get the line number correctly emitted before the .ent directive,
4352 and after any .file directives. Define as empty so that the function
4353 is not declared before the .ent directive elsewhere. */
4355 #undef ASM_DECLARE_FUNCTION_NAME
4356 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4358 /* This is how to store into the string LABEL
4359 the symbol_ref name of an internal numbered label where
4360 PREFIX is the class of label and NUM is the number within the class.
4361 This is suitable for output with `assemble_name'. */
4363 #undef ASM_GENERATE_INTERNAL_LABEL
4364 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4365 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4367 /* This is how to output an element of a case-vector that is absolute. */
4369 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4370 fprintf (STREAM, "\t%s\t%sL%d\n", \
4371 Pmode == DImode ? ".dword" : ".word", \
4372 LOCAL_LABEL_PREFIX, \
4375 /* This is how to output an element of a case-vector that is relative.
4376 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4377 TARGET_EMBEDDED_PIC). */
4379 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4381 if (TARGET_MIPS16) \
4382 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4383 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4384 else if (TARGET_EMBEDDED_PIC) \
4385 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4386 Pmode == DImode ? ".dword" : ".word", \
4387 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4388 else if (mips_abi == ABI_32 || mips_abi == ABI_O64 \
4389 || (TARGET_GAS && mips_abi == ABI_N32) \
4390 || (TARGET_GAS && mips_abi == ABI_64)) \
4391 fprintf (STREAM, "\t%s\t%sL%d\n", \
4392 Pmode == DImode ? ".gpdword" : ".gpword", \
4393 LOCAL_LABEL_PREFIX, VALUE); \
4395 fprintf (STREAM, "\t%s\t%sL%d\n", \
4396 Pmode == DImode ? ".dword" : ".word", \
4397 LOCAL_LABEL_PREFIX, VALUE); \
4400 /* When generating embedded PIC or mips16 code we want to put the jump
4401 table in the .text section. In all other cases, we want to put the
4402 jump table in the .rdata section. Unfortunately, we can't use
4403 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4404 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4405 section if appropriate. */
4406 #undef ASM_OUTPUT_CASE_LABEL
4407 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4409 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4410 function_section (current_function_decl); \
4411 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
4414 /* This is how to output an assembler line
4415 that says to advance the location counter
4416 to a multiple of 2**LOG bytes. */
4418 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4419 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4421 /* This is how to output an assembler line to advance the location
4422 counter by SIZE bytes. */
4424 #undef ASM_OUTPUT_SKIP
4425 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4426 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4428 /* This is how to output a string. */
4429 #undef ASM_OUTPUT_ASCII
4430 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4431 mips_output_ascii (STREAM, STRING, LEN)
4433 /* Output #ident as a in the read-only data section. */
4434 #undef ASM_OUTPUT_IDENT
4435 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4437 const char *p = STRING; \
4438 int size = strlen (p) + 1; \
4439 readonly_data_section (); \
4440 assemble_string (p, size); \
4443 /* Default to -G 8 */
4444 #ifndef MIPS_DEFAULT_GVALUE
4445 #define MIPS_DEFAULT_GVALUE 8
4448 /* Define the strings to put out for each section in the object file. */
4449 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4450 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4451 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4453 #undef READONLY_DATA_SECTION_ASM_OP
4454 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4456 #define SMALL_DATA_SECTION sdata_section
4458 /* What other sections we support other than the normal .data/.text. */
4460 #undef EXTRA_SECTIONS
4461 #define EXTRA_SECTIONS in_sdata
4463 /* Define the additional functions to select our additional sections. */
4465 /* on the MIPS it is not a good idea to put constants in the text
4466 section, since this defeats the sdata/data mechanism. This is
4467 especially true when -O is used. In this case an effort is made to
4468 address with faster (gp) register relative addressing, which can
4469 only get at sdata and sbss items (there is no stext !!) However,
4470 if the constant is too large for sdata, and it's readonly, it
4471 will go into the .rdata section. */
4473 #undef EXTRA_SECTION_FUNCTIONS
4474 #define EXTRA_SECTION_FUNCTIONS \
4478 if (in_section != in_sdata) \
4480 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4481 in_section = in_sdata; \
4485 /* Given a decl node or constant node, choose the section to output it in
4486 and select that section. */
4488 #undef TARGET_ASM_SELECT_SECTION
4489 #define TARGET_ASM_SELECT_SECTION mips_select_section
4491 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4494 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4495 TARGET_64BIT ? "dsubu" : "subu", \
4496 reg_names[STACK_POINTER_REGNUM], \
4497 reg_names[STACK_POINTER_REGNUM], \
4498 TARGET_64BIT ? "sd" : "sw", \
4500 reg_names[STACK_POINTER_REGNUM]); \
4504 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4507 if (! set_noreorder) \
4508 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4510 dslots_load_total++; \
4511 dslots_load_filled++; \
4512 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4513 TARGET_64BIT ? "ld" : "lw", \
4515 reg_names[STACK_POINTER_REGNUM], \
4516 TARGET_64BIT ? "daddu" : "addu", \
4517 reg_names[STACK_POINTER_REGNUM], \
4518 reg_names[STACK_POINTER_REGNUM]); \
4520 if (! set_noreorder) \
4521 fprintf (STREAM, "\t.set\treorder\n"); \
4525 /* How to start an assembler comment.
4526 The leading space is important (the mips native assembler requires it). */
4527 #ifndef ASM_COMMENT_START
4528 #define ASM_COMMENT_START " #"
4532 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4533 and mips-tdump.c to print them out.
4535 These must match the corresponding definitions in gdb/mipsread.c.
4536 Unfortunately, gcc and gdb do not currently share any directories. */
4538 #define CODE_MASK 0x8F300
4539 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4540 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4541 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4544 /* Default definitions for size_t and ptrdiff_t. We must override the
4545 definitions from ../svr4.h on mips-*-linux-gnu. */
4548 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4551 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4553 /* See mips_expand_prologue's use of loadgp for when this should be
4556 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4557 && mips_abi != ABI_32 \
4558 && mips_abi != ABI_O64)
4560 /* In mips16 mode, we need to look through the function to check for
4561 PC relative loads that are out of range. */
4562 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4564 /* We need to use a special set of functions to handle hard floating
4565 point code in mips16 mode. */
4567 #ifndef INIT_SUBTARGET_OPTABS
4568 #define INIT_SUBTARGET_OPTABS
4571 #define INIT_TARGET_OPTABS \
4574 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4575 INIT_SUBTARGET_OPTABS; \
4578 add_optab->handlers[(int) SFmode].libfunc = \
4579 init_one_libfunc ("__mips16_addsf3"); \
4580 sub_optab->handlers[(int) SFmode].libfunc = \
4581 init_one_libfunc ("__mips16_subsf3"); \
4582 smul_optab->handlers[(int) SFmode].libfunc = \
4583 init_one_libfunc ("__mips16_mulsf3"); \
4584 sdiv_optab->handlers[(int) SFmode].libfunc = \
4585 init_one_libfunc ("__mips16_divsf3"); \
4587 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4588 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4589 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4590 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4591 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4592 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4594 floatsisf_libfunc = \
4595 init_one_libfunc ("__mips16_floatsisf"); \
4597 init_one_libfunc ("__mips16_fixsfsi"); \
4599 if (TARGET_DOUBLE_FLOAT) \
4601 add_optab->handlers[(int) DFmode].libfunc = \
4602 init_one_libfunc ("__mips16_adddf3"); \
4603 sub_optab->handlers[(int) DFmode].libfunc = \
4604 init_one_libfunc ("__mips16_subdf3"); \
4605 smul_optab->handlers[(int) DFmode].libfunc = \
4606 init_one_libfunc ("__mips16_muldf3"); \
4607 sdiv_optab->handlers[(int) DFmode].libfunc = \
4608 init_one_libfunc ("__mips16_divdf3"); \
4610 extendsfdf2_libfunc = \
4611 init_one_libfunc ("__mips16_extendsfdf2"); \
4612 truncdfsf2_libfunc = \
4613 init_one_libfunc ("__mips16_truncdfsf2"); \
4616 init_one_libfunc ("__mips16_eqdf2"); \
4618 init_one_libfunc ("__mips16_nedf2"); \
4620 init_one_libfunc ("__mips16_gtdf2"); \
4622 init_one_libfunc ("__mips16_gedf2"); \
4624 init_one_libfunc ("__mips16_ltdf2"); \
4626 init_one_libfunc ("__mips16_ledf2"); \
4628 floatsidf_libfunc = \
4629 init_one_libfunc ("__mips16_floatsidf"); \
4631 init_one_libfunc ("__mips16_fixdfsi"); \
4637 #define DFMODE_NAN \
4638 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4639 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4640 #define SFMODE_NAN \
4641 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4642 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4644 /* Generate calls to memcpy, etc., not bcopy, etc. */
4645 #define TARGET_MEM_FUNCTIONS