1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern int target_flags;
31 /* MIPS external variables defined in mips.c. */
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
73 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
74 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
75 to work on a 64 bit machine. */
83 /* Information about one recognized processor. Defined here for the
84 benefit of TARGET_CPU_CPP_BUILTINS. */
85 struct mips_cpu_info {
86 /* The 'canonical' name of the processor as far as GCC is concerned.
87 It's typically a manufacturer's prefix followed by a numerical
88 designation. It should be lower case. */
91 /* The internal processor number that most closely matches this
92 entry. Several processors can have the same value, if there's no
93 difference between them from GCC's point of view. */
94 enum processor_type cpu;
96 /* The ISA level that the processor implements. */
100 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern int mips_entry; /* generate entry/exit for mips16 */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern int mips_string_length; /* length of strings for mips16 */
126 extern const struct mips_cpu_info mips_cpu_info_table[];
127 extern const struct mips_cpu_info *mips_arch_info;
128 extern const struct mips_cpu_info *mips_tune_info;
130 /* Macros to silence warnings about numbers being signed in traditional
131 C and unsigned in ISO C when compiled on 32-bit hosts. */
133 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
134 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
135 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
138 /* Run-time compilation parameters selecting different hardware subsets. */
140 /* Macros used in the machine description to test the flags. */
142 /* Bits for real switches */
143 #define MASK_INT64 0x00000001 /* ints are 64 bits */
144 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
145 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
146 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
147 multiply-add operations. */
148 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
149 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
150 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
151 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
152 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
153 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
154 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
155 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
156 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
157 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
158 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
159 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
160 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
161 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
162 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
163 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
164 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
165 #define MASK_NO_CHECK_ZERO_DIV \
166 0x00200000 /* divide by zero checking */
167 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
169 #define MASK_UNINIT_CONST_IN_RODATA \
170 0x00800000 /* Store uninitialized
172 #define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
174 /* Debug switches, not documented */
175 #define MASK_DEBUG 0 /* unused */
176 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
177 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
178 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
179 #define MASK_DEBUG_D 0 /* don't do define_split's */
180 #define MASK_DEBUG_E 0 /* function_arg debug */
181 #define MASK_DEBUG_F 0 /* ??? */
182 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
183 #define MASK_DEBUG_I 0 /* unused */
185 /* Dummy switches used only in specs */
186 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
188 /* r4000 64 bit sizes */
189 #define TARGET_INT64 (target_flags & MASK_INT64)
190 #define TARGET_LONG64 (target_flags & MASK_LONG64)
191 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
192 #define TARGET_64BIT (target_flags & MASK_64BIT)
194 /* Mips vs. GNU linker */
195 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
197 /* Mips vs. GNU assembler */
198 #define TARGET_GAS (target_flags & MASK_GAS)
199 #define TARGET_MIPS_AS (!TARGET_GAS)
202 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
203 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
204 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
205 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
206 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
207 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
208 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
209 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
210 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
212 /* Reg. Naming in .s ($21 vs. $a0) */
213 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
215 /* call memcpy instead of inline code */
216 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
218 /* .abicalls, etc from Pyramid V.4 */
219 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
220 #define TARGET_XGOT (target_flags & MASK_XGOT)
222 /* software floating point */
223 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
224 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
226 /* always call through a register */
227 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
229 /* generate embedded PIC code;
231 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
233 /* for embedded systems, optimize for
234 reduced RAM space instead of for
236 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
238 /* always store uninitialized const
239 variables in rodata, requires
240 TARGET_EMBEDDED_DATA. */
241 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
243 /* generate big endian code. */
244 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
246 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
247 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
249 #define TARGET_MAD (target_flags & MASK_MAD)
251 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
253 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
255 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
257 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
259 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
261 /* True if we should use NewABI-style relocation operators for
262 symbolic addresses. This is never true for mips16 code,
263 which has its own conventions. */
265 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
268 /* True if the call patterns should be split into a jalr followed by
269 an instruction to restore $gp. This is only ever true for SVR4 PIC,
270 in which $gp is call-clobbered. It is only safe to split the load
271 from the call when every use of $gp is explicit. */
273 #define TARGET_SPLIT_CALLS \
274 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
276 /* True if we can optimize sibling calls. For simplicity, we only
277 handle cases in which call_insn_operand will reject invalid
278 sibcall addresses. There are two cases in which this isn't true:
280 - TARGET_MIPS16. call_insn_operand accepts constant addresses
281 but there is no direct jump instruction. It isn't worth
282 using sibling calls in this case anyway; they would usually
283 be longer than normal calls.
285 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
286 accepts global constants, but "jr $25" is the only allowed
289 #define TARGET_SIBCALLS \
290 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
292 /* True if .gpword or .gpdword should be used for switch tables.
293 Not all SGI assemblers support this. */
295 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
297 /* Generate mips16 code */
298 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
300 /* Generic ISA defines. */
301 #define ISA_MIPS1 (mips_isa == 1)
302 #define ISA_MIPS2 (mips_isa == 2)
303 #define ISA_MIPS3 (mips_isa == 3)
304 #define ISA_MIPS4 (mips_isa == 4)
305 #define ISA_MIPS32 (mips_isa == 32)
306 #define ISA_MIPS32R2 (mips_isa == 33)
307 #define ISA_MIPS64 (mips_isa == 64)
309 /* Architecture target defines. */
310 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
311 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
312 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
313 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
314 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
315 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
316 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
317 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
318 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
319 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
320 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
321 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
322 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
324 /* Scheduling target defines. */
325 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
326 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
327 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
328 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
329 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
330 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
331 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
332 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
333 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
334 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
335 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
337 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
339 /* Define preprocessor macros for the -march and -mtune options.
340 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
341 processor. If INFO's canonical name is "foo", define PREFIX to
342 be "foo", and define an additional macro PREFIX_FOO. */
343 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
348 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
349 for (p = macro; *p != 0; p++) \
352 builtin_define (macro); \
353 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
358 /* Target CPU builtins. */
359 #define TARGET_CPU_CPP_BUILTINS() \
362 builtin_assert ("cpu=mips"); \
363 builtin_define ("__mips__"); \
364 builtin_define ("_mips"); \
366 /* We do this here because __mips is defined below \
367 and so we can't use builtin_define_std. */ \
369 builtin_define ("mips"); \
371 /* Treat _R3000 and _R4000 like register-size defines, \
372 which is how they've historically been used. */ \
375 builtin_define ("__mips64"); \
376 builtin_define_std ("R4000"); \
377 builtin_define ("_R4000"); \
381 builtin_define_std ("R3000"); \
382 builtin_define ("_R3000"); \
384 if (TARGET_FLOAT64) \
385 builtin_define ("__mips_fpr=64"); \
387 builtin_define ("__mips_fpr=32"); \
390 builtin_define ("__mips16"); \
392 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
393 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
397 builtin_define ("__mips=1"); \
398 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
400 else if (ISA_MIPS2) \
402 builtin_define ("__mips=2"); \
403 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
405 else if (ISA_MIPS3) \
407 builtin_define ("__mips=3"); \
408 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
410 else if (ISA_MIPS4) \
412 builtin_define ("__mips=4"); \
413 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
415 else if (ISA_MIPS32) \
417 builtin_define ("__mips=32"); \
418 builtin_define ("__mips_isa_rev=1"); \
419 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
421 else if (ISA_MIPS32R2) \
423 builtin_define ("__mips=32"); \
424 builtin_define ("__mips_isa_rev=2"); \
425 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
427 else if (ISA_MIPS64) \
429 builtin_define ("__mips=64"); \
430 builtin_define ("__mips_isa_rev=1"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
434 if (TARGET_HARD_FLOAT) \
435 builtin_define ("__mips_hard_float"); \
436 else if (TARGET_SOFT_FLOAT) \
437 builtin_define ("__mips_soft_float"); \
439 if (TARGET_SINGLE_FLOAT) \
440 builtin_define ("__mips_single_float"); \
442 if (TARGET_BIG_ENDIAN) \
444 builtin_define_std ("MIPSEB"); \
445 builtin_define ("_MIPSEB"); \
449 builtin_define_std ("MIPSEL"); \
450 builtin_define ("_MIPSEL"); \
453 /* Macros dependent on the C dialect. */ \
454 if (preprocessing_asm_p ()) \
456 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
457 builtin_define ("_LANGUAGE_ASSEMBLY"); \
459 else if (c_dialect_cxx ()) \
461 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
462 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
463 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
467 builtin_define_std ("LANGUAGE_C"); \
468 builtin_define ("_LANGUAGE_C"); \
470 if (c_dialect_objc ()) \
472 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
473 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
474 /* Bizzare, but needed at least for Irix. */ \
475 builtin_define_std ("LANGUAGE_C"); \
476 builtin_define ("_LANGUAGE_C"); \
479 if (mips_abi == ABI_EABI) \
480 builtin_define ("__mips_eabi"); \
486 /* Macro to define tables used to set the flags.
487 This is a list in braces of pairs in braces,
488 each pair being { "NAME", VALUE }
489 where VALUE is the bits to set or minus the bits to clear.
490 An empty string NAME is used to identify the default VALUE. */
492 #define TARGET_SWITCHES \
494 SUBTARGET_TARGET_SWITCHES \
495 {"int64", MASK_INT64 | MASK_LONG64, \
496 N_("Use 64-bit int type")}, \
497 {"long64", MASK_LONG64, \
498 N_("Use 64-bit long type")}, \
499 {"long32", -(MASK_LONG64 | MASK_INT64), \
500 N_("Use 32-bit long type")}, \
501 {"split-addresses", MASK_SPLIT_ADDR, \
502 N_("Optimize lui/addiu address loads")}, \
503 {"no-split-addresses", -MASK_SPLIT_ADDR, \
504 N_("Don't optimize lui/addiu address loads")}, \
505 {"mips-as", -MASK_GAS, \
506 N_("Use MIPS as")}, \
509 {"rnames", MASK_NAME_REGS, \
510 N_("Use symbolic register names")}, \
511 {"no-rnames", -MASK_NAME_REGS, \
512 N_("Don't use symbolic register names")}, \
514 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
516 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
518 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
520 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
522 N_("Output compiler statistics (now ignored)")}, \
524 N_("Don't output compiler statistics")}, \
525 {"memcpy", MASK_MEMCPY, \
526 N_("Don't optimize block moves")}, \
527 {"no-memcpy", -MASK_MEMCPY, \
528 N_("Optimize block moves")}, \
529 {"mips-tfile", MASK_MIPS_TFILE, \
530 N_("Use mips-tfile asm postpass")}, \
531 {"no-mips-tfile", -MASK_MIPS_TFILE, \
532 N_("Don't use mips-tfile asm postpass")}, \
533 {"soft-float", MASK_SOFT_FLOAT, \
534 N_("Use software floating point")}, \
535 {"hard-float", -MASK_SOFT_FLOAT, \
536 N_("Use hardware floating point")}, \
537 {"fp64", MASK_FLOAT64, \
538 N_("Use 64-bit FP registers")}, \
539 {"fp32", -MASK_FLOAT64, \
540 N_("Use 32-bit FP registers")}, \
541 {"gp64", MASK_64BIT, \
542 N_("Use 64-bit general registers")}, \
543 {"gp32", -MASK_64BIT, \
544 N_("Use 32-bit general registers")}, \
545 {"abicalls", MASK_ABICALLS, \
546 N_("Use Irix PIC")}, \
547 {"no-abicalls", -MASK_ABICALLS, \
548 N_("Don't use Irix PIC")}, \
549 {"long-calls", MASK_LONG_CALLS, \
550 N_("Use indirect calls")}, \
551 {"no-long-calls", -MASK_LONG_CALLS, \
552 N_("Don't use indirect calls")}, \
553 {"embedded-pic", MASK_EMBEDDED_PIC, \
554 N_("Use embedded PIC")}, \
555 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
556 N_("Don't use embedded PIC")}, \
557 {"embedded-data", MASK_EMBEDDED_DATA, \
558 N_("Use ROM instead of RAM")}, \
559 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
560 N_("Don't use ROM instead of RAM")}, \
561 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
562 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
563 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
564 N_("Don't put uninitialized constants in ROM")}, \
565 {"eb", MASK_BIG_ENDIAN, \
566 N_("Use big-endian byte order")}, \
567 {"el", -MASK_BIG_ENDIAN, \
568 N_("Use little-endian byte order")}, \
569 {"single-float", MASK_SINGLE_FLOAT, \
570 N_("Use single (32-bit) FP only")}, \
571 {"double-float", -MASK_SINGLE_FLOAT, \
572 N_("Don't use single (32-bit) FP only")}, \
574 N_("Use multiply accumulate")}, \
575 {"no-mad", -MASK_MAD, \
576 N_("Don't use multiply accumulate")}, \
577 {"no-fused-madd", MASK_NO_FUSED_MADD, \
578 N_("Don't generate fused multiply/add instructions")}, \
579 {"fused-madd", -MASK_NO_FUSED_MADD, \
580 N_("Generate fused multiply/add instructions")}, \
581 {"fix4300", MASK_4300_MUL_FIX, \
582 N_("Work around early 4300 hardware bug")}, \
583 {"no-fix4300", -MASK_4300_MUL_FIX, \
584 N_("Don't work around early 4300 hardware bug")}, \
585 {"fix-sb1", MASK_FIX_SB1, \
586 N_("Work around errata for early SB-1 revision 2 cores")}, \
587 {"no-fix-sb1", -MASK_FIX_SB1, \
588 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
589 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
590 N_("Trap on integer divide by zero")}, \
591 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
592 N_("Don't trap on integer divide by zero")}, \
593 { "branch-likely", MASK_BRANCHLIKELY, \
594 N_("Use Branch Likely instructions, overriding default for arch")}, \
595 { "no-branch-likely", -MASK_BRANCHLIKELY, \
596 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
597 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
598 N_("Use NewABI-style %reloc() assembly operators")}, \
599 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
600 N_("Use assembler macros instead of relocation operators")}, \
601 {"ips16", MASK_MIPS16, \
602 N_("Generate mips16 code") }, \
603 {"no-mips16", -MASK_MIPS16, \
604 N_("Generate normal-mode code") }, \
605 {"xgot", MASK_XGOT, \
606 N_("Lift restrictions on GOT size") }, \
607 {"no-xgot", -MASK_XGOT, \
608 N_("Do not lift restrictions on GOT size") }, \
609 {"debug", MASK_DEBUG, \
611 {"debuga", MASK_DEBUG_A, \
613 {"debugb", MASK_DEBUG_B, \
615 {"debugc", MASK_DEBUG_C, \
617 {"debugd", MASK_DEBUG_D, \
619 {"debuge", MASK_DEBUG_E, \
621 {"debugf", MASK_DEBUG_F, \
623 {"debugg", MASK_DEBUG_G, \
625 {"debugi", MASK_DEBUG_I, \
627 {"", (TARGET_DEFAULT \
628 | TARGET_CPU_DEFAULT \
629 | TARGET_ENDIAN_DEFAULT), \
633 /* Default target_flags if no switches are specified */
635 #ifndef TARGET_DEFAULT
636 #define TARGET_DEFAULT 0
639 #ifndef TARGET_CPU_DEFAULT
640 #define TARGET_CPU_DEFAULT 0
643 #ifndef TARGET_ENDIAN_DEFAULT
644 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
647 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
648 #ifndef MIPS_ISA_DEFAULT
649 #ifndef MIPS_CPU_STRING_DEFAULT
650 #define MIPS_CPU_STRING_DEFAULT "from-abi"
656 /* Make this compile time constant for libgcc2 */
658 #define TARGET_64BIT 1
660 #define TARGET_64BIT 0
662 #endif /* IN_LIBGCC2 */
664 #ifndef MULTILIB_ENDIAN_DEFAULT
665 #if TARGET_ENDIAN_DEFAULT == 0
666 #define MULTILIB_ENDIAN_DEFAULT "EL"
668 #define MULTILIB_ENDIAN_DEFAULT "EB"
672 #ifndef MULTILIB_ISA_DEFAULT
673 # if MIPS_ISA_DEFAULT == 1
674 # define MULTILIB_ISA_DEFAULT "mips1"
676 # if MIPS_ISA_DEFAULT == 2
677 # define MULTILIB_ISA_DEFAULT "mips2"
679 # if MIPS_ISA_DEFAULT == 3
680 # define MULTILIB_ISA_DEFAULT "mips3"
682 # if MIPS_ISA_DEFAULT == 4
683 # define MULTILIB_ISA_DEFAULT "mips4"
685 # if MIPS_ISA_DEFAULT == 32
686 # define MULTILIB_ISA_DEFAULT "mips32"
688 # if MIPS_ISA_DEFAULT == 33
689 # define MULTILIB_ISA_DEFAULT "mips32r2"
691 # if MIPS_ISA_DEFAULT == 64
692 # define MULTILIB_ISA_DEFAULT "mips64"
694 # define MULTILIB_ISA_DEFAULT "mips1"
704 #ifndef MULTILIB_DEFAULTS
705 #define MULTILIB_DEFAULTS \
706 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
709 /* We must pass -EL to the linker by default for little endian embedded
710 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
711 linker will default to using big-endian output files. The OUTPUT_FORMAT
712 line must be in the linker script, otherwise -EB/-EL will not work. */
715 #if TARGET_ENDIAN_DEFAULT == 0
716 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
718 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
722 #define TARGET_OPTIONS \
724 SUBTARGET_TARGET_OPTIONS \
725 { "tune=", &mips_tune_string, \
726 N_("Specify CPU for scheduling purposes"), 0}, \
727 { "arch=", &mips_arch_string, \
728 N_("Specify CPU for code generation purposes"), 0}, \
729 { "abi=", &mips_abi_string, \
730 N_("Specify an ABI"), 0}, \
731 { "ips", &mips_isa_string, \
732 N_("Specify a Standard MIPS ISA"), 0}, \
733 { "no-flush-func", &mips_cache_flush_func, \
734 N_("Don't call any cache flush functions"), 0}, \
735 { "flush-func=", &mips_cache_flush_func, \
736 N_("Specify cache flush function"), 0}, \
739 /* This is meant to be redefined in the host dependent files. */
740 #define SUBTARGET_TARGET_OPTIONS
742 /* Support for a compile-time default CPU, et cetera. The rules are:
743 --with-arch is ignored if -march is specified or a -mips is specified
744 (other than -mips16).
745 --with-tune is ignored if -mtune is specified.
746 --with-abi is ignored if -mabi is specified.
747 --with-float is ignored if -mhard-float or -msoft-float are
749 #define OPTION_DEFAULT_SPECS \
750 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
751 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
752 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
753 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
756 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
760 /* Generate three-operand multiply instructions for SImode. */
761 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
771 /* Generate three-operand multiply instructions for DImode. */
772 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
775 /* Macros to decide whether certain features are available or not,
776 depending on the instruction set architecture level. */
778 #define HAVE_SQRT_P() (!ISA_MIPS1)
780 /* True if the ABI can only work with 64-bit integer registers. We
781 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
782 otherwise floating-point registers must also be 64-bit. */
783 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
784 || mips_abi == ABI_O64 \
785 || mips_abi == ABI_N32)
787 /* Likewise for 32-bit regs. */
788 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
790 /* True if symbols are 64 bits wide. At present, n64 is the only
791 ABI for which this is true. */
792 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
794 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
795 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
799 /* ISA has branch likely instructions (eg. mips2). */
800 /* Disable branchlikely for tx39 until compare rewrite. They haven't
801 been generated up to this point. */
802 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
805 /* ISA has the conditional move instructions introduced in mips4. */
806 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
810 && !TARGET_MIPS5500 \
813 /* ISA has just the integer condition move instructions (movn,movz) */
814 #define ISA_HAS_INT_CONDMOVE 0
816 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
817 branch on CC, and move (both FP and non-FP) on CC. */
818 #define ISA_HAS_8CC (ISA_MIPS4 \
823 /* This is a catch all for other mips4 instructions: indexed load, the
824 FP madd and msub instructions, and the FP recip and recip sqrt
826 #define ISA_HAS_FP4 ((ISA_MIPS4 \
830 /* ISA has conditional trap instructions. */
831 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
834 /* ISA has integer multiply-accumulate instructions, madd and msub. */
835 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
840 /* ISA has floating-point nmadd and nmsub instructions. */
841 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
843 && (!TARGET_MIPS5400 || TARGET_MAD) \
846 /* ISA has count leading zeroes/ones instruction (not implemented). */
847 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
852 /* ISA has double-word count leading zeroes/ones instruction (not
854 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
857 /* ISA has three operand multiply instructions that put
858 the high part in an accumulator: mulhi or mulhiu. */
859 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
864 /* ISA has three operand multiply instructions that
865 negates the result and puts the result in an accumulator. */
866 #define ISA_HAS_MULS (TARGET_MIPS5400 \
871 /* ISA has three operand multiply instructions that subtracts the
872 result from a 4th operand and puts the result in an accumulator. */
873 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
877 /* ISA has three operand multiply instructions that the result
878 from a 4th operand and puts the result in an accumulator. */
879 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
885 /* ISA has 32-bit rotate right instruction. */
886 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
893 /* ISA has 64-bit rotate right instruction. */
894 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
896 && (TARGET_MIPS5400 \
901 /* ISA has data prefetch instructions. This controls use of 'pref'. */
902 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
908 /* ISA has data indexed prefetch instructions. This controls use of
909 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
910 (prefx is a cop1x instruction, so can only be used if FP is
912 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
916 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
917 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
918 also requires TARGET_DOUBLE_FLOAT. */
919 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
921 /* ISA includes the MIPS32r2 seb and seh instructions. */
922 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
926 /* True if the result of a load is not available to the next instruction.
927 A nop will then be needed between instructions like "lw $4,..."
928 and "addiu $4,$4,1". */
929 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
930 && !TARGET_MIPS3900 \
933 /* Likewise mtc1 and mfc1. */
934 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
936 /* Likewise floating-point comparisons. */
937 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
939 /* True if mflo and mfhi can be immediately followed by instructions
940 which write to the HI and LO registers. Most targets require a
941 two-instruction gap. */
942 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
944 /* Add -G xx support. */
946 #undef SWITCH_TAKES_ARG
947 #define SWITCH_TAKES_ARG(CHAR) \
948 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
950 #define OVERRIDE_OPTIONS override_options ()
952 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
954 /* Show we can debug even without a frame pointer. */
955 #define CAN_DEBUG_WITHOUT_FP
957 /* Tell collect what flags to pass to nm. */
959 #define NM_FLAGS "-Bn"
963 /* Assembler specs. */
965 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
968 #define MIPS_AS_ASM_SPEC "\
969 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
970 %{pipe: %e-pipe is not supported} \
971 %{K} %(subtarget_mips_as_asm_spec)"
973 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
974 rather than gas. It may be overridden by subtargets. */
976 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
977 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
980 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
983 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
985 #define SUBTARGET_TARGET_SWITCHES
987 #ifndef MIPS_ABI_DEFAULT
988 #define MIPS_ABI_DEFAULT ABI_32
991 /* Use the most portable ABI flag for the ASM specs. */
993 #if MIPS_ABI_DEFAULT == ABI_32
994 #define MULTILIB_ABI_DEFAULT "mabi=32"
995 #define ASM_ABI_DEFAULT_SPEC "-32"
998 #if MIPS_ABI_DEFAULT == ABI_O64
999 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1000 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1003 #if MIPS_ABI_DEFAULT == ABI_N32
1004 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1005 #define ASM_ABI_DEFAULT_SPEC "-n32"
1008 #if MIPS_ABI_DEFAULT == ABI_64
1009 #define MULTILIB_ABI_DEFAULT "mabi=64"
1010 #define ASM_ABI_DEFAULT_SPEC "-64"
1013 #if MIPS_ABI_DEFAULT == ABI_EABI
1014 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1015 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1018 /* Only ELF targets can switch the ABI. */
1019 #ifndef OBJECT_FORMAT_ELF
1020 #undef ASM_ABI_DEFAULT_SPEC
1021 #define ASM_ABI_DEFAULT_SPEC ""
1024 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1025 GAS_ASM_SPEC as the default, depending upon the value of
1028 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1031 #define TARGET_ASM_SPEC "\
1032 %{mmips-as: %(mips_as_asm_spec)} \
1033 %{!mmips-as: %(gas_asm_spec)}"
1037 #define TARGET_ASM_SPEC "\
1038 %{!mgas: %(mips_as_asm_spec)} \
1039 %{mgas: %(gas_asm_spec)}"
1041 #endif /* not GAS */
1043 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1044 to the assembler. It may be overridden by subtargets. */
1045 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1046 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1048 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1051 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1052 the assembler. It may be overridden by subtargets. */
1053 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1054 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1055 %{g} %{g0} %{g1} %{g2} %{g3} \
1056 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1057 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1058 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1059 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1063 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1064 and stabs debugging info. */
1065 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1067 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1069 #define MDEBUG_ASM_SPEC ""
1070 #endif /* not GAS */
1072 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1073 overridden by subtargets. */
1075 #ifndef SUBTARGET_ASM_SPEC
1076 #define SUBTARGET_ASM_SPEC ""
1079 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1080 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1081 whether we're using GAS. These options can only be used properly
1082 with GAS, and it is better to get an error from a non-GAS assembler
1083 than to silently generate bad code. */
1087 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1088 %{mips32} %{mips32r2} %{mips64} \
1089 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1090 %(subtarget_asm_optimizing_spec) \
1091 %(subtarget_asm_debugging_spec) \
1093 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1094 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1095 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1096 %(target_asm_spec) \
1097 %(subtarget_asm_spec)"
1099 /* Extra switches sometimes passed to the linker. */
1100 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1101 will interpret it as a -b option. */
1104 #define LINK_SPEC "\
1106 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1107 %{bestGnum} %{shared} %{non_shared}"
1108 #endif /* LINK_SPEC defined */
1111 /* Specs for the compiler proper */
1113 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1114 overridden by subtargets. */
1115 #ifndef SUBTARGET_CC1_SPEC
1116 #define SUBTARGET_CC1_SPEC ""
1119 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1123 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1124 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1126 %(subtarget_cc1_spec)"
1129 /* Preprocessor specs. */
1131 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1132 overridden by subtargets. */
1133 #ifndef SUBTARGET_CPP_SPEC
1134 #define SUBTARGET_CPP_SPEC ""
1137 #define CPP_SPEC "%(subtarget_cpp_spec)"
1139 /* This macro defines names of additional specifications to put in the specs
1140 that can be used in various specifications like CC1_SPEC. Its definition
1141 is an initializer with a subgrouping for each command option.
1143 Each subgrouping contains a string constant, that defines the
1144 specification name, and a string constant that used by the GCC driver
1147 Do not define this macro if it does not need to do anything. */
1149 #define EXTRA_SPECS \
1150 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1151 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1152 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1153 { "gas_asm_spec", GAS_ASM_SPEC }, \
1154 { "target_asm_spec", TARGET_ASM_SPEC }, \
1155 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1156 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1157 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1158 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1159 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1160 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1161 { "endian_spec", ENDIAN_SPEC }, \
1162 SUBTARGET_EXTRA_SPECS
1164 #ifndef SUBTARGET_EXTRA_SPECS
1165 #define SUBTARGET_EXTRA_SPECS
1168 /* If defined, this macro is an additional prefix to try after
1169 `STANDARD_EXEC_PREFIX'. */
1171 #ifndef MD_EXEC_PREFIX
1172 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1175 #ifndef MD_STARTFILE_PREFIX
1176 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1180 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1181 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1183 /* By default, turn on GDB extensions. */
1184 #define DEFAULT_GDB_EXTENSIONS 1
1186 /* If we are passing smuggling stabs through the MIPS ECOFF object
1187 format, put a comment in front of the .stab<x> operation so
1188 that the MIPS assembler does not choke. The mips-tfile program
1189 will correctly put the stab into the object file. */
1191 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1192 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1193 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1195 /* Local compiler-generated symbols must have a prefix that the assembler
1196 understands. By default, this is $, although some targets (e.g.,
1197 NetBSD-ELF) need to override this. */
1199 #ifndef LOCAL_LABEL_PREFIX
1200 #define LOCAL_LABEL_PREFIX "$"
1203 /* By default on the mips, external symbols do not have an underscore
1204 prepended, but some targets (e.g., NetBSD) require this. */
1206 #ifndef USER_LABEL_PREFIX
1207 #define USER_LABEL_PREFIX ""
1210 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1211 since the length can run past this up to a continuation point. */
1212 #undef DBX_CONTIN_LENGTH
1213 #define DBX_CONTIN_LENGTH 1500
1215 /* How to renumber registers for dbx and gdb. */
1216 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1218 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1219 #define DWARF_FRAME_REGNUM(REG) (REG)
1221 /* The DWARF 2 CFA column which tracks the return address. */
1222 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1224 /* The DWARF 2 CFA column which tracks the return address from a
1225 signal handler context. */
1226 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1228 /* Before the prologue, RA lives in r31. */
1229 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1231 /* Describe how we implement __builtin_eh_return. */
1232 #define EH_RETURN_DATA_REGNO(N) \
1233 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1235 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1237 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1238 The default for this in 64-bit mode is 8, which causes problems with
1239 SFmode register saves. */
1240 #define DWARF_CIE_DATA_ALIGNMENT 4
1242 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1244 /* Correct the offset of automatic variables and arguments. Note that
1245 the MIPS debug format wants all automatic variables and arguments
1246 to be in terms of the virtual frame pointer (stack pointer before
1247 any adjustment in the function), while the MIPS 3.0 linker wants
1248 the frame pointer to be the stack pointer after the initial
1251 #define DEBUGGER_AUTO_OFFSET(X) \
1252 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1253 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1254 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1256 /* Target machine storage layout */
1258 #define BITS_BIG_ENDIAN 0
1259 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1260 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1262 /* Define this to set the endianness to use in libgcc2.c, which can
1263 not depend on target_flags. */
1264 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1265 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1267 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1270 #define MAX_BITS_PER_WORD 64
1272 /* Width of a word, in units (bytes). */
1273 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1274 #define MIN_UNITS_PER_WORD 4
1276 /* For MIPS, width of a floating point register. */
1277 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1279 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1280 the next available register. */
1281 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1283 /* The largest size of value that can be held in floating-point
1284 registers and moved with a single instruction. */
1285 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1287 /* The largest size of value that can be held in floating-point
1289 #define UNITS_PER_FPVALUE \
1290 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1292 /* The number of bytes in a double. */
1293 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1295 /* Tell the preprocessor the maximum size of wchar_t. */
1296 #ifndef MAX_WCHAR_TYPE_SIZE
1297 #ifndef WCHAR_TYPE_SIZE
1298 #define MAX_WCHAR_TYPE_SIZE 64
1302 /* Set the sizes of the core types. */
1303 #define SHORT_TYPE_SIZE 16
1304 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1305 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1306 #define LONG_LONG_TYPE_SIZE 64
1308 #define MAX_LONG_TYPE_SIZE 64
1310 #define FLOAT_TYPE_SIZE 32
1311 #define DOUBLE_TYPE_SIZE 64
1312 #define LONG_DOUBLE_TYPE_SIZE \
1313 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1315 /* long double is not a fixed mode, but the idea is that, if we
1316 support long double, we also want a 128-bit integer type. */
1317 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1320 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1321 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1322 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1324 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1328 /* Width in bits of a pointer. */
1329 #ifndef POINTER_SIZE
1330 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1333 #define POINTERS_EXTEND_UNSIGNED 0
1335 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1336 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1337 || mips_abi == ABI_64 \
1338 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1341 /* Allocation boundary (in *bits*) for the code of a function. */
1342 #define FUNCTION_BOUNDARY 32
1344 /* Alignment of field after `int : 0' in a structure. */
1345 #define EMPTY_FIELD_BOUNDARY 32
1347 /* Every structure's size must be a multiple of this. */
1348 /* 8 is observed right on a DECstation and on riscos 4.02. */
1349 #define STRUCTURE_SIZE_BOUNDARY 8
1351 /* There is no point aligning anything to a rounder boundary than this. */
1352 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1354 /* All accesses must be aligned. */
1355 #define STRICT_ALIGNMENT 1
1357 /* Define this if you wish to imitate the way many other C compilers
1358 handle alignment of bitfields and the structures that contain
1361 The behavior is that the type written for a bit-field (`int',
1362 `short', or other integer type) imposes an alignment for the
1363 entire structure, as if the structure really did contain an
1364 ordinary field of that type. In addition, the bit-field is placed
1365 within the structure so that it would fit within such a field,
1366 not crossing a boundary for it.
1368 Thus, on most machines, a bit-field whose type is written as `int'
1369 would not cross a four-byte boundary, and would force four-byte
1370 alignment for the whole structure. (The alignment used may not
1371 be four bytes; it is controlled by the other alignment
1374 If the macro is defined, its definition should be a C expression;
1375 a nonzero value for the expression enables this behavior. */
1377 #define PCC_BITFIELD_TYPE_MATTERS 1
1379 /* If defined, a C expression to compute the alignment given to a
1380 constant that is being placed in memory. CONSTANT is the constant
1381 and ALIGN is the alignment that the object would ordinarily have.
1382 The value of this macro is used instead of that alignment to align
1385 If this macro is not defined, then ALIGN is used.
1387 The typical use of this macro is to increase alignment for string
1388 constants to be word aligned so that `strcpy' calls that copy
1389 constants can be done inline. */
1391 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1392 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1393 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1395 /* If defined, a C expression to compute the alignment for a static
1396 variable. TYPE is the data type, and ALIGN is the alignment that
1397 the object would ordinarily have. The value of this macro is used
1398 instead of that alignment to align the object.
1400 If this macro is not defined, then ALIGN is used.
1402 One use of this macro is to increase alignment of medium-size
1403 data to make it all fit in fewer cache lines. Another is to
1404 cause character arrays to be word-aligned so that `strcpy' calls
1405 that copy constants to character arrays can be done inline. */
1407 #undef DATA_ALIGNMENT
1408 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1409 ((((ALIGN) < BITS_PER_WORD) \
1410 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1411 || TREE_CODE (TYPE) == UNION_TYPE \
1412 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1415 #define PAD_VARARGS_DOWN \
1416 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1418 /* Arguments declared as 'char' or 'short' in a prototype should be
1419 passed as 'int's. */
1420 #define PROMOTE_PROTOTYPES 1
1422 /* Define if operations between registers always perform the operation
1423 on the full register even if a narrower mode is specified. */
1424 #define WORD_REGISTER_OPERATIONS
1426 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1427 moves. All other references are zero extended. */
1428 #define LOAD_EXTEND_OP(MODE) \
1429 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1430 ? SIGN_EXTEND : ZERO_EXTEND)
1432 /* Define this macro if it is advisable to hold scalars in registers
1433 in a wider mode than that declared by the program. In such cases,
1434 the value is constrained to be within the bounds of the declared
1435 type, but kept valid in the wider mode. The signedness of the
1436 extension may differ from that of the type. */
1438 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1439 if (GET_MODE_CLASS (MODE) == MODE_INT \
1440 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1442 if ((MODE) == SImode) \
1447 /* Define if loading short immediate values into registers sign extends. */
1448 #define SHORT_IMMEDIATES_SIGN_EXTEND
1451 /* Define this if function arguments should also be promoted using the above
1453 #define PROMOTE_FUNCTION_ARGS
1455 /* Likewise, if the function return value is promoted. */
1456 #define PROMOTE_FUNCTION_RETURN
1459 /* Standard register usage. */
1461 /* Number of hardware registers. We have:
1463 - 32 integer registers
1464 - 32 floating point registers
1465 - 8 condition code registers
1466 - 2 accumulator registers (hi and lo)
1467 - 32 registers each for coprocessors 0, 2 and 3
1468 - 6 dummy entries that were used at various times in the past. */
1470 #define FIRST_PSEUDO_REGISTER 176
1472 /* By default, fix the kernel registers ($26 and $27), the global
1473 pointer ($28) and the stack pointer ($29). This can change
1474 depending on the command-line options.
1476 Regarding coprocessor registers: without evidence to the contrary,
1477 it's best to assume that each coprocessor register has a unique
1478 use. This can be overridden, in, e.g., override_options() or
1479 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1480 for a particular target. */
1482 #define FIXED_REGISTERS \
1484 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1485 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1488 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1489 /* COP0 registers */ \
1490 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1491 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1492 /* COP2 registers */ \
1493 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1494 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1495 /* COP3 registers */ \
1496 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1497 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1501 /* Set up this array for o32 by default.
1503 Note that we don't mark $31 as a call-clobbered register. The idea is
1504 that it's really the call instructions themselves which clobber $31.
1505 We don't care what the called function does with it afterwards.
1507 This approach makes it easier to implement sibcalls. Unlike normal
1508 calls, sibcalls don't clobber $31, so the register reaches the
1509 called function in tact. EPILOGUE_USES says that $31 is useful
1510 to the called function. */
1512 #define CALL_USED_REGISTERS \
1514 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1515 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1516 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1517 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 /* COP0 registers */ \
1520 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1522 /* COP2 registers */ \
1523 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1524 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1525 /* COP3 registers */ \
1526 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1527 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1531 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1533 #define CALL_REALLY_USED_REGISTERS \
1534 { /* General registers. */ \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1537 /* Floating-point registers. */ \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 /* COP0 registers */ \
1543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1545 /* COP2 registers */ \
1546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1548 /* COP3 registers */ \
1549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1553 /* Internal macros to classify a register number as to whether it's a
1554 general purpose register, a floating point register, a
1555 multiply/divide register, or a status register. */
1557 #define GP_REG_FIRST 0
1558 #define GP_REG_LAST 31
1559 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1560 #define GP_DBX_FIRST 0
1562 #define FP_REG_FIRST 32
1563 #define FP_REG_LAST 63
1564 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1565 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1567 #define MD_REG_FIRST 64
1568 #define MD_REG_LAST 65
1569 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1570 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1572 #define ST_REG_FIRST 67
1573 #define ST_REG_LAST 74
1574 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1577 /* FIXME: renumber. */
1578 #define COP0_REG_FIRST 80
1579 #define COP0_REG_LAST 111
1580 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1582 #define COP2_REG_FIRST 112
1583 #define COP2_REG_LAST 143
1584 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1586 #define COP3_REG_FIRST 144
1587 #define COP3_REG_LAST 175
1588 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1589 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1590 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1592 #define AT_REGNUM (GP_REG_FIRST + 1)
1593 #define HI_REGNUM (MD_REG_FIRST + 0)
1594 #define LO_REGNUM (MD_REG_FIRST + 1)
1596 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1597 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1598 should be used instead. */
1599 #define FPSW_REGNUM ST_REG_FIRST
1601 #define GP_REG_P(REGNO) \
1602 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1603 #define M16_REG_P(REGNO) \
1604 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1605 #define FP_REG_P(REGNO) \
1606 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1607 #define MD_REG_P(REGNO) \
1608 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1609 #define ST_REG_P(REGNO) \
1610 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1611 #define COP0_REG_P(REGNO) \
1612 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1613 #define COP2_REG_P(REGNO) \
1614 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1615 #define COP3_REG_P(REGNO) \
1616 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1617 #define ALL_COP_REG_P(REGNO) \
1618 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1620 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1622 /* Return coprocessor number from register number. */
1624 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1625 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1626 : COP3_REG_P (REGNO) ? '3' : '?')
1629 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1631 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1632 array built in override_options. Because machmodes.h is not yet
1633 included before this file is processed, the MODE bound can't be
1636 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1638 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1639 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1641 /* Value is 1 if it is a good idea to tie two pseudo registers
1642 when one has mode MODE1 and one has mode MODE2.
1643 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1644 for any hard reg, then this must be 0 for correct output. */
1645 #define MODES_TIEABLE_P(MODE1, MODE2) \
1646 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1647 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1648 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1649 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1651 /* Register to use for pushing function arguments. */
1652 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1654 /* Base register for access to local variables of the function. We
1655 pretend that the frame pointer is $1, and then eliminate it to
1656 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1657 a fixed register, and will not be used for anything else. */
1658 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1660 /* $30 is not available on the mips16, so we use $17 as the frame
1662 #define HARD_FRAME_POINTER_REGNUM \
1663 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1665 /* Value should be nonzero if functions must have frame pointers.
1666 Zero means the frame pointer need not be set up (and parms
1667 may be accessed via the stack pointer) in functions that seem suitable.
1668 This is computed in `reload', in reload1.c. */
1669 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1671 /* Base register for access to arguments of the function. */
1672 #define ARG_POINTER_REGNUM GP_REG_FIRST
1674 /* Register in which static-chain is passed to a function. */
1675 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1677 /* Pass structure addresses as an "invisible" first argument. */
1678 #define STRUCT_VALUE 0
1680 /* Registers used as temporaries in prologue/epilogue code. If we're
1681 generating mips16 code, these registers must come from the core set
1682 of 8. The prologue register mustn't conflict with any incoming
1683 arguments, the static chain pointer, or the frame pointer. The
1684 epilogue temporary mustn't conflict with the return registers, the
1685 frame pointer, the EH stack adjustment, or the EH data registers. */
1687 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1688 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1690 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1691 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1693 /* Define this macro if it is as good or better to call a constant
1694 function address than to call an address kept in a register. */
1695 #define NO_FUNCTION_CSE 1
1697 /* Define this macro if it is as good or better for a function to
1698 call itself with an explicit address than to call an address
1699 kept in a register. */
1700 #define NO_RECURSIVE_FUNCTION_CSE 1
1702 /* The ABI-defined global pointer. Sometimes we use a different
1703 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1704 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1706 /* We normally use $28 as the global pointer. However, when generating
1707 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1708 register instead. They can then avoid saving and restoring $28
1709 and perhaps avoid using a frame at all.
1711 When a leaf function uses something other than $28, mips_expand_prologue
1712 will modify pic_offset_table_rtx in place. Take the register number
1713 from there after reload. */
1714 #define PIC_OFFSET_TABLE_REGNUM \
1715 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1717 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1719 /* Define the classes of registers for register constraints in the
1720 machine description. Also define ranges of constants.
1722 One of the classes must always be named ALL_REGS and include all hard regs.
1723 If there is more than one class, another class must be named NO_REGS
1724 and contain no registers.
1726 The name GENERAL_REGS must be the name of a class (or an alias for
1727 another name such as ALL_REGS). This is the class of registers
1728 that is allowed by "g" or "r" in a register constraint.
1729 Also, registers outside this class are allocated only when
1730 instructions express preferences for them.
1732 The classes must be numbered in nondecreasing order; that is,
1733 a larger-numbered class must never be contained completely
1734 in a smaller-numbered class.
1736 For any two classes, it is very desirable that there be another
1737 class that represents their union. */
1741 NO_REGS, /* no registers in set */
1742 M16_NA_REGS, /* mips16 regs not used to pass args */
1743 M16_REGS, /* mips16 directly accessible registers */
1744 T_REG, /* mips16 T register ($24) */
1745 M16_T_REGS, /* mips16 registers plus T register */
1746 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1747 LEA_REGS, /* Every GPR except $25 */
1748 GR_REGS, /* integer registers */
1749 FP_REGS, /* floating point registers */
1750 HI_REG, /* hi register */
1751 LO_REG, /* lo register */
1752 MD_REGS, /* multiply/divide registers (hi/lo) */
1753 COP0_REGS, /* generic coprocessor classes */
1756 HI_AND_GR_REGS, /* union classes */
1763 ALL_COP_AND_GR_REGS,
1764 ST_REGS, /* status registers (fp status) */
1765 ALL_REGS, /* all registers */
1766 LIM_REG_CLASSES /* max value + 1 */
1769 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1771 #define GENERAL_REGS GR_REGS
1773 /* An initializer containing the names of the register classes as C
1774 string constants. These names are used in writing some of the
1777 #define REG_CLASS_NAMES \
1784 "PIC_FN_ADDR_REG", \
1791 /* coprocessor registers */ \
1798 "COP0_AND_GR_REGS", \
1799 "COP2_AND_GR_REGS", \
1800 "COP3_AND_GR_REGS", \
1802 "ALL_COP_AND_GR_REGS", \
1807 /* An initializer containing the contents of the register classes,
1808 as integers which are bit masks. The Nth integer specifies the
1809 contents of class N. The way the integer MASK is interpreted is
1810 that register R is in the class if `MASK & (1 << R)' is 1.
1812 When the machine has more than 32 registers, an integer does not
1813 suffice. Then the integers are replaced by sub-initializers,
1814 braced groupings containing several integers. Each
1815 sub-initializer must be suitable as an initializer for the type
1816 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1818 #define REG_CLASS_CONTENTS \
1820 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1821 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1822 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1823 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1824 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1825 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1826 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1827 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1828 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1829 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1830 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1831 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1832 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1833 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1834 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1835 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1836 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1837 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1838 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1839 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1840 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1841 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1842 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1843 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1844 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1848 /* A C expression whose value is a register class containing hard
1849 register REGNO. In general there is more that one such class;
1850 choose a class which is "minimal", meaning that no smaller class
1851 also contains the register. */
1853 extern const enum reg_class mips_regno_to_class[];
1855 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1857 /* A macro whose definition is the name of the class to which a
1858 valid base register must belong. A base register is one used in
1859 an address which is the register value plus a displacement. */
1861 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1863 /* A macro whose definition is the name of the class to which a
1864 valid index register must belong. An index register is one used
1865 in an address where its value is either multiplied by a scale
1866 factor or added to another register (as well as added to a
1869 #define INDEX_REG_CLASS NO_REGS
1871 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1872 registers explicitly used in the rtl to be used as spill registers
1873 but prevents the compiler from extending the lifetime of these
1876 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1878 /* This macro is used later on in the file. */
1879 #define GR_REG_CLASS_P(CLASS) \
1880 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1881 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1882 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1884 /* This macro is also used later on in the file. */
1885 #define COP_REG_CLASS_P(CLASS) \
1886 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1888 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1889 is the default value (allocate the registers in numeric order). We
1890 define it just so that we can override it for the mips16 target in
1891 ORDER_REGS_FOR_LOCAL_ALLOC. */
1893 #define REG_ALLOC_ORDER \
1894 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1895 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1896 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1897 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1898 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1899 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1900 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1901 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1902 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1903 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1904 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1907 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1908 to be rearranged based on a particular function. On the mips16, we
1909 want to allocate $24 (T_REG) before other registers for
1910 instructions for which it is possible. */
1912 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1914 /* REGISTER AND CONSTANT CLASSES */
1916 /* Get reg_class from a letter such as appears in the machine
1919 DEFINED REGISTER CLASSES:
1921 'd' General (aka integer) registers
1922 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1923 'y' General registers (in both mips16 and non mips16 mode)
1924 'e' mips16 non argument registers (M16_NA_REGS)
1925 't' mips16 temporary register ($24)
1926 'f' Floating point registers
1929 'x' Multiply/divide registers
1930 'z' FP Status register
1934 'b' All registers */
1936 extern enum reg_class mips_char_to_class[256];
1938 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1940 /* True if VALUE is a signed 16-bit number. */
1942 #define SMALL_OPERAND(VALUE) \
1943 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1945 /* True if VALUE is an unsigned 16-bit number. */
1947 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1948 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1950 /* True if VALUE can be loaded into a register using LUI. */
1952 #define LUI_OPERAND(VALUE) \
1953 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1954 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1956 /* Return a value X with the low 16 bits clear, and such that
1957 VALUE - X is a signed 16-bit value. */
1959 #define CONST_HIGH_PART(VALUE) \
1960 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1962 #define CONST_LOW_PART(VALUE) \
1963 ((VALUE) - CONST_HIGH_PART (VALUE))
1965 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1966 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1967 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1969 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1970 string can be used to stand for particular ranges of immediate
1971 operands. This macro defines what the ranges are. C is the
1972 letter, and VALUE is a constant value. Return 1 if VALUE is
1973 in the range specified by C. */
1977 `I' is used for the range of constants an arithmetic insn can
1978 actually contain (16 bits signed integers).
1980 `J' is used for the range which is just zero (ie, $r0).
1982 `K' is used for the range of constants a logical insn can actually
1983 contain (16 bit zero-extended integers).
1985 `L' is used for the range of constants that be loaded with lui
1986 (ie, the bottom 16 bits are zero).
1988 `M' is used for the range of constants that take two words to load
1989 (ie, not matched by `I', `K', and `L').
1991 `N' is used for negative 16 bit constants other than -65536.
1993 `O' is a 15 bit signed integer.
1995 `P' is used for positive 16 bit constants. */
1997 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1998 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1999 : (C) == 'J' ? ((VALUE) == 0) \
2000 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2001 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2002 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2003 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2004 && !LUI_OPERAND (VALUE)) \
2005 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2006 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2007 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2010 /* Similar, but for floating constants, and defining letters G and H.
2011 Here VALUE is the CONST_DOUBLE rtx itself. */
2015 'G' : Floating point 0 */
2017 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2019 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2021 /* True if OP is a constant that should not be moved into $25.
2022 We need this because many versions of gas treat 'la $25,foo' as
2023 part of a call sequence and allow a global 'foo' to be lazily bound. */
2025 #define DANGEROUS_FOR_LA25_P(OP) \
2027 && !TARGET_EXPLICIT_RELOCS \
2028 && mips_global_pic_constant_p (OP))
2030 /* Letters in the range `Q' through `U' may be defined in a
2031 machine-dependent fashion to stand for arbitrary operand types.
2032 The machine description macro `EXTRA_CONSTRAINT' is passed the
2033 operand as its first argument and the constraint letter as its
2036 `Q' is for signed 16-bit constants.
2037 `R' is for single-instruction memory references. Note that this
2038 constraint has often been used in linux and glibc code.
2039 `S' is for legitimate constant call addresses.
2040 `T' is for constant move_operands that cannot be safely loaded into $25.
2041 `U' is for constant move_operands that can be safely loaded into $25.
2042 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2043 This is true for all non-mips16 references (although it can somtimes
2044 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2045 stack and constant-pool references. */
2047 #define EXTRA_CONSTRAINT(OP,CODE) \
2048 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2049 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2050 && mips_fetch_insns (OP) == 1) \
2051 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2052 && call_insn_operand (OP, VOIDmode)) \
2053 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2054 && move_operand (OP, VOIDmode) \
2055 && DANGEROUS_FOR_LA25_P (OP)) \
2056 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2057 && move_operand (OP, VOIDmode) \
2058 && !DANGEROUS_FOR_LA25_P (OP)) \
2059 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2060 && memory_operand (OP, VOIDmode) \
2061 && (!TARGET_MIPS16 \
2062 || (!stack_operand (OP, VOIDmode) \
2063 && !CONSTANT_P (XEXP (OP, 0))))) \
2066 /* Say which of the above are memory constraints. */
2067 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2069 /* Given an rtx X being reloaded into a reg required to be
2070 in class CLASS, return the class of reg to actually use.
2071 In general this is just CLASS; but on some machines
2072 in some cases it is preferable to use a more restrictive class. */
2074 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2075 ((CLASS) != ALL_REGS \
2076 ? (! TARGET_MIPS16 \
2078 : ((CLASS) != GR_REGS \
2081 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2082 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2083 ? (TARGET_SOFT_FLOAT \
2084 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2086 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2087 || GET_MODE (X) == VOIDmode) \
2088 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2091 /* Certain machines have the property that some registers cannot be
2092 copied to some other registers without using memory. Define this
2093 macro on those machines to be a C expression that is nonzero if
2094 objects of mode MODE in registers of CLASS1 can only be copied to
2095 registers of class CLASS2 by storing a register of CLASS1 into
2096 memory and loading that memory location into a register of CLASS2.
2098 Do not define this macro if its value would always be zero. */
2100 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2101 ((!TARGET_DEBUG_H_MODE \
2102 && GET_MODE_CLASS (MODE) == MODE_INT \
2103 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2104 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2105 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2106 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2107 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2109 /* The HI and LO registers can only be reloaded via the general
2110 registers. Condition code registers can only be loaded to the
2111 general registers, and from the floating point registers. */
2113 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2114 mips_secondary_reload_class (CLASS, MODE, X, 1)
2115 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2116 mips_secondary_reload_class (CLASS, MODE, X, 0)
2118 /* Return the maximum number of consecutive registers
2119 needed to represent mode MODE in a register of class CLASS. */
2121 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2123 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2124 mips_cannot_change_mode_class (FROM, TO, CLASS)
2126 /* Stack layout; function entry, exit and calling. */
2128 #define STACK_GROWS_DOWNWARD
2130 /* The offset of the first local variable from the beginning of the frame.
2131 See compute_frame_size for details about the frame layout. */
2132 #define STARTING_FRAME_OFFSET \
2133 (current_function_outgoing_args_size \
2134 + (TARGET_ABICALLS && !TARGET_NEWABI \
2135 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2137 #define RETURN_ADDR_RTX mips_return_addr
2139 /* Since the mips16 ISA mode is encoded in the least-significant bit
2140 of the address, mask it off return addresses for purposes of
2141 finding exception handling regions. */
2143 #define MASK_RETURN_ADDR GEN_INT (-2)
2146 /* Similarly, don't use the least-significant bit to tell pointers to
2147 code from vtable index. */
2149 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2151 /* The eliminations to $17 are only used for mips16 code. See the
2152 definition of HARD_FRAME_POINTER_REGNUM. */
2154 #define ELIMINABLE_REGS \
2155 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2156 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2157 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2158 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2159 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2160 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2162 /* We can always eliminate to the hard frame pointer. We can eliminate
2163 to the stack pointer unless a frame pointer is needed.
2165 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2166 reload may be unable to compute the address of a local variable,
2167 since there is no way to add a large constant to the stack pointer
2168 without using a temporary register. */
2169 #define CAN_ELIMINATE(FROM, TO) \
2170 ((TO) == HARD_FRAME_POINTER_REGNUM \
2171 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2172 && (!TARGET_MIPS16 \
2173 || compute_frame_size (get_frame_size ()) < 32768)))
2175 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2176 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2178 /* Allocate stack space for arguments at the beginning of each function. */
2179 #define ACCUMULATE_OUTGOING_ARGS 1
2181 /* The argument pointer always points to the first argument. */
2182 #define FIRST_PARM_OFFSET(FNDECL) 0
2184 /* o32 and o64 reserve stack space for all argument registers. */
2185 #define REG_PARM_STACK_SPACE(FNDECL) \
2186 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2187 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2190 /* Define this if it is the responsibility of the caller to
2191 allocate the area reserved for arguments passed in registers.
2192 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2193 of this macro is to determine whether the space is included in
2194 `current_function_outgoing_args_size'. */
2195 #define OUTGOING_REG_PARM_STACK_SPACE
2197 #define STACK_BOUNDARY \
2198 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2202 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2204 /* Symbolic macros for the registers used to return integer and floating
2207 #define GP_RETURN (GP_REG_FIRST + 2)
2208 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2210 #define MAX_ARGS_IN_REGISTERS \
2211 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2213 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2215 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2217 /* Symbolic macros for the first/last argument registers. */
2219 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2220 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2221 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2222 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2224 #define LIBCALL_VALUE(MODE) \
2225 mips_function_value (NULL_TREE, NULL, (MODE))
2227 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2228 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2230 /* 1 if N is a possible register number for a function value.
2231 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2232 Currently, R2 and F0 are only implemented here (C has no complex type) */
2234 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2235 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2236 && (N) == FP_RETURN + 2))
2238 /* 1 if N is a possible register number for function argument passing.
2239 We have no FP argument registers when soft-float. When FP registers
2240 are 32 bits, we can't directly reference the odd numbered ones. */
2242 #define FUNCTION_ARG_REGNO_P(N) \
2243 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2244 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2245 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2248 #define RETURN_IN_MEMORY(TYPE) mips_return_in_memory (TYPE)
2250 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2251 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2254 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2256 /* This structure has to cope with two different argument allocation
2257 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2258 first N words go in registers and the rest go on the stack. If I < N,
2259 the Ith word might go in Ith integer argument register or the
2260 Ith floating-point one. For these ABIs, we only need to remember
2261 the number of words passed so far.
2263 The EABI instead allocates the integer and floating-point arguments
2264 separately. The first N words of FP arguments go in FP registers,
2265 the rest go on the stack. Likewise, the first N words of the other
2266 arguments go in integer registers, and the rest go on the stack. We
2267 need to maintain three counts: the number of integer registers used,
2268 the number of floating-point registers used, and the number of words
2269 passed on the stack.
2271 We could keep separate information for the two ABIs (a word count for
2272 the standard ABIs, and three separate counts for the EABI). But it
2273 seems simpler to view the standard ABIs as forms of EABI that do not
2274 allocate floating-point registers.
2276 So for the standard ABIs, the first N words are allocated to integer
2277 registers, and function_arg decides on an argument-by-argument basis
2278 whether that argument should really go in an integer register, or in
2279 a floating-point one. */
2281 typedef struct mips_args {
2282 /* Always true for varargs functions. Otherwise true if at least
2283 one argument has been passed in an integer register. */
2286 /* The number of arguments seen so far. */
2287 unsigned int arg_number;
2289 /* For EABI, the number of integer registers used so far. For other
2290 ABIs, the number of words passed in registers (whether integer
2291 or floating-point). */
2292 unsigned int num_gprs;
2294 /* For EABI, the number of floating-point registers used so far. */
2295 unsigned int num_fprs;
2297 /* The number of words passed on the stack. */
2298 unsigned int stack_words;
2300 /* On the mips16, we need to keep track of which floating point
2301 arguments were passed in general registers, but would have been
2302 passed in the FP regs if this were a 32 bit function, so that we
2303 can move them to the FP regs if we wind up calling a 32 bit
2304 function. We record this information in fp_code, encoded in base
2305 four. A zero digit means no floating point argument, a one digit
2306 means an SFmode argument, and a two digit means a DFmode argument,
2307 and a three digit is not used. The low order digit is the first
2308 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2309 an SFmode argument. ??? A more sophisticated approach will be
2310 needed if MIPS_ABI != ABI_32. */
2313 /* True if the function has a prototype. */
2317 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2318 for a call to a function whose data type is FNTYPE.
2319 For a library call, FNTYPE is 0.
2323 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2324 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2326 /* Update the data in CUM to advance over an argument
2327 of mode MODE and data type TYPE.
2328 (TYPE is null for libcalls where that information may not be available.) */
2330 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2331 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2333 /* Determine where to put an argument to a function.
2334 Value is zero to push the argument on the stack,
2335 or a hard register in which to store the argument.
2337 MODE is the argument's machine mode.
2338 TYPE is the data type of the argument (as a tree).
2339 This is null for libcalls where that information may
2341 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2342 the preceding args and about the function being called.
2343 NAMED is nonzero if this argument is a named parameter
2344 (otherwise it is an extra parameter matching an ellipsis). */
2346 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2347 function_arg( &CUM, MODE, TYPE, NAMED)
2349 /* For an arg passed partly in registers and partly in memory,
2350 this is the number of registers used.
2351 For args passed entirely in registers or entirely in memory, zero. */
2353 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2354 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2356 /* If defined, a C expression that gives the alignment boundary, in
2357 bits, of an argument with the specified mode and type. If it is
2358 not defined, `PARM_BOUNDARY' is used for all arguments. */
2360 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2362 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2364 : TYPE_ALIGN(TYPE)) \
2365 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2367 : GET_MODE_ALIGNMENT(MODE)))
2369 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2370 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2372 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2373 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2375 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2376 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2378 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2379 (mips_abi == ABI_EABI && (NAMED) \
2380 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2382 /* Modified version of the macro in expr.h. Only return true if
2383 the type has a variable size or if the front end requires it
2384 to be passed by reference. */
2385 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2387 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2388 || TREE_ADDRESSABLE (TYPE)))
2390 /* True if using EABI and varargs can be passed in floating-point
2391 registers. Under these conditions, we need a more complex form
2392 of va_list, which tracks GPR, FPR and stack arguments separately. */
2393 #define EABI_FLOAT_VARARGS_P \
2394 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2397 /* Say that the epilogue uses the return address register. Note that
2398 in the case of sibcalls, the values "used by the epilogue" are
2399 considered live at the start of the called function. */
2400 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2402 /* Treat LOC as a byte offset from the stack pointer and round it up
2403 to the next fully-aligned offset. */
2404 #define MIPS_STACK_ALIGN(LOC) \
2405 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2406 ? ((LOC) + 7) & ~7 \
2407 : ((LOC) + 15) & ~15)
2410 /* Define the `__builtin_va_list' type for the ABI. */
2411 #define BUILD_VA_LIST_TYPE(VALIST) \
2412 (VALIST) = mips_build_va_list ()
2414 /* Implement `va_start' for varargs and stdarg. */
2415 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2416 mips_va_start (valist, nextarg)
2418 /* Implement `va_arg'. */
2419 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2420 mips_va_arg (valist, type)
2422 /* Output assembler code to FILE to increment profiler label # LABELNO
2423 for profiling a function entry. */
2425 #define FUNCTION_PROFILER(FILE, LABELNO) \
2427 if (TARGET_MIPS16) \
2428 sorry ("mips16 function profiling"); \
2429 fprintf (FILE, "\t.set\tnoat\n"); \
2430 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2431 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2432 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2435 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2436 TARGET_64BIT ? "dsubu" : "subu", \
2437 reg_names[STACK_POINTER_REGNUM], \
2438 reg_names[STACK_POINTER_REGNUM], \
2439 Pmode == DImode ? 16 : 8); \
2441 fprintf (FILE, "\tjal\t_mcount\n"); \
2442 fprintf (FILE, "\t.set\tat\n"); \
2445 /* Define this macro if the code for function profiling should come
2446 before the function prologue. Normally, the profiling code comes
2449 /* #define PROFILE_BEFORE_PROLOGUE */
2451 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2452 the stack pointer does not matter. The value is tested only in
2453 functions that have frame pointers.
2454 No definition is equivalent to always zero. */
2456 #define EXIT_IGNORE_STACK 1
2459 /* A C statement to output, on the stream FILE, assembler code for a
2460 block of data that contains the constant parts of a trampoline.
2461 This code should not include a label--the label is taken care of
2464 #define TRAMPOLINE_TEMPLATE(STREAM) \
2466 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2467 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2468 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2469 if (ptr_mode == DImode) \
2471 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2472 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2476 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2477 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2479 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2480 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2481 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2482 if (ptr_mode == DImode) \
2484 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2485 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2489 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2490 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2494 /* A C expression for the size in bytes of the trampoline, as an
2497 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2499 /* Alignment required for trampolines, in bits. */
2501 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2503 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2504 program and data caches. */
2506 #ifndef CACHE_FLUSH_FUNC
2507 #define CACHE_FLUSH_FUNC "_flush_cache"
2510 /* A C statement to initialize the variable parts of a trampoline.
2511 ADDR is an RTX for the address of the trampoline; FNADDR is an
2512 RTX for the address of the nested function; STATIC_CHAIN is an
2513 RTX for the static chain value that should be passed to the
2514 function when it is called. */
2516 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2518 rtx func_addr, chain_addr; \
2520 func_addr = plus_constant (ADDR, 32); \
2521 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2522 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2523 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2524 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2525 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
2527 /* Flush both caches. We need to flush the data cache in case \
2528 the system has a write-back cache. */ \
2529 /* ??? Should check the return value for errors. */ \
2530 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2531 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2532 0, VOIDmode, 3, ADDR, Pmode, \
2533 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2534 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2537 /* Addressing modes, and classification of registers for them. */
2539 /* These assume that REGNO is a hard or pseudo reg number.
2540 They give nonzero only if REGNO is a hard reg of the suitable class
2541 or a pseudo reg currently allocated to a suitable hard reg.
2542 These definitions are NOT overridden anywhere. */
2544 #define BASE_REG_P(regno, mode) \
2546 ? (M16_REG_P (regno) \
2547 || (regno) == FRAME_POINTER_REGNUM \
2548 || (regno) == ARG_POINTER_REGNUM \
2549 || ((regno) == STACK_POINTER_REGNUM \
2550 && (GET_MODE_SIZE (mode) == 4 \
2551 || GET_MODE_SIZE (mode) == 8))) \
2554 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2555 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2558 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2559 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2561 #define REGNO_OK_FOR_INDEX_P(regno) 0
2562 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2563 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2565 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2566 and check its validity for a certain class.
2567 We have two alternate definitions for each of them.
2568 The usual definition accepts all pseudo regs; the other rejects them all.
2569 The symbol REG_OK_STRICT causes the latter definition to be used.
2571 Most source files want to accept pseudo regs in the hope that
2572 they will get allocated to the class that the insn wants them to be in.
2573 Some source files that are used after register allocation
2574 need to be strict. */
2576 #ifndef REG_OK_STRICT
2577 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2578 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2580 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2581 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2584 #define REG_OK_FOR_INDEX_P(X) 0
2587 /* Maximum number of registers that can appear in a valid memory address. */
2589 #define MAX_REGS_PER_ADDRESS 1
2591 /* A C compound statement with a conditional `goto LABEL;' executed
2592 if X (an RTX) is a legitimate memory address on the target
2593 machine for a memory operand of mode MODE. */
2596 #define GO_PRINTF(x) fprintf(stderr, (x))
2597 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2598 #define GO_DEBUG_RTX(x) debug_rtx(x)
2601 #define GO_PRINTF(x)
2602 #define GO_PRINTF2(x,y)
2603 #define GO_DEBUG_RTX(x)
2606 #ifdef REG_OK_STRICT
2607 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2609 if (mips_legitimate_address_p (MODE, X, 1)) \
2613 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2615 if (mips_legitimate_address_p (MODE, X, 0)) \
2620 /* Check for constness inline but use mips_legitimate_address_p
2621 to check whether a constant really is an address. */
2623 #define CONSTANT_ADDRESS_P(X) \
2624 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2626 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2628 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2630 if (mips_legitimize_address (&(X), MODE)) \
2635 /* A C statement or compound statement with a conditional `goto
2636 LABEL;' executed if memory address X (an RTX) can have different
2637 meanings depending on the machine mode of the memory reference it
2640 Autoincrement and autodecrement addresses typically have
2641 mode-dependent effects because the amount of the increment or
2642 decrement is the size of the operand being addressed. Some
2643 machines have other mode-dependent addresses. Many RISC machines
2644 have no mode-dependent addresses.
2646 You may assume that ADDR is a valid address for the machine. */
2648 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2650 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2651 'the start of the function that this code is output in'. */
2653 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2654 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2655 asm_fprintf ((FILE), "%U%s", \
2656 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2658 asm_fprintf ((FILE), "%U%s", (NAME))
2660 /* The mips16 wants the constant pool to be after the function,
2661 because the PC relative load instructions use unsigned offsets. */
2663 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
2665 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
2666 mips_string_length = 0;
2668 /* Specify the machine mode that this machine uses
2669 for the index in the tablejump instruction.
2670 ??? Using HImode in mips16 mode can cause overflow. */
2671 #define CASE_VECTOR_MODE \
2672 (TARGET_MIPS16 ? HImode : ptr_mode)
2674 /* Define as C expression which evaluates to nonzero if the tablejump
2675 instruction expects the table to contain offsets from the address of the
2677 Do not define this if the table should contain absolute addresses. */
2678 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2680 /* Define this as 1 if `char' should by default be signed; else as 0. */
2681 #ifndef DEFAULT_SIGNED_CHAR
2682 #define DEFAULT_SIGNED_CHAR 1
2685 /* Max number of bytes we can move from memory to memory
2686 in one reasonably fast instruction. */
2687 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2688 #define MAX_MOVE_MAX 8
2690 /* Define this macro as a C expression which is nonzero if
2691 accessing less than a word of memory (i.e. a `char' or a
2692 `short') is no faster than accessing a word of memory, i.e., if
2693 such access require more than one instruction or if there is no
2694 difference in cost between byte and (aligned) word loads.
2696 On RISC machines, it tends to generate better code to define
2697 this as 1, since it avoids making a QI or HI mode register. */
2698 #define SLOW_BYTE_ACCESS 1
2700 /* Define this to be nonzero if shift instructions ignore all but the low-order
2702 #define SHIFT_COUNT_TRUNCATED 1
2704 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2705 is done just by pretending it is already truncated. */
2706 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2707 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2710 /* Specify the machine mode that pointers have.
2711 After generation of rtl, the compiler makes no further distinction
2712 between pointers and any other objects of this machine mode. */
2715 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2718 /* Give call MEMs SImode since it is the "most permissive" mode
2719 for both 32-bit and 64-bit targets. */
2721 #define FUNCTION_MODE SImode
2724 /* The cost of loading values from the constant pool. It should be
2725 larger than the cost of any constant we want to synthesize in-line. */
2727 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2729 /* A C expression for the cost of moving data from a register in
2730 class FROM to one in class TO. The classes are expressed using
2731 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2732 the default; other values are interpreted relative to that.
2734 It is not required that the cost always equal 2 when FROM is the
2735 same as TO; on some machines it is expensive to move between
2736 registers if they are not general registers.
2738 If reload sees an insn consisting of a single `set' between two
2739 hard registers, and if `REGISTER_MOVE_COST' applied to their
2740 classes returns a value of 2, reload does not check to ensure
2741 that the constraints of the insn are met. Setting a cost of
2742 other than 2 will allow reload to verify that the constraints are
2743 met. You should do this if the `movM' pattern's constraints do
2744 not allow such copying. */
2746 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2747 mips_register_move_cost (MODE, FROM, TO)
2749 /* ??? Fix this to be right for the R8000. */
2750 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2751 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2752 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2754 /* Define if copies to/from condition code registers should be avoided.
2756 This is needed for the MIPS because reload_outcc is not complete;
2757 it needs to handle cases where the source is a general or another
2758 condition code register. */
2759 #define AVOID_CCMODE_COPIES
2761 /* A C expression for the cost of a branch instruction. A value of
2762 1 is the default; other values are interpreted relative to that. */
2764 /* ??? Fix this to be right for the R8000. */
2765 #define BRANCH_COST \
2767 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2770 /* If defined, modifies the length assigned to instruction INSN as a
2771 function of the context in which it is used. LENGTH is an lvalue
2772 that contains the initially computed length of the insn and should
2773 be updated with the correct length of the insn. */
2774 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2775 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2778 /* Optionally define this if you have added predicates to
2779 `MACHINE.c'. This macro is called within an initializer of an
2780 array of structures. The first field in the structure is the
2781 name of a predicate and the second field is an array of rtl
2782 codes. For each predicate, list all rtl codes that can be in
2783 expressions matched by the predicate. The list should have a
2784 trailing comma. Here is an example of two entries in the list
2785 for a typical RISC machine:
2787 #define PREDICATE_CODES \
2788 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2789 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2791 Defining this macro does not affect the generated code (however,
2792 incorrect definitions that omit an rtl code that may be matched
2793 by the predicate can cause the compiler to malfunction).
2794 Instead, it allows the table built by `genrecog' to be more
2795 compact and efficient, thus speeding up the compiler. The most
2796 important predicates to include in the list specified by this
2797 macro are thoses used in the most insn patterns. */
2799 #define PREDICATE_CODES \
2800 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2801 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2802 {"const_arith_operand", { CONST, CONST_INT }}, \
2803 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2804 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2805 {"small_int", { CONST_INT }}, \
2806 {"mips_const_double_ok", { CONST_DOUBLE }}, \
2807 {"const_float_1_operand", { CONST_DOUBLE }}, \
2808 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2809 {"simple_memory_operand", { MEM, SUBREG }}, \
2810 {"equality_op", { EQ, NE }}, \
2811 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2813 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2814 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2815 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2816 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2817 SYMBOL_REF, LABEL_REF, SUBREG, \
2819 {"stack_operand", { MEM }}, \
2820 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2821 CONST_DOUBLE, CONST }}, \
2822 {"fcc_register_operand", { REG, SUBREG }}, \
2823 {"hilo_operand", { REG }}, \
2824 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2826 /* A list of predicates that do special things with modes, and so
2827 should not elicit warnings for VOIDmode match_operand. */
2829 #define SPECIAL_MODE_PREDICATES \
2830 "pc_or_label_operand",
2832 /* Control the assembler format that we output. */
2834 /* Output to assembler file text saying following lines
2835 may contain character constants, extra white space, comments, etc. */
2838 #define ASM_APP_ON " #APP\n"
2841 /* Output to assembler file text saying following lines
2842 no longer contain unusual constructs. */
2845 #define ASM_APP_OFF " #NO_APP\n"
2848 /* How to refer to registers in assembler output.
2849 This sequence is indexed by compiler's hard-register-number (see above).
2851 In order to support the two different conventions for register names,
2852 we use the name of a table set up in mips.c, which is overwritten
2853 if -mrnames is used. */
2855 #define REGISTER_NAMES \
2857 &mips_reg_names[ 0][0], \
2858 &mips_reg_names[ 1][0], \
2859 &mips_reg_names[ 2][0], \
2860 &mips_reg_names[ 3][0], \
2861 &mips_reg_names[ 4][0], \
2862 &mips_reg_names[ 5][0], \
2863 &mips_reg_names[ 6][0], \
2864 &mips_reg_names[ 7][0], \
2865 &mips_reg_names[ 8][0], \
2866 &mips_reg_names[ 9][0], \
2867 &mips_reg_names[10][0], \
2868 &mips_reg_names[11][0], \
2869 &mips_reg_names[12][0], \
2870 &mips_reg_names[13][0], \
2871 &mips_reg_names[14][0], \
2872 &mips_reg_names[15][0], \
2873 &mips_reg_names[16][0], \
2874 &mips_reg_names[17][0], \
2875 &mips_reg_names[18][0], \
2876 &mips_reg_names[19][0], \
2877 &mips_reg_names[20][0], \
2878 &mips_reg_names[21][0], \
2879 &mips_reg_names[22][0], \
2880 &mips_reg_names[23][0], \
2881 &mips_reg_names[24][0], \
2882 &mips_reg_names[25][0], \
2883 &mips_reg_names[26][0], \
2884 &mips_reg_names[27][0], \
2885 &mips_reg_names[28][0], \
2886 &mips_reg_names[29][0], \
2887 &mips_reg_names[30][0], \
2888 &mips_reg_names[31][0], \
2889 &mips_reg_names[32][0], \
2890 &mips_reg_names[33][0], \
2891 &mips_reg_names[34][0], \
2892 &mips_reg_names[35][0], \
2893 &mips_reg_names[36][0], \
2894 &mips_reg_names[37][0], \
2895 &mips_reg_names[38][0], \
2896 &mips_reg_names[39][0], \
2897 &mips_reg_names[40][0], \
2898 &mips_reg_names[41][0], \
2899 &mips_reg_names[42][0], \
2900 &mips_reg_names[43][0], \
2901 &mips_reg_names[44][0], \
2902 &mips_reg_names[45][0], \
2903 &mips_reg_names[46][0], \
2904 &mips_reg_names[47][0], \
2905 &mips_reg_names[48][0], \
2906 &mips_reg_names[49][0], \
2907 &mips_reg_names[50][0], \
2908 &mips_reg_names[51][0], \
2909 &mips_reg_names[52][0], \
2910 &mips_reg_names[53][0], \
2911 &mips_reg_names[54][0], \
2912 &mips_reg_names[55][0], \
2913 &mips_reg_names[56][0], \
2914 &mips_reg_names[57][0], \
2915 &mips_reg_names[58][0], \
2916 &mips_reg_names[59][0], \
2917 &mips_reg_names[60][0], \
2918 &mips_reg_names[61][0], \
2919 &mips_reg_names[62][0], \
2920 &mips_reg_names[63][0], \
2921 &mips_reg_names[64][0], \
2922 &mips_reg_names[65][0], \
2923 &mips_reg_names[66][0], \
2924 &mips_reg_names[67][0], \
2925 &mips_reg_names[68][0], \
2926 &mips_reg_names[69][0], \
2927 &mips_reg_names[70][0], \
2928 &mips_reg_names[71][0], \
2929 &mips_reg_names[72][0], \
2930 &mips_reg_names[73][0], \
2931 &mips_reg_names[74][0], \
2932 &mips_reg_names[75][0], \
2933 &mips_reg_names[76][0], \
2934 &mips_reg_names[77][0], \
2935 &mips_reg_names[78][0], \
2936 &mips_reg_names[79][0], \
2937 &mips_reg_names[80][0], \
2938 &mips_reg_names[81][0], \
2939 &mips_reg_names[82][0], \
2940 &mips_reg_names[83][0], \
2941 &mips_reg_names[84][0], \
2942 &mips_reg_names[85][0], \
2943 &mips_reg_names[86][0], \
2944 &mips_reg_names[87][0], \
2945 &mips_reg_names[88][0], \
2946 &mips_reg_names[89][0], \
2947 &mips_reg_names[90][0], \
2948 &mips_reg_names[91][0], \
2949 &mips_reg_names[92][0], \
2950 &mips_reg_names[93][0], \
2951 &mips_reg_names[94][0], \
2952 &mips_reg_names[95][0], \
2953 &mips_reg_names[96][0], \
2954 &mips_reg_names[97][0], \
2955 &mips_reg_names[98][0], \
2956 &mips_reg_names[99][0], \
2957 &mips_reg_names[100][0], \
2958 &mips_reg_names[101][0], \
2959 &mips_reg_names[102][0], \
2960 &mips_reg_names[103][0], \
2961 &mips_reg_names[104][0], \
2962 &mips_reg_names[105][0], \
2963 &mips_reg_names[106][0], \
2964 &mips_reg_names[107][0], \
2965 &mips_reg_names[108][0], \
2966 &mips_reg_names[109][0], \
2967 &mips_reg_names[110][0], \
2968 &mips_reg_names[111][0], \
2969 &mips_reg_names[112][0], \
2970 &mips_reg_names[113][0], \
2971 &mips_reg_names[114][0], \
2972 &mips_reg_names[115][0], \
2973 &mips_reg_names[116][0], \
2974 &mips_reg_names[117][0], \
2975 &mips_reg_names[118][0], \
2976 &mips_reg_names[119][0], \
2977 &mips_reg_names[120][0], \
2978 &mips_reg_names[121][0], \
2979 &mips_reg_names[122][0], \
2980 &mips_reg_names[123][0], \
2981 &mips_reg_names[124][0], \
2982 &mips_reg_names[125][0], \
2983 &mips_reg_names[126][0], \
2984 &mips_reg_names[127][0], \
2985 &mips_reg_names[128][0], \
2986 &mips_reg_names[129][0], \
2987 &mips_reg_names[130][0], \
2988 &mips_reg_names[131][0], \
2989 &mips_reg_names[132][0], \
2990 &mips_reg_names[133][0], \
2991 &mips_reg_names[134][0], \
2992 &mips_reg_names[135][0], \
2993 &mips_reg_names[136][0], \
2994 &mips_reg_names[137][0], \
2995 &mips_reg_names[138][0], \
2996 &mips_reg_names[139][0], \
2997 &mips_reg_names[140][0], \
2998 &mips_reg_names[141][0], \
2999 &mips_reg_names[142][0], \
3000 &mips_reg_names[143][0], \
3001 &mips_reg_names[144][0], \
3002 &mips_reg_names[145][0], \
3003 &mips_reg_names[146][0], \
3004 &mips_reg_names[147][0], \
3005 &mips_reg_names[148][0], \
3006 &mips_reg_names[149][0], \
3007 &mips_reg_names[150][0], \
3008 &mips_reg_names[151][0], \
3009 &mips_reg_names[152][0], \
3010 &mips_reg_names[153][0], \
3011 &mips_reg_names[154][0], \
3012 &mips_reg_names[155][0], \
3013 &mips_reg_names[156][0], \
3014 &mips_reg_names[157][0], \
3015 &mips_reg_names[158][0], \
3016 &mips_reg_names[159][0], \
3017 &mips_reg_names[160][0], \
3018 &mips_reg_names[161][0], \
3019 &mips_reg_names[162][0], \
3020 &mips_reg_names[163][0], \
3021 &mips_reg_names[164][0], \
3022 &mips_reg_names[165][0], \
3023 &mips_reg_names[166][0], \
3024 &mips_reg_names[167][0], \
3025 &mips_reg_names[168][0], \
3026 &mips_reg_names[169][0], \
3027 &mips_reg_names[170][0], \
3028 &mips_reg_names[171][0], \
3029 &mips_reg_names[172][0], \
3030 &mips_reg_names[173][0], \
3031 &mips_reg_names[174][0], \
3032 &mips_reg_names[175][0] \
3035 /* If defined, a C initializer for an array of structures
3036 containing a name and a register number. This macro defines
3037 additional names for hard registers, thus allowing the `asm'
3038 option in declarations to refer to registers using alternate
3041 We define both names for the integer registers here. */
3043 #define ADDITIONAL_REGISTER_NAMES \
3045 { "$0", 0 + GP_REG_FIRST }, \
3046 { "$1", 1 + GP_REG_FIRST }, \
3047 { "$2", 2 + GP_REG_FIRST }, \
3048 { "$3", 3 + GP_REG_FIRST }, \
3049 { "$4", 4 + GP_REG_FIRST }, \
3050 { "$5", 5 + GP_REG_FIRST }, \
3051 { "$6", 6 + GP_REG_FIRST }, \
3052 { "$7", 7 + GP_REG_FIRST }, \
3053 { "$8", 8 + GP_REG_FIRST }, \
3054 { "$9", 9 + GP_REG_FIRST }, \
3055 { "$10", 10 + GP_REG_FIRST }, \
3056 { "$11", 11 + GP_REG_FIRST }, \
3057 { "$12", 12 + GP_REG_FIRST }, \
3058 { "$13", 13 + GP_REG_FIRST }, \
3059 { "$14", 14 + GP_REG_FIRST }, \
3060 { "$15", 15 + GP_REG_FIRST }, \
3061 { "$16", 16 + GP_REG_FIRST }, \
3062 { "$17", 17 + GP_REG_FIRST }, \
3063 { "$18", 18 + GP_REG_FIRST }, \
3064 { "$19", 19 + GP_REG_FIRST }, \
3065 { "$20", 20 + GP_REG_FIRST }, \
3066 { "$21", 21 + GP_REG_FIRST }, \
3067 { "$22", 22 + GP_REG_FIRST }, \
3068 { "$23", 23 + GP_REG_FIRST }, \
3069 { "$24", 24 + GP_REG_FIRST }, \
3070 { "$25", 25 + GP_REG_FIRST }, \
3071 { "$26", 26 + GP_REG_FIRST }, \
3072 { "$27", 27 + GP_REG_FIRST }, \
3073 { "$28", 28 + GP_REG_FIRST }, \
3074 { "$29", 29 + GP_REG_FIRST }, \
3075 { "$30", 30 + GP_REG_FIRST }, \
3076 { "$31", 31 + GP_REG_FIRST }, \
3077 { "$sp", 29 + GP_REG_FIRST }, \
3078 { "$fp", 30 + GP_REG_FIRST }, \
3079 { "at", 1 + GP_REG_FIRST }, \
3080 { "v0", 2 + GP_REG_FIRST }, \
3081 { "v1", 3 + GP_REG_FIRST }, \
3082 { "a0", 4 + GP_REG_FIRST }, \
3083 { "a1", 5 + GP_REG_FIRST }, \
3084 { "a2", 6 + GP_REG_FIRST }, \
3085 { "a3", 7 + GP_REG_FIRST }, \
3086 { "t0", 8 + GP_REG_FIRST }, \
3087 { "t1", 9 + GP_REG_FIRST }, \
3088 { "t2", 10 + GP_REG_FIRST }, \
3089 { "t3", 11 + GP_REG_FIRST }, \
3090 { "t4", 12 + GP_REG_FIRST }, \
3091 { "t5", 13 + GP_REG_FIRST }, \
3092 { "t6", 14 + GP_REG_FIRST }, \
3093 { "t7", 15 + GP_REG_FIRST }, \
3094 { "s0", 16 + GP_REG_FIRST }, \
3095 { "s1", 17 + GP_REG_FIRST }, \
3096 { "s2", 18 + GP_REG_FIRST }, \
3097 { "s3", 19 + GP_REG_FIRST }, \
3098 { "s4", 20 + GP_REG_FIRST }, \
3099 { "s5", 21 + GP_REG_FIRST }, \
3100 { "s6", 22 + GP_REG_FIRST }, \
3101 { "s7", 23 + GP_REG_FIRST }, \
3102 { "t8", 24 + GP_REG_FIRST }, \
3103 { "t9", 25 + GP_REG_FIRST }, \
3104 { "k0", 26 + GP_REG_FIRST }, \
3105 { "k1", 27 + GP_REG_FIRST }, \
3106 { "gp", 28 + GP_REG_FIRST }, \
3107 { "sp", 29 + GP_REG_FIRST }, \
3108 { "fp", 30 + GP_REG_FIRST }, \
3109 { "ra", 31 + GP_REG_FIRST }, \
3110 { "$sp", 29 + GP_REG_FIRST }, \
3111 { "$fp", 30 + GP_REG_FIRST } \
3112 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3115 /* This is meant to be redefined in the host dependent files. It is a
3116 set of alternative names and regnums for mips coprocessors. */
3118 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3120 /* A C compound statement to output to stdio stream STREAM the
3121 assembler syntax for an instruction operand X. X is an RTL
3124 CODE is a value that can be used to specify one of several ways
3125 of printing the operand. It is used when identical operands
3126 must be printed differently depending on the context. CODE
3127 comes from the `%' specification that was used to request
3128 printing of the operand. If the specification was just `%DIGIT'
3129 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3130 is the ASCII code for LTR.
3132 If X is a register, this macro should print the register's name.
3133 The names can be found in an array `reg_names' whose type is
3134 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3136 When the machine description has a specification `%PUNCT' (a `%'
3137 followed by a punctuation character), this macro is called with
3138 a null pointer for X and the punctuation character for CODE.
3140 See mips.c for the MIPS specific codes. */
3142 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3144 /* A C expression which evaluates to true if CODE is a valid
3145 punctuation character for use in the `PRINT_OPERAND' macro. If
3146 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3147 punctuation characters (except for the standard one, `%') are
3148 used in this way. */
3150 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3152 /* A C compound statement to output to stdio stream STREAM the
3153 assembler syntax for an instruction operand that is a memory
3154 reference whose address is ADDR. ADDR is an RTL expression. */
3156 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3159 /* A C statement, to be executed after all slot-filler instructions
3160 have been output. If necessary, call `dbr_sequence_length' to
3161 determine the number of slots filled in a sequence (zero if not
3162 currently outputting a sequence), to decide how many no-ops to
3163 output, or whatever.
3165 Don't define this macro if it has nothing to do, but it is
3166 helpful in reading assembly output if the extent of the delay
3167 sequence is made explicit (e.g. with white space).
3169 Note that output routines for instructions with delay slots must
3170 be prepared to deal with not being output as part of a sequence
3171 (i.e. when the scheduling pass is not run, or when no slot
3172 fillers could be found.) The variable `final_sequence' is null
3173 when not processing a sequence, otherwise it contains the
3174 `sequence' rtx being output. */
3176 #define DBR_OUTPUT_SEQEND(STREAM) \
3179 if (set_nomacro > 0 && --set_nomacro == 0) \
3180 fputs ("\t.set\tmacro\n", STREAM); \
3182 if (set_noreorder > 0 && --set_noreorder == 0) \
3183 fputs ("\t.set\treorder\n", STREAM); \
3185 fputs ("\n", STREAM); \
3190 /* How to tell the debugger about changes of source files. */
3192 #ifndef SET_FILE_NUMBER
3193 #define SET_FILE_NUMBER() ++num_source_filenames
3196 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3197 mips_output_filename (STREAM, NAME)
3199 /* This is defined so that it can be overridden in iris6.h. */
3200 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3203 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3204 output_quoted_string (STREAM, NAME); \
3205 fputs ("\n", STREAM); \
3209 /* This is how to output a note the debugger telling it the line number
3210 to which the following sequence of instructions corresponds.
3211 Silicon graphics puts a label after each .loc. */
3213 #ifndef LABEL_AFTER_LOC
3214 #define LABEL_AFTER_LOC(STREAM)
3217 #ifndef ASM_OUTPUT_SOURCE_LINE
3218 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3219 mips_output_lineno (STREAM, LINE)
3222 /* The MIPS implementation uses some labels for its own purpose. The
3223 following lists what labels are created, and are all formed by the
3224 pattern $L[a-z].*. The machine independent portion of GCC creates
3225 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3227 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3228 $Lb[0-9]+ Begin blocks for MIPS debug support
3229 $Lc[0-9]+ Label for use in s<xx> operation.
3230 $Le[0-9]+ End blocks for MIPS debug support */
3232 #undef ASM_DECLARE_OBJECT_NAME
3233 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3234 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3236 /* Globalizing directive for a label. */
3237 #define GLOBAL_ASM_OP "\t.globl\t"
3239 /* This says how to define a global common symbol. */
3241 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3243 /* If the target wants uninitialized const declarations in \
3244 .rdata then don't put them in .comm */ \
3245 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3246 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3247 && (DECL_INITIAL (DECL) == 0 \
3248 || DECL_INITIAL (DECL) == error_mark_node)) \
3250 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3251 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3253 readonly_data_section (); \
3254 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3255 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3259 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3264 /* This says how to define a local common symbol (ie, not visible to
3267 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3268 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3271 /* This says how to output an external. It would be possible not to
3272 output anything and let undefined symbol become external. However
3273 the assembler uses length information on externals to allocate in
3274 data/sdata bss/sbss, thereby saving exec time. */
3276 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3277 mips_output_external(STREAM,DECL,NAME)
3280 /* This is how to declare a function name. The actual work of
3281 emitting the label is moved to function_prologue, so that we can
3282 get the line number correctly emitted before the .ent directive,
3283 and after any .file directives. Define as empty so that the function
3284 is not declared before the .ent directive elsewhere. */
3286 #undef ASM_DECLARE_FUNCTION_NAME
3287 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3289 /* This is how to store into the string LABEL
3290 the symbol_ref name of an internal numbered label where
3291 PREFIX is the class of label and NUM is the number within the class.
3292 This is suitable for output with `assemble_name'. */
3294 #undef ASM_GENERATE_INTERNAL_LABEL
3295 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3296 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3298 /* This is how to output an element of a case-vector that is absolute. */
3300 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3301 fprintf (STREAM, "\t%s\t%sL%d\n", \
3302 ptr_mode == DImode ? ".dword" : ".word", \
3303 LOCAL_LABEL_PREFIX, \
3306 /* This is how to output an element of a case-vector that is relative.
3307 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3308 TARGET_EMBEDDED_PIC). */
3310 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3312 if (TARGET_MIPS16) \
3313 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3314 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3315 else if (TARGET_EMBEDDED_PIC) \
3316 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3317 ptr_mode == DImode ? ".dword" : ".word", \
3318 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3319 else if (TARGET_GPWORD) \
3320 fprintf (STREAM, "\t%s\t%sL%d\n", \
3321 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3322 LOCAL_LABEL_PREFIX, VALUE); \
3324 fprintf (STREAM, "\t%s\t%sL%d\n", \
3325 ptr_mode == DImode ? ".dword" : ".word", \
3326 LOCAL_LABEL_PREFIX, VALUE); \
3329 /* When generating embedded PIC or mips16 code we want to put the jump
3330 table in the .text section. In all other cases, we want to put the
3331 jump table in the .rdata section. Unfortunately, we can't use
3332 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3333 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3334 section if appropriate. */
3335 #undef ASM_OUTPUT_CASE_LABEL
3336 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3338 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3339 function_section (current_function_decl); \
3340 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3343 /* This is how to output an assembler line
3344 that says to advance the location counter
3345 to a multiple of 2**LOG bytes. */
3347 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3348 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3350 /* This is how to output an assembler line to advance the location
3351 counter by SIZE bytes. */
3353 #undef ASM_OUTPUT_SKIP
3354 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3355 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3357 /* This is how to output a string. */
3358 #undef ASM_OUTPUT_ASCII
3359 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3360 mips_output_ascii (STREAM, STRING, LEN)
3362 /* Output #ident as a in the read-only data section. */
3363 #undef ASM_OUTPUT_IDENT
3364 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3366 const char *p = STRING; \
3367 int size = strlen (p) + 1; \
3368 readonly_data_section (); \
3369 assemble_string (p, size); \
3372 /* Default to -G 8 */
3373 #ifndef MIPS_DEFAULT_GVALUE
3374 #define MIPS_DEFAULT_GVALUE 8
3377 /* Define the strings to put out for each section in the object file. */
3378 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3379 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3380 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3382 #undef READONLY_DATA_SECTION_ASM_OP
3383 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3385 /* Given a decl node or constant node, choose the section to output it in
3386 and select that section. */
3388 #undef TARGET_ASM_SELECT_SECTION
3389 #define TARGET_ASM_SELECT_SECTION mips_select_section
3391 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3394 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3395 TARGET_64BIT ? "dsubu" : "subu", \
3396 reg_names[STACK_POINTER_REGNUM], \
3397 reg_names[STACK_POINTER_REGNUM], \
3398 TARGET_64BIT ? "sd" : "sw", \
3400 reg_names[STACK_POINTER_REGNUM]); \
3404 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3407 if (! set_noreorder) \
3408 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3410 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3411 TARGET_64BIT ? "ld" : "lw", \
3413 reg_names[STACK_POINTER_REGNUM], \
3414 TARGET_64BIT ? "daddu" : "addu", \
3415 reg_names[STACK_POINTER_REGNUM], \
3416 reg_names[STACK_POINTER_REGNUM]); \
3418 if (! set_noreorder) \
3419 fprintf (STREAM, "\t.set\treorder\n"); \
3423 /* How to start an assembler comment.
3424 The leading space is important (the mips native assembler requires it). */
3425 #ifndef ASM_COMMENT_START
3426 #define ASM_COMMENT_START " #"
3429 /* Default definitions for size_t and ptrdiff_t. We must override the
3430 definitions from ../svr4.h on mips-*-linux-gnu. */
3433 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3436 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3438 /* See mips_expand_prologue's use of loadgp for when this should be
3441 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3442 && mips_abi != ABI_32 \
3443 && mips_abi != ABI_O64)
3446 #define DFMODE_NAN \
3447 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
3448 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
3449 #define SFMODE_NAN \
3450 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
3451 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
3453 /* Generate calls to memcpy, etc., not bcopy, etc. */
3454 #define TARGET_MEM_FUNCTIONS
3457 /* Since the bits of the _init and _fini function is spread across
3458 many object files, each potentially with its own GP, we must assume
3459 we need to load our GP. We don't preserve $gp or $ra, since each
3460 init/fini chunk is supposed to initialize $gp, and crti/crtn
3461 already take care of preserving $ra and, when appropriate, $gp. */
3462 #if _MIPS_SIM == _MIPS_SIM_ABI32
3463 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3464 asm (SECTION_OP "\n\
3470 jal " USER_LABEL_PREFIX #FUNC "\n\
3471 " TEXT_SECTION_ASM_OP);
3472 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3473 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3474 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3475 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3476 asm (SECTION_OP "\n\
3481 .cpsetup $31, $2, 1b\n\
3482 jal " USER_LABEL_PREFIX #FUNC "\n\
3483 " TEXT_SECTION_ASM_OP);
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